From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001 From: Angelos Mouzakitis Date: Tue, 10 Oct 2023 14:33:42 +0000 Subject: Add submodule dependency files Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec --- roms/u-boot/include/.gitignore | 4 + roms/u-boot/include/ACEX1K.h | 79 + roms/u-boot/include/MCD_dma.h | 369 ++ roms/u-boot/include/MCD_progCheck.h | 10 + roms/u-boot/include/MCD_tasksInit.h | 43 + roms/u-boot/include/SA-1100.h | 2833 ++++++++++++ roms/u-boot/include/_exports.h | 86 + roms/u-boot/include/acpi/acpi_device.h | 498 +++ roms/u-boot/include/acpi/acpi_dp.h | 287 ++ roms/u-boot/include/acpi/acpi_s3.h | 134 + roms/u-boot/include/acpi/acpi_table.h | 705 +++ roms/u-boot/include/acpi/acpigen.h | 981 +++++ roms/u-boot/include/adc.h | 308 ++ roms/u-boot/include/addr_map.h | 24 + roms/u-boot/include/ahci.h | 288 ++ roms/u-boot/include/ali512x.h | 37 + roms/u-boot/include/altera.h | 128 + roms/u-boot/include/andestech/andes_pcu.h | 354 ++ roms/u-boot/include/android_ab.h | 35 + roms/u-boot/include/android_bootloader_message.h | 256 ++ roms/u-boot/include/android_image.h | 139 + roms/u-boot/include/ansi.h | 25 + roms/u-boot/include/api.h | 20 + roms/u-boot/include/api_public.h | 140 + roms/u-boot/include/armcoremodule.h | 75 + roms/u-boot/include/asm-generic/atomic-long.h | 262 ++ roms/u-boot/include/asm-generic/atomic.h | 150 + roms/u-boot/include/asm-generic/bitops/__ffs.h | 43 + roms/u-boot/include/asm-generic/bitops/__fls.h | 43 + roms/u-boot/include/asm-generic/bitops/fls.h | 41 + roms/u-boot/include/asm-generic/bitops/fls64.h | 36 + roms/u-boot/include/asm-generic/bitsperlong.h | 8 + roms/u-boot/include/asm-generic/global_data.h | 602 +++ roms/u-boot/include/asm-generic/gpio.h | 840 ++++ roms/u-boot/include/asm-generic/int-ll64.h | 47 + roms/u-boot/include/asm-generic/io.h | 109 + roms/u-boot/include/asm-generic/ioctl.h | 105 + roms/u-boot/include/asm-generic/pe.h | 56 + roms/u-boot/include/asm-generic/sections.h | 99 + roms/u-boot/include/asm-generic/signal.h | 101 + roms/u-boot/include/asm-generic/types.h | 9 + roms/u-boot/include/asm-generic/u-boot.h | 79 + roms/u-boot/include/asm-generic/unaligned.h | 26 + roms/u-boot/include/asm-offsets.h | 6 + roms/u-boot/include/ata.h | 213 + roms/u-boot/include/atf_common.h | 198 + roms/u-boot/include/atmel_hlcdc.h | 225 + roms/u-boot/include/atmel_lcd.h | 56 + roms/u-boot/include/atmel_lcdc.h | 164 + roms/u-boot/include/atmel_mci.h | 217 + roms/u-boot/include/atsha204a-i2c.h | 69 + roms/u-boot/include/audio_codec.h | 50 + roms/u-boot/include/autoboot.h | 46 + roms/u-boot/include/avb_verify.h | 101 + roms/u-boot/include/axi.h | 120 + roms/u-boot/include/axp152.h | 26 + roms/u-boot/include/axp209.h | 86 + roms/u-boot/include/axp221.h | 65 + roms/u-boot/include/axp305.h | 17 + roms/u-boot/include/axp809.h | 59 + roms/u-boot/include/axp818.h | 73 + roms/u-boot/include/axp_pmic.h | 44 + roms/u-boot/include/backlight.h | 57 + roms/u-boot/include/bcb.h | 21 + roms/u-boot/include/bcd.h | 23 + roms/u-boot/include/bedbug/bedbug.h | 40 + roms/u-boot/include/bedbug/ppc.h | 408 ++ roms/u-boot/include/bedbug/regs.h | 400 ++ roms/u-boot/include/bedbug/tables.h | 601 +++ roms/u-boot/include/bedbug/type.h | 29 + roms/u-boot/include/binman.h | 96 + roms/u-boot/include/binman_sym.h | 92 + roms/u-boot/include/bios_emul.h | 82 + roms/u-boot/include/bitfield.h | 90 + roms/u-boot/include/blk.h | 686 +++ roms/u-boot/include/bloblist.h | 263 ++ roms/u-boot/include/bmp_layout.h | 59 + roms/u-boot/include/boot_fit.h | 13 + roms/u-boot/include/bootcount.h | 145 + roms/u-boot/include/bootm.h | 128 + roms/u-boot/include/bootretry.h | 58 + roms/u-boot/include/bootstage.h | 438 ++ roms/u-boot/include/bouncebuf.h | 86 + roms/u-boot/include/broadcom/chimp.h | 55 + roms/u-boot/include/btrfs.h | 24 + roms/u-boot/include/bus_vcxk.h | 19 + roms/u-boot/include/button.h | 61 + roms/u-boot/include/bzlib.h | 332 ++ roms/u-boot/include/cache.h | 71 + roms/u-boot/include/capitalization.h | 2028 +++++++++ roms/u-boot/include/cavium/atf.h | 21 + roms/u-boot/include/cavium/atf_part.h | 25 + roms/u-boot/include/cavium/thunderx_svc.h | 66 + roms/u-boot/include/cbfs.h | 297 ++ roms/u-boot/include/charset.h | 307 ++ roms/u-boot/include/circbuf.h | 26 + roms/u-boot/include/cli.h | 158 + roms/u-boot/include/cli_hush.h | 26 + roms/u-boot/include/clk-uclass.h | 111 + roms/u-boot/include/clk.h | 575 +++ roms/u-boot/include/clock_legacy.h | 14 + roms/u-boot/include/cmd_spl.h | 14 + roms/u-boot/include/command.h | 441 ++ roms/u-boot/include/common.h | 35 + roms/u-boot/include/common_timing_params.h | 68 + roms/u-boot/include/compiler.h | 162 + roms/u-boot/include/config_distro_bootcmd.h | 504 +++ roms/u-boot/include/config_fallbacks.h | 55 + roms/u-boot/include/config_fsl_chain_trust.h | 100 + roms/u-boot/include/config_phylib_all_drivers.h | 15 + roms/u-boot/include/config_uncmd_spl.h | 22 + roms/u-boot/include/configs/10m50_devboard.h | 66 + roms/u-boot/include/configs/3c120_devboard.h | 66 + roms/u-boot/include/configs/M5208EVBE.h | 169 + roms/u-boot/include/configs/M52277EVB.h | 243 + roms/u-boot/include/configs/M5235EVB.h | 194 + roms/u-boot/include/configs/M5249EVB.h | 149 + roms/u-boot/include/configs/M5253DEMO.h | 201 + roms/u-boot/include/configs/M5272C3.h | 182 + roms/u-boot/include/configs/M5275EVB.h | 181 + roms/u-boot/include/configs/M5282EVB.h | 190 + roms/u-boot/include/configs/M53017EVB.h | 193 + roms/u-boot/include/configs/M5329EVB.h | 206 + roms/u-boot/include/configs/M5373EVB.h | 208 + roms/u-boot/include/configs/M54418TWR.h | 283 ++ roms/u-boot/include/configs/M54451EVB.h | 242 + roms/u-boot/include/configs/M54455EVB.h | 356 ++ roms/u-boot/include/configs/M5475EVB.h | 241 + roms/u-boot/include/configs/M5485EVB.h | 228 + roms/u-boot/include/configs/MCR3000.h | 104 + roms/u-boot/include/configs/MPC8313ERDB_NAND.h | 392 ++ roms/u-boot/include/configs/MPC8313ERDB_NOR.h | 361 ++ roms/u-boot/include/configs/MPC8315ERDB.h | 370 ++ roms/u-boot/include/configs/MPC8323ERDB.h | 309 ++ roms/u-boot/include/configs/MPC832XEMDS.h | 302 ++ roms/u-boot/include/configs/MPC8349EMDS.h | 374 ++ roms/u-boot/include/configs/MPC8349EMDS_SDRAM.h | 431 ++ roms/u-boot/include/configs/MPC837XERDB.h | 412 ++ roms/u-boot/include/configs/MPC8540ADS.h | 355 ++ roms/u-boot/include/configs/MPC8541CDS.h | 384 ++ roms/u-boot/include/configs/MPC8548CDS.h | 517 +++ roms/u-boot/include/configs/MPC8555CDS.h | 380 ++ roms/u-boot/include/configs/MPC8560ADS.h | 389 ++ roms/u-boot/include/configs/MPC8568MDS.h | 400 ++ roms/u-boot/include/configs/P1010RDB.h | 758 ++++ roms/u-boot/include/configs/P2041RDB.h | 573 +++ roms/u-boot/include/configs/P3041DS.h | 24 + roms/u-boot/include/configs/P4080DS.h | 23 + roms/u-boot/include/configs/P5040DS.h | 19 + roms/u-boot/include/configs/SBx81LIFKW.h | 95 + roms/u-boot/include/configs/SBx81LIFXCAT.h | 95 + roms/u-boot/include/configs/T102xRDB.h | 709 +++ roms/u-boot/include/configs/T104xRDB.h | 805 ++++ roms/u-boot/include/configs/T208xQDS.h | 751 ++++ roms/u-boot/include/configs/T208xRDB.h | 709 +++ roms/u-boot/include/configs/T4240RDB.h | 666 +++ roms/u-boot/include/configs/TQM834x.h | 277 ++ roms/u-boot/include/configs/UCP1020.h | 832 ++++ roms/u-boot/include/configs/adp-ae3xx.h | 216 + roms/u-boot/include/configs/adp-ag101p.h | 331 ++ roms/u-boot/include/configs/alt.h | 52 + roms/u-boot/include/configs/am335x_evm.h | 319 ++ roms/u-boot/include/configs/am335x_guardian.h | 143 + roms/u-boot/include/configs/am335x_igep003x.h | 128 + roms/u-boot/include/configs/am335x_shc.h | 232 + roms/u-boot/include/configs/am335x_sl50.h | 80 + roms/u-boot/include/configs/am3517_evm.h | 174 + roms/u-boot/include/configs/am43xx_evm.h | 270 ++ roms/u-boot/include/configs/am57xx_evm.h | 83 + roms/u-boot/include/configs/am64x_evm.h | 113 + roms/u-boot/include/configs/am65x_evm.h | 154 + roms/u-boot/include/configs/amcore.h | 102 + roms/u-boot/include/configs/ap121.h | 39 + roms/u-boot/include/configs/ap143.h | 43 + roms/u-boot/include/configs/ap152.h | 45 + roms/u-boot/include/configs/apalis-imx8.h | 107 + roms/u-boot/include/configs/apalis-imx8x.h | 145 + roms/u-boot/include/configs/apalis-tk1.h | 124 + roms/u-boot/include/configs/apalis_imx6.h | 188 + roms/u-boot/include/configs/apalis_t30.h | 60 + roms/u-boot/include/configs/aristainetos2.h | 455 ++ roms/u-boot/include/configs/armadillo-800eva.h | 81 + roms/u-boot/include/configs/arndale.h | 31 + roms/u-boot/include/configs/aspeed-common.h | 55 + roms/u-boot/include/configs/aspenite.h | 32 + roms/u-boot/include/configs/astro_mcf5373l.h | 288 ++ roms/u-boot/include/configs/at91-sama5_common.h | 60 + roms/u-boot/include/configs/at91rm9200ek.h | 162 + roms/u-boot/include/configs/at91sam9260ek.h | 142 + roms/u-boot/include/configs/at91sam9261ek.h | 123 + roms/u-boot/include/configs/at91sam9263ek.h | 232 + roms/u-boot/include/configs/at91sam9m10g45ek.h | 130 + roms/u-boot/include/configs/at91sam9n12ek.h | 137 + roms/u-boot/include/configs/at91sam9rlek.h | 96 + roms/u-boot/include/configs/at91sam9x5ek.h | 120 + roms/u-boot/include/configs/ax25-ae350.h | 158 + roms/u-boot/include/configs/axs10x.h | 72 + roms/u-boot/include/configs/baltos.h | 258 ++ roms/u-boot/include/configs/bayleybay.h | 23 + roms/u-boot/include/configs/bcm7260.h | 34 + roms/u-boot/include/configs/bcm7445.h | 36 + roms/u-boot/include/configs/bcm_ns3.h | 819 ++++ roms/u-boot/include/configs/bcmstb.h | 162 + roms/u-boot/include/configs/beacon-rzg2m.h | 84 + roms/u-boot/include/configs/beaver.h | 32 + roms/u-boot/include/configs/bg0900.h | 41 + roms/u-boot/include/configs/bitmain_antminer_s9.h | 27 + roms/u-boot/include/configs/bk4r1.h | 250 ++ roms/u-boot/include/configs/blanche.h | 53 + roms/u-boot/include/configs/bmips_bcm3380.h | 25 + roms/u-boot/include/configs/bmips_bcm6318.h | 34 + roms/u-boot/include/configs/bmips_bcm63268.h | 34 + roms/u-boot/include/configs/bmips_bcm6328.h | 34 + roms/u-boot/include/configs/bmips_bcm6338.h | 29 + roms/u-boot/include/configs/bmips_bcm6348.h | 36 + roms/u-boot/include/configs/bmips_bcm6358.h | 38 + roms/u-boot/include/configs/bmips_bcm6362.h | 34 + roms/u-boot/include/configs/bmips_bcm6368.h | 38 + roms/u-boot/include/configs/bmips_bcm6838.h | 25 + roms/u-boot/include/configs/bmips_common.h | 28 + roms/u-boot/include/configs/boston.h | 54 + roms/u-boot/include/configs/broadcom_bcm963158.h | 42 + roms/u-boot/include/configs/broadcom_bcm968360bg.h | 40 + .../include/configs/broadcom_bcm968380gerg.h | 13 + .../include/configs/broadcom_bcm968580xref.h | 41 + roms/u-boot/include/configs/brppt1.h | 184 + roms/u-boot/include/configs/brppt2.h | 114 + roms/u-boot/include/configs/brsmarc1.h | 72 + roms/u-boot/include/configs/brxre1.h | 68 + roms/u-boot/include/configs/bur_am335x_common.h | 96 + roms/u-boot/include/configs/bur_cfg_common.h | 40 + roms/u-boot/include/configs/caddy2.h | 315 ++ roms/u-boot/include/configs/capricorn-common.h | 160 + roms/u-boot/include/configs/cardhu.h | 35 + roms/u-boot/include/configs/cei-tk1-som.h | 35 + roms/u-boot/include/configs/cgtqmx8.h | 181 + roms/u-boot/include/configs/cherryhill.h | 19 + roms/u-boot/include/configs/chiliboard.h | 168 + roms/u-boot/include/configs/chromebook_coral.h | 42 + roms/u-boot/include/configs/chromebook_link.h | 20 + roms/u-boot/include/configs/chromebook_samus.h | 28 + roms/u-boot/include/configs/chromebox_panther.h | 12 + roms/u-boot/include/configs/ci20.h | 62 + roms/u-boot/include/configs/cl-som-imx7.h | 147 + roms/u-boot/include/configs/clearfog.h | 171 + roms/u-boot/include/configs/cm_fx6.h | 210 + roms/u-boot/include/configs/cm_t335.h | 148 + roms/u-boot/include/configs/cm_t43.h | 123 + roms/u-boot/include/configs/cobra5272.h | 311 ++ roms/u-boot/include/configs/colibri-imx6ull.h | 156 + roms/u-boot/include/configs/colibri-imx8x.h | 145 + roms/u-boot/include/configs/colibri_imx6.h | 168 + roms/u-boot/include/configs/colibri_imx7.h | 219 + roms/u-boot/include/configs/colibri_pxa270.h | 174 + roms/u-boot/include/configs/colibri_t20.h | 54 + roms/u-boot/include/configs/colibri_t30.h | 58 + roms/u-boot/include/configs/colibri_vf.h | 148 + roms/u-boot/include/configs/comtrend_ar5315u.h | 10 + roms/u-boot/include/configs/comtrend_ar5387un.h | 10 + roms/u-boot/include/configs/comtrend_ct5361.h | 10 + roms/u-boot/include/configs/comtrend_vr3032u.h | 15 + roms/u-boot/include/configs/comtrend_wap5813n.h | 10 + roms/u-boot/include/configs/condor.h | 35 + .../include/configs/conga-qeval20-qa3-e3845.h | 37 + roms/u-boot/include/configs/controlcenterdc.h | 174 + roms/u-boot/include/configs/coreboot.h | 32 + roms/u-boot/include/configs/corenet_ds.h | 591 +++ roms/u-boot/include/configs/corvus.h | 138 + roms/u-boot/include/configs/cougarcanyon2.h | 21 + roms/u-boot/include/configs/crownbay.h | 25 + roms/u-boot/include/configs/crs3xx-98dx3236.h | 35 + roms/u-boot/include/configs/da850evm.h | 246 ++ roms/u-boot/include/configs/dalmore.h | 30 + roms/u-boot/include/configs/dart_6ul.h | 113 + roms/u-boot/include/configs/db-88f6720.h | 71 + roms/u-boot/include/configs/db-88f6820-amc.h | 75 + roms/u-boot/include/configs/db-88f6820-gp.h | 94 + roms/u-boot/include/configs/db-mv784mp-gp.h | 88 + roms/u-boot/include/configs/db-xc3-24g4xg.h | 37 + roms/u-boot/include/configs/deneb.h | 19 + roms/u-boot/include/configs/devkit3250.h | 178 + roms/u-boot/include/configs/devkit8000.h | 172 + roms/u-boot/include/configs/dfi-bt700.h | 42 + roms/u-boot/include/configs/dh_imx6.h | 128 + roms/u-boot/include/configs/dh_stm32mp1.h | 15 + roms/u-boot/include/configs/display5.h | 350 ++ roms/u-boot/include/configs/dns325.h | 94 + roms/u-boot/include/configs/dockstar.h | 66 + roms/u-boot/include/configs/dra7xx_evm.h | 132 + roms/u-boot/include/configs/draak.h | 30 + roms/u-boot/include/configs/draco.h | 79 + roms/u-boot/include/configs/dragonboard410c.h | 89 + roms/u-boot/include/configs/dragonboard820c.h | 60 + roms/u-boot/include/configs/dreamplug.h | 55 + roms/u-boot/include/configs/ds109.h | 58 + roms/u-boot/include/configs/ds414.h | 101 + roms/u-boot/include/configs/durian.h | 43 + roms/u-boot/include/configs/eagle.h | 26 + roms/u-boot/include/configs/eb_cpu5282.h | 236 + roms/u-boot/include/configs/ebisu.h | 35 + roms/u-boot/include/configs/edb93xx.h | 184 + roms/u-boot/include/configs/edison.h | 29 + roms/u-boot/include/configs/edminiv2.h | 188 + roms/u-boot/include/configs/efi-x86_app.h | 17 + roms/u-boot/include/configs/efi-x86_payload.h | 32 + roms/u-boot/include/configs/el6x_common.h | 87 + roms/u-boot/include/configs/elgin_rv1108.h | 11 + roms/u-boot/include/configs/embestmx6boards.h | 124 + roms/u-boot/include/configs/emsdp.h | 36 + roms/u-boot/include/configs/espresso7420.h | 24 + roms/u-boot/include/configs/etamin.h | 210 + roms/u-boot/include/configs/ethernut5.h | 143 + roms/u-boot/include/configs/evb_ast2500.h | 19 + roms/u-boot/include/configs/evb_ast2600.h | 16 + roms/u-boot/include/configs/evb_px30.h | 17 + roms/u-boot/include/configs/evb_px5.h | 11 + roms/u-boot/include/configs/evb_rk3036.h | 11 + roms/u-boot/include/configs/evb_rk3128.h | 11 + roms/u-boot/include/configs/evb_rk3229.h | 11 + roms/u-boot/include/configs/evb_rk3288.h | 16 + roms/u-boot/include/configs/evb_rk3308.h | 17 + roms/u-boot/include/configs/evb_rk3328.h | 13 + roms/u-boot/include/configs/evb_rk3399.h | 18 + roms/u-boot/include/configs/evb_rv1108.h | 28 + roms/u-boot/include/configs/exynos-common.h | 46 + roms/u-boot/include/configs/exynos4-common.h | 89 + roms/u-boot/include/configs/exynos5-common.h | 158 + roms/u-boot/include/configs/exynos5-dt-common.h | 36 + roms/u-boot/include/configs/exynos5250-common.h | 32 + roms/u-boot/include/configs/exynos5420-common.h | 40 + roms/u-boot/include/configs/exynos7420-common.h | 96 + roms/u-boot/include/configs/firefly-rk3288.h | 16 + roms/u-boot/include/configs/firefly_rk3308.h | 17 + roms/u-boot/include/configs/flea3.h | 178 + roms/u-boot/include/configs/galileo.h | 30 + .../configs/gardena-smart-gateway-at91sam.h | 82 + .../include/configs/gardena-smart-gateway-mt7688.h | 64 + roms/u-boot/include/configs/gazerbeam.h | 126 + roms/u-boot/include/configs/ge_b1x5v2.h | 127 + roms/u-boot/include/configs/ge_bx50v3.h | 167 + roms/u-boot/include/configs/geekbox.h | 11 + roms/u-boot/include/configs/giedi.h | 19 + roms/u-boot/include/configs/goflexhome.h | 75 + roms/u-boot/include/configs/gose.h | 47 + roms/u-boot/include/configs/gplugd.h | 75 + roms/u-boot/include/configs/grpeach.h | 39 + roms/u-boot/include/configs/gru.h | 16 + roms/u-boot/include/configs/guruplug.h | 69 + roms/u-boot/include/configs/gw_ventana.h | 277 ++ roms/u-boot/include/configs/harmony.h | 36 + roms/u-boot/include/configs/helios4.h | 172 + roms/u-boot/include/configs/highbank.h | 55 + roms/u-boot/include/configs/hihope-rzg2.h | 20 + roms/u-boot/include/configs/hikey.h | 86 + roms/u-boot/include/configs/hikey960.h | 56 + roms/u-boot/include/configs/hsdk-4xd.h | 119 + roms/u-boot/include/configs/hsdk.h | 118 + roms/u-boot/include/configs/huawei_hg556a.h | 10 + roms/u-boot/include/configs/ib62x0.h | 70 + roms/u-boot/include/configs/iconnect.h | 59 + roms/u-boot/include/configs/ids8313.h | 297 ++ roms/u-boot/include/configs/imgtec_xilfpga.h | 54 + roms/u-boot/include/configs/imx27lite-common.h | 159 + roms/u-boot/include/configs/imx6-engicam.h | 183 + roms/u-boot/include/configs/imx6_logic.h | 166 + roms/u-boot/include/configs/imx6_spl.h | 90 + roms/u-boot/include/configs/imx6dl-mamoj.h | 86 + roms/u-boot/include/configs/imx7-cm.h | 110 + roms/u-boot/include/configs/imx7_spl.h | 54 + roms/u-boot/include/configs/imx8mm-cl-iot-gate.h | 196 + roms/u-boot/include/configs/imx8mm_beacon.h | 141 + roms/u-boot/include/configs/imx8mm_evk.h | 107 + roms/u-boot/include/configs/imx8mm_icore_mx8mm.h | 100 + roms/u-boot/include/configs/imx8mm_venice.h | 125 + roms/u-boot/include/configs/imx8mn_beacon.h | 159 + roms/u-boot/include/configs/imx8mn_evk.h | 98 + roms/u-boot/include/configs/imx8mp_evk.h | 125 + roms/u-boot/include/configs/imx8mq_cm.h | 104 + roms/u-boot/include/configs/imx8mq_evk.h | 151 + roms/u-boot/include/configs/imx8mq_phanbell.h | 196 + roms/u-boot/include/configs/imx8qm_mek.h | 177 + roms/u-boot/include/configs/imx8qm_rom7720.h | 166 + roms/u-boot/include/configs/imx8qxp_mek.h | 186 + roms/u-boot/include/configs/imxrt1020-evk.h | 44 + roms/u-boot/include/configs/imxrt1050-evk.h | 55 + roms/u-boot/include/configs/integrator-common.h | 88 + roms/u-boot/include/configs/integratorap.h | 48 + roms/u-boot/include/configs/integratorcp.h | 64 + roms/u-boot/include/configs/iot_devkit.h | 80 + roms/u-boot/include/configs/j721e_evm.h | 180 + roms/u-boot/include/configs/jetson-tk1.h | 33 + roms/u-boot/include/configs/k2e_evm.h | 52 + roms/u-boot/include/configs/k2g_evm.h | 94 + roms/u-boot/include/configs/k2hk_evm.h | 51 + roms/u-boot/include/configs/k2l_evm.h | 50 + roms/u-boot/include/configs/km/keymile-common.h | 193 + roms/u-boot/include/configs/km/km-mpc8309.h | 137 + roms/u-boot/include/configs/km/km-mpc832x.h | 76 + roms/u-boot/include/configs/km/km-mpc8360.h | 76 + roms/u-boot/include/configs/km/km-mpc83xx.h | 130 + roms/u-boot/include/configs/km/km-powerpc.h | 60 + roms/u-boot/include/configs/km/km_arm.h | 199 + roms/u-boot/include/configs/km/pg-wcom-ls102xa.h | 307 ++ roms/u-boot/include/configs/km_kirkwood.h | 134 + roms/u-boot/include/configs/kmcent2.h | 513 +++ roms/u-boot/include/configs/kmcoge5ne.h | 58 + roms/u-boot/include/configs/kmeter1.h | 23 + roms/u-boot/include/configs/kmopti2.h | 34 + roms/u-boot/include/configs/kmp204x.h | 416 ++ roms/u-boot/include/configs/kmsupx5.h | 34 + roms/u-boot/include/configs/kmtegr1.h | 58 + roms/u-boot/include/configs/kmtepr2.h | 34 + roms/u-boot/include/configs/koelsch.h | 47 + roms/u-boot/include/configs/kontron_sl28.h | 102 + roms/u-boot/include/configs/kp_imx53.h | 98 + roms/u-boot/include/configs/kp_imx6q_tpc.h | 125 + roms/u-boot/include/configs/kylin_rk3036.h | 18 + roms/u-boot/include/configs/kzm9g.h | 104 + roms/u-boot/include/configs/lacie_kw.h | 150 + roms/u-boot/include/configs/lager.h | 48 + roms/u-boot/include/configs/legoev3.h | 141 + roms/u-boot/include/configs/libretech-ac.h | 21 + roms/u-boot/include/configs/linkit-smart-7688.h | 65 + roms/u-boot/include/configs/lion_rk3368.h | 17 + roms/u-boot/include/configs/liteboard.h | 144 + roms/u-boot/include/configs/ls1012a2g5rdb.h | 94 + roms/u-boot/include/configs/ls1012a_common.h | 122 + roms/u-boot/include/configs/ls1012afrdm.h | 65 + roms/u-boot/include/configs/ls1012afrwy.h | 108 + roms/u-boot/include/configs/ls1012aqds.h | 157 + roms/u-boot/include/configs/ls1012ardb.h | 107 + roms/u-boot/include/configs/ls1021aiot.h | 222 + roms/u-boot/include/configs/ls1021aqds.h | 486 ++ roms/u-boot/include/configs/ls1021atsn.h | 242 + roms/u-boot/include/configs/ls1021atwr.h | 458 ++ roms/u-boot/include/configs/ls1028a_common.h | 125 + roms/u-boot/include/configs/ls1028aqds.h | 165 + roms/u-boot/include/configs/ls1028ardb.h | 153 + roms/u-boot/include/configs/ls1043a_common.h | 342 ++ roms/u-boot/include/configs/ls1043aqds.h | 402 ++ roms/u-boot/include/configs/ls1043ardb.h | 276 ++ roms/u-boot/include/configs/ls1046a_common.h | 311 ++ roms/u-boot/include/configs/ls1046afrwy.h | 131 + roms/u-boot/include/configs/ls1046aqds.h | 443 ++ roms/u-boot/include/configs/ls1046ardb.h | 197 + roms/u-boot/include/configs/ls1088a_common.h | 242 + roms/u-boot/include/configs/ls1088aqds.h | 574 +++ roms/u-boot/include/configs/ls1088ardb.h | 522 +++ roms/u-boot/include/configs/ls2080a_common.h | 220 + roms/u-boot/include/configs/ls2080aqds.h | 494 +++ roms/u-boot/include/configs/ls2080ardb.h | 586 +++ roms/u-boot/include/configs/lsxl.h | 127 + roms/u-boot/include/configs/lx2160a_common.h | 295 ++ roms/u-boot/include/configs/lx2160aqds.h | 74 + roms/u-boot/include/configs/lx2160ardb.h | 70 + roms/u-boot/include/configs/lx2162aqds.h | 78 + roms/u-boot/include/configs/m53menlo.h | 231 + roms/u-boot/include/configs/malta.h | 81 + roms/u-boot/include/configs/maxbcm.h | 72 + roms/u-boot/include/configs/mccmon6.h | 246 ++ roms/u-boot/include/configs/medcom-wide.h | 29 + roms/u-boot/include/configs/meerkat96.h | 41 + roms/u-boot/include/configs/meesc.h | 109 + roms/u-boot/include/configs/meson64.h | 97 + roms/u-boot/include/configs/meson64_android.h | 134 + roms/u-boot/include/configs/microblaze-generic.h | 172 + .../u-boot/include/configs/microchip_mpfs_icicle.h | 40 + roms/u-boot/include/configs/minnowmax.h | 25 + roms/u-boot/include/configs/miqi_rk3288.h | 16 + roms/u-boot/include/configs/mpc8308_p1m.h | 307 ++ roms/u-boot/include/configs/mt7620.h | 46 + roms/u-boot/include/configs/mt7622.h | 41 + roms/u-boot/include/configs/mt7623.h | 72 + roms/u-boot/include/configs/mt7628.h | 55 + roms/u-boot/include/configs/mt7629.h | 56 + roms/u-boot/include/configs/mt8183.h | 41 + roms/u-boot/include/configs/mt8512.h | 53 + roms/u-boot/include/configs/mt8516.h | 41 + roms/u-boot/include/configs/mt8518.h | 61 + roms/u-boot/include/configs/mv-common.h | 78 + roms/u-boot/include/configs/mv-plug-common.h | 22 + roms/u-boot/include/configs/mvebu_armada-37xx.h | 116 + roms/u-boot/include/configs/mvebu_armada-8k.h | 102 + roms/u-boot/include/configs/mx23_olinuxino.h | 118 + roms/u-boot/include/configs/mx23evk.h | 102 + roms/u-boot/include/configs/mx28evk.h | 226 + roms/u-boot/include/configs/mx51evk.h | 181 + roms/u-boot/include/configs/mx53cx9020.h | 98 + roms/u-boot/include/configs/mx53loco.h | 175 + roms/u-boot/include/configs/mx53ppd.h | 148 + roms/u-boot/include/configs/mx6_common.h | 62 + roms/u-boot/include/configs/mx6cuboxi.h | 119 + roms/u-boot/include/configs/mx6memcal.h | 46 + roms/u-boot/include/configs/mx6sabre_common.h | 180 + roms/u-boot/include/configs/mx6sabreauto.h | 75 + roms/u-boot/include/configs/mx6sabresd.h | 62 + roms/u-boot/include/configs/mx6slevk.h | 135 + roms/u-boot/include/configs/mx6sllevk.h | 134 + roms/u-boot/include/configs/mx6sxsabreauto.h | 143 + roms/u-boot/include/configs/mx6sxsabresd.h | 184 + roms/u-boot/include/configs/mx6ul_14x14_evk.h | 189 + roms/u-boot/include/configs/mx6ullevk.h | 166 + roms/u-boot/include/configs/mx7_common.h | 58 + roms/u-boot/include/configs/mx7dsabresd.h | 145 + roms/u-boot/include/configs/mx7ulp_com.h | 88 + roms/u-boot/include/configs/mx7ulp_evk.h | 138 + roms/u-boot/include/configs/mxs.h | 141 + roms/u-boot/include/configs/mys_6ulx.h | 74 + roms/u-boot/include/configs/nas220.h | 90 + roms/u-boot/include/configs/netgear_cg3100d.h | 8 + roms/u-boot/include/configs/netgear_dgnd3700v2.h | 10 + roms/u-boot/include/configs/nitrogen6x.h | 150 + roms/u-boot/include/configs/nokia_rx51.h | 249 ++ roms/u-boot/include/configs/novena.h | 184 + roms/u-boot/include/configs/npi_imx6ull.h | 96 + roms/u-boot/include/configs/nsa310s.h | 59 + roms/u-boot/include/configs/nsim.h | 37 + roms/u-boot/include/configs/nyan-big.h | 35 + roms/u-boot/include/configs/o4-imx6ull-nano.h | 33 + roms/u-boot/include/configs/octeon_common.h | 26 + roms/u-boot/include/configs/octeon_ebb7304.h | 20 + roms/u-boot/include/configs/octeon_nic23.h | 21 + roms/u-boot/include/configs/octeontx2_common.h | 71 + roms/u-boot/include/configs/octeontx_common.h | 107 + roms/u-boot/include/configs/odroid.h | 179 + roms/u-boot/include/configs/odroid_go2.h | 15 + roms/u-boot/include/configs/odroid_xu3.h | 106 + roms/u-boot/include/configs/omap3_beagle.h | 223 + roms/u-boot/include/configs/omap3_evm.h | 155 + roms/u-boot/include/configs/omap3_igep00x0.h | 97 + roms/u-boot/include/configs/omap3_logic.h | 206 + roms/u-boot/include/configs/omap4_panda.h | 32 + roms/u-boot/include/configs/omap4_sdp4430.h | 24 + roms/u-boot/include/configs/omap5_uevm.h | 61 + roms/u-boot/include/configs/omapl138_lcdk.h | 222 + roms/u-boot/include/configs/openrd.h | 77 + roms/u-boot/include/configs/opos6uldev.h | 190 + roms/u-boot/include/configs/origen.h | 87 + roms/u-boot/include/configs/owl-common.h | 36 + roms/u-boot/include/configs/p1_p2_rdb_pc.h | 771 ++++ roms/u-boot/include/configs/p2371-0000.h | 28 + roms/u-boot/include/configs/p2371-2180.h | 31 + roms/u-boot/include/configs/p2571.h | 29 + roms/u-boot/include/configs/p2771-0000.h | 43 + roms/u-boot/include/configs/p3450-0000.h | 46 + roms/u-boot/include/configs/paz00.h | 28 + roms/u-boot/include/configs/pcl063.h | 86 + roms/u-boot/include/configs/pcl063_ull.h | 106 + roms/u-boot/include/configs/pcm052.h | 159 + roms/u-boot/include/configs/pcm058.h | 65 + roms/u-boot/include/configs/pdu001.h | 78 + roms/u-boot/include/configs/peach-pi.h | 38 + roms/u-boot/include/configs/peach-pit.h | 29 + roms/u-boot/include/configs/pg-wcom-expu1.h | 53 + roms/u-boot/include/configs/pg-wcom-seli8.h | 45 + roms/u-boot/include/configs/phycore_am335x_r2.h | 125 + roms/u-boot/include/configs/phycore_imx8mm.h | 130 + roms/u-boot/include/configs/phycore_imx8mp.h | 106 + roms/u-boot/include/configs/phycore_rk3288.h | 19 + roms/u-boot/include/configs/pic32mzdask.h | 107 + roms/u-boot/include/configs/pico-imx6.h | 151 + roms/u-boot/include/configs/pico-imx6ul.h | 154 + roms/u-boot/include/configs/pico-imx7d.h | 171 + roms/u-boot/include/configs/pico-imx8mq.h | 177 + roms/u-boot/include/configs/pinebook-pro-rk3399.h | 22 + roms/u-boot/include/configs/plutux.h | 29 + roms/u-boot/include/configs/pm9261.h | 255 ++ roms/u-boot/include/configs/pm9263.h | 284 ++ roms/u-boot/include/configs/pm9g45.h | 121 + roms/u-boot/include/configs/pogo_e02.h | 61 + roms/u-boot/include/configs/poplar.h | 58 + roms/u-boot/include/configs/popmetal_rk3288.h | 12 + roms/u-boot/include/configs/porter.h | 52 + roms/u-boot/include/configs/presidio_asic.h | 92 + roms/u-boot/include/configs/puma_rk3399.h | 15 + roms/u-boot/include/configs/px30_common.h | 59 + roms/u-boot/include/configs/px30_core.h | 15 + roms/u-boot/include/configs/pxa-common.h | 34 + roms/u-boot/include/configs/pxm2.h | 124 + roms/u-boot/include/configs/qemu-arm.h | 52 + roms/u-boot/include/configs/qemu-ppce500.h | 111 + roms/u-boot/include/configs/qemu-riscv.h | 68 + roms/u-boot/include/configs/qemu-x86.h | 48 + roms/u-boot/include/configs/r2dplus.h | 59 + roms/u-boot/include/configs/rastaban.h | 84 + roms/u-boot/include/configs/rcar-gen2-common.h | 54 + roms/u-boot/include/configs/rcar-gen3-common.h | 84 + roms/u-boot/include/configs/rk3036_common.h | 51 + roms/u-boot/include/configs/rk3128_common.h | 55 + roms/u-boot/include/configs/rk3188_common.h | 63 + roms/u-boot/include/configs/rk322x_common.h | 53 + roms/u-boot/include/configs/rk3288_common.h | 65 + roms/u-boot/include/configs/rk3308_common.h | 58 + roms/u-boot/include/configs/rk3328_common.h | 54 + roms/u-boot/include/configs/rk3368_common.h | 53 + roms/u-boot/include/configs/rk3399_common.h | 78 + roms/u-boot/include/configs/roc-pc-rk3399.h | 18 + roms/u-boot/include/configs/rock.h | 12 + roms/u-boot/include/configs/rock2.h | 16 + roms/u-boot/include/configs/rock960_rk3399.h | 20 + roms/u-boot/include/configs/rockchip-common.h | 87 + roms/u-boot/include/configs/rockpro64_rk3399.h | 20 + roms/u-boot/include/configs/rpi.h | 213 + roms/u-boot/include/configs/rut.h | 119 + roms/u-boot/include/configs/rv1108_common.h | 43 + roms/u-boot/include/configs/s5p4418_nanopi2.h | 219 + roms/u-boot/include/configs/s5p_goni.h | 167 + roms/u-boot/include/configs/s5pc210_universal.h | 159 + roms/u-boot/include/configs/sagem_f@st1704.h | 8 + roms/u-boot/include/configs/salvator-x.h | 32 + roms/u-boot/include/configs/sam9x60ek.h | 86 + roms/u-boot/include/configs/sama5d27_som1_ek.h | 52 + roms/u-boot/include/configs/sama5d27_wlsom1_ek.h | 45 + roms/u-boot/include/configs/sama5d2_icp.h | 62 + roms/u-boot/include/configs/sama5d2_ptc_ek.h | 38 + roms/u-boot/include/configs/sama5d2_xplained.h | 73 + roms/u-boot/include/configs/sama5d3_xplained.h | 82 + roms/u-boot/include/configs/sama5d3xek.h | 94 + roms/u-boot/include/configs/sama5d4_xplained.h | 58 + roms/u-boot/include/configs/sama5d4ek.h | 58 + roms/u-boot/include/configs/sama7g5ek.h | 45 + roms/u-boot/include/configs/sandbox.h | 133 + roms/u-boot/include/configs/sandbox_spl.h | 11 + roms/u-boot/include/configs/sbc8349.h | 322 ++ roms/u-boot/include/configs/sbc8548.h | 540 +++ roms/u-boot/include/configs/sbc8641d.h | 509 +++ roms/u-boot/include/configs/seaboard.h | 39 + roms/u-boot/include/configs/sei510.h | 32 + roms/u-boot/include/configs/sei610.h | 31 + roms/u-boot/include/configs/sfr_nb4_ser.h | 10 + roms/u-boot/include/configs/sheep_rk3368.h | 15 + roms/u-boot/include/configs/sheevaplug.h | 62 + roms/u-boot/include/configs/siemens-am33x-common.h | 449 ++ roms/u-boot/include/configs/siemens-ccp-common.h | 19 + roms/u-boot/include/configs/siemens-env-common.h | 201 + roms/u-boot/include/configs/sifive-unleashed.h | 86 + roms/u-boot/include/configs/sifive-unmatched.h | 83 + roms/u-boot/include/configs/silinux-ek874.h | 20 + roms/u-boot/include/configs/silk.h | 52 + roms/u-boot/include/configs/sipeed-maix.h | 32 + roms/u-boot/include/configs/slimbootloader.h | 49 + roms/u-boot/include/configs/smartweb.h | 211 + roms/u-boot/include/configs/smdk5250.h | 21 + roms/u-boot/include/configs/smdk5420.h | 33 + roms/u-boot/include/configs/smdkc100.h | 150 + roms/u-boot/include/configs/smdkv310.h | 74 + roms/u-boot/include/configs/smegw01.h | 63 + roms/u-boot/include/configs/snapper9260.h | 115 + roms/u-boot/include/configs/snapper9g45.h | 99 + roms/u-boot/include/configs/sniper.h | 142 + roms/u-boot/include/configs/snow.h | 20 + roms/u-boot/include/configs/socfpga_agilex_socdk.h | 12 + .../u-boot/include/configs/socfpga_arria10_socdk.h | 45 + roms/u-boot/include/configs/socfpga_arria5_secu1.h | 126 + roms/u-boot/include/configs/socfpga_arria5_socdk.h | 20 + roms/u-boot/include/configs/socfpga_common.h | 254 ++ .../include/configs/socfpga_cyclone5_socdk.h | 20 + roms/u-boot/include/configs/socfpga_dbm_soc1.h | 94 + roms/u-boot/include/configs/socfpga_de0_nano_soc.h | 20 + roms/u-boot/include/configs/socfpga_de10_nano.h | 20 + roms/u-boot/include/configs/socfpga_de1_soc.h | 20 + roms/u-boot/include/configs/socfpga_is1.h | 32 + roms/u-boot/include/configs/socfpga_mcvevk.h | 101 + roms/u-boot/include/configs/socfpga_soc64_common.h | 213 + roms/u-boot/include/configs/socfpga_sockit.h | 20 + roms/u-boot/include/configs/socfpga_socrates.h | 20 + roms/u-boot/include/configs/socfpga_sr1500.h | 35 + .../include/configs/socfpga_stratix10_socdk.h | 12 + roms/u-boot/include/configs/socfpga_vining_fpga.h | 201 + roms/u-boot/include/configs/socrates.h | 284 ++ roms/u-boot/include/configs/som-db5800-som-6867.h | 24 + .../include/configs/somlabs_visionsom_6ull.h | 107 + roms/u-boot/include/configs/spear-common.h | 168 + roms/u-boot/include/configs/spear3xx_evb.h | 141 + roms/u-boot/include/configs/spear6xx_evb.h | 36 + roms/u-boot/include/configs/spring.h | 15 + roms/u-boot/include/configs/stemmy.h | 29 + roms/u-boot/include/configs/stih410-b2260.h | 75 + roms/u-boot/include/configs/stm32f429-discovery.h | 47 + roms/u-boot/include/configs/stm32f429-evaluation.h | 54 + roms/u-boot/include/configs/stm32f469-discovery.h | 54 + roms/u-boot/include/configs/stm32f746-disco.h | 80 + roms/u-boot/include/configs/stm32h743-disco.h | 48 + roms/u-boot/include/configs/stm32h743-eval.h | 48 + roms/u-boot/include/configs/stm32h750-art-pi.h | 48 + roms/u-boot/include/configs/stm32mp1.h | 178 + roms/u-boot/include/configs/stmark2.h | 169 + roms/u-boot/include/configs/stout.h | 56 + roms/u-boot/include/configs/stv0991.h | 50 + roms/u-boot/include/configs/sun4i.h | 21 + roms/u-boot/include/configs/sun50i.h | 26 + roms/u-boot/include/configs/sun5i.h | 21 + roms/u-boot/include/configs/sun6i.h | 25 + roms/u-boot/include/configs/sun7i.h | 25 + roms/u-boot/include/configs/sun8i.h | 20 + roms/u-boot/include/configs/sun9i.h | 20 + roms/u-boot/include/configs/sunxi-common.h | 471 ++ roms/u-boot/include/configs/syzygy_hub.h | 65 + roms/u-boot/include/configs/t4qds.h | 240 + roms/u-boot/include/configs/tam3517-common.h | 308 ++ roms/u-boot/include/configs/taurus.h | 211 + roms/u-boot/include/configs/tb100.h | 60 + roms/u-boot/include/configs/tbs2910.h | 109 + roms/u-boot/include/configs/tec-ng.h | 32 + roms/u-boot/include/configs/tec.h | 29 + roms/u-boot/include/configs/tegra-common-post.h | 121 + .../include/configs/tegra-common-usb-gadget.h | 20 + roms/u-boot/include/configs/tegra-common.h | 83 + roms/u-boot/include/configs/tegra114-common.h | 65 + roms/u-boot/include/configs/tegra124-common.h | 70 + roms/u-boot/include/configs/tegra186-common.h | 61 + roms/u-boot/include/configs/tegra20-common.h | 87 + roms/u-boot/include/configs/tegra210-common.h | 60 + roms/u-boot/include/configs/tegra30-common.h | 62 + .../include/configs/theadorable-x86-common.h | 143 + .../configs/theadorable-x86-conga-qa3-e3845.h | 29 + .../include/configs/theadorable-x86-dfi-bt700.h | 32 + roms/u-boot/include/configs/theadorable.h | 102 + roms/u-boot/include/configs/thuban.h | 77 + roms/u-boot/include/configs/thunderx_88xx.h | 69 + roms/u-boot/include/configs/ti814x_evm.h | 148 + roms/u-boot/include/configs/ti816x_evm.h | 107 + roms/u-boot/include/configs/ti_am335x_common.h | 62 + roms/u-boot/include/configs/ti_armv7_common.h | 212 + roms/u-boot/include/configs/ti_armv7_keystone2.h | 283 ++ roms/u-boot/include/configs/ti_armv7_omap.h | 28 + roms/u-boot/include/configs/ti_omap3_common.h | 68 + roms/u-boot/include/configs/ti_omap4_common.h | 130 + roms/u-boot/include/configs/ti_omap5_common.h | 107 + roms/u-boot/include/configs/tinker_rk3288.h | 25 + roms/u-boot/include/configs/topic_miami.h | 106 + roms/u-boot/include/configs/total_compute.h | 89 + roms/u-boot/include/configs/tplink_wdr4300.h | 55 + roms/u-boot/include/configs/tqma6.h | 328 ++ roms/u-boot/include/configs/tqma6_mba6.h | 20 + roms/u-boot/include/configs/tqma6_wru4.h | 35 + roms/u-boot/include/configs/trats.h | 182 + roms/u-boot/include/configs/trats2.h | 163 + roms/u-boot/include/configs/trimslice.h | 30 + roms/u-boot/include/configs/tuge1.h | 34 + roms/u-boot/include/configs/turris_mox.h | 96 + roms/u-boot/include/configs/turris_omnia.h | 144 + roms/u-boot/include/configs/tuxx1.h | 38 + roms/u-boot/include/configs/udoo.h | 74 + roms/u-boot/include/configs/udoo_neo.h | 86 + roms/u-boot/include/configs/ulcb.h | 32 + roms/u-boot/include/configs/uniphier.h | 213 + roms/u-boot/include/configs/usb_a9263.h | 86 + roms/u-boot/include/configs/usbarmory.h | 94 + roms/u-boot/include/configs/vcoreiii.h | 64 + roms/u-boot/include/configs/ve8313.h | 260 ++ roms/u-boot/include/configs/venice2.h | 29 + roms/u-boot/include/configs/ventana.h | 26 + roms/u-boot/include/configs/verdin-imx8mm.h | 128 + roms/u-boot/include/configs/vexpress_aemv8a.h | 227 + roms/u-boot/include/configs/vexpress_common.h | 241 + roms/u-boot/include/configs/veyron.h | 18 + roms/u-boot/include/configs/vf610twr.h | 180 + roms/u-boot/include/configs/vinco.h | 102 + roms/u-boot/include/configs/vining_2000.h | 86 + roms/u-boot/include/configs/vme8349.h | 315 ++ roms/u-boot/include/configs/vocore2.h | 53 + roms/u-boot/include/configs/vyasa-rk3288.h | 38 + roms/u-boot/include/configs/wandboard.h | 121 + roms/u-boot/include/configs/warp.h | 144 + roms/u-boot/include/configs/warp7.h | 160 + roms/u-boot/include/configs/work_92105.h | 143 + roms/u-boot/include/configs/x530.h | 103 + roms/u-boot/include/configs/x600.h | 228 + roms/u-boot/include/configs/x86-chromebook.h | 35 + roms/u-boot/include/configs/x86-common.h | 130 + roms/u-boot/include/configs/xea.h | 193 + roms/u-boot/include/configs/xenguest_arm64.h | 44 + roms/u-boot/include/configs/xilinx_versal.h | 164 + roms/u-boot/include/configs/xilinx_versal_mini.h | 27 + .../include/configs/xilinx_versal_mini_qspi.h | 18 + roms/u-boot/include/configs/xilinx_zynqmp.h | 271 ++ roms/u-boot/include/configs/xilinx_zynqmp_mini.h | 29 + .../include/configs/xilinx_zynqmp_mini_emmc.h | 18 + .../include/configs/xilinx_zynqmp_mini_nand.h | 20 + .../include/configs/xilinx_zynqmp_mini_qspi.h | 18 + roms/u-boot/include/configs/xilinx_zynqmp_r5.h | 37 + roms/u-boot/include/configs/xpedite517x.h | 646 +++ roms/u-boot/include/configs/xpedite520x.h | 445 ++ roms/u-boot/include/configs/xpedite537x.h | 496 +++ roms/u-boot/include/configs/xpedite550x.h | 494 +++ roms/u-boot/include/configs/xpress.h | 124 + roms/u-boot/include/configs/xtfpga.h | 225 + roms/u-boot/include/configs/zmx25.h | 91 + roms/u-boot/include/configs/zynq-common.h | 272 ++ roms/u-boot/include/configs/zynq_cse.h | 32 + roms/u-boot/include/console.h | 148 + roms/u-boot/include/cortina.h | 78 + roms/u-boot/include/cp1250.h | 40 + roms/u-boot/include/cp437.h | 40 + roms/u-boot/include/cpsw.h | 85 + roms/u-boot/include/cpu.h | 165 + roms/u-boot/include/cpu_func.h | 89 + roms/u-boot/include/cramfs/cramfs_fs.h | 100 + roms/u-boot/include/cros_ec.h | 655 +++ roms/u-boot/include/cros_ec_message.h | 28 + roms/u-boot/include/crypto/internal/rsa.h | 57 + roms/u-boot/include/crypto/pkcs7.h | 54 + roms/u-boot/include/crypto/pkcs7_parser.h | 69 + roms/u-boot/include/crypto/public_key.h | 90 + roms/u-boot/include/crypto/x509_parser.h | 61 + roms/u-boot/include/ctype.h | 1 + roms/u-boot/include/ddr_spd.h | 564 +++ roms/u-boot/include/debug_uart.h | 200 + roms/u-boot/include/dfu.h | 554 +++ roms/u-boot/include/dialog_pmic.h | 173 + roms/u-boot/include/display.h | 97 + roms/u-boot/include/display_options.h | 77 + roms/u-boot/include/div64.h | 244 + roms/u-boot/include/dm-demo.h | 37 + roms/u-boot/include/dm.h | 20 + roms/u-boot/include/dm/acpi.h | 241 + roms/u-boot/include/dm/device-internal.h | 429 ++ roms/u-boot/include/dm/device.h | 997 +++++ roms/u-boot/include/dm/device_compat.h | 121 + roms/u-boot/include/dm/devres.h | 293 ++ roms/u-boot/include/dm/fdtaddr.h | 149 + roms/u-boot/include/dm/lists.h | 93 + roms/u-boot/include/dm/of.h | 134 + roms/u-boot/include/dm/of_access.h | 507 +++ roms/u-boot/include/dm/of_addr.h | 98 + roms/u-boot/include/dm/of_extra.h | 117 + roms/u-boot/include/dm/ofnode.h | 1083 +++++ roms/u-boot/include/dm/pci.h | 43 + roms/u-boot/include/dm/pinctrl.h | 626 +++ roms/u-boot/include/dm/platdata.h | 74 + roms/u-boot/include/dm/platform_data/fsl_espi.h | 16 + .../include/dm/platform_data/lpc32xx_hsuart.h | 18 + roms/u-boot/include/dm/platform_data/net_ethoc.h | 20 + roms/u-boot/include/dm/platform_data/pfe_dm_eth.h | 20 + roms/u-boot/include/dm/platform_data/pxa_mmc_gen.h | 22 + .../include/dm/platform_data/serial_bcm283x_mu.h | 23 + .../include/dm/platform_data/serial_coldfire.h | 22 + roms/u-boot/include/dm/platform_data/serial_mxc.h | 15 + .../u-boot/include/dm/platform_data/serial_pl01x.h | 30 + roms/u-boot/include/dm/platform_data/serial_pxa.h | 55 + roms/u-boot/include/dm/platform_data/serial_sh.h | 36 + .../u-boot/include/dm/platform_data/spi_coldfire.h | 29 + roms/u-boot/include/dm/platform_data/spi_davinci.h | 15 + roms/u-boot/include/dm/platform_data/spi_pl022.h | 21 + roms/u-boot/include/dm/read.h | 1078 +++++ roms/u-boot/include/dm/root.h | 134 + roms/u-boot/include/dm/simple_bus.h | 15 + roms/u-boot/include/dm/test.h | 226 + roms/u-boot/include/dm/uclass-id.h | 137 + roms/u-boot/include/dm/uclass-internal.h | 315 ++ roms/u-boot/include/dm/uclass.h | 482 ++ roms/u-boot/include/dm/util.h | 60 + roms/u-boot/include/dm9000.h | 16 + roms/u-boot/include/dma-uclass.h | 139 + roms/u-boot/include/dma.h | 345 ++ roms/u-boot/include/dp83848.h | 84 + roms/u-boot/include/ds1722.h | 14 + roms/u-boot/include/dsi_host.h | 73 + .../include/dt-bindings/arm/ux500_pm_domains.h | 15 + roms/u-boot/include/dt-bindings/bus/ti-sysc.h | 28 + roms/u-boot/include/dt-bindings/clk/at91.h | 22 + roms/u-boot/include/dt-bindings/clk/mpc83xx-clk.h | 33 + roms/u-boot/include/dt-bindings/clk/ti-dra7-atl.h | 40 + roms/u-boot/include/dt-bindings/clk/versaclock.h | 13 + .../include/dt-bindings/clock/actions,s700-cmu.h | 118 + .../include/dt-bindings/clock/actions,s900-cmu.h | 129 + .../include/dt-bindings/clock/agilex-clock.h | 71 + roms/u-boot/include/dt-bindings/clock/am3.h | 227 + .../include/dt-bindings/clock/aspeed-clock.h | 42 + .../include/dt-bindings/clock/ast2600-clock.h | 62 + roms/u-boot/include/dt-bindings/clock/at91.h | 23 + roms/u-boot/include/dt-bindings/clock/axg-aoclkc.h | 31 + .../include/dt-bindings/clock/axg-audio-clkc.h | 94 + roms/u-boot/include/dt-bindings/clock/axg-clkc.h | 76 + .../u-boot/include/dt-bindings/clock/bcm2835-aux.h | 9 + roms/u-boot/include/dt-bindings/clock/bcm2835.h | 60 + .../include/dt-bindings/clock/bcm3380-clock.h | 22 + .../include/dt-bindings/clock/bcm6318-clock.h | 47 + .../include/dt-bindings/clock/bcm63268-clock.h | 51 + .../include/dt-bindings/clock/bcm6328-clock.h | 24 + .../include/dt-bindings/clock/bcm6338-clock.h | 18 + .../include/dt-bindings/clock/bcm6348-clock.h | 21 + .../include/dt-bindings/clock/bcm6358-clock.h | 23 + .../include/dt-bindings/clock/bcm6362-clock.h | 32 + .../include/dt-bindings/clock/bcm6368-clock.h | 30 + .../include/dt-bindings/clock/boston-clock.h | 12 + .../include/dt-bindings/clock/exynos7420-clk.h | 207 + .../u-boot/include/dt-bindings/clock/g12a-aoclkc.h | 36 + roms/u-boot/include/dt-bindings/clock/g12a-clkc.h | 151 + .../u-boot/include/dt-bindings/clock/gxbb-aoclkc.h | 74 + roms/u-boot/include/dt-bindings/clock/gxbb-clkc.h | 151 + .../include/dt-bindings/clock/hi3660-clock.h | 214 + .../include/dt-bindings/clock/hi6220-clock.h | 173 + .../u-boot/include/dt-bindings/clock/histb-clock.h | 82 + roms/u-boot/include/dt-bindings/clock/imx5-clock.h | 219 + .../include/dt-bindings/clock/imx6qdl-clock.h | 274 ++ .../include/dt-bindings/clock/imx6sl-clock.h | 180 + .../include/dt-bindings/clock/imx6sll-clock.h | 204 + .../include/dt-bindings/clock/imx6sx-clock.h | 281 ++ .../include/dt-bindings/clock/imx6ul-clock.h | 262 ++ .../u-boot/include/dt-bindings/clock/imx7d-clock.h | 459 ++ .../include/dt-bindings/clock/imx7ulp-clock.h | 161 + .../include/dt-bindings/clock/imx8mm-clock.h | 279 ++ .../include/dt-bindings/clock/imx8mn-clock.h | 239 + .../include/dt-bindings/clock/imx8mp-clock.h | 389 ++ .../include/dt-bindings/clock/imx8mq-clock.h | 436 ++ .../include/dt-bindings/clock/imx8qm-clock.h | 846 ++++ .../include/dt-bindings/clock/imx8qxp-clock.h | 583 +++ .../include/dt-bindings/clock/imxrt1020-clock.h | 52 + .../include/dt-bindings/clock/imxrt1050-clock.h | 67 + .../u-boot/include/dt-bindings/clock/intel-clock.h | 15 + roms/u-boot/include/dt-bindings/clock/jz4780-cgu.h | 89 + .../u-boot/include/dt-bindings/clock/k210-sysctl.h | 60 + .../include/dt-bindings/clock/maxim,max77802.h | 22 + .../include/dt-bindings/clock/microchip,clock.h | 28 + .../dt-bindings/clock/microchip-mpfs-clock.h | 45 + roms/u-boot/include/dt-bindings/clock/mt7620-clk.h | 40 + roms/u-boot/include/dt-bindings/clock/mt7622-clk.h | 271 ++ roms/u-boot/include/dt-bindings/clock/mt7623-clk.h | 413 ++ roms/u-boot/include/dt-bindings/clock/mt7628-clk.h | 37 + roms/u-boot/include/dt-bindings/clock/mt7629-clk.h | 206 + roms/u-boot/include/dt-bindings/clock/mt8183-clk.h | 329 ++ roms/u-boot/include/dt-bindings/clock/mt8512-clk.h | 197 + roms/u-boot/include/dt-bindings/clock/mt8516-clk.h | 251 ++ roms/u-boot/include/dt-bindings/clock/mt8518-clk.h | 249 ++ .../include/dt-bindings/clock/octeon-clock.h | 12 + roms/u-boot/include/dt-bindings/clock/omap4.h | 149 + roms/u-boot/include/dt-bindings/clock/omap5.h | 129 + roms/u-boot/include/dt-bindings/clock/px30-cru.h | 389 ++ .../include/dt-bindings/clock/qcom,ipq4019-gcc.h | 96 + .../include/dt-bindings/clock/r7s72100-clock.h | 112 + .../include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 59 + .../include/dt-bindings/clock/r8a774b1-cpg-mssr.h | 57 + .../include/dt-bindings/clock/r8a774c0-cpg-mssr.h | 61 + .../include/dt-bindings/clock/r8a774e1-cpg-mssr.h | 59 + .../include/dt-bindings/clock/r8a7790-clock.h | 158 + .../include/dt-bindings/clock/r8a7790-cpg-mssr.h | 48 + .../include/dt-bindings/clock/r8a7791-clock.h | 161 + .../include/dt-bindings/clock/r8a7791-cpg-mssr.h | 44 + .../include/dt-bindings/clock/r8a7792-clock.h | 98 + .../include/dt-bindings/clock/r8a7792-cpg-mssr.h | 39 + .../include/dt-bindings/clock/r8a7793-clock.h | 159 + .../include/dt-bindings/clock/r8a7793-cpg-mssr.h | 44 + .../include/dt-bindings/clock/r8a7794-clock.h | 137 + .../include/dt-bindings/clock/r8a7794-cpg-mssr.h | 43 + .../include/dt-bindings/clock/r8a7795-cpg-mssr.h | 66 + .../include/dt-bindings/clock/r8a7796-cpg-mssr.h | 65 + .../include/dt-bindings/clock/r8a77965-cpg-mssr.h | 62 + .../include/dt-bindings/clock/r8a77970-cpg-mssr.h | 48 + .../include/dt-bindings/clock/r8a77980-cpg-mssr.h | 51 + .../include/dt-bindings/clock/r8a77990-cpg-mssr.h | 62 + .../include/dt-bindings/clock/r8a77995-cpg-mssr.h | 54 + .../include/dt-bindings/clock/renesas-cpg-mssr.h | 15 + roms/u-boot/include/dt-bindings/clock/rk3036-cru.h | 185 + .../u-boot/include/dt-bindings/clock/rk3066a-cru.h | 31 + roms/u-boot/include/dt-bindings/clock/rk3128-cru.h | 189 + .../include/dt-bindings/clock/rk3188-cru-common.h | 255 ++ roms/u-boot/include/dt-bindings/clock/rk3188-cru.h | 47 + roms/u-boot/include/dt-bindings/clock/rk3228-cru.h | 237 + roms/u-boot/include/dt-bindings/clock/rk3288-cru.h | 370 ++ roms/u-boot/include/dt-bindings/clock/rk3308-cru.h | 387 ++ roms/u-boot/include/dt-bindings/clock/rk3328-cru.h | 393 ++ roms/u-boot/include/dt-bindings/clock/rk3368-cru.h | 381 ++ roms/u-boot/include/dt-bindings/clock/rk3399-cru.h | 749 ++++ .../include/dt-bindings/clock/rockchip,rk808.h | 11 + roms/u-boot/include/dt-bindings/clock/rv1108-cru.h | 356 ++ .../include/dt-bindings/clock/sifive-fu540-prci.h | 18 + .../include/dt-bindings/clock/sifive-fu740-prci.h | 25 + .../include/dt-bindings/clock/snps,hsdk-cgu.h | 43 + roms/u-boot/include/dt-bindings/clock/ste-ab8500.h | 12 + .../include/dt-bindings/clock/stih407-clks.h | 90 + .../include/dt-bindings/clock/stih410-clks.h | 25 + .../include/dt-bindings/clock/stm32fx-clock.h | 63 + .../include/dt-bindings/clock/stm32h7-clks.h | 167 + .../include/dt-bindings/clock/stm32mp1-clks.h | 251 ++ .../include/dt-bindings/clock/stm32mp1-clksrc.h | 284 ++ .../include/dt-bindings/clock/sun4i-a10-ccu.h | 202 + .../include/dt-bindings/clock/sun4i-a10-pll2.h | 53 + .../include/dt-bindings/clock/sun50i-a64-ccu.h | 138 + .../include/dt-bindings/clock/sun50i-h6-ccu.h | 125 + .../include/dt-bindings/clock/sun50i-h6-r-ccu.h | 26 + .../include/dt-bindings/clock/sun50i-h616-ccu.h | 115 + roms/u-boot/include/dt-bindings/clock/sun5i-ccu.h | 106 + .../include/dt-bindings/clock/sun6i-a31-ccu.h | 191 + .../include/dt-bindings/clock/sun7i-a20-ccu.h | 53 + .../include/dt-bindings/clock/sun8i-a23-a33-ccu.h | 127 + .../include/dt-bindings/clock/sun8i-a83t-ccu.h | 140 + roms/u-boot/include/dt-bindings/clock/sun8i-de2.h | 21 + .../include/dt-bindings/clock/sun8i-h3-ccu.h | 152 + .../u-boot/include/dt-bindings/clock/sun8i-r-ccu.h | 59 + .../include/dt-bindings/clock/sun8i-r40-ccu.h | 191 + .../include/dt-bindings/clock/sun8i-tcon-top.h | 11 + .../include/dt-bindings/clock/sun8i-v3s-ccu.h | 107 + .../include/dt-bindings/clock/sun9i-a80-ccu.h | 162 + .../include/dt-bindings/clock/sun9i-a80-de.h | 80 + .../include/dt-bindings/clock/sun9i-a80-usb.h | 59 + .../include/dt-bindings/clock/tegra114-car.h | 343 ++ .../dt-bindings/clock/tegra124-car-common.h | 345 ++ .../include/dt-bindings/clock/tegra124-car.h | 19 + .../include/dt-bindings/clock/tegra186-clock.h | 940 ++++ .../u-boot/include/dt-bindings/clock/tegra20-car.h | 158 + .../include/dt-bindings/clock/tegra210-car.h | 401 ++ .../u-boot/include/dt-bindings/clock/tegra30-car.h | 273 ++ .../include/dt-bindings/clock/xlnx-versal-clk.h | 123 + .../include/dt-bindings/clock/xlnx-zynqmp-clk.h | 126 + .../include/dt-bindings/comphy/comphy_data.h | 54 + roms/u-boot/include/dt-bindings/display/tda998x.h | 8 + roms/u-boot/include/dt-bindings/dma/at91.h | 52 + roms/u-boot/include/dt-bindings/dma/bcm6318-dma.h | 14 + roms/u-boot/include/dt-bindings/dma/bcm63268-dma.h | 14 + roms/u-boot/include/dt-bindings/dma/bcm6328-dma.h | 14 + roms/u-boot/include/dt-bindings/dma/bcm6338-dma.h | 14 + roms/u-boot/include/dt-bindings/dma/bcm6348-dma.h | 16 + roms/u-boot/include/dt-bindings/dma/bcm6358-dma.h | 16 + roms/u-boot/include/dt-bindings/dma/bcm6362-dma.h | 14 + roms/u-boot/include/dt-bindings/dma/bcm6368-dma.h | 14 + roms/u-boot/include/dt-bindings/dma/sun4i-a10.h | 56 + .../include/dt-bindings/dma/xlnx-zynqmp-dpdma.h | 16 + roms/u-boot/include/dt-bindings/gpio/gpio.h | 42 + .../include/dt-bindings/gpio/meson-axg-gpio.h | 116 + .../include/dt-bindings/gpio/meson-g12a-gpio.h | 114 + .../include/dt-bindings/gpio/meson-gxbb-gpio.h | 148 + .../include/dt-bindings/gpio/meson-gxl-gpio.h | 125 + .../u-boot/include/dt-bindings/gpio/sandbox-gpio.h | 24 + roms/u-boot/include/dt-bindings/gpio/tegra-gpio.h | 51 + .../include/dt-bindings/gpio/tegra186-gpio.h | 59 + .../include/dt-bindings/gpio/uniphier-gpio.h | 18 + roms/u-boot/include/dt-bindings/gpio/x86-gpio.h | 43 + roms/u-boot/include/dt-bindings/input/gpio-keys.h | 13 + roms/u-boot/include/dt-bindings/input/input.h | 17 + .../include/dt-bindings/input/linux-event-codes.h | 805 ++++ .../dt-bindings/interrupt-controller/arm-gic.h | 23 + .../dt-bindings/interrupt-controller/irq-st.h | 30 + .../include/dt-bindings/interrupt-controller/irq.h | 19 + .../dt-bindings/interrupt-controller/mips-gic.h | 9 + .../dt-bindings/interrupt-controller/x86-irq.h | 14 + .../dt-bindings/interrupt-router/intel-irq.h | 30 + roms/u-boot/include/dt-bindings/leds/common.h | 75 + .../u-boot/include/dt-bindings/leds/leds-netxbig.h | 18 + roms/u-boot/include/dt-bindings/leds/leds-ns2.h | 9 + .../u-boot/include/dt-bindings/leds/leds-pca9532.h | 18 + .../include/dt-bindings/mailbox/tegra186-hsp.h | 19 + roms/u-boot/include/dt-bindings/media/omap3-isp.h | 22 + roms/u-boot/include/dt-bindings/media/tda1997x.h | 74 + .../u-boot/include/dt-bindings/memory/bcm-ns3-mc.h | 63 + .../include/dt-bindings/memory/imxrt-sdram.h | 100 + .../include/dt-bindings/memory/mpc83xx-sdram.h | 161 + .../u-boot/include/dt-bindings/memory/rk3368-dmc.h | 30 + .../include/dt-bindings/memory/stm32-sdram.h | 48 + .../include/dt-bindings/memory/tegra114-mc.h | 25 + .../include/dt-bindings/memory/tegra124-mc.h | 31 + .../include/dt-bindings/memory/tegra210-mc.h | 36 + .../u-boot/include/dt-bindings/memory/tegra30-mc.h | 24 + roms/u-boot/include/dt-bindings/mfd/dbx500-prcmu.h | 84 + roms/u-boot/include/dt-bindings/mfd/k210-sysctl.h | 38 + roms/u-boot/include/dt-bindings/mfd/st,stpmic1.h | 50 + roms/u-boot/include/dt-bindings/mfd/st-lpc.h | 16 + roms/u-boot/include/dt-bindings/mfd/stm32f4-rcc.h | 108 + roms/u-boot/include/dt-bindings/mfd/stm32f7-rcc.h | 115 + roms/u-boot/include/dt-bindings/mfd/stm32h7-rcc.h | 138 + roms/u-boot/include/dt-bindings/mrc/quark.h | 82 + roms/u-boot/include/dt-bindings/mscc/jr2_data.h | 19 + roms/u-boot/include/dt-bindings/mscc/luton_data.h | 17 + roms/u-boot/include/dt-bindings/mscc/ocelot_data.h | 19 + roms/u-boot/include/dt-bindings/mscc/serval_data.h | 19 + roms/u-boot/include/dt-bindings/mux/mux.h | 17 + roms/u-boot/include/dt-bindings/mux/ti-serdes.h | 93 + .../include/dt-bindings/net/microchip-lan78xx.h | 21 + .../include/dt-bindings/net/mscc-phy-vsc8531.h | 40 + roms/u-boot/include/dt-bindings/net/qca-ar803x.h | 13 + roms/u-boot/include/dt-bindings/net/ti-dp83867.h | 50 + .../include/dt-bindings/phy/phy-am654-serdes.h | 13 + roms/u-boot/include/dt-bindings/phy/phy.h | 23 + roms/u-boot/include/dt-bindings/pinctrl/am33xx.h | 43 + roms/u-boot/include/dt-bindings/pinctrl/am43xx.h | 39 + roms/u-boot/include/dt-bindings/pinctrl/at91.h | 49 + roms/u-boot/include/dt-bindings/pinctrl/bcm2835.h | 26 + .../include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h | 41 + roms/u-boot/include/dt-bindings/pinctrl/dra.h | 80 + roms/u-boot/include/dt-bindings/pinctrl/hisi.h | 74 + .../include/dt-bindings/pinctrl/k210-pinctrl.h | 277 ++ roms/u-boot/include/dt-bindings/pinctrl/k3.h | 44 + roms/u-boot/include/dt-bindings/pinctrl/omap.h | 93 + .../include/dt-bindings/pinctrl/pads-imx8qm.h | 961 ++++ .../include/dt-bindings/pinctrl/pads-imx8qxp.h | 757 ++++ .../dt-bindings/pinctrl/pinctrl-snapdragon.h | 22 + .../dt-bindings/pinctrl/pinctrl-tegra-xusb.h | 7 + .../include/dt-bindings/pinctrl/pinctrl-tegra.h | 37 + .../include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 19 + .../include/dt-bindings/pinctrl/pins-imx8mq.h | 632 +++ .../include/dt-bindings/pinctrl/pins-imxrt1020.h | 761 ++++ .../include/dt-bindings/pinctrl/pins-imxrt1050.h | 993 +++++ .../include/dt-bindings/pinctrl/r7s72100-pinctrl.h | 18 + roms/u-boot/include/dt-bindings/pinctrl/rockchip.h | 60 + .../include/dt-bindings/pinctrl/sandbox-pinmux.h | 19 + .../include/dt-bindings/pinctrl/stm32-pinfunc.h | 42 + .../u-boot/include/dt-bindings/pinctrl/sun4i-a10.h | 62 + .../u-boot/include/dt-bindings/pmic/sandbox_pmic.h | 34 + .../power-domain/bcm6318-power-domain.h | 12 + .../power-domain/bcm63268-power-domain.h | 24 + .../power-domain/bcm6328-power-domain.h | 20 + .../power-domain/bcm6362-power-domain.h | 24 + .../include/dt-bindings/power-domain/rk3288.h | 11 + roms/u-boot/include/dt-bindings/power/imx7-power.h | 16 + .../include/dt-bindings/power/imx8mm-power.h | 22 + .../include/dt-bindings/power/imx8mn-power.h | 15 + .../include/dt-bindings/power/imx8mq-power.h | 21 + .../include/dt-bindings/power/meson-axg-power.h | 14 + .../include/dt-bindings/power/meson-g12a-power.h | 13 + .../include/dt-bindings/power/meson-gxbb-power.h | 13 + .../include/dt-bindings/power/meson-sm1-power.h | 18 + .../include/dt-bindings/power/mt7623-power.h | 19 + .../include/dt-bindings/power/mt7629-power.h | 13 + roms/u-boot/include/dt-bindings/power/px30-power.h | 27 + .../include/dt-bindings/power/r8a774a1-sysc.h | 31 + .../include/dt-bindings/power/r8a774b1-sysc.h | 26 + .../include/dt-bindings/power/r8a774c0-sysc.h | 25 + .../include/dt-bindings/power/r8a774e1-sysc.h | 36 + .../include/dt-bindings/power/r8a7790-sysc.h | 31 + .../include/dt-bindings/power/r8a7791-sysc.h | 23 + .../include/dt-bindings/power/r8a7792-sysc.h | 23 + .../include/dt-bindings/power/r8a7793-sysc.h | 25 + .../include/dt-bindings/power/r8a7794-sysc.h | 26 + .../include/dt-bindings/power/r8a7795-sysc.h | 42 + .../include/dt-bindings/power/r8a7796-sysc.h | 36 + .../include/dt-bindings/power/r8a77965-sysc.h | 29 + .../include/dt-bindings/power/r8a77970-sysc.h | 31 + .../include/dt-bindings/power/r8a77980-sysc.h | 43 + .../include/dt-bindings/power/r8a77990-sysc.h | 26 + .../include/dt-bindings/power/r8a77995-sysc.h | 23 + .../include/dt-bindings/power/raspberrypi-power.h | 41 + .../include/dt-bindings/power/rk3328-power.h | 19 + .../include/dt-bindings/power/rk3399-power.h | 53 + .../include/dt-bindings/power/tegra186-powergate.h | 28 + .../include/dt-bindings/power/xlnx-versal-power.h | 42 + .../include/dt-bindings/power/xlnx-zynqmp-power.h | 39 + roms/u-boot/include/dt-bindings/pwm/pwm.h | 14 + .../dt-bindings/regulator/dlg,da9063-regulator.h | 16 + .../include/dt-bindings/regulator/maxim,max77802.h | 18 + .../include/dt-bindings/reset/actions,s700-reset.h | 34 + .../include/dt-bindings/reset/actions,s900-reset.h | 65 + .../include/dt-bindings/reset/altr,rst-mgr-a10.h | 110 + .../include/dt-bindings/reset/altr,rst-mgr-s10.h | 96 + .../include/dt-bindings/reset/altr,rst-mgr.h | 82 + .../reset/amlogic,meson-axg-audio-arb.h | 19 + .../dt-bindings/reset/amlogic,meson-axg-reset.h | 123 + .../reset/amlogic,meson-g12a-audio-reset.h | 53 + .../dt-bindings/reset/amlogic,meson-g12a-reset.h | 137 + .../dt-bindings/reset/amlogic,meson-gxbb-reset.h | 161 + .../include/dt-bindings/reset/ast2500-reset.h | 49 + .../include/dt-bindings/reset/ast2600-reset.h | 70 + roms/u-boot/include/dt-bindings/reset/axg-aoclkc.h | 20 + .../include/dt-bindings/reset/bcm3380-reset.h | 15 + .../include/dt-bindings/reset/bcm6318-reset.h | 25 + .../include/dt-bindings/reset/bcm63268-reset.h | 31 + .../include/dt-bindings/reset/bcm6328-reset.h | 23 + .../include/dt-bindings/reset/bcm6338-reset.h | 21 + .../include/dt-bindings/reset/bcm6348-reset.h | 21 + .../include/dt-bindings/reset/bcm6358-reset.h | 20 + .../include/dt-bindings/reset/bcm6362-reset.h | 27 + .../include/dt-bindings/reset/bcm6368-reset.h | 21 + .../u-boot/include/dt-bindings/reset/g12a-aoclkc.h | 18 + .../u-boot/include/dt-bindings/reset/gxbb-aoclkc.h | 66 + roms/u-boot/include/dt-bindings/reset/imx7-reset.h | 52 + .../include/dt-bindings/reset/imx8mq-reset.h | 64 + .../u-boot/include/dt-bindings/reset/k210-sysctl.h | 38 + .../include/dt-bindings/reset/mt7620-reset.h | 35 + .../include/dt-bindings/reset/mt7623-reset.h | 25 + .../include/dt-bindings/reset/mt7628-reset.h | 36 + .../include/dt-bindings/reset/mt7629-reset.h | 39 + .../include/dt-bindings/reset/qcom,ipq4019-reset.h | 92 + .../dt-bindings/reset/raspberrypi,firmware-reset.h | 13 + .../include/dt-bindings/reset/sifive-fu540-prci.h | 19 + .../include/dt-bindings/reset/sifive-fu740-prci.h | 19 + .../include/dt-bindings/reset/snps,hsdk-reset.h | 17 + .../include/dt-bindings/reset/stih407-resets.h | 65 + .../include/dt-bindings/reset/stm32mp1-resets.h | 109 + .../include/dt-bindings/reset/sun4i-a10-ccu.h | 69 + .../include/dt-bindings/reset/sun50i-a64-ccu.h | 98 + .../include/dt-bindings/reset/sun50i-h6-ccu.h | 73 + .../include/dt-bindings/reset/sun50i-h6-r-ccu.h | 18 + .../include/dt-bindings/reset/sun50i-h616-ccu.h | 70 + roms/u-boot/include/dt-bindings/reset/sun5i-ccu.h | 32 + .../include/dt-bindings/reset/sun6i-a31-ccu.h | 106 + .../include/dt-bindings/reset/sun8i-a23-a33-ccu.h | 87 + .../include/dt-bindings/reset/sun8i-a83t-ccu.h | 98 + roms/u-boot/include/dt-bindings/reset/sun8i-de2.h | 15 + .../include/dt-bindings/reset/sun8i-h3-ccu.h | 106 + .../u-boot/include/dt-bindings/reset/sun8i-r-ccu.h | 53 + .../include/dt-bindings/reset/sun8i-r40-ccu.h | 130 + .../include/dt-bindings/reset/sun8i-v3s-ccu.h | 78 + .../include/dt-bindings/reset/sun9i-a80-ccu.h | 102 + .../include/dt-bindings/reset/sun9i-a80-de.h | 58 + .../include/dt-bindings/reset/sun9i-a80-usb.h | 56 + .../include/dt-bindings/reset/tegra124-car.h | 12 + .../include/dt-bindings/reset/tegra186-reset.h | 205 + roms/u-boot/include/dt-bindings/reset/ti-syscon.h | 38 + .../include/dt-bindings/reset/xlnx-zynqmp-resets.h | 130 + roms/u-boot/include/dt-bindings/soc/bcm2835-pm.h | 28 + roms/u-boot/include/dt-bindings/soc/imx8_pd.h | 188 + roms/u-boot/include/dt-bindings/soc/imx_rsrc.h | 558 +++ .../include/dt-bindings/soc/rockchip,boot-mode.h | 16 + .../include/dt-bindings/soc/ti,sci_pm_domain.h | 9 + roms/u-boot/include/dt-bindings/sound/azalia.h | 44 + .../include/dt-bindings/sound/fsl-imx-audmux.h | 64 + roms/u-boot/include/dt-bindings/sound/meson-aiu.h | 18 + .../dt-bindings/sound/meson-g12a-toacodec.h | 10 + .../dt-bindings/sound/meson-g12a-tohdmitx.h | 13 + roms/u-boot/include/dt-bindings/sound/nhlt.h | 24 + .../dt-bindings/sound/tlv320aic31xx-micbias.h | 8 + .../dt-bindings/thermal/tegra124-soctherm.h | 14 + roms/u-boot/include/dt-bindings/thermal/thermal.h | 16 + roms/u-boot/include/dt-bindings/usb/pd.h | 88 + roms/u-boot/include/dt-bindings/video/rk3288.h | 11 + roms/u-boot/include/dt-structs.h | 32 + roms/u-boot/include/dt_table.h | 49 + roms/u-boot/include/dw_hdmi.h | 560 +++ roms/u-boot/include/dwc3-omap-uboot.h | 31 + roms/u-boot/include/dwc3-sti-glue.h | 41 + roms/u-boot/include/dwc3-uboot.h | 65 + roms/u-boot/include/dwc_ahsata.h | 15 + roms/u-boot/include/dwmmc.h | 311 ++ roms/u-boot/include/e500.h | 47 + roms/u-boot/include/ec_commands.h | 4642 ++++++++++++++++++++ roms/u-boot/include/edid.h | 345 ++ roms/u-boot/include/eeprom.h | 28 + roms/u-boot/include/eeprom_field.h | 38 + roms/u-boot/include/eeprom_layout.h | 32 + roms/u-boot/include/efi.h | 493 +++ roms/u-boot/include/efi_api.h | 1995 +++++++++ roms/u-boot/include/efi_driver.h | 39 + roms/u-boot/include/efi_dt_fixup.h | 39 + roms/u-boot/include/efi_load_initrd.h | 25 + roms/u-boot/include/efi_loader.h | 976 ++++ roms/u-boot/include/efi_rng.h | 32 + roms/u-boot/include/efi_selftest.h | 174 + roms/u-boot/include/efi_tcg2.h | 170 + roms/u-boot/include/efi_variable.h | 320 ++ roms/u-boot/include/elf.h | 701 +++ roms/u-boot/include/env.h | 393 ++ roms/u-boot/include/env_attr.h | 38 + roms/u-boot/include/env_callback.h | 83 + roms/u-boot/include/env_default.h | 123 + roms/u-boot/include/env_flags.h | 182 + roms/u-boot/include/env_internal.h | 251 ++ roms/u-boot/include/environment/distro/sf.h | 41 + roms/u-boot/include/environment/ti/boot.h | 243 + roms/u-boot/include/environment/ti/dfu.h | 81 + roms/u-boot/include/environment/ti/k3_dfu.h | 46 + roms/u-boot/include/environment/ti/k3_rproc.h | 52 + roms/u-boot/include/environment/ti/mmc.h | 73 + roms/u-boot/include/environment/ti/nand.h | 26 + roms/u-boot/include/environment/ti/spi.h | 14 + roms/u-boot/include/environment/ti/ufs.h | 33 + roms/u-boot/include/errno.h | 38 + roms/u-boot/include/eth_phy.h | 18 + roms/u-boot/include/ethsw.h | 100 + roms/u-boot/include/exception.h | 60 + roms/u-boot/include/exports.h | 81 + roms/u-boot/include/ext4fs.h | 169 + roms/u-boot/include/ext_common.h | 224 + roms/u-boot/include/extension_board.h | 31 + roms/u-boot/include/exynos_lcd.h | 81 + roms/u-boot/include/faraday/ftahbc020s.h | 46 + roms/u-boot/include/faraday/ftpci100.h | 84 + roms/u-boot/include/faraday/ftpmu010.h | 234 + roms/u-boot/include/faraday/ftsdc010.h | 246 ++ roms/u-boot/include/faraday/ftsdmc020.h | 90 + roms/u-boot/include/faraday/ftsdmc021.h | 139 + roms/u-boot/include/faraday/ftsmc020.h | 73 + roms/u-boot/include/faraday/fttmr010.h | 60 + roms/u-boot/include/faraday/ftwdt010_wdt.h | 93 + roms/u-boot/include/fastboot-internal.h | 36 + roms/u-boot/include/fastboot.h | 179 + roms/u-boot/include/fat.h | 232 + roms/u-boot/include/fb_mmc.h | 42 + roms/u-boot/include/fb_nand.h | 40 + roms/u-boot/include/fdt.h | 1 + roms/u-boot/include/fdt_region.h | 304 ++ roms/u-boot/include/fdt_simplefb.h | 13 + roms/u-boot/include/fdt_support.h | 391 ++ roms/u-boot/include/fdtdec.h | 1219 +++++ roms/u-boot/include/fis.h | 141 + roms/u-boot/include/flash.h | 517 +++ roms/u-boot/include/fm_eth.h | 219 + roms/u-boot/include/fpga.h | 79 + roms/u-boot/include/fs.h | 274 ++ roms/u-boot/include/fs_internal.h | 16 + roms/u-boot/include/fs_loader.h | 55 + roms/u-boot/include/fsl-mc/fsl_dpaa_fd.h | 120 + roms/u-boot/include/fsl-mc/fsl_dpbp.h | 229 + roms/u-boot/include/fsl-mc/fsl_dpio.h | 243 + roms/u-boot/include/fsl-mc/fsl_dpmac.h | 476 ++ roms/u-boot/include/fsl-mc/fsl_dpmng.h | 46 + roms/u-boot/include/fsl-mc/fsl_dpni.h | 1326 ++++++ roms/u-boot/include/fsl-mc/fsl_dprc.h | 957 ++++ roms/u-boot/include/fsl-mc/fsl_dpsparser.h | 208 + roms/u-boot/include/fsl-mc/fsl_mc.h | 68 + roms/u-boot/include/fsl-mc/fsl_mc_cmd.h | 182 + roms/u-boot/include/fsl-mc/fsl_mc_private.h | 86 + roms/u-boot/include/fsl-mc/fsl_mc_sys.h | 25 + roms/u-boot/include/fsl-mc/fsl_qbman_base.h | 86 + roms/u-boot/include/fsl-mc/fsl_qbman_portal.h | 174 + roms/u-boot/include/fsl-mc/ldpaa_wriop.h | 73 + roms/u-boot/include/fsl_csu.h | 35 + roms/u-boot/include/fsl_dcu_fb.h | 22 + roms/u-boot/include/fsl_ddr.h | 143 + roms/u-boot/include/fsl_ddr_dimm_params.h | 120 + roms/u-boot/include/fsl_ddr_sdram.h | 490 +++ roms/u-boot/include/fsl_ddrc_version.h | 17 + roms/u-boot/include/fsl_devdis.h | 17 + roms/u-boot/include/fsl_diu_fb.h | 14 + roms/u-boot/include/fsl_dspi.h | 150 + roms/u-boot/include/fsl_dtsec.h | 230 + roms/u-boot/include/fsl_errata.h | 91 + roms/u-boot/include/fsl_esdhc.h | 259 ++ roms/u-boot/include/fsl_esdhc_imx.h | 272 ++ roms/u-boot/include/fsl_fman.h | 463 ++ roms/u-boot/include/fsl_ifc.h | 1061 +++++ roms/u-boot/include/fsl_immap.h | 186 + roms/u-boot/include/fsl_lpuart.h | 72 + roms/u-boot/include/fsl_mdio.h | 68 + roms/u-boot/include/fsl_memac.h | 264 ++ roms/u-boot/include/fsl_mmdc.h | 171 + roms/u-boot/include/fsl_pmic.h | 160 + roms/u-boot/include/fsl_qbman.h | 74 + roms/u-boot/include/fsl_qe.h | 304 ++ roms/u-boot/include/fsl_sec.h | 384 ++ roms/u-boot/include/fsl_sec_mon.h | 62 + roms/u-boot/include/fsl_secboot_err.h | 130 + roms/u-boot/include/fsl_sfp.h | 92 + roms/u-boot/include/fsl_tgec.h | 201 + roms/u-boot/include/fsl_usb.h | 100 + roms/u-boot/include/fsl_validate.h | 283 ++ roms/u-boot/include/fsl_wdog.h | 19 + roms/u-boot/include/fuse.h | 27 + roms/u-boot/include/g_dnl.h | 48 + roms/u-boot/include/gdsys_fpga.h | 91 + roms/u-boot/include/generic-phy.h | 423 ++ roms/u-boot/include/getopt.h | 130 + roms/u-boot/include/gt64120.h | 538 +++ roms/u-boot/include/gzip.h | 105 + roms/u-boot/include/handoff.h | 47 + roms/u-boot/include/hang.h | 22 + roms/u-boot/include/hash.h | 162 + roms/u-boot/include/hda_codec.h | 103 + roms/u-boot/include/hexdump.h | 91 + roms/u-boot/include/host_arch.h | 24 + roms/u-boot/include/hw_sha.h | 101 + roms/u-boot/include/hwconfig.h | 99 + roms/u-boot/include/hwspinlock.h | 140 + roms/u-boot/include/i2c.h | 989 +++++ roms/u-boot/include/i2c_eeprom.h | 56 + roms/u-boot/include/i2s.h | 126 + roms/u-boot/include/i8042.h | 75 + roms/u-boot/include/ide.h | 71 + roms/u-boot/include/image-android-dt.h | 20 + roms/u-boot/include/image-sparse.h | 42 + roms/u-boot/include/image.h | 1650 +++++++ roms/u-boot/include/imx8image.h | 272 ++ roms/u-boot/include/imx_lpi2c.h | 523 +++ roms/u-boot/include/imx_sip.h | 19 + roms/u-boot/include/imx_thermal.h | 22 + roms/u-boot/include/imximage.h | 220 + roms/u-boot/include/init.h | 341 ++ roms/u-boot/include/initcall.h | 57 + roms/u-boot/include/input.h | 202 + roms/u-boot/include/inttypes.h | 271 ++ roms/u-boot/include/iomux.h | 37 + roms/u-boot/include/ioports.h | 62 + roms/u-boot/include/iotrace.h | 156 + roms/u-boot/include/ipu_pixfmt.h | 67 + roms/u-boot/include/irq.h | 269 ++ roms/u-boot/include/irq_func.h | 26 + roms/u-boot/include/jffs2/compr_rubin.h | 11 + roms/u-boot/include/jffs2/jffs2.h | 234 + roms/u-boot/include/jffs2/jffs2_1pass.h | 3 + roms/u-boot/include/jffs2/load_kernel.h | 70 + roms/u-boot/include/jffs2/mini_inflate.h | 66 + roms/u-boot/include/k3-avs.h | 30 + roms/u-boot/include/kendryte/bypass.h | 31 + roms/u-boot/include/kendryte/clk.h | 35 + roms/u-boot/include/kendryte/pll.h | 58 + roms/u-boot/include/key_matrix.h | 85 + roms/u-boot/include/keyboard.h | 79 + roms/u-boot/include/keys/asymmetric-type.h | 88 + roms/u-boot/include/kgdb.h | 70 + roms/u-boot/include/lattice.h | 298 ++ roms/u-boot/include/lcd.h | 221 + roms/u-boot/include/lcd_console.h | 102 + roms/u-boot/include/lcdvideo.h | 69 + roms/u-boot/include/ld9040.h | 15 + roms/u-boot/include/led.h | 120 + roms/u-boot/include/libata.h | 654 +++ roms/u-boot/include/libtizen.h | 16 + roms/u-boot/include/linker_lists.h | 278 ++ roms/u-boot/include/linux/apm_bios.h | 211 + roms/u-boot/include/linux/arm-smccc.h | 125 + roms/u-boot/include/linux/asn1.h | 65 + roms/u-boot/include/linux/asn1_ber_bytecode.h | 89 + roms/u-boot/include/linux/asn1_decoder.h | 20 + roms/u-boot/include/linux/bch.h | 67 + roms/u-boot/include/linux/bitfield.h | 159 + roms/u-boot/include/linux/bitmap.h | 217 + roms/u-boot/include/linux/bitops.h | 225 + roms/u-boot/include/linux/bitrev.h | 105 + roms/u-boot/include/linux/bug.h | 52 + roms/u-boot/include/linux/build_bug.h | 84 + roms/u-boot/include/linux/byteorder/big_endian.h | 110 + roms/u-boot/include/linux/byteorder/generic.h | 207 + .../u-boot/include/linux/byteorder/little_endian.h | 110 + roms/u-boot/include/linux/byteorder/swab.h | 156 + roms/u-boot/include/linux/clk-provider.h | 254 ++ .../include/linux/clk/analogbits-wrpll-cln28hpc.h | 79 + roms/u-boot/include/linux/clk/at91_pmc.h | 247 ++ roms/u-boot/include/linux/compat.h | 389 ++ roms/u-boot/include/linux/compiler-clang.h | 44 + roms/u-boot/include/linux/compiler-gcc.h | 174 + roms/u-boot/include/linux/compiler-intel.h | 34 + roms/u-boot/include/linux/compiler.h | 355 ++ roms/u-boot/include/linux/compiler_attributes.h | 273 ++ roms/u-boot/include/linux/compiler_types.h | 246 ++ roms/u-boot/include/linux/completion.h | 173 + roms/u-boot/include/linux/const.h | 34 + roms/u-boot/include/linux/crc32.h | 27 + roms/u-boot/include/linux/crc7.h | 14 + roms/u-boot/include/linux/ctype.h | 60 + roms/u-boot/include/linux/delay.h | 21 + roms/u-boot/include/linux/dma-direction.h | 13 + roms/u-boot/include/linux/dma-mapping.h | 64 + roms/u-boot/include/linux/drm_dp_helper.h | 406 ++ roms/u-boot/include/linux/edd.h | 185 + roms/u-boot/include/linux/err.h | 59 + roms/u-boot/include/linux/errno.h | 168 + roms/u-boot/include/linux/ethtool.h | 725 +++ roms/u-boot/include/linux/fb.h | 619 +++ roms/u-boot/include/linux/if_ether.h | 178 + roms/u-boot/include/linux/immap_qe.h | 593 +++ roms/u-boot/include/linux/input.h | 152 + roms/u-boot/include/linux/intel-smc.h | 539 +++ roms/u-boot/include/linux/io.h | 72 + roms/u-boot/include/linux/ioctl.h | 6 + roms/u-boot/include/linux/iopoll.h | 79 + roms/u-boot/include/linux/ioport.h | 192 + roms/u-boot/include/linux/kbuild.h | 20 + roms/u-boot/include/linux/kconfig.h | 110 + roms/u-boot/include/linux/kernel.h | 287 ++ roms/u-boot/include/linux/libfdt.h | 13 + roms/u-boot/include/linux/libfdt_env.h | 33 + roms/u-boot/include/linux/linkage.h | 74 + roms/u-boot/include/linux/linux_string.h | 8 + roms/u-boot/include/linux/list.h | 699 +++ roms/u-boot/include/linux/list_sort.h | 11 + roms/u-boot/include/linux/log2.h | 215 + roms/u-boot/include/linux/lzo.h | 51 + roms/u-boot/include/linux/math64.h | 257 ++ roms/u-boot/include/linux/mbus.h | 73 + roms/u-boot/include/linux/mc146818rtc.h | 86 + roms/u-boot/include/linux/mdio.h | 310 ++ roms/u-boot/include/linux/mii.h | 230 + roms/u-boot/include/linux/mtd/bbm.h | 161 + roms/u-boot/include/linux/mtd/cfi.h | 32 + roms/u-boot/include/linux/mtd/concat.h | 23 + roms/u-boot/include/linux/mtd/doc2000.h | 207 + roms/u-boot/include/linux/mtd/flashchip.h | 103 + roms/u-boot/include/linux/mtd/fsl_upm.h | 44 + roms/u-boot/include/linux/mtd/fsmc_nand.h | 84 + roms/u-boot/include/linux/mtd/mtd.h | 601 +++ roms/u-boot/include/linux/mtd/nand.h | 748 ++++ roms/u-boot/include/linux/mtd/nand_bch.h | 68 + roms/u-boot/include/linux/mtd/nand_ecc.h | 27 + roms/u-boot/include/linux/mtd/ndfc.h | 67 + roms/u-boot/include/linux/mtd/omap_elm.h | 79 + roms/u-boot/include/linux/mtd/omap_gpmc.h | 97 + roms/u-boot/include/linux/mtd/onenand.h | 180 + roms/u-boot/include/linux/mtd/onenand_regs.h | 208 + roms/u-boot/include/linux/mtd/partitions.h | 110 + roms/u-boot/include/linux/mtd/rawnand.h | 1333 ++++++ roms/u-boot/include/linux/mtd/samsung_onenand.h | 116 + roms/u-boot/include/linux/mtd/spi-nor.h | 444 ++ roms/u-boot/include/linux/mtd/spinand.h | 450 ++ roms/u-boot/include/linux/mtd/st_smi.h | 100 + roms/u-boot/include/linux/mtd/ubi.h | 289 ++ roms/u-boot/include/linux/netdevice.h | 61 + roms/u-boot/include/linux/oid_registry.h | 117 + roms/u-boot/include/linux/poison.h | 11 + roms/u-boot/include/linux/posix_types.h | 48 + roms/u-boot/include/linux/printk.h | 87 + roms/u-boot/include/linux/psci.h | 132 + roms/u-boot/include/linux/rbtree.h | 97 + roms/u-boot/include/linux/rbtree_augmented.h | 219 + roms/u-boot/include/linux/screen_info.h | 84 + roms/u-boot/include/linux/serial_reg.h | 387 ++ roms/u-boot/include/linux/sizes.h | 51 + roms/u-boot/include/linux/soc/ti/cppi5.h | 996 +++++ .../u-boot/include/linux/soc/ti/k3-navss-ringacc.h | 251 ++ roms/u-boot/include/linux/soc/ti/k3-sec-proxy.h | 25 + roms/u-boot/include/linux/soc/ti/ti-udma.h | 43 + roms/u-boot/include/linux/soc/ti/ti_sci_protocol.h | 702 +++ roms/u-boot/include/linux/stat.h | 158 + roms/u-boot/include/linux/stddef.h | 20 + roms/u-boot/include/linux/string.h | 139 + roms/u-boot/include/linux/stringify.h | 12 + roms/u-boot/include/linux/time.h | 164 + roms/u-boot/include/linux/typecheck.h | 24 + roms/u-boot/include/linux/types.h | 170 + roms/u-boot/include/linux/unaligned/access_ok.h | 66 + roms/u-boot/include/linux/unaligned/be_byteshift.h | 70 + roms/u-boot/include/linux/unaligned/generic.h | 68 + roms/u-boot/include/linux/unaligned/le_byteshift.h | 70 + roms/u-boot/include/linux/usb/at91_udc.h | 19 + roms/u-boot/include/linux/usb/atmel_usba_udc.h | 25 + roms/u-boot/include/linux/usb/cdc.h | 224 + roms/u-boot/include/linux/usb/ch9.h | 1063 +++++ roms/u-boot/include/linux/usb/composite.h | 417 ++ roms/u-boot/include/linux/usb/dwc3-omap.h | 18 + roms/u-boot/include/linux/usb/dwc3.h | 223 + roms/u-boot/include/linux/usb/gadget.h | 990 +++++ roms/u-boot/include/linux/usb/musb.h | 156 + roms/u-boot/include/linux/usb/otg.h | 39 + roms/u-boot/include/linux/usb/phy.h | 37 + roms/u-boot/include/linux/usb/xhci-fsl.h | 73 + roms/u-boot/include/linux/usb/xhci-omap.h | 145 + roms/u-boot/include/linux/utf.h | 75 + roms/u-boot/include/linux/xxhash.h | 229 + roms/u-boot/include/linux/zstd.h | 1147 +++++ roms/u-boot/include/linux_logo.h | 1445 ++++++ roms/u-boot/include/lmb.h | 97 + roms/u-boot/include/log.h | 666 +++ roms/u-boot/include/lxt971a.h | 131 + roms/u-boot/include/lynxkdi.h | 24 + roms/u-boot/include/lz4.h | 24 + roms/u-boot/include/lzma/LzmaDec.h | 15 + roms/u-boot/include/lzma/LzmaTools.h | 14 + roms/u-boot/include/lzma/LzmaTypes.h | 19 + roms/u-boot/include/mailbox-uclass.h | 82 + roms/u-boot/include/mailbox.h | 147 + roms/u-boot/include/malloc.h | 990 +++++ roms/u-boot/include/mapmem.h | 31 + roms/u-boot/include/mc13783.h | 63 + roms/u-boot/include/mc13892.h | 206 + roms/u-boot/include/mc34704.h | 45 + roms/u-boot/include/mc9sdz60.h | 66 + roms/u-boot/include/media_bus_format.h | 156 + roms/u-boot/include/memalign.h | 115 + roms/u-boot/include/membuff.h | 245 ++ roms/u-boot/include/menu.h | 38 + roms/u-boot/include/micrel.h | 50 + roms/u-boot/include/mii_phy.h | 8 + roms/u-boot/include/miiphy.h | 210 + roms/u-boot/include/mipi_display.h | 138 + roms/u-boot/include/mipi_dsi.h | 490 +++ roms/u-boot/include/misc.h | 146 + roms/u-boot/include/mk48t59.h | 47 + roms/u-boot/include/mm_communication.h | 251 ++ roms/u-boot/include/mmc.h | 990 +++++ roms/u-boot/include/mpc106.h | 140 + roms/u-boot/include/mpc83xx.h | 1585 +++++++ roms/u-boot/include/mpc85xx.h | 67 + roms/u-boot/include/mpc86xx.h | 90 + roms/u-boot/include/mpc8xx.h | 603 +++ roms/u-boot/include/mpc8xx_irq.h | 59 + roms/u-boot/include/msc01.h | 134 + roms/u-boot/include/mtd.h | 16 + roms/u-boot/include/mtd/cfi_flash.h | 183 + roms/u-boot/include/mtd/mtd-abi.h | 274 ++ roms/u-boot/include/mtd/ubi-user.h | 446 ++ roms/u-boot/include/mtd_node.h | 11 + roms/u-boot/include/mux-internal.h | 109 + roms/u-boot/include/mux.h | 159 + roms/u-boot/include/mv88e6352.h | 75 + roms/u-boot/include/mvebu/comphy.h | 22 + roms/u-boot/include/mvebu_mmc.h | 267 ++ roms/u-boot/include/mvmfp.h | 99 + roms/u-boot/include/mxs_nand.h | 103 + roms/u-boot/include/nand.h | 156 + roms/u-boot/include/net.h | 942 ++++ roms/u-boot/include/net/dsa.h | 165 + roms/u-boot/include/net/fastboot.h | 21 + roms/u-boot/include/net/ncsi-pkt.h | 442 ++ roms/u-boot/include/net/ncsi.h | 14 + roms/u-boot/include/net/pcap.h | 55 + roms/u-boot/include/net/pfe_eth/pfe/cbus.h | 76 + roms/u-boot/include/net/pfe_eth/pfe/cbus/bmu.h | 39 + .../include/net/pfe_eth/pfe/cbus/class_csr.h | 180 + roms/u-boot/include/net/pfe_eth/pfe/cbus/emac.h | 140 + roms/u-boot/include/net/pfe_eth/pfe/cbus/gpi.h | 61 + roms/u-boot/include/net/pfe_eth/pfe/cbus/hif.h | 68 + .../include/net/pfe_eth/pfe/cbus/hif_nocpy.h | 39 + roms/u-boot/include/net/pfe_eth/pfe/cbus/tmu_csr.h | 148 + .../u-boot/include/net/pfe_eth/pfe/cbus/util_csr.h | 46 + roms/u-boot/include/net/pfe_eth/pfe/pfe_hw.h | 169 + roms/u-boot/include/net/pfe_eth/pfe_driver.h | 58 + roms/u-boot/include/net/pfe_eth/pfe_eth.h | 104 + roms/u-boot/include/net/pfe_eth/pfe_firmware.h | 16 + roms/u-boot/include/net/pfe_eth/pfe_mdio.h | 12 + roms/u-boot/include/net/sntp.h | 58 + roms/u-boot/include/net/tftp.h | 30 + roms/u-boot/include/net/udp.h | 41 + roms/u-boot/include/netdev.h | 135 + roms/u-boot/include/ns16550.h | 271 ++ roms/u-boot/include/nuvoton_nct6102d.h | 33 + roms/u-boot/include/nvme.h | 93 + roms/u-boot/include/of_live.h | 23 + roms/u-boot/include/omap3_spi.h | 78 + roms/u-boot/include/onenand_uboot.h | 55 + roms/u-boot/include/opensbi.h | 56 + roms/u-boot/include/os.h | 459 ++ roms/u-boot/include/p2sb.h | 175 + roms/u-boot/include/palmas.h | 147 + roms/u-boot/include/panel.h | 68 + roms/u-boot/include/part.h | 528 +++ roms/u-boot/include/part_efi.h | 127 + roms/u-boot/include/pca953x.h | 26 + roms/u-boot/include/pca9564.h | 35 + roms/u-boot/include/pca9698.h | 17 + roms/u-boot/include/pch.h | 161 + roms/u-boot/include/pci.h | 1776 ++++++++ roms/u-boot/include/pci_ep.h | 414 ++ roms/u-boot/include/pci_gt64120.h | 16 + roms/u-boot/include/pci_ids.h | 3154 +++++++++++++ roms/u-boot/include/pci_msc01.h | 16 + roms/u-boot/include/pci_rom.h | 67 + roms/u-boot/include/pci_tegra.h | 10 + roms/u-boot/include/pe.h | 273 ++ roms/u-boot/include/phy-mipi-dphy.h | 284 ++ roms/u-boot/include/phy-sun4i-usb.h | 34 + roms/u-boot/include/phy.h | 578 +++ roms/u-boot/include/phy_interface.h | 108 + roms/u-boot/include/phys2bus.h | 41 + roms/u-boot/include/physmem.h | 21 + roms/u-boot/include/post.h | 175 + roms/u-boot/include/power-domain-uclass.h | 81 + roms/u-boot/include/power-domain.h | 192 + roms/u-boot/include/power/acpi_pmc.h | 199 + roms/u-boot/include/power/act8846_pmic.h | 36 + roms/u-boot/include/power/as3722.h | 32 + roms/u-boot/include/power/battery.h | 21 + roms/u-boot/include/power/bd71837.h | 103 + roms/u-boot/include/power/da9063_pmic.h | 320 ++ roms/u-boot/include/power/fan53555.h | 14 + roms/u-boot/include/power/fg_battery_cell_params.h | 73 + roms/u-boot/include/power/hi6553_pmic.h | 78 + roms/u-boot/include/power/lp873x.h | 19 + roms/u-boot/include/power/lp87565.h | 12 + roms/u-boot/include/power/ltc3676_pmic.h | 50 + roms/u-boot/include/power/max17042_fg.h | 57 + roms/u-boot/include/power/max77686_pmic.h | 227 + roms/u-boot/include/power/max77693_fg.h | 48 + roms/u-boot/include/power/max77693_muic.h | 73 + roms/u-boot/include/power/max77693_pmic.h | 40 + roms/u-boot/include/power/max8997_muic.h | 44 + roms/u-boot/include/power/max8997_pmic.h | 196 + roms/u-boot/include/power/max8998_pmic.h | 71 + roms/u-boot/include/power/mc34vr500_pmic.h | 174 + roms/u-boot/include/power/mp5416.h | 41 + roms/u-boot/include/power/palmas.h | 26 + roms/u-boot/include/power/pca9450.h | 59 + roms/u-boot/include/power/pfuze100_pmic.h | 258 ++ roms/u-boot/include/power/pfuze3000_pmic.h | 82 + roms/u-boot/include/power/pmic.h | 330 ++ roms/u-boot/include/power/power_chrg.h | 26 + roms/u-boot/include/power/regulator.h | 667 +++ roms/u-boot/include/power/rk8xx_pmic.h | 236 + roms/u-boot/include/power/rn5t567_pmic.h | 112 + roms/u-boot/include/power/s2mps11.h | 164 + roms/u-boot/include/power/s5m8767.h | 84 + roms/u-boot/include/power/sandbox_pmic.h | 144 + roms/u-boot/include/power/stpmic1.h | 113 + roms/u-boot/include/power/tps62362.h | 28 + roms/u-boot/include/power/tps65090.h | 55 + roms/u-boot/include/power/tps65217.h | 89 + roms/u-boot/include/power/tps65218.h | 82 + roms/u-boot/include/power/tps65910.h | 78 + roms/u-boot/include/power/tps65910_pmic.h | 129 + roms/u-boot/include/power/tps65941.h | 26 + roms/u-boot/include/ppc_asm.tmpl | 286 ++ roms/u-boot/include/ppc_defs.h | 74 + roms/u-boot/include/pvblock.h | 17 + roms/u-boot/include/pwm.h | 99 + roms/u-boot/include/pwrseq.h | 17 + roms/u-boot/include/pxa_lcd.h | 80 + roms/u-boot/include/qfw.h | 319 ++ roms/u-boot/include/radeon.h | 1988 +++++++++ roms/u-boot/include/ram.h | 39 + roms/u-boot/include/rand.h | 40 + roms/u-boot/include/rc4.h | 20 + roms/u-boot/include/regmap.h | 532 +++ roms/u-boot/include/reiserfs.h | 72 + roms/u-boot/include/relocate.h | 38 + roms/u-boot/include/remoteproc.h | 366 ++ roms/u-boot/include/reset-uclass.h | 89 + roms/u-boot/include/reset.h | 472 ++ roms/u-boot/include/rng.h | 43 + roms/u-boot/include/rtc.h | 324 ++ roms/u-boot/include/rtc_def.h | 35 + roms/u-boot/include/s_record.h | 97 + roms/u-boot/include/samsung-usb-phy-uboot.h | 15 + roms/u-boot/include/samsung/exynos5-dt-types.h | 31 + roms/u-boot/include/samsung/misc.h | 39 + roms/u-boot/include/sandbox-adc.h | 30 + roms/u-boot/include/sandbox-clk.h | 88 + roms/u-boot/include/sandboxblockdev.h | 26 + roms/u-boot/include/sandboxfs.h | 40 + roms/u-boot/include/sandboxtee.h | 30 + roms/u-boot/include/sata.h | 24 + roms/u-boot/include/scf0403_lcd.h | 10 + roms/u-boot/include/scmi_agent-uclass.h | 24 + roms/u-boot/include/scmi_agent.h | 68 + roms/u-boot/include/scmi_protocols.h | 292 ++ roms/u-boot/include/scp03.h | 21 + roms/u-boot/include/scsi.h | 252 ++ roms/u-boot/include/sdhci.h | 512 +++ roms/u-boot/include/sdp.h | 22 + roms/u-boot/include/search.h | 127 + roms/u-boot/include/serial.h | 349 ++ roms/u-boot/include/sh_pfc.h | 195 + roms/u-boot/include/signatures.h | 62 + roms/u-boot/include/sja1000.h | 43 + roms/u-boot/include/slre.h | 100 + roms/u-boot/include/smbios.h | 292 ++ roms/u-boot/include/smem.h | 91 + roms/u-boot/include/smsc_lpc47m.h | 40 + roms/u-boot/include/smsc_sio1007.h | 114 + roms/u-boot/include/soc.h | 147 + roms/u-boot/include/sort.h | 34 + roms/u-boot/include/sound.h | 153 + roms/u-boot/include/sparse_defs.h | 6 + roms/u-boot/include/sparse_format.h | 48 + roms/u-boot/include/spartan2.h | 111 + roms/u-boot/include/spartan3.h | 134 + roms/u-boot/include/spd.h | 93 + roms/u-boot/include/spd_sdram.h | 6 + roms/u-boot/include/spi-mem.h | 260 ++ roms/u-boot/include/spi.h | 728 +++ roms/u-boot/include/spi_flash.h | 211 + roms/u-boot/include/spl.h | 730 +++ roms/u-boot/include/spl_gpio.h | 62 + roms/u-boot/include/splash.h | 80 + roms/u-boot/include/spmi/spmi.h | 46 + roms/u-boot/include/squashfs.h | 26 + roms/u-boot/include/st_logo_data.h | 3266 ++++++++++++++ roms/u-boot/include/status_led.h | 102 + roms/u-boot/include/stdint.h | 7 + roms/u-boot/include/stdio.h | 59 + roms/u-boot/include/stdio_dev.h | 110 + roms/u-boot/include/stdlib.h | 11 + roms/u-boot/include/stm32_rcc.h | 97 + roms/u-boot/include/stratixII.h | 13 + roms/u-boot/include/string.h | 1 + roms/u-boot/include/sunxi_image.h | 82 + roms/u-boot/include/sy8106a.h | 10 + roms/u-boot/include/sym53c8xx.h | 552 +++ roms/u-boot/include/synopsys/dwcddr21mctl.h | 324 ++ roms/u-boot/include/syscon.h | 105 + roms/u-boot/include/sysinfo.h | 242 + roms/u-boot/include/sysreset.h | 121 + roms/u-boot/include/tables_csum.h | 21 + roms/u-boot/include/tca642x.h | 69 + roms/u-boot/include/tee.h | 380 ++ roms/u-boot/include/tee/optee.h | 82 + roms/u-boot/include/tee/optee_ta_avb.h | 64 + roms/u-boot/include/tee/optee_ta_rpc_test.h | 30 + roms/u-boot/include/tee/optee_ta_scp03.h | 21 + roms/u-boot/include/tegra-kbc.h | 33 + roms/u-boot/include/test/compression.h | 16 + roms/u-boot/include/test/env.h | 15 + roms/u-boot/include/test/export.h | 16 + roms/u-boot/include/test/lib.h | 14 + roms/u-boot/include/test/log.h | 19 + roms/u-boot/include/test/optee.h | 14 + roms/u-boot/include/test/overlay.h | 15 + roms/u-boot/include/test/suites.h | 51 + roms/u-boot/include/test/test.h | 136 + roms/u-boot/include/test/ut.h | 387 ++ roms/u-boot/include/thermal.h | 33 + roms/u-boot/include/thor.h | 20 + roms/u-boot/include/ti-usb-phy-uboot.h | 21 + roms/u-boot/include/time.h | 129 + roms/u-boot/include/timer.h | 110 + roms/u-boot/include/timestamp.h | 13 + roms/u-boot/include/tlv_eeprom.h | 152 + roms/u-boot/include/tmu.h | 46 + roms/u-boot/include/tpm-common.h | 306 ++ roms/u-boot/include/tpm-v1.h | 594 +++ roms/u-boot/include/tpm-v2.h | 626 +++ roms/u-boot/include/tpm_api.h | 322 ++ roms/u-boot/include/tps6586x.h | 53 + roms/u-boot/include/trace.h | 104 + roms/u-boot/include/tsec.h | 438 ++ roms/u-boot/include/tsi148.h | 201 + roms/u-boot/include/twl4030.h | 708 +++ roms/u-boot/include/twl6030.h | 225 + roms/u-boot/include/u-boot/aes.h | 46 + roms/u-boot/include/u-boot/crc.h | 123 + roms/u-boot/include/u-boot/ecdsa.h | 94 + roms/u-boot/include/u-boot/fdt-libcrypto.h | 27 + roms/u-boot/include/u-boot/hash-checksum.h | 29 + roms/u-boot/include/u-boot/md5.h | 34 + roms/u-boot/include/u-boot/rsa-mod-exp.h | 103 + roms/u-boot/include/u-boot/rsa.h | 171 + roms/u-boot/include/u-boot/sha1.h | 108 + roms/u-boot/include/u-boot/sha256.h | 25 + roms/u-boot/include/u-boot/sha512.h | 38 + roms/u-boot/include/u-boot/u-boot.lds.h | 25 + roms/u-boot/include/u-boot/variadic-macro.h | 58 + roms/u-boot/include/u-boot/zlib.h | 763 ++++ roms/u-boot/include/ubi_uboot.h | 81 + roms/u-boot/include/ubifs_uboot.h | 34 + roms/u-boot/include/ubispl.h | 95 + roms/u-boot/include/uboot_aes.h | 110 + roms/u-boot/include/ufs.h | 32 + roms/u-boot/include/universe.h | 131 + roms/u-boot/include/usb.h | 1103 +++++ roms/u-boot/include/usb/ci_udc.h | 13 + roms/u-boot/include/usb/designware_udc.h | 183 + roms/u-boot/include/usb/dwc2_udc.h | 39 + roms/u-boot/include/usb/ehci-ci.h | 285 ++ roms/u-boot/include/usb/fotg210.h | 362 ++ roms/u-boot/include/usb/fusbh200.h | 59 + roms/u-boot/include/usb/pxa27x_udc.h | 31 + roms/u-boot/include/usb/udc.h | 51 + roms/u-boot/include/usb/ulpi.h | 318 ++ roms/u-boot/include/usb/xhci.h | 1299 ++++++ roms/u-boot/include/usb_cdc_acm.h | 29 + roms/u-boot/include/usb_defs.h | 365 ++ roms/u-boot/include/usb_ether.h | 131 + roms/u-boot/include/usb_mass_storage.h | 32 + roms/u-boot/include/usbdescriptors.h | 534 +++ roms/u-boot/include/usbdevice.h | 762 ++++ roms/u-boot/include/usbroothubdes.h | 128 + roms/u-boot/include/uuid.h | 47 + roms/u-boot/include/vbe.h | 113 + roms/u-boot/include/versalpl.h | 20 + roms/u-boot/include/version.h | 22 + roms/u-boot/include/video.h | 344 ++ roms/u-boot/include/video_bridge.h | 111 + roms/u-boot/include/video_console.h | 308 ++ roms/u-boot/include/video_easylogo.h | 26 + roms/u-boot/include/video_fb.h | 91 + roms/u-boot/include/video_font.h | 16 + roms/u-boot/include/video_font_4x6.h | 2153 +++++++++ roms/u-boot/include/video_font_data.h | 4629 +++++++++++++++++++ roms/u-boot/include/video_osd.h | 192 + roms/u-boot/include/virtex2.h | 105 + roms/u-boot/include/virtio.h | 711 +++ roms/u-boot/include/virtio_ring.h | 320 ++ roms/u-boot/include/virtio_types.h | 24 + roms/u-boot/include/vsc7385.h | 12 + roms/u-boot/include/vsc9953.h | 723 +++ roms/u-boot/include/vsprintf.h | 245 ++ roms/u-boot/include/vxworks.h | 93 + roms/u-boot/include/w1-eeprom.h | 31 + roms/u-boot/include/w1.h | 55 + roms/u-boot/include/w83c553f.h | 161 + roms/u-boot/include/wait_bit.h | 87 + roms/u-boot/include/watchdog.h | 87 + roms/u-boot/include/wdt.h | 110 + roms/u-boot/include/winbond_w83627.h | 34 + roms/u-boot/include/xen.h | 24 + roms/u-boot/include/xen/arm/interface.h | 88 + roms/u-boot/include/xen/events.h | 42 + roms/u-boot/include/xen/gnttab.h | 23 + roms/u-boot/include/xen/hvm.h | 27 + roms/u-boot/include/xen/interface/event_channel.h | 279 ++ roms/u-boot/include/xen/interface/grant_table.h | 565 +++ roms/u-boot/include/xen/interface/hvm/hvm_op.h | 55 + roms/u-boot/include/xen/interface/hvm/params.h | 116 + roms/u-boot/include/xen/interface/io/blkif.h | 701 +++ roms/u-boot/include/xen/interface/io/console.h | 39 + roms/u-boot/include/xen/interface/io/protocols.h | 28 + roms/u-boot/include/xen/interface/io/ring.h | 462 ++ roms/u-boot/include/xen/interface/io/xenbus.h | 64 + roms/u-boot/include/xen/interface/io/xs_wire.h | 134 + roms/u-boot/include/xen/interface/memory.h | 332 ++ roms/u-boot/include/xen/interface/sched.h | 171 + roms/u-boot/include/xen/interface/xen.h | 208 + roms/u-boot/include/xen/xenbus.h | 116 + roms/u-boot/include/xilinx.h | 87 + roms/u-boot/include/xyzModem.h | 71 + roms/u-boot/include/zfs/dmu.h | 107 + roms/u-boot/include/zfs/dmu_objset.h | 30 + roms/u-boot/include/zfs/dnode.h | 68 + roms/u-boot/include/zfs/dsl_dataset.h | 40 + roms/u-boot/include/zfs/dsl_dir.h | 36 + roms/u-boot/include/zfs/sa_impl.h | 22 + roms/u-boot/include/zfs/spa.h | 279 ++ roms/u-boot/include/zfs/uberblock_impl.h | 44 + roms/u-boot/include/zfs/vdev_impl.h | 57 + roms/u-boot/include/zfs/zap_impl.h | 98 + roms/u-boot/include/zfs/zap_leaf.h | 90 + roms/u-boot/include/zfs/zfs.h | 109 + roms/u-boot/include/zfs/zfs_acl.h | 42 + roms/u-boot/include/zfs/zfs_znode.h | 58 + roms/u-boot/include/zfs/zil.h | 44 + roms/u-boot/include/zfs/zio.h | 79 + roms/u-boot/include/zfs/zio_checksum.h | 37 + roms/u-boot/include/zfs_common.h | 106 + roms/u-boot/include/zynq_bootimg.h | 33 + roms/u-boot/include/zynqmp_firmware.h | 111 + roms/u-boot/include/zynqmp_tap_delay.h | 20 + roms/u-boot/include/zynqmppl.h | 31 + roms/u-boot/include/zynqpl.h | 69 + 1904 files changed, 294203 insertions(+) create mode 100644 roms/u-boot/include/.gitignore create mode 100644 roms/u-boot/include/ACEX1K.h create mode 100644 roms/u-boot/include/MCD_dma.h create mode 100644 roms/u-boot/include/MCD_progCheck.h create mode 100644 roms/u-boot/include/MCD_tasksInit.h create mode 100644 roms/u-boot/include/SA-1100.h create mode 100644 roms/u-boot/include/_exports.h create mode 100644 roms/u-boot/include/acpi/acpi_device.h create mode 100644 roms/u-boot/include/acpi/acpi_dp.h create mode 100644 roms/u-boot/include/acpi/acpi_s3.h create mode 100644 roms/u-boot/include/acpi/acpi_table.h create mode 100644 roms/u-boot/include/acpi/acpigen.h create mode 100644 roms/u-boot/include/adc.h create mode 100644 roms/u-boot/include/addr_map.h create mode 100644 roms/u-boot/include/ahci.h create mode 100644 roms/u-boot/include/ali512x.h create mode 100644 roms/u-boot/include/altera.h create mode 100644 roms/u-boot/include/andestech/andes_pcu.h create mode 100644 roms/u-boot/include/android_ab.h create mode 100644 roms/u-boot/include/android_bootloader_message.h create mode 100644 roms/u-boot/include/android_image.h create mode 100644 roms/u-boot/include/ansi.h create mode 100644 roms/u-boot/include/api.h create mode 100644 roms/u-boot/include/api_public.h create mode 100644 roms/u-boot/include/armcoremodule.h create mode 100644 roms/u-boot/include/asm-generic/atomic-long.h create mode 100644 roms/u-boot/include/asm-generic/atomic.h create mode 100644 roms/u-boot/include/asm-generic/bitops/__ffs.h create mode 100644 roms/u-boot/include/asm-generic/bitops/__fls.h create mode 100644 roms/u-boot/include/asm-generic/bitops/fls.h create mode 100644 roms/u-boot/include/asm-generic/bitops/fls64.h create mode 100644 roms/u-boot/include/asm-generic/bitsperlong.h create mode 100644 roms/u-boot/include/asm-generic/global_data.h create mode 100644 roms/u-boot/include/asm-generic/gpio.h create mode 100644 roms/u-boot/include/asm-generic/int-ll64.h create mode 100644 roms/u-boot/include/asm-generic/io.h create mode 100644 roms/u-boot/include/asm-generic/ioctl.h create mode 100644 roms/u-boot/include/asm-generic/pe.h create mode 100644 roms/u-boot/include/asm-generic/sections.h create mode 100644 roms/u-boot/include/asm-generic/signal.h create mode 100644 roms/u-boot/include/asm-generic/types.h create mode 100644 roms/u-boot/include/asm-generic/u-boot.h create mode 100644 roms/u-boot/include/asm-generic/unaligned.h create mode 100644 roms/u-boot/include/asm-offsets.h create mode 100644 roms/u-boot/include/ata.h create mode 100644 roms/u-boot/include/atf_common.h create mode 100644 roms/u-boot/include/atmel_hlcdc.h create mode 100644 roms/u-boot/include/atmel_lcd.h create mode 100644 roms/u-boot/include/atmel_lcdc.h create mode 100644 roms/u-boot/include/atmel_mci.h create mode 100644 roms/u-boot/include/atsha204a-i2c.h create mode 100644 roms/u-boot/include/audio_codec.h create mode 100644 roms/u-boot/include/autoboot.h create mode 100644 roms/u-boot/include/avb_verify.h create mode 100644 roms/u-boot/include/axi.h create mode 100644 roms/u-boot/include/axp152.h create mode 100644 roms/u-boot/include/axp209.h create mode 100644 roms/u-boot/include/axp221.h create mode 100644 roms/u-boot/include/axp305.h create mode 100644 roms/u-boot/include/axp809.h create mode 100644 roms/u-boot/include/axp818.h create mode 100644 roms/u-boot/include/axp_pmic.h create mode 100644 roms/u-boot/include/backlight.h create mode 100644 roms/u-boot/include/bcb.h create mode 100644 roms/u-boot/include/bcd.h create mode 100644 roms/u-boot/include/bedbug/bedbug.h create mode 100644 roms/u-boot/include/bedbug/ppc.h create mode 100644 roms/u-boot/include/bedbug/regs.h create mode 100644 roms/u-boot/include/bedbug/tables.h create mode 100644 roms/u-boot/include/bedbug/type.h create mode 100644 roms/u-boot/include/binman.h create mode 100644 roms/u-boot/include/binman_sym.h create mode 100644 roms/u-boot/include/bios_emul.h create mode 100644 roms/u-boot/include/bitfield.h create mode 100644 roms/u-boot/include/blk.h create mode 100644 roms/u-boot/include/bloblist.h create mode 100644 roms/u-boot/include/bmp_layout.h create mode 100644 roms/u-boot/include/boot_fit.h create mode 100644 roms/u-boot/include/bootcount.h create mode 100644 roms/u-boot/include/bootm.h create mode 100644 roms/u-boot/include/bootretry.h create mode 100644 roms/u-boot/include/bootstage.h create mode 100644 roms/u-boot/include/bouncebuf.h create mode 100644 roms/u-boot/include/broadcom/chimp.h create mode 100644 roms/u-boot/include/btrfs.h create mode 100644 roms/u-boot/include/bus_vcxk.h create mode 100644 roms/u-boot/include/button.h create mode 100644 roms/u-boot/include/bzlib.h create mode 100644 roms/u-boot/include/cache.h create mode 100644 roms/u-boot/include/capitalization.h create mode 100644 roms/u-boot/include/cavium/atf.h create mode 100644 roms/u-boot/include/cavium/atf_part.h create mode 100644 roms/u-boot/include/cavium/thunderx_svc.h create mode 100644 roms/u-boot/include/cbfs.h create mode 100644 roms/u-boot/include/charset.h create mode 100644 roms/u-boot/include/circbuf.h create mode 100644 roms/u-boot/include/cli.h create mode 100644 roms/u-boot/include/cli_hush.h create mode 100644 roms/u-boot/include/clk-uclass.h create mode 100644 roms/u-boot/include/clk.h create mode 100644 roms/u-boot/include/clock_legacy.h create mode 100644 roms/u-boot/include/cmd_spl.h create mode 100644 roms/u-boot/include/command.h create mode 100644 roms/u-boot/include/common.h create mode 100644 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roms/u-boot/include/zfs/zfs_acl.h create mode 100644 roms/u-boot/include/zfs/zfs_znode.h create mode 100644 roms/u-boot/include/zfs/zil.h create mode 100644 roms/u-boot/include/zfs/zio.h create mode 100644 roms/u-boot/include/zfs/zio_checksum.h create mode 100644 roms/u-boot/include/zfs_common.h create mode 100644 roms/u-boot/include/zynq_bootimg.h create mode 100644 roms/u-boot/include/zynqmp_firmware.h create mode 100644 roms/u-boot/include/zynqmp_tap_delay.h create mode 100644 roms/u-boot/include/zynqmppl.h create mode 100644 roms/u-boot/include/zynqpl.h (limited to 'roms/u-boot/include') diff --git a/roms/u-boot/include/.gitignore b/roms/u-boot/include/.gitignore new file mode 100644 index 000000000..8e41a9511 --- /dev/null +++ b/roms/u-boot/include/.gitignore @@ -0,0 +1,4 @@ +/autoconf.mk* +/bmp_logo.h +/bmp_logo_data.h +/config.h diff --git a/roms/u-boot/include/ACEX1K.h b/roms/u-boot/include/ACEX1K.h new file mode 100644 index 000000000..7c5253c66 --- /dev/null +++ b/roms/u-boot/include/ACEX1K.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2003 + * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de + * + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + */ + +#ifndef _ACEX1K_H_ +#define _ACEX1K_H_ + +#include + +extern int ACEX1K_load(Altera_desc *desc, const void *image, size_t size); +extern int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize); +extern int ACEX1K_info(Altera_desc *desc); + +extern int CYC2_load(Altera_desc *desc, const void *image, size_t size); +extern int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize); +extern int CYC2_info(Altera_desc *desc); + +/* Slave Serial Implementation function table */ +typedef struct { + Altera_pre_fn pre; + Altera_config_fn config; + Altera_clk_fn clk; + Altera_status_fn status; + Altera_done_fn done; + Altera_data_fn data; + Altera_abort_fn abort; + Altera_post_fn post; +} Altera_ACEX1K_Passive_Serial_fns; + +/* Slave Serial Implementation function table */ +typedef struct { + Altera_pre_fn pre; + Altera_config_fn config; + Altera_status_fn status; + Altera_done_fn done; + Altera_write_fn write; + Altera_abort_fn abort; + Altera_post_fn post; +} Altera_CYC2_Passive_Serial_fns; + +/* Device Image Sizes + *********************************************************************/ +/* ACEX1K */ +/* FIXME: Which size do we mean? + * Datasheet says 1337000/8=167125Bytes, + * Filesize of an *.rbf file is 166965 Bytes + */ +#if 0 +#define Altera_EP1K100_SIZE 1337000/8 /* 167125 Bytes */ +#endif +#define Altera_EP1K100_SIZE (166965*8) + +#define Altera_EP2C8_SIZE 247942 +#define Altera_EP2C20_SIZE 586562 +#define Altera_EP2C35_SIZE 883905 +#define Altera_EP3C5_SIZE 368011 /* .rbf size in bytes */ + +#define ALTERA_EP4CE6_SIZE 368011 /* 2944088 Bits */ +#define ALTERA_EP4CE10_SIZE 368011 /* 2944088 Bits */ +#define ALTERA_EP4CE15_SIZE 510856 /* 4086848 Bits */ +#define ALTERA_EP4CE22_SIZE 718569 /* 5748552 Bits */ +#define ALTERA_EP4CE30_SIZE 1191788 /* 9534304 Bits */ +#define ALTERA_EP4CE40_SIZE 1191788 /* 9534304 Bits */ +#define ALTERA_EP4CE55_SIZE 1861195 /* 14889560 Bits */ +#define ALTERA_EP4CE75_SIZE 2495719 /* 19965752 Bits */ +#define ALTERA_EP4CE115_SIZE 3571462 /* 28571696 Bits */ + +/* Descriptor Macros + *********************************************************************/ +/* ACEX1K devices */ +#define Altera_EP1K100_DESC(iface, fn_table, cookie) \ +{ Altera_ACEX1K, iface, Altera_EP1K100_SIZE, fn_table, cookie } + +#endif /* _ACEX1K_H_ */ diff --git a/roms/u-boot/include/MCD_dma.h b/roms/u-boot/include/MCD_dma.h new file mode 100644 index 000000000..2f16c8904 --- /dev/null +++ b/roms/u-boot/include/MCD_dma.h @@ -0,0 +1,369 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + */ + +#ifndef _MCD_API_H +#define _MCD_API_H + +/* Turn Execution Unit tasks ON (#define) or OFF (#undef) */ +#undef MCD_INCLUDE_EU + +/* Number of DMA channels */ +#define NCHANNELS 16 + +/* Total number of variants */ +#ifdef MCD_INCLUDE_EU +#define NUMOFVARIANTS 6 +#else +#define NUMOFVARIANTS 4 +#endif + +/* Define sizes of the various tables */ +#define TASK_TABLE_SIZE (NCHANNELS*32) +#define VAR_TAB_SIZE (128) +#define CONTEXT_SAVE_SIZE (128) +#define FUNCDESC_TAB_SIZE (256) + +#ifdef MCD_INCLUDE_EU +#define FUNCDESC_TAB_NUM 16 +#else +#define FUNCDESC_TAB_NUM 1 +#endif + +#ifndef DEFINESONLY + +/* Portability typedefs */ +#if 1 +#include "common.h" +#else +#ifndef s32 +typedef int s32; +#endif +#ifndef u32 +typedef unsigned int u32; +#endif +#ifndef s16 +typedef short s16; +#endif +#ifndef u16 +typedef unsigned short u16; +#endif +#ifndef s8 +typedef char s8; +#endif +#ifndef u8 +typedef unsigned char u8; +#endif +#endif + +/* + * These structures represent the internal registers of the + * multi-channel DMA + */ +struct dmaRegs_s { + u32 taskbar; /* task table base address */ + u32 currPtr; + u32 endPtr; + u32 varTablePtr; + u16 dma_rsvd0; + u16 ptdControl; /* ptd control */ + u32 intPending; /* interrupt pending */ + u32 intMask; /* interrupt mask */ + u16 taskControl[16]; /* task control */ + u8 priority[32]; /* priority */ + u32 initiatorMux; /* initiator mux control */ + u32 taskSize0; /* task size control 0. */ + u32 taskSize1; /* task size control 1. */ + u32 dma_rsvd1; /* reserved */ + u32 dma_rsvd2; /* reserved */ + u32 debugComp1; /* debug comparator 1 */ + u32 debugComp2; /* debug comparator 2 */ + u32 debugControl; /* debug control */ + u32 debugStatus; /* debug status */ + u32 ptdDebug; /* priority task decode debug */ + u32 dma_rsvd3[31]; /* reserved */ +}; +typedef volatile struct dmaRegs_s dmaRegs; + +#endif + +/* PTD contrl reg bits */ +#define PTD_CTL_TSK_PRI 0x8000 +#define PTD_CTL_COMM_PREFETCH 0x0001 + +/* Task Control reg bits and field masks */ +#define TASK_CTL_EN 0x8000 +#define TASK_CTL_VALID 0x4000 +#define TASK_CTL_ALWAYS 0x2000 +#define TASK_CTL_INIT_MASK 0x1f00 +#define TASK_CTL_ASTRT 0x0080 +#define TASK_CTL_HIPRITSKEN 0x0040 +#define TASK_CTL_HLDINITNUM 0x0020 +#define TASK_CTL_ASTSKNUM_MASK 0x000f + +/* Priority reg bits and field masks */ +#define PRIORITY_HLD 0x80 +#define PRIORITY_PRI_MASK 0x07 + +/* Debug Control reg bits and field masks */ +#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000 +#define DBG_CTL_AUTO_ARM 0x00008000 +#define DBG_CTL_BREAK 0x00004000 +#define DBG_CTL_COMP1_TYP_MASK 0x00003800 +#define DBG_CTL_COMP2_TYP_MASK 0x00000070 +#define DBG_CTL_EXT_BREAK 0x00000004 +#define DBG_CTL_INT_BREAK 0x00000002 + +/* + * PTD Debug reg selector addresses + * This reg must be written with a value to show the contents of + * one of the desired internal register. + */ +#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */ +#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and + have initiators asserted */ + +/* General return values */ +#define MCD_OK 0 +#define MCD_ERROR -1 +#define MCD_TABLE_UNALIGNED -2 +#define MCD_CHANNEL_INVALID -3 + +/* MCD_initDma input flags */ +#define MCD_RELOC_TASKS 0x00000001 +#define MCD_NO_RELOC_TASKS 0x00000000 +#define MCD_COMM_PREFETCH_EN 0x00000002 /* MCF547x/548x ONLY */ + +/* + * MCD_dmaStatus Status Values for each channel: + * MCD_NO_DMA - No DMA has been requested since reset + * MCD_IDLE - DMA active, but the initiator is currently inactive + * MCD_RUNNING - DMA active, and the initiator is currently active + * MCD_PAUSED - DMA active but it is currently paused + * MCD_HALTED - the most recent DMA has been killed with MCD_killTask() + * MCD_DONE - the most recent DMA has completed + */ +#define MCD_NO_DMA 1 +#define MCD_IDLE 2 +#define MCD_RUNNING 3 +#define MCD_PAUSED 4 +#define MCD_HALTED 5 +#define MCD_DONE 6 + +/* MCD_startDma parameter defines */ + +/* Constants for the funcDesc parameter */ +/* + * MCD_NO_BYTE_SWAP - to disable byte swapping + * MCD_BYTE_REVERSE - to reverse the bytes of each u32 of the DMAed data + * MCD_U16_REVERSE - to reverse the 16-bit halves of each 32-bit data + * value being DMAed + * MCD_U16_BYTE_REVERSE - to reverse the byte halves of each 16-bit half of + * each 32-bit data value DMAed + * MCD_NO_BIT_REV - do not reverse the bits of each byte DMAed + * MCD_BIT_REV - reverse the bits of each byte DMAed + * MCD_CRC16 - to perform CRC-16 on DMAed data + * MCD_CRCCCITT - to perform CRC-CCITT on DMAed data + * MCD_CRC32 - to perform CRC-32 on DMAed data + * MCD_CSUMINET - to perform internet checksums on DMAed data + * MCD_NO_CSUM - to perform no checksumming + */ +#define MCD_NO_BYTE_SWAP 0x00045670 +#define MCD_BYTE_REVERSE 0x00076540 +#define MCD_U16_REVERSE 0x00067450 +#define MCD_U16_BYTE_REVERSE 0x00054760 +#define MCD_NO_BIT_REV 0x00000000 +#define MCD_BIT_REV 0x00088880 +/* CRCing: */ +#define MCD_CRC16 0xc0100000 +#define MCD_CRCCCITT 0xc0200000 +#define MCD_CRC32 0xc0300000 +#define MCD_CSUMINET 0xc0400000 +#define MCD_NO_CSUM 0xa0000000 + +#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | \ + MCD_NO_CSUM) +#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM) + +/* Constants for the flags parameter */ +#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */ +#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */ +#define MCD_TT_FLAGS_SP 0x00000004 /* MCF547x/548x ONLY */ +#define MCD_TT_FLAGS_MASK 0x000000ff +#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW) + +#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */ +#define MCD_CHAIN_DMA /* TBD */ +#define MCD_EU_DMA /* TBD */ +#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */ +#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */ + +/* these flags are valid for MCD_startDma and the chained buffer descriptors */ +/* + * MCD_BUF_READY - indicates that this buf is now under the DMA's ctrl + * MCD_WRAP - to tell the FEC Dmas to wrap to the first BD + * MCD_INTERRUPT - to generate an interrupt after completion of the DMA + * MCD_END_FRAME - tell the DMA to end the frame when transferring + * last byte of data in buffer + * MCD_CRC_RESTART - to empty out the accumulated checksum prior to + * performing the DMA + */ +#define MCD_BUF_READY 0x80000000 +#define MCD_WRAP 0x20000000 +#define MCD_INTERRUPT 0x10000000 +#define MCD_END_FRAME 0x08000000 +#define MCD_CRC_RESTART 0x40000000 + +/* Defines for the FEC buffer descriptor control/status word*/ +#define MCD_FEC_BUF_READY 0x8000 +#define MCD_FEC_WRAP 0x2000 +#define MCD_FEC_INTERRUPT 0x1000 +#define MCD_FEC_END_FRAME 0x0800 + +/* Defines for general intuitiveness */ + +#define MCD_TRUE 1 +#define MCD_FALSE 0 + +/* Three different cases for destination and source. */ +#define MINUS1 -1 +#define ZERO 0 +#define PLUS1 1 + +#ifndef DEFINESONLY + +/* Task Table Entry struct*/ +typedef struct { + u32 TDTstart; /* task descriptor table start */ + u32 TDTend; /* task descriptor table end */ + u32 varTab; /* variable table start */ + u32 FDTandFlags; /* function descriptor table start & flags */ + volatile u32 descAddrAndStatus; + volatile u32 modifiedVarTab; + u32 contextSaveSpace; /* context save space start */ + u32 literalBases; +} TaskTableEntry; + +/* Chained buffer descriptor: + * flags - flags describing the DMA + * csumResult - checksum performed since last checksum reset + * srcAddr - the address to move data from + * destAddr - the address to move data to + * lastDestAddr - the last address written to + * dmaSize - the no of bytes to xfer independent of the xfer sz + * next - next buffer descriptor in chain + * info - private info about this descriptor; DMA does not affect it + */ +typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; +struct MCD_bufDesc_struct { + u32 flags; + u32 csumResult; + s8 *srcAddr; + s8 *destAddr; + s8 *lastDestAddr; + u32 dmaSize; + MCD_bufDesc *next; + u32 info; +}; + +/* Progress Query struct: + * lastSrcAddr - the most-recent or last, post-increment source address + * lastDestAddr - the most-recent or last, post-increment destination address + * dmaSize - the amount of data transferred for the current buffer + * currBufDesc - pointer to the current buffer descriptor being DMAed + */ + +typedef volatile struct MCD_XferProg_struct { + s8 *lastSrcAddr; + s8 *lastDestAddr; + u32 dmaSize; + MCD_bufDesc *currBufDesc; +} MCD_XferProg; + +/* FEC buffer descriptor */ +typedef volatile struct MCD_bufDescFec_struct { + u16 statCtrl; + u16 length; + u32 dataPointer; +} MCD_bufDescFec; + +/*************************************************************************/ +/* API function Prototypes - see MCD_dmaApi.c for further notes */ + +/* MCD_startDma starts a particular kind of DMA: + * srcAddr - the channel on which to run the DMA + * srcIncr - the address to move data from, or buffer-descriptor address + * destAddr - the amount to increment the source address per transfer + * destIncr - the address to move data to + * dmaSize - the amount to increment the destination address per transfer + * xferSize - the number bytes in of each data movement (1, 2, or 4) + * initiator - what device initiates the DMA + * priority - priority of the DMA + * flags - flags describing the DMA + * funcDesc - description of byte swapping, bit swapping, and CRC actions + */ +int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr, + s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator, + int priority, u32 flags, u32 funcDesc); + +/* + * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA + * registers, relocating and creating the appropriate task structures, and + * setting up some global settings + */ +int MCD_initDma(dmaRegs * sDmaBarAddr, void *taskTableDest, u32 flags); + +/* MCD_dmaStatus() returns the status of the DMA on the requested channel. */ +int MCD_dmaStatus(int channel); + +/* MCD_XferProgrQuery() returns progress of DMA on requested channel */ +int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep); + +/* + * MCD_killDma() halts the DMA on the requested channel, without any + * intention of resuming the DMA. + */ +int MCD_killDma(int channel); + +/* + * MCD_continDma() continues a DMA which as stopped due to encountering an + * unready buffer descriptor. + */ +int MCD_continDma(int channel); + +/* + * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is + * running on that channel). + */ +int MCD_pauseDma(int channel); + +/* + * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is + * running on that channel). + */ +int MCD_resumeDma(int channel); + +/* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */ +int MCD_csumQuery(int channel, u32 * csum); + +/* + * MCD_getCodeSize provides the packed size required by the microcoded task + * and structures. + */ +int MCD_getCodeSize(void); + +/* + * MCD_getVersion provides a pointer to a version string and returns a + * version number. + */ +int MCD_getVersion(char **longVersion); + +/* macro for setting a location in the variable table */ +#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value +/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function, + so I'm avoiding surrounding it with "do {} while(0)" */ + +#endif /* DEFINESONLY */ + +#endif /* _MCD_API_H */ diff --git a/roms/u-boot/include/MCD_progCheck.h b/roms/u-boot/include/MCD_progCheck.h new file mode 100644 index 000000000..1ec8fbfbd --- /dev/null +++ b/roms/u-boot/include/MCD_progCheck.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + */ + + /* This file is autogenerated. Do not change */ +#define CURRBD 4 +#define DCOUNT 6 +#define DESTPTR 5 +#define SRCPTR 7 diff --git a/roms/u-boot/include/MCD_tasksInit.h b/roms/u-boot/include/MCD_tasksInit.h new file mode 100644 index 000000000..9f582beb5 --- /dev/null +++ b/roms/u-boot/include/MCD_tasksInit.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + */ + +#ifndef MCD_TSK_INIT_H +#define MCD_TSK_INIT_H 1 + +/* + * Do not edit! + */ + +/* Task 0 */ +void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, + int xferSize, short xferSizeIncr, int *cSave, + volatile TaskTableEntry * taskTable, int channel); + +/* Task 1 */ +void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, + short destIncr, int dmaSize, short xferSizeIncr, + int flags, int *currBD, int *cSave, + volatile TaskTableEntry * taskTable, int channel); + +/* Task 2 */ +void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, + int xferSize, short xferSizeIncr, int *cSave, + volatile TaskTableEntry * taskTable, int channel); + +/* Task 3 */ +void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, + short destIncr, int dmaSize, short xferSizeIncr, + int flags, int *currBD, int *cSave, + volatile TaskTableEntry * taskTable, int channel); + +/* Task 4 */ +void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, + volatile TaskTableEntry * taskTable, int channel); + +/* Task 5 */ +void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, + volatile TaskTableEntry * taskTable, int channel); + +#endif /* MCD_TSK_INIT_H */ diff --git a/roms/u-boot/include/SA-1100.h b/roms/u-boot/include/SA-1100.h new file mode 100644 index 000000000..7589df238 --- /dev/null +++ b/roms/u-boot/include/SA-1100.h @@ -0,0 +1,2833 @@ +/* + * FILE SA-1100.h + * + * Version 1.2 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date January 1998 (April 1997) + * System StrongARM SA-1100 + * Language C or ARM Assembly + * Purpose Definition of constants related to the StrongARM + * SA-1100 microprocessor (Advanced RISC Machine (ARM) + * architecture version 4). This file is based on the + * StrongARM SA-1100 data sheet version 2.2. + * + * Language-specific definitions are selected by the + * macro "LANGUAGE", which should be defined as either + * "C" (default) or "Assembly". + */ + + +#ifndef LANGUAGE +# ifdef __ASSEMBLY__ +# define LANGUAGE Assembly +# else +# define LANGUAGE C +# endif +#endif + +#ifndef io_p2v +#define io_p2v(PhAdd) (PhAdd) +#endif + +#include + +#define C 0 +#define Assembly 1 + + +#if LANGUAGE == C +typedef unsigned short Word16 ; +typedef unsigned int Word32 ; +typedef Word32 Word ; +typedef Word Quad [4] ; +typedef void *Address ; +typedef void (*ExcpHndlr) (void) ; +#endif /* LANGUAGE == C */ + + +/* + * Memory + */ + +#define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */ + +#define StMemBnkSp MemBnkSp /* Static Memory Bank Space [byte] */ +#define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */ + /* [byte] */ +#define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */ + /* [byte] */ +#define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */ + /* [byte] */ +#define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */ + /* [byte] */ + +#define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */ +#define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */ +#define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */ +#define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */ +#define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */ + +#define ZeroMemSp MemBnkSp /* Zero Memory bank Space [byte] */ + +#define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \ + (0x00000000 + (Nb)*StMemBnkSp) +#define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */ +#define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */ +#define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */ +#define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */ + +#if LANGUAGE == C +typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ; +#define StMemBnk /* Static Memory Bank [0..3] */ \ + ((StMemBnkType *) io_p2v (_StMemBnk (0))) +#define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */ +#define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */ +#define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */ +#define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */ +#endif /* LANGUAGE == C */ + +#define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \ + (0xC0000000 + (Nb)*DRAMBnkSp) +#define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */ +#define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */ +#define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */ +#define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */ + +#if LANGUAGE == C +typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ; +#define DRAMBnk /* DRAM Bank [0..3] */ \ + ((DRAMBnkType *) io_p2v (_DRAMBnk (0))) +#define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */ +#define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */ +#define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */ +#define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */ +#endif /* LANGUAGE == C */ + +#define _ZeroMem 0xE0000000 /* Zero Memory bank */ + +#if LANGUAGE == C +typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ; +#define ZeroMem /* Zero Memory bank */ \ + (*((ZeroMemType *) io_p2v (_ZeroMem))) +#endif /* LANGUAGE == C */ + + +/* + * Personal Computer Memory Card International Association (PCMCIA) sockets + */ + +#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ +#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ +#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ +#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ +#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ + +#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ +#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ +#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ +#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ + +#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ +#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ +#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ +#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ + +#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ + (0x20000000 + (Nb)*PCMCIASp) +#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ +#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ + (_PCMCIA (Nb) + 2*PCMCIAPrtSp) +#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ + (_PCMCIA (Nb) + 3*PCMCIAPrtSp) + +#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ +#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ +#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ +#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ + +#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ +#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ +#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ +#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ + +#if LANGUAGE == C + +typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ; +typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; + +#define PCMCIA0 /* PCMCIA 0 */ \ + (*((PCMCIAType *) io_p2v (_PCMCIA0))) +#define PCMCIA0IO /* PCMCIA 0 I/O */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO))) +#define PCMCIA0Attr /* PCMCIA 0 Attribute */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr))) +#define PCMCIA0Mem /* PCMCIA 0 Memory */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem))) + +#define PCMCIA1 /* PCMCIA 1 */ \ + (*((PCMCIAType *) io_p2v (_PCMCIA1))) +#define PCMCIA1IO /* PCMCIA 1 I/O */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO))) +#define PCMCIA1Attr /* PCMCIA 1 Attribute */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr))) +#define PCMCIA1Mem /* PCMCIA 1 Memory */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem))) + +#endif /* LANGUAGE == C */ + + +/* + * Universal Serial Bus (USB) Device Controller (UDC) control registers + * + * Registers + * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control Register (read/write). + * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Address Register (read/write). + * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Output Maximum Packet size register + * (read/write). + * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Input Maximum Packet size register + * (read/write). + * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control/Status register end-point 0 + * (read/write). + * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control/Status register end-point 1 + * (output, read/write). + * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control/Status register end-point 2 + * (input, read/write). + * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Data register end-point 0 + * (read/write). + * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Write Count register end-point 0 + * (read). + * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Data Register (read/write). + * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Status Register (read/write). + */ + +#define _Ser0UDCCR 0x80000000 /* Ser. port 0 UDC Control Reg. */ +#define _Ser0UDCAR 0x80000004 /* Ser. port 0 UDC Address Reg. */ +#define _Ser0UDCOMP 0x80000008 /* Ser. port 0 UDC Output Maximum */ + /* Packet size reg. */ +#define _Ser0UDCIMP 0x8000000C /* Ser. port 0 UDC Input Maximum */ + /* Packet size reg. */ +#define _Ser0UDCCS0 0x80000010 /* Ser. port 0 UDC Control/Status */ + /* reg. end-point 0 */ +#define _Ser0UDCCS1 0x80000014 /* Ser. port 0 UDC Control/Status */ + /* reg. end-point 1 (output) */ +#define _Ser0UDCCS2 0x80000018 /* Ser. port 0 UDC Control/Status */ + /* reg. end-point 2 (input) */ +#define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */ + /* end-point 0 */ +#define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */ + /* reg. end-point 0 */ +#define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */ +#define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */ + +#if LANGUAGE == C +#define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCCR))) +#define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCAR))) +#define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \ + /* Packet size reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCOMP))) +#define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \ + /* Packet size reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCIMP))) +#define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \ + /* reg. end-point 0 */ \ + (*((volatile Word *) io_p2v (_Ser0UDCCS0))) +#define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \ + /* reg. end-point 1 (output) */ \ + (*((volatile Word *) io_p2v (_Ser0UDCCS1))) +#define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \ + /* reg. end-point 2 (input) */ \ + (*((volatile Word *) io_p2v (_Ser0UDCCS2))) +#define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \ + /* end-point 0 */ \ + (*((volatile Word *) io_p2v (_Ser0UDCD0))) +#define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \ + /* reg. end-point 0 */ \ + (*((volatile Word *) io_p2v (_Ser0UDCWC))) +#define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCDR))) +#define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCSR))) +#endif /* LANGUAGE == C */ + +#define UDCCR_UDD 0x00000001 /* UDC Disable */ +#define UDCCR_UDA 0x00000002 /* UDC Active (read) */ +#define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ +#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ + /* (disable) */ +#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ + /* (disable) */ +#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ + /* (disable) */ +#define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ + /* (disable) */ +#define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ +#define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ + +#define UDCAR_ADD Fld (7, 0) /* function ADDress */ + +#define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ + /* [byte] */ +#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ + /* [1..256 byte] */ \ + (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) + +#define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ + /* [byte] */ +#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ + /* [1..256 byte] */ \ + (((Size) - 1) << FShft (UDCIMP_INMAXP)) + +#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ +#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ +#define UDCCS0_SST 0x00000004 /* Sent STall */ +#define UDCCS0_FST 0x00000008 /* Force STall */ +#define UDCCS0_DE 0x00000010 /* Data End */ +#define UDCCS0_SE 0x00000020 /* Setup End (read) */ +#define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ + /* (write) */ +#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ + +#define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ + /* Service request (read) */ +#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ +#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ +#define UDCCS1_SST 0x00000008 /* Sent STall */ +#define UDCCS1_FST 0x00000010 /* Force STall */ +#define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ + +#define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ + /* Service request (read) */ +#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ +#define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ +#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ +#define UDCCS2_SST 0x00000010 /* Sent STall */ +#define UDCCS2_FST 0x00000020 /* Force STall */ + +#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ + +#define UDCWC_WC Fld (4, 0) /* Write Count */ + +#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ + +#define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */ +#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ +#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ +#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ +#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ +#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ + + +/* + * Universal Asynchronous Receiver/Transmitter (UART) control registers + * + * Registers + * Ser1UTCR0 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 0 + * (read/write). + * Ser1UTCR1 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 1 + * (read/write). + * Ser1UTCR2 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 2 + * (read/write). + * Ser1UTCR3 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 3 + * (read/write). + * Ser1UTDR Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Data Register + * (read/write). + * Ser1UTSR0 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 0 + * (read/write). + * Ser1UTSR1 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 1 (read). + * + * Ser2UTCR0 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 0 + * (read/write). + * Ser2UTCR1 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 1 + * (read/write). + * Ser2UTCR2 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 2 + * (read/write). + * Ser2UTCR3 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 3 + * (read/write). + * Ser2UTCR4 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 4 + * (read/write). + * Ser2UTDR Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Data Register + * (read/write). + * Ser2UTSR0 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 0 + * (read/write). + * Ser2UTSR1 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 1 (read). + * + * Ser3UTCR0 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 0 + * (read/write). + * Ser3UTCR1 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 1 + * (read/write). + * Ser3UTCR2 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 2 + * (read/write). + * Ser3UTCR3 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 3 + * (read/write). + * Ser3UTDR Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Data Register + * (read/write). + * Ser3UTSR0 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 0 + * (read/write). + * Ser3UTSR1 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 1 (read). + * + * Clocks + * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz + * or 3.5795 MHz). + * fua, Tua Frequency, period of the UART communication. + */ + +#define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \ + (0x80010000 + ((Nb) - 1)*0x00020000) +#define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \ + (0x80010004 + ((Nb) - 1)*0x00020000) +#define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \ + (0x80010008 + ((Nb) - 1)*0x00020000) +#define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \ + (0x8001000C + ((Nb) - 1)*0x00020000) +#define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \ + (0x80010010 + ((Nb) - 1)*0x00020000) +#define _UTDR(Nb) /* UART Data Reg. [1..3] */ \ + (0x80010014 + ((Nb) - 1)*0x00020000) +#define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \ + (0x8001001C + ((Nb) - 1)*0x00020000) +#define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \ + (0x80010020 + ((Nb) - 1)*0x00020000) + +#define _Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ +#define _Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ +#define _Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */ +#define _Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */ +#define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ +#define _Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */ +#define _Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */ + +#define _Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */ +#define _Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */ +#define _Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */ +#define _Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */ +#define _Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */ +#define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ +#define _Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */ +#define _Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */ + +#define _Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */ +#define _Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */ +#define _Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */ +#define _Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */ +#define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ +#define _Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */ +#define _Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */ + +#if LANGUAGE == C + +#define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser1UTCR0))) +#define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser1UTCR1))) +#define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_Ser1UTCR2))) +#define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \ + (*((volatile Word *) io_p2v (_Ser1UTCR3))) +#define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser1UTDR))) +#define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser1UTSR0))) +#define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser1UTSR1))) + +#define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser2UTCR0))) +#define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser2UTCR1))) +#define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_Ser2UTCR2))) +#define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \ + (*((volatile Word *) io_p2v (_Ser2UTCR3))) +#define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \ + (*((volatile Word *) io_p2v (_Ser2UTCR4))) +#define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser2UTDR))) +#define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser2UTSR0))) +#define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser2UTSR1))) + +#define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser3UTCR0))) +#define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser3UTCR1))) +#define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_Ser3UTCR2))) +#define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \ + (*((volatile Word *) io_p2v (_Ser3UTCR3))) +#define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser3UTDR))) +#define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser3UTSR0))) +#define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser3UTSR1))) + +#elif LANGUAGE == Assembly +#define Ser1UTCR0 ( io_p2v (_Ser1UTCR0)) +#define Ser1UTCR1 ( io_p2v (_Ser1UTCR1)) +#define Ser1UTCR2 ( io_p2v (_Ser1UTCR2)) +#define Ser1UTCR3 ( io_p2v (_Ser1UTCR3)) +#define Ser1UTDR ( io_p2v (_Ser1UTDR)) +#define Ser1UTSR0 ( io_p2v (_Ser1UTSR0)) +#define Ser1UTSR1 ( io_p2v (_Ser1UTSR1)) + +#define Ser2UTCR0 ( io_p2v (_Ser2UTCR0)) +#define Ser2UTCR1 ( io_p2v (_Ser2UTCR1)) +#define Ser2UTCR2 ( io_p2v (_Ser2UTCR2)) +#define Ser2UTCR3 ( io_p2v (_Ser2UTCR3)) +#define Ser2UTCR4 ( io_p2v (_Ser2UTCR4)) +#define Ser2UTDR ( io_p2v (_Ser2UTDR)) +#define Ser2UTSR0 ( io_p2v (_Ser2UTSR0)) +#define Ser2UTSR1 ( io_p2v (_Ser2UTSR1)) + +#define Ser3UTCR0 ( io_p2v (_Ser3UTCR0)) +#define Ser3UTCR1 ( io_p2v (_Ser3UTCR1)) +#define Ser3UTCR2 ( io_p2v (_Ser3UTCR2)) +#define Ser3UTCR3 ( io_p2v (_Ser3UTCR3)) +#define Ser3UTDR ( io_p2v (_Ser3UTDR)) +#define Ser3UTSR0 ( io_p2v (_Ser3UTSR0)) +#define Ser3UTSR1 ( io_p2v (_Ser3UTSR1)) + +#endif /* LANGUAGE == C */ + +#define UTCR0_PE 0x00000001 /* Parity Enable */ +#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ +#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ +#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ +#define UTCR0_SBS 0x00000004 /* Stop Bit Select */ +#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ +#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ +#define UTCR0_DSS 0x00000008 /* Data Size Select */ +#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ +#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ +#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ + /* (ser. port 1: GPIO [18], */ + /* ser. port 3: GPIO [20]) */ +#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ +#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ +#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ +#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ +#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ +#define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */ +#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ + (UTCR0_1StpBit + UTCR0_8BitData) + +#define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ +#define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ + /* fua = fxtl/(16*(BRD[11:0] + 1)) */ + /* Tua = 16*(BRD [11:0] + 1)*Txtl */ +#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ + (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ + FShft (UTCR1_BRD)) +#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ + (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ + FShft (UTCR2_BRD)) + /* fua = fxtl/(16*Floor (Div/16)) */ + /* Tua = 16*Floor (Div/16)*Txtl */ +#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ + (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ + FShft (UTCR1_BRD)) +#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ + (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ + FShft (UTCR2_BRD)) + /* fua = fxtl/(16*Ceil (Div/16)) */ + /* Tua = 16*Ceil (Div/16)*Txtl */ + +#define UTCR3_RXE 0x00000001 /* Receive Enable */ +#define UTCR3_TXE 0x00000002 /* Transmit Enable */ +#define UTCR3_BRK 0x00000004 /* BReaK mode */ +#define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ + /* more Interrupt Enable */ +#define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ + /* Interrupt Enable */ +#define UTCR3_LBM 0x00000020 /* Look-Back Mode */ +#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ + /* TIE, LBM can be set or cleared) */ \ + (UTCR3_RXE + UTCR3_TXE) + +#define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */ + /* (HP-SIR) modulation Enable */ +#define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */ +#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ +#define UTCR4_LPM 0x00000002 /* Low-Power Mode */ +#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ +#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ + +#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#if 0 /* Hidden receive FIFO bits */ +#define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */ +#define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */ +#define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ +#endif /* 0 */ + +#define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */ + /* Service request (read) */ +#define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */ + /* more Service request (read) */ +#define UTSR0_RID 0x00000004 /* Receiver IDle */ +#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ +#define UTSR0_REB 0x00000010 /* Receive End of Break */ +#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ + +#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ +#define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */ +#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */ +#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ +#define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */ +#define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */ + + +/* + * Synchronous Data Link Controller (SDLC) control registers + * + * Registers + * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 0 (read/write). + * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 1 (read/write). + * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 2 (read/write). + * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 3 (read/write). + * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 4 (read/write). + * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) + * Data Register (read/write). + * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) + * Status Register 0 (read/write). + * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) + * Status Register 1 (read/write). + * + * Clocks + * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz + * or 3.5795 MHz). + * fsd, Tsd Frequency, period of the SDLC communication. + */ + +#define _Ser1SDCR0 0x80020060 /* Ser. port 1 SDLC Control Reg. 0 */ +#define _Ser1SDCR1 0x80020064 /* Ser. port 1 SDLC Control Reg. 1 */ +#define _Ser1SDCR2 0x80020068 /* Ser. port 1 SDLC Control Reg. 2 */ +#define _Ser1SDCR3 0x8002006C /* Ser. port 1 SDLC Control Reg. 3 */ +#define _Ser1SDCR4 0x80020070 /* Ser. port 1 SDLC Control Reg. 4 */ +#define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */ +#define _Ser1SDSR0 0x80020080 /* Ser. port 1 SDLC Status Reg. 0 */ +#define _Ser1SDSR1 0x80020084 /* Ser. port 1 SDLC Status Reg. 1 */ + +#if LANGUAGE == C +#define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser1SDCR0))) +#define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser1SDCR1))) +#define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_Ser1SDCR2))) +#define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \ + (*((volatile Word *) io_p2v (_Ser1SDCR3))) +#define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \ + (*((volatile Word *) io_p2v (_Ser1SDCR4))) +#define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser1SDDR))) +#define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser1SDSR0))) +#define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser1SDSR1))) +#endif /* LANGUAGE == C */ + +#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ +#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ +#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ +#define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */ +#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ +#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ +#define SDCR0_LBM 0x00000004 /* Look-Back Mode */ +#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ +#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ +#define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */ +#define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */ +#define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */ + /* (GPIO [16]) */ +#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ +#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ +#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ +#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */ +#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */ +#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */ +#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */ +#define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */ + +#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ + /* (GPIO [17]) */ +#define SDCR1_TXE 0x00000002 /* Transmit Enable */ +#define SDCR1_RXE 0x00000004 /* Receive Enable */ +#define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ + /* more Interrupt Enable */ +#define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ + /* Interrupt Enable */ +#define SDCR1_AME 0x00000020 /* Address Match Enable */ +#define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */ +#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ +#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */ +#define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */ + +#define SDCR2_AMV Fld (8, 0) /* Address Match Value */ + +#define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ +#define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ + /* fsd = fxtl/(16*(BRD[11:0] + 1)) */ + /* Tsd = 16*(BRD[11:0] + 1)*Txtl */ +#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ + (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \ + FShft (SDCR3_BRD)) +#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ + (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \ + FShft (SDCR4_BRD)) + /* fsd = fxtl/(16*Floor (Div/16)) */ + /* Tsd = 16*Floor (Div/16)*Txtl */ +#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ + (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \ + FShft (SDCR3_BRD)) +#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ + (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \ + FShft (SDCR4_BRD)) + /* fsd = fxtl/(16*Ceil (Div/16)) */ + /* Tsd = 16*Ceil (Div/16)*Txtl */ + +#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#if 0 /* Hidden receive FIFO bits */ +#define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ +#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */ +#define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ +#endif /* 0 */ + +#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */ +#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ +#define SDSR0_RAB 0x00000004 /* Receive ABort */ +#define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ + /* Service request (read) */ +#define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */ + /* more Service request (read) */ + +#define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ +#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ +#define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ +#define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ +#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */ +#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */ +#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */ +#define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */ + + +/* + * High-Speed Serial to Parallel controller (HSSP) control registers + * + * Registers + * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Control Register 0 (read/write). + * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Control Register 1 (read/write). + * Ser2HSDR Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Data Register (read/write). + * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Status Register 0 (read/write). + * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Status Register 1 (read). + * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Control Register 2 (read/write). + * [The HSCR2 register is only implemented in + * versions 2.0 (rev. = 8) and higher of the StrongARM + * SA-1100.] + */ + +#define _Ser2HSCR0 0x80040060 /* Ser. port 2 HSSP Control Reg. 0 */ +#define _Ser2HSCR1 0x80040064 /* Ser. port 2 HSSP Control Reg. 1 */ +#define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */ +#define _Ser2HSSR0 0x80040074 /* Ser. port 2 HSSP Status Reg. 0 */ +#define _Ser2HSSR1 0x80040078 /* Ser. port 2 HSSP Status Reg. 1 */ +#define _Ser2HSCR2 0x90060028 /* Ser. port 2 HSSP Control Reg. 2 */ + +#if LANGUAGE == C +#define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser2HSCR0))) +#define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser2HSCR1))) +#define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser2HSDR))) +#define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser2HSSR0))) +#define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser2HSSR1))) +#define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_Ser2HSCR2))) +#endif /* LANGUAGE == C */ + +#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ +#define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */ +#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */ +#define HSCR0_LBM 0x00000002 /* Look-Back Mode */ +#define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */ +#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */ +#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */ +#define HSCR0_TXE 0x00000008 /* Transmit Enable */ +#define HSCR0_RXE 0x00000010 /* Receive Enable */ +#define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */ + /* more Interrupt Enable */ +#define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */ + /* Interrupt Enable */ +#define HSCR0_AME 0x00000080 /* Address Match Enable */ + +#define HSCR1_AMV Fld (8, 0) /* Address Match Value */ + +#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#if 0 /* Hidden receive FIFO bits */ +#define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ +#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */ +#define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ +#endif /* 0 */ + +#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */ +#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ +#define HSSR0_RAB 0x00000004 /* Receive ABort */ +#define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ + /* Service request (read) */ +#define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */ + /* more Service request (read) */ +#define HSSR0_FRE 0x00000020 /* receive FRaming Error */ + +#define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ +#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */ +#define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ +#define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ +#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */ +#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */ +#define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */ + +#define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */ +#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ + /* (inverted) */ +#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ + /* (non-inverted) */ +#define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */ +#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ + /* (inverted) */ +#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ + /* (non-inverted) */ + + +/* + * Multi-media Communications Port (MCP) control registers + * + * Registers + * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP) + * Control Register 0 (read/write). + * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP) + * Data Register 0 (audio, read/write). + * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP) + * Data Register 1 (telecom, read/write). + * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP) + * Data Register 2 (CODEC registers, read/write). + * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP) + * Status Register (read/write). + * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP) + * Control Register 1 (read/write). + * [The MCCR1 register is only implemented in + * versions 2.0 (rev. = 8) and higher of the StrongARM + * SA-1100.] + * + * Clocks + * fmc, Tmc Frequency, period of the MCP communication (10 MHz, + * 12 MHz, or GPIO [21]). + * faud, Taud Frequency, period of the audio sampling. + * ftcm, Ttcm Frequency, period of the telecom sampling. + */ + +#define _Ser4MCCR0 0x80060000 /* Ser. port 4 MCP Control Reg. 0 */ +#define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */ + /* (audio) */ +#define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */ + /* (telecom) */ +#define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */ + /* (CODEC reg.) */ +#define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */ +#define _Ser4MCCR1 0x90060030 /* Ser. port 4 MCP Control Reg. 1 */ + +#if LANGUAGE == C +#define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser4MCCR0))) +#define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \ + /* (audio) */ \ + (*((volatile Word *) io_p2v (_Ser4MCDR0))) +#define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \ + /* (telecom) */ \ + (*((volatile Word *) io_p2v (_Ser4MCDR1))) +#define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \ + /* (CODEC reg.) */ \ + (*((volatile Word *) io_p2v (_Ser4MCDR2))) +#define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \ + (*((volatile Word *) io_p2v (_Ser4MCSR))) +#define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser4MCCR1))) +#endif /* LANGUAGE == C */ + +#define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */ + /* [6..127] */ + /* faud = fmc/(32*ASD) */ + /* Taud = 32*ASD*Tmc */ +#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ + /* [192..4064] */ \ + ((Div)/32 << FShft (MCCR0_ASD)) + /* faud = fmc/(32*Floor (Div/32)) */ + /* Taud = 32*Floor (Div/32)*Tmc */ +#define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \ + (((Div) + 31)/32 << FShft (MCCR0_ASD)) + /* faud = fmc/(32*Ceil (Div/32)) */ + /* Taud = 32*Ceil (Div/32)*Tmc */ +#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ + /* Divisor/32 [16..127] */ + /* ftcm = fmc/(32*TSD) */ + /* Ttcm = 32*TSD*Tmc */ +#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ + /* [512..4064] */ \ + ((Div)/32 << FShft (MCCR0_TSD)) + /* ftcm = fmc/(32*Floor (Div/32)) */ + /* Ttcm = 32*Floor (Div/32)*Tmc */ +#define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \ + (((Div) + 31)/32 << FShft (MCCR0_TSD)) + /* ftcm = fmc/(32*Ceil (Div/32)) */ + /* Ttcm = 32*Ceil (Div/32)*Tmc */ +#define MCCR0_MCE 0x00010000 /* MCP Enable */ +#define MCCR0_ECS 0x00020000 /* External Clock Select */ +#define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */ +#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ +#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ + /* sampling/storing Mode */ +#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ +#define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */ +#define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */ + /* or less interrupt Enable */ +#define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */ + /* or more interrupt Enable */ +#define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */ + /* or less interrupt Enable */ +#define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */ + /* more interrupt Enable */ +#define MCCR0_LBM 0x00800000 /* Look-Back Mode */ +#define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */ +#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ + (((Div) - 1) << FShft (MCCR0_ECP)) + +#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ + /* FIFOs */ + +#define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */ + /* FIFOs */ + + /* receive/transmit CODEC reg. */ + /* FIFOs: */ +#define MCDR2_DATA Fld (16, 0) /* reg. DATA */ +#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ +#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ +#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */ +#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ + +#define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */ + /* or less Service request (read) */ +#define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */ + /* more Service request (read) */ +#define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */ + /* or less Service request (read) */ +#define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */ + /* or more Service request (read) */ +#define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */ +#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ +#define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */ +#define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */ +#define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */ + /* (read) */ +#define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */ + /* (read) */ +#define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */ + /* (read) */ +#define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */ + /* (read) */ +#define MCSR_CWC 0x00001000 /* CODEC register Write Completed */ + /* (read) */ +#define MCSR_CRC 0x00002000 /* CODEC register Read Completed */ + /* (read) */ +#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ +#define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */ + +#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ +#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ + /* (11.981 MHz) */ +#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ + /* (9.585 MHz) */ + + +/* + * Synchronous Serial Port (SSP) control registers + * + * Registers + * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control + * Register 0 (read/write). + * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control + * Register 1 (read/write). + * [Bits SPO and SP are only implemented in versions 2.0 + * (rev. = 8) and higher of the StrongARM SA-1100.] + * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data + * Register (read/write). + * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status + * Register (read/write). + * + * Clocks + * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz + * or 3.5795 MHz). + * fss, Tss Frequency, period of the SSP communication. + */ + +#define _Ser4SSCR0 0x80070060 /* Ser. port 4 SSP Control Reg. 0 */ +#define _Ser4SSCR1 0x80070064 /* Ser. port 4 SSP Control Reg. 1 */ +#define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */ +#define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */ + +#if LANGUAGE == C +#define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser4SSCR0))) +#define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser4SSCR1))) +#define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser4SSDR))) +#define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \ + (*((volatile Word *) io_p2v (_Ser4SSSR))) +#endif /* LANGUAGE == C */ + +#define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */ +#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ + (((Size) - 1) << FShft (SSCR0_DSS)) +#define SSCR0_FRF Fld (2, 4) /* FRame Format */ +#define SSCR0_Motorola /* Motorola Serial Peripheral */ \ + /* Interface (SPI) format */ \ + (0 << FShft (SSCR0_FRF)) +#define SSCR0_TI /* Texas Instruments Synchronous */ \ + /* Serial format */ \ + (1 << FShft (SSCR0_FRF)) +#define SSCR0_National /* National Microwire format */ \ + (2 << FShft (SSCR0_FRF)) +#define SSCR0_SSE 0x00000080 /* SSP Enable */ +#define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */ + /* fss = fxtl/(2*(SCR + 1)) */ + /* Tss = 2*(SCR + 1)*Txtl */ +#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ + (((Div) - 2)/2 << FShft (SSCR0_SCR)) + /* fss = fxtl/(2*Floor (Div/2)) */ + /* Tss = 2*Floor (Div/2)*Txtl */ +#define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \ + (((Div) - 1)/2 << FShft (SSCR0_SCR)) + /* fss = fxtl/(2*Ceil (Div/2)) */ + /* Tss = 2*Ceil (Div/2)*Txtl */ + +#define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ + /* Interrupt Enable */ +#define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */ + /* Interrupt Enable */ +#define SSCR1_LBM 0x00000004 /* Look-Back Mode */ +#define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ +#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ +#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ +#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ +#define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */ + /* after frame (SFRM, 1st edge) */ +#define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */ + /* after frame (SFRM, 1st edge) */ +#define SSCR1_ECS 0x00000020 /* External Clock Select */ +#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ +#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ + +#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ + +#define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */ +#define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ +#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ +#define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */ + /* Service request (read) */ +#define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */ + /* Service request (read) */ +#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ + + +/* + * Operating System (OS) timer control registers + * + * Registers + * OSMR0 Operating System (OS) timer Match Register 0 + * (read/write). + * OSMR1 Operating System (OS) timer Match Register 1 + * (read/write). + * OSMR2 Operating System (OS) timer Match Register 2 + * (read/write). + * OSMR3 Operating System (OS) timer Match Register 3 + * (read/write). + * OSCR Operating System (OS) timer Counter Register + * (read/write). + * OSSR Operating System (OS) timer Status Register + * (read/write). + * OWER Operating System (OS) timer Watch-dog Enable Register + * (read/write). + * OIER Operating System (OS) timer Interrupt Enable Register + * (read/write). + */ + +#define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \ + (0x90000000 + (Nb)*4) +#define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */ +#define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */ +#define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */ +#define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */ +#define _OSCR 0x90000010 /* OS timer Counter Reg. */ +#define _OSSR 0x90000014 /* OS timer Status Reg. */ +#define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */ +#define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */ + +#if LANGUAGE == C +#define OSMR /* OS timer Match Reg. [0..3] */ \ + ((volatile Word *) io_p2v (_OSMR (0))) +#define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */ +#define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */ +#define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */ +#define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */ +#define OSCR /* OS timer Counter Reg. */ \ + (*((volatile Word *) io_p2v (_OSCR))) +#define OSSR /* OS timer Status Reg. */ \ + (*((volatile Word *) io_p2v (_OSSR))) +#define OWER /* OS timer Watch-dog Enable Reg. */ \ + (*((volatile Word *) io_p2v (_OWER))) +#define OIER /* OS timer Interrupt Enable Reg. */ \ + (*((volatile Word *) io_p2v (_OIER))) +#endif /* LANGUAGE == C */ + +#define OSSR_M(Nb) /* Match detected [0..3] */ \ + (0x00000001 << (Nb)) +#define OSSR_M0 OSSR_M (0) /* Match detected 0 */ +#define OSSR_M1 OSSR_M (1) /* Match detected 1 */ +#define OSSR_M2 OSSR_M (2) /* Match detected 2 */ +#define OSSR_M3 OSSR_M (3) /* Match detected 3 */ + +#define OWER_WME 0x00000001 /* Watch-dog Match Enable */ + /* (set only) */ + +#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ + (0x00000001 << (Nb)) +#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ +#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ +#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ +#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */ + + +/* + * Real-Time Clock (RTC) control registers + * + * Registers + * RTAR Real-Time Clock (RTC) Alarm Register (read/write). + * RCNR Real-Time Clock (RTC) CouNt Register (read/write). + * RTTR Real-Time Clock (RTC) Trim Register (read/write). + * RTSR Real-Time Clock (RTC) Status Register (read/write). + * + * Clocks + * frtx, Trtx Frequency, period of the real-time clock crystal + * (32.768 kHz nominal). + * frtc, Trtc Frequency, period of the real-time clock counter + * (1 Hz nominal). + */ + +#define _RTAR 0x90010000 /* RTC Alarm Reg. */ +#define _RCNR 0x90010004 /* RTC CouNt Reg. */ +#define _RTTR 0x90010008 /* RTC Trim Reg. */ +#define _RTSR 0x90010010 /* RTC Status Reg. */ + +#if LANGUAGE == C +#define RTAR /* RTC Alarm Reg. */ \ + (*((volatile Word *) io_p2v (_RTAR))) +#define RCNR /* RTC CouNt Reg. */ \ + (*((volatile Word *) io_p2v (_RCNR))) +#define RTTR /* RTC Trim Reg. */ \ + (*((volatile Word *) io_p2v (_RTTR))) +#define RTSR /* RTC Status Reg. */ \ + (*((volatile Word *) io_p2v (_RTSR))) +#endif /* LANGUAGE == C */ + +#define RTTR_C Fld (16, 0) /* clock divider Count - 1 */ +#define RTTR_D Fld (10, 16) /* trim Delete count */ + /* frtc = (1023*(C + 1) - D)*frtx/ */ + /* (1023*(C + 1)^2) */ + /* Trtc = (1023*(C + 1)^2)*Trtx/ */ + /* (1023*(C + 1) - D) */ + +#define RTSR_AL 0x00000001 /* ALarm detected */ +#define RTSR_HZ 0x00000002 /* 1 Hz clock detected */ +#define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */ +#define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */ + + +/* + * Power Manager (PM) control registers + * + * Registers + * PMCR Power Manager (PM) Control Register (read/write). + * PSSR Power Manager (PM) Sleep Status Register (read/write). + * PSPR Power Manager (PM) Scratch-Pad Register (read/write). + * PWER Power Manager (PM) Wake-up Enable Register + * (read/write). + * PCFR Power Manager (PM) general ConFiguration Register + * (read/write). + * PPCR Power Manager (PM) Phase-Locked Loop (PLL) + * Configuration Register (read/write). + * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO) + * Sleep state Register (read/write, see GPIO pins). + * POSR Power Manager (PM) Oscillator Status Register (read). + * + * Clocks + * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz + * or 3.5795 MHz). + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + */ + +#define _PMCR 0x90020000 /* PM Control Reg. */ +#define _PSSR 0x90020004 /* PM Sleep Status Reg. */ +#define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */ +#define _PWER 0x9002000C /* PM Wake-up Enable Reg. */ +#define _PCFR 0x90020010 /* PM general ConFiguration Reg. */ +#define _PPCR 0x90020014 /* PM PLL Configuration Reg. */ +#define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */ +#define _POSR 0x9002001C /* PM Oscillator Status Reg. */ + +#if LANGUAGE == C +#define PMCR /* PM Control Reg. */ \ + (*((volatile Word *) io_p2v (_PMCR))) +#define PSSR /* PM Sleep Status Reg. */ \ + (*((volatile Word *) io_p2v (_PSSR))) +#define PSPR /* PM Scratch-Pad Reg. */ \ + (*((volatile Word *) io_p2v (_PSPR))) +#define PWER /* PM Wake-up Enable Reg. */ \ + (*((volatile Word *) io_p2v (_PWER))) +#define PCFR /* PM general ConFiguration Reg. */ \ + (*((volatile Word *) io_p2v (_PCFR))) +#define PPCR /* PM PLL Configuration Reg. */ \ + (*((volatile Word *) io_p2v (_PPCR))) +#define PGSR /* PM GPIO Sleep state Reg. */ \ + (*((volatile Word *) io_p2v (_PGSR))) +#define POSR /* PM Oscillator Status Reg. */ \ + (*((volatile Word *) io_p2v (_POSR))) + +#elif LANGUAGE == Assembly +#define PMCR (io_p2v (_PMCR)) +#define PSSR (io_p2v (_PSSR)) +#define PSPR (io_p2v (_PSPR)) +#define PWER (io_p2v (_PWER)) +#define PCFR (io_p2v (_PCFR)) +#define PPCR (io_p2v (_PPCR)) +#define PGSR (io_p2v (_PGSR)) +#define POSR (io_p2v (_POSR)) + +#endif /* LANGUAGE == C */ + +#define PMCR_SF 0x00000001 /* Sleep Force (set only) */ + +#define PSSR_SS 0x00000001 /* Software Sleep */ +#define PSSR_BFS 0x00000002 /* Battery Fault Status */ + /* (BATT_FAULT) */ +#define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */ +#define PSSR_DH 0x00000008 /* DRAM control Hold */ +#define PSSR_PH 0x00000010 /* Peripheral control Hold */ + +#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ +#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ +#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ +#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ +#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ +#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ +#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ +#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ +#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ +#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ +#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ +#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ +#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ +#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ +#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ +#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ +#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ +#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */ +#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */ +#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */ +#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */ +#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */ +#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */ +#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */ +#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */ +#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */ +#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */ +#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */ +#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */ +#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ + +#define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */ +#define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */ +#define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */ +#define PCFR_FP 0x00000002 /* Float PCMCIA pins */ +#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */ +#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */ +#define PCFR_FS 0x00000004 /* Float Static memory pins */ +#define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */ +#define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */ +#define PCFR_FO 0x00000008 /* Force RTC oscillator */ + /* (32.768 kHz) enable On */ + +#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ +#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ + (0x00 << FShft (PPCR_CCF)) +#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ + (0x01 << FShft (PPCR_CCF)) +#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ + (0x02 << FShft (PPCR_CCF)) +#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ + (0x03 << FShft (PPCR_CCF)) +#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ + (0x04 << FShft (PPCR_CCF)) +#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ + (0x05 << FShft (PPCR_CCF)) +#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ + (0x06 << FShft (PPCR_CCF)) +#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ + (0x07 << FShft (PPCR_CCF)) +#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ + (0x08 << FShft (PPCR_CCF)) +#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ + (0x09 << FShft (PPCR_CCF)) +#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ + (0x0A << FShft (PPCR_CCF)) +#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ + (0x0B << FShft (PPCR_CCF)) +#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ + (0x0C << FShft (PPCR_CCF)) +#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ + (0x0D << FShft (PPCR_CCF)) +#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ + (0x0E << FShft (PPCR_CCF)) +#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ + (0x0F << FShft (PPCR_CCF)) + /* 3.6864 MHz crystal (fxtl): */ +#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ +#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ +#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ +#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */ +#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */ +#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */ +#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */ +#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */ +#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */ +#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */ +#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */ +#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */ +#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */ +#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ +#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ +#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ + /* 3.5795 MHz crystal (fxtl): */ +#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ +#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ +#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ +#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */ +#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */ +#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */ +#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */ +#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */ +#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */ +#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */ +#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */ +#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */ +#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */ +#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */ +#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */ +#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */ + +#define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */ + + +/* + * Reset Controller (RC) control registers + * + * Registers + * RSRR Reset Controller (RC) Software Reset Register + * (read/write). + * RCSR Reset Controller (RC) Status Register (read/write). + */ + +#define _RSRR 0x90030000 /* RC Software Reset Reg. */ +#define _RCSR 0x90030004 /* RC Status Reg. */ + +#if LANGUAGE == C +#define RSRR /* RC Software Reset Reg. */ \ + (*((volatile Word *) io_p2v (_RSRR))) +#define RCSR /* RC Status Reg. */ \ + (*((volatile Word *) io_p2v (_RCSR))) +#endif /* LANGUAGE == C */ + +#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ + +#define RCSR_HWR 0x00000001 /* HardWare Reset */ +#define RCSR_SWR 0x00000002 /* SoftWare Reset */ +#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */ +#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */ + + +/* + * Test unit control registers + * + * Registers + * TUCR Test Unit Control Register (read/write). + */ + +#define _TUCR 0x90030008 /* Test Unit Control Reg. */ + +#if LANGUAGE == C +#define TUCR /* Test Unit Control Reg. */ \ + (*((volatile Word *) io_p2v (_TUCR))) +#endif /* LANGUAGE == C */ + +#define TUCR_TIC 0x00000040 /* TIC mode */ +#define TUCR_TTST 0x00000080 /* Trim TeST mode */ +#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ + /* Check */ +#define TUCR_PMD 0x00000200 /* Power Management Disable */ +#define TUCR_MR 0x00000400 /* Memory Request mode */ +#define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */ +#define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */ + /* grant (MBGNT) on GPIO [22:21] */ +#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ +#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ +#define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */ +#define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */ +#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ +#define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */ +#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ + (0 << FShft (TUCR_TSEL)) +#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ + (1 << FShft (TUCR_TSEL)) +#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ + (2 << FShft (TUCR_TSEL)) +#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ + (3 << FShft (TUCR_TSEL)) +#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ + /* Clocks on GPIO [26:27] */ \ + (4 << FShft (TUCR_TSEL)) +#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ + /* (Alternative) */ \ + (5 << FShft (TUCR_TSEL)) +#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ + (6 << FShft (TUCR_TSEL)) +#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ + (7 << FShft (TUCR_TSEL)) + + +/* + * General-Purpose Input/Output (GPIO) control registers + * + * Registers + * GPLR General-Purpose Input/Output (GPIO) Pin Level + * Register (read). + * GPDR General-Purpose Input/Output (GPIO) Pin Direction + * Register (read/write). + * GPSR General-Purpose Input/Output (GPIO) Pin output Set + * Register (write). + * GPCR General-Purpose Input/Output (GPIO) Pin output Clear + * Register (write). + * GRER General-Purpose Input/Output (GPIO) Rising-Edge + * detect Register (read/write). + * GFER General-Purpose Input/Output (GPIO) Falling-Edge + * detect Register (read/write). + * GEDR General-Purpose Input/Output (GPIO) Edge Detect + * status Register (read/write). + * GAFR General-Purpose Input/Output (GPIO) Alternate + * Function Register (read/write). + * + * Clock + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + */ + +#define _GPLR 0x90040000 /* GPIO Pin Level Reg. */ +#define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */ +#define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */ +#define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */ +#define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */ +#define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */ +#define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */ +#define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */ + +#if LANGUAGE == C +#define GPLR /* GPIO Pin Level Reg. */ \ + (*((volatile Word *) io_p2v (_GPLR))) +#define GPDR /* GPIO Pin Direction Reg. */ \ + (*((volatile Word *) io_p2v (_GPDR))) +#define GPSR /* GPIO Pin output Set Reg. */ \ + (*((volatile Word *) io_p2v (_GPSR))) +#define GPCR /* GPIO Pin output Clear Reg. */ \ + (*((volatile Word *) io_p2v (_GPCR))) +#define GRER /* GPIO Rising-Edge detect Reg. */ \ + (*((volatile Word *) io_p2v (_GRER))) +#define GFER /* GPIO Falling-Edge detect Reg. */ \ + (*((volatile Word *) io_p2v (_GFER))) +#define GEDR /* GPIO Edge Detect status Reg. */ \ + (*((volatile Word *) io_p2v (_GEDR))) +#define GAFR /* GPIO Alternate Function Reg. */ \ + (*((volatile Word *) io_p2v (_GAFR))) +#elif LANGUAGE == Assembly + +#define GPLR (io_p2v (_GPLR)) +#define GPDR (io_p2v (_GPDR)) +#define GPSR (io_p2v (_GPSR)) +#define GPCR (io_p2v (_GPCR)) +#define GRER (io_p2v (_GRER)) +#define GFER (io_p2v (_GFER)) +#define GEDR (io_p2v (_GEDR)) +#define GAFR (io_p2v (_GAFR)) + +#endif /* LANGUAGE == C */ + +#define GPIO_MIN (0) +#define GPIO_MAX (27) + +#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ + (0x00000001 << (Nb)) +#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ +#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ +#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ +#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */ +#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */ +#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */ +#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */ +#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */ +#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */ +#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */ +#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */ +#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */ +#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */ +#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */ +#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */ +#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */ +#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */ +#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */ +#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */ +#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */ +#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */ +#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */ +#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */ +#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */ +#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */ +#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */ +#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */ +#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ + +#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ + GPIO_GPIO ((Nb) - 6) +#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ +#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ +#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ +#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */ +#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */ +#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ +#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ +#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ + /* ser. port 4: */ +#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ +#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ +#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ +#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ + /* ser. port 1: */ +#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ +#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ +#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ +#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ +#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ + /* ser. port 4: */ +#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ + /* ser. port 3: */ +#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ + /* ser. port 4: */ +#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ + /* test controller: */ +#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ +#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ +#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ +#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */ +#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */ +#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */ +#define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */ +#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */ + +#define GPDR_In 0 /* Input */ +#define GPDR_Out 1 /* Output */ + + +/* + * Interrupt Controller (IC) control registers + * + * Registers + * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ) + * Pending register (read). + * ICMR Interrupt Controller (IC) Mask Register (read/write). + * ICLR Interrupt Controller (IC) Level Register (read/write). + * ICCR Interrupt Controller (IC) Control Register + * (read/write). + * [The ICCR register is only implemented in versions 2.0 + * (rev. = 8) and higher of the StrongARM SA-1100.] + * ICFP Interrupt Controller (IC) Fast Interrupt reQuest + * (FIQ) Pending register (read). + * ICPR Interrupt Controller (IC) Pending Register (read). + * [The ICPR register is active low (inverted) in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it is active high (non-inverted) in + * versions 2.0 (rev. = 8) and higher.] + */ + +#define _ICIP 0x90050000 /* IC IRQ Pending reg. */ +#define _ICMR 0x90050004 /* IC Mask Reg. */ +#define _ICLR 0x90050008 /* IC Level Reg. */ +#define _ICCR 0x9005000C /* IC Control Reg. */ +#define _ICFP 0x90050010 /* IC FIQ Pending reg. */ +#define _ICPR 0x90050020 /* IC Pending Reg. */ + +#if LANGUAGE == C +#define ICIP /* IC IRQ Pending reg. */ \ + (*((volatile Word *) io_p2v (_ICIP))) +#define ICMR /* IC Mask Reg. */ \ + (*((volatile Word *) io_p2v (_ICMR))) +#define ICLR /* IC Level Reg. */ \ + (*((volatile Word *) io_p2v (_ICLR))) +#define ICCR /* IC Control Reg. */ \ + (*((volatile Word *) io_p2v (_ICCR))) +#define ICFP /* IC FIQ Pending reg. */ \ + (*((volatile Word *) io_p2v (_ICFP))) +#define ICPR /* IC Pending Reg. */ \ + (*((volatile Word *) io_p2v (_ICPR))) +#endif /* LANGUAGE == C */ + +#define IC_GPIO(Nb) /* GPIO [0..10] */ \ + (0x00000001 << (Nb)) +#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ +#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ +#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ +#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */ +#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */ +#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */ +#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */ +#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */ +#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */ +#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */ +#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */ +#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */ +#define IC_LCD 0x00001000 /* LCD controller */ +#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */ +#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */ +#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ +#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */ +#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ +#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ +#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ +#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ + (0x00100000 << (Nb)) +#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ +#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ +#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ +#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */ +#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ +#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ +#define IC_OST(Nb) /* OS Timer match [0..3] */ \ + (0x04000000 << (Nb)) +#define IC_OST0 IC_OST (0) /* OS Timer match 0 */ +#define IC_OST1 IC_OST (1) /* OS Timer match 1 */ +#define IC_OST2 IC_OST (2) /* OS Timer match 2 */ +#define IC_OST3 IC_OST (3) /* OS Timer match 3 */ +#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */ +#define IC_RTCAlrm 0x80000000 /* RTC Alarm */ + +#define ICLR_IRQ 0 /* Interrupt ReQuest */ +#define ICLR_FIQ 1 /* Fast Interrupt reQuest */ + +#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ + /* Mask */ +#define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */ + /* (ICMR ignored) */ +#define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */ + /* enable (ICMR used) */ + + +/* + * Peripheral Pin Controller (PPC) control registers + * + * Registers + * PPDR Peripheral Pin Controller (PPC) Pin Direction + * Register (read/write). + * PPSR Peripheral Pin Controller (PPC) Pin State Register + * (read/write). + * PPAR Peripheral Pin Controller (PPC) Pin Assignment + * Register (read/write). + * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin + * Direction Register (read/write). + * PPFR Peripheral Pin Controller (PPC) Pin Flag Register + * (read). + */ + +#define _PPDR 0x90060000 /* PPC Pin Direction Reg. */ +#define _PPSR 0x90060004 /* PPC Pin State Reg. */ +#define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */ +#define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */ + /* Reg. */ +#define _PPFR 0x90060010 /* PPC Pin Flag Reg. */ + +#if LANGUAGE == C +#define PPDR /* PPC Pin Direction Reg. */ \ + (*((volatile Word *) io_p2v (_PPDR))) +#define PPSR /* PPC Pin State Reg. */ \ + (*((volatile Word *) io_p2v (_PPSR))) +#define PPAR /* PPC Pin Assignment Reg. */ \ + (*((volatile Word *) io_p2v (_PPAR))) +#define PSDR /* PPC Sleep-mode pin Direction */ \ + /* Reg. */ \ + (*((volatile Word *) io_p2v (_PSDR))) +#define PPFR /* PPC Pin Flag Reg. */ \ + (*((volatile Word *) io_p2v (_PPFR))) +#endif /* LANGUAGE == C */ + +#define PPC_LDD(Nb) /* LCD Data [0..7] */ \ + (0x00000001 << (Nb)) +#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ +#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ +#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ +#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */ +#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */ +#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */ +#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */ +#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */ +#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */ +#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ +#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ +#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ + /* ser. port 1: */ +#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ +#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ + /* ser. port 2: */ +#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ +#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ + /* ser. port 3: */ +#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ +#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ + /* ser. port 4: */ +#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ +#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ +#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ +#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */ + +#define PPDR_In 0 /* Input */ +#define PPDR_Out 1 /* Output */ + + /* ser. port 1: */ +#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ +#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ +#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ + /* ser. port 4: */ +#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ +#define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */ + /* & SFRM_C */ +#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ + +#define PSDR_OutL 0 /* Output Low in sleep mode */ +#define PSDR_Flt 1 /* Floating (input) in sleep mode */ + +#define PPFR_LCD 0x00000001 /* LCD controller */ +#define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */ +#define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */ +#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */ +#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */ +#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ +#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */ +#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */ +#define PPFR_PerEn 0 /* Peripheral Enabled */ +#define PPFR_PPCEn 1 /* PPC Enabled */ + + +/* + * Dynamic Random-Access Memory (DRAM) control registers + * + * Registers + * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM) + * CoNFiGuration register (read/write). + * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM) + * Column Address Strobe (CAS) shift register 0 + * (read/write). + * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM) + * Column Address Strobe (CAS) shift register 1 + * (read/write). + * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM) + * Column Address Strobe (CAS) shift register 2 + * (read/write). + * + * Clocks + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). + * fcas, Tcas Frequency, period of the DRAM CAS shift registers. + */ + + /* Memory system: */ +#define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */ +#define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \ + (0xA0000004 + (Nb)*4) +#define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */ +#define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */ +#define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */ + +#if LANGUAGE == C + /* Memory system: */ +#define MDCNFG /* DRAM CoNFiGuration reg. */ \ + (*((volatile Word *) io_p2v (_MDCNFG))) +#define MDCAS /* DRAM CAS shift reg. [0..3] */ \ + ((volatile Word *) io_p2v (_MDCAS (0))) +#define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */ +#define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */ +#define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */ + +#elif LANGUAGE == Assembly + +#define MDCNFG (io_p2v(_MDCNFG)) + +#endif /* LANGUAGE == C */ + +/* SA1100 MDCNFG values */ +#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ + (0x00000001 << (Nb)) +#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ +#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ +#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ +#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ +#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ +#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ + (((Add) - 9) << FShft (MDCNFG_DRAC)) +#define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */ + /* (fcas = fcpu/2) */ +#define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */ +#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ + (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP)) +#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ + (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP)) +#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ +#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ + (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR)) +#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ + (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR)) +#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ +#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ + ((Tcpu) << FShft (MDCNFG_TDL)) +#define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */ + /* [Tmem] */ +#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ + /* [0..262136 Tcpu] */ \ + ((Tcpu)/8 << FShft (MDCNFG_DRI)) + +/* SA1110 MDCNFG values */ +#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ +#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */ +#define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */ +#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ +#define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */ + /* bank 0/1 */ +#define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */ +#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ +#define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/ + /* deassertion 0/1 */ +#define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */ +#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ +#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ +#define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */ +#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ +#define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */ + /* bank 0/1 */ +#define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */ +#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ +#define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/ + /* deassertion 0/1 */ +#define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */ + + +/* + * Static memory control registers + * + * Registers + * MSC0 Memory system: Static memory Control register 0 + * (read/write). + * MSC1 Memory system: Static memory Control register 1 + * (read/write). + * + * Clocks + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). + */ + + /* Memory system: */ +#define _MSC(Nb) /* Static memory Control reg. */ \ + /* [0..1] */ \ + (0xA0000010 + (Nb)*4) +#define _MSC0 _MSC (0) /* Static memory Control reg. 0 */ +#define _MSC1 _MSC (1) /* Static memory Control reg. 1 */ +#define _MSC2 0xA000002C /* Static memory Control reg. 2, not contiguous */ + +#if LANGUAGE == C + /* Memory system: */ +#define MSC /* Static memory Control reg. */ \ + /* [0..1] */ \ + ((volatile Word *) io_p2v (_MSC (0))) +#define MSC0 (MSC [0]) /* Static memory Control reg. 0 */ +#define MSC1 (MSC [1]) /* Static memory Control reg. 1 */ +#define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */ + +#elif LANGUAGE == Assembly + +#define MSC0 io_p2v(0xa0000010) +#define MSC1 io_p2v(0xa0000014) +#define MSC2 io_p2v(0xa000002c) + +#endif /* LANGUAGE == C */ + +#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ + Fld (16, ((Nb) Modulo 2)*16) +#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ +#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ +#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ +#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */ + +#define MSC_RT Fld (2, 0) /* ROM/static memory Type */ +#define MSC_NonBrst /* Non-Burst static memory */ \ + (0 << FShft (MSC_RT)) +#define MSC_SRAM /* 32-bit byte-writable SRAM */ \ + (1 << FShft (MSC_RT)) +#define MSC_Brst4 /* Burst-of-4 static memory */ \ + (2 << FShft (MSC_RT)) +#define MSC_Brst8 /* Burst-of-8 static memory */ \ + (3 << FShft (MSC_RT)) +#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ +#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ +#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ +#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ + /* First access - 1(.5) [Tmem] */ +#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ + /* static memory) [3..65 Tcpu] */ \ + ((((Tcpu) - 3)/2) << FShft (MSC_RDF)) +#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) +#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ + /* static memory) [2..64 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) +#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ + ((((Tcpu) - 1)/2) << FShft (MSC_RDF)) +#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ + /* Next access - 1 [Tmem] */ +#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ + /* static memory) [2..64 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) +#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ + ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) +#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ + /* static memory) [2..64 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) +#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ + ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) +#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ + /* time/2 [Tmem] */ +#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ + (((Tcpu)/4) << FShft (MSC_RRR)) +#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ + ((((Tcpu) + 3)/4) << FShft (MSC_RRR)) + + +/* + * Personal Computer Memory Card International Association (PCMCIA) control + * register + * + * Register + * MECR Memory system: Expansion memory bus (PCMCIA) + * Configuration Register (read/write). + * + * Clocks + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). + * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK). + */ + + /* Memory system: */ +#define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */ + /* Configuration Reg. */ + +#if LANGUAGE == C + /* Memory system: */ +#define MECR /* Expansion memory bus (PCMCIA) */ \ + /* Configuration Reg. */ \ + (*((volatile Word *) io_p2v (_MECR))) +#endif /* LANGUAGE == C */ + +#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ + Fld (15, (Nb)*16) +#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ +#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ + +#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ +#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MECR_BSIO)) +#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ + ((((Tcpu) - 1)/2) << FShft (MECR_BSIO)) +#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ + /* [Tmem] */ +#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MECR_BSA)) +#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ + ((((Tcpu) - 1)/2) << FShft (MECR_BSA)) +#define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */ +#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MECR_BSM)) +#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ + ((((Tcpu) - 1)/2) << FShft (MECR_BSM)) + +/* + * On SA1110 only + */ + +#define _MDREFR 0xA000001C + +#if LANGUAGE == C + /* Memory system: */ +#define MDREFR \ + (*((volatile Word *) io_p2v (_MDREFR))) + +#elif LANGUAGE == Assembly + +#define MDREFR (io_p2v(_MDREFR)) + +#endif /* LANGUAGE == C */ + +#define MDREFR_TRASR Fld (4, 0) +#define MDREFR_DRI Fld (12, 4) +#define MDREFR_E0PIN (1 << 16) +#define MDREFR_K0RUN (1 << 17) +#define MDREFR_K0DB2 (1 << 18) +#define MDREFR_E1PIN (1 << 20) +#define MDREFR_K1RUN (1 << 21) +#define MDREFR_K1DB2 (1 << 22) +#define MDREFR_K2RUN (1 << 25) +#define MDREFR_K2DB2 (1 << 26) +#define MDREFR_EAPD (1 << 28) +#define MDREFR_KAPD (1 << 29) +#define MDREFR_SLFRSH (1 << 31) + + +/* + * Direct Memory Access (DMA) control registers + * + * Registers + * DDAR0 Direct Memory Access (DMA) Device Address Register + * channel 0 (read/write). + * DCSR0 Direct Memory Access (DMA) Control and Status + * Register channel 0 (read/write). + * DBSA0 Direct Memory Access (DMA) Buffer Start address + * register A channel 0 (read/write). + * DBTA0 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 0 (read/write). + * DBSB0 Direct Memory Access (DMA) Buffer Start address + * register B channel 0 (read/write). + * DBTB0 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 0 (read/write). + * + * DDAR1 Direct Memory Access (DMA) Device Address Register + * channel 1 (read/write). + * DCSR1 Direct Memory Access (DMA) Control and Status + * Register channel 1 (read/write). + * DBSA1 Direct Memory Access (DMA) Buffer Start address + * register A channel 1 (read/write). + * DBTA1 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 1 (read/write). + * DBSB1 Direct Memory Access (DMA) Buffer Start address + * register B channel 1 (read/write). + * DBTB1 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 1 (read/write). + * + * DDAR2 Direct Memory Access (DMA) Device Address Register + * channel 2 (read/write). + * DCSR2 Direct Memory Access (DMA) Control and Status + * Register channel 2 (read/write). + * DBSA2 Direct Memory Access (DMA) Buffer Start address + * register A channel 2 (read/write). + * DBTA2 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 2 (read/write). + * DBSB2 Direct Memory Access (DMA) Buffer Start address + * register B channel 2 (read/write). + * DBTB2 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 2 (read/write). + * + * DDAR3 Direct Memory Access (DMA) Device Address Register + * channel 3 (read/write). + * DCSR3 Direct Memory Access (DMA) Control and Status + * Register channel 3 (read/write). + * DBSA3 Direct Memory Access (DMA) Buffer Start address + * register A channel 3 (read/write). + * DBTA3 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 3 (read/write). + * DBSB3 Direct Memory Access (DMA) Buffer Start address + * register B channel 3 (read/write). + * DBTB3 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 3 (read/write). + * + * DDAR4 Direct Memory Access (DMA) Device Address Register + * channel 4 (read/write). + * DCSR4 Direct Memory Access (DMA) Control and Status + * Register channel 4 (read/write). + * DBSA4 Direct Memory Access (DMA) Buffer Start address + * register A channel 4 (read/write). + * DBTA4 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 4 (read/write). + * DBSB4 Direct Memory Access (DMA) Buffer Start address + * register B channel 4 (read/write). + * DBTB4 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 4 (read/write). + * + * DDAR5 Direct Memory Access (DMA) Device Address Register + * channel 5 (read/write). + * DCSR5 Direct Memory Access (DMA) Control and Status + * Register channel 5 (read/write). + * DBSA5 Direct Memory Access (DMA) Buffer Start address + * register A channel 5 (read/write). + * DBTA5 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 5 (read/write). + * DBSB5 Direct Memory Access (DMA) Buffer Start address + * register B channel 5 (read/write). + * DBTB5 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 5 (read/write). + */ + +#define DMASp 0x00000020 /* DMA control reg. Space [byte] */ + +#define _DDAR(Nb) /* DMA Device Address Reg. */ \ + /* channel [0..5] */ \ + (0xB0000000 + (Nb)*DMASp) +#define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \ + /* channel [0..5] (write) */ \ + (0xB0000004 + (Nb)*DMASp) +#define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \ + /* channel [0..5] (write) */ \ + (0xB0000008 + (Nb)*DMASp) +#define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \ + /* channel [0..5] (read) */ \ + (0xB000000C + (Nb)*DMASp) +#define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \ + /* channel [0..5] */ \ + (0xB0000010 + (Nb)*DMASp) +#define _DBTA(Nb) /* DMA Buffer Transfer count */ \ + /* reg. A channel [0..5] */ \ + (0xB0000014 + (Nb)*DMASp) +#define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \ + /* channel [0..5] */ \ + (0xB0000018 + (Nb)*DMASp) +#define _DBTB(Nb) /* DMA Buffer Transfer count */ \ + /* reg. B channel [0..5] */ \ + (0xB000001C + (Nb)*DMASp) + +#define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */ + /* channel 0 */ +#define _SetDCSR0 _SetDCSR (0) /* Set DMA Control & Status Reg. */ + /* channel 0 (write) */ +#define _ClrDCSR0 _ClrDCSR (0) /* Clear DMA Control & Status Reg. */ + /* channel 0 (write) */ +#define _RdDCSR0 _RdDCSR (0) /* Read DMA Control & Status Reg. */ + /* channel 0 (read) */ +#define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */ + /* channel 0 */ +#define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */ + /* reg. A channel 0 */ +#define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */ + /* channel 0 */ +#define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */ + /* reg. B channel 0 */ + +#define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */ + /* channel 1 */ +#define _SetDCSR1 _SetDCSR (1) /* Set DMA Control & Status Reg. */ + /* channel 1 (write) */ +#define _ClrDCSR1 _ClrDCSR (1) /* Clear DMA Control & Status Reg. */ + /* channel 1 (write) */ +#define _RdDCSR1 _RdDCSR (1) /* Read DMA Control & Status Reg. */ + /* channel 1 (read) */ +#define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */ + /* channel 1 */ +#define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */ + /* reg. A channel 1 */ +#define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */ + /* channel 1 */ +#define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */ + /* reg. B channel 1 */ + +#define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */ + /* channel 2 */ +#define _SetDCSR2 _SetDCSR (2) /* Set DMA Control & Status Reg. */ + /* channel 2 (write) */ +#define _ClrDCSR2 _ClrDCSR (2) /* Clear DMA Control & Status Reg. */ + /* channel 2 (write) */ +#define _RdDCSR2 _RdDCSR (2) /* Read DMA Control & Status Reg. */ + /* channel 2 (read) */ +#define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */ + /* channel 2 */ +#define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */ + /* reg. A channel 2 */ +#define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */ + /* channel 2 */ +#define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */ + /* reg. B channel 2 */ + +#define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */ + /* channel 3 */ +#define _SetDCSR3 _SetDCSR (3) /* Set DMA Control & Status Reg. */ + /* channel 3 (write) */ +#define _ClrDCSR3 _ClrDCSR (3) /* Clear DMA Control & Status Reg. */ + /* channel 3 (write) */ +#define _RdDCSR3 _RdDCSR (3) /* Read DMA Control & Status Reg. */ + /* channel 3 (read) */ +#define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */ + /* channel 3 */ +#define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */ + /* reg. A channel 3 */ +#define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */ + /* channel 3 */ +#define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */ + /* reg. B channel 3 */ + +#define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */ + /* channel 4 */ +#define _SetDCSR4 _SetDCSR (4) /* Set DMA Control & Status Reg. */ + /* channel 4 (write) */ +#define _ClrDCSR4 _ClrDCSR (4) /* Clear DMA Control & Status Reg. */ + /* channel 4 (write) */ +#define _RdDCSR4 _RdDCSR (4) /* Read DMA Control & Status Reg. */ + /* channel 4 (read) */ +#define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */ + /* channel 4 */ +#define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */ + /* reg. A channel 4 */ +#define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */ + /* channel 4 */ +#define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */ + /* reg. B channel 4 */ + +#define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */ + /* channel 5 */ +#define _SetDCSR5 _SetDCSR (5) /* Set DMA Control & Status Reg. */ + /* channel 5 (write) */ +#define _ClrDCSR5 _ClrDCSR (5) /* Clear DMA Control & Status Reg. */ + /* channel 5 (write) */ +#define _RdDCSR5 _RdDCSR (5) /* Read DMA Control & Status Reg. */ + /* channel 5 (read) */ +#define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */ + /* channel 5 */ +#define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */ + /* reg. A channel 5 */ +#define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */ + /* channel 5 */ +#define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */ + /* reg. B channel 5 */ + +#if LANGUAGE == C + +#define DDAR0 /* DMA Device Address Reg. */ \ + /* channel 0 */ \ + (*((volatile Word *) io_p2v (_DDAR0))) +#define SetDCSR0 /* Set DMA Control & Status Reg. */ \ + /* channel 0 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR0))) +#define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \ + /* channel 0 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR0))) +#define RdDCSR0 /* Read DMA Control & Status Reg. */ \ + /* channel 0 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR0))) +#define DBSA0 /* DMA Buffer Start address reg. A */ \ + /* channel 0 */ \ + (*((volatile Address *) io_p2v (_DBSA0))) +#define DBTA0 /* DMA Buffer Transfer count */ \ + /* reg. A channel 0 */ \ + (*((volatile Word *) io_p2v (_DBTA0))) +#define DBSB0 /* DMA Buffer Start address reg. B */ \ + /* channel 0 */ \ + (*((volatile Address *) io_p2v (_DBSB0))) +#define DBTB0 /* DMA Buffer Transfer count */ \ + /* reg. B channel 0 */ \ + (*((volatile Word *) io_p2v (_DBTB0))) + +#define DDAR1 /* DMA Device Address Reg. */ \ + /* channel 1 */ \ + (*((volatile Word *) io_p2v (_DDAR1))) +#define SetDCSR1 /* Set DMA Control & Status Reg. */ \ + /* channel 1 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR1))) +#define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \ + /* channel 1 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR1))) +#define RdDCSR1 /* Read DMA Control & Status Reg. */ \ + /* channel 1 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR1))) +#define DBSA1 /* DMA Buffer Start address reg. A */ \ + /* channel 1 */ \ + (*((volatile Address *) io_p2v (_DBSA1))) +#define DBTA1 /* DMA Buffer Transfer count */ \ + /* reg. A channel 1 */ \ + (*((volatile Word *) io_p2v (_DBTA1))) +#define DBSB1 /* DMA Buffer Start address reg. B */ \ + /* channel 1 */ \ + (*((volatile Address *) io_p2v (_DBSB1))) +#define DBTB1 /* DMA Buffer Transfer count */ \ + /* reg. B channel 1 */ \ + (*((volatile Word *) io_p2v (_DBTB1))) + +#define DDAR2 /* DMA Device Address Reg. */ \ + /* channel 2 */ \ + (*((volatile Word *) io_p2v (_DDAR2))) +#define SetDCSR2 /* Set DMA Control & Status Reg. */ \ + /* channel 2 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR2))) +#define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \ + /* channel 2 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR2))) +#define RdDCSR2 /* Read DMA Control & Status Reg. */ \ + /* channel 2 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR2))) +#define DBSA2 /* DMA Buffer Start address reg. A */ \ + /* channel 2 */ \ + (*((volatile Address *) io_p2v (_DBSA2))) +#define DBTA2 /* DMA Buffer Transfer count */ \ + /* reg. A channel 2 */ \ + (*((volatile Word *) io_p2v (_DBTA2))) +#define DBSB2 /* DMA Buffer Start address reg. B */ \ + /* channel 2 */ \ + (*((volatile Address *) io_p2v (_DBSB2))) +#define DBTB2 /* DMA Buffer Transfer count */ \ + /* reg. B channel 2 */ \ + (*((volatile Word *) io_p2v (_DBTB2))) + +#define DDAR3 /* DMA Device Address Reg. */ \ + /* channel 3 */ \ + (*((volatile Word *) io_p2v (_DDAR3))) +#define SetDCSR3 /* Set DMA Control & Status Reg. */ \ + /* channel 3 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR3))) +#define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \ + /* channel 3 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR3))) +#define RdDCSR3 /* Read DMA Control & Status Reg. */ \ + /* channel 3 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR3))) +#define DBSA3 /* DMA Buffer Start address reg. A */ \ + /* channel 3 */ \ + (*((volatile Address *) io_p2v (_DBSA3))) +#define DBTA3 /* DMA Buffer Transfer count */ \ + /* reg. A channel 3 */ \ + (*((volatile Word *) io_p2v (_DBTA3))) +#define DBSB3 /* DMA Buffer Start address reg. B */ \ + /* channel 3 */ \ + (*((volatile Address *) io_p2v (_DBSB3))) +#define DBTB3 /* DMA Buffer Transfer count */ \ + /* reg. B channel 3 */ \ + (*((volatile Word *) io_p2v (_DBTB3))) + +#define DDAR4 /* DMA Device Address Reg. */ \ + /* channel 4 */ \ + (*((volatile Word *) io_p2v (_DDAR4))) +#define SetDCSR4 /* Set DMA Control & Status Reg. */ \ + /* channel 4 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR4))) +#define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \ + /* channel 4 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR4))) +#define RdDCSR4 /* Read DMA Control & Status Reg. */ \ + /* channel 4 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR4))) +#define DBSA4 /* DMA Buffer Start address reg. A */ \ + /* channel 4 */ \ + (*((volatile Address *) io_p2v (_DBSA4))) +#define DBTA4 /* DMA Buffer Transfer count */ \ + /* reg. A channel 4 */ \ + (*((volatile Word *) io_p2v (_DBTA4))) +#define DBSB4 /* DMA Buffer Start address reg. B */ \ + /* channel 4 */ \ + (*((volatile Address *) io_p2v (_DBSB4))) +#define DBTB4 /* DMA Buffer Transfer count */ \ + /* reg. B channel 4 */ \ + (*((volatile Word *) io_p2v (_DBTB4))) + +#define DDAR5 /* DMA Device Address Reg. */ \ + /* channel 5 */ \ + (*((volatile Word *) io_p2v (_DDAR5))) +#define SetDCSR5 /* Set DMA Control & Status Reg. */ \ + /* channel 5 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR5))) +#define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \ + /* channel 5 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR5))) +#define RdDCSR5 /* Read DMA Control & Status Reg. */ \ + /* channel 5 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR5))) +#define DBSA5 /* DMA Buffer Start address reg. A */ \ + /* channel 5 */ \ + (*((volatile Address *) io_p2v (_DBSA5))) +#define DBTA5 /* DMA Buffer Transfer count */ \ + /* reg. A channel 5 */ \ + (*((volatile Word *) io_p2v (_DBTA5))) +#define DBSB5 /* DMA Buffer Start address reg. B */ \ + /* channel 5 */ \ + (*((volatile Address *) io_p2v (_DBSB5))) +#define DBTB5 /* DMA Buffer Transfer count */ \ + /* reg. B channel 5 */ \ + (*((volatile Word *) io_p2v (_DBTB5))) + +#endif /* LANGUAGE == C */ + +#define DDAR_RW 0x00000001 /* device data Read/Write */ +#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */ + /* (memory -> device) */ +#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */ + /* (device -> memory) */ +#define DDAR_E 0x00000002 /* big/little Endian device */ +#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */ +#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */ +#define DDAR_BS 0x00000004 /* device Burst Size */ +#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */ +#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */ +#define DDAR_DW 0x00000008 /* device Data Width */ +#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */ +#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */ +#define DDAR_DS Fld (4, 4) /* Device Select */ +#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \ + (0x0 << FShft (DDAR_DS)) +#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \ + (0x1 << FShft (DDAR_DS)) +#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \ + (0x2 << FShft (DDAR_DS)) +#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \ + (0x3 << FShft (DDAR_DS)) +#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \ + (0x4 << FShft (DDAR_DS)) +#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \ + (0x5 << FShft (DDAR_DS)) +#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \ + (0x6 << FShft (DDAR_DS)) +#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \ + (0x7 << FShft (DDAR_DS)) +#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \ + (0x8 << FShft (DDAR_DS)) +#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \ + (0x9 << FShft (DDAR_DS)) +#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \ + /* (audio) */ \ + (0xA << FShft (DDAR_DS)) +#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \ + /* (audio) */ \ + (0xB << FShft (DDAR_DS)) +#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \ + /* (telecom) */ \ + (0xC << FShft (DDAR_DS)) +#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \ + /* (telecom) */ \ + (0xD << FShft (DDAR_DS)) +#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \ + (0xE << FShft (DDAR_DS)) +#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \ + (0xF << FShft (DDAR_DS)) +#define DDAR_DA Fld (24, 8) /* Device Address */ +#define DDAR_DevAdd(Add) /* Device Address */ \ + (((Add) & 0xF0000000) | \ + (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2))) +#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \ + (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ + DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR)) +#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \ + (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ + DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR)) +#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR)) +#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR)) +#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR)) +#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR)) +#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR)) +#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR)) +#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \ + (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ + DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR)) +#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \ + (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ + DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR)) +#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR)) +#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR)) +#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0)) +#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0)) +#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \ + /* (telecom) */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1)) +#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \ + /* (telecom) */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1)) +#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR)) +#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR)) + +#define DCSR_RUN 0x00000001 /* DMA RUNing */ +#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ +#define DCSR_ERROR 0x00000004 /* DMA ERROR */ +#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ +#define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */ +#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */ +#define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */ +#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */ +#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */ +#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */ + +#define DBT_TC Fld (13, 0) /* Transfer Count */ +#define DBTA_TCA DBT_TC /* Transfer Count buffer A */ +#define DBTB_TCB DBT_TC /* Transfer Count buffer B */ + + +/* + * Liquid Crystal Display (LCD) control registers + * + * Registers + * LCCR0 Liquid Crystal Display (LCD) Control Register 0 + * (read/write). + * [Bits LDM, BAM, and ERM are only implemented in + * versions 2.0 (rev. = 8) and higher of the StrongARM + * SA-1100.] + * LCSR Liquid Crystal Display (LCD) Status Register + * (read/write). + * [Bit LDD can be only read in versions 1.0 (rev. = 1) + * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be + * read and written (cleared) in versions 2.0 (rev. = 8) + * and higher.] + * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Base Address Register channel 1 (read/write). + * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Current Address Register channel 1 (read). + * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Base Address Register channel 2 (read/write). + * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Current Address Register channel 2 (read). + * LCCR1 Liquid Crystal Display (LCD) Control Register 1 + * (read/write). + * [The LCCR1 register can be only written in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it can be written and read in + * versions 2.0 (rev. = 8) and higher.] + * LCCR2 Liquid Crystal Display (LCD) Control Register 2 + * (read/write). + * [The LCCR1 register can be only written in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it can be written and read in + * versions 2.0 (rev. = 8) and higher.] + * LCCR3 Liquid Crystal Display (LCD) Control Register 3 + * (read/write). + * [The LCCR1 register can be only written in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it can be written and read in + * versions 2.0 (rev. = 8) and higher. Bit PCP is only + * implemented in versions 2.0 (rev. = 8) and higher of + * the StrongARM SA-1100.] + * + * Clocks + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). + * fpix, Tpix Frequency, period of the pixel clock. + * fln, Tln Frequency, period of the line clock. + * fac, Tac Frequency, period of the AC bias clock. + */ + +#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ +#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ + /* [byte] */ \ + (16*LCD_PEntrySp) +#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ + /* [byte] */ \ + (256*LCD_PEntrySp) +#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ + /* dummy-Palette Space [byte] */ \ + (16*LCD_PEntrySp) + +#define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */ +#define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */ +#define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */ +#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ +#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ +#define LCD_4Bit /* LCD 4-Bit pixel mode */ \ + (0 << FShft (LCD_PBS)) +#define LCD_8Bit /* LCD 8-Bit pixel mode */ \ + (1 << FShft (LCD_PBS)) +#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ + (2 << FShft (LCD_PBS)) + +#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ +#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ +#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */ +#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */ +#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */ +#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */ +#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */ +#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */ +#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */ +#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */ +#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */ +#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */ +#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */ +#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ +#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ +#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ + /* (Alternative) */ + +#define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */ +#define _LCSR 0xB0100004 /* LCD Status Reg. */ +#define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */ + /* channel 1 */ +#define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */ + /* channel 1 */ +#define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */ + /* channel 2 */ +#define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */ + /* channel 2 */ +#define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */ +#define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */ +#define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */ + +#if LANGUAGE == C +#define LCCR0 /* LCD Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_LCCR0))) +#define LCSR /* LCD Status Reg. */ \ + (*((volatile Word *) io_p2v (_LCSR))) +#define DBAR1 /* LCD DMA Base Address Reg. */ \ + /* channel 1 */ \ + (*((volatile Address *) io_p2v (_DBAR1))) +#define DCAR1 /* LCD DMA Current Address Reg. */ \ + /* channel 1 */ \ + (*((volatile Address *) io_p2v (_DCAR1))) +#define DBAR2 /* LCD DMA Base Address Reg. */ \ + /* channel 2 */ \ + (*((volatile Address *) io_p2v (_DBAR2))) +#define DCAR2 /* LCD DMA Current Address Reg. */ \ + /* channel 2 */ \ + (*((volatile Address *) io_p2v (_DCAR2))) +#define LCCR1 /* LCD Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_LCCR1))) +#define LCCR2 /* LCD Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_LCCR2))) +#define LCCR3 /* LCD Control Reg. 3 */ \ + (*((volatile Word *) io_p2v (_LCCR3))) +#endif /* LANGUAGE == C */ + +#define LCCR0_LEN 0x00000001 /* LCD ENable */ +#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ +#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ +#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ +#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ + /* Select */ +#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ +#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ +#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ + /* interrupt Mask (disable) */ +#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ + /* interrupt Mask (disable) */ +#define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */ + /* IUU, OOL, OUL, OOU, and OUU) */ + /* interrupt Mask (disable) */ +#define LCCR0_PAS 0x00000080 /* Passive/Active display Select */ +#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ +#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ +#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */ +#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ +#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ +#define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */ + /* display mode) */ +#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ + /* display */ +#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ + /* display */ +#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ + /* [Tmem] */ +#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ + /* [0..510 Tcpu] */ \ + ((Tcpu)/2 << FShft (LCCR0_PDD)) + +#define LCSR_LDD 0x00000001 /* LCD Disable Done */ +#define LCSR_BAU 0x00000002 /* Base Address Update (read) */ +#define LCSR_BER 0x00000004 /* Bus ERror */ +#define LCSR_ABC 0x00000008 /* AC Bias clock Count */ +#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ + /* panel */ +#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ + /* panel */ +#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ + /* panel */ +#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ + /* panel */ +#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ + /* panel */ +#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ + /* panel */ +#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ + /* panel */ +#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ + /* panel */ + +#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ +#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ + (((Pixel) - 16)/16 << FShft (LCCR1_PPL)) +#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ + /* pulse Width - 2 [Tpix] (L_LCLK) */ +#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ + /* pulse Width [2..65 Tpix] */ \ + (((Tpix) - 2) << FShft (LCCR1_HSW)) +#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ + /* count - 1 [Tpix] */ +#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ + /* [1..256 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_ELW)) +#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ + /* Wait count - 1 [Tpix] */ +#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ + /* [1..256 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_BLW)) + +#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ +#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ + (((Line) - 1) << FShft (LCCR2_LPP)) +#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ + /* Width - 1 [Tln] (L_FCLK) */ +#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ + /* Width [1..64 Tln] */ \ + (((Tln) - 1) << FShft (LCCR2_VSW)) +#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ + /* count [Tln] */ +#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ + /* [0..255 Tln] */ \ + ((Tln) << FShft (LCCR2_EFW)) +#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ + /* Wait count [Tln] */ +#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ + /* [0..255 Tln] */ \ + ((Tln) << FShft (LCCR2_BFW)) + +#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ + /* [1..255] (L_PCLK) */ + /* fpix = fcpu/(2*(PCD + 2)) */ + /* Tpix = 2*(PCD + 2)*Tcpu */ +#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ + (((Div) - 4)/2 << FShft (LCCR3_PCD)) + /* fpix = fcpu/(2*Floor (Div/2)) */ + /* Tpix = 2*Floor (Div/2)*Tcpu */ +#define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \ + (((Div) - 3)/2 << FShft (LCCR3_PCD)) + /* fpix = fcpu/(2*Ceil (Div/2)) */ + /* Tpix = 2*Ceil (Div/2)*Tcpu */ +#define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */ + /* [Tln] (L_BIAS) */ +#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ + (((Div) - 2)/2 << FShft (LCCR3_ACB)) + /* fac = fln/(2*Floor (Div/2)) */ + /* Tac = 2*Floor (Div/2)*Tln */ +#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ + (((Div) - 1)/2 << FShft (LCCR3_ACB)) + /* fac = fln/(2*Ceil (Div/2)) */ + /* Tac = 2*Ceil (Div/2)*Tln */ +#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ + /* Interrupt */ +#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ + /* Off */ \ + (0 << FShft (LCCR3_API)) +#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ + /* [1..15] */ \ + ((Trans) << FShft (LCCR3_API)) +#define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ + /* Polarity (L_FCLK) */ +#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ + /* active High */ +#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ + /* active Low */ +#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ + /* pulse Polarity (L_LCLK) */ +#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ + /* pulse active High */ +#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ + /* pulse active Low */ +#define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */ +#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ +#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ +#define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */ + /* active display mode) */ +#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ +#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ + + +#undef C +#undef Assembly diff --git a/roms/u-boot/include/_exports.h b/roms/u-boot/include/_exports.h new file mode 100644 index 000000000..8030d70c0 --- /dev/null +++ b/roms/u-boot/include/_exports.h @@ -0,0 +1,86 @@ +/* + * You need to use #ifdef around functions that may not exist + * in the final configuration (such as i2c). + * use a dummyfunction as first parameter to EXPORT_FUNC. + * As an example see the CONFIG_CMD_I2C section below + */ +#ifndef EXPORT_FUNC +#define EXPORT_FUNC(a, b, c, ...) +#endif + EXPORT_FUNC(get_version, unsigned long, get_version, void) + EXPORT_FUNC(getchar, int, getc, void) + EXPORT_FUNC(tstc, int, tstc, void) + EXPORT_FUNC(putc, void, putc, const char) + EXPORT_FUNC(puts, void, puts, const char *) + EXPORT_FUNC(printf, int, printf, const char*, ...) +#if (defined(CONFIG_X86) && !defined(CONFIG_X86_64)) || defined(CONFIG_PPC) + EXPORT_FUNC(irq_install_handler, void, install_hdlr, + int, interrupt_handler_t, void*) + + EXPORT_FUNC(irq_free_handler, void, free_hdlr, int) +#else + EXPORT_FUNC(dummy, void, install_hdlr, void) + EXPORT_FUNC(dummy, void, free_hdlr, void) +#endif + EXPORT_FUNC(malloc, void *, malloc, size_t) +#if !CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) + EXPORT_FUNC(free, void, free, void *) +#endif + EXPORT_FUNC(udelay, void, udelay, unsigned long) + EXPORT_FUNC(get_timer, unsigned long, get_timer, unsigned long) + EXPORT_FUNC(vprintf, int, vprintf, const char *, va_list) + EXPORT_FUNC(do_reset, int, do_reset, struct cmd_tbl *, + int , int , char * const []) + EXPORT_FUNC(env_get, char *, env_get, const char*) + EXPORT_FUNC(env_set, int, env_set, const char *, const char *) + EXPORT_FUNC(simple_strtoul, unsigned long, simple_strtoul, + const char *, char **, unsigned int) + EXPORT_FUNC(strict_strtoul, int, strict_strtoul, + const char *, unsigned int , unsigned long *) + EXPORT_FUNC(simple_strtol, long, simple_strtol, + const char *, char **, unsigned int) + EXPORT_FUNC(strcmp, int, strcmp, const char *cs, const char *ct) +#if defined(CONFIG_CMD_I2C) && !CONFIG_IS_ENABLED(DM_I2C) + EXPORT_FUNC(i2c_write, int, i2c_write, uchar, uint, int , uchar * , int) + EXPORT_FUNC(i2c_read, int, i2c_read, uchar, uint, int , uchar * , int) +#else + EXPORT_FUNC(dummy, void, i2c_write, void) + EXPORT_FUNC(dummy, void, i2c_read, void) +#endif + +#if !defined(CONFIG_CMD_SPI) || defined(CONFIG_DM_SPI) + EXPORT_FUNC(dummy, void, spi_setup_slave, void) + EXPORT_FUNC(dummy, void, spi_free_slave, void) +#else + EXPORT_FUNC(spi_setup_slave, struct spi_slave *, spi_setup_slave, + unsigned int, unsigned int, unsigned int, unsigned int) + EXPORT_FUNC(spi_free_slave, void, spi_free_slave, struct spi_slave *) +#endif +#ifndef CONFIG_CMD_SPI + EXPORT_FUNC(dummy, void, spi_claim_bus, void) + EXPORT_FUNC(dummy, void, spi_release_bus, void) + EXPORT_FUNC(dummy, void, spi_xfer, void) +#else + EXPORT_FUNC(spi_claim_bus, int, spi_claim_bus, struct spi_slave *) + EXPORT_FUNC(spi_release_bus, void, spi_release_bus, struct spi_slave *) + EXPORT_FUNC(spi_xfer, int, spi_xfer, struct spi_slave *, + unsigned int, const void *, void *, unsigned long) +#endif + EXPORT_FUNC(ustrtoul, unsigned long, ustrtoul, + const char *, char **, unsigned int) + EXPORT_FUNC(ustrtoull, unsigned long long, ustrtoull, + const char *, char **, unsigned int) + EXPORT_FUNC(strcpy, char *, strcpy, char *dest, const char *src) + EXPORT_FUNC(mdelay, void, mdelay, unsigned long msec) + EXPORT_FUNC(memset, void *, memset, void *, int, size_t) +#ifdef CONFIG_PHY_AQUANTIA + EXPORT_FUNC(mdio_get_current_dev, struct mii_dev *, + mdio_get_current_dev, void) + EXPORT_FUNC(phy_find_by_mask, struct phy_device *, phy_find_by_mask, + struct mii_dev *bus, unsigned phy_mask, + phy_interface_t interface) + EXPORT_FUNC(mdio_phydev_for_ethname, struct phy_device *, + mdio_phydev_for_ethname, const char *ethname) + EXPORT_FUNC(miiphy_set_current_dev, int, miiphy_set_current_dev, + const char *devname) +#endif diff --git a/roms/u-boot/include/acpi/acpi_device.h b/roms/u-boot/include/acpi/acpi_device.h new file mode 100644 index 000000000..2c8846250 --- /dev/null +++ b/roms/u-boot/include/acpi/acpi_device.h @@ -0,0 +1,498 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Generation of tables for particular device types + * + * Copyright 2019 Google LLC + * Mostly taken from coreboot file of the same name + */ + +#ifndef __ACPI_DEVICE_H +#define __ACPI_DEVICE_H + +#include +#include +#include +#include +#include + +struct acpi_ctx; +struct gpio_desc; +struct irq; +struct udevice; + +/* ACPI descriptor values for common descriptors: SERIAL_BUS means I2C */ +#define ACPI_DESCRIPTOR_LARGE BIT(7) +#define ACPI_DESCRIPTOR_REGISTER (ACPI_DESCRIPTOR_LARGE | 2) +#define ACPI_DESCRIPTOR_INTERRUPT (ACPI_DESCRIPTOR_LARGE | 9) +#define ACPI_DESCRIPTOR_GPIO (ACPI_DESCRIPTOR_LARGE | 12) +#define ACPI_DESCRIPTOR_SERIAL_BUS (ACPI_DESCRIPTOR_LARGE | 14) + +/* Length of a full path to an ACPI device */ +#define ACPI_PATH_MAX 30 + +/* UUID for an I2C _DSM method */ +#define ACPI_DSM_I2C_HID_UUID "3cdff6f7-4267-4555-ad05-b30a3d8938de" + +/* Values that can be returned for ACPI device _STA method */ +enum acpi_dev_status { + ACPI_DSTATUS_PRESENT = BIT(0), + ACPI_DSTATUS_ENABLED = BIT(1), + ACPI_DSTATUS_SHOW_IN_UI = BIT(2), + ACPI_DSTATUS_OK = BIT(3), + ACPI_DSTATUS_HAS_BATTERY = BIT(4), + + ACPI_DSTATUS_ALL_OFF = 0, + ACPI_DSTATUS_HIDDEN_ON = ACPI_DSTATUS_PRESENT | ACPI_DSTATUS_ENABLED | + ACPI_DSTATUS_OK, + ACPI_DSTATUS_ALL_ON = ACPI_DSTATUS_HIDDEN_ON | + ACPI_DSTATUS_SHOW_IN_UI, +}; + +/** enum acpi_irq_mode - edge/level trigger mode */ +enum acpi_irq_mode { + ACPI_IRQ_EDGE_TRIGGERED, + ACPI_IRQ_LEVEL_TRIGGERED, +}; + +/** + * enum acpi_irq_polarity - polarity of interrupt + * + * @ACPI_IRQ_ACTIVE_LOW - for ACPI_IRQ_EDGE_TRIGGERED this means falling edge + * @ACPI_IRQ_ACTIVE_HIGH - for ACPI_IRQ_EDGE_TRIGGERED this means rising edge + * @ACPI_IRQ_ACTIVE_BOTH - not meaningful for ACPI_IRQ_EDGE_TRIGGERED + */ +enum acpi_irq_polarity { + ACPI_IRQ_ACTIVE_LOW, + ACPI_IRQ_ACTIVE_HIGH, + ACPI_IRQ_ACTIVE_BOTH, +}; + +/** + * enum acpi_irq_shared - whether interrupt is shared or not + * + * @ACPI_IRQ_EXCLUSIVE: only this device uses the interrupt + * @ACPI_IRQ_SHARED: other devices may use this interrupt + */ +enum acpi_irq_shared { + ACPI_IRQ_EXCLUSIVE, + ACPI_IRQ_SHARED, +}; + +/** enum acpi_irq_wake - indicates whether this interrupt can wake the device */ +enum acpi_irq_wake { + ACPI_IRQ_NO_WAKE, + ACPI_IRQ_WAKE, +}; + +/** + * struct acpi_irq - representation of an ACPI interrupt + * + * @pin: ACPI pin that is monitored for the interrupt + * @mode: Edge/level triggering + * @polarity: Interrupt polarity + * @shared: Whether interrupt is shared or not + * @wake: Whether interrupt can wake the device from sleep + */ +struct acpi_irq { + unsigned int pin; + enum acpi_irq_mode mode; + enum acpi_irq_polarity polarity; + enum acpi_irq_shared shared; + enum acpi_irq_wake wake; +}; + +/** + * enum acpi_gpio_type - type of the descriptor + * + * @ACPI_GPIO_TYPE_INTERRUPT: GpioInterrupt + * @ACPI_GPIO_TYPE_IO: GpioIo + */ +enum acpi_gpio_type { + ACPI_GPIO_TYPE_INTERRUPT, + ACPI_GPIO_TYPE_IO, +}; + +/** + * enum acpi_gpio_pull - pull direction + * + * @ACPI_GPIO_PULL_DEFAULT: Use default value for pin + * @ACPI_GPIO_PULL_UP: Pull up + * @ACPI_GPIO_PULL_DOWN: Pull down + * @ACPI_GPIO_PULL_NONE: No pullup/pulldown + */ +enum acpi_gpio_pull { + ACPI_GPIO_PULL_DEFAULT, + ACPI_GPIO_PULL_UP, + ACPI_GPIO_PULL_DOWN, + ACPI_GPIO_PULL_NONE, +}; + +/** + * enum acpi_gpio_io_restrict - controls input/output of pin + * + * @ACPI_GPIO_IO_RESTRICT_NONE: no restrictions + * @ACPI_GPIO_IO_RESTRICT_INPUT: input only (no output) + * @ACPI_GPIO_IO_RESTRICT_OUTPUT: output only (no input) + * @ACPI_GPIO_IO_RESTRICT_PRESERVE: preserve settings when driver not active + */ +enum acpi_gpio_io_restrict { + ACPI_GPIO_IO_RESTRICT_NONE, + ACPI_GPIO_IO_RESTRICT_INPUT, + ACPI_GPIO_IO_RESTRICT_OUTPUT, + ACPI_GPIO_IO_RESTRICT_PRESERVE, +}; + +/** enum acpi_gpio_polarity - controls the GPIO polarity */ +enum acpi_gpio_polarity { + ACPI_GPIO_ACTIVE_HIGH = 0, + ACPI_GPIO_ACTIVE_LOW = 1, +}; + +#define ACPI_GPIO_REVISION_ID 1 +#define ACPI_GPIO_MAX_PINS 2 + +/** + * struct acpi_gpio - representation of an ACPI GPIO + * + * @pin_count: Number of pins represented + * @pins: List of pins + * @pin0_addr: Address in memory of the control registers for pin 0. This is + * used when generating ACPI tables + * @type: GPIO type + * @pull: Pullup/pulldown setting + * @resource: Resource name for this GPIO controller + * For GpioInt: + * @interrupt_debounce_timeout: Debounce timeout in units of 10us + * @irq: Interrupt + * + * For GpioIo: + * @output_drive_strength: Drive strength in units of 10uA + * @io_shared; true if GPIO is shared + * @io_restrict: I/O restriction setting + * @polarity: GPIO polarity + * + * Note that GpioIo() doesn't have any means of Active Low / High setting, so a + * _DSD must be provided to mitigate this. This parameter does not make sense + * for GpioInt() since it has its own means to define it. + * + * GpioIo() doesn't properly communicate the initial state of the output pin, + * thus Linux assumes the simple rule: + * + * Pull Bias Polarity Requested... + * + * Implicit x AS IS (assumed firmware configured for us) + * Explicit x (no _DSD) as Pull Bias (Up == High, Down == Low), + * assuming non-active (Polarity = !Pull Bias) + * + * Down Low as low, assuming active + * Down High as low, assuming non-active + * Up Low as high, assuming non-active + * Up High as high, assuming active + * + * GpioIo() can be used as interrupt and in this case the IoRestriction mustn't + * be OutputOnly. It also requires active_low flag from _DSD in cases where it's + * needed (better to always provide than rely on above assumption made on OS + * level). + */ +struct acpi_gpio { + int pin_count; + u16 pins[ACPI_GPIO_MAX_PINS]; + ulong pin0_addr; + + enum acpi_gpio_type type; + enum acpi_gpio_pull pull; + char resource[ACPI_PATH_MAX]; + + /* GpioInt */ + u16 interrupt_debounce_timeout; + struct acpi_irq irq; + + /* GpioIo */ + u16 output_drive_strength; + bool io_shared; + enum acpi_gpio_io_restrict io_restrict; + enum acpi_gpio_polarity polarity; +}; + +/* ACPI Descriptors for Serial Bus interfaces */ +#define ACPI_SERIAL_BUS_TYPE_I2C 1 +#define ACPI_SERIAL_BUS_TYPE_SPI 2 +#define ACPI_I2C_SERIAL_BUS_REVISION_ID 1 /* TODO: upgrade to 2 */ +#define ACPI_I2C_TYPE_SPECIFIC_REVISION_ID 1 +#define ACPI_SPI_SERIAL_BUS_REVISION_ID 1 +#define ACPI_SPI_TYPE_SPECIFIC_REVISION_ID 1 + +/** + * struct acpi_i2c - representation of an ACPI I2C device + * + * @address: 7-bit or 10-bit I2C address + * @mode_10bit: Which address size is used + * @speed: Bus speed in Hz + * @resource: Resource name for the I2C controller + */ +struct acpi_i2c { + u16 address; + enum i2c_address_mode mode_10bit; + enum i2c_speed_rate speed; + const char *resource; +}; + +/** + * struct acpi_spi - representation of an ACPI SPI device + * + * @device_select: Chip select used by this device (typically 0) + * @device_select_polarity: Polarity for the device + * @wire_mode: Number of wires used for SPI + * @speed: Bus speed in Hz + * @data_bit_length: Word length for SPI (typically 8) + * @clock_phase: Clock phase to capture data + * @clock_polarity: Bus polarity + * @resource: Resource name for the SPI controller + */ +struct acpi_spi { + u16 device_select; + enum spi_polarity device_select_polarity; + enum spi_wire_mode wire_mode; + unsigned int speed; + u8 data_bit_length; + enum spi_clock_phase clock_phase; + enum spi_polarity clock_polarity; + const char *resource; +}; + +/** + * struct acpi_i2c_priv - Information read from device tree + * + * This is used by devices which want to specify various pieces of ACPI + * information, including power control. It allows a generic function to + * generate the information for ACPI, based on device-tree properties. + * + * @disable_gpio_export_in_crs: Don't export GPIOs in the CRS + * @reset_gpio: GPIO used to assert reset to the device + * @enable_gpio: GPIO used to enable the device + * @stop_gpio: GPIO used to stop the device + * @irq_gpio: GPIO used for interrupt (if @irq is not used) + * @irq: IRQ used for interrupt (if @irq_gpio is not used) + * @hid: _HID value for device (required) + * @uid: _UID value for device + * @desc: _DDN value for device + * @wake: Wake event, e.g. GPE0_DW1_15; 0 if none + * @property_count: Number of other DSD properties (currently always 0) + * @probed: true set set 'linux,probed' property + * @compat_string: Device tree compatible string to report through ACPI + * @has_power_resource: true if this device has a power resource + * @reset_delay_ms: Delay after de-asserting reset, in ms + * @reset_off_delay_ms: Delay after asserting reset (during power off) + * @enable_delay_ms: Delay after asserting enable + * @enable_off_delay_ms: Delay after de-asserting enable (during power off) + * @stop_delay_ms: Delay after de-aserting stop + * @stop_off_delay_ms: Delay after asserting stop (during power off) + * @hid_desc_reg_offset: HID register offset (for Human Interface Devices) + */ +struct acpi_i2c_priv { + bool disable_gpio_export_in_crs; + struct gpio_desc reset_gpio; + struct gpio_desc enable_gpio; + struct gpio_desc irq_gpio; + struct gpio_desc stop_gpio; + struct irq irq; + const char *hid; + u32 uid; + const char *desc; + u32 wake; + u32 property_count; + bool probed; + const char *compat_string; + bool has_power_resource; + u32 reset_delay_ms; + u32 reset_off_delay_ms; + u32 enable_delay_ms; + u32 enable_off_delay_ms; + u32 stop_delay_ms; + u32 stop_off_delay_ms; + u32 hid_desc_reg_offset; +}; + +/** + * acpi_device_path() - Get the full path to an ACPI device + * + * This gets the full path in the form XXXX.YYYY.ZZZZ where XXXX is the root + * and ZZZZ is the device. All parent devices are added to the path. + * + * @dev: Device to check + * @buf: Buffer to place the path in (should be ACPI_PATH_MAX long) + * @maxlen: Size of buffer (typically ACPI_PATH_MAX) + * @return 0 if OK, -ve on error + */ +int acpi_device_path(const struct udevice *dev, char *buf, int maxlen); + +/** + * acpi_device_scope() - Get the scope of an ACPI device + * + * This gets the scope which is the full path of the parent device, as per + * acpi_device_path(). + * + * @dev: Device to check + * @buf: Buffer to place the path in (should be ACPI_PATH_MAX long) + * @maxlen: Size of buffer (typically ACPI_PATH_MAX) + * @return 0 if OK, -EINVAL if the device has no parent, other -ve on other + * error + */ +int acpi_device_scope(const struct udevice *dev, char *scope, int maxlen); + +/** + * acpi_device_status() - Get the status of a device + * + * This currently just returns ACPI_DSTATUS_ALL_ON. It does not support + * inactive or hidden devices. + * + * @dev: Device to check + * @return device status, as ACPI_DSTATUS_... + */ +enum acpi_dev_status acpi_device_status(const struct udevice *dev); + +/** + * acpi_device_write_interrupt_irq() - Write an interrupt descriptor + * + * This writes an ACPI interrupt descriptor for the given interrupt, converting + * fields as needed. + * + * @ctx: ACPI context pointer + * @req_irq: Interrupt to output + * @return IRQ pin number if OK, -ve on error + */ +int acpi_device_write_interrupt_irq(struct acpi_ctx *ctx, + const struct irq *req_irq); + +/** + * acpi_device_write_gpio() - Write GpioIo() or GpioInt() descriptor + * + * @gpio: GPIO information to write + * @return GPIO pin number of first GPIO if OK, -ve on error + */ +int acpi_device_write_gpio(struct acpi_ctx *ctx, const struct acpi_gpio *gpio); + +/** + * acpi_device_write_gpio_desc() - Write a GPIO to ACPI + * + * This creates a GPIO descriptor for a GPIO, including information ACPI needs + * to use it. + * + * @ctx: ACPI context pointer + * @desc: GPIO to write + * @return 0 if OK, -ve on error + */ +int acpi_device_write_gpio_desc(struct acpi_ctx *ctx, + const struct gpio_desc *desc); + +/** + * acpi_device_write_interrupt_or_gpio() - Write interrupt or GPIO to ACPI + * + * This reads an interrupt from the device tree "interrupts-extended" property, + * if available. If not it reads the first GPIO with the name @prop. + * + * If an interrupt is found, an ACPI interrupt descriptor is written to the ACPI + * output. If not, but if a GPIO is found, a GPIO descriptor is written. + * + * @return irq or GPIO pin number if OK, -ve if neither an interrupt nor a GPIO + * could be found, or some other error occurred + */ +int acpi_device_write_interrupt_or_gpio(struct acpi_ctx *ctx, + struct udevice *dev, const char *prop); + +/** + * acpi_device_write_dsm_i2c_hid() - Write a device-specific method for HID + * + * This writes a DSM for an I2C Human-Interface Device based on the config + * provided + * + * @hid_desc_reg_offset: HID register offset + */ +int acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx, + int hid_desc_reg_offset); + +/** + * acpi_device_write_i2c_dev() - Write an I2C device to ACPI + * + * This creates a I2cSerialBusV2 descriptor for an I2C device, including + * information ACPI needs to use it. + * + * @ctx: ACPI context pointer + * @dev: I2C device to write + * @return I2C address of device if OK, -ve on error + */ +int acpi_device_write_i2c_dev(struct acpi_ctx *ctx, const struct udevice *dev); + +/** + * acpi_device_write_spi_dev() - Write a SPI device to ACPI + * + * This writes a serial bus descriptor for the SPI device so that ACPI can use + * it + * + * @ctx: ACPI context pointer + * @dev: SPI device to write + * @return 0 if OK, -ve on error + */ +int acpi_device_write_spi_dev(struct acpi_ctx *ctx, const struct udevice *dev); + +/** + * acpi_device_add_power_res() - Add a basic PowerResource block for a device + * + * This includes GPIOs to control enable, reset and stop operation of the + * device. Each GPIO is optional, but at least one must be provided. + * This can be applied to any device that has power control, so is fairly + * generic. + * + * Reset - Put the device into / take the device out of reset. + * Enable - Enable / disable power to device. + * Stop - Stop / start operation of device. + * + * @ctx: ACPI context pointer + * @tx_state_val: Mask to use to toggle the TX state on the GPIO pin, e,g. + * PAD_CFG0_TX_STATE + * @dw0_read: Name to use to read dw0, e.g. "\\_SB.GPC0" + * @dw0_write: Name to use to read dw0, e.g. "\\_SB.SPC0" + * @reset_gpio: GPIO used to take device out of reset or to put it into reset + * @reset_delay_ms: Delay to be inserted after device is taken out of reset + * (_ON method delay) + * @reset_off_delay_ms: Delay to be inserted after device is put into reset + * (_OFF method delay) + * @enable_gpio: GPIO used to enable device + * @enable_delay_ms: Delay to be inserted after device is enabled + * @enable_off_delay_ms: Delay to be inserted after device is disabled + * (_OFF method delay) + * @stop_gpio: GPIO used to stop operation of device + * @stop_delay_ms: Delay to be inserted after disabling stop (_ON method delay) + * @stop_off_delay_ms: Delay to be inserted after enabling stop. + * (_OFF method delay) + * + * @return 0 if OK, -ve if at least one GPIO is not provided + */ +int acpi_device_add_power_res(struct acpi_ctx *ctx, u32 tx_state_val, + const char *dw0_read, const char *dw0_write, + const struct gpio_desc *reset_gpio, + uint reset_delay_ms, uint reset_off_delay_ms, + const struct gpio_desc *enable_gpio, + uint enable_delay_ms, uint enable_off_delay_ms, + const struct gpio_desc *stop_gpio, + uint stop_delay_ms, uint stop_off_delay_ms); + +/** + * acpi_device_infer_name() - Infer the name from its uclass or parent + * + * Many ACPI devices have a standard name that can be inferred from the uclass + * they are in, or the uclass of their parent. These rules are implemented in + * this function. It attempts to produce a name for a device based on these + * rules. + * + * NOTE: This currently supports only x86 devices. Feel free to enhance it for + * other architectures as needed. + * + * @dev: Device to check + * @out_name: Place to put the name (must hold ACPI_NAME_MAX bytes) + * @return 0 if a name was found, -ENOENT if not found, -ENXIO if the device + * sequence number could not be determined + */ +int acpi_device_infer_name(const struct udevice *dev, char *out_name); + +#endif diff --git a/roms/u-boot/include/acpi/acpi_dp.h b/roms/u-boot/include/acpi/acpi_dp.h new file mode 100644 index 000000000..5e539b1d2 --- /dev/null +++ b/roms/u-boot/include/acpi/acpi_dp.h @@ -0,0 +1,287 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device properties, a temporary data structure for adding to ACPI code + * + * Copyright 2019 Google LLC + * Mostly taken from coreboot file acpi_device.h + */ + +#ifndef __ACPI_DP_H +#define __ACPI_DP_H + +struct acpi_ctx; + +#include + +/* + * Writing Device Properties objects via _DSD + * + * This is described in ACPI 6.3 section 6.2.5 + * + * This provides a structure to handle nested device-specific data which ends + * up in a _DSD table. + * + * https://www.kernel.org/doc/html/latest/firmware-guide/acpi/DSD-properties-rules.html + * https://uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf + * https://uefi.org/sites/default/files/resources/_DSD-hierarchical-data-extension-UUID-v1.1.pdf + * + * The Device Property Hierarchy can be multiple levels deep with multiple + * children possible in each level. In order to support this flexibility + * the device property hierarchy must be built up before being written out. + * + * For example: + * + * Child table with string and integer: + * struct acpi_dp *child = acpi_dp_new_table("CHLD"); + * acpi_dp_add_string(child, "childstring", "CHILD"); + * acpi_dp_add_integer(child, "childint", 100); + * + * _DSD table with integer and gpio and child pointer: + * struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); + * acpi_dp_add_integer(dsd, "number1", 1); + * acpi_dp_add_gpio(dsd, "gpio", "\_SB.PCI0.GPIO", 0, 0, 1); + * acpi_dp_add_child(dsd, "child", child); + * + * Write entries into SSDT and clean up resources: + * acpi_dp_write(dsd); + * + * Name(_DSD, Package() { + * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") + * Package() { + * Package() { "gpio", Package() { \_SB.PCI0.GPIO, 0, 0, 0 } } + * Package() { "number1", 1 } + * } + * ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b") + * Package() { + * Package() { "child", CHLD } + * } + * } + * Name(CHLD, Package() { + * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") + * Package() { + * Package() { "childstring", "CHILD" } + * Package() { "childint", 100 } + * } + * } + */ + +#define ACPI_DP_UUID "daffd814-6eba-4d8c-8a91-bc9bbf4aa301" +#define ACPI_DP_CHILD_UUID "dbb8e3e6-5886-4ba6-8795-1319f52a966b" + +/** + * enum acpi_dp_type - types of device property objects + * + * These refer to the types defined by struct acpi_dp below + * + * @ACPI_DP_TYPE_UNKNOWN: Unknown / do not use + * @ACPI_DP_TYPE_INTEGER: Integer value (u64) in @integer + * @ACPI_DP_TYPE_STRING: String value in @string + * @ACPI_DP_TYPE_REFERENCE: Reference to another object, with value in @string + * @ACPI_DP_TYPE_TABLE: Type for a top-level table which may have children + * @ACPI_DP_TYPE_ARRAY: Array of items with first item in @array and following + * items linked from that item's @next + * @ACPI_DP_TYPE_CHILD: Child object, with siblings in that child's @next + */ +enum acpi_dp_type { + ACPI_DP_TYPE_UNKNOWN, + ACPI_DP_TYPE_INTEGER, + ACPI_DP_TYPE_STRING, + ACPI_DP_TYPE_REFERENCE, + ACPI_DP_TYPE_TABLE, + ACPI_DP_TYPE_ARRAY, + ACPI_DP_TYPE_CHILD, +}; + +/** + * struct acpi_dp - ACPI device properties + * + * @type: Table type + * @name: Name of object, typically _DSD but could be CHLD for a child object. + * This can be NULL if there is no name + * @next: Next object in list (next array element or next sibling) + * @child: Pointer to first child, if @type == ACPI_DP_TYPE_CHILD, else NULL + * @array: First array element, if @type == ACPI_DP_TYPE_ARRAY, else NULL + * @integer: Integer value of the property, if @type == ACPI_DP_TYPE_INTEGER + * @string: String value of the property, if @type == ACPI_DP_TYPE_STRING; + * child name if @type == ACPI_DP_TYPE_CHILD; + * reference name if @type == ACPI_DP_TYPE_REFERENCE; + */ +struct acpi_dp { + enum acpi_dp_type type; + const char *name; + struct acpi_dp *next; + union { + struct acpi_dp *child; + struct acpi_dp *array; + }; + union { + u64 integer; + const char *string; + }; +}; + +/** + * acpi_dp_new_table() - Start a new Device Property table + * + * @ref: ACPI reference (e.g. "_DSD") + * @return pointer to table, or NULL if out of memory + */ +struct acpi_dp *acpi_dp_new_table(const char *ref); + +/** + * acpi_dp_add_integer() - Add integer Device Property + * + * A new node is added to the end of the property list of @dp + * + * @dp: Table to add this property to + * @name: Name of property, or NULL for none + * @value: Integer value + * @return pointer to new node, or NULL if out of memory + */ +struct acpi_dp *acpi_dp_add_integer(struct acpi_dp *dp, const char *name, + u64 value); + +/** + * acpi_dp_add_string() - Add string Device Property + * + * A new node is added to the end of the property list of @dp + * + * @dp: Table to add this property to + * @name: Name of property, or NULL for none + * @string: String value + * @return pointer to new node, or NULL if out of memory + */ +struct acpi_dp *acpi_dp_add_string(struct acpi_dp *dp, const char *name, + const char *string); + +/** + * acpi_dp_add_reference() - Add reference Device Property + * + * A new node is added to the end of the property list of @dp + * + * @dp: Table to add this property to + * @name: Name of property, or NULL for none + * @reference: Reference value + * @return pointer to new node, or NULL if out of memory + */ +struct acpi_dp *acpi_dp_add_reference(struct acpi_dp *dp, const char *name, + const char *reference); + +/** + * acpi_dp_add_array() - Add array Device Property + * + * A new node is added to the end of the property list of @dp, with the array + * attached to that. + * + * @dp: Table to add this property to + * @name: Name of property, or NULL for none + * @return pointer to new node, or NULL if out of memory + */ +struct acpi_dp *acpi_dp_add_array(struct acpi_dp *dp, struct acpi_dp *array); + +/** + * acpi_dp_add_integer_array() - Add an array of integers + * + * A new node is added to the end of the property list of @dp, with the array + * attached to that. Each element of the array becomes a new node. + * + * @dp: Table to add this property to + * @name: Name of property, or NULL for none + * @return pointer to new array node, or NULL if out of memory + */ +struct acpi_dp *acpi_dp_add_integer_array(struct acpi_dp *dp, const char *name, + u64 *array, int len); + +/** + * acpi_dp_add_child() - Add a child table of Device Properties + * + * A new node is added as a child of @dp + * + * @dp: Table to add this child to + * @name: Name of child, or NULL for none + * @child: Child node to add + * @return pointer to new child node, or NULL if out of memory + */ +struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const char *name, + struct acpi_dp *child); + +/** + * acpi_dp_add_gpio() - Add a GPIO to a list of Device Properties + * + * A new node is added to the end of the property list of @dp, with the + * GPIO properties added to the the new node + * + * @dp: Table to add this property to + * @name: Name of property + * @ref: Reference to device with a _CRS containing GpioIO or GpioInt + * @index: Index of the GPIO resource in _CRS starting from zero + * @pin: Pin in the GPIO resource, typically zero + * @polarity: GPIO polarity. Note that ACPI_IRQ_ACTIVE_BOTH is not supported + * @return pointer to new node, or NULL if out of memory + */ +struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, + const char *ref, int index, int pin, + enum acpi_gpio_polarity polarity); + +/** + * acpi_dp_write() - Write Device Property hierarchy and clean up resources + * + * This writes the table using acpigen and then frees it + * + * @ctx: ACPI context + * @table: Table to write + * @return 0 if OK, -ve on error + */ +int acpi_dp_write(struct acpi_ctx *ctx, struct acpi_dp *table); + +/** + * acpi_dp_ofnode_copy_int() - Copy a property from device tree to DP + * + * This copies an integer property from the device tree to the ACPI DP table. + * + * @node: Node to copy from + * @dp: DP to copy to + * @prop: Property name to copy + * @return 0 if OK, -ve on error + */ +int acpi_dp_ofnode_copy_int(ofnode node, struct acpi_dp *dp, const char *prop); + +/** + * acpi_dp_ofnode_copy_str() - Copy a property from device tree to DP + * + * This copies a string property from the device tree to the ACPI DP table. + * + * @node: Node to copy from + * @dp: DP to copy to + * @prop: Property name to copy + * @return 0 if OK, -ve on error + */ +int acpi_dp_ofnode_copy_str(ofnode node, struct acpi_dp *dp, const char *prop); + +/** + * acpi_dp_dev_copy_int() - Copy a property from device tree to DP + * + * This copies an integer property from the device tree to the ACPI DP table. + * + * @dev: Device to copy from + * @dp: DP to copy to + * @prop: Property name to copy + * @return 0 if OK, -ve on error + */ +int acpi_dp_dev_copy_int(const struct udevice *dev, struct acpi_dp *dp, + const char *prop); + +/** + * acpi_dp_dev_copy_str() - Copy a property from device tree to DP + * + * This copies a string property from the device tree to the ACPI DP table. + * + * @dev: Device to copy from + * @dp: DP to copy to + * @prop: Property name to copy + * @return 0 if OK, -ve on error + */ +int acpi_dp_dev_copy_str(const struct udevice *dev, struct acpi_dp *dp, + const char *prop); + +#endif diff --git a/roms/u-boot/include/acpi/acpi_s3.h b/roms/u-boot/include/acpi/acpi_s3.h new file mode 100644 index 000000000..847139baa --- /dev/null +++ b/roms/u-boot/include/acpi/acpi_s3.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017, Bin Meng + */ + +#ifndef __ASM_ACPI_S3_H__ +#define __ASM_ACPI_S3_H__ + +#define WAKEUP_BASE 0x600 + +/* PM1_STATUS register */ +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define RTC_STS (1 << 10) +#define SLPBTN_STS (1 << 9) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMR_STS (1 << 0) + +/* PM1_CNT register */ +#define SLP_EN (1 << 13) +#define SLP_TYP_SHIFT 10 +#define SLP_TYP (7 << SLP_TYP_SHIFT) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 + +/* PM1_STS register */ +#define RTC_EN BIT(10) +#define PWRBTN_EN BIT(8) + +/* Memory size reserved for S3 resume */ +#define S3_RESERVE_SIZE 0x1000 + +#ifndef __ASSEMBLY__ + +extern char __wakeup[]; +extern int __wakeup_size; + +enum acpi_sleep_state { + ACPI_S0, + ACPI_S1, + ACPI_S2, + ACPI_S3, + ACPI_S4, + ACPI_S5, +}; + +/** + * acpi_ss_string() - get ACPI-defined sleep state string + * + * @pm1_cnt: ACPI-defined sleep state + * @return: a pointer to the sleep state string. + */ +static inline char *acpi_ss_string(enum acpi_sleep_state state) +{ + char *ss_string[] = { "S0", "S1", "S2", "S3", "S4", "S5"}; + + return ss_string[state]; +} + +/** + * acpi_sleep_from_pm1() - get ACPI-defined sleep state from PM1_CNT register + * + * @pm1_cnt: PM1_CNT register value + * @return: ACPI-defined sleep state if given valid PM1_CNT register value, + * -EINVAL otherwise. + */ +static inline enum acpi_sleep_state acpi_sleep_from_pm1(u32 pm1_cnt) +{ + switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { + case SLP_TYP_S0: + return ACPI_S0; + case SLP_TYP_S1: + return ACPI_S1; + case SLP_TYP_S3: + return ACPI_S3; + case SLP_TYP_S4: + return ACPI_S4; + case SLP_TYP_S5: + return ACPI_S5; + } + + return -EINVAL; +} + +/** + * chipset_prev_sleep_state() - Get chipset previous sleep state + * + * This returns chipset previous sleep state from ACPI registers. + * Platform codes must supply this routine in order to support ACPI S3. + * + * @return ACPI_S0/S1/S2/S3/S4/S5. + */ +enum acpi_sleep_state chipset_prev_sleep_state(void); + +/** + * chipset_clear_sleep_state() - Clear chipset sleep state + * + * This clears chipset sleep state in ACPI registers. + * Platform codes must supply this routine in order to support ACPI S3. + */ +void chipset_clear_sleep_state(void); + +struct acpi_fadt; +/** + * acpi_resume() - Do ACPI S3 resume + * + * This calls U-Boot wake up assembly stub and jumps to OS's wake up vector. + * + * @fadt: FADT table pointer in the ACPI table + * @return: Never returns + */ +void acpi_resume(struct acpi_fadt *fadt); + +/** + * acpi_s3_reserve() - Reserve memory for ACPI S3 resume + * + * This copies memory where real mode interrupt handler stubs reside to the + * reserved place on the stack. + * + * This routine should be called by reserve_arch() before U-Boot is relocated + * when ACPI S3 resume is enabled. + * + * @return: 0 always + */ +int acpi_s3_reserve(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ACPI_S3_H__ */ diff --git a/roms/u-boot/include/acpi/acpi_table.h b/roms/u-boot/include/acpi/acpi_table.h new file mode 100644 index 000000000..a28eb71f4 --- /dev/null +++ b/roms/u-boot/include/acpi/acpi_table.h @@ -0,0 +1,705 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Helpers for ACPI table generation + * + * Based on acpi.c from coreboot + * + * Copyright 2019 Google LLC + * + * Copyright (C) 2015, Saket Sinha + * Copyright (C) 2016, Bin Meng + */ + +#ifndef __ACPI_TABLE_H__ +#define __ACPI_TABLE_H__ + +#include + +#define RSDP_SIG "RSD PTR " /* RSDP pointer signature */ +#define OEM_ID "U-BOOT" /* U-Boot */ +#define OEM_TABLE_ID "U-BOOTBL" /* U-Boot Table */ +#define ASLC_ID "INTL" /* Intel ASL Compiler */ + +/* TODO(sjg@chromium.org): Figure out how to get compiler revision */ +#define ASL_REVISION 0 + +#define ACPI_RSDP_REV_ACPI_1_0 0 +#define ACPI_RSDP_REV_ACPI_2_0 2 + +#if !defined(__ACPI__) + +#include + +struct acpi_ctx; + +/* + * RSDP (Root System Description Pointer) + * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum + */ +struct acpi_rsdp { + char signature[8]; /* RSDP signature */ + u8 checksum; /* Checksum of the first 20 bytes */ + char oem_id[6]; /* OEM ID */ + u8 revision; /* 0 for ACPI 1.0, others 2 */ + u32 rsdt_address; /* Physical address of RSDT (32 bits) */ + u32 length; /* Total RSDP length (incl. extended part) */ + u64 xsdt_address; /* Physical address of XSDT (64 bits) */ + u8 ext_checksum; /* Checksum of the whole table */ + u8 reserved[3]; +}; + +/* Generic ACPI header, provided by (almost) all tables */ +struct __packed acpi_table_header { + char signature[ACPI_NAME_LEN]; /* ACPI signature (4 ASCII chars) */ + u32 length; /* Table length in bytes (incl. header) */ + u8 revision; /* Table version (not ACPI version!) */ + volatile u8 checksum; /* To make sum of entire table == 0 */ + char oem_id[6]; /* OEM identification */ + char oem_table_id[8]; /* OEM table identification */ + u32 oem_revision; /* OEM revision number */ + char aslc_id[4]; /* ASL compiler vendor ID */ + u32 aslc_revision; /* ASL compiler revision number */ +}; + +struct acpi_gen_regaddr { + u8 space_id; /* Address space ID */ + u8 bit_width; /* Register size in bits */ + u8 bit_offset; /* Register bit offset */ + u8 access_size; /* Access size */ + u32 addrl; /* Register address, low 32 bits */ + u32 addrh; /* Register address, high 32 bits */ +}; + +/* A maximum number of 32 ACPI tables ought to be enough for now */ +#define MAX_ACPI_TABLES 32 + +/* RSDT (Root System Description Table) */ +struct acpi_rsdt { + struct acpi_table_header header; + u32 entry[MAX_ACPI_TABLES]; +}; + +/* XSDT (Extended System Description Table) */ +struct acpi_xsdt { + struct acpi_table_header header; + u64 entry[MAX_ACPI_TABLES]; +}; + +/* HPET timers */ +struct __packed acpi_hpet { + struct acpi_table_header header; + u32 id; + struct acpi_gen_regaddr addr; + u8 number; + u16 min_tick; + u8 attributes; +}; + +struct __packed acpi_tpm2 { + struct acpi_table_header header; + u16 platform_class; + u8 reserved[2]; + u64 control_area; + u32 start_method; + u8 msp[12]; + u32 laml; + u64 lasa; +}; + +struct __packed acpi_tcpa { + struct acpi_table_header header; + u16 platform_class; + u32 laml; + u64 lasa; +}; + +/* FADT Preferred Power Management Profile */ +enum acpi_pm_profile { + ACPI_PM_UNSPECIFIED = 0, + ACPI_PM_DESKTOP, + ACPI_PM_MOBILE, + ACPI_PM_WORKSTATION, + ACPI_PM_ENTERPRISE_SERVER, + ACPI_PM_SOHO_SERVER, + ACPI_PM_APPLIANCE_PC, + ACPI_PM_PERFORMANCE_SERVER, + ACPI_PM_TABLET +}; + +/* FADT flags for p_lvl2_lat and p_lvl3_lat */ +#define ACPI_FADT_C2_NOT_SUPPORTED 101 +#define ACPI_FADT_C3_NOT_SUPPORTED 1001 + +/* FADT Boot Architecture Flags */ +#define ACPI_FADT_LEGACY_FREE 0x00 +#define ACPI_FADT_LEGACY_DEVICES BIT(0) +#define ACPI_FADT_8042 BIT(1) +#define ACPI_FADT_VGA_NOT_PRESENT BIT(2) +#define ACPI_FADT_MSI_NOT_SUPPORTED BIT(3) +#define ACPI_FADT_NO_PCIE_ASPM_CONTROL BIT(4) + +/* FADT Feature Flags */ +#define ACPI_FADT_WBINVD BIT(0) +#define ACPI_FADT_WBINVD_FLUSH BIT(1) +#define ACPI_FADT_C1_SUPPORTED BIT(2) +#define ACPI_FADT_C2_MP_SUPPORTED BIT(3) +#define ACPI_FADT_POWER_BUTTON BIT(4) +#define ACPI_FADT_SLEEP_BUTTON BIT(5) +#define ACPI_FADT_FIXED_RTC BIT(6) +#define ACPI_FADT_S4_RTC_WAKE BIT(7) +#define ACPI_FADT_32BIT_TIMER BIT(8) +#define ACPI_FADT_DOCKING_SUPPORTED BIT(9) +#define ACPI_FADT_RESET_REGISTER BIT(10) +#define ACPI_FADT_SEALED_CASE BIT(11) +#define ACPI_FADT_HEADLESS BIT(12) +#define ACPI_FADT_SLEEP_TYPE BIT(13) +#define ACPI_FADT_PCI_EXPRESS_WAKE BIT(14) +#define ACPI_FADT_PLATFORM_CLOCK BIT(15) +#define ACPI_FADT_S4_RTC_VALID BIT(16) +#define ACPI_FADT_REMOTE_POWER_ON BIT(17) +#define ACPI_FADT_APIC_CLUSTER BIT(18) +#define ACPI_FADT_APIC_PHYSICAL BIT(19) +#define ACPI_FADT_HW_REDUCED_ACPI BIT(20) +#define ACPI_FADT_LOW_PWR_IDLE_S0 BIT(21) + +enum acpi_address_space_type { + ACPI_ADDRESS_SPACE_MEMORY = 0, /* System memory */ + ACPI_ADDRESS_SPACE_IO, /* System I/O */ + ACPI_ADDRESS_SPACE_PCI, /* PCI config space */ + ACPI_ADDRESS_SPACE_EC, /* Embedded controller */ + ACPI_ADDRESS_SPACE_SMBUS, /* SMBus */ + ACPI_ADDRESS_SPACE_PCC = 0x0a, /* Platform Comm. Channel */ + ACPI_ADDRESS_SPACE_FIXED = 0x7f /* Functional fixed hardware */ +}; + +enum acpi_address_space_size { + ACPI_ACCESS_SIZE_UNDEFINED = 0, + ACPI_ACCESS_SIZE_BYTE_ACCESS, + ACPI_ACCESS_SIZE_WORD_ACCESS, + ACPI_ACCESS_SIZE_DWORD_ACCESS, + ACPI_ACCESS_SIZE_QWORD_ACCESS +}; + +/* FADT (Fixed ACPI Description Table) */ +struct __packed acpi_fadt { + struct acpi_table_header header; + u32 firmware_ctrl; + u32 dsdt; + u8 res1; + u8 preferred_pm_profile; + u16 sci_int; + u32 smi_cmd; + u8 acpi_enable; + u8 acpi_disable; + u8 s4bios_req; + u8 pstate_cnt; + u32 pm1a_evt_blk; + u32 pm1b_evt_blk; + u32 pm1a_cnt_blk; + u32 pm1b_cnt_blk; + u32 pm2_cnt_blk; + u32 pm_tmr_blk; + u32 gpe0_blk; + u32 gpe1_blk; + u8 pm1_evt_len; + u8 pm1_cnt_len; + u8 pm2_cnt_len; + u8 pm_tmr_len; + u8 gpe0_blk_len; + u8 gpe1_blk_len; + u8 gpe1_base; + u8 cst_cnt; + u16 p_lvl2_lat; + u16 p_lvl3_lat; + u16 flush_size; + u16 flush_stride; + u8 duty_offset; + u8 duty_width; + u8 day_alrm; + u8 mon_alrm; + u8 century; + u16 iapc_boot_arch; + u8 res2; + u32 flags; + struct acpi_gen_regaddr reset_reg; + u8 reset_value; + u16 arm_boot_arch; + u8 minor_revision; + u32 x_firmware_ctl_l; + u32 x_firmware_ctl_h; + u32 x_dsdt_l; + u32 x_dsdt_h; + struct acpi_gen_regaddr x_pm1a_evt_blk; + struct acpi_gen_regaddr x_pm1b_evt_blk; + struct acpi_gen_regaddr x_pm1a_cnt_blk; + struct acpi_gen_regaddr x_pm1b_cnt_blk; + struct acpi_gen_regaddr x_pm2_cnt_blk; + struct acpi_gen_regaddr x_pm_tmr_blk; + struct acpi_gen_regaddr x_gpe0_blk; + struct acpi_gen_regaddr x_gpe1_blk; +}; + +/* FADT TABLE Revision values - note these do not match the ACPI revision */ +#define ACPI_FADT_REV_ACPI_1_0 1 +#define ACPI_FADT_REV_ACPI_2_0 3 +#define ACPI_FADT_REV_ACPI_3_0 4 +#define ACPI_FADT_REV_ACPI_4_0 4 +#define ACPI_FADT_REV_ACPI_5_0 5 +#define ACPI_FADT_REV_ACPI_6_0 6 + +/* MADT TABLE Revision values - note these do not match the ACPI revision */ +#define ACPI_MADT_REV_ACPI_3_0 2 +#define ACPI_MADT_REV_ACPI_4_0 3 +#define ACPI_MADT_REV_ACPI_5_0 3 +#define ACPI_MADT_REV_ACPI_6_0 5 + +#define ACPI_MCFG_REV_ACPI_3_0 1 + +/* IVRS Revision Field */ +#define IVRS_FORMAT_FIXED 0x01 /* Type 10h & 11h only */ +#define IVRS_FORMAT_MIXED 0x02 /* Type 10h, 11h, & 40h */ + +/* FACS flags */ +#define ACPI_FACS_S4BIOS_F BIT(0) +#define ACPI_FACS_64BIT_WAKE_F BIT(1) + +/* FACS (Firmware ACPI Control Structure) */ +struct acpi_facs { + char signature[ACPI_NAME_LEN]; /* "FACS" */ + u32 length; /* Length in bytes (>= 64) */ + u32 hardware_signature; /* Hardware signature */ + u32 firmware_waking_vector; /* Firmware waking vector */ + u32 global_lock; /* Global lock */ + u32 flags; /* FACS flags */ + u32 x_firmware_waking_vector_l; /* X FW waking vector, low */ + u32 x_firmware_waking_vector_h; /* X FW waking vector, high */ + u8 version; /* Version 2 */ + u8 res1[3]; + u32 ospm_flags; /* OSPM enabled flags */ + u8 res2[24]; +}; + +/* MADT flags */ +#define ACPI_MADT_PCAT_COMPAT BIT(0) + +/* MADT (Multiple APIC Description Table) */ +struct acpi_madt { + struct acpi_table_header header; + u32 lapic_addr; /* Local APIC address */ + u32 flags; /* Multiple APIC flags */ +}; + +/* MADT: APIC Structure Type*/ +enum acpi_apic_types { + ACPI_APIC_LAPIC = 0, /* Processor local APIC */ + ACPI_APIC_IOAPIC, /* I/O APIC */ + ACPI_APIC_IRQ_SRC_OVERRIDE, /* Interrupt source override */ + ACPI_APIC_NMI_SRC, /* NMI source */ + ACPI_APIC_LAPIC_NMI, /* Local APIC NMI */ + ACPI_APIC_LAPIC_ADDR_OVERRIDE, /* Local APIC address override */ + ACPI_APIC_IOSAPIC, /* I/O SAPIC */ + ACPI_APIC_LSAPIC, /* Local SAPIC */ + ACPI_APIC_PLATFORM_IRQ_SRC, /* Platform interrupt sources */ + ACPI_APIC_LX2APIC, /* Processor local x2APIC */ + ACPI_APIC_LX2APIC_NMI, /* Local x2APIC NMI */ +}; + +/* MADT: Processor Local APIC Structure */ + +#define LOCAL_APIC_FLAG_ENABLED BIT(0) + +struct acpi_madt_lapic { + u8 type; /* Type (0) */ + u8 length; /* Length in bytes (8) */ + u8 processor_id; /* ACPI processor ID */ + u8 apic_id; /* Local APIC ID */ + u32 flags; /* Local APIC flags */ +}; + +/* MADT: I/O APIC Structure */ +struct acpi_madt_ioapic { + u8 type; /* Type (1) */ + u8 length; /* Length in bytes (12) */ + u8 ioapic_id; /* I/O APIC ID */ + u8 reserved; + u32 ioapic_addr; /* I/O APIC address */ + u32 gsi_base; /* Global system interrupt base */ +}; + +/* MADT: Interrupt Source Override Structure */ +struct __packed acpi_madt_irqoverride { + u8 type; /* Type (2) */ + u8 length; /* Length in bytes (10) */ + u8 bus; /* ISA (0) */ + u8 source; /* Bus-relative int. source (IRQ) */ + u32 gsirq; /* Global system interrupt */ + u16 flags; /* MPS INTI flags */ +}; + +/* MADT: Local APIC NMI Structure */ +struct __packed acpi_madt_lapic_nmi { + u8 type; /* Type (4) */ + u8 length; /* Length in bytes (6) */ + u8 processor_id; /* ACPI processor ID */ + u16 flags; /* MPS INTI flags */ + u8 lint; /* Local APIC LINT# */ +}; + +/* MCFG (PCI Express MMIO config space BAR description table) */ +struct acpi_mcfg { + struct acpi_table_header header; + u8 reserved[8]; +}; + +struct acpi_mcfg_mmconfig { + u32 base_address_l; + u32 base_address_h; + u16 pci_segment_group_number; + u8 start_bus_number; + u8 end_bus_number; + u8 reserved[4]; +}; + +/* PM1_CNT bit defines */ +#define PM1_CNT_SCI_EN BIT(0) + +/* ACPI global NVS structure */ +struct acpi_global_nvs; + +/* CSRT (Core System Resource Table) */ +struct acpi_csrt { + struct acpi_table_header header; +}; + +struct acpi_csrt_group { + u32 length; + u32 vendor_id; + u32 subvendor_id; + u16 device_id; + u16 subdevice_id; + u16 revision; + u16 reserved; + u32 shared_info_length; +}; + +struct acpi_csrt_shared_info { + u16 major_version; + u16 minor_version; + u32 mmio_base_low; + u32 mmio_base_high; + u32 gsi_interrupt; + u8 interrupt_polarity; + u8 interrupt_mode; + u8 num_channels; + u8 dma_address_width; + u16 base_request_line; + u16 num_handshake_signals; + u32 max_block_size; +}; + +/* Port types for ACPI _UPC object */ +enum acpi_upc_type { + UPC_TYPE_A, + UPC_TYPE_MINI_AB, + UPC_TYPE_EXPRESSCARD, + UPC_TYPE_USB3_A, + UPC_TYPE_USB3_B, + UPC_TYPE_USB3_MICRO_B, + UPC_TYPE_USB3_MICRO_AB, + UPC_TYPE_USB3_POWER_B, + UPC_TYPE_C_USB2_ONLY, + UPC_TYPE_C_USB2_SS_SWITCH, + UPC_TYPE_C_USB2_SS, + UPC_TYPE_PROPRIETARY = 0xff, + /* + * The following types are not directly defined in the ACPI + * spec but are used by coreboot to identify a USB device type. + */ + UPC_TYPE_INTERNAL = 0xff, + UPC_TYPE_UNUSED, + UPC_TYPE_HUB +}; + +enum dev_scope_type { + SCOPE_PCI_ENDPOINT = 1, + SCOPE_PCI_SUB = 2, + SCOPE_IOAPIC = 3, + SCOPE_MSI_HPET = 4, + SCOPE_ACPI_NAMESPACE_DEVICE = 5 +}; + +struct __packed dev_scope { + u8 type; + u8 length; + u8 reserved[2]; + u8 enumeration; + u8 start_bus; + struct { + u8 dev; + u8 fn; + } __packed path[0]; +}; + +enum dmar_type { + DMAR_DRHD = 0, + DMAR_RMRR = 1, + DMAR_ATSR = 2, + DMAR_RHSA = 3, + DMAR_ANDD = 4 +}; + +enum { + DRHD_INCLUDE_PCI_ALL = BIT(0) +}; + +enum dmar_flags { + DMAR_INTR_REMAP = BIT(0), + DMAR_X2APIC_OPT_OUT = BIT(1), + DMAR_CTRL_PLATFORM_OPT_IN_FLAG = BIT(2), +}; + +struct dmar_entry { + u16 type; + u16 length; + u8 flags; + u8 reserved; + u16 segment; + u64 bar; +}; + +struct dmar_rmrr_entry { + u16 type; + u16 length; + u16 reserved; + u16 segment; + u64 bar; + u64 limit; +}; + +/* DMAR (DMA Remapping Reporting Structure) */ +struct __packed acpi_dmar { + struct acpi_table_header header; + u8 host_address_width; + u8 flags; + u8 reserved[10]; + struct dmar_entry structure[0]; +}; + +/* DBG2 definitions are partially used for SPCR interface_type */ + +/* Types for port_type field */ + +#define ACPI_DBG2_SERIAL_PORT 0x8000 +#define ACPI_DBG2_1394_PORT 0x8001 +#define ACPI_DBG2_USB_PORT 0x8002 +#define ACPI_DBG2_NET_PORT 0x8003 + +/* Subtypes for port_subtype field */ + +#define ACPI_DBG2_16550_COMPATIBLE 0x0000 +#define ACPI_DBG2_16550_SUBSET 0x0001 +#define ACPI_DBG2_ARM_PL011 0x0003 +#define ACPI_DBG2_ARM_SBSA_32BIT 0x000D +#define ACPI_DBG2_ARM_SBSA_GENERIC 0x000E +#define ACPI_DBG2_ARM_DCC 0x000F +#define ACPI_DBG2_BCM2835 0x0010 + +#define ACPI_DBG2_1394_STANDARD 0x0000 + +#define ACPI_DBG2_USB_XHCI 0x0000 +#define ACPI_DBG2_USB_EHCI 0x0001 + +#define ACPI_DBG2_UNKNOWN 0x00FF + +/* DBG2: Microsoft Debug Port Table 2 header */ +struct __packed acpi_dbg2_header { + struct acpi_table_header header; + u32 devices_offset; + u32 devices_count; +}; + +/* DBG2: Microsoft Debug Port Table 2 device entry */ +struct __packed acpi_dbg2_device { + u8 revision; + u16 length; + u8 address_count; + u16 namespace_string_length; + u16 namespace_string_offset; + u16 oem_data_length; + u16 oem_data_offset; + u16 port_type; + u16 port_subtype; + u8 reserved[2]; + u16 base_address_offset; + u16 address_size_offset; +}; + +/* SPCR (Serial Port Console Redirection table) */ +struct __packed acpi_spcr { + struct acpi_table_header header; + u8 interface_type; + u8 reserved[3]; + struct acpi_gen_regaddr serial_port; + u8 interrupt_type; + u8 pc_interrupt; + u32 interrupt; /* Global system interrupt */ + u8 baud_rate; + u8 parity; + u8 stop_bits; + u8 flow_control; + u8 terminal_type; + u8 reserved1; + u16 pci_device_id; /* Must be 0xffff if not PCI device */ + u16 pci_vendor_id; /* Must be 0xffff if not PCI device */ + u8 pci_bus; + u8 pci_device; + u8 pci_function; + u32 pci_flags; + u8 pci_segment; + u32 reserved2; +}; + +/* Tables defined/reserved by ACPI and generated by U-Boot */ +enum acpi_tables { + ACPITAB_BERT, + ACPITAB_DBG2, + ACPITAB_DMAR, + ACPITAB_DSDT, + ACPITAB_ECDT, + ACPITAB_FACS, + ACPITAB_FADT, + ACPITAB_HEST, + ACPITAB_HPET, + ACPITAB_IVRS, + ACPITAB_MADT, + ACPITAB_MCFG, + ACPITAB_NHLT, + ACPITAB_RSDP, + ACPITAB_RSDT, + ACPITAB_SLIT, + ACPITAB_SPCR, + ACPITAB_SPMI, + ACPITAB_SRAT, + ACPITAB_SSDT, + ACPITAB_TCPA, + ACPITAB_TPM2, + ACPITAB_VFCT, + ACPITAB_XSDT, + + ACPITAB_COUNT, +}; + +/** + * acpi_get_table_revision() - Get the revision number generated for a table + * + * This keeps the version-number information in one place + * + * @table: ACPI table to check + * @return version number that U-Boot generates + */ +int acpi_get_table_revision(enum acpi_tables table); + +/** + * acpi_create_dmar() - Create a DMA Remapping Reporting (DMAR) table + * + * @dmar: Place to put the table + * @flags: DMAR flags to use + * @return 0 if OK, -ve on error + */ +int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags); + +/** + * acpi_create_dbg2() - Create a DBG2 table + * + * This table describes how to access the debug UART + * + * @dbg2: Place to put information + * @port_type: Serial port type (see ACPI_DBG2_...) + * @port_subtype: Serial port sub-type (see ACPI_DBG2_...) + * @address: ACPI address of port + * @address_size: Size of address space + * @device_path: Path of device (created using acpi_device_path()) + */ +void acpi_create_dbg2(struct acpi_dbg2_header *dbg2, + int port_type, int port_subtype, + struct acpi_gen_regaddr *address, uint32_t address_size, + const char *device_path); + +/** + * acpi_fill_header() - Set up a new table header + * + * This sets all fields except length, revision, checksum and aslc_revision + * + * @header: ACPI header to update + * @signature: Table signature to use (4 characters) + */ +void acpi_fill_header(struct acpi_table_header *header, char *signature); + +/** + * acpi_align() - Align the ACPI output pointer to a 16-byte boundary + * + * @ctx: ACPI context + */ +void acpi_align(struct acpi_ctx *ctx); + +/** + * acpi_align64() - Align the ACPI output pointer to a 64-byte boundary + * + * @ctx: ACPI context + */ +void acpi_align64(struct acpi_ctx *ctx); + +/** + * acpi_inc() - Increment the ACPI output pointer by a bit + * + * The pointer is NOT aligned afterwards. + * + * @ctx: ACPI context + * @amount: Amount to increment by + */ +void acpi_inc(struct acpi_ctx *ctx, uint amount); + +/** + * acpi_inc_align() - Increment the ACPI output pointer by a bit and align + * + * The pointer is aligned afterwards to a 16-byte boundary + * + * @ctx: ACPI context + * @amount: Amount to increment by + */ +void acpi_inc_align(struct acpi_ctx *ctx, uint amount); + +/** + * acpi_add_table() - Add a new table to the RSDP and XSDT + * + * @ctx: ACPI context + * @table: Table to add + * @return 0 if OK, -E2BIG if too many tables + */ +int acpi_add_table(struct acpi_ctx *ctx, void *table); + +/** + * acpi_setup_base_tables() - Set up context along with RSDP, RSDT and XSDT + * + * Set up the context with the given start position. Some basic tables are + * always needed, so set them up as well. + * + * @ctx: Context to set up + */ +void acpi_setup_base_tables(struct acpi_ctx *ctx, void *start); + +/** + * acpi_write_rsdp() - Write out an RSDP indicating where the ACPI tables are + * + * @rsdp: Address to write RSDP + * @rsdt: Address of RSDT + * @xsdt: Address of XSDT + */ +void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt, + struct acpi_xsdt *xsdt); + +#endif /* !__ACPI__*/ + +#include + +#endif /* __ACPI_TABLE_H__ */ diff --git a/roms/u-boot/include/acpi/acpigen.h b/roms/u-boot/include/acpi/acpigen.h new file mode 100644 index 000000000..976f4dbb9 --- /dev/null +++ b/roms/u-boot/include/acpi/acpigen.h @@ -0,0 +1,981 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Core ACPI (Advanced Configuration and Power Interface) support + * + * Copyright 2019 Google LLC + * + * Modified from coreboot file acpigen.h + */ + +#ifndef __ACPI_ACPIGEN_H +#define __ACPI_ACPIGEN_H + +#include +#include + +struct acpi_cstate; +struct acpi_ctx; +struct acpi_gen_regaddr; +struct acpi_gpio; + +/* Top 4 bits of the value used to indicate a three-byte length value */ +#define ACPI_PKG_LEN_3_BYTES 0x80 + +#define ACPI_METHOD_NARGS_MASK 0x7 +#define ACPI_METHOD_SERIALIZED_MASK BIT(3) + +#define ACPI_END_TAG 0x79 + +/* ACPI Op/Prefix codes */ +enum { + ZERO_OP = 0x00, + ONE_OP = 0x01, + NAME_OP = 0x08, + BYTE_PREFIX = 0x0a, + WORD_PREFIX = 0x0b, + DWORD_PREFIX = 0x0c, + STRING_PREFIX = 0x0d, + QWORD_PREFIX = 0x0e, + SCOPE_OP = 0x10, + BUFFER_OP = 0x11, + PACKAGE_OP = 0x12, + METHOD_OP = 0x14, + SLEEP_OP = 0x22, + DUAL_NAME_PREFIX = 0x2e, + MULTI_NAME_PREFIX = 0x2f, + DEBUG_OP = 0x31, + EXT_OP_PREFIX = 0x5b, + ROOT_PREFIX = 0x5c, + LOCAL0_OP = 0x60, + LOCAL1_OP = 0x61, + LOCAL2_OP = 0x62, + LOCAL3_OP = 0x63, + LOCAL4_OP = 0x64, + LOCAL5_OP = 0x65, + LOCAL6_OP = 0x66, + LOCAL7_OP = 0x67, + ARG0_OP = 0x68, + ARG1_OP = 0x69, + ARG2_OP = 0x6a, + ARG3_OP = 0x6b, + ARG4_OP = 0x6c, + ARG5_OP = 0x6d, + ARG6_OP = 0x6e, + STORE_OP = 0x70, + AND_OP = 0x7b, + OR_OP = 0x7d, + NOT_OP = 0x80, + DEVICE_OP = 0x82, + PROCESSOR_OP = 0x83, + POWER_RES_OP = 0x84, + NOTIFY_OP = 0x86, + LEQUAL_OP = 0x93, + TO_BUFFER_OP = 0x96, + TO_INTEGER_OP = 0x99, + IF_OP = 0xa0, + ELSE_OP = 0xa1, + RETURN_OP = 0xa4, +}; + +/** + * enum psd_coord - Coordination types for P-states + * + * The type of coordination that exists (hardware) or is required (software) as + * a result of the underlying hardware dependency + */ +enum psd_coord { + SW_ALL = 0xfc, + SW_ANY = 0xfd, + HW_ALL = 0xfe +}; + +/** + * enum csd_coord - Coordination types for C-states + * + * The type of coordination that exists (hardware) or is required (software) as + * a result of the underlying hardware dependency + */ +enum csd_coord { + CSD_HW_ALL = 0xfe, +}; + +/** + * struct acpi_cstate - Information about a C-State + * + * @ctype: C State type (1=C1, 2=C2, 3=C3) + * @latency: Worst-case latency to enter and exit the C State (in uS) + * @power: Average power consumption of the processor when in this C-State (mW) + * @resource: Register to read to place the processor in this state + */ +struct acpi_cstate { + uint ctype; + uint latency; + uint power; + struct acpi_gen_regaddr resource; +}; + +/** + * struct acpi_tstate - Information about a Throttling Supported State + * + * See ACPI v6.3 section 8.4.5.2: _TSS (Throttling Supported States) + * + * @percent: Percent of the core CPU operating frequency that will be + * available when this throttling state is invoked + * @power: Throttling state’s maximum power dissipation (mw) + * @latency: Worst-case latency (uS) that the CPU is unavailable during a + * transition from any throttling state to this throttling state + * @control: Value to be written to the Processor Control Register + * (THROTTLE_CTRL) to initiate a transition to this throttling state + * @status: Value in THROTTLE_STATUS when in this state + */ +struct acpi_tstate { + uint percent; + uint power; + uint latency; + uint control; + uint status; +}; + +/** + * acpigen_get_current() - Get the current ACPI code output pointer + * + * @ctx: ACPI context pointer + * @return output pointer + */ +u8 *acpigen_get_current(struct acpi_ctx *ctx); + +/** + * acpigen_emit_byte() - Emit a byte to the ACPI code + * + * @ctx: ACPI context pointer + * @data: Value to output + */ +void acpigen_emit_byte(struct acpi_ctx *ctx, uint data); + +/** + * acpigen_emit_word() - Emit a 16-bit word to the ACPI code + * + * @ctx: ACPI context pointer + * @data: Value to output + */ +void acpigen_emit_word(struct acpi_ctx *ctx, uint data); + +/** + * acpigen_emit_dword() - Emit a 32-bit 'double word' to the ACPI code + * + * @ctx: ACPI context pointer + * @data: Value to output + */ +void acpigen_emit_dword(struct acpi_ctx *ctx, uint data); + +/** + * acpigen_emit_stream() - Emit a stream of bytes + * + * @ctx: ACPI context pointer + * @data: Data to output + * @size: Size of data in bytes + */ +void acpigen_emit_stream(struct acpi_ctx *ctx, const char *data, int size); + +/** + * acpigen_emit_string() - Emit a string + * + * Emit a string with a null terminator + * + * @ctx: ACPI context pointer + * @str: String to output, or NULL for an empty string + */ +void acpigen_emit_string(struct acpi_ctx *ctx, const char *str); + +/** + * acpigen_write_len_f() - Write a 'forward' length placeholder + * + * This adds space for a length value in the ACPI stream and pushes the current + * position (before the length) on the stack. After calling this you can write + * some data and then call acpigen_pop_len() to update the length value. + * + * Usage: + * + * acpigen_write_len_f() ------\ + * acpigen_write...() | + * acpigen_write...() | + * acpigen_write_len_f() --\ | + * acpigen_write...() | | + * acpigen_write...() | | + * acpigen_pop_len() ------/ | + * acpigen_write...() | + * acpigen_pop_len() ----------/ + * + * See ACPI 6.3 section 20.2.4 Package Length Encoding + * + * This implementation always uses a 3-byte packet length for simplicity. It + * could be adjusted to support other lengths. + * + * @ctx: ACPI context pointer + */ +void acpigen_write_len_f(struct acpi_ctx *ctx); + +/** + * acpigen_pop_len() - Update the previously stacked length placeholder + * + * Call this after the data for the block has been written. It updates the + * top length value in the stack and pops it off. + * + * @ctx: ACPI context pointer + */ +void acpigen_pop_len(struct acpi_ctx *ctx); + +/** + * acpigen_write_package() - Start writing a package + * + * A package collects together a number of elements in the ACPI code. To write + * a package use: + * + * acpigen_write_package(ctx, 3); + * ...write things + * acpigen_pop_len() + * + * If you don't know the number of elements in advance, acpigen_write_package() + * returns a pointer to the value so you can update it later: + * + * char *num_elements = acpigen_write_package(ctx, 0); + * ...write things + * *num_elements += 1; + * ...write things + * *num_elements += 1; + * acpigen_pop_len() + * + * @ctx: ACPI context pointer + * @nr_el: Number of elements (0 if not known) + * @returns pointer to the number of elements, which can be updated by the + * caller if needed + */ +char *acpigen_write_package(struct acpi_ctx *ctx, int nr_el); + +/** + * acpigen_write_byte() - Write a byte + * + * @ctx: ACPI context pointer + * @data: Value to write + */ +void acpigen_write_byte(struct acpi_ctx *ctx, unsigned int data); + +/** + * acpigen_write_word() - Write a word + * + * @ctx: ACPI context pointer + * @data: Value to write + */ +void acpigen_write_word(struct acpi_ctx *ctx, unsigned int data); + +/** + * acpigen_write_dword() - Write a dword + * + * @ctx: ACPI context pointer + * @data: Value to write + */ +void acpigen_write_dword(struct acpi_ctx *ctx, unsigned int data); + +/** + * acpigen_write_qword() - Write a qword + * + * @ctx: ACPI context pointer + * @data: Value to write + */ +void acpigen_write_qword(struct acpi_ctx *ctx, u64 data); + +/** + * acpigen_write_zero() - Write zero + * + * @ctx: ACPI context pointer + */ +void acpigen_write_zero(struct acpi_ctx *ctx); + +/** + * acpigen_write_one() - Write one + * + * @ctx: ACPI context pointer + */ +void acpigen_write_one(struct acpi_ctx *ctx); + +/** + * acpigen_write_integer() - Write an integer + * + * This writes an operation (BYTE_OP, WORD_OP, DWORD_OP, QWORD_OP depending on + * the integer size) and an integer value. Note that WORD means 16 bits in ACPI. + * + * @ctx: ACPI context pointer + * @data: Integer to write + */ +void acpigen_write_integer(struct acpi_ctx *ctx, u64 data); + +/** + * acpigen_write_name_zero() - Write a named zero value + * + * @ctx: ACPI context pointer + * @name: Name of the value + */ +void acpigen_write_name_zero(struct acpi_ctx *ctx, const char *name); + +/** + * acpigen_write_name_one() - Write a named one value + * + * @ctx: ACPI context pointer + * @name: Name of the value + */ +void acpigen_write_name_one(struct acpi_ctx *ctx, const char *name); + +/** + * acpigen_write_name_byte() - Write a named byte value + * + * @ctx: ACPI context pointer + * @name: Name of the value + * @val: Value to write + */ +void acpigen_write_name_byte(struct acpi_ctx *ctx, const char *name, uint val); + +/** + * acpigen_write_name_word() - Write a named word value + * + * @ctx: ACPI context pointer + * @name: Name of the value + * @val: Value to write + */ +void acpigen_write_name_word(struct acpi_ctx *ctx, const char *name, uint val); + +/** + * acpigen_write_name_dword() - Write a named dword value + * + * @ctx: ACPI context pointer + * @name: Name of the value + * @val: Value to write + */ +void acpigen_write_name_dword(struct acpi_ctx *ctx, const char *name, uint val); + +/** + * acpigen_write_name_qword() - Write a named qword value + * + * @ctx: ACPI context pointer + * @name: Name of the value + * @val: Value to write + */ +void acpigen_write_name_qword(struct acpi_ctx *ctx, const char *name, u64 val); + +/** + * acpigen_write_name_integer() - Write a named integer value + * + * @ctx: ACPI context pointer + * @name: Name of the value + * @val: Value to write + */ +void acpigen_write_name_integer(struct acpi_ctx *ctx, const char *name, + u64 val); + +/** + * acpigen_write_name_string() - Write a named string value + * + * @ctx: ACPI context pointer + * @name: Name of the value + * @string: String to write + */ +void acpigen_write_name_string(struct acpi_ctx *ctx, const char *name, + const char *string); + +/** + * acpigen_write_string() - Write a string + * + * This writes a STRING_PREFIX followed by a null-terminated string + * + * @ctx: ACPI context pointer + * @str: String to write + */ +void acpigen_write_string(struct acpi_ctx *ctx, const char *str); + +/** + * acpigen_emit_namestring() - Emit an ACPI name + * + * This writes out an ACPI name or path in the required special format. It does + * not add the NAME_OP prefix. + * + * @ctx: ACPI context pointer + * @namepath: Name / path to emit + */ +void acpigen_emit_namestring(struct acpi_ctx *ctx, const char *namepath); + +/** + * acpigen_write_name() - Write out an ACPI name + * + * This writes out an ACPI name or path in the required special format with a + * NAME_OP prefix. + * + * @ctx: ACPI context pointer + * @namepath: Name / path to emit + */ +void acpigen_write_name(struct acpi_ctx *ctx, const char *namepath); + +/** + * acpigen_write_scope() - Write a scope + * + * @ctx: ACPI context pointer + * @scope: Scope to write (e.g. "\\_SB.ABCD") + */ +void acpigen_write_scope(struct acpi_ctx *ctx, const char *scope); + +/** + * acpigen_write_uuid() - Write a UUID + * + * This writes out a UUID in the format used by ACPI, with a BUFFER_OP prefix. + * + * @ctx: ACPI context pointer + * @uuid: UUID to write in the form aabbccdd-eeff-gghh-iijj-kkllmmnnoopp + * @return 0 if OK, -EINVAL if the format is incorrect + */ +int acpigen_write_uuid(struct acpi_ctx *ctx, const char *uuid); + +/** + * acpigen_emit_ext_op() - Emit an extended op with the EXT_OP_PREFIX prefix + * + * @ctx: ACPI context pointer + * @op: Operation code (e.g. SLEEP_OP) + */ +void acpigen_emit_ext_op(struct acpi_ctx *ctx, uint op); + +/** + * acpigen_write_method() - Write a method header + * + * @ctx: ACPI context pointer + * @name: Method name (4 characters) + * @nargs: Number of method arguments (0 if none) + */ +void acpigen_write_method(struct acpi_ctx *ctx, const char *name, int nargs); + +/** + * acpigen_write_method_serialized() - Write a method header + * + * This sets the 'serialized' flag so that the method is thread-safe + * + * @ctx: ACPI context pointer + * @name: Method name (4 characters) + * @nargs: Number of method arguments (0 if none) + */ +void acpigen_write_method_serialized(struct acpi_ctx *ctx, const char *name, + int nargs); + +/** + * acpigen_write_device() - Write an ACPI device + * + * @ctx: ACPI context pointer + * @name: Device name to write + */ +void acpigen_write_device(struct acpi_ctx *ctx, const char *name); + +/** + * acpigen_write_sta() - Write a _STA method + * + * @ctx: ACPI context pointer + * @status: Status value to return + */ +void acpigen_write_sta(struct acpi_ctx *ctx, uint status); + +/** + * acpigen_write_resourcetemplate_header() - Write a ResourceTemplate header + * + * @ctx: ACPI context pointer + */ +void acpigen_write_resourcetemplate_header(struct acpi_ctx *ctx); + +/** + * acpigen_write_resourcetemplate_footer() - Write a ResourceTemplate footer + * + * @ctx: ACPI context pointer + */ +void acpigen_write_resourcetemplate_footer(struct acpi_ctx *ctx); + +/** + * acpigen_write_register_resource() - Write a register resource + * + * This writes a header, the address information and a footer + * + * @ctx: ACPI context pointer + * @addr: Address to write + */ +void acpigen_write_register_resource(struct acpi_ctx *ctx, + const struct acpi_gen_regaddr *addr); + +/** + * acpigen_write_sleep() - Write a sleep operation + * + * @ctx: ACPI context pointer + * @sleep_ms: Number of milliseconds to sleep for + */ +void acpigen_write_sleep(struct acpi_ctx *ctx, u64 sleep_ms); + +/** + * acpigen_write_store() - Write a store operation + * + * @ctx: ACPI context pointer + */ +void acpigen_write_store(struct acpi_ctx *ctx); + +/** + * acpigen_write_debug_string() - Write a debug string + * + * This writes a debug operation with an associated string + * + * @ctx: ACPI context pointer + * @str: String to write + */ +void acpigen_write_debug_string(struct acpi_ctx *ctx, const char *str); + +/** + * acpigen_write_or() - Write a bitwise OR operation + * + * res = arg1 | arg2 + * + * @ctx: ACPI context pointer + * @arg1: ACPI opcode for operand 1 (e.g. LOCAL0_OP) + * @arg2: ACPI opcode for operand 2 (e.g. LOCAL1_OP) + * @res: ACPI opcode for result (e.g. LOCAL2_OP) + */ +void acpigen_write_or(struct acpi_ctx *ctx, u8 arg1, u8 arg2, u8 res); + +/** + * acpigen_write_and() - Write a bitwise AND operation + * + * res = arg1 & arg2 + * + * @ctx: ACPI context pointer + * @arg1: ACPI opcode for operand 1 (e.g. LOCAL0_OP) + * @arg2: ACPI opcode for operand 2 (e.g. LOCAL1_OP) + * @res: ACPI opcode for result (e.g. LOCAL2_OP) + */ +void acpigen_write_and(struct acpi_ctx *ctx, u8 arg1, u8 arg2, u8 res); + +/** + * acpigen_write_not() - Write a bitwise NOT operation + * + * res = ~arg1 + * + * @ctx: ACPI context pointer + * @arg: ACPI opcode for operand (e.g. LOCAL0_OP) + * @res: ACPI opcode for result (e.g. LOCAL2_OP) + */ +void acpigen_write_not(struct acpi_ctx *ctx, u8 arg, u8 res); + +/** + * acpigen_write_power_res() - Write a power resource + * + * Name (_PRx, Package(One) { name }) + * ... + * PowerResource (name, level, order) + * + * The caller should fill in the rest of the power resource and then call + * acpigen_pop_len() to close it off + * + * @ctx: ACPI context pointer + * @name: Name of power resource (e.g. "PRIC") + * @level: Deepest sleep level that this resource must be kept on (0=S0, 3=S3) + * @order: Order that this must be enabled/disabled (e.g. 0) + * @dev_stats: List of states to define, e.g. {"_PR0", "_PR3"} + * @dev_states_count: Number of dev states + */ +void acpigen_write_power_res(struct acpi_ctx *ctx, const char *name, uint level, + uint order, const char *const dev_states[], + size_t dev_states_count); + +/** + * acpigen_set_enable_tx_gpio() - Emit ACPI code to enable/disable a GPIO + * + * This emits code to either enable to disable a Tx GPIO. It takes account of + * the GPIO polarity. + * + * The code needs access to the DW0 register for the pad being used. This is + * provided by gpio->pin0_addr and ACPI methods must be defined for the board + * which can read and write the pad's DW0 register given this address: + * @dw0_read: takes a single argument, the DW0 address + * returns the DW0 value + * @dw0:write: takes two arguments, the DW0 address and the value to write + * no return value + * + * Example code (-- means comment): + * + * -- Get Pad Configuration DW0 register value + * Method (GPC0, 0x1, Serialized) + * { + * -- Arg0 - GPIO DW0 address + * Store (Arg0, Local0) + * OperationRegion (PDW0, SystemMemory, Local0, 4) + * Field (PDW0, AnyAcc, NoLock, Preserve) { + * TEMP, 32 + * } + * Return (TEMP) + * } + * + * -- Set Pad Configuration DW0 register value + * Method (SPC0, 0x2, Serialized) + * { + * -- Arg0 - GPIO DW0 address + * -- Arg1 - Value for DW0 register + * Store (Arg0, Local0) + * OperationRegion (PDW0, SystemMemory, Local0, 4) + * Field (PDW0, AnyAcc, NoLock, Preserve) { + * TEMP,32 + * } + * Store (Arg1, TEMP) + * } + * + * + * @ctx: ACPI context pointer + * @tx_state_val: Mask to use to toggle the TX state on the GPIO pin, e,g. + * PAD_CFG0_TX_STATE + * @dw0_read: Method name to use to read dw0, e.g. "\\_SB.GPC0" + * @dw0_write: Method name to use to read dw0, e.g. "\\_SB.SPC0" + * @gpio: GPIO to change + * @enable: true to enable GPIO, false to disable + * Returns 0 on success, -ve on error. + */ +int acpigen_set_enable_tx_gpio(struct acpi_ctx *ctx, u32 tx_state_val, + const char *dw0_read, const char *dw0_write, + struct acpi_gpio *gpio, bool enable); + +/** + * acpigen_write_prw() - Write a power resource for wake (_PRW) + * + * @ctx: ACPI context pointer + * @wake: GPE that wakes up the device + * @level: Deepest power system sleeping state that can be entered while still + * providing wake functionality + */ +void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level); + +/** + * acpigen_write_if() - Write an If block + * + * This requires a call to acpigen_pop_len() to complete the block + * + * @ctx: ACPI context pointer + */ +void acpigen_write_if(struct acpi_ctx *ctx); + +/** + * acpigen_write_if_lequal_op_int() - Write comparison between op and integer + * + * Generates ACPI code for checking if operand1 and operand2 are equal + * + * If (Lequal (op, val)) + * + * @ctx: ACPI context pointer + * @op: Operand to check + * @val: Value to check against + */ +void acpigen_write_if_lequal_op_int(struct acpi_ctx *ctx, uint op, u64 val); + +/** + * acpigen_write_else() - Write an Ef block + * + * This requires a call to acpigen_pop_len() to complete the block + * + * @ctx: ACPI context pointer + */ +void acpigen_write_else(struct acpi_ctx *ctx); + +/** + * acpigen_write_to_buffer() - Write a ToBuffer operation + * + * E.g.: to generate: ToBuffer (Arg0, Local0) + * use acpigen_write_to_buffer(ctx, ARG0_OP, LOCAL0_OP) + * + * @ctx: ACPI context pointer + * @src: Source argument + * @dst: Destination argument + */ +void acpigen_write_to_buffer(struct acpi_ctx *ctx, uint src, uint dst); + +/** + * acpigen_write_to_integer() - Write a ToInteger operation + * + * E.g.: to generate: ToInteger (Arg0, Local0) + * use acpigen_write_to_integer(ctx, ARG0_OP, LOCAL0_OP) + * + * @ctx: ACPI context pointer + * @src: Source argument + * @dst: Destination argument + */ +void acpigen_write_to_integer(struct acpi_ctx *ctx, uint src, uint dst); + +/** + * acpigen_write_return_byte_buffer() - Write a return of a byte buffer + * + * @ctx: ACPI context pointer + * @arr: Array of bytes to return + * @size: Number of bytes + */ +void acpigen_write_return_byte_buffer(struct acpi_ctx *ctx, u8 *arr, + size_t size); + +/** + * acpigen_write_return_singleton_buffer() - Write a return of a 1-byte buffer + * + * @ctx: ACPI context pointer + * @arg: Byte to return + */ +void acpigen_write_return_singleton_buffer(struct acpi_ctx *ctx, uint arg); + +/** + * acpigen_write_return_byte() - Write a return of a byte + * + * @ctx: ACPI context pointer + * @arg: Byte to return + */ +void acpigen_write_return_byte(struct acpi_ctx *ctx, uint arg); + +/** + * acpigen_write_dsm_start() - Start a _DSM method + * + * Generate ACPI AML code to start the _DSM method. + * + * The functions need to be called in the correct sequence as below. + * + * Within the region, Local0 and Local1 must be are left + * untouched, but Local2-Local7 can be used + * + * Arguments passed into _DSM method: + * Arg0 = UUID + * Arg1 = Revision + * Arg2 = Function index + * Arg3 = Function-specific arguments + * + * AML code generated looks like this: + * Method (_DSM, 4, Serialized) { -- acpigen_write_dsm_start) + * ToBuffer (Arg0, Local0) + * If (LEqual (Local0, ToUUID(uuid))) { -- acpigen_write_dsm_uuid_start + * ToInteger (Arg2, Local1) + * If (LEqual (Local1, 0)) { -- acpigen_write_dsm_uuid_start_cond + * + * } -- acpigen_write_dsm_uuid_end_cond + * ... + * If (LEqual (Local1, n)) { -- acpigen_write_dsm_uuid_start_cond + * + * } -- acpigen_write_dsm_uuid_end_cond + * Return (Buffer (One) { 0x0 }) + * } -- acpigen_write_dsm_uuid_end + * ... + * If (LEqual (Local0, ToUUID(uuidn))) { + * ... + * } + * Return (Buffer (One) { 0x0 }) -- acpigen_write_dsm_end + * } + * + * @ctx: ACPI context pointer + */ +void acpigen_write_dsm_start(struct acpi_ctx *ctx); + +/** + * acpigen_write_dsm_uuid_start() - Start a new UUID block + * + * This starts generation of code to handle a particular UUID: + * + * If (LEqual (Local0, ToUUID(uuid))) { + * ToInteger (Arg2, Local1) + * + * @ctx: ACPI context pointer + */ +int acpigen_write_dsm_uuid_start(struct acpi_ctx *ctx, const char *uuid); + +/** + * acpigen_write_dsm_uuid_start_cond() - Start a new condition block + * + * This starts generation of condition-checking code to handle a particular + * function: + * + * If (LEqual (Local1, i)) + * + * @ctx: ACPI context pointer + */ +void acpigen_write_dsm_uuid_start_cond(struct acpi_ctx *ctx, int seq); + +/** + * acpigen_write_dsm_uuid_end_cond() - Start a new condition block + * + * This ends generation of condition-checking code to handle a particular + * function: + * + * } + * + * @ctx: ACPI context pointer + */ +void acpigen_write_dsm_uuid_end_cond(struct acpi_ctx *ctx); + +/** + * acpigen_write_dsm_uuid_end() - End a UUID block + * + * This ends generation of code to handle a particular UUID: + * + * Return (Buffer (One) { 0x0 }) + * + * @ctx: ACPI context pointer + */ +void acpigen_write_dsm_uuid_end(struct acpi_ctx *ctx); + +/** + * acpigen_write_dsm_end() - End a _DSM method + * + * This ends generates of the _DSM block: + * + * Return (Buffer (One) { 0x0 }) + * + * @ctx: ACPI context pointer + */ +void acpigen_write_dsm_end(struct acpi_ctx *ctx); + +/** + * acpigen_write_processor() - Write a Processor package + * + * This emits a Processor package header with the required information. The + * caller must complete the information and call acpigen_pop_len() at the end + * + * @ctx: ACPI context pointer + * @cpuindex: CPU number + * @pblock_addr: PBlk system IO address + * @pblock_len: PBlk length + */ +void acpigen_write_processor(struct acpi_ctx *ctx, uint cpuindex, + u32 pblock_addr, uint pblock_len); + +/** + * acpigen_write_processor_package() - Write a package containing the processors + * + * The package containins the name of each processor in the SoC + * + * @ctx: ACPI context pointer + * @name: Package name (.e.g "PPKG") + * @first_core: Number of the first core (e.g. 0) + * @core_count: Number of cores (e.g. 4) + */ +void acpigen_write_processor_package(struct acpi_ctx *ctx, const char *name, + uint first_core, uint core_count); + +/** + * acpigen_write_processor_cnot() - Write a processor notification method + * + * This writes a method that notifies all CPU cores + * + * @ctx: ACPI context pointer + * @num_cores: Number of CPU cores + */ +void acpigen_write_processor_cnot(struct acpi_ctx *ctx, const uint num_cores); + +/** + * acpigen_write_ppc() - generates a function returning max P-states + * + * @ctx: ACPI context pointer + * @num_pstates: Number of pstates to return + */ +void acpigen_write_ppc(struct acpi_ctx *ctx, uint num_pstates); + +/** + * acpigen_write_ppc() - generates a function returning PPCM + * + * This returns the maximum number of supported P-states, as saved in the + * variable PPCM + * + * @ctx: ACPI context pointer + */ +void acpigen_write_ppc_nvs(struct acpi_ctx *ctx); + +/** + * acpigen_write_tpc() - Write a _TPC method that returns the TPC limit + * + * @ctx: ACPI context pointer + * @gnvs_tpc_limit: Variable that holds the TPC limit + */ +void acpigen_write_tpc(struct acpi_ctx *ctx, const char *gnvs_tpc_limit); + +/** + * acpigen_write_pss_package() - Write a PSS package + * + * See ACPI v6.3 section 8.4.6: Processor Performance Control + * + * @ctx: ACPI context pointer + * @corefreq: CPU core frequency in MHz + * @translat: worst-case latency in uS that the CPU is unavailable during a + * transition from any performance state to this performance state + * @busmlat: worst-case latency in microseconds that Bus Masters are prevented + * from accessing memory during a transition from any performance state to + * this performance state + * @control: Value to write to PERF_CTRL to move to this performance state + * @status: Expected PERF_STATUS value when in this state + */ +void acpigen_write_pss_package(struct acpi_ctx *ctx, uint corefreq, uint power, + uint translat, uint busmlat, uint control, + uint status); + +/** + * acpigen_write_psd_package() - Write a PSD package + * + * Writes a P-State dependency package + * + * See ACPI v6.3 section 8.4.6.5: _PSD (P-State Dependency) + * + * @ctx: ACPI context pointer + * @domain: Dependency domain number to which this P state entry belongs + * @numprocs: Number of processors belonging to the domain for this logical + * processor’s P-states + * @coordtype: Coordination type + */ +void acpigen_write_psd_package(struct acpi_ctx *ctx, uint domain, uint numprocs, + enum psd_coord coordtype); + +/** + * acpigen_write_cst_package() - Write a _CST package + * + * See ACPI v6.3 section 8.4.2.1: _CST (C States) + * + * @ctx: ACPI context pointer + * @entry: Array of entries + * @nentries; Number of entries + */ +void acpigen_write_cst_package(struct acpi_ctx *ctx, + const struct acpi_cstate *entry, int nentries); + +/** + * acpigen_write_csd_package() - Write a _CSD Package + * + * See ACPI v6.3 section 8.4.2.2: _CSD (C-State Dependency) + * + * @ctx: ACPI context pointer + * @domain: dependency domain number to which this C state entry belongs + * @numprocs: number of processors belonging to the domain for the particular + * C-state + * @coordtype: Co-ordination type + * @index: Index of the C-State entry in the _CST object for which the + * dependency applies + */ +void acpigen_write_csd_package(struct acpi_ctx *ctx, uint domain, uint numprocs, + enum csd_coord coordtype, uint index); + +/** + * acpigen_write_tss_package() - Write a _TSS package + * + * @ctx: ACPI context pointer + * @entry: Entries to write + * @nentries: Number of entries to write + */ +void acpigen_write_tss_package(struct acpi_ctx *ctx, + struct acpi_tstate *entry, int nentries); + +/** + * acpigen_write_tsd_package() - Write a _TSD package + * + * See ACPI v6.3 section 8.4.5.4: _TSD (T-State Dependency) + * + * @ctx: ACPI context pointer + * @domain: dependency domain number to which this T state entry belongs + * @numprocs: Number of processors belonging to the domain for this logical + * processor’s T-states + * @coordtype: Coordination type + */ +void acpigen_write_tsd_package(struct acpi_ctx *ctx, uint domain, uint numprocs, + enum psd_coord coordtype); + +#endif diff --git a/roms/u-boot/include/adc.h b/roms/u-boot/include/adc.h new file mode 100644 index 000000000..0d1a66690 --- /dev/null +++ b/roms/u-boot/include/adc.h @@ -0,0 +1,308 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak + */ + +#ifndef _ADC_H_ +#define _ADC_H_ + +/* ADC_CHANNEL() - ADC channel bit mask, to select only required channels */ +#define ADC_CHANNEL(x) (1 << x) + +/* The last possible selected channel with 32-bit mask */ +#define ADC_MAX_CHANNEL 31 + +/** + * adc_data_format: define the ADC output data format, can be useful when + * the device's input Voltage range is bipolar. + * - ADC_DATA_FORMAT_BIN - binary offset + * - ADC_DATA_FORMAT_2S - two's complement + * + * Note: Device's driver should fill the 'data_format' field of its uclass's + * platform data using one of the above data format types. + */ +enum adc_data_format { + ADC_DATA_FORMAT_BIN, + ADC_DATA_FORMAT_2S, +}; + +/** + * struct adc_channel - structure to hold channel conversion data. + * Useful to keep the result of a multi-channel conversion output. + * + * @id - channel id + * @data - channel conversion data + */ +struct adc_channel { + int id; + unsigned int data; +}; + +/** + * struct adc_uclass_plat - basic ADC info + * + * Note: The positive/negative reference Voltage is only a name and it doesn't + * provide an information about the value polarity. It is possible, for both + * values to be a negative or positive. For this purpose the uclass's platform + * data provides a bool fields: 'vdd/vss_supply_is_negative'. This is useful, + * since the regulator API returns only a positive Voltage values. + * + * To get the reference Voltage values with polarity, use functions: + * - adc_vdd_value() + * - adc_vss_value() + * Those are useful for some cases of ADC's references, e.g.: + * * Vdd: +3.3V; Vss: -3.3V -> 6.6 Vdiff + * * Vdd: +3.3V; Vss: +0.3V -> 3.0 Vdiff + * * Vdd: +3.3V; Vss: 0.0V -> 3.3 Vdiff + * The last one is usually standard and doesn't require the fdt polarity info. + * + * For more informations read binding info: + * - doc/device-tree-bindings/adc/adc.txt + * + * @data_mask - conversion output data mask + * @data_timeout_us - single channel conversion timeout + * @multidata_timeout_us - multi channel conversion timeout + * @channel_mask - bit mask of available channels [0:31] + * @vdd_supply - positive reference Voltage supply (regulator) + * @vss_supply - negative reference Voltage supply (regulator) + * @vdd_polarity_negative - positive reference Voltage has negative polarity + * @vss_polarity_negative - negative reference Voltage has negative polarity + * @vdd_microvolts - positive reference Voltage value + * @vss_microvolts - negative reference Voltage value + */ +struct adc_uclass_plat { + int data_format; + unsigned int data_mask; + unsigned int data_timeout_us; + unsigned int multidata_timeout_us; + unsigned int channel_mask; + struct udevice *vdd_supply; + struct udevice *vss_supply; + bool vdd_polarity_negative; + bool vss_polarity_negative; + int vdd_microvolts; + int vss_microvolts; +}; + +/** + * struct adc_ops - ADC device operations for single/multi-channel operation. + */ +struct adc_ops { + /** + * start_channel() - start conversion with its default parameters + * for the given channel number. + * + * @dev: ADC device to init + * @channel: analog channel number + * @return: 0 if OK, -ve on error + */ + int (*start_channel)(struct udevice *dev, int channel); + + /** + * start_channels() - start conversion with its default parameters + * for the channel numbers selected by the bit mask. + * + * This is optional, useful when the hardware supports multichannel + * conversion by the single software trigger. + * + * @dev: ADC device to init + * @channel_mask: bit mask of selected analog channels + * @return: 0 if OK, -ve on error + */ + int (*start_channels)(struct udevice *dev, unsigned int channel_mask); + + /** + * channel_data() - get conversion output data for the given channel. + * + * Note: The implementation of this function should only check, that + * the conversion data is available at the call time. If the hardware + * requires some delay to get the data, then this function should + * return with -EBUSY value. The ADC API will call it in a loop, + * until the data is available or the timeout expires. The maximum + * timeout for this operation is defined by the field 'data_timeout_us' + * in ADC uclasses platform data structure. + * + * @dev: ADC device to trigger + * @channel: selected analog channel number + * @data: returned pointer to selected channel's output data + * @return: 0 if OK, -EBUSY if busy, and other negative on error + */ + int (*channel_data)(struct udevice *dev, int channel, + unsigned int *data); + + /** + * channels_data() - get conversion data for the selected channels. + * + * This is optional, useful when multichannel conversion is supported + * by the hardware, by the single software trigger. + * + * For the proper implementation, please look at the 'Note' for the + * above method. The only difference is in used timeout value, which + * is defined by field 'multidata_timeout_us'. + * + * @dev: ADC device to trigger + * @channel_mask: bit mask of selected analog channels + * @channels: returned pointer to array of output data for channels + * selected by the given mask + * @return: 0 if OK, -ve on error + */ + int (*channels_data)(struct udevice *dev, unsigned int channel_mask, + struct adc_channel *channels); + + /** + * stop() - stop conversion of the given ADC device + * + * @dev: ADC device to stop + * @return: 0 if OK, -ve on error + */ + int (*stop)(struct udevice *dev); +}; + +/** + * adc_start_channel() - start conversion for given device/channel and exit. + * + * @dev: ADC device + * @channel: analog channel number + * @return: 0 if OK, -ve on error + */ +int adc_start_channel(struct udevice *dev, int channel); + +/** + * adc_start_channels() - start conversion for given device/channels and exit. + * + * Note: + * To use this function, device must implement method: start_channels(). + * + * @dev: ADC device to start + * @channel_mask: channel selection - a bit mask + * @channel_mask: bit mask of analog channels + * @return: 0 if OK, -ve on error + */ +int adc_start_channels(struct udevice *dev, unsigned int channel_mask); + +/** + * adc_channel_data() - get conversion data for the given device channel number. + * + * @dev: ADC device to read + * @channel: analog channel number + * @data: pointer to returned channel's data + * @return: 0 if OK, -ve on error + */ +int adc_channel_data(struct udevice *dev, int channel, unsigned int *data); + +/** + * adc_channels_data() - get conversion data for the channels selected by mask + * + * Note: + * To use this function, device must implement methods: + * - start_channels() + * - channels_data() + * + * @dev: ADC device to read + * @channel_mask: channel selection - a bit mask + * @channels: pointer to structure array of returned data for each channel + * @return: 0 if OK, -ve on error + */ +int adc_channels_data(struct udevice *dev, unsigned int channel_mask, + struct adc_channel *channels); + +/** + * adc_data_mask() - get data mask (ADC resolution bitmask) for given ADC device + * + * This can be used if adc uclass platform data is filled. + * + * @dev: ADC device to check + * @data_mask: pointer to the returned data bitmask + * @return: 0 if OK, -ve on error + */ +int adc_data_mask(struct udevice *dev, unsigned int *data_mask); + +/** + * adc_channel_mask() - get channel mask for given ADC device + * + * This can be used if adc uclass platform data is filled. + * + * @dev: ADC device to check + * @channel_mask: pointer to the returned channel bitmask + * @return: 0 if OK, -ve on error + */ +int adc_channel_mask(struct udevice *dev, unsigned int *channel_mask); + +/** + * adc_channel_single_shot() - get output data of conversion for the ADC + * device's channel. This function searches for the device with the given name, + * starts the given channel conversion and returns the output data. + * + * Note: To use this function, device must implement metods: + * - start_channel() + * - channel_data() + * + * @name: device's name to search + * @channel: device's input channel to init + * @data: pointer to conversion output data + * @return: 0 if OK, -ve on error + */ +int adc_channel_single_shot(const char *name, int channel, unsigned int *data); + +/** + * adc_channels_single_shot() - get ADC conversion output data for the selected + * device's channels. This function searches for the device by the given name, + * starts the selected channels conversion and returns the output data as array + * of type 'struct adc_channel'. + * + * Note: This function can be used if device implements one of ADC's single + * or multi-channel operation API. If multi-channel operation is not supported, + * then each selected channel is triggered by the sequence start/data in a loop. + * + * @name: device's name to search + * @channel_mask: channel selection - a bit mask + * @channels: pointer to conversion output data for the selected channels + * @return: 0 if OK, -ve on error + */ +int adc_channels_single_shot(const char *name, unsigned int channel_mask, + struct adc_channel *channels); + +/** + * adc_vdd_value() - get the ADC device's positive reference Voltage value + * + * Note: Depending on bool value 'vdd_supply_is_negative' of platform data, + * the returned uV value can be negative, and it's not an error. + * + * @dev: ADC device to check + * @uV: Voltage value with polarization sign (uV) + * @return: 0 on success or -ve on error +*/ +int adc_vdd_value(struct udevice *dev, int *uV); + +/** + * adc_vss_value() - get the ADC device's negative reference Voltage value + * + * Note: Depending on bool value 'vdd_supply_is_negative' of platform data, + * the returned uV value can be negative, and it's not an error. + * + * @dev: ADC device to check + * @uV: Voltage value with polarization sign (uV) + * @return: 0 on success or -ve on error +*/ +int adc_vss_value(struct udevice *dev, int *uV); + +/** + * adc_stop() - stop operation for given ADC device. + * + * @dev: ADC device to stop + * @return: 0 if OK, -ve on error + */ +int adc_stop(struct udevice *dev); + +/** + * adc_raw_to_uV() - converts raw value to microvolts for given ADC device. + * + * @dev: ADC device used from conversion + * @raw: raw value to convert + * @uV: converted value in microvolts + * @return: 0 on success or -ve on error + */ +int adc_raw_to_uV(struct udevice *dev, unsigned int raw, int *uV); + +#endif diff --git a/roms/u-boot/include/addr_map.h b/roms/u-boot/include/addr_map.h new file mode 100644 index 000000000..55d3a6a16 --- /dev/null +++ b/roms/u-boot/include/addr_map.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ADDR_MAP_H +#define __ADDR_MAP_H + +/* + * Copyright 2008 Freescale Semiconductor, Inc. + */ + +#include + +struct addrmap { + phys_addr_t paddr; + phys_size_t size; + unsigned long vaddr; +}; + +extern struct addrmap address_map[CONFIG_SYS_NUM_ADDR_MAP]; + +phys_addr_t addrmap_virt_to_phys(void *vaddr); +void *addrmap_phys_to_virt(phys_addr_t paddr); +void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr, + phys_size_t size, int idx); + +#endif diff --git a/roms/u-boot/include/ahci.h b/roms/u-boot/include/ahci.h new file mode 100644 index 000000000..fb96dd886 --- /dev/null +++ b/roms/u-boot/include/ahci.h @@ -0,0 +1,288 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. + * Author: Jason Jin + * Zhang Wei + */ +#ifndef _AHCI_H_ +#define _AHCI_H_ + +#include + +#define AHCI_PCI_BAR 0x24 +#define AHCI_MAX_SG 56 /* hardware max is 64K */ +#define AHCI_CMD_SLOT_SZ 32 +#define AHCI_MAX_CMD_SLOT 32 +#define AHCI_RX_FIS_SZ 256 +#define AHCI_CMD_TBL_HDR 0x80 +#define AHCI_CMD_TBL_CDB 0x40 +#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16) +#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \ + AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ) +#define AHCI_CMD_ATAPI (1 << 5) +#define AHCI_CMD_WRITE (1 << 6) +#define AHCI_CMD_PREFETCH (1 << 7) +#define AHCI_CMD_RESET (1 << 8) +#define AHCI_CMD_CLR_BUSY (1 << 10) + +#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ + +/* Global controller registers */ +#define HOST_CAP 0x00 /* host capabilities */ +#define HOST_CTL 0x04 /* global host control */ +#define HOST_IRQ_STAT 0x08 /* interrupt status */ +#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ +#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ +#define HOST_CAP2 0x24 /* host capabilities, extended */ + +/* HOST_CTL bits */ +#define HOST_RESET (1 << 0) /* reset controller; self-clear */ +#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */ +#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */ + +/* Registers for each SATA port */ +#define PORT_LST_ADDR 0x00 /* command list DMA addr */ +#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */ +#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */ +#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */ +#define PORT_IRQ_STAT 0x10 /* interrupt status */ +#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */ +#define PORT_CMD 0x18 /* port command */ +#define PORT_TFDATA 0x20 /* taskfile data */ +#define PORT_SIG 0x24 /* device TF signature */ +#define PORT_CMD_ISSUE 0x38 /* command issue */ +#define PORT_SCR 0x28 /* SATA phy register block */ +#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */ +#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */ +#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */ +#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */ + +#ifdef CONFIG_SUNXI_AHCI +#define PORT_P0DMACR 0x70 /* SUNXI specific "DMA register" */ +#endif + +/* PORT_IRQ_{STAT,MASK} bits */ +#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ +#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ +#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ +#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ +#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ +#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ +#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ +#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ + +#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ +#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ +#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ +#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ +#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ +#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ +#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ +#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ +#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ + +#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \ + | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR + +#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \ + | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \ + | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \ + | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \ + | PORT_IRQ_D2H_REG_FIS + +/* PORT_SCR_STAT bits */ +#define PORT_SCR_STAT_DET_MASK 0x3 +#define PORT_SCR_STAT_DET_COMINIT 0x1 +#define PORT_SCR_STAT_DET_PHYRDY 0x3 + +/* PORT_CMD bits */ +#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ +#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ +#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ +#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ +#define PORT_CMD_CLO (1 << 3) /* Command list override */ +#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ +#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ +#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ + +#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ +#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ +#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ + +#define AHCI_MAX_PORTS 32 + +#define ATA_FLAG_SATA (1 << 3) +#define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */ +#define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */ +#define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */ +#define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */ +#define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */ + +struct ahci_cmd_hdr { + u32 opts; + u32 status; + u32 tbl_addr; + u32 tbl_addr_hi; + u32 reserved[4]; +}; + +struct ahci_sg { + u32 addr; + u32 addr_hi; + u32 reserved; + u32 flags_size; +}; + +struct ahci_ioports { + void __iomem *port_mmio; + struct ahci_cmd_hdr *cmd_slot; + struct ahci_sg *cmd_tbl_sg; + ulong cmd_tbl; + u32 rx_fis; +}; + +/** + * struct ahci_uc_priv - information about an AHCI controller + * + * When driver model is used, this is accessible using dev_get_uclass_priv(dev) + * where dev is the controller (although at present it sometimes stands alone). + */ +struct ahci_uc_priv { +#if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI) + /* + * TODO(sjg@chromium.org): Drop this once this structure is only used + * in a driver-model context (i.e. attached to a device with + * dev_get_uclass_priv() + */ + struct udevice *dev; +#else + pci_dev_t dev; +#endif + struct ahci_ioports port[AHCI_MAX_PORTS]; + u16 *ataid[AHCI_MAX_PORTS]; + u32 n_ports; + u32 hard_port_no; + u32 host_flags; + u32 host_set_flags; + void __iomem *mmio_base; + u32 pio_mask; + u32 udma_mask; + u32 flags; + u32 cap; /* cache of HOST_CAP register */ + u32 port_map; /* cache of HOST_PORTS_IMPL reg */ + u32 link_port_map; /*linkup port map*/ +}; + +struct ahci_ops { + /** + * reset() - reset the controller + * + * @dev: Controller to reset + * @return 0 if OK, -ve on error + */ + int (*reset)(struct udevice *dev); + + /** + * port_status() - get the status of a SATA port + * + * @dev: Controller to reset + * @port: Port number to check (0 for first) + * @return 0 if detected, -ENXIO if nothing on port, other -ve on error + */ + int (*port_status)(struct udevice *dev, int port); + + /** + * scan() - scan SATA ports + * + * @dev: Controller to scan + * @return 0 if OK, -ve on error + */ + int (*scan)(struct udevice *dev); +}; + +#define ahci_get_ops(dev) ((struct ahci_ops *)(dev)->driver->ops) + +/** + * sata_reset() - reset the controller + * + * @dev: Controller to reset + * @return 0 if OK, -ve on error + */ +int sata_reset(struct udevice *dev); + +/** + * sata_port_status() - get the status of a SATA port + * + * @dev: Controller to reset + * @port: Port number to check (0 for first) + * @return 0 if detected, -ENXIO if nothin on port, other -ve on error + */ +int sata_dm_port_status(struct udevice *dev, int port); + +/** + * sata_scan() - scan SATA ports + * + * @dev: Controller to scan + * @return 0 if OK, -ve on error + */ +int sata_scan(struct udevice *dev); + +int ahci_init(void __iomem *base); +int ahci_reset(void __iomem *base); + +/** + * ahci_init_one_dm() - set up a single AHCI port + * + * @dev: Controller to init + */ +int ahci_init_one_dm(struct udevice *dev); + +/** + * ahci_start_ports_dm() - start all AHCI ports for a controller + * + * @dev: Controller containing ports to start + */ +int ahci_start_ports_dm(struct udevice *dev); + +/** + * ahci_init_dm() - init AHCI for a controller, finding all ports + * + * @dev: Device to init + */ +int ahci_init_dm(struct udevice *dev, void __iomem *base); + +/** + * ahci_bind_scsi() - bind a new SCSI bus as a child + * + * Note that the SCSI bus device will itself bind block devices + * + * @ahci_dev: AHCI parent device + * @devp: Returns new SCSI bus device + * @return 0 if OK, -ve on error + */ +int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp); + +/** + * ahci_probe_scsi() - probe and scan the attached SCSI bus + * + * Note that the SCSI device will itself bind block devices for any storage + * devices it finds. + * + * @ahci_dev: AHCI parent device + * @base: Base address of AHCI port + * @return 0 if OK, -ve on error + */ +int ahci_probe_scsi(struct udevice *ahci_dev, ulong base); + +/** + * ahci_probe_scsi_pci() - probe and scan the attached SCSI bus on PCI + * + * Note that the SCSI device will itself bind block devices for any storage + * devices it finds. + * + * @ahci_dev: AHCI parent device + * @return 0 if OK, -ve on error + */ +int ahci_probe_scsi_pci(struct udevice *ahci_dev); + +#endif diff --git a/roms/u-boot/include/ali512x.h b/roms/u-boot/include/ali512x.h new file mode 100644 index 000000000..6bb67009c --- /dev/null +++ b/roms/u-boot/include/ali512x.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB . + */ + +#ifndef __ASM_IC_ALI512X_H_ +#define __ASM_IC_ALI512X_H_ + +# define ALI_INDEX 0x3f0 +# define ALI_DATA 0x3f1 + +# define ALI_ENABLED 1 +# define ALI_DISABLED 0 + +# define ALI_UART1 0 +# define ALI_UART2 1 + +/* setup functions */ +void ali512x_init(void); +void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel); +void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel); +void ali512x_set_uart(int enabled, int index, u16 io, u8 irq); +void ali512x_set_rtc(int enabled, u16 io, u8 irq); +void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq); +void ali512x_set_cio(int enabled); + + +/* common I/O functions */ +void ali512x_cio_function(int pin, int special, int inv, int input); +void ali512x_cio_out(int pin, int value); +int ali512x_cio_in(int pin); + +/* misc features */ +void ali512x_set_uart2_irda(int enabled); + +#endif diff --git a/roms/u-boot/include/altera.h b/roms/u-boot/include/altera.h new file mode 100644 index 000000000..946413c66 --- /dev/null +++ b/roms/u-boot/include/altera.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + */ + +#include + +#ifndef _ALTERA_H_ +#define _ALTERA_H_ + +/* + * For the StratixV FPGA programming via SPI, the following + * information is coded in the 32bit cookie: + * Bit 31 ... Bit 0 + * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin + */ +#define FPGA_COOKIE(bus, dev, config, done) \ + (((bus) << 24) | ((dev) << 16) | ((config) << 8) | (done)) +#define COOKIE2SPI_BUS(c) (((c) >> 24) & 0xff) +#define COOKIE2SPI_DEV(c) (((c) >> 16) & 0xff) +#define COOKIE2CONFIG(c) (((c) >> 8) & 0xff) +#define COOKIE2DONE(c) ((c) & 0xff) + +enum altera_iface { + /* insert all new types after this */ + min_altera_iface_type, + /* serial data and external clock */ + passive_serial, + /* parallel data */ + passive_parallel_synchronous, + /* parallel data */ + passive_parallel_asynchronous, + /* serial data w/ internal clock (not used) */ + passive_serial_asynchronous, + /* jtag/tap serial (not used ) */ + altera_jtag_mode, + /* fast passive parallel (FPP) */ + fast_passive_parallel, + /* fast passive parallel with security (FPPS) */ + fast_passive_parallel_security, + /* secure device manager (SDM) mailbox */ + secure_device_manager_mailbox, + /* insert all new types before this */ + max_altera_iface_type, +}; + +enum altera_family { + /* insert all new types after this */ + min_altera_type, + /* ACEX1K Family */ + Altera_ACEX1K, + /* CYCLONII Family */ + Altera_CYC2, + /* StratixII Family */ + Altera_StratixII, + /* StratixV Family */ + Altera_StratixV, + /* SoCFPGA Family */ + Altera_SoCFPGA, + /* Intel FPGA Family with SDM (Secure Device Manager) Mailbox */ + Intel_FPGA_SDM_Mailbox, + + /* Add new models here */ + + /* insert all new types before this */ + max_altera_type, +}; + +typedef struct { + /* part type */ + enum altera_family family; + /* interface type */ + enum altera_iface iface; + /* bytes of data part can accept */ + size_t size; + /* interface function table */ + void *iface_fns; + /* base interface address */ + void *base; + /* implementation specific cookie */ + int cookie; +} Altera_desc; + +/* Generic Altera Functions + *********************************************************************/ +extern int altera_load(Altera_desc *desc, const void *image, size_t size); +extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize); +extern int altera_info(Altera_desc *desc); + +/* Board specific implementation specific function types + *********************************************************************/ +typedef int (*Altera_pre_fn)( int cookie ); +typedef int (*Altera_config_fn)( int assert_config, int flush, int cookie ); +typedef int (*Altera_status_fn)( int cookie ); +typedef int (*Altera_done_fn)( int cookie ); +typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie ); +typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie ); +typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie); +typedef int (*Altera_abort_fn)( int cookie ); +typedef int (*Altera_post_fn)( int cookie ); + +typedef struct { + Altera_pre_fn pre; + Altera_config_fn config; + Altera_status_fn status; + Altera_done_fn done; + Altera_clk_fn clk; + Altera_data_fn data; + Altera_write_fn write; + Altera_abort_fn abort; + Altera_post_fn post; +} altera_board_specific_func; + +#ifdef CONFIG_FPGA_SOCFPGA +int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); +#endif + +#ifdef CONFIG_FPGA_STRATIX_V +int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); +#endif + +#ifdef CONFIG_FPGA_INTEL_SDM_MAILBOX +int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, + size_t rbf_size); +#endif + +#endif /* _ALTERA_H_ */ diff --git a/roms/u-boot/include/andestech/andes_pcu.h b/roms/u-boot/include/andestech/andes_pcu.h new file mode 100644 index 000000000..d24b82d18 --- /dev/null +++ b/roms/u-boot/include/andestech/andes_pcu.h @@ -0,0 +1,354 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 Andes Technology Corp + * Macpaul Lin + */ + +/* + * Andes Power Control Unit + */ +#ifndef __ANDES_PCU_H +#define __ANDES_PCU_H + +#ifndef __ASSEMBLY__ + +struct pcs { + unsigned int cr; /* PCSx Configuration (clock scaling) */ + unsigned int parm; /* PCSx Parameter*/ + unsigned int stat1; /* PCSx Status 1 */ + unsigned int stat2; /* PCSx Stusts 2 */ + unsigned int pdd; /* PCSx PDD */ +}; + +struct andes_pcu { + unsigned int rev; /* 0x00 - PCU Revision */ + unsigned int spinfo; /* 0x04 - Scratch Pad Info */ + unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */ + unsigned int soc_id; /* 0x10 - SoC ID */ + unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */ + unsigned int soc_apb; /* 0x18 - SoC APB configuration */ + unsigned int rsvd2; /* 0x1C */ + unsigned int dcsrcr0; /* 0x20 - Driving Capability + and Slew Rate Control 0 */ + unsigned int dcsrcr1; /* 0x24 - Driving Capability + and Slew Rate Control 1 */ + unsigned int dcsrcr2; /* 0x28 - Driving Capability + and Slew Rate Control 2 */ + unsigned int rsvd3; /* 0x2C */ + unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */ + unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */ + unsigned int dmaes; /* 0x38 - DMA Engine Selection */ + unsigned int rsvd4; /* 0x3C */ + unsigned int oscc; /* 0x40 - OSC Control */ + unsigned int pwmcd; /* 0x44 - PWM Clock divider */ + unsigned int socmisc; /* 0x48 - SoC Misc. */ + unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */ + unsigned int bsmcr; /* 0x80 - BSM Controrl */ + unsigned int bsmst; /* 0x84 - BSM Status */ + unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/ + unsigned int west; /* 0x8C - Wakeup Event Status */ + unsigned int rsttiming; /* 0x90 - Reset Timing */ + unsigned int intr_st; /* 0x94 - PCU Interrupt Status */ + unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */ + struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */ + unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */ + struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */ + unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */ + struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */ + unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */ + struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */ + unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */ + struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */ + unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */ + struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */ + unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */ + struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */ + unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */ + struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */ + unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */ + struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */ + unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */ + unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager + Scratch Pad Memory 0 */ +}; +#endif /* __ASSEMBLY__ */ + +/* + * PCU Revision Register (ro) + */ +#define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff) +#define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff) + +/* + * Scratch Pad Info Register (ro) + */ +#define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff) +#define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf) + +/* + * SoC ID Register (ro) + */ +#define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf) +#define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff) +#define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff) + +/* + * SoC AHB Configuration Register (ro) + */ +#define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) +#define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1) +#define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) +#define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3) +#define ANDES_PCU_SOC_AHB_SPIROM(x) ((x) << 4) +#define ANDES_PCU_SOC_AHB_DDR2C(x) ((x) << 5) +#define ANDES_PCU_SOC_AHB_DDR2MEM(x) ((x) << 6) +#define ANDES_PCU_SOC_AHB_DMAC(x) ((x) << 7) +#define ANDES_PCU_SOC_AHB_DLM2(x) ((x) << 8) +#define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9) +#define ANDES_PCU_SOC_AHB_GMAC(x) ((x) << 12) +#define ANDES_PCU_SOC_AHB_IDE(x) ((x) << 13) +#define ANDES_PCU_SOC_AHB_USBOTG(x) ((x) << 14) +#define ANDES_PCU_SOC_AHB_INTC(x) ((x) << 15) +#define ANDES_PCU_SOC_AHB_LPCIO(x) ((x) << 16) +#define ANDES_PCU_SOC_AHB_LPCREG(x) ((x) << 17) +#define ANDES_PCU_SOC_AHB_PCIIO(x) ((x) << 18) +#define ANDES_PCU_SOC_AHB_PCIMEM(x) ((x) << 19) +#define ANDES_PCU_SOC_AHB_L2CC(x) ((x) << 20) +#define ANDES_PCU_SOC_AHB_AHB2AHBREG(x) ((x) << 27) +#define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x) ((x) << 28) +#define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x) ((x) << 29) +#define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x) ((x) << 30) +#define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x) ((x) << 31) + +/* + * SoC APB Configuration Register (ro) + */ +#define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1) +#define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2) +#define ANDES_PCU_SOC_APB_UART1(x) ((x) << 3) +#define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5) +#define ANDES_PCU_SOC_APB_AC97I2S(x) ((x) << 6) +#define ANDES_PCU_SOC_APB_UART2(x) ((x) << 8) +#define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16) +#define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17) +#define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18) +#define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19) +#define ANDES_PCU_SOC_APB_GPIO(x) ((x) << 20) +#define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22) +#define ANDES_PCU_SOC_APB_PWM(x) ((x) << 23) + +/* + * Driving Capability and Slew Rate Control Register 0 (rw) + */ +#define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0) +#define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8) +#define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12) +#define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16) +#define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20) + +/* + * Driving Capability and Slew Rate Control Register 1 (rw) + */ +#define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0) + +/* + * Driving Capability and Slew Rate Control Register 2 (rw) + */ +#define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0) +#define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4) +#define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8) +#define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12) +#define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16) +#define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20) +#define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24) +#define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28) + +/* + * Multi-function Port Setting Register 0 (rw) + */ +#define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0) +#define ANDES_PCU_MFPSR0_IDEMODE(x) ((x) << 1) +#define ANDES_PCU_MFPSR0_MINI_TC01(x) ((x) << 2) +#define ANDES_PCU_MFPSR0_AHB_DEBUG(x) ((x) << 3) +#define ANDES_PCU_MFPSR0_AHB_TARGET(x) ((x) << 4) +#define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28) +#define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x) ((x) << 31) + +/* + * Multi-function Port Setting Register 1 (rw) + */ +#define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0) +#define ANDES_PCU_MFPSR1_PWM0(x) ((x) << 1) +#define ANDES_PCU_MFPSR1_PWM1(x) ((x) << 2) +#define ANDES_PCU_MFPSR1_AC97CLKOUT(x) ((x) << 3) +#define ANDES_PCU_MFPSR1_PWREN(x) ((x) << 4) +#define ANDES_PCU_MFPSR1_PME(x) ((x) << 5) +#define ANDES_PCU_MFPSR1_I2C(x) ((x) << 6) +#define ANDES_PCU_MFPSR1_UART1(x) ((x) << 7) +#define ANDES_PCU_MFPSR1_UART2(x) ((x) << 8) +#define ANDES_PCU_MFPSR1_SPI(x) ((x) << 9) +#define ANDES_PCU_MFPSR1_SD(x) ((x) << 10) +#define ANDES_PCU_MFPSR1_GPUPLLSRC(x) ((x) << 27) +#define ANDES_PCU_MFPSR1_DVOMODE(x) ((x) << 28) +#define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x) ((x) << 29) +#define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x) ((x) << 30) +#define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x) ((x) << 31) + +/* + * DMA Engine Selection Register (rw) + */ +#define ANDES_PCU_DMAES_AC97RX(x) ((x) << 2) +#define ANDES_PCU_DMAES_AC97TX(x) ((x) << 3) +#define ANDES_PCU_DMAES_UART1RX(x) ((x) << 4) +#define ANDES_PCU_DMAES_UART1TX(x) ((x) << 5) +#define ANDES_PCU_DMAES_UART2RX(x) ((x) << 6) +#define ANDES_PCU_DMAES_UART2TX(x) ((x) << 7) +#define ANDES_PCU_DMAES_SDDMA(x) ((x) << 8) +#define ANDES_PCU_DMAES_CFCDMA(x) ((x) << 9) + +/* + * OSC Control Register (rw) + */ +#define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0) +#define ANDES_PCU_OSCC_OSCH_STABLE(x) ((x) << 1) +#define ANDES_PCU_OSCC_OSCH_TRI(x) ((x) << 2) +#define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4) +#define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6) +#define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8) + +/* + * PWM Clock Divider Register (rw) + */ +#define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0) + +/* + * SoC Misc. Register (rw) + */ +#define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0) +#define ANDES_PCU_SOCMISC_RSCPUB(x) ((x) << 1) +#define ANDES_PCU_SOCMISC_RSPCI(x) ((x) << 2) +#define ANDES_PCU_SOCMISC_USBWAKE(x) ((x) << 3) +#define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4) +#define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6) +#define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x) (((x) << 8) +#define ANDES_PCU_SOCMISC_300MHZSEL(x) (((x) << 9) +#define ANDES_PCU_SOCMISC_DDRDLL_SRST(x) (((x) << 10) +#define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x) (((x) << 11) +#define ANDES_PCU_SOCMISC_DDRDLL_TEST(x) (((x) << 12) +#define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x) (((x) << 13) +#define ANDES_PCU_SOCMISC_ENCPUA(x) (((x) << 14) +#define ANDES_PCU_SOCMISC_ENCPUB(x) (((x) << 15) +#define ANDES_PCU_SOCMISC_PWON_PWBTN(x) (((x) << 16) +#define ANDES_PCU_SOCMISC_PWON_GPIO1(x) (((x) << 17) +#define ANDES_PCU_SOCMISC_PWON_GPIO2(x) (((x) << 18) +#define ANDES_PCU_SOCMISC_PWON_GPIO3(x) (((x) << 19) +#define ANDES_PCU_SOCMISC_PWON_GPIO4(x) (((x) << 20) +#define ANDES_PCU_SOCMISC_PWON_GPIO5(x) (((x) << 21) +#define ANDES_PCU_SOCMISC_PWON_WOL(x) (((x) << 22) +#define ANDES_PCU_SOCMISC_PWON_RTC(x) (((x) << 23) +#define ANDES_PCU_SOCMISC_PWON_RTCALM(x) (((x) << 24) +#define ANDES_PCU_SOCMISC_PWON_XDBGIN(x) (((x) << 25) +#define ANDES_PCU_SOCMISC_PWON_PME(x) (((x) << 26) +#define ANDES_PCU_SOCMISC_PWON_PWFAIL(x) (((x) << 27) +#define ANDES_PCU_SOCMISC_CPUA_SRSTED(x) (((x) << 28) +#define ANDES_PCU_SOCMISC_CPUB_SRSTED(x) (((x) << 29) +#define ANDES_PCU_SOCMISC_WD_RESET(x) (((x) << 30) +#define ANDES_PCU_SOCMISC_HW_RESET(x) (((x) << 31) + +/* + * BSM Control Register (rw) + */ +#define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0) +#define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4) +#define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24) +#define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28) +#define ANDES_PCU_BSMCR_IE(x) ((x) << 31) + +/* + * BSM Status Register + */ +#define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0) +#define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4) +#define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24) +#define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28) + +/* + * Wakeup Event Sensitivity Register (rw) + */ +#define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0) + +/* + * Wakeup Event Status Register (ro) + */ +#define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0) + +/* + * Reset Timing Register + */ +#define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0) +#define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8) +#define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16) +#define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24) + +/* + * PCU Interrupt Status Register + */ +#define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0) +#define ANDES_PCU_INTR_ST_PCS1(x) ((x) << 1) +#define ANDES_PCU_INTR_ST_PCS2(x) ((x) << 2) +#define ANDES_PCU_INTR_ST_PCS3(x) ((x) << 3) +#define ANDES_PCU_INTR_ST_PCS4(x) ((x) << 4) +#define ANDES_PCU_INTR_ST_PCS5(x) ((x) << 5) +#define ANDES_PCU_INTR_ST_PCS6(x) ((x) << 6) +#define ANDES_PCU_INTR_ST_PCS7(x) ((x) << 7) +#define ANDES_PCU_INTR_ST_PCS8(x) ((x) << 8) +#define ANDES_PCU_INTR_ST_PCS9(x) ((x) << 9) + +/* + * PCSx Configuration Register + */ +#define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0) +#define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16) +#define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20) +#define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */ + +/* + * PCSx Parameter Register (rw) + */ +#define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0) +#define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24) +#define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28) +#define ANDES_PCU_PCSX_PARM_IE(x) (((x) << 31) + +/* + * PCSx Status Register 1 + */ +#define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0) +#define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28) + +/* + * PCSx Status Register 2 + */ +#define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0) +#define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24) + +/* + * PCSx PDD Register + * This is reserved for PCS(1-7) + */ +#define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0) +#define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8) +#define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16) +#define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24) + +#define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0) +#define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6) +#define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12) +#define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18) +#define ANDES_PCU_PCS9_PDD_TICKTYPE(x) ((x) << 24) +#define ANDES_PCU_PCS9_PDD_GPU_SRST(x) ((x) << 27) +#define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28) +#define ANDES_PCU_PCS9_PDD_SUS2DRAM(x) ((x) << 30) +#define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x) ((x) << 31) + +#endif /* __ANDES_PCU_H */ diff --git a/roms/u-boot/include/android_ab.h b/roms/u-boot/include/android_ab.h new file mode 100644 index 000000000..0941eb6b9 --- /dev/null +++ b/roms/u-boot/include/android_ab.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (C) 2017 The Android Open Source Project + */ + +#ifndef __ANDROID_AB_H +#define __ANDROID_AB_H + +struct blk_desc; +struct disk_partition; + +/* Android standard boot slot names are 'a', 'b', 'c', ... */ +#define BOOT_SLOT_NAME(slot_num) ('a' + (slot_num)) + +/* Number of slots */ +#define NUM_SLOTS 2 + +/** + * Select the slot where to boot from. + * + * On Android devices with more than one boot slot (multiple copies of the + * kernel and system images) selects which slot should be used to boot from and + * registers the boot attempt. This is used in by the new A/B update model where + * one slot is updated in the background while running from the other slot. If + * the selected slot did not successfully boot in the past, a boot attempt is + * registered before returning from this function so it isn't selected + * indefinitely. + * + * @param[in] dev_desc Place to store the device description pointer + * @param[in] part_info Place to store the partition information + * @return The slot number (>= 0) on success, or a negative on error + */ +int ab_select_slot(struct blk_desc *dev_desc, struct disk_partition *part_info); + +#endif /* __ANDROID_AB_H */ diff --git a/roms/u-boot/include/android_bootloader_message.h b/roms/u-boot/include/android_bootloader_message.h new file mode 100644 index 000000000..286d7ab0f --- /dev/null +++ b/roms/u-boot/include/android_bootloader_message.h @@ -0,0 +1,256 @@ +/* + * This is from the Android Project, + * Repository: https://android.googlesource.com/platform/bootable/recovery + * File: bootloader_message/include/bootloader_message/bootloader_message.h + * Commit: See U-Boot commit description + * + * Copyright (C) 2008 The Android Open Source Project + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __ANDROID_BOOTLOADER_MESSAGE_H +#define __ANDROID_BOOTLOADER_MESSAGE_H + +#ifndef __UBOOT__ +#include +#include +#include +#else +/* compiler.h defines the types that otherwise are included from stdint.h and + * stddef.h + */ +#include +#endif + +// Spaces used by misc partition are as below: +// 0 - 2K For bootloader_message +// 2K - 16K Used by Vendor's bootloader (the 2K - 4K range may be optionally used +// as bootloader_message_ab struct) +// 16K - 64K Used by uncrypt and recovery to store wipe_package for A/B devices +// Note that these offsets are admitted by bootloader,recovery and uncrypt, so they +// are not configurable without changing all of them. +static const size_t BOOTLOADER_MESSAGE_OFFSET_IN_MISC = 0; +static const size_t WIPE_PACKAGE_OFFSET_IN_MISC = 16 * 1024; + +/* Bootloader Message (2-KiB) + * + * This structure describes the content of a block in flash + * that is used for recovery and the bootloader to talk to + * each other. + * + * The command field is updated by linux when it wants to + * reboot into recovery or to update radio or bootloader firmware. + * It is also updated by the bootloader when firmware update + * is complete (to boot into recovery for any final cleanup) + * + * The status field was used by the bootloader after the completion + * of an "update-radio" or "update-hboot" command, which has been + * deprecated since Froyo. + * + * The recovery field is only written by linux and used + * for the system to send a message to recovery or the + * other way around. + * + * The stage field is written by packages which restart themselves + * multiple times, so that the UI can reflect which invocation of the + * package it is. If the value is of the format "#/#" (eg, "1/3"), + * the UI will add a simple indicator of that status. + * + * We used to have slot_suffix field for A/B boot control metadata in + * this struct, which gets unintentionally cleared by recovery or + * uncrypt. Move it into struct bootloader_message_ab to avoid the + * issue. + */ +struct bootloader_message { + char command[32]; + char status[32]; + char recovery[768]; + + // The 'recovery' field used to be 1024 bytes. It has only ever + // been used to store the recovery command line, so 768 bytes + // should be plenty. We carve off the last 256 bytes to store the + // stage string (for multistage packages) and possible future + // expansion. + char stage[32]; + + // The 'reserved' field used to be 224 bytes when it was initially + // carved off from the 1024-byte recovery field. Bump it up to + // 1184-byte so that the entire bootloader_message struct rounds up + // to 2048-byte. + char reserved[1184]; +}; + +/** + * We must be cautious when changing the bootloader_message struct size, + * because A/B-specific fields may end up with different offsets. + */ +#ifndef __UBOOT__ +#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus) +static_assert(sizeof(struct bootloader_message) == 2048, + "struct bootloader_message size changes, which may break A/B devices"); +#endif +#endif /* __UBOOT__ */ + +/** + * The A/B-specific bootloader message structure (4-KiB). + * + * We separate A/B boot control metadata from the regular bootloader + * message struct and keep it here. Everything that's A/B-specific + * stays after struct bootloader_message, which should be managed by + * the A/B-bootloader or boot control HAL. + * + * The slot_suffix field is used for A/B implementations where the + * bootloader does not set the androidboot.ro.boot.slot_suffix kernel + * commandline parameter. This is used by fs_mgr to mount /system and + * other partitions with the slotselect flag set in fstab. A/B + * implementations are free to use all 32 bytes and may store private + * data past the first NUL-byte in this field. It is encouraged, but + * not mandatory, to use 'struct bootloader_control' described below. + * + * The update_channel field is used to store the Omaha update channel + * if update_engine is compiled with Omaha support. + */ +struct bootloader_message_ab { + struct bootloader_message message; + char slot_suffix[32]; + char update_channel[128]; + + // Round up the entire struct to 4096-byte. + char reserved[1888]; +}; + +/** + * Be cautious about the struct size change, in case we put anything post + * bootloader_message_ab struct (b/29159185). + */ +#ifndef __UBOOT__ +#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus) +static_assert(sizeof(struct bootloader_message_ab) == 4096, + "struct bootloader_message_ab size changes"); +#endif +#endif /* __UBOOT__ */ + +#define BOOT_CTRL_MAGIC 0x42414342 /* Bootloader Control AB */ +#define BOOT_CTRL_VERSION 1 + +struct slot_metadata { + // Slot priority with 15 meaning highest priority, 1 lowest + // priority and 0 the slot is unbootable. + uint8_t priority : 4; + // Number of times left attempting to boot this slot. + uint8_t tries_remaining : 3; + // 1 if this slot has booted successfully, 0 otherwise. + uint8_t successful_boot : 1; + // 1 if this slot is corrupted from a dm-verity corruption, 0 + // otherwise. + uint8_t verity_corrupted : 1; + // Reserved for further use. + uint8_t reserved : 7; +} __attribute__((packed)); + +/* Bootloader Control AB + * + * This struct can be used to manage A/B metadata. It is designed to + * be put in the 'slot_suffix' field of the 'bootloader_message' + * structure described above. It is encouraged to use the + * 'bootloader_control' structure to store the A/B metadata, but not + * mandatory. + */ +struct bootloader_control { + // NUL terminated active slot suffix. + char slot_suffix[4]; + // Bootloader Control AB magic number (see BOOT_CTRL_MAGIC). + uint32_t magic; + // Version of struct being used (see BOOT_CTRL_VERSION). + uint8_t version; + // Number of slots being managed. + uint8_t nb_slot : 3; + // Number of times left attempting to boot recovery. + uint8_t recovery_tries_remaining : 3; + // Ensure 4-bytes alignment for slot_info field. + uint8_t reserved0[2]; + // Per-slot information. Up to 4 slots. + struct slot_metadata slot_info[4]; + // Reserved for further use. + uint8_t reserved1[8]; + // CRC32 of all 28 bytes preceding this field (little endian + // format). + uint32_t crc32_le; +} __attribute__((packed)); + +#ifndef __UBOOT__ +#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus) +static_assert(sizeof(struct bootloader_control) == + sizeof(((struct bootloader_message_ab *)0)->slot_suffix), + "struct bootloader_control has wrong size"); +#endif +#endif /* __UBOOT__ */ + +#ifndef __UBOOT__ +#ifdef __cplusplus + +#include +#include + +// Return the block device name for the bootloader message partition and waits +// for the device for up to 10 seconds. In case of error returns the empty +// string. +std::string get_bootloader_message_blk_device(std::string* err); + +// Read bootloader message into boot. Error message will be set in err. +bool read_bootloader_message(bootloader_message* boot, std::string* err); + +// Read bootloader message from the specified misc device into boot. +bool read_bootloader_message_from(bootloader_message* boot, const std::string& misc_blk_device, + std::string* err); + +// Write bootloader message to BCB. +bool write_bootloader_message(const bootloader_message& boot, std::string* err); + +// Write bootloader message to the specified BCB device. +bool write_bootloader_message_to(const bootloader_message& boot, + const std::string& misc_blk_device, std::string* err); + +// Write bootloader message (boots into recovery with the options) to BCB. Will +// set the command and recovery fields, and reset the rest. +bool write_bootloader_message(const std::vector& options, std::string* err); + +// Write bootloader message (boots into recovery with the options) to the specific BCB device. Will +// set the command and recovery fields, and reset the rest. +bool write_bootloader_message_to(const std::vector& options, + const std::string& misc_blk_device, std::string* err); + +// Update bootloader message (boots into recovery with the options) to BCB. Will +// only update the command and recovery fields. +bool update_bootloader_message(const std::vector& options, std::string* err); + +// Update bootloader message (boots into recovery with the |options|) in |boot|. Will only update +// the command and recovery fields. +bool update_bootloader_message_in_struct(bootloader_message* boot, + const std::vector& options); + +// Clear BCB. +bool clear_bootloader_message(std::string* err); + +// Writes the reboot-bootloader reboot reason to the bootloader_message. +bool write_reboot_bootloader(std::string* err); + +// Read the wipe package from BCB (from offset WIPE_PACKAGE_OFFSET_IN_MISC). +bool read_wipe_package(std::string* package_data, size_t size, std::string* err); + +// Write the wipe package into BCB (to offset WIPE_PACKAGE_OFFSET_IN_MISC). +bool write_wipe_package(const std::string& package_data, std::string* err); + +#else + +#include + +// C Interface. +bool write_bootloader_message(const char* options); +bool write_reboot_bootloader(void); + +#endif // ifdef __cplusplus +#endif /* __UBOOT__ */ + +#endif /* __ANDROID_BOOTLOADER_MESSAGE_H */ diff --git a/roms/u-boot/include/android_image.h b/roms/u-boot/include/android_image.h new file mode 100644 index 000000000..54d25af06 --- /dev/null +++ b/roms/u-boot/include/android_image.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * This is from the Android Project, + * Repository: https://android.googlesource.com/platform/system/tools/mkbootimg + * File: include/bootimg/bootimg.h + * Commit: e55998a0f2b61b685d5eb4a486ca3a0c680b1a2f + * + * Copyright (C) 2007 The Android Open Source Project + */ + +#ifndef _ANDROID_IMAGE_H_ +#define _ANDROID_IMAGE_H_ + +#include +#include + +#define ANDR_BOOT_MAGIC "ANDROID!" +#define ANDR_BOOT_MAGIC_SIZE 8 +#define ANDR_BOOT_NAME_SIZE 16 +#define ANDR_BOOT_ARGS_SIZE 512 +#define ANDR_BOOT_EXTRA_ARGS_SIZE 1024 + +/* The bootloader expects the structure of andr_img_hdr with header + * version 0 to be as follows: */ +struct andr_img_hdr { + /* Must be ANDR_BOOT_MAGIC. */ + char magic[ANDR_BOOT_MAGIC_SIZE]; + + u32 kernel_size; /* size in bytes */ + u32 kernel_addr; /* physical load addr */ + + u32 ramdisk_size; /* size in bytes */ + u32 ramdisk_addr; /* physical load addr */ + + u32 second_size; /* size in bytes */ + u32 second_addr; /* physical load addr */ + + u32 tags_addr; /* physical addr for kernel tags */ + u32 page_size; /* flash page size we assume */ + + /* Version of the boot image header. */ + u32 header_version; + + /* Operating system version and security patch level. + * For version "A.B.C" and patch level "Y-M-D": + * (7 bits for each of A, B, C; 7 bits for (Y-2000), 4 bits for M) + * os_version = A[31:25] B[24:18] C[17:11] (Y-2000)[10:4] M[3:0] */ + u32 os_version; + + char name[ANDR_BOOT_NAME_SIZE]; /* asciiz product name */ + + char cmdline[ANDR_BOOT_ARGS_SIZE]; + + u32 id[8]; /* timestamp / checksum / sha1 / etc */ + + /* Supplemental command line data; kept here to maintain + * binary compatibility with older versions of mkbootimg. */ + char extra_cmdline[ANDR_BOOT_EXTRA_ARGS_SIZE]; + + /* Fields in boot_img_hdr_v1 and newer. */ + u32 recovery_dtbo_size; /* size in bytes for recovery DTBO/ACPIO image */ + u64 recovery_dtbo_offset; /* offset to recovery dtbo/acpio in boot image */ + u32 header_size; + + /* Fields in boot_img_hdr_v2 and newer. */ + u32 dtb_size; /* size in bytes for DTB image */ + u64 dtb_addr; /* physical load address for DTB image */ +} __attribute__((packed)); + +/* When a boot header is of version 0, the structure of boot image is as + * follows: + * + * +-----------------+ + * | boot header | 1 page + * +-----------------+ + * | kernel | n pages + * +-----------------+ + * | ramdisk | m pages + * +-----------------+ + * | second stage | o pages + * +-----------------+ + * + * n = (kernel_size + page_size - 1) / page_size + * m = (ramdisk_size + page_size - 1) / page_size + * o = (second_size + page_size - 1) / page_size + * + * 0. all entities are page_size aligned in flash + * 1. kernel and ramdisk are required (size != 0) + * 2. second is optional (second_size == 0 -> no second) + * 3. load each element (kernel, ramdisk, second) at + * the specified physical address (kernel_addr, etc) + * 4. prepare tags at tag_addr. kernel_args[] is + * appended to the kernel commandline in the tags. + * 5. r0 = 0, r1 = MACHINE_TYPE, r2 = tags_addr + * 6. if second_size != 0: jump to second_addr + * else: jump to kernel_addr + */ + +/* When the boot image header has a version of 2, the structure of the boot + * image is as follows: + * + * +---------------------+ + * | boot header | 1 page + * +---------------------+ + * | kernel | n pages + * +---------------------+ + * | ramdisk | m pages + * +---------------------+ + * | second stage | o pages + * +---------------------+ + * | recovery dtbo/acpio | p pages + * +---------------------+ + * | dtb | q pages + * +---------------------+ + * + * n = (kernel_size + page_size - 1) / page_size + * m = (ramdisk_size + page_size - 1) / page_size + * o = (second_size + page_size - 1) / page_size + * p = (recovery_dtbo_size + page_size - 1) / page_size + * q = (dtb_size + page_size - 1) / page_size + * + * 0. all entities are page_size aligned in flash + * 1. kernel, ramdisk and DTB are required (size != 0) + * 2. recovery_dtbo/recovery_acpio is required for recovery.img in non-A/B + * devices(recovery_dtbo_size != 0) + * 3. second is optional (second_size == 0 -> no second) + * 4. load each element (kernel, ramdisk, second, dtb) at + * the specified physical address (kernel_addr, etc) + * 5. If booting to recovery mode in a non-A/B device, extract recovery + * dtbo/acpio and apply the correct set of overlays on the base device tree + * depending on the hardware/product revision. + * 6. prepare tags at tag_addr. kernel_args[] is + * appended to the kernel commandline in the tags. + * 7. r0 = 0, r1 = MACHINE_TYPE, r2 = tags_addr + * 8. if second_size != 0: jump to second_addr + * else: jump to kernel_addr + */ + +#endif diff --git a/roms/u-boot/include/ansi.h b/roms/u-boot/include/ansi.h new file mode 100644 index 000000000..af1a3712c --- /dev/null +++ b/roms/u-boot/include/ansi.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Pali Rohár + */ + +/* + * ANSI terminal + */ + +#define ANSI_CURSOR_UP "\e[%dA" +#define ANSI_CURSOR_DOWN "\e[%dB" +#define ANSI_CURSOR_FORWARD "\e[%dC" +#define ANSI_CURSOR_BACK "\e[%dD" +#define ANSI_CURSOR_NEXTLINE "\e[%dE" +#define ANSI_CURSOR_PREVIOUSLINE "\e[%dF" +#define ANSI_CURSOR_COLUMN "\e[%dG" +#define ANSI_CURSOR_POSITION "\e[%d;%dH" +#define ANSI_CURSOR_SHOW "\e[?25h" +#define ANSI_CURSOR_HIDE "\e[?25l" +#define ANSI_CLEAR_CONSOLE "\e[2J" +#define ANSI_CLEAR_LINE_TO_END "\e[0K" +#define ANSI_CLEAR_LINE "\e[2K" +#define ANSI_COLOR_RESET "\e[0m" +#define ANSI_COLOR_REVERSE "\e[7m" diff --git a/roms/u-boot/include/api.h b/roms/u-boot/include/api.h new file mode 100644 index 000000000..83412a7c8 --- /dev/null +++ b/roms/u-boot/include/api.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2017 Google, Inc + * Written by Simon Glass + */ + +#ifndef __API_H +#define __API_H + +/** + * api_init() - Initialize API for external applications + * + * Initialize API for external (standalone) applications running on top of + * U-Boot. It is called during the generic post-relocation init sequence. + * + * Return: 0 if OK + */ +int api_init(void); + +#endif diff --git a/roms/u-boot/include/api_public.h b/roms/u-boot/include/api_public.h new file mode 100644 index 000000000..5a4465ea8 --- /dev/null +++ b/roms/u-boot/include/api_public.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-2-Clause */ +/* + * (C) Copyright 2007-2008 Semihalf + * + * Written by: Rafal Jaworowski + */ + +#ifndef _API_PUBLIC_H_ +#define _API_PUBLIC_H_ + +#define API_EINVAL 1 /* invalid argument(s) */ +#define API_ENODEV 2 /* no device */ +#define API_ENOMEM 3 /* no memory */ +#define API_EBUSY 4 /* busy, occupied etc. */ +#define API_EIO 5 /* I/O error */ +#define API_ESYSC 6 /* syscall error */ + +typedef int (*scp_t)(int, int *, ...); + +#define API_SIG_VERSION 1 +#define API_SIG_MAGIC "UBootAPI" +#define API_SIG_MAGLEN 8 + +struct api_signature { + char magic[API_SIG_MAGLEN]; /* magic string */ + uint16_t version; /* API version */ + uint32_t checksum; /* checksum of this sig struct */ + scp_t syscall; /* entry point to the API */ +}; + +enum { + API_RSVD = 0, + API_GETC, + API_PUTC, + API_TSTC, + API_PUTS, + API_RESET, + API_GET_SYS_INFO, + API_UDELAY, + API_GET_TIMER, + API_DEV_ENUM, + API_DEV_OPEN, + API_DEV_CLOSE, + API_DEV_READ, + API_DEV_WRITE, + API_ENV_ENUM, + API_ENV_GET, + API_ENV_SET, + API_DISPLAY_GET_INFO, + API_DISPLAY_DRAW_BITMAP, + API_DISPLAY_CLEAR, + API_MAXCALL +}; + +#define MR_ATTR_FLASH 0x0001 +#define MR_ATTR_DRAM 0x0002 +#define MR_ATTR_SRAM 0x0003 + +struct mem_region { + unsigned long start; + unsigned long size; + int flags; +}; + +struct sys_info { + unsigned long clk_bus; + unsigned long clk_cpu; + unsigned long bar; + struct mem_region *mr; + int mr_no; /* number of memory regions */ +}; + +/* + * FIXME: Previously this code was: + * + * #undef CONFIG_SYS_64BIT_LBA + * #ifdef CONFIG_SYS_64BIT_LBA + * typedef u_int64_t lbasize_t; + * #else + * typedef unsigned long lbasize_t; + * #endif + * + * But we cannot just undefine CONFIG_SYS_64BIT_LBA, because then in + * api/api_storage.c the type signature of lbaint_t will be different if + * CONFIG_SYS_64BIT_LBA is enabled for the board, which can result in various + * bugs. + * So simply define lbasize_t as an unsigned long, since this was what was done + * anyway for at least 13 years, but don't undefine CONFIG_SYS_64BIT_LBA. + */ +typedef unsigned long lbasize_t; + +typedef unsigned long lbastart_t; + +#define DEV_TYP_NONE 0x0000 +#define DEV_TYP_NET 0x0001 + +#define DEV_TYP_STOR 0x0002 +#define DT_STOR_IDE 0x0010 +#define DT_STOR_SCSI 0x0020 +#define DT_STOR_USB 0x0040 +#define DT_STOR_MMC 0x0080 +#define DT_STOR_SATA 0x0100 + +#define DEV_STA_CLOSED 0x0000 /* invalid, closed */ +#define DEV_STA_OPEN 0x0001 /* open i.e. active */ + +struct device_info { + int type; + void *cookie; + + union { + struct { + lbasize_t block_count; /* no of blocks */ + unsigned long block_size; /* size of one block */ + } storage; + + struct { + unsigned char hwaddr[6]; + } net; + } info; +#define di_stor info.storage +#define di_net info.net + + int state; +}; + +#define DISPLAY_TYPE_LCD 0x0001 +#define DISPLAY_TYPE_VIDEO 0x0002 + +struct display_info { + int type; + /* screen size in pixels */ + int pixel_width; + int pixel_height; + /* screen size in rows and columns of text */ + int screen_rows; + int screen_cols; +}; + +#endif /* _API_PUBLIC_H_ */ diff --git a/roms/u-boot/include/armcoremodule.h b/roms/u-boot/include/armcoremodule.h new file mode 100644 index 000000000..613b88427 --- /dev/null +++ b/roms/u-boot/include/armcoremodule.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2005 + * ARM Ltd. + * Peter Pearse, + * Configuration for ARM Core Modules. + * No standalonw port yet available + * - this file is included by both integratorap.h & integratorcp.h + */ + +#ifndef __ARMCOREMODULE_H +#define __ARMCOREMODULE_H + +#define CM_BASE 0x10000000 + +/* CM registers common to all CMs */ +/* Note that observed values after reboot into the ARM Boot Monitor + have been used as defaults, rather than the POR values */ +#define OS_CTRL 0x0000000C +#define CMMASK_REMAP 0x00000005 /* set remap & led */ +#define CMMASK_RESET 0x00000008 +#define OS_LOCK 0x00000014 +#define CMVAL_LOCK1 0x0000A000 /* locking value */ +#define CMVAL_LOCK2 0x0000005F /* locking value */ +#define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */ +#define OS_SDRAM 0x00000020 +#define OS_INIT 0x00000024 +#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */ +#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */ +#define CMMASK_LOWVEC 0x00000000 /* vectors @ 0x00000000 */ +#define CMMASK_LE 0xFFFFFFF7 /* little endian */ +#define CMMASK_CMxx6_COMMON 0x00000013 /* Common value for CMxx6 */ + /* - observed reset value of */ + /* CM926EJ-S */ + /* CM1136-EJ-S */ + +#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) +#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual */ + /* - PLL test clock bypassed */ + /* - bus clock ratio 2 */ + /* - little endian */ + /* - vectors at zero */ +#endif /* CM1022xx */ + +/* Determine CM characteristics */ + +#undef CONFIG_CM_MULTIPLE_SSRAM +#undef CONFIG_CM_SPD_DETECT +#undef CONFIG_CM_REMAP +#undef CONFIG_CM_INIT +#undef CONFIG_CM_TCRAM + +#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S) +#define CONFIG_CM_MULTIPLE_SSRAM /* CM has multiple SSRAM mapping */ +#endif + +/* Excalibur core module has reduced functionality */ +#ifndef CONFIG_CM922T_XA10 +#define CONFIG_CM_SPD_DETECT /* CM supports SPD query */ +#define OS_SPD 0x00000100 /* Address of SPD data */ +#define CONFIG_CM_REMAP /* CM supports remapping */ +#define CONFIG_CM_INIT /* CM has initialization reg */ +#endif /* NOT EXCALIBUR */ + +#if defined(CONFIG_CM926EJ_S) || defined (CONFIG_CM946E_S) || \ + defined(CONFIG_CM966E_S) || defined (CONFIG_CM1026EJ_S) || \ + defined(CONFIG_CM1136JF_S) +#define CONFIG_CM_TCRAM /* CM has TCRAM */ +#endif + +#ifdef CONFIG_CM_SPD_DETECT +#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */ +#endif + +#endif /* __ARMCOREMODULE_H */ diff --git a/roms/u-boot/include/asm-generic/atomic-long.h b/roms/u-boot/include/asm-generic/atomic-long.h new file mode 100644 index 000000000..32f288b70 --- /dev/null +++ b/roms/u-boot/include/asm-generic/atomic-long.h @@ -0,0 +1,262 @@ +#ifndef _ASM_GENERIC_ATOMIC_LONG_H +#define _ASM_GENERIC_ATOMIC_LONG_H +/* + * Copyright (C) 2005 Silicon Graphics, Inc. + * Christoph Lameter + * + * Allows to provide arch independent atomic definitions without the need to + * edit all arch specific atomic.h files. + */ + +#include + +/* + * Suppport for atomic_long_t + * + * Casts for parameters are avoided for existing atomic functions in order to + * avoid issues with cast-as-lval under gcc 4.x and other limitations that the + * macros of a platform may have. + */ + +#if BITS_PER_LONG == 64 + +typedef atomic64_t atomic_long_t; + +#define ATOMIC_LONG_INIT(i) ATOMIC64_INIT(i) + +static inline long atomic_long_read(atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return (long)atomic64_read(v); +} + +static inline void atomic_long_set(atomic_long_t *l, long i) +{ + atomic64_t *v = (atomic64_t *)l; + + atomic64_set(v, i); +} + +static inline void atomic_long_inc(atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + atomic64_inc(v); +} + +static inline void atomic_long_dec(atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + atomic64_dec(v); +} + +static inline void atomic_long_add(long i, atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + atomic64_add(i, v); +} + +static inline void atomic_long_sub(long i, atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + atomic64_sub(i, v); +} + +#ifndef __UBOOT__ +static inline int atomic_long_sub_and_test(long i, atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return atomic64_sub_and_test(i, v); +} + +static inline int atomic_long_dec_and_test(atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return atomic64_dec_and_test(v); +} + +static inline int atomic_long_inc_and_test(atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return atomic64_inc_and_test(v); +} + +static inline int atomic_long_add_negative(long i, atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return atomic64_add_negative(i, v); +} + +static inline long atomic_long_add_return(long i, atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return (long)atomic64_add_return(i, v); +} + +static inline long atomic_long_sub_return(long i, atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return (long)atomic64_sub_return(i, v); +} + +static inline long atomic_long_inc_return(atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return (long)atomic64_inc_return(v); +} + +static inline long atomic_long_dec_return(atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return (long)atomic64_dec_return(v); +} + +static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u) +{ + atomic64_t *v = (atomic64_t *)l; + + return (long)atomic64_add_unless(v, a, u); +} + +#define atomic_long_inc_not_zero(l) atomic64_inc_not_zero((atomic64_t *)(l)) + +#define atomic_long_cmpxchg(l, old, new) \ + (atomic64_cmpxchg((atomic64_t *)(l), (old), (new))) +#define atomic_long_xchg(v, new) \ + (atomic64_xchg((atomic64_t *)(v), (new))) +#endif /* __UBOOT__ */ + +#else /* BITS_PER_LONG == 64 */ + +typedef atomic_t atomic_long_t; + +#define ATOMIC_LONG_INIT(i) ATOMIC_INIT(i) +static inline long atomic_long_read(atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return (long)atomic_read(v); +} + +static inline void atomic_long_set(atomic_long_t *l, long i) +{ + atomic_t *v = (atomic_t *)l; + + atomic_set(v, i); +} + +static inline void atomic_long_inc(atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + atomic_inc(v); +} + +static inline void atomic_long_dec(atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + atomic_dec(v); +} + +static inline void atomic_long_add(long i, atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + atomic_add(i, v); +} + +static inline void atomic_long_sub(long i, atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + atomic_sub(i, v); +} + +#ifndef __UBOOT__ +static inline int atomic_long_sub_and_test(long i, atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return atomic_sub_and_test(i, v); +} + +static inline int atomic_long_dec_and_test(atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return atomic_dec_and_test(v); +} + +static inline int atomic_long_inc_and_test(atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return atomic_inc_and_test(v); +} + +static inline int atomic_long_add_negative(long i, atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return atomic_add_negative(i, v); +} + +static inline long atomic_long_add_return(long i, atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return (long)atomic_add_return(i, v); +} + +static inline long atomic_long_sub_return(long i, atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return (long)atomic_sub_return(i, v); +} + +static inline long atomic_long_inc_return(atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return (long)atomic_inc_return(v); +} + +static inline long atomic_long_dec_return(atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return (long)atomic_dec_return(v); +} + +static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u) +{ + atomic_t *v = (atomic_t *)l; + + return (long)atomic_add_unless(v, a, u); +} + +#define atomic_long_inc_not_zero(l) atomic_inc_not_zero((atomic_t *)(l)) + +#define atomic_long_cmpxchg(l, old, new) \ + (atomic_cmpxchg((atomic_t *)(l), (old), (new))) +#define atomic_long_xchg(v, new) \ + (atomic_xchg((atomic_t *)(v), (new))) +#endif /* __UBOOT__ */ + +#endif /* BITS_PER_LONG == 64 */ + +#endif /* _ASM_GENERIC_ATOMIC_LONG_H */ diff --git a/roms/u-boot/include/asm-generic/atomic.h b/roms/u-boot/include/asm-generic/atomic.h new file mode 100644 index 000000000..94d074719 --- /dev/null +++ b/roms/u-boot/include/asm-generic/atomic.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _ASM_GENERIC_ATOMIC_H +#define _ASM_GENERIC_ATOMIC_H + +typedef struct { volatile int counter; } atomic_t; +#if BITS_PER_LONG == 32 +typedef struct { volatile long long counter; } atomic64_t; +#else /* BIT_PER_LONG == 32 */ +typedef struct { volatile long counter; } atomic64_t; +#endif + +#define ATOMIC_INIT(i) { (i) } + +#define atomic_read(v) ((v)->counter) +#define atomic_set(v, i) ((v)->counter = (i)) +#define atomic64_read(v) atomic_read(v) +#define atomic64_set(v, i) atomic_set(v, i) + +static inline void atomic_add(int i, atomic_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic_sub(int i, atomic_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} + +static inline void atomic_inc(atomic_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + ++v->counter; + local_irq_restore(flags); +} + +static inline void atomic_dec(atomic_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + --v->counter; + local_irq_restore(flags); +} + +static inline int atomic_dec_and_test(volatile atomic_t *v) +{ + unsigned long flags = 0; + int val; + + local_irq_save(flags); + val = v->counter; + v->counter = val -= 1; + local_irq_restore(flags); + + return val == 0; +} + +static inline int atomic_add_negative(int i, volatile atomic_t *v) +{ + unsigned long flags = 0; + int val; + + local_irq_save(flags); + val = v->counter; + v->counter = val += i; + local_irq_restore(flags); + + return val < 0; +} + +static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) +{ + unsigned long flags = 0; + + local_irq_save(flags); + *addr &= ~mask; + local_irq_restore(flags); +} + +#if BITS_PER_LONG == 32 + +static inline void atomic64_add(long long i, volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic64_sub(long long i, volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} + +#else /* BIT_PER_LONG == 32 */ + +static inline void atomic64_add(long i, volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic64_sub(long i, volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} +#endif + +static inline void atomic64_inc(volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter += 1; + local_irq_restore(flags); +} + +static inline void atomic64_dec(volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter -= 1; + local_irq_restore(flags); +} + +#endif diff --git a/roms/u-boot/include/asm-generic/bitops/__ffs.h b/roms/u-boot/include/asm-generic/bitops/__ffs.h new file mode 100644 index 000000000..937d7c435 --- /dev/null +++ b/roms/u-boot/include/asm-generic/bitops/__ffs.h @@ -0,0 +1,43 @@ +#ifndef _ASM_GENERIC_BITOPS___FFS_H_ +#define _ASM_GENERIC_BITOPS___FFS_H_ + +#include + +/** + * __ffs - find first bit in word. + * @word: The word to search + * + * Undefined if no bit exists, so code should check against 0 first. + */ +static __always_inline unsigned long __ffs(unsigned long word) +{ + int num = 0; + +#if BITS_PER_LONG == 64 + if ((word & 0xffffffff) == 0) { + num += 32; + word >>= 32; + } +#endif + if ((word & 0xffff) == 0) { + num += 16; + word >>= 16; + } + if ((word & 0xff) == 0) { + num += 8; + word >>= 8; + } + if ((word & 0xf) == 0) { + num += 4; + word >>= 4; + } + if ((word & 0x3) == 0) { + num += 2; + word >>= 2; + } + if ((word & 0x1) == 0) + num += 1; + return num; +} + +#endif /* _ASM_GENERIC_BITOPS___FFS_H_ */ diff --git a/roms/u-boot/include/asm-generic/bitops/__fls.h b/roms/u-boot/include/asm-generic/bitops/__fls.h new file mode 100644 index 000000000..a60a7ccb6 --- /dev/null +++ b/roms/u-boot/include/asm-generic/bitops/__fls.h @@ -0,0 +1,43 @@ +#ifndef _ASM_GENERIC_BITOPS___FLS_H_ +#define _ASM_GENERIC_BITOPS___FLS_H_ + +#include + +/** + * __fls - find last (most-significant) set bit in a long word + * @word: the word to search + * + * Undefined if no set bit exists, so code should check against 0 first. + */ +static __always_inline unsigned long __fls(unsigned long word) +{ + int num = BITS_PER_LONG - 1; + +#if BITS_PER_LONG == 64 + if (!(word & (~0ul << 32))) { + num -= 32; + word <<= 32; + } +#endif + if (!(word & (~0ul << (BITS_PER_LONG-16)))) { + num -= 16; + word <<= 16; + } + if (!(word & (~0ul << (BITS_PER_LONG-8)))) { + num -= 8; + word <<= 8; + } + if (!(word & (~0ul << (BITS_PER_LONG-4)))) { + num -= 4; + word <<= 4; + } + if (!(word & (~0ul << (BITS_PER_LONG-2)))) { + num -= 2; + word <<= 2; + } + if (!(word & (~0ul << (BITS_PER_LONG-1)))) + num -= 1; + return num; +} + +#endif /* _ASM_GENERIC_BITOPS___FLS_H_ */ diff --git a/roms/u-boot/include/asm-generic/bitops/fls.h b/roms/u-boot/include/asm-generic/bitops/fls.h new file mode 100644 index 000000000..0576d1f42 --- /dev/null +++ b/roms/u-boot/include/asm-generic/bitops/fls.h @@ -0,0 +1,41 @@ +#ifndef _ASM_GENERIC_BITOPS_FLS_H_ +#define _ASM_GENERIC_BITOPS_FLS_H_ + +/** + * fls - find last (most-significant) bit set + * @x: the word to search + * + * This is defined the same way as ffs. + * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. + */ + +static __always_inline int fls(int x) +{ + int r = 32; + + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; +} + +#endif /* _ASM_GENERIC_BITOPS_FLS_H_ */ diff --git a/roms/u-boot/include/asm-generic/bitops/fls64.h b/roms/u-boot/include/asm-generic/bitops/fls64.h new file mode 100644 index 000000000..b097cf844 --- /dev/null +++ b/roms/u-boot/include/asm-generic/bitops/fls64.h @@ -0,0 +1,36 @@ +#ifndef _ASM_GENERIC_BITOPS_FLS64_H_ +#define _ASM_GENERIC_BITOPS_FLS64_H_ + +#include + +/** + * fls64 - find last set bit in a 64-bit word + * @x: the word to search + * + * This is defined in a similar way as the libc and compiler builtin + * ffsll, but returns the position of the most significant set bit. + * + * fls64(value) returns 0 if value is 0 or the position of the last + * set bit if value is nonzero. The last (most significant) bit is + * at position 64. + */ +#if BITS_PER_LONG == 32 +static __always_inline int fls64(__u64 x) +{ + __u32 h = x >> 32; + if (h) + return fls(h) + 32; + return fls(x); +} +#elif BITS_PER_LONG == 64 +static __always_inline int fls64(__u64 x) +{ + if (x == 0) + return 0; + return __fls(x) + 1; +} +#else +#error BITS_PER_LONG not 32 or 64 +#endif + +#endif /* _ASM_GENERIC_BITOPS_FLS64_H_ */ diff --git a/roms/u-boot/include/asm-generic/bitsperlong.h b/roms/u-boot/include/asm-generic/bitsperlong.h new file mode 100644 index 000000000..75ee21e86 --- /dev/null +++ b/roms/u-boot/include/asm-generic/bitsperlong.h @@ -0,0 +1,8 @@ +#ifndef __ASM_GENERIC_BITS_PER_LONG +#define __ASM_GENERIC_BITS_PER_LONG + +#ifndef BITS_PER_LONG_LONG +#define BITS_PER_LONG_LONG 64 +#endif + +#endif /* __ASM_GENERIC_BITS_PER_LONG */ diff --git a/roms/u-boot/include/asm-generic/global_data.h b/roms/u-boot/include/asm-generic/global_data.h new file mode 100644 index 000000000..47921d27b --- /dev/null +++ b/roms/u-boot/include/asm-generic/global_data.h @@ -0,0 +1,602 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * (C) Copyright 2002-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef __ASM_GENERIC_GBL_DATA_H +#define __ASM_GENERIC_GBL_DATA_H +/* + * The following data structure is placed in some memory which is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t) + * + * Each architecture has its own private fields. For now all are private + */ + +#ifndef __ASSEMBLY__ +#include +#include +#include + +struct acpi_ctx; +struct driver_rt; + +typedef struct global_data gd_t; + +/** + * struct global_data - global data structure + */ +struct global_data { + /** + * @bd: board information + */ + struct bd_info *bd; + /** + * @flags: global data flags + * + * See &enum gd_flags + */ + unsigned long flags; + /** + * @baudrate: baud rate of the serial interface + */ + unsigned int baudrate; + /** + * @cpu_clk: CPU clock rate in Hz + */ + unsigned long cpu_clk; + /** + * @bus_clk: platform clock rate in Hz + */ + unsigned long bus_clk; + /** + * @pci_clk: PCI clock rate in Hz + */ + /* We cannot bracket this with CONFIG_PCI due to mpc5xxx */ + unsigned long pci_clk; + /** + * @mem_clk: memory clock rate in Hz + */ + unsigned long mem_clk; +#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) + /** + * @fb_base: base address of frame buffer memory + */ + unsigned long fb_base; +#endif +#if defined(CONFIG_POST) + /** + * @post_log_word: active POST tests + * + * @post_log_word is a bit mask defining which POST tests are recorded + * (see constants POST_*). + */ + unsigned long post_log_word; + /** + * @post_log_res: POST results + * + * @post_log_res is a bit mask with the POST results. A bit with value 1 + * indicates successful execution. + */ + unsigned long post_log_res; + /** + * @post_init_f_time: time in ms when post_init_f() started + */ + unsigned long post_init_f_time; +#endif +#ifdef CONFIG_BOARD_TYPES + /** + * @board_type: board type + * + * If a U-Boot configuration supports multiple board types, the actual + * board type may be stored in this field. + */ + unsigned long board_type; +#endif + /** + * @have_console: console is available + * + * A value of 1 indicates that serial_init() was called and a console + * is available. + * A value of 0 indicates that console input and output drivers shall + * not be called. + */ + unsigned long have_console; +#if CONFIG_IS_ENABLED(PRE_CONSOLE_BUFFER) + /** + * @precon_buf_idx: pre-console buffer index + * + * @precon_buf_idx indicates the current position of the buffer used to + * collect output before the console becomes available + */ + unsigned long precon_buf_idx; +#endif + /** + * @env_addr: address of environment structure + * + * @env_addr contains the address of the structure holding the + * environment variables. + */ + unsigned long env_addr; + /** + * @env_valid: environment is valid + * + * See &enum env_valid + */ + unsigned long env_valid; + /** + * @env_has_init: bit mask indicating environment locations + * + * &enum env_location defines which bit relates to which location + */ + unsigned long env_has_init; + /** + * @env_load_prio: priority of the loaded environment + */ + int env_load_prio; + /** + * @ram_base: base address of RAM used by U-Boot + */ + unsigned long ram_base; + /** + * @ram_top: top address of RAM used by U-Boot + */ + phys_addr_t ram_top; + /** + * @relocaddr: start address of U-Boot in RAM + * + * After relocation this field indicates the address to which U-Boot + * has been relocated. It can be displayed using the bdinfo command. + * Its value is needed to display the source code when debugging with + * GDB using the 'add-symbol-file u-boot ' command. + */ + unsigned long relocaddr; + /** + * @ram_size: RAM size in bytes + */ + phys_size_t ram_size; + /** + * @mon_len: monitor length in bytes + */ + unsigned long mon_len; + /** + * @irq_sp: IRQ stack pointer + */ + unsigned long irq_sp; + /** + * @start_addr_sp: initial stack pointer address + */ + unsigned long start_addr_sp; + /** + * @reloc_off: relocation offset + */ + unsigned long reloc_off; + /** + * @new_gd: pointer to relocated global data + */ + struct global_data *new_gd; + +#ifdef CONFIG_DM + /** + * @dm_root: root instance for Driver Model + */ + struct udevice *dm_root; + /** + * @dm_root_f: pre-relocation root instance + */ + struct udevice *dm_root_f; + /** + * @uclass_root_s: + * head of core tree when uclasses are not in read-only memory. + * + * When uclasses are in read-only memory, @uclass_root_s is not used and + * @uclass_root points to the root node generated by dtoc. + */ + struct list_head uclass_root_s; + /** + * @uclass_root: + * pointer to head of core tree, if uclasses are in read-only memory and + * cannot be adjusted to use @uclass_root as a list head. + * + * When not in read-only memory, @uclass_root_s is used to hold the + * uclass root, and @uclass_root points to the address of + * @uclass_root_s. + */ + struct list_head *uclass_root; +# if CONFIG_IS_ENABLED(OF_PLATDATA_DRIVER_RT) + /** @dm_driver_rt: Dynamic info about the driver */ + struct driver_rt *dm_driver_rt; +# endif +#if CONFIG_IS_ENABLED(OF_PLATDATA_RT) + /** @dm_udevice_rt: Dynamic info about the udevice */ + struct udevice_rt *dm_udevice_rt; + /** + * @dm_priv_base: Base address of the priv/plat region used when + * udevices and uclasses are in read-only memory. This is NULL if not + * used + */ + void *dm_priv_base; +# endif +#endif +#ifdef CONFIG_TIMER + /** + * @timer: timer instance for Driver Model + */ + struct udevice *timer; +#endif + /** + * @fdt_blob: U-Boot's own device tree, NULL if none + */ + const void *fdt_blob; + /** + * @new_fdt: relocated device tree + */ + void *new_fdt; + /** + * @fdt_size: space reserved for relocated device space + */ + unsigned long fdt_size; +#if CONFIG_IS_ENABLED(OF_LIVE) + /** + * @of_root: root node of the live tree + */ + struct device_node *of_root; +#endif + +#if CONFIG_IS_ENABLED(MULTI_DTB_FIT) + /** + * @multi_dtb_fit: pointer to uncompressed multi-dtb FIT image + */ + const void *multi_dtb_fit; +#endif + /** + * @jt: jump table + * + * The jump table contains pointers to exported functions. A pointer to + * the jump table is passed to standalone applications. + */ + struct jt_funcs *jt; + /** + * @env_buf: buffer for env_get() before reloc + */ + char env_buf[32]; +#ifdef CONFIG_TRACE + /** + * @trace_buff: trace buffer + * + * When tracing function in U-Boot this field points to the buffer + * recording the function calls. + */ + void *trace_buff; +#endif +#if defined(CONFIG_SYS_I2C) + /** + * @cur_i2c_bus: currently used I2C bus + */ + int cur_i2c_bus; +#endif + /** + * @timebase_h: high 32 bits of timer + */ + unsigned int timebase_h; + /** + * @timebase_l: low 32 bits of timer + */ + unsigned int timebase_l; +#if CONFIG_VAL(SYS_MALLOC_F_LEN) + /** + * @malloc_base: base address of early malloc() + */ + unsigned long malloc_base; + /** + * @malloc_limit: limit address of early malloc() + */ + unsigned long malloc_limit; + /** + * @malloc_ptr: current address of early malloc() + */ + unsigned long malloc_ptr; +#endif +#ifdef CONFIG_PCI + /** + * @hose: PCI hose for early use + */ + struct pci_controller *hose; + /** + * @pci_ram_top: top of region accessible to PCI + */ + phys_addr_t pci_ram_top; +#endif +#ifdef CONFIG_PCI_BOOTDELAY + /** + * @pcidelay_done: delay time before scanning of PIC hose expired + * + * If CONFIG_PCI_BOOTDELAY=y, pci_hose_scan() waits for the number of + * milliseconds defined by environment variable pcidelay before + * scanning. Once this delay has expired the flag @pcidelay_done + * is set to 1. + */ + int pcidelay_done; +#endif + /** + * @cur_serial_dev: current serial device + */ + struct udevice *cur_serial_dev; + /** + * @arch: architecture-specific data + */ + struct arch_global_data arch; +#ifdef CONFIG_CONSOLE_RECORD + /** + * @console_out: output buffer for console recording + * + * This buffer is used to collect output during console recording. + */ + struct membuff console_out; + /** + * @console_in: input buffer for console recording + * + * If console recording is activated, this buffer can be used to + * emulate input. + */ + struct membuff console_in; +#endif +#ifdef CONFIG_DM_VIDEO + /** + * @video_top: top of video frame buffer area + */ + ulong video_top; + /** + * @video_bottom: bottom of video frame buffer area + */ + ulong video_bottom; +#endif +#ifdef CONFIG_BOOTSTAGE + /** + * @bootstage: boot stage information + */ + struct bootstage_data *bootstage; + /** + * @new_bootstage: relocated boot stage information + */ + struct bootstage_data *new_bootstage; +#endif +#ifdef CONFIG_LOG + /** + * @log_drop_count: number of dropped log messages + * + * This counter is incremented for each log message which can not + * be processed because logging is not yet available as signaled by + * flag %GD_FLG_LOG_READY in @flags. + */ + int log_drop_count; + /** + * @default_log_level: default logging level + * + * For logging devices without filters @default_log_level defines the + * logging level, cf. &enum log_level_t. + */ + int default_log_level; + /** + * @log_head: list of logging devices + */ + struct list_head log_head; + /** + * @log_fmt: bit mask for logging format + * + * The @log_fmt bit mask selects the fields to be shown in log messages. + * &enum log_fmt defines the bits of the bit mask. + */ + int log_fmt; + + /** + * @processing_msg: a log message is being processed + * + * This flag is used to suppress the creation of additional messages + * while another message is being processed. + */ + bool processing_msg; + /** + * @logc_prev: logging category of previous message + * + * This value is used as logging category for continuation messages. + */ + int logc_prev; + /** + * @logl_prev: logging level of the previous message + * + * This value is used as logging level for continuation messages. + */ + int logl_prev; + /** + * @log_cont: Previous log line did not finished wtih \n + * + * This allows for chained log messages on the same line + */ + bool log_cont; +#endif +#if CONFIG_IS_ENABLED(BLOBLIST) + /** + * @bloblist: blob list information + */ + struct bloblist_hdr *bloblist; + /** + * @new_bloblist: relocated blob list information + */ + struct bloblist_hdr *new_bloblist; +#endif +#if CONFIG_IS_ENABLED(HANDOFF) + /** + * @spl_handoff: SPL hand-off information + */ + struct spl_handoff *spl_handoff; +#endif +#if defined(CONFIG_TRANSLATION_OFFSET) + /** + * @translation_offset: optional translation offset + * + * See CONFIG_TRANSLATION_OFFSET. + */ + fdt_addr_t translation_offset; +#endif +#if CONFIG_IS_ENABLED(WDT) + /** + * @watchdog_dev: watchdog device + */ + struct udevice *watchdog_dev; +#endif +#ifdef CONFIG_GENERATE_ACPI_TABLE + /** + * @acpi_ctx: ACPI context pointer + */ + struct acpi_ctx *acpi_ctx; +#endif +#if CONFIG_IS_ENABLED(GENERATE_SMBIOS_TABLE) + /** + * @smbios_version: Points to SMBIOS type 0 version + */ + char *smbios_version; +#endif +}; + +/** + * gd_board_type() - retrieve board type + * + * Return: global board type + */ +#ifdef CONFIG_BOARD_TYPES +#define gd_board_type() gd->board_type +#else +#define gd_board_type() 0 +#endif + +/* These macros help avoid #ifdefs in the code */ +#if CONFIG_IS_ENABLED(OF_LIVE) +#define gd_of_root() gd->of_root +#define gd_of_root_ptr() &gd->of_root +#define gd_set_of_root(_root) gd->of_root = (_root) +#else +#define gd_of_root() NULL +#define gd_of_root_ptr() NULL +#define gd_set_of_root(_root) +#endif + +#if CONFIG_IS_ENABLED(OF_PLATDATA_DRIVER_RT) +#define gd_set_dm_driver_rt(dyn) gd->dm_driver_rt = dyn +#define gd_dm_driver_rt() gd->dm_driver_rt +#else +#define gd_set_dm_driver_rt(dyn) +#define gd_dm_driver_rt() NULL +#endif + +#if CONFIG_IS_ENABLED(OF_PLATDATA_RT) +#define gd_set_dm_udevice_rt(dyn) gd->dm_udevice_rt = dyn +#define gd_dm_udevice_rt() gd->dm_udevice_rt +#define gd_set_dm_priv_base(dyn) gd->dm_priv_base = dyn +#define gd_dm_priv_base() gd->dm_priv_base +#else +#define gd_set_dm_udevice_rt(dyn) +#define gd_dm_udevice_rt() NULL +#define gd_set_dm_priv_base(dyn) +#define gd_dm_priv_base() NULL +#endif + +#ifdef CONFIG_GENERATE_ACPI_TABLE +#define gd_acpi_ctx() gd->acpi_ctx +#else +#define gd_acpi_ctx() NULL +#endif + +/** + * enum gd_flags - global data flags + * + * See field flags of &struct global_data. + */ +enum gd_flags { + /** + * @GD_FLG_RELOC: code was relocated to RAM + */ + GD_FLG_RELOC = 0x00001, + /** + * @GD_FLG_DEVINIT: devices have been initialized + */ + GD_FLG_DEVINIT = 0x00002, + /** + * @GD_FLG_SILENT: silent mode + */ + GD_FLG_SILENT = 0x00004, + /** + * @GD_FLG_POSTFAIL: critical POST test failed + */ + GD_FLG_POSTFAIL = 0x00008, + /** + * @GD_FLG_POSTSTOP: POST sequence aborted + */ + GD_FLG_POSTSTOP = 0x00010, + /** + * @GD_FLG_LOGINIT: log Buffer has been initialized + */ + GD_FLG_LOGINIT = 0x00020, + /** + * @GD_FLG_DISABLE_CONSOLE: disable console (in & out) + */ + GD_FLG_DISABLE_CONSOLE = 0x00040, + /** + * @GD_FLG_ENV_READY: environment imported into hash table + */ + GD_FLG_ENV_READY = 0x00080, + /** + * @GD_FLG_SERIAL_READY: pre-relocation serial console ready + */ + GD_FLG_SERIAL_READY = 0x00100, + /** + * @GD_FLG_FULL_MALLOC_INIT: full malloc() is ready + */ + GD_FLG_FULL_MALLOC_INIT = 0x00200, + /** + * @GD_FLG_SPL_INIT: spl_init() has been called + */ + GD_FLG_SPL_INIT = 0x00400, + /** + * @GD_FLG_SKIP_RELOC: don't relocate + */ + GD_FLG_SKIP_RELOC = 0x00800, + /** + * @GD_FLG_RECORD: record console + */ + GD_FLG_RECORD = 0x01000, + /** + * @GD_FLG_ENV_DEFAULT: default variable flag + */ + GD_FLG_ENV_DEFAULT = 0x02000, + /** + * @GD_FLG_SPL_EARLY_INIT: early SPL initialization is done + */ + GD_FLG_SPL_EARLY_INIT = 0x04000, + /** + * @GD_FLG_LOG_READY: log system is ready for use + */ + GD_FLG_LOG_READY = 0x08000, + /** + * @GD_FLG_WDT_READY: watchdog is ready for use + */ + GD_FLG_WDT_READY = 0x10000, + /** + * @GD_FLG_SKIP_LL_INIT: don't perform low-level initialization + */ + GD_FLG_SKIP_LL_INIT = 0x20000, + /** + * @GD_FLG_SMP_READY: SMP initialization is complete + */ + GD_FLG_SMP_READY = 0x40000, +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_GENERIC_GBL_DATA_H */ diff --git a/roms/u-boot/include/asm-generic/gpio.h b/roms/u-boot/include/asm-generic/gpio.h new file mode 100644 index 000000000..e33cde7ab --- /dev/null +++ b/roms/u-boot/include/asm-generic/gpio.h @@ -0,0 +1,840 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2011, NVIDIA Corp. All rights reserved. + */ + +#ifndef _ASM_GENERIC_GPIO_H_ +#define _ASM_GENERIC_GPIO_H_ + +#include +#include + +struct acpi_gpio; +struct ofnode_phandle_args; + +/* + * Generic GPIO API for U-Boot + * + * -- + * NB: This is deprecated. Please use the driver model functions instead: + * + * - gpio_request_by_name() + * - dm_gpio_get_value() etc. + * + * For now we need a dm_ prefix on some functions to avoid name collision. + * -- + * + * GPIOs are numbered from 0 to GPIO_COUNT-1 which value is defined + * by the SOC/architecture. + * + * Each GPIO can be an input or output. If an input then its value can + * be read as 0 or 1. If an output then its value can be set to 0 or 1. + * If you try to write an input then the value is undefined. If you try + * to read an output, barring something very unusual, you will get + * back the value of the output that you previously set. + * + * In some cases the operation may fail, for example if the GPIO number + * is out of range, or the GPIO is not available because its pin is + * being used by another function. In that case, functions may return + * an error value of -1. + */ + +/** + * @deprecated Please use driver model instead + * Request a GPIO. This should be called before any of the other functions + * are used on this GPIO. + * + * Note: With driver model, the label is allocated so there is no need for + * the caller to preserve it. + * + * @param gpio GPIO number + * @param label User label for this GPIO + * @return 0 if ok, -1 on error + */ +int gpio_request(unsigned gpio, const char *label); + +/** + * @deprecated Please use driver model instead + * Stop using the GPIO. This function should not alter pin configuration. + * + * @param gpio GPIO number + * @return 0 if ok, -1 on error + */ +int gpio_free(unsigned gpio); + +/** + * @deprecated Please use driver model instead + * Make a GPIO an input. + * + * @param gpio GPIO number + * @return 0 if ok, -1 on error + */ +int gpio_direction_input(unsigned gpio); + +/** + * @deprecated Please use driver model instead + * Make a GPIO an output, and set its value. + * + * @param gpio GPIO number + * @param value GPIO value (0 for low or 1 for high) + * @return 0 if ok, -1 on error + */ +int gpio_direction_output(unsigned gpio, int value); + +/** + * @deprecated Please use driver model instead + * Get a GPIO's value. This will work whether the GPIO is an input + * or an output. + * + * @param gpio GPIO number + * @return 0 if low, 1 if high, -1 on error + */ +int gpio_get_value(unsigned gpio); + +/** + * @deprecated Please use driver model instead + * Set an output GPIO's value. The GPIO must already be an output or + * this function may have no effect. + * + * @param gpio GPIO number + * @param value GPIO value (0 for low or 1 for high) + * @return 0 if ok, -1 on error + */ +int gpio_set_value(unsigned gpio, int value); + +/* State of a GPIO, as reported by get_function() */ +enum gpio_func_t { + GPIOF_INPUT = 0, + GPIOF_OUTPUT, + GPIOF_UNUSED, /* Not claimed */ + GPIOF_UNKNOWN, /* Not known */ + GPIOF_FUNC, /* Not used as a GPIO */ + + GPIOF_COUNT, +}; + +struct udevice; + +struct gpio_desc { + struct udevice *dev; /* Device, NULL for invalid GPIO */ + unsigned long flags; +#define GPIOD_IS_OUT BIT(1) /* GPIO is an output */ +#define GPIOD_IS_IN BIT(2) /* GPIO is an input */ +#define GPIOD_ACTIVE_LOW BIT(3) /* GPIO is active when value is low */ +#define GPIOD_IS_OUT_ACTIVE BIT(4) /* set output active */ +#define GPIOD_OPEN_DRAIN BIT(5) /* GPIO is open drain type */ +#define GPIOD_OPEN_SOURCE BIT(6) /* GPIO is open source type */ +#define GPIOD_PULL_UP BIT(7) /* GPIO has pull-up enabled */ +#define GPIOD_PULL_DOWN BIT(8) /* GPIO has pull-down enabled */ + +/* Flags for updating the above */ +#define GPIOD_MASK_DIR (GPIOD_IS_OUT | GPIOD_IS_IN | \ + GPIOD_IS_OUT_ACTIVE) +#define GPIOD_MASK_DSTYPE (GPIOD_OPEN_DRAIN | GPIOD_OPEN_SOURCE) +#define GPIOD_MASK_PULL (GPIOD_PULL_UP | GPIOD_PULL_DOWN) + + uint offset; /* GPIO offset within the device */ + /* + * We could consider adding the GPIO label in here. Possibly we could + * use this structure for internal GPIO information. + */ +}; + +/** + * dm_gpio_is_valid() - Check if a GPIO is valid + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @return true if valid, false if not + */ +static inline bool dm_gpio_is_valid(const struct gpio_desc *desc) +{ + return desc->dev != NULL; +} + +/** + * gpio_get_status() - get the current GPIO status as a string + * + * Obtain the current GPIO status as a string which can be presented to the + * user. A typical string is: + * + * "b4: in: 1 [x] sdmmc_cd" + * + * which means this is GPIO bank b, offset 4, currently set to input, current + * value 1, [x] means that it is requested and the owner is 'sdmmc_cd' + * + * TODO(sjg@chromium.org): This should use struct gpio_desc + * + * @dev: Device to check + * @offset: Offset of device GPIO to check + * @buf: Place to put string + * @buffsize: Size of string including \0 + */ +int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize); + +/** + * gpio_get_function() - get the current function for a GPIO pin + * + * Note this returns GPIOF_UNUSED if the GPIO is not requested. + * + * TODO(sjg@chromium.org): This should use struct gpio_desc + * + * @dev: Device to check + * @offset: Offset of device GPIO to check + * @namep: If non-NULL, this is set to the name given when the GPIO + * was requested, or -1 if it has not been requested + * @return -ENODATA if the driver returned an unknown function, + * -ENODEV if the device is not active, -EINVAL if the offset is invalid. + * GPIOF_UNUSED if the GPIO has not been requested. Otherwise returns the + * function from enum gpio_func_t. + */ +int gpio_get_function(struct udevice *dev, int offset, const char **namep); + +/** + * gpio_get_raw_function() - get the current raw function for a GPIO pin + * + * Note this does not return GPIOF_UNUSED - it will always return the GPIO + * driver's view of a pin function, even if it is not correctly set up. + * + * TODO(sjg@chromium.org): This should use struct gpio_desc + * + * @dev: Device to check + * @offset: Offset of device GPIO to check + * @namep: If non-NULL, this is set to the name given when the GPIO + * was requested, or -1 if it has not been requested + * @return -ENODATA if the driver returned an unknown function, + * -ENODEV if the device is not active, -EINVAL if the offset is invalid. + * Otherwise returns the function from enum gpio_func_t. + */ +int gpio_get_raw_function(struct udevice *dev, int offset, const char **namep); + +/** + * gpio_requestf() - request a GPIO using a format string for the owner + * + * This is a helper function for gpio_request(). It allows you to provide + * a printf()-format string for the GPIO owner. It calls gpio_request() with + * the string that is created + */ +int gpio_requestf(unsigned gpio, const char *fmt, ...) + __attribute__ ((format (__printf__, 2, 3))); + +struct fdtdec_phandle_args; + +/** + * gpio_xlate_offs_flags() - implementation for common use of dm_gpio_ops.xlate + * + * This routine sets the offset field to args[0] and the flags field to + * GPIOD_ACTIVE_LOW if the GPIO_ACTIVE_LOW flag is present in args[1]. + */ +int gpio_xlate_offs_flags(struct udevice *dev, struct gpio_desc *desc, + struct ofnode_phandle_args *args); + +/** + * struct struct dm_gpio_ops - Driver model GPIO operations + * + * Refer to functions above for description. These function largely copy + * the old API. + * + * This is trying to be close to Linux GPIO API. Once the U-Boot uses the + * new DM GPIO API, this should be really easy to flip over to the Linux + * GPIO API-alike interface. + * + * Also it would be useful to standardise additional functions like + * pullup, slew rate and drive strength. + * + * gpio_request() and gpio_free() are optional - if NULL then they will + * not be called. + * + * Note that @offset is the offset from the base GPIO of the device. So + * offset 0 is the device's first GPIO and offset o-1 is the last GPIO, + * where o is the number of GPIO lines controlled by the device. A device + * is typically used to control a single bank of GPIOs. Within complex + * SoCs there may be many banks and therefore many devices all referring + * to the different IO addresses within the SoC. + * + * The uclass combines all GPIO devices together to provide a consistent + * numbering from 0 to n-1, where n is the number of GPIOs in total across + * all devices. Be careful not to confuse offset with gpio in the parameters. + */ +struct dm_gpio_ops { + int (*request)(struct udevice *dev, unsigned offset, const char *label); + int (*rfree)(struct udevice *dev, unsigned int offset); + + /** + * direction_input() - deprecated + * + * Equivalent to set_flags(...GPIOD_IS_IN) + */ + int (*direction_input)(struct udevice *dev, unsigned offset); + + /** + * direction_output() - deprecated + * + * Equivalent to set_flags(...GPIOD_IS_OUT) with GPIOD_IS_OUT_ACTIVE + * also set if @value + */ + int (*direction_output)(struct udevice *dev, unsigned offset, + int value); + + int (*get_value)(struct udevice *dev, unsigned offset); + + /** + * set_value() - Sets the GPIO value of an output + * + * If the driver provides an @set_flags() method then that is used + * in preference to this, with GPIOD_IS_OUT_ACTIVE set according to + * @value. + */ + int (*set_value)(struct udevice *dev, unsigned offset, int value); + /** + * get_function() Get the GPIO function + * + * @dev: Device to check + * @offset: GPIO offset within that device + * @return current function - GPIOF_... + */ + int (*get_function)(struct udevice *dev, unsigned offset); + + /** + * xlate() - Translate phandle arguments into a GPIO description + * + * This function should set up the fields in desc according to the + * information in the arguments. The uclass will have set up: + * + * @desc->dev to @dev + * @desc->flags to 0 + * @desc->offset to 0 + * + * This method is optional and defaults to gpio_xlate_offs_flags, + * which will parse offset and the GPIO_ACTIVE_LOW flag in the first + * two arguments. + * + * Note that @dev is passed in as a parameter to follow driver model + * uclass conventions, even though it is already available as + * desc->dev. + * + * @dev: GPIO device + * @desc: Place to put GPIO description + * @args: Arguments provided in description + * @return 0 if OK, -ve on error + */ + int (*xlate)(struct udevice *dev, struct gpio_desc *desc, + struct ofnode_phandle_args *args); + + /** + * set_flags() - Adjust GPIO flags + * + * This function should set up the GPIO configuration according to the + * information provided by @flags. + * + * If any flags cannot be set (e.g. the driver or hardware does not + * support them or this particular GPIO does not have the requested + * feature), the driver should return -EINVAL. + * + * The uclass checks that flags do not obviously conflict (e.g. input + * and output). If the driver finds other conflicts it should return + * -ERECALLCONFLICT + * + * Note that GPIOD_ACTIVE_LOW should be ignored, since the uclass + * adjusts for it automatically. For example, for an output GPIO, + * GPIOD_ACTIVE_LOW causes GPIOD_IS_OUT_ACTIVE to be inverted by the + * uclass, so the driver always sees the value that should be set at the + * pin (1=high, 0=low). + * + * This method is required and should be implemented by new drivers. At + * some point, it will supersede direction_input() and + * direction_output(), which wil be removed. + * + * @dev: GPIO device + * @offset: GPIO offset within that device + * @flags: New flags value (GPIOD_...) + * + * @return 0 if OK, -EINVAL if unsupported, -ERECALLCONFLICT if flags + * conflict in some * non-obvious way and were not applied, + * other -ve on error + */ + int (*set_flags)(struct udevice *dev, unsigned int offset, ulong flags); + + /** + * get_flags() - Get GPIO flags + * + * This function return the GPIO flags used. It should read this from + * the hardware directly. + * + * This method is optional. + * + * @dev: GPIO device + * @offset: GPIO offset within that device + * @flagsp: place to put the current flags value + * @return 0 if OK, -ve on error + */ + int (*get_flags)(struct udevice *dev, unsigned int offset, + ulong *flagsp); + +#if CONFIG_IS_ENABLED(ACPIGEN) + /** + * get_acpi() - Get the ACPI info for a GPIO + * + * This converts a GPIO to an ACPI structure for adding to the ACPI + * tables. + * + * @desc: GPIO description to convert + * @gpio: Output ACPI GPIO information + * @return ACPI pin number or -ve on error + */ + int (*get_acpi)(const struct gpio_desc *desc, struct acpi_gpio *gpio); +#endif +}; + +/** + * struct gpio_dev_priv - information about a device used by the uclass + * + * The uclass combines all active GPIO devices into a unified numbering + * scheme. To do this it maintains some private information about each + * device. + * + * To implement driver model support in your GPIO driver, add a probe + * handler, and set @gpio_count and @bank_name correctly in that handler. + * This tells the uclass the name of the GPIO bank and the number of GPIOs + * it contains. + * + * @bank_name: Name of the GPIO device (e.g 'a' means GPIOs will be called + * 'A0', 'A1', etc. + * @gpio_count: Number of GPIOs in this device + * @gpio_base: Base GPIO number for this device. For the first active device + * this will be 0; the numbering for others will follow sequentially so that + * @gpio_base for device 1 will equal the number of GPIOs in device 0. + * @name: Array of pointers to the name for each GPIO in this bank. The + * value of the pointer will be NULL if the GPIO has not been claimed. + */ +struct gpio_dev_priv { + const char *bank_name; + unsigned gpio_count; + unsigned gpio_base; + char **name; +}; + +/* Access the GPIO operations for a device */ +#define gpio_get_ops(dev) ((struct dm_gpio_ops *)(dev)->driver->ops) + +/** + * gpio_get_bank_info - Return information about a GPIO bank/device + * + * This looks up a device and returns both its GPIO base name and the number + * of GPIOs it controls. + * + * @dev: Device to look up + * @offset_count: Returns number of GPIOs within this bank + * @return bank name of this device + */ +const char *gpio_get_bank_info(struct udevice *dev, int *offset_count); + +/** + * dm_gpio_lookup_name() - Look up a named GPIO and return its description + * + * The name of a GPIO is typically its bank name followed by a number from 0. + * For example A0 is the first GPIO in bank A. Each bank is a separate driver + * model device. + * + * @name: Name to look up + * @desc: Returns description, on success + * @return 0 if OK, -ve on error + */ +int dm_gpio_lookup_name(const char *name, struct gpio_desc *desc); + +/** + * gpio_hog_lookup_name() - Look up a named GPIO and return the gpio descr. + * + * @name: Name to look up + * @desc: Returns GPIO description, on success, else NULL + * @return: Returns 0 if OK, else -ENODEV + */ +int gpio_hog_lookup_name(const char *name, struct gpio_desc **desc); + +/** + * gpio_hog_probe_all() - probe all gpio devices with + * gpio-hog subnodes. + * + * @return: Returns return value from device_probe() + */ +int gpio_hog_probe_all(void); + +/** + * gpio_lookup_name - Look up a GPIO name and return its details + * + * This is used to convert a named GPIO into a device, offset and GPIO + * number. + * + * @name: GPIO name to look up + * @devp: Returns pointer to device which contains this GPIO + * @offsetp: Returns the offset number within this device + * @gpiop: Returns the absolute GPIO number, numbered from 0 + */ +int gpio_lookup_name(const char *name, struct udevice **devp, + unsigned int *offsetp, unsigned int *gpiop); + +/** + * gpio_get_values_as_int() - Turn the values of a list of GPIOs into an int + * + * This puts the value of the first GPIO into bit 0, the second into bit 1, + * etc. then returns the resulting integer. + * + * @gpio_list: List of GPIOs to collect + * @return resulting integer value, or -ve on error + */ +int gpio_get_values_as_int(const int *gpio_list); + +/** + * dm_gpio_get_values_as_int() - Turn the values of a list of GPIOs into an int + * + * This puts the value of the first GPIO into bit 0, the second into bit 1, + * etc. then returns the resulting integer. + * + * @desc_list: List of GPIOs to collect + * @count: Number of GPIOs + * @return resulting integer value, or -ve on error + */ +int dm_gpio_get_values_as_int(const struct gpio_desc *desc_list, int count); + +/** + * dm_gpio_get_values_as_int_base3() - Create a base-3 int from a list of GPIOs + * + * This uses pull-ups/pull-downs to figure out whether a GPIO line is externally + * pulled down, pulled up or floating. This allows three different strap values + * for each pin: + * 0 : external pull-down + * 1 : external pull-up + * 2 : floating + * + * With this it is possible to obtain more combinations from the same number of + * strapping pins, when compared to dm_gpio_get_values_as_int(). The external + * pull resistors should be made stronger that the internal SoC pull resistors, + * for this to work. + * + * With 2 pins, 6 combinations are possible, compared with 4 + * With 3 pins, 27 are possible, compared with 8 + * + * @desc_list: List of GPIOs to collect + * @count: Number of GPIOs + * @return resulting integer value, or -ve on error + */ +int dm_gpio_get_values_as_int_base3(struct gpio_desc *desc_list, + int count); + +/** + * gpio_claim_vector() - claim a number of GPIOs for input + * + * @gpio_num_array: array of gpios to claim, terminated by -1 + * @fmt: format string for GPIO names, e.g. "board_id%d" + * @return 0 if OK, -ve on error + */ +int gpio_claim_vector(const int *gpio_num_array, const char *fmt); + +/** + * gpio_request_by_name() - Locate and request a GPIO by name + * + * This operates by looking up the given list name in the device (device + * tree property) and requesting the GPIO for use. The property must exist + * in @dev's node. + * + * Use @flags to specify whether the GPIO should be an input or output. In + * principle this can also come from the device tree binding but most + * bindings don't provide this information. Specifically, when the GPIO uclass + * calls the xlate() method, it can return default flags, which are then + * ORed with this @flags. + * + * If we find that requesting the GPIO is not always needed we could add a + * new function or a new GPIOD_NO_REQUEST flag. + * + * At present driver model has no reference counting so if one device + * requests a GPIO which subsequently is unbound, the @desc->dev pointer + * will be invalid. However this will only happen if the GPIO device is + * unbound, not if it is removed, so this seems like a reasonable limitation + * for now. There is no real use case for unbinding drivers in normal + * operation. + * + * The device tree binding is doc/device-tree-bindings/gpio/gpio.txt in + * generate terms and each specific device may add additional details in + * a binding file in the same directory. + * + * @dev: Device requesting the GPIO + * @list_name: Name of GPIO list (e.g. "board-id-gpios") + * @index: Index number of the GPIO in that list use request (0=first) + * @desc: Returns GPIO description information. If there is no such + * GPIO, @desc->dev will be NULL. + * @flags: Indicates the GPIO input/output settings (GPIOD_...) + * @return 0 if OK, -ENOENT if the GPIO does not exist, -EINVAL if there is + * something wrong with the list, or other -ve for another error (e.g. + * -EBUSY if a GPIO was already requested) + */ +int gpio_request_by_name(struct udevice *dev, const char *list_name, + int index, struct gpio_desc *desc, int flags); + +/** + * gpio_request_list_by_name() - Request a list of GPIOs + * + * Reads all the GPIOs from a list and requests them. See + * gpio_request_by_name() for additional details. Lists should not be + * misused to hold unrelated or optional GPIOs. They should only be used + * for things like parallel data lines. A zero phandle terminates the list + * the list. + * + * This function will either succeed, and request all GPIOs in the list, or + * fail and request none (it will free already-requested GPIOs in case of + * an error part-way through). + * + * @dev: Device requesting the GPIO + * @list_name: Name of GPIO list (e.g. "board-id-gpios") + * @desc_list: Returns a list of GPIO description information + * @max_count: Maximum number of GPIOs to return (@desc_list must be at least + * this big) + * @flags: Indicates the GPIO input/output settings (GPIOD_...) + * @return number of GPIOs requested, or -ve on error + */ +int gpio_request_list_by_name(struct udevice *dev, const char *list_name, + struct gpio_desc *desc_list, int max_count, + int flags); + +/** + * dm_gpio_request() - manually request a GPIO + * + * Note: This function should only be used for testing / debugging. Instead. + * use gpio_request_by_name() to pull GPIOs from the device tree. + * + * @desc: GPIO description of GPIO to request (see dm_gpio_lookup_name()) + * @label: Label to attach to the GPIO while claimed + * @return 0 if OK, -ve on error + */ +int dm_gpio_request(struct gpio_desc *desc, const char *label); + +/** + * gpio_get_list_count() - Returns the number of GPIOs in a list + * + * Counts the GPIOs in a list. See gpio_request_by_name() for additional + * details. + * + * @dev: Device requesting the GPIO + * @list_name: Name of GPIO list (e.g. "board-id-gpios") + * @return number of GPIOs (0 for an empty property) or -ENOENT if the list + * does not exist + */ +int gpio_get_list_count(struct udevice *dev, const char *list_name); + +/** + * gpio_request_by_name_nodev() - request GPIOs without a device + * + * This is a version of gpio_request_list_by_name() that does not use a + * device. Avoid it unless the caller is not yet using driver model + */ +int gpio_request_by_name_nodev(ofnode node, const char *list_name, int index, + struct gpio_desc *desc, int flags); + +/** + * gpio_request_list_by_name_nodev() - request GPIOs without a device + * + * This is a version of gpio_request_list_by_name() that does not use a + * device. Avoid it unless the caller is not yet using driver model + */ +int gpio_request_list_by_name_nodev(ofnode node, const char *list_name, + struct gpio_desc *desc_list, int max_count, + int flags); + +/** + * gpio_dev_request_index() - request single GPIO from gpio device + * + * @dev: GPIO device + * @nodename: Name of node for which gpio gets requested, used + * for the gpio label name + * @list_name: Name of GPIO list (e.g. "board-id-gpios") + * @index: Index number of the GPIO in that list use request (0=first) + * @flags: GPIOD_* flags + * @dtflags: GPIO flags read from DT defined see GPIOD_* + * @desc: returns GPIO descriptor filled from this function + * @return: return value from gpio_request_tail() + */ +int gpio_dev_request_index(struct udevice *dev, const char *nodename, + char *list_name, int index, int flags, + int dtflags, struct gpio_desc *desc); + +/** + * dm_gpio_free() - Free a single GPIO + * + * This frees a single GPIOs previously returned from gpio_request_by_name(). + * + * @dev: Device which requested the GPIO + * @desc: GPIO to free + * @return 0 if OK, -ve on error + */ +int dm_gpio_free(struct udevice *dev, struct gpio_desc *desc); + +/** + * gpio_free_list() - Free a list of GPIOs + * + * This frees a list of GPIOs previously returned from + * gpio_request_list_by_name(). + * + * @dev: Device which requested the GPIOs + * @desc: List of GPIOs to free + * @count: Number of GPIOs in the list + * @return 0 if OK, -ve on error + */ +int gpio_free_list(struct udevice *dev, struct gpio_desc *desc, int count); + +/** + * gpio_free_list_nodev() - free GPIOs without a device + * + * This is a version of gpio_free_list() that does not use a + * device. Avoid it unless the caller is not yet using driver model + */ +int gpio_free_list_nodev(struct gpio_desc *desc, int count); + +/** + * dm_gpio_get_value() - Get the value of a GPIO + * + * This is the driver model version of the existing gpio_get_value() function + * and should be used instead of that. + * + * For now, these functions have a dm_ prefix since they conflict with + * existing names. + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @return GPIO value (0 for inactive, 1 for active) or -ve on error + */ +int dm_gpio_get_value(const struct gpio_desc *desc); + +int dm_gpio_set_value(const struct gpio_desc *desc, int value); + +/** + * dm_gpio_clrset_flags() - Update flags + * + * This updates the flags as directled. Note that desc->flags is updated by this + * function on success. If any changes cannot be made, best efforts are made. + * + * By use of @clr and @set any of flags can be individually updated, or left + * alone + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @clr: Flags to clear (GPIOD_...) + * @set: Flags to set (GPIOD_...) + * @return 0 if OK, -EINVAL if the flags had obvious conflicts, + * -ERECALLCONFLICT if there was a non-obvious hardware conflict when attempting + * to set the flags + */ +int dm_gpio_clrset_flags(struct gpio_desc *desc, ulong clr, ulong set); + +/** + * dm_gpio_set_dir_flags() - Set direction using description and added flags + * + * This sets up the direction according to the provided flags and the GPIO + * description (desc->flags) which include direction information. + * Note that desc->flags is updated by this function. + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @flags: New flags to use + * @return 0 if OK, -ve on error, in which case desc->flags is not updated + */ +int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags); + +/** + * dm_gpios_clrset_flags() - Sets flags for a set of GPIOs + * + * This clears and sets flags individually for each GPIO. + * + * @desc: List of GPIOs to update + * @count: Number of GPIOs in the list + * @clr: Flags to clear (GPIOD_...), e.g. GPIOD_MASK_DIR if you are + * changing the direction + * @set: Flags to set (GPIOD_...) + * @return 0 if OK, -ve on error + */ +int dm_gpios_clrset_flags(struct gpio_desc *desc, int count, ulong clr, + ulong set); + +/** + * dm_gpio_get_flags() - Get flags + * + * Read the current flags + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @flags: place to put the used flags + * @return 0 if OK, -ve on error, in which case desc->flags is not updated + */ +int dm_gpio_get_flags(struct gpio_desc *desc, ulong *flags); + +/** + * gpio_get_number() - Get the global GPIO number of a GPIO + * + * This should only be used for debugging or interest. It returns the number + * that should be used for gpio_get_value() etc. to access this GPIO. + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @return GPIO number, or -ve if not found + */ +int gpio_get_number(const struct gpio_desc *desc); + +/** + * gpio_get_acpi() - Get the ACPI pin for a GPIO + * + * This converts a GPIO to an ACPI pin number for adding to the ACPI + * tables. If the GPIO is invalid, the pin_count and pins[0] are set to 0 + * + * @desc: GPIO description to convert + * @gpio: Output ACPI GPIO information + * @return ACPI pin number or -ve on error + */ +int gpio_get_acpi(const struct gpio_desc *desc, struct acpi_gpio *gpio); + +/** + * devm_gpiod_get_index - Resource-managed gpiod_get() + * @dev: GPIO consumer + * @con_id: function within the GPIO consumer + * @index: index of the GPIO to obtain in the consumer + * @flags: optional GPIO initialization flags + * + * Managed gpiod_get(). GPIO descriptors returned from this function are + * automatically disposed on device unbind. + * Return the GPIO descriptor corresponding to the function con_id of device + * dev, -ENOENT if no GPIO has been assigned to the requested function, or + * another IS_ERR() code if an error occurred while trying to acquire the GPIO. + */ +struct gpio_desc *devm_gpiod_get_index(struct udevice *dev, const char *id, + unsigned int index, int flags); + +#define devm_gpiod_get(dev, id, flags) devm_gpiod_get_index(dev, id, 0, flags) +/** + * gpiod_get_optional - obtain an optional GPIO for a given GPIO function + * @dev: GPIO consumer, can be NULL for system-global GPIOs + * @con_id: function within the GPIO consumer + * @index: index of the GPIO to obtain in the consumer + * @flags: optional GPIO initialization flags + * + * This is equivalent to devm_gpiod_get(), except that when no GPIO was + * assigned to the requested function it will return NULL. This is convenient + * for drivers that need to handle optional GPIOs. + */ +struct gpio_desc *devm_gpiod_get_index_optional(struct udevice *dev, + const char *id, + unsigned int index, + int flags); + +#define devm_gpiod_get_optional(dev, id, flags) \ + devm_gpiod_get_index_optional(dev, id, 0, flags) + +/** + * devm_gpiod_put - Resource-managed gpiod_put() + * @dev: GPIO consumer + * @desc: GPIO descriptor to dispose of + * + * Dispose of a GPIO descriptor obtained with devm_gpiod_get() or + * devm_gpiod_get_index(). Normally this function will not be called as the GPIO + * will be disposed of by the resource management code. + */ +void devm_gpiod_put(struct udevice *dev, struct gpio_desc *desc); + +#endif /* _ASM_GENERIC_GPIO_H_ */ diff --git a/roms/u-boot/include/asm-generic/int-ll64.h b/roms/u-boot/include/asm-generic/int-ll64.h new file mode 100644 index 000000000..7451718a6 --- /dev/null +++ b/roms/u-boot/include/asm-generic/int-ll64.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * asm-generic/int-ll64.h + * + * Integer declarations for architectures which use "long long" + * for 64-bit types. + */ + +#ifndef _ASM_GENERIC_INT_LL64_H +#define _ASM_GENERIC_INT_LL64_H + +#ifndef __ASSEMBLY__ +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#ifdef __GNUC__ +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; +#else +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +typedef __s8 s8; +typedef __u8 u8; +typedef __s16 s16; +typedef __u16 u16; +typedef __s32 s32; +typedef __u32 u32; +typedef __s64 s64; +typedef __u64 u64; + +#endif /* __ASSEMBLY__ */ + + +#endif /* _ASM_GENERIC_INT_LL64_H */ diff --git a/roms/u-boot/include/asm-generic/io.h b/roms/u-boot/include/asm-generic/io.h new file mode 100644 index 000000000..7a2f0dba3 --- /dev/null +++ b/roms/u-boot/include/asm-generic/io.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Generic I/O functions. + * + * Copyright (c) 2016 Imagination Technologies Ltd. + */ + +#ifndef __ASM_GENERIC_IO_H__ +#define __ASM_GENERIC_IO_H__ + +/* + * This file should be included at the end of each architecture-specific + * asm/io.h such that we may provide generic implementations without + * conflicting with architecture-specific code. + */ + +#ifndef __ASSEMBLY__ + +/** + * phys_to_virt() - Return a virtual address mapped to a given physical address + * @paddr: the physical address + * + * Returns a virtual address which the CPU can access that maps to the physical + * address @paddr. This should only be used where it is known that no dynamic + * mapping is required. In general, map_physmem should be used instead. + * + * Returns: a virtual address which maps to @paddr + */ +#ifndef phys_to_virt +static inline void *phys_to_virt(phys_addr_t paddr) +{ + return (void *)(unsigned long)paddr; +} +#endif + +/** + * virt_to_phys() - Return the physical address that a virtual address maps to + * @vaddr: the virtual address + * + * Returns the physical address which the CPU-accessible virtual address @vaddr + * maps to. + * + * Returns: the physical address which @vaddr maps to + */ +#ifndef virt_to_phys +static inline phys_addr_t virt_to_phys(void *vaddr) +{ + return (phys_addr_t)((unsigned long)vaddr); +} +#endif + +/* + * Flags for use with map_physmem() & unmap_physmem(). Architectures need not + * support all of these, in which case they will be defined as zero here & + * ignored. Callers that may run on multiple architectures should therefore + * treat them as hints rather than requirements. + */ +#ifndef MAP_NOCACHE +# define MAP_NOCACHE 0 /* Produce an uncached mapping */ +#endif +#ifndef MAP_WRCOMBINE +# define MAP_WRCOMBINE 0 /* Allow write-combining on the mapping */ +#endif +#ifndef MAP_WRBACK +# define MAP_WRBACK 0 /* Map using write-back caching */ +#endif +#ifndef MAP_WRTHROUGH +# define MAP_WRTHROUGH 0 /* Map using write-through caching */ +#endif + +/** + * map_physmem() - Return a virtual address mapped to a given physical address + * @paddr: the physical address + * @len: the length of the required mapping + * @flags: flags affecting the type of mapping + * + * Return a virtual address through which the CPU may access the memory at + * physical address @paddr. The mapping will be valid for at least @len bytes, + * and may be affected by flags passed to the @flags argument. This function + * may create new mappings, so should generally be paired with a matching call + * to unmap_physmem once the caller is finished with the memory in question. + * + * Returns: a virtual address suitably mapped to @paddr + */ +#ifndef map_physmem +static inline void *map_physmem(phys_addr_t paddr, unsigned long len, + unsigned long flags) +{ + return phys_to_virt(paddr); +} +#endif + +/** + * unmap_physmem() - Remove mappings created by a prior call to map_physmem() + * @vaddr: the virtual address which map_physmem() previously returned + * @flags: flags matching those originally passed to map_physmem() + * + * Unmap memory which was previously mapped by a call to map_physmem(). If + * map_physmem() dynamically created a mapping for the memory in question then + * unmap_physmem() will remove that mapping. + */ +#ifndef unmap_physmem +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ +} +#endif + +#endif /* !__ASSEMBLY__ */ +#endif /* __ASM_GENERIC_IO_H__ */ diff --git a/roms/u-boot/include/asm-generic/ioctl.h b/roms/u-boot/include/asm-generic/ioctl.h new file mode 100644 index 000000000..15828b2d6 --- /dev/null +++ b/roms/u-boot/include/asm-generic/ioctl.h @@ -0,0 +1,105 @@ +#ifndef _ASM_GENERIC_IOCTL_H +#define _ASM_GENERIC_IOCTL_H + +/* ioctl command encoding: 32 bits total, command in lower 16 bits, + * size of the parameter structure in the lower 14 bits of the + * upper 16 bits. + * Encoding the size of the parameter structure in the ioctl request + * is useful for catching programs compiled with old versions + * and to avoid overwriting user space outside the user buffer area. + * The highest 2 bits are reserved for indicating the ``access mode''. + * NOTE: This limits the max parameter size to 16kB -1 ! + */ + +/* + * The following is for compatibility across the various Linux + * platforms. The generic ioctl numbering scheme doesn't really enforce + * a type field. De facto, however, the top 8 bits of the lower 16 + * bits are indeed used as a type field, so we might just as well make + * this explicit here. Please be sure to use the decoding macros + * below from now on. + */ +#define _IOC_NRBITS 8 +#define _IOC_TYPEBITS 8 + +/* + * Let any architecture override either of the following before + * including this file. + */ + +#ifndef _IOC_SIZEBITS +# define _IOC_SIZEBITS 14 +#endif + +#ifndef _IOC_DIRBITS +# define _IOC_DIRBITS 2 +#endif + +#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1) +#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) +#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) +#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) + +#define _IOC_NRSHIFT 0 +#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) +#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) +#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) + +/* + * Direction bits, which any architecture can choose to override + * before including this file. + */ + +#ifndef _IOC_NONE +# define _IOC_NONE 0U +#endif + +#ifndef _IOC_WRITE +# define _IOC_WRITE 1U +#endif + +#ifndef _IOC_READ +# define _IOC_READ 2U +#endif + +#define _IOC(dir,type,nr,size) \ + (((dir) << _IOC_DIRSHIFT) | \ + ((type) << _IOC_TYPESHIFT) | \ + ((nr) << _IOC_NRSHIFT) | \ + ((size) << _IOC_SIZESHIFT)) + +#ifdef __KERNEL__ +/* provoke compile error for invalid uses of size argument */ +extern unsigned int __invalid_size_argument_for_IOC; +#define _IOC_TYPECHECK(t) \ + ((sizeof(t) == sizeof(t[1]) && \ + sizeof(t) < (1 << _IOC_SIZEBITS)) ? \ + sizeof(t) : __invalid_size_argument_for_IOC) +#else +#define _IOC_TYPECHECK(t) (sizeof(t)) +#endif + +/* used to create numbers */ +#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) +#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size))) +#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) +#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) +#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) +#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) +#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) + +/* used to decode ioctl numbers.. */ +#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) +#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) +#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) +#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) + +/* ...and for the drivers/sound files... */ + +#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) +#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) +#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) +#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) +#define IOCSIZE_SHIFT (_IOC_SIZESHIFT) + +#endif /* _ASM_GENERIC_IOCTL_H */ diff --git a/roms/u-boot/include/asm-generic/pe.h b/roms/u-boot/include/asm-generic/pe.h new file mode 100644 index 000000000..a1df74713 --- /dev/null +++ b/roms/u-boot/include/asm-generic/pe.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Portable Executable and Common Object Constants + * + * Copyright (c) 2018 Heinrich Schuchardt + * + * based on the "Microsoft Portable Executable and Common Object File Format + * Specification", revision 11, 2017-01-23 + */ + +#ifndef _ASM_PE_H +#define _ASM_PE_H + +/* Characteristics */ +#define IMAGE_FILE_RELOCS_STRIPPED 0x0001 +#define IMAGE_FILE_EXECUTABLE_IMAGE 0x0002 +#define IMAGE_FILE_LINE_NUMS_STRIPPED 0x0004 +#define IMAGE_FILE_LOCAL_SYMS_STRIPPED 0x0008 +#define IMAGE_FILE_AGGRESSIVE_WS_TRIM 0x0010 +#define IMAGE_FILE_LARGE_ADDRESS_AWARE 0x0020 +/* Reserved 0x0040 */ +#define IMAGE_FILE_BYTES_REVERSED_LO 0x0080 +#define IMAGE_FILE_32BIT_MACHINE 0x0100 +#define IMAGE_FILE_DEBUG_STRIPPED 0x0200 +#define IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP 0x0400 +#define IMAGE_FILE_NET_RUN_FROM_SWAP 0x0800 +#define IMAGE_FILE_SYSTEM 0x1000 +#define IMAGE_FILE_DLL 0x2000 +#define IMAGE_FILE_UP_SYSTEM_ONLY 0x4000 +#define IMAGE_FILE_BYTES_REVERSED_HI 0x8000 + +/* Machine types */ +#define IMAGE_FILE_MACHINE_I386 0x014c +#define IMAGE_FILE_MACHINE_ARM 0x01c0 +#define IMAGE_FILE_MACHINE_THUMB 0x01c2 +#define IMAGE_FILE_MACHINE_ARMNT 0x01c4 +#define IMAGE_FILE_MACHINE_AMD64 0x8664 +#define IMAGE_FILE_MACHINE_ARM64 0xaa64 +#define IMAGE_FILE_MACHINE_RISCV32 0x5032 +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 + +/* Header magic constants */ +#define IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x010b +#define IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x020b +#define IMAGE_DOS_SIGNATURE 0x5a4d /* MZ */ +#define IMAGE_NT_SIGNATURE 0x00004550 /* PE00 */ + +/* Subsystem type */ +#define IMAGE_SUBSYSTEM_EFI_APPLICATION 10 +#define IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11 +#define IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12 +#define IMAGE_SUBSYSTEM_EFI_ROM 13 + +#define LINUX_ARM64_MAGIC 0x644d5241 + +#endif /* _ASM_PE_H */ diff --git a/roms/u-boot/include/asm-generic/sections.h b/roms/u-boot/include/asm-generic/sections.h new file mode 100644 index 000000000..267f1db73 --- /dev/null +++ b/roms/u-boot/include/asm-generic/sections.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + */ + +/* Taken from Linux kernel, commit f56c3196 */ + +#ifndef _ASM_GENERIC_SECTIONS_H_ +#define _ASM_GENERIC_SECTIONS_H_ + +#include + +/* References to section boundaries */ + +extern char _text[], _stext[], _etext[]; +extern char _data[], _sdata[], _edata[]; +extern char __bss_start[], __bss_stop[]; +extern char __init_begin[], __init_end[]; +extern char _sinittext[], _einittext[]; +extern char _end[], _init[]; +extern char __per_cpu_load[], __per_cpu_start[], __per_cpu_end[]; +extern char __kprobes_text_start[], __kprobes_text_end[]; +extern char __entry_text_start[], __entry_text_end[]; +extern char __initdata_begin[], __initdata_end[]; +extern char __start_rodata[], __end_rodata[]; +extern char __efi_helloworld_begin[]; +extern char __efi_helloworld_end[]; +extern char __efi_var_file_begin[]; +extern char __efi_var_file_end[]; + +/* Private data used by of-platdata devices/uclasses */ +extern char __priv_data_start[], __priv_data_end[]; + +/* Start and end of .ctors section - used for constructor calls. */ +extern char __ctors_start[], __ctors_end[]; + +/* function descriptor handling (if any). Override + * in asm/sections.h */ +#ifndef dereference_function_descriptor +#define dereference_function_descriptor(p) (p) +#endif + +/* random extra sections (if any). Override + * in asm/sections.h */ +#ifndef arch_is_kernel_text +static inline int arch_is_kernel_text(unsigned long addr) +{ + return 0; +} +#endif + +#ifndef arch_is_kernel_data +static inline int arch_is_kernel_data(unsigned long addr) +{ + return 0; +} +#endif + +/* U-Boot-specific things begin here */ + +/* Start of U-Boot text region */ +extern char __text_start[]; + +/* This marks the end of the text region which must be relocated */ +extern char __image_copy_end[]; + +/* + * This is the U-Boot entry point - prior to relocation it should be same + * as __text_start + */ +extern void _start(void); + +/* + * ARM defines its symbols as char[]. Other arches define them as ulongs. + */ +#ifdef CONFIG_ARM + +extern char __bss_start[]; +extern char __bss_end[]; +extern char __image_copy_start[]; +extern char __image_copy_end[]; +extern char _image_binary_end[]; +extern char __rel_dyn_start[]; +extern char __rel_dyn_end[]; + +#else /* don't use offsets: */ + +/* Exports from the Linker Script */ +extern ulong __data_end; +extern ulong __rel_dyn_start; +extern ulong __rel_dyn_end; +extern ulong __bss_end; +extern ulong _image_binary_end; + +extern ulong _TEXT_BASE; /* code start */ + +#endif + +#endif /* _ASM_GENERIC_SECTIONS_H_ */ diff --git a/roms/u-boot/include/asm-generic/signal.h b/roms/u-boot/include/asm-generic/signal.h new file mode 100644 index 000000000..af939478c --- /dev/null +++ b/roms/u-boot/include/asm-generic/signal.h @@ -0,0 +1,101 @@ +#ifndef __ASM_GENERIC_SIGNAL_H +#define __ASM_GENERIC_SIGNAL_H + +#include + +#define _NSIG 64 +#define _NSIG_BPW BITS_PER_LONG +#define _NSIG_WORDS (_NSIG / _NSIG_BPW) + +#define SIGHUP 1 +#define SIGINT 2 +#define SIGQUIT 3 +#define SIGILL 4 +#define SIGTRAP 5 +#define SIGABRT 6 +#define SIGIOT 6 +#define SIGBUS 7 +#define SIGFPE 8 +#define SIGKILL 9 +#define SIGUSR1 10 +#define SIGSEGV 11 +#define SIGUSR2 12 +#define SIGPIPE 13 +#define SIGALRM 14 +#define SIGTERM 15 +#define SIGSTKFLT 16 +#define SIGCHLD 17 +#define SIGCONT 18 +#define SIGSTOP 19 +#define SIGTSTP 20 +#define SIGTTIN 21 +#define SIGTTOU 22 +#define SIGURG 23 +#define SIGXCPU 24 +#define SIGXFSZ 25 +#define SIGVTALRM 26 +#define SIGPROF 27 +#define SIGWINCH 28 +#define SIGIO 29 +#define SIGPOLL SIGIO +/* +#define SIGLOST 29 +*/ +#define SIGPWR 30 +#define SIGSYS 31 +#define SIGUNUSED 31 + +/* These should not be considered constants from userland. */ +#define SIGRTMIN 32 +#ifndef SIGRTMAX +#define SIGRTMAX _NSIG +#endif + +/* + * SA_FLAGS values: + * + * SA_ONSTACK indicates that a registered stack_t will be used. + * SA_RESTART flag to get restarting signals (which were the default long ago) + * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. + * SA_RESETHAND clears the handler when the signal is delivered. + * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. + * SA_NODEFER prevents the current signal from being masked in the handler. + * + * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single + * Unix names RESETHAND and NODEFER respectively. + */ +#define SA_NOCLDSTOP 0x00000001 +#define SA_NOCLDWAIT 0x00000002 +#define SA_SIGINFO 0x00000004 +#define SA_ONSTACK 0x08000000 +#define SA_RESTART 0x10000000 +#define SA_NODEFER 0x40000000 +#define SA_RESETHAND 0x80000000 + +#define SA_NOMASK SA_NODEFER +#define SA_ONESHOT SA_RESETHAND + +/* + * New architectures should not define the obsolete + * SA_RESTORER 0x04000000 + */ + +/* + * sigaltstack controls + */ +#define SS_ONSTACK 1 +#define SS_DISABLE 2 + +#define MINSIGSTKSZ 2048 +#define SIGSTKSZ 8192 + +#ifndef __ASSEMBLY__ +typedef struct { + unsigned long sig[_NSIG_WORDS]; +} sigset_t; + +/* not actually used, but required for linux/syscalls.h */ + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_GENERIC_SIGNAL_H */ diff --git a/roms/u-boot/include/asm-generic/types.h b/roms/u-boot/include/asm-generic/types.h new file mode 100644 index 000000000..7c076c56c --- /dev/null +++ b/roms/u-boot/include/asm-generic/types.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_TYPES_H +#define _ASM_GENERIC_TYPES_H +/* + * int-ll64 is used everywhere now. + */ +#include + +#endif /* _ASM_GENERIC_TYPES_H */ diff --git a/roms/u-boot/include/asm-generic/u-boot.h b/roms/u-boot/include/asm-generic/u-boot.h new file mode 100644 index 000000000..637de0c45 --- /dev/null +++ b/roms/u-boot/include/asm-generic/u-boot.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * (C) Copyright 2000 - 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef __ASM_GENERIC_U_BOOT_H__ +#define __ASM_GENERIC_U_BOOT_H__ + +/* + * Board information passed to Linux kernel from U-Boot + * + * include/asm-ppc/u-boot.h + */ + +#ifndef __ASSEMBLY__ + +#include +#include + +struct bd_info { + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ +#ifdef CONFIG_ARM + unsigned long bi_arm_freq; /* arm frequency */ + unsigned long bi_dsp_freq; /* dsp core frequency */ + unsigned long bi_ddr_freq; /* ddr frequency */ +#endif +#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) + unsigned long bi_immr_base; /* base of IMMR register */ +#endif +#if defined(CONFIG_M68K) + unsigned long bi_mbar_base; /* base of internal registers */ +#endif +#if defined(CONFIG_MPC83xx) + unsigned long bi_immrbar; +#endif + unsigned long bi_bootflags; /* boot / reboot flag (Unused) */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */ + unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ + unsigned long bi_intfreq; /* Internal Freq, in MHz */ + unsigned long bi_busfreq; /* Bus Freq, in MHz */ +#if defined(CONFIG_CPM2) + unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ + unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ + unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ + unsigned long bi_vco; /* VCO Out from PLL, in MHz */ +#endif +#if defined(CONFIG_M68K) + unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ +#endif +#if defined(CONFIG_EXTRA_CLOCK) + unsigned long bi_inpfreq; /* input Freq in MHz */ + unsigned long bi_vcofreq; /* vco Freq in MHz */ + unsigned long bi_flbfreq; /* Flexbus Freq in MHz */ +#endif + ulong bi_arch_number; /* unique id for this board */ + ulong bi_boot_params; /* where this board expects params */ + struct { /* RAM configuration */ + phys_addr_t start; + phys_size_t size; + } bi_dram[CONFIG_NR_DRAM_BANKS]; +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_GENERIC_U_BOOT_H__ */ diff --git a/roms/u-boot/include/asm-generic/unaligned.h b/roms/u-boot/include/asm-generic/unaligned.h new file mode 100644 index 000000000..3d33a5a06 --- /dev/null +++ b/roms/u-boot/include/asm-generic/unaligned.h @@ -0,0 +1,26 @@ +#ifndef _GENERIC_UNALIGNED_H +#define _GENERIC_UNALIGNED_H + +#include + +#include +#include +#include + +/* + * Select endianness + */ +#if defined(__LITTLE_ENDIAN) +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le +#elif defined(__BIG_ENDIAN) +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be +#else +#error invalid endian +#endif + +/* Allow unaligned memory access */ +void allow_unaligned(void); + +#endif diff --git a/roms/u-boot/include/asm-offsets.h b/roms/u-boot/include/asm-offsets.h new file mode 100644 index 000000000..ad3bf1f0b --- /dev/null +++ b/roms/u-boot/include/asm-offsets.h @@ -0,0 +1,6 @@ +#ifndef DO_DEPS_ONLY + +#include +/* #include */ + +#endif diff --git a/roms/u-boot/include/ata.h b/roms/u-boot/include/ata.h new file mode 100644 index 000000000..32ad5f642 --- /dev/null +++ b/roms/u-boot/include/ata.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +/* + * Most of the following information was derived from the document + * "Information Technology - AT Attachment-3 Interface (ATA-3)", + * ANSI X3.298-1997. + */ + +#ifndef _ATA_H +#define _ATA_H + +#include + +/* Register addressing depends on the hardware design; for instance, + * 8-bit (register) and 16-bit (data) accesses might use different + * address spaces. This is implemented by the following definitions. + */ +#ifndef CONFIG_SYS_ATA_STRIDE +#define CONFIG_SYS_ATA_STRIDE 1 +#endif + +#define ATA_IO_DATA(x) (CONFIG_SYS_ATA_DATA_OFFSET+((x) * CONFIG_SYS_ATA_STRIDE)) +#define ATA_IO_REG(x) (CONFIG_SYS_ATA_REG_OFFSET +((x) * CONFIG_SYS_ATA_STRIDE)) +#define ATA_IO_ALT(x) (CONFIG_SYS_ATA_ALT_OFFSET +((x) * CONFIG_SYS_ATA_STRIDE)) + +/* + * I/O Register Descriptions + */ +#define ATA_DATA_REG ATA_IO_DATA(0) +#define ATA_ERROR_REG ATA_IO_REG(1) +#define ATA_SECT_CNT ATA_IO_REG(2) +#define ATA_SECT_NUM ATA_IO_REG(3) +#define ATA_CYL_LOW ATA_IO_REG(4) +#define ATA_CYL_HIGH ATA_IO_REG(5) +#define ATA_DEV_HD ATA_IO_REG(6) +#define ATA_COMMAND ATA_IO_REG(7) +#define ATA_DATA_EVEN ATA_IO_REG(8) +#define ATA_DATA_ODD ATA_IO_REG(9) +#define ATA_STATUS ATA_COMMAND +#define ATA_DEV_CTL ATA_IO_ALT(6) +#define ATA_LBA_LOW ATA_SECT_NUM +#define ATA_LBA_MID ATA_CYL_LOW +#define ATA_LBA_HIGH ATA_CYL_HIGH +#define ATA_LBA_SEL ATA_DEV_CTL + +/* + * Status register bits + */ +#define ATA_STAT_BUSY 0x80 /* Device Busy */ +#define ATA_STAT_READY 0x40 /* Device Ready */ +#define ATA_STAT_FAULT 0x20 /* Device Fault */ +#define ATA_STAT_SEEK 0x10 /* Device Seek Complete */ +#define ATA_STAT_DRQ 0x08 /* Data Request (ready) */ +#define ATA_STAT_CORR 0x04 /* Corrected Data Error */ +#define ATA_STAT_INDEX 0x02 /* Vendor specific */ +#define ATA_STAT_ERR 0x01 /* Error */ + +/* + * Device / Head Register Bits + */ +#ifndef ATA_DEVICE +#define ATA_DEVICE(x) ((x & 1)<<4) +#endif /* ATA_DEVICE */ +#define ATA_LBA 0xE0 + +/* + * ATAPI Commands + */ +#define ATAPI_CMD_INQUIRY 0x12 +#define ATAPI_CMD_REQ_SENSE 0x03 +#define ATAPI_CMD_READ_CAP 0x25 +#define ATAPI_CMD_START_STOP 0x1B +#define ATAPI_CMD_READ_12 0xA8 + + +#define ATA_GET_ERR() inb(ATA_STATUS) +#define ATA_GET_STAT() inb(ATA_STATUS) +#define ATA_OK_STAT(stat,good,bad) (((stat)&((good)|(bad)))==(good)) +#define ATA_BAD_R_STAT (ATA_STAT_BUSY | ATA_STAT_ERR) +#define ATA_BAD_W_STAT (ATA_BAD_R_STAT | ATA_STAT_FAULT) +#define ATA_BAD_STAT (ATA_BAD_R_STAT | ATA_STAT_DRQ) +#define ATA_DRIVE_READY (ATA_READY_STAT | ATA_STAT_SEEK) +#define ATA_DATA_READY (ATA_STAT_DRQ) + +#define ATA_BLOCKSIZE 512 /* bytes */ +#define ATA_BLOCKSHIFT 9 /* 2 ^ ATA_BLOCKSIZESHIFT = 512 */ +#define ATA_SECTORWORDS (512 / sizeof(uint32_t)) + +#ifndef ATA_RESET_TIME +#define ATA_RESET_TIME 60 /* spec allows up to 31 seconds */ +#endif + +/* ------------------------------------------------------------------------- */ + +/* + * structure returned by ATA_CMD_IDENT, as per ANSI ATA2 rev.2f spec + */ +typedef struct hd_driveid { + unsigned short config; /* lots of obsolete bit flags */ + unsigned short cyls; /* "physical" cyls */ + unsigned short reserved2; /* reserved (word 2) */ + unsigned short heads; /* "physical" heads */ + unsigned short track_bytes; /* unformatted bytes per track */ + unsigned short sector_bytes; /* unformatted bytes per sector */ + unsigned short sectors; /* "physical" sectors per track */ + unsigned short vendor0; /* vendor unique */ + unsigned short vendor1; /* vendor unique */ + unsigned short vendor2; /* vendor unique */ + unsigned char serial_no[20]; /* 0 = not_specified */ + unsigned short buf_type; + unsigned short buf_size; /* 512 byte increments; 0 = not_specified */ + unsigned short ecc_bytes; /* for r/w long cmds; 0 = not_specified */ + unsigned char fw_rev[8]; /* 0 = not_specified */ + unsigned char model[40]; /* 0 = not_specified */ + unsigned char max_multsect; /* 0=not_implemented */ + unsigned char vendor3; /* vendor unique */ + unsigned short dword_io; /* 0=not_implemented; 1=implemented */ + unsigned char vendor4; /* vendor unique */ + unsigned char capability; /* bits 0:DMA 1:LBA 2:IORDYsw 3:IORDYsup*/ + unsigned short reserved50; /* reserved (word 50) */ + unsigned char vendor5; /* vendor unique */ + unsigned char tPIO; /* 0=slow, 1=medium, 2=fast */ + unsigned char vendor6; /* vendor unique */ + unsigned char tDMA; /* 0=slow, 1=medium, 2=fast */ + unsigned short field_valid; /* bits 0:cur_ok 1:eide_ok */ + unsigned short cur_cyls; /* logical cylinders */ + unsigned short cur_heads; /* logical heads */ + unsigned short cur_sectors; /* logical sectors per track */ + unsigned short cur_capacity0; /* logical total sectors on drive */ + unsigned short cur_capacity1; /* (2 words, misaligned int) */ + unsigned char multsect; /* current multiple sector count */ + unsigned char multsect_valid; /* when (bit0==1) multsect is ok */ + unsigned short lba_capacity[2];/* two words containing total number of sectors */ + unsigned short dma_1word; /* single-word dma info */ + unsigned short dma_mword; /* multiple-word dma info */ + unsigned short eide_pio_modes; /* bits 0:mode3 1:mode4 */ + unsigned short eide_dma_min; /* min mword dma cycle time (ns) */ + unsigned short eide_dma_time; /* recommended mword dma cycle time (ns) */ + unsigned short eide_pio; /* min cycle time (ns), no IORDY */ + unsigned short eide_pio_iordy; /* min cycle time (ns), with IORDY */ + unsigned short words69_70[2]; /* reserved words 69-70 */ + unsigned short words71_74[4]; /* reserved words 71-74 */ + unsigned short queue_depth; /* */ + unsigned short words76_79[4]; /* reserved words 76-79 */ + unsigned short major_rev_num; /* */ + unsigned short minor_rev_num; /* */ + unsigned short command_set_1; /* bits 0:Smart 1:Security 2:Removable 3:PM */ + unsigned short command_set_2; /* bits 14:Smart Enabled 13:0 zero 10:lba48 support*/ + unsigned short cfsse; /* command set-feature supported extensions */ + unsigned short cfs_enable_1; /* command set-feature enabled */ + unsigned short cfs_enable_2; /* command set-feature enabled */ + unsigned short csf_default; /* command set-feature default */ + unsigned short dma_ultra; /* */ + unsigned short word89; /* reserved (word 89) */ + unsigned short word90; /* reserved (word 90) */ + unsigned short CurAPMvalues; /* current APM values */ + unsigned short word92; /* reserved (word 92) */ + unsigned short hw_config; /* hardware config */ + unsigned short words94_99[6];/* reserved words 94-99 */ + /*unsigned long long lba48_capacity; /--* 4 16bit values containing lba 48 total number of sectors */ + unsigned short lba48_capacity[4]; /* 4 16bit values containing lba 48 total number of sectors */ + unsigned short words104_125[22];/* reserved words 104-125 */ + unsigned short last_lun; /* reserved (word 126) */ + unsigned short word127; /* reserved (word 127) */ + unsigned short dlf; /* device lock function + * 15:9 reserved + * 8 security level 1:max 0:high + * 7:6 reserved + * 5 enhanced erase + * 4 expire + * 3 frozen + * 2 locked + * 1 en/disabled + * 0 capability + */ + unsigned short csfo; /* current set features options + * 15:4 reserved + * 3 auto reassign + * 2 reverting + * 1 read-look-ahead + * 0 write cache + */ + unsigned short words130_155[26];/* reserved vendor words 130-155 */ + unsigned short word156; + unsigned short words157_159[3];/* reserved vendor words 157-159 */ + unsigned short words160_162[3];/* reserved words 160-162 */ + unsigned short cf_advanced_caps; + unsigned short words164_255[92];/* reserved words 164-255 */ +} hd_driveid_t; + + +/* + * PIO Mode Configuration + * + * See ATA-3 (AT Attachment-3 Interface) documentation, Figure 14 / Table 21 + */ + +typedef struct { + unsigned int t_setup; /* Setup Time in [ns] or clocks */ + unsigned int t_length; /* Length Time in [ns] or clocks */ + unsigned int t_hold; /* Hold Time in [ns] or clocks */ +} +pio_config_t; + +#define IDE_MAX_PIO_MODE 4 /* max suppurted PIO mode */ + +/* ------------------------------------------------------------------------- */ + +#endif /* _ATA_H */ diff --git a/roms/u-boot/include/atf_common.h b/roms/u-boot/include/atf_common.h new file mode 100644 index 000000000..d69892fac --- /dev/null +++ b/roms/u-boot/include/atf_common.h @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * This is from the ARM TF Project, + * Repository: https://github.com/ARM-software/arm-trusted-firmware.git + * File: include/common/bl_common.h + * Portions copyright (c) 2013-2016, ARM Limited and Contributors. All rights + * reserved. + * Copyright (C) 2016-2017 Rockchip Electronic Co.,Ltd + */ + +#ifndef __BL_COMMON_H__ +#define __BL_COMMON_H__ + +#define ATF_PARAM_EP 0x01 +#define ATF_PARAM_IMAGE_BINARY 0x02 +#define ATF_PARAM_BL31 0x03 +#define ATF_PARAM_BL_PARAMS 0x05 + +#define ATF_VERSION_1 0x01 +#define ATF_VERSION_2 0x02 + +#define ATF_BL31_IMAGE_ID 0x03 +#define ATF_BL32_IMAGE_ID 0x04 +#define ATF_BL33_IMAGE_ID 0x05 + +#define ATF_EP_SECURE 0x0 +#define ATF_EP_NON_SECURE 0x1 + +#define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \ + (_p)->h.type = (uint8_t)(_type); \ + (_p)->h.version = (uint8_t)(_ver); \ + (_p)->h.size = (uint16_t)sizeof(*_p); \ + (_p)->h.attr = (uint32_t)(_attr) ; \ + } while (0) + +#define MODE_RW_SHIFT 0x4 +#define MODE_RW_MASK 0x1 +#define MODE_RW_64 0x0 +#define MODE_RW_32 0x1 + +#define MODE_EL_SHIFT 0x2 +#define MODE_EL_MASK 0x3 +#define MODE_EL3 0x3 +#define MODE_EL2 0x2 +#define MODE_EL1 0x1 +#define MODE_EL0 0x0 + +#define MODE_SP_SHIFT 0x0 +#define MODE_SP_MASK 0x1 +#define MODE_SP_EL0 0x0 +#define MODE_SP_ELX 0x1 + +#define SPSR_DAIF_SHIFT 6 +#define SPSR_DAIF_MASK 0x0f + +#define SPSR_64(el, sp, daif) \ + (MODE_RW_64 << MODE_RW_SHIFT | \ + ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \ + ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \ + ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT) + +#define SPSR_FIQ (1 << 6) +#define SPSR_IRQ (1 << 7) +#define SPSR_SERROR (1 << 8) +#define SPSR_DEBUG (1 << 9) +#define SPSR_EXCEPTION_MASK (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG) + +#define DAIF_FIQ_BIT (1<<0) +#define DAIF_IRQ_BIT (1<<1) +#define DAIF_ABT_BIT (1<<2) +#define DAIF_DBG_BIT (1<<3) +#define DISABLE_ALL_EXECPTIONS \ + (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) + +#ifndef __ASSEMBLY__ + +/******************************************************************************* + * Structure used for telling the next BL how much of a particular type of + * memory is available for its use and how much is already used. + ******************************************************************************/ +struct aapcs64_params { + unsigned long arg0; + unsigned long arg1; + unsigned long arg2; + unsigned long arg3; + unsigned long arg4; + unsigned long arg5; + unsigned long arg6; + unsigned long arg7; +}; + +/*************************************************************************** + * This structure provides version information and the size of the + * structure, attributes for the structure it represents + ***************************************************************************/ +struct param_header { + uint8_t type; /* type of the structure */ + uint8_t version; /* version of this structure */ + uint16_t size; /* size of this structure in bytes */ + uint32_t attr; /* attributes: unused bits SBZ */ +}; + +/***************************************************************************** + * This structure represents the superset of information needed while + * switching exception levels. The only two mechanisms to do so are + * ERET & SMC. Security state is indicated using bit zero of header + * attribute + * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start + * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while + * processing SMC to jump to BL31. + *****************************************************************************/ +struct entry_point_info { + struct param_header h; + uintptr_t pc; + uint32_t spsr; + struct aapcs64_params args; +}; + +/***************************************************************************** + * Image info binary provides information from the image loader that + * can be used by the firmware to manage available trusted RAM. + * More advanced firmware image formats can provide additional + * information that enables optimization or greater flexibility in the + * common firmware code + *****************************************************************************/ +struct atf_image_info { + struct param_header h; + uintptr_t image_base; /* physical address of base of image */ + uint32_t image_size; /* bytes read from image file */ +#if CONFIG_IS_ENABLED(ATF_LOAD_IMAGE_V2) + uint32_t image_max_size; +#endif +}; + +/***************************************************************************** + * The image descriptor struct definition. + *****************************************************************************/ +struct image_desc { + /* Contains unique image id for the image. */ + unsigned int image_id; + /* + * This member contains Image state information. + * Refer IMAGE_STATE_XXX defined above. + */ + unsigned int state; + uint32_t copied_size; /* image size copied in blocks */ + struct atf_image_info atf_image_info; + struct entry_point_info ep_info; +}; + +/******************************************************************************* + * This structure represents the superset of information that can be passed to + * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be + * populated only if BL2 detects its presence. A pointer to a structure of this + * type should be passed in X0 to BL31's cold boot entrypoint. + * + * Use of this structure and the X0 parameter is not mandatory: the BL31 + * platform code can use other mechanisms to provide the necessary information + * about BL32 and BL33 to the common and SPD code. + * + * BL31 image information is mandatory if this structure is used. If either of + * the optional BL32 and BL33 image information is not provided, this is + * indicated by the respective image_info pointers being zero. + ******************************************************************************/ +struct bl31_params { + struct param_header h; + struct atf_image_info *bl31_image_info; + struct entry_point_info *bl32_ep_info; + struct atf_image_info *bl32_image_info; + struct entry_point_info *bl33_ep_info; + struct atf_image_info *bl33_image_info; +}; + +/* BL image node in the BL image execution sequence */ +struct bl_params_node { + unsigned int image_id; + struct atf_image_info *image_info; + struct entry_point_info *ep_info; + struct bl_params_node *next_params_info; +}; + +/* + * BL image head node in the BL image execution sequence + * It is also used to pass information to next BL image. + */ +struct bl_params { + struct param_header h; + struct bl_params_node *head; +}; + +#define for_each_bl_params_node(bl_params, node) \ + for ((node) = (bl_params)->head; \ + (node); \ + (node) = (node)->next_params_info) + +#endif /*__ASSEMBLY__ */ + +#endif /* __BL_COMMON_H__ */ diff --git a/roms/u-boot/include/atmel_hlcdc.h b/roms/u-boot/include/atmel_hlcdc.h new file mode 100644 index 000000000..5e339f50f --- /dev/null +++ b/roms/u-boot/include/atmel_hlcdc.h @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Header file for AT91/AT32 MULTI LAYER LCD Controller + * + * Data structure and register user interface + * + * Copyright (C) 2012 Atmel Corporation + */ +#ifndef __ATMEL_HLCDC_H__ +#define __ATMEL_HLCDC_H__ + +/* Atmel multi layer lcdc hardware registers */ +struct atmel_hlcd_regs { + u32 lcdc_lcdcfg0; + u32 lcdc_lcdcfg1; + u32 lcdc_lcdcfg2; + u32 lcdc_lcdcfg3; + u32 lcdc_lcdcfg4; + u32 lcdc_lcdcfg5; + u32 lcdc_lcdcfg6; + u32 res1; + u32 lcdc_lcden; + u32 lcdc_lcddis; + u32 lcdc_lcdsr; + u32 res2; + u32 lcdc_lcdidr; + u32 res3[3]; + u32 lcdc_basecher; + u32 res4[3]; + u32 lcdc_baseidr; + u32 res5[3]; + u32 lcdc_baseaddr; + u32 lcdc_basectrl; + u32 lcdc_basenext; + u32 lcdc_basecfg0; + u32 lcdc_basecfg1; + u32 lcdc_basecfg2; + u32 lcdc_basecfg3; + u32 lcdc_basecfg4; +}; + +#define LCDC_LCDCFG0_CLKPOL (0x1 << 0) +#define LCDC_LCDCFG0_CLKSEL (0x1 << 2) +#define LCDC_LCDCFG0_CLKPWMSEL (0x1 << 3) +#define LCDC_LCDCFG0_CGDISBASE (0x1 << 8) +#define LCDC_LCDCFG0_CGDISOVR1 (0x1 << 9) +#define LCDC_LCDCFG0_CGDISHEO (0x1 << 11) +#define LCDC_LCDCFG0_CGDISHCR (0x1 << 12) +#define LCDC_LCDCFG0_CLKDIV_Pos 16 +#define LCDC_LCDCFG0_CLKDIV_Msk (0xff << LCDC_LCDCFG0_CLKDIV_Pos) +#define LCDC_LCDCFG0_CLKDIV(value) \ + ((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos))) + +#define LCDC_LCDCFG1_HSPW_Pos 0 +#define LCDC_LCDCFG1_HSPW_Msk (0x3f << LCDC_LCDCFG1_HSPW_Pos) +#define LCDC_LCDCFG1_HSPW(value) \ + ((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos))) +#define LCDC_LCDCFG1_VSPW_Pos 16 +#define LCDC_LCDCFG1_VSPW_Msk (0x3f << LCDC_LCDCFG1_VSPW_Pos) +#define LCDC_LCDCFG1_VSPW(value) \ + ((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos))) + +#define LCDC_LCDCFG2_VFPW_Pos 0 +#define LCDC_LCDCFG2_VFPW_Msk (0x3f << LCDC_LCDCFG2_VFPW_Pos) +#define LCDC_LCDCFG2_VFPW(value) \ + ((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos))) +#define LCDC_LCDCFG2_VBPW_Pos 16 +#define LCDC_LCDCFG2_VBPW_Msk (0x3f << LCDC_LCDCFG2_VBPW_Pos) +#define LCDC_LCDCFG2_VBPW(value) \ + ((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos))) + +#define LCDC_LCDCFG3_HFPW_Pos 0 +#define LCDC_LCDCFG3_HFPW_Msk (0xff << LCDC_LCDCFG3_HFPW_Pos) +#define LCDC_LCDCFG3_HFPW(value) \ + ((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos))) +#define LCDC_LCDCFG3_HBPW_Pos 16 +#define LCDC_LCDCFG3_HBPW_Msk (0xff << LCDC_LCDCFG3_HBPW_Pos) +#define LCDC_LCDCFG3_HBPW(value) \ + ((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos))) + +#define LCDC_LCDCFG4_PPL_Pos 0 +#define LCDC_LCDCFG4_PPL_Msk (0x7ff << LCDC_LCDCFG4_PPL_Pos) +#define LCDC_LCDCFG4_PPL(value) \ + ((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos))) +#define LCDC_LCDCFG4_RPF_Pos 16 +#define LCDC_LCDCFG4_RPF_Msk (0x7ff << LCDC_LCDCFG4_RPF_Pos) +#define LCDC_LCDCFG4_RPF(value) \ + ((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos))) + +#define LCDC_LCDCFG5_HSPOL (0x1 << 0) +#define LCDC_LCDCFG5_VSPOL (0x1 << 1) +#define LCDC_LCDCFG5_VSPDLYS (0x1 << 2) +#define LCDC_LCDCFG5_VSPDLYE (0x1 << 3) +#define LCDC_LCDCFG5_DISPPOL (0x1 << 4) +#define LCDC_LCDCFG5_SERIAL (0x1 << 5) +#define LCDC_LCDCFG5_DITHER (0x1 << 6) +#define LCDC_LCDCFG5_DISPDLY (0x1 << 7) +#define LCDC_LCDCFG5_MODE_Pos 8 +#define LCDC_LCDCFG5_MODE_Msk (0x3 << LCDC_LCDCFG5_MODE_Pos) +#define LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0 << 8) +#define LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1 << 8) +#define LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2 << 8) +#define LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3 << 8) +#define LCDC_LCDCFG5_VSPSU (0x1 << 12) +#define LCDC_LCDCFG5_VSPHO (0x1 << 13) +#define LCDC_LCDCFG5_GUARDTIME_Pos 16 +#define LCDC_LCDCFG5_GUARDTIME_Msk (0x1f << LCDC_LCDCFG5_GUARDTIME_Pos) +#define LCDC_LCDCFG5_GUARDTIME(value) \ + ((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos))) + +#define LCDC_LCDCFG6_PWMPS_Pos 0 +#define LCDC_LCDCFG6_PWMPS_Msk (0x7 << LCDC_LCDCFG6_PWMPS_Pos) +#define LCDC_LCDCFG6_PWMPS(value) \ + ((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos))) +#define LCDC_LCDCFG6_PWMPOL (0x1 << 4) +#define LCDC_LCDCFG6_PWMCVAL_Pos 8 +#define LCDC_LCDCFG6_PWMCVAL_Msk (0xff << LCDC_LCDCFG6_PWMCVAL_Pos) +#define LCDC_LCDCFG6_PWMCVAL(value) \ + ((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos))) + +#define LCDC_LCDEN_CLKEN (0x1 << 0) +#define LCDC_LCDEN_SYNCEN (0x1 << 1) +#define LCDC_LCDEN_DISPEN (0x1 << 2) +#define LCDC_LCDEN_PWMEN (0x1 << 3) + +#define LCDC_LCDDIS_CLKDIS (0x1 << 0) +#define LCDC_LCDDIS_SYNCDIS (0x1 << 1) +#define LCDC_LCDDIS_DISPDIS (0x1 << 2) +#define LCDC_LCDDIS_PWMDIS (0x1 << 3) +#define LCDC_LCDDIS_CLKRST (0x1 << 8) +#define LCDC_LCDDIS_SYNCRST (0x1 << 9) +#define LCDC_LCDDIS_DISPRST (0x1 << 10) +#define LCDC_LCDDIS_PWMRST (0x1 << 11) + +#define LCDC_LCDSR_CLKSTS (0x1 << 0) +#define LCDC_LCDSR_LCDSTS (0x1 << 1) +#define LCDC_LCDSR_DISPSTS (0x1 << 2) +#define LCDC_LCDSR_PWMSTS (0x1 << 3) +#define LCDC_LCDSR_SIPSTS (0x1 << 4) + +#define LCDC_LCDIDR_SOFID (0x1 << 0) +#define LCDC_LCDIDR_DISID (0x1 << 1) +#define LCDC_LCDIDR_DISPID (0x1 << 2) +#define LCDC_LCDIDR_FIFOERRID (0x1 << 4) +#define LCDC_LCDIDR_BASEID (0x1 << 8) +#define LCDC_LCDIDR_OVR1ID (0x1 << 9) +#define LCDC_LCDIDR_HEOID (0x1 << 11) +#define LCDC_LCDIDR_HCRID (0x1 << 12) + +#define LCDC_BASECHER_CHEN (0x1 << 0) +#define LCDC_BASECHER_UPDATEEN (0x1 << 1) +#define LCDC_BASECHER_A2QEN (0x1 << 2) + +#define LCDC_BASEIDR_DMA (0x1 << 2) +#define LCDC_BASEIDR_DSCR (0x1 << 3) +#define LCDC_BASEIDR_ADD (0x1 << 4) +#define LCDC_BASEIDR_DONE (0x1 << 5) +#define LCDC_BASEIDR_OVR (0x1 << 6) + +#define LCDC_BASECTRL_DFETCH (0x1 << 0) +#define LCDC_BASECTRL_LFETCH (0x1 << 1) +#define LCDC_BASECTRL_DMAIEN (0x1 << 2) +#define LCDC_BASECTRL_DSCRIEN (0x1 << 3) +#define LCDC_BASECTRL_ADDIEN (0x1 << 4) +#define LCDC_BASECTRL_DONEIEN (0x1 << 5) + +#define LCDC_BASECFG0_BLEN_Pos 4 +#define LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0 << 4) +#define LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1 << 4) +#define LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2 << 4) +#define LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3 << 4) +#define LCDC_BASECFG0_DLBO (0x1 << 8) + +#define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) +#define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) +#define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) +#define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) +#define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) +#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) +#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) +#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) +#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) +#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) +#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) +#define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) +#define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) +#define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) + +#define LCDC_BASECFG2_XSTRIDE_Pos 0 +#define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffff << LCDC_BASECFG2_XSTRIDE_Pos) +#define LCDC_BASECFG2_XSTRIDE(value) \ + ((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos))) + +#define LCDC_BASECFG3_BDEF_Pos 0 +#define LCDC_BASECFG3_BDEF_Msk (0xff << LCDC_BASECFG3_BDEF_Pos) +#define LCDC_BASECFG3_BDEF(value) \ + ((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos))) +#define LCDC_BASECFG3_GDEF_Pos 8 +#define LCDC_BASECFG3_GDEF_Msk (0xff << LCDC_BASECFG3_GDEF_Pos) +#define LCDC_BASECFG3_GDEF(value) \ + ((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos))) +#define LCDC_BASECFG3_RDEF_Pos 16 +#define LCDC_BASECFG3_RDEF_Msk (0xff << LCDC_BASECFG3_RDEF_Pos) +#define LCDC_BASECFG3_RDEF(value) \ + ((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos))) + +#define LCDC_BASECLUT_BCLUT_Pos 0 +#define LCDC_BASECLUT_BCLUT_Msk (0xff << LCDC_BASECLUT_BCLUT_Pos) +#define LCDC_BASECLUT_GCLUT_Pos 8 +#define LCDC_BASECLUT_GCLUT_Msk (0xff << LCDC_BASECLUT_GCLUT_Pos) +#define LCDC_BASECLUT_RCLUT_Pos 16 +#define LCDC_BASECLUT_RCLUT_Msk (0xff << LCDC_BASECLUT_RCLUT_Pos) + +#define LCDC_BASECFG4_DMA (0x1 << 8) +#define LCDC_BASECFG4_REP (0x1 << 9) + +struct lcd_dma_desc { + u32 address; + u32 control; + u32 next; +}; + +#define ATMEL_LCDC_LUT(n) (0x0400 + ((n)*4)) + +#endif /* __ATMEL_HLCDC_H__ */ diff --git a/roms/u-boot/include/atmel_lcd.h b/roms/u-boot/include/atmel_lcd.h new file mode 100644 index 000000000..66436b9b2 --- /dev/null +++ b/roms/u-boot/include/atmel_lcd.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * atmel_lcd.h - Atmel LCD Controller structures + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef _ATMEL_LCD_H_ +#define _ATMEL_LCD_H_ + +/** + * struct atmel_lcd_plat - platform data for Atmel LCDs with driver model + * + * @timing_index: Index of LCD timing to use in device tree node + */ +struct atmel_lcd_plat { + int timing_index; +}; + +typedef struct vidinfo { + ushort vl_col; /* Number of columns (i.e. 640) */ + ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ + u_long vl_clk; /* pixel clock in ps */ + + /* LCD configuration register */ + u_long vl_sync; /* Horizontal / vertical sync */ + u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ + u_long vl_tft; /* 0 = passive, 1 = TFT */ + u_long vl_cont_pol_low; /* contrast polarity is low */ + u_long vl_clk_pol; /* clock polarity */ + + /* Horizontal control register. */ + u_long vl_hsync_len; /* Length of horizontal sync */ + u_long vl_left_margin; /* Time from sync to picture */ + u_long vl_right_margin; /* Time from picture to sync */ + + /* Vertical control register. */ + u_long vl_vsync_len; /* Length of vertical sync */ + u_long vl_upper_margin; /* Time from sync to picture */ + u_long vl_lower_margin; /* Time from picture to sync */ + + u_long mmio; /* Memory mapped registers */ + + u_int logo_width; + u_int logo_height; + int logo_x_offset; + int logo_y_offset; + u_long logo_addr; +} vidinfo_t; + +void atmel_logo_info(vidinfo_t *info); +void microchip_logo_info(vidinfo_t *info); + +#endif diff --git a/roms/u-boot/include/atmel_lcdc.h b/roms/u-boot/include/atmel_lcdc.h new file mode 100644 index 000000000..759f8da31 --- /dev/null +++ b/roms/u-boot/include/atmel_lcdc.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Header file for AT91/AT32 LCD Controller + * + * Data structure and register user interface + * + * Copyright (C) 2007 Atmel Corporation + */ +#ifndef __ATMEL_LCDC_H__ +#define __ATMEL_LCDC_H__ + +#define ATMEL_LCDC_DMABADDR1 0x00 +#define ATMEL_LCDC_DMABADDR2 0x04 +#define ATMEL_LCDC_DMAFRMPT1 0x08 +#define ATMEL_LCDC_DMAFRMPT2 0x0c +#define ATMEL_LCDC_DMAFRMADD1 0x10 +#define ATMEL_LCDC_DMAFRMADD2 0x14 + +#define ATMEL_LCDC_DMAFRMCFG 0x18 +#define ATMEL_LCDC_FRSIZE (0x7fffff << 0) +#define ATMEL_LCDC_BLENGTH_OFFSET 24 +#define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET) + +#define ATMEL_LCDC_DMACON 0x1c +#define ATMEL_LCDC_DMAEN (0x1 << 0) +#define ATMEL_LCDC_DMARST (0x1 << 1) +#define ATMEL_LCDC_DMABUSY (0x1 << 2) +#define ATMEL_LCDC_DMAUPDT (0x1 << 3) +#define ATMEL_LCDC_DMA2DEN (0x1 << 4) + +#define ATMEL_LCDC_DMA2DCFG 0x20 +#define ATMEL_LCDC_ADDRINC_OFFSET 0 +#define ATMEL_LCDC_ADDRINC (0xffff) +#define ATMEL_LCDC_PIXELOFF_OFFSET 24 +#define ATMEL_LCDC_PIXELOFF (0x1f << 24) + +#define ATMEL_LCDC_LCDCON1 0x0800 +#define ATMEL_LCDC_BYPASS (1 << 0) +#define ATMEL_LCDC_CLKVAL_OFFSET 12 +#define ATMEL_LCDC_CLKVAL (0x1ff << ATMEL_LCDC_CLKVAL_OFFSET) +#define ATMEL_LCDC_LINCNT (0x7ff << 21) + +#define ATMEL_LCDC_LCDCON2 0x0804 +#define ATMEL_LCDC_DISTYPE (3 << 0) +#define ATMEL_LCDC_DISTYPE_STNMONO (0 << 0) +#define ATMEL_LCDC_DISTYPE_STNCOLOR (1 << 0) +#define ATMEL_LCDC_DISTYPE_TFT (2 << 0) +#define ATMEL_LCDC_SCANMOD (1 << 2) +#define ATMEL_LCDC_SCANMOD_SINGLE (0 << 2) +#define ATMEL_LCDC_SCANMOD_DUAL (1 << 2) +#define ATMEL_LCDC_IFWIDTH (3 << 3) +#define ATMEL_LCDC_IFWIDTH_4 (0 << 3) +#define ATMEL_LCDC_IFWIDTH_8 (1 << 3) +#define ATMEL_LCDC_IFWIDTH_16 (2 << 3) +#define ATMEL_LCDC_PIXELSIZE (7 << 5) +#define ATMEL_LCDC_PIXELSIZE_1 (0 << 5) +#define ATMEL_LCDC_PIXELSIZE_2 (1 << 5) +#define ATMEL_LCDC_PIXELSIZE_4 (2 << 5) +#define ATMEL_LCDC_PIXELSIZE_8 (3 << 5) +#define ATMEL_LCDC_PIXELSIZE_16 (4 << 5) +#define ATMEL_LCDC_PIXELSIZE_24 (5 << 5) +#define ATMEL_LCDC_PIXELSIZE_32 (6 << 5) +#define ATMEL_LCDC_INVVD (1 << 8) +#define ATMEL_LCDC_INVVD_NORMAL (0 << 8) +#define ATMEL_LCDC_INVVD_INVERTED (1 << 8) +#define ATMEL_LCDC_INVFRAME (1 << 9 ) +#define ATMEL_LCDC_INVFRAME_NORMAL (0 << 9) +#define ATMEL_LCDC_INVFRAME_INVERTED (1 << 9) +#define ATMEL_LCDC_INVLINE (1 << 10) +#define ATMEL_LCDC_INVLINE_NORMAL (0 << 10) +#define ATMEL_LCDC_INVLINE_INVERTED (1 << 10) +#define ATMEL_LCDC_INVCLK (1 << 11) +#define ATMEL_LCDC_INVCLK_NORMAL (0 << 11) +#define ATMEL_LCDC_INVCLK_INVERTED (1 << 11) +#define ATMEL_LCDC_INVDVAL (1 << 12) +#define ATMEL_LCDC_INVDVAL_NORMAL (0 << 12) +#define ATMEL_LCDC_INVDVAL_INVERTED (1 << 12) +#define ATMEL_LCDC_CLKMOD (1 << 15) +#define ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) +#define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) +#define ATMEL_LCDC_MEMOR (1 << 31) +#define ATMEL_LCDC_MEMOR_BIG (0 << 31) +#define ATMEL_LCDC_MEMOR_LITTLE (1 << 31) + +#define ATMEL_LCDC_TIM1 0x0808 +#define ATMEL_LCDC_VFP (0xffU << 0) +#define ATMEL_LCDC_VBP_OFFSET 8 +#define ATMEL_LCDC_VBP (0xffU << ATMEL_LCDC_VBP_OFFSET) +#define ATMEL_LCDC_VPW_OFFSET 16 +#define ATMEL_LCDC_VPW (0x3fU << ATMEL_LCDC_VPW_OFFSET) +#define ATMEL_LCDC_VHDLY_OFFSET 24 +#define ATMEL_LCDC_VHDLY (0xfU << ATMEL_LCDC_VHDLY_OFFSET) + +#define ATMEL_LCDC_TIM2 0x080c +#define ATMEL_LCDC_HBP (0xffU << 0) +#define ATMEL_LCDC_HPW_OFFSET 8 +#define ATMEL_LCDC_HPW (0x3fU << ATMEL_LCDC_HPW_OFFSET) +#define ATMEL_LCDC_HFP_OFFSET 21 +#define ATMEL_LCDC_HFP (0x7ffU << ATMEL_LCDC_HFP_OFFSET) + +#define ATMEL_LCDC_LCDFRMCFG 0x0810 +#define ATMEL_LCDC_LINEVAL (0x7ff << 0) +#define ATMEL_LCDC_HOZVAL_OFFSET 21 +#define ATMEL_LCDC_HOZVAL (0x7ff << ATMEL_LCDC_HOZVAL_OFFSET) + +#define ATMEL_LCDC_FIFO 0x0814 +#define ATMEL_LCDC_FIFOTH (0xffff) + +#define ATMEL_LCDC_MVAL 0x0818 + +#define ATMEL_LCDC_DP1_2 0x081c +#define ATMEL_LCDC_DP4_7 0x0820 +#define ATMEL_LCDC_DP3_5 0x0824 +#define ATMEL_LCDC_DP2_3 0x0828 +#define ATMEL_LCDC_DP5_7 0x082c +#define ATMEL_LCDC_DP3_4 0x0830 +#define ATMEL_LCDC_DP4_5 0x0834 +#define ATMEL_LCDC_DP6_7 0x0838 +#define ATMEL_LCDC_DP1_2_VAL (0xff) +#define ATMEL_LCDC_DP4_7_VAL (0xfffffff) +#define ATMEL_LCDC_DP3_5_VAL (0xfffff) +#define ATMEL_LCDC_DP2_3_VAL (0xfff) +#define ATMEL_LCDC_DP5_7_VAL (0xfffffff) +#define ATMEL_LCDC_DP3_4_VAL (0xffff) +#define ATMEL_LCDC_DP4_5_VAL (0xfffff) +#define ATMEL_LCDC_DP6_7_VAL (0xfffffff) + +#define ATMEL_LCDC_PWRCON 0x083c +#define ATMEL_LCDC_PWR (1 << 0) +#define ATMEL_LCDC_GUARDT_OFFSET 1 +#define ATMEL_LCDC_GUARDT (0x7f << ATMEL_LCDC_GUARDT_OFFSET) +#define ATMEL_LCDC_BUSY (1 << 31) + +#define ATMEL_LCDC_CONTRAST_CTR 0x0840 +#define ATMEL_LCDC_PS (3 << 0) +#define ATMEL_LCDC_PS_DIV1 (0 << 0) +#define ATMEL_LCDC_PS_DIV2 (1 << 0) +#define ATMEL_LCDC_PS_DIV4 (2 << 0) +#define ATMEL_LCDC_PS_DIV8 (3 << 0) +#define ATMEL_LCDC_POL (1 << 2) +#define ATMEL_LCDC_POL_NEGATIVE (0 << 2) +#define ATMEL_LCDC_POL_POSITIVE (1 << 2) +#define ATMEL_LCDC_ENA (1 << 3) +#define ATMEL_LCDC_ENA_PWMDISABLE (0 << 3) +#define ATMEL_LCDC_ENA_PWMENABLE (1 << 3) + +#define ATMEL_LCDC_CONTRAST_VAL 0x0844 +#define ATMEL_LCDC_CVAL (0xff) + +#define ATMEL_LCDC_IER 0x0848 +#define ATMEL_LCDC_IDR 0x084c +#define ATMEL_LCDC_IMR 0x0850 +#define ATMEL_LCDC_ISR 0x0854 +#define ATMEL_LCDC_ICR 0x0858 +#define ATMEL_LCDC_LNI (1 << 0) +#define ATMEL_LCDC_LSTLNI (1 << 1) +#define ATMEL_LCDC_EOFI (1 << 2) +#define ATMEL_LCDC_UFLWI (1 << 4) +#define ATMEL_LCDC_OWRI (1 << 5) +#define ATMEL_LCDC_MERI (1 << 6) + +#define ATMEL_LCDC_LUT(n) (0x0c00 + ((n)*4)) + +#endif /* __ATMEL_LCDC_H__ */ diff --git a/roms/u-boot/include/atmel_mci.h b/roms/u-boot/include/atmel_mci.h new file mode 100644 index 000000000..c7591166e --- /dev/null +++ b/roms/u-boot/include/atmel_mci.h @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2005-2006 Atmel Corporation + */ +#ifndef __ATMEL_MCI_H__ +#define __ATMEL_MCI_H__ + +int atmel_mci_init(void *regs); + +#ifndef __ASSEMBLY__ + +/* + * Structure for struct SoC access. + * Names starting with '_' are fillers. + */ +typedef struct atmel_mci { + /* reg Offset */ + u32 cr; /* 0x00 */ + u32 mr; /* 0x04 */ + u32 dtor; /* 0x08 */ + u32 sdcr; /* 0x0c */ + u32 argr; /* 0x10 */ + u32 cmdr; /* 0x14 */ + u32 blkr; /* 0x18 */ + u32 _1c; /* 0x1c */ + u32 rspr; /* 0x20 */ + u32 rspr1; /* 0x24 */ + u32 rspr2; /* 0x28 */ + u32 rspr3; /* 0x2c */ + u32 rdr; /* 0x30 */ + u32 tdr; /* 0x34 */ + u32 _38; /* 0x38 */ + u32 _3c; /* 0x3c */ + u32 sr; /* 0x40 */ + u32 ier; /* 0x44 */ + u32 idr; /* 0x48 */ + u32 imr; /* 0x4c */ + u32 dma; /* 0x50 */ + u32 cfg; /* 0x54 */ + u32 reserved[41]; + u32 version; +} atmel_mci_t; + +#endif /* __ASSEMBLY__ */ + +/* Bitfields in CR */ +#define MMCI_MCIEN_OFFSET 0 +#define MMCI_MCIEN_SIZE 1 +#define MMCI_MCIDIS_OFFSET 1 +#define MMCI_MCIDIS_SIZE 1 +#define MMCI_PWSEN_OFFSET 2 +#define MMCI_PWSEN_SIZE 1 +#define MMCI_PWSDIS_OFFSET 3 +#define MMCI_PWSDIS_SIZE 1 +#define MMCI_SWRST_OFFSET 7 +#define MMCI_SWRST_SIZE 1 + +/* Bitfields in MR */ +#define MMCI_CLKDIV_OFFSET 0 +#define MMCI_CLKDIV_SIZE 8 +#define MMCI_PWSDIV_OFFSET 8 +#define MMCI_PWSDIV_SIZE 3 +#define MMCI_RDPROOF_OFFSET 11 +#define MMCI_RDPROOF_SIZE 1 +#define MMCI_WRPROOF_OFFSET 12 +#define MMCI_WRPROOF_SIZE 1 +#define MMCI_PDCPADV_OFFSET 14 +#define MMCI_PDCPADV_SIZE 1 +#define MMCI_PDCMODE_OFFSET 15 +#define MMCI_PDCMODE_SIZE 1 +/* MCI IP version >= 0x500, MR bit 16 used for CLKODD */ +#define MMCI_CLKODD_OFFSET 16 +#define MMCI_CLKODD_SIZE 1 +/* MCI IP version < 0x200, MR higher 16bits for BLKLEN */ +#define MMCI_BLKLEN_OFFSET 16 +#define MMCI_BLKLEN_SIZE 16 + +/* Bitfields in DTOR */ +#define MMCI_DTOCYC_OFFSET 0 +#define MMCI_DTOCYC_SIZE 4 +#define MMCI_DTOMUL_OFFSET 4 +#define MMCI_DTOMUL_SIZE 3 + +/* Bitfields in SDCR */ +#define MMCI_SCDSEL_OFFSET 0 +#define MMCI_SCDSEL_SIZE 4 +#define MMCI_SCDBUS_OFFSET 7 +#define MMCI_SCDBUS_SIZE 1 + +/* Bitfields in ARGR */ +#define MMCI_ARG_OFFSET 0 +#define MMCI_ARG_SIZE 32 + +/* Bitfields in CMDR */ +#define MMCI_CMDNB_OFFSET 0 +#define MMCI_CMDNB_SIZE 6 +#define MMCI_RSPTYP_OFFSET 6 +#define MMCI_RSPTYP_SIZE 2 +#define MMCI_SPCMD_OFFSET 8 +#define MMCI_SPCMD_SIZE 3 +#define MMCI_OPDCMD_OFFSET 11 +#define MMCI_OPDCMD_SIZE 1 +#define MMCI_MAXLAT_OFFSET 12 +#define MMCI_MAXLAT_SIZE 1 +#define MMCI_TRCMD_OFFSET 16 +#define MMCI_TRCMD_SIZE 2 +#define MMCI_TRDIR_OFFSET 18 +#define MMCI_TRDIR_SIZE 1 +#define MMCI_TRTYP_OFFSET 19 +#define MMCI_TRTYP_SIZE 2 + +/* Bitfields in BLKR */ +/* MMCI_BLKLEN_OFFSET/SIZE already defined in MR */ +#define MMCI_BCNT_OFFSET 0 +#define MMCI_BCNT_SIZE 16 + +/* Bitfields in RSPRx */ +#define MMCI_RSP_OFFSET 0 +#define MMCI_RSP_SIZE 32 + +/* Bitfields in SR/IER/IDR/IMR */ +#define MMCI_CMDRDY_OFFSET 0 +#define MMCI_CMDRDY_SIZE 1 +#define MMCI_RXRDY_OFFSET 1 +#define MMCI_RXRDY_SIZE 1 +#define MMCI_TXRDY_OFFSET 2 +#define MMCI_TXRDY_SIZE 1 +#define MMCI_BLKE_OFFSET 3 +#define MMCI_BLKE_SIZE 1 +#define MMCI_DTIP_OFFSET 4 +#define MMCI_DTIP_SIZE 1 +#define MMCI_NOTBUSY_OFFSET 5 +#define MMCI_NOTBUSY_SIZE 1 +#define MMCI_ENDRX_OFFSET 6 +#define MMCI_ENDRX_SIZE 1 +#define MMCI_ENDTX_OFFSET 7 +#define MMCI_ENDTX_SIZE 1 +#define MMCI_RXBUFF_OFFSET 14 +#define MMCI_RXBUFF_SIZE 1 +#define MMCI_TXBUFE_OFFSET 15 +#define MMCI_TXBUFE_SIZE 1 +#define MMCI_RINDE_OFFSET 16 +#define MMCI_RINDE_SIZE 1 +#define MMCI_RDIRE_OFFSET 17 +#define MMCI_RDIRE_SIZE 1 +#define MMCI_RCRCE_OFFSET 18 +#define MMCI_RCRCE_SIZE 1 +#define MMCI_RENDE_OFFSET 19 +#define MMCI_RENDE_SIZE 1 +#define MMCI_RTOE_OFFSET 20 +#define MMCI_RTOE_SIZE 1 +#define MMCI_DCRCE_OFFSET 21 +#define MMCI_DCRCE_SIZE 1 +#define MMCI_DTOE_OFFSET 22 +#define MMCI_DTOE_SIZE 1 +#define MMCI_OVRE_OFFSET 30 +#define MMCI_OVRE_SIZE 1 +#define MMCI_UNRE_OFFSET 31 +#define MMCI_UNRE_SIZE 1 + +/* Constants for DTOMUL */ +#define MMCI_DTOMUL_1_CYCLE 0 +#define MMCI_DTOMUL_16_CYCLES 1 +#define MMCI_DTOMUL_128_CYCLES 2 +#define MMCI_DTOMUL_256_CYCLES 3 +#define MMCI_DTOMUL_1024_CYCLES 4 +#define MMCI_DTOMUL_4096_CYCLES 5 +#define MMCI_DTOMUL_65536_CYCLES 6 +#define MMCI_DTOMUL_1048576_CYCLES 7 + +/* Constants for RSPTYP */ +#define MMCI_RSPTYP_NO_RESP 0 +#define MMCI_RSPTYP_48_BIT_RESP 1 +#define MMCI_RSPTYP_136_BIT_RESP 2 + +/* Constants for SPCMD */ +#define MMCI_SPCMD_NO_SPEC_CMD 0 +#define MMCI_SPCMD_INIT_CMD 1 +#define MMCI_SPCMD_SYNC_CMD 2 +#define MMCI_SPCMD_INT_CMD 4 +#define MMCI_SPCMD_INT_RESP 5 + +/* Constants for TRCMD */ +#define MMCI_TRCMD_NO_TRANS 0 +#define MMCI_TRCMD_START_TRANS 1 +#define MMCI_TRCMD_STOP_TRANS 2 + +/* Constants for TRTYP */ +#define MMCI_TRTYP_BLOCK 0 +#define MMCI_TRTYP_MULTI_BLOCK 1 +#define MMCI_TRTYP_STREAM 2 + +/* Bitfields in CFG */ +#define MMCI_FIFOMODE_OFFSET 0 +#define MMCI_FIFOMODE_SIZE 1 +#define MMCI_FERRCTRL_OFFSET 4 +#define MMCI_FERRCTRL_SIZE 1 +#define MMCI_HSMODE_OFFSET 8 +#define MMCI_HSMODE_SIZE 1 +#define MMCI_LSYNC_OFFSET 12 +#define MMCI_LSYNC_SIZE 1 + +/* Bit manipulation macros */ +#define MMCI_BIT(name) \ + (1 << MMCI_##name##_OFFSET) +#define MMCI_BF(name,value) \ + (((value) & ((1 << MMCI_##name##_SIZE) - 1)) \ + << MMCI_##name##_OFFSET) +#define MMCI_BFEXT(name,value) \ + (((value) >> MMCI_##name##_OFFSET)\ + & ((1 << MMCI_##name##_SIZE) - 1)) +#define MMCI_BFINS(name,value,old) \ + (((old) & ~(((1 << MMCI_##name##_SIZE) - 1) \ + << MMCI_##name##_OFFSET)) \ + | MMCI_BF(name,value)) + +#endif /* __ATMEL_MCI_H__ */ diff --git a/roms/u-boot/include/atsha204a-i2c.h b/roms/u-boot/include/atsha204a-i2c.h new file mode 100644 index 000000000..344fd8ace --- /dev/null +++ b/roms/u-boot/include/atsha204a-i2c.h @@ -0,0 +1,69 @@ +/* + * I2C Driver for Atmel ATSHA204 over I2C + * + * Copyright (C) 2014 Josh Datko, Cryptotronix, jbd@cryptotronix.com + * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com + * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _ATSHA204_I2C_H_ +#define _ATSHA204_I2C_H_ + +enum atsha204a_zone +{ + ATSHA204A_ZONE_CONFIG = 0, + ATSHA204A_ZONE_OTP = 1, + ATSHA204A_ZONE_DATA = 2, +}; + +enum atsha204a_status +{ + ATSHA204A_STATUS_SUCCESS = 0x00, + ATSHA204A_STATUS_MISCOMPARE = 0x01, + ATSHA204A_STATUS_PARSE_ERROR = 0x03, + ATSHA204A_STATUS_EXEC_ERROR = 0x0F, + ATSHA204A_STATUS_AFTER_WAKE = 0x11, + ATSHA204A_STATUS_CRC_ERROR = 0xFF, +}; + +enum atsha204a_func +{ + ATSHA204A_FUNC_RESET = 0x00, + ATSHA204A_FUNC_SLEEP = 0x01, + ATSHA204A_FUNC_IDLE = 0x02, + ATSHA204A_FUNC_COMMAND = 0x03, +}; + +enum atsha204a_cmd +{ + ATSHA204A_CMD_READ = 0x02, + ATSHA204A_CMD_RANDOM = 0x1B, +}; + +struct atsha204a_resp +{ + u8 length; + u8 code; + u8 data[82]; +} __attribute__ ((packed)); + +struct atsha204a_req +{ + u8 function; + u8 length; + u8 command; + u8 param1; + u16 param2; + u8 data[78]; +} __attribute__ ((packed)); + +int atsha204a_wakeup(struct udevice *); +int atsha204a_idle(struct udevice *); +int atsha204a_sleep(struct udevice *); +int atsha204a_read(struct udevice *, enum atsha204a_zone, bool, u16, u8 *); +int atsha204a_get_random(struct udevice *, u8 *, size_t); + +#endif /* _ATSHA204_I2C_H_ */ diff --git a/roms/u-boot/include/audio_codec.h b/roms/u-boot/include/audio_codec.h new file mode 100644 index 000000000..2ea4ff096 --- /dev/null +++ b/roms/u-boot/include/audio_codec.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 Google LLC + * Written by Simon Glass + */ + +#ifndef __AUDIO_CODEC_H__ +#define __AUDIO_CODEC_H__ + +struct udevice; + +/* + * An audio codec turns digital data into sound with various parameters to + * control its operation. + */ + +/* Operations for sound */ +struct audio_codec_ops { + /** + * set_params() - Set audio codec parameters + * + * @dev: Sound device + * @inteface: Interface number to use on codec + * @rate: Sampling rate in Hz + * @mclk_freq: Codec clock frequency in Hz + * @bits_per_sample: Must be 16 or 24 + * @channels: Number of channels to use (1=mono, 2=stereo) + * @return 0 if OK, -ve on error + */ + int (*set_params)(struct udevice *dev, int interface, int rate, + int mclk_freq, int bits_per_sample, uint channels); +}; + +#define audio_codec_get_ops(dev) ((struct audio_codec_ops *)(dev)->driver->ops) + +/** + * audio_codec_set_params() - Set audio codec parameters + * + * @dev: Sound device + * @inteface: Interface number to use on codec + * @rate: Sampling rate in Hz + * @mclk_freq: Codec clock frequency in Hz + * @bits_per_sample: Must be 16 or 24 + * @channels: Number of channels to use (1=mono, 2=stereo) + * @return 0 if OK, -ve on error + */ +int audio_codec_set_params(struct udevice *dev, int interface, int rate, + int mclk_freq, int bits_per_sample, uint channels); + +#endif /* __AUDIO_CODEC_H__ */ diff --git a/roms/u-boot/include/autoboot.h b/roms/u-boot/include/autoboot.h new file mode 100644 index 000000000..ac8157e57 --- /dev/null +++ b/roms/u-boot/include/autoboot.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Add to readline cmdline-editing by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, + */ + +#ifndef __AUTOBOOT_H +#define __AUTOBOOT_H + +#ifdef CONFIG_AUTOBOOT +/** + * bootdelay_process() - process the bootd delay + * + * Process the boot delay, boot limit, then get the value of either + * bootcmd, failbootcmd or altbootcmd depending on the current state. + * Return this command so it can be executed. + * + * @return command to executed + */ +const char *bootdelay_process(void); + +/** + * autoboot_command() - run the autoboot command + * + * If enabled, run the autoboot command returned from bootdelay_process(). + * Also do the CONFIG_AUTOBOOT_MENUKEY processing if enabled. + * + * @cmd: Command to run + */ +void autoboot_command(const char *cmd); +#else +static inline const char *bootdelay_process(void) +{ + return NULL; +} + +static inline void autoboot_command(const char *s) +{ +} +#endif + +#endif diff --git a/roms/u-boot/include/avb_verify.h b/roms/u-boot/include/avb_verify.h new file mode 100644 index 000000000..1e787ba66 --- /dev/null +++ b/roms/u-boot/include/avb_verify.h @@ -0,0 +1,101 @@ + +/* + * (C) Copyright 2018, Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _AVB_VERIFY_H +#define _AVB_VERIFY_H + +#include <../lib/libavb/libavb.h> +#include +#include + +#define AVB_MAX_ARGS 1024 +#define VERITY_TABLE_OPT_RESTART "restart_on_corruption" +#define VERITY_TABLE_OPT_LOGGING "ignore_corruption" +#define ALLOWED_BUF_ALIGN 8 + +enum avb_boot_state { + AVB_GREEN, + AVB_YELLOW, + AVB_ORANGE, + AVB_RED, +}; + +struct AvbOpsData { + struct AvbOps ops; + int mmc_dev; + enum avb_boot_state boot_state; +#ifdef CONFIG_OPTEE_TA_AVB + struct udevice *tee; + u32 session; +#endif +}; + +struct mmc_part { + int dev_num; + struct mmc *mmc; + struct blk_desc *mmc_blk; + struct disk_partition info; +}; + +enum mmc_io_type { + IO_READ, + IO_WRITE +}; + +AvbOps *avb_ops_alloc(int boot_device); +void avb_ops_free(AvbOps *ops); + +char *avb_set_state(AvbOps *ops, enum avb_boot_state boot_state); +char *avb_set_enforce_verity(const char *cmdline); +char *avb_set_ignore_corruption(const char *cmdline); + +char *append_cmd_line(char *cmdline_orig, char *cmdline_new); + +/** + * ============================================================================ + * I/O helper inline functions + * ============================================================================ + */ +static inline uint64_t calc_offset(struct mmc_part *part, int64_t offset) +{ + u64 part_size = part->info.size * part->info.blksz; + + if (offset < 0) + return part_size + offset; + + return offset; +} + +static inline size_t get_sector_buf_size(void) +{ + return (size_t)CONFIG_AVB_BUF_SIZE; +} + +static inline void *get_sector_buf(void) +{ + return map_sysmem(CONFIG_AVB_BUF_ADDR, CONFIG_AVB_BUF_SIZE); +} + +static inline bool is_buf_unaligned(void *buffer) +{ + return (bool)((uintptr_t)buffer % ALLOWED_BUF_ALIGN); +} + +static inline int get_boot_device(AvbOps *ops) +{ + struct AvbOpsData *data; + + if (ops) { + data = ops->user_data; + if (data) + return data->mmc_dev; + } + + return -1; +} + +#endif /* _AVB_VERIFY_H */ diff --git a/roms/u-boot/include/axi.h b/roms/u-boot/include/axi.h new file mode 100644 index 000000000..59fb0b2e4 --- /dev/null +++ b/roms/u-boot/include/axi.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017, 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#ifndef _AXI_H_ +#define _AXI_H_ + +struct udevice; + +/** + * enum axi_size_t - Determine size of AXI transfer + * @AXI_SIZE_8: AXI sransfer is 8-bit wide + * @AXI_SIZE_16: AXI sransfer is 16-bit wide + * @AXI_SIZE_32: AXI sransfer is 32-bit wide + */ +enum axi_size_t { + AXI_SIZE_8, + AXI_SIZE_16, + AXI_SIZE_32, +}; + +struct axi_ops { + /** + * read() - Read a single value from a specified address on a AXI bus + * @dev: AXI bus to read from. + * @address: The address to read from. + * @data: Pointer to a variable that takes the data value read + * from the address on the AXI bus. + * @size: The size of the data to be read. + * + * Return: 0 if OK, -ve on error. + */ + int (*read)(struct udevice *dev, ulong address, void *data, + enum axi_size_t size); + + /** + * write() - Write a single value to a specified address on a AXI bus + * @dev: AXI bus to write to. + * @address: The address to write to. + * @data: Pointer to the data value to be written to the address + * on the AXI bus. + * @size: The size of the data to write. + * + * Return 0 if OK, -ve on error. + */ + int (*write)(struct udevice *dev, ulong address, void *data, + enum axi_size_t size); +}; + +#define axi_get_ops(dev) ((struct axi_ops *)(dev)->driver->ops) + +/** + * axi_read() - Read a single value from a specified address on a AXI bus + * @dev: AXI bus to read from. + * @address: The address to read from. + * @data: Pointer to a variable that takes the data value read from the + * address on the AXI bus. + * @size: The size of the data to write. + * + * Return: 0 if OK, -ve on error. + */ +int axi_read(struct udevice *dev, ulong address, void *data, + enum axi_size_t size); + +/** + * axi_write() - Write a single value to a specified address on a AXI bus + * @dev: AXI bus to write to. + * @address: The address to write to. + * @data: Pointer to the data value to be written to the address on the + * AXI bus. + * @size: The size of the data to write. + * + * Return: 0 if OK, -ve on error. + */ +int axi_write(struct udevice *dev, ulong address, void *data, + enum axi_size_t size); + +struct axi_emul_ops { + /** + * read() - Read a single value from a specified address on a AXI bus + * @dev: AXI bus to read from. + * @address: The address to read from. + * @data: Pointer to a variable that takes the data value read + * from the address on the AXI bus. + * @size: The size of the data to be read. + * + * Return: 0 if OK, -ve on error. + */ + int (*read)(struct udevice *dev, ulong address, void *data, + enum axi_size_t size); + + /** + * write() - Write a single value to a specified address on a AXI bus + * @dev: AXI bus to write to. + * @address: The address to write to. + * @data: Pointer to the data value to be written to the address + * on the AXI bus. + * @size: The size of the data to write. + * + * Return: 0 if OK, -ve on error. + */ + int (*write)(struct udevice *dev, ulong address, void *data, + enum axi_size_t size); + + /** + * get_store() - Get address of internal storage of a emulated AXI + * device + * @dev: Emulated AXI device to get the pointer of the internal + * storage for. + * @storep: Pointer to the internal storage of the emulated AXI + * device. + * + * Return: 0 if OK, -ve on error. + */ + int (*get_store)(struct udevice *dev, u8 **storep); +}; + +#endif diff --git a/roms/u-boot/include/axp152.h b/roms/u-boot/include/axp152.h new file mode 100644 index 000000000..c81f17250 --- /dev/null +++ b/roms/u-boot/include/axp152.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 Henrik Nordstrom + */ + +enum axp152_reg { + AXP152_CHIP_VERSION = 0x3, + AXP152_DCDC2_VOLTAGE = 0x23, + AXP152_DCDC3_VOLTAGE = 0x27, + AXP152_DCDC4_VOLTAGE = 0x2B, + AXP152_LDO2_VOLTAGE = 0x2A, + AXP152_SHUTDOWN = 0x32, +}; + +#define AXP152_POWEROFF (1 << 7) + +/* For axp_gpio.c */ +#define AXP_GPIO0_CTRL 0x90 +#define AXP_GPIO1_CTRL 0x91 +#define AXP_GPIO2_CTRL 0x92 +#define AXP_GPIO3_CTRL 0x93 +#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ +#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ +#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ +#define AXP_GPIO_STATE 0x97 +#define AXP_GPIO_STATE_OFFSET 0 diff --git a/roms/u-boot/include/axp209.h b/roms/u-boot/include/axp209.h new file mode 100644 index 000000000..f4f1b2fe5 --- /dev/null +++ b/roms/u-boot/include/axp209.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 Henrik Nordstrom + */ + +#include + +enum axp209_reg { + AXP209_POWER_STATUS = 0x00, + AXP209_CHIP_VERSION = 0x03, + AXP209_OUTPUT_CTRL = 0x12, + AXP209_DCDC2_VOLTAGE = 0x23, + AXP209_VRC_DCDC2_LDO3 = 0x25, + AXP209_DCDC3_VOLTAGE = 0x27, + AXP209_LDO24_VOLTAGE = 0x28, + AXP209_LDO3_VOLTAGE = 0x29, + AXP209_IRQ_ENABLE1 = 0x40, + AXP209_IRQ_ENABLE2 = 0x41, + AXP209_IRQ_ENABLE3 = 0x42, + AXP209_IRQ_ENABLE4 = 0x43, + AXP209_IRQ_ENABLE5 = 0x44, + AXP209_IRQ_STATUS5 = 0x4c, + AXP209_SHUTDOWN = 0x32, +}; + +#define AXP209_POWER_STATUS_ON_BY_DC BIT(0) +#define AXP209_POWER_STATUS_VBUS_USABLE BIT(4) + +#define AXP209_CHIP_VERSION_MASK 0x0f + +#define AXP209_OUTPUT_CTRL_EXTEN BIT(0) +#define AXP209_OUTPUT_CTRL_DCDC3 BIT(1) +#define AXP209_OUTPUT_CTRL_LDO2 BIT(2) +#define AXP209_OUTPUT_CTRL_LDO4 BIT(3) +#define AXP209_OUTPUT_CTRL_DCDC2 BIT(4) +#define AXP209_OUTPUT_CTRL_LDO3 BIT(6) + +/* + * AXP209 datasheet contains wrong information about LDO3 VRC: + * - VRC is actually enabled when BIT(1) is True + * - VRC is actually not enabled by default (BIT(3) = 0 after reset) + */ +#define AXP209_VRC_LDO3_EN BIT(3) +#define AXP209_VRC_DCDC2_EN BIT(2) +#define AXP209_VRC_LDO3_800uV_uS (BIT(1) | AXP209_VRC_LDO3_EN) +#define AXP209_VRC_LDO3_1600uV_uS AXP209_VRC_LDO3_EN +#define AXP209_VRC_DCDC2_800uV_uS (BIT(0) | AXP209_VRC_DCDC2_EN) +#define AXP209_VRC_DCDC2_1600uV_uS AXP209_VRC_DCDC2_EN +#define AXP209_VRC_LDO3_MASK 0xa +#define AXP209_VRC_DCDC2_MASK 0x5 +#define AXP209_VRC_DCDC2_SLOPE_SET(reg, cfg) \ + (((reg) & ~AXP209_VRC_DCDC2_MASK) | \ + ((cfg) & AXP209_VRC_DCDC2_MASK)) +#define AXP209_VRC_LDO3_SLOPE_SET(reg, cfg) \ + (((reg) & ~AXP209_VRC_LDO3_MASK) | \ + ((cfg) & AXP209_VRC_LDO3_MASK)) + +#define AXP209_LDO24_LDO2_MASK 0xf0 +#define AXP209_LDO24_LDO4_MASK 0x0f +#define AXP209_LDO24_LDO2_SET(reg, cfg) \ + (((reg) & ~AXP209_LDO24_LDO2_MASK) | \ + (((cfg) << 4) & AXP209_LDO24_LDO2_MASK)) +#define AXP209_LDO24_LDO4_SET(reg, cfg) \ + (((reg) & ~AXP209_LDO24_LDO4_MASK) | \ + (((cfg) << 0) & AXP209_LDO24_LDO4_MASK)) + +#define AXP209_LDO3_VOLTAGE_FROM_LDO3IN BIT(7) +#define AXP209_LDO3_VOLTAGE_MASK 0x7f +#define AXP209_LDO3_VOLTAGE_SET(x) ((x) & AXP209_LDO3_VOLTAGE_MASK) + +#define AXP209_IRQ5_PEK_UP BIT(6) +#define AXP209_IRQ5_PEK_DOWN BIT(5) + +#define AXP209_POWEROFF BIT(7) + +/* For axp_gpio.c */ +#define AXP_POWER_STATUS 0x00 +#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5) +#define AXP_GPIO0_CTRL 0x90 +#define AXP_GPIO1_CTRL 0x92 +#define AXP_GPIO2_CTRL 0x93 +#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ +#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ +#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ +#define AXP_GPIO_STATE 0x94 +#define AXP_GPIO_STATE_OFFSET 4 diff --git a/roms/u-boot/include/axp221.h b/roms/u-boot/include/axp221.h new file mode 100644 index 000000000..caffb910f --- /dev/null +++ b/roms/u-boot/include/axp221.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 Oliver Schinagl + * + * X-Powers AXP221 Power Management IC driver + */ + +/* Page 0 addresses */ +#define AXP221_CHIP_ID 0x03 +#define AXP221_OUTPUT_CTRL1 0x10 +#define AXP221_OUTPUT_CTRL1_DCDC0_EN (1 << 0) +#define AXP221_OUTPUT_CTRL1_DCDC1_EN (1 << 1) +#define AXP221_OUTPUT_CTRL1_DCDC2_EN (1 << 2) +#define AXP221_OUTPUT_CTRL1_DCDC3_EN (1 << 3) +#define AXP221_OUTPUT_CTRL1_DCDC4_EN (1 << 4) +#define AXP221_OUTPUT_CTRL1_DCDC5_EN (1 << 5) +#define AXP221_OUTPUT_CTRL1_ALDO1_EN (1 << 6) +#define AXP221_OUTPUT_CTRL1_ALDO2_EN (1 << 7) +#define AXP221_OUTPUT_CTRL2 0x12 +#define AXP221_OUTPUT_CTRL2_ELDO1_EN (1 << 0) +#define AXP221_OUTPUT_CTRL2_ELDO2_EN (1 << 1) +#define AXP221_OUTPUT_CTRL2_ELDO3_EN (1 << 2) +#define AXP221_OUTPUT_CTRL2_DLDO1_EN (1 << 3) +#define AXP221_OUTPUT_CTRL2_DLDO2_EN (1 << 4) +#define AXP221_OUTPUT_CTRL2_DLDO3_EN (1 << 5) +#define AXP221_OUTPUT_CTRL2_DLDO4_EN (1 << 6) +#define AXP221_OUTPUT_CTRL2_DCDC1SW_EN (1 << 7) +#define AXP221_OUTPUT_CTRL3 0x13 +#define AXP221_OUTPUT_CTRL3_ALDO3_EN (1 << 7) +#define AXP221_DLDO1_CTRL 0x15 +#define AXP221_DLDO2_CTRL 0x16 +#define AXP221_DLDO3_CTRL 0x17 +#define AXP221_DLDO4_CTRL 0x18 +#define AXP221_ELDO1_CTRL 0x19 +#define AXP221_ELDO2_CTRL 0x1a +#define AXP221_ELDO3_CTRL 0x1b +#define AXP221_DCDC1_CTRL 0x21 +#define AXP221_DCDC2_CTRL 0x22 +#define AXP221_DCDC3_CTRL 0x23 +#define AXP221_DCDC4_CTRL 0x24 +#define AXP221_DCDC5_CTRL 0x25 +#define AXP221_ALDO1_CTRL 0x28 +#define AXP221_ALDO2_CTRL 0x29 +#define AXP221_ALDO3_CTRL 0x2a +#define AXP221_SHUTDOWN 0x32 +#define AXP221_SHUTDOWN_POWEROFF (1 << 7) +#define AXP221_PAGE 0xff + +/* Page 1 addresses */ +#define AXP221_SID 0x20 + +/* For axp_gpio.c */ +#define AXP_POWER_STATUS 0x00 +#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +#define AXP_VBUS_IPSOUT 0x30 +#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) +#define AXP_MISC_CTRL 0x8f +#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) +#define AXP_GPIO0_CTRL 0x90 +#define AXP_GPIO1_CTRL 0x92 +#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ +#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ +#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ +#define AXP_GPIO_STATE 0x94 +#define AXP_GPIO_STATE_OFFSET 0 diff --git a/roms/u-boot/include/axp305.h b/roms/u-boot/include/axp305.h new file mode 100644 index 000000000..225c5040a --- /dev/null +++ b/roms/u-boot/include/axp305.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2020 Jernej Skrabec + */ + +enum axp305_reg { + AXP305_CHIP_VERSION = 0x3, + AXP305_OUTPUT_CTRL1 = 0x10, + AXP305_DCDCD_VOLTAGE = 0x15, + AXP305_SHUTDOWN = 0x32, +}; + +#define AXP305_CHIP_VERSION_MASK 0xcf + +#define AXP305_OUTPUT_CTRL1_DCDCD_EN (1 << 3) + +#define AXP305_POWEROFF (1 << 7) diff --git a/roms/u-boot/include/axp809.h b/roms/u-boot/include/axp809.h new file mode 100644 index 000000000..86b292533 --- /dev/null +++ b/roms/u-boot/include/axp809.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Chen-Yu Tsai + * + * X-Powers AXP809 Power Management IC driver + */ + +#define AXP809_CHIP_ID 0x03 + +#define AXP809_OUTPUT_CTRL1 0x10 +#define AXP809_OUTPUT_CTRL1_DC5LDO_EN (1 << 0) +#define AXP809_OUTPUT_CTRL1_DCDC1_EN (1 << 1) +#define AXP809_OUTPUT_CTRL1_DCDC2_EN (1 << 2) +#define AXP809_OUTPUT_CTRL1_DCDC3_EN (1 << 3) +#define AXP809_OUTPUT_CTRL1_DCDC4_EN (1 << 4) +#define AXP809_OUTPUT_CTRL1_DCDC5_EN (1 << 5) +#define AXP809_OUTPUT_CTRL1_ALDO1_EN (1 << 6) +#define AXP809_OUTPUT_CTRL1_ALDO2_EN (1 << 7) +#define AXP809_OUTPUT_CTRL2 0x12 +#define AXP809_OUTPUT_CTRL2_ELDO1_EN (1 << 0) +#define AXP809_OUTPUT_CTRL2_ELDO2_EN (1 << 1) +#define AXP809_OUTPUT_CTRL2_ELDO3_EN (1 << 2) +#define AXP809_OUTPUT_CTRL2_DLDO1_EN (1 << 3) +#define AXP809_OUTPUT_CTRL2_DLDO2_EN (1 << 4) +#define AXP809_OUTPUT_CTRL2_ALDO3_EN (1 << 5) +#define AXP809_OUTPUT_CTRL2_SWOUT_EN (1 << 6) +#define AXP809_OUTPUT_CTRL2_DC1SW_EN (1 << 7) + +#define AXP809_DLDO1_CTRL 0x15 +#define AXP809_DLDO2_CTRL 0x16 +#define AXP809_ELDO1_CTRL 0x19 +#define AXP809_ELDO2_CTRL 0x1a +#define AXP809_ELDO3_CTRL 0x1b +#define AXP809_DC5LDO_CTRL 0x1c +#define AXP809_DCDC1_CTRL 0x21 +#define AXP809_DCDC2_CTRL 0x22 +#define AXP809_DCDC3_CTRL 0x23 +#define AXP809_DCDC4_CTRL 0x24 +#define AXP809_DCDC5_CTRL 0x25 +#define AXP809_ALDO1_CTRL 0x28 +#define AXP809_ALDO2_CTRL 0x29 +#define AXP809_ALDO3_CTRL 0x2a +#define AXP809_SHUTDOWN 0x32 +#define AXP809_SHUTDOWN_POWEROFF (1 << 7) + +/* For axp_gpio.c */ +#define AXP_POWER_STATUS 0x00 +#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +#define AXP_VBUS_IPSOUT 0x30 +#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) +#define AXP_MISC_CTRL 0x8f +#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) +#define AXP_GPIO0_CTRL 0x90 +#define AXP_GPIO1_CTRL 0x92 +#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ +#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ +#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ +#define AXP_GPIO_STATE 0x94 +#define AXP_GPIO_STATE_OFFSET 0 diff --git a/roms/u-boot/include/axp818.h b/roms/u-boot/include/axp818.h new file mode 100644 index 000000000..b16fe0b15 --- /dev/null +++ b/roms/u-boot/include/axp818.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Vishnu Patekar + * + * X-Powers AXP818 Power Management IC driver + */ + +#define AXP818_CHIP_ID 0x03 + +#define AXP818_OUTPUT_CTRL1 0x10 +#define AXP818_OUTPUT_CTRL1_DCDC1_EN (1 << 0) +#define AXP818_OUTPUT_CTRL1_DCDC2_EN (1 << 1) +#define AXP818_OUTPUT_CTRL1_DCDC3_EN (1 << 2) +#define AXP818_OUTPUT_CTRL1_DCDC4_EN (1 << 3) +#define AXP818_OUTPUT_CTRL1_DCDC5_EN (1 << 4) +#define AXP818_OUTPUT_CTRL1_DCDC6_EN (1 << 5) +#define AXP818_OUTPUT_CTRL1_DCDC7_EN (1 << 6) +#define AXP818_OUTPUT_CTRL2 0x12 +#define AXP818_OUTPUT_CTRL2_ELDO1_EN (1 << 0) +#define AXP818_OUTPUT_CTRL2_ELDO2_EN (1 << 1) +#define AXP818_OUTPUT_CTRL2_ELDO3_EN (1 << 2) +#define AXP818_OUTPUT_CTRL2_DLDO1_EN (1 << 3) +#define AXP818_OUTPUT_CTRL2_DLDO2_EN (1 << 4) +#define AXP818_OUTPUT_CTRL2_DLDO3_EN (1 << 5) +#define AXP818_OUTPUT_CTRL2_DLDO4_EN (1 << 6) +#define AXP818_OUTPUT_CTRL2_SW_EN (1 << 7) +#define AXP818_OUTPUT_CTRL3 0x13 +#define AXP818_OUTPUT_CTRL3_FLDO1_EN (1 << 2) +#define AXP818_OUTPUT_CTRL3_FLDO2_EN (1 << 3) +#define AXP818_OUTPUT_CTRL3_FLDO3_EN (1 << 4) +#define AXP818_OUTPUT_CTRL3_ALDO1_EN (1 << 5) +#define AXP818_OUTPUT_CTRL3_ALDO2_EN (1 << 6) +#define AXP818_OUTPUT_CTRL3_ALDO3_EN (1 << 7) + +#define AXP818_DLDO1_CTRL 0x15 +#define AXP818_DLDO2_CTRL 0x16 +#define AXP818_DLDO3_CTRL 0x17 +#define AXP818_DLDO4_CTRL 0x18 +#define AXP818_ELDO1_CTRL 0x19 +#define AXP818_ELDO2_CTRL 0x1a +#define AXP818_ELDO3_CTRL 0x1b +#define AXP818_FLDO1_CTRL 0x1c +#define AXP818_FLDO2_3_CTRL 0x1d +#define AXP818_FLDO2_3_CTRL_FLDO3_VOL (1 << 4) +#define AXP818_DCDC1_CTRL 0x20 +#define AXP818_DCDC2_CTRL 0x21 +#define AXP818_DCDC3_CTRL 0x22 +#define AXP818_DCDC4_CTRL 0x23 +#define AXP818_DCDC5_CTRL 0x24 +#define AXP818_DCDC6_CTRL 0x25 +#define AXP818_DCDC7_CTRL 0x26 + +#define AXP818_ALDO1_CTRL 0x28 +#define AXP818_ALDO2_CTRL 0x29 +#define AXP818_ALDO3_CTRL 0x2a + +#define AXP818_SHUTDOWN 0x32 +#define AXP818_SHUTDOWN_POWEROFF (1 << 7) + +/* For axp_gpio.c */ +#define AXP_POWER_STATUS 0x00 +#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +#define AXP_VBUS_IPSOUT 0x30 +#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) +#define AXP_MISC_CTRL 0x8f +#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) +#define AXP_GPIO0_CTRL 0x90 +#define AXP_GPIO1_CTRL 0x92 +#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ +#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ +#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ +#define AXP_GPIO_STATE 0x94 +#define AXP_GPIO_STATE_OFFSET 0 diff --git a/roms/u-boot/include/axp_pmic.h b/roms/u-boot/include/axp_pmic.h new file mode 100644 index 000000000..405044c3a --- /dev/null +++ b/roms/u-boot/include/axp_pmic.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Hans de Goede + * + * X-Powers AX Power Management IC support header + */ +#ifndef _AXP_PMIC_H_ + +#ifdef CONFIG_AXP152_POWER +#include +#endif +#ifdef CONFIG_AXP209_POWER +#include +#endif +#ifdef CONFIG_AXP221_POWER +#include +#endif +#ifdef CONFIG_AXP305_POWER +#include +#endif +#ifdef CONFIG_AXP809_POWER +#include +#endif +#ifdef CONFIG_AXP818_POWER +#include +#endif + +int axp_set_dcdc1(unsigned int mvolt); +int axp_set_dcdc2(unsigned int mvolt); +int axp_set_dcdc3(unsigned int mvolt); +int axp_set_dcdc4(unsigned int mvolt); +int axp_set_dcdc5(unsigned int mvolt); +int axp_set_aldo1(unsigned int mvolt); +int axp_set_aldo2(unsigned int mvolt); +int axp_set_aldo3(unsigned int mvolt); +int axp_set_aldo4(unsigned int mvolt); +int axp_set_dldo(int dldo_num, unsigned int mvolt); +int axp_set_eldo(int eldo_num, unsigned int mvolt); +int axp_set_fldo(int fldo_num, unsigned int mvolt); +int axp_set_sw(bool on); +int axp_init(void); +int axp_get_sid(unsigned int *sid); + +#endif diff --git a/roms/u-boot/include/backlight.h b/roms/u-boot/include/backlight.h new file mode 100644 index 000000000..b44da50bc --- /dev/null +++ b/roms/u-boot/include/backlight.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2016 Google, Inc + * Written by Simon Glass + */ + +#ifndef _BACKLIGHT_H +#define _BACKLIGHT_H + +struct udevice; + +enum { + BACKLIGHT_MAX = 100, + BACKLIGHT_MIN = 0, + BACKLIGHT_OFF = -1, + BACKLIGHT_DEFAULT = -2, +}; + +struct backlight_ops { + /** + * enable() - Enable a backlight + * + * @dev: Backlight device to enable + * @return 0 if OK, -ve on error + */ + int (*enable)(struct udevice *dev); + + /** + * set_brightness - Set brightness + * + * @dev: Backlight device to update + * @percent: Brightness value (0 to 100, or BACKLIGHT_... value) + * @return 0 if OK, -ve on error + */ + int (*set_brightness)(struct udevice *dev, int percent); +}; + +#define backlight_get_ops(dev) ((struct backlight_ops *)(dev)->driver->ops) + +/** + * backlight_enable() - Enable a backlight + * + * @dev: Backlight device to enable + * @return 0 if OK, -ve on error + */ +int backlight_enable(struct udevice *dev); + +/** + * backlight_set_brightness - Set brightness + * + * @dev: Backlight device to update + * @percent: Brightness value (0 to 100, or BACKLIGHT_... value) + * @return 0 if OK, -ve on error + */ +int backlight_set_brightness(struct udevice *dev, int percent); + +#endif diff --git a/roms/u-boot/include/bcb.h b/roms/u-boot/include/bcb.h new file mode 100644 index 000000000..897e83d37 --- /dev/null +++ b/roms/u-boot/include/bcb.h @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Eugeniu Rosca + * + * Android Bootloader Control Block Header + */ + +#ifndef __BCB_H__ +#define __BCB_H__ + +#if CONFIG_IS_ENABLED(CMD_BCB) +int bcb_write_reboot_reason(int devnum, char *partp, const char *reasonp); +#else +#include +static inline int bcb_write_reboot_reason(int devnum, char *partp, const char *reasonp) +{ + return -EOPNOTSUPP; +} +#endif + +#endif /* __BCB_H__ */ diff --git a/roms/u-boot/include/bcd.h b/roms/u-boot/include/bcd.h new file mode 100644 index 000000000..9ecd32828 --- /dev/null +++ b/roms/u-boot/include/bcd.h @@ -0,0 +1,23 @@ +/* Permission is hereby granted to copy, modify and redistribute this code + * in terms of the GNU Library General Public License, Version 2 or later, + * at your option. + */ + +/* inline functions to translate to/from binary and binary-coded decimal + * (frequently found in RTC chips). + */ + +#ifndef _BCD_H +#define _BCD_H + +static inline unsigned int bcd2bin(unsigned int val) +{ + return ((val) & 0x0f) + ((val & 0xff) >> 4) * 10; +} + +static inline unsigned int bin2bcd(unsigned int val) +{ + return (((val / 10) << 4) | (val % 10)); +} + +#endif /* _BCD_H */ diff --git a/roms/u-boot/include/bedbug/bedbug.h b/roms/u-boot/include/bedbug/bedbug.h new file mode 100644 index 000000000..0c5d687f8 --- /dev/null +++ b/roms/u-boot/include/bedbug/bedbug.h @@ -0,0 +1,40 @@ +/* $Id$ */ + +#ifndef _BEDBUG_H +#define _BEDBUG_H + +#ifndef NULL +#define NULL 0 +#endif + +#define _USE_PROTOTYPES + +#ifndef isblank +#define isblank(c) isspace((int)(c)) +#endif + +#ifndef __P +#if defined(_USE_PROTOTYPES) && (defined(__STDC__) || defined(__cplusplus)) +#define __P(protos) protos /* full-blown ANSI C */ +#else +#define __P(protos) () /* traditional C preprocessor */ +#endif +#endif + +#endif /* _BEDBUG_H */ + + +/* + * Copyright (c) 2001 William L. Pitts + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ diff --git a/roms/u-boot/include/bedbug/ppc.h b/roms/u-boot/include/bedbug/ppc.h new file mode 100644 index 000000000..76d86fdbf --- /dev/null +++ b/roms/u-boot/include/bedbug/ppc.h @@ -0,0 +1,408 @@ +/* $Id$ */ + +#ifndef _PPC_H +#define _PPC_H + +/*====================================================================== + * + * OPERANDS + * + *======================================================================*/ + +enum OP_FIELD { + O_AA = 1, O_BD, O_BI, O_BO, O_crbD, O_crbA, O_crbB, O_CRM, O_d, O_frC, O_frD, + O_frS, O_IMM, O_LI, O_LK, O_MB, O_ME, O_NB, O_OE, O_rA, O_rB, O_Rc, O_rD, + O_rS, O_SH, O_SIMM, O_SR, O_TO, O_UIMM, O_crfD, O_crfS, O_L, O_spr, O_tbr, + O_cr2 }; + +struct operand { + enum OP_FIELD field; /* The operand identifier from the + enum above */ + + char * name; /* Symbolic name of this operand */ + + unsigned int bits; /* The number of bits used by this + operand */ + + unsigned int shift; /* How far to the right the operand + should be shifted so that it is + aligned at the beginning of the + word */ + + unsigned int hint; /* A bitwise-inclusive-OR of the + values shown below. These are used + tell the disassembler how to print + this operand */ +}; + +/* Values for operand hint */ +#define OH_SILENT 0x01 /* dont print this operand */ +#define OH_ADDR 0x02 /* this operand is an address */ +#define OH_REG 0x04 /* this operand is a register */ +#define OH_SPR 0x08 /* this operand is an SPR */ +#define OH_TBR 0x10 /* this operand is a TBR */ +#define OH_OFFSET 0x20 /* this operand is an offset */ +#define OH_LITERAL 0x40 /* a literal string */ + + +/*====================================================================== + * + * OPCODES + * + *======================================================================*/ + +/* From the MPCxxx instruction set documentation, all instructions are + * 32 bits long and word aligned. Bits 0-5 always specify the primary + * opcode. Many instructions also have an extended opcode. + */ + +#define GET_OPCD(i) (((unsigned long)(i) >> 26) & 0x3f) +#define MAKE_OPCODE(i) ((((unsigned long)(i)) & 0x3f) << 26) + +/* The MPC860 User's Manual, Appendix D.4 contains the definitions of the + * instruction forms + */ + + +/*------------------------------------------------- + * I-Form Instructions: + * bX + *------------------------------------------------- + * OPCD | LI |AA|LK + *-------------------------------------------------*/ + +#define I_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1)) +#define I_MASK I_OPCODE(0x3f,0x1,0x1) + + +/*------------------------------------------------- + * B-Form Instructions: + * bcX + *------------------------------------------------- + * OPCD | BO | BI | BD |AA|LK + *-------------------------------------------------*/ + +#define B_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1)) +#define B_MASK B_OPCODE(0x3f,0x1,0x1) + + +/*------------------------------------------------- + * SC-Form Instructions: + * sc + *------------------------------------------------- + * OPCD | 00000 | 00000 | 00000000000000 |1|0 + *-------------------------------------------------*/ + +#define SC_OPCODE(i) (MAKE_OPCODE(i) | 0x2) +#define SC_MASK SC_OPCODE(0x3f) + + +/*------------------------------------------------- + * D-Form Instructions: + * addi addic addic. addis andi. andis. cmpi cmpli + * lbz lbzu lha lhau lhz lhzu lmw lwz lwzu mulli + * ori oris stb stbu sth sthu stmw stw stwu subfic + * twi xori xoris + *------------------------------------------------- + * OPCD | D | A | d + * OPCD | D | A | SIMM + * OPCD | S | A | d + * OPCD | S | A | UIMM + * OPCD |crfD|0|L| A | SIMM + * OPCD |crfD|0|L| A | UIMM + * OPCD | TO | A | SIMM + *-------------------------------------------------*/ + +#define D_OPCODE(i) MAKE_OPCODE(i) +#define D_MASK MAKE_OPCODE(0x3f) + + +/*------------------------------------------------- + * DS-Form Instructions: + * (none supported by MPC860) + *------------------------------------------------- + * OPCD | D | A | ds |XO + * OPCD | S | A | ds |XO + *-------------------------------------------------*/ + +#define DS_OPCODE(i,xo) (MAKE_OPCODE(i) | ((xo) & 0x3)) +#define DS_MASK DS_OPCODE(0x3f,0x1) + + +/*--------------------------------------------------- + * X-Form Instructions: + * andX andcX cmp cmpl cntlzwX dcbf dcbi dcbst dcbt + * dcbtst dcbz eciwx ecowx eieio eqvX extsbX extshX + * icbi lbzux lbxz lhaux lhax lhbrx lhzux lhxz lswi + * lswx lwarx lwbrx lwzux lwxz mcrfs mcrxr mfcr + * mfmsr mfsr mfsrin mtmsr mtsr mtsrin nandX norX + * orX orcX slwX srawX srawiX srwX stbux stbx + * sthbrx sthuxsthx stswi stswx stwbrx stwcx. stwux + * stwx sync tlbie tlbld tlbli tlbsync tw xorX + *--------------------------------------------------- + * OPCD | D | A | B | XO |0 + * OPCD | D | A | NB | XO |0 + * OPCD | D | 00000 | B | XO |0 + * OPCD | D | 00000 | 00000 | XO |0 + * OPCD | D |0| SR | 00000 | XO |0 + * OPCD | S | A | B | XO |Rc + * OPCD | S | A | B | XO |1 + * OPCD | S | A | B | XO |0 + * OPCD | S | A | NB | XO |0 + * OPCD | S | A | 00000 | XO |Rc + * OPCD | S | 00000 | B | XO |0 + * OPCD | S | 00000 | 00000 | XO |0 + * OPCD | S |0| SR | 00000 | XO |0 + * OPCD | S | A | SH | XO |Rc + * OPCD |crfD|0|L| A | SH | XO |0 + * OPCD |crfD |00| A | B | XO |0 + * OPCD |crfD |00|crfS |00| 00000 | XO |0 + * OPCD |crfD |00| 00000 | 00000 | XO |0 + * OPCD |crfD |00| 00000 | IMM |0| XO |Rc + * OPCD | TO | A | B | XO |0 + * OPCD | D | 00000 | B | XO |Rc + * OPCD | D | 00000 | 00000 | XO |Rc + * OPCD | crbD | 00000 | 00000 | XO |Rc + * OPCD | 00000 | A | B | XO |0 + * OPCD | 00000 | 00000 | B | XO |0 + * OPCD | 00000 | 00000 | 00000 | XO |0 + *---------------------------------------------------*/ + +#define X_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \ + ((rc) & 0x1)) +#define X_MASK X_OPCODE(0x3f,0x3ff,0x1) + + +/*--------------------------------------------------- + * XL-Form Instructions: + * bcctrX bclrX crand crandc creqv crnand crnor cror + * croc crxorisync mcrf rfi + *--------------------------------------------------- + * OPCD | BO | BI | 00000 | XO |LK + * OPCD | crbD | crbA | crbB | XO |0 + * OPCD |crfD |00|crfS |00| 00000 | XO |0 + * OPCD | 00000 | 00000 | 00000 | XO |0 + *---------------------------------------------------*/ + +#define XL_OPCODE(i,xo,lk) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \ + ((lk) & 0x1)) +#define XL_MASK XL_OPCODE(0x3f,0x3ff,0x1) + + +/*--------------------------------------------------- + * XFX-Form Instructions: + * mfspr mftb mtcrf mtspr + *--------------------------------------------------- + * OPCD | D | spr | XO |0 + * OPCD | D |0| CRM |0| XO |0 + * OPCD | S | spr | XO |0 + * OPCD | D | tbr | XO |0 + *---------------------------------------------------*/ + +#define XFX_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \ + ((rc) & 0x1)) +#define XFX_MASK XFX_OPCODE(0x3f,0x3ff,0x1) + + +/*--------------------------------------------------- + * XFL-Form Instructions: + * (none supported by MPC860) + *--------------------------------------------------- + * OPCD |0| FM |0| B | XO |0 + *---------------------------------------------------*/ + +#define XFL_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \ + ((rc) & 0x1)) +#define XFL_MASK XFL_OPCODE(0x3f,0x3ff,0x1) + + +/*--------------------------------------------------- + * XS-Form Instructions: + * (none supported by MPC860) + *--------------------------------------------------- + * OPCD | S | A | sh | XO |sh|LK + *---------------------------------------------------*/ + +#define XS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1ff) << 2) | \ + ((rc) & 0x1)) +#define XS_MASK XS_OPCODE(0x3f,0x1ff,0x1) + + +/*--------------------------------------------------- + * XO-Form Instructions: + * addX addcXaddeX addmeX addzeX divwX divwuX mulhwX + * mulhwuX mullwX negX subfX subfcX subfeX subfmeX + * subfzeX + *--------------------------------------------------- + * OPCD | D | A | B |OE| XO |Rc + * OPCD | D | A | B |0 | XO |Rc + * OPCD | D | A | 00000 |OE| XO |Rc + *---------------------------------------------------*/ + +#define XO_OPCODE(i,xo,oe,rc) (MAKE_OPCODE(i) | (((oe) & 0x1) << 10) | \ + (((xo) & 0x1ff) << 1) | ((rc) & 0x1)) +#define XO_MASK XO_OPCODE(0x3f,0x1ff,0x1,0x1) + + +/*--------------------------------------------------- + * A-Form Instructions: + * (none supported by MPC860) + *--------------------------------------------------- + * OPCD | D | A | B |00000| XO |Rc + * OPCD | D | A | B | C | XO |Rc + * OPCD | D | A | 00000 | C | XO |Rc + * OPCD | D | 00000 | B |00000| XO |Rc + *---------------------------------------------------*/ + +#define A_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1f) << 1) | \ + ((rc) & 0x1)) +#define A_MASK A_OPCODE(0x3f,0x1f,0x1) + + +/*--------------------------------------------------- + * M-Form Instructions: + * rlwimiX rlwinmX rlwnmX + *--------------------------------------------------- + * OPCD | S | A | SH | MB | ME |Rc + * OPCD | S | A | B | MB | ME |Rc + *---------------------------------------------------*/ + +#define M_OPCODE(i,rc) (MAKE_OPCODE(i) | ((rc) & 0x1)) +#define M_MASK M_OPCODE(0x3f,0x1) + + +/*--------------------------------------------------- + * MD-Form Instructions: + * (none supported by MPC860) + *--------------------------------------------------- + * OPCD | S | A | sh | mb | XO |sh|Rc + * OPCD | S | A | sh | me | XO |sh|Rc + *---------------------------------------------------*/ + +#define MD_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x7) << 2) | \ + ((rc) & 0x1)) +#define MD_MASK MD_OPCODE(0x3f,0x7,0x1) + + +/*--------------------------------------------------- + * MDS-Form Instructions: + * (none supported by MPC860) + *--------------------------------------------------- + * OPCD | S | A | B | mb | XO |Rc + * OPCD | S | A | B | me | XO |Rc + *---------------------------------------------------*/ + +#define MDS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0xf) << 1) | \ + ((rc) & 0x1)) +#define MDS_MASK MDS_OPCODE(0x3f,0xf,0x1) + +#define INSTRUCTION( memaddr ) ntohl(*(unsigned long *)(memaddr)) + +#define MAX_OPERANDS 8 + +struct ppc_ctx; + +struct opcode { + unsigned long opcode; /* The complete opcode as produced by + one of the XXX_OPCODE macros above */ + + unsigned long mask; /* The mask to use on an instruction + before comparing with the opcode + field to see if it matches */ + + enum OP_FIELD fields[MAX_OPERANDS]; + /* An array defining the operands for + this opcode. The values of the + array are the operand identifiers */ + + int (*hfunc)(struct ppc_ctx *); + /* Address of a function to handle the given + mnemonic */ + + char * name; /* The symbolic name of this opcode */ + + unsigned int hint; /* A bitwise-inclusive-OR of the + values shown below. These are used + tell the disassembler how to print + some operands for this opcode */ +}; + +/* values for opcode hints */ +#define H_RELATIVE 0x1 /* The address operand is relative */ +#define H_IMM_HIGH 0x2 /* [U|S]IMM field shifted high */ +#define H_RA0_IS_0 0x4 /* If rA = 0 then treat as literal 0 */ + +struct ppc_ctx { + struct opcode * op; + unsigned long instr; + unsigned int flags; + int datalen; + char data[ 256 ]; + char radix_fmt[ 8 ]; + unsigned char * virtual; +}; + + +/*====================================================================== + * + * FUNCTIONS + * + *======================================================================*/ + +/* Values for flags as passed to various ppc routines */ +#define F_RADOCTAL 0x1 /* output radix = unsigned octal */ +#define F_RADUDECIMAL 0x2 /* output radix = unsigned decimal */ +#define F_RADSDECIMAL 0x4 /* output radix = signed decimal */ +#define F_RADHEX 0x8 /* output radix = unsigned hex */ +#define F_SIMPLE 0x10 /* use simplified mnemonics */ +#define F_SYMBOL 0x20 /* use symbol lookups for addresses */ +#define F_INSTR 0x40 /* output the raw instruction */ +#define F_LOCALMEM 0x80 /* retrieve opcodes from local memory + rather than from the HMI */ +#define F_LINENO 0x100 /* show line number info if available */ +#define F_VALIDONLY 0x200 /* cache: valid entries only */ + +/* Values for assembler error codes */ +#define E_ASM_BAD_OPCODE 1 +#define E_ASM_NUM_OPERANDS 2 +#define E_ASM_BAD_REGISTER 3 +#define E_ASM_BAD_SPR 4 +#define E_ASM_BAD_TBR 5 + +extern int disppc __P((unsigned char *,unsigned char *,int, + int (*)(const char *), unsigned long)); +extern int print_source_line __P((char *,char *,int, + int (*pfunc)(const char *))); +extern int find_next_address __P((unsigned char *,int,struct pt_regs *)); +extern int handle_bc __P((struct ppc_ctx *)); +extern unsigned long asmppc __P((unsigned long,char*,int*)); +extern char *asm_error_str __P((int)); + +/*====================================================================== + * + * GLOBAL VARIABLES + * + *======================================================================*/ + +extern struct operand operands[]; +extern const unsigned int n_operands; +extern struct opcode opcodes[]; +extern const unsigned int n_opcodes; + +#endif /* _PPC_H */ + + +/* + * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ diff --git a/roms/u-boot/include/bedbug/regs.h b/roms/u-boot/include/bedbug/regs.h new file mode 100644 index 000000000..304a336cc --- /dev/null +++ b/roms/u-boot/include/bedbug/regs.h @@ -0,0 +1,400 @@ +/* $Id$ */ + +#ifndef _REGS_H +#define _REGS_H + +/* Special Purpose Registers */ + +#define SPR_CR -1 +#define SPR_MSR -2 + +#define SPR_XER 1 +#define SPR_LR 8 +#define SPR_CTR 9 +#define SPR_DSISR 18 +#define SPR_DAR 19 +#define SPR_DEC 22 +#define SPR_SRR0 26 +#define SPR_SRR1 27 +#define SPR_EIE 80 +#define SPR_EID 81 +#define SPR_CMPA 144 +#define SPR_CMPB 145 +#define SPR_CMPC 146 +#define SPR_CMPD 147 +#define SPR_ICR 148 +#define SPR_DER 149 +#define SPR_COUNTA 150 +#define SPR_COUNTB 151 +#define SPR_CMPE 152 +#define SPR_CMPF 153 +#define SPR_CMPG 154 +#define SPR_CMPH 155 +#define SPR_LCTRL1 156 +#define SPR_LCTRL2 157 +#define SPR_ICTRL 158 +#define SPR_BAR 159 +#define SPR_USPRG0 256 +#define SPR_SPRG4_RO 260 +#define SPR_SPRG5_RO 261 +#define SPR_SPRG6_RO 262 +#define SPR_SPRG7_RO 263 +#define SPR_SPRG0 272 +#define SPR_SPRG1 273 +#define SPR_SPRG2 274 +#define SPR_SPRG3 275 +#define SPR_SPRG4 276 +#define SPR_SPRG5 277 +#define SPR_SPRG6 278 +#define SPR_SPRG7 279 +#define SPR_EAR 282 /* MPC603e core */ +#define SPR_TBL 284 +#define SPR_TBU 285 +#define SPR_PVR 287 +#define SPR_IC_CST 560 +#define SPR_IC_ADR 561 +#define SPR_IC_DAT 562 +#define SPR_DC_CST 568 +#define SPR_DC_ADR 569 +#define SPR_DC_DAT 570 +#define SPR_DPDR 630 +#define SPR_IMMR 638 +#define SPR_MI_CTR 784 +#define SPR_MI_AP 786 +#define SPR_MI_EPN 787 +#define SPR_MI_TWC 789 +#define SPR_MI_RPN 790 +#define SPR_MD_CTR 792 +#define SPR_M_CASID 793 +#define SPR_MD_AP 794 +#define SPR_MD_EPN 795 +#define SPR_M_TWB 796 +#define SPR_MD_TWC 797 +#define SPR_MD_RPN 798 +#define SPR_M_TW 799 +#define SPR_MI_DBCAM 816 +#define SPR_MI_DBRAM0 817 +#define SPR_MI_DBRAM1 818 +#define SPR_MD_DBCAM 824 +#define SPR_MD_DBRAM0 825 +#define SPR_MD_DBRAM1 826 +#define SPR_ZPR 944 +#define SPR_PID 945 +#define SPR_CCR0 947 +#define SPR_IAC3 948 +#define SPR_IAC4 949 +#define SPR_DVC1 950 +#define SPR_DVC2 951 +#define SPR_SGR 953 +#define SPR_DCWR 954 +#define SPR_SLER 955 +#define SPR_SU0R 956 +#define SPR_DBCR1 957 +#define SPR_ICDBDR 979 +#define SPR_ESR 980 +#define SPR_DEAR 981 +#define SPR_EVPR 982 +#define SPR_TSR 984 +#define SPR_TCR 986 +#define SPR_PIT 987 +#define SPR_SRR2 990 +#define SPR_SRR3 991 +#define SPR_DBSR 1008 +#define SPR_DBCR0 1010 +#define SPR_IABR 1010 /* MPC603e core */ +#define SPR_IAC1 1012 +#define SPR_IAC2 1013 +#define SPR_DAC1 1014 +#define SPR_DAC2 1015 +#define SPR_DCCR 1018 +#define SPR_ICCR 1019 + +/* Bits for the DBCR0 register */ +#define DBCR0_EDM 0x80000000 +#define DBCR0_IDM 0x40000000 +#define DBCR0_RST 0x30000000 +#define DBCR0_IC 0x08000000 +#define DBCR0_BT 0x04000000 +#define DBCR0_EDE 0x02000000 +#define DBCR0_TDE 0x01000000 +#define DBCR0_IA1 0x00800000 +#define DBCR0_IA2 0x00400000 +#define DBCR0_IA12 0x00200000 +#define DBCR0_IA12X 0x00100000 +#define DBCR0_IA3 0x00080000 +#define DBCR0_IA4 0x00040000 +#define DBCR0_IA34 0x00020000 +#define DBCR0_IA34X 0x00010000 +#define DBCR0_IA12T 0x00008000 +#define DBCR0_IA34T 0x00004000 +#define DBCR0_FT 0x00000001 + +/* Bits for the DBCR1 register */ +#define DBCR1_D1R 0x80000000 +#define DBCR1_D2R 0x40000000 +#define DBCR1_D1W 0x20000000 +#define DBCR1_D2W 0x10000000 +#define DBCR1_D1S 0x0C000000 +#define DBCR1_D2S 0x03000000 +#define DBCR1_DA12 0x00800000 +#define DBCR1_DA12X 0x00400000 +#define DBCR1_DV1M 0x000C0000 +#define DBCR1_DV2M 0x00030000 +#define DBCR1_DV1BE 0x0000F000 +#define DBCR1_DV2BE 0x00000F00 + +/* + * DBSR bits which have conflicting definitions on true Book E versus PPC40x + */ +#ifdef CONFIG_BOOKE +#define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ +#define DBSR_IA2 0x00400000 /* Instr Address Compare 2 Event */ +#define DBSR_IA3 0x00200000 /* Instr Address Compare 3 Event */ +#define DBSR_IA4 0x00100000 /* Instr Address Compare 4 Event */ +#endif +#define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ +#define DBSR_IA2 0x02000000 /* Instr Address Compare 2 Event */ +#define DBSR_IA3 0x00080000 /* Instr Address Compare 3 Event */ +#define DBSR_IA4 0x00040000 /* Instr Address Compare 4 Event */ + +struct spr_info { + int spr_val; + char spr_name[ 10 ]; +}; + +extern struct spr_info spr_map[]; +extern const unsigned int n_sprs; + + +#define SET_REGISTER( str, val ) \ +({ unsigned long __value = (val); \ + asm volatile( str : : "r" (__value)); \ + __value; }) + +#define GET_REGISTER( str ) \ +({ unsigned long __value; \ + asm volatile( str : "=r" (__value) : ); \ + __value; }) + +#define GET_CR() GET_REGISTER( "mfcr %0" ) +#define SET_CR(val) SET_REGISTER( "mtcr %0", val ) +#define GET_MSR() GET_REGISTER( "mfmsr %0" ) +#define SET_MSR(val) SET_REGISTER( "mtmsr %0", val ) +#define GET_XER() GET_REGISTER( "mfspr %0,1" ) +#define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val ) +#define GET_LR() GET_REGISTER( "mfspr %0,8" ) +#define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val ) +#define GET_CTR() GET_REGISTER( "mfspr %0,9" ) +#define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val ) +#define GET_DSISR() GET_REGISTER( "mfspr %0,18" ) +#define SET_DSISR(val) SET_REGISTER( "mtspr 18,%0", val ) +#define GET_DAR() GET_REGISTER( "mfspr %0,19" ) +#define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val ) +#define GET_DEC() GET_REGISTER( "mfspr %0,22" ) +#define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val ) +#define GET_SRR0() GET_REGISTER( "mfspr %0,26" ) +#define SET_SRR0(val) SET_REGISTER( "mtspr 26,%0", val ) +#define GET_SRR1() GET_REGISTER( "mfspr %0,27" ) +#define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val ) +#define GET_EIE() GET_REGISTER( "mfspr %0,80" ) +#define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val ) +#define GET_EID() GET_REGISTER( "mfspr %0,81" ) +#define SET_EID(val) SET_REGISTER( "mtspr 81,%0", val ) +#define GET_CMPA() GET_REGISTER( "mfspr %0,144" ) +#define SET_CMPA(val) SET_REGISTER( "mtspr 144,%0", val ) +#define GET_CMPB() GET_REGISTER( "mfspr %0,145" ) +#define SET_CMPB(val) SET_REGISTER( "mtspr 145,%0", val ) +#define GET_CMPC() GET_REGISTER( "mfspr %0,146" ) +#define SET_CMPC(val) SET_REGISTER( "mtspr 146,%0", val ) +#define GET_CMPD() GET_REGISTER( "mfspr %0,147" ) +#define SET_CMPD(val) SET_REGISTER( "mtspr 147,%0", val ) +#define GET_ICR() GET_REGISTER( "mfspr %0,148" ) +#define SET_ICR(val) SET_REGISTER( "mtspr 148,%0", val ) +#define GET_DER() GET_REGISTER( "mfspr %0,149" ) +#define SET_DER(val) SET_REGISTER( "mtspr 149,%0", val ) +#define GET_COUNTA() GET_REGISTER( "mfspr %0,150" ) +#define SET_COUNTA(val) SET_REGISTER( "mtspr 150,%0", val ) +#define GET_COUNTB() GET_REGISTER( "mfspr %0,151" ) +#define SET_COUNTB(val) SET_REGISTER( "mtspr 151,%0", val ) +#define GET_CMPE() GET_REGISTER( "mfspr %0,152" ) +#define SET_CMPE(val) SET_REGISTER( "mtspr 152,%0", val ) +#define GET_CMPF() GET_REGISTER( "mfspr %0,153" ) +#define SET_CMPF(val) SET_REGISTER( "mtspr 153,%0", val ) +#define GET_CMPG() GET_REGISTER( "mfspr %0,154" ) +#define SET_CMPG(val) SET_REGISTER( "mtspr 154,%0", val ) +#define GET_CMPH() GET_REGISTER( "mfspr %0,155" ) +#define SET_CMPH(val) SET_REGISTER( "mtspr 155,%0", val ) +#define GET_LCTRL1() GET_REGISTER( "mfspr %0,156" ) +#define SET_LCTRL1(val) SET_REGISTER( "mtspr 156,%0", val ) +#define GET_LCTRL2() GET_REGISTER( "mfspr %0,157" ) +#define SET_LCTRL2(val) SET_REGISTER( "mtspr 157,%0", val ) +#define GET_ICTRL() GET_REGISTER( "mfspr %0,158" ) +#define SET_ICTRL(val) SET_REGISTER( "mtspr 158,%0", val ) +#define GET_BAR() GET_REGISTER( "mfspr %0,159" ) +#define SET_BAR(val) SET_REGISTER( "mtspr 159,%0", val ) +#define GET_USPRG0() GET_REGISTER( "mfspr %0,256" ) +#define SET_USPRG0(val) SET_REGISTER( "mtspr 256,%0", val ) +#define GET_SPRG4_RO() GET_REGISTER( "mfspr %0,260" ) +#define SET_SPRG4_RO(val) SET_REGISTER( "mtspr 260,%0", val ) +#define GET_SPRG5_RO() GET_REGISTER( "mfspr %0,261" ) +#define SET_SPRG5_RO(val) SET_REGISTER( "mtspr 261,%0", val ) +#define GET_SPRG6_RO() GET_REGISTER( "mfspr %0,262" ) +#define SET_SPRG6_RO(val) SET_REGISTER( "mtspr 262,%0", val ) +#define GET_SPRG7_RO() GET_REGISTER( "mfspr %0,263" ) +#define SET_SPRG7_RO(val) SET_REGISTER( "mtspr 263,%0", val ) +#define GET_SPRG0() GET_REGISTER( "mfspr %0,272" ) +#define SET_SPRG0(val) SET_REGISTER( "mtspr 272,%0", val ) +#define GET_SPRG1() GET_REGISTER( "mfspr %0,273" ) +#define SET_SPRG1(val) SET_REGISTER( "mtspr 273,%0", val ) +#define GET_SPRG2() GET_REGISTER( "mfspr %0,274" ) +#define SET_SPRG2(val) SET_REGISTER( "mtspr 274,%0", val ) +#define GET_SPRG3() GET_REGISTER( "mfspr %0,275" ) +#define SET_SPRG3(val) SET_REGISTER( "mtspr 275,%0", val ) +#define GET_SPRG4() GET_REGISTER( "mfspr %0,276" ) +#define SET_SPRG4(val) SET_REGISTER( "mtspr 276,%0", val ) +#define GET_SPRG5() GET_REGISTER( "mfspr %0,277" ) +#define SET_SPRG5(val) SET_REGISTER( "mtspr 277,%0", val ) +#define GET_SPRG6() GET_REGISTER( "mfspr %0,278" ) +#define SET_SPRG6(val) SET_REGISTER( "mtspr 278,%0", val ) +#define GET_SPRG7() GET_REGISTER( "mfspr %0,279" ) +#define SET_SPRG7(val) SET_REGISTER( "mtspr 279,%0", val ) +#define GET_EAR() GET_REGISTER( "mfspr %0,282" ) +#define SET_EAR(val) SET_REGISTER( "mtspr 282,%0", val ) +#define GET_TBL() GET_REGISTER( "mfspr %0,284" ) +#define SET_TBL(val) SET_REGISTER( "mtspr 284,%0", val ) +#define GET_TBU() GET_REGISTER( "mfspr %0,285" ) +#define SET_TBU(val) SET_REGISTER( "mtspr 285,%0", val ) +#define GET_PVR() GET_REGISTER( "mfspr %0,287" ) +#define SET_PVR(val) SET_REGISTER( "mtspr 287,%0", val ) +#define GET_IC_CST() GET_REGISTER( "mfspr %0,560" ) +#define SET_IC_CST(val) SET_REGISTER( "mtspr 560,%0", val ) +#define GET_IC_ADR() GET_REGISTER( "mfspr %0,561" ) +#define SET_IC_ADR(val) SET_REGISTER( "mtspr 561,%0", val ) +#define GET_IC_DAT() GET_REGISTER( "mfspr %0,562" ) +#define SET_IC_DAT(val) SET_REGISTER( "mtspr 562,%0", val ) +#define GET_DC_CST() GET_REGISTER( "mfspr %0,568" ) +#define SET_DC_CST(val) SET_REGISTER( "mtspr 568,%0", val ) +#define GET_DC_ADR() GET_REGISTER( "mfspr %0,569" ) +#define SET_DC_ADR(val) SET_REGISTER( "mtspr 569,%0", val ) +#define GET_DC_DAT() GET_REGISTER( "mfspr %0,570" ) +#define SET_DC_DAT(val) SET_REGISTER( "mtspr 570,%0", val ) +#define GET_DPDR() GET_REGISTER( "mfspr %0,630" ) +#define SET_DPDR(val) SET_REGISTER( "mtspr 630,%0", val ) +#define GET_IMMR() GET_REGISTER( "mfspr %0,638" ) +#define SET_IMMR(val) SET_REGISTER( "mtspr 638,%0", val ) +#define GET_MI_CTR() GET_REGISTER( "mfspr %0,784" ) +#define SET_MI_CTR(val) SET_REGISTER( "mtspr 784,%0", val ) +#define GET_MI_AP() GET_REGISTER( "mfspr %0,786" ) +#define SET_MI_AP(val) SET_REGISTER( "mtspr 786,%0", val ) +#define GET_MI_EPN() GET_REGISTER( "mfspr %0,787" ) +#define SET_MI_EPN(val) SET_REGISTER( "mtspr 787,%0", val ) +#define GET_MI_TWC() GET_REGISTER( "mfspr %0,789" ) +#define SET_MI_TWC(val) SET_REGISTER( "mtspr 789,%0", val ) +#define GET_MI_RPN() GET_REGISTER( "mfspr %0,790" ) +#define SET_MI_RPN(val) SET_REGISTER( "mtspr 790,%0", val ) +#define GET_MD_CTR() GET_REGISTER( "mfspr %0,792" ) +#define SET_MD_CTR(val) SET_REGISTER( "mtspr 792,%0", val ) +#define GET_M_CASID() GET_REGISTER( "mfspr %0,793" ) +#define SET_M_CASID(val) SET_REGISTER( "mtspr 793,%0", val ) +#define GET_MD_AP() GET_REGISTER( "mfspr %0,794" ) +#define SET_MD_AP(val) SET_REGISTER( "mtspr ,794%0", val ) +#define GET_MD_EPN() GET_REGISTER( "mfspr %0,795" ) +#define SET_MD_EPN(val) SET_REGISTER( "mtspr 795,%0", val ) +#define GET_M_TWB() GET_REGISTER( "mfspr %0,796" ) +#define SET_M_TWB(val) SET_REGISTER( "mtspr 796,%0", val ) +#define GET_MD_TWC() GET_REGISTER( "mfspr %0,797" ) +#define SET_MD_TWC(val) SET_REGISTER( "mtspr 797,%0", val ) +#define GET_MD_RPN() GET_REGISTER( "mfspr %0,798" ) +#define SET_MD_RPN(val) SET_REGISTER( "mtspr 798,%0", val ) +#define GET_M_TW() GET_REGISTER( "mfspr %0,799" ) +#define SET_M_TW(val) SET_REGISTER( "mtspr 799,%0", val ) +#define GET_MI_DBCAM() GET_REGISTER( "mfspr %0,816" ) +#define SET_MI_DBCAM(val) SET_REGISTER( "mtspr 816,%0", val ) +#define GET_MI_DBRAM0() GET_REGISTER( "mfspr %0,817" ) +#define SET_MI_DBRAM0(val) SET_REGISTER( "mtspr 817,%0", val ) +#define GET_MI_DBRAM1() GET_REGISTER( "mfspr %0,818" ) +#define SET_MI_DBRAM1(val) SET_REGISTER( "mtspr 818,%0", val ) +#define GET_MD_DBCAM() GET_REGISTER( "mfspr %0,824" ) +#define SET_MD_DBCA(val) SET_REGISTER( "mtspr 824,%0", val ) +#define GET_MD_DBRAM0() GET_REGISTER( "mfspr %0,825" ) +#define SET_MD_DBRAM0(val) SET_REGISTER( "mtspr 825,%0", val ) +#define GET_MD_DBRAM1() GET_REGISTER( "mfspr %0,826" ) +#define SET_MD_DBRAM1(val) SET_REGISTER( "mtspr 826,%0", val ) +#define GET_ZPR() GET_REGISTER( "mfspr %0,944" ) +#define SET_ZPR(val) SET_REGISTER( "mtspr 944,%0", val ) +#define GET_PID() GET_REGISTER( "mfspr %0,945" ) +#define SET_PID(val) SET_REGISTER( "mtspr 945,%0", val ) +#define GET_CCR0() GET_REGISTER( "mfspr %0,947" ) +#define SET_CCR0(val) SET_REGISTER( "mtspr 947,%0", val ) +#define GET_IAC3() GET_REGISTER( "mfspr %0,948" ) +#define SET_IAC3(val) SET_REGISTER( "mtspr 948,%0", val ) +#define GET_IAC4() GET_REGISTER( "mfspr %0,949" ) +#define SET_IAC4(val) SET_REGISTER( "mtspr 949,%0", val ) +#define GET_DVC1() GET_REGISTER( "mfspr %0,950" ) +#define SET_DVC1(val) SET_REGISTER( "mtspr 950,%0", val ) +#define GET_DVC2() GET_REGISTER( "mfspr %0,951" ) +#define SET_DVC2(val) SET_REGISTER( "mtspr 951,%0", val ) +#define GET_SGR() GET_REGISTER( "mfspr %0,953" ) +#define SET_SGR(val) SET_REGISTER( "mtspr 953,%0", val ) +#define GET_DCWR() GET_REGISTER( "mfspr %0,954" ) +#define SET_DCWR(val) SET_REGISTER( "mtspr 954,%0", val ) +#define GET_SLER() GET_REGISTER( "mfspr %0,955" ) +#define SET_SLER(val) SET_REGISTER( "mtspr 955,%0", val ) +#define GET_SU0R() GET_REGISTER( "mfspr %0,956" ) +#define SET_SU0R(val) SET_REGISTER( "mtspr 956,%0", val ) +#define GET_DBCR1() GET_REGISTER( "mfspr %0,957" ) +#define SET_DBCR1(val) SET_REGISTER( "mtspr 957,%0", val ) +#define GET_ICDBDR() GET_REGISTER( "mfspr %0,979" ) +#define SET_ICDBDR(val) SET_REGISTER( "mtspr 979,%0", val ) +#define GET_ESR() GET_REGISTER( "mfspr %0,980" ) +#define SET_ESR(val) SET_REGISTER( "mtspr 980,%0", val ) +#define GET_DEAR() GET_REGISTER( "mfspr %0,981" ) +#define SET_DEAR(val) SET_REGISTER( "mtspr 981,%0", val ) +#define GET_EVPR() GET_REGISTER( "mfspr %0,982" ) +#define SET_EVPR(val) SET_REGISTER( "mtspr 982,%0", val ) +#define GET_TSR() GET_REGISTER( "mfspr %0,984" ) +#define SET_TSR(val) SET_REGISTER( "mtspr 984,%0", val ) +#define GET_TCR() GET_REGISTER( "mfspr %0,986" ) +#define SET_TCR(val) SET_REGISTER( "mtspr 986,%0", val ) +#define GET_PIT() GET_REGISTER( "mfspr %0,987" ) +#define SET_PIT(val) SET_REGISTER( "mtspr 987,%0", val ) +#define GET_SRR2() GET_REGISTER( "mfspr %0,990" ) +#define SET_SRR2(val) SET_REGISTER( "mtspr 990,%0", val ) +#define GET_SRR3() GET_REGISTER( "mfspr %0,991" ) +#define SET_SRR3(val) SET_REGISTER( "mtspr 991,%0", val ) +#define GET_DBSR() GET_REGISTER( "mfspr %0,1008" ) +#define SET_DBSR(val) SET_REGISTER( "mtspr 1008,%0", val ) +#define GET_DBCR0() GET_REGISTER( "mfspr %0,1010" ) +#define SET_DBCR0(val) SET_REGISTER( "mtspr 1010,%0", val ) +#define GET_IABR() GET_REGISTER( "mfspr %0,1010" ) +#define SET_IABR(val) SET_REGISTER( "mtspr 1010,%0", val ) +#define GET_IAC1() GET_REGISTER( "mfspr %0,1012" ) +#define SET_IAC1(val) SET_REGISTER( "mtspr 1012,%0", val ) +#define GET_IAC2() GET_REGISTER( "mfspr %0,1013" ) +#define SET_IAC2(val) SET_REGISTER( "mtspr 1013,%0", val ) +#define GET_DAC1() GET_REGISTER( "mfspr %0,1014" ) +#define SET_DAC1(val) SET_REGISTER( "mtspr 1014,%0", val ) +#define GET_DAC2() GET_REGISTER( "mfspr %0,1015" ) +#define SET_DAC2(val) SET_REGISTER( "mtspr 1015,%0", val ) +#define GET_DCCR() GET_REGISTER( "mfspr %0,1018" ) +#define SET_DCCR(val) SET_REGISTER( "mtspr 1018,%0", val ) +#define GET_ICCR() GET_REGISTER( "mfspr %0,1019" ) +#define SET_ICCR(val) SET_REGISTER( "mtspr 1019,%0", val ) + +#endif /* _REGS_H */ + + +/* + * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ diff --git a/roms/u-boot/include/bedbug/tables.h b/roms/u-boot/include/bedbug/tables.h new file mode 100644 index 000000000..e675de320 --- /dev/null +++ b/roms/u-boot/include/bedbug/tables.h @@ -0,0 +1,601 @@ +/* $Id$ */ + +#ifndef TABLES_H +#define TABLES_H + +/* This is only included by common/bedbug.c, and depends on the following + * files to already be included + * common.h + * bedbug/bedbug.h + * bedbug/ppc.h + * bedbug/regs.h + */ + +struct operand operands[] = { + /*Field Name Bits Shift Hint Position */ + /*----- ------ ----- ----- ---- ------------ */ + { O_AA, "O_AA", 1, 1, OH_SILENT }, /* 30 */ + { O_BD, "O_BD", 14, 2, OH_ADDR }, /* 16-29 */ + { O_BI, "O_BI", 5, 16, 0 }, /* 11-15 */ + { O_BO, "O_BO", 5, 21, 0 }, /* 6-10 */ + { O_crbD, "O_crbD", 5, 21, 0 }, /* 6-10 */ + { O_crbA, "O_crbA", 5, 16, 0 }, /* 11-15 */ + { O_crbB, "O_crbB", 5, 11, 0 }, /* 16-20 */ + { O_CRM, "O_CRM", 8, 12, 0 }, /* 12-19 */ + { O_d, "O_d", 15, 0, OH_OFFSET }, /* 16-31 */ + { O_frC, "O_frC", 5, 6, 0 }, /* 21-25 */ + { O_frD, "O_frD", 5, 21, 0 }, /* 6-10 */ + { O_frS, "O_frS", 5, 21, 0 }, /* 6-10 */ + { O_IMM, "O_IMM", 4, 12, 0 }, /* 16-19 */ + { O_LI, "O_LI", 24, 2, OH_ADDR }, /* 6-29 */ + { O_LK, "O_LK", 1, 0, OH_SILENT }, /* 31 */ + { O_MB, "O_MB", 5, 6, 0 }, /* 21-25 */ + { O_ME, "O_ME", 5, 1, 0 }, /* 26-30 */ + { O_NB, "O_NB", 5, 11, 0 }, /* 16-20 */ + { O_OE, "O_OE", 1, 10, OH_SILENT }, /* 21 */ + { O_rA, "O_rA", 5, 16, OH_REG }, /* 11-15 */ + { O_rB, "O_rB", 5, 11, OH_REG }, /* 16-20 */ + { O_Rc, "O_Rc", 1, 0, OH_SILENT }, /* 31 */ + { O_rD, "O_rD", 5, 21, OH_REG }, /* 6-10 */ + { O_rS, "O_rS", 5, 21, OH_REG }, /* 6-10 */ + { O_SH, "O_SH", 5, 11, 0 }, /* 16-20 */ + { O_SIMM, "O_SIMM", 16, 0, 0 }, /* 16-31 */ + { O_SR, "O_SR", 4, 16, 0 }, /* 12-15 */ + { O_TO, "O_TO", 5, 21, 0 }, /* 6-10 */ + { O_UIMM, "O_UIMM", 16, 0, 0 }, /* 16-31 */ + { O_crfD, "O_crfD", 3, 23, 0 }, /* 6- 8 */ + { O_crfS, "O_crfS", 3, 18, 0 }, /* 11-13 */ + { O_L, "O_L", 1, 21, 0 }, /* 10 */ + { O_spr, "O_spr", 10, 11, OH_SPR }, /* 11-20 */ + { O_tbr, "O_tbr", 10, 11, OH_TBR }, /* 11-20 */ + { O_cr2, "O_cr2", 0, 0, OH_LITERAL }, /* "cr2" */ +}; + +const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]); + +/* A note about the fields array in the opcodes structure: + The operands are listed in the order they appear in the output. + + This table is arranged in numeric order of the opcode. Note that some + opcodes have defined bits in odd places so not all forms of a command + will be in the same place. This is done so that a binary search can be + done to find the opcodes. Note that table D.2 in the MPC860 User's + Manual "Instructions Sorted by Opcode" does not account for these + bit locations */ + +struct opcode opcodes[] = { + { D_OPCODE(3), D_MASK, {O_TO, O_rA, O_SIMM, 0}, + 0, "twi", 0 }, + { D_OPCODE(7), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "mulli", 0 }, + { D_OPCODE(8), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "subfic", 0 }, + { D_OPCODE(10), D_MASK, {O_crfD, O_L, O_rA, O_UIMM, 0}, + 0, "cmpli", 0 }, + { D_OPCODE(11), D_MASK, {O_crfD, O_L, O_rA, O_SIMM, 0}, + 0, "cmpi", 0 }, + { D_OPCODE(12), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addic", 0 }, + { D_OPCODE(13), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addic.", 0 }, + { D_OPCODE(14), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addi", H_RA0_IS_0 }, + { D_OPCODE(15), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addis", H_RA0_IS_0|H_IMM_HIGH }, + { B_OPCODE(16,0,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + handle_bc, "bc", H_RELATIVE }, + { B_OPCODE(16,0,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + 0, "bcl", H_RELATIVE }, + { B_OPCODE(16,1,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + 0, "bca", 0 }, + { B_OPCODE(16,1,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + 0, "bcla", 0 }, + { SC_OPCODE(17), SC_MASK, {0}, + 0, "sc", 0 }, + { I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "b", H_RELATIVE }, + { I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "bl", H_RELATIVE }, + { I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "ba", 0 }, + { I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "bla", 0 }, + { XL_OPCODE(19,0,0), XL_MASK, {O_crfD, O_crfS}, + 0, "mcrf", 0 }, + { XL_OPCODE(19,16,0), XL_MASK, {O_BO, O_BI, O_LK, 0}, + 0, "bclr", 0 }, + { XL_OPCODE(19,16,1), XL_MASK, {O_BO, O_BI, O_LK, 0}, + 0, "bclrl", 0 }, + { XL_OPCODE(19,33,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crnor", 0 }, + { XL_OPCODE(19,50,0), XL_MASK, {0}, + 0, "rfi", 0 }, + { XL_OPCODE(19,129,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crandc", 0 }, + { XL_OPCODE(19,150,0), XL_MASK, {0}, + 0, "isync", 0 }, + { XL_OPCODE(19,193,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crxor", 0 }, + { XL_OPCODE(19,225,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crnand", 0 }, + { XL_OPCODE(19,257,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crand", 0 }, + { XL_OPCODE(19,289,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "creqv", 0 }, + { XL_OPCODE(19,417,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crorc", 0 }, + { XL_OPCODE(19,449,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "cror", 0 }, + { XL_OPCODE(19,528,0), XL_MASK, {O_BO, O_BI, O_LK, 0}, + 0, "bcctr", 0 }, + { XL_OPCODE(19,528,1), XL_MASK, {O_BO, O_BI, O_LK, 0}, + 0, "bcctrl", 0 }, + { M_OPCODE(20,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwimi", 0 }, + { M_OPCODE(20,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwimi.", 0 }, + { M_OPCODE(21,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwinm", 0 }, + { M_OPCODE(21,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwinm.", 0 }, + { M_OPCODE(23,0), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0}, + 0, "rlwnm", 0 }, + { M_OPCODE(23,1), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0}, + 0, "rlwnm.", 0 }, + { D_OPCODE(24), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "ori", 0 }, + { D_OPCODE(25), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "oris", H_IMM_HIGH }, + { D_OPCODE(26), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "xori", 0 }, + { D_OPCODE(27), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "xoris", H_IMM_HIGH }, + { D_OPCODE(28), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "andi.", 0 }, + { D_OPCODE(29), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "andis.", H_IMM_HIGH }, + { X_OPCODE(31,0,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0}, + 0, "cmp", 0 }, + { X_OPCODE(31,4,0), X_MASK, {O_TO, O_rA, O_rB, 0}, + 0, "tw", 0 }, + { XO_OPCODE(31,8,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfc", 0 }, + { XO_OPCODE(31,8,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfc.", 0 }, + { XO_OPCODE(31,10,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addc", 0 }, + { XO_OPCODE(31,10,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addc.", 0 }, + { XO_OPCODE(31,11,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, + 0, "mulhwu", 0 }, + { XO_OPCODE(31,11,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, + 0, "mulhwu.", 0 }, + { X_OPCODE(31,19,0), X_MASK, {O_rD, 0}, + 0, "mfcr", 0 }, + { X_OPCODE(31,20,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwarx", H_RA0_IS_0 }, + { X_OPCODE(31,23,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwzx", H_RA0_IS_0 }, + { X_OPCODE(31,24,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "slw", 0 }, + { X_OPCODE(31,24,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "slw.", 0 }, + { X_OPCODE(31,26,0), X_MASK, {O_rA, O_rS, O_Rc, 0 }, + 0, "cntlzw", 0 }, + { X_OPCODE(31,26,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "cntlzw.", 0 }, + { X_OPCODE(31,28,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "and", 0 }, + { X_OPCODE(31,28,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "and.", 0 }, + { X_OPCODE(31,32,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0}, + 0, "cmpl", 0 }, + { XO_OPCODE(31,40,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subf", 0 }, + { XO_OPCODE(31,40,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subf.", 0 }, + { X_OPCODE(31,54,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbst", H_RA0_IS_0 }, + { X_OPCODE(31,55,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwzux", 0 }, + { X_OPCODE(31,60,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "andc", 0 }, + { X_OPCODE(31,60,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "andc.", 0 }, + { XO_OPCODE(31,75,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, + 0, "mulhw", 0 }, + { XO_OPCODE(31,75,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, + 0, "mulhw.", 0 }, + { X_OPCODE(31,83,0), X_MASK, {O_rD, 0}, + 0, "mfmsr", 0 }, + { X_OPCODE(31,86,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbf", H_RA0_IS_0 }, + { X_OPCODE(31,87,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lbzx", H_RA0_IS_0 }, + { XO_OPCODE(31,104,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "neg", 0 }, + { XO_OPCODE(31,104,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "neg.", 0 }, + { X_OPCODE(31,119,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lbzux", 0 }, + { X_OPCODE(31,124,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "nor", 0 }, + { X_OPCODE(31,124,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "nor.", 0 }, + { XO_OPCODE(31,136,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfe", 0 }, + { XO_OPCODE(31,136,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfe.", 0 }, + { XO_OPCODE(31,138,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "adde", 0 }, + { XO_OPCODE(31,138,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "adde.", 0 }, + { XFX_OPCODE(31,144,0), XFX_MASK, {O_CRM, O_rS, 0}, + 0, "mtcrf", 0 }, + { X_OPCODE(31,146,0), X_MASK, {O_rS, 0}, + 0, "mtmsr", 0 }, + { X_OPCODE(31,150,1), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stwcx.", 0 }, + { X_OPCODE(31,151,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stwx", 0 }, + { X_OPCODE(31,183,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stwux", 0 }, + { XO_OPCODE(31,200,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfze", 0 }, + { XO_OPCODE(31,200,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfze.", 0 }, + { XO_OPCODE(31,202,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addze", 0 }, + { XO_OPCODE(31,202,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addze.", 0 }, + { X_OPCODE(31,210,0), X_MASK, {O_SR, O_rS, 0}, + 0, "mtsr", 0 }, + { X_OPCODE(31,215,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stbx", H_RA0_IS_0 }, + { XO_OPCODE(31,232,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfme", 0 }, + { XO_OPCODE(31,232,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfme.", 0 }, + { XO_OPCODE(31,234,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addme", 0 }, + { XO_OPCODE(31,234,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addme.", 0 }, + { XO_OPCODE(31,235,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "mullw", 0 }, + { XO_OPCODE(31,235,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "mullw.", 0 }, + { X_OPCODE(31,242,0), X_MASK, {O_rS, O_rB, 0}, + 0, "mtsrin", 0 }, + { X_OPCODE(31,246,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbtst", H_RA0_IS_0 }, + { X_OPCODE(31,247,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stbux", 0 }, + { XO_OPCODE(31,266,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "add", 0 }, + { XO_OPCODE(31,266,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "add.", 0 }, + { X_OPCODE(31,278,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbt", H_RA0_IS_0 }, + { X_OPCODE(31,279,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lhzx", H_RA0_IS_0 }, + { X_OPCODE(31,284,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "eqv", 0 }, + { X_OPCODE(31,284,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "eqv.", 0 }, + { X_OPCODE(31,306,0), X_MASK, {O_rB, 0}, + 0, "tlbie", 0 }, + { X_OPCODE(31,310,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "eciwx", H_RA0_IS_0 }, + { X_OPCODE(31,311,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lhzux", 0 }, + { X_OPCODE(31,316,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "xor", 0 }, + { X_OPCODE(31,316,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "xor.", 0 }, + { XFX_OPCODE(31,339,0), XFX_MASK, {O_rD, O_spr, 0}, + 0, "mfspr", 0 }, + { X_OPCODE(31,343,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lhax", H_RA0_IS_0 }, + { X_OPCODE(31,370,0), X_MASK, {0}, + 0, "tlbia", 0 }, + { XFX_OPCODE(31,371,0), XFX_MASK, {O_rD, O_tbr, 0}, + 0, "mftb", 0 }, + { X_OPCODE(31,375,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lhaux", 0 }, + { X_OPCODE(31,407,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "sthx", H_RA0_IS_0 }, + { X_OPCODE(31,412,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "orc", 0 }, + { X_OPCODE(31,412,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "orc.", 0 }, + { X_OPCODE(31,438,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "ecowx", H_RA0_IS_0 }, + { X_OPCODE(31,439,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "sthux", 0 }, + { X_OPCODE(31,444,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "or", 0 }, + { X_OPCODE(31,444,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "or.", 0 }, + { XO_OPCODE(31,459,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwu", 0 }, + { XO_OPCODE(31,459,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwu.", 0 }, + { XFX_OPCODE(31,467,0), XFX_MASK, {O_spr, O_rS, 0}, + 0, "mtspr", 0 }, + { X_OPCODE(31,470,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbi", H_RA0_IS_0 }, + { X_OPCODE(31,476,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "nand", 0 }, + { X_OPCODE(31,476,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc,0}, + 0, "nand.", 0 }, + { XO_OPCODE(31,491,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divw", 0 }, + { XO_OPCODE(31,491,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divw.", 0 }, + { X_OPCODE(31,512,0), X_MASK, {O_crfD, 0}, + 0, "mcrxr", 0 }, + { XO_OPCODE(31,8,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfco", 0 }, + { XO_OPCODE(31,8,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfco.", 0 }, + { XO_OPCODE(31,10,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addco", 0 }, + { XO_OPCODE(31,10,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addco.", 0 }, + { X_OPCODE(31,533,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lswx", H_RA0_IS_0 }, + { X_OPCODE(31,534,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwbrx", H_RA0_IS_0 }, + { X_OPCODE(31,536,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "srw", 0 }, + { X_OPCODE(31,536,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "srw.", 0 }, + { XO_OPCODE(31,40,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfo", 0 }, + { XO_OPCODE(31,40,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfo.", 0 }, + { X_OPCODE(31,566,0), X_MASK, {0}, + 0, "tlbsync", 0 }, + { X_OPCODE(31,595,0), X_MASK, {O_rD, O_SR, 0}, + 0, "mfsr", 0 }, + { X_OPCODE(31,597,0), X_MASK, {O_rD, O_rA, O_NB, 0}, + 0, "lswi", H_RA0_IS_0 }, + { X_OPCODE(31,598,0), X_MASK, {0}, + 0, "sync", 0 }, + { XO_OPCODE(31,104,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "nego", 0 }, + { XO_OPCODE(31,104,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "nego.", 0 }, + { XO_OPCODE(31,136,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfeo", 0 }, + { XO_OPCODE(31,136,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfeo.", 0 }, + { XO_OPCODE(31,138,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addeo", 0 }, + { XO_OPCODE(31,138,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addeo.", 0 }, + { X_OPCODE(31,659,0), X_MASK, {O_rD, O_rB, 0}, + 0, "mfsrin", 0 }, + { X_OPCODE(31,661,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stswx", H_RA0_IS_0 }, + { X_OPCODE(31,662,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stwbrx", H_RA0_IS_0 }, + { XO_OPCODE(31,200,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfzeo", 0 }, + { XO_OPCODE(31,200,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfzeo.", 0 }, + { XO_OPCODE(31,202,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addzeo", 0 }, + { XO_OPCODE(31,202,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addzeo.", 0 }, + { X_OPCODE(31,725,0), X_MASK, {O_rS, O_rA, O_NB, 0}, + 0, "stswi", H_RA0_IS_0 }, + { XO_OPCODE(31,232,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfmeo", 0 }, + { XO_OPCODE(31,232,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfmeo.", 0 }, + { XO_OPCODE(31,234,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addmeo", 0 }, + { XO_OPCODE(31,234,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addmeo.", 0 }, + { XO_OPCODE(31,235,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "mullwo", 0 }, + { XO_OPCODE(31,235,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "mullwo.", 0 }, + { XO_OPCODE(31,266,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addo", 0 }, + { XO_OPCODE(31,266,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addo.", 0 }, + { X_OPCODE(31,790,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lhbrx", H_RA0_IS_0 }, + { X_OPCODE(31,792,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "sraw", 0 }, + { X_OPCODE(31,792,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "sraw.", 0 }, + { X_OPCODE(31,824,0), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0}, + 0, "srawi", 0 }, + { X_OPCODE(31,824,1), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0}, + 0, "srawi.", 0 }, + { X_OPCODE(31,854,0), X_MASK, {0}, + 0, "eieio", 0 }, + { X_OPCODE(31,918,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "sthbrx", H_RA0_IS_0 }, + { X_OPCODE(31,922,0), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "extsh", 0 }, + { X_OPCODE(31,922,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "extsh.", 0 }, + { X_OPCODE(31,954,0), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "extsb", 0 }, + { X_OPCODE(31,954,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "extsb.", 0 }, + { XO_OPCODE(31,459,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwuo", 0 }, + { XO_OPCODE(31,459,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwuo.", 0 }, + { X_OPCODE(31,978,0), X_MASK, {O_rB, 0}, + 0, "tlbld", 0 }, + { X_OPCODE(31,982,0), X_MASK, {O_rA, O_rB, 0}, + 0, "icbi", H_RA0_IS_0 }, + { XO_OPCODE(31,491,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwo", 0 }, + { XO_OPCODE(31,491,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwo.", 0 }, + { X_OPCODE(31,1010,0), X_MASK, {O_rB, 0}, + 0, "tlbli", 0 }, + { X_OPCODE(31,1014,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbz", H_RA0_IS_0 }, + { D_OPCODE(32), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lwz", H_RA0_IS_0 }, + { D_OPCODE(33), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lwzu", 0 }, + { D_OPCODE(34), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lbz", H_RA0_IS_0 }, + { D_OPCODE(35), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lbzu", 0 }, + { D_OPCODE(36), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stw", H_RA0_IS_0 }, + { D_OPCODE(37), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stwu", 0 }, + { D_OPCODE(38), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stb", H_RA0_IS_0 }, + { D_OPCODE(39), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stbu", 0 }, + { D_OPCODE(40), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lhz", H_RA0_IS_0 }, + { D_OPCODE(41), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lhzu", 0 }, + { D_OPCODE(42), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lha", H_RA0_IS_0 }, + { D_OPCODE(43), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lhau", 0 }, + { D_OPCODE(44), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "sth", H_RA0_IS_0 }, + { D_OPCODE(45), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "sthu", 0 }, + { D_OPCODE(46), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lmw", H_RA0_IS_0 }, + { D_OPCODE(47), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stmw", H_RA0_IS_0 }, +}; + +const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]); + +struct spr_info spr_map[] = { + { SPR_XER, "XER" }, + { SPR_LR, "LR" }, + { SPR_CTR, "CTR" }, + { SPR_DSISR, "DSISR" }, + { SPR_DAR, "DAR" }, + { SPR_DEC, "DEC" }, + { SPR_SRR0, "SRR0" }, + { SPR_SRR1, "SRR1" }, + { SPR_EIE, "EIE" }, + { SPR_EID, "EID" }, + { SPR_CMPA, "CMPA" }, + { SPR_CMPB, "CMPB" }, + { SPR_CMPC, "CMPC" }, + { SPR_CMPD, "CMPD" }, + { SPR_ICR, "ICR" }, + { SPR_DER, "DER" }, + { SPR_COUNTA, "COUNTA" }, + { SPR_COUNTB, "COUNTB" }, + { SPR_CMPE, "CMPE" }, + { SPR_CMPF, "CMPF" }, + { SPR_CMPG, "CMPG" }, + { SPR_CMPH, "CMPH" }, + { SPR_LCTRL1, "LCTRL1" }, + { SPR_LCTRL2, "LCTRL2" }, + { SPR_ICTRL, "ICTRL" }, + { SPR_BAR, "BAR" }, + { SPR_USPRG0, "USPRG0" }, + { SPR_SPRG4_RO, "SPRG4_RO" }, + { SPR_SPRG5_RO, "SPRG5_RO" }, + { SPR_SPRG6_RO, "SPRG6_RO" }, + { SPR_SPRG7_RO, "SPRG7_RO" }, + { SPR_SPRG0, "SPRG0" }, + { SPR_SPRG1, "SPRG1" }, + { SPR_SPRG2, "SPRG2" }, + { SPR_SPRG3, "SPRG3" }, + { SPR_SPRG4, "SPRG4" }, + { SPR_SPRG5, "SPRG5" }, + { SPR_SPRG6, "SPRG6" }, + { SPR_SPRG7, "SPRG7" }, + { SPR_EAR, "EAR" }, + { SPR_TBL, "TBL" }, + { SPR_TBU, "TBU" }, + { SPR_IC_CST, "IC_CST" }, + { SPR_IC_ADR, "IC_ADR" }, + { SPR_IC_DAT, "IC_DAT" }, + { SPR_DC_CST, "DC_CST" }, + { SPR_DC_ADR, "DC_ADR" }, + { SPR_DC_DAT, "DC_DAT" }, + { SPR_DPDR, "DPDR" }, + { SPR_IMMR, "IMMR" }, + { SPR_MI_CTR, "MI_CTR" }, + { SPR_MI_AP, "MI_AP" }, + { SPR_MI_EPN, "MI_EPN" }, + { SPR_MI_TWC, "MI_TWC" }, + { SPR_MI_RPN, "MI_RPN" }, + { SPR_MD_CTR, "MD_CTR" }, + { SPR_M_CASID, "M_CASID" }, + { SPR_MD_AP, "MD_AP" }, + { SPR_MD_EPN, "MD_EPN" }, + { SPR_M_TWB, "M_TWB" }, + { SPR_MD_TWC, "MD_TWC" }, + { SPR_MD_RPN, "MD_RPN" }, + { SPR_M_TW, "M_TW" }, + { SPR_MI_DBCAM, "MI_DBCAM" }, + { SPR_MI_DBRAM0, "MI_DBRAM0" }, + { SPR_MI_DBRAM1, "MI_DBRAM1" }, + { SPR_MD_DBCAM, "MD_DBCAM" }, + { SPR_MD_DBRAM0, "MD_DBRAM0" }, + { SPR_MD_DBRAM1, "MD_DBRAM1" }, + { SPR_ZPR, "ZPR" }, + { SPR_PID, "PID" }, + { SPR_CCR0, "CCR0" }, + { SPR_IAC3, "IAC3" }, + { SPR_IAC4, "IAC4" }, + { SPR_DVC1, "DVC1" }, + { SPR_DVC2, "DVC2" }, + { SPR_SGR, "SGR" }, + { SPR_DCWR, "DCWR" }, + { SPR_SLER, "SLER" }, + { SPR_SU0R, "SU0R" }, + { SPR_DBCR1, "DBCR1" }, + { SPR_ICDBDR, "ICDBDR" }, + { SPR_ESR, "ESR" }, + { SPR_DEAR, "DEAR" }, + { SPR_EVPR, "EVPR" }, + { SPR_TSR, "TSR" }, + { SPR_TCR, "TCR" }, + { SPR_PIT, "PIT" }, + { SPR_SRR2, "SRR2" }, + { SPR_SRR3, "SRR3" }, + { SPR_DBSR, "DBSR" }, + { SPR_DBCR0, "DBCR0" }, + { SPR_IAC1, "IAC1" }, + { SPR_IAC2, "IAC2" }, + { SPR_DAC1, "DAC1" }, + { SPR_DAC2, "DAC2" }, + { SPR_DCCR, "DCCR" }, + { SPR_ICCR, "ICCR" }, +}; + +const unsigned int n_sprs = sizeof(spr_map) / sizeof(spr_map[0]); + +#endif + +/* + * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ diff --git a/roms/u-boot/include/bedbug/type.h b/roms/u-boot/include/bedbug/type.h new file mode 100644 index 000000000..f7a719caf --- /dev/null +++ b/roms/u-boot/include/bedbug/type.h @@ -0,0 +1,29 @@ +#ifndef _TYPE_BEDBUG_H +#define _TYPE_BEDBUG_H + +struct cmd_tbl; + +/* Supporting routines */ +int bedbug_puts (const char *); +int bedbug_init(void); +void bedbug860_init (void); +void do_bedbug_breakpoint (struct pt_regs *); +void bedbug_main_loop (unsigned long, struct pt_regs *); + + +typedef struct { + int hw_debug_enabled; + int stopped; + int current_bp; + struct pt_regs *regs; + + void (*do_break)(struct cmd_tbl *cmd, int flags, int argc, + char *const argv[]); + void (*break_isr) (struct pt_regs *); + int (*find_empty) (void); + int (*set) (int, unsigned long); + int (*clear) (int); +} CPU_DEBUG_CTX; + + +#endif /* _TYPE_BEDBUG_H */ diff --git a/roms/u-boot/include/binman.h b/roms/u-boot/include/binman.h new file mode 100644 index 000000000..5958dfb44 --- /dev/null +++ b/roms/u-boot/include/binman.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Access to binman information at runtime + * + * Copyright 2019 Google LLC + * Written by Simon Glass + */ + +#ifndef _BINMAN_H_ +#define _BINMAN_H_ + +#include + +/** + *struct binman_entry - information about a binman entry + * + * @image_pos: Position of entry in the image + * @size: Size of entry + */ +struct binman_entry { + u32 image_pos; + u32 size; +}; + +/** + * binman_entry_map() - Look up the address of an entry in memory + * + * @parent: Parent binman node + * @name: Name of entry + * @bufp: Returns a pointer to the entry + * @sizep: Returns the size of the entry + * @return 0 on success, -EPERM if the ROM offset is not set, -ENOENT if the + * entry cannot be found, other error code other error + */ +int binman_entry_map(ofnode parent, const char *name, void **bufp, int *sizep); + +/** + * binman_set_rom_offset() - Set the ROM memory-map offset + * + * @rom_offset: Offset from an image_pos to the memory-mapped address. This + * tells binman that ROM image_pos x can be addressed at rom_offset + x + */ +void binman_set_rom_offset(int rom_offset); + +/** + * binman_get_rom_offset() - Get the ROM memory-map offset + * + * @returns offset from an image_pos to the memory-mapped address + */ +int binman_get_rom_offset(void); + +/** + * binman_entry_find() - Find a binman symbol + * + * This searches the binman information in the device tree for a symbol of the + * given name + * + * @name: Path to entry to examine (e.g. "/read-only/u-boot") + * @entry: Returns information about the entry + * @return 0 if OK, -ENOENT if the path is not found, other -ve value if the + * binman information is invalid (missing image-pos or size) + */ +int binman_entry_find(const char *name, struct binman_entry *entry); + +/** + * binman_section_find_node() - Find a binman node + * + * @name: Name of node to look for + * @return Node that was found, ofnode_null() if not found + */ +ofnode binman_section_find_node(const char *name); + +/** + * binman_select_subnode() - Select a subnode to use to find entries + * + * Normally binman selects the top-level node for future entry requests, such as + * binman_entry_find(). This function allows a subnode to be chosen instead. + * + * @name: Name of subnode, typically a section. This must be in the top-level + * binman node + * @return 0 if OK, -EINVAL if there is no /binman node, -ECHILD if multiple + * images are being used but the first image is not available, -ENOENT if + * the requested subnode cannot be found + */ +int binman_select_subnode(const char *name); + +/** + * binman_init() - Set up the binman symbol information + * + * This locates the binary symbol information in the device tree ready for use + * + * @return 0 if OK, -ENOMEM if out of memory, -EINVAL if there is no binman node + */ +int binman_init(void); + +#endif diff --git a/roms/u-boot/include/binman_sym.h b/roms/u-boot/include/binman_sym.h new file mode 100644 index 000000000..72e6765fe --- /dev/null +++ b/roms/u-boot/include/binman_sym.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Symbol access for symbols set up by binman as part of the build. + * + * This allows C code to access the position of a particular part of the image + * assembled by binman. + * + * Copyright (c) 2017 Google, Inc + */ + +#ifndef __BINMAN_SYM_H +#define __BINMAN_SYM_H + +#define BINMAN_SYM_MISSING (-1UL) + +#ifdef CONFIG_BINMAN + +/** + * binman_symname() - Internal function to get a binman symbol name + * + * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl') + * @_prop_name: Property value to get from that entry (e.g. 'pos') + * @returns name of the symbol for that entry and property + */ +#define binman_symname(_entry_name, _prop_name) \ + _binman_ ## _entry_name ## _prop_ ## _prop_name + +/** + * binman_sym_declare() - Declare a symbol that will be used at run-time + * + * @_type: Type f the symbol (e.g. unsigned long) + * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl') + * @_prop_name: Property value to get from that entry (e.g. 'pos') + */ +#define binman_sym_declare(_type, _entry_name, _prop_name) \ + _type binman_symname(_entry_name, _prop_name) \ + __attribute__((aligned(4), unused, section(".binman_sym"))) + +/** + * binman_sym_extern() - Declare a extern symbol that will be used at run-time + * + * @_type: Type f the symbol (e.g. unsigned long) + * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl') + * @_prop_name: Property value to get from that entry (e.g. 'pos') + */ +#define binman_sym_extern(_type, _entry_name, _prop_name) \ + extern _type binman_symname(_entry_name, _prop_name) \ + __attribute__((aligned(4), unused, section(".binman_sym"))) + +/** + * binman_sym_declare_optional() - Declare an optional symbol + * + * If this symbol cannot be provided by binman, an error will not be generated. + * Instead the image will be assigned the value BINMAN_SYM_MISSING. + * + * @_type: Type f the symbol (e.g. unsigned long) + * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl') + * @_prop_name: Property value to get from that entry (e.g. 'pos') + */ +#define binman_sym_declare_optional(_type, _entry_name, _prop_name) \ + _type binman_symname(_entry_name, _prop_name) \ + __attribute__((aligned(4), weak, unused, \ + section(".binman_sym"))) + +/** + * binman_sym() - Access a previously declared symbol + * + * This is used to get the value of a symbol. E.g.: + * + * ulong address = binman_sym(ulong, u_boot_spl, pos); + * + * @_type: Type f the symbol (e.g. unsigned long) + * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl') + * @_prop_name: Property value to get from that entry (e.g. 'pos') + * @returns value of that property (filled in by binman) + */ +#define binman_sym(_type, _entry_name, _prop_name) \ + (*(_type *)&binman_symname(_entry_name, _prop_name)) + +#else /* !BINMAN */ + +#define binman_sym_declare(_type, _entry_name, _prop_name) + +#define binman_sym_declare_optional(_type, _entry_name, _prop_name) + +#define binman_sym_extern(_type, _entry_name, _prop_name) + +#define binman_sym(_type, _entry_name, _prop_name) BINMAN_SYM_MISSING + +#endif /* BINMAN */ + +#endif diff --git a/roms/u-boot/include/bios_emul.h b/roms/u-boot/include/bios_emul.h new file mode 100644 index 000000000..158e0f223 --- /dev/null +++ b/roms/u-boot/include/bios_emul.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 1996-1999 SciTech Software, Inc. + */ + +#ifndef _BIOS_EMUL_H +#define _BIOS_EMUL_H + +/* Include the register header directly here */ +#include "../drivers/bios_emulator/include/x86emu/regs.h" +#include + +/**************************************************************************** +REMARKS: +Data structure used to describe the details for the BIOS emulator system +environment as used by the X86 emulator library. + +HEADER: +biosemu.h + +MEMBERS: +vgaInfo - VGA BIOS information structure +biosmem_base - Base of the BIOS image +biosmem_limit - Limit of the BIOS image +busmem_base - Base of the VGA bus memory +****************************************************************************/ +typedef struct { + int function; + int device; + int bus; + u32 VendorID; + u32 DeviceID; +#ifdef CONFIG_DM_PCI + struct udevice *pcidev; +#else + pci_dev_t pcidev; +#endif + void *BIOSImage; + u32 BIOSImageLen; + u8 LowMem[1536]; +} BE_VGAInfo; + +struct vbe_mode_info; + +#ifdef CONFIG_DM_PCI +int BootVideoCardBIOS(struct udevice *pcidev, BE_VGAInfo **pVGAInfo, + int clean_up); +#else +int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up); +#endif + +/* Run a BIOS ROM natively (only supported on x86 machines) */ +void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode, + struct vbe_mode_info *mode_info); + +/** + * bios_set_interrupt_handler() - Install an interrupt handler for the BIOS + * + * This installs an interrupt handler that the BIOS will call when needed. + * + * @intnum: Interrupt number to install a handler for + * @int_handler_func: Function to call to handle interrupt + */ +void bios_set_interrupt_handler(int intnum, int (*int_handler_func)(void)); + +void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void)); + +#ifdef CONFIG_DM_PCI +int biosemu_setup(struct udevice *pcidev, BE_VGAInfo **pVGAInfo); + +int biosemu_run(struct udevice *dev, uchar *bios_rom, int bios_len, + BE_VGAInfo *vga_info, int clean_up, int vesa_mode, + struct vbe_mode_info *mode_info); +#else +int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo); + +int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len, + BE_VGAInfo *vga_info, int clean_up, int vesa_mode, + struct vbe_mode_info *mode_info); +#endif + +#endif diff --git a/roms/u-boot/include/bitfield.h b/roms/u-boot/include/bitfield.h new file mode 100644 index 000000000..d3ceeedcc --- /dev/null +++ b/roms/u-boot/include/bitfield.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 Broadcom Corporation. + */ + +/* + * Bitfield operations + * + * These are generic bitfield operations which allow manipulation of variable + * width bitfields within a word. One use of this would be to use data tables + * to determine how to reprogram fields within R/W hardware registers. + * + * Example: + * + * old_reg_val + * +--------+----+---+--+-----+----------+ + * | | | | | old | | + * +--------+----+---+--+-----+----------+ + * + * new_reg_val + * +--------+----+---+--+-----+----------+ + * | | | | | new | | + * +--------+----+---+--+-----+----------+ + * + * mask = bitfield_mask(10, 5); + * old = bitfield_extract(old_reg_val, 10, 5); + * new_reg_val = bitfield_replace(old_reg_val, 10, 5, new); + * + * or + * + * mask = bitfield_mask(10, 5); + * old = bitfield_extract_by_mask(old_reg_val, mask); + * new_reg_val = bitfield_replace_by_mask(old_reg_val, mask, new); + * + * The numbers 10 and 5 could for example come from data + * tables which describe all bitfields in all registers. + */ + +#include +#include + +/* Produces a mask of set bits covering a range of a uint value */ +static inline uint bitfield_mask(uint shift, uint width) +{ + return ((1 << width) - 1) << shift; +} + +/* Extract the value of a bitfield found within a given register value */ +static inline uint bitfield_extract(uint reg_val, uint shift, uint width) +{ + return (reg_val & bitfield_mask(shift, width)) >> shift; +} + +/* + * Replace the value of a bitfield found within a given register value + * Returns the newly modified uint value with the replaced field. + */ +static inline uint bitfield_replace(uint reg_val, uint shift, uint width, + uint bitfield_val) +{ + uint mask = bitfield_mask(shift, width); + + return (reg_val & ~mask) | ((bitfield_val << shift) & mask); +} + +/* Produces a shift of the bitfield given a mask */ +static inline uint bitfield_shift(uint mask) +{ + return mask ? ffs(mask) - 1 : 0; +} + +/* Extract the value of a bitfield found within a given register value */ +static inline uint bitfield_extract_by_mask(uint reg_val, uint mask) +{ + uint shift = bitfield_shift(mask); + + return (reg_val & mask) >> shift; +} + +/* + * Replace the value of a bitfield found within a given register value + * Returns the newly modified uint value with the replaced field. + */ +static inline uint bitfield_replace_by_mask(uint reg_val, uint mask, + uint bitfield_val) +{ + uint shift = bitfield_shift(mask); + + return (reg_val & ~mask) | ((bitfield_val << shift) & mask); +} diff --git a/roms/u-boot/include/blk.h b/roms/u-boot/include/blk.h new file mode 100644 index 000000000..c4401b002 --- /dev/null +++ b/roms/u-boot/include/blk.h @@ -0,0 +1,686 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef BLK_H +#define BLK_H + +#include + +#ifdef CONFIG_SYS_64BIT_LBA +typedef uint64_t lbaint_t; +#define LBAFlength "ll" +#else +typedef ulong lbaint_t; +#define LBAFlength "l" +#endif +#define LBAF "%" LBAFlength "x" +#define LBAFU "%" LBAFlength "u" + +/* Interface types: */ +enum if_type { + IF_TYPE_UNKNOWN = 0, + IF_TYPE_IDE, + IF_TYPE_SCSI, + IF_TYPE_ATAPI, + IF_TYPE_USB, + IF_TYPE_DOC, + IF_TYPE_MMC, + IF_TYPE_SD, + IF_TYPE_SATA, + IF_TYPE_HOST, + IF_TYPE_NVME, + IF_TYPE_EFI, + IF_TYPE_PVBLOCK, + IF_TYPE_VIRTIO, + + IF_TYPE_COUNT, /* Number of interface types */ +}; + +#define BLK_VEN_SIZE 40 +#define BLK_PRD_SIZE 20 +#define BLK_REV_SIZE 8 + +/* + * Identifies the partition table type (ie. MBR vs GPT GUID) signature + */ +enum sig_type { + SIG_TYPE_NONE, + SIG_TYPE_MBR, + SIG_TYPE_GUID, + + SIG_TYPE_COUNT /* Number of signature types */ +}; + +/* + * With driver model (CONFIG_BLK) this is uclass platform data, accessible + * with dev_get_uclass_plat(dev) + */ +struct blk_desc { + /* + * TODO: With driver model we should be able to use the parent + * device's uclass instead. + */ + enum if_type if_type; /* type of the interface */ + int devnum; /* device number */ + unsigned char part_type; /* partition type */ + unsigned char target; /* target SCSI ID */ + unsigned char lun; /* target LUN */ + unsigned char hwpart; /* HW partition, e.g. for eMMC */ + unsigned char type; /* device type */ + unsigned char removable; /* removable device */ +#ifdef CONFIG_LBA48 + /* device can use 48bit addr (ATA/ATAPI v7) */ + unsigned char lba48; +#endif + lbaint_t lba; /* number of blocks */ + unsigned long blksz; /* block size */ + int log2blksz; /* for convenience: log2(blksz) */ + char vendor[BLK_VEN_SIZE + 1]; /* device vendor string */ + char product[BLK_PRD_SIZE + 1]; /* device product number */ + char revision[BLK_REV_SIZE + 1]; /* firmware revision */ + enum sig_type sig_type; /* Partition table signature type */ + union { + uint32_t mbr_sig; /* MBR integer signature */ + efi_guid_t guid_sig; /* GPT GUID Signature */ + }; +#if CONFIG_IS_ENABLED(BLK) + /* + * For now we have a few functions which take struct blk_desc as a + * parameter. This field allows them to look up the associated + * device. Once these functions are removed we can drop this field. + */ + struct udevice *bdev; +#else + unsigned long (*block_read)(struct blk_desc *block_dev, + lbaint_t start, + lbaint_t blkcnt, + void *buffer); + unsigned long (*block_write)(struct blk_desc *block_dev, + lbaint_t start, + lbaint_t blkcnt, + const void *buffer); + unsigned long (*block_erase)(struct blk_desc *block_dev, + lbaint_t start, + lbaint_t blkcnt); + void *priv; /* driver private struct pointer */ +#endif +}; + +#define BLOCK_CNT(size, blk_desc) (PAD_COUNT(size, blk_desc->blksz)) +#define PAD_TO_BLOCKSIZE(size, blk_desc) \ + (PAD_SIZE(size, blk_desc->blksz)) + +#if CONFIG_IS_ENABLED(BLOCK_CACHE) + +/** + * blkcache_init() - initialize the block cache list pointers + */ +int blkcache_init(void); + +/** + * blkcache_read() - attempt to read a set of blocks from cache + * + * @param iftype - IF_TYPE_x for type of device + * @param dev - device index of particular type + * @param start - starting block number + * @param blkcnt - number of blocks to read + * @param blksz - size in bytes of each block + * @param buf - buffer to contain cached data + * + * @return - 1 if block returned from cache, 0 otherwise. + */ +int blkcache_read(int iftype, int dev, + lbaint_t start, lbaint_t blkcnt, + unsigned long blksz, void *buffer); + +/** + * blkcache_fill() - make data read from a block device available + * to the block cache + * + * @param iftype - IF_TYPE_x for type of device + * @param dev - device index of particular type + * @param start - starting block number + * @param blkcnt - number of blocks available + * @param blksz - size in bytes of each block + * @param buf - buffer containing data to cache + * + */ +void blkcache_fill(int iftype, int dev, + lbaint_t start, lbaint_t blkcnt, + unsigned long blksz, void const *buffer); + +/** + * blkcache_invalidate() - discard the cache for a set of blocks + * because of a write or device (re)initialization. + * + * @param iftype - IF_TYPE_x for type of device + * @param dev - device index of particular type + */ +void blkcache_invalidate(int iftype, int dev); + +/** + * blkcache_configure() - configure block cache + * + * @param blocks - maximum blocks per entry + * @param entries - maximum entries in cache + */ +void blkcache_configure(unsigned blocks, unsigned entries); + +/* + * statistics of the block cache + */ +struct block_cache_stats { + unsigned hits; + unsigned misses; + unsigned entries; /* current entry count */ + unsigned max_blocks_per_entry; + unsigned max_entries; +}; + +/** + * get_blkcache_stats() - return statistics and reset + * + * @param stats - statistics are copied here + */ +void blkcache_stats(struct block_cache_stats *stats); + +#else + +static inline int blkcache_read(int iftype, int dev, + lbaint_t start, lbaint_t blkcnt, + unsigned long blksz, void *buffer) +{ + return 0; +} + +static inline void blkcache_fill(int iftype, int dev, + lbaint_t start, lbaint_t blkcnt, + unsigned long blksz, void const *buffer) {} + +static inline void blkcache_invalidate(int iftype, int dev) {} + +#endif + +#if CONFIG_IS_ENABLED(BLK) +struct udevice; + +/* Operations on block devices */ +struct blk_ops { + /** + * read() - read from a block device + * + * @dev: Device to read from + * @start: Start block number to read (0=first) + * @blkcnt: Number of blocks to read + * @buffer: Destination buffer for data read + * @return number of blocks read, or -ve error number (see the + * IS_ERR_VALUE() macro + */ + unsigned long (*read)(struct udevice *dev, lbaint_t start, + lbaint_t blkcnt, void *buffer); + + /** + * write() - write to a block device + * + * @dev: Device to write to + * @start: Start block number to write (0=first) + * @blkcnt: Number of blocks to write + * @buffer: Source buffer for data to write + * @return number of blocks written, or -ve error number (see the + * IS_ERR_VALUE() macro + */ + unsigned long (*write)(struct udevice *dev, lbaint_t start, + lbaint_t blkcnt, const void *buffer); + + /** + * erase() - erase a section of a block device + * + * @dev: Device to (partially) erase + * @start: Start block number to erase (0=first) + * @blkcnt: Number of blocks to erase + * @return number of blocks erased, or -ve error number (see the + * IS_ERR_VALUE() macro + */ + unsigned long (*erase)(struct udevice *dev, lbaint_t start, + lbaint_t blkcnt); + + /** + * select_hwpart() - select a particular hardware partition + * + * Some devices (e.g. MMC) can support partitioning at the hardware + * level. This is quite separate from the normal idea of + * software-based partitions. MMC hardware partitions must be + * explicitly selected. Once selected only the region of the device + * covered by that partition is accessible. + * + * The MMC standard provides for two boot partitions (numbered 1 and 2), + * rpmb (3), and up to 4 addition general-purpose partitions (4-7). + * + * @desc: Block device to update + * @hwpart: Hardware partition number to select. 0 means the raw + * device, 1 is the first partition, 2 is the second, etc. + * @return 0 if OK, -ve on error + */ + int (*select_hwpart)(struct udevice *dev, int hwpart); +}; + +#define blk_get_ops(dev) ((struct blk_ops *)(dev)->driver->ops) + +/* + * These functions should take struct udevice instead of struct blk_desc, + * but this is convenient for migration to driver model. Add a 'd' prefix + * to the function operations, so that blk_read(), etc. can be reserved for + * functions with the correct arguments. + */ +unsigned long blk_dread(struct blk_desc *block_dev, lbaint_t start, + lbaint_t blkcnt, void *buffer); +unsigned long blk_dwrite(struct blk_desc *block_dev, lbaint_t start, + lbaint_t blkcnt, const void *buffer); +unsigned long blk_derase(struct blk_desc *block_dev, lbaint_t start, + lbaint_t blkcnt); + +/** + * blk_find_device() - Find a block device + * + * This function does not activate the device. The device will be returned + * whether or not it is activated. + * + * @if_type: Interface type (enum if_type_t) + * @devnum: Device number (specific to each interface type) + * @devp: the device, if found + * @return 0 if found, -ENODEV if no device found, or other -ve error value + */ +int blk_find_device(int if_type, int devnum, struct udevice **devp); + +/** + * blk_get_device() - Find and probe a block device ready for use + * + * @if_type: Interface type (enum if_type_t) + * @devnum: Device number (specific to each interface type) + * @devp: the device, if found + * @return 0 if found, -ENODEV if no device found, or other -ve error value + */ +int blk_get_device(int if_type, int devnum, struct udevice **devp); + +/** + * blk_first_device() - Find the first device for a given interface + * + * The device is probed ready for use + * + * @devnum: Device number (specific to each interface type) + * @devp: the device, if found + * @return 0 if found, -ENODEV if no device, or other -ve error value + */ +int blk_first_device(int if_type, struct udevice **devp); + +/** + * blk_next_device() - Find the next device for a given interface + * + * This can be called repeatedly after blk_first_device() to iterate through + * all devices of the given interface type. + * + * The device is probed ready for use + * + * @devp: On entry, the previous device returned. On exit, the next + * device, if found + * @return 0 if found, -ENODEV if no device, or other -ve error value + */ +int blk_next_device(struct udevice **devp); + +/** + * blk_create_device() - Create a new block device + * + * @parent: Parent of the new device + * @drv_name: Driver name to use for the block device + * @name: Name for the device + * @if_type: Interface type (enum if_type_t) + * @devnum: Device number, specific to the interface type, or -1 to + * allocate the next available number + * @blksz: Block size of the device in bytes (typically 512) + * @lba: Total number of blocks of the device + * @devp: the new device (which has not been probed) + */ +int blk_create_device(struct udevice *parent, const char *drv_name, + const char *name, int if_type, int devnum, int blksz, + lbaint_t lba, struct udevice **devp); + +/** + * blk_create_devicef() - Create a new named block device + * + * @parent: Parent of the new device + * @drv_name: Driver name to use for the block device + * @name: Name for the device (parent name is prepended) + * @if_type: Interface type (enum if_type_t) + * @devnum: Device number, specific to the interface type, or -1 to + * allocate the next available number + * @blksz: Block size of the device in bytes (typically 512) + * @lba: Total number of blocks of the device + * @devp: the new device (which has not been probed) + */ +int blk_create_devicef(struct udevice *parent, const char *drv_name, + const char *name, int if_type, int devnum, int blksz, + lbaint_t lba, struct udevice **devp); + +/** + * blk_unbind_all() - Unbind all device of the given interface type + * + * The devices are removed and then unbound. + * + * @if_type: Interface type to unbind + * @return 0 if OK, -ve on error + */ +int blk_unbind_all(int if_type); + +/** + * blk_find_max_devnum() - find the maximum device number for an interface type + * + * Finds the last allocated device number for an interface type @if_type. The + * next number is safe to use for a newly allocated device. + * + * @if_type: Interface type to scan + * @return maximum device number found, or -ENODEV if none, or other -ve on + * error + */ +int blk_find_max_devnum(enum if_type if_type); + +/** + * blk_next_free_devnum() - get the next device number for an interface type + * + * Finds the next number that is safe to use for a newly allocated device for + * an interface type @if_type. + * + * @if_type: Interface type to scan + * @return next device number safe to use, or -ve on error + */ +int blk_next_free_devnum(enum if_type if_type); + +/** + * blk_select_hwpart() - select a hardware partition + * + * Select a hardware partition if the device supports it (typically MMC does) + * + * @dev: Device to update + * @hwpart: Partition number to select + * @return 0 if OK, -ve on error + */ +int blk_select_hwpart(struct udevice *dev, int hwpart); + +/** + * blk_get_from_parent() - obtain a block device by looking up its parent + * + * All devices with + */ +int blk_get_from_parent(struct udevice *parent, struct udevice **devp); + +/** + * blk_get_by_device() - Get the block device descriptor for the given device + * @dev: Instance of a storage device + * + * Return: With block device descriptor on success , NULL if there is no such + * block device. + */ +struct blk_desc *blk_get_by_device(struct udevice *dev); + +#else +#include +/* + * These functions should take struct udevice instead of struct blk_desc, + * but this is convenient for migration to driver model. Add a 'd' prefix + * to the function operations, so that blk_read(), etc. can be reserved for + * functions with the correct arguments. + */ +static inline ulong blk_dread(struct blk_desc *block_dev, lbaint_t start, + lbaint_t blkcnt, void *buffer) +{ + ulong blks_read; + if (blkcache_read(block_dev->if_type, block_dev->devnum, + start, blkcnt, block_dev->blksz, buffer)) + return blkcnt; + + /* + * We could check if block_read is NULL and return -ENOSYS. But this + * bloats the code slightly (cause some board to fail to build), and + * it would be an error to try an operation that does not exist. + */ + blks_read = block_dev->block_read(block_dev, start, blkcnt, buffer); + if (blks_read == blkcnt) + blkcache_fill(block_dev->if_type, block_dev->devnum, + start, blkcnt, block_dev->blksz, buffer); + + return blks_read; +} + +static inline ulong blk_dwrite(struct blk_desc *block_dev, lbaint_t start, + lbaint_t blkcnt, const void *buffer) +{ + blkcache_invalidate(block_dev->if_type, block_dev->devnum); + return block_dev->block_write(block_dev, start, blkcnt, buffer); +} + +static inline ulong blk_derase(struct blk_desc *block_dev, lbaint_t start, + lbaint_t blkcnt) +{ + blkcache_invalidate(block_dev->if_type, block_dev->devnum); + return block_dev->block_erase(block_dev, start, blkcnt); +} + +/** + * struct blk_driver - Driver for block interface types + * + * This provides access to the block devices for each interface type. One + * driver should be provided using U_BOOT_LEGACY_BLK() for each interface + * type that is to be supported. + * + * @if_typename: Interface type name + * @if_type: Interface type + * @max_devs: Maximum number of devices supported + * @desc: Pointer to list of devices for this interface type, + * or NULL to use @get_dev() instead + */ +struct blk_driver { + const char *if_typename; + enum if_type if_type; + int max_devs; + struct blk_desc *desc; + /** + * get_dev() - get a pointer to a block device given its number + * + * Each interface allocates its own devices and typically + * struct blk_desc is contained with the interface's data structure. + * There is no global numbering for block devices. This method allows + * the device for an interface type to be obtained when @desc is NULL. + * + * @devnum: Device number (0 for first device on that interface, + * 1 for second, etc. + * @descp: Returns pointer to the block device on success + * @return 0 if OK, -ve on error + */ + int (*get_dev)(int devnum, struct blk_desc **descp); + + /** + * select_hwpart() - Select a hardware partition + * + * Some devices (e.g. MMC) can support partitioning at the hardware + * level. This is quite separate from the normal idea of + * software-based partitions. MMC hardware partitions must be + * explicitly selected. Once selected only the region of the device + * covered by that partition is accessible. + * + * The MMC standard provides for two boot partitions (numbered 1 and 2), + * rpmb (3), and up to 4 addition general-purpose partitions (4-7). + * Partition 0 is the main user-data partition. + * + * @desc: Block device descriptor + * @hwpart: Hardware partition number to select. 0 means the main + * user-data partition, 1 is the first partition, 2 is + * the second, etc. + * @return 0 if OK, other value for an error + */ + int (*select_hwpart)(struct blk_desc *desc, int hwpart); +}; + +/* + * Declare a new U-Boot legacy block driver. New drivers should use driver + * model (UCLASS_BLK). + */ +#define U_BOOT_LEGACY_BLK(__name) \ + ll_entry_declare(struct blk_driver, __name, blk_driver) + +struct blk_driver *blk_driver_lookup_type(int if_type); + +#endif /* !CONFIG_BLK */ + +/** + * blk_get_devnum_by_typename() - Get a block device by type and number + * + * This looks through the available block devices of the given type, returning + * the one with the given @devnum. + * + * @if_type: Block device type + * @devnum: Device number + * @return point to block device descriptor, or NULL if not found + */ +struct blk_desc *blk_get_devnum_by_type(enum if_type if_type, int devnum); + +/** + * blk_get_devnum_by_type() - Get a block device by type name, and number + * + * This looks up the block device type based on @if_typename, then calls + * blk_get_devnum_by_type(). + * + * @if_typename: Block device type name + * @devnum: Device number + * @return point to block device descriptor, or NULL if not found + */ +struct blk_desc *blk_get_devnum_by_typename(const char *if_typename, + int devnum); + +/** + * blk_dselect_hwpart() - select a hardware partition + * + * This selects a hardware partition (such as is supported by MMC). The block + * device size may change as this effectively points the block device to a + * partition at the hardware level. See the select_hwpart() method above. + * + * @desc: Block device descriptor for the device to select + * @hwpart: Partition number to select + * @return 0 if OK, -ve on error + */ +int blk_dselect_hwpart(struct blk_desc *desc, int hwpart); + +/** + * blk_list_part() - list the partitions for block devices of a given type + * + * This looks up the partition type for each block device of type @if_type, + * then displays a list of partitions. + * + * @if_type: Block device type + * @return 0 if OK, -ENODEV if there is none of that type + */ +int blk_list_part(enum if_type if_type); + +/** + * blk_list_devices() - list the block devices of a given type + * + * This lists each block device of the type @if_type, showing the capacity + * as well as type-specific information. + * + * @if_type: Block device type + */ +void blk_list_devices(enum if_type if_type); + +/** + * blk_show_device() - show information about a given block device + * + * This shows the block device capacity as well as type-specific information. + * + * @if_type: Block device type + * @devnum: Device number + * @return 0 if OK, -ENODEV for invalid device number + */ +int blk_show_device(enum if_type if_type, int devnum); + +/** + * blk_print_device_num() - show information about a given block device + * + * This is similar to blk_show_device() but returns an error if the block + * device type is unknown. + * + * @if_type: Block device type + * @devnum: Device number + * @return 0 if OK, -ENODEV for invalid device number, -ENOENT if the block + * device is not connected + */ +int blk_print_device_num(enum if_type if_type, int devnum); + +/** + * blk_print_part_devnum() - print the partition information for a device + * + * @if_type: Block device type + * @devnum: Device number + * @return 0 if OK, -ENOENT if the block device is not connected, -ENOSYS if + * the interface type is not supported, other -ve on other error + */ +int blk_print_part_devnum(enum if_type if_type, int devnum); + +/** + * blk_read_devnum() - read blocks from a device + * + * @if_type: Block device type + * @devnum: Device number + * @blkcnt: Number of blocks to read + * @buffer: Address to write data to + * @return number of blocks read, or -ve error number on error + */ +ulong blk_read_devnum(enum if_type if_type, int devnum, lbaint_t start, + lbaint_t blkcnt, void *buffer); + +/** + * blk_write_devnum() - write blocks to a device + * + * @if_type: Block device type + * @devnum: Device number + * @blkcnt: Number of blocks to write + * @buffer: Address to read data from + * @return number of blocks written, or -ve error number on error + */ +ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start, + lbaint_t blkcnt, const void *buffer); + +/** + * blk_select_hwpart_devnum() - select a hardware partition + * + * This is similar to blk_dselect_hwpart() but it looks up the interface and + * device number. + * + * @if_type: Block device type + * @devnum: Device number + * @hwpart: Partition number to select + * @return 0 if OK, -ve on error + */ +int blk_select_hwpart_devnum(enum if_type if_type, int devnum, int hwpart); + +/** + * blk_get_if_type_name() - Get the name of an interface type + * + * @if_type: Interface type to check + * @return name of interface, or NULL if none + */ +const char *blk_get_if_type_name(enum if_type if_type); + +/** + * blk_common_cmd() - handle common commands with block devices + * + * @args: Number of arguments to the command (argv[0] is the command itself) + * @argv: Command arguments + * @if_type: Interface type + * @cur_devnump: Current device number for this interface type + * @return 0 if OK, CMD_RET_ERROR on error + */ +int blk_common_cmd(int argc, char *const argv[], enum if_type if_type, + int *cur_devnump); + +#endif diff --git a/roms/u-boot/include/bloblist.h b/roms/u-boot/include/bloblist.h new file mode 100644 index 000000000..964b974fd --- /dev/null +++ b/roms/u-boot/include/bloblist.h @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This provides a standard way of passing information between boot phases + * (TPL -> SPL -> U-Boot proper.) + * + * A list of blobs of data, tagged with their owner. The list resides in memory + * and can be updated by SPL, U-Boot, etc. + * + * Copyright 2018 Google, Inc + * Written by Simon Glass + */ + +#ifndef __BLOBLIST_H +#define __BLOBLIST_H + +enum { + BLOBLIST_VERSION = 0, + BLOBLIST_MAGIC = 0xb00757a3, + BLOBLIST_ALIGN = 16, +}; + +/* Supported tags - add new ones to tag_name in bloblist.c */ +enum bloblist_tag_t { + BLOBLISTT_NONE = 0, + + /* Vendor-specific tags are permitted here */ + BLOBLISTT_EC_HOSTEVENT, /* Chromium OS EC host-event mask */ + BLOBLISTT_SPL_HANDOFF, /* Hand-off info from SPL */ + BLOBLISTT_VBOOT_CTX, /* Chromium OS verified boot context */ + BLOBLISTT_VBOOT_HANDOFF, /* Chromium OS internal handoff info */ + /* + * Advanced Configuration and Power Interface Global Non-Volatile + * Sleeping table. This forms part of the ACPI tables passed to Linux. + */ + BLOBLISTT_ACPI_GNVS, + BLOBLISTT_INTEL_VBT, /* Intel Video-BIOS table */ + BLOBLISTT_TPM2_TCG_LOG, /* TPM v2 log space */ + BLOBLISTT_TCPA_LOG, /* TPM log space */ + BLOBLISTT_ACPI_TABLES, /* ACPI tables for x86 */ + BLOBLISTT_SMBIOS_TABLES, /* SMBIOS tables for x86 */ + + BLOBLISTT_COUNT +}; + +/** + * struct bloblist_hdr - header for the bloblist + * + * This is stored at the start of the bloblist which is always on a 16-byte + * boundary. Records follow this header. The bloblist normally stays in the + * same place in memory as SPL and U-Boot execute, but it can be safely moved + * around. + * + * None of the bloblist structures contain pointers but it is possible to put + * pointers inside a bloblist record if desired. This is not encouraged, + * since it can make part of the bloblist inaccessible if the pointer is + * no-longer valid. It is better to just store all the data inside a bloblist + * record. + * + * Each bloblist record is aligned to a 16-byte boundary and follows immediately + * from the last. + * + * @version: BLOBLIST_VERSION + * @hdr_size: Size of this header, normally sizeof(struct bloblist_hdr). The + * first bloblist_rec starts at this offset from the start of the header + * @flags: Space for BLOBLISTF_... flags (none yet) + * @magic: BLOBLIST_MAGIC + * @size: Total size of all records (non-zero if valid) including this header. + * The bloblist extends for this many bytes from the start of this header. + * @alloced: Total size allocated for this bloblist. When adding new records, + * the bloblist can grow up to this size. This starts out as + * sizeof(bloblist_hdr) since we need at least that much space to store a + * valid bloblist + * @spare: Spare space (for future use) + * @chksum: CRC32 for the entire bloblist allocated area. Since any of the + * blobs can be altered after being created, this checksum is only valid + * when the bloblist is finalised before jumping to the next stage of boot. + * Note: @chksum is last to make it easier to exclude it from the checksum + * calculation. + */ +struct bloblist_hdr { + u32 version; + u32 hdr_size; + u32 flags; + u32 magic; + + u32 size; + u32 alloced; + u32 spare; + u32 chksum; +}; + +/** + * struct bloblist_rec - record for the bloblist + * + * NOTE: Only exported for testing purposes. Do not use this struct. + * + * The bloblist contains a number of records each consisting of this record + * structure followed by the data contained. Each records is 16-byte aligned. + * + * @tag: Tag indicating what the record contains + * @hdr_size: Size of this header, normally sizeof(struct bloblist_rec). The + * record's data starts at this offset from the start of the record + * @size: Size of record in bytes, excluding the header size. This does not + * need to be aligned (e.g. 3 is OK). + * @spare: Spare space for other things + */ +struct bloblist_rec { + u32 tag; + u32 hdr_size; + u32 size; + u32 spare; +}; + +/** + * bloblist_find() - Find a blob + * + * Searches the bloblist and returns the blob with the matching tag + * + * @tag: Tag to search for (enum bloblist_tag_t) + * @size: Expected size of the blob, or 0 for any size + * @return pointer to blob if found, or NULL if not found, or a blob was found + * but it is the wrong size + */ +void *bloblist_find(uint tag, int size); + +/** + * bloblist_add() - Add a new blob + * + * Add a new blob to the bloblist + * + * This should only be called if you konw there is no existing blob for a + * particular tag. It is typically safe to call in the first phase of U-Boot + * (e.g. TPL or SPL). After that, bloblist_ensure() should be used instead. + * + * @tag: Tag to add (enum bloblist_tag_t) + * @size: Size of the blob + * @align: Alignment of the blob (in bytes), 0 for default + * @return pointer to the newly added block, or NULL if there is not enough + * space for the blob + */ +void *bloblist_add(uint tag, int size, int align); + +/** + * bloblist_ensure_size() - Find or add a blob + * + * Find an existing blob, or add a new one if not found + * + * @tag: Tag to add (enum bloblist_tag_t) + * @size: Size of the blob + * @blobp: Returns a pointer to blob on success + * @align: Alignment of the blob (in bytes), 0 for default + * @return 0 if OK, -ENOSPC if it is missing and could not be added due to lack + * of space, or -ESPIPE it exists but has the wrong size + */ +int bloblist_ensure_size(uint tag, int size, int align, void **blobp); + +/** + * bloblist_ensure() - Find or add a blob + * + * Find an existing blob, or add a new one if not found + * + * @tag: Tag to add (enum bloblist_tag_t) + * @size: Size of the blob + * @return pointer to blob, or NULL if it is missing and could not be added due + * to lack of space, or it exists but has the wrong size + */ +void *bloblist_ensure(uint tag, int size); + +/** + * bloblist_ensure_size_ret() - Find or add a blob + * + * Find an existing blob, or add a new one if not found + * + * @tag: Tag to add (enum bloblist_tag_t) + * @sizep: Size of the blob to create; returns size of actual blob + * @blobp: Returns a pointer to blob on success + * @return 0 if OK, -ENOSPC if it is missing and could not be added due to lack + * of space + */ +int bloblist_ensure_size_ret(uint tag, int *sizep, void **blobp); + +/** + * bloblist_new() - Create a new, empty bloblist of a given size + * + * @addr: Address of bloblist + * @size: Initial size for bloblist + * @flags: Flags to use for bloblist + * @return 0 if OK, -EFAULT if addr is not aligned correctly, -ENOSPC is the + * area is not large enough + */ +int bloblist_new(ulong addr, uint size, uint flags); + +/** + * bloblist_check() - Check if a bloblist exists + * + * @addr: Address of bloblist + * @size: Expected size of blobsize, or 0 to detect the size + * @return 0 if OK, -ENOENT if the magic number doesn't match (indicating that + * there problem is no bloblist at the given address), -EPROTONOSUPPORT + * if the version does not match, -EIO if the checksum does not match, + * -EFBIG if the expected size does not match the detected size, -ENOSPC + * if the size is not large enough to hold the headers + */ +int bloblist_check(ulong addr, uint size); + +/** + * bloblist_finish() - Set up the bloblist for the next U-Boot part + * + * This sets the correct checksum for the bloblist. This ensures that the + * bloblist will be detected correctly by the next phase of U-Boot. + * + * @return 0 + */ +int bloblist_finish(void); + +/** + * bloblist_get_stats() - Get information about the bloblist + * + * This returns useful information about the bloblist + */ +void bloblist_get_stats(ulong *basep, ulong *sizep, ulong *allocedp); + +/** + * bloblist_show_stats() - Show information about the bloblist + * + * This shows useful information about the bloblist on the console + */ +void bloblist_show_stats(void); + +/** + * bloblist_show_list() - Show a list of blobs in the bloblist + * + * This shows a list of blobs, showing their address, size and tag. + */ +void bloblist_show_list(void); + +/** + * bloblist_tag_name() - Get the name for a tag + * + * @tag: Tag to check + * @return name of tag, or "invalid" if an invalid tag is provided + */ +const char *bloblist_tag_name(enum bloblist_tag_t tag); + +/** + * bloblist_reloc() - Relocate the bloblist and optionally resize it + * + * @to: Pointer to new bloblist location (must not overlap old location) + * @to:size: New size for bloblist (must be larger than from_size) + * @from: Pointer to bloblist to relocate + * @from_size: Size of bloblist to relocate + */ +void bloblist_reloc(void *to, uint to_size, void *from, uint from_size); + +/** + * bloblist_init() - Init the bloblist system with a single bloblist + * + * This uses CONFIG_BLOBLIST_ADDR and CONFIG_BLOBLIST_SIZE to set up a bloblist + * for use by U-Boot. + */ +int bloblist_init(void); + +#endif /* __BLOBLIST_H */ diff --git a/roms/u-boot/include/bmp_layout.h b/roms/u-boot/include/bmp_layout.h new file mode 100644 index 000000000..a5c9498dc --- /dev/null +++ b/roms/u-boot/include/bmp_layout.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* (C) Copyright 2002 + * Detlev Zundel, DENX Software Engineering, dzu@denx.de. + */ + +/************************************************************************/ +/* ** Layout of a bmp file */ +/************************************************************************/ + +#ifndef _BMP_H_ +#define _BMP_H_ + +struct __packed bmp_color_table_entry { + __u8 blue; + __u8 green; + __u8 red; + __u8 reserved; +}; + +/* When accessing these fields, remember that they are stored in little + endian format, so use linux macros, e.g. le32_to_cpu(width) */ + +struct __packed bmp_header { + /* Header */ + char signature[2]; + __u32 file_size; + __u32 reserved; + __u32 data_offset; + /* InfoHeader */ + __u32 size; + __u32 width; + __u32 height; + __u16 planes; + __u16 bit_count; + __u32 compression; + __u32 image_size; + __u32 x_pixels_per_m; + __u32 y_pixels_per_m; + __u32 colors_used; + __u32 colors_important; + /* ColorTable */ +}; + +struct bmp_image { + struct bmp_header header; + /* We use a zero sized array just as a placeholder for variable + sized array */ + struct bmp_color_table_entry color_table[0]; +}; + +/* Data in the bmp_image is aligned to this length */ +#define BMP_DATA_ALIGN 4 + +/* Constants for the compression field */ +#define BMP_BI_RGB 0 +#define BMP_BI_RLE8 1 +#define BMP_BI_RLE4 2 + +#endif /* _BMP_H_ */ diff --git a/roms/u-boot/include/boot_fit.h b/roms/u-boot/include/boot_fit.h new file mode 100644 index 000000000..f75fed66b --- /dev/null +++ b/roms/u-boot/include/boot_fit.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Texas Instruments + * Written by Franklin Cooper Jr. + */ + +/** + * locate_dtb_in_fit - Find a DTB matching the board in a FIT image + * @fit: pointer to the FIT image + * + * @return a pointer to a matching DTB blob if found, NULL otherwise + */ +void *locate_dtb_in_fit(const void *fit); diff --git a/roms/u-boot/include/bootcount.h b/roms/u-boot/include/bootcount.h new file mode 100644 index 000000000..796b237c8 --- /dev/null +++ b/roms/u-boot/include/bootcount.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + */ +#ifndef _BOOTCOUNT_H__ +#define _BOOTCOUNT_H__ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_DM_BOOTCOUNT + +struct bootcount_ops { + /** + * get() - get the current bootcount value + * + * Returns the current counter value of the bootcount backing + * store. + * + * @dev: Device to read from + * @bootcount: Address to put the current bootcount value + */ + int (*get)(struct udevice *dev, u32 *bootcount); + + /** + * set() - set a bootcount value (e.g. to reset or increment) + * + * Sets the value in the bootcount backing store. + * + * @dev: Device to read from + * @bootcount: New bootcount value to store + */ + int (*set)(struct udevice *dev, const u32 bootcount); +}; + +/* Access the operations for a bootcount device */ +#define bootcount_get_ops(dev) ((struct bootcount_ops *)(dev)->driver->ops) + +/** + * dm_bootcount_get() - Read the current value from a bootcount storage + * + * @dev: Device to read from + * @bootcount: Place to put the current bootcount + * @return 0 if OK, -ve on error + */ +int dm_bootcount_get(struct udevice *dev, u32 *bootcount); + +/** + * dm_bootcount_set() - Write a value to a bootcount storage + * + * @dev: Device to read from + * @bootcount: Value to be written to the backing storage + * @return 0 if OK, -ve on error + */ +int dm_bootcount_set(struct udevice *dev, u32 bootcount); + +#endif + +/** bootcount_store() - store the current bootcount */ +void bootcount_store(ulong); + +/** + * bootcount_load() - load the current bootcount + * + * @return bootcount, read from the appropriate location + */ +ulong bootcount_load(void); + +#if defined(CONFIG_SPL_BOOTCOUNT_LIMIT) || defined(CONFIG_TPL_BOOTCOUNT_LIMIT) || defined(CONFIG_BOOTCOUNT_LIMIT) + +#if !defined(CONFIG_SYS_BOOTCOUNT_LE) && !defined(CONFIG_SYS_BOOTCOUNT_BE) +# if __BYTE_ORDER == __LITTLE_ENDIAN +# define CONFIG_SYS_BOOTCOUNT_LE +# else +# define CONFIG_SYS_BOOTCOUNT_BE +# endif +#endif + +#ifdef CONFIG_SYS_BOOTCOUNT_LE +static inline void raw_bootcount_store(volatile u32 *addr, u32 data) +{ + out_le32(addr, data); +} + +static inline u32 raw_bootcount_load(volatile u32 *addr) +{ + return in_le32(addr); +} +#else +static inline void raw_bootcount_store(volatile u32 *addr, u32 data) +{ + out_be32(addr, data); +} + +static inline u32 raw_bootcount_load(volatile u32 *addr) +{ + return in_be32(addr); +} +#endif + +DECLARE_GLOBAL_DATA_PTR; +static inline int bootcount_error(void) +{ + unsigned long bootcount = bootcount_load(); + unsigned long bootlimit = env_get_ulong("bootlimit", 10, 0); + + if (bootlimit && bootcount > bootlimit) { + printf("Warning: Bootlimit (%lu) exceeded.", bootlimit); + if (!(gd->flags & GD_FLG_SPL_INIT)) + printf(" Using altbootcmd."); + printf("\n"); + + return 1; + } + + return 0; +} + +static inline void bootcount_inc(void) +{ + unsigned long bootcount = bootcount_load(); + + if (gd->flags & GD_FLG_SPL_INIT) { + bootcount_store(++bootcount); + return; + } + +#ifndef CONFIG_SPL_BUILD + /* Only increment bootcount when no bootcount support in SPL */ +#if !defined(CONFIG_SPL_BOOTCOUNT_LIMIT) && !defined(CONFIG_TPL_BOOTCOUNT_LIMIT) + bootcount_store(++bootcount); +#endif + env_set_ulong("bootcount", bootcount); +#endif /* !CONFIG_SPL_BUILD */ +} + +#else +static inline int bootcount_error(void) { return 0; } +static inline void bootcount_inc(void) {} +#endif /* CONFIG_SPL_BOOTCOUNT_LIMIT || CONFIG_TPL_BOOTCOUNT_LIMIT || CONFIG_BOOTCOUNT_LIMIT */ +#endif /* _BOOTCOUNT_H__ */ diff --git a/roms/u-boot/include/bootm.h b/roms/u-boot/include/bootm.h new file mode 100644 index 000000000..7f88ec718 --- /dev/null +++ b/roms/u-boot/include/bootm.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef _BOOTM_H +#define _BOOTM_H + +#include + +struct cmd_tbl; + +#define BOOTM_ERR_RESET (-1) +#define BOOTM_ERR_OVERLAP (-2) +#define BOOTM_ERR_UNIMPLEMENTED (-3) + +/* + * Continue booting an OS image; caller already has: + * - copied image header to global variable `header' + * - checked header magic number, checksums (both header & image), + * - verified image architecture (PPC) and type (KERNEL or MULTI), + * - loaded (first part of) image to header load address, + * - disabled interrupts. + * + * @flag: Flags indicating what to do (BOOTM_STATE_...) + * @argc: Number of arguments. Note that the arguments are shifted down + * so that 0 is the first argument not processed by U-Boot, and + * argc is adjusted accordingly. This avoids confusion as to how + * many arguments are available for the OS. + * @images: Pointers to os/initrd/fdt + * @return 1 on error. On success the OS boots so this function does + * not return. + */ +typedef int boot_os_fn(int flag, int argc, char *const argv[], + bootm_headers_t *images); + +extern boot_os_fn do_bootm_linux; +extern boot_os_fn do_bootm_vxworks; + +int do_bootelf(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +void lynxkdi_boot(image_header_t *hdr); + +boot_os_fn *bootm_os_get_boot_func(int os); + +#if defined(CONFIG_FIT_SIGNATURE) +int bootm_host_load_images(const void *fit, int cfg_noffset); +#endif + +int boot_selected_os(int argc, char *const argv[], int state, + bootm_headers_t *images, boot_os_fn *boot_fn); + +ulong bootm_disable_interrupts(void); + +/* This is a special function used by booti/bootz */ +int bootm_find_images(int flag, int argc, char *const argv[], ulong start, + ulong size); + +int do_bootm_states(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[], int states, bootm_headers_t *images, + int boot_progress); + +void arch_preboot_os(void); + +/* + * boards should define this to disable devices when EFI exits from boot + * services. + * + * TODO(sjg@chromium.org>): Update this to use driver model's device_remove(). + */ +void board_quiesce_devices(void); + +/** + * switch_to_non_secure_mode() - switch to non-secure mode + */ +void switch_to_non_secure_mode(void); + +/* Flags to control bootm_process_cmdline() */ +enum bootm_cmdline_t { + BOOTM_CL_SILENT = 1 << 0, /* Do silent console processing */ + BOOTM_CL_SUBST = 1 << 1, /* Do substitution */ + + BOOTM_CL_ALL = 3, /* All substitutions */ +}; + +/** + * arch_preboot_os() - arch specific configuration before booting + */ +void arch_preboot_os(void); + +/** + * board_preboot_os() - board specific configuration before booting + */ +void board_preboot_os(void); + +/* + * bootm_process_cmdline() - Process fix-ups for the command line + * + * This handles: + * + * - making Linux boot silently if requested ('silent_linux' envvar) + * - performing substitutions in the command line ('bootargs_subst' envvar) + * + * @maxlen must provide enough space for the string being processed plus the + * resulting string + * + * @buf: buffer holding commandline string to adjust + * @maxlen: Maximum length of buffer at @buf (including \0) + * @flags: Flags to control what happens (see bootm_cmdline_t) + * @return 0 if OK, -ENOMEM if out of memory, -ENOSPC if the commandline is too + * long + */ +int bootm_process_cmdline(char *buf, int maxlen, int flags); + +/** + * bootm_process_cmdline_env() - Process fix-ups for the command line + * + * Updates the 'bootargs' envvar as required. This handles: + * + * - making Linux boot silently if requested ('silent_linux' envvar) + * - performing substitutions in the command line ('bootargs_subst' envvar) + * + * @flags: Flags to control what happens (see bootm_cmdline_t) + * @return 0 if OK, -ENOMEM if out of memory + */ +int bootm_process_cmdline_env(int flags); + +#endif diff --git a/roms/u-boot/include/bootretry.h b/roms/u-boot/include/bootretry.h new file mode 100644 index 000000000..0cedd300c --- /dev/null +++ b/roms/u-boot/include/bootretry.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef __BOOTRETRY_H +#define __BOOTRETRY_H + +#ifdef CONFIG_BOOT_RETRY_TIME +/** + * bootretry_tstc_timeout() - ensure we get a keypress before timeout + * + * Check for a keypress repeatedly, resetting the watchdog each time. If a + * keypress is not received within the command timeout, return an error. + * + * @return 0 if a key is received in time, -ETIMEDOUT if not + */ +int bootretry_tstc_timeout(void); + +/** + * bootretry_init_cmd_timeout() - set up command timeout + * + * Get the required command timeout from the environment. + */ +void bootretry_init_cmd_timeout(void); + +/** + * bootretry_reset_cmd_timeout() - reset command timeout + * + * Reset the command timeout so that the user has a fresh start. This is + * typically used when input is received from the user. + */ +void bootretry_reset_cmd_timeout(void); + +/** bootretry_dont_retry() - Indicate that we should not retry the boot */ +void bootretry_dont_retry(void); +#else +static inline int bootretry_tstc_timeout(void) +{ + return 0; +} + +static inline void bootretry_init_cmd_timeout(void) +{ +} + +static inline void bootretry_reset_cmd_timeout(void) +{ +} + +static inline void bootretry_dont_retry(void) +{ +} + +#endif + +#endif diff --git a/roms/u-boot/include/bootstage.h b/roms/u-boot/include/bootstage.h new file mode 100644 index 000000000..00c85fb86 --- /dev/null +++ b/roms/u-boot/include/bootstage.h @@ -0,0 +1,438 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This file implements recording of each stage of the boot process. It is + * intended to implement timing of each stage, reporting this information + * to the user and passing it to the OS for logging / further analysis. + * Note that it requires timer_get_boot_us() to be defined by the board + * + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#ifndef _BOOTSTAGE_H +#define _BOOTSTAGE_H + +/* Flags for each bootstage record */ +enum bootstage_flags { + BOOTSTAGEF_ERROR = 1 << 0, /* Error record */ + BOOTSTAGEF_ALLOC = 1 << 1, /* Allocate an id */ +}; + +/* bootstate sub-IDs used for kernel and ramdisk ranges */ +enum { + BOOTSTAGE_SUB_FORMAT, + BOOTSTAGE_SUB_FORMAT_OK, + BOOTSTAGE_SUB_NO_UNIT_NAME, + BOOTSTAGE_SUB_UNIT_NAME, + BOOTSTAGE_SUB_SUBNODE, + + BOOTSTAGE_SUB_CHECK, + BOOTSTAGE_SUB_HASH = 5, + BOOTSTAGE_SUB_CHECK_ARCH = 5, + BOOTSTAGE_SUB_CHECK_ALL, + BOOTSTAGE_SUB_GET_DATA, + BOOTSTAGE_SUB_CHECK_ALL_OK = 7, + BOOTSTAGE_SUB_GET_DATA_OK, + BOOTSTAGE_SUB_LOAD, +}; + +/* + * A list of boot stages that we know about. Each of these indicates the + * state that we are at, and the action that we are about to perform. For + * errors, we issue an error for an item when it fails. Therefore the + * normal sequence is: + * + * progress action1 + * progress action2 + * progress action3 + * + * and an error condition where action 3 failed would be: + * + * progress action1 + * progress action2 + * progress action3 + * error on action3 + */ +enum bootstage_id { + BOOTSTAGE_ID_START = 0, + BOOTSTAGE_ID_CHECK_MAGIC, /* Checking image magic */ + BOOTSTAGE_ID_CHECK_HEADER, /* Checking image header */ + BOOTSTAGE_ID_CHECK_CHECKSUM, /* Checking image checksum */ + BOOTSTAGE_ID_CHECK_ARCH, /* Checking architecture */ + + BOOTSTAGE_ID_CHECK_IMAGETYPE = 5,/* Checking image type */ + BOOTSTAGE_ID_DECOMP_IMAGE, /* Decompressing image */ + BOOTSTAGE_ID_KERNEL_LOADED, /* Kernel has been loaded */ + BOOTSTAGE_ID_DECOMP_UNIMPL = 7, /* Odd decompression algorithm */ + BOOTSTAGE_ID_CHECK_BOOT_OS, /* Calling OS-specific boot function */ + BOOTSTAGE_ID_BOOT_OS_RETURNED, /* Tried to boot OS, but it returned */ + BOOTSTAGE_ID_CHECK_RAMDISK = 9, /* Checking ram disk */ + + BOOTSTAGE_ID_RD_MAGIC, /* Checking ram disk magic */ + BOOTSTAGE_ID_RD_HDR_CHECKSUM, /* Checking ram disk heder checksum */ + BOOTSTAGE_ID_RD_CHECKSUM, /* Checking ram disk checksum */ + BOOTSTAGE_ID_COPY_RAMDISK = 12, /* Copying ram disk into place */ + BOOTSTAGE_ID_RAMDISK, /* Checking for valid ramdisk */ + BOOTSTAGE_ID_NO_RAMDISK, /* No ram disk found (not an error) */ + + BOOTSTAGE_ID_RUN_OS = 15, /* Exiting U-Boot, entering OS */ + + BOOTSTAGE_ID_NEED_RESET = 30, + BOOTSTAGE_ID_POST_FAIL, /* Post failure */ + BOOTSTAGE_ID_POST_FAIL_R, /* Post failure reported after reloc */ + + /* + * This set is reported only by x86, and the meaning is different. In + * this case we are reporting completion of a particular stage. + * This should probably change in the x86 code (which doesn't report + * errors in any case), but discussion this can perhaps wait until we + * have a generic board implementation. + */ + BOOTSTAGE_ID_BOARD_INIT_R, /* We have relocated */ + BOOTSTAGE_ID_BOARD_GLOBAL_DATA, /* Global data is set up */ + + BOOTSTAGE_ID_BOARD_INIT_SEQ, /* We completed the init sequence */ + BOOTSTAGE_ID_BOARD_FLASH, /* We have configured flash banks */ + BOOTSTAGE_ID_BOARD_FLASH_37, /* In case you didn't hear... */ + BOOTSTAGE_ID_BOARD_ENV, /* Environment is relocated & ready */ + BOOTSTAGE_ID_BOARD_PCI, /* PCI is up */ + + BOOTSTAGE_ID_BOARD_INTERRUPTS, /* Exceptions / interrupts ready */ + BOOTSTAGE_ID_BOARD_DONE, /* Board init done, off to main loop */ + /* ^^^ here ends the x86 sequence */ + + /* Boot stages related to loading a kernel from an IDE device */ + BOOTSTAGE_ID_IDE_START = 41, + BOOTSTAGE_ID_IDE_ADDR, + BOOTSTAGE_ID_IDE_BOOT_DEVICE, + BOOTSTAGE_ID_IDE_TYPE, + + BOOTSTAGE_ID_IDE_PART, + BOOTSTAGE_ID_IDE_PART_INFO, + BOOTSTAGE_ID_IDE_PART_TYPE, + BOOTSTAGE_ID_IDE_PART_READ, + BOOTSTAGE_ID_IDE_FORMAT, + + BOOTSTAGE_ID_IDE_CHECKSUM, /* 50 */ + BOOTSTAGE_ID_IDE_READ, + + /* Boot stages related to loading a kernel from an NAND device */ + BOOTSTAGE_ID_NAND_PART, + BOOTSTAGE_ID_NAND_SUFFIX, + BOOTSTAGE_ID_NAND_BOOT_DEVICE, + BOOTSTAGE_ID_NAND_HDR_READ = 55, + BOOTSTAGE_ID_NAND_AVAILABLE = 55, + BOOTSTAGE_ID_NAND_TYPE = 57, + BOOTSTAGE_ID_NAND_READ, + + /* Boot stages related to loading a kernel from an network device */ + BOOTSTAGE_ID_NET_CHECKSUM = 60, + BOOTSTAGE_ID_NET_ETH_START = 64, + BOOTSTAGE_ID_NET_ETH_INIT, + + BOOTSTAGE_ID_NET_START = 80, + BOOTSTAGE_ID_NET_NETLOOP_OK, + BOOTSTAGE_ID_NET_LOADED, + BOOTSTAGE_ID_NET_DONE_ERR, + BOOTSTAGE_ID_NET_DONE, + + BOOTSTAGE_ID_FIT_FDT_START = 90, + /* + * Boot stages related to loading a FIT image. Some of these are a + * bit wonky. + */ + BOOTSTAGE_ID_FIT_KERNEL_START = 100, + + BOOTSTAGE_ID_FIT_CONFIG = 110, + BOOTSTAGE_ID_FIT_TYPE, + BOOTSTAGE_ID_FIT_KERNEL_INFO, + + BOOTSTAGE_ID_FIT_COMPRESSION, + BOOTSTAGE_ID_FIT_OS, + BOOTSTAGE_ID_FIT_LOADADDR, + BOOTSTAGE_ID_OVERWRITTEN, + + /* Next 10 IDs used by BOOTSTAGE_SUB_... */ + BOOTSTAGE_ID_FIT_RD_START = 120, /* Ramdisk stages */ + + /* Next 10 IDs used by BOOTSTAGE_SUB_... */ + BOOTSTAGE_ID_FIT_SETUP_START = 130, /* x86 setup stages */ + + BOOTSTAGE_ID_IDE_FIT_READ = 140, + BOOTSTAGE_ID_IDE_FIT_READ_OK, + + BOOTSTAGE_ID_NAND_FIT_READ = 150, + BOOTSTAGE_ID_NAND_FIT_READ_OK, + + BOOTSTAGE_ID_FIT_LOADABLE_START = 160, /* for Loadable Images */ + /* + * These boot stages are new, higher level, and not directly related + * to the old boot progress numbers. They are useful for recording + * rough boot timing information. + */ + BOOTSTAGE_ID_AWAKE, + BOOTSTAGE_ID_START_TPL, + BOOTSTAGE_ID_END_TPL, + BOOTSTAGE_ID_START_SPL, + BOOTSTAGE_ID_END_SPL, + BOOTSTAGE_ID_START_UBOOT_F, + BOOTSTAGE_ID_START_UBOOT_R, + BOOTSTAGE_ID_USB_START, + BOOTSTAGE_ID_ETH_START, + BOOTSTAGE_ID_BOOTP_START, + BOOTSTAGE_ID_BOOTP_STOP, + BOOTSTAGE_ID_BOOTM_START, + BOOTSTAGE_ID_BOOTM_HANDOFF, + BOOTSTAGE_ID_MAIN_LOOP, + BOOTSTAGE_ID_ENTER_CLI_LOOP, + BOOTSTAGE_KERNELREAD_START, + BOOTSTAGE_KERNELREAD_STOP, + BOOTSTAGE_ID_BOARD_INIT, + BOOTSTAGE_ID_BOARD_INIT_DONE, + + BOOTSTAGE_ID_CPU_AWAKE, + BOOTSTAGE_ID_MAIN_CPU_AWAKE, + BOOTSTAGE_ID_MAIN_CPU_READY, + + BOOTSTAGE_ID_ACCUM_LCD, + BOOTSTAGE_ID_ACCUM_SCSI, + BOOTSTAGE_ID_ACCUM_SPI, + BOOTSTAGE_ID_ACCUM_DECOMP, + BOOTSTAGE_ID_ACCUM_OF_LIVE, + BOOTSTAGE_ID_FPGA_INIT, + BOOTSTAGE_ID_ACCUM_DM_SPL, + BOOTSTAGE_ID_ACCUM_DM_F, + BOOTSTAGE_ID_ACCUM_DM_R, + BOOTSTAGE_ID_ACCUM_FSP_M, + BOOTSTAGE_ID_ACCUM_FSP_S, + BOOTSTAGE_ID_ACCUM_MMAP_SPI, + + /* a few spare for the user, from here */ + BOOTSTAGE_ID_USER, + BOOTSTAGE_ID_ALLOC, +}; + +/* + * Return the time since boot in microseconds, This is needed for bootstage + * and should be defined in CPU- or board-specific code. If undefined then + * you will get a link error. + */ +ulong timer_get_boot_us(void); + +#if defined(USE_HOSTCC) +#define show_boot_progress(val) do {} while (0) +#else +/** + * Board code can implement show_boot_progress() if needed. + * + * @param val Progress state (enum bootstage_id), or -id if an error + * has occurred. + */ +void show_boot_progress(int val); +#endif + +#if !defined(USE_HOSTCC) +#if CONFIG_IS_ENABLED(BOOTSTAGE) +#define ENABLE_BOOTSTAGE +#endif +#endif + +#ifdef ENABLE_BOOTSTAGE + +/* This is the full bootstage implementation */ + +/** + * Relocate existing bootstage records + * + * Call this after relocation has happened and after malloc has been initted. + * We need to copy any pointers in bootstage records that were added pre- + * relocation, since memory can be overwritten later. + * @return Always returns 0, to indicate success + */ +int bootstage_relocate(void); + +/** + * Add a new bootstage record + * + * @param id Bootstage ID to use (ignored if flags & BOOTSTAGEF_ALLOC) + * @param name Name of record, or NULL for none + * @param flags Flags (BOOTSTAGEF_...) + * @param mark Time to record in this record, in microseconds + */ +ulong bootstage_add_record(enum bootstage_id id, const char *name, + int flags, ulong mark); + +/** + * Mark a time stamp for the current boot stage. + */ +ulong bootstage_mark(enum bootstage_id id); + +ulong bootstage_error(enum bootstage_id id); + +ulong bootstage_mark_name(enum bootstage_id id, const char *name); + +/** + * Mark a time stamp in the given function and line number + * + * See BOOTSTAGE_MARKER() for a convenient macro. + * + * @param file Filename to record (NULL if none) + * @param func Function name to record + * @param linenum Line number to record + * @return recorded time stamp + */ +ulong bootstage_mark_code(const char *file, const char *func, + int linenum); + +/** + * Mark the start of a bootstage activity. The end will be marked later with + * bootstage_accum() and at that point we accumulate the time taken. Calling + * this function turns the given id into a accumulator rather than and + * absolute mark in time. Accumulators record the total amount of time spent + * in an activty during boot. + * + * @param id Bootstage id to record this timestamp against + * @param name Textual name to display for this id in the report (maybe NULL) + * @return start timestamp in microseconds + */ +uint32_t bootstage_start(enum bootstage_id id, const char *name); + +/** + * Mark the end of a bootstage activity + * + * After previously marking the start of an activity with bootstage_start(), + * call this function to mark the end. You can call these functions in pairs + * as many times as you like. + * + * @param id Bootstage id to record this timestamp against + * @return time spent in this iteration of the activity (i.e. the time now + * less the start time recorded in the last bootstage_start() call + * with this id. + */ +uint32_t bootstage_accum(enum bootstage_id id); + +/* Print a report about boot time */ +void bootstage_report(void); + +/** + * Add bootstage information to the device tree + * + * @return 0 if ok, -ve on error + */ +int bootstage_fdt_add_report(void); + +/** + * Stash bootstage data into memory + * + * @param base Base address of memory buffer + * @param size Size of memory buffer + * @return 0 if stashed ok, -1 if out of space + */ +int bootstage_stash(void *base, int size); + +/** + * Read bootstage data from memory + * + * Bootstage data is read from memory and placed in the bootstage table + * in the user records. + * + * @param base Base address of memory buffer + * @param size Size of memory buffer (-1 if unknown) + * @return 0 if unstashed ok, -ENOENT if bootstage info not found, -ENOSPC if + * there is not space for read the stashed data, or other error if + * something else went wrong + */ +int bootstage_unstash(const void *base, int size); + +/** + * bootstage_get_size() - Get the size of the bootstage data + * + * @return size of boostage data in bytes + */ +int bootstage_get_size(void); + +/** + * bootstage_init() - Prepare bootstage for use + * + * @first: true if this is the first time bootstage is set up. This causes it + * to add a 'reset' record with a time of 0. + */ +int bootstage_init(bool first); + +#else +static inline ulong bootstage_add_record(enum bootstage_id id, + const char *name, int flags, ulong mark) +{ + return 0; +} + +/* + * This is a dummy implementation which just calls show_boot_progress(), + * and won't even do that unless CONFIG_SHOW_BOOT_PROGRESS is defined + */ + +static inline int bootstage_relocate(void) +{ + return 0; +} + +static inline ulong bootstage_mark(enum bootstage_id id) +{ + show_boot_progress(id); + return 0; +} + +static inline ulong bootstage_error(enum bootstage_id id) +{ + show_boot_progress(-id); + return 0; +} + +static inline ulong bootstage_mark_name(enum bootstage_id id, const char *name) +{ + show_boot_progress(id); + return 0; +} + +static inline ulong bootstage_mark_code(const char *file, const char *func, + int linenum) +{ + return 0; +} + +static inline uint32_t bootstage_start(enum bootstage_id id, const char *name) +{ + return 0; +} + +static inline uint32_t bootstage_accum(enum bootstage_id id) +{ + return 0; +} + +static inline int bootstage_stash(void *base, int size) +{ + return 0; /* Pretend to succeed */ +} + +static inline int bootstage_unstash(const void *base, int size) +{ + return 0; /* Pretend to succeed */ +} + +static inline int bootstage_get_size(void) +{ + return 0; +} + +static inline int bootstage_init(bool first) +{ + return 0; +} + +#endif /* ENABLE_BOOTSTAGE */ + +/* Helper macro for adding a bootstage to a line of code */ +#define BOOTSTAGE_MARKER() \ + bootstage_mark_code(__FILE__, __func__, __LINE__) + +#endif diff --git a/roms/u-boot/include/bouncebuf.h b/roms/u-boot/include/bouncebuf.h new file mode 100644 index 000000000..7427bd12e --- /dev/null +++ b/roms/u-boot/include/bouncebuf.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Generic bounce buffer implementation + * + * Copyright (C) 2012 Marek Vasut + */ + +#ifndef __INCLUDE_BOUNCEBUF_H__ +#define __INCLUDE_BOUNCEBUF_H__ + +#include + +/* + * GEN_BB_READ -- Data are read from the buffer eg. by DMA hardware. + * The source buffer is copied into the bounce buffer (if unaligned, otherwise + * the source buffer is used directly) upon start() call, then the operation + * requiring the aligned transfer happens, then the bounce buffer is lost upon + * stop() call. + */ +#define GEN_BB_READ (1 << 0) +/* + * GEN_BB_WRITE -- Data are written into the buffer eg. by DMA hardware. + * The source buffer starts in an undefined state upon start() call, then the + * operation requiring the aligned transfer happens, then the bounce buffer is + * copied into the destination buffer (if unaligned, otherwise destination + * buffer is used directly) upon stop() call. + */ +#define GEN_BB_WRITE (1 << 1) +/* + * GEN_BB_RW -- Data are read and written into the buffer eg. by DMA hardware. + * The source buffer is copied into the bounce buffer (if unaligned, otherwise + * the source buffer is used directly) upon start() call, then the operation + * requiring the aligned transfer happens, then the bounce buffer is copied + * into the destination buffer (if unaligned, otherwise destination buffer is + * used directly) upon stop() call. + */ +#define GEN_BB_RW (GEN_BB_READ | GEN_BB_WRITE) + +struct bounce_buffer { + /* Copy of data parameter passed to start() */ + void *user_buffer; + /* + * DMA-aligned buffer. This field is always set to the value that + * should be used for DMA; either equal to .user_buffer, or to a + * freshly allocated aligned buffer. + */ + void *bounce_buffer; + /* Copy of len parameter passed to start() */ + size_t len; + /* DMA-aligned buffer length */ + size_t len_aligned; + /* Copy of flags parameter passed to start() */ + unsigned int flags; +}; + +/** + * bounce_buffer_start() -- Start the bounce buffer session + * state: stores state passed between bounce_buffer_{start,stop} + * data: pointer to buffer to be aligned + * len: length of the buffer + * flags: flags describing the transaction, see above. + */ +int bounce_buffer_start(struct bounce_buffer *state, void *data, + size_t len, unsigned int flags); + +/** + * bounce_buffer_start() -- Start the bounce buffer session with external align check function + * state: stores state passed between bounce_buffer_{start,stop} + * data: pointer to buffer to be aligned + * len: length of the buffer + * flags: flags describing the transaction, see above. + * alignment: alignment of the newly allocated bounce buffer + * addr_is_aligned: function for checking the alignment instead of the default one + */ +int bounce_buffer_start_extalign(struct bounce_buffer *state, void *data, + size_t len, unsigned int flags, + size_t alignment, + int (*addr_is_aligned)(struct bounce_buffer *state)); + +/** + * bounce_buffer_stop() -- Finish the bounce buffer session + * state: stores state passed between bounce_buffer_{start,stop} + */ +int bounce_buffer_stop(struct bounce_buffer *state); + +#endif diff --git a/roms/u-boot/include/broadcom/chimp.h b/roms/u-boot/include/broadcom/chimp.h new file mode 100644 index 000000000..738f73eef --- /dev/null +++ b/roms/u-boot/include/broadcom/chimp.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Broadcom. + * + */ + +#ifndef __CHIMP_H__ +#define __CHIMP_H__ + +#include + +/* + * Chimp binary has health status like initialization complete, + * crash or running fine + */ +#define BCM_CHIMP_RUNNIG_GOOD 0x8000 + +enum { + CHIMP_HANDSHAKE_SUCCESS = 0, + CHIMP_HANDSHAKE_WAIT_ERROR, + CHIMP_HANDSHAKE_WAIT_TIMEOUT, +}; + +/** + * chimp_fastboot_optee() - api to load bnxt firmware + * + * @return: 0 on success and -ve on failure + */ +int chimp_fastboot_optee(void); + +/** + * chimp_health_status_optee() - get chimp health status + * + * Chimp health status could be firmware is in good condition or + * bad condition because of crash/hang. + * + * @status: pointer to get chimp health status + * + * @return: 0 on success and -ve on failure + */ +int chimp_health_status_optee(u32 *status); + +/** + * chimp_handshake_status_optee() - get chimp handshake status. + * + * To know firmware is loaded and running. + * + * @timeout: timeout value, if 0 then default timeout is considered by op-tee + * @hstatus: pointer to chimp handshake status + * + * @return: 0 on success and -ve on failure + */ +int chimp_handshake_status_optee(u32 timeout, u32 *hstatus); + +#endif diff --git a/roms/u-boot/include/btrfs.h b/roms/u-boot/include/btrfs.h new file mode 100644 index 000000000..a7605e158 --- /dev/null +++ b/roms/u-boot/include/btrfs.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * BTRFS filesystem implementation for U-Boot + * + * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz + */ + +#ifndef __U_BOOT_BTRFS_H__ +#define __U_BOOT_BTRFS_H__ + +struct blk_desc; +struct disk_partition; + +int btrfs_probe(struct blk_desc *fs_dev_desc, + struct disk_partition *fs_partition); +int btrfs_ls(const char *); +int btrfs_exists(const char *); +int btrfs_size(const char *, loff_t *); +int btrfs_read(const char *, void *, loff_t, loff_t, loff_t *); +void btrfs_close(void); +int btrfs_uuid(char *); +void btrfs_list_subvols(void); + +#endif /* __U_BOOT_BTRFS_H__ */ diff --git a/roms/u-boot/include/bus_vcxk.h b/roms/u-boot/include/bus_vcxk.h new file mode 100644 index 000000000..eecba407b --- /dev/null +++ b/roms/u-boot/include/bus_vcxk.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2005-2009 + * Jens Scharsig @ BuS Elektronik GmbH & Co. KG, + */ + +#ifndef __BUS_VCXK_H_ +#define __BUS_VCXK_H_ + +extern int vcxk_init(unsigned long width, unsigned long height); +extern void vcxk_setpixel(int x, int y, unsigned long color); +extern int vcxk_acknowledge_wait(void); +extern int vcxk_request(void); +extern void vcxk_loadimage(ulong source); +extern int vcxk_display_bitmap(ulong addr, int x, int y); +extern void vcxk_setbrightness(unsigned int side, short brightness); +extern int video_display_bitmap(ulong addr, int x, int y); + +#endif diff --git a/roms/u-boot/include/button.h b/roms/u-boot/include/button.h new file mode 100644 index 000000000..ee14fadf0 --- /dev/null +++ b/roms/u-boot/include/button.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Philippe Reynes + */ + +#ifndef __BUTTON_H +#define __BUTTON_H + +struct udevice; + +/** + * struct button_uc_plat - Platform data the uclass stores about each device + * + * @label: Button label + */ +struct button_uc_plat { + const char *label; +}; + +/** + * enum button_state_t - State used for button + * - BUTTON_OFF - Button is not pressed + * - BUTTON_ON - Button is pressed + * - BUTTON_COUNT - Number of button state + */ +enum button_state_t { + BUTTON_OFF = 0, + BUTTON_ON = 1, + BUTTON_COUNT, +}; + +struct button_ops { + /** + * get_state() - get the state of a button + * + * @dev: button device to change + * @return button state button_state_t, or -ve on error + */ + enum button_state_t (*get_state)(struct udevice *dev); +}; + +#define button_get_ops(dev) ((struct button_ops *)(dev)->driver->ops) + +/** + * button_get_by_label() - Find a button device by label + * + * @label: button label to look up + * @devp: Returns the associated device, if found + * @return 0 if found, -ENODEV if not found, other -ve on error + */ +int button_get_by_label(const char *label, struct udevice **devp); + +/** + * button_get_state() - get the state of a button + * + * @dev: button device to change + * @return button state button_state_t, or -ve on error + */ +enum button_state_t button_get_state(struct udevice *dev); + +#endif diff --git a/roms/u-boot/include/bzlib.h b/roms/u-boot/include/bzlib.h new file mode 100644 index 000000000..19314f8f6 --- /dev/null +++ b/roms/u-boot/include/bzlib.h @@ -0,0 +1,332 @@ +/* + * This file is a modified version of bzlib.h from the bzip2-1.0.2 + * distribution which can be found at http://sources.redhat.com/bzip2/ + */ + +/*-------------------------------------------------------------*/ +/*--- Public header file for the library. ---*/ +/*--- bzlib.h ---*/ +/*-------------------------------------------------------------*/ + +/*-- + This file is a part of bzip2 and/or libbzip2, a program and + library for lossless, block-sorting data compression. + + Copyright (C) 1996-2002 Julian R Seward. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. The origin of this software must not be misrepresented; you must + not claim that you wrote the original software. If you use this + software in a product, an acknowledgment in the product + documentation would be appreciated but is not required. + + 3. Altered source versions must be plainly marked as such, and must + not be misrepresented as being the original software. + + 4. The name of the author may not be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + Julian Seward, Cambridge, UK. + jseward@acm.org + bzip2/libbzip2 version 1.0 of 21 March 2000 + + This program is based on (at least) the work of: + Mike Burrows + David Wheeler + Peter Fenwick + Alistair Moffat + Radford Neal + Ian H. Witten + Robert Sedgewick + Jon L. Bentley + + For more information on these sources, see the manual. +--*/ + + +#ifndef _BZLIB_H +#define _BZLIB_H + +/* Configure for U-Boot environment */ +#define BZ_NO_STDIO + +#ifndef CONFIG_SANDBOX +#define BZ_NO_COMPRESS +#endif +/* End of configuration for U-Boot environment */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define BZ_RUN 0 +#define BZ_FLUSH 1 +#define BZ_FINISH 2 + +#define BZ_OK 0 +#define BZ_RUN_OK 1 +#define BZ_FLUSH_OK 2 +#define BZ_FINISH_OK 3 +#define BZ_STREAM_END 4 +#define BZ_SEQUENCE_ERROR (-1) +#define BZ_PARAM_ERROR (-2) +#define BZ_MEM_ERROR (-3) +#define BZ_DATA_ERROR (-4) +#define BZ_DATA_ERROR_MAGIC (-5) +#define BZ_IO_ERROR (-6) +#define BZ_UNEXPECTED_EOF (-7) +#define BZ_OUTBUFF_FULL (-8) +#define BZ_CONFIG_ERROR (-9) + +typedef + struct { + char *next_in; + unsigned int avail_in; + unsigned int total_in_lo32; + unsigned int total_in_hi32; + + char *next_out; + unsigned int avail_out; + unsigned int total_out_lo32; + unsigned int total_out_hi32; + + void *state; + + void *(*bzalloc)(void *,int,int); + void (*bzfree)(void *,void *); + void *opaque; + } + bz_stream; + + +#ifndef BZ_IMPORT +#define BZ_EXPORT +#endif + +#ifdef _WIN32 +# include +# ifdef small + /* windows.h define small to char */ +# undef small +# endif +# ifdef BZ_EXPORT +# define BZ_API(func) WINAPI func +# define BZ_EXTERN extern +# else + /* import windows dll dynamically */ +# define BZ_API(func) (WINAPI * func) +# define BZ_EXTERN +# endif +#else +# define BZ_API(func) func +# define BZ_EXTERN extern +#endif + + +/*-- Core (low-level) library functions --*/ + +BZ_EXTERN int BZ_API(BZ2_bzCompressInit) ( + bz_stream* strm, + int blockSize100k, + int verbosity, + int workFactor + ); + +BZ_EXTERN int BZ_API(BZ2_bzCompress) ( + bz_stream* strm, + int action + ); + +BZ_EXTERN int BZ_API(BZ2_bzCompressEnd) ( + bz_stream* strm + ); + +BZ_EXTERN int BZ_API(BZ2_bzDecompressInit) ( + bz_stream *strm, + int verbosity, + int small + ); + +BZ_EXTERN int BZ_API(BZ2_bzDecompress) ( + bz_stream* strm + ); + +BZ_EXTERN int BZ_API(BZ2_bzDecompressEnd) ( + bz_stream *strm + ); + + +/*-- High(er) level library functions --*/ + +#ifndef BZ_NO_STDIO +#define BZ_MAX_UNUSED 5000 + +/* Need a definitition for FILE */ +#include + +typedef void BZFILE; + +BZ_EXTERN BZFILE* BZ_API(BZ2_bzReadOpen) ( + int* bzerror, + FILE* f, + int verbosity, + int small, + void* unused, + int nUnused + ); + +BZ_EXTERN void BZ_API(BZ2_bzReadClose) ( + int* bzerror, + BZFILE* b + ); + +BZ_EXTERN void BZ_API(BZ2_bzReadGetUnused) ( + int* bzerror, + BZFILE* b, + void** unused, + int* nUnused + ); + +BZ_EXTERN int BZ_API(BZ2_bzRead) ( + int* bzerror, + BZFILE* b, + void* buf, + int len + ); + +BZ_EXTERN BZFILE* BZ_API(BZ2_bzWriteOpen) ( + int* bzerror, + FILE* f, + int blockSize100k, + int verbosity, + int workFactor + ); + +BZ_EXTERN void BZ_API(BZ2_bzWrite) ( + int* bzerror, + BZFILE* b, + void* buf, + int len + ); + +BZ_EXTERN void BZ_API(BZ2_bzWriteClose) ( + int* bzerror, + BZFILE* b, + int abandon, + unsigned int* nbytes_in, + unsigned int* nbytes_out + ); + +BZ_EXTERN void BZ_API(BZ2_bzWriteClose64) ( + int* bzerror, + BZFILE* b, + int abandon, + unsigned int* nbytes_in_lo32, + unsigned int* nbytes_in_hi32, + unsigned int* nbytes_out_lo32, + unsigned int* nbytes_out_hi32 + ); +#endif + + +/*-- Utility functions --*/ + +BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffCompress) ( + char* dest, + unsigned int* destLen, + char* source, + unsigned int sourceLen, + int blockSize100k, + int verbosity, + int workFactor + ); + +BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffDecompress) ( + char* dest, + unsigned int* destLen, + char* source, + unsigned int sourceLen, + int small, + int verbosity + ); + + +/*-- + Code contributed by Yoshioka Tsuneo + (QWF00133@niftyserve.or.jp/tsuneo-y@is.aist-nara.ac.jp), + to support better zlib compatibility. + This code is not _officially_ part of libbzip2 (yet); + I haven't tested it, documented it, or considered the + threading-safeness of it. + If this code breaks, please contact both Yoshioka and me. +--*/ + +BZ_EXTERN const char * BZ_API(BZ2_bzlibVersion) ( + void + ); + +#ifndef BZ_NO_STDIO +BZ_EXTERN BZFILE * BZ_API(BZ2_bzopen) ( + const char *path, + const char *mode + ); + +BZ_EXTERN BZFILE * BZ_API(BZ2_bzdopen) ( + int fd, + const char *mode + ); + +BZ_EXTERN int BZ_API(BZ2_bzread) ( + BZFILE* b, + void* buf, + int len + ); + +BZ_EXTERN int BZ_API(BZ2_bzwrite) ( + BZFILE* b, + void* buf, + int len + ); + +BZ_EXTERN int BZ_API(BZ2_bzflush) ( + BZFILE* b + ); + +BZ_EXTERN void BZ_API(BZ2_bzclose) ( + BZFILE* b + ); + +BZ_EXTERN const char * BZ_API(BZ2_bzerror) ( + BZFILE *b, + int *errnum + ); +#endif + +#ifdef __cplusplus +} +#endif + +#endif + +/*-------------------------------------------------------------*/ +/*--- end bzlib.h ---*/ +/*-------------------------------------------------------------*/ diff --git a/roms/u-boot/include/cache.h b/roms/u-boot/include/cache.h new file mode 100644 index 000000000..ecb7956ef --- /dev/null +++ b/roms/u-boot/include/cache.h @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation + */ + +#ifndef __CACHE_H +#define __CACHE_H + +struct udevice; + +/* + * Structure for the cache controller + */ +struct cache_info { + phys_addr_t base; /* Base physical address of cache device. */ +}; + +struct cache_ops { + /** + * get_info() - Get basic cache info + * + * @dev: Device to check (UCLASS_CACHE) + * @info: Place to put info + * @return 0 if OK, -ve on error + */ + int (*get_info)(struct udevice *dev, struct cache_info *info); + + /** + * enable() - Enable cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ + int (*enable)(struct udevice *dev); + + /** + * disable() - Flush and disable cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ + int (*disable)(struct udevice *dev); +}; + +#define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops) + +/** + * cache_get_info() - Get information about a cache controller + * + * @dev: Device to check (UCLASS_CACHE) + * @info: Returns cache info + * @return 0 if OK, -ve on error + */ +int cache_get_info(struct udevice *dev, struct cache_info *info); + +/** + * cache_enable() - Enable cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ +int cache_enable(struct udevice *dev); + +/** + * cache_disable() - Flush and disable cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ +int cache_disable(struct udevice *dev); +#endif diff --git a/roms/u-boot/include/capitalization.h b/roms/u-boot/include/capitalization.h new file mode 100644 index 000000000..9d7e8d259 --- /dev/null +++ b/roms/u-boot/include/capitalization.h @@ -0,0 +1,2028 @@ +/* SPDX-License-Identifier: Unicode-DFS-2016 */ +/* + * Capitalization tables + */ + +struct capitalization_table { + u16 upper; + u16 lower; +}; + +/* + * Correspondence table for small and capital Unicode letters in the range of + * 0x0000 - 0xffff based on http://www.unicode.org/Public/UCA/11.0.0/allkeys.txt + */ +#define UNICODE_CAPITALIZATION_TABLE { \ + { 0x0531, /* ARMENIAN CAPITAL LETTER AYB */ \ + 0x0561, /* ARMENIAN SMALL LETTER AYB */ }, \ + { 0x0532, /* ARMENIAN CAPITAL LETTER BEN */ \ + 0x0562, /* ARMENIAN SMALL LETTER BEN */ }, \ + { 0x053E, /* ARMENIAN CAPITAL LETTER CA */ \ + 0x056E, /* ARMENIAN SMALL LETTER CA */ }, \ + { 0x0549, /* ARMENIAN CAPITAL LETTER CHA */ \ + 0x0579, /* ARMENIAN SMALL LETTER CHA */ }, \ + { 0x0543, /* ARMENIAN CAPITAL LETTER CHEH */ \ + 0x0573, /* ARMENIAN SMALL LETTER CHEH */ }, \ + { 0x0551, /* ARMENIAN CAPITAL LETTER CO */ \ + 0x0581, /* ARMENIAN SMALL LETTER CO */ }, \ + { 0x0534, /* ARMENIAN CAPITAL LETTER DA */ \ + 0x0564, /* ARMENIAN SMALL LETTER DA */ }, \ + { 0x0535, /* ARMENIAN CAPITAL LETTER ECH */ \ + 0x0565, /* ARMENIAN SMALL LETTER ECH */ }, \ + { 0x0537, /* ARMENIAN CAPITAL LETTER EH */ \ + 0x0567, /* ARMENIAN SMALL LETTER EH */ }, \ + { 0x0538, /* ARMENIAN CAPITAL LETTER ET */ \ + 0x0568, /* ARMENIAN SMALL LETTER ET */ }, \ + { 0x0556, /* ARMENIAN CAPITAL LETTER FEH */ \ + 0x0586, /* ARMENIAN SMALL LETTER FEH */ }, \ + { 0x0542, /* ARMENIAN CAPITAL LETTER GHAD */ \ + 0x0572, /* ARMENIAN SMALL LETTER GHAD */ }, \ + { 0x0533, /* ARMENIAN CAPITAL LETTER GIM */ \ + 0x0563, /* ARMENIAN SMALL LETTER GIM */ }, \ + { 0x0540, /* ARMENIAN CAPITAL LETTER HO */ \ + 0x0570, /* ARMENIAN SMALL LETTER HO */ }, \ + { 0x053B, /* ARMENIAN CAPITAL LETTER INI */ \ + 0x056B, /* ARMENIAN SMALL LETTER INI */ }, \ + { 0x0541, /* ARMENIAN CAPITAL LETTER JA */ \ + 0x0571, /* ARMENIAN SMALL LETTER JA */ }, \ + { 0x054B, /* ARMENIAN CAPITAL LETTER JHEH */ \ + 0x057B, /* ARMENIAN SMALL LETTER JHEH */ }, \ + { 0x0554, /* ARMENIAN CAPITAL LETTER KEH */ \ + 0x0584, /* ARMENIAN SMALL LETTER KEH */ }, \ + { 0x053F, /* ARMENIAN CAPITAL LETTER KEN */ \ + 0x056F, /* ARMENIAN SMALL LETTER KEN */ }, \ + { 0x053C, /* ARMENIAN CAPITAL LETTER LIWN */ \ + 0x056C, /* ARMENIAN SMALL LETTER LIWN */ }, \ + { 0x0544, /* ARMENIAN CAPITAL LETTER MEN */ \ + 0x0574, /* ARMENIAN SMALL LETTER MEN */ }, \ + { 0x0546, /* ARMENIAN CAPITAL LETTER NOW */ \ + 0x0576, /* ARMENIAN SMALL LETTER NOW */ }, \ + { 0x0555, /* ARMENIAN CAPITAL LETTER OH */ \ + 0x0585, /* ARMENIAN SMALL LETTER OH */ }, \ + { 0x054A, /* ARMENIAN CAPITAL LETTER PEH */ \ + 0x057A, /* ARMENIAN SMALL LETTER PEH */ }, \ + { 0x0553, /* ARMENIAN CAPITAL LETTER PIWR */ \ + 0x0583, /* ARMENIAN SMALL LETTER PIWR */ }, \ + { 0x054C, /* ARMENIAN CAPITAL LETTER RA */ \ + 0x057C, /* ARMENIAN SMALL LETTER RA */ }, \ + { 0x0550, /* ARMENIAN CAPITAL LETTER REH */ \ + 0x0580, /* ARMENIAN SMALL LETTER REH */ }, \ + { 0x054D, /* ARMENIAN CAPITAL LETTER SEH */ \ + 0x057D, /* ARMENIAN SMALL LETTER SEH */ }, \ + { 0x0547, /* ARMENIAN CAPITAL LETTER SHA */ \ + 0x0577, /* ARMENIAN SMALL LETTER SHA */ }, \ + { 0x054F, /* ARMENIAN CAPITAL LETTER TIWN */ \ + 0x057F, /* ARMENIAN SMALL LETTER TIWN */ }, \ + { 0x0539, /* ARMENIAN CAPITAL LETTER TO */ \ + 0x0569, /* ARMENIAN SMALL LETTER TO */ }, \ + { 0x054E, /* ARMENIAN CAPITAL LETTER VEW */ \ + 0x057E, /* ARMENIAN SMALL LETTER VEW */ }, \ + { 0x0548, /* ARMENIAN CAPITAL LETTER VO */ \ + 0x0578, /* ARMENIAN SMALL LETTER VO */ }, \ + { 0x053D, /* ARMENIAN CAPITAL LETTER XEH */ \ + 0x056D, /* ARMENIAN SMALL LETTER XEH */ }, \ + { 0x0545, /* ARMENIAN CAPITAL LETTER YI */ \ + 0x0575, /* ARMENIAN SMALL LETTER YI */ }, \ + { 0x0552, /* ARMENIAN CAPITAL LETTER YIWN */ \ + 0x0582, /* ARMENIAN SMALL LETTER YIWN */ }, \ + { 0x0536, /* ARMENIAN CAPITAL LETTER ZA */ \ + 0x0566, /* ARMENIAN SMALL LETTER ZA */ }, \ + { 0x053A, /* ARMENIAN CAPITAL LETTER ZHE */ \ + 0x056A, /* ARMENIAN SMALL LETTER ZHE */ }, \ + { 0x24B6, /* CIRCLED LATIN CAPITAL LETTER A */ \ + 0x24D0, /* CIRCLED LATIN SMALL LETTER A */ }, \ + { 0x24B7, /* CIRCLED LATIN CAPITAL LETTER B */ \ + 0x24D1, /* CIRCLED LATIN SMALL LETTER B */ }, \ + { 0x24B8, /* CIRCLED LATIN CAPITAL LETTER C */ \ + 0x24D2, /* CIRCLED LATIN SMALL LETTER C */ }, \ + { 0x24B9, /* CIRCLED LATIN CAPITAL LETTER D */ \ + 0x24D3, /* CIRCLED LATIN SMALL LETTER D */ }, \ + { 0x24BA, /* CIRCLED LATIN CAPITAL LETTER E */ \ + 0x24D4, /* CIRCLED LATIN SMALL LETTER E */ }, \ + { 0x24BB, /* CIRCLED LATIN CAPITAL LETTER F */ \ + 0x24D5, /* CIRCLED LATIN SMALL LETTER F */ }, \ + { 0x24BC, /* CIRCLED LATIN CAPITAL LETTER G */ \ + 0x24D6, /* CIRCLED LATIN SMALL LETTER G */ }, \ + { 0x24BD, /* CIRCLED LATIN CAPITAL LETTER H */ \ + 0x24D7, /* CIRCLED LATIN SMALL LETTER H */ }, \ + { 0x24BE, /* CIRCLED LATIN CAPITAL LETTER I */ \ + 0x24D8, /* CIRCLED LATIN SMALL LETTER I */ }, \ + { 0x24BF, /* CIRCLED LATIN CAPITAL LETTER J */ \ + 0x24D9, /* CIRCLED LATIN SMALL LETTER J */ }, \ + { 0x24C0, /* CIRCLED LATIN CAPITAL LETTER K */ \ + 0x24DA, /* CIRCLED LATIN SMALL LETTER K */ }, \ + { 0x24C1, /* CIRCLED LATIN CAPITAL LETTER L */ \ + 0x24DB, /* CIRCLED LATIN SMALL LETTER L */ }, \ + { 0x24C2, /* CIRCLED LATIN CAPITAL LETTER M */ \ + 0x24DC, /* CIRCLED LATIN SMALL LETTER M */ }, \ + { 0x24C3, /* CIRCLED LATIN CAPITAL LETTER N */ \ + 0x24DD, /* CIRCLED LATIN SMALL LETTER N */ }, \ + { 0x24C4, /* CIRCLED LATIN CAPITAL LETTER O */ \ + 0x24DE, /* CIRCLED LATIN SMALL LETTER O */ }, \ + { 0x24C5, /* CIRCLED LATIN CAPITAL LETTER P */ \ + 0x24DF, /* CIRCLED LATIN SMALL LETTER P */ }, \ + { 0x24C6, /* CIRCLED LATIN CAPITAL LETTER Q */ \ + 0x24E0, /* CIRCLED LATIN SMALL LETTER Q */ }, \ + { 0x24C7, /* CIRCLED LATIN CAPITAL LETTER R */ \ + 0x24E1, /* CIRCLED LATIN SMALL LETTER R */ }, \ + { 0x24C8, /* CIRCLED LATIN CAPITAL LETTER S */ \ + 0x24E2, /* CIRCLED LATIN SMALL LETTER S */ }, \ + { 0x24C9, /* CIRCLED LATIN CAPITAL LETTER T */ \ + 0x24E3, /* CIRCLED LATIN SMALL LETTER T */ }, \ + { 0x24CA, /* CIRCLED LATIN CAPITAL LETTER U */ \ + 0x24E4, /* CIRCLED LATIN SMALL LETTER U */ }, \ + { 0x24CB, /* CIRCLED LATIN CAPITAL LETTER V */ \ + 0x24E5, /* CIRCLED LATIN SMALL LETTER V */ }, \ + { 0x24CC, /* CIRCLED LATIN CAPITAL LETTER W */ \ + 0x24E6, /* CIRCLED LATIN SMALL LETTER W */ }, \ + { 0x24CD, /* CIRCLED LATIN CAPITAL LETTER X */ \ + 0x24E7, /* CIRCLED LATIN SMALL LETTER X */ }, \ + { 0x24CE, /* CIRCLED LATIN CAPITAL LETTER Y */ \ + 0x24E8, /* CIRCLED LATIN SMALL LETTER Y */ }, \ + { 0x24CF, /* CIRCLED LATIN CAPITAL LETTER Z */ \ + 0x24E9, /* CIRCLED LATIN SMALL LETTER Z */ }, \ + { 0x2CC8, /* COPTIC CAPITAL LETTER AKHMIMIC KHEI */ \ + 0x2CC9, /* COPTIC SMALL LETTER AKHMIMIC KHEI */ }, \ + { 0x2C80, /* COPTIC CAPITAL LETTER ALFA */ \ + 0x2C81, /* COPTIC SMALL LETTER ALFA */ }, \ + { 0x2CF2, /* COPTIC CAPITAL LETTER BOHAIRIC KHEI */ \ + 0x2CF3, /* COPTIC SMALL LETTER BOHAIRIC KHEI */ }, \ + { 0x2CC2, /* COPTIC CAPITAL LETTER CROSSED SHEI */ \ + 0x2CC3, /* COPTIC SMALL LETTER CROSSED SHEI */ }, \ + { 0x2CB6, /* COPTIC CAPITAL LETTER CRYPTOGRAMMIC EIE */ \ + 0x2CB7, /* COPTIC SMALL LETTER CRYPTOGRAMMIC EIE */ }, \ + { 0x2CED, /* COPTIC CAPITAL LETTER CRYPTOGRAMMIC GANGIA */ \ + 0x2CEE, /* COPTIC SMALL LETTER CRYPTOGRAMMIC GANGIA */ }, \ + { 0x2CBC, /* COPTIC CAPITAL LETTER CRYPTOGRAMMIC NI */ \ + 0x2CBD, /* COPTIC SMALL LETTER CRYPTOGRAMMIC NI */ }, \ + { 0x2CEB, /* COPTIC CAPITAL LETTER CRYPTOGRAMMIC SHEI */ \ + 0x2CEC, /* COPTIC SMALL LETTER CRYPTOGRAMMIC SHEI */ }, \ + { 0x2C86, /* COPTIC CAPITAL LETTER DALDA */ \ + 0x2C87, /* COPTIC SMALL LETTER DALDA */ }, \ + { 0x03EE, /* COPTIC CAPITAL LETTER DEI */ \ + 0x03EF, /* COPTIC SMALL LETTER DEI */ }, \ + { 0x2CB2, /* COPTIC CAPITAL LETTER DIALECT-P ALEF */ \ + 0x2CB3, /* COPTIC SMALL LETTER DIALECT-P ALEF */ }, \ + { 0x2CCA, /* COPTIC CAPITAL LETTER DIALECT-P HORI */ \ + 0x2CCB, /* COPTIC SMALL LETTER DIALECT-P HORI */ }, \ + { 0x2CB8, /* COPTIC CAPITAL LETTER DIALECT-P KAPA */ \ + 0x2CB9, /* COPTIC SMALL LETTER DIALECT-P KAPA */ }, \ + { 0x2CBA, /* COPTIC CAPITAL LETTER DIALECT-P NI */ \ + 0x2CBB, /* COPTIC SMALL LETTER DIALECT-P NI */ }, \ + { 0x2C88, /* COPTIC CAPITAL LETTER EIE */ \ + 0x2C89, /* COPTIC SMALL LETTER EIE */ }, \ + { 0x03E4, /* COPTIC CAPITAL LETTER FEI */ \ + 0x03E5, /* COPTIC SMALL LETTER FEI */ }, \ + { 0x2CAA, /* COPTIC CAPITAL LETTER FI */ \ + 0x2CAB, /* COPTIC SMALL LETTER FI */ }, \ + { 0x2C84, /* COPTIC CAPITAL LETTER GAMMA */ \ + 0x2C85, /* COPTIC SMALL LETTER GAMMA */ }, \ + { 0x03EA, /* COPTIC CAPITAL LETTER GANGIA */ \ + 0x03EB, /* COPTIC SMALL LETTER GANGIA */ }, \ + { 0x2C8E, /* COPTIC CAPITAL LETTER HATE */ \ + 0x2C8F, /* COPTIC SMALL LETTER HATE */ }, \ + { 0x03E8, /* COPTIC CAPITAL LETTER HORI */ \ + 0x03E9, /* COPTIC SMALL LETTER HORI */ }, \ + { 0x2C92, /* COPTIC CAPITAL LETTER IAUDA */ \ + 0x2C93, /* COPTIC SMALL LETTER IAUDA */ }, \ + { 0x2C94, /* COPTIC CAPITAL LETTER KAPA */ \ + 0x2C95, /* COPTIC SMALL LETTER KAPA */ }, \ + { 0x03E6, /* COPTIC CAPITAL LETTER KHEI */ \ + 0x03E7, /* COPTIC SMALL LETTER KHEI */ }, \ + { 0x2CAC, /* COPTIC CAPITAL LETTER KHI */ \ + 0x2CAD, /* COPTIC SMALL LETTER KHI */ }, \ + { 0x2C9C, /* COPTIC CAPITAL LETTER KSI */ \ + 0x2C9D, /* COPTIC SMALL LETTER KSI */ }, \ + { 0x2C96, /* COPTIC CAPITAL LETTER LAULA */ \ + 0x2C97, /* COPTIC SMALL LETTER LAULA */ }, \ + { 0x2CD0, /* COPTIC CAPITAL LETTER L-SHAPED HA */ \ + 0x2CD1, /* COPTIC SMALL LETTER L-SHAPED HA */ }, \ + { 0x2C98, /* COPTIC CAPITAL LETTER MI */ \ + 0x2C99, /* COPTIC SMALL LETTER MI */ }, \ + { 0x2C9A, /* COPTIC CAPITAL LETTER NI */ \ + 0x2C9B, /* COPTIC SMALL LETTER NI */ }, \ + { 0x2C9E, /* COPTIC CAPITAL LETTER O */ \ + 0x2C9F, /* COPTIC SMALL LETTER O */ }, \ + { 0x2CB4, /* COPTIC CAPITAL LETTER OLD COPTIC AIN */ \ + 0x2CB5, /* COPTIC SMALL LETTER OLD COPTIC AIN */ }, \ + { 0x2CD8, /* COPTIC CAPITAL LETTER OLD COPTIC DJA */ \ + 0x2CD9, /* COPTIC SMALL LETTER OLD COPTIC DJA */ }, \ + { 0x2CC6, /* COPTIC CAPITAL LETTER OLD COPTIC ESH */ \ + 0x2CC7, /* COPTIC SMALL LETTER OLD COPTIC ESH */ }, \ + { 0x2CD6, /* COPTIC CAPITAL LETTER OLD COPTIC GANGIA */ \ + 0x2CD7, /* COPTIC SMALL LETTER OLD COPTIC GANGIA */ }, \ + { 0x2CCE, /* COPTIC CAPITAL LETTER OLD COPTIC HA */ \ + 0x2CCF, /* COPTIC SMALL LETTER OLD COPTIC HA */ }, \ + { 0x2CD4, /* COPTIC CAPITAL LETTER OLD COPTIC HAT */ \ + 0x2CD5, /* COPTIC SMALL LETTER OLD COPTIC HAT */ }, \ + { 0x2CD2, /* COPTIC CAPITAL LETTER OLD COPTIC HEI */ \ + 0x2CD3, /* COPTIC SMALL LETTER OLD COPTIC HEI */ }, \ + { 0x2CCC, /* COPTIC CAPITAL LETTER OLD COPTIC HORI */ \ + 0x2CCD, /* COPTIC SMALL LETTER OLD COPTIC HORI */ }, \ + { 0x2CBE, /* COPTIC CAPITAL LETTER OLD COPTIC OOU */ \ + 0x2CBF, /* COPTIC SMALL LETTER OLD COPTIC OOU */ }, \ + { 0x2CC4, /* COPTIC CAPITAL LETTER OLD COPTIC SHEI */ \ + 0x2CC5, /* COPTIC SMALL LETTER OLD COPTIC SHEI */ }, \ + { 0x2CDA, /* COPTIC CAPITAL LETTER OLD COPTIC SHIMA */ \ + 0x2CDB, /* COPTIC SMALL LETTER OLD COPTIC SHIMA */ }, \ + { 0x2CDE, /* COPTIC CAPITAL LETTER OLD NUBIAN NGI */ \ + 0x2CDF, /* COPTIC SMALL LETTER OLD NUBIAN NGI */ }, \ + { 0x2CE0, /* COPTIC CAPITAL LETTER OLD NUBIAN NYI */ \ + 0x2CE1, /* COPTIC SMALL LETTER OLD NUBIAN NYI */ }, \ + { 0x2CDC, /* COPTIC CAPITAL LETTER OLD NUBIAN SHIMA */ \ + 0x2CDD, /* COPTIC SMALL LETTER OLD NUBIAN SHIMA */ }, \ + { 0x2CE2, /* COPTIC CAPITAL LETTER OLD NUBIAN WAU */ \ + 0x2CE3, /* COPTIC SMALL LETTER OLD NUBIAN WAU */ }, \ + { 0x2CB0, /* COPTIC CAPITAL LETTER OOU */ \ + 0x2CB1, /* COPTIC SMALL LETTER OOU */ }, \ + { 0x2CA0, /* COPTIC CAPITAL LETTER PI */ \ + 0x2CA1, /* COPTIC SMALL LETTER PI */ }, \ + { 0x2CAE, /* COPTIC CAPITAL LETTER PSI */ \ + 0x2CAF, /* COPTIC SMALL LETTER PSI */ }, \ + { 0x2CA2, /* COPTIC CAPITAL LETTER RO */ \ + 0x2CA3, /* COPTIC SMALL LETTER RO */ }, \ + { 0x2CC0, /* COPTIC CAPITAL LETTER SAMPI */ \ + 0x2CC1, /* COPTIC SMALL LETTER SAMPI */ }, \ + { 0x03E2, /* COPTIC CAPITAL LETTER SHEI */ \ + 0x03E3, /* COPTIC SMALL LETTER SHEI */ }, \ + { 0x03EC, /* COPTIC CAPITAL LETTER SHIMA */ \ + 0x03ED, /* COPTIC SMALL LETTER SHIMA */ }, \ + { 0x2CA4, /* COPTIC CAPITAL LETTER SIMA */ \ + 0x2CA5, /* COPTIC SMALL LETTER SIMA */ }, \ + { 0x2C8A, /* COPTIC CAPITAL LETTER SOU */ \ + 0x2C8B, /* COPTIC SMALL LETTER SOU */ }, \ + { 0x2CA6, /* COPTIC CAPITAL LETTER TAU */ \ + 0x2CA7, /* COPTIC SMALL LETTER TAU */ }, \ + { 0x2C90, /* COPTIC CAPITAL LETTER THETHE */ \ + 0x2C91, /* COPTIC SMALL LETTER THETHE */ }, \ + { 0x2CA8, /* COPTIC CAPITAL LETTER UA */ \ + 0x2CA9, /* COPTIC SMALL LETTER UA */ }, \ + { 0x2C82, /* COPTIC CAPITAL LETTER VIDA */ \ + 0x2C83, /* COPTIC SMALL LETTER VIDA */ }, \ + { 0x2C8C, /* COPTIC CAPITAL LETTER ZATA */ \ + 0x2C8D, /* COPTIC SMALL LETTER ZATA */ }, \ + { 0x0410, /* CYRILLIC CAPITAL LETTER A */ \ + 0x0430, /* CYRILLIC SMALL LETTER A */ }, \ + { 0x04D0, /* CYRILLIC CAPITAL LETTER A WITH BREVE */ \ + 0x04D1, /* CYRILLIC SMALL LETTER A WITH BREVE */ }, \ + { 0x04D2, /* CYRILLIC CAPITAL LETTER A WITH DIAERESIS */ \ + 0x04D3, /* CYRILLIC SMALL LETTER A WITH DIAERESIS */ }, \ + { 0x04BC, /* CYRILLIC CAPITAL LETTER ABKHASIAN CHE */ \ + 0x04BD, /* CYRILLIC SMALL LETTER ABKHASIAN CHE */ }, \ + { 0x04BE, /* CYRILLIC CAPITAL LETTER ABKHASIAN CHE WITH DESCENDER */ \ + 0x04BF, /* CYRILLIC SMALL LETTER ABKHASIAN CHE WITH DESCENDER */ }, \ + { 0x04E0, /* CYRILLIC CAPITAL LETTER ABKHASIAN DZE */ \ + 0x04E1, /* CYRILLIC SMALL LETTER ABKHASIAN DZE */ }, \ + { 0x04A8, /* CYRILLIC CAPITAL LETTER ABKHASIAN HA */ \ + 0x04A9, /* CYRILLIC SMALL LETTER ABKHASIAN HA */ }, \ + { 0x051E, /* CYRILLIC CAPITAL LETTER ALEUT KA */ \ + 0x051F, /* CYRILLIC SMALL LETTER ALEUT KA */ }, \ + { 0x04E8, /* CYRILLIC CAPITAL LETTER BARRED O */ \ + 0x04E9, /* CYRILLIC SMALL LETTER BARRED O */ }, \ + { 0x04EA, /* CYRILLIC CAPITAL LETTER BARRED O WITH DIAERESIS */ \ + 0x04EB, /* CYRILLIC SMALL LETTER BARRED O WITH DIAERESIS */ }, \ + { 0x04A0, /* CYRILLIC CAPITAL LETTER BASHKIR KA */ \ + 0x04A1, /* CYRILLIC SMALL LETTER BASHKIR KA */ }, \ + { 0x0411, /* CYRILLIC CAPITAL LETTER BE */ \ + 0x0431, /* CYRILLIC SMALL LETTER BE */ }, \ + { 0x046A, /* CYRILLIC CAPITAL LETTER BIG YUS */ \ + 0x046B, /* CYRILLIC SMALL LETTER BIG YUS */ }, \ + { 0xA66A, /* CYRILLIC CAPITAL LETTER BINOCULAR O */ \ + 0xA66B, /* CYRILLIC SMALL LETTER BINOCULAR O */ }, \ + { 0xA65A, /* CYRILLIC CAPITAL LETTER BLENDED YUS */ \ + 0xA65B, /* CYRILLIC SMALL LETTER BLENDED YUS */ }, \ + { 0xA64C, /* CYRILLIC CAPITAL LETTER BROAD OMEGA */ \ + 0xA64D, /* CYRILLIC SMALL LETTER BROAD OMEGA */ }, \ + { 0x0406, /* CYRILLIC CAPITAL LETTER BYELORUSSIAN-UKRAINIAN I */ \ + 0x0456, /* CYRILLIC SMALL LETTER BYELORUSSIAN-UKRAINIAN I */ }, \ + { 0xA686, /* CYRILLIC CAPITAL LETTER CCHE */ \ + 0xA687, /* CYRILLIC SMALL LETTER CCHE */ }, \ + { 0x0427, /* CYRILLIC CAPITAL LETTER CHE */ \ + 0x0447, /* CYRILLIC SMALL LETTER CHE */ }, \ + { 0x04B6, /* CYRILLIC CAPITAL LETTER CHE WITH DESCENDER */ \ + 0x04B7, /* CYRILLIC SMALL LETTER CHE WITH DESCENDER */ }, \ + { 0x04F4, /* CYRILLIC CAPITAL LETTER CHE WITH DIAERESIS */ \ + 0x04F5, /* CYRILLIC SMALL LETTER CHE WITH DIAERESIS */ }, \ + { 0x04B8, /* CYRILLIC CAPITAL LETTER CHE WITH VERTICAL STROKE */ \ + 0x04B9, /* CYRILLIC SMALL LETTER CHE WITH VERTICAL STROKE */ }, \ + { 0xA658, /* CYRILLIC CAPITAL LETTER CLOSED LITTLE YUS */ \ + 0xA659, /* CYRILLIC SMALL LETTER CLOSED LITTLE YUS */ }, \ + { 0xA69A, /* CYRILLIC CAPITAL LETTER CROSSED O */ \ + 0xA69B, /* CYRILLIC SMALL LETTER CROSSED O */ }, \ + { 0x052C, /* CYRILLIC CAPITAL LETTER DCHE */ \ + 0x052D, /* CYRILLIC SMALL LETTER DCHE */ }, \ + { 0x0414, /* CYRILLIC CAPITAL LETTER DE */ \ + 0x0434, /* CYRILLIC SMALL LETTER DE */ }, \ + { 0x0402, /* CYRILLIC CAPITAL LETTER DJE */ \ + 0x0452, /* CYRILLIC SMALL LETTER DJE */ }, \ + { 0xA648, /* CYRILLIC CAPITAL LETTER DJERV */ \ + 0xA649, /* CYRILLIC SMALL LETTER DJERV */ }, \ + { 0xA66C, /* CYRILLIC CAPITAL LETTER DOUBLE MONOCULAR O */ \ + 0xA66D, /* CYRILLIC SMALL LETTER DOUBLE MONOCULAR O */ }, \ + { 0xA698, /* CYRILLIC CAPITAL LETTER DOUBLE O */ \ + 0xA699, /* CYRILLIC SMALL LETTER DOUBLE O */ }, \ + { 0xA680, /* CYRILLIC CAPITAL LETTER DWE */ \ + 0xA681, /* CYRILLIC SMALL LETTER DWE */ }, \ + { 0x0405, /* CYRILLIC CAPITAL LETTER DZE */ \ + 0x0455, /* CYRILLIC SMALL LETTER DZE */ }, \ + { 0xA642, /* CYRILLIC CAPITAL LETTER DZELO */ \ + 0xA643, /* CYRILLIC SMALL LETTER DZELO */ }, \ + { 0x040F, /* CYRILLIC CAPITAL LETTER DZHE */ \ + 0x045F, /* CYRILLIC SMALL LETTER DZHE */ }, \ + { 0xA682, /* CYRILLIC CAPITAL LETTER DZWE */ \ + 0xA683, /* CYRILLIC SMALL LETTER DZWE */ }, \ + { 0xA688, /* CYRILLIC CAPITAL LETTER DZZE */ \ + 0xA689, /* CYRILLIC SMALL LETTER DZZE */ }, \ + { 0x052A, /* CYRILLIC CAPITAL LETTER DZZHE */ \ + 0x052B, /* CYRILLIC SMALL LETTER DZZHE */ }, \ + { 0x042D, /* CYRILLIC CAPITAL LETTER E */ \ + 0x044D, /* CYRILLIC SMALL LETTER E */ }, \ + { 0x04EC, /* CYRILLIC CAPITAL LETTER E WITH DIAERESIS */ \ + 0x04ED, /* CYRILLIC SMALL LETTER E WITH DIAERESIS */ }, \ + { 0x0424, /* CYRILLIC CAPITAL LETTER EF */ \ + 0x0444, /* CYRILLIC SMALL LETTER EF */ }, \ + { 0x041B, /* CYRILLIC CAPITAL LETTER EL */ \ + 0x043B, /* CYRILLIC SMALL LETTER EL */ }, \ + { 0x052E, /* CYRILLIC CAPITAL LETTER EL WITH DESCENDER */ \ + 0x052F, /* CYRILLIC SMALL LETTER EL WITH DESCENDER */ }, \ + { 0x0512, /* CYRILLIC CAPITAL LETTER EL WITH HOOK */ \ + 0x0513, /* CYRILLIC SMALL LETTER EL WITH HOOK */ }, \ + { 0x0520, /* CYRILLIC CAPITAL LETTER EL WITH MIDDLE HOOK */ \ + 0x0521, /* CYRILLIC SMALL LETTER EL WITH MIDDLE HOOK */ }, \ + { 0x04C5, /* CYRILLIC CAPITAL LETTER EL WITH TAIL */ \ + 0x04C6, /* CYRILLIC SMALL LETTER EL WITH TAIL */ }, \ + { 0x041C, /* CYRILLIC CAPITAL LETTER EM */ \ + 0x043C, /* CYRILLIC SMALL LETTER EM */ }, \ + { 0x04CD, /* CYRILLIC CAPITAL LETTER EM WITH TAIL */ \ + 0x04CE, /* CYRILLIC SMALL LETTER EM WITH TAIL */ }, \ + { 0x041D, /* CYRILLIC CAPITAL LETTER EN */ \ + 0x043D, /* CYRILLIC SMALL LETTER EN */ }, \ + { 0x04A2, /* CYRILLIC CAPITAL LETTER EN WITH DESCENDER */ \ + 0x04A3, /* CYRILLIC SMALL LETTER EN WITH DESCENDER */ }, \ + { 0x04C7, /* CYRILLIC CAPITAL LETTER EN WITH HOOK */ \ + 0x04C8, /* CYRILLIC SMALL LETTER EN WITH HOOK */ }, \ + { 0x0528, /* CYRILLIC CAPITAL LETTER EN WITH LEFT HOOK */ \ + 0x0529, /* CYRILLIC SMALL LETTER EN WITH LEFT HOOK */ }, \ + { 0x0522, /* CYRILLIC CAPITAL LETTER EN WITH MIDDLE HOOK */ \ + 0x0523, /* CYRILLIC SMALL LETTER EN WITH MIDDLE HOOK */ }, \ + { 0x04C9, /* CYRILLIC CAPITAL LETTER EN WITH TAIL */ \ + 0x04CA, /* CYRILLIC SMALL LETTER EN WITH TAIL */ }, \ + { 0x0420, /* CYRILLIC CAPITAL LETTER ER */ \ + 0x0440, /* CYRILLIC SMALL LETTER ER */ }, \ + { 0x048E, /* CYRILLIC CAPITAL LETTER ER WITH TICK */ \ + 0x048F, /* CYRILLIC SMALL LETTER ER WITH TICK */ }, \ + { 0x0421, /* CYRILLIC CAPITAL LETTER ES */ \ + 0x0441, /* CYRILLIC SMALL LETTER ES */ }, \ + { 0x04AA, /* CYRILLIC CAPITAL LETTER ES WITH DESCENDER */ \ + 0x04AB, /* CYRILLIC SMALL LETTER ES WITH DESCENDER */ }, \ + { 0x0472, /* CYRILLIC CAPITAL LETTER FITA */ \ + 0x0473, /* CYRILLIC SMALL LETTER FITA */ }, \ + { 0x0413, /* CYRILLIC CAPITAL LETTER GHE */ \ + 0x0433, /* CYRILLIC SMALL LETTER GHE */ }, \ + { 0x04F6, /* CYRILLIC CAPITAL LETTER GHE WITH DESCENDER */ \ + 0x04F7, /* CYRILLIC SMALL LETTER GHE WITH DESCENDER */ }, \ + { 0x0494, /* CYRILLIC CAPITAL LETTER GHE WITH MIDDLE HOOK */ \ + 0x0495, /* CYRILLIC SMALL LETTER GHE WITH MIDDLE HOOK */ }, \ + { 0x0492, /* CYRILLIC CAPITAL LETTER GHE WITH STROKE */ \ + 0x0493, /* CYRILLIC SMALL LETTER GHE WITH STROKE */ }, \ + { 0x04FA, /* CYRILLIC CAPITAL LETTER GHE WITH STROKE AND HOOK */ \ + 0x04FB, /* CYRILLIC SMALL LETTER GHE WITH STROKE AND HOOK */ }, \ + { 0x0490, /* CYRILLIC CAPITAL LETTER GHE WITH UPTURN */ \ + 0x0491, /* CYRILLIC SMALL LETTER GHE WITH UPTURN */ }, \ + { 0x0403, /* CYRILLIC CAPITAL LETTER GJE */ \ + 0x0453, /* CYRILLIC SMALL LETTER GJE */ }, \ + { 0x0425, /* CYRILLIC CAPITAL LETTER HA */ \ + 0x0445, /* CYRILLIC SMALL LETTER HA */ }, \ + { 0x04B2, /* CYRILLIC CAPITAL LETTER HA WITH DESCENDER */ \ + 0x04B3, /* CYRILLIC SMALL LETTER HA WITH DESCENDER */ }, \ + { 0x04FC, /* CYRILLIC CAPITAL LETTER HA WITH HOOK */ \ + 0x04FD, /* CYRILLIC SMALL LETTER HA WITH HOOK */ }, \ + { 0x04FE, /* CYRILLIC CAPITAL LETTER HA WITH STROKE */ \ + 0x04FF, /* CYRILLIC SMALL LETTER HA WITH STROKE */ }, \ + { 0x042A, /* CYRILLIC CAPITAL LETTER HARD SIGN */ \ + 0x044A, /* CYRILLIC SMALL LETTER HARD SIGN */ }, \ + { 0xA694, /* CYRILLIC CAPITAL LETTER HWE */ \ + 0xA695, /* CYRILLIC SMALL LETTER HWE */ }, \ + { 0x0418, /* CYRILLIC CAPITAL LETTER I */ \ + 0x0438, /* CYRILLIC SMALL LETTER I */ }, \ + { 0x04E4, /* CYRILLIC CAPITAL LETTER I WITH DIAERESIS */ \ + 0x04E5, /* CYRILLIC SMALL LETTER I WITH DIAERESIS */ }, \ + { 0x040D, /* CYRILLIC CAPITAL LETTER I WITH GRAVE */ \ + 0x045D, /* CYRILLIC SMALL LETTER I WITH GRAVE */ }, \ + { 0x04E2, /* CYRILLIC CAPITAL LETTER I WITH MACRON */ \ + 0x04E3, /* CYRILLIC SMALL LETTER I WITH MACRON */ }, \ + { 0x0415, /* CYRILLIC CAPITAL LETTER IE */ \ + 0x0435, /* CYRILLIC SMALL LETTER IE */ }, \ + { 0x04D6, /* CYRILLIC CAPITAL LETTER IE WITH BREVE */ \ + 0x04D7, /* CYRILLIC SMALL LETTER IE WITH BREVE */ }, \ + { 0x0400, /* CYRILLIC CAPITAL LETTER IE WITH GRAVE */ \ + 0x0450, /* CYRILLIC SMALL LETTER IE WITH GRAVE */ }, \ + { 0x0401, /* CYRILLIC CAPITAL LETTER IO */ \ + 0x0451, /* CYRILLIC SMALL LETTER IO */ }, \ + { 0xA646, /* CYRILLIC CAPITAL LETTER IOTA */ \ + 0xA647, /* CYRILLIC SMALL LETTER IOTA */ }, \ + { 0xA656, /* CYRILLIC CAPITAL LETTER IOTIFIED A */ \ + 0xA657, /* CYRILLIC SMALL LETTER IOTIFIED A */ }, \ + { 0x046C, /* CYRILLIC CAPITAL LETTER IOTIFIED BIG YUS */ \ + 0x046D, /* CYRILLIC SMALL LETTER IOTIFIED BIG YUS */ }, \ + { 0xA65C, /* CYRILLIC CAPITAL LETTER IOTIFIED CLOSED LITTLE YUS */ \ + 0xA65D, /* CYRILLIC SMALL LETTER IOTIFIED CLOSED LITTLE YUS */ }, \ + { 0x0464, /* CYRILLIC CAPITAL LETTER IOTIFIED E */ \ + 0x0465, /* CYRILLIC SMALL LETTER IOTIFIED E */ }, \ + { 0x0468, /* CYRILLIC CAPITAL LETTER IOTIFIED LITTLE YUS */ \ + 0x0469, /* CYRILLIC SMALL LETTER IOTIFIED LITTLE YUS */ }, \ + { 0xA652, /* CYRILLIC CAPITAL LETTER IOTIFIED YAT */ \ + 0xA653, /* CYRILLIC SMALL LETTER IOTIFIED YAT */ }, \ + { 0x0474, /* CYRILLIC CAPITAL LETTER IZHITSA */ \ + 0x0475, /* CYRILLIC SMALL LETTER IZHITSA */ }, \ + { 0x0476, /* CYRILLIC CAPITAL LETTER IZHITSA WITH DOUBLE GRAVE ACCENT */ \ + 0x0477, /* CYRILLIC SMALL LETTER IZHITSA WITH DOUBLE GRAVE ACCENT */ }, \ + { 0x0408, /* CYRILLIC CAPITAL LETTER JE */ \ + 0x0458, /* CYRILLIC SMALL LETTER JE */ }, \ + { 0x041A, /* CYRILLIC CAPITAL LETTER KA */ \ + 0x043A, /* CYRILLIC SMALL LETTER KA */ }, \ + { 0x049A, /* CYRILLIC CAPITAL LETTER KA WITH DESCENDER */ \ + 0x049B, /* CYRILLIC SMALL LETTER KA WITH DESCENDER */ }, \ + { 0x04C3, /* CYRILLIC CAPITAL LETTER KA WITH HOOK */ \ + 0x04C4, /* CYRILLIC SMALL LETTER KA WITH HOOK */ }, \ + { 0x049E, /* CYRILLIC CAPITAL LETTER KA WITH STROKE */ \ + 0x049F, /* CYRILLIC SMALL LETTER KA WITH STROKE */ }, \ + { 0x049C, /* CYRILLIC CAPITAL LETTER KA WITH VERTICAL STROKE */ \ + 0x049D, /* CYRILLIC SMALL LETTER KA WITH VERTICAL STROKE */ }, \ + { 0x04CB, /* CYRILLIC CAPITAL LETTER KHAKASSIAN CHE */ \ + 0x04CC, /* CYRILLIC SMALL LETTER KHAKASSIAN CHE */ }, \ + { 0x040C, /* CYRILLIC CAPITAL LETTER KJE */ \ + 0x045C, /* CYRILLIC SMALL LETTER KJE */ }, \ + { 0x0500, /* CYRILLIC CAPITAL LETTER KOMI DE */ \ + 0x0501, /* CYRILLIC SMALL LETTER KOMI DE */ }, \ + { 0x0502, /* CYRILLIC CAPITAL LETTER KOMI DJE */ \ + 0x0503, /* CYRILLIC SMALL LETTER KOMI DJE */ }, \ + { 0x0506, /* CYRILLIC CAPITAL LETTER KOMI DZJE */ \ + 0x0507, /* CYRILLIC SMALL LETTER KOMI DZJE */ }, \ + { 0x0508, /* CYRILLIC CAPITAL LETTER KOMI LJE */ \ + 0x0509, /* CYRILLIC SMALL LETTER KOMI LJE */ }, \ + { 0x050A, /* CYRILLIC CAPITAL LETTER KOMI NJE */ \ + 0x050B, /* CYRILLIC SMALL LETTER KOMI NJE */ }, \ + { 0x050C, /* CYRILLIC CAPITAL LETTER KOMI SJE */ \ + 0x050D, /* CYRILLIC SMALL LETTER KOMI SJE */ }, \ + { 0x050E, /* CYRILLIC CAPITAL LETTER KOMI TJE */ \ + 0x050F, /* CYRILLIC SMALL LETTER KOMI TJE */ }, \ + { 0x0504, /* CYRILLIC CAPITAL LETTER KOMI ZJE */ \ + 0x0505, /* CYRILLIC SMALL LETTER KOMI ZJE */ }, \ + { 0x0480, /* CYRILLIC CAPITAL LETTER KOPPA */ \ + 0x0481, /* CYRILLIC SMALL LETTER KOPPA */ }, \ + { 0x046E, /* CYRILLIC CAPITAL LETTER KSI */ \ + 0x046F, /* CYRILLIC SMALL LETTER KSI */ }, \ + { 0x0514, /* CYRILLIC CAPITAL LETTER LHA */ \ + 0x0515, /* CYRILLIC SMALL LETTER LHA */ }, \ + { 0x0466, /* CYRILLIC CAPITAL LETTER LITTLE YUS */ \ + 0x0467, /* CYRILLIC SMALL LETTER LITTLE YUS */ }, \ + { 0x0409, /* CYRILLIC CAPITAL LETTER LJE */ \ + 0x0459, /* CYRILLIC SMALL LETTER LJE */ }, \ + { 0xA668, /* CYRILLIC CAPITAL LETTER MONOCULAR O */ \ + 0xA669, /* CYRILLIC SMALL LETTER MONOCULAR O */ }, \ + { 0xA64A, /* CYRILLIC CAPITAL LETTER MONOGRAPH UK */ \ + 0xA64B, /* CYRILLIC SMALL LETTER MONOGRAPH UK */ }, \ + { 0xA64E, /* CYRILLIC CAPITAL LETTER NEUTRAL YER */ \ + 0xA64F, /* CYRILLIC SMALL LETTER NEUTRAL YER */ }, \ + { 0x040A, /* CYRILLIC CAPITAL LETTER NJE */ \ + 0x045A, /* CYRILLIC SMALL LETTER NJE */ }, \ + { 0x041E, /* CYRILLIC CAPITAL LETTER O */ \ + 0x043E, /* CYRILLIC SMALL LETTER O */ }, \ + { 0x04E6, /* CYRILLIC CAPITAL LETTER O WITH DIAERESIS */ \ + 0x04E7, /* CYRILLIC SMALL LETTER O WITH DIAERESIS */ }, \ + { 0x0460, /* CYRILLIC CAPITAL LETTER OMEGA */ \ + 0x0461, /* CYRILLIC SMALL LETTER OMEGA */ }, \ + { 0x047C, /* CYRILLIC CAPITAL LETTER OMEGA WITH TITLO */ \ + 0x047D, /* CYRILLIC SMALL LETTER OMEGA WITH TITLO */ }, \ + { 0x047E, /* CYRILLIC CAPITAL LETTER OT */ \ + 0x047F, /* CYRILLIC SMALL LETTER OT */ }, \ + { 0x041F, /* CYRILLIC CAPITAL LETTER PE */ \ + 0x043F, /* CYRILLIC SMALL LETTER PE */ }, \ + { 0x0524, /* CYRILLIC CAPITAL LETTER PE WITH DESCENDER */ \ + 0x0525, /* CYRILLIC SMALL LETTER PE WITH DESCENDER */ }, \ + { 0x04A6, /* CYRILLIC CAPITAL LETTER PE WITH MIDDLE HOOK */ \ + 0x04A7, /* CYRILLIC SMALL LETTER PE WITH MIDDLE HOOK */ }, \ + { 0x0470, /* CYRILLIC CAPITAL LETTER PSI */ \ + 0x0471, /* CYRILLIC SMALL LETTER PSI */ }, \ + { 0x051A, /* CYRILLIC CAPITAL LETTER QA */ \ + 0x051B, /* CYRILLIC SMALL LETTER QA */ }, \ + { 0xA644, /* CYRILLIC CAPITAL LETTER REVERSED DZE */ \ + 0xA645, /* CYRILLIC SMALL LETTER REVERSED DZE */ }, \ + { 0xA660, /* CYRILLIC CAPITAL LETTER REVERSED TSE */ \ + 0xA661, /* CYRILLIC SMALL LETTER REVERSED TSE */ }, \ + { 0xA654, /* CYRILLIC CAPITAL LETTER REVERSED YU */ \ + 0xA655, /* CYRILLIC SMALL LETTER REVERSED YU */ }, \ + { 0x0510, /* CYRILLIC CAPITAL LETTER REVERSED ZE */ \ + 0x0511, /* CYRILLIC SMALL LETTER REVERSED ZE */ }, \ + { 0x0516, /* CYRILLIC CAPITAL LETTER RHA */ \ + 0x0517, /* CYRILLIC SMALL LETTER RHA */ }, \ + { 0x047A, /* CYRILLIC CAPITAL LETTER ROUND OMEGA */ \ + 0x047B, /* CYRILLIC SMALL LETTER ROUND OMEGA */ }, \ + { 0x04D8, /* CYRILLIC CAPITAL LETTER SCHWA */ \ + 0x04D9, /* CYRILLIC SMALL LETTER SCHWA */ }, \ + { 0x04DA, /* CYRILLIC CAPITAL LETTER SCHWA WITH DIAERESIS */ \ + 0x04DB, /* CYRILLIC SMALL LETTER SCHWA WITH DIAERESIS */ }, \ + { 0x048C, /* CYRILLIC CAPITAL LETTER SEMISOFT SIGN */ \ + 0x048D, /* CYRILLIC SMALL LETTER SEMISOFT SIGN */ }, \ + { 0x0428, /* CYRILLIC CAPITAL LETTER SHA */ \ + 0x0448, /* CYRILLIC SMALL LETTER SHA */ }, \ + { 0x0429, /* CYRILLIC CAPITAL LETTER SHCHA */ \ + 0x0449, /* CYRILLIC SMALL LETTER SHCHA */ }, \ + { 0x04BA, /* CYRILLIC CAPITAL LETTER SHHA */ \ + 0x04BB, /* CYRILLIC SMALL LETTER SHHA */ }, \ + { 0x0526, /* CYRILLIC CAPITAL LETTER SHHA WITH DESCENDER */ \ + 0x0527, /* CYRILLIC SMALL LETTER SHHA WITH DESCENDER */ }, \ + { 0x048A, /* CYRILLIC CAPITAL LETTER SHORT I WITH TAIL */ \ + 0x048B, /* CYRILLIC SMALL LETTER SHORT I WITH TAIL */ }, \ + { 0x040E, /* CYRILLIC CAPITAL LETTER SHORT U */ \ + 0x045E, /* CYRILLIC SMALL LETTER SHORT U */ }, \ + { 0xA696, /* CYRILLIC CAPITAL LETTER SHWE */ \ + 0xA697, /* CYRILLIC SMALL LETTER SHWE */ }, \ + { 0xA662, /* CYRILLIC CAPITAL LETTER SOFT DE */ \ + 0xA663, /* CYRILLIC SMALL LETTER SOFT DE */ }, \ + { 0xA664, /* CYRILLIC CAPITAL LETTER SOFT EL */ \ + 0xA665, /* CYRILLIC SMALL LETTER SOFT EL */ }, \ + { 0xA666, /* CYRILLIC CAPITAL LETTER SOFT EM */ \ + 0xA667, /* CYRILLIC SMALL LETTER SOFT EM */ }, \ + { 0x042C, /* CYRILLIC CAPITAL LETTER SOFT SIGN */ \ + 0x044C, /* CYRILLIC SMALL LETTER SOFT SIGN */ }, \ + { 0x04AE, /* CYRILLIC CAPITAL LETTER STRAIGHT U */ \ + 0x04AF, /* CYRILLIC SMALL LETTER STRAIGHT U */ }, \ + { 0x04B0, /* CYRILLIC CAPITAL LETTER STRAIGHT U WITH STROKE */ \ + 0x04B1, /* CYRILLIC SMALL LETTER STRAIGHT U WITH STROKE */ }, \ + { 0xA692, /* CYRILLIC CAPITAL LETTER TCHE */ \ + 0xA693, /* CYRILLIC SMALL LETTER TCHE */ }, \ + { 0x0422, /* CYRILLIC CAPITAL LETTER TE */ \ + 0x0442, /* CYRILLIC SMALL LETTER TE */ }, \ + { 0x04AC, /* CYRILLIC CAPITAL LETTER TE WITH DESCENDER */ \ + 0x04AD, /* CYRILLIC SMALL LETTER TE WITH DESCENDER */ }, \ + { 0xA68A, /* CYRILLIC CAPITAL LETTER TE WITH MIDDLE HOOK */ \ + 0xA68B, /* CYRILLIC SMALL LETTER TE WITH MIDDLE HOOK */ }, \ + { 0x0426, /* CYRILLIC CAPITAL LETTER TSE */ \ + 0x0446, /* CYRILLIC SMALL LETTER TSE */ }, \ + { 0x040B, /* CYRILLIC CAPITAL LETTER TSHE */ \ + 0x045B, /* CYRILLIC SMALL LETTER TSHE */ }, \ + { 0xA690, /* CYRILLIC CAPITAL LETTER TSSE */ \ + 0xA691, /* CYRILLIC SMALL LETTER TSSE */ }, \ + { 0xA68E, /* CYRILLIC CAPITAL LETTER TSWE */ \ + 0xA68F, /* CYRILLIC SMALL LETTER TSWE */ }, \ + { 0xA68C, /* CYRILLIC CAPITAL LETTER TWE */ \ + 0xA68D, /* CYRILLIC SMALL LETTER TWE */ }, \ + { 0x0423, /* CYRILLIC CAPITAL LETTER U */ \ + 0x0443, /* CYRILLIC SMALL LETTER U */ }, \ + { 0x04F0, /* CYRILLIC CAPITAL LETTER U WITH DIAERESIS */ \ + 0x04F1, /* CYRILLIC SMALL LETTER U WITH DIAERESIS */ }, \ + { 0x04F2, /* CYRILLIC CAPITAL LETTER U WITH DOUBLE ACUTE */ \ + 0x04F3, /* CYRILLIC SMALL LETTER U WITH DOUBLE ACUTE */ }, \ + { 0x04EE, /* CYRILLIC CAPITAL LETTER U WITH MACRON */ \ + 0x04EF, /* CYRILLIC SMALL LETTER U WITH MACRON */ }, \ + { 0x0478, /* CYRILLIC CAPITAL LETTER UK */ \ + 0x0479, /* CYRILLIC SMALL LETTER UK */ }, \ + { 0x0404, /* CYRILLIC CAPITAL LETTER UKRAINIAN IE */ \ + 0x0454, /* CYRILLIC SMALL LETTER UKRAINIAN IE */ }, \ + { 0x0412, /* CYRILLIC CAPITAL LETTER VE */ \ + 0x0432, /* CYRILLIC SMALL LETTER VE */ }, \ + { 0x051C, /* CYRILLIC CAPITAL LETTER WE */ \ + 0x051D, /* CYRILLIC SMALL LETTER WE */ }, \ + { 0x042F, /* CYRILLIC CAPITAL LETTER YA */ \ + 0x044F, /* CYRILLIC SMALL LETTER YA */ }, \ + { 0x0518, /* CYRILLIC CAPITAL LETTER YAE */ \ + 0x0519, /* CYRILLIC SMALL LETTER YAE */ }, \ + { 0x0462, /* CYRILLIC CAPITAL LETTER YAT */ \ + 0x0463, /* CYRILLIC SMALL LETTER YAT */ }, \ + { 0x042B, /* CYRILLIC CAPITAL LETTER YERU */ \ + 0x044B, /* CYRILLIC SMALL LETTER YERU */ }, \ + { 0xA650, /* CYRILLIC CAPITAL LETTER YERU WITH BACK YER */ \ + 0xA651, /* CYRILLIC SMALL LETTER YERU WITH BACK YER */ }, \ + { 0x04F8, /* CYRILLIC CAPITAL LETTER YERU WITH DIAERESIS */ \ + 0x04F9, /* CYRILLIC SMALL LETTER YERU WITH DIAERESIS */ }, \ + { 0x0407, /* CYRILLIC CAPITAL LETTER YI */ \ + 0x0457, /* CYRILLIC SMALL LETTER YI */ }, \ + { 0xA65E, /* CYRILLIC CAPITAL LETTER YN */ \ + 0xA65F, /* CYRILLIC SMALL LETTER YN */ }, \ + { 0x042E, /* CYRILLIC CAPITAL LETTER YU */ \ + 0x044E, /* CYRILLIC SMALL LETTER YU */ }, \ + { 0x0417, /* CYRILLIC CAPITAL LETTER ZE */ \ + 0x0437, /* CYRILLIC SMALL LETTER ZE */ }, \ + { 0x0498, /* CYRILLIC CAPITAL LETTER ZE WITH DESCENDER */ \ + 0x0499, /* CYRILLIC SMALL LETTER ZE WITH DESCENDER */ }, \ + { 0x04DE, /* CYRILLIC CAPITAL LETTER ZE WITH DIAERESIS */ \ + 0x04DF, /* CYRILLIC SMALL LETTER ZE WITH DIAERESIS */ }, \ + { 0xA640, /* CYRILLIC CAPITAL LETTER ZEMLYA */ \ + 0xA641, /* CYRILLIC SMALL LETTER ZEMLYA */ }, \ + { 0x0416, /* CYRILLIC CAPITAL LETTER ZHE */ \ + 0x0436, /* CYRILLIC SMALL LETTER ZHE */ }, \ + { 0x04C1, /* CYRILLIC CAPITAL LETTER ZHE WITH BREVE */ \ + 0x04C2, /* CYRILLIC SMALL LETTER ZHE WITH BREVE */ }, \ + { 0x0496, /* CYRILLIC CAPITAL LETTER ZHE WITH DESCENDER */ \ + 0x0497, /* CYRILLIC SMALL LETTER ZHE WITH DESCENDER */ }, \ + { 0x04DC, /* CYRILLIC CAPITAL LETTER ZHE WITH DIAERESIS */ \ + 0x04DD, /* CYRILLIC SMALL LETTER ZHE WITH DIAERESIS */ }, \ + { 0xA684, /* CYRILLIC CAPITAL LETTER ZHWE */ \ + 0xA685, /* CYRILLIC SMALL LETTER ZHWE */ }, \ + { 0xFF21, /* FULLWIDTH LATIN CAPITAL LETTER A */ \ + 0xFF41, /* FULLWIDTH LATIN SMALL LETTER A */ }, \ + { 0xFF22, /* FULLWIDTH LATIN CAPITAL LETTER B */ \ + 0xFF42, /* FULLWIDTH LATIN SMALL LETTER B */ }, \ + { 0xFF23, /* FULLWIDTH LATIN CAPITAL LETTER C */ \ + 0xFF43, /* FULLWIDTH LATIN SMALL LETTER C */ }, \ + { 0xFF24, /* FULLWIDTH LATIN CAPITAL LETTER D */ \ + 0xFF44, /* FULLWIDTH LATIN SMALL LETTER D */ }, \ + { 0xFF25, /* FULLWIDTH LATIN CAPITAL LETTER E */ \ + 0xFF45, /* FULLWIDTH LATIN SMALL LETTER E */ }, \ + { 0xFF26, /* FULLWIDTH LATIN CAPITAL LETTER F */ \ + 0xFF46, /* FULLWIDTH LATIN SMALL LETTER F */ }, \ + { 0xFF27, /* FULLWIDTH LATIN CAPITAL LETTER G */ \ + 0xFF47, /* FULLWIDTH LATIN SMALL LETTER G */ }, \ + { 0xFF28, /* FULLWIDTH LATIN CAPITAL LETTER H */ \ + 0xFF48, /* FULLWIDTH LATIN SMALL LETTER H */ }, \ + { 0xFF29, /* FULLWIDTH LATIN CAPITAL LETTER I */ \ + 0xFF49, /* FULLWIDTH LATIN SMALL LETTER I */ }, \ + { 0xFF2A, /* FULLWIDTH LATIN CAPITAL LETTER J */ \ + 0xFF4A, /* FULLWIDTH LATIN SMALL LETTER J */ }, \ + { 0xFF2B, /* FULLWIDTH LATIN CAPITAL LETTER K */ \ + 0xFF4B, /* FULLWIDTH LATIN SMALL LETTER K */ }, \ + { 0xFF2C, /* FULLWIDTH LATIN CAPITAL LETTER L */ \ + 0xFF4C, /* FULLWIDTH LATIN SMALL LETTER L */ }, \ + { 0xFF2D, /* FULLWIDTH LATIN CAPITAL LETTER M */ \ + 0xFF4D, /* FULLWIDTH LATIN SMALL LETTER M */ }, \ + { 0xFF2E, /* FULLWIDTH LATIN CAPITAL LETTER N */ \ + 0xFF4E, /* FULLWIDTH LATIN SMALL LETTER N */ }, \ + { 0xFF2F, /* FULLWIDTH LATIN CAPITAL LETTER O */ \ + 0xFF4F, /* FULLWIDTH LATIN SMALL LETTER O */ }, \ + { 0xFF30, /* FULLWIDTH LATIN CAPITAL LETTER P */ \ + 0xFF50, /* FULLWIDTH LATIN SMALL LETTER P */ }, \ + { 0xFF31, /* FULLWIDTH LATIN CAPITAL LETTER Q */ \ + 0xFF51, /* FULLWIDTH LATIN SMALL LETTER Q */ }, \ + { 0xFF32, /* FULLWIDTH LATIN CAPITAL LETTER R */ \ + 0xFF52, /* FULLWIDTH LATIN SMALL LETTER R */ }, \ + { 0xFF33, /* FULLWIDTH LATIN CAPITAL LETTER S */ \ + 0xFF53, /* FULLWIDTH LATIN SMALL LETTER S */ }, \ + { 0xFF34, /* FULLWIDTH LATIN CAPITAL LETTER T */ \ + 0xFF54, /* FULLWIDTH LATIN SMALL LETTER T */ }, \ + { 0xFF35, /* FULLWIDTH LATIN CAPITAL LETTER U */ \ + 0xFF55, /* FULLWIDTH LATIN SMALL LETTER U */ }, \ + { 0xFF36, /* FULLWIDTH LATIN CAPITAL LETTER V */ \ + 0xFF56, /* FULLWIDTH LATIN SMALL LETTER V */ }, \ + { 0xFF37, /* FULLWIDTH LATIN CAPITAL LETTER W */ \ + 0xFF57, /* FULLWIDTH LATIN SMALL LETTER W */ }, \ + { 0xFF38, /* FULLWIDTH LATIN CAPITAL LETTER X */ \ + 0xFF58, /* FULLWIDTH LATIN SMALL LETTER X */ }, \ + { 0xFF39, /* FULLWIDTH LATIN CAPITAL LETTER Y */ \ + 0xFF59, /* FULLWIDTH LATIN SMALL LETTER Y */ }, \ + { 0xFF3A, /* FULLWIDTH LATIN CAPITAL LETTER Z */ \ + 0xFF5A, /* FULLWIDTH LATIN SMALL LETTER Z */ }, \ + { 0x10CD, /* GEORGIAN CAPITAL LETTER AEN */ \ + 0x2D2D, /* GEORGIAN SMALL LETTER AEN */ }, \ + { 0x10A0, /* GEORGIAN CAPITAL LETTER AN */ \ + 0x2D00, /* GEORGIAN SMALL LETTER AN */ }, \ + { 0x10A1, /* GEORGIAN CAPITAL LETTER BAN */ \ + 0x2D01, /* GEORGIAN SMALL LETTER BAN */ }, \ + { 0x10BA, /* GEORGIAN CAPITAL LETTER CAN */ \ + 0x2D1A, /* GEORGIAN SMALL LETTER CAN */ }, \ + { 0x10BD, /* GEORGIAN CAPITAL LETTER CHAR */ \ + 0x2D1D, /* GEORGIAN SMALL LETTER CHAR */ }, \ + { 0x10B9, /* GEORGIAN CAPITAL LETTER CHIN */ \ + 0x2D19, /* GEORGIAN SMALL LETTER CHIN */ }, \ + { 0x10BC, /* GEORGIAN CAPITAL LETTER CIL */ \ + 0x2D1C, /* GEORGIAN SMALL LETTER CIL */ }, \ + { 0x10A3, /* GEORGIAN CAPITAL LETTER DON */ \ + 0x2D03, /* GEORGIAN SMALL LETTER DON */ }, \ + { 0x10A4, /* GEORGIAN CAPITAL LETTER EN */ \ + 0x2D04, /* GEORGIAN SMALL LETTER EN */ }, \ + { 0x10A2, /* GEORGIAN CAPITAL LETTER GAN */ \ + 0x2D02, /* GEORGIAN SMALL LETTER GAN */ }, \ + { 0x10B6, /* GEORGIAN CAPITAL LETTER GHAN */ \ + 0x2D16, /* GEORGIAN SMALL LETTER GHAN */ }, \ + { 0x10C0, /* GEORGIAN CAPITAL LETTER HAE */ \ + 0x2D20, /* GEORGIAN SMALL LETTER HAE */ }, \ + { 0x10C4, /* GEORGIAN CAPITAL LETTER HAR */ \ + 0x2D24, /* GEORGIAN SMALL LETTER HAR */ }, \ + { 0x10C1, /* GEORGIAN CAPITAL LETTER HE */ \ + 0x2D21, /* GEORGIAN SMALL LETTER HE */ }, \ + { 0x10C2, /* GEORGIAN CAPITAL LETTER HIE */ \ + 0x2D22, /* GEORGIAN SMALL LETTER HIE */ }, \ + { 0x10C5, /* GEORGIAN CAPITAL LETTER HOE */ \ + 0x2D25, /* GEORGIAN SMALL LETTER HOE */ }, \ + { 0x10A8, /* GEORGIAN CAPITAL LETTER IN */ \ + 0x2D08, /* GEORGIAN SMALL LETTER IN */ }, \ + { 0x10BF, /* GEORGIAN CAPITAL LETTER JHAN */ \ + 0x2D1F, /* GEORGIAN SMALL LETTER JHAN */ }, \ + { 0x10BB, /* GEORGIAN CAPITAL LETTER JIL */ \ + 0x2D1B, /* GEORGIAN SMALL LETTER JIL */ }, \ + { 0x10A9, /* GEORGIAN CAPITAL LETTER KAN */ \ + 0x2D09, /* GEORGIAN SMALL LETTER KAN */ }, \ + { 0x10B5, /* GEORGIAN CAPITAL LETTER KHAR */ \ + 0x2D15, /* GEORGIAN SMALL LETTER KHAR */ }, \ + { 0x10AA, /* GEORGIAN CAPITAL LETTER LAS */ \ + 0x2D0A, /* GEORGIAN SMALL LETTER LAS */ }, \ + { 0x10AB, /* GEORGIAN CAPITAL LETTER MAN */ \ + 0x2D0B, /* GEORGIAN SMALL LETTER MAN */ }, \ + { 0x10AC, /* GEORGIAN CAPITAL LETTER NAR */ \ + 0x2D0C, /* GEORGIAN SMALL LETTER NAR */ }, \ + { 0x10AD, /* GEORGIAN CAPITAL LETTER ON */ \ + 0x2D0D, /* GEORGIAN SMALL LETTER ON */ }, \ + { 0x10AE, /* GEORGIAN CAPITAL LETTER PAR */ \ + 0x2D0E, /* GEORGIAN SMALL LETTER PAR */ }, \ + { 0x10B4, /* GEORGIAN CAPITAL LETTER PHAR */ \ + 0x2D14, /* GEORGIAN SMALL LETTER PHAR */ }, \ + { 0x10B7, /* GEORGIAN CAPITAL LETTER QAR */ \ + 0x2D17, /* GEORGIAN SMALL LETTER QAR */ }, \ + { 0x10B0, /* GEORGIAN CAPITAL LETTER RAE */ \ + 0x2D10, /* GEORGIAN SMALL LETTER RAE */ }, \ + { 0x10B1, /* GEORGIAN CAPITAL LETTER SAN */ \ + 0x2D11, /* GEORGIAN SMALL LETTER SAN */ }, \ + { 0x10B8, /* GEORGIAN CAPITAL LETTER SHIN */ \ + 0x2D18, /* GEORGIAN SMALL LETTER SHIN */ }, \ + { 0x10A7, /* GEORGIAN CAPITAL LETTER TAN */ \ + 0x2D07, /* GEORGIAN SMALL LETTER TAN */ }, \ + { 0x10B2, /* GEORGIAN CAPITAL LETTER TAR */ \ + 0x2D12, /* GEORGIAN SMALL LETTER TAR */ }, \ + { 0x10B3, /* GEORGIAN CAPITAL LETTER UN */ \ + 0x2D13, /* GEORGIAN SMALL LETTER UN */ }, \ + { 0x10A5, /* GEORGIAN CAPITAL LETTER VIN */ \ + 0x2D05, /* GEORGIAN SMALL LETTER VIN */ }, \ + { 0x10C3, /* GEORGIAN CAPITAL LETTER WE */ \ + 0x2D23, /* GEORGIAN SMALL LETTER WE */ }, \ + { 0x10BE, /* GEORGIAN CAPITAL LETTER XAN */ \ + 0x2D1E, /* GEORGIAN SMALL LETTER XAN */ }, \ + { 0x10C7, /* GEORGIAN CAPITAL LETTER YN */ \ + 0x2D27, /* GEORGIAN SMALL LETTER YN */ }, \ + { 0x10A6, /* GEORGIAN CAPITAL LETTER ZEN */ \ + 0x2D06, /* GEORGIAN SMALL LETTER ZEN */ }, \ + { 0x10AF, /* GEORGIAN CAPITAL LETTER ZHAR */ \ + 0x2D0F, /* GEORGIAN SMALL LETTER ZHAR */ }, \ + { 0x2C00, /* GLAGOLITIC CAPITAL LETTER AZU */ \ + 0x2C30, /* GLAGOLITIC SMALL LETTER AZU */ }, \ + { 0x2C28, /* GLAGOLITIC CAPITAL LETTER BIG YUS */ \ + 0x2C58, /* GLAGOLITIC SMALL LETTER BIG YUS */ }, \ + { 0x2C01, /* GLAGOLITIC CAPITAL LETTER BUKY */ \ + 0x2C31, /* GLAGOLITIC SMALL LETTER BUKY */ }, \ + { 0x2C1D, /* GLAGOLITIC CAPITAL LETTER CHRIVI */ \ + 0x2C4D, /* GLAGOLITIC SMALL LETTER CHRIVI */ }, \ + { 0x2C0C, /* GLAGOLITIC CAPITAL LETTER DJERVI */ \ + 0x2C3C, /* GLAGOLITIC SMALL LETTER DJERVI */ }, \ + { 0x2C04, /* GLAGOLITIC CAPITAL LETTER DOBRO */ \ + 0x2C34, /* GLAGOLITIC SMALL LETTER DOBRO */ }, \ + { 0x2C07, /* GLAGOLITIC CAPITAL LETTER DZELO */ \ + 0x2C37, /* GLAGOLITIC SMALL LETTER DZELO */ }, \ + { 0x2C2A, /* GLAGOLITIC CAPITAL LETTER FITA */ \ + 0x2C5A, /* GLAGOLITIC SMALL LETTER FITA */ }, \ + { 0x2C17, /* GLAGOLITIC CAPITAL LETTER FRITU */ \ + 0x2C47, /* GLAGOLITIC SMALL LETTER FRITU */ }, \ + { 0x2C03, /* GLAGOLITIC CAPITAL LETTER GLAGOLI */ \ + 0x2C33, /* GLAGOLITIC SMALL LETTER GLAGOLI */ }, \ + { 0x2C18, /* GLAGOLITIC CAPITAL LETTER HERU */ \ + 0x2C48, /* GLAGOLITIC SMALL LETTER HERU */ }, \ + { 0x2C0B, /* GLAGOLITIC CAPITAL LETTER I */ \ + 0x2C3B, /* GLAGOLITIC SMALL LETTER I */ }, \ + { 0x2C0A, /* GLAGOLITIC CAPITAL LETTER INITIAL IZHE */ \ + 0x2C3A, /* GLAGOLITIC SMALL LETTER INITIAL IZHE */ }, \ + { 0x2C29, /* GLAGOLITIC CAPITAL LETTER IOTATED BIG YUS */ \ + 0x2C59, /* GLAGOLITIC SMALL LETTER IOTATED BIG YUS */ }, \ + { 0x2C27, /* GLAGOLITIC CAPITAL LETTER IOTATED SMALL YUS */ \ + 0x2C57, /* GLAGOLITIC SMALL LETTER IOTATED SMALL YUS */ }, \ + { 0x2C09, /* GLAGOLITIC CAPITAL LETTER IZHE */ \ + 0x2C39, /* GLAGOLITIC SMALL LETTER IZHE */ }, \ + { 0x2C2B, /* GLAGOLITIC CAPITAL LETTER IZHITSA */ \ + 0x2C5B, /* GLAGOLITIC SMALL LETTER IZHITSA */ }, \ + { 0x2C0D, /* GLAGOLITIC CAPITAL LETTER KAKO */ \ + 0x2C3D, /* GLAGOLITIC SMALL LETTER KAKO */ }, \ + { 0x2C2E, /* GLAGOLITIC CAPITAL LETTER LATINATE MYSLITE */ \ + 0x2C5E, /* GLAGOLITIC SMALL LETTER LATINATE MYSLITE */ }, \ + { 0x2C0E, /* GLAGOLITIC CAPITAL LETTER LJUDIJE */ \ + 0x2C3E, /* GLAGOLITIC SMALL LETTER LJUDIJE */ }, \ + { 0x2C0F, /* GLAGOLITIC CAPITAL LETTER MYSLITE */ \ + 0x2C3F, /* GLAGOLITIC SMALL LETTER MYSLITE */ }, \ + { 0x2C10, /* GLAGOLITIC CAPITAL LETTER NASHI */ \ + 0x2C40, /* GLAGOLITIC SMALL LETTER NASHI */ }, \ + { 0x2C11, /* GLAGOLITIC CAPITAL LETTER ONU */ \ + 0x2C41, /* GLAGOLITIC SMALL LETTER ONU */ }, \ + { 0x2C19, /* GLAGOLITIC CAPITAL LETTER OTU */ \ + 0x2C49, /* GLAGOLITIC SMALL LETTER OTU */ }, \ + { 0x2C1A, /* GLAGOLITIC CAPITAL LETTER PE */ \ + 0x2C4A, /* GLAGOLITIC SMALL LETTER PE */ }, \ + { 0x2C12, /* GLAGOLITIC CAPITAL LETTER POKOJI */ \ + 0x2C42, /* GLAGOLITIC SMALL LETTER POKOJI */ }, \ + { 0x2C13, /* GLAGOLITIC CAPITAL LETTER RITSI */ \ + 0x2C43, /* GLAGOLITIC SMALL LETTER RITSI */ }, \ + { 0x2C1E, /* GLAGOLITIC CAPITAL LETTER SHA */ \ + 0x2C4E, /* GLAGOLITIC SMALL LETTER SHA */ }, \ + { 0x2C1B, /* GLAGOLITIC CAPITAL LETTER SHTA */ \ + 0x2C4B, /* GLAGOLITIC SMALL LETTER SHTA */ }, \ + { 0x2C2C, /* GLAGOLITIC CAPITAL LETTER SHTAPIC */ \ + 0x2C5C, /* GLAGOLITIC SMALL LETTER SHTAPIC */ }, \ + { 0x2C14, /* GLAGOLITIC CAPITAL LETTER SLOVO */ \ + 0x2C44, /* GLAGOLITIC SMALL LETTER SLOVO */ }, \ + { 0x2C24, /* GLAGOLITIC CAPITAL LETTER SMALL YUS */ \ + 0x2C54, /* GLAGOLITIC SMALL LETTER SMALL YUS */ }, \ + { 0x2C25, /* GLAGOLITIC CAPITAL LETTER SMALL YUS WITH TAIL */ \ + 0x2C55, /* GLAGOLITIC SMALL LETTER SMALL YUS WITH TAIL */ }, \ + { 0x2C22, /* GLAGOLITIC CAPITAL LETTER SPIDERY HA */ \ + 0x2C52, /* GLAGOLITIC SMALL LETTER SPIDERY HA */ }, \ + { 0x2C2D, /* GLAGOLITIC CAPITAL LETTER TROKUTASTI A */ \ + 0x2C5D, /* GLAGOLITIC SMALL LETTER TROKUTASTI A */ }, \ + { 0x2C1C, /* GLAGOLITIC CAPITAL LETTER TSI */ \ + 0x2C4C, /* GLAGOLITIC SMALL LETTER TSI */ }, \ + { 0x2C15, /* GLAGOLITIC CAPITAL LETTER TVRIDO */ \ + 0x2C45, /* GLAGOLITIC SMALL LETTER TVRIDO */ }, \ + { 0x2C16, /* GLAGOLITIC CAPITAL LETTER UKU */ \ + 0x2C46, /* GLAGOLITIC SMALL LETTER UKU */ }, \ + { 0x2C02, /* GLAGOLITIC CAPITAL LETTER VEDE */ \ + 0x2C32, /* GLAGOLITIC SMALL LETTER VEDE */ }, \ + { 0x2C21, /* GLAGOLITIC CAPITAL LETTER YATI */ \ + 0x2C51, /* GLAGOLITIC SMALL LETTER YATI */ }, \ + { 0x2C20, /* GLAGOLITIC CAPITAL LETTER YERI */ \ + 0x2C50, /* GLAGOLITIC SMALL LETTER YERI */ }, \ + { 0x2C1F, /* GLAGOLITIC CAPITAL LETTER YERU */ \ + 0x2C4F, /* GLAGOLITIC SMALL LETTER YERU */ }, \ + { 0x2C05, /* GLAGOLITIC CAPITAL LETTER YESTU */ \ + 0x2C35, /* GLAGOLITIC SMALL LETTER YESTU */ }, \ + { 0x2C26, /* GLAGOLITIC CAPITAL LETTER YO */ \ + 0x2C56, /* GLAGOLITIC SMALL LETTER YO */ }, \ + { 0x2C23, /* GLAGOLITIC CAPITAL LETTER YU */ \ + 0x2C53, /* GLAGOLITIC SMALL LETTER YU */ }, \ + { 0x2C08, /* GLAGOLITIC CAPITAL LETTER ZEMLJA */ \ + 0x2C38, /* GLAGOLITIC SMALL LETTER ZEMLJA */ }, \ + { 0x2C06, /* GLAGOLITIC CAPITAL LETTER ZHIVETE */ \ + 0x2C36, /* GLAGOLITIC SMALL LETTER ZHIVETE */ }, \ + { 0x0391, /* GREEK CAPITAL LETTER ALPHA */ \ + 0x03B1, /* GREEK SMALL LETTER ALPHA */ }, \ + { 0x1F09, /* GREEK CAPITAL LETTER ALPHA WITH DASIA */ \ + 0x1F01, /* GREEK SMALL LETTER ALPHA WITH DASIA */ }, \ + { 0x1F0D, /* GREEK CAPITAL LETTER ALPHA WITH DASIA AND OXIA */ \ + 0x1F05, /* GREEK SMALL LETTER ALPHA WITH DASIA AND OXIA */ }, \ + { 0x1F0F, /* GREEK CAPITAL LETTER ALPHA WITH DASIA AND PERISPOMENI */ \ + 0x1F07, /* GREEK SMALL LETTER ALPHA WITH DASIA AND PERISPOMENI */ }, \ + { 0x1F0B, /* GREEK CAPITAL LETTER ALPHA WITH DASIA AND VARIA */ \ + 0x1F03, /* GREEK SMALL LETTER ALPHA WITH DASIA AND VARIA */ }, \ + { 0x1FB9, /* GREEK CAPITAL LETTER ALPHA WITH MACRON */ \ + 0x1FB1, /* GREEK SMALL LETTER ALPHA WITH MACRON */ }, \ + { 0x1FBB, /* GREEK CAPITAL LETTER ALPHA WITH OXIA */ \ + 0x1F71, /* GREEK SMALL LETTER ALPHA WITH OXIA */ }, \ + { 0x1F08, /* GREEK CAPITAL LETTER ALPHA WITH PSILI */ \ + 0x1F00, /* GREEK SMALL LETTER ALPHA WITH PSILI */ }, \ + { 0x1F0C, /* GREEK CAPITAL LETTER ALPHA WITH PSILI AND OXIA */ \ + 0x1F04, /* GREEK SMALL LETTER ALPHA WITH PSILI AND OXIA */ }, \ + { 0x1F0E, /* GREEK CAPITAL LETTER ALPHA WITH PSILI AND PERISPOMENI */ \ + 0x1F06, /* GREEK SMALL LETTER ALPHA WITH PSILI AND PERISPOMENI */ }, \ + { 0x1F0A, /* GREEK CAPITAL LETTER ALPHA WITH PSILI AND VARIA */ \ + 0x1F02, /* GREEK SMALL LETTER ALPHA WITH PSILI AND VARIA */ }, \ + { 0x0386, /* GREEK CAPITAL LETTER ALPHA WITH TONOS */ \ + 0x03AC, /* GREEK SMALL LETTER ALPHA WITH TONOS */ }, \ + { 0x1FBA, /* GREEK CAPITAL LETTER ALPHA WITH VARIA */ \ + 0x1F70, /* GREEK SMALL LETTER ALPHA WITH VARIA */ }, \ + { 0x1FB8, /* GREEK CAPITAL LETTER ALPHA WITH VRACHY */ \ + 0x1FB0, /* GREEK SMALL LETTER ALPHA WITH VRACHY */ }, \ + { 0x0372, /* GREEK CAPITAL LETTER ARCHAIC SAMPI */ \ + 0x0373, /* GREEK SMALL LETTER ARCHAIC SAMPI */ }, \ + { 0x0392, /* GREEK CAPITAL LETTER BETA */ \ + 0x03B2, /* GREEK SMALL LETTER BETA */ }, \ + { 0x03A7, /* GREEK CAPITAL LETTER CHI */ \ + 0x03C7, /* GREEK SMALL LETTER CHI */ }, \ + { 0x0394, /* GREEK CAPITAL LETTER DELTA */ \ + 0x03B4, /* GREEK SMALL LETTER DELTA */ }, \ + { 0x0395, /* GREEK CAPITAL LETTER EPSILON */ \ + 0x03B5, /* GREEK SMALL LETTER EPSILON */ }, \ + { 0x1F19, /* GREEK CAPITAL LETTER EPSILON WITH DASIA */ \ + 0x1F11, /* GREEK SMALL LETTER EPSILON WITH DASIA */ }, \ + { 0x1F1D, /* GREEK CAPITAL LETTER EPSILON WITH DASIA AND OXIA */ \ + 0x1F15, /* GREEK SMALL LETTER EPSILON WITH DASIA AND OXIA */ }, \ + { 0x1F1B, /* GREEK CAPITAL LETTER EPSILON WITH DASIA AND VARIA */ \ + 0x1F13, /* GREEK SMALL LETTER EPSILON WITH DASIA AND VARIA */ }, \ + { 0x1FC9, /* GREEK CAPITAL LETTER EPSILON WITH OXIA */ \ + 0x1F73, /* GREEK SMALL LETTER EPSILON WITH OXIA */ }, \ + { 0x1F18, /* GREEK CAPITAL LETTER EPSILON WITH PSILI */ \ + 0x1F10, /* GREEK SMALL LETTER EPSILON WITH PSILI */ }, \ + { 0x1F1C, /* GREEK CAPITAL LETTER EPSILON WITH PSILI AND OXIA */ \ + 0x1F14, /* GREEK SMALL LETTER EPSILON WITH PSILI AND OXIA */ }, \ + { 0x1F1A, /* GREEK CAPITAL LETTER EPSILON WITH PSILI AND VARIA */ \ + 0x1F12, /* GREEK SMALL LETTER EPSILON WITH PSILI AND VARIA */ }, \ + { 0x0388, /* GREEK CAPITAL LETTER EPSILON WITH TONOS */ \ + 0x03AD, /* GREEK SMALL LETTER EPSILON WITH TONOS */ }, \ + { 0x1FC8, /* GREEK CAPITAL LETTER EPSILON WITH VARIA */ \ + 0x1F72, /* GREEK SMALL LETTER EPSILON WITH VARIA */ }, \ + { 0x0397, /* GREEK CAPITAL LETTER ETA */ \ + 0x03B7, /* GREEK SMALL LETTER ETA */ }, \ + { 0x1F29, /* GREEK CAPITAL LETTER ETA WITH DASIA */ \ + 0x1F21, /* GREEK SMALL LETTER ETA WITH DASIA */ }, \ + { 0x1F2D, /* GREEK CAPITAL LETTER ETA WITH DASIA AND OXIA */ \ + 0x1F25, /* GREEK SMALL LETTER ETA WITH DASIA AND OXIA */ }, \ + { 0x1F2F, /* GREEK CAPITAL LETTER ETA WITH DASIA AND PERISPOMENI */ \ + 0x1F27, /* GREEK SMALL LETTER ETA WITH DASIA AND PERISPOMENI */ }, \ + { 0x1F2B, /* GREEK CAPITAL LETTER ETA WITH DASIA AND VARIA */ \ + 0x1F23, /* GREEK SMALL LETTER ETA WITH DASIA AND VARIA */ }, \ + { 0x1FCB, /* GREEK CAPITAL LETTER ETA WITH OXIA */ \ + 0x1F75, /* GREEK SMALL LETTER ETA WITH OXIA */ }, \ + { 0x1F28, /* GREEK CAPITAL LETTER ETA WITH PSILI */ \ + 0x1F20, /* GREEK SMALL LETTER ETA WITH PSILI */ }, \ + { 0x1F2C, /* GREEK CAPITAL LETTER ETA WITH PSILI AND OXIA */ \ + 0x1F24, /* GREEK SMALL LETTER ETA WITH PSILI AND OXIA */ }, \ + { 0x1F2E, /* GREEK CAPITAL LETTER ETA WITH PSILI AND PERISPOMENI */ \ + 0x1F26, /* GREEK SMALL LETTER ETA WITH PSILI AND PERISPOMENI */ }, \ + { 0x1F2A, /* GREEK CAPITAL LETTER ETA WITH PSILI AND VARIA */ \ + 0x1F22, /* GREEK SMALL LETTER ETA WITH PSILI AND VARIA */ }, \ + { 0x0389, /* GREEK CAPITAL LETTER ETA WITH TONOS */ \ + 0x03AE, /* GREEK SMALL LETTER ETA WITH TONOS */ }, \ + { 0x1FCA, /* GREEK CAPITAL LETTER ETA WITH VARIA */ \ + 0x1F74, /* GREEK SMALL LETTER ETA WITH VARIA */ }, \ + { 0x0393, /* GREEK CAPITAL LETTER GAMMA */ \ + 0x03B3, /* GREEK SMALL LETTER GAMMA */ }, \ + { 0x0370, /* GREEK CAPITAL LETTER HETA */ \ + 0x0371, /* GREEK SMALL LETTER HETA */ }, \ + { 0x0399, /* GREEK CAPITAL LETTER IOTA */ \ + 0x03B9, /* GREEK SMALL LETTER IOTA */ }, \ + { 0x1F39, /* GREEK CAPITAL LETTER IOTA WITH DASIA */ \ + 0x1F31, /* GREEK SMALL LETTER IOTA WITH DASIA */ }, \ + { 0x1F3D, /* GREEK CAPITAL LETTER IOTA WITH DASIA AND OXIA */ \ + 0x1F35, /* GREEK SMALL LETTER IOTA WITH DASIA AND OXIA */ }, \ + { 0x1F3F, /* GREEK CAPITAL LETTER IOTA WITH DASIA AND PERISPOMENI */ \ + 0x1F37, /* GREEK SMALL LETTER IOTA WITH DASIA AND PERISPOMENI */ }, \ + { 0x1F3B, /* GREEK CAPITAL LETTER IOTA WITH DASIA AND VARIA */ \ + 0x1F33, /* GREEK SMALL LETTER IOTA WITH DASIA AND VARIA */ }, \ + { 0x03AA, /* GREEK CAPITAL LETTER IOTA WITH DIALYTIKA */ \ + 0x03CA, /* GREEK SMALL LETTER IOTA WITH DIALYTIKA */ }, \ + { 0x1FD9, /* GREEK CAPITAL LETTER IOTA WITH MACRON */ \ + 0x1FD1, /* GREEK SMALL LETTER IOTA WITH MACRON */ }, \ + { 0x1FDB, /* GREEK CAPITAL LETTER IOTA WITH OXIA */ \ + 0x1F77, /* GREEK SMALL LETTER IOTA WITH OXIA */ }, \ + { 0x1F38, /* GREEK CAPITAL LETTER IOTA WITH PSILI */ \ + 0x1F30, /* GREEK SMALL LETTER IOTA WITH PSILI */ }, \ + { 0x1F3C, /* GREEK CAPITAL LETTER IOTA WITH PSILI AND OXIA */ \ + 0x1F34, /* GREEK SMALL LETTER IOTA WITH PSILI AND OXIA */ }, \ + { 0x1F3E, /* GREEK CAPITAL LETTER IOTA WITH PSILI AND PERISPOMENI */ \ + 0x1F36, /* GREEK SMALL LETTER IOTA WITH PSILI AND PERISPOMENI */ }, \ + { 0x1F3A, /* GREEK CAPITAL LETTER IOTA WITH PSILI AND VARIA */ \ + 0x1F32, /* GREEK SMALL LETTER IOTA WITH PSILI AND VARIA */ }, \ + { 0x038A, /* GREEK CAPITAL LETTER IOTA WITH TONOS */ \ + 0x03AF, /* GREEK SMALL LETTER IOTA WITH TONOS */ }, \ + { 0x1FDA, /* GREEK CAPITAL LETTER IOTA WITH VARIA */ \ + 0x1F76, /* GREEK SMALL LETTER IOTA WITH VARIA */ }, \ + { 0x1FD8, /* GREEK CAPITAL LETTER IOTA WITH VRACHY */ \ + 0x1FD0, /* GREEK SMALL LETTER IOTA WITH VRACHY */ }, \ + { 0x039A, /* GREEK CAPITAL LETTER KAPPA */ \ + 0x03BA, /* GREEK SMALL LETTER KAPPA */ }, \ + { 0x039B, /* GREEK CAPITAL LETTER LAMDA */ \ + 0x03BB, /* GREEK SMALL LETTER LAMDA */ }, \ + { 0x039C, /* GREEK CAPITAL LETTER MU */ \ + 0x03BC, /* GREEK SMALL LETTER MU */ }, \ + { 0x039D, /* GREEK CAPITAL LETTER NU */ \ + 0x03BD, /* GREEK SMALL LETTER NU */ }, \ + { 0x03A9, /* GREEK CAPITAL LETTER OMEGA */ \ + 0x03C9, /* GREEK SMALL LETTER OMEGA */ }, \ + { 0x1F69, /* GREEK CAPITAL LETTER OMEGA WITH DASIA */ \ + 0x1F61, /* GREEK SMALL LETTER OMEGA WITH DASIA */ }, \ + { 0x1F6D, /* GREEK CAPITAL LETTER OMEGA WITH DASIA AND OXIA */ \ + 0x1F65, /* GREEK SMALL LETTER OMEGA WITH DASIA AND OXIA */ }, \ + { 0x1F6F, /* GREEK CAPITAL LETTER OMEGA WITH DASIA AND PERISPOMENI */ \ + 0x1F67, /* GREEK SMALL LETTER OMEGA WITH DASIA AND PERISPOMENI */ }, \ + { 0x1F6B, /* GREEK CAPITAL LETTER OMEGA WITH DASIA AND VARIA */ \ + 0x1F63, /* GREEK SMALL LETTER OMEGA WITH DASIA AND VARIA */ }, \ + { 0x1FFB, /* GREEK CAPITAL LETTER OMEGA WITH OXIA */ \ + 0x1F7D, /* GREEK SMALL LETTER OMEGA WITH OXIA */ }, \ + { 0x1F68, /* GREEK CAPITAL LETTER OMEGA WITH PSILI */ \ + 0x1F60, /* GREEK SMALL LETTER OMEGA WITH PSILI */ }, \ + { 0x1F6C, /* GREEK CAPITAL LETTER OMEGA WITH PSILI AND OXIA */ \ + 0x1F64, /* GREEK SMALL LETTER OMEGA WITH PSILI AND OXIA */ }, \ + { 0x1F6E, /* GREEK CAPITAL LETTER OMEGA WITH PSILI AND PERISPOMENI */ \ + 0x1F66, /* GREEK SMALL LETTER OMEGA WITH PSILI AND PERISPOMENI */ }, \ + { 0x1F6A, /* GREEK CAPITAL LETTER OMEGA WITH PSILI AND VARIA */ \ + 0x1F62, /* GREEK SMALL LETTER OMEGA WITH PSILI AND VARIA */ }, \ + { 0x038F, /* GREEK CAPITAL LETTER OMEGA WITH TONOS */ \ + 0x03CE, /* GREEK SMALL LETTER OMEGA WITH TONOS */ }, \ + { 0x1FFA, /* GREEK CAPITAL LETTER OMEGA WITH VARIA */ \ + 0x1F7C, /* GREEK SMALL LETTER OMEGA WITH VARIA */ }, \ + { 0x039F, /* GREEK CAPITAL LETTER OMICRON */ \ + 0x03BF, /* GREEK SMALL LETTER OMICRON */ }, \ + { 0x1F49, /* GREEK CAPITAL LETTER OMICRON WITH DASIA */ \ + 0x1F41, /* GREEK SMALL LETTER OMICRON WITH DASIA */ }, \ + { 0x1F4D, /* GREEK CAPITAL LETTER OMICRON WITH DASIA AND OXIA */ \ + 0x1F45, /* GREEK SMALL LETTER OMICRON WITH DASIA AND OXIA */ }, \ + { 0x1F4B, /* GREEK CAPITAL LETTER OMICRON WITH DASIA AND VARIA */ \ + 0x1F43, /* GREEK SMALL LETTER OMICRON WITH DASIA AND VARIA */ }, \ + { 0x1FF9, /* GREEK CAPITAL LETTER OMICRON WITH OXIA */ \ + 0x1F79, /* GREEK SMALL LETTER OMICRON WITH OXIA */ }, \ + { 0x1F48, /* GREEK CAPITAL LETTER OMICRON WITH PSILI */ \ + 0x1F40, /* GREEK SMALL LETTER OMICRON WITH PSILI */ }, \ + { 0x1F4C, /* GREEK CAPITAL LETTER OMICRON WITH PSILI AND OXIA */ \ + 0x1F44, /* GREEK SMALL LETTER OMICRON WITH PSILI AND OXIA */ }, \ + { 0x1F4A, /* GREEK CAPITAL LETTER OMICRON WITH PSILI AND VARIA */ \ + 0x1F42, /* GREEK SMALL LETTER OMICRON WITH PSILI AND VARIA */ }, \ + { 0x038C, /* GREEK CAPITAL LETTER OMICRON WITH TONOS */ \ + 0x03CC, /* GREEK SMALL LETTER OMICRON WITH TONOS */ }, \ + { 0x1FF8, /* GREEK CAPITAL LETTER OMICRON WITH VARIA */ \ + 0x1F78, /* GREEK SMALL LETTER OMICRON WITH VARIA */ }, \ + { 0x0376, /* GREEK CAPITAL LETTER PAMPHYLIAN DIGAMMA */ \ + 0x0377, /* GREEK SMALL LETTER PAMPHYLIAN DIGAMMA */ }, \ + { 0x03A6, /* GREEK CAPITAL LETTER PHI */ \ + 0x03C6, /* GREEK SMALL LETTER PHI */ }, \ + { 0x03A0, /* GREEK CAPITAL LETTER PI */ \ + 0x03C0, /* GREEK SMALL LETTER PI */ }, \ + { 0x03A8, /* GREEK CAPITAL LETTER PSI */ \ + 0x03C8, /* GREEK SMALL LETTER PSI */ }, \ + { 0x03A1, /* GREEK CAPITAL LETTER RHO */ \ + 0x03C1, /* GREEK SMALL LETTER RHO */ }, \ + { 0x1FEC, /* GREEK CAPITAL LETTER RHO WITH DASIA */ \ + 0x1FE5, /* GREEK SMALL LETTER RHO WITH DASIA */ }, \ + { 0x03FA, /* GREEK CAPITAL LETTER SAN */ \ + 0x03FB, /* GREEK SMALL LETTER SAN */ }, \ + { 0x03F7, /* GREEK CAPITAL LETTER SHO */ \ + 0x03F8, /* GREEK SMALL LETTER SHO */ }, \ + { 0x03A3, /* GREEK CAPITAL LETTER SIGMA */ \ + 0x03C3, /* GREEK SMALL LETTER SIGMA */ }, \ + { 0x03A4, /* GREEK CAPITAL LETTER TAU */ \ + 0x03C4, /* GREEK SMALL LETTER TAU */ }, \ + { 0x0398, /* GREEK CAPITAL LETTER THETA */ \ + 0x03B8, /* GREEK SMALL LETTER THETA */ }, \ + { 0x03A5, /* GREEK CAPITAL LETTER UPSILON */ \ + 0x03C5, /* GREEK SMALL LETTER UPSILON */ }, \ + { 0x1F59, /* GREEK CAPITAL LETTER UPSILON WITH DASIA */ \ + 0x1F51, /* GREEK SMALL LETTER UPSILON WITH DASIA */ }, \ + { 0x1F5D, /* GREEK CAPITAL LETTER UPSILON WITH DASIA AND OXIA */ \ + 0x1F55, /* GREEK SMALL LETTER UPSILON WITH DASIA AND OXIA */ }, \ + { 0x1F5F, /* GREEK CAPITAL LETTER UPSILON WITH DASIA AND PERISPOMENI */ \ + 0x1F57, /* GREEK SMALL LETTER UPSILON WITH DASIA AND PERISPOMENI */ }, \ + { 0x1F5B, /* GREEK CAPITAL LETTER UPSILON WITH DASIA AND VARIA */ \ + 0x1F53, /* GREEK SMALL LETTER UPSILON WITH DASIA AND VARIA */ }, \ + { 0x03AB, /* GREEK CAPITAL LETTER UPSILON WITH DIALYTIKA */ \ + 0x03CB, /* GREEK SMALL LETTER UPSILON WITH DIALYTIKA */ }, \ + { 0x1FE9, /* GREEK CAPITAL LETTER UPSILON WITH MACRON */ \ + 0x1FE1, /* GREEK SMALL LETTER UPSILON WITH MACRON */ }, \ + { 0x1FEB, /* GREEK CAPITAL LETTER UPSILON WITH OXIA */ \ + 0x1F7B, /* GREEK SMALL LETTER UPSILON WITH OXIA */ }, \ + { 0x038E, /* GREEK CAPITAL LETTER UPSILON WITH TONOS */ \ + 0x03CD, /* GREEK SMALL LETTER UPSILON WITH TONOS */ }, \ + { 0x1FEA, /* GREEK CAPITAL LETTER UPSILON WITH VARIA */ \ + 0x1F7A, /* GREEK SMALL LETTER UPSILON WITH VARIA */ }, \ + { 0x1FE8, /* GREEK CAPITAL LETTER UPSILON WITH VRACHY */ \ + 0x1FE0, /* GREEK SMALL LETTER UPSILON WITH VRACHY */ }, \ + { 0x039E, /* GREEK CAPITAL LETTER XI */ \ + 0x03BE, /* GREEK SMALL LETTER XI */ }, \ + { 0x0396, /* GREEK CAPITAL LETTER ZETA */ \ + 0x03B6, /* GREEK SMALL LETTER ZETA */ }, \ + { 0x0041, /* LATIN CAPITAL LETTER A */ \ + 0x0061, /* LATIN SMALL LETTER A */ }, \ + { 0x00C1, /* LATIN CAPITAL LETTER A WITH ACUTE */ \ + 0x00E1, /* LATIN SMALL LETTER A WITH ACUTE */ }, \ + { 0x0102, /* LATIN CAPITAL LETTER A WITH BREVE */ \ + 0x0103, /* LATIN SMALL LETTER A WITH BREVE */ }, \ + { 0x1EAE, /* LATIN CAPITAL LETTER A WITH BREVE AND ACUTE */ \ + 0x1EAF, /* LATIN SMALL LETTER A WITH BREVE AND ACUTE */ }, \ + { 0x1EB6, /* LATIN CAPITAL LETTER A WITH BREVE AND DOT BELOW */ \ + 0x1EB7, /* LATIN SMALL LETTER A WITH BREVE AND DOT BELOW */ }, \ + { 0x1EB0, /* LATIN CAPITAL LETTER A WITH BREVE AND GRAVE */ \ + 0x1EB1, /* LATIN SMALL LETTER A WITH BREVE AND GRAVE */ }, \ + { 0x1EB2, /* LATIN CAPITAL LETTER A WITH BREVE AND HOOK ABOVE */ \ + 0x1EB3, /* LATIN SMALL LETTER A WITH BREVE AND HOOK ABOVE */ }, \ + { 0x1EB4, /* LATIN CAPITAL LETTER A WITH BREVE AND TILDE */ \ + 0x1EB5, /* LATIN SMALL LETTER A WITH BREVE AND TILDE */ }, \ + { 0x01CD, /* LATIN CAPITAL LETTER A WITH CARON */ \ + 0x01CE, /* LATIN SMALL LETTER A WITH CARON */ }, \ + { 0x00C2, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX */ \ + 0x00E2, /* LATIN SMALL LETTER A WITH CIRCUMFLEX */ }, \ + { 0x1EA4, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND ACUTE */ \ + 0x1EA5, /* LATIN SMALL LETTER A WITH CIRCUMFLEX AND ACUTE */ }, \ + { 0x1EAC, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND DOT BELOW */ \ + 0x1EAD, /* LATIN SMALL LETTER A WITH CIRCUMFLEX AND DOT BELOW */ }, \ + { 0x1EA6, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND GRAVE */ \ + 0x1EA7, /* LATIN SMALL LETTER A WITH CIRCUMFLEX AND GRAVE */ }, \ + { 0x1EA8, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND HOOK ABOVE */ \ + 0x1EA9, /* LATIN SMALL LETTER A WITH CIRCUMFLEX AND HOOK ABOVE */ }, \ + { 0x1EAA, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND TILDE */ \ + 0x1EAB, /* LATIN SMALL LETTER A WITH CIRCUMFLEX AND TILDE */ }, \ + { 0x00C4, /* LATIN CAPITAL LETTER A WITH DIAERESIS */ \ + 0x00E4, /* LATIN SMALL LETTER A WITH DIAERESIS */ }, \ + { 0x01DE, /* LATIN CAPITAL LETTER A WITH DIAERESIS AND MACRON */ \ + 0x01DF, /* LATIN SMALL LETTER A WITH DIAERESIS AND MACRON */ }, \ + { 0x0226, /* LATIN CAPITAL LETTER A WITH DOT ABOVE */ \ + 0x0227, /* LATIN SMALL LETTER A WITH DOT ABOVE */ }, \ + { 0x01E0, /* LATIN CAPITAL LETTER A WITH DOT ABOVE AND MACRON */ \ + 0x01E1, /* LATIN SMALL LETTER A WITH DOT ABOVE AND MACRON */ }, \ + { 0x1EA0, /* LATIN CAPITAL LETTER A WITH DOT BELOW */ \ + 0x1EA1, /* LATIN SMALL LETTER A WITH DOT BELOW */ }, \ + { 0x0200, /* LATIN CAPITAL LETTER A WITH DOUBLE GRAVE */ \ + 0x0201, /* LATIN SMALL LETTER A WITH DOUBLE GRAVE */ }, \ + { 0x00C0, /* LATIN CAPITAL LETTER A WITH GRAVE */ \ + 0x00E0, /* LATIN SMALL LETTER A WITH GRAVE */ }, \ + { 0x1EA2, /* LATIN CAPITAL LETTER A WITH HOOK ABOVE */ \ + 0x1EA3, /* LATIN SMALL LETTER A WITH HOOK ABOVE */ }, \ + { 0x0202, /* LATIN CAPITAL LETTER A WITH INVERTED BREVE */ \ + 0x0203, /* LATIN SMALL LETTER A WITH INVERTED BREVE */ }, \ + { 0x0100, /* LATIN CAPITAL LETTER A WITH MACRON */ \ + 0x0101, /* LATIN SMALL LETTER A WITH MACRON */ }, \ + { 0x0104, /* LATIN CAPITAL LETTER A WITH OGONEK */ \ + 0x0105, /* LATIN SMALL LETTER A WITH OGONEK */ }, \ + { 0x00C5, /* LATIN CAPITAL LETTER A WITH RING ABOVE */ \ + 0x00E5, /* LATIN SMALL LETTER A WITH RING ABOVE */ }, \ + { 0x01FA, /* LATIN CAPITAL LETTER A WITH RING ABOVE AND ACUTE */ \ + 0x01FB, /* LATIN SMALL LETTER A WITH RING ABOVE AND ACUTE */ }, \ + { 0x1E00, /* LATIN CAPITAL LETTER A WITH RING BELOW */ \ + 0x1E01, /* LATIN SMALL LETTER A WITH RING BELOW */ }, \ + { 0x023A, /* LATIN CAPITAL LETTER A WITH STROKE */ \ + 0x2C65, /* LATIN SMALL LETTER A WITH STROKE */ }, \ + { 0x00C3, /* LATIN CAPITAL LETTER A WITH TILDE */ \ + 0x00E3, /* LATIN SMALL LETTER A WITH TILDE */ }, \ + { 0xA732, /* LATIN CAPITAL LETTER AA */ \ + 0xA733, /* LATIN SMALL LETTER AA */ }, \ + { 0x00C6, /* LATIN CAPITAL LETTER AE */ \ + 0x00E6, /* LATIN SMALL LETTER AE */ }, \ + { 0x01FC, /* LATIN CAPITAL LETTER AE WITH ACUTE */ \ + 0x01FD, /* LATIN SMALL LETTER AE WITH ACUTE */ }, \ + { 0x01E2, /* LATIN CAPITAL LETTER AE WITH MACRON */ \ + 0x01E3, /* LATIN SMALL LETTER AE WITH MACRON */ }, \ + { 0x2C6D, /* LATIN CAPITAL LETTER ALPHA */ \ + 0x0251, /* LATIN SMALL LETTER ALPHA */ }, \ + { 0xA734, /* LATIN CAPITAL LETTER AO */ \ + 0xA735, /* LATIN SMALL LETTER AO */ }, \ + { 0xA736, /* LATIN CAPITAL LETTER AU */ \ + 0xA737, /* LATIN SMALL LETTER AU */ }, \ + { 0xA738, /* LATIN CAPITAL LETTER AV */ \ + 0xA739, /* LATIN SMALL LETTER AV */ }, \ + { 0xA73A, /* LATIN CAPITAL LETTER AV WITH HORIZONTAL BAR */ \ + 0xA73B, /* LATIN SMALL LETTER AV WITH HORIZONTAL BAR */ }, \ + { 0xA73C, /* LATIN CAPITAL LETTER AY */ \ + 0xA73D, /* LATIN SMALL LETTER AY */ }, \ + { 0x0042, /* LATIN CAPITAL LETTER B */ \ + 0x0062, /* LATIN SMALL LETTER B */ }, \ + { 0x1E02, /* LATIN CAPITAL LETTER B WITH DOT ABOVE */ \ + 0x1E03, /* LATIN SMALL LETTER B WITH DOT ABOVE */ }, \ + { 0x1E04, /* LATIN CAPITAL LETTER B WITH DOT BELOW */ \ + 0x1E05, /* LATIN SMALL LETTER B WITH DOT BELOW */ }, \ + { 0xA796, /* LATIN CAPITAL LETTER B WITH FLOURISH */ \ + 0xA797, /* LATIN SMALL LETTER B WITH FLOURISH */ }, \ + { 0x0181, /* LATIN CAPITAL LETTER B WITH HOOK */ \ + 0x0253, /* LATIN SMALL LETTER B WITH HOOK */ }, \ + { 0x1E06, /* LATIN CAPITAL LETTER B WITH LINE BELOW */ \ + 0x1E07, /* LATIN SMALL LETTER B WITH LINE BELOW */ }, \ + { 0x0243, /* LATIN CAPITAL LETTER B WITH STROKE */ \ + 0x0180, /* LATIN SMALL LETTER B WITH STROKE */ }, \ + { 0x0182, /* LATIN CAPITAL LETTER B WITH TOPBAR */ \ + 0x0183, /* LATIN SMALL LETTER B WITH TOPBAR */ }, \ + { 0xA7B4, /* LATIN CAPITAL LETTER BETA */ \ + 0xA7B5, /* LATIN SMALL LETTER BETA */ }, \ + { 0xA746, /* LATIN CAPITAL LETTER BROKEN L */ \ + 0xA747, /* LATIN SMALL LETTER BROKEN L */ }, \ + { 0x0043, /* LATIN CAPITAL LETTER C */ \ + 0x0063, /* LATIN SMALL LETTER C */ }, \ + { 0x0106, /* LATIN CAPITAL LETTER C WITH ACUTE */ \ + 0x0107, /* LATIN SMALL LETTER C WITH ACUTE */ }, \ + { 0xA792, /* LATIN CAPITAL LETTER C WITH BAR */ \ + 0xA793, /* LATIN SMALL LETTER C WITH BAR */ }, \ + { 0x010C, /* LATIN CAPITAL LETTER C WITH CARON */ \ + 0x010D, /* LATIN SMALL LETTER C WITH CARON */ }, \ + { 0x00C7, /* LATIN CAPITAL LETTER C WITH CEDILLA */ \ + 0x00E7, /* LATIN SMALL LETTER C WITH CEDILLA */ }, \ + { 0x1E08, /* LATIN CAPITAL LETTER C WITH CEDILLA AND ACUTE */ \ + 0x1E09, /* LATIN SMALL LETTER C WITH CEDILLA AND ACUTE */ }, \ + { 0x0108, /* LATIN CAPITAL LETTER C WITH CIRCUMFLEX */ \ + 0x0109, /* LATIN SMALL LETTER C WITH CIRCUMFLEX */ }, \ + { 0x010A, /* LATIN CAPITAL LETTER C WITH DOT ABOVE */ \ + 0x010B, /* LATIN SMALL LETTER C WITH DOT ABOVE */ }, \ + { 0x0187, /* LATIN CAPITAL LETTER C WITH HOOK */ \ + 0x0188, /* LATIN SMALL LETTER C WITH HOOK */ }, \ + { 0x023B, /* LATIN CAPITAL LETTER C WITH STROKE */ \ + 0x023C, /* LATIN SMALL LETTER C WITH STROKE */ }, \ + { 0xA7B3, /* LATIN CAPITAL LETTER CHI */ \ + 0xAB53, /* LATIN SMALL LETTER CHI */ }, \ + { 0xA76E, /* LATIN CAPITAL LETTER CON */ \ + 0xA76F, /* LATIN SMALL LETTER CON */ }, \ + { 0xA72C, /* LATIN CAPITAL LETTER CUATRILLO */ \ + 0xA72D, /* LATIN SMALL LETTER CUATRILLO */ }, \ + { 0xA72E, /* LATIN CAPITAL LETTER CUATRILLO WITH COMMA */ \ + 0xA72F, /* LATIN SMALL LETTER CUATRILLO WITH COMMA */ }, \ + { 0x0044, /* LATIN CAPITAL LETTER D */ \ + 0x0064, /* LATIN SMALL LETTER D */ }, \ + { 0x010E, /* LATIN CAPITAL LETTER D WITH CARON */ \ + 0x010F, /* LATIN SMALL LETTER D WITH CARON */ }, \ + { 0x1E10, /* LATIN CAPITAL LETTER D WITH CEDILLA */ \ + 0x1E11, /* LATIN SMALL LETTER D WITH CEDILLA */ }, \ + { 0x1E12, /* LATIN CAPITAL LETTER D WITH CIRCUMFLEX BELOW */ \ + 0x1E13, /* LATIN SMALL LETTER D WITH CIRCUMFLEX BELOW */ }, \ + { 0x1E0A, /* LATIN CAPITAL LETTER D WITH DOT ABOVE */ \ + 0x1E0B, /* LATIN SMALL LETTER D WITH DOT ABOVE */ }, \ + { 0x1E0C, /* LATIN CAPITAL LETTER D WITH DOT BELOW */ \ + 0x1E0D, /* LATIN SMALL LETTER D WITH DOT BELOW */ }, \ + { 0x018A, /* LATIN CAPITAL LETTER D WITH HOOK */ \ + 0x0257, /* LATIN SMALL LETTER D WITH HOOK */ }, \ + { 0x1E0E, /* LATIN CAPITAL LETTER D WITH LINE BELOW */ \ + 0x1E0F, /* LATIN SMALL LETTER D WITH LINE BELOW */ }, \ + { 0x0110, /* LATIN CAPITAL LETTER D WITH STROKE */ \ + 0x0111, /* LATIN SMALL LETTER D WITH STROKE */ }, \ + { 0x018B, /* LATIN CAPITAL LETTER D WITH TOPBAR */ \ + 0x018C, /* LATIN SMALL LETTER D WITH TOPBAR */ }, \ + { 0x01F1, /* LATIN CAPITAL LETTER DZ */ \ + 0x01F3, /* LATIN SMALL LETTER DZ */ }, \ + { 0x01C4, /* LATIN CAPITAL LETTER DZ WITH CARON */ \ + 0x01C6, /* LATIN SMALL LETTER DZ WITH CARON */ }, \ + { 0x0045, /* LATIN CAPITAL LETTER E */ \ + 0x0065, /* LATIN SMALL LETTER E */ }, \ + { 0x00C9, /* LATIN CAPITAL LETTER E WITH ACUTE */ \ + 0x00E9, /* LATIN SMALL LETTER E WITH ACUTE */ }, \ + { 0x0114, /* LATIN CAPITAL LETTER E WITH BREVE */ \ + 0x0115, /* LATIN SMALL LETTER E WITH BREVE */ }, \ + { 0x011A, /* LATIN CAPITAL LETTER E WITH CARON */ \ + 0x011B, /* LATIN SMALL LETTER E WITH CARON */ }, \ + { 0x0228, /* LATIN CAPITAL LETTER E WITH CEDILLA */ \ + 0x0229, /* LATIN SMALL LETTER E WITH CEDILLA */ }, \ + { 0x1E1C, /* LATIN CAPITAL LETTER E WITH CEDILLA AND BREVE */ \ + 0x1E1D, /* LATIN SMALL LETTER E WITH CEDILLA AND BREVE */ }, \ + { 0x00CA, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX */ \ + 0x00EA, /* LATIN SMALL LETTER E WITH CIRCUMFLEX */ }, \ + { 0x1EBE, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND ACUTE */ \ + 0x1EBF, /* LATIN SMALL LETTER E WITH CIRCUMFLEX AND ACUTE */ }, \ + { 0x1EC6, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND DOT BELOW */ \ + 0x1EC7, /* LATIN SMALL LETTER E WITH CIRCUMFLEX AND DOT BELOW */ }, \ + { 0x1EC0, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND GRAVE */ \ + 0x1EC1, /* LATIN SMALL LETTER E WITH CIRCUMFLEX AND GRAVE */ }, \ + { 0x1EC2, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND HOOK ABOVE */ \ + 0x1EC3, /* LATIN SMALL LETTER E WITH CIRCUMFLEX AND HOOK ABOVE */ }, \ + { 0x1EC4, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND TILDE */ \ + 0x1EC5, /* LATIN SMALL LETTER E WITH CIRCUMFLEX AND TILDE */ }, \ + { 0x1E18, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX BELOW */ \ + 0x1E19, /* LATIN SMALL LETTER E WITH CIRCUMFLEX BELOW */ }, \ + { 0x00CB, /* LATIN CAPITAL LETTER E WITH DIAERESIS */ \ + 0x00EB, /* LATIN SMALL LETTER E WITH DIAERESIS */ }, \ + { 0x0116, /* LATIN CAPITAL LETTER E WITH DOT ABOVE */ \ + 0x0117, /* LATIN SMALL LETTER E WITH DOT ABOVE */ }, \ + { 0x1EB8, /* LATIN CAPITAL LETTER E WITH DOT BELOW */ \ + 0x1EB9, /* LATIN SMALL LETTER E WITH DOT BELOW */ }, \ + { 0x0204, /* LATIN CAPITAL LETTER E WITH DOUBLE GRAVE */ \ + 0x0205, /* LATIN SMALL LETTER E WITH DOUBLE GRAVE */ }, \ + { 0x00C8, /* LATIN CAPITAL LETTER E WITH GRAVE */ \ + 0x00E8, /* LATIN SMALL LETTER E WITH GRAVE */ }, \ + { 0x1EBA, /* LATIN CAPITAL LETTER E WITH HOOK ABOVE */ \ + 0x1EBB, /* LATIN SMALL LETTER E WITH HOOK ABOVE */ }, \ + { 0x0206, /* LATIN CAPITAL LETTER E WITH INVERTED BREVE */ \ + 0x0207, /* LATIN SMALL LETTER E WITH INVERTED BREVE */ }, \ + { 0x0112, /* LATIN CAPITAL LETTER E WITH MACRON */ \ + 0x0113, /* LATIN SMALL LETTER E WITH MACRON */ }, \ + { 0x1E16, /* LATIN CAPITAL LETTER E WITH MACRON AND ACUTE */ \ + 0x1E17, /* LATIN SMALL LETTER E WITH MACRON AND ACUTE */ }, \ + { 0x1E14, /* LATIN CAPITAL LETTER E WITH MACRON AND GRAVE */ \ + 0x1E15, /* LATIN SMALL LETTER E WITH MACRON AND GRAVE */ }, \ + { 0x0118, /* LATIN CAPITAL LETTER E WITH OGONEK */ \ + 0x0119, /* LATIN SMALL LETTER E WITH OGONEK */ }, \ + { 0x0246, /* LATIN CAPITAL LETTER E WITH STROKE */ \ + 0x0247, /* LATIN SMALL LETTER E WITH STROKE */ }, \ + { 0x1EBC, /* LATIN CAPITAL LETTER E WITH TILDE */ \ + 0x1EBD, /* LATIN SMALL LETTER E WITH TILDE */ }, \ + { 0x1E1A, /* LATIN CAPITAL LETTER E WITH TILDE BELOW */ \ + 0x1E1B, /* LATIN SMALL LETTER E WITH TILDE BELOW */ }, \ + { 0xA724, /* LATIN CAPITAL LETTER EGYPTOLOGICAL AIN */ \ + 0xA725, /* LATIN SMALL LETTER EGYPTOLOGICAL AIN */ }, \ + { 0xA722, /* LATIN CAPITAL LETTER EGYPTOLOGICAL ALEF */ \ + 0xA723, /* LATIN SMALL LETTER EGYPTOLOGICAL ALEF */ }, \ + { 0x014A, /* LATIN CAPITAL LETTER ENG */ \ + 0x014B, /* LATIN SMALL LETTER ENG */ }, \ + { 0x01A9, /* LATIN CAPITAL LETTER ESH */ \ + 0x0283, /* LATIN SMALL LETTER ESH */ }, \ + { 0xA76A, /* LATIN CAPITAL LETTER ET */ \ + 0xA76B, /* LATIN SMALL LETTER ET */ }, \ + { 0x00D0, /* LATIN CAPITAL LETTER ETH */ \ + 0x00F0, /* LATIN SMALL LETTER ETH */ }, \ + { 0x01B7, /* LATIN CAPITAL LETTER EZH */ \ + 0x0292, /* LATIN SMALL LETTER EZH */ }, \ + { 0x01B8, /* LATIN CAPITAL LETTER EZH REVERSED */ \ + 0x01B9, /* LATIN SMALL LETTER EZH REVERSED */ }, \ + { 0x01EE, /* LATIN CAPITAL LETTER EZH WITH CARON */ \ + 0x01EF, /* LATIN SMALL LETTER EZH WITH CARON */ }, \ + { 0x0046, /* LATIN CAPITAL LETTER F */ \ + 0x0066, /* LATIN SMALL LETTER F */ }, \ + { 0x1E1E, /* LATIN CAPITAL LETTER F WITH DOT ABOVE */ \ + 0x1E1F, /* LATIN SMALL LETTER F WITH DOT ABOVE */ }, \ + { 0x0191, /* LATIN CAPITAL LETTER F WITH HOOK */ \ + 0x0192, /* LATIN SMALL LETTER F WITH HOOK */ }, \ + { 0xA798, /* LATIN CAPITAL LETTER F WITH STROKE */ \ + 0xA799, /* LATIN SMALL LETTER F WITH STROKE */ }, \ + { 0x0047, /* LATIN CAPITAL LETTER G */ \ + 0x0067, /* LATIN SMALL LETTER G */ }, \ + { 0x01F4, /* LATIN CAPITAL LETTER G WITH ACUTE */ \ + 0x01F5, /* LATIN SMALL LETTER G WITH ACUTE */ }, \ + { 0x011E, /* LATIN CAPITAL LETTER G WITH BREVE */ \ + 0x011F, /* LATIN SMALL LETTER G WITH BREVE */ }, \ + { 0x01E6, /* LATIN CAPITAL LETTER G WITH CARON */ \ + 0x01E7, /* LATIN SMALL LETTER G WITH CARON */ }, \ + { 0x0122, /* LATIN CAPITAL LETTER G WITH CEDILLA */ \ + 0x0123, /* LATIN SMALL LETTER G WITH CEDILLA */ }, \ + { 0x011C, /* LATIN CAPITAL LETTER G WITH CIRCUMFLEX */ \ + 0x011D, /* LATIN SMALL LETTER G WITH CIRCUMFLEX */ }, \ + { 0x0120, /* LATIN CAPITAL LETTER G WITH DOT ABOVE */ \ + 0x0121, /* LATIN SMALL LETTER G WITH DOT ABOVE */ }, \ + { 0x0193, /* LATIN CAPITAL LETTER G WITH HOOK */ \ + 0x0260, /* LATIN SMALL LETTER G WITH HOOK */ }, \ + { 0x1E20, /* LATIN CAPITAL LETTER G WITH MACRON */ \ + 0x1E21, /* LATIN SMALL LETTER G WITH MACRON */ }, \ + { 0xA7A0, /* LATIN CAPITAL LETTER G WITH OBLIQUE STROKE */ \ + 0xA7A1, /* LATIN SMALL LETTER G WITH OBLIQUE STROKE */ }, \ + { 0x01E4, /* LATIN CAPITAL LETTER G WITH STROKE */ \ + 0x01E5, /* LATIN SMALL LETTER G WITH STROKE */ }, \ + { 0x0194, /* LATIN CAPITAL LETTER GAMMA */ \ + 0x0263, /* LATIN SMALL LETTER GAMMA */ }, \ + { 0x0241, /* LATIN CAPITAL LETTER GLOTTAL STOP */ \ + 0x0242, /* LATIN SMALL LETTER GLOTTAL STOP */ }, \ + { 0x0048, /* LATIN CAPITAL LETTER H */ \ + 0x0068, /* LATIN SMALL LETTER H */ }, \ + { 0x1E2A, /* LATIN CAPITAL LETTER H WITH BREVE BELOW */ \ + 0x1E2B, /* LATIN SMALL LETTER H WITH BREVE BELOW */ }, \ + { 0x021E, /* LATIN CAPITAL LETTER H WITH CARON */ \ + 0x021F, /* LATIN SMALL LETTER H WITH CARON */ }, \ + { 0x1E28, /* LATIN CAPITAL LETTER H WITH CEDILLA */ \ + 0x1E29, /* LATIN SMALL LETTER H WITH CEDILLA */ }, \ + { 0x0124, /* LATIN CAPITAL LETTER H WITH CIRCUMFLEX */ \ + 0x0125, /* LATIN SMALL LETTER H WITH CIRCUMFLEX */ }, \ + { 0x2C67, /* LATIN CAPITAL LETTER H WITH DESCENDER */ \ + 0x2C68, /* LATIN SMALL LETTER H WITH DESCENDER */ }, \ + { 0x1E26, /* LATIN CAPITAL LETTER H WITH DIAERESIS */ \ + 0x1E27, /* LATIN SMALL LETTER H WITH DIAERESIS */ }, \ + { 0x1E22, /* LATIN CAPITAL LETTER H WITH DOT ABOVE */ \ + 0x1E23, /* LATIN SMALL LETTER H WITH DOT ABOVE */ }, \ + { 0x1E24, /* LATIN CAPITAL LETTER H WITH DOT BELOW */ \ + 0x1E25, /* LATIN SMALL LETTER H WITH DOT BELOW */ }, \ + { 0xA7AA, /* LATIN CAPITAL LETTER H WITH HOOK */ \ + 0x0266, /* LATIN SMALL LETTER H WITH HOOK */ }, \ + { 0x0126, /* LATIN CAPITAL LETTER H WITH STROKE */ \ + 0x0127, /* LATIN SMALL LETTER H WITH STROKE */ }, \ + { 0x2C75, /* LATIN CAPITAL LETTER HALF H */ \ + 0x2C76, /* LATIN SMALL LETTER HALF H */ }, \ + { 0xA726, /* LATIN CAPITAL LETTER HENG */ \ + 0xA727, /* LATIN SMALL LETTER HENG */ }, \ + { 0x0049, /* LATIN CAPITAL LETTER I */ \ + 0x0069, /* LATIN SMALL LETTER I */ }, \ + { 0x00CD, /* LATIN CAPITAL LETTER I WITH ACUTE */ \ + 0x00ED, /* LATIN SMALL LETTER I WITH ACUTE */ }, \ + { 0x012C, /* LATIN CAPITAL LETTER I WITH BREVE */ \ + 0x012D, /* LATIN SMALL LETTER I WITH BREVE */ }, \ + { 0x01CF, /* LATIN CAPITAL LETTER I WITH CARON */ \ + 0x01D0, /* LATIN SMALL LETTER I WITH CARON */ }, \ + { 0x00CE, /* LATIN CAPITAL LETTER I WITH CIRCUMFLEX */ \ + 0x00EE, /* LATIN SMALL LETTER I WITH CIRCUMFLEX */ }, \ + { 0x00CF, /* LATIN CAPITAL LETTER I WITH DIAERESIS */ \ + 0x00EF, /* LATIN SMALL LETTER I WITH DIAERESIS */ }, \ + { 0x1E2E, /* LATIN CAPITAL LETTER I WITH DIAERESIS AND ACUTE */ \ + 0x1E2F, /* LATIN SMALL LETTER I WITH DIAERESIS AND ACUTE */ }, \ + { 0x1ECA, /* LATIN CAPITAL LETTER I WITH DOT BELOW */ \ + 0x1ECB, /* LATIN SMALL LETTER I WITH DOT BELOW */ }, \ + { 0x0208, /* LATIN CAPITAL LETTER I WITH DOUBLE GRAVE */ \ + 0x0209, /* LATIN SMALL LETTER I WITH DOUBLE GRAVE */ }, \ + { 0x00CC, /* LATIN CAPITAL LETTER I WITH GRAVE */ \ + 0x00EC, /* LATIN SMALL LETTER I WITH GRAVE */ }, \ + { 0x1EC8, /* LATIN CAPITAL LETTER I WITH HOOK ABOVE */ \ + 0x1EC9, /* LATIN SMALL LETTER I WITH HOOK ABOVE */ }, \ + { 0x020A, /* LATIN CAPITAL LETTER I WITH INVERTED BREVE */ \ + 0x020B, /* LATIN SMALL LETTER I WITH INVERTED BREVE */ }, \ + { 0x012A, /* LATIN CAPITAL LETTER I WITH MACRON */ \ + 0x012B, /* LATIN SMALL LETTER I WITH MACRON */ }, \ + { 0x012E, /* LATIN CAPITAL LETTER I WITH OGONEK */ \ + 0x012F, /* LATIN SMALL LETTER I WITH OGONEK */ }, \ + { 0x0197, /* LATIN CAPITAL LETTER I WITH STROKE */ \ + 0x0268, /* LATIN SMALL LETTER I WITH STROKE */ }, \ + { 0x0128, /* LATIN CAPITAL LETTER I WITH TILDE */ \ + 0x0129, /* LATIN SMALL LETTER I WITH TILDE */ }, \ + { 0x1E2C, /* LATIN CAPITAL LETTER I WITH TILDE BELOW */ \ + 0x1E2D, /* LATIN SMALL LETTER I WITH TILDE BELOW */ }, \ + { 0xA779, /* LATIN CAPITAL LETTER INSULAR D */ \ + 0xA77A, /* LATIN SMALL LETTER INSULAR D */ }, \ + { 0xA77B, /* LATIN CAPITAL LETTER INSULAR F */ \ + 0xA77C, /* LATIN SMALL LETTER INSULAR F */ }, \ + { 0xA77D, /* LATIN CAPITAL LETTER INSULAR G */ \ + 0x1D79, /* LATIN SMALL LETTER INSULAR G */ }, \ + { 0xA782, /* LATIN CAPITAL LETTER INSULAR R */ \ + 0xA783, /* LATIN SMALL LETTER INSULAR R */ }, \ + { 0xA784, /* LATIN CAPITAL LETTER INSULAR S */ \ + 0xA785, /* LATIN SMALL LETTER INSULAR S */ }, \ + { 0xA786, /* LATIN CAPITAL LETTER INSULAR T */ \ + 0xA787, /* LATIN SMALL LETTER INSULAR T */ }, \ + { 0x0196, /* LATIN CAPITAL LETTER IOTA */ \ + 0x0269, /* LATIN SMALL LETTER IOTA */ }, \ + { 0xA76C, /* LATIN CAPITAL LETTER IS */ \ + 0xA76D, /* LATIN SMALL LETTER IS */ }, \ + { 0x004A, /* LATIN CAPITAL LETTER J */ \ + 0x006A, /* LATIN SMALL LETTER J */ }, \ + { 0x0134, /* LATIN CAPITAL LETTER J WITH CIRCUMFLEX */ \ + 0x0135, /* LATIN SMALL LETTER J WITH CIRCUMFLEX */ }, \ + { 0xA7B2, /* LATIN CAPITAL LETTER J WITH CROSSED-TAIL */ \ + 0x029D, /* LATIN SMALL LETTER J WITH CROSSED-TAIL */ }, \ + { 0x0248, /* LATIN CAPITAL LETTER J WITH STROKE */ \ + 0x0249, /* LATIN SMALL LETTER J WITH STROKE */ }, \ + { 0x004B, /* LATIN CAPITAL LETTER K */ \ + 0x006B, /* LATIN SMALL LETTER K */ }, \ + { 0x1E30, /* LATIN CAPITAL LETTER K WITH ACUTE */ \ + 0x1E31, /* LATIN SMALL LETTER K WITH ACUTE */ }, \ + { 0x01E8, /* LATIN CAPITAL LETTER K WITH CARON */ \ + 0x01E9, /* LATIN SMALL LETTER K WITH CARON */ }, \ + { 0x0136, /* LATIN CAPITAL LETTER K WITH CEDILLA */ \ + 0x0137, /* LATIN SMALL LETTER K WITH CEDILLA */ }, \ + { 0x2C69, /* LATIN CAPITAL LETTER K WITH DESCENDER */ \ + 0x2C6A, /* LATIN SMALL LETTER K WITH DESCENDER */ }, \ + { 0xA742, /* LATIN CAPITAL LETTER K WITH DIAGONAL STROKE */ \ + 0xA743, /* LATIN SMALL LETTER K WITH DIAGONAL STROKE */ }, \ + { 0x1E32, /* LATIN CAPITAL LETTER K WITH DOT BELOW */ \ + 0x1E33, /* LATIN SMALL LETTER K WITH DOT BELOW */ }, \ + { 0x0198, /* LATIN CAPITAL LETTER K WITH HOOK */ \ + 0x0199, /* LATIN SMALL LETTER K WITH HOOK */ }, \ + { 0x1E34, /* LATIN CAPITAL LETTER K WITH LINE BELOW */ \ + 0x1E35, /* LATIN SMALL LETTER K WITH LINE BELOW */ }, \ + { 0xA7A2, /* LATIN CAPITAL LETTER K WITH OBLIQUE STROKE */ \ + 0xA7A3, /* LATIN SMALL LETTER K WITH OBLIQUE STROKE */ }, \ + { 0xA740, /* LATIN CAPITAL LETTER K WITH STROKE */ \ + 0xA741, /* LATIN SMALL LETTER K WITH STROKE */ }, \ + { 0xA744, /* LATIN CAPITAL LETTER K WITH STROKE AND DIAGONAL STROKE */ \ + 0xA745, /* LATIN SMALL LETTER K WITH STROKE AND DIAGONAL STROKE */ }, \ + { 0x004C, /* LATIN CAPITAL LETTER L */ \ + 0x006C, /* LATIN SMALL LETTER L */ }, \ + { 0x0139, /* LATIN CAPITAL LETTER L WITH ACUTE */ \ + 0x013A, /* LATIN SMALL LETTER L WITH ACUTE */ }, \ + { 0x023D, /* LATIN CAPITAL LETTER L WITH BAR */ \ + 0x019A, /* LATIN SMALL LETTER L WITH BAR */ }, \ + { 0xA7AD, /* LATIN CAPITAL LETTER L WITH BELT */ \ + 0x026C, /* LATIN SMALL LETTER L WITH BELT */ }, \ + { 0x013D, /* LATIN CAPITAL LETTER L WITH CARON */ \ + 0x013E, /* LATIN SMALL LETTER L WITH CARON */ }, \ + { 0x013B, /* LATIN CAPITAL LETTER L WITH CEDILLA */ \ + 0x013C, /* LATIN SMALL LETTER L WITH CEDILLA */ }, \ + { 0x1E3C, /* LATIN CAPITAL LETTER L WITH CIRCUMFLEX BELOW */ \ + 0x1E3D, /* LATIN SMALL LETTER L WITH CIRCUMFLEX BELOW */ }, \ + { 0x1E36, /* LATIN CAPITAL LETTER L WITH DOT BELOW */ \ + 0x1E37, /* LATIN SMALL LETTER L WITH DOT BELOW */ }, \ + { 0x1E38, /* LATIN CAPITAL LETTER L WITH DOT BELOW AND MACRON */ \ + 0x1E39, /* LATIN SMALL LETTER L WITH DOT BELOW AND MACRON */ }, \ + { 0x2C60, /* LATIN CAPITAL LETTER L WITH DOUBLE BAR */ \ + 0x2C61, /* LATIN SMALL LETTER L WITH DOUBLE BAR */ }, \ + { 0xA748, /* LATIN CAPITAL LETTER L WITH HIGH STROKE */ \ + 0xA749, /* LATIN SMALL LETTER L WITH HIGH STROKE */ }, \ + { 0x1E3A, /* LATIN CAPITAL LETTER L WITH LINE BELOW */ \ + 0x1E3B, /* LATIN SMALL LETTER L WITH LINE BELOW */ }, \ + { 0x013F, /* LATIN CAPITAL LETTER L WITH MIDDLE DOT */ \ + 0x0140, /* LATIN SMALL LETTER L WITH MIDDLE DOT */ }, \ + { 0x2C62, /* LATIN CAPITAL LETTER L WITH MIDDLE TILDE */ \ + 0x026B, /* LATIN SMALL LETTER L WITH MIDDLE TILDE */ }, \ + { 0x0141, /* LATIN CAPITAL LETTER L WITH STROKE */ \ + 0x0142, /* LATIN SMALL LETTER L WITH STROKE */ }, \ + { 0x01C7, /* LATIN CAPITAL LETTER LJ */ \ + 0x01C9, /* LATIN SMALL LETTER LJ */ }, \ + { 0x004D, /* LATIN CAPITAL LETTER M */ \ + 0x006D, /* LATIN SMALL LETTER M */ }, \ + { 0x1E3E, /* LATIN CAPITAL LETTER M WITH ACUTE */ \ + 0x1E3F, /* LATIN SMALL LETTER M WITH ACUTE */ }, \ + { 0x1E40, /* LATIN CAPITAL LETTER M WITH DOT ABOVE */ \ + 0x1E41, /* LATIN SMALL LETTER M WITH DOT ABOVE */ }, \ + { 0x1E42, /* LATIN CAPITAL LETTER M WITH DOT BELOW */ \ + 0x1E43, /* LATIN SMALL LETTER M WITH DOT BELOW */ }, \ + { 0x2C6E, /* LATIN CAPITAL LETTER M WITH HOOK */ \ + 0x0271, /* LATIN SMALL LETTER M WITH HOOK */ }, \ + { 0x1EFA, /* LATIN CAPITAL LETTER MIDDLE-WELSH LL */ \ + 0x1EFB, /* LATIN SMALL LETTER MIDDLE-WELSH LL */ }, \ + { 0x1EFC, /* LATIN CAPITAL LETTER MIDDLE-WELSH V */ \ + 0x1EFD, /* LATIN SMALL LETTER MIDDLE-WELSH V */ }, \ + { 0x004E, /* LATIN CAPITAL LETTER N */ \ + 0x006E, /* LATIN SMALL LETTER N */ }, \ + { 0x0143, /* LATIN CAPITAL LETTER N WITH ACUTE */ \ + 0x0144, /* LATIN SMALL LETTER N WITH ACUTE */ }, \ + { 0x0147, /* LATIN CAPITAL LETTER N WITH CARON */ \ + 0x0148, /* LATIN SMALL LETTER N WITH CARON */ }, \ + { 0x0145, /* LATIN CAPITAL LETTER N WITH CEDILLA */ \ + 0x0146, /* LATIN SMALL LETTER N WITH CEDILLA */ }, \ + { 0x1E4A, /* LATIN CAPITAL LETTER N WITH CIRCUMFLEX BELOW */ \ + 0x1E4B, /* LATIN SMALL LETTER N WITH CIRCUMFLEX BELOW */ }, \ + { 0xA790, /* LATIN CAPITAL LETTER N WITH DESCENDER */ \ + 0xA791, /* LATIN SMALL LETTER N WITH DESCENDER */ }, \ + { 0x1E44, /* LATIN CAPITAL LETTER N WITH DOT ABOVE */ \ + 0x1E45, /* LATIN SMALL LETTER N WITH DOT ABOVE */ }, \ + { 0x1E46, /* LATIN CAPITAL LETTER N WITH DOT BELOW */ \ + 0x1E47, /* LATIN SMALL LETTER N WITH DOT BELOW */ }, \ + { 0x01F8, /* LATIN CAPITAL LETTER N WITH GRAVE */ \ + 0x01F9, /* LATIN SMALL LETTER N WITH GRAVE */ }, \ + { 0x019D, /* LATIN CAPITAL LETTER N WITH LEFT HOOK */ \ + 0x0272, /* LATIN SMALL LETTER N WITH LEFT HOOK */ }, \ + { 0x1E48, /* LATIN CAPITAL LETTER N WITH LINE BELOW */ \ + 0x1E49, /* LATIN SMALL LETTER N WITH LINE BELOW */ }, \ + { 0x0220, /* LATIN CAPITAL LETTER N WITH LONG RIGHT LEG */ \ + 0x019E, /* LATIN SMALL LETTER N WITH LONG RIGHT LEG */ }, \ + { 0xA7A4, /* LATIN CAPITAL LETTER N WITH OBLIQUE STROKE */ \ + 0xA7A5, /* LATIN SMALL LETTER N WITH OBLIQUE STROKE */ }, \ + { 0x00D1, /* LATIN CAPITAL LETTER N WITH TILDE */ \ + 0x00F1, /* LATIN SMALL LETTER N WITH TILDE */ }, \ + { 0x01CA, /* LATIN CAPITAL LETTER NJ */ \ + 0x01CC, /* LATIN SMALL LETTER NJ */ }, \ + { 0x004F, /* LATIN CAPITAL LETTER O */ \ + 0x006F, /* LATIN SMALL LETTER O */ }, \ + { 0x00D3, /* LATIN CAPITAL LETTER O WITH ACUTE */ \ + 0x00F3, /* LATIN SMALL LETTER O WITH ACUTE */ }, \ + { 0x014E, /* LATIN CAPITAL LETTER O WITH BREVE */ \ + 0x014F, /* LATIN SMALL LETTER O WITH BREVE */ }, \ + { 0x01D1, /* LATIN CAPITAL LETTER O WITH CARON */ \ + 0x01D2, /* LATIN SMALL LETTER O WITH CARON */ }, \ + { 0x00D4, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX */ \ + 0x00F4, /* LATIN SMALL LETTER O WITH CIRCUMFLEX */ }, \ + { 0x1ED0, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND ACUTE */ \ + 0x1ED1, /* LATIN SMALL LETTER O WITH CIRCUMFLEX AND ACUTE */ }, \ + { 0x1ED8, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND DOT BELOW */ \ + 0x1ED9, /* LATIN SMALL LETTER O WITH CIRCUMFLEX AND DOT BELOW */ }, \ + { 0x1ED2, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND GRAVE */ \ + 0x1ED3, /* LATIN SMALL LETTER O WITH CIRCUMFLEX AND GRAVE */ }, \ + { 0x1ED4, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND HOOK ABOVE */ \ + 0x1ED5, /* LATIN SMALL LETTER O WITH CIRCUMFLEX AND HOOK ABOVE */ }, \ + { 0x1ED6, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND TILDE */ \ + 0x1ED7, /* LATIN SMALL LETTER O WITH CIRCUMFLEX AND TILDE */ }, \ + { 0x00D6, /* LATIN CAPITAL LETTER O WITH DIAERESIS */ \ + 0x00F6, /* LATIN SMALL LETTER O WITH DIAERESIS */ }, \ + { 0x022A, /* LATIN CAPITAL LETTER O WITH DIAERESIS AND MACRON */ \ + 0x022B, /* LATIN SMALL LETTER O WITH DIAERESIS AND MACRON */ }, \ + { 0x022E, /* LATIN CAPITAL LETTER O WITH DOT ABOVE */ \ + 0x022F, /* LATIN SMALL LETTER O WITH DOT ABOVE */ }, \ + { 0x0230, /* LATIN CAPITAL LETTER O WITH DOT ABOVE AND MACRON */ \ + 0x0231, /* LATIN SMALL LETTER O WITH DOT ABOVE AND MACRON */ }, \ + { 0x1ECC, /* LATIN CAPITAL LETTER O WITH DOT BELOW */ \ + 0x1ECD, /* LATIN SMALL LETTER O WITH DOT BELOW */ }, \ + { 0x0150, /* LATIN CAPITAL LETTER O WITH DOUBLE ACUTE */ \ + 0x0151, /* LATIN SMALL LETTER O WITH DOUBLE ACUTE */ }, \ + { 0x020C, /* LATIN CAPITAL LETTER O WITH DOUBLE GRAVE */ \ + 0x020D, /* LATIN SMALL LETTER O WITH DOUBLE GRAVE */ }, \ + { 0x00D2, /* LATIN CAPITAL LETTER O WITH GRAVE */ \ + 0x00F2, /* LATIN SMALL LETTER O WITH GRAVE */ }, \ + { 0x1ECE, /* LATIN CAPITAL LETTER O WITH HOOK ABOVE */ \ + 0x1ECF, /* LATIN SMALL LETTER O WITH HOOK ABOVE */ }, \ + { 0x01A0, /* LATIN CAPITAL LETTER O WITH HORN */ \ + 0x01A1, /* LATIN SMALL LETTER O WITH HORN */ }, \ + { 0x1EDA, /* LATIN CAPITAL LETTER O WITH HORN AND ACUTE */ \ + 0x1EDB, /* LATIN SMALL LETTER O WITH HORN AND ACUTE */ }, \ + { 0x1EE2, /* LATIN CAPITAL LETTER O WITH HORN AND DOT BELOW */ \ + 0x1EE3, /* LATIN SMALL LETTER O WITH HORN AND DOT BELOW */ }, \ + { 0x1EDC, /* LATIN CAPITAL LETTER O WITH HORN AND GRAVE */ \ + 0x1EDD, /* LATIN SMALL LETTER O WITH HORN AND GRAVE */ }, \ + { 0x1EDE, /* LATIN CAPITAL LETTER O WITH HORN AND HOOK ABOVE */ \ + 0x1EDF, /* LATIN SMALL LETTER O WITH HORN AND HOOK ABOVE */ }, \ + { 0x1EE0, /* LATIN CAPITAL LETTER O WITH HORN AND TILDE */ \ + 0x1EE1, /* LATIN SMALL LETTER O WITH HORN AND TILDE */ }, \ + { 0x020E, /* LATIN CAPITAL LETTER O WITH INVERTED BREVE */ \ + 0x020F, /* LATIN SMALL LETTER O WITH INVERTED BREVE */ }, \ + { 0xA74A, /* LATIN CAPITAL LETTER O WITH LONG STROKE OVERLAY */ \ + 0xA74B, /* LATIN SMALL LETTER O WITH LONG STROKE OVERLAY */ }, \ + { 0xA74C, /* LATIN CAPITAL LETTER O WITH LOOP */ \ + 0xA74D, /* LATIN SMALL LETTER O WITH LOOP */ }, \ + { 0x014C, /* LATIN CAPITAL LETTER O WITH MACRON */ \ + 0x014D, /* LATIN SMALL LETTER O WITH MACRON */ }, \ + { 0x1E52, /* LATIN CAPITAL LETTER O WITH MACRON AND ACUTE */ \ + 0x1E53, /* LATIN SMALL LETTER O WITH MACRON AND ACUTE */ }, \ + { 0x1E50, /* LATIN CAPITAL LETTER O WITH MACRON AND GRAVE */ \ + 0x1E51, /* LATIN SMALL LETTER O WITH MACRON AND GRAVE */ }, \ + { 0x01EA, /* LATIN CAPITAL LETTER O WITH OGONEK */ \ + 0x01EB, /* LATIN SMALL LETTER O WITH OGONEK */ }, \ + { 0x01EC, /* LATIN CAPITAL LETTER O WITH OGONEK AND MACRON */ \ + 0x01ED, /* LATIN SMALL LETTER O WITH OGONEK AND MACRON */ }, \ + { 0x00D8, /* LATIN CAPITAL LETTER O WITH STROKE */ \ + 0x00F8, /* LATIN SMALL LETTER O WITH STROKE */ }, \ + { 0x01FE, /* LATIN CAPITAL LETTER O WITH STROKE AND ACUTE */ \ + 0x01FF, /* LATIN SMALL LETTER O WITH STROKE AND ACUTE */ }, \ + { 0x00D5, /* LATIN CAPITAL LETTER O WITH TILDE */ \ + 0x00F5, /* LATIN SMALL LETTER O WITH TILDE */ }, \ + { 0x1E4C, /* LATIN CAPITAL LETTER O WITH TILDE AND ACUTE */ \ + 0x1E4D, /* LATIN SMALL LETTER O WITH TILDE AND ACUTE */ }, \ + { 0x1E4E, /* LATIN CAPITAL LETTER O WITH TILDE AND DIAERESIS */ \ + 0x1E4F, /* LATIN SMALL LETTER O WITH TILDE AND DIAERESIS */ }, \ + { 0x022C, /* LATIN CAPITAL LETTER O WITH TILDE AND MACRON */ \ + 0x022D, /* LATIN SMALL LETTER O WITH TILDE AND MACRON */ }, \ + { 0x01A2, /* LATIN CAPITAL LETTER OI */ \ + 0x01A3, /* LATIN SMALL LETTER OI */ }, \ + { 0xA7B6, /* LATIN CAPITAL LETTER OMEGA */ \ + 0xA7B7, /* LATIN SMALL LETTER OMEGA */ }, \ + { 0xA74E, /* LATIN CAPITAL LETTER OO */ \ + 0xA74F, /* LATIN SMALL LETTER OO */ }, \ + { 0x0190, /* LATIN CAPITAL LETTER OPEN E */ \ + 0x025B, /* LATIN SMALL LETTER OPEN E */ }, \ + { 0x0186, /* LATIN CAPITAL LETTER OPEN O */ \ + 0x0254, /* LATIN SMALL LETTER OPEN O */ }, \ + { 0x0222, /* LATIN CAPITAL LETTER OU */ \ + 0x0223, /* LATIN SMALL LETTER OU */ }, \ + { 0x0050, /* LATIN CAPITAL LETTER P */ \ + 0x0070, /* LATIN SMALL LETTER P */ }, \ + { 0x1E54, /* LATIN CAPITAL LETTER P WITH ACUTE */ \ + 0x1E55, /* LATIN SMALL LETTER P WITH ACUTE */ }, \ + { 0x1E56, /* LATIN CAPITAL LETTER P WITH DOT ABOVE */ \ + 0x1E57, /* LATIN SMALL LETTER P WITH DOT ABOVE */ }, \ + { 0xA752, /* LATIN CAPITAL LETTER P WITH FLOURISH */ \ + 0xA753, /* LATIN SMALL LETTER P WITH FLOURISH */ }, \ + { 0x01A4, /* LATIN CAPITAL LETTER P WITH HOOK */ \ + 0x01A5, /* LATIN SMALL LETTER P WITH HOOK */ }, \ + { 0xA754, /* LATIN CAPITAL LETTER P WITH SQUIRREL TAIL */ \ + 0xA755, /* LATIN SMALL LETTER P WITH SQUIRREL TAIL */ }, \ + { 0x2C63, /* LATIN CAPITAL LETTER P WITH STROKE */ \ + 0x1D7D, /* LATIN SMALL LETTER P WITH STROKE */ }, \ + { 0xA750, /* LATIN CAPITAL LETTER P WITH STROKE THROUGH DESCENDER */ \ + 0xA751, /* LATIN SMALL LETTER P WITH STROKE THROUGH DESCENDER */ }, \ + { 0x0051, /* LATIN CAPITAL LETTER Q */ \ + 0x0071, /* LATIN SMALL LETTER Q */ }, \ + { 0xA758, /* LATIN CAPITAL LETTER Q WITH DIAGONAL STROKE */ \ + 0xA759, /* LATIN SMALL LETTER Q WITH DIAGONAL STROKE */ }, \ + { 0xA756, /* LATIN CAPITAL LETTER Q WITH STROKE THROUGH DESCENDER */ \ + 0xA757, /* LATIN SMALL LETTER Q WITH STROKE THROUGH DESCENDER */ }, \ + { 0x0052, /* LATIN CAPITAL LETTER R */ \ + 0x0072, /* LATIN SMALL LETTER R */ }, \ + { 0xA75A, /* LATIN CAPITAL LETTER R ROTUNDA */ \ + 0xA75B, /* LATIN SMALL LETTER R ROTUNDA */ }, \ + { 0x0154, /* LATIN CAPITAL LETTER R WITH ACUTE */ \ + 0x0155, /* LATIN SMALL LETTER R WITH ACUTE */ }, \ + { 0x0158, /* LATIN CAPITAL LETTER R WITH CARON */ \ + 0x0159, /* LATIN SMALL LETTER R WITH CARON */ }, \ + { 0x0156, /* LATIN CAPITAL LETTER R WITH CEDILLA */ \ + 0x0157, /* LATIN SMALL LETTER R WITH CEDILLA */ }, \ + { 0x1E58, /* LATIN CAPITAL LETTER R WITH DOT ABOVE */ \ + 0x1E59, /* LATIN SMALL LETTER R WITH DOT ABOVE */ }, \ + { 0x1E5A, /* LATIN CAPITAL LETTER R WITH DOT BELOW */ \ + 0x1E5B, /* LATIN SMALL LETTER R WITH DOT BELOW */ }, \ + { 0x1E5C, /* LATIN CAPITAL LETTER R WITH DOT BELOW AND MACRON */ \ + 0x1E5D, /* LATIN SMALL LETTER R WITH DOT BELOW AND MACRON */ }, \ + { 0x0210, /* LATIN CAPITAL LETTER R WITH DOUBLE GRAVE */ \ + 0x0211, /* LATIN SMALL LETTER R WITH DOUBLE GRAVE */ }, \ + { 0x0212, /* LATIN CAPITAL LETTER R WITH INVERTED BREVE */ \ + 0x0213, /* LATIN SMALL LETTER R WITH INVERTED BREVE */ }, \ + { 0x1E5E, /* LATIN CAPITAL LETTER R WITH LINE BELOW */ \ + 0x1E5F, /* LATIN SMALL LETTER R WITH LINE BELOW */ }, \ + { 0xA7A6, /* LATIN CAPITAL LETTER R WITH OBLIQUE STROKE */ \ + 0xA7A7, /* LATIN SMALL LETTER R WITH OBLIQUE STROKE */ }, \ + { 0x024C, /* LATIN CAPITAL LETTER R WITH STROKE */ \ + 0x024D, /* LATIN SMALL LETTER R WITH STROKE */ }, \ + { 0x2C64, /* LATIN CAPITAL LETTER R WITH TAIL */ \ + 0x027D, /* LATIN SMALL LETTER R WITH TAIL */ }, \ + { 0xA73E, /* LATIN CAPITAL LETTER REVERSED C WITH DOT */ \ + 0xA73F, /* LATIN SMALL LETTER REVERSED C WITH DOT */ }, \ + { 0x018E, /* LATIN CAPITAL LETTER REVERSED E */ \ + 0x0258, /* LATIN SMALL LETTER REVERSED E */ }, \ + { 0xA7AB, /* LATIN CAPITAL LETTER REVERSED OPEN E */ \ + 0x025C, /* LATIN SMALL LETTER REVERSED OPEN E */ }, \ + { 0xA75C, /* LATIN CAPITAL LETTER RUM ROTUNDA */ \ + 0xA75D, /* LATIN SMALL LETTER RUM ROTUNDA */ }, \ + { 0x0053, /* LATIN CAPITAL LETTER S */ \ + 0x0073, /* LATIN SMALL LETTER S */ }, \ + { 0x015A, /* LATIN CAPITAL LETTER S WITH ACUTE */ \ + 0x015B, /* LATIN SMALL LETTER S WITH ACUTE */ }, \ + { 0x1E64, /* LATIN CAPITAL LETTER S WITH ACUTE AND DOT ABOVE */ \ + 0x1E65, /* LATIN SMALL LETTER S WITH ACUTE AND DOT ABOVE */ }, \ + { 0x0160, /* LATIN CAPITAL LETTER S WITH CARON */ \ + 0x0161, /* LATIN SMALL LETTER S WITH CARON */ }, \ + { 0x1E66, /* LATIN CAPITAL LETTER S WITH CARON AND DOT ABOVE */ \ + 0x1E67, /* LATIN SMALL LETTER S WITH CARON AND DOT ABOVE */ }, \ + { 0x015E, /* LATIN CAPITAL LETTER S WITH CEDILLA */ \ + 0x015F, /* LATIN SMALL LETTER S WITH CEDILLA */ }, \ + { 0x015C, /* LATIN CAPITAL LETTER S WITH CIRCUMFLEX */ \ + 0x015D, /* LATIN SMALL LETTER S WITH CIRCUMFLEX */ }, \ + { 0x0218, /* LATIN CAPITAL LETTER S WITH COMMA BELOW */ \ + 0x0219, /* LATIN SMALL LETTER S WITH COMMA BELOW */ }, \ + { 0x1E60, /* LATIN CAPITAL LETTER S WITH DOT ABOVE */ \ + 0x1E61, /* LATIN SMALL LETTER S WITH DOT ABOVE */ }, \ + { 0x1E62, /* LATIN CAPITAL LETTER S WITH DOT BELOW */ \ + 0x1E63, /* LATIN SMALL LETTER S WITH DOT BELOW */ }, \ + { 0x1E68, /* LATIN CAPITAL LETTER S WITH DOT BELOW AND DOT ABOVE */ \ + 0x1E69, /* LATIN SMALL LETTER S WITH DOT BELOW AND DOT ABOVE */ }, \ + { 0xA7A8, /* LATIN CAPITAL LETTER S WITH OBLIQUE STROKE */ \ + 0xA7A9, /* LATIN SMALL LETTER S WITH OBLIQUE STROKE */ }, \ + { 0x2C7E, /* LATIN CAPITAL LETTER S WITH SWASH TAIL */ \ + 0x023F, /* LATIN SMALL LETTER S WITH SWASH TAIL */ }, \ + { 0xA78B, /* LATIN CAPITAL LETTER SALTILLO */ \ + 0xA78C, /* LATIN SMALL LETTER SALTILLO */ }, \ + { 0x018F, /* LATIN CAPITAL LETTER SCHWA */ \ + 0x0259, /* LATIN SMALL LETTER SCHWA */ }, \ + { 0xA7AC, /* LATIN CAPITAL LETTER SCRIPT G */ \ + 0x0261, /* LATIN SMALL LETTER SCRIPT G */ }, \ + { 0x1E9E, /* LATIN CAPITAL LETTER SHARP S */ \ + 0x00DF, /* LATIN SMALL LETTER SHARP S */ }, \ + { 0x0054, /* LATIN CAPITAL LETTER T */ \ + 0x0074, /* LATIN SMALL LETTER T */ }, \ + { 0x0164, /* LATIN CAPITAL LETTER T WITH CARON */ \ + 0x0165, /* LATIN SMALL LETTER T WITH CARON */ }, \ + { 0x0162, /* LATIN CAPITAL LETTER T WITH CEDILLA */ \ + 0x0163, /* LATIN SMALL LETTER T WITH CEDILLA */ }, \ + { 0x1E70, /* LATIN CAPITAL LETTER T WITH CIRCUMFLEX BELOW */ \ + 0x1E71, /* LATIN SMALL LETTER T WITH CIRCUMFLEX BELOW */ }, \ + { 0x021A, /* LATIN CAPITAL LETTER T WITH COMMA BELOW */ \ + 0x021B, /* LATIN SMALL LETTER T WITH COMMA BELOW */ }, \ + { 0x023E, /* LATIN CAPITAL LETTER T WITH DIAGONAL STROKE */ \ + 0x2C66, /* LATIN SMALL LETTER T WITH DIAGONAL STROKE */ }, \ + { 0x1E6A, /* LATIN CAPITAL LETTER T WITH DOT ABOVE */ \ + 0x1E6B, /* LATIN SMALL LETTER T WITH DOT ABOVE */ }, \ + { 0x1E6C, /* LATIN CAPITAL LETTER T WITH DOT BELOW */ \ + 0x1E6D, /* LATIN SMALL LETTER T WITH DOT BELOW */ }, \ + { 0x01AC, /* LATIN CAPITAL LETTER T WITH HOOK */ \ + 0x01AD, /* LATIN SMALL LETTER T WITH HOOK */ }, \ + { 0x1E6E, /* LATIN CAPITAL LETTER T WITH LINE BELOW */ \ + 0x1E6F, /* LATIN SMALL LETTER T WITH LINE BELOW */ }, \ + { 0x01AE, /* LATIN CAPITAL LETTER T WITH RETROFLEX HOOK */ \ + 0x0288, /* LATIN SMALL LETTER T WITH RETROFLEX HOOK */ }, \ + { 0x0166, /* LATIN CAPITAL LETTER T WITH STROKE */ \ + 0x0167, /* LATIN SMALL LETTER T WITH STROKE */ }, \ + { 0x00DE, /* LATIN CAPITAL LETTER THORN */ \ + 0x00FE, /* LATIN SMALL LETTER THORN */ }, \ + { 0xA764, /* LATIN CAPITAL LETTER THORN WITH STROKE */ \ + 0xA765, /* LATIN SMALL LETTER THORN WITH STROKE */ }, \ + { 0xA766, /* LATIN CAPITAL LETTER THORN WITH STROKE THROUGH DESCENDER */ \ + 0xA767, /* LATIN SMALL LETTER THORN WITH STROKE THROUGH DESCENDER */ }, \ + { 0x01BC, /* LATIN CAPITAL LETTER TONE FIVE */ \ + 0x01BD, /* LATIN SMALL LETTER TONE FIVE */ }, \ + { 0x0184, /* LATIN CAPITAL LETTER TONE SIX */ \ + 0x0185, /* LATIN SMALL LETTER TONE SIX */ }, \ + { 0x01A7, /* LATIN CAPITAL LETTER TONE TWO */ \ + 0x01A8, /* LATIN SMALL LETTER TONE TWO */ }, \ + { 0xA72A, /* LATIN CAPITAL LETTER TRESILLO */ \ + 0xA72B, /* LATIN SMALL LETTER TRESILLO */ }, \ + { 0x2C6F, /* LATIN CAPITAL LETTER TURNED A */ \ + 0x0250, /* LATIN SMALL LETTER TURNED A */ }, \ + { 0x2C70, /* LATIN CAPITAL LETTER TURNED ALPHA */ \ + 0x0252, /* LATIN SMALL LETTER TURNED ALPHA */ }, \ + { 0xA78D, /* LATIN CAPITAL LETTER TURNED H */ \ + 0x0265, /* LATIN SMALL LETTER TURNED H */ }, \ + { 0xA77E, /* LATIN CAPITAL LETTER TURNED INSULAR G */ \ + 0xA77F, /* LATIN SMALL LETTER TURNED INSULAR G */ }, \ + { 0xA7B0, /* LATIN CAPITAL LETTER TURNED K */ \ + 0x029E, /* LATIN SMALL LETTER TURNED K */ }, \ + { 0xA780, /* LATIN CAPITAL LETTER TURNED L */ \ + 0xA781, /* LATIN SMALL LETTER TURNED L */ }, \ + { 0x019C, /* LATIN CAPITAL LETTER TURNED M */ \ + 0x026F, /* LATIN SMALL LETTER TURNED M */ }, \ + { 0xA7B1, /* LATIN CAPITAL LETTER TURNED T */ \ + 0x0287, /* LATIN SMALL LETTER TURNED T */ }, \ + { 0x0245, /* LATIN CAPITAL LETTER TURNED V */ \ + 0x028C, /* LATIN SMALL LETTER TURNED V */ }, \ + { 0xA728, /* LATIN CAPITAL LETTER TZ */ \ + 0xA729, /* LATIN SMALL LETTER TZ */ }, \ + { 0x0055, /* LATIN CAPITAL LETTER U */ \ + 0x0075, /* LATIN SMALL LETTER U */ }, \ + { 0x0244, /* LATIN CAPITAL LETTER U BAR */ \ + 0x0289, /* LATIN SMALL LETTER U BAR */ }, \ + { 0x00DA, /* LATIN CAPITAL LETTER U WITH ACUTE */ \ + 0x00FA, /* LATIN SMALL LETTER U WITH ACUTE */ }, \ + { 0x016C, /* LATIN CAPITAL LETTER U WITH BREVE */ \ + 0x016D, /* LATIN SMALL LETTER U WITH BREVE */ }, \ + { 0x01D3, /* LATIN CAPITAL LETTER U WITH CARON */ \ + 0x01D4, /* LATIN SMALL LETTER U WITH CARON */ }, \ + { 0x00DB, /* LATIN CAPITAL LETTER U WITH CIRCUMFLEX */ \ + 0x00FB, /* LATIN SMALL LETTER U WITH CIRCUMFLEX */ }, \ + { 0x1E76, /* LATIN CAPITAL LETTER U WITH CIRCUMFLEX BELOW */ \ + 0x1E77, /* LATIN SMALL LETTER U WITH CIRCUMFLEX BELOW */ }, \ + { 0x00DC, /* LATIN CAPITAL LETTER U WITH DIAERESIS */ \ + 0x00FC, /* LATIN SMALL LETTER U WITH DIAERESIS */ }, \ + { 0x01D7, /* LATIN CAPITAL LETTER U WITH DIAERESIS AND ACUTE */ \ + 0x01D8, /* LATIN SMALL LETTER U WITH DIAERESIS AND ACUTE */ }, \ + { 0x01D9, /* LATIN CAPITAL LETTER U WITH DIAERESIS AND CARON */ \ + 0x01DA, /* LATIN SMALL LETTER U WITH DIAERESIS AND CARON */ }, \ + { 0x01DB, /* LATIN CAPITAL LETTER U WITH DIAERESIS AND GRAVE */ \ + 0x01DC, /* LATIN SMALL LETTER U WITH DIAERESIS AND GRAVE */ }, \ + { 0x01D5, /* LATIN CAPITAL LETTER U WITH DIAERESIS AND MACRON */ \ + 0x01D6, /* LATIN SMALL LETTER U WITH DIAERESIS AND MACRON */ }, \ + { 0x1E72, /* LATIN CAPITAL LETTER U WITH DIAERESIS BELOW */ \ + 0x1E73, /* LATIN SMALL LETTER U WITH DIAERESIS BELOW */ }, \ + { 0x1EE4, /* LATIN CAPITAL LETTER U WITH DOT BELOW */ \ + 0x1EE5, /* LATIN SMALL LETTER U WITH DOT BELOW */ }, \ + { 0x0170, /* LATIN CAPITAL LETTER U WITH DOUBLE ACUTE */ \ + 0x0171, /* LATIN SMALL LETTER U WITH DOUBLE ACUTE */ }, \ + { 0x0214, /* LATIN CAPITAL LETTER U WITH DOUBLE GRAVE */ \ + 0x0215, /* LATIN SMALL LETTER U WITH DOUBLE GRAVE */ }, \ + { 0x00D9, /* LATIN CAPITAL LETTER U WITH GRAVE */ \ + 0x00F9, /* LATIN SMALL LETTER U WITH GRAVE */ }, \ + { 0x1EE6, /* LATIN CAPITAL LETTER U WITH HOOK ABOVE */ \ + 0x1EE7, /* LATIN SMALL LETTER U WITH HOOK ABOVE */ }, \ + { 0x01AF, /* LATIN CAPITAL LETTER U WITH HORN */ \ + 0x01B0, /* LATIN SMALL LETTER U WITH HORN */ }, \ + { 0x1EE8, /* LATIN CAPITAL LETTER U WITH HORN AND ACUTE */ \ + 0x1EE9, /* LATIN SMALL LETTER U WITH HORN AND ACUTE */ }, \ + { 0x1EF0, /* LATIN CAPITAL LETTER U WITH HORN AND DOT BELOW */ \ + 0x1EF1, /* LATIN SMALL LETTER U WITH HORN AND DOT BELOW */ }, \ + { 0x1EEA, /* LATIN CAPITAL LETTER U WITH HORN AND GRAVE */ \ + 0x1EEB, /* LATIN SMALL LETTER U WITH HORN AND GRAVE */ }, \ + { 0x1EEC, /* LATIN CAPITAL LETTER U WITH HORN AND HOOK ABOVE */ \ + 0x1EED, /* LATIN SMALL LETTER U WITH HORN AND HOOK ABOVE */ }, \ + { 0x1EEE, /* LATIN CAPITAL LETTER U WITH HORN AND TILDE */ \ + 0x1EEF, /* LATIN SMALL LETTER U WITH HORN AND TILDE */ }, \ + { 0x0216, /* LATIN CAPITAL LETTER U WITH INVERTED BREVE */ \ + 0x0217, /* LATIN SMALL LETTER U WITH INVERTED BREVE */ }, \ + { 0x016A, /* LATIN CAPITAL LETTER U WITH MACRON */ \ + 0x016B, /* LATIN SMALL LETTER U WITH MACRON */ }, \ + { 0x1E7A, /* LATIN CAPITAL LETTER U WITH MACRON AND DIAERESIS */ \ + 0x1E7B, /* LATIN SMALL LETTER U WITH MACRON AND DIAERESIS */ }, \ + { 0x0172, /* LATIN CAPITAL LETTER U WITH OGONEK */ \ + 0x0173, /* LATIN SMALL LETTER U WITH OGONEK */ }, \ + { 0x016E, /* LATIN CAPITAL LETTER U WITH RING ABOVE */ \ + 0x016F, /* LATIN SMALL LETTER U WITH RING ABOVE */ }, \ + { 0xA7B8, /* LATIN CAPITAL LETTER U WITH STROKE */ \ + 0xA7B9, /* LATIN SMALL LETTER U WITH STROKE */ }, \ + { 0x0168, /* LATIN CAPITAL LETTER U WITH TILDE */ \ + 0x0169, /* LATIN SMALL LETTER U WITH TILDE */ }, \ + { 0x1E78, /* LATIN CAPITAL LETTER U WITH TILDE AND ACUTE */ \ + 0x1E79, /* LATIN SMALL LETTER U WITH TILDE AND ACUTE */ }, \ + { 0x1E74, /* LATIN CAPITAL LETTER U WITH TILDE BELOW */ \ + 0x1E75, /* LATIN SMALL LETTER U WITH TILDE BELOW */ }, \ + { 0x01B1, /* LATIN CAPITAL LETTER UPSILON */ \ + 0x028A, /* LATIN SMALL LETTER UPSILON */ }, \ + { 0x0056, /* LATIN CAPITAL LETTER V */ \ + 0x0076, /* LATIN SMALL LETTER V */ }, \ + { 0xA75E, /* LATIN CAPITAL LETTER V WITH DIAGONAL STROKE */ \ + 0xA75F, /* LATIN SMALL LETTER V WITH DIAGONAL STROKE */ }, \ + { 0x1E7E, /* LATIN CAPITAL LETTER V WITH DOT BELOW */ \ + 0x1E7F, /* LATIN SMALL LETTER V WITH DOT BELOW */ }, \ + { 0x01B2, /* LATIN CAPITAL LETTER V WITH HOOK */ \ + 0x028B, /* LATIN SMALL LETTER V WITH HOOK */ }, \ + { 0x1E7C, /* LATIN CAPITAL LETTER V WITH TILDE */ \ + 0x1E7D, /* LATIN SMALL LETTER V WITH TILDE */ }, \ + { 0xA768, /* LATIN CAPITAL LETTER VEND */ \ + 0xA769, /* LATIN SMALL LETTER VEND */ }, \ + { 0xA762, /* LATIN CAPITAL LETTER VISIGOTHIC Z */ \ + 0xA763, /* LATIN SMALL LETTER VISIGOTHIC Z */ }, \ + { 0xA79A, /* LATIN CAPITAL LETTER VOLAPUK AE */ \ + 0xA79B, /* LATIN SMALL LETTER VOLAPUK AE */ }, \ + { 0xA79C, /* LATIN CAPITAL LETTER VOLAPUK OE */ \ + 0xA79D, /* LATIN SMALL LETTER VOLAPUK OE */ }, \ + { 0xA79E, /* LATIN CAPITAL LETTER VOLAPUK UE */ \ + 0xA79F, /* LATIN SMALL LETTER VOLAPUK UE */ }, \ + { 0xA760, /* LATIN CAPITAL LETTER VY */ \ + 0xA761, /* LATIN SMALL LETTER VY */ }, \ + { 0x0057, /* LATIN CAPITAL LETTER W */ \ + 0x0077, /* LATIN SMALL LETTER W */ }, \ + { 0x1E82, /* LATIN CAPITAL LETTER W WITH ACUTE */ \ + 0x1E83, /* LATIN SMALL LETTER W WITH ACUTE */ }, \ + { 0x0174, /* LATIN CAPITAL LETTER W WITH CIRCUMFLEX */ \ + 0x0175, /* LATIN SMALL LETTER W WITH CIRCUMFLEX */ }, \ + { 0x1E84, /* LATIN CAPITAL LETTER W WITH DIAERESIS */ \ + 0x1E85, /* LATIN SMALL LETTER W WITH DIAERESIS */ }, \ + { 0x1E86, /* LATIN CAPITAL LETTER W WITH DOT ABOVE */ \ + 0x1E87, /* LATIN SMALL LETTER W WITH DOT ABOVE */ }, \ + { 0x1E88, /* LATIN CAPITAL LETTER W WITH DOT BELOW */ \ + 0x1E89, /* LATIN SMALL LETTER W WITH DOT BELOW */ }, \ + { 0x1E80, /* LATIN CAPITAL LETTER W WITH GRAVE */ \ + 0x1E81, /* LATIN SMALL LETTER W WITH GRAVE */ }, \ + { 0x2C72, /* LATIN CAPITAL LETTER W WITH HOOK */ \ + 0x2C73, /* LATIN SMALL LETTER W WITH HOOK */ }, \ + { 0x0058, /* LATIN CAPITAL LETTER X */ \ + 0x0078, /* LATIN SMALL LETTER X */ }, \ + { 0x1E8C, /* LATIN CAPITAL LETTER X WITH DIAERESIS */ \ + 0x1E8D, /* LATIN SMALL LETTER X WITH DIAERESIS */ }, \ + { 0x1E8A, /* LATIN CAPITAL LETTER X WITH DOT ABOVE */ \ + 0x1E8B, /* LATIN SMALL LETTER X WITH DOT ABOVE */ }, \ + { 0x0059, /* LATIN CAPITAL LETTER Y */ \ + 0x0079, /* LATIN SMALL LETTER Y */ }, \ + { 0x00DD, /* LATIN CAPITAL LETTER Y WITH ACUTE */ \ + 0x00FD, /* LATIN SMALL LETTER Y WITH ACUTE */ }, \ + { 0x0176, /* LATIN CAPITAL LETTER Y WITH CIRCUMFLEX */ \ + 0x0177, /* LATIN SMALL LETTER Y WITH CIRCUMFLEX */ }, \ + { 0x0178, /* LATIN CAPITAL LETTER Y WITH DIAERESIS */ \ + 0x00FF, /* LATIN SMALL LETTER Y WITH DIAERESIS */ }, \ + { 0x1E8E, /* LATIN CAPITAL LETTER Y WITH DOT ABOVE */ \ + 0x1E8F, /* LATIN SMALL LETTER Y WITH DOT ABOVE */ }, \ + { 0x1EF4, /* LATIN CAPITAL LETTER Y WITH DOT BELOW */ \ + 0x1EF5, /* LATIN SMALL LETTER Y WITH DOT BELOW */ }, \ + { 0x1EF2, /* LATIN CAPITAL LETTER Y WITH GRAVE */ \ + 0x1EF3, /* LATIN SMALL LETTER Y WITH GRAVE */ }, \ + { 0x01B3, /* LATIN CAPITAL LETTER Y WITH HOOK */ \ + 0x01B4, /* LATIN SMALL LETTER Y WITH HOOK */ }, \ + { 0x1EF6, /* LATIN CAPITAL LETTER Y WITH HOOK ABOVE */ \ + 0x1EF7, /* LATIN SMALL LETTER Y WITH HOOK ABOVE */ }, \ + { 0x1EFE, /* LATIN CAPITAL LETTER Y WITH LOOP */ \ + 0x1EFF, /* LATIN SMALL LETTER Y WITH LOOP */ }, \ + { 0x0232, /* LATIN CAPITAL LETTER Y WITH MACRON */ \ + 0x0233, /* LATIN SMALL LETTER Y WITH MACRON */ }, \ + { 0x024E, /* LATIN CAPITAL LETTER Y WITH STROKE */ \ + 0x024F, /* LATIN SMALL LETTER Y WITH STROKE */ }, \ + { 0x1EF8, /* LATIN CAPITAL LETTER Y WITH TILDE */ \ + 0x1EF9, /* LATIN SMALL LETTER Y WITH TILDE */ }, \ + { 0x021C, /* LATIN CAPITAL LETTER YOGH */ \ + 0x021D, /* LATIN SMALL LETTER YOGH */ }, \ + { 0x005A, /* LATIN CAPITAL LETTER Z */ \ + 0x007A, /* LATIN SMALL LETTER Z */ }, \ + { 0x0179, /* LATIN CAPITAL LETTER Z WITH ACUTE */ \ + 0x017A, /* LATIN SMALL LETTER Z WITH ACUTE */ }, \ + { 0x017D, /* LATIN CAPITAL LETTER Z WITH CARON */ \ + 0x017E, /* LATIN SMALL LETTER Z WITH CARON */ }, \ + { 0x1E90, /* LATIN CAPITAL LETTER Z WITH CIRCUMFLEX */ \ + 0x1E91, /* LATIN SMALL LETTER Z WITH CIRCUMFLEX */ }, \ + { 0x2C6B, /* LATIN CAPITAL LETTER Z WITH DESCENDER */ \ + 0x2C6C, /* LATIN SMALL LETTER Z WITH DESCENDER */ }, \ + { 0x017B, /* LATIN CAPITAL LETTER Z WITH DOT ABOVE */ \ + 0x017C, /* LATIN SMALL LETTER Z WITH DOT ABOVE */ }, \ + { 0x1E92, /* LATIN CAPITAL LETTER Z WITH DOT BELOW */ \ + 0x1E93, /* LATIN SMALL LETTER Z WITH DOT BELOW */ }, \ + { 0x0224, /* LATIN CAPITAL LETTER Z WITH HOOK */ \ + 0x0225, /* LATIN SMALL LETTER Z WITH HOOK */ }, \ + { 0x1E94, /* LATIN CAPITAL LETTER Z WITH LINE BELOW */ \ + 0x1E95, /* LATIN SMALL LETTER Z WITH LINE BELOW */ }, \ + { 0x01B5, /* LATIN CAPITAL LETTER Z WITH STROKE */ \ + 0x01B6, /* LATIN SMALL LETTER Z WITH STROKE */ }, \ + { 0x2C7F, /* LATIN CAPITAL LETTER Z WITH SWASH TAIL */ \ + 0x0240, /* LATIN SMALL LETTER Z WITH SWASH TAIL */ }, \ + { 0x0000, /* END OF LIST CAPITAL LETTERS */ \ + 0x0000, /* END OF LIST SMALL LETTERS */ }, \ +} + +/* + * Correspondence table for small and capital letters of codepage 437. + * Letters A-Z are handled in code. + */ +#define CP437_CAPITALIZATION_TABLE { \ + { 0x00C4, /* LATIN CAPITAL LETTER A WITH DIAERESIS */ \ + 0x00E4, /* LATIN SMALL LETTER A WITH DIAERESIS */ }, \ + { 0x00C5, /* LATIN CAPITAL LETTER A WITH RING ABOVE */ \ + 0x00E5, /* LATIN SMALL LETTER A WITH RING ABOVE */ }, \ + { 0x00C6, /* LATIN CAPITAL LETTER AE */ \ + 0x00E6, /* LATIN SMALL LETTER AE */ }, \ + { 0x00C7, /* LATIN CAPITAL LETTER C WITH CEDILLA */ \ + 0x00E7, /* LATIN SMALL LETTER C WITH CEDILLA */ }, \ + { 0x00C9, /* LATIN CAPITAL LETTER E WITH ACUTE */ \ + 0x00E9, /* LATIN SMALL LETTER E WITH ACUTE */ }, \ + { 0x00D1, /* LATIN CAPITAL LETTER N WITH TILDE */ \ + 0x00F1, /* LATIN SMALL LETTER N WITH TILDE */ }, \ + { 0x00D6, /* LATIN CAPITAL LETTER O WITH DIAERESIS */ \ + 0x00F6, /* LATIN SMALL LETTER O WITH DIAERESIS */ }, \ + { 0x00DC, /* LATIN CAPITAL LETTER U WITH DIAERESIS */ \ + 0x00FC, /* LATIN SMALL LETTER U WITH DIAERESIS */ }, \ + { 0x03A3, /* GREEK CAPITAL LETTER SIGMA */ \ + 0x03C3, /* GREEK SMALL LETTER SIGMA */ }, \ + { 0x03A6, /* GREEK CAPITAL LETTER PHI */ \ + 0x03C6, /* GREEK SMALL LETTER PHI */ }, \ + { 0x0000, 0x0000, }, \ +} + +/* + * Correspondence table for small and capital letters of codepage 1250. + * Letters A-Z are handled in code. + */ +#define CP1250_CAPITALIZATION_TABLE { \ + { 0x00C1, /* LATIN CAPITAL LETTER A WITH ACUTE */ \ + 0x00E1, /* LATIN SMALL LETTER A WITH ACUTE */ }, \ + { 0x00C2, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX */ \ + 0x00E2, /* LATIN SMALL LETTER A WITH CIRCUMFLEX */ }, \ + { 0x00C4, /* LATIN CAPITAL LETTER A WITH DIAERESIS */ \ + 0x00E4, /* LATIN SMALL LETTER A WITH DIAERESIS */ }, \ + { 0x00C7, /* LATIN CAPITAL LETTER C WITH CEDILLA */ \ + 0x00E7, /* LATIN SMALL LETTER C WITH CEDILLA */ }, \ + { 0x00C9, /* LATIN CAPITAL LETTER E WITH ACUTE */ \ + 0x00E9, /* LATIN SMALL LETTER E WITH ACUTE */ }, \ + { 0x00CB, /* LATIN CAPITAL LETTER E WITH DIAERESIS */ \ + 0x00EB, /* LATIN SMALL LETTER E WITH DIAERESIS */ }, \ + { 0x00CD, /* LATIN CAPITAL LETTER I WITH ACUTE */ \ + 0x00ED, /* LATIN SMALL LETTER I WITH ACUTE */ }, \ + { 0x00CE, /* LATIN CAPITAL LETTER I WITH CIRCUMFLEX */ \ + 0x00EE, /* LATIN SMALL LETTER I WITH CIRCUMFLEX */ }, \ + { 0x00D3, /* LATIN CAPITAL LETTER O WITH ACUTE */ \ + 0x00F3, /* LATIN SMALL LETTER O WITH ACUTE */ }, \ + { 0x00D4, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX */ \ + 0x00F4, /* LATIN SMALL LETTER O WITH CIRCUMFLEX */ }, \ + { 0x00D6, /* LATIN CAPITAL LETTER O WITH DIAERESIS */ \ + 0x00F6, /* LATIN SMALL LETTER O WITH DIAERESIS */ }, \ + { 0x00DA, /* LATIN CAPITAL LETTER U WITH ACUTE */ \ + 0x00FA, /* LATIN SMALL LETTER U WITH ACUTE */ }, \ + { 0x00DC, /* LATIN CAPITAL LETTER U WITH DIAERESIS */ \ + 0x00FC, /* LATIN SMALL LETTER U WITH DIAERESIS */ }, \ + { 0x00DD, /* LATIN CAPITAL LETTER Y WITH ACUTE */ \ + 0x00FD, /* LATIN SMALL LETTER Y WITH ACUTE */ }, \ + { 0x0102, /* LATIN CAPITAL LETTER A WITH BREVE */ \ + 0x0103, /* LATIN SMALL LETTER A WITH BREVE */ }, \ + { 0x0104, /* LATIN CAPITAL LETTER A WITH OGONEK */ \ + 0x0105, /* LATIN SMALL LETTER A WITH OGONEK */ }, \ + { 0x0106, /* LATIN CAPITAL LETTER C WITH ACUTE */ \ + 0x0107, /* LATIN SMALL LETTER C WITH ACUTE */ }, \ + { 0x010C, /* LATIN CAPITAL LETTER C WITH CARON */ \ + 0x010D, /* LATIN SMALL LETTER C WITH CARON */ }, \ + { 0x010E, /* LATIN CAPITAL LETTER D WITH CARON */ \ + 0x010F, /* LATIN SMALL LETTER D WITH CARON */ }, \ + { 0x0110, /* LATIN CAPITAL LETTER D WITH STROKE */ \ + 0x0111, /* LATIN SMALL LETTER D WITH STROKE */ }, \ + { 0x0118, /* LATIN CAPITAL LETTER E WITH OGONEK */ \ + 0x0119, /* LATIN SMALL LETTER E WITH OGONEK */ }, \ + { 0x011A, /* LATIN CAPITAL LETTER E WITH CARON */ \ + 0x011B, /* LATIN SMALL LETTER E WITH CARON */ }, \ + { 0x0139, /* LATIN CAPITAL LETTER L WITH ACUTE */ \ + 0x013A, /* LATIN SMALL LETTER L WITH ACUTE */ }, \ + { 0x013D, /* LATIN CAPITAL LETTER L WITH CARON */ \ + 0x013E, /* LATIN SMALL LETTER L WITH CARON */ }, \ + { 0x0141, /* LATIN CAPITAL LETTER L WITH STROKE */ \ + 0x0142, /* LATIN SMALL LETTER L WITH STROKE */ }, \ + { 0x0143, /* LATIN CAPITAL LETTER N WITH ACUTE */ \ + 0x0144, /* LATIN SMALL LETTER N WITH ACUTE */ }, \ + { 0x0147, /* LATIN CAPITAL LETTER N WITH CARON */ \ + 0x0148, /* LATIN SMALL LETTER N WITH CARON */ }, \ + { 0x0150, /* LATIN CAPITAL LETTER O WITH DOUBLE ACUTE */ \ + 0x0151, /* LATIN SMALL LETTER O WITH DOUBLE ACUTE */ }, \ + { 0x0154, /* LATIN CAPITAL LETTER R WITH ACUTE */ \ + 0x0155, /* LATIN SMALL LETTER R WITH ACUTE */ }, \ + { 0x0158, /* LATIN CAPITAL LETTER R WITH CARON */ \ + 0x0159, /* LATIN SMALL LETTER R WITH CARON */ }, \ + { 0x015A, /* LATIN CAPITAL LETTER S WITH ACUTE */ \ + 0x015B, /* LATIN SMALL LETTER S WITH ACUTE */ }, \ + { 0x015E, /* LATIN CAPITAL LETTER S WITH CEDILLA */ \ + 0x015F, /* LATIN SMALL LETTER S WITH CEDILLA */ }, \ + { 0x0160, /* LATIN CAPITAL LETTER S WITH CARON */ \ + 0x0161, /* LATIN SMALL LETTER S WITH CARON */ }, \ + { 0x0162, /* LATIN CAPITAL LETTER T WITH CEDILLA */ \ + 0x0163, /* LATIN SMALL LETTER T WITH CEDILLA */ }, \ + { 0x0164, /* LATIN CAPITAL LETTER T WITH CARON */ \ + 0x0165, /* LATIN SMALL LETTER T WITH CARON */ }, \ + { 0x016E, /* LATIN CAPITAL LETTER U WITH RING ABOVE */ \ + 0x016F, /* LATIN SMALL LETTER U WITH RING ABOVE */ }, \ + { 0x0170, /* LATIN CAPITAL LETTER U WITH DOUBLE ACUTE */ \ + 0x0171, /* LATIN SMALL LETTER U WITH DOUBLE ACUTE */ }, \ + { 0x0179, /* LATIN CAPITAL LETTER Z WITH ACUTE */ \ + 0x017A, /* LATIN SMALL LETTER Z WITH ACUTE */ }, \ + { 0x017B, /* LATIN CAPITAL LETTER Z WITH DOT ABOVE */ \ + 0x017C, /* LATIN SMALL LETTER Z WITH DOT ABOVE */ }, \ + { 0x017D, /* LATIN CAPITAL LETTER Z WITH CARON */ \ + 0x017E, /* LATIN SMALL LETTER Z WITH CARON */ }, \ + { 0x0000, 0x0000, }, \ +} diff --git a/roms/u-boot/include/cavium/atf.h b/roms/u-boot/include/cavium/atf.h new file mode 100644 index 000000000..3cf05c43d --- /dev/null +++ b/roms/u-boot/include/cavium/atf.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/** + * (C) Copyright 2014, Cavium Inc. +**/ +#ifndef __ATF_H__ +#define __ATF_H__ +#include + +ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size); +ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size); +ssize_t atf_get_pcount(void); +ssize_t atf_get_part(struct storage_partition *part, unsigned int index); +ssize_t atf_erase_nor(uintptr_t offset, size_t size); +ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size); +ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size); +ssize_t atf_dram_size(unsigned int node); +ssize_t atf_node_count(void); +ssize_t atf_env_count(void); +ssize_t atf_env_string(size_t index, char *str); + +#endif diff --git a/roms/u-boot/include/cavium/atf_part.h b/roms/u-boot/include/cavium/atf_part.h new file mode 100644 index 000000000..6c00b019c --- /dev/null +++ b/roms/u-boot/include/cavium/atf_part.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/** + * (C) Copyright 2014, Cavium Inc. +**/ + +#ifndef __ATF_PART_H__ +#define __ATF_PART_H__ + +struct storage_partition { + unsigned int type; + unsigned int size; + unsigned long offset; +}; + +enum { + PARTITION_NBL1FW_REST = 0, + PARTITION_BL2_BL31 = 1, + PARTITION_UBOOT = 2, + PARTITION_UEFI = 2, + PARTITION_KERNEL = 3, + PARTITION_DEVICE_TREE = 4, + PARTITION_LAST, +}; + +#endif diff --git a/roms/u-boot/include/cavium/thunderx_svc.h b/roms/u-boot/include/cavium/thunderx_svc.h new file mode 100644 index 000000000..de36d6623 --- /dev/null +++ b/roms/u-boot/include/cavium/thunderx_svc.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/** + * (C) Copyright 2014, Cavium Inc. +**/ + +#ifndef __THUNDERX_SVC_H__ +#define __THUNDERX_SVC_H__ + +/* SMC function IDs for general purpose queries */ + +#define THUNDERX_SVC_CALL_COUNT 0x4300ff00 +#define THUNDERX_SVC_UID 0x4300ff01 + +#define THUNDERX_SVC_VERSION 0x4300ff03 + +#define ARM_STD_SVC_VERSION 0x8400ff03 + +/* ThunderX Service Calls version numbers */ +#define THUNDERX_VERSION_MAJOR 0x0 +#define THUNDERX_VERSION_MINOR 0x1 + +#define THUNDERX_MMC_READ 0x43000101 +/* x1 - block address + * x2 - size + * x3 - buffer address + */ +#define THUNDERX_MMC_WRITE 0x43000102 +/* x1 - block address + * x2 - size + * x3 - buffer address + */ + +#define THUNDERX_NOR_READ 0x43000111 +/* x1 - block address + * x2 - size + * x3 - buffer address + */ +#define THUNDERX_NOR_WRITE 0x43000112 +/* x1 - block address + * x2 - size + * x3 - buffer address + */ +#define THUNDERX_NOR_ERASE 0x43000113 +/* x1 - block address + */ + +#define THUNDERX_PART_COUNT 0x43000201 +#define THUNDERX_GET_PART 0x43000202 +/* x1 - pointer to the buffer + * x2 - index + */ + +#define THUNDERX_DRAM_SIZE 0x43000301 +/* x1 - node number + */ + +#define THUNDERX_GTI_SYNC 0x43000401 + +#define THUNDERX_ENV_COUNT 0x43000501 +#define THUNDERX_ENV_STRING 0x43000502 +/* x1 - index + */ + +#define THUNDERX_NODE_COUNT 0x43000601 + +#endif /* __THUNDERX_SVC_H__ */ diff --git a/roms/u-boot/include/cbfs.h b/roms/u-boot/include/cbfs.h new file mode 100644 index 000000000..ae94f1dcd --- /dev/null +++ b/roms/u-boot/include/cbfs.h @@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + */ + +#ifndef __CBFS_H +#define __CBFS_H + +#include +#include + +struct cbfs_priv; + +enum cbfs_result { + CBFS_SUCCESS = 0, + CBFS_NOT_INITIALIZED, + CBFS_BAD_HEADER, + CBFS_BAD_FILE, + CBFS_FILE_NOT_FOUND +}; + +enum cbfs_filetype { + CBFS_TYPE_BOOTBLOCK = 0x01, + CBFS_TYPE_CBFSHEADER = 0x02, + CBFS_TYPE_STAGE = 0x10, + CBFS_TYPE_PAYLOAD = 0x20, + CBFS_TYPE_FIT = 0x21, + CBFS_TYPE_OPTIONROM = 0x30, + CBFS_TYPE_BOOTSPLASH = 0x40, + CBFS_TYPE_RAW = 0x50, + CBFS_TYPE_VSA = 0x51, + CBFS_TYPE_MBI = 0x52, + CBFS_TYPE_MICROCODE = 0x53, + CBFS_TYPE_FSP = 0x60, + CBFS_TYPE_MRC = 0x61, + CBFS_TYPE_MMA = 0x62, + CBFS_TYPE_EFI = 0x63, + CBFS_TYPE_STRUCT = 0x70, + CBFS_TYPE_CMOS_DEFAULT = 0xaa, + CBFS_TYPE_SPD = 0xab, + CBFS_TYPE_MRC_CACHE = 0xac, + CBFS_TYPE_CMOS_LAYOUT = 0x01aa +}; + +enum { + CBFS_HEADER_MAGIC = 0x4f524243, + CBFS_SIZE_UNKNOWN = 0xffffffff, + CBFS_ALIGN_SIZE = 0x40, +}; + +/** + * struct cbfs_header - header at the start of a CBFS region + * + * All fields use big-endian format. + * + * @magic: Magic number (CBFS_HEADER_MAGIC) + */ +struct cbfs_header { + u32 magic; + u32 version; + u32 rom_size; + u32 boot_block_size; + u32 align; + u32 offset; + u32 pad[2]; +} __packed; + +struct cbfs_fileheader { + u8 magic[8]; + u32 len; + u32 type; + /* offset to struct cbfs_file_attribute or 0 */ + u32 attributes_offset; + u32 offset; + char filename[]; +} __packed; + +/** + * These are standard values for the known compression alogrithms that coreboot + * knows about for stages and payloads. Of course, other CBFS users can use + * whatever values they want, as long as they understand them. + */ +#define CBFS_COMPRESS_NONE 0 +#define CBFS_COMPRESS_LZMA 1 +#define CBFS_COMPRESS_LZ4 2 + +/* + * Depending on how the header was initialized, it may be backed with 0x00 or + * 0xff, so support both + */ +#define CBFS_FILE_ATTR_TAG_UNUSED 0 +#define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff +#define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c +#define CBFS_FILE_ATTR_TAG_HASH 0x68736148 + +/* + * The common fields of extended cbfs file attributes. Attributes are expected + * to start with tag/len, then append their specific fields + */ +struct cbfs_file_attribute { + u32 tag; + /* len covers the whole structure, incl. tag and len */ + u32 len; + u8 data[0]; +} __packed; + +struct cbfs_file_attr_compression { + u32 tag; + u32 len; + /* whole file compression format. 0 if no compression. */ + u32 compression; + u32 decompressed_size; +} __packed; + +struct cbfs_file_attr_hash { + u32 tag; + u32 len; + u32 hash_type; + /* hash_data is len - sizeof(struct) bytes */ + u8 hash_data[]; +} __packed; + +struct cbfs_cachenode { + struct cbfs_cachenode *next; + void *data; + char *name; + u32 type; + u32 data_length; + u32 name_length; + u32 attr_offset; + u32 comp_algo; + u32 decomp_size; +}; + +/** + * file_cbfs_error() - Return a string describing the most recent error + * condition. + * + * @return A pointer to the constant string. + */ +const char *file_cbfs_error(void); + +/** + * cbfs_get_result() - Get the result of the last CBFS operation + * + *@return last result + */ +enum cbfs_result cbfs_get_result(void); + +/** + * file_cbfs_init() - Initialize the CBFS driver and load metadata into RAM. + * + * @end_of_rom: Points to the end of the ROM the CBFS should be read from + * @return 0 if OK, -ve on error + */ +int file_cbfs_init(ulong end_of_rom); + +/** + * file_cbfs_get_header() - Get the header structure for the current CBFS. + * + * @return A pointer to the constant structure, or NULL if there is none. + */ +const struct cbfs_header *file_cbfs_get_header(void); + +/** + * cbfs_get_first() - Get the first file in a CBFS + * + * @return pointer to first file, or NULL if it is empty + */ +const struct cbfs_cachenode *cbfs_get_first(const struct cbfs_priv *priv); + +/** + * cbfs_get_next() - Get the next file in a CBFS + * + * @filep: Pointer to current file; updated to point to the next file, if any, + * else NULL + */ +void cbfs_get_next(const struct cbfs_cachenode **filep); + +/** + * file_cbfs_get_first() - Get a handle for the first file in CBFS. + * + * @return A handle for the first file in CBFS, NULL on error. + */ +const struct cbfs_cachenode *file_cbfs_get_first(void); + +/** + * file_cbfs_get_next() - Get a handle to the file after this one in CBFS. + * + * @file: A pointer to the handle to advance. + */ +void file_cbfs_get_next(const struct cbfs_cachenode **file); + +/** + * file_cbfs_find() - Find a file with a particular name in CBFS. + * + * @name: The name to search for. + * + * @return A handle to the file, or NULL on error. + */ +const struct cbfs_cachenode *file_cbfs_find(const char *name); + +/** + * cbfs_find_file() - Find a file in a given CBFS + * + * @cbfs: CBFS to look in (use cbfs_init_mem() to set it up) + * @name: Filename to look for + * @return pointer to CBFS node if found, else NULL + */ +const struct cbfs_cachenode *cbfs_find_file(struct cbfs_priv *cbfs, + const char *name); + +/** + * cbfs_init_mem() - Set up a new CBFS + * + * @base: Base address of CBFS + * @size: Size of CBFS if known, else CBFS_SIZE_UNKNOWN + * @require_header: true to read a header at the start, false to not require one + * @cbfsp: Returns a pointer to CBFS on success + * @return 0 if OK, -ve on error + */ +int cbfs_init_mem(ulong base, ulong size, bool require_hdr, + struct cbfs_priv **privp); + +/***************************************************************************/ +/* All of the functions below can be used without first initializing CBFS. */ +/***************************************************************************/ + +/** + * file_cbfs_find_uncached() - Find a file in CBFS given the end of the ROM + * + * Note that @node should be declared by the caller. This design is to avoid + * the need for allocation here. + * + * @end_of_rom: Points to the end of the ROM the CBFS should be read from + * @name: The name to search for + * @node: Returns the contents of the node if found (i.e. copied into *node) + * @return 0 on success, -ENOENT if not found, -EFAULT on bad header + */ +int file_cbfs_find_uncached(ulong end_of_rom, const char *name, + struct cbfs_cachenode *node); + +/** + * file_cbfs_find_uncached_base() - Find a file in CBFS given the base address + * + * Note that @node should be declared by the caller. This design is to avoid + * the need for allocation here. + * + * @base: Points to the base of the CBFS + * @name: The name to search for + * @node: Returns the contents of the node if found (i.e. copied into *node) + * @return 0 on success, -ENOENT if not found, -EFAULT on bad header + */ +int file_cbfs_find_uncached_base(ulong base, const char *name, + struct cbfs_cachenode *node); + +/** + * file_cbfs_name() - Get the name of a file in CBFS. + * + * @file: The handle to the file. + * + * @return The name of the file, NULL on error. + */ +const char *file_cbfs_name(const struct cbfs_cachenode *file); + +/** + * file_cbfs_size() - Get the size of a file in CBFS. + * + * @file: The handle to the file. + * + * @return The size of the file, zero on error. + */ +u32 file_cbfs_size(const struct cbfs_cachenode *file); + +/** + * file_cbfs_type() - Get the type of a file in CBFS. + * + * @file: The handle to the file. + * + * @return The type of the file, zero on error. + */ +u32 file_cbfs_type(const struct cbfs_cachenode *file); + +/** + * file_cbfs_read() - Read a file from CBFS into RAM + * + * @file: A handle to the file to read. + * @buffer: Where to read it into memory. + * @maxsize: Maximum number of bytes to read + * + * @return If positive or zero, the number of characters read. If negative, an + * error occurred. + */ +long file_cbfs_read(const struct cbfs_cachenode *file, void *buffer, + unsigned long maxsize); + +#endif /* __CBFS_H */ diff --git a/roms/u-boot/include/charset.h b/roms/u-boot/include/charset.h new file mode 100644 index 000000000..b93d02309 --- /dev/null +++ b/roms/u-boot/include/charset.h @@ -0,0 +1,307 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * charset conversion utils + * + * Copyright (c) 2017 Rob Clark + */ + +#ifndef __CHARSET_H_ +#define __CHARSET_H_ + +#include +#include + +#define MAX_UTF8_PER_UTF16 3 + +/* + * codepage_437 - Unicode to codepage 437 translation table + */ +extern const u16 codepage_437[128]; + +/** + * console_read_unicode() - read Unicode code point from console + * + * @code: pointer to store Unicode code point + * Return: 0 = success + */ +int console_read_unicode(s32 *code); + +/** + * utf8_get() - get next UTF-8 code point from buffer + * + * @src: pointer to current byte, updated to point to next byte + * Return: code point, or 0 for end of string, or -1 if no legal + * code point is found. In case of an error src points to + * the incorrect byte. + */ +s32 utf8_get(const char **src); + +/** + * utf8_put() - write UTF-8 code point to buffer + * + * @code: code point + * @dst: pointer to destination buffer, updated to next position + * Return: -1 if the input parameters are invalid + */ +int utf8_put(s32 code, char **dst); + +/** + * utf8_utf16_strnlen() - length of a truncated utf-8 string after conversion + * to utf-16 + * + * @src: utf-8 string + * @count: maximum number of code points to convert + * Return: length in u16 after conversion to utf-16 without the + * trailing \0. If an invalid UTF-8 sequence is hit one + * u16 will be reserved for a replacement character. + */ +size_t utf8_utf16_strnlen(const char *src, size_t count); + +/** + * utf8_utf16_strlen() - length of a utf-8 string after conversion to utf-16 + * + * @a: utf-8 string + * Return: length in u16 after conversion to utf-16 without the + * trailing \0. If an invalid UTF-8 sequence is hit one + * u16 will be reserved for a replacement character. + */ +#define utf8_utf16_strlen(a) utf8_utf16_strnlen((a), SIZE_MAX) + +/** + * utf8_utf16_strncpy() - copy utf-8 string to utf-16 string + * + * @dst: destination buffer + * @src: source buffer + * @count: maximum number of code points to copy + * Return: -1 if the input parameters are invalid + */ +int utf8_utf16_strncpy(u16 **dst, const char *src, size_t count); + +/** + * utf8_utf16_strcpy() - copy utf-8 string to utf-16 string + * + * @d: destination buffer + * @s: source buffer + * Return: -1 if the input parameters are invalid + */ +#define utf8_utf16_strcpy(d, s) utf8_utf16_strncpy((d), (s), SIZE_MAX) + +/** + * utf16_get() - get next UTF-16 code point from buffer + * + * @src: pointer to current word, updated to point to next word + * Return: code point, or 0 for end of string, or -1 if no legal + * code point is found. In case of an error src points to + * the incorrect word. + */ +s32 utf16_get(const u16 **src); + +/** + * utf16_put() - write UTF-16 code point to buffer + * + * @code: code point + * @dst: pointer to destination buffer, updated to next position + * Return: -1 if the input parameters are invalid + */ +int utf16_put(s32 code, u16 **dst); + +/** + * utf16_strnlen() - length of a truncated utf-16 string + * + * @src: utf-16 string + * @count: maximum number of code points to convert + * Return: length in code points. If an invalid UTF-16 sequence is + * hit one position will be reserved for a replacement + * character. + */ +size_t utf16_strnlen(const u16 *src, size_t count); + +/** + * utf16_utf8_strnlen() - length of a truncated utf-16 string after conversion + * to utf-8 + * + * @src: utf-16 string + * @count: maximum number of code points to convert + * Return: length in bytes after conversion to utf-8 without the + * trailing \0. If an invalid UTF-16 sequence is hit one + * byte will be reserved for a replacement character. + */ +size_t utf16_utf8_strnlen(const u16 *src, size_t count); + +/** + * utf16_utf8_strlen() - length of a utf-16 string after conversion to utf-8 + * + * @a: utf-16 string + * Return: length in bytes after conversion to utf-8 without the + * trailing \0. If an invalid UTF-16 sequence is hit one + * byte will be reserved for a replacement character. + */ +#define utf16_utf8_strlen(a) utf16_utf8_strnlen((a), SIZE_MAX) + +/** + * utf16_utf8_strncpy() - copy utf-16 string to utf-8 string + * + * @dst: destination buffer + * @src: source buffer + * @count: maximum number of code points to copy + * Return: -1 if the input parameters are invalid + */ +int utf16_utf8_strncpy(char **dst, const u16 *src, size_t count); + +/** + * utf16_utf8_strcpy() - copy utf-16 string to utf-8 string + * + * @d: destination buffer + * @s: source buffer + * Return: -1 if the input parameters are invalid + */ +#define utf16_utf8_strcpy(d, s) utf16_utf8_strncpy((d), (s), SIZE_MAX) + +/** + * utf_to_lower() - convert a Unicode letter to lower case + * + * @code: letter to convert + * Return: lower case letter or unchanged letter + */ +s32 utf_to_lower(const s32 code); + +/** + * utf_to_upper() - convert a Unicode letter to upper case + * + * @code: letter to convert + * Return: upper case letter or unchanged letter + */ +s32 utf_to_upper(const s32 code); + +/** + * u16_strncmp() - compare two u16 string + * + * @s1: first string to compare + * @s2: second string to compare + * @n: maximum number of u16 to compare + * Return: 0 if the first n u16 are the same in s1 and s2 + * < 0 if the first different u16 in s1 is less than the + * corresponding u16 in s2 + * > 0 if the first different u16 in s1 is greater than the + * corresponding u16 in s2 + */ +int u16_strncmp(const u16 *s1, const u16 *s2, size_t n); + +/** + * u16_strcmp() - compare two u16 string + * + * @s1: first string to compare + * @s2: second string to compare + * Return: 0 if the first n u16 are the same in s1 and s2 + * < 0 if the first different u16 in s1 is less than the + * corresponding u16 in s2 + * > 0 if the first different u16 in s1 is greater than the + * corresponding u16 in s2 + */ +#define u16_strcmp(s1, s2) u16_strncmp((s1), (s2), SIZE_MAX) + +/** + * u16_strlen - count non-zero words + * + * This function matches wsclen() if the -fshort-wchar compiler flag is set. + * In the EFI context we explicitly need a function handling u16 strings. + * + * @in: null terminated u16 string + * Return: number of non-zero words. + * This is not the number of utf-16 letters! + */ +size_t u16_strlen(const void *in); + +/** + * u16_strsize() - count size of u16 string in bytes including the null + * character + * + * Counts the number of bytes occupied by a u16 string + * + * @in: null terminated u16 string + * Return: bytes in a u16 string + */ +size_t u16_strsize(const void *in); + +/** + * u16_strnlen() - count non-zero words + * + * This function matches wscnlen_s() if the -fshort-wchar compiler flag is set. + * In the EFI context we explicitly need a function handling u16 strings. + * + * @in: null terminated u16 string + * @count: maximum number of words to count + * Return: number of non-zero words. + * This is not the number of utf-16 letters! + */ +size_t u16_strnlen(const u16 *in, size_t count); + +/** + * u16_strcpy() - copy u16 string + * + * Copy u16 string pointed to by src, including terminating null word, to + * the buffer pointed to by dest. + * + * @dest: destination buffer + * @src: source buffer (null terminated) + * Return: 'dest' address + */ +u16 *u16_strcpy(u16 *dest, const u16 *src); + +/** + * u16_strdup() - duplicate u16 string + * + * Copy u16 string pointed to by src, including terminating null word, to a + * newly allocated buffer. + * + * @src: source buffer (null terminated) + * Return: allocated new buffer on success, NULL on failure + */ +u16 *u16_strdup(const void *src); + +/** + * utf16_to_utf8() - Convert an utf16 string to utf8 + * + * Converts 'size' characters of the utf16 string 'src' to utf8 + * written to the 'dest' buffer. + * + * NOTE that a single utf16 character can generate up to 3 utf8 + * characters. See MAX_UTF8_PER_UTF16. + * + * @dest: the destination buffer to write the utf8 characters + * @src: the source utf16 string + * @size: the number of utf16 characters to convert + * Return: the pointer to the first unwritten byte in 'dest' + */ +uint8_t *utf16_to_utf8(uint8_t *dest, const uint16_t *src, size_t size); + +/** + * utf_to_cp() - translate Unicode code point to 8bit codepage + * + * Codepoints that do not exist in the codepage are rendered as question mark. + * + * @c: pointer to Unicode code point to be translated + * @codepage: Unicode to codepage translation table + * Return: 0 on success, -ENOENT if codepoint cannot be translated + */ +int utf_to_cp(s32 *c, const u16 *codepage); + +/** + * utf8_to_cp437_stream() - convert UTF-8 stream to codepage 437 + * + * @c: next UTF-8 character to convert + * @buffer: buffer, at least 5 characters + * Return: next codepage 437 character or 0 + */ +int utf8_to_cp437_stream(u8 c, char *buffer); + +/** + * utf8_to_utf32_stream() - convert UTF-8 stream to UTF-32 + * + * @c: next UTF-8 character to convert + * @buffer: buffer, at least 5 characters + * Return: next codepage 437 character or 0 + */ +int utf8_to_utf32_stream(u8 c, char *buffer); + +#endif /* __CHARSET_H_ */ diff --git a/roms/u-boot/include/circbuf.h b/roms/u-boot/include/circbuf.h new file mode 100644 index 000000000..e8ec12763 --- /dev/null +++ b/roms/u-boot/include/circbuf.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + */ + +#ifndef __CIRCBUF_H__ +#define __CIRCBUF_H__ + +typedef struct circbuf { + unsigned int size; /* current number of bytes held */ + unsigned int totalsize; /* number of bytes allocated */ + + char *top; /* pointer to current buffer start */ + char *tail; /* pointer to space for next element */ + + char *data; /* all data */ + char *end; /* end of data buffer */ +} circbuf_t; + +int buf_init (circbuf_t * buf, unsigned int size); +int buf_free (circbuf_t * buf); +int buf_pop (circbuf_t * buf, char *dest, unsigned int len); +int buf_push (circbuf_t * buf, const char *src, unsigned int len); + +#endif diff --git a/roms/u-boot/include/cli.h b/roms/u-boot/include/cli.h new file mode 100644 index 000000000..3449fa6ae --- /dev/null +++ b/roms/u-boot/include/cli.h @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 Google, Inc + * Simon Glass + */ + +#ifndef __CLI_H +#define __CLI_H + +/** + * Go into the command loop + * + * This will return if we get a timeout waiting for a command. See + * CONFIG_BOOT_RETRY_TIME. + */ +void cli_simple_loop(void); + +/** + * cli_simple_run_command() - Execute a command with the simple CLI + * + * @cmd: String containing the command to execute + * @flag Flag value - see CMD_FLAG_... + * @return 1 - command executed, repeatable + * 0 - command executed but not repeatable, interrupted commands are + * always considered not repeatable + * -1 - not executed (unrecognized, bootd recursion or too many args) + * (If cmd is NULL or "" or longer than CONFIG_SYS_CBSIZE-1 it is + * considered unrecognized) + */ +int cli_simple_run_command(const char *cmd, int flag); + +/** + * cli_simple_process_macros() - Expand $() and ${} format env. variables + * + * @param input Input string possible containing $() / ${} vars + * @param output Output string with $() / ${} vars expanded + * @param max_size Maximum size of @output (including terminator) + * @return 0 if OK, -ENOSPC if we ran out of space in @output + */ +int cli_simple_process_macros(const char *input, char *output, int max_size); + +/** + * cli_simple_run_command_list() - Execute a list of command + * + * The commands should be separated by ; or \n and will be executed + * by the built-in parser. + * + * This function cannot take a const char * for the command, since if it + * finds newlines in the string, it replaces them with \0. + * + * @param cmd String containing list of commands + * @param flag Execution flags (CMD_FLAG_...) + * @return 0 on success, or != 0 on error. + */ +int cli_simple_run_command_list(char *cmd, int flag); + +/** + * cli_readline() - read a line into the console_buffer + * + * This is a convenience function which calls cli_readline_into_buffer(). + * + * @prompt: Prompt to display + * @return command line length excluding terminator, or -ve on error + */ +int cli_readline(const char *const prompt); + +/** + * readline_into_buffer() - read a line into a buffer + * + * Display the prompt, then read a command line into @buffer. The + * maximum line length is CONFIG_SYS_CBSIZE including a \0 terminator, which + * will always be added. + * + * The command is echoed as it is typed. Command editing is supported if + * CONFIG_CMDLINE_EDITING is defined. Tab auto-complete is supported if + * CONFIG_AUTO_COMPLETE is defined. If CONFIG_BOOT_RETRY_TIME is defined, + * then a timeout will be applied. + * + * If CONFIG_BOOT_RETRY_TIME is defined and retry_time >= 0, + * time out when time goes past endtime (timebase time in ticks). + * + * @prompt: Prompt to display + * @buffer: Place to put the line that is entered + * @timeout: Timeout in milliseconds, 0 if none + * @return command line length excluding terminator, or -ve on error: of the + * timeout is exceeded (either CONFIG_BOOT_RETRY_TIME or the timeout + * parameter), then -2 is returned. If a break is detected (Ctrl-C) then + * -1 is returned. + */ +int cli_readline_into_buffer(const char *const prompt, char *buffer, + int timeout); + +/** + * parse_line() - split a command line down into separate arguments + * + * The argv[] array is filled with pointers into @line, and each argument + * is terminated by \0 (i.e. @line is changed in the process unless there + * is only one argument). + * + * #argv is terminated by a NULL after the last argument pointer. + * + * At most CONFIG_SYS_MAXARGS arguments are permited - if there are more + * than that then an error is printed, and this function returns + * CONFIG_SYS_MAXARGS, with argv[] set up to that point. + * + * @line: Command line to parse + * @args: Array to hold arguments + * @return number of arguments + */ +int cli_simple_parse_line(char *line, char *argv[]); + +#if CONFIG_IS_ENABLED(OF_CONTROL) +/** + * cli_process_fdt() - process the boot command from the FDT + * + * If bootcmmd is defined in the /config node of the FDT, we use that + * as the boot command. Further, if bootsecure is set to 1 (in the same + * node) then we return true, indicating that the command should be executed + * as securely as possible, avoiding the CLI parser. + * + * @cmdp: On entry, the command that will be executed if the FDT does + * not have a command. Returns the command to execute after + * checking the FDT. + * @return true to execute securely, else false + */ +bool cli_process_fdt(const char **cmdp); + +/** cli_secure_boot_cmd() - execute a command as securely as possible + * + * This avoids using the parser, thus executing the command with the + * smallest amount of code. Parameters are not supported. + */ +void cli_secure_boot_cmd(const char *cmd); +#else +static inline bool cli_process_fdt(const char **cmdp) +{ + return false; +} + +static inline void cli_secure_boot_cmd(const char *cmd) +{ +} +#endif /* CONFIG_OF_CONTROL */ + +/** + * Go into the command loop + * + * This will return if we get a timeout waiting for a command, but only for + * the simple parser (not hush). See CONFIG_BOOT_RETRY_TIME. + */ +void cli_loop(void); + +/** Set up the command line interpreter ready for action */ +void cli_init(void); + +#define endtick(seconds) (get_ticks() + (uint64_t)(seconds) * get_tbclk()) + +#endif diff --git a/roms/u-boot/include/cli_hush.h b/roms/u-boot/include/cli_hush.h new file mode 100644 index 000000000..2bd35670c --- /dev/null +++ b/roms/u-boot/include/cli_hush.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef _CLI_HUSH_H_ +#define _CLI_HUSH_H_ + +#define FLAG_EXIT_FROM_LOOP 1 +#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */ +#define FLAG_REPARSING (1 << 2) /* >=2nd pass */ +#define FLAG_CONT_ON_NEWLINE (1 << 3) /* continue when we see \n */ + +extern int u_boot_hush_start(void); +extern int parse_string_outer(const char *, int); +extern int parse_file_outer(void); + +int set_local_var(const char *s, int flg_export); +void unset_local_var(const char *name); +char *get_local_var(const char *s); + +#if defined(CONFIG_HUSH_INIT_VAR) +extern int hush_init_var (void); +#endif +#endif diff --git a/roms/u-boot/include/clk-uclass.h b/roms/u-boot/include/clk-uclass.h new file mode 100644 index 000000000..50e8681b5 --- /dev/null +++ b/roms/u-boot/include/clk-uclass.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass + * Copyright (c) 2016, NVIDIA CORPORATION. + */ + +#ifndef _CLK_UCLASS_H +#define _CLK_UCLASS_H + +/* See clk.h for background documentation. */ + +#include + +struct ofnode_phandle_args; + +/** + * struct clk_ops - The functions that a clock driver must implement. + */ +struct clk_ops { + /** + * of_xlate - Translate a client's device-tree (OF) clock specifier. + * + * The clock core calls this function as the first step in implementing + * a client's clk_get_by_*() call. + * + * If this function pointer is set to NULL, the clock core will use a + * default implementation, which assumes #clock-cells = <1>, and that + * the DT cell contains a simple integer clock ID. + * + * At present, the clock API solely supports device-tree. If this + * changes, other xxx_xlate() functions may be added to support those + * other mechanisms. + * + * @clock: The clock struct to hold the translation result. + * @args: The clock specifier values from device tree. + * @return 0 if OK, or a negative error code. + */ + int (*of_xlate)(struct clk *clock, + struct ofnode_phandle_args *args); + /** + * request - Request a translated clock. + * + * The clock core calls this function as the second step in + * implementing a client's clk_get_by_*() call, following a successful + * xxx_xlate() call, or as the only step in implementing a client's + * clk_request() call. + * + * @clock: The clock struct to request; this has been fille in by + * a previoux xxx_xlate() function call, or by the caller + * of clk_request(). + * @return 0 if OK, or a negative error code. + */ + int (*request)(struct clk *clock); + /** + * rfree - Free a previously requested clock. + * + * This is the implementation of the client clk_free() API. + * + * @clock: The clock to free. + * @return 0 if OK, or a negative error code. + */ + int (*rfree)(struct clk *clock); + /** + * round_rate() - Adjust a rate to the exact rate a clock can provide. + * + * @clk: The clock to manipulate. + * @rate: Desidered clock rate in Hz. + * @return rounded rate in Hz, or -ve error code. + */ + ulong (*round_rate)(struct clk *clk, ulong rate); + /** + * get_rate() - Get current clock rate. + * + * @clk: The clock to query. + * @return clock rate in Hz, or -ve error code + */ + ulong (*get_rate)(struct clk *clk); + /** + * set_rate() - Set current clock rate. + * + * @clk: The clock to manipulate. + * @rate: New clock rate in Hz. + * @return new rate, or -ve error code. + */ + ulong (*set_rate)(struct clk *clk, ulong rate); + /** + * set_parent() - Set current clock parent + * + * @clk: The clock to manipulate. + * @parent: New clock parent. + * @return zero on success, or -ve error code. + */ + int (*set_parent)(struct clk *clk, struct clk *parent); + /** + * enable() - Enable a clock. + * + * @clk: The clock to manipulate. + * @return zero on success, or -ve error code. + */ + int (*enable)(struct clk *clk); + /** + * disable() - Disable a clock. + * + * @clk: The clock to manipulate. + * @return zero on success, or -ve error code. + */ + int (*disable)(struct clk *clk); +}; + +#endif diff --git a/roms/u-boot/include/clk.h b/roms/u-boot/include/clk.h new file mode 100644 index 000000000..ca6b85fa6 --- /dev/null +++ b/roms/u-boot/include/clk.h @@ -0,0 +1,575 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass + * Copyright (c) 2016, NVIDIA CORPORATION. + */ + +#ifndef _CLK_H_ +#define _CLK_H_ + +#include +#include +#include +#include + +/** + * A clock is a hardware signal that oscillates autonomously at a specific + * frequency and duty cycle. Most hardware modules require one or more clock + * signal to drive their operation. Clock signals are typically generated + * externally to the HW module consuming them, by an entity this API calls a + * clock provider. This API provides a standard means for drivers to enable and + * disable clocks, and to set the rate at which they oscillate. + * + * A driver that implements UCLASS_CLK is a clock provider. A provider will + * often implement multiple separate clocks, since the hardware it manages + * often has this capability. clk-uclass.h describes the interface which + * clock providers must implement. + * + * Clock consumers/clients are the HW modules driven by the clock signals. This + * header file describes the API used by drivers for those HW modules. + */ + +struct udevice; + +/** + * struct clk - A handle to (allowing control of) a single clock. + * + * Clients provide storage for clock handles. The content of the structure is + * managed solely by the clock API and clock drivers. A clock struct is + * initialized by "get"ing the clock struct. The clock struct is passed to all + * other clock APIs to identify which clock signal to operate upon. + * + * @dev: The device which implements the clock signal. + * @rate: The clock rate (in HZ). + * @flags: Flags used across common clock structure (e.g. CLK_) + * Clock IP blocks specific flags (i.e. mux, div, gate, etc) are defined + * in struct's for those devices (e.g. struct clk_mux). + * @id: The clock signal ID within the provider. + * @data: An optional data field for scenarios where a single integer ID is not + * sufficient. If used, it can be populated through an .of_xlate op and + * processed during the various clock ops. + * + * Should additional information to identify and configure any clock signal + * for any provider be required in the future, the struct could be expanded to + * either (a) add more fields to allow clock providers to store additional + * information, or (b) replace the id field with an opaque pointer, which the + * provider would dynamically allocated during its .of_xlate op, and process + * during is .request op. This may require the addition of an extra op to clean + * up the allocation. + */ +struct clk { + struct udevice *dev; + long long rate; /* in HZ */ + u32 flags; + int enable_count; + /* + * Written by of_xlate. In the future, we might add more fields here. + */ + unsigned long id; + unsigned long data; +}; + +/** + * struct clk_bulk - A handle to (allowing control of) a bulk of clocks. + * + * Clients provide storage for the clock bulk. The content of the structure is + * managed solely by the clock API. A clock bulk struct is + * initialized by "get"ing the clock bulk struct. + * The clock bulk struct is passed to all other bulk clock APIs to apply + * the API to all the clock in the bulk struct. + * + * @clks: An array of clock handles. + * @count: The number of clock handles in the clks array. + */ +struct clk_bulk { + struct clk *clks; + unsigned int count; +}; + +#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK) +struct phandle_1_arg; +int clk_get_by_driver_info(struct udevice *dev, + struct phandle_1_arg *cells, struct clk *clk); + +/** + * clk_get_by_index - Get/request a clock by integer index. + * + * This looks up and requests a clock. The index is relative to the client + * device; each device is assumed to have n clocks associated with it somehow, + * and this function finds and requests one of them. The mapping of client + * device clock indices to provider clocks may be via device-tree properties, + * board-provided mapping tables, or some other mechanism. + * + * @dev: The client device. + * @index: The index of the clock to request, within the client's list of + * clocks. + * @clock A pointer to a clock struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int clk_get_by_index(struct udevice *dev, int index, struct clk *clk); + +/** + * clk_get_by_index_nodev - Get/request a clock by integer index + * without a device. + * + * This is a version of clk_get_by_index() that does not use a device. + * + * @node: The client ofnode. + * @index: The index of the clock to request, within the client's list of + * clocks. + * @clock A pointer to a clock struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk); + +/** + * clk_get_bulk - Get/request all clocks of a device. + * + * This looks up and requests all clocks of the client device; each device is + * assumed to have n clocks associated with it somehow, and this function finds + * and requests all of them in a separate structure. The mapping of client + * device clock indices to provider clocks may be via device-tree properties, + * board-provided mapping tables, or some other mechanism. + * + * @dev: The client device. + * @bulk A pointer to a clock bulk struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk); + +/** + * clk_get_by_name - Get/request a clock by name. + * + * This looks up and requests a clock. The name is relative to the client + * device; each device is assumed to have n clocks associated with it somehow, + * and this function finds and requests one of them. The mapping of client + * device clock names to provider clocks may be via device-tree properties, + * board-provided mapping tables, or some other mechanism. + * + * @dev: The client device. + * @name: The name of the clock to request, within the client's list of + * clocks. + * @clock: A pointer to a clock struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk); + +/** + * clk_get_by_name_nodev - Get/request a clock by name without a device. + * + * This is a version of clk_get_by_name() that does not use a device. + * + * @node: The client ofnode. + * @name: The name of the clock to request, within the client's list of + * clocks. + * @clock: A pointer to a clock struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk); + +/** + * clk_get_optional_nodev - Get/request an optinonal clock by name + * without a device. + * @node: The client ofnode. + * @name: The name of the clock to request. + * @name: The name of the clock to request, within the client's list of + * clocks. + * @clock: A pointer to a clock struct to initialize. + * + * Behaves the same as clk_get_by_name_nodev() except where there is + * no clock producer, in this case, skip the error number -ENODATA, and + * the function returns 0. + */ +int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk); + +/** + * devm_clk_get - lookup and obtain a managed reference to a clock producer. + * @dev: device for clock "consumer" + * @id: clock consumer ID + * + * Returns a struct clk corresponding to the clock producer, or + * valid IS_ERR() condition containing errno. The implementation + * uses @dev and @id to determine the clock consumer, and thereby + * the clock producer. (IOW, @id may be identical strings, but + * clk_get may return different clock producers depending on @dev.) + * + * Drivers must assume that the clock source is not enabled. + * + * devm_clk_get should not be called from within interrupt context. + * + * The clock will automatically be freed when the device is unbound + * from the bus. + */ +struct clk *devm_clk_get(struct udevice *dev, const char *id); + +/** + * devm_clk_get_optional - lookup and obtain a managed reference to an optional + * clock producer. + * @dev: device for clock "consumer" + * @id: clock consumer ID + * + * Behaves the same as devm_clk_get() except where there is no clock producer. + * In this case, instead of returning -ENOENT, the function returns NULL. + */ +struct clk *devm_clk_get_optional(struct udevice *dev, const char *id); + +/** + * clk_release_all() - Disable (turn off)/Free an array of previously + * requested clocks. + * + * For each clock contained in the clock array, this function will check if + * clock has been previously requested and then will disable and free it. + * + * @clk: A clock struct array that was previously successfully + * requested by clk_request/get_by_*(). + * @count Number of clock contained in the array + * @return zero on success, or -ve error code. + */ +int clk_release_all(struct clk *clk, int count); + +/** + * devm_clk_put - "free" a managed clock source + * @dev: device used to acquire the clock + * @clk: clock source acquired with devm_clk_get() + * + * Note: drivers must ensure that all clk_enable calls made on this + * clock source are balanced by clk_disable calls prior to calling + * this function. + * + * clk_put should not be called from within interrupt context. + */ +void devm_clk_put(struct udevice *dev, struct clk *clk); + +#else +static inline int clk_get_by_index(struct udevice *dev, int index, + struct clk *clk) +{ + return -ENOSYS; +} + +static inline int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk) +{ + return -ENOSYS; +} + +static inline int clk_get_by_name(struct udevice *dev, const char *name, + struct clk *clk) +{ + return -ENOSYS; +} + +static inline int +clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) +{ + return -ENOSYS; +} + +static inline int +clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk) +{ + return -ENOSYS; +} + +static inline int clk_release_all(struct clk *clk, int count) +{ + return -ENOSYS; +} +#endif + +#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \ + CONFIG_IS_ENABLED(CLK) +/** + * clk_set_defaults - Process 'assigned-{clocks/clock-parents/clock-rates}' + * properties to configure clocks + * + * @dev: A device to process (the ofnode associated with this device + * will be processed). + * @stage: A integer. 0 indicates that this is called before the device + * is probed. 1 indicates that this is called just after the + * device has been probed + */ +int clk_set_defaults(struct udevice *dev, int stage); +#else +static inline int clk_set_defaults(struct udevice *dev, int stage) +{ + return 0; +} +#endif + +/** + * clk_release_bulk() - Disable (turn off)/Free an array of previously + * requested clocks in a clock bulk struct. + * + * For each clock contained in the clock bulk struct, this function will check + * if clock has been previously requested and then will disable and free it. + * + * @clk: A clock bulk struct that was previously successfully + * requested by clk_get_bulk(). + * @return zero on success, or -ve error code. + */ +static inline int clk_release_bulk(struct clk_bulk *bulk) +{ + return clk_release_all(bulk->clks, bulk->count); +} + +#if CONFIG_IS_ENABLED(CLK) +/** + * clk_request - Request a clock by provider-specific ID. + * + * This requests a clock using a provider-specific ID. Generally, this function + * should not be used, since clk_get_by_index/name() provide an interface that + * better separates clients from intimate knowledge of clock providers. + * However, this function may be useful in core SoC-specific code. + * + * @dev: The clock provider device. + * @clock: A pointer to a clock struct to initialize. The caller must + * have already initialized any field in this struct which the + * clock provider uses to identify the clock. + * @return 0 if OK, or a negative error code. + */ +int clk_request(struct udevice *dev, struct clk *clk); + +/** + * clk_free - Free a previously requested clock. + * + * @clock: A clock struct that was previously successfully requested by + * clk_request/get_by_*(). + * @return 0 if OK, or a negative error code. + */ +int clk_free(struct clk *clk); + +/** + * clk_get_rate() - Get current clock rate. + * + * @clk: A clock struct that was previously successfully requested by + * clk_request/get_by_*(). + * @return clock rate in Hz, or -ve error code. + */ +ulong clk_get_rate(struct clk *clk); + +/** + * clk_get_parent() - Get current clock's parent. + * + * @clk: A clock struct that was previously successfully requested by + * clk_request/get_by_*(). + * @return pointer to parent's struct clk, or error code passed as pointer + */ +struct clk *clk_get_parent(struct clk *clk); + +/** + * clk_get_parent_rate() - Get parent of current clock rate. + * + * @clk: A clock struct that was previously successfully requested by + * clk_request/get_by_*(). + * @return clock rate in Hz, or -ve error code. + */ +long long clk_get_parent_rate(struct clk *clk); + +/** + * clk_round_rate() - Adjust a rate to the exact rate a clock can provide + * + * This answers the question "if I were to pass @rate to clk_set_rate(), + * what clock rate would I end up with?" without changing the hardware + * in any way. In other words: + * + * rate = clk_round_rate(clk, r); + * + * and: + * + * rate = clk_set_rate(clk, r); + * + * are equivalent except the former does not modify the clock hardware + * in any way. + * + * @clk: A clock struct that was previously successfully requested by + * clk_request/get_by_*(). + * @rate: desired clock rate in Hz. + * @return rounded rate in Hz, or -ve error code. + */ +ulong clk_round_rate(struct clk *clk, ulong rate); + +/** + * clk_set_rate() - Set current clock rate. + * + * @clk: A clock struct that was previously successfully requested by + * clk_request/get_by_*(). + * @rate: New clock rate in Hz. + * @return new rate, or -ve error code. + */ +ulong clk_set_rate(struct clk *clk, ulong rate); + +/** + * clk_set_parent() - Set current clock parent. + * + * @clk: A clock struct that was previously successfully requested by + * clk_request/get_by_*(). + * @parent: A clock struct that was previously successfully requested by + * clk_request/get_by_*(). + * @return new rate, or -ve error code. + */ +int clk_set_parent(struct clk *clk, struct clk *parent); + +/** + * clk_enable() - Enable (turn on) a clock. + * + * @clk: A clock struct that was previously successfully requested by + * clk_request/get_by_*(). + * @return zero on success, or -ve error code. + */ +int clk_enable(struct clk *clk); + +/** + * clk_enable_bulk() - Enable (turn on) all clocks in a clock bulk struct. + * + * @bulk: A clock bulk struct that was previously successfully requested + * by clk_get_bulk(). + * @return zero on success, or -ve error code. + */ +int clk_enable_bulk(struct clk_bulk *bulk); + +/** + * clk_disable() - Disable (turn off) a clock. + * + * @clk: A clock struct that was previously successfully requested by + * clk_request/get_by_*(). + * @return zero on success, or -ve error code. + */ +int clk_disable(struct clk *clk); + +/** + * clk_disable_bulk() - Disable (turn off) all clocks in a clock bulk struct. + * + * @bulk: A clock bulk struct that was previously successfully requested + * by clk_get_bulk(). + * @return zero on success, or -ve error code. + */ +int clk_disable_bulk(struct clk_bulk *bulk); + +/** + * clk_is_match - check if two clk's point to the same hardware clock + * @p: clk compared against q + * @q: clk compared against p + * + * Returns true if the two struct clk pointers both point to the same hardware + * clock node. + * + * Returns false otherwise. Note that two NULL clks are treated as matching. + */ +bool clk_is_match(const struct clk *p, const struct clk *q); + +/** + * clk_get_by_id() - Get the clock by its ID + * + * @id: The clock ID to search for + * + * @clkp: A pointer to clock struct that has been found among added clocks + * to UCLASS_CLK + * @return zero on success, or -ENOENT on error + */ +int clk_get_by_id(ulong id, struct clk **clkp); + +/** + * clk_dev_binded() - Check whether the clk has a device binded + * + * @clk A pointer to the clk + * + * @return true on binded, or false on no + */ +bool clk_dev_binded(struct clk *clk); + +#else /* CONFIG_IS_ENABLED(CLK) */ + +static inline int clk_request(struct udevice *dev, struct clk *clk) +{ + return -ENOSYS; +} + +static inline int clk_free(struct clk *clk) +{ + return 0; +} + +static inline ulong clk_get_rate(struct clk *clk) +{ + return -ENOSYS; +} + +static inline struct clk *clk_get_parent(struct clk *clk) +{ + return ERR_PTR(-ENOSYS); +} + +static inline long long clk_get_parent_rate(struct clk *clk) +{ + return -ENOSYS; +} + +static inline ulong clk_round_rate(struct clk *clk, ulong rate) +{ + return -ENOSYS; +} + +static inline ulong clk_set_rate(struct clk *clk, ulong rate) +{ + return -ENOSYS; +} + +static inline int clk_set_parent(struct clk *clk, struct clk *parent) +{ + return -ENOSYS; +} + +static inline int clk_enable(struct clk *clk) +{ + return 0; +} + +static inline int clk_enable_bulk(struct clk_bulk *bulk) +{ + return 0; +} + +static inline int clk_disable(struct clk *clk) +{ + return 0; +} + +static inline int clk_disable_bulk(struct clk_bulk *bulk) +{ + return 0; +} + +static inline bool clk_is_match(const struct clk *p, const struct clk *q) +{ + return false; +} + +static inline int clk_get_by_id(ulong id, struct clk **clkp) +{ + return -ENOSYS; +} + +static inline bool clk_dev_binded(struct clk *clk) +{ + return false; +} +#endif /* CONFIG_IS_ENABLED(CLK) */ + +/** + * clk_valid() - check if clk is valid + * + * @clk: the clock to check + * @return true if valid, or false + */ +static inline bool clk_valid(struct clk *clk) +{ + return clk && !!clk->dev; +} + +int soc_clk_dump(void); + +#endif + +#define clk_prepare_enable(clk) clk_enable(clk) +#define clk_disable_unprepare(clk) clk_disable(clk) diff --git a/roms/u-boot/include/clock_legacy.h b/roms/u-boot/include/clock_legacy.h new file mode 100644 index 000000000..b0a8333ea --- /dev/null +++ b/roms/u-boot/include/clock_legacy.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef __CLOCK_LEGACY_H +#define __CLOCK_LEGACY_H + +int get_clocks(void); +unsigned long get_bus_freq(unsigned long dummy); +int get_serial_clock(void); + +#endif diff --git a/roms/u-boot/include/cmd_spl.h b/roms/u-boot/include/cmd_spl.h new file mode 100644 index 000000000..51ec12edb --- /dev/null +++ b/roms/u-boot/include/cmd_spl.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz + */ +#ifndef _NAND_SPL_H_ +#define _NAND_SPL_H_ + +#define SPL_EXPORT (0x00000001) + +#define SPL_EXPORT_FDT (0x00000001) +#define SPL_EXPORT_ATAGS (0x00000002) +#define SPL_EXPORT_LAST SPL_EXPORT_ATAGS + +#endif /* _NAND_SPL_H_ */ diff --git a/roms/u-boot/include/command.h b/roms/u-boot/include/command.h new file mode 100644 index 000000000..137cfbc32 --- /dev/null +++ b/roms/u-boot/include/command.h @@ -0,0 +1,441 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +/* + * Definitions for Command Processor + */ +#ifndef __COMMAND_H +#define __COMMAND_H + +#include +#include + +#ifndef NULL +#define NULL 0 +#endif + +/* Default to a width of 8 characters for help message command width */ +#ifndef CONFIG_SYS_HELP_CMD_WIDTH +#define CONFIG_SYS_HELP_CMD_WIDTH 10 +#endif + +#ifndef __ASSEMBLY__ +/* + * Monitor Command Table + */ + +struct cmd_tbl { + char *name; /* Command Name */ + int maxargs; /* maximum number of arguments */ + /* + * Same as ->cmd() except the command + * tells us if it can be repeated. + * Replaces the old ->repeatable field + * which was not able to make + * repeatable property different for + * the main command and sub-commands. + */ + int (*cmd_rep)(struct cmd_tbl *cmd, int flags, int argc, + char *const argv[], int *repeatable); + /* Implementation function */ + int (*cmd)(struct cmd_tbl *cmd, int flags, int argc, + char *const argv[]); + char *usage; /* Usage message (short) */ +#ifdef CONFIG_SYS_LONGHELP + char *help; /* Help message (long) */ +#endif +#ifdef CONFIG_AUTO_COMPLETE + /* do auto completion on the arguments */ + int (*complete)(int argc, char *const argv[], + char last_char, int maxv, char *cmdv[]); +#endif +}; + +#if defined(CONFIG_CMD_RUN) +int do_run(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); +#endif + +/* common/command.c */ +int _do_help(struct cmd_tbl *cmd_start, int cmd_items, struct cmd_tbl *cmdtp, + int flag, int argc, char *const argv[]); +struct cmd_tbl *find_cmd(const char *cmd); +struct cmd_tbl *find_cmd_tbl(const char *cmd, struct cmd_tbl *table, + int table_len); +int complete_subcmdv(struct cmd_tbl *cmdtp, int count, int argc, + char *const argv[], char last_char, int maxv, + char *cmdv[]); + +int cmd_usage(const struct cmd_tbl *cmdtp); + +/* Dummy ->cmd and ->cmd_rep wrappers. */ +int cmd_always_repeatable(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[], int *repeatable); +int cmd_never_repeatable(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[], int *repeatable); +int cmd_discard_repeatable(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); + +static inline bool cmd_is_repeatable(struct cmd_tbl *cmdtp) +{ + return cmdtp->cmd_rep == cmd_always_repeatable; +} + +#ifdef CONFIG_AUTO_COMPLETE +int var_complete(int argc, char *const argv[], char last_char, int maxv, + char *cmdv[]); +int cmd_auto_complete(const char *const prompt, char *buf, int *np, + int *colp); +#endif + +/** + * cmd_process_error() - report and process a possible error + * + * @cmdtp: Command which caused the error + * @err: Error code (0 if none, -ve for error, like -EIO) + * @return 0 (CMD_RET_SUCCESS) if there is not error, + * 1 (CMD_RET_FAILURE) if an error is found + * -1 (CMD_RET_USAGE) if 'usage' error is found + */ +int cmd_process_error(struct cmd_tbl *cmdtp, int err); + +/* + * Monitor Command + * + * All commands use a common argument format: + * + * void function(struct cmd_tbl *cmdtp, int flag, int argc, + * char *const argv[]); + */ + +#if defined(CONFIG_CMD_MEMORY) || \ + defined(CONFIG_CMD_I2C) || \ + defined(CONFIG_CMD_ITEST) || \ + defined(CONFIG_CMD_PCI) || \ + defined(CONFIG_CMD_SETEXPR) +#define CMD_DATA_SIZE +#define CMD_DATA_SIZE_ERR (-1) +#define CMD_DATA_SIZE_STR (-2) + +/** + * cmd_get_data_size() - Get the data-size specifier from a command + * + * This reads a '.x' size specifier appended to a command. For example 'md.b' + * is the 'md' command with a '.b' specifier, meaning that the command should + * use bytes. + * + * Valid characters are: + * + * b - byte + * w - word (16 bits) + * l - long (32 bits) + * q - quad (64 bits) + * s - string + * + * @arg: Pointers to the command to check. If a valid specifier is present it + * will be the last character of the string, following a '.' + * @default_size: Default size to return if there is no specifier + * @return data size in bytes (1, 2, 4, 8) or CMD_DATA_SIZE_ERR for an invalid + * character, or CMD_DATA_SIZE_STR for a string + */ +int cmd_get_data_size(char *arg, int default_size); +#endif + +#ifdef CONFIG_CMD_BOOTD +int do_bootd(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); +#endif +#ifdef CONFIG_CMD_BOOTM +int do_bootm(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); +int bootm_maybe_autostart(struct cmd_tbl *cmdtp, const char *cmd); +#else +static inline int bootm_maybe_autostart(struct cmd_tbl *cmdtp, const char *cmd) +{ + return 0; +} +#endif + +int do_bootz(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); + +int do_booti(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); + +int do_zboot_parent(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[], int *repeatable); + +int common_diskboot(struct cmd_tbl *cmdtp, const char *intf, int argc, + char *const argv[]); + +int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); +int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); + +unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, + char *const argv[]); + +#if defined(CONFIG_CMD_NVEDIT_EFI) +int do_env_print_efi(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); +int do_env_set_efi(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); +#endif + +/** + * setexpr_regex_sub() - Replace a regex pattern with a string + * + * @data: Buffer containing the string to update + * @data_size: Size of buffer (must be large enough for the new string) + * @nbuf: Back-reference buffer + * @nbuf_size: Size of back-reference buffer (must be larger enough for @s plus + * all back-reference expansions) + * @r: Regular expression to find + * @s: String to replace with + * @global: true to replace all matches in @data, false to replace just the + * first + * @return 0 if OK, 1 on error + */ +int setexpr_regex_sub(char *data, uint data_size, char *nbuf, uint nbuf_size, + const char *r, const char *s, bool global); + +/* + * Error codes that commands return to cmd_process(). We use the standard 0 + * and 1 for success and failure, but add one more case - failure with a + * request to call cmd_usage(). But the cmd_process() function handles + * CMD_RET_USAGE itself and after calling cmd_usage() it will return 1. + * This is just a convenience for commands to avoid them having to call + * cmd_usage() all over the place. + */ +enum command_ret_t { + CMD_RET_SUCCESS, /* 0 = Success */ + CMD_RET_FAILURE, /* 1 = Failure */ + CMD_RET_USAGE = -1, /* Failure, please report 'usage' error */ +}; + +/** + * Process a command with arguments. We look up the command and execute it + * if valid. Otherwise we print a usage message. + * + * @param flag Some flags normally 0 (see CMD_FLAG_.. above) + * @param argc Number of arguments (arg 0 must be the command text) + * @param argv Arguments + * @param repeatable This function sets this to 0 if the command is not + * repeatable. If the command is repeatable, the value + * is left unchanged. + * @param ticks If ticks is not null, this function set it to the + * number of ticks the command took to complete. + * @return 0 if the command succeeded, 1 if it failed + */ +int cmd_process(int flag, int argc, char *const argv[], int *repeatable, + unsigned long *ticks); + +void fixup_cmdtable(struct cmd_tbl *cmdtp, int size); + +/** + * board_run_command() - Fallback function to execute a command + * + * When no command line features are enabled in U-Boot, this function is + * called to execute a command. Typically the function can look at the + * command and perform a few very specific tasks, such as booting the + * system in a particular way. + * + * This function is only used when CONFIG_CMDLINE is not enabled. + * + * In normal situations this function should not return, since U-Boot will + * simply hang. + * + * @cmdline: Command line string to execute + * @return 0 if OK, 1 for error + */ +int board_run_command(const char *cmdline); + +int run_command(const char *cmd, int flag); +int run_command_repeatable(const char *cmd, int flag); + +/** + * Run a list of commands separated by ; or even \0 + * + * Note that if 'len' is not -1, then the command does not need to be nul + * terminated, Memory will be allocated for the command in that case. + * + * @param cmd List of commands to run, each separated bu semicolon + * @param len Length of commands excluding terminator if known (-1 if not) + * @param flag Execution flags (CMD_FLAG_...) + * @return 0 on success, or != 0 on error. + */ +int run_command_list(const char *cmd, int len, int flag); +#endif /* __ASSEMBLY__ */ + +/* + * Command Flags: + */ +#define CMD_FLAG_REPEAT 0x0001 /* repeat last command */ +#define CMD_FLAG_BOOTD 0x0002 /* command is from bootd */ +#define CMD_FLAG_ENV 0x0004 /* command is from the environment */ + +#ifdef CONFIG_AUTO_COMPLETE +# define _CMD_COMPLETE(x) x, +#else +# define _CMD_COMPLETE(x) +#endif +#ifdef CONFIG_SYS_LONGHELP +# define _CMD_HELP(x) x, +#else +# define _CMD_HELP(x) +#endif + +#ifdef CONFIG_NEEDS_MANUAL_RELOC +#define U_BOOT_SUBCMDS_RELOC(_cmdname) \ + static void _cmdname##_subcmds_reloc(void) \ + { \ + static int relocated; \ + \ + if (relocated) \ + return; \ + \ + fixup_cmdtable(_cmdname##_subcmds, \ + ARRAY_SIZE(_cmdname##_subcmds)); \ + relocated = 1; \ + } +#else +#define U_BOOT_SUBCMDS_RELOC(_cmdname) \ + static void _cmdname##_subcmds_reloc(void) { } +#endif + +#define U_BOOT_SUBCMDS_DO_CMD(_cmdname) \ + static int do_##_cmdname(struct cmd_tbl *cmdtp, int flag, \ + int argc, char *const argv[], \ + int *repeatable) \ + { \ + struct cmd_tbl *subcmd; \ + \ + _cmdname##_subcmds_reloc(); \ + \ + /* We need at least the cmd and subcmd names. */ \ + if (argc < 2 || argc > CONFIG_SYS_MAXARGS) \ + return CMD_RET_USAGE; \ + \ + subcmd = find_cmd_tbl(argv[1], _cmdname##_subcmds, \ + ARRAY_SIZE(_cmdname##_subcmds)); \ + if (!subcmd || argc - 1 > subcmd->maxargs) \ + return CMD_RET_USAGE; \ + \ + if (flag == CMD_FLAG_REPEAT && \ + !cmd_is_repeatable(subcmd)) \ + return CMD_RET_SUCCESS; \ + \ + return subcmd->cmd_rep(subcmd, flag, argc - 1, \ + argv + 1, repeatable); \ + } + +#ifdef CONFIG_AUTO_COMPLETE +#define U_BOOT_SUBCMDS_COMPLETE(_cmdname) \ + static int complete_##_cmdname(int argc, char *const argv[], \ + char last_char, int maxv, \ + char *cmdv[]) \ + { \ + return complete_subcmdv(_cmdname##_subcmds, \ + ARRAY_SIZE(_cmdname##_subcmds), \ + argc - 1, argv + 1, last_char, \ + maxv, cmdv); \ + } +#else +#define U_BOOT_SUBCMDS_COMPLETE(_cmdname) +#endif + +#define U_BOOT_SUBCMDS(_cmdname, ...) \ + static struct cmd_tbl _cmdname##_subcmds[] = { __VA_ARGS__ }; \ + U_BOOT_SUBCMDS_RELOC(_cmdname) \ + U_BOOT_SUBCMDS_DO_CMD(_cmdname) \ + U_BOOT_SUBCMDS_COMPLETE(_cmdname) + +#ifdef CONFIG_CMDLINE +#define U_BOOT_CMDREP_MKENT_COMPLETE(_name, _maxargs, _cmd_rep, \ + _usage, _help, _comp) \ + { #_name, _maxargs, _cmd_rep, cmd_discard_repeatable, \ + _usage, _CMD_HELP(_help) _CMD_COMPLETE(_comp) } + +#define U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \ + _usage, _help, _comp) \ + { #_name, _maxargs, \ + _rep ? cmd_always_repeatable : cmd_never_repeatable, \ + _cmd, _usage, _CMD_HELP(_help) _CMD_COMPLETE(_comp) } + +#define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, _comp) \ + ll_entry_declare(struct cmd_tbl, _name, cmd) = \ + U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \ + _usage, _help, _comp); + +#define U_BOOT_CMDREP_COMPLETE(_name, _maxargs, _cmd_rep, _usage, \ + _help, _comp) \ + ll_entry_declare(struct cmd_tbl, _name, cmd) = \ + U_BOOT_CMDREP_MKENT_COMPLETE(_name, _maxargs, _cmd_rep, \ + _usage, _help, _comp) + +#else +#define U_BOOT_SUBCMD_START(name) static struct cmd_tbl name[] = {}; +#define U_BOOT_SUBCMD_END + +#define _CMD_REMOVE(_name, _cmd) \ + int __remove_ ## _name(void) \ + { \ + if (0) \ + _cmd(NULL, 0, 0, NULL); \ + return 0; \ + } + +#define _CMD_REMOVE_REP(_name, _cmd) \ + int __remove_ ## _name(void) \ + { \ + if (0) \ + _cmd(NULL, 0, 0, NULL, NULL); \ + return 0; \ + } + +#define U_BOOT_CMDREP_MKENT_COMPLETE(_name, _maxargs, _cmd_rep, \ + _usage, _help, _comp) \ + { #_name, _maxargs, 0 ? _cmd_rep : NULL, NULL, _usage, \ + _CMD_HELP(_help) _CMD_COMPLETE(_comp) } + +#define U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, \ + _help, _comp) \ + { #_name, _maxargs, NULL, 0 ? _cmd : NULL, _usage, \ + _CMD_HELP(_help) _CMD_COMPLETE(_comp) } + +#define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, \ + _comp) \ + _CMD_REMOVE(sub_ ## _name, _cmd) + +#define U_BOOT_CMDREP_COMPLETE(_name, _maxargs, _cmd_rep, _usage, \ + _help, _comp) \ + _CMD_REMOVE_REP(sub_ ## _name, _cmd_rep) + +#endif /* CONFIG_CMDLINE */ + +#define U_BOOT_CMD(_name, _maxargs, _rep, _cmd, _usage, _help) \ + U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, NULL) + +#define U_BOOT_CMD_MKENT(_name, _maxargs, _rep, _cmd, _usage, _help) \ + U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \ + _usage, _help, NULL) + +#define U_BOOT_SUBCMD_MKENT_COMPLETE(_name, _maxargs, _rep, _do_cmd, \ + _comp) \ + U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _do_cmd, \ + "", "", _comp) + +#define U_BOOT_SUBCMD_MKENT(_name, _maxargs, _rep, _do_cmd) \ + U_BOOT_SUBCMD_MKENT_COMPLETE(_name, _maxargs, _rep, _do_cmd, \ + NULL) + +#define U_BOOT_CMD_WITH_SUBCMDS(_name, _usage, _help, ...) \ + U_BOOT_SUBCMDS(_name, __VA_ARGS__) \ + U_BOOT_CMDREP_COMPLETE(_name, CONFIG_SYS_MAXARGS, do_##_name, \ + _usage, _help, complete_##_name) + +#endif /* __COMMAND_H */ diff --git a/roms/u-boot/include/common.h b/roms/u-boot/include/common.h new file mode 100644 index 000000000..71df59bca --- /dev/null +++ b/roms/u-boot/include/common.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Common header file for U-Boot + * + * This file still includes quite a few headers that should be included + * individually as needed. Patches to remove things are welcome. + * + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef __COMMON_H_ +#define __COMMON_H_ 1 + +#ifndef __ASSEMBLY__ /* put C only stuff in this section */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* boot information for Linux kernel */ +#include +#include +#endif /* __ASSEMBLY__ */ + +/* Pull in stuff for the build system */ +#ifdef DO_DEPS_ONLY +# include +#endif + +#endif /* __COMMON_H_ */ diff --git a/roms/u-boot/include/common_timing_params.h b/roms/u-boot/include/common_timing_params.h new file mode 100644 index 000000000..96704cd2f --- /dev/null +++ b/roms/u-boot/include/common_timing_params.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + */ + +#ifndef COMMON_TIMING_PARAMS_H +#define COMMON_TIMING_PARAMS_H + +typedef struct { + /* parameters to constrict */ + + unsigned int tckmin_x_ps; + unsigned int tckmax_ps; + unsigned int trcd_ps; + unsigned int trp_ps; + unsigned int tras_ps; +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) + unsigned int taamin_ps; +#endif + +#ifdef CONFIG_SYS_FSL_DDR4 + unsigned int trfc1_ps; + unsigned int trfc2_ps; + unsigned int trfc4_ps; + unsigned int trrds_ps; + unsigned int trrdl_ps; + unsigned int tccdl_ps; + unsigned int trfc_slr_ps; +#else + unsigned int twtr_ps; /* maximum = 63750 ps */ + unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns + = 511750 ps */ + + unsigned int trrd_ps; /* maximum = 63750 ps */ + unsigned int trtp_ps; /* byte 38, spd->trtp */ +#endif + unsigned int twr_ps; /* maximum = 63750 ps */ + unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ + + unsigned int refresh_rate_ps; + unsigned int extended_op_srt; + +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) + unsigned int tis_ps; /* byte 32, spd->ca_setup */ + unsigned int tih_ps; /* byte 33, spd->ca_hold */ + unsigned int tds_ps; /* byte 34, spd->data_setup */ + unsigned int tdh_ps; /* byte 35, spd->data_hold */ + unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ + unsigned int tqhs_ps; /* byte 45, spd->tqhs */ +#endif + + unsigned int ndimms_present; + unsigned int lowest_common_spd_caslat; + unsigned int highest_common_derated_caslat; + unsigned int additive_latency; + unsigned int all_dimms_burst_lengths_bitmask; + unsigned int all_dimms_registered; + unsigned int all_dimms_unbuffered; + unsigned int all_dimms_ecc_capable; + + unsigned long long total_mem; + unsigned long long base_address; + + /* DDR3 RDIMM */ + unsigned char rcw[16]; /* Register Control Word 0-15 */ +} common_timing_params_t; + +#endif diff --git a/roms/u-boot/include/compiler.h b/roms/u-boot/include/compiler.h new file mode 100644 index 000000000..27b984349 --- /dev/null +++ b/roms/u-boot/include/compiler.h @@ -0,0 +1,162 @@ +/* + * Keep all the ugly #ifdef for system stuff here + */ + +#ifndef __COMPILER_H__ +#define __COMPILER_H__ + +#include +#include + +#ifdef USE_HOSTCC + +#if defined(__BEOS__) || \ + defined(__NetBSD__) || \ + defined(__FreeBSD__) || \ + defined(__sun__) || \ + defined(__APPLE__) +# include +#elif defined(__linux__) || defined(__WIN32__) || defined(__MINGW32__) || defined(__OpenBSD__) +# include +#endif + +#include +#include +#include +#include +#include + +#if !defined(__WIN32__) && !defined(__MINGW32__) +# include +#endif + +/* Not all systems (like Windows) has this define, and yes + * we do replace/emulate mmap() on those systems ... + */ +#ifndef MAP_FAILED +# define MAP_FAILED ((void *)-1) +#endif + +#include +#ifndef O_BINARY /* should be define'd on __WIN32__ */ +#define O_BINARY 0 +#endif + +#ifdef __linux__ +# include +# include +#elif defined(__MACH__) || defined(__FreeBSD__) +# include +#endif +#ifdef __FreeBSD__ +# include /* htole32 and friends */ +# define __BYTE_ORDER BYTE_ORDER +# define __LITTLE_ENDIAN LITTLE_ENDIAN +# define __BIG_ENDIAN BIG_ENDIAN +#elif defined(__OpenBSD__) +# include +# define __BYTE_ORDER BYTE_ORDER +# define __LITTLE_ENDIAN LITTLE_ENDIAN +# define __BIG_ENDIAN BIG_ENDIAN +#endif + +#include + +typedef uint8_t __u8; +typedef uint16_t __u16; +typedef uint32_t __u32; +typedef unsigned int uint; +typedef unsigned long ulong; + +#define uswap_16(x) \ + ((((x) & 0xff00) >> 8) | \ + (((x) & 0x00ff) << 8)) +#define uswap_32(x) \ + ((((x) & 0xff000000) >> 24) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x000000ff) << 24)) +#define _uswap_64(x, sfx) \ + ((((x) & 0xff00000000000000##sfx) >> 56) | \ + (((x) & 0x00ff000000000000##sfx) >> 40) | \ + (((x) & 0x0000ff0000000000##sfx) >> 24) | \ + (((x) & 0x000000ff00000000##sfx) >> 8) | \ + (((x) & 0x00000000ff000000##sfx) << 8) | \ + (((x) & 0x0000000000ff0000##sfx) << 24) | \ + (((x) & 0x000000000000ff00##sfx) << 40) | \ + (((x) & 0x00000000000000ff##sfx) << 56)) +#if defined(__GNUC__) +# define uswap_64(x) _uswap_64(x, ull) +#else +# define uswap_64(x) _uswap_64(x, ) +#endif + +#if __BYTE_ORDER == __LITTLE_ENDIAN +# define cpu_to_le16(x) (x) +# define cpu_to_le32(x) (x) +# define cpu_to_le64(x) (x) +# define le16_to_cpu(x) (x) +# define le32_to_cpu(x) (x) +# define le64_to_cpu(x) (x) +# define cpu_to_be16(x) uswap_16(x) +# define cpu_to_be32(x) uswap_32(x) +# define cpu_to_be64(x) uswap_64(x) +# define be16_to_cpu(x) uswap_16(x) +# define be32_to_cpu(x) uswap_32(x) +# define be64_to_cpu(x) uswap_64(x) +#else +# define cpu_to_le16(x) uswap_16(x) +# define cpu_to_le32(x) uswap_32(x) +# define cpu_to_le64(x) uswap_64(x) +# define le16_to_cpu(x) uswap_16(x) +# define le32_to_cpu(x) uswap_32(x) +# define le64_to_cpu(x) uswap_64(x) +# define cpu_to_be16(x) (x) +# define cpu_to_be32(x) (x) +# define cpu_to_be64(x) (x) +# define be16_to_cpu(x) (x) +# define be32_to_cpu(x) (x) +# define be64_to_cpu(x) (x) +#endif + +#else /* !USE_HOSTCC */ + +/* Type for `void *' pointers. */ +typedef unsigned long int uintptr_t; + +#include +#include +#include + +#if __SIZEOF_LONG__ == 8 +# define __WORDSIZE 64 +#elif __SIZEOF_LONG__ == 4 +# define __WORDSIZE 32 +#else +/* + * Assume 32-bit for now - only newer toolchains support this feature and + * this is only required for sandbox support at present. + */ +#define __WORDSIZE 32 +#endif + +#endif /* USE_HOSTCC */ + +#define likely(x) __builtin_expect(!!(x), 1) +#define unlikely(x) __builtin_expect(!!(x), 0) + +#ifdef __LP64__ +#define MEM_SUPPORT_64BIT_DATA 1 +#else +#define MEM_SUPPORT_64BIT_DATA 0 +#endif + +static inline bool host_build(void) { +#ifdef USE_HOSTCC + return true; +#else + return false; +#endif +} + +#endif diff --git a/roms/u-boot/include/config_distro_bootcmd.h b/roms/u-boot/include/config_distro_bootcmd.h new file mode 100644 index 000000000..2627c2a6a --- /dev/null +++ b/roms/u-boot/include/config_distro_bootcmd.h @@ -0,0 +1,504 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 + * NVIDIA Corporation + * + * Copyright 2014 Red Hat, Inc. + */ + +#ifndef _CONFIG_CMD_DISTRO_BOOTCMD_H +#define _CONFIG_CMD_DISTRO_BOOTCMD_H + +/* + * A note on error handling: It is possible for BOOT_TARGET_DEVICES to + * reference a device that is not enabled in the U-Boot configuration, e.g. + * it may include MMC in the list without CONFIG_CMD_MMC being enabled. Given + * that BOOT_TARGET_DEVICES is a macro that's expanded by the C pre-processor + * at compile time, it's not possible to detect and report such problems via + * a simple #ifdef/#error combination. Still, the code needs to report errors. + * The best way I've found to do this is to make BOOT_TARGET_DEVICES expand to + * reference a non-existent symbol, and have the name of that symbol encode + * the error message. Consequently, this file contains references to e.g. + * BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC. Given the + * prevalence of capitals here, this looks like a pre-processor macro and + * hence seems like it should be all capitals, but it's really an error + * message that includes some other pre-processor symbols in the text. + */ + +#define BOOTENV_SHARED_BLKDEV_BODY(devtypel) \ + "if " #devtypel " dev ${devnum}; then " \ + "devtype=" #devtypel "; " \ + "run scan_dev_for_boot_part; " \ + "fi\0" + +#define BOOTENV_SHARED_BLKDEV(devtypel) \ + #devtypel "_boot=" \ + BOOTENV_SHARED_BLKDEV_BODY(devtypel) + +#define BOOTENV_DEV_BLKDEV(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "devnum=" #instance "; " \ + "run " #devtypel "_boot\0" + +#define BOOTENV_DEV_NAME_BLKDEV(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#ifdef CONFIG_SANDBOX +#define BOOTENV_SHARED_HOST BOOTENV_SHARED_BLKDEV(host) +#define BOOTENV_DEV_HOST BOOTENV_DEV_BLKDEV +#define BOOTENV_DEV_NAME_HOST BOOTENV_DEV_NAME_BLKDEV +#else +#define BOOTENV_SHARED_HOST +#define BOOTENV_DEV_HOST \ + BOOT_TARGET_DEVICES_references_HOST_without_CONFIG_SANDBOX +#define BOOTENV_DEV_NAME_HOST \ + BOOT_TARGET_DEVICES_references_HOST_without_CONFIG_SANDBOX +#endif + +#ifdef CONFIG_CMD_MMC +#define BOOTENV_SHARED_MMC BOOTENV_SHARED_BLKDEV(mmc) +#define BOOTENV_DEV_MMC BOOTENV_DEV_BLKDEV +#define BOOTENV_DEV_NAME_MMC BOOTENV_DEV_NAME_BLKDEV +#else +#define BOOTENV_SHARED_MMC +#define BOOTENV_DEV_MMC \ + BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC +#define BOOTENV_DEV_NAME_MMC \ + BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC +#endif + +#ifdef CONFIG_CMD_UBIFS +#define BOOTENV_SHARED_UBIFS \ + "ubifs_boot=" \ + "env exists bootubipart || " \ + "env set bootubipart UBI; " \ + "env exists bootubivol || " \ + "env set bootubivol boot; " \ + "if ubi part ${bootubipart} && " \ + "ubifsmount ubi${devnum}:${bootubivol}; " \ + "then " \ + "devtype=ubi; " \ + "run scan_dev_for_boot; " \ + "fi\0" +#define BOOTENV_DEV_UBIFS BOOTENV_DEV_BLKDEV +#define BOOTENV_DEV_NAME_UBIFS BOOTENV_DEV_NAME_BLKDEV +#else +#define BOOTENV_SHARED_UBIFS +#define BOOTENV_DEV_UBIFS \ + BOOT_TARGET_DEVICES_references_UBIFS_without_CONFIG_CMD_UBIFS +#define BOOTENV_DEV_NAME_UBIFS \ + BOOT_TARGET_DEVICES_references_UBIFS_without_CONFIG_CMD_UBIFS +#endif + +#ifdef CONFIG_EFI_LOADER +#if defined(CONFIG_ARM64) +#define BOOTEFI_NAME "bootaa64.efi" +#elif defined(CONFIG_ARM) +#define BOOTEFI_NAME "bootarm.efi" +#elif defined(CONFIG_X86_RUN_32BIT) +#define BOOTEFI_NAME "bootia32.efi" +#elif defined(CONFIG_X86_RUN_64BIT) +#define BOOTEFI_NAME "bootx64.efi" +#elif defined(CONFIG_ARCH_RV32I) +#define BOOTEFI_NAME "bootriscv32.efi" +#elif defined(CONFIG_ARCH_RV64I) +#define BOOTEFI_NAME "bootriscv64.efi" +#endif +#endif + +#ifdef BOOTEFI_NAME +#if defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +/* + * On 32bit ARM systems there is a reasonable number of systems that follow + * the $soc-$board$boardver.dtb name scheme for their device trees. Use that + * scheme if we don't have an explicit fdtfile variable. + */ +#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \ + "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \ + "setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; " \ + "fi; " +#else +#ifndef BOOTENV_EFI_SET_FDTFILE_FALLBACK +#define BOOTENV_EFI_SET_FDTFILE_FALLBACK +#endif +#endif + +#ifdef CONFIG_CMD_BOOTEFI_BOOTMGR +#define BOOTENV_EFI_BOOTMGR \ + "boot_efi_bootmgr=" \ + "if fdt addr ${fdt_addr_r}; then " \ + "bootefi bootmgr ${fdt_addr_r};" \ + "else " \ + "bootefi bootmgr;" \ + "fi\0" +#else +#define BOOTENV_EFI_BOOTMGR +#endif + +#define BOOTENV_SHARED_EFI \ + BOOTENV_EFI_BOOTMGR \ + \ + "boot_efi_binary=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${kernel_addr_r} efi/boot/"BOOTEFI_NAME"; " \ + "if fdt addr ${fdt_addr_r}; then " \ + "bootefi ${kernel_addr_r} ${fdt_addr_r};" \ + "else " \ + "bootefi ${kernel_addr_r} ${fdtcontroladdr};" \ + "fi\0" \ + \ + "load_efi_dtb=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${fdt_addr_r} ${prefix}${efi_fdtfile}\0" \ + \ + "efi_dtb_prefixes=/ /dtb/ /dtb/current/\0" \ + "scan_dev_for_efi=" \ + "setenv efi_fdtfile ${fdtfile}; " \ + BOOTENV_EFI_SET_FDTFILE_FALLBACK \ + "for prefix in ${efi_dtb_prefixes}; do " \ + "if test -e ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${prefix}${efi_fdtfile}; then " \ + "run load_efi_dtb; " \ + "fi;" \ + "done;" \ + "run boot_efi_bootmgr;" \ + "if test -e ${devtype} ${devnum}:${distro_bootpart} " \ + "efi/boot/"BOOTEFI_NAME"; then " \ + "echo Found EFI removable media binary " \ + "efi/boot/"BOOTEFI_NAME"; " \ + "run boot_efi_binary; " \ + "echo EFI LOAD FAILED: continuing...; " \ + "fi; " \ + "setenv efi_fdtfile\0" +#define SCAN_DEV_FOR_EFI "run scan_dev_for_efi;" +#else +#define BOOTENV_SHARED_EFI +#define SCAN_DEV_FOR_EFI +#endif + +#ifdef CONFIG_SATA +#define BOOTENV_SHARED_SATA BOOTENV_SHARED_BLKDEV(sata) +#define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV +#define BOOTENV_DEV_NAME_SATA BOOTENV_DEV_NAME_BLKDEV +#else +#define BOOTENV_SHARED_SATA +#define BOOTENV_DEV_SATA \ + BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_SATA +#define BOOTENV_DEV_NAME_SATA \ + BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_SATA +#endif + +#ifdef CONFIG_NVME +#define BOOTENV_RUN_NVME_INIT "run nvme_init; " +#define BOOTENV_SET_NVME_NEED_INIT "setenv nvme_need_init; " +#define BOOTENV_SHARED_NVME \ + "nvme_init=" \ + "if ${nvme_need_init}; then " \ + "setenv nvme_need_init false; " \ + "nvme scan; " \ + "fi\0" \ + \ + "nvme_boot=" \ + BOOTENV_RUN_PCI_ENUM \ + BOOTENV_RUN_NVME_INIT \ + BOOTENV_SHARED_BLKDEV_BODY(nvme) +#define BOOTENV_DEV_NVME BOOTENV_DEV_BLKDEV +#define BOOTENV_DEV_NAME_NVME BOOTENV_DEV_NAME_BLKDEV +#else +#define BOOTENV_RUN_NVME_INIT +#define BOOTENV_SET_NVME_NEED_INIT +#define BOOTENV_SHARED_NVME +#define BOOTENV_DEV_NVME \ + BOOT_TARGET_DEVICES_references_NVME_without_CONFIG_NVME +#define BOOTENV_DEV_NAME_NVME \ + BOOT_TARGET_DEVICES_references_NVME_without_CONFIG_NVME +#endif + +#ifdef CONFIG_SCSI +#define BOOTENV_RUN_SCSI_INIT "run scsi_init; " +#define BOOTENV_SET_SCSI_NEED_INIT "scsi_need_init=; " +#define BOOTENV_SHARED_SCSI \ + "scsi_init=" \ + "if ${scsi_need_init}; then " \ + "scsi_need_init=false; " \ + "scsi scan; " \ + "fi\0" \ + \ + "scsi_boot=" \ + BOOTENV_RUN_SCSI_INIT \ + BOOTENV_SHARED_BLKDEV_BODY(scsi) +#define BOOTENV_DEV_SCSI BOOTENV_DEV_BLKDEV +#define BOOTENV_DEV_NAME_SCSI BOOTENV_DEV_NAME_BLKDEV +#else +#define BOOTENV_RUN_SCSI_INIT +#define BOOTENV_SET_SCSI_NEED_INIT +#define BOOTENV_SHARED_SCSI +#define BOOTENV_DEV_SCSI \ + BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI +#define BOOTENV_DEV_NAME_SCSI \ + BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI +#endif + +#ifdef CONFIG_IDE +#define BOOTENV_RUN_IDE_INIT "run ide_init; " +#define BOOTENV_SET_IDE_NEED_INIT "setenv ide_need_init; " +#define BOOTENV_SHARED_IDE \ + "ide_init=" \ + "if ${ide_need_init}; then " \ + "setenv ide_need_init false; " \ + "ide reset; " \ + "fi\0" \ + \ + "ide_boot=" \ + BOOTENV_RUN_IDE_INIT \ + BOOTENV_SHARED_BLKDEV_BODY(ide) +#define BOOTENV_DEV_IDE BOOTENV_DEV_BLKDEV +#define BOOTENV_DEV_NAME_IDE BOOTENV_DEV_NAME_BLKDEV +#else +#define BOOTENV_RUN_IDE_INIT +#define BOOTENV_SET_IDE_NEED_INIT +#define BOOTENV_SHARED_IDE +#define BOOTENV_DEV_IDE \ + BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_IDE +#define BOOTENV_DEV_NAME_IDE \ + BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_IDE +#endif + +#if defined(CONFIG_DM_PCI) +#define BOOTENV_RUN_PCI_ENUM "run boot_pci_enum; " +#define BOOTENV_SHARED_PCI \ + "boot_pci_enum=pci enum\0" +#else +#define BOOTENV_RUN_PCI_ENUM +#define BOOTENV_SHARED_PCI +#endif + +#ifdef CONFIG_CMD_USB +#define BOOTENV_RUN_NET_USB_START "run boot_net_usb_start; " +#define BOOTENV_SHARED_USB \ + "boot_net_usb_start=usb start\0" \ + "usb_boot=" \ + "usb start; " \ + BOOTENV_SHARED_BLKDEV_BODY(usb) +#define BOOTENV_DEV_USB BOOTENV_DEV_BLKDEV +#define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV +#else +#define BOOTENV_RUN_NET_USB_START +#define BOOTENV_SHARED_USB +#define BOOTENV_DEV_USB \ + BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB +#define BOOTENV_DEV_NAME_USB \ + BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB +#endif + +#ifdef CONFIG_CMD_VIRTIO +#define BOOTENV_RUN_VIRTIO_INIT "run virtio_init; " +#define BOOTENV_SET_VIRTIO_NEED_INIT "virtio_need_init=; " +#define BOOTENV_SHARED_VIRTIO \ + "virtio_init=" \ + "if ${virtio_need_init}; then " \ + "virtio_need_init=false; " \ + "virtio scan; " \ + "fi\0" \ + \ + "virtio_boot=" \ + BOOTENV_RUN_PCI_ENUM \ + BOOTENV_RUN_VIRTIO_INIT \ + BOOTENV_SHARED_BLKDEV_BODY(virtio) +#define BOOTENV_DEV_VIRTIO BOOTENV_DEV_BLKDEV +#define BOOTENV_DEV_NAME_VIRTIO BOOTENV_DEV_NAME_BLKDEV +#else +#define BOOTENV_RUN_VIRTIO_INIT +#define BOOTENV_SET_VIRTIO_NEED_INIT +#define BOOTENV_SHARED_VIRTIO +#define BOOTENV_DEV_VIRTIO \ + BOOT_TARGET_DEVICES_references_VIRTIO_without_CONFIG_CMD_VIRTIO +#define BOOTENV_DEV_NAME_VIRTIO \ + BOOT_TARGET_DEVICES_references_VIRTIO_without_CONFIG_CMD_VIRTIO +#endif + +#if defined(CONFIG_CMD_DHCP) +#if defined(CONFIG_EFI_LOADER) +/* http://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml */ +#if defined(CONFIG_ARM64) || defined(__aarch64__) +#define BOOTENV_EFI_PXE_ARCH "0xb" +#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00011:UNDI:003000" +#elif defined(CONFIG_ARM) || defined(__arm__) +#define BOOTENV_EFI_PXE_ARCH "0xa" +#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00010:UNDI:003000" +#elif defined(CONFIG_X86) || defined(__x86_64__) +#define BOOTENV_EFI_PXE_ARCH "0x7" +#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00007:UNDI:003000" +#elif defined(__i386__) +#define BOOTENV_EFI_PXE_ARCH "0x6" +#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00006:UNDI:003000" +#elif defined(CONFIG_ARCH_RV32I) || ((defined(__riscv) && __riscv_xlen == 32)) +#define BOOTENV_EFI_PXE_ARCH "0x19" +#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00025:UNDI:003000" +#elif defined(CONFIG_ARCH_RV64I) || ((defined(__riscv) && __riscv_xlen == 64)) +#define BOOTENV_EFI_PXE_ARCH "0x1b" +#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00027:UNDI:003000" +#elif defined(CONFIG_SANDBOX) +# error "sandbox EFI support is only supported on ARM and x86" +#else +#error Please specify an EFI client identifier +#endif + +/* + * Ask the dhcp server for an EFI binary. If we get one, check for a + * device tree in the same folder. Then boot everything. If the file was + * not an EFI binary, we just return from the bootefi command and continue. + */ +#define BOOTENV_EFI_RUN_DHCP \ + "setenv efi_fdtfile ${fdtfile}; " \ + BOOTENV_EFI_SET_FDTFILE_FALLBACK \ + "setenv efi_old_vci ${bootp_vci};" \ + "setenv efi_old_arch ${bootp_arch};" \ + "setenv bootp_vci " BOOTENV_EFI_PXE_VCI ";" \ + "setenv bootp_arch " BOOTENV_EFI_PXE_ARCH ";" \ + "if dhcp ${kernel_addr_r}; then " \ + "tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};" \ + "if fdt addr ${fdt_addr_r}; then " \ + "bootefi ${kernel_addr_r} ${fdt_addr_r}; " \ + "else " \ + "bootefi ${kernel_addr_r} ${fdtcontroladdr};" \ + "fi;" \ + "fi;" \ + "setenv bootp_vci ${efi_old_vci};" \ + "setenv bootp_arch ${efi_old_arch};" \ + "setenv efi_fdtfile;" \ + "setenv efi_old_arch;" \ + "setenv efi_old_vci;" +#else +#define BOOTENV_EFI_RUN_DHCP +#endif +#define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \ + "bootcmd_dhcp=" \ + "setenv devtype " #devtypel "; " \ + BOOTENV_RUN_NET_USB_START \ + BOOTENV_RUN_PCI_ENUM \ + "if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \ + "source ${scriptaddr}; " \ + "fi;" \ + BOOTENV_EFI_RUN_DHCP \ + "\0" +#define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \ + "dhcp " +#else +#define BOOTENV_DEV_DHCP \ + BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP +#define BOOTENV_DEV_NAME_DHCP \ + BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP +#endif + +#if defined(CONFIG_CMD_DHCP) && defined(CONFIG_CMD_PXE) +#define BOOTENV_DEV_PXE(devtypeu, devtypel, instance) \ + "bootcmd_pxe=" \ + BOOTENV_RUN_NET_USB_START \ + BOOTENV_RUN_PCI_ENUM \ + "dhcp; " \ + "if pxe get; then " \ + "pxe boot; " \ + "fi\0" +#define BOOTENV_DEV_NAME_PXE(devtypeu, devtypel, instance) \ + "pxe " +#else +#define BOOTENV_DEV_PXE \ + BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE +#define BOOTENV_DEV_NAME_PXE \ + BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE +#endif + +#define BOOTENV_DEV_NAME(devtypeu, devtypel, instance) \ + BOOTENV_DEV_NAME_##devtypeu(devtypeu, devtypel, instance) +#define BOOTENV_BOOT_TARGETS \ + "boot_targets=" BOOT_TARGET_DEVICES(BOOTENV_DEV_NAME) "\0" + +#define BOOTENV_DEV(devtypeu, devtypel, instance) \ + BOOTENV_DEV_##devtypeu(devtypeu, devtypel, instance) +#define BOOTENV \ + BOOTENV_SHARED_HOST \ + BOOTENV_SHARED_MMC \ + BOOTENV_SHARED_PCI \ + BOOTENV_SHARED_USB \ + BOOTENV_SHARED_SATA \ + BOOTENV_SHARED_SCSI \ + BOOTENV_SHARED_NVME \ + BOOTENV_SHARED_IDE \ + BOOTENV_SHARED_UBIFS \ + BOOTENV_SHARED_EFI \ + BOOTENV_SHARED_VIRTIO \ + "boot_prefixes=/ /boot/\0" \ + "boot_scripts=boot.scr.uimg boot.scr\0" \ + "boot_script_dhcp=boot.scr.uimg\0" \ + BOOTENV_BOOT_TARGETS \ + \ + "boot_syslinux_conf=extlinux/extlinux.conf\0" \ + "boot_extlinux=" \ + "sysboot ${devtype} ${devnum}:${distro_bootpart} any " \ + "${scriptaddr} ${prefix}${boot_syslinux_conf}\0" \ + \ + "scan_dev_for_extlinux=" \ + "if test -e ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${prefix}${boot_syslinux_conf}; then " \ + "echo Found ${prefix}${boot_syslinux_conf}; " \ + "run boot_extlinux; " \ + "echo SCRIPT FAILED: continuing...; " \ + "fi\0" \ + \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "source ${scriptaddr}\0" \ + \ + "scan_dev_for_scripts=" \ + "for script in ${boot_scripts}; do " \ + "if test -e ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${prefix}${script}; then " \ + "echo Found U-Boot script " \ + "${prefix}${script}; " \ + "run boot_a_script; " \ + "echo SCRIPT FAILED: continuing...; " \ + "fi; " \ + "done\0" \ + \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_extlinux; " \ + "run scan_dev_for_scripts; " \ + "done;" \ + SCAN_DEV_FOR_EFI \ + "\0" \ + \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} -bootable devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done; " \ + "setenv devplist\0" \ + \ + BOOT_TARGET_DEVICES(BOOTENV_DEV) \ + \ + "distro_bootcmd=" BOOTENV_SET_SCSI_NEED_INIT \ + BOOTENV_SET_NVME_NEED_INIT \ + BOOTENV_SET_IDE_NEED_INIT \ + BOOTENV_SET_VIRTIO_NEED_INIT \ + "for target in ${boot_targets}; do " \ + "run bootcmd_${target}; " \ + "done\0" + +#ifndef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "run distro_bootcmd" +#endif + +#endif /* _CONFIG_CMD_DISTRO_BOOTCMD_H */ diff --git a/roms/u-boot/include/config_fallbacks.h b/roms/u-boot/include/config_fallbacks.h new file mode 100644 index 000000000..a318926fe --- /dev/null +++ b/roms/u-boot/include/config_fallbacks.h @@ -0,0 +1,55 @@ +/* + * Copyright 2012 Texas Instruments + * + * This file is licensed under the terms of the GNU General Public + * License Version 2. This file is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __CONFIG_FALLBACKS_H +#define __CONFIG_FALLBACKS_H + +#ifdef CONFIG_SPL +#ifdef CONFIG_SPL_PAD_TO +#ifdef CONFIG_SPL_MAX_SIZE +#if CONFIG_SPL_PAD_TO && CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE +#error CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE +#endif +#endif +#else +#ifdef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE +#else +#define CONFIG_SPL_PAD_TO 0 +#endif +#endif +#endif + +#ifndef CONFIG_SYS_BAUDRATE_TABLE +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#endif + +/* Console I/O Buffer Size */ +#ifndef CONFIG_SYS_CBSIZE +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 +#else +#define CONFIG_SYS_CBSIZE 256 +#endif +#endif + +#ifndef CONFIG_SYS_PBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#endif + +#ifndef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 16 +#endif + +#if CONFIG_IS_ENABLED(DM_I2C) +# ifdef CONFIG_SYS_I2C +# error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used" +# endif +#endif + +#endif /* __CONFIG_FALLBACKS_H */ diff --git a/roms/u-boot/include/config_fsl_chain_trust.h b/roms/u-boot/include/config_fsl_chain_trust.h new file mode 100644 index 000000000..3922241be --- /dev/null +++ b/roms/u-boot/include/config_fsl_chain_trust.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __CONFIG_FSL_CHAIN_TRUST_H +#define __CONFIG_FSL_CHAIN_TRUST_H + +#include + +#ifdef CONFIG_CHAIN_OF_TRUST + +#ifndef CONFIG_EXTRA_ENV +#define CONFIG_EXTRA_ENV "" +#endif + +/* + * Control should not reach back to uboot after validation of images + * for secure boot flow and therefore bootscript should have + * the bootm command. If control reaches back to uboot anyhow + * after validating images, core should just spin. + */ + +/* + * Define the key hash for boot script here if public/private key pair used to + * sign bootscript are different from the SRK hash put in the fuse + * Example of defining KEY_HASH is + * #define CONFIG_BOOTSCRIPT_KEY_HASH \ + * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" + */ + +#ifdef CONFIG_USE_BOOTARGS +#define CONFIG_SET_BOOTARGS "setenv bootargs \'" CONFIG_BOOTARGS" \';" +#else +#define CONFIG_SET_BOOTARGS "setenv bootargs \'root=/dev/ram " \ + "rw console=ttyS0,115200 ramdisk_size=600000\';" +#endif + + +#ifdef CONFIG_BOOTSCRIPT_KEY_HASH +#define CONFIG_SECBOOT \ + "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ + CONFIG_SET_BOOTARGS \ + CONFIG_EXTRA_ENV \ + "esbc_validate $bs_hdraddr " \ + __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \ + "source $img_addr;" \ + "esbc_halt\0" +#else +#define CONFIG_SECBOOT \ + "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ + CONFIG_SET_BOOTARGS \ + CONFIG_EXTRA_ENV \ + "esbc_validate $bs_hdraddr;" \ + "source $img_addr;" \ + "esbc_halt\0" +#endif + +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BS_COPY_ENV \ + "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ + "setenv bs_hdr_device " __stringify(CONFIG_BS_HDR_ADDR_DEVICE)";" \ + "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \ + "setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \ + "setenv bs_device " __stringify(CONFIG_BS_ADDR_DEVICE)";" \ + "setenv bs_size " __stringify(CONFIG_BS_SIZE)";" + +/* For secure boot flow, default environment used will be used */ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_NAND_BOOT) || \ + defined(CONFIG_SD_BOOT) +#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_NAND_BOOT) +#define CONFIG_BS_COPY_CMD \ + "nand read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ + "nand read $bs_ram $bs_device $bs_size ;" +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_BS_COPY_CMD \ + "mmc read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ + "mmc read $bs_ram $bs_device $bs_size ;" +#endif +#else +#define CONFIG_BS_COPY_CMD \ + "cp.b $bs_hdr_device $bs_hdr_ram $bs_hdr_size ;" \ + "cp.b $bs_device $bs_ram $bs_size ;" +#endif +#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ + +#ifndef CONFIG_BS_COPY_ENV +#define CONFIG_BS_COPY_ENV +#endif + +#ifndef CONFIG_BS_COPY_CMD +#define CONFIG_BS_COPY_CMD +#endif + +#define CONFIG_CHAIN_BOOT_CMD CONFIG_BS_COPY_ENV \ + CONFIG_BS_COPY_CMD \ + CONFIG_SECBOOT + +#endif +#endif diff --git a/roms/u-boot/include/config_phylib_all_drivers.h b/roms/u-boot/include/config_phylib_all_drivers.h new file mode 100644 index 000000000..8e587bc7e --- /dev/null +++ b/roms/u-boot/include/config_phylib_all_drivers.h @@ -0,0 +1,15 @@ +/* + * Enable all PHYs + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * Copyright 2011 Freescale Semiconductor, Inc. + * author Andy Fleming + * + */ +#ifndef _CONFIG_PHYLIB_ALL_H +#define _CONFIG_PHYLIB_ALL_H + +#endif /*_CONFIG_PHYLIB_ALL_H */ diff --git a/roms/u-boot/include/config_uncmd_spl.h b/roms/u-boot/include/config_uncmd_spl.h new file mode 100644 index 000000000..af7e3e49f --- /dev/null +++ b/roms/u-boot/include/config_uncmd_spl.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Ilya Yanok, ilya.yanok@gmail.com + */ + +#ifndef __CONFIG_UNCMD_SPL_H__ +#define __CONFIG_UNCMD_SPL_H__ + +#ifdef CONFIG_SPL_BUILD +/* SPL needs only BOOTP + TFTP so undefine other stuff to save space */ + +#ifndef CONFIG_SPL_DM +#undef CONFIG_DM_SERIAL +#undef CONFIG_DM_I2C +#undef CONFIG_DM_SPI +#endif + +#undef CONFIG_DM_STDIO + +#endif /* CONFIG_SPL_BUILD */ +#endif /* __CONFIG_UNCMD_SPL_H__ */ diff --git a/roms/u-boot/include/configs/10m50_devboard.h b/roms/u-boot/include/configs/10m50_devboard.h new file mode 100644 index 000000000..3ffc74492 --- /dev/null +++ b/roms/u-boot/include/configs/10m50_devboard.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2005, Psyent Corporation + * Scott McNutt + * (C) Copyright 2010, Thomas Chou + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * BOARD/CPU + */ + +/* + * SERIAL + */ +#define CONFIG_SYS_NS16550_MEM32 + +/* + * Flash + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 + +/* + * NET options + */ +#define CONFIG_SYS_RX_ETH_BUFFER 0 +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * MEMORY ORGANIZATION + * -Monitor at top of sdram. + * -The heap is placed below the monitor + * -The stack is placed below the heap (&grows down). + */ +#define CONFIG_SYS_SDRAM_BASE 0xc8000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_MALLOC_LEN 0x20000 + +/* + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above + * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + */ + +/* + * MISC + */ +#define CONFIG_SYS_LOAD_ADDR 0xcc000000 /* Half of RAM */ +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/3c120_devboard.h b/roms/u-boot/include/configs/3c120_devboard.h new file mode 100644 index 000000000..3f065ff31 --- /dev/null +++ b/roms/u-boot/include/configs/3c120_devboard.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2005, Psyent Corporation + * Scott McNutt + * (C) Copyright 2010, Thomas Chou + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * BOARD/CPU + */ + +/* + * SERIAL + */ + +/* + * CFI Flash + */ +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +/* + * NET options + */ +#define CONFIG_SYS_RX_ETH_BUFFER 0 +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * MEMORY ORGANIZATION + * -Monitor at top of sdram. + * -The heap is placed below the monitor + * -The stack is placed below the heap (&grows down). + */ +#define CONFIG_SYS_SDRAM_BASE 0xD0000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_MALLOC_LEN 0x20000 + +/* + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above + * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + */ + +/* + * MISC + */ +#define CONFIG_SYS_LOAD_ADDR 0xd4000000 /* Half of RAM */ +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/M5208EVBE.h b/roms/u-boot/include/configs/M5208EVBE.h new file mode 100644 index 000000000..fc389b8e8 --- /dev/null +++ b/roms/u-boot/include/configs/M5208EVBE.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the Freescale MCF5208EVBe. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +#ifndef _M5208EVBE_H +#define _M5208EVBE_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 5000 + +#ifdef CONFIG_MCFFEC +# define CONFIG_MII_INIT 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_HAS_ETH1 +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +/* Timer */ +#define CONFIG_MCFTMR + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 80000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +#define CONFIG_UDP_CHECKSUM + +#ifdef CONFIG_MCFFEC +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +#endif /* CONFIG_MCFFEC */ + +#define CONFIG_HOSTNAME "M5208EVBe" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 3ffff;" \ + "era 0 3ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ + +#define CONFIG_SYS_LOAD_ADDR 0x40010000 + +#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ +#define CONFIG_SYS_PLL_ODR 0x36 +#define CONFIG_SYS_PLL_FDR 0x7D + +#define CONFIG_SYS_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/* Definitions for initial stack pointer and data area (in DPRAM) */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CONFIG_SYS_SDRAM_CFG1 0x43711630 +#define CONFIG_SYS_SDRAM_CFG2 0x56670000 +#define CONFIG_SYS_SDRAM_CTRL 0xE1002000 +#define CONFIG_SYS_SDRAM_EMOD 0x80010000 +#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 + +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) + +/* FLASH organization */ +#ifdef CONFIG_SYS_FLASH_CFI +# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ +#endif + +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE + +/* + * Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ + +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + env/embedded.o(.text*); + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + +/* Chipselect bank definitions */ +/* + * CS0 - NOR Flash + * CS1 - Available + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ +#define CONFIG_SYS_CS0_BASE 0 +#define CONFIG_SYS_CS0_MASK 0x007F0001 +#define CONFIG_SYS_CS0_CTRL 0x00001FA0 + +#endif /* _M5208EVBE_H */ diff --git a/roms/u-boot/include/configs/M52277EVB.h b/roms/u-boot/include/configs/M52277EVB.h new file mode 100644 index 000000000..0428be729 --- /dev/null +++ b/roms/u-boot/include/configs/M52277EVB.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the Freescale MCF52277 EVB board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M52277EVB_H +#define _M52277EVB_H + +#include + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +#undef CONFIG_WATCHDOG + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#define CONFIG_HOSTNAME "M52277EVB" +#define CONFIG_SYS_UBOOT_END 0x3FFFF +#define CONFIG_SYS_LOAD_ADDR2 0x40010007 +#ifdef CONFIG_SYS_STMICRO_BOOT +/* ST Micro serial flash */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=0x40010000\0" \ + "uboot=u-boot.bin\0" \ + "load=loadb ${loadaddr} ${baudrate};" \ + "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ + "upd=run load; run prog\0" \ + "prog=sf probe 0:2 10000 1;" \ + "sf erase 0 30000;" \ + "sf write ${loadaddr} 0 30000;" \ + "save\0" \ + "" +#endif +#ifdef CONFIG_SYS_SPANSION_BOOT +#define CONFIG_EXTRA_ENV_SETTINGS \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=0x40010000\0" \ + "uboot=u-boot.bin\0" \ + "load=loadb ${loadaddr} ${baudrate}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ + " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ + "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ + __stringify(CONFIG_SYS_UBOOT_END) ";" \ + "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ + " ${filesize}; save\0" \ + "updsbf=run loadsbf; run progsbf\0" \ + "loadsbf=loadb ${loadaddr} ${baudrate};" \ + "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ + "progsbf=sf probe 0:2 10000 1;" \ + "sf erase 0 30000;" \ + "sf write ${loadaddr} 0 30000;" \ + "" +#endif + +/* LCD */ +#ifdef CONFIG_CMD_BMP +#define CONFIG_LCD_LOGO +#define CONFIG_SHARP_LQ035Q7DH06 +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 +#define CONFIG_SYS_USB_EHCI_CPU_INIT +#endif + +/* Realtime clock */ +#define CONFIG_MCFRTC +#undef RTC_DEBUG +#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) + +/* Timer */ +#define CONFIG_MCFTMR + +/* I2c */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 80000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +/* DSPI and Serial Flash */ +#define CONFIG_CF_DSPI +#define CONFIG_SYS_SBFHDR_SIZE 0x7 + +/* Input, PCI, Flexbus, and VCO */ +#define CONFIG_EXTRA_CLOCK + +#define CONFIG_SYS_INPUT_CLKSRC 16000000 + +#define CONFIG_PRAM 2048 /* 2048 KB */ + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) + +#define CONFIG_SYS_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/* + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) +#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ +#define CONFIG_SYS_SDRAM_CFG1 0x43711630 +#define CONFIG_SYS_SDRAM_CFG2 0x56670000 +#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 +#define CONFIG_SYS_SDRAM_EMOD 0x81810000 +#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 +#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 + +#ifdef CONFIG_CF_SBF +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) +#else +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) + +/* + * Configuration for environment + * Environment is not embedded in u-boot. First time runing may have env + * crc error warning if there is no correct environment on the flash. + */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#ifdef CONFIG_SYS_STMICRO_BOOT +# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE +#endif +#ifdef CONFIG_SYS_SPANSION_BOOT +# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE +#endif + +#ifdef CONFIG_SYS_FLASH_CFI +# define CONFIG_FLASH_SPANSION_S29WS_N 1 +# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CONFIG_SYS_FLASH_CHECKSUM +# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } +#endif + +#define LDS_BOARD_TEXT \ + arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ + arch/m68k/lib/built-in.o (.text*) + +/* + * This is setting for JFFS2 support in u-boot. + * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. + */ +#ifdef CONFIG_CMD_JFFS2 +# define CONFIG_JFFS2_DEV "nor0" +# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) +# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ +/* + * CS0 - NOR Flash + * CS1 - Available + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ + +#ifdef CONFIG_CF_SBF +#define CONFIG_SYS_CS0_BASE 0x04000000 +#define CONFIG_SYS_CS0_MASK 0x00FF0001 +#define CONFIG_SYS_CS0_CTRL 0x00001FA0 +#else +#define CONFIG_SYS_CS0_BASE 0x00000000 +#define CONFIG_SYS_CS0_MASK 0x00FF0001 +#define CONFIG_SYS_CS0_CTRL 0x00001FA0 +#endif + +#endif /* _M52277EVB_H */ diff --git a/roms/u-boot/include/configs/M5235EVB.h b/roms/u-boot/include/configs/M5235EVB.h new file mode 100644 index 000000000..4ab3d4831 --- /dev/null +++ b/roms/u-boot/include/configs/M5235EVB.h @@ -0,0 +1,194 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the Freescale MCF5329 FireEngine board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5235EVB_H +#define _M5235EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#ifdef CONFIG_MCFFEC +# define CONFIG_MII_INIT 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +/* Timer */ +#define CONFIG_MCFTMR + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_i2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 80000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR +#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) +#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) +#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#define CONFIG_BOOTFILE "u-boot.bin" +#ifdef CONFIG_MCFFEC +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME "M5235EVB" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) + +#define CONFIG_SYS_CLK 75000000 +#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 + +#define CONFIG_SYS_MBAR 0x40000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_CTRL 0x21 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ + +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#ifdef CONFIG_SYS_FLASH_CFI +# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +#ifdef NORFLASH_PS32BIT +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT +#else +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#endif +# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +#endif + +#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ + +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + env/embedded.o(.text); + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - Available + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + * CS6 - Available + * CS7 - Available + */ +#ifdef NORFLASH_PS32BIT +# define CONFIG_SYS_CS0_BASE 0xFFC00000 +# define CONFIG_SYS_CS0_MASK 0x003f0001 +# define CONFIG_SYS_CS0_CTRL 0x00001D00 +#else +# define CONFIG_SYS_CS0_BASE 0xFFE00000 +# define CONFIG_SYS_CS0_MASK 0x001f0001 +# define CONFIG_SYS_CS0_CTRL 0x00001D80 +#endif + +#endif /* _M5329EVB_H */ diff --git a/roms/u-boot/include/configs/M5249EVB.h b/roms/u-boot/include/configs/M5249EVB.h new file mode 100644 index 000000000..1a1a11076 --- /dev/null +++ b/roms/u-boot/include/configs/M5249EVB.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the esd TASREG board. + * + * (C) Copyright 2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5249EVB_H +#define _M5249EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCFTMR + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +#undef CONFIG_WATCHDOG + +#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ + +/* + * BOOTP options + */ +#undef CONFIG_BOOTP_BOOTFILESIZE + +#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ + +/* + * Clock configuration: enable only one of the following options + */ + +#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ +#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ +#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CONFIG_SYS_MBAR2 0x80000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + env/embedded.o(.text); + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) + +#if 0 /* test-only */ +#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ +#endif + +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) + +#define CONFIG_SYS_MONITOR_LEN 0x20000 +#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#ifdef CONFIG_SYS_FLASH_CFI + +# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CONFIG_SYS_FLASH_CHECKSUM +# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ + CF_ADDRMASK(2) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ + +/* CS0 - AMD Flash, address 0xffc00000 */ +#define CONFIG_SYS_CS0_BASE 0xffe00000 +#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ +/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ +#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ + +/* CS1 - FPGA, address 0xe0000000 */ +#define CONFIG_SYS_CS1_BASE 0xe0000000 +#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ +#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ + +/*----------------------------------------------------------------------- + * Port configuration + */ +#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ +#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ + +#endif /* M5249 */ diff --git a/roms/u-boot/include/configs/M5253DEMO.h b/roms/u-boot/include/configs/M5253DEMO.h new file mode 100644 index 000000000..54f6fa7c1 --- /dev/null +++ b/roms/u-boot/include/configs/M5253DEMO.h @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Hayden Fraser (Hayden.Fraser@freescale.com) + */ + +#ifndef _M5253DEMO_H +#define _M5253DEMO_H + +#include + +#define CONFIG_MCFTMR + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +#undef CONFIG_WATCHDOG /* disable watchdog */ + + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ + +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + env/embedded.o(.text*); + +#ifdef CONFIG_IDE +/* ATA */ +# define CONFIG_IDE_RESET 1 +# define CONFIG_IDE_PREINIT 1 +# define CONFIG_ATAPI +# undef CONFIG_LBA48 + +# define CONFIG_SYS_IDE_MAXBUS 1 +# define CONFIG_SYS_IDE_MAXDEVICE 2 + +# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) +# define CONFIG_SYS_ATA_IDE0_OFFSET 0 + +# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ +# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ +# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ +# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ +#endif + +#define CONFIG_DRIVER_DM9000 +#ifdef CONFIG_DRIVER_DM9000 +# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) +# define DM9000_IO CONFIG_DM9000_BASE +# define DM9000_DATA (CONFIG_DM9000_BASE + 4) +# undef CONFIG_DM9000_DEBUG +# define CONFIG_DM9000_BYTE_SWAPPED + +# define CONFIG_OVERWRITE_ETHADDR_ONCE + +# define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0xff800000 0xff82ffff;" \ + "era 0xff800000 0xff82ffff;" \ + "cp.b ${loadaddr} 0xff800000 ${filesize};" \ + "save\0" \ + "" +#endif + +#define CONFIG_HOSTNAME "M5253DEMO" + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 80000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR +#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) +#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) +#define CONFIG_SYS_I2C_PINMUX_SET (0) + +#define CONFIG_SYS_LOAD_ADDR 0x00100000 + +#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ +#define CONFIG_SYS_FAST_CLK +#ifdef CONFIG_SYS_FAST_CLK +# define CONFIG_SYS_PLLCR 0x1243E054 +# define CONFIG_SYS_CLK 140000000 +#else +# define CONFIG_SYS_PLLCR 0x135a4140 +# define CONFIG_SYS_CLK 70000000 +#endif + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ + +/* + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ + +#ifdef CONFIG_MONITOR_IS_IN_RAM +# define CONFIG_SYS_MONITOR_BASE 0x20000 +#else +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif + +#define CONFIG_SYS_MONITOR_LEN 0x40000 +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) + +/* FLASH organization */ +#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 + +#define FLASH_SST6401B 0x200 +#define SST_ID_xF6401B 0x236D236D + +#ifdef CONFIG_SYS_FLASH_CFI +/* + * Unable to use CFI driver, due to incompatible sector erase command by SST. + * Amd/Atmel use 0x30 for sector erase, SST use 0x50. + * 0x30 is block erase in SST + */ +# define CONFIG_SYS_FLASH_SIZE 0x800000 +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_FLASH_CFI_LEGACY +#else +# define CONFIG_SYS_SST_SECT 2048 +# define CONFIG_SYS_SST_SECTSZ 0x1000 +# define CONFIG_SYS_FLASH_WRITE_TOUT 500 +#endif + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ + CF_ADDRMASK(8) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + +/* Port configuration */ +#define CONFIG_SYS_FECI2C 0xF0 + +#define CONFIG_SYS_CS0_BASE 0xFF800000 +#define CONFIG_SYS_CS0_MASK 0x007F0021 +#define CONFIG_SYS_CS0_CTRL 0x00001D80 + +#define CONFIG_SYS_CS1_BASE 0xE0000000 +#define CONFIG_SYS_CS1_MASK 0x00000001 +#define CONFIG_SYS_CS1_CTRL 0x00003DD8 + +/*----------------------------------------------------------------------- + * Port configuration + */ +#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ +#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ + +#endif /* _M5253DEMO_H */ diff --git a/roms/u-boot/include/configs/M5272C3.h b/roms/u-boot/include/configs/M5272C3.h new file mode 100644 index 000000000..2cdd4369d --- /dev/null +++ b/roms/u-boot/include/configs/M5272C3.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the Motorola MC5272C3 board. + * + * (C) Copyright 2003 Josef Baumgartner + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5272C3_H +#define _M5272C3_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCFTMR + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ + +#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ + +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + env/embedded.o(.text); + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#ifdef CONFIG_MCFFEC +# define CONFIG_MII_INIT 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +#ifdef CONFIG_MCFFEC +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +#endif /* CONFIG_MCFFEC */ + +#define CONFIG_HOSTNAME "M5272C3" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" + +#define CONFIG_SYS_LOAD_ADDR 0x20000 +#define CONFIG_SYS_CLK 66000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CONFIG_SYS_SCR 0x0003 +#define CONFIG_SYS_SPR 0xffff + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ +#define CONFIG_SYS_FLASH_BASE 0xffe00000 + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_BASE 0x20000 +#else +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif + +#define CONFIG_SYS_MONITOR_LEN 0x20000 +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/* + * FLASH organization + */ +#ifdef CONFIG_SYS_FLASH_CFI +# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ +#define CONFIG_SYS_BR0_PRELIM 0xFFE00201 +#define CONFIG_SYS_OR0_PRELIM 0xFFE00014 +#define CONFIG_SYS_BR1_PRELIM 0 +#define CONFIG_SYS_OR1_PRELIM 0 +#define CONFIG_SYS_BR2_PRELIM 0x30000001 +#define CONFIG_SYS_OR2_PRELIM 0xFFF80000 +#define CONFIG_SYS_BR3_PRELIM 0 +#define CONFIG_SYS_OR3_PRELIM 0 +#define CONFIG_SYS_BR4_PRELIM 0 +#define CONFIG_SYS_OR4_PRELIM 0 +#define CONFIG_SYS_BR5_PRELIM 0 +#define CONFIG_SYS_OR5_PRELIM 0 +#define CONFIG_SYS_BR6_PRELIM 0 +#define CONFIG_SYS_OR6_PRELIM 0 +#define CONFIG_SYS_BR7_PRELIM 0x00000701 +#define CONFIG_SYS_OR7_PRELIM 0xFFC0007C + +/*----------------------------------------------------------------------- + * Port configuration + */ +#define CONFIG_SYS_PACNT 0x00000000 +#define CONFIG_SYS_PADDR 0x0000 +#define CONFIG_SYS_PADAT 0x0000 +#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ +#define CONFIG_SYS_PBDDR 0x0000 +#define CONFIG_SYS_PBDAT 0x0000 +#define CONFIG_SYS_PDCNT 0x00000000 +#endif /* _M5272C3_H */ diff --git a/roms/u-boot/include/configs/M5275EVB.h b/roms/u-boot/include/configs/M5275EVB.h new file mode 100644 index 000000000..ed93f4ad7 --- /dev/null +++ b/roms/u-boot/include/configs/M5275EVB.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the Motorola MC5275EVB board. + * + * By Arthur Shipkowski + * Copyright (C) 2005 Videon Central, Inc. + * + * Based off of M5272C3 board code by Josef Baumgartner + * + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5275EVB_H +#define _M5275EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MCFTMR + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ + +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + env/embedded.o(.text); + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* Available command configuration */ + +#ifdef CONFIG_MCFFEC +#define CONFIG_MII_INIT 1 +#define CONFIG_SYS_DISCOVER_PHY +#define CONFIG_SYS_RX_ETH_BUFFER 8 +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_HAS_ETH1 +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +#ifndef CONFIG_SYS_DISCOVER_PHY +#define FECDUPLEX FULL +#define FECSPEED _100BASET +#else +#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#endif +#endif +#endif + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 80000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR +#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) +#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) +#define CONFIG_SYS_I2C_PINMUX_SET (0x000F) + +#define CONFIG_SYS_LOAD_ADDR 0x800000 + +#define CONFIG_BOOTCOMMAND "bootm ffe40000" + +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_RETRY_COUNT 5 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${uboot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" + +#define CONFIG_SYS_CLK 150000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CONFIG_SYS_MBAR 0x40000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_BASE 0x20000 +#else +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif + +#define CONFIG_SYS_MONITOR_LEN 0x20000 +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 + +#define CONFIG_SYS_FLASH_SIZE 0x200000 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ +#define CONFIG_SYS_CS0_BASE 0xffe00000 +#define CONFIG_SYS_CS0_CTRL 0x00001980 +#define CONFIG_SYS_CS0_MASK 0x001F0001 + +#define CONFIG_SYS_CS1_BASE 0x30000000 +#define CONFIG_SYS_CS1_CTRL 0x00001900 +#define CONFIG_SYS_CS1_MASK 0x00070001 + +/*----------------------------------------------------------------------- + * Port configuration + */ +#define CONFIG_SYS_FECI2C 0x0FA0 + +#endif /* _M5275EVB_H */ diff --git a/roms/u-boot/include/configs/M5282EVB.h b/roms/u-boot/include/configs/M5282EVB.h new file mode 100644 index 000000000..6a50a25d3 --- /dev/null +++ b/roms/u-boot/include/configs/M5282EVB.h @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the Motorola MC5282EVB board. + * + * (C) Copyright 2003 Josef Baumgartner + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _CONFIG_M5282EVB_H +#define _CONFIG_M5282EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCFTMR + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ + +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + env/embedded.o(.text*); + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#ifdef CONFIG_MCFFEC +# define CONFIG_MII_INIT 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +#ifdef CONFIG_MCFFEC +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +#endif /* CONFIG_MCFFEC */ + +#define CONFIG_HOSTNAME "M5282EVB" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" + +#define CONFIG_SYS_LOAD_ADDR 0x20000 + +#define CONFIG_SYS_CLK 64000000 + +/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ + +#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ +#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +#define CONFIG_SYS_MBAR 0x40000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 +#define CONFIG_SYS_INT_FLASH_ENABLE 0x21 + +/* If M5282 port is fully implemented the monitor base will be behind + * the vector table. */ +#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#else +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ +#endif + +#define CONFIG_SYS_MONITOR_LEN 0x20000 +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#ifdef CONFIG_SYS_FLASH_CFI + +# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CONFIG_SYS_FLASH_CHECKSUM +# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ + CF_CACR_CEIB | CF_CACR_DBWE | \ + CF_CACR_EUSP) + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ +#define CONFIG_SYS_CS0_BASE 0xFFE00000 +#define CONFIG_SYS_CS0_CTRL 0x00001980 +#define CONFIG_SYS_CS0_MASK 0x001F0001 + +/*----------------------------------------------------------------------- + * Port configuration + */ +#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ +#define CONFIG_SYS_PADDR 0x0000000 +#define CONFIG_SYS_PADAT 0x0000000 + +#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ +#define CONFIG_SYS_PBDDR 0x0000000 +#define CONFIG_SYS_PBDAT 0x0000000 + +#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ +#define CONFIG_SYS_PCDDR 0x0000000 +#define CONFIG_SYS_PCDAT 0x0000000 + +#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ +#define CONFIG_SYS_PCDDR 0x0000000 +#define CONFIG_SYS_PCDAT 0x0000000 + +#define CONFIG_SYS_PEHLPAR 0xC0 +#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ +#define CONFIG_SYS_DDRUA 0x05 +#define CONFIG_SYS_PJPAR 0xFF + +#endif /* _CONFIG_M5282EVB_H */ diff --git a/roms/u-boot/include/configs/M53017EVB.h b/roms/u-boot/include/configs/M53017EVB.h new file mode 100644 index 000000000..b934dc138 --- /dev/null +++ b/roms/u-boot/include/configs/M53017EVB.h @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the Freescale MCF53017EVB. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M53017EVB_H +#define _M53017EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 5000 + +#define CONFIG_SYS_UNIFY_CACHE + +#ifdef CONFIG_MCFFEC +# define CONFIG_MII_INIT 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_TX_ETH_BUFFER 8 +# define CONFIG_SYS_FEC_BUF_USE_SRAM +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_HAS_ETH1 + +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +#define CONFIG_MCFRTC +#undef RTC_DEBUG +#define CONFIG_SYS_RTC_CNT (0x8000) +#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) + +/* Timer */ +#define CONFIG_MCFTMR + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 80000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +#define CONFIG_UDP_CHECKSUM + +#ifdef CONFIG_MCFFEC +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME "M53017" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 3ffff;" \ + "era 0 3ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ + +#define CONFIG_SYS_LOAD_ADDR 0x40010000 + +#define CONFIG_SYS_CLK 80000000 +#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 + +#define CONFIG_SYS_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/* + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ +#define CONFIG_SYS_SDRAM_CFG1 0x43711630 +#define CONFIG_SYS_SDRAM_CFG2 0x56670000 +#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 +#define CONFIG_SYS_SDRAM_EMOD 0x80010000 +#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 + +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#ifdef CONFIG_SYS_FLASH_CFI +# define CONFIG_FLASH_SPANSION_S29WS_N 1 +# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +#endif + +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ + +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + env/embedded.o(.text*) + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash + * CS1 - Ext SRAM + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ +#define CONFIG_SYS_CS0_BASE 0 +#define CONFIG_SYS_CS0_MASK 0x00FF0001 +#define CONFIG_SYS_CS0_CTRL 0x00001FA0 + +#define CONFIG_SYS_CS1_BASE 0xC0000000 +#define CONFIG_SYS_CS1_MASK 0x00070001 +#define CONFIG_SYS_CS1_CTRL 0x00001FA0 + +#endif /* _M53017EVB_H */ diff --git a/roms/u-boot/include/configs/M5329EVB.h b/roms/u-boot/include/configs/M5329EVB.h new file mode 100644 index 000000000..5c88f09f6 --- /dev/null +++ b/roms/u-boot/include/configs/M5329EVB.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the Freescale MCF5329 FireEngine board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5329EVB_H +#define _M5329EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ + +#define CONFIG_SYS_UNIFY_CACHE + +#ifdef CONFIG_MCFFEC +# define CONFIG_MII_INIT 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +#define CONFIG_MCFRTC +#undef RTC_DEBUG + +/* Timer */ +#define CONFIG_MCFTMR + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 80000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +#define CONFIG_UDP_CHECKSUM + +#ifdef CONFIG_MCFFEC +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME "M5329EVB" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 3ffff;" \ + "era 0 3ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ + +#define CONFIG_SYS_LOAD_ADDR 0x40010000 + +#define CONFIG_SYS_CLK 80000000 +#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 + +#define CONFIG_SYS_MBAR 0xFC000000 + +#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CONFIG_SYS_SDRAM_CFG1 0x53722730 +#define CONFIG_SYS_SDRAM_CFG2 0x56670000 +#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 +#define CONFIG_SYS_SDRAM_EMOD 0x40010000 +#define CONFIG_SYS_SDRAM_MODE 0x018D0000 + +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#ifdef CONFIG_SYS_FLASH_CFI +# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +#endif + +#ifdef CONFIG_NANDFLASH_SIZE +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE +# define CONFIG_SYS_NAND_SIZE 1 +# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +# define NAND_ALLOW_ERASE_ALL 1 +# define CONFIG_JFFS2_NAND 1 +# define CONFIG_JFFS2_DEV "nand0" +# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) +# define CONFIG_JFFS2_PART_OFFSET 0x00000000 +#endif + +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ + +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + env/embedded.o(.text*); + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - CompactFlash and registers + * CS2 - NAND Flash 16, 32, or 64MB + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ +#define CONFIG_SYS_CS0_BASE 0 +#define CONFIG_SYS_CS0_MASK 0x007f0001 +#define CONFIG_SYS_CS0_CTRL 0x00001fa0 + +#define CONFIG_SYS_CS1_BASE 0x10000000 +#define CONFIG_SYS_CS1_MASK 0x001f0001 +#define CONFIG_SYS_CS1_CTRL 0x002A3780 + +#ifdef CONFIG_NANDFLASH_SIZE +#define CONFIG_SYS_CS2_BASE 0x20000000 +#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) +#define CONFIG_SYS_CS2_CTRL 0x00001f60 +#endif + +#endif /* _M5329EVB_H */ diff --git a/roms/u-boot/include/configs/M5373EVB.h b/roms/u-boot/include/configs/M5373EVB.h new file mode 100644 index 000000000..f94cc0290 --- /dev/null +++ b/roms/u-boot/include/configs/M5373EVB.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the Freescale MCF5373 FireEngine board. + * + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5373EVB_H +#define _M5373EVB_H + +#include + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ + +#define CONFIG_SYS_UNIFY_CACHE + +#ifdef CONFIG_MCFFEC +# define CONFIG_MII_INIT 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +#define CONFIG_MCFRTC +#undef RTC_DEBUG + +/* Timer */ +#define CONFIG_MCFTMR + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 80000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +#define CONFIG_UDP_CHECKSUM + +#ifdef CONFIG_MCFFEC +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME "M5373EVB" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 3ffff;" \ + "era 0 3ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ + +#define CONFIG_SYS_LOAD_ADDR 0x40010000 + +#define CONFIG_SYS_CLK 80000000 +#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 + +#define CONFIG_SYS_MBAR 0xFC000000 + +#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CONFIG_SYS_SDRAM_CFG1 0x53722730 +#define CONFIG_SYS_SDRAM_CFG2 0x56670000 +#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 +#define CONFIG_SYS_SDRAM_EMOD 0x40010000 +#define CONFIG_SYS_SDRAM_MODE 0x018D0000 + +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#ifdef CONFIG_SYS_FLASH_CFI +# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +#endif + +#ifdef CONFIG_NANDFLASH_SIZE +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE +# define CONFIG_SYS_NAND_SIZE 1 +# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +# define NAND_ALLOW_ERASE_ALL 1 +# define CONFIG_JFFS2_NAND 1 +# define CONFIG_JFFS2_DEV "nand0" +# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) +# define CONFIG_JFFS2_PART_OFFSET 0x00000000 +#endif + +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ + +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + env/embedded.o(.text*); + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - CompactFlash and registers + * CS2 - NAND Flash 16, 32, or 64MB + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ +#define CONFIG_SYS_CS0_BASE 0 +#define CONFIG_SYS_CS0_MASK 0x007f0001 +#define CONFIG_SYS_CS0_CTRL 0x00001fa0 + +#define CONFIG_SYS_CS1_BASE 0x10000000 +#define CONFIG_SYS_CS1_MASK 0x001f0001 +#define CONFIG_SYS_CS1_CTRL 0x002A3780 + +#ifdef CONFIG_NANDFLASH_SIZE +#define CONFIG_SYS_CS2_BASE 0x20000000 +#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) +#define CONFIG_SYS_CS2_CTRL 0x00001f60 +#endif + +#endif /* _M5373EVB_H */ diff --git a/roms/u-boot/include/configs/M54418TWR.h b/roms/u-boot/include/configs/M54418TWR.h new file mode 100644 index 000000000..5447f84ca --- /dev/null +++ b/roms/u-boot/include/configs/M54418TWR.h @@ -0,0 +1,283 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the Freescale MCF54418 TWR board. + * + * Copyright 2010-2012 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M54418TWR_H +#define _M54418TWR_H + +#include + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) +#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*) + +#undef CONFIG_WATCHDOG + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * NAND FLASH + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_JFFS2_NAND +#define CONFIG_NAND_FSL_NFC +#define CONFIG_SYS_NAND_BASE 0xFC0FC000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE +#define CONFIG_SYS_NAND_SELECT_DEVICE +#endif + +/* Network configuration */ +#ifdef CONFIG_MCFFEC +#define CONFIG_MII_INIT 1 +#define CONFIG_SYS_DISCOVER_PHY +#define CONFIG_SYS_RX_ETH_BUFFER 2 +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_SYS_TX_ETH_BUFFER 2 +#define CONFIG_HAS_ETH1 + +#define CONFIG_ETHPRIME "FEC0" +#define CONFIG_IPADDR 192.168.1.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 + +#define CONFIG_SYS_FEC_BUF_USE_SRAM +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +#ifndef CONFIG_SYS_DISCOVER_PHY +#define FECDUPLEX FULL +#define FECSPEED _100BASET +#define LINKSTATUS 1 +#else +#define LINKSTATUS 0 +#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#endif +#endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +#define CONFIG_HOSTNAME "M54418TWR" + +#if defined(CONFIG_CF_SBF) +/* ST Micro serial flash */ +#define CONFIG_SYS_LOAD_ADDR2 0x40010007 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=0x40010000\0" \ + "sbfhdr=sbfhdr.bin\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${sbfhdr};" \ + "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ + "upd=run load; run prog\0" \ + "prog=sf probe 0:1 1000000 3;" \ + "sf erase 0 40000;" \ + "sf write ${loadaddr} 0 40000;" \ + "save\0" \ + "" +#elif defined(CONFIG_SYS_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=0x40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${u-boot};\0" \ + "upd=run load; run prog\0" \ + "prog=nand device 0;" \ + "nand erase 0 40000;" \ + "nb_update ${loadaddr} ${filesize};" \ + "save\0" \ + "" +#else +#define CONFIG_SYS_UBOOT_END 0x3FFFF +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off mram" " ;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" +#endif + +/* Realtime clock */ +#undef CONFIG_MCFRTC +#define CONFIG_RTC_MCFRRTC +#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 + +/* Timer */ +#define CONFIG_MCFTMR + +/* I2c */ +#undef CONFIG_SYS_FSL_I2C +#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ +/* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SPEED 80000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +/* DSPI and Serial Flash */ +#define CONFIG_CF_DSPI +#define CONFIG_SERIAL_FLASH +#define CONFIG_SYS_SBFHDR_SIZE 0x7 + +/* Input, PCI, Flexbus, and VCO */ +#define CONFIG_EXTRA_CLOCK + +#define CONFIG_PRAM 2048 /* 2048 KB */ + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) + +#define CONFIG_SYS_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +/* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) - 32) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ + +#define CONFIG_SYS_DRAM_TEST + +#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) +#define CONFIG_SERIAL_BOOT +#endif + +#if defined(CONFIG_SERIAL_BOOT) +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) +#else +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif + +#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) +/* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +/* Reserve 256 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ + +/* FLASH organization */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE + +#ifdef CONFIG_SYS_FLASH_CFI + +/* Max size that the board might have */ +#define CONFIG_SYS_FLASH_SIZE 0x1000000 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 270 +/* "Real" (hardware) sectors protection */ +#define CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } +#else +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 270 +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 0 +#endif + +/* + * This is setting for JFFS2 support in u-boot. + * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. + */ +#ifdef CONFIG_CMD_JFFS2 +#define CONFIG_JFFS2_DEV "nand0" +#define CONFIG_JFFS2_PART_OFFSET (0x800000) + +#endif + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + +#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 12) + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ +/* + * CS0 - NOR Flash 16MB + * CS1 - Available + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ + + /* Flash */ +#define CONFIG_SYS_CS0_BASE 0x00000000 +#define CONFIG_SYS_CS0_MASK 0x000F0101 +#define CONFIG_SYS_CS0_CTRL 0x00001D60 + +#endif /* _M54418TWR_H */ diff --git a/roms/u-boot/include/configs/M54451EVB.h b/roms/u-boot/include/configs/M54451EVB.h new file mode 100644 index 000000000..f5bafb70e --- /dev/null +++ b/roms/u-boot/include/configs/M54451EVB.h @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the Freescale MCF54451 EVB board. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M54451EVB_H +#define _M54451EVB_H + +#include + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_M54451EVB /* M54451EVB board */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +#define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*) + +#undef CONFIG_WATCHDOG + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* Network configuration */ +#ifdef CONFIG_MCFFEC +# define CONFIG_MII_INIT 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_ETHPRIME "FEC0" +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 + +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +#define CONFIG_HOSTNAME "M54451EVB" +#ifdef CONFIG_SYS_STMICRO_BOOT +/* ST Micro serial flash */ +#define CONFIG_SYS_LOAD_ADDR2 0x40010007 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=0x40010000\0" \ + "sbfhdr=sbfhdr.bin\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${sbfhdr};" \ + "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ + "upd=run load; run prog\0" \ + "prog=sf probe 0:1 1000000 3;" \ + "sf erase 0 30000;" \ + "sf write ${loadaddr} 0 30000;" \ + "save\0" \ + "" +#else +#define CONFIG_SYS_UBOOT_END 0x3FFFF +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ + "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" +#endif + +/* Realtime clock */ +#define CONFIG_MCFRTC +#undef RTC_DEBUG +#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) + +/* Timer */ +#define CONFIG_MCFTMR + +/* I2c */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 80000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +/* DSPI and Serial Flash */ +#define CONFIG_CF_DSPI +#define CONFIG_SERIAL_FLASH +#define CONFIG_SYS_SBFHDR_SIZE 0x7 + +/* Input, PCI, Flexbus, and VCO */ +#define CONFIG_EXTRA_CLOCK + +#define CONFIG_PRAM 2048 /* 2048 KB */ + +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) + +#define CONFIG_SYS_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ +#define CONFIG_SYS_SDRAM_CFG1 0x33633F30 +#define CONFIG_SYS_SDRAM_CFG2 0x57670000 +#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 +#define CONFIG_SYS_SDRAM_EMOD 0x80810000 +#define CONFIG_SYS_SDRAM_MODE 0x008D0000 +#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 + +#ifdef CONFIG_CF_SBF +# define CONFIG_SERIAL_BOOT +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) +#else +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +/* Reserve 256 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/* Configuration for environment + * Environment is not embedded in u-boot. First time runing may have env + * crc error warning if there is no correct environment on the flash. + */ + +/* FLASH organization */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE + +#ifdef CONFIG_SYS_FLASH_CFI + +# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CONFIG_SYS_FLASH_CHECKSUM +# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } + +#endif + +/* + * This is setting for JFFS2 support in u-boot. + * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. + */ +#ifdef CONFIG_CMD_JFFS2 +# define CONFIG_JFFS2_DEV "nor0" +# define CONFIG_JFFS2_PART_SIZE 0x01000000 +# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) +#endif + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ +/* + * CS0 - NOR Flash 16MB + * CS1 - Available + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ + + /* Flash */ +#define CONFIG_SYS_CS0_BASE 0x00000000 +#define CONFIG_SYS_CS0_MASK 0x00FF0001 +#define CONFIG_SYS_CS0_CTRL 0x00004D80 + +#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE + +#endif /* _M54451EVB_H */ diff --git a/roms/u-boot/include/configs/M54455EVB.h b/roms/u-boot/include/configs/M54455EVB.h new file mode 100644 index 000000000..f3621d632 --- /dev/null +++ b/roms/u-boot/include/configs/M54455EVB.h @@ -0,0 +1,356 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the Freescale MCF54455 EVB board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M54455EVB_H +#define _M54455EVB_H + +#include + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_M54455EVB /* M54455EVB board */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +#define LDS_BOARD_TEXT board/freescale/m54455evb/sbf_dram_init.o (.text*) + +#undef CONFIG_WATCHDOG + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* Network configuration */ +#ifdef CONFIG_MCFFEC +# define CONFIG_MII_INIT 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_HAS_ETH1 +# define CONFIG_ETHPRIME "FEC0" +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 + +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +#define CONFIG_HOSTNAME "M54455EVB" +#ifdef CONFIG_SYS_STMICRO_BOOT +/* ST Micro serial flash */ +#define CONFIG_SYS_LOAD_ADDR2 0x40010013 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=0x40010000\0" \ + "sbfhdr=sbfhdr.bin\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${sbfhdr};" \ + "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ + "upd=run load; run prog\0" \ + "prog=sf probe 0:1 1000000 3;" \ + "sf erase 0 30000;" \ + "sf write ${loadaddr} 0 0x30000;" \ + "save\0" \ + "" +#else +/* Atmel and Intel */ +#ifdef CONFIG_SYS_ATMEL_BOOT +# define CONFIG_SYS_UBOOT_END 0x0403FFFF +#elif defined(CONFIG_SYS_INTEL_BOOT) +# define CONFIG_SYS_UBOOT_END 0x3FFFF +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=0x40010000\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${uboot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ + " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ + "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ + __stringify(CONFIG_SYS_UBOOT_END) ";" \ + "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ + " ${filesize}; save\0" \ + "" +#endif + +/* ATA configuration */ +#define CONFIG_IDE_RESET 1 +#define CONFIG_IDE_PREINIT 1 +#define CONFIG_ATAPI +#undef CONFIG_LBA48 + +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 2 + +#define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0 + +#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ +#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ +#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ +#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ + +/* Realtime clock */ +#define CONFIG_MCFRTC +#undef RTC_DEBUG +#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) + +/* Timer */ +#define CONFIG_MCFTMR + +/* I2c */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 80000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +/* DSPI and Serial Flash */ +#define CONFIG_CF_DSPI +#define CONFIG_SYS_SBFHDR_SIZE 0x13 + +/* PCI */ +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 + +#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 + +#define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 +#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS +#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_SYS_PCI_IO_BUS 0xB1000000 +#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS +#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 + +#define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 +#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS +#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 +#endif + +/* FPGA - Spartan 2 */ +/* experiment +#define CONFIG_FPGA_COUNT 1 +#define CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_SYS_FPGA_CHECK_CTRLC +*/ + +/* Input, PCI, Flexbus, and VCO */ +#define CONFIG_EXTRA_CLOCK + +#define CONFIG_PRAM 2048 /* 2048 KB */ + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) + +#define CONFIG_SYS_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_BASE1 0x48000000 +#define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ +#define CONFIG_SYS_SDRAM_CFG1 0x65311610 +#define CONFIG_SYS_SDRAM_CFG2 0x59670000 +#define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 +#define CONFIG_SYS_SDRAM_EMOD 0x40010000 +#define CONFIG_SYS_SDRAM_MODE 0x00010033 +#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA + +#ifdef CONFIG_CF_SBF +# define CONFIG_SERIAL_BOOT +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) +#else +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +/* Reserve 256 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/* + * Configuration for environment + * Environment is not embedded in u-boot. First time runing may have env + * crc error warning if there is no correct environment on the flash. + */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#ifdef CONFIG_SYS_STMICRO_BOOT +# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE +#endif +#ifdef CONFIG_SYS_ATMEL_BOOT +# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE +# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE +#endif +#ifdef CONFIG_SYS_INTEL_BOOT +# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE +# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE +#endif + +#ifdef CONFIG_SYS_FLASH_CFI + +# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT +# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CONFIG_SYS_FLASH_CHECKSUM +# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } +# define CONFIG_FLASH_CFI_LEGACY + +#ifdef CONFIG_FLASH_CFI_LEGACY +# define CONFIG_SYS_ATMEL_REGION 4 +# define CONFIG_SYS_ATMEL_TOTALSECT 11 +# define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} +# define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} +#endif +#endif + +/* + * This is setting for JFFS2 support in u-boot. + * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. + */ +#ifdef CONFIG_CMD_JFFS2 +#ifdef CF_STMICRO_BOOT +# define CONFIG_JFFS2_DEV "nor1" +# define CONFIG_JFFS2_PART_SIZE 0x01000000 +# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) +#endif +#ifdef CONFIG_SYS_ATMEL_BOOT +# define CONFIG_JFFS2_DEV "nor1" +# define CONFIG_JFFS2_PART_SIZE 0x01000000 +# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) +#endif +#ifdef CONFIG_SYS_INTEL_BOOT +# define CONFIG_JFFS2_DEV "nor0" +# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) +# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) +#endif +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - CompactFlash and registers + * CS2 - CPLD + * CS3 - FPGA + * CS4 - Available + * CS5 - Available + */ + +#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) + /* Atmel Flash */ +#define CONFIG_SYS_CS0_BASE 0x04000000 +#define CONFIG_SYS_CS0_MASK 0x00070001 +#define CONFIG_SYS_CS0_CTRL 0x00001140 +/* Intel Flash */ +#define CONFIG_SYS_CS1_BASE 0x00000000 +#define CONFIG_SYS_CS1_MASK 0x01FF0001 +#define CONFIG_SYS_CS1_CTRL 0x00000D60 + +#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE +#else +/* Intel Flash */ +#define CONFIG_SYS_CS0_BASE 0x00000000 +#define CONFIG_SYS_CS0_MASK 0x01FF0001 +#define CONFIG_SYS_CS0_CTRL 0x00000D60 + /* Atmel Flash */ +#define CONFIG_SYS_CS1_BASE 0x04000000 +#define CONFIG_SYS_CS1_MASK 0x00070001 +#define CONFIG_SYS_CS1_CTRL 0x00001140 + +#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE +#endif + +/* CPLD */ +#define CONFIG_SYS_CS2_BASE 0x08000000 +#define CONFIG_SYS_CS2_MASK 0x00070001 +#define CONFIG_SYS_CS2_CTRL 0x003f1140 + +/* FPGA */ +#define CONFIG_SYS_CS3_BASE 0x09000000 +#define CONFIG_SYS_CS3_MASK 0x00070001 +#define CONFIG_SYS_CS3_CTRL 0x00000020 + +#endif /* _M54455EVB_H */ diff --git a/roms/u-boot/include/configs/M5475EVB.h b/roms/u-boot/include/configs/M5475EVB.h new file mode 100644 index 000000000..406830c98 --- /dev/null +++ b/roms/u-boot/include/configs/M5475EVB.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the Freescale MCF5475 board. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5475EVB_H +#define _M5475EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +#undef CONFIG_HW_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ + +#define CONFIG_SLTTMR + +#ifdef CONFIG_FSLDMAFEC +# define CONFIG_MII_INIT 1 +# define CONFIG_HAS_ETH1 +# define CONFIG_SYS_DMA_USE_INTSRAM 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 32 +# define CONFIG_SYS_TX_ETH_BUFFER 48 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ + +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +#endif + +#ifdef CONFIG_CMD_USB +# define CONFIG_USB_OHCI_NEW + +# define CONFIG_PCI_OHCI + +# undef CONFIG_SYS_USB_OHCI_BOARD_INIT +# undef CONFIG_SYS_USB_OHCI_CPU_INIT +# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 +# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" +# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#endif + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 80000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +/* PCI */ +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 + +#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 + +#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS +#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_SYS_PCI_IO_BUS 0x71000000 +#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS +#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 + +#define CONFIG_SYS_PCI_CFG_BUS 0x70000000 +#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS +#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 +#endif + +#define CONFIG_UDP_CHECKSUM + +#ifdef CONFIG_MCFFEC +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME "M547xEVB" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off bank 1;" \ + "era ff800000 ff83ffff;" \ + "cp.b ${loadaddr} ff800000 ${filesize};"\ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ + +#define CONFIG_SYS_LOAD_ADDR 0x00010000 + +#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK +#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 + +#define CONFIG_SYS_MBAR 0xF0000000 +#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) +#define CONFIG_SYS_INTSRAMSZ 0x8000 + +/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_CTRL 0x21 +#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) +#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM1_CTRL 0x21 +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_CFG1 0x73711630 +#define CONFIG_SYS_SDRAM_CFG2 0x46770000 +#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 +#define CONFIG_SYS_SDRAM_EMOD 0x40010000 +#define CONFIG_SYS_SDRAM_MODE 0x018D0000 +#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA +#ifdef CONFIG_SYS_DRAMSZ1 +# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) +#else +# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ +#endif + +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 + +/* Reserve 256 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#ifdef CONFIG_SYS_FLASH_CFI +# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +#ifdef CONFIG_SYS_NOR1SZ +# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ +# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) +# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } +#else +# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) +#endif +#endif + +/* Configuration for environment + * Environment is not embedded in u-boot but at offset 0x40000 on the flash. + * First time runing may have env crc error warning if there is + * no correct environment on the flash. + */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ + CF_CACR_IDCM) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ + CF_CACR_IEC | CF_CACR_ICINVA) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - NOR Flash + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ +#define CONFIG_SYS_CS0_BASE 0xFF800000 +#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) +#define CONFIG_SYS_CS0_CTRL 0x00101980 + +#ifdef CONFIG_SYS_NOR1SZ +#define CONFIG_SYS_CS1_BASE 0xE0000000 +#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) +#define CONFIG_SYS_CS1_CTRL 0x00101D80 +#endif + +#endif /* _M5475EVB_H */ diff --git a/roms/u-boot/include/configs/M5485EVB.h b/roms/u-boot/include/configs/M5485EVB.h new file mode 100644 index 000000000..cd8dd6704 --- /dev/null +++ b/roms/u-boot/include/configs/M5485EVB.h @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the Freescale MCF5485 FireEngine board. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5485EVB_H +#define _M5485EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +#undef CONFIG_HW_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ + +#define CONFIG_SLTTMR + +#ifdef CONFIG_FSLDMAFEC +# define CONFIG_MII_INIT 1 +# define CONFIG_HAS_ETH1 +# define CONFIG_SYS_DMA_USE_INTSRAM 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 32 +# define CONFIG_SYS_TX_ETH_BUFFER 48 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ + +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +#endif + +#ifdef CONFIG_CMD_USB +# define CONFIG_USB_OHCI_NEW +/*# define CONFIG_PCI_OHCI*/ +# define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000 +# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 +# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" +# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#endif + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 80000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +/* PCI */ +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 + +#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS +#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_SYS_PCI_IO_BUS 0x71000000 +#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS +#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 + +#define CONFIG_SYS_PCI_CFG_BUS 0x70000000 +#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS +#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 +#endif + +#define CONFIG_UDP_CHECKSUM + +#define CONFIG_HOSTNAME "M548xEVB" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off bank 1;" \ + "era ff800000 ff83ffff;" \ + "cp.b ${loadaddr} ff800000 ${filesize};"\ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ + +#define CONFIG_SYS_LOAD_ADDR 0x00010000 + +#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK +#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 + +#define CONFIG_SYS_MBAR 0xF0000000 +#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) +#define CONFIG_SYS_INTSRAMSZ 0x8000 + +/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_CTRL 0x21 +#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) +#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM1_CTRL 0x21 +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_CFG1 0x73711630 +#define CONFIG_SYS_SDRAM_CFG2 0x46770000 +#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 +#define CONFIG_SYS_SDRAM_EMOD 0x40010000 +#define CONFIG_SYS_SDRAM_MODE 0x018D0000 +#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA +#ifdef CONFIG_SYS_DRAMSZ1 +# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) +#else +# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ +#endif + +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 + +/* Reserve 256 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#ifdef CONFIG_SYS_FLASH_CFI +# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +#ifdef CONFIG_SYS_NOR1SZ +# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ +# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) +# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } +#else +# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) +#endif +#endif + +/* Configuration for environment + * Environment is not embedded in u-boot. First time runing may have env + * crc error warning if there is no correct environment on the flash. + */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ + CF_CACR_IDCM) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ + CF_CACR_IEC | CF_CACR_ICINVA) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - NOR Flash + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ +#define CONFIG_SYS_CS0_BASE 0xFF800000 +#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) +#define CONFIG_SYS_CS0_CTRL 0x00101980 + +#ifdef CONFIG_SYS_NOR1SZ +#define CONFIG_SYS_CS1_BASE 0xE0000000 +#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) +#define CONFIG_SYS_CS1_CTRL 0x00101D80 +#endif + +#endif /* _M5485EVB_H */ diff --git a/roms/u-boot/include/configs/MCR3000.h b/roms/u-boot/include/configs/MCR3000.h new file mode 100644 index 000000000..48e9ecdb8 --- /dev/null +++ b/roms/u-boot/include/configs/MCR3000.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2010-2017 CS Systemes d'Information + * Christophe Leroy + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "sdram_type=SDRAM\0" \ + "flash_type=AM29LV160DB\0" \ + "loadaddr=0x400000\0" \ + "filename=uImage.lzma\0" \ + "nfsroot=/opt/ofs\0" \ + "dhcp_ip=ip=:::::eth0:dhcp\0" \ + "console_args=console=ttyCPM0,115200N8\0" \ + "flashboot=setenv bootargs " \ + "${console_args} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ + "mcr3k:eth0:off;" \ + "${ofl_args}; " \ + "bootm 0x04060000 - 0x04050000\0" \ + "tftpboot=setenv bootargs " \ + "${console_args} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ + "mcr3k:eth0:off " \ + "${ofl_args}; " \ + "tftp ${loadaddr} ${filename};" \ + "tftp 0xf00000 mcr3000.dtb;" \ + "bootm ${loadaddr} - 0xf00000\0" \ + "netboot=dhcp ${loadaddr} ${filename};" \ + "tftp 0xf00000 mcr3000.dtb;" \ + "setenv bootargs " \ + "root=/dev/nfs rw " \ + "${console_args} " \ + "${dhcp_ip};" \ + "bootm ${loadaddr} - 0xf00000\0" \ + "nfsboot=setenv bootargs " \ + "root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} " \ + "${console_args} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ + "mcr3k:eth0:off;" \ + "bootm 0x04060000 - 0x04050000\0" \ + "dhcpboot=dhcp ${loadaddr} ${filename};" \ + "tftp 0xf00000 mcr3000.dtb;" \ + "setenv bootargs " \ + "${console_args} " \ + "${dhcp_ip} " \ + "${ofl_args}; " \ + "bootm ${loadaddr} - 0xf00000\0" + +#define CONFIG_IPADDR 192.168.0.3 +#define CONFIG_SERVERIP 192.168.0.1 +#define CONFIG_NETMASK 255.0.0.0 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR 0x200000 + +#define CONFIG_SYS_HZ 1000 + +/* Definitions for initial stack pointer and data area (in DPRAM) */ +#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800) +#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800) + +/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +/* FLASH organization */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 35 +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CONFIG_SYS_MONITOR_LEN (320 << 10) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MALLOC_LEN (4096 << 10) + +/* Environment Configuration */ + +/* environment is in FLASH */ + +/* Ethernet configuration part */ +#define CONFIG_SYS_DISCOVER_PHY 1 +#define CONFIG_MII_INIT 1 + +/* NAND configuration part */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0x0C000000 + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/MPC8313ERDB_NAND.h b/roms/u-boot/include/configs/MPC8313ERDB_NAND.h new file mode 100644 index 000000000..2db0c6fd7 --- /dev/null +++ b/roms/u-boot/include/configs/MPC8313ERDB_NAND.h @@ -0,0 +1,392 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. + */ +/* + * mpc8313epb board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 + +#define CONFIG_SPL_INIT_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif + +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 +#define CONFIG_SPL_MAX_SIZE (4 * 1024) +#define CONFIG_SPL_PAD_TO 0x4000 + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#define CONFIG_PCI_INDIRECT_BRIDGE + +/* + * On-board devices + * + * TSEC1 is VSC switch + * TSEC2 is SoC TSEC + */ +#define CONFIG_VSC7385_ENET +#define CONFIG_TSEC2 + +#if !defined(CONFIG_SPL_BUILD) +#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR +#endif + +/* Early revs of this board will lock up hard when attempting + * to access the PMC registers, unless a JTAG debugger is + * connected, or some resistor modifications are made. + */ +#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 + +/* + * Device configurations + */ + +/* Vitesse 7385 */ + +#ifdef CONFIG_VSC7385_ENET + +#define CONFIG_TSEC1 + +/* The flash address and size of the VSC7385 firmware image */ +#define CONFIG_VSC7385_IMAGE 0xFE7FE000 +#define CONFIG_VSC7385_IMAGE_SIZE 8192 + +#endif + +/* + * DDR Setup + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ + +/* + * Manually set up DDR parameters, as this board does not + * seem to have the SPD connected to I2C. + */ +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ODT_RD_NEVER \ + | CSCONFIG_ODT_WR_ONLY_CURRENT \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) + /* 0x80010102 */ + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00220802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (10 << TIMING_CFG1_REFREC_SHIFT) \ + | (3 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x3835a322 */ +#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (5 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x129048c6 */ /* P9-45,may need tuning */ +#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x05100500 */ +#if defined(CONFIG_DDR_2T_TIMING) +#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_32 \ + | SDRAM_CFG_2T_EN) + /* 0x43088000 */ +#else +#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_32) + /* 0x43080000 */ +#endif +#define CONFIG_SYS_SDRAM_CFG2 0x00401000 +/* set burst length to 8 for 32-bit data path */ +#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0632 << SDRAM_MODE_SD_SHIFT)) + /* 0x44480632 */ +#define CONFIG_SYS_DDR_MODE_2 0x8000C000 + +#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + /*0x02000000*/ +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ + | DDRCDR_PZ_NOMZ \ + | DDRCDR_NZ_NOMZ \ + | DDRCDR_M_ODR) + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ + !defined(CONFIG_SPL_BUILD) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ + +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* drivers/mtd/nand/raw/nand.c */ +#if defined(CONFIG_SPL_BUILD) +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#else +#define CONFIG_SYS_NAND_BASE 0xE2800000 +#endif + +#define CONFIG_MTD_PARTITION + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 +#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) + +/* Still needed for spl_minimal.c */ +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM + +/* local bus write LED / read status buffer (BCSR) mapping */ +#define CONFIG_SYS_BCSR_ADDR 0xFA000000 +#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ + /* map at 0xFA000000 on LCS3 */ + +/* Vitesse 7385 */ + +#ifdef CONFIG_VSC7385_ENET + + /* VSC7385 Base address on LCS2 */ +#define CONFIG_SYS_VSC7385_BASE 0xF0000000 +#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ + + +#endif + +#define CONFIG_MPC83XX_GPIO 1 + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +/* + * TSEC + */ + +#define CONFIG_GMII /* MII PHY management */ + +#ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x1c +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC1_PHYIDX 0 +#endif + +#ifdef CONFIG_TSEC2 +#define CONFIG_HAS_ETH1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define TSEC2_PHY_ADDR 4 +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC2_PHYIDX 0 +#endif + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC1" + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * Environment + */ +#define CONFIG_ENV_RANGE (CONFIG_SYS_NAND_BLOCK_SIZE * 4) + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + + /* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) + +/* System IO Config */ +#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ + /* Enable Internal USB Phy and GPIO on LCD Connector */ +#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) + +/* + * Environment Configuration + */ + +#define CONFIG_NETDEV "eth1" + +#define CONFIG_HOSTNAME "mpc8313erdb" +#define CONFIG_ROOTPATH "/nfs/root/path" +#define CONFIG_BOOTFILE "uImage" + /* U-Boot image on TFTP server */ +#define CONFIG_UBOOTPATH "u-boot.bin" +#define CONFIG_FDTFILE "mpc8313erdb.dtb" + + /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" CONFIG_NETDEV "\0" \ + "ethprime=TSEC1\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize\0" \ + "fdtaddr=780000\0" \ + "fdtfile=" CONFIG_FDTFILE "\0" \ + "console=ttyS0\0" \ + "setbootargs=setenv bootargs " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ + "$netdev:off " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setbootargs;" \ + "run setipargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv rootdev /dev/ram;" \ + "run setbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/MPC8313ERDB_NOR.h b/roms/u-boot/include/configs/MPC8313ERDB_NOR.h new file mode 100644 index 000000000..c223ea561 --- /dev/null +++ b/roms/u-boot/include/configs/MPC8313ERDB_NOR.h @@ -0,0 +1,361 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. + */ +/* + * mpc8313epb board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#include +#define CONFIG_PCI_INDIRECT_BRIDGE + +/* + * On-board devices + * + * TSEC1 is VSC switch + * TSEC2 is SoC TSEC + */ +#define CONFIG_VSC7385_ENET +#define CONFIG_TSEC2 + +/* Early revs of this board will lock up hard when attempting + * to access the PMC registers, unless a JTAG debugger is + * connected, or some resistor modifications are made. + */ +#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 + +/* + * Device configurations + */ + +/* Vitesse 7385 */ + +#ifdef CONFIG_VSC7385_ENET + +#define CONFIG_TSEC1 + +/* The flash address and size of the VSC7385 firmware image */ +#define CONFIG_VSC7385_IMAGE 0xFE7FE000 +#define CONFIG_VSC7385_IMAGE_SIZE 8192 + +#endif + +/* + * DDR Setup + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ + +/* + * Manually set up DDR parameters, as this board does not + * seem to have the SPD connected to I2C. + */ +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ODT_RD_NEVER \ + | CSCONFIG_ODT_WR_ONLY_CURRENT \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) + /* 0x80010102 */ + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00220802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (10 << TIMING_CFG1_REFREC_SHIFT) \ + | (3 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x3835a322 */ +#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (5 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x129048c6 */ /* P9-45,may need tuning */ +#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x05100500 */ +#if defined(CONFIG_DDR_2T_TIMING) +#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_32 \ + | SDRAM_CFG_2T_EN) + /* 0x43088000 */ +#else +#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_32) + /* 0x43080000 */ +#endif +#define CONFIG_SYS_SDRAM_CFG2 0x00401000 +/* set burst length to 8 for 32-bit data path */ +#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0632 << SDRAM_MODE_SD_SHIFT)) + /* 0x44480632 */ +#define CONFIG_SYS_DDR_MODE_2 0x8000C000 + +#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + /*0x02000000*/ +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ + | DDRCDR_PZ_NOMZ \ + | DDRCDR_NZ_NOMZ \ + | DDRCDR_M_ODR) + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ + !defined(CONFIG_SPL_BUILD) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ + +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* drivers/mtd/nand/nand.c */ +#define CONFIG_SYS_NAND_BASE 0xE2800000 + +#define CONFIG_MTD_PARTITION + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 +#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) + +/* Still needed for spl_minimal.c */ +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM + +/* local bus write LED / read status buffer (BCSR) mapping */ +#define CONFIG_SYS_BCSR_ADDR 0xFA000000 +#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ + /* map at 0xFA000000 on LCS3 */ +/* Vitesse 7385 */ + +#ifdef CONFIG_VSC7385_ENET + + /* VSC7385 Base address on LCS2 */ +#define CONFIG_SYS_VSC7385_BASE 0xF0000000 +#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ + + +#endif + +#define CONFIG_MPC83XX_GPIO 1 + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +/* + * TSEC + */ + +#define CONFIG_GMII /* MII PHY management */ + +#ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x1c +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC1_PHYIDX 0 +#endif + +#ifdef CONFIG_TSEC2 +#define CONFIG_HAS_ETH1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define TSEC2_PHY_ADDR 4 +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC2_PHYIDX 0 +#endif + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC1" + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * Environment + */ +#if !defined(CONFIG_SYS_RAMBOOT) +/* Address and size of Redundant Environment Sector */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + + /* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) + +/* System IO Config */ +#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ + /* Enable Internal USB Phy and GPIO on LCD Connector */ +#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) + +/* + * Environment Configuration + */ + +#define CONFIG_NETDEV "eth1" + +#define CONFIG_HOSTNAME "mpc8313erdb" +#define CONFIG_ROOTPATH "/nfs/root/path" +#define CONFIG_BOOTFILE "uImage" + /* U-Boot image on TFTP server */ +#define CONFIG_UBOOTPATH "u-boot.bin" +#define CONFIG_FDTFILE "mpc8313erdb.dtb" + + /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" CONFIG_NETDEV "\0" \ + "ethprime=TSEC1\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize\0" \ + "fdtaddr=780000\0" \ + "fdtfile=" CONFIG_FDTFILE "\0" \ + "console=ttyS0\0" \ + "setbootargs=setenv bootargs " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ + "$netdev:off " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setbootargs;" \ + "run setipargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv rootdev /dev/ram;" \ + "run setbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/MPC8315ERDB.h b/roms/u-boot/include/configs/MPC8315ERDB.h new file mode 100644 index 000000000..688aa5ea9 --- /dev/null +++ b/roms/u-boot/include/configs/MPC8315ERDB.h @@ -0,0 +1,370 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. + * + * Dave Liu + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x00000000 +#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */ + +#define CONFIG_HWCONFIG + +/* + * DDR Setup + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ + | DDRCDR_PZ_LOZ \ + | DDRCDR_NZ_LOZ \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN) + /* 0x7b880001 */ +/* + * Manually set up DDR parameters + * consist of two chips HY5PS12621BFP-C4 from HYNIX + */ +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ODT_RD_NEVER \ + | CSCONFIG_ODT_WR_ONLY_CURRENT \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) + /* 0x80010102 */ +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00220802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (6 << TIMING_CFG1_REFREC_SHIFT) \ + | (2 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x27256222 */ +#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (4 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x121048c5 */ +#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x03600100 */ +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_32) + /* 0x43080000 */ +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ +#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0232 << SDRAM_MODE_SD_SHIFT)) + /* ODT 150ohm CL=3, AL=1 on SDRAM */ +#define CONFIG_SYS_DDR_MODE2 0x00000000 + +/* + * Memory test + */ +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +/* 127 64KB sectors and 8 8KB top sectors per device */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* + * NAND Flash on the Local Bus + */ + +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#else +#define CONFIG_SYS_NAND_BASE 0xE0600000 +#endif + +#define CONFIG_MTD_PARTITION + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 +#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 + + + +/* Still needed for spl_minimal.c */ +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM + +#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ + !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } + +/* + * Board info - revision and where boot from + */ +#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 + +/* + * Config on-board RTC + */ +#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE +#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE +#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 +#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ + +#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 +#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 + +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + +#define CONFIG_SYS_PCIE2_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 +#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 + +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_PCIE + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_SYS_SCCR_USBDRCM 3 + +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_PHY_TYPE "utmi" +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +/* + * TSEC + */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) + +/* + * TSEC ethernet configuration + */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: eTSEC[0-1] */ +#define CONFIG_ETHPRIME "eTSEC1" + +/* + * SATA + */ +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1_OFFSET 0x18000 +#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2_OFFSET 0x19000 +#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#ifdef CONFIG_FSL_SATA +#define CONFIG_LBA48 +#endif + +/* + * Environment + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* + * MMU Setup + */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=ramfs.83xx\0" \ + "fdtaddr=780000\0" \ + "fdtfile=mpc8315erdb.dtb\0" \ + "usb_phy_type=utmi\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ + "$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/MPC8323ERDB.h b/roms/u-boot/include/configs/MPC8323ERDB.h new file mode 100644 index 000000000..6effaeaa9 --- /dev/null +++ b/roms/u-boot/include/configs/MPC8323ERDB.h @@ -0,0 +1,309 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL 0x00000000 + +/* + * DDR Setup + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ + +#undef CONFIG_SPD_EEPROM +#if defined(CONFIG_SPD_EEPROM) +/* Determine DDR configuration from I2C interface + */ +#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ +#else +/* Manually set up DDR parameters + */ +#define CONFIG_SYS_DDR_SIZE 64 /* MB */ +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_9) + /* 0x80010101 */ +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00220802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (3 << TIMING_CFG1_REFREC_SHIFT) \ + | (2 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x26253222 */ +#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (31 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x1f9048c7 */ +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + /* 0x02000000 */ +#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0232 << SDRAM_MODE_SD_SHIFT)) + /* 0x44480232 */ +#define CONFIG_SYS_DDR_MODE2 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x03200064 */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003 +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_32_BE) + /* 0x43080000 */ +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#endif + +/* + * Memory test + */ +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ + + + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ + +#undef CONFIG_SYS_FLASH_CHECKSUM + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } + +/* + * Config on-board EEPROM + */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0xd0000000 +#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE +#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_PCI_SKIP_HOST_BRIDGE + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* ETH3 */ + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 4 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +#define CONFIG_UEC_ETH2 /* ETH4 */ + +#ifdef CONFIG_UEC_ETH2 +#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ +#define CONFIG_SYS_UEC2_RX_CLK QE_CLK16 +#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3 +#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC2_PHY_ADDR 0 +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if (CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ +#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ + +/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM + * (see CONFIG_SYS_I2C_EEPROM) */ + /* MAC address offset in I2C EEPROM */ +#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 + +#define CONFIG_NETDEV "eth1" + +#define CONFIG_HOSTNAME "mpc8323erdb" +#define CONFIG_ROOTPATH "/nfsroot" +#define CONFIG_BOOTFILE "uImage" + /* U-Boot image on TFTP server */ +#define CONFIG_UBOOTPATH "u-boot.bin" +#define CONFIG_FDTFILE "mpc832x_rdb.dtb" +#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" + + /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" CONFIG_NETDEV "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ + "tftpflash=tftp $loadaddr $uboot;" \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize\0" \ + "fdtaddr=780000\0" \ + "fdtfile=" CONFIG_FDTFILE "\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ + "console=ttyS0\0" \ + "setbootargs=setenv bootargs " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ + "$netdev:off "\ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setbootargs;" \ + "run setipargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv rootdev /dev/ram;" \ + "run setbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/MPC832XEMDS.h b/roms/u-boot/include/configs/MPC832XEMDS.h new file mode 100644 index 000000000..94d73295d --- /dev/null +++ b/roms/u-boot/include/configs/MPC832XEMDS.h @@ -0,0 +1,302 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL 0x00000000 + +/* + * DDR Setup + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ + +#undef CONFIG_SPD_EEPROM +#if defined(CONFIG_SPD_EEPROM) +/* Determine DDR configuration from I2C interface + */ +#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ +#else +/* Manually set up DDR parameters + */ +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_AP \ + | CSCONFIG_ODT_WR_CFG \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) + /* 0x80840102 */ +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00220802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (13 << TIMING_CFG1_REFREC_SHIFT) \ + | (3 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x3935D322 */ +#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (31 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (10 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x0F9048CA */ +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + /* 0x02000000 */ +#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0232 << SDRAM_MODE_SD_SHIFT)) + /* 0x44400232 */ +#define CONFIG_SYS_DDR_MODE2 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x03200064 */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_32_BE) + /* 0x43080000 */ +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#endif + +/* + * Memory test + */ +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ + + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ + +#undef CONFIG_SYS_FLASH_CHECKSUM + +/* + * BCSR on the Local Bus + */ +#define CONFIG_SYS_BCSR 0xF8000000 + /* Access window base at BCSR base */ + + +/* + * Windows to access PIB via local bus + */ + /* PIB window base 0xF8008000 */ +#define CONFIG_SYS_PIB_BASE 0xF8008000 +#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) + +/* + * CS2 on Local Bus, to PIB + */ + + +/* + * CS3 on Local Bus, to PIB + */ + + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } + +/* + * Config on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ + +#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 +#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE + +#define CONFIG_83XX_PCI_STREAMING + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* ETH3 */ + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 3 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +#define CONFIG_UEC_ETH2 /* ETH4 */ + +#ifdef CONFIG_UEC_ETH2 +#define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC2_RX_CLK QE_CLK7 +#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8 +#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC2_PHY_ADDR 4 +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#endif + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=ramfs.83xx\0" \ + "fdtaddr=780000\0" \ + "fdtfile=mpc832x_mds.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ + "$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/MPC8349EMDS.h b/roms/u-boot/include/configs/MPC8349EMDS.h new file mode 100644 index 000000000..2cf2e2de5 --- /dev/null +++ b/roms/u-boot/include/configs/MPC8349EMDS.h @@ -0,0 +1,374 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +/* + * mpc8349emds board configuration file + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ + +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ + +/* + * DDR Setup + */ +#define CONFIG_DDR_ECC /* support DDR ECC function */ +#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ + +/* + * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver + * unselect it to use old spd_sdram.c + */ +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x52 +#define SPD_EEPROM_ADDRESS2 0x51 +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +/* + * 32-bit data path mode. + * + * Please note that using this mode for devices with the real density of 64-bit + * effectively reduces the amount of available memory due to the effect of + * wrapping around while translating address to row/columns, for example in the + * 256MB module the upper 128MB get aliased with contents of the lower + * 128MB); normally this define should be used for devices with real 32-bit + * data path. + */ +#undef CONFIG_DDR_32BIT + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ + | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#undef CONFIG_DDR_2T_TIMING + +/* + * DDRCDR - DDR Control Driver Register + */ +#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 + +#if defined(CONFIG_SPD_EEPROM) +/* + * Determine DDR configuration from I2C interface. + */ +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +#else +/* + * Manually set up DDR parameters + */ +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#if defined(CONFIG_DDR_II) +#define CONFIG_SYS_DDRCDR 0x80080001 +#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 +#define CONFIG_SYS_DDR_TIMING_0 0x00220802 +#define CONFIG_SYS_DDR_TIMING_1 0x38357322 +#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 +#define CONFIG_SYS_DDR_MODE 0x47d00432 +#define CONFIG_SYS_DDR_MODE2 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 +#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#else +#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) +#define CONFIG_SYS_DDR_TIMING_1 0x36332321 +#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ + +#if defined(CONFIG_DDR_32BIT) +/* set burst length to 8 for 32-bit data path */ + /* DLL,normal,seq,4/2.5, 8 burst len */ +#define CONFIG_SYS_DDR_MODE 0x00000023 +#else +/* the default burst length is 4 - for 64-bit data path */ + /* DLL,normal,seq,4/2.5, 4 burst len */ +#define CONFIG_SYS_DDR_MODE 0x00000022 +#endif +#endif +#endif + +/* + * SDRAM on the Local Bus + */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ + + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +/* + * BCSR register on local bus 32KB, 8-bit wide for MDS config reg + */ +#define CONFIG_SYS_BCSR 0xE2400000 + /* Access window base at BCSR base */ + + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ + +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } + +/* SPI */ +#undef CONFIG_SOFT_SPI /* SPI bit-banged */ + +/* GPIOs. Used as SPI chip selects */ +#define CONFIG_SYS_GPIO1_PRELIM +#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ +#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ + +/* TSEC */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) + +/* USB */ +#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 +#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE +#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 +#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_83XX_PCI_STREAMING + + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + +/* + * TSEC configuration + */ + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_GMII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * Environment + */ +#ifndef CONFIG_SYS_RAMBOOT +/* Address and size of Redundant Environment Sector */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +/* + * System performance + */ +#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ +#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ + +/* System IO Config */ +#define CONFIG_SYS_SICRH 0 +#define CONFIG_SYS_SICRL SICRL_LDP_A + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH0 +#endif + +#define CONFIG_HOSTNAME "mpc8349emds" +#define CONFIG_ROOTPATH "/nfsroot/rootfs" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=mpc8349emds\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ + "update=protect off fe000000 fe03ffff; " \ + "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ + "upd=run load update\0" \ + "fdtaddr=780000\0" \ + "fdtfile=mpc834x_mds.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ + "$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/MPC8349EMDS_SDRAM.h b/roms/u-boot/include/configs/MPC8349EMDS_SDRAM.h new file mode 100644 index 000000000..cfec59e86 --- /dev/null +++ b/roms/u-boot/include/configs/MPC8349EMDS_SDRAM.h @@ -0,0 +1,431 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +/* + * mpc8349emds board configuration file + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ + +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ + +/* + * DDR Setup + */ +#define CONFIG_DDR_ECC /* support DDR ECC function */ +#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ + +/* + * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver + * unselect it to use old spd_sdram.c + */ +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x52 +#define SPD_EEPROM_ADDRESS2 0x51 +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +/* + * 32-bit data path mode. + * + * Please note that using this mode for devices with the real density of 64-bit + * effectively reduces the amount of available memory due to the effect of + * wrapping around while translating address to row/columns, for example in the + * 256MB module the upper 128MB get aliased with contents of the lower + * 128MB); normally this define should be used for devices with real 32-bit + * data path. + */ +#undef CONFIG_DDR_32BIT + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ + | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#undef CONFIG_DDR_2T_TIMING + +/* + * DDRCDR - DDR Control Driver Register + */ +#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 + +#if defined(CONFIG_SPD_EEPROM) +/* + * Determine DDR configuration from I2C interface. + */ +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +#else +/* + * Manually set up DDR parameters + */ +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#if defined(CONFIG_DDR_II) +#define CONFIG_SYS_DDRCDR 0x80080001 +#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 +#define CONFIG_SYS_DDR_TIMING_0 0x00220802 +#define CONFIG_SYS_DDR_TIMING_1 0x38357322 +#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 +#define CONFIG_SYS_DDR_MODE 0x47d00432 +#define CONFIG_SYS_DDR_MODE2 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 +#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#else +#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) +#define CONFIG_SYS_DDR_TIMING_1 0x36332321 +#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ + +#if defined(CONFIG_DDR_32BIT) +/* set burst length to 8 for 32-bit data path */ + /* DLL,normal,seq,4/2.5, 8 burst len */ +#define CONFIG_SYS_DDR_MODE 0x00000023 +#else +/* the default burst length is 4 - for 64-bit data path */ + /* DLL,normal,seq,4/2.5, 4 burst len */ +#define CONFIG_SYS_DDR_MODE 0x00000022 +#endif +#endif +#endif + +/* + * SDRAM on the Local Bus + */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +/* + * BCSR register on local bus 32KB, 8-bit wide for MDS config reg + */ +#define CONFIG_SYS_BCSR 0xE2400000 + /* Access window base at BCSR base */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ + +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ + +/* + * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. + */ + +/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 + */ + +/* + * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 + */ + + + /* LB sdram refresh timer, about 6us */ +#define CONFIG_SYS_LBC_LSRT 0x32000000 + /* LB refresh timer prescal, 266MHz/32 */ +#define CONFIG_SYS_LBC_MRTPR 0x20000000 + +#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ + | LSDMR_BSMA1516 \ + | LSDMR_RFCR8 \ + | LSDMR_PRETOACT6 \ + | LSDMR_ACTTORW3 \ + | LSDMR_BL8 \ + | LSDMR_WRC3 \ + | LSDMR_CL3) + +/* + * SDRAM Controller configuration sequence. + */ +#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) +#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) +#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) +#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) +#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } + +/* SPI */ +#undef CONFIG_SOFT_SPI /* SPI bit-banged */ + +/* GPIOs. Used as SPI chip selects */ +#define CONFIG_SYS_GPIO1_PRELIM +#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ +#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ + +/* TSEC */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) + +/* USB */ +#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 +#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE +#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 +#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_83XX_PCI_STREAMING + + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + +/* + * TSEC configuration + */ + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_GMII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * Environment + */ +#ifndef CONFIG_SYS_RAMBOOT +/* Address and size of Redundant Environment Sector */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +/* + * System performance + */ +#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ +#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ +#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ +#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ + +/* System IO Config */ +#define CONFIG_SYS_SICRH 0 +#define CONFIG_SYS_SICRL SICRL_LDP_A + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH0 +#endif + +#define CONFIG_HOSTNAME "mpc8349emds" +#define CONFIG_ROOTPATH "/nfsroot/rootfs" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=mpc8349emds\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ + "update=protect off fe000000 fe03ffff; " \ + "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ + "upd=run load update\0" \ + "fdtaddr=780000\0" \ + "fdtfile=mpc834x_mds.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ + "$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/MPC837XERDB.h b/roms/u-boot/include/configs/MPC837XERDB.h new file mode 100644 index 000000000..ae368a1f1 --- /dev/null +++ b/roms/u-boot/include/configs/MPC837XERDB.h @@ -0,0 +1,412 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Kevin Lam + * Joe D'Abbraccio + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ + +#define CONFIG_HWCONFIG + +/* + * On-board devices + */ +#define CONFIG_VSC7385_ENET + +/* System performance - define the value i.e. CONFIG_SYS_XXX +*/ + +/* System Clock Configuration Register */ +#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ +#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ +#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x08200000 +#define CONFIG_SYS_SICRL 0x00000000 + +/* + * Output Buffer Impedance + */ +#define CONFIG_SYS_OBIR 0x30100000 + +/* + * Device configurations + */ + +/* Vitesse 7385 */ + +#ifdef CONFIG_VSC7385_ENET + +#define CONFIG_TSEC2 + +/* The flash address and size of the VSC7385 firmware image */ +#define CONFIG_VSC7385_IMAGE 0xFE7FE000 +#define CONFIG_VSC7385_IMAGE_SIZE 8192 + +#endif + +/* + * DDR Setup + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 +#define CONFIG_SYS_83XX_DDR_USES_CS0 + +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) + +#undef CONFIG_DDR_ECC /* support DDR ECC function */ +#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ + +#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ + +/* + * Manually set up DDR parameters + */ +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ODT_WR_ONLY_CURRENT \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00260802 */ /* DDR400 */ +#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (7 << TIMING_CFG1_CASLAT_SHIFT) \ + | (13 << TIMING_CFG1_REFREC_SHIFT) \ + | (3 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x3937d322 */ +#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (5 << TIMING_CFG2_CPO_SHIFT) \ + | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x02984cc8 */ + +#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x06090100 */ + +#if defined(CONFIG_DDR_2T_TIMING) +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_32_BE \ + | SDRAM_CFG_2T_EN) + /* 0x43088000 */ +#else +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2) + /* 0x43000000 */ +#endif +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ +#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0442 << SDRAM_MODE_SD_SHIFT)) + /* 0x04400442 */ /* DDR400 */ +#define CONFIG_SYS_DDR_MODE2 0x00000000 + +/* + * Memory test + */ +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ + + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* + * NAND Flash on the Local Bus + */ +#define CONFIG_SYS_NAND_BASE 0xE0600000 + + +/* Vitesse 7385 */ + +#define CONFIG_SYS_VSC7385_BASE 0xF0000000 + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* SERDES */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 +#define CONFIG_FSL_SERDES2 0xe3100 + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } + +/* + * Config on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE +#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE +#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 +#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ + +#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 +#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 + +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + +#define CONFIG_SYS_PCIE2_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 +#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#endif /* CONFIG_PCI */ + +/* + * TSEC + */ +#ifdef CONFIG_TSEC_ENET + +#define CONFIG_GMII /* MII PHY management */ + +#define CONFIG_TSEC1 + +#ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 2 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC1_PHYIDX 0 +#endif + +#ifdef CONFIG_TSEC2 +#define CONFIG_HAS_ETH1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define TSEC2_PHY_ADDR 0x1c +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_PHYIDX 0 +#endif + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif + +/* + * SATA + */ +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1_OFFSET 0x18000 +#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2_OFFSET 0x19000 +#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#ifdef CONFIG_FSL_SATA +#define CONFIG_LBA48 +#endif + +/* + * Environment + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC_PIN_MUX +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +#define CONFIG_NETDEV "eth1" + +#define CONFIG_HOSTNAME "mpc837x_rdb" +#define CONFIG_ROOTPATH "/nfsroot" +#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" +#define CONFIG_BOOTFILE "uImage" + /* U-Boot image on TFTP server */ +#define CONFIG_UBOOTPATH "u-boot.bin" +#define CONFIG_FDTFILE "mpc8379_rdb.dtb" + + /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" CONFIG_NETDEV "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ + "tftpflash=tftp $loadaddr $uboot;" \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize\0" \ + "fdtaddr=780000\0" \ + "fdtfile=" CONFIG_FDTFILE "\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ + "console=ttyS0\0" \ + "setbootargs=setenv bootargs " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ + "$netdev:off " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setbootargs;" \ + "run setipargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv rootdev /dev/ram;" \ + "run setbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/MPC8540ADS.h b/roms/u-boot/include/configs/MPC8540ADS.h new file mode 100644 index 000000000..af90fe167 --- /dev/null +++ b/roms/u-boot/include/configs/MPC8540ADS.h @@ -0,0 +1,355 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2004, 2011 Freescale Semiconductor. + * (C) Copyright 2002,2003 Motorola,Inc. + * Xianghua Xiao + */ + +/* + * mpc8540ads board configuration file + * + * Please refer to doc/README.mpc85xx for more info. + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_SERVERIP, etc in this file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * default CCARBAR is at 0xff700000 + * assume U-Boot is less than 0.5MB + */ + +#ifndef CONFIG_HAS_FEC +#define CONFIG_HAS_FEC 1 /* 8540 has FEC */ +#endif + +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ + +/* + * sysclk for MPC85xx + * + * Two valid values are: + * 33000000 + * 66000000 + * + * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz + * is likely the desired value here, so that is now the default. + * The board, however, can run at 66MHz. In any event, this value + * must match the settings of some switches. Details can be found + * in the README.mpc85xxads. + * + * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to + * 33MHz to accommodate, based on a PCI pin. + * Note that PCI-X won't work at 33MHz. + */ + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 33000000 +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* DDR Setup */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_SPD + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +/* I2C addresses of SPD EEPROMs */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ + +/* These are used when DDR doesn't use SPD. */ +#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 +#define CONFIG_SYS_DDR_TIMING_1 0x37344321 +#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ +#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ + +/* + * SDRAM on the Local Bus + */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ +#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ + +#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_FLASH_EMPTY_INFO + +/* + * Local Bus Definitions + */ + +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CONFIG_SYS_BR2_PRELIM 0xf0001861 + +/* + * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CONFIG_SYS_OR2_PRELIM 0xfc006901 + +#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ + +#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ + | LSDMR_RFCR5 \ + | LSDMR_PRETOACT3 \ + | LSDMR_ACTTORW3 \ + | LSDMR_BL8 \ + | LSDMR_WRC2 \ + | LSDMR_CL3 \ + | LSDMR_RFEN \ + ) + +/* + * SDRAM Controller configuration sequence. + */ +#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) +#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) +#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) +#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) +#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) + +/* + * 32KB, 8-bit wide for ADS config reg + */ +#define CONFIG_SYS_BR4_PRELIM 0xf8000801 +#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 +#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } + +/* RapidIO MMU */ +#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ +#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ +#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ + +#if defined(CONFIG_PCI) + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +#if CONFIG_HAS_FEC +#define CONFIG_MPC85XX_FEC 1 +#define CONFIG_MPC85XX_FEC_NAME "FEC" +#define FEC_PHY_ADDR 3 +#define FEC_PHYIDX 0 +#define FEC_FLAGS 0 +#endif + +/* Options are: TSEC[0-1], FEC */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#endif + +#define CONFIG_IPADDR 192.168.1.253 + +#define CONFIG_HOSTNAME "unknown" +#define CONFIG_ROOTPATH "/nfsroot" +#define CONFIG_BOOTFILE "your.uImage" + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/MPC8541CDS.h b/roms/u-boot/include/configs/MPC8541CDS.h new file mode 100644 index 000000000..ea4da6a5f --- /dev/null +++ b/roms/u-boot/include/configs/MPC8541CDS.h @@ -0,0 +1,384 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2004, 2011 Freescale Semiconductor. + */ + +/* + * mpc8541cds board configuration file + * + * Please refer to doc/README.mpc85xxcds for more info. + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_CPM2 1 /* has CPM2 */ + +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ + +#ifndef __ASSEMBLY__ +extern unsigned long get_clock_freq(void); +#endif +#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* DDR Setup */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_SPD + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +/* I2C addresses of SPD EEPROMs */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ + +/* + * Make sure required options are set + */ +#ifndef CONFIG_SPD_EEPROM +#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") +#endif + +/* + * Local Bus Definitions + */ + +/* + * FLASH on the Local Bus + * Two banks, 8M each, using the CFI driver. + * Boot from BR0/OR0 bank at 0xff00_0000 + * Alternate BR1/OR1 bank at 0xff80_0000 + * + * BR0, BR1: + * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 + * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 + * Port Size = 16 bits = BRx[19:20] = 10 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 + * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 + * + * OR0, OR1: + * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 + * Reserved ORx[17:18] = 11, confusion here? + * CSNT = ORx[20] = 1 + * ACS = half cycle delay = ORx[21:22] = 11 + * SCY = 6 = ORx[24:27] = 0110 + * TRLX = use relaxed timing = ORx[29] = 1 + * EAD = use external address latch delay = OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx + */ + +#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ + +#define CONFIG_SYS_BR0_PRELIM 0xff801001 +#define CONFIG_SYS_BR1_PRELIM 0xff001001 + +#define CONFIG_SYS_OR0_PRELIM 0xff806e65 +#define CONFIG_SYS_OR1_PRELIM 0xff806e65 + +#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO + +/* + * SDRAM on the Local Bus + */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CONFIG_SYS_BR2_PRELIM 0xf0001861 + +/* + * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CONFIG_SYS_OR2_PRELIM 0xfc006901 + +#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ + +/* + * Common settings for all Local Bus SDRAM commands. + * At run time, either BSMA1516 (for CPU 1.1) + * or BSMA1617 (for CPU 1.0) (old) + * is OR'ed in too. + */ +#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ + | LSDMR_PRETOACT7 \ + | LSDMR_ACTTORW7 \ + | LSDMR_BL8 \ + | LSDMR_WRC4 \ + | LSDMR_CL3 \ + | LSDMR_RFEN \ + ) + +/* + * The CADMUS registers are connected to CS3 on CDS. + * The new memory map places CADMUS at 0xf8000000. + * + * For BR3, need: + * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 + * port-size = 8-bits = BR[19:20] = 01 + * no parity checking = BR[21:22] = 00 + * GPMC for MSEL = BR[24:26] = 000 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 + * + * For OR3, need: + * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 + * disable buffer ctrl OR[19] = 0 + * CSNT OR[20] = 1 + * ACS OR[21:22] = 11 + * XACS OR[23] = 1 + * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe + * SETA OR[28] = 0 + * TRLX OR[29] = 1 + * EHTR OR[30] = 1 + * EAD extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 + */ + +#define CONFIG_FSL_CADMUS + +#define CADMUS_BASE_ADDR 0xf8000000 +#define CONFIG_SYS_BR3_PRELIM 0xf8000801 +#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_CCID +#define CONFIG_SYS_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ + +#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 +#define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ + +#ifdef CONFIG_LEGACY +#define BRIDGE_ID 17 +#define VIA_ID 2 +#else +#define BRIDGE_ID 28 +#define VIA_ID 4 +#endif + +#if defined(CONFIG_PCI) + +#define CONFIG_MPC85XX_PCI2 + + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#endif + +#define CONFIG_IPADDR 192.168.1.253 + +#define CONFIG_HOSTNAME "unknown" +#define CONFIG_ROOTPATH "/nfsroot" +#define CONFIG_BOOTFILE "your.uImage" + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS1\0" \ + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/MPC8548CDS.h b/roms/u-boot/include/configs/MPC8548CDS.h new file mode 100644 index 000000000..9f83931be --- /dev/null +++ b/roms/u-boot/include/configs/MPC8548CDS.h @@ -0,0 +1,517 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. + * Copyright 2020 NXP + */ + +/* + * mpc8548cds board configuration file + * + * Please refer to doc/README.mpc85xxcds for more info. + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + +#define CONFIG_PCI1 /* PCI controller 1 */ +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ +#undef CONFIG_PCI2 +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ + +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ + +#ifndef __ASSEMBLY__ +#include +extern unsigned long get_clock_freq(void); +#endif +#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* DDR Setup */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_SPD + +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +/* I2C addresses of SPD EEPROMs */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ + +/* Make sure required options are set */ +#ifndef CONFIG_SPD_EEPROM +#error ("CONFIG_SPD_EEPROM is required") +#endif + +/* + * Physical Address Map + * + * 32bit: + * 0x0000_0000 0x7fff_ffff DDR 2G cacheable + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable + * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable + * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable + * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable + * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable + * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable + * + * 36bit: + * 0x00000_0000 0x07fff_ffff DDR 2G cacheable + * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable + * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable + * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable + * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable + * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable + * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable + * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable + * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable + * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable + * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable + * + */ + +/* + * Local Bus Definitions + */ + +/* + * FLASH on the Local Bus + * Two banks, 8M each, using the CFI driver. + * Boot from BR0/OR0 bank at 0xff00_0000 + * Alternate BR1/OR1 bank at 0xff80_0000 + * + * BR0, BR1: + * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 + * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 + * Port Size = 16 bits = BRx[19:20] = 10 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 + * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 + * + * OR0, OR1: + * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 + * Reserved ORx[17:18] = 11, confusion here? + * CSNT = ORx[20] = 1 + * ACS = half cycle delay = ORx[21:22] = 11 + * SCY = 6 = ORx[24:27] = 0110 + * TRLX = use relaxed timing = ORx[29] = 1 + * EAD = use external address latch delay = OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx + */ + +#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_BR0_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) +#define CONFIG_SYS_BR1_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) + +#define CONFIG_SYS_OR0_PRELIM 0xff806e65 +#define CONFIG_SYS_OR1_PRELIM 0xff806e65 + +#define CONFIG_SYS_FLASH_BANKS_LIST \ + {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO + +#define CONFIG_HWCONFIG /* enable hwconfig */ + +/* + * SDRAM on the Local Bus + */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull +#else +#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE +#endif +#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CONFIG_SYS_BR2_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ + | BR_PS_32 | (3< + */ + +/* + * mpc8560ads board configuration file + * + * Please refer to doc/README.mpc85xx for more info. + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_SERVERIP, etc. in this file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* High Level Configuration Options */ +#define CONFIG_CPM2 1 /* has CPM2 */ + +/* + * default CCARBAR is at 0xff700000 + * assume U-Boot is less than 0.5MB + */ + +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ + +/* + * sysclk for MPC85xx + * + * Two valid values are: + * 33000000 + * 66000000 + * + * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz + * is likely the desired value here, so that is now the default. + * The board, however, can run at 66MHz. In any event, this value + * must match the settings of some switches. Details can be found + * in the README.mpc85xxads. + */ + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 33000000 +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ + +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* DDR Setup */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_SPD + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +/* I2C addresses of SPD EEPROMs */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ + +/* These are used when DDR doesn't use SPD. */ +#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 +#define CONFIG_SYS_DDR_TIMING_1 0x37344321 +#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ +#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ + +/* + * SDRAM on the Local Bus + */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ +#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ + +#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_FLASH_EMPTY_INFO + +/* + * Local Bus Definitions + */ + +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CONFIG_SYS_BR2_PRELIM 0xf0001861 + +/* + * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CONFIG_SYS_OR2_PRELIM 0xfc006901 + +#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ + +#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ + | LSDMR_RFCR5 \ + | LSDMR_PRETOACT3 \ + | LSDMR_ACTTORW3 \ + | LSDMR_BL8 \ + | LSDMR_WRC2 \ + | LSDMR_CL3 \ + | LSDMR_RFEN \ + ) + +/* + * SDRAM Controller configuration sequence. + */ +#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) +#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) +#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) +#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) +#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) + +/* + * 32KB, 8-bit wide for ADS config reg + */ +#define CONFIG_SYS_BR4_PRELIM 0xf8000801 +#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 +#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } + +/* RapidIO MMU */ +#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ +#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ +#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ + +#if defined(CONFIG_PCI) + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + +#ifdef CONFIG_TSEC_ENET + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ + +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ + +#if (CONFIG_ETHER_INDEX == 2) + /* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - Select bus for bd/buffers + * - Full duplex + */ + #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) + #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) + #define CONFIG_SYS_CPMFCR_RAMTYPE 0 + #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) + #define FETH2_RST 0x01 +#elif (CONFIG_ETHER_INDEX == 3) + /* need more definitions here for FE3 */ + #define FETH3_RST 0x80 +#endif /* CONFIG_ETHER_INDEX */ + +/* + * GPIO pins used for bit-banged MII communications + */ +#define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + +#define MDIO_ACTIVE (iop->pdir |= 0x00400000) +#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) +#define MDIO_READ ((iop->pdat & 0x00400000) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ + else iop->pdat &= ~0x00400000 + +#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ + else iop->pdat &= ~0x00200000 + +#define MIIDELAY udelay(1) + +#endif + +/* + * Environment + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ + +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#endif + +#define CONFIG_IPADDR 192.168.1.253 + +#define CONFIG_HOSTNAME "unknown" +#define CONFIG_ROOTPATH "/nfsroot" +#define CONFIG_BOOTFILE "your.uImage" + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyCPM\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc8560ads.dtb\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/MPC8568MDS.h b/roms/u-boot/include/configs/MPC8568MDS.h new file mode 100644 index 000000000..2c43981a1 --- /dev/null +++ b/roms/u-boot/include/configs/MPC8568MDS.h @@ -0,0 +1,400 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. + */ + +/* + * mpc8568mds board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + +#define CONFIG_PCI1 1 /* PCI controller */ +#define CONFIG_PCIE1 1 /* PCIE controller */ +#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ + +#ifndef __ASSEMBLY__ +extern unsigned long get_clock_freq(void); +#endif /*Replace a call to get_clock_freq (after it is implemented)*/ +#define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* DDR Setup */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_SPD +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +/* I2C addresses of SPD EEPROMs */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ + +/* Make sure required options are set */ +#ifndef CONFIG_SPD_EEPROM +#error ("CONFIG_SPD_EEPROM is required") +#endif + +/* + * Local Bus Definitions + */ + +/* + * FLASH on the Local Bus + * Two banks, 8M each, using the CFI driver. + * Boot from BR0/OR0 bank at 0xff00_0000 + * Alternate BR1/OR1 bank at 0xff80_0000 + * + * BR0, BR1: + * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 + * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 + * Port Size = 16 bits = BRx[19:20] = 10 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 + * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 + * + * OR0, OR1: + * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 + * Reserved ORx[17:18] = 11, confusion here? + * CSNT = ORx[20] = 1 + * ACS = half cycle delay = ORx[21:22] = 11 + * SCY = 6 = ORx[24:27] = 0110 + * TRLX = use relaxed timing = ORx[29] = 1 + * EAD = use external address latch delay = OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx + */ +#define CONFIG_SYS_BCSR_BASE 0xf8000000 + +#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ + +/*Chip select 0 - Flash*/ +#define CONFIG_SYS_BR0_PRELIM 0xfe001001 +#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 + +/*Chip slelect 1 - BCSR*/ +#define CONFIG_SYS_BR1_PRELIM 0xf8000801 +#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 + +/*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO + +/* + * SDRAM on the LocalBus + */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/*Chip select 2 - SDRAM*/ +#define CONFIG_SYS_BR2_PRELIM 0xf0001861 +#define CONFIG_SYS_OR2_PRELIM 0xfc006901 + +#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ + +/* + * Common settings for all Local Bus SDRAM commands. + * At run time, either BSMA1516 (for CPU 1.1) + * or BSMA1617 (for CPU 1.0) (old) + * is OR'ed in too. + */ +#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ + | LSDMR_PRETOACT7 \ + | LSDMR_ACTTORW7 \ + | LSDMR_BL8 \ + | LSDMR_WRC4 \ + | LSDMR_CL3 \ + | LSDMR_RFEN \ + ) + +/* + * The bcsr registers are connected to CS3 on MDS. + * The new memory map places bcsr at 0xf8000000. + * + * For BR3, need: + * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 + * port-size = 8-bits = BR[19:20] = 01 + * no parity checking = BR[21:22] = 00 + * GPMC for MSEL = BR[24:26] = 000 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 + * + * For OR3, need: + * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 + * disable buffer ctrl OR[19] = 0 + * CSNT OR[20] = 1 + * ACS OR[21:22] = 11 + * XACS OR[23] = 1 + * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe + * SETA OR[28] = 0 + * TRLX OR[29] = 1 + * EHTR OR[30] = 1 + * EAD extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 + */ +#define CONFIG_SYS_BCSR (0xf8000000) + +/*Chip slelect 4 - PIB*/ +#define CONFIG_SYS_BR4_PRELIM 0xf8008801 +#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 + +/*Chip select 5 - PIB*/ +#define CONFIG_SYS_BR5_PRELIM 0xf8010801 +#define CONFIG_SYS_OR5_PRELIM 0xffff69f7 + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 + +/* + * General PCI + * Memory Addresses are mapped 1-1. I/O is mapped from 0 + */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ + +#define CONFIG_SYS_PCIE1_NAME "Slot" +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ + +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ + +#ifdef CONFIG_QE +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#ifndef CONFIG_TSEC_ENET +#define CONFIG_ETHPRIME "UEC0" +#endif +#define CONFIG_PHY_MODE_NEED_CHANGE +#define CONFIG_eTSEC_MDIO_BUS + +#ifdef CONFIG_eTSEC_MDIO_BUS +#define CONFIG_MIIM_ADDRESS 0xE0024520 +#endif + +#define CONFIG_UEC_ETH1 /* GETH1 */ + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 +#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 7 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 +#endif + +#define CONFIG_UEC_ETH2 /* GETH2 */ + +#ifdef CONFIG_UEC_ETH2 +#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ +#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 +#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH +#define CONFIG_SYS_UEC2_PHY_ADDR 1 +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 +#endif +#endif /* CONFIG_QE */ + +#if defined(CONFIG_PCI) + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" + +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 3 + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: eTSEC[0-1] */ +#define CONFIG_ETHPRIME "eTSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#endif + +#define CONFIG_IPADDR 192.168.1.253 + +#define CONFIG_HOSTNAME "unknown" +#define CONFIG_ROOTPATH "/nfsroot" +#define CONFIG_BOOTFILE "your.uImage" + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs\0" \ + "ramargs=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs\0" \ + +#define CONFIG_NFSBOOTCOMMAND \ + "run nfsargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "run ramargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/P1010RDB.h b/roms/u-boot/include/configs/P1010RDB.h new file mode 100644 index 000000000..1b68fd107 --- /dev/null +++ b/roms/u-boot/include/configs/P1010RDB.h @@ -0,0 +1,758 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + */ + +/* + * P010 RDB board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include +#define CONFIG_NAND_FSL_IFC + +#ifdef CONFIG_SDCARD +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_PAD_TO 0x18000 +#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif +#endif + +#ifdef CONFIG_SPIFLASH +#ifdef CONFIG_NXP_ESBC +#define CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc +#else +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_PAD_TO 0x18000 +#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif +#endif +#endif + +#ifdef CONFIG_MTD_RAW_NAND +#ifdef CONFIG_NXP_ESBC +#define CONFIG_SPL_INIT_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" + +#define CONFIG_SPL_MAX_SIZE 8192 +#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 +#define CONFIG_SPL_RELOC_STACK 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 +#else +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_NAND_INIT +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SPL_MAX_SIZE (128 << 10) +#define CONFIG_TPL_TEXT_BASE 0xD0001000 +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) +#elif defined(CONFIG_SPL_BUILD) +#define CONFIG_SPL_INIT_MINIMAL +#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_MAX_SIZE 8192 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 +#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) +#endif +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_TPL_PAD_TO 0x20000 +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#endif +#endif + +#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ +#define CONFIG_RAMBOOT_NAND +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE +#elif defined(CONFIG_SPL_BUILD) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* High Level Configuration Options */ +#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ + +#if defined(CONFIG_PCI) +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +/* + * PCI Windows + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#endif + +/* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif + +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ +#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +#if defined(CONFIG_TARGET_P1010RDB_PA) +#define CONFIG_SYS_PCIE2_NAME "PCIe Slot" +#elif defined(CONFIG_TARGET_P1010RDB_PB) +#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" +#endif +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#endif + +#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ + +#define CONFIG_HWCONFIG +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + + +#define CONFIG_ENABLE_36BIT_PHYS + +/* DDR Setup */ +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_DDR_SPD +#define CONFIG_SYS_SPD_BUS_NUM 1 +#define SPD_EEPROM_ADDRESS 0x52 + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#ifndef __ASSEMBLY__ +extern unsigned long get_sdram_size(void); +#endif +#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 + +/* DDR3 Controller Settings */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ +#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 +#define CONFIG_SYS_DDR_TIMING_4 0x00000001 +#define CONFIG_SYS_DDR_TIMING_5 0x03402400 + +#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 +#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 +#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 +#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 +#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 +#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 + +/* settings for DDR3 at 667MT/s */ +#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 +#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 +#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 +#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD +#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 +#define CONFIG_SYS_DDR_MODE_1_667 0x00441210 +#define CONFIG_SYS_DDR_MODE_2_667 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 +#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 + +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* Don't relocate CCSRBAR while in NAND_SPL */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif + +/* + * Memory map + * + * 0x0000_0000 0x3fff_ffff DDR 1G cacheable + * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable + * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable + * + * Localbus non-cacheable + * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable + * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* + * IFC Definitions + */ +/* NOR Flash on IFC */ + +#define CONFIG_SYS_FLASH_BASE 0xee000000 +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5) +#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ + FTIM1_NOR_TRAD_NOR(0x0f) +#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWP(0x1c) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* CFI for NOR Flash */ +#define CONFIG_SYS_FLASH_EMPTY_INFO + +/* NAND Flash on IFC */ +#define CONFIG_SYS_NAND_BASE 0xff800000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_MTD_PARTITION + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#if defined(CONFIG_TARGET_P1010RDB_PA) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ + | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ + | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ + | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ +#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) + +#elif defined(CONFIG_TARGET_P1010RDB_PB) +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) +#endif + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#if defined(CONFIG_TARGET_P1010RDB_PA) +/* NAND Flash Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ + FTIM0_NAND_TWP(0x0C) | \ + FTIM0_NAND_TWCHT(0x04) | \ + FTIM0_NAND_TWH(0x05) +#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ + FTIM1_NAND_TWBE(0x1d) | \ + FTIM1_NAND_TRR(0x07) | \ + FTIM1_NAND_TRP(0x0c) +#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ + FTIM2_NAND_TREH(0x05) | \ + FTIM2_NAND_TWHRE(0x0f) +#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) + +#elif defined(CONFIG_TARGET_P1010RDB_PB) +/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 +#endif + +#define CONFIG_SYS_NAND_DDR_LAW 11 + +/* Set up IFC registers for boot location NOR/NAND */ +#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +/* CPLD on IFC */ +#define CONFIG_SYS_CPLD_BASE 0xffb00000 + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull +#else +#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#endif + +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR3 0x0 +/* CPLD Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ + defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) +#define CONFIG_A003399_NOR_WORKAROUND +#endif +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ + - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ + +/* + * Config the L2 Cache as L2 SRAM + */ +#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) +#elif defined(CONFIG_MTD_RAW_NAND) +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) +#else +#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) +#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) +#endif +#endif +#endif + +/* Serial Port */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* I2C */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define I2C_PCA9557_ADDR1 0x18 +#define I2C_PCA9557_ADDR2 0x19 +#define I2C_PCA9557_BUS_NUM 0 +#define CONFIG_SYS_I2C_FSL + +/* I2C EEPROM */ +#if defined(CONFIG_TARGET_P1010RDB_PB) +#define CONFIG_ID_EEPROM +#ifdef CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#endif +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ +#endif +/* enable read and write access to EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* RTC */ +#define CONFIG_RTC_PT7C4338 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * SPI interface will not be available in case of NAND boot SPI CS0 will be + * used for SLIC + */ +#if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT) +/* eSPI - Enhanced SPI */ +#endif + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define TSEC1_PHY_ADDR 1 +#define TSEC2_PHY_ADDR 0 +#define TSEC3_PHY_ADDR 2 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +/* TBI PHY configuration for SGMII mode */ +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + +#endif /* CONFIG_TSEC_ENET */ + +/* SATA */ +#define CONFIG_FSL_SATA_V2 + +#ifdef CONFIG_FSL_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#endif /* #ifdef CONFIG_FSL_SATA */ + +#ifdef CONFIG_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#endif + +#define CONFIG_HAS_FSL_DR_USB + +#if defined(CONFIG_HAS_FSL_DR_USB) +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#endif +#endif + +/* + * Environment + */ +#if defined(CONFIG_SDCARD) +#define CONFIG_FSL_FIXED_MMC_LOCATION +#elif defined(CONFIG_MTD_RAW_NAND) +#ifdef CONFIG_TPL_BUILD +#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#else +#if defined(CONFIG_TARGET_P1010RDB_PA) +#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ +#elif defined(CONFIG_TARGET_P1010RDB_PB) +#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ +#endif +#endif +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ + || defined(CONFIG_FSL_SATA) +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#endif + +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "loadaddr=1000000\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=rootfs.ext2.gz.uboot\0" \ + "fdtaddr=1e00000\0" \ + "fdtfile=p1010rdb.dtb\0" \ + "bdev=sda1\0" \ + "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ + "othbootargs=ramdisk_size=600000\0" \ + "usbfatboot=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "usb start;" \ + "fatload usb 0:2 $loadaddr $bootfile;" \ + "fatload usb 0:2 $fdtaddr $fdtfile;" \ + "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + "usbext2boot=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "usb start;" \ + "ext2load usb 0:4 $loadaddr $bootfile;" \ + "ext2load usb 0:4 $fdtaddr $fdtfile;" \ + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + CONFIG_BOOTMODE + +#if defined(CONFIG_TARGET_P1010RDB_PA) +#define CONFIG_BOOTMODE \ + "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ + "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ + "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ + "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ + "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ + "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" + +#elif defined(CONFIG_TARGET_P1010RDB_PB) +#define CONFIG_BOOTMODE \ + "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ + "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ + "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ + "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ + "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ + "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ + "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ + "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ + "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ + "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" +#endif + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/P2041RDB.h b/roms/u-boot/include/configs/P2041RDB.h new file mode 100644 index 000000000..715154a0d --- /dev/null +++ b/roms/u-boot/include/configs/P2041RDB.h @@ -0,0 +1,573 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + */ + +/* + * P2041 RDB board configuration file + * Also supports P2040 RDB + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg +#endif + +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +/* High Level Configuration Options */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ +#define CONFIG_SRIO_PCIE_BOOT_MASTER +#define CONFIG_SYS_DPAA_RMAN /* RMan */ + +#if defined(CONFIG_SPIFLASH) +#elif defined(CONFIG_SDCARD) + #define CONFIG_FSL_FIXED_MMC_LOCATION +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(unsigned long dummy); +#include +#endif +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ + CONFIG_RAMBOOT_TEXT_BASE) +#else +#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#endif +#define CONFIG_SYS_L3_SIZE (1024 << 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x52 +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * Local Bus Definitions + */ + +/* Set the local bus clock 1/8 of platform clock */ +#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 + +/* + * This board doesn't have a promjet connector. + * However, it uses commone corenet board LAW and TLB. + * It is necessary to use the same start address with proper offset. + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_FLASH_BR_PRELIM \ + (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ + BR_PS_16 | BR_V) +#define CONFIG_SYS_FLASH_OR_PRELIM \ + ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ + | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) + +#define CONFIG_FSL_CPLD +#define CPLD_BASE 0xffdf0000 /* CPLD registers */ +#ifdef CONFIG_PHYS_64BIT +#define CPLD_BASE_PHYS 0xfffdf0000ull +#else +#define CPLD_BASE_PHYS CPLD_BASE +#endif + +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ + +#define PIXIS_LBMAP_SWITCH 7 +#define PIXIS_LBMAP_MASK 0xf0 +#define PIXIS_LBMAP_SHIFT 4 +#define PIXIS_LBMAP_ALTBANK 0x40 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_NAND_FSL_ELBC +/* Nand Flash */ +#ifdef CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* NAND flash config */ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | (2<> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull +#else +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#endif +#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + */ +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) +#elif defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 +#else +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) + +#ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#endif /* CONFIG_PCI */ + +/* SATA */ +#define CONFIG_FSL_SATA_V2 + +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 +#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 +#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 +#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 +#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 + +#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c +#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d +#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e +#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f + +#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 + +#define CONFIG_SYS_TBIPA_VALUE 8 +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* +* USB +*/ +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_HAS_FSL_MPH_USB + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif + +#ifdef CONFIG_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH u-boot.bin + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ + "bank_intlv=cs0_cs1\0" \ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ + "usb_dr_mode=host\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ + "fdtaddr=1e00000\0" \ + "fdtfile=p2041rdb/p2041rdb.dtb\0" \ + "bdev=sda3\0" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT + +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/P3041DS.h b/roms/u-boot/include/configs/P3041DS.h new file mode 100644 index 000000000..2f6cc5d8e --- /dev/null +++ b/roms/u-boot/include/configs/P3041DS.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + */ + +/* + * P3041 DS board configuration file + * + */ +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE3 +#define CONFIG_PCIE4 +#define CONFIG_SYS_DPAA_RMAN + +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ +#define CONFIG_SRIO_PCIE_BOOT_MASTER +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#include "corenet_ds.h" diff --git a/roms/u-boot/include/configs/P4080DS.h b/roms/u-boot/include/configs/P4080DS.h new file mode 100644 index 000000000..ed88b4184 --- /dev/null +++ b/roms/u-boot/include/configs/P4080DS.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + */ + +/* + * P4080 DS board configuration file + * Also supports P4040 DS + */ +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#define CONFIG_PCIE3 + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_LBA48 + +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ +#define CONFIG_SRIO_PCIE_BOOT_MASTER +#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ + +#include "corenet_ds.h" diff --git a/roms/u-boot/include/configs/P5040DS.h b/roms/u-boot/include/configs/P5040DS.h new file mode 100644 index 000000000..12666d6ee --- /dev/null +++ b/roms/u-boot/include/configs/P5040DS.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + */ + +/* + * P5040 DS board configuration file + * + */ +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_PCIE3 +#define CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_FSL_RAID_ENGINE + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#include "corenet_ds.h" diff --git a/roms/u-boot/include/configs/SBx81LIFKW.h b/roms/u-boot/include/configs/SBx81LIFKW.h new file mode 100644 index 000000000..eaa6b9246 --- /dev/null +++ b/roms/u-boot/include/configs/SBx81LIFKW.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Allied Telesis + */ + +#ifndef _CONFIG_SBX81LIFKW_H +#define _CONFIG_SBX81LIFKW_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg + +/* additions for new ARM relocation support */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ +#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ +#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ +#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ +#define CONFIG_KIRKWOOD_GPIO 1 + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" +#define MTDPARTS_MTDOOPS "errlog" +#define CONFIG_DOS_PARTITION + +/* + * Environment variables configurations + */ + +/* + * U-Boot bootcode configuration + */ + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ + +/* size in bytes reserved for initial data */ + +#include +/* There is no PHY directly connected so don't ask it for link status */ +#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN + +/* + * Other required minimal configurations + */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NET_MULTI /* specify more that one ports available */ +#define CONFIG_MVGBE /* Enable kirkwood Gbe Controller Driver */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */ +#define CONFIG_PHY_BASE_ADR 0x01 +#endif /* CONFIG_CMD_NET */ + +#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */ + +#endif /* _CONFIG_SBX81LIFKW_H */ diff --git a/roms/u-boot/include/configs/SBx81LIFXCAT.h b/roms/u-boot/include/configs/SBx81LIFXCAT.h new file mode 100644 index 000000000..c0dc3d38c --- /dev/null +++ b/roms/u-boot/include/configs/SBx81LIFXCAT.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Allied Telesis + */ + +#ifndef _CONFIG_SBX81LIFXCAT_H +#define _CONFIG_SBX81LIFXCAT_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg + +/* additions for new ARM relocation support */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ +#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ +#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ +#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ +#define CONFIG_KIRKWOOD_GPIO 1 + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" +#define MTDPARTS_MTDOOPS "errlog" +#define CONFIG_DOS_PARTITION + +/* + * Environment variables configurations + */ + +/* + * U-Boot bootcode configuration + */ + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ + +/* size in bytes reserved for initial data */ + +#include +/* There is no PHY directly connected so don't ask it for link status */ +#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN + +/* + * Other required minimal configurations + */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NET_MULTI /* specify more that one ports available */ +#define CONFIG_MVGBE /* Enable kirkwood Gbe Controller Driver */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */ +#define CONFIG_PHY_BASE_ADR 0x01 +#endif /* CONFIG_CMD_NET */ + +#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */ + +#endif /* _CONFIG_SBX81LIFXCAT_H */ diff --git a/roms/u-boot/include/configs/T102xRDB.h b/roms/u-boot/include/configs/T102xRDB.h new file mode 100644 index 000000000..35b11ad88 --- /dev/null +++ b/roms/u-boot/include/configs/T102xRDB.h @@ -0,0 +1,709 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + */ + +/* + * T1024/T1023 RDB board configuration file + */ + +#ifndef __T1024RDB_H +#define __T1024RDB_H + +#include + +/* High Level Configuration Options */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS + +/* support deep sleep */ +#ifdef CONFIG_ARCH_T1024 +#define CONFIG_DEEP_SLEEP +#endif + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif + +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#if defined(CONFIG_TARGET_T1024RDB) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg +#elif defined(CONFIG_TARGET_T1023RDB) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg +#endif +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#if defined(CONFIG_TARGET_T1024RDB) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg +#elif defined(CONFIG_TARGET_T1023RDB) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg +#endif +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#if defined(CONFIG_TARGET_T1024RDB) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg +#elif defined(CONFIG_TARGET_T1023RDB) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg +#endif +#endif + +#endif /* CONFIG_RAMBOOT_PBL */ + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +/* PCIe Boot - Master */ +#define CONFIG_SRIO_PCIE_BOOT_MASTER +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#else +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 +#endif +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#else +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 +#endif +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* PCIe Boot - Slave */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +/* Set 1M boot space for PCIe boot */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (256 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#if defined(CONFIG_TARGET_T1024RDB) +#define CONFIG_DDR_SPD +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x51 +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#elif defined(CONFIG_TARGET_T1023RDB) +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_SYS_SDRAM_SIZE 2048 +#endif + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) + +/* NOR Flash Timing Params */ +#if defined(CONFIG_TARGET_T1024RDB) +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#elif defined(CONFIG_TARGET_T1023RDB) +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ + CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) +#endif +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + +#ifdef CONFIG_TARGET_T1024RDB +/* CPLD on IFC */ +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR2 0x0 + +/* CPLD Timing parameters for IFC CS2 */ +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS2_FTIM3 0x0 +#endif + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#if defined(CONFIG_TARGET_T1024RDB) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) +#elif defined(CONFIG_TARGET_T1023RDB) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#endif + +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#if defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +/* Serial Port */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Video */ +#undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +/* + * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so + * disable empty flash sector detection, which is I/O-intensive. + */ +#undef CONFIG_SYS_FLASH_EMPTY_INFO +#endif + +/* I2C */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ +#define I2C_PCA6408_BUS_NUM 1 +#define I2C_PCA6408_ADDR 0x20 + +/* I2C bus multiplexer */ +#define I2C_MUX_CH_DEFAULT 0x8 + +/* + * RTC configuration + */ +#define RTC +#define CONFIG_RTC_DS1337 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * eSPI - Enhanced SPI + */ + +/* + * General PCIe + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#ifdef CONFIG_PCI +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#endif + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#ifdef CONFIG_PCIE2 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#endif + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#ifdef CONFIG_PCIE3 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#endif + +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#endif /* CONFIG_PCI */ + +/* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif + +/* + * SDHC + */ +#ifdef CONFIG_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#else +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#endif +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#else +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#endif +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN + +/* Default address of microcode for the Linux FMan driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_QE_FW_ADDR 0x130000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). + */ +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) +#elif defined(CONFIG_MTD_RAW_NAND) +#if defined(CONFIG_TARGET_T1024RDB) +#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_TARGET_T1023RDB) +#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) +#endif +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 +#else +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_TARGET_T1024RDB) +#define RGMII_PHY1_ADDR 0x2 +#define RGMII_PHY2_ADDR 0x6 +#define SGMII_AQR_PHY_ADDR 0x2 +#define FM1_10GEC1_PHY_ADDR 0x1 +#elif defined(CONFIG_TARGET_T1023RDB) +#define RGMII_PHY1_ADDR 0x1 +#define SGMII_RTK_PHY_ADDR 0x3 +#define SGMII_AQR_PHY_ADDR 0x2 +#endif +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_ETHPRIME "FM1@DTSEC4" +#endif + +/* + * Dynamic MTD Partition support with mtdparts + */ + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ +#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ +#define __USB_PHY_TYPE utmi + +#ifdef CONFIG_ARCH_T1024 +#define CONFIG_BOARDNAME t1024rdb +#define BANK_INTLV cs0_cs1 +#else +#define CONFIG_BOARDNAME t1023rdb +#define BANK_INTLV null +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ + "bank_intlv=" __stringify(BANK_INTLV) "\0" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ + "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ + "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ + __stringify(CONFIG_BOARDNAME) ".dtb\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ + "netdev=eth0\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "fdtaddr=1e00000\0" \ + "bdev=sda3\0" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#include + +#endif /* __T1024RDB_H */ diff --git a/roms/u-boot/include/configs/T104xRDB.h b/roms/u-boot/include/configs/T104xRDB.h new file mode 100644 index 000000000..ea239f74c --- /dev/null +++ b/roms/u-boot/include/configs/T104xRDB.h @@ -0,0 +1,805 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * T104x RDB board configuration file + */ +#include + +#ifdef CONFIG_RAMBOOT_PBL + +#ifndef CONFIG_NXP_ESBC +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg +#else +#define CONFIG_SYS_FSL_PBL_PBI \ + $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg +#endif + +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 + +#ifdef CONFIG_MTD_RAW_NAND +#ifdef CONFIG_NXP_ESBC +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. + */ +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ + CONFIG_U_BOOT_HDR_SIZE) +#else +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#endif +#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#ifdef CONFIG_TARGET_T1040RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg +#endif +#ifdef CONFIG_TARGET_T1042RDB_PI +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg +#endif +#ifdef CONFIG_TARGET_T1042RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg +#endif +#ifdef CONFIG_TARGET_T1040D4RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg +#endif +#ifdef CONFIG_TARGET_T1042D4RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg +#endif +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#ifdef CONFIG_TARGET_T1040RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg +#endif +#ifdef CONFIG_TARGET_T1042RDB_PI +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg +#endif +#ifdef CONFIG_TARGET_T1042RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg +#endif +#ifdef CONFIG_TARGET_T1040D4RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg +#endif +#ifdef CONFIG_TARGET_T1042D4RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg +#endif +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#ifdef CONFIG_TARGET_T1040RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg +#endif +#ifdef CONFIG_TARGET_T1042RDB_PI +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg +#endif +#ifdef CONFIG_TARGET_T1042RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg +#endif +#ifdef CONFIG_TARGET_T1040D4RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg +#endif +#ifdef CONFIG_TARGET_T1042D4RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg +#endif +#endif + +#endif + +/* High Level Configuration Options */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ + +/* support deep sleep */ +#define CONFIG_DEEP_SLEEP + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ +#define CONFIG_PCIE4 /* PCIE controller 4 */ + +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#if defined(CONFIG_SPIFLASH) +#elif defined(CONFIG_MTD_RAW_NAND) +#ifdef CONFIG_NXP_ESBC +#define CONFIG_RAMBOOT_NAND +#define CONFIG_BOOTSCRIPT_COPY_RAM +#endif +#endif + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 66666666 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +/* + * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence + * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address + * (CONFIG_SYS_INIT_L3_VADDR) will be different. + */ +#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE 256 << 10 +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) +#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x51 + +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + +#define CONFIG_SYS_NOR_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) + +/* + * TDM Definition + */ +#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + +/* CPLD on IFC */ +#define CPLD_LBMAP_MASK 0x3F +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_OVERRIDE 0x40 +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ +#define CPLD_LBMAP_RESET 0xFF +#define CPLD_LBMAP_SHIFT 0x03 + +#if defined(CONFIG_TARGET_T1042RDB_PI) +#define CPLD_DIU_SEL_DFP 0x80 +#elif defined(CONFIG_TARGET_T1042D4RDB) +#define CPLD_DIU_SEL_DFP 0xc0 +#endif + +#if defined(CONFIG_TARGET_T1040D4RDB) +#define CPLD_INT_MASK_ALL 0xFF +#define CPLD_INT_MASK_THERM 0x80 +#define CPLD_INT_MASK_DVI_DFP 0x40 +#define CPLD_INT_MASK_QSGMII1 0x20 +#define CPLD_INT_MASK_QSGMII2 0x10 +#define CPLD_INT_MASK_SGMI1 0x08 +#define CPLD_INT_MASK_SGMI2 0x04 +#define CPLD_INT_MASK_TDMR1 0x02 +#define CPLD_INT_MASK_TDMR2 0x01 +#endif + +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR2 0x0 +/* CPLD Timing parameters for IFC CS2 */ +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS2_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + +#if defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008044 +#if defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_A008044_WORKAROUND +#endif +#endif + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +#if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) +/* Video */ +#define CONFIG_FSL_DIU_FB + +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_FSL_DIU_CH7301 +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#endif +#endif + +/* I2C */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C3_SPEED 400000 +#define CONFIG_SYS_FSL_I2C4_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR 0x70 +#define I2C_MUX_CH_DEFAULT 0x8 + +#if defined(CONFIG_TARGET_T1042RDB_PI) || \ + defined(CONFIG_TARGET_T1040D4RDB) || \ + defined(CONFIG_TARGET_T1042D4RDB) +/* LDI/DVI Encoder for display */ +#define CONFIG_SYS_I2C_LDI_ADDR 0x38 +#define CONFIG_SYS_I2C_DVI_ADDR 0x75 +#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 + +/* + * RTC configuration + */ +#define RTC +#define CONFIG_RTC_DS1337 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/*DVI encoder*/ +#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 +#endif + +/* + * eSPI - Enhanced SPI + */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +#ifdef CONFIG_PCI +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#endif + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#ifdef CONFIG_PCIE2 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#endif + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#ifdef CONFIG_PCIE3 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#endif + +/* controller 4, Base address 203000 */ +#ifdef CONFIG_PCIE4 +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#endif + +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#endif /* CONFIG_PCI */ + +/* SATA */ +#define CONFIG_FSL_SATA_V2 +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#endif + +/* +* USB +*/ +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_HAS_FSL_DR_USB +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif +#endif + +#ifdef CONFIG_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME + +#define CONFIG_U_QE + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. + */ +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#elif defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#endif + +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_QE_FW_ADDR 0x130000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) +#elif defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 +#endif + +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_FMAN_ENET +#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#elif defined(CONFIG_TARGET_T1040D4RDB) +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 +#elif defined(CONFIG_TARGET_T1042D4RDB) +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 +#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 +#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 +#endif + +#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 +#else +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 +#endif + +/* Enable VSC9953 L2 Switch driver on T1040 SoC */ +#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) +#define CONFIG_VSC9953 +#ifdef CONFIG_TARGET_T1040RDB +#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 +#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 +#else +#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 +#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c +#endif +#endif + +#define CONFIG_ETHPRIME "FM1@DTSEC4" +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Dynamic MTD Partition support with mtdparts + */ + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define __USB_PHY_TYPE utmi +#define RAMDISKFILE "t104xrdb/ramdisk.uboot" + +#ifdef CONFIG_TARGET_T1040RDB +#define FDTFILE "t1040rdb/t1040rdb.dtb" +#elif defined(CONFIG_TARGET_T1042RDB_PI) +#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" +#elif defined(CONFIG_TARGET_T1042RDB) +#define FDTFILE "t1042rdb/t1042rdb.dtb" +#elif defined(CONFIG_TARGET_T1040D4RDB) +#define FDTFILE "t1042rdb/t1040d4rdb.dtb" +#elif defined(CONFIG_TARGET_T1042D4RDB) +#define FDTFILE "t1042rdb/t1042d4rdb.dtb" +#endif + +#ifdef CONFIG_FSL_DIU_FB +#define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" +#else +#define DIU_ENVIRONMENT +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ + "fdtaddr=1e00000\0" \ + "fdtfile=" __stringify(FDTFILE) "\0" \ + "bdev=sda3\0" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/T208xQDS.h b/roms/u-boot/include/configs/T208xQDS.h new file mode 100644 index 000000000..7bc792b8d --- /dev/null +++ b/roms/u-boot/include/configs/T208xQDS.h @@ -0,0 +1,751 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2011-2013 Freescale Semiconductor, Inc. + * Copyright 2020-2021 NXP + */ + +/* + * T2080/T2081 QDS board configuration file + */ + +#ifndef __T208xQDS_H +#define __T208xQDS_H + +#include + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ +#if defined(CONFIG_ARCH_T2080) +#define CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ +#endif + +/* High Level Configuration Options */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg + +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif + +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#if defined(CONFIG_ARCH_T2080) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg +#endif +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#if defined(CONFIG_ARCH_T2080) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg +#endif +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#if defined(CONFIG_ARCH_T2080) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg +#endif +#endif + +#endif /* CONFIG_RAMBOOT_PBL */ + +#define CONFIG_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (512 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_DDR_SPD +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CTRL_INTLV_PREFERED cacheline + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} + +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define QIXIS_BASE 0xffdf0000 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_RCW_SRC_NAND 0x104 +#define QIXIS_RCW_SRC_SD 0x040 +#define QIXIS_RST_CTL_RESET 0x83 +#define QIXIS_RST_FORCE_MEM 0x1 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) + +#define CONFIG_SYS_CSPR3_EXT (0xf) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CONFIG_SYS_CSOR3 0x0 +/* QIXIS Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */\ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#if defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* + * I2C + */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +#define CONFIG_SYS_FSL_I2C_SPEED 100000 +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 +#define CONFIG_SYS_FSL_I2C3_SPEED 100000 +#define CONFIG_SYS_FSL_I2C4_SPEED 100000 +#endif + +#define CONFIG_SYS_I2C_FSL + +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ +#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ +#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ +#define I2C_MUX_CH_DEFAULT 0x8 + +#define I2C_MUX_CH_VOL_MONITOR 0xa + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +#define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_VID +#endif +#define CONFIG_VOL_MONITOR_IR36021_SET +#define CONFIG_VOL_MONITOR_IR36021_READ +/* The lowest and highest voltage allowed for T208xQDS */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + +/* + * RapidIO + */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ + +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* + * SRIO_PCIE_BOOT - SLAVE + */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#endif + +/* + * eSPI - Enhanced SPI + */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ +#define CONFIG_PCIE4 /* PCIE controller 4 */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull + +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull + +#ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_BMAN_NUM_PORTALS 18 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 18 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +#define CONFIG_SYS_PMAN +#define CONFIG_SYS_DPAA_DCE +#define CONFIG_SYS_DPAA_RMAN /* RMan */ +#define CONFIG_SYS_INTERLAKEN + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. + */ +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#elif defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 +#else +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 +#define FM1_10GEC1_PHY_ADDR 0x3 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_ETHPRIME "FM1@DTSEC3" +#endif + +/* + * SATA + */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA +#define CONFIG_LBA48 +#endif + +/* + * USB + */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_HAS_FSL_DR_USB +#endif + +/* + * SDHC + */ +#ifdef CONFIG_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#endif + +/* + * Dynamic MTD Partition support with mtdparts + */ + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:" \ + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ + "bank_intlv=auto;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t2080qds/ramdisk.uboot\0" \ + "fdtaddr=1e00000\0" \ + "fdtfile=t2080qds/t2080qds.dtb\0" \ + "bdev=sda3\0" + +/* + * For emulation this causes u-boot to jump to the start of the + * proof point app code automatically + */ +#define CONFIG_PROOF_POINTS \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x29000000 - - -;" \ + "cpu 2 release 0x29000000 - - -;" \ + "cpu 3 release 0x29000000 - - -;" \ + "cpu 4 release 0x29000000 - - -;" \ + "cpu 5 release 0x29000000 - - -;" \ + "cpu 6 release 0x29000000 - - -;" \ + "cpu 7 release 0x29000000 - - -;" \ + "go 0x29000000" + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_ALU \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x01000000 - - -;" \ + "cpu 2 release 0x01000000 - - -;" \ + "cpu 3 release 0x01000000 - - -;" \ + "cpu 4 release 0x01000000 - - -;" \ + "cpu 5 release 0x01000000 - - -;" \ + "cpu 6 release 0x01000000 - - -;" \ + "cpu 7 release 0x01000000 - - -;" \ + "go 0x01000000" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#include + +#endif /* __T208xQDS_H */ diff --git a/roms/u-boot/include/configs/T208xRDB.h b/roms/u-boot/include/configs/T208xRDB.h new file mode 100644 index 000000000..9449e30bf --- /dev/null +++ b/roms/u-boot/include/configs/T208xRDB.h @@ -0,0 +1,709 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020-2021 NXP + */ + +/* + * T2080 RDB/PCIe board configuration file + */ + +#ifndef __T2080RDB_H +#define __T2080RDB_H + +#include + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ +#define CONFIG_FSL_SATA_V2 + +/* High Level Configuration Options */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg + +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif + +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg +#endif + +#endif /* CONFIG_RAMBOOT_PBL */ + +#define CONFIG_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ 66660000 +#define CONFIG_DDR_CLK_FREQ 133330000 + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (512 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_DDR_SPD +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CTRL_INTLV_PREFERED cacheline + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } + +/* CPLD on IFC */ +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR2 0x0 + +/* CPLD Timing parameters for IFC CS2 */ +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS2_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */\ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + +#if defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* + * I2C + */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +#define CONFIG_SYS_FSL_I2C_SPEED 100000 +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 +#define CONFIG_SYS_FSL_I2C3_SPEED 100000 +#define CONFIG_SYS_FSL_I2C4_SPEED 100000 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +#define CONFIG_SYS_I2C_FSL + +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ +#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ +#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ +#define I2C_MUX_CH_DEFAULT 0x8 + +#define I2C_MUX_CH_VOL_MONITOR 0xa + +#define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_VID +#endif +#define CONFIG_VOL_MONITOR_IR36021_SET +#define CONFIG_VOL_MONITOR_IR36021_READ +/* The lowest and highest voltage allowed for T208xRDB */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + +/* + * RapidIO + */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ + +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* + * SRIO_PCIE_BOOT - SLAVE + */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#endif + +/* + * eSPI - Enhanced SPI + */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ +#define CONFIG_PCIE4 /* PCIE controller 4 */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull + +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull + +#ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_BMAN_NUM_PORTALS 18 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 18 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +#define CONFIG_SYS_PMAN +#define CONFIG_SYS_DPAA_DCE +#define CONFIG_SYS_DPAA_RMAN /* RMan */ +#define CONFIG_SYS_INTERLAKEN + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#define CONFIG_CORTINA_FW_ADDR 0x120000 + +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. + */ +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) + +#elif defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_CORTINA_FW_ADDR 0xFFE10000 +#else +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_CORTINA_FW_ADDR 0xEFE00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_CORTINA_FW_LENGTH 0x40000 +#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ +#define RGMII_PHY2_ADDR 0x02 +#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ +#define CORTINA_PHY_ADDR2 0x0d +/* Aquantia AQ1202 10G Base-T used by board revisions up to C */ +#define FM1_10GEC3_PHY_ADDR 0x00 +#define FM1_10GEC4_PHY_ADDR 0x01 +/* Aquantia AQR113C 10G Base-T used by board revisions D and up */ +#define AQR113C_PHY_ADDR1 0x00 +#define AQR113C_PHY_ADDR2 0x08 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_ETHPRIME "FM1@DTSEC3" +#endif + +/* + * SATA + */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA +#define CONFIG_LBA48 +#endif + +/* + * USB + */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_HAS_FSL_DR_USB +#endif + +/* + * SDHC + */ +#ifdef CONFIG_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#endif + +/* + * Dynamic MTD Partition support with mtdparts + */ + +/* + * Environment + */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:" \ + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ + "bank_intlv=auto;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ + "fdtaddr=1e00000\0" \ + "fdtfile=t2080rdb/t2080rdb.dtb\0" \ + "bdev=sda3\0" + +/* + * For emulation this causes u-boot to jump to the start of the + * proof point app code automatically + */ +#define CONFIG_PROOF_POINTS \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x29000000 - - -;" \ + "cpu 2 release 0x29000000 - - -;" \ + "cpu 3 release 0x29000000 - - -;" \ + "cpu 4 release 0x29000000 - - -;" \ + "cpu 5 release 0x29000000 - - -;" \ + "cpu 6 release 0x29000000 - - -;" \ + "cpu 7 release 0x29000000 - - -;" \ + "go 0x29000000" + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_ALU \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x01000000 - - -;" \ + "cpu 2 release 0x01000000 - - -;" \ + "cpu 3 release 0x01000000 - - -;" \ + "cpu 4 release 0x01000000 - - -;" \ + "cpu 5 release 0x01000000 - - -;" \ + "cpu 6 release 0x01000000 - - -;" \ + "cpu 7 release 0x01000000 - - -;" \ + "go 0x01000000" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#include + +#endif /* __T2080RDB_H */ diff --git a/roms/u-boot/include/configs/T4240RDB.h b/roms/u-boot/include/configs/T4240RDB.h new file mode 100644 index 000000000..139beae08 --- /dev/null +++ b/roms/u-boot/include/configs/T4240RDB.h @@ -0,0 +1,666 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020-2021 NXP + */ + +/* + * T4240 RDB board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE4 + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg +#ifndef CONFIG_SDCARD +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#else +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif + +#endif +#endif /* CONFIG_RAMBOOT_PBL */ + +#define CONFIG_DDR_ECC + +/* High Level Configuration Options */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (512 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_DDR_SPD + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* I2C */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +#define CONFIG_SYS_I2C_FSL + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull + +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull + +#ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#endif /* CONFIG_PCI */ + +/* SATA */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_SYS_CLK_FREQ 66666666 +#define CONFIG_DDR_CLK_FREQ 133333333 + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +/* + * DDR Setup + */ +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x52 +#define SPD_EEPROM_ADDRESS2 0x54 +#define SPD_EEPROM_ADDRESS3 0x56 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + +#if defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 + +/* CPLD on IFC */ +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR3_EXT (0xf) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) + +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CONFIG_SYS_CSOR3 0x0 + +/* CPLD Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +/* I2C */ +#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ + +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_VOL_MONITOR 0xa +#define I2C_MUX_CH_VSC3316_FS 0xc +#define I2C_MUX_CH_VSC3316_BS 0xd + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +#define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_VID +#endif +#define CONFIG_VOL_MONITOR_IR36021_SET +#define CONFIG_VOL_MONITOR_IR36021_READ +/* The lowest and highest voltage allowed for T4240RDB */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + +/* + * eSPI - Enhanced SPI + */ + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_BMAN_NUM_PORTALS 50 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 50 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +#define CONFIG_SYS_PMAN +#define CONFIG_SYS_DPAA_DCE +#define CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_INTERLAKEN + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. + */ +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#elif defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_CORTINA_FW_ADDR 0xefe00000 +#define CONFIG_CORTINA_FW_LENGTH 0x40000 +#define SGMII_PHY_ADDR1 0x0 +#define SGMII_PHY_ADDR2 0x1 +#define SGMII_PHY_ADDR3 0x2 +#define SGMII_PHY_ADDR4 0x3 +#define SGMII_PHY_ADDR5 0x4 +#define SGMII_PHY_ADDR6 0x5 +#define SGMII_PHY_ADDR7 0x6 +#define SGMII_PHY_ADDR8 0x7 +#define FM1_10GEC1_PHY_ADDR 0x10 +#define FM1_10GEC2_PHY_ADDR 0x11 +#define FM2_10GEC1_PHY_ADDR 0x12 +#define FM2_10GEC2_PHY_ADDR 0x13 +#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR +#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR +#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR +#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR +#endif + +/* SATA */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#endif + +/* +* USB +*/ +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#endif + + +#define __USB_PHY_TYPE utmi + +/* + * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be + * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way + * interleaving. It can be cacheline, page, bank, superbank. + * See doc/README.fsl-ddr for details. + */ +#ifdef CONFIG_ARCH_T4240 +#define CTRL_INTLV_PREFERED 3way_4KB +#else +#define CTRL_INTLV_PREFERED cacheline +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:" \ + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ + "bank_intlv=auto;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ + "fdtaddr=1e00000\0" \ + "fdtfile=t4240rdb/t4240rdb.dtb\0" \ + "bdev=sda3\0" + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/TQM834x.h b/roms/u-boot/include/configs/TQM834x.h new file mode 100644 index 000000000..aa70f01dd --- /dev/null +++ b/roms/u-boot/include/configs/TQM834x.h @@ -0,0 +1,277 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +/* + * TQM8349 board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ + +/* board pre init: do not call, nothing to do */ + +/* detect the number of flash banks */ + +/* + * DDR Setup + */ + /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define DDR_CASLAT_25 /* CASLAT set to 2.5 */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ + +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ + +/* + * FLASH on the Local Bus + */ +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ + +/* + * FLASH bank number detection + */ + +/* + * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of + * Flash banks has to be determined at runtime and stored in a gloabl variable + * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is + * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array + * flash_info, and should be made sufficiently large to accomodate the number + * of banks that might actually be detected. Since most (all?) Flash related + * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on + * the board, it is defined as tqm834x_num_flash_banks. + */ +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 + +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ + + +/* disable remaining mappings */ +#define CONFIG_SYS_BR1_PRELIM 0x00000000 +#define CONFIG_SYS_OR1_PRELIM 0x00000000 + +#define CONFIG_SYS_BR2_PRELIM 0x00000000 +#define CONFIG_SYS_OR2_PRELIM 0x00000000 + +#define CONFIG_SYS_BR3_PRELIM 0x00000000 +#define CONFIG_SYS_OR3_PRELIM 0x00000000 + +/* + * Monitor config + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +# define CONFIG_SYS_RAMBOOT +#else +# undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ + +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + + /* Reserve 384 kB = 3 sect. for Mon */ +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) + /* Reserve 512 kB for malloc */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 + +/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ + +/* I2C RTC */ +#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * TSEC + */ + +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +#if defined(CONFIG_PCI) + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +/* PCI1 host bridge */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE \ + (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 +#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE +#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ + + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE + #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE + #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ +#endif + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + +/* + * Environment + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) + +/* System IO Config */ +#define CONFIG_SYS_SICRH 0 +#define CONFIG_SYS_SICRL SICRL_LDP_A + +/* PCI */ +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#endif + +/* + * Environment Configuration + */ + + /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 400000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=tqm834x\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "flash_nfs_old=run nfsargs addip addcons;" \ + "bootm ${kernel_addr}\0" \ + "flash_nfs=run nfsargs addip addcons;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "flash_self_old=run ramargs addip addcons;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_self=run ramargs addip addcons;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "net_nfs_old=tftp 400000 ${bootfile};" \ + "run nfsargs addip addcons;bootm\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "tftp ${fdt_addr_r} ${fdt_file}; " \ + "run nfsargs addip addcons; " \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=tqm834x/uImage\0" \ + "fdtfile=tqm834x/tqm834x.dtb\0" \ + "kernel_addr_r=400000\0" \ + "fdt_addr_r=600000\0" \ + "ramdisk_addr_r=800000\0" \ + "kernel_addr=800C0000\0" \ + "fdt_addr=800A0000\0" \ + "ramdisk_addr=80300000\0" \ + "u-boot=tqm834x/u-boot.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=protect off 80000000 +${filesize};" \ + "era 80000000 +${filesize};" \ + "cp.b 200000 80000000 ${filesize}\0" \ + "upd=run load update\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +/* + * JFFS2 partitions + */ +/* mtdparts command line support */ + +/* default mtd partition table */ +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/UCP1020.h b/roms/u-boot/include/configs/UCP1020.h new file mode 100644 index 000000000..c3cc72e13 --- /dev/null +++ b/roms/u-boot/include/configs/UCP1020.h @@ -0,0 +1,832 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013-2019 Arcturus Networks, Inc. + * https://www.arcturusnetworks.com/products/ucp1020/ + * based on include/configs/p1_p2_rdb_pc.h + * original copyright follows: + * Copyright 2009-2011 Freescale Semiconductor, Inc. + */ + +/* + * QorIQ uCP1020-xx boards configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/*** Arcturus FirmWare Environment */ + +#define MAX_SERIAL_SIZE 15 +#define MAX_HWADDR_SIZE 17 + +#define MAX_FWENV_ADDR 4 + +#define FWENV_MMC 1 +#define FWENV_SPI_FLASH 2 +#define FWENV_NOR_FLASH 3 +/* + #define FWENV_TYPE FWENV_MMC + #define FWENV_TYPE FWENV_SPI_FLASH +*/ +#define FWENV_TYPE FWENV_NOR_FLASH + +#if (FWENV_TYPE == FWENV_MMC) +#define FWENV_ADDR1 -1 +#define FWENV_ADDR2 -1 +#define FWENV_ADDR3 -1 +#define FWENV_ADDR4 -1 +#define EMPY_CHAR 0 +#endif + +#if (FWENV_TYPE == FWENV_SPI_FLASH) +#ifndef CONFIG_SF_DEFAULT_SPEED +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#endif +#ifndef CONFIG_SF_DEFAULT_MODE +#define CONFIG_SF_DEFAULT_MODE SPI_MODE0 +#endif +#ifndef CONFIG_SF_DEFAULT_CS +#define CONFIG_SF_DEFAULT_CS 0 +#endif +#ifndef CONFIG_SF_DEFAULT_BUS +#define CONFIG_SF_DEFAULT_BUS 0 +#endif +#define FWENV_ADDR1 (0x200 - sizeof(smac)) +#define FWENV_ADDR2 (0x400 - sizeof(smac)) +#define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac)) +#define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac)) +#define EMPY_CHAR 0xff +#endif + +#if (FWENV_TYPE == FWENV_NOR_FLASH) +#define FWENV_ADDR1 0xEC080000 +#define FWENV_ADDR2 -1 +#define FWENV_ADDR3 -1 +#define FWENV_ADDR4 -1 +#define EMPY_CHAR 0xff +#endif +/***********************************/ + +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#if defined(CONFIG_TARTGET_UCP1020T1) + +#define CONFIG_UCP1020_REV_1_3 + +#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" + +#define CONFIG_TSEC1 +#define CONFIG_TSEC3 +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF +#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE +#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD +#define CONFIG_IPADDR 10.80.41.229 +#define CONFIG_SERVERIP 10.80.41.227 +#define CONFIG_NETMASK 255.255.252.0 +#define CONFIG_ETHPRIME "eTSEC3" + +#define CONFIG_SYS_L2_SIZE (256 << 10) + +#endif + +#if defined(CONFIG_TARGET_UCP1020) + +#define CONFIG_UCP1020 +#define CONFIG_UCP1020_REV_1_3 + +#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" + +#define CONFIG_TSEC1 +#define CONFIG_TSEC3 +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF +#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE +#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD +#define CONFIG_IPADDR 192.168.1.81 +#define CONFIG_IPADDR1 192.168.1.82 +#define CONFIG_IPADDR2 192.168.1.83 +#define CONFIG_SERVERIP 192.168.1.80 +#define CONFIG_GATEWAYIP 102.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_SYS_L2_SIZE (256 << 10) + +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RAMBOOT_SDCARD +#define CONFIG_SYS_RAMBOOT +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_LBA48 + +#define CONFIG_SYS_CLK_FREQ 66666666 +#define CONFIG_DDR_CLK_FREQ 66666666 + +#define CONFIG_HWCONFIG + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE +#define CONFIG_BTB + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k + SPL code*/ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif + +/* DDR Setup */ +#define CONFIG_DDR_ECC_ENABLE +#ifndef CONFIG_DDR_ECC_ENABLE +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_DDR_SPD +#endif +#define CONFIG_SYS_SPD_BUS_NUM 1 + +#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +/* Default settings for DDR3 */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 + +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 + +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#ifdef CONFIG_DDR_ECC_ENABLE +#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ +#else +#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ +#endif +#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 +#define CONFIG_SYS_DDR_TIMING_4 0x00220001 +#define CONFIG_SYS_DDR_TIMING_5 0x03402400 + +#define CONFIG_SYS_DDR_TIMING_3 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0 0x00330004 +#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 +#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF +#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 +#define CONFIG_SYS_DDR_MODE_1 0x40461520 +#define CONFIG_SYS_DDR_MODE_2 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL 0x0C300000 + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable + * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) + * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 + * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable + * (early boot only) + * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* + * Local Bus Definitions + */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ +#define CONFIG_SYS_FLASH_BASE 0xec000000 + +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ + | BR_PS_16 | BR_V) + +#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +/* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +/* Size of used area in RAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ + +#define CONFIG_SYS_PMC_BASE 0xff980000 +#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE +#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ + BR_PS_8 | BR_V) +#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ + OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ + OR_GPCM_EAD) + +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#ifdef CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#endif + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } +#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ + +#define CONFIG_RTC_DS1337 +#define CONFIG_RTC_DS1337_NOOSC +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 +#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C +#define CONFIG_SYS_I2C_IDT6V49205B 0x69 + +#if defined(CONFIG_PCI) +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 2, direct to uli, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 1, Slot 2, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#endif /* CONFIG_PCI */ + +/* + * Environment + */ +#if !defined(CONFIG_ENV_FIT_UCBOOT) && defined(CONFIG_RAMBOOT_SDCARD) +#define CONFIG_FSL_FIXED_MMC_LOCATION +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB + +#if defined(CONFIG_HAS_FSL_DR_USB) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#endif +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#ifdef CONFIG_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#endif + +/* Misc Extra Settings */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) + +#if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3) +#else +#error "UCP1020 module revision is not defined !!!" +#endif + +#define CONFIG_BOOTP_SERVERIP + +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define TSEC1_PHY_ADDR 4 +#define TSEC2_PHY_ADDR 0 +#define TSEC2_PHY_ADDR_SGMII 0x00 +#define TSEC3_PHY_ADDR 6 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#endif + +#define CONFIG_HOSTNAME "UCP1020" +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#if defined(CONFIG_DONGLE) + +#define CONFIG_EXTRA_ENV_SETTINGS \ +"bootcmd=run prog_spi_mbrbootcramfs\0" \ +"bootfile=uImage\0" \ +"consoledev=ttyS0\0" \ +"cramfsfile=image.cramfs\0" \ +"dtbaddr=0x00c00000\0" \ +"dtbfile=image.dtb\0" \ +"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ +"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ +"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ +"fileaddr=0x01000000\0" \ +"filesize=0x00080000\0" \ +"flashmbr=sf probe 0; " \ + "tftp $loadaddr $mbr; " \ + "sf erase $mbr_offset +$filesize; " \ + "sf write $loadaddr $mbr_offset $filesize\0" \ +"flashrecovery=tftp $recoveryaddr $cramfsfile; " \ + "protect off $nor_recoveryaddr +$filesize; " \ + "erase $nor_recoveryaddr +$filesize; " \ + "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ + "protect on $nor_recoveryaddr +$filesize\0 " \ +"flashuboot=tftp $ubootaddr $ubootfile; " \ + "protect off $nor_ubootaddr +$filesize; " \ + "erase $nor_ubootaddr +$filesize; " \ + "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ + "protect on $nor_ubootaddr +$filesize\0 " \ +"flashworking=tftp $workingaddr $cramfsfile; " \ + "protect off $nor_workingaddr +$filesize; " \ + "erase $nor_workingaddr +$filesize; " \ + "cp.b $workingaddr $nor_workingaddr $filesize; " \ + "protect on $nor_workingaddr +$filesize\0 " \ +"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ +"kerneladdr=0x01100000\0" \ +"kernelfile=uImage\0" \ +"loadaddr=0x01000000\0" \ +"mbr=uCP1020d.mbr\0" \ +"mbr_offset=0x00000000\0" \ +"mmbr=uCP1020Quiet.mbr\0" \ +"mmcpart=0:2\0" \ +"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ + "mmc erase 1 1; " \ + "mmc write $loadaddr 1 1\0" \ +"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ + "mmc erase 0x40 0x400; " \ + "mmc write $loadaddr 0x40 0x400\0" \ +"netdev=eth0\0" \ +"nor_recoveryaddr=0xEC0A0000\0" \ +"nor_ubootaddr=0xEFF80000\0" \ +"nor_workingaddr=0xECFA0000\0" \ +"norbootrecovery=setenv bootargs $recoverybootargs" \ + " console=$consoledev,$baudrate $othbootargs; " \ + "run norloadrecovery; " \ + "bootm $kerneladdr - $dtbaddr\0" \ +"norbootworking=setenv bootargs $workingbootargs" \ + " console=$consoledev,$baudrate $othbootargs; " \ + "run norloadworking; " \ + "bootm $kerneladdr - $dtbaddr\0" \ +"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ + "setenv cramfsaddr $nor_recoveryaddr; " \ + "cramfsload $dtbaddr $dtbfile; " \ + "cramfsload $kerneladdr $kernelfile\0" \ +"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ + "setenv cramfsaddr $nor_workingaddr; " \ + "cramfsload $dtbaddr $dtbfile; " \ + "cramfsload $kerneladdr $kernelfile\0" \ +"prog_spi_mbr=run spi__mbr\0" \ +"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ +"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ + "run spi__cramfs\0" \ +"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ + " console=$consoledev,$baudrate $othbootargs; " \ + "tftp $rootfsaddr $rootfsfile; " \ + "tftp $loadaddr $kernelfile; " \ + "tftp $dtbaddr $dtbfile; " \ + "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ +"ramdisk_size=120000\0" \ +"ramdiskfile=rootfs.ext2.gz.uboot\0" \ +"recoveryaddr=0x02F00000\0" \ +"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ +"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ + "mw.l 0xffe0f008 0x00400000\0" \ +"rootfsaddr=0x02F00000\0" \ +"rootfsfile=rootfs.ext2.gz.uboot\0" \ +"rootpath=/opt/nfsroot\0" \ +"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ + "protect off 0xeC000000 +$filesize; " \ + "erase 0xEC000000 +$filesize; " \ + "cp.b $loadaddr 0xEC000000 $filesize; " \ + "cmp.b $loadaddr 0xEC000000 $filesize; " \ + "protect on 0xeC000000 +$filesize\0" \ +"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ + "protect off 0xeFF80000 +$filesize; " \ + "erase 0xEFF80000 +$filesize; " \ + "cp.b $loadaddr 0xEFF80000 $filesize; " \ + "cmp.b $loadaddr 0xEFF80000 $filesize; " \ + "protect on 0xeFF80000 +$filesize\0" \ +"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ + "sf probe 0; sf erase 0x8000 +$filesize; " \ + "sf write $loadaddr 0x8000 $filesize\0" \ +"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ + "protect off 0xec0a0000 +$filesize; " \ + "erase 0xeC0A0000 +$filesize; " \ + "cp.b $loadaddr 0xeC0A0000 $filesize; " \ + "protect on 0xec0a0000 +$filesize\0" \ +"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ + "sf probe 1; sf erase 0 +$filesize; " \ + "sf write $loadaddr 0 $filesize\0" \ +"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ + "sf probe 0; sf erase 0 +$filesize; " \ + "sf write $loadaddr 0 $filesize\0" \ +"tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ +"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ +"ubootaddr=0x01000000\0" \ +"ubootfile=u-boot.bin\0" \ +"ubootd=u-boot4dongle.bin\0" \ +"upgrade=run flashworking\0" \ +"usb_phy_type=ulpi\0 " \ +"workingaddr=0x02F00000\0" \ +"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" + +#else + +#if defined(CONFIG_UCP1020T1) + +#define CONFIG_EXTRA_ENV_SETTINGS \ +"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ +"bootfile=uImage\0" \ +"consoledev=ttyS0\0" \ +"cramfsfile=image.cramfs\0" \ +"dtbaddr=0x00c00000\0" \ +"dtbfile=image.dtb\0" \ +"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ +"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ +"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ +"fileaddr=0x01000000\0" \ +"filesize=0x00080000\0" \ +"flashmbr=sf probe 0; " \ + "tftp $loadaddr $mbr; " \ + "sf erase $mbr_offset +$filesize; " \ + "sf write $loadaddr $mbr_offset $filesize\0" \ +"flashrecovery=tftp $recoveryaddr $cramfsfile; " \ + "protect off $nor_recoveryaddr +$filesize; " \ + "erase $nor_recoveryaddr +$filesize; " \ + "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ + "protect on $nor_recoveryaddr +$filesize\0 " \ +"flashuboot=tftp $ubootaddr $ubootfile; " \ + "protect off $nor_ubootaddr +$filesize; " \ + "erase $nor_ubootaddr +$filesize; " \ + "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ + "protect on $nor_ubootaddr +$filesize\0 " \ +"flashworking=tftp $workingaddr $cramfsfile; " \ + "protect off $nor_workingaddr +$filesize; " \ + "erase $nor_workingaddr +$filesize; " \ + "cp.b $workingaddr $nor_workingaddr $filesize; " \ + "protect on $nor_workingaddr +$filesize\0 " \ +"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ +"kerneladdr=0x01100000\0" \ +"kernelfile=uImage\0" \ +"loadaddr=0x01000000\0" \ +"mbr=uCP1020.mbr\0" \ +"mbr_offset=0x00000000\0" \ +"netdev=eth0\0" \ +"nor_recoveryaddr=0xEC0A0000\0" \ +"nor_ubootaddr=0xEFF80000\0" \ +"nor_workingaddr=0xECFA0000\0" \ +"norbootrecovery=setenv bootargs $recoverybootargs" \ + " console=$consoledev,$baudrate $othbootargs; " \ + "run norloadrecovery; " \ + "bootm $kerneladdr - $dtbaddr\0" \ +"norbootworking=setenv bootargs $workingbootargs" \ + " console=$consoledev,$baudrate $othbootargs; " \ + "run norloadworking; " \ + "bootm $kerneladdr - $dtbaddr\0" \ +"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ + "setenv cramfsaddr $nor_recoveryaddr; " \ + "cramfsload $dtbaddr $dtbfile; " \ + "cramfsload $kerneladdr $kernelfile\0" \ +"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ + "setenv cramfsaddr $nor_workingaddr; " \ + "cramfsload $dtbaddr $dtbfile; " \ + "cramfsload $kerneladdr $kernelfile\0" \ +"othbootargs=quiet\0" \ +"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ + " console=$consoledev,$baudrate $othbootargs; " \ + "tftp $rootfsaddr $rootfsfile; " \ + "tftp $loadaddr $kernelfile; " \ + "tftp $dtbaddr $dtbfile; " \ + "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ +"ramdisk_size=120000\0" \ +"ramdiskfile=rootfs.ext2.gz.uboot\0" \ +"recoveryaddr=0x02F00000\0" \ +"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ +"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ + "mw.l 0xffe0f008 0x00400000\0" \ +"rootfsaddr=0x02F00000\0" \ +"rootfsfile=rootfs.ext2.gz.uboot\0" \ +"rootpath=/opt/nfsroot\0" \ +"silent=1\0" \ +"tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ +"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ +"ubootaddr=0x01000000\0" \ +"ubootfile=u-boot.bin\0" \ +"upgrade=run flashworking\0" \ +"workingaddr=0x02F00000\0" \ +"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" + +#else /* For Arcturus Modules */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ +"bootcmd=run norkernel\0" \ +"bootfile=uImage\0" \ +"consoledev=ttyS0\0" \ +"dtbaddr=0x00c00000\0" \ +"dtbfile=image.dtb\0" \ +"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ +"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ +"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ +"fileaddr=0x01000000\0" \ +"filesize=0x00080000\0" \ +"flashmbr=sf probe 0; " \ + "tftp $loadaddr $mbr; " \ + "sf erase $mbr_offset +$filesize; " \ + "sf write $loadaddr $mbr_offset $filesize\0" \ +"flashuboot=tftp $loadaddr $ubootfile; " \ + "protect off $nor_ubootaddr0 +$filesize; " \ + "erase $nor_ubootaddr0 +$filesize; " \ + "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ + "protect on $nor_ubootaddr0 +$filesize; " \ + "protect off $nor_ubootaddr1 +$filesize; " \ + "erase $nor_ubootaddr1 +$filesize; " \ + "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ + "protect on $nor_ubootaddr1 +$filesize\0 " \ +"format0=protect off $part0base +$part0size; " \ + "erase $part0base +$part0size\0" \ +"format1=protect off $part1base +$part1size; " \ + "erase $part1base +$part1size\0" \ +"format2=protect off $part2base +$part2size; " \ + "erase $part2base +$part2size\0" \ +"format3=protect off $part3base +$part3size; " \ + "erase $part3base +$part3size\0" \ +"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ +"kerneladdr=0x01100000\0" \ +"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ +"kernelfile=uImage\0" \ +"loadaddr=0x01000000\0" \ +"mbr=uCP1020.mbr\0" \ +"mbr_offset=0x00000000\0" \ +"netdev=eth0\0" \ +"nor_ubootaddr0=0xEC000000\0" \ +"nor_ubootaddr1=0xEFF80000\0" \ +"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ + "run norkernelload; " \ + "bootm $kerneladdr - $dtbaddr\0" \ +"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ + "setenv cramfsaddr $part0base; " \ + "cramfsload $dtbaddr $dtbfile; " \ + "cramfsload $kerneladdr $kernelfile\0" \ +"part0base=0xEC100000\0" \ +"part0size=0x00700000\0" \ +"part1base=0xEC800000\0" \ +"part1size=0x02000000\0" \ +"part2base=0xEE800000\0" \ +"part2size=0x00800000\0" \ +"part3base=0xEF000000\0" \ +"part3size=0x00F80000\0" \ +"partENVbase=0xEC080000\0" \ +"partENVsize=0x00080000\0" \ +"program0=tftp part0-000000.bin; " \ + "protect off $part0base +$filesize; " \ + "erase $part0base +$filesize; " \ + "cp.b $loadaddr $part0base $filesize; " \ + "echo Verifying...; " \ + "cmp.b $loadaddr $part0base $filesize\0" \ +"program1=tftp part1-000000.bin; " \ + "protect off $part1base +$filesize; " \ + "erase $part1base +$filesize; " \ + "cp.b $loadaddr $part1base $filesize; " \ + "echo Verifying...; " \ + "cmp.b $loadaddr $part1base $filesize\0" \ +"program2=tftp part2-000000.bin; " \ + "protect off $part2base +$filesize; " \ + "erase $part2base +$filesize; " \ + "cp.b $loadaddr $part2base $filesize; " \ + "echo Verifying...; " \ + "cmp.b $loadaddr $part2base $filesize\0" \ +"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ + " console=$consoledev,$baudrate $othbootargs; " \ + "tftp $rootfsaddr $rootfsfile; " \ + "tftp $loadaddr $kernelfile; " \ + "tftp $dtbaddr $dtbfile; " \ + "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ +"ramdisk_size=120000\0" \ +"ramdiskfile=rootfs.ext2.gz.uboot\0" \ +"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ + "mw.l 0xffe0f008 0x00400000\0" \ +"rootfsaddr=0x02F00000\0" \ +"rootfsfile=rootfs.ext2.gz.uboot\0" \ +"rootpath=/opt/nfsroot\0" \ +"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ + "sf probe 0; sf erase 0 +$filesize; " \ + "sf write $loadaddr 0 $filesize\0" \ +"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ + "protect off 0xeC000000 +$filesize; " \ + "erase 0xEC000000 +$filesize; " \ + "cp.b $loadaddr 0xEC000000 $filesize; " \ + "cmp.b $loadaddr 0xEC000000 $filesize; " \ + "protect on 0xeC000000 +$filesize\0" \ +"tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ +"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ +"ubootfile=u-boot.bin\0" \ +"upgrade=run flashuboot\0" \ +"usb_phy_type=ulpi\0 " \ +"boot_nfs= " \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr\0" \ +"boot_hd = " \ + "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "usb start;" \ + "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ + "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ + "bootm $loadaddr - $fdtaddr\0" \ +"boot_usb_fat = " \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs " \ + "ramdisk_size=$ramdisk_size;" \ + "usb start;" \ + "fatload usb 0:2 $loadaddr $bootfile;" \ + "fatload usb 0:2 $fdtaddr $fdtfile;" \ + "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ +"boot_usb_ext2 = " \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs " \ + "ramdisk_size=$ramdisk_size;" \ + "usb start;" \ + "ext2load usb 0:4 $loadaddr $bootfile;" \ + "ext2load usb 0:4 $fdtaddr $fdtfile;" \ + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ +"boot_nor = " \ + "setenv bootargs root=/dev/$jffs2nor rw " \ + "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ + "bootm $norbootaddr - $norfdtaddr\0 " \ +"boot_ram = " \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs " \ + "ramdisk_size=$ramdisk_size;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" + +#endif +#endif + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/adp-ae3xx.h b/roms/u-boot/include/configs/adp-ae3xx.h new file mode 100644 index 000000000..a7adb599c --- /dev/null +++ b/roms/u-boot/include/configs/adp-ae3xx.h @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * CPU and Board Configuration Options + */ +#define CONFIG_USE_INTERRUPT + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SKIP_TRUNOFF_WATCHDOG + +#define CONFIG_ARCH_MAP_SYSMEM + +#define CONFIG_BOOTP_SERVERIP + +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_OF_CONTROL +#undef CONFIG_OF_SEPARATE +#define CONFIG_OF_EMBED +#endif +#endif + +/* + * Timer + */ +#define CONFIG_SYS_CLK_FREQ 39062500 +#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ + +/* + * Use Externel CLOCK or PCLK + */ +#undef CONFIG_FTRTC010_EXTCLK + +#ifndef CONFIG_FTRTC010_EXTCLK +#define CONFIG_FTRTC010_PCLK +#endif + +#ifdef CONFIG_FTRTC010_EXTCLK +#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ +#else +#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ +#endif + +#define TIMER_LOAD_VAL 0xffffffff + +/* + * Real Time Clock + */ +#define CONFIG_RTC_FTRTC010 + +/* + * Real Time Clock Divider + * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) + */ +#define OSC_5MHZ (5*1000000) +#define OSC_CLK (4*OSC_5MHZ) +#define RTC_DIV_COUNT (0.5) /* Why?? */ + +/* + * Serial console configuration + */ + +/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE +#ifndef CONFIG_DM_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#endif +#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ + +/* + * Miscellaneous configurable options + */ + +/* + * Size of malloc() pool + */ +/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ +#define CONFIG_SYS_MALLOC_LEN (512 << 10) + +/* + * Physical Memory Map + */ +#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ + +#define PHYS_SDRAM_1 \ + (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ + +#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ +#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Load address and memory test area should agree with + * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. + */ +#define CONFIG_SYS_LOAD_ADDR 0x300000 + +/* memtest works on 63 MB in DRAM */ + +/* + * Static memory controller configuration + */ +#define CONFIG_FTSMC020 + +#ifdef CONFIG_FTSMC020 +#include + +#define CONFIG_SYS_FTSMC020_CONFIGS { \ + { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ + { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ +} + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ +#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ + FTSMC020_TPR_AST(1) | \ + FTSMC020_TPR_CTW(1) | \ + FTSMC020_TPR_ATI(1) | \ + FTSMC020_TPR_AT2(1) | \ + FTSMC020_TPR_WTC(1) | \ + FTSMC020_TPR_AHT(1) | \ + FTSMC020_TPR_TRNA(1)) +#endif + +/* + * FLASH on ADP_AG101P is connected to BANK0 + * Just disalbe the other BANK to avoid detection error. + */ +#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define FTSMC020_BANK1_CONFIG (0x00) +#define FTSMC020_BANK1_TIMING (0x00) +#endif /* CONFIG_FTSMC020 */ + +/* + * FLASH and environment organization + */ +/* use CFI framework */ + +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL + +/* support JEDEC */ +#ifdef CONFIG_CFI_FLASH +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#endif + +/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ +#define PHYS_FLASH_1 0x88000000 /* BANK 0 */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ + +/* max number of memory banks */ +/* + * There are 4 banks supported for this Controller, + * but we have only 1 bank connected to flash on board + */ +#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#endif +#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} + +/* max number of sectors on one chip */ +#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +/* environments */ + + +/* SPI FLASH */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + +/* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) +/* Increase max gunzip size */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/adp-ag101p.h b/roms/u-boot/include/configs/adp-ag101p.h new file mode 100644 index 000000000..afec9ba24 --- /dev/null +++ b/roms/u-boot/include/configs/adp-ag101p.h @@ -0,0 +1,331 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * CPU and Board Configuration Options + */ +#define CONFIG_USE_INTERRUPT + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_ARCH_MAP_SYSMEM + +#define CONFIG_BOOTP_SERVERIP + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_MEM_REMAP +#endif + +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_OF_CONTROL +#undef CONFIG_OF_SEPARATE +#define CONFIG_OF_EMBED +#endif +#endif + +/* + * Timer + */ +#define CONFIG_SYS_CLK_FREQ 39062500 +#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ + +/* + * Use Externel CLOCK or PCLK + */ +#undef CONFIG_FTRTC010_EXTCLK + +#ifndef CONFIG_FTRTC010_EXTCLK +#define CONFIG_FTRTC010_PCLK +#endif + +#ifdef CONFIG_FTRTC010_EXTCLK +#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ +#else +#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ +#endif + +#define TIMER_LOAD_VAL 0xffffffff + +/* + * Real Time Clock + */ +#define CONFIG_RTC_FTRTC010 + +/* + * Real Time Clock Divider + * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) + */ +#define OSC_5MHZ (5*1000000) +#define OSC_CLK (4*OSC_5MHZ) +#define RTC_DIV_COUNT (0.5) /* Why?? */ + +/* + * Serial console configuration + */ + +/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE +#ifndef CONFIG_DM_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#endif +#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ + +/* + * Miscellaneous configurable options + */ + +/* + * Size of malloc() pool + */ +/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ +#define CONFIG_SYS_MALLOC_LEN (512 << 10) + +/* + * AHB Controller configuration + */ +#define CONFIG_FTAHBC020S + +#ifdef CONFIG_FTAHBC020S +#include + +/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ +#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 + +/* + * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, + * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote + * in C language. + */ +#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ + (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ + FTAHBC020S_SLAVE_BSR_SIZE(0xb)) +#endif + +/* + * Watchdog + */ +#define CONFIG_FTWDT010_WATCHDOG + +/* + * PMU Power controller configuration + */ +#define CONFIG_PMU +#define CONFIG_FTPMU010_POWER + +#ifdef CONFIG_FTPMU010_POWER +#include +#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E +#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ + FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ + FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ + FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ + FTPMU010_SDRAMHTC_CKE_DCSR | \ + FTPMU010_SDRAMHTC_DQM_DCSR | \ + FTPMU010_SDRAMHTC_SDCLK_DCSR) +#endif + +/* + * SDRAM controller configuration + */ +#define CONFIG_FTSDMC021 + +#ifdef CONFIG_FTSDMC021 +#include + +#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ + FTSDMC021_TP1_TRP(1) | \ + FTSDMC021_TP1_TRCD(1) | \ + FTSDMC021_TP1_TRF(3) | \ + FTSDMC021_TP1_TWR(1) | \ + FTSDMC021_TP1_TCL(2)) + +#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ + FTSDMC021_TP2_INI_REFT(8) | \ + FTSDMC021_TP2_REF_INTV(0x180)) + +/* + * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, + * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in + * C language. + */ +#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ + FTSDMC021_CR1_DSZ(3) | \ + FTSDMC021_CR1_MBW(2) | \ + FTSDMC021_CR1_BNKSIZE(6)) + +#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ + FTSDMC021_CR2_IREF | \ + FTSDMC021_CR2_ISMR) + +#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE +#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ + CONFIG_SYS_FTSDMC021_BANK0_BASE) + +#define CONFIG_SYS_FTSDMC021_BANK1_BASE \ + (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) +#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ + CONFIG_SYS_FTSDMC021_BANK1_BASE) +#endif + +/* + * Physical Memory Map + */ +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ +#else +#ifdef CONFIG_MEM_REMAP +#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ +#else +#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ +#endif +#endif + +#define PHYS_SDRAM_1 \ + (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ + +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ +#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ +#else +#ifdef CONFIG_MEM_REMAP +#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ +#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ +#else +#define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#endif +#endif + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 + +#ifdef CONFIG_MEM_REMAP +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ + GENERATED_GBL_DATA_SIZE) +#else +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) +#endif /* CONFIG_MEM_REMAP */ + +/* + * Load address and memory test area should agree with + * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. + */ +#define CONFIG_SYS_LOAD_ADDR 0x300000 + +/* memtest works on 63 MB in DRAM */ + +/* + * Static memory controller configuration + */ +#define CONFIG_FTSMC020 + +#ifdef CONFIG_FTSMC020 +#include + +#define CONFIG_SYS_FTSMC020_CONFIGS { \ + { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ + { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ +} + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ +#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ + FTSMC020_TPR_AST(1) | \ + FTSMC020_TPR_CTW(1) | \ + FTSMC020_TPR_ATI(1) | \ + FTSMC020_TPR_AT2(1) | \ + FTSMC020_TPR_WTC(1) | \ + FTSMC020_TPR_AHT(1) | \ + FTSMC020_TPR_TRNA(1)) +#endif + +/* + * FLASH on ADP_AG101P is connected to BANK0 + * Just disalbe the other BANK to avoid detection error. + */ +#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define FTSMC020_BANK1_CONFIG (0x00) +#define FTSMC020_BANK1_TIMING (0x00) +#endif /* CONFIG_FTSMC020 */ + +/* + * FLASH and environment organization + */ +/* use CFI framework */ + +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL + +/* support JEDEC */ + +/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#define PHYS_FLASH_1 0x80000000 /* BANK 0 */ +#else +#ifdef CONFIG_MEM_REMAP +#define PHYS_FLASH_1 0x80000000 /* BANK 0 */ +#else +#define PHYS_FLASH_1 0x00000000 /* BANK 0 */ +#endif +#endif /* CONFIG_MEM_REMAP */ + +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ + +/* max number of memory banks */ +/* + * There are 4 banks supported for this Controller, + * but we have only 1 bank connected to flash on board + */ +#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#endif +#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} + +/* max number of sectors on one chip */ +#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +/* environments */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + +/* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) +/* Increase max gunzip size */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/alt.h b/roms/u-boot/include/configs/alt.h new file mode 100644 index 000000000..8456a6b2c --- /dev/null +++ b/roms/u-boot/include/configs/alt.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * include/configs/alt.h + * This file is alt board configuration. + * + * Copyright (C) 2014 Renesas Electronics Corporation + */ + +#ifndef __ALT_H +#define __ALT_H + +#include "rcar-gen2-common.h" + +#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 +#define STACK_AREA_SIZE 0x00100000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) + +/* FLASH */ +#define CONFIG_SPI_FLASH_QUAD + +/* SH Ether */ +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "usb_pgood_delay=2000\0" + +/* SPL support */ +#define CONFIG_SPL_STACK 0xe6340000 +#define CONFIG_SPL_MAX_SIZE 0x4000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIF2 +#define CONFIG_SH_SCIF_CLK_FREQ 65000000 +#endif + +#endif /* __ALT_H */ diff --git a/roms/u-boot/include/configs/am335x_evm.h b/roms/u-boot/include/configs/am335x_evm.h new file mode 100644 index 000000000..5af90d932 --- /dev/null +++ b/roms/u-boot/include/configs/am335x_evm.h @@ -0,0 +1,319 @@ +/* + * am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CONFIG_AM335X_EVM_H +#define __CONFIG_AM335X_EVM_H + +#include +#include + +#ifndef CONFIG_SPL_BUILD +# define CONFIG_TIMESTAMP +#endif + +#define CONFIG_SYS_BOOTM_LEN SZ_16M + +#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#ifdef CONFIG_MTD_RAW_NAND +#define NANDARGS \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ + "nand read ${loadaddr} NAND.kernel; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" +#else +#define NANDARGS "" +#endif + +#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv mmcdev " #instance"; "\ + "setenv bootpart " #instance":2 ; "\ + "run mmcboot\0" + +#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel "=" \ + "run nandboot\0" + +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#if CONFIG_IS_ENABLED(CMD_USB) +# define BOOT_TARGET_USB(func) func(USB, usb, 0) +#else +# define BOOT_TARGET_USB(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_PXE) +# define BOOT_TARGET_PXE(func) func(PXE, pxe, na) +#else +# define BOOT_TARGET_PXE(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_DHCP) +# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) +#else +# define BOOT_TARGET_DHCP(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(LEGACY_MMC, legacy_mmc, 0) \ + func(MMC, mmc, 1) \ + func(LEGACY_MMC, legacy_mmc, 1) \ + func(NAND, nand, 0) \ + BOOT_TARGET_USB(func) \ + BOOT_TARGET_PXE(func) \ + BOOT_TARGET_DHCP(func) + +#include + +#ifndef CONFIG_SPL_BUILD +#include +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + DEFAULT_FIT_TI_ARGS \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "fdtfile=undefined\0" \ + "console=ttyO0,115200n8\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=bootloader,start=384K,size=1792K," \ + "uuid=${uuid_gpt_bootloader};" \ + "name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs}\0" \ + "optargs=\0" \ + "ramroot=/dev/ram0 rw\0" \ + "ramrootfstype=ext2\0" \ + "spiroot=/dev/mtdblock4 rw\0" \ + "spirootfstype=jffs2\0" \ + "spisrcaddr=0xe0000\0" \ + "spiimgsize=0x362000\0" \ + "spibusno=0\0" \ + "spiargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${spiroot} " \ + "rootfstype=${spirootfstype}\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ + "spiboot=echo Booting from spi ...; " \ + "run spiargs; " \ + "sf probe ${spibusno}:0; " \ + "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \ + "bootz ${loadaddr}\0" \ + "ramboot=echo Booting from ramdisk ...; " \ + "run ramargs; " \ + "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ + "findfdt="\ + "if test $board_name = A335BONE; then " \ + "setenv fdtfile am335x-bone.dtb; fi; " \ + "if test $board_name = A335BNLT; then " \ + "setenv fdtfile am335x-boneblack.dtb; fi; " \ + "if test $board_name = A335PBGL; then " \ + "setenv fdtfile am335x-pocketbeagle.dtb; fi; " \ + "if test $board_name = BBBW; then " \ + "setenv fdtfile am335x-boneblack-wireless.dtb; fi; " \ + "if test $board_name = BBG1; then " \ + "setenv fdtfile am335x-bonegreen.dtb; fi; " \ + "if test $board_name = BBGW; then " \ + "setenv fdtfile am335x-bonegreen-wireless.dtb; fi; " \ + "if test $board_name = BBBL; then " \ + "setenv fdtfile am335x-boneblue.dtb; fi; " \ + "if test $board_name = BBEN; then " \ + "setenv fdtfile am335x-sancloud-bbe.dtb; fi; " \ + "if test $board_name = A33515BB; then " \ + "setenv fdtfile am335x-evm.dtb; fi; " \ + "if test $board_name = A335X_SK; then " \ + "setenv fdtfile am335x-evmsk.dtb; fi; " \ + "if test $board_name = A335_ICE; then " \ + "setenv fdtfile am335x-icev2.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree to use; fi; \0" \ + "init_console=" \ + "if test $board_name = A335_ICE; then "\ + "setenv console ttyO3,115200n8;" \ + "else " \ + "setenv console ttyO0,115200n8;" \ + "fi;\0" \ + NANDARGS \ + NETARGS \ + DFUARGS \ + BOOTENV +#endif + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ + +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* PMIC support */ +#define CONFIG_POWER_TPS65217 +#define CONFIG_POWER_TPS65910 + +/* SPL */ +#ifndef CONFIG_NOR_BOOT +/* Bootcount using the RTC block */ +#define CONFIG_SYS_BOOTCOUNT_BE + +/* USB gadget RNDIS */ +#endif + +#ifdef CONFIG_MTD_RAW_NAND +/* NAND: device related configs */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +/* NAND: driver related configs */ +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 +/* NAND: SPL related configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ +#endif +#endif /* !CONFIG_MTD_RAW_NAND */ + +/* + * For NOR boot, we must set this to the start of where NOR is mapped + * in memory. + */ + +/* + * USB configuration. We enable MUSB support, both for host and for + * gadget. We set USB0 as peripheral and USB1 as host, based on the + * board schematic and physical port wired to each. Then for host we + * add mass storage support and for gadget we add both RNDIS ethernet + * and DFU. + */ +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +/* + * Disable MMC DM for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_MMC +#undef CONFIG_TIMER +#endif + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER) +/* Remove other SPL modes. */ +/* disable host part of MUSB in SPL */ +/* disable EFI partitions and partition UUID support */ +#endif + +/* USB Device Firmware Update support */ +#ifndef CONFIG_SPL_BUILD +#define DFUARGS \ + DFU_ALT_INFO_EMMC \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_NAND +#endif + +/* + * Default to using SPI for environment, etc. + * 0x000000 - 0x020000 : SPL (128KiB) + * 0x020000 - 0x0A0000 : U-Boot (512KiB) + * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB) + * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB) + * 0x0E0000 - 0x442000 : Linux Kernel + * 0x442000 - 0x800000 : Userland + */ +#if defined(CONFIG_SPI_BOOT) +/* SPL related */ +#elif defined(CONFIG_EMMC_BOOT) +#define CONFIG_SYS_MMC_MAX_DEVICE 2 +#elif defined(CONFIG_ENV_IS_IN_NAND) +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#endif + +/* Network. */ +/* Enable Atheros phy driver */ + +/* + * NOR Size = 16 MiB + * Number of Sectors/Blocks = 128 + * Sector Size = 128 KiB + * Word length = 16 bits + * Default layout: + * 0x000000 - 0x07FFFF : U-Boot (512 KiB) + * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB) + * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB) + * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB) + * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB) + */ +#if defined(CONFIG_NOR) +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_SIZE 0x01000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#endif /* NOR support */ + +#ifdef CONFIG_DRIVER_TI_CPSW +#define CONFIG_CLOCK_SYNTHESIZER +#define CLK_SYNTHESIZER_I2C_ADDR 0x65 +#endif + +#endif /* ! __CONFIG_AM335X_EVM_H */ diff --git a/roms/u-boot/include/configs/am335x_guardian.h b/roms/u-boot/include/configs/am335x_guardian.h new file mode 100644 index 000000000..c34c07a49 --- /dev/null +++ b/roms/u-boot/include/configs/am335x_guardian.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * am335x_guardian_.h + * + * Copyright (C) 2018 Robert Bosch Power Tools GmbH + * Copyright (C) 2018 sjoerd Simons + * + */ + +#ifndef __CONFIG_AM335X_GUARDIAN_H +#define __CONFIG_AM335X_GUARDIAN_H + +#include + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_TIMESTAMP +#endif + +#define CONFIG_SYS_BOOTM_LEN (16 << 20) + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifndef CONFIG_SPL_BUILD + +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x80000000\0" \ + "pxefile_addr_r=0x80100000\0" \ + "kernel_addr_r=0x82000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x88080000\0" \ + +#define BOOT_TARGET_DEVICES(func) \ + func(UBIFS, ubifs, 0) + +#define AM335XX_BOARD_FDTFILE "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" + +#include + +#define GUARDIAN_DEFAULT_PROD_ENV \ + "factory_assembly_status=0\0" \ + "main_pcba_part_number=0\0" \ + "main_pcba_supplier=0\0" \ + "main_pcba_timestamp=0\0" \ + "main_pcba_hardware_version=0\0" \ + "main_pcba_id=0\0" \ + "main_pcba_aux_1=0\0" \ + "main_pcba_aux_2=0\0" \ + "main_pcba_aux_3=0\0" \ + "main_pcba_aux_4=0\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + AM335XX_BOARD_FDTFILE \ + MEM_LAYOUT_ENV_SETTINGS \ + BOOTENV \ + GUARDIAN_DEFAULT_PROD_ENV \ + "bootubivol=rootfs\0" \ + "distro_bootcmd=" \ + "setenv autoload no; " \ + "setenv rootflags \"bulk_read,chk_data_crc\"; " \ + "setenv ethact usb_ether; " \ + "if test \"${swi_status}\" -eq 1; then " \ + "setenv extrabootargs \"swi_attached\"; " \ + "if dhcp; then " \ + "sleep 1; " \ + "if tftp \"${tftp_load_addr}\" \"bootscript.scr\"; then " \ + "source \"${tftp_load_addr}\"; " \ + "fi; " \ + "fi; " \ + "fi;" \ + "run bootcmd_ubifs0;\0" \ + "altbootcmd=" \ + "setenv boot_syslinux_conf \"extlinux/extlinux-rollback.conf\"; " \ + "run distro_bootcmd; " \ + "setenv boot_syslinux_conf \"extlinux/extlinux.conf\"; " \ + "run bootcmd_ubifs0;\0" + +#endif /* ! CONFIG_SPL_BUILD */ + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ + +/* PMIC support */ +#define CONFIG_POWER_TPS65217 + +/* Bootcount using the RTC block */ +#define CONFIG_SYS_BOOTCOUNT_LE + +#ifdef CONFIG_MTD_RAW_NAND + +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 4096 +#define CONFIG_SYS_NAND_OOBSIZE 256 +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) + +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ + 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ + 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \ + 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ + 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \ + 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \ + 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ + 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \ + 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \ + 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \ + 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \ + 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \ + 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \ + 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \ + 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \ + 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \ + 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ + } +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 26 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW +#define MTDIDS_DEFAULT "nand0=nand.0" + +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + +#endif /* CONFIG_MTD_RAW_NAND */ + +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +#endif /* ! __CONFIG_AM335X_GUARDIAN_H */ diff --git a/roms/u-boot/include/configs/am335x_igep003x.h b/roms/u-boot/include/configs/am335x_igep003x.h new file mode 100644 index 000000000..95ba949b2 --- /dev/null +++ b/roms/u-boot/include/configs/am335x_igep003x.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CONFIG_IGEP003X_H +#define __CONFIG_IGEP003X_H + +#include + +/* Clock defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "console=ttyO0,115200n8\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \ + "load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run mmcload; then " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr};" \ + "fi;" \ + "fi;\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=1\0" \ + "nandrootfstype=ubifs rootwait\0" \ + "nandload=ubi part UBI; " \ + "ubi read ${loadaddr} kernel; " \ + "ubi read ${fdtaddr} dtb \0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype} \0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "run nandload; " \ + "bootz ${loadaddr} - ${fdtaddr} \0" \ + "netload=tftpboot ${loadaddr} ${bootfile}; " \ + "tftpboot ${fdtaddr} ${fdtfile} \0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "ip=${ipaddr} nfsroot=${serverip}:${rootnfs},v3,tcp \0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "run netload; " \ + "bootz ${loadaddr} - ${fdtaddr} \0" \ + "findfdt="\ + "if test ${board_name} = igep0033; then " \ + "setenv fdtfile am335x-igep-base0033.dtb; fi; " \ + "if test ${board_name} = igep0034; then " \ + "setenv fdtfile am335x-igep-base0040.dtb; fi; " \ + "if test ${board_name} = igep0034-lite; then " \ + "setenv fdtfile am335x-igep-base0040-lite.dtb; fi; " \ + "if test ${fdtfile} = ''; then " \ + "echo WARNING: Could not determine device tree to use; fi; \0" +#endif + +#define CONFIG_BOOTCOMMAND \ + "run findfdt;" \ + "run mmcboot;" \ + "run nandboot;" \ + "run netboot;" + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ + +/* Ethernet support */ + +/* NAND support */ +#define CONFIG_SYS_NAND_ONFI_DETECTION 1 + +/* NAND config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW + +#endif /* ! __CONFIG_IGEP003X_H */ diff --git a/roms/u-boot/include/configs/am335x_shc.h b/roms/u-boot/include/configs/am335x_shc.h new file mode 100644 index 000000000..387d50d51 --- /dev/null +++ b/roms/u-boot/include/configs/am335x_shc.h @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef __CONFIG_AM335X_SHC_H +#define __CONFIG_AM335X_SHC_H + +#include + +/* settings we don;t want on this board */ + +#ifndef CONFIG_SPL_BUILD +# define CONFIG_TIMESTAMP +#endif + +#define CONFIG_SYS_BOOTM_LEN (16 << 20) + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_HSMMC2_8BIT + +#ifndef CONFIG_SHC_ICT +/* + * In builds other than ICT, reset to retry after timeout + * Define a timeout after which a stopped bootloader continues autoboot + * (only works with CONFIG_RESET_TO_RETRY) + */ +# define CONFIG_BOOT_RETRY_TIME 30 +# define CONFIG_RESET_TO_RETRY +#endif + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "kloadaddr=0x84000000\0" \ + "fdtaddr=0x85000000\0" \ + "fdt_high=0xffffffff\0" \ + "rdaddr=0x81000000\0" \ + "bootfile=uImage\0" \ + "fdtfile=am335x-shc.dtb\0" \ + "verify=no\0" \ + "serverip=10.55.152.184\0" \ + "rootpath=/srv/nfs/shc-rootfs\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=quiet\0" \ + "mmcdev=1\0" \ + "harakiri=0\0" \ + "mmcpart=2\0" \ + "active_root=root1\0" \ + "inactive_root=root2\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "nfsopts=nolock\0" \ + "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ + "::off\0" \ + "ip_method=none\0" \ + "bootargs_defaults=setenv bootargs " \ + "console=${console} " \ + "${optargs}\0" \ + "mmcargs=run bootargs_defaults;" \ + "setenv bootargs ${bootargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype} ip=${ip_method}\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=if fatload mmc ${mmcdev} ${loadaddr} ${bootenv}; then " \ + "echo Loaded environment from ${bootenv}; " \ + "run importbootenv; " \ + "fi;\0" \ + "importbootenv=echo Importing environment variables from uEnv.txt ...; " \ + "env import -t $loadaddr $filesize\0" \ + "loaduimagefat=fatload mmc ${mmcdev} ${kloadaddr} ${bootfile}\0" \ + "loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${kloadaddr} /boot/${bootfile}\0" \ + "loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdtaddr} /boot/${fdtfile}\0" \ + "netloaduimage=tftp ${loadaddr} ${bootfile}\0" \ + "netloadfdt=tftp ${fdtaddr} ${fdtfile}\0" \ + "mmcboot=echo Booting Linux from ${mmcdevice} ...; " \ + "run mmcargs; " \ + "if run loadfdt; then " \ + "echo device tree detected; " \ + "bootm ${kloadaddr} - ${fdtaddr}; " \ + "else " \ + "bootm ${kloadaddr}; " \ + "fi; \0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "run netloaduimage; " \ + "run netargs; " \ + "echo NFS path: ${serverip}:${rootpath};" \ + "if run netloadfdt; then " \ + "echo device tree detected; " \ + "bootm ${loadaddr} - ${fdtaddr}; " \ + "else " \ + "bootm ${loadaddr}; " \ + "fi; \0" \ + "emmc_erase=if test ${harakiri} = 1 ; then echo erase emmc ...; setenv mmcdev 1; mmc erase 0 200; reset; fi; \0" \ + "mmcpart_gp=mmcpart gp 1 40; \0" \ + "mmcpart_enhance=mmcpart enhance 0 64; \0" \ + "mmcpart_rel_write=mmcpart rel_write 1f; \0" \ + "mmcpart_commit=mmcpart commit 1; \0" \ + "mmc_hw_part=run mmcpart_gp; run mmcpart_enhance; run mmcpart_rel_write; run mmcpart_commit; \0" \ + "led_success=gpio set 22; \0" \ + "fusecmd=mmc dev 1; if mmcpart iscommitted; then echo HW Partitioning already committed; mmcpart list; else run mmc_hw_part; fi; run led_success; \0" \ + "uenv_exec=if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi;\0" \ + "sd_setup=echo SD/MMC-Card detected on device 0; " \ + "setenv mmcdevice SD; " \ + "setenv mmcdev 0; " \ + "setenv mmcpart 2; " \ + "setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0" \ + "emmc_setup=echo eMMC detected on device 1; " \ + "setenv mmcdevice eMMC; " \ + "setenv mmcdev 1; " \ + "run emmc_erase; " \ + "if test ${active_root} = root2; then " \ + "echo Active root is partition 6 (root2); " \ + "setenv mmcpart 6; " \ + "else " \ + "echo Active root is partition 5 (root1); " \ + "setenv mmcpart 5; " \ + "fi; " \ + "setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0" +#endif /* #ifndef CONFIG_SPL_BUILD */ + +#if defined CONFIG_SHC_NETBOOT +/* Network Boot */ +# define CONFIG_BOOTCOMMAND \ + "run fusecmd; " \ + "if run netboot; then " \ + "echo Booting from network; " \ + "else " \ + "echo ERROR: Cannot boot from network!; " \ + "panic; " \ + "fi; " + +#elif defined CONFIG_SHC_SDBOOT /* !defined CONFIG_SHC_NETBOOT */ +/* SD-Card Boot */ +# define CONFIG_BOOTCOMMAND \ + "if mmc dev 0; mmc rescan; then " \ + "run sd_setup; " \ + "else " \ + "echo ERROR: SD/MMC-Card not detected!; " \ + "panic; " \ + "fi; " \ + "if run loaduimage; then " \ + "echo Bootable SD/MMC-Card inserted, booting from it!; " \ + "run mmcboot; " \ + "else " \ + "echo ERROR: Unable to load uImage from SD/MMC-Card!; " \ + "panic; " \ + "fi; " + +#elif defined CONFIG_SHC_ICT +/* ICT adapter boots only u-boot and does HW partitioning */ +# define CONFIG_BOOTCOMMAND \ + "if mmc dev 0; mmc rescan; then " \ + "run sd_setup; " \ + "else " \ + "echo ERROR: SD/MMC-Card not detected!; " \ + "panic; " \ + "fi; " \ + "run fusecmd; " + +#else /* !defined CONFIG_SHC_NETBOOT, !defined CONFIG_SHC_SDBOOT */ +/* Regular Boot from internal eMMC */ +# define CONFIG_BOOTCOMMAND \ + "if mmc dev 1; mmc rescan; then " \ + "run emmc_setup; " \ + "else " \ + "echo ERROR: eMMC device not detected!; " \ + "panic; " \ + "fi; " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else " \ + "echo ERROR Unable to load uImage from eMMC!; " \ + "echo Performing Rollback!; " \ + "setenv _active_ ${active_root}; " \ + "setenv _inactive_ ${inactive_root}; " \ + "setenv active_root ${_inactive_}; " \ + "setenv inactive_root ${_active_}; " \ + "saveenv; " \ + "reset; " \ + "fi; " + +#endif /* Regular Boot */ + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ + +/* PMIC support */ +#define CONFIG_POWER_TPS65217 + +/* SPL */ + +/* + * Disable MMC DM for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_MMC +#undef CONFIG_TIMER +#endif + +#define CONFIG_NET_RETRY_COUNT 10 + +/* I2C configuration */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 1 +#endif /* ! __CONFIG_AM335X_SHC_H */ diff --git a/roms/u-boot/include/configs/am335x_sl50.h b/roms/u-boot/include/configs/am335x_sl50.h new file mode 100644 index 000000000..16849d870 --- /dev/null +++ b/roms/u-boot/include/configs/am335x_sl50.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * am335x_sl50.h + * + * Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/ + */ + +#ifndef __CONFIG_AM335X_EVM_H +#define __CONFIG_AM335X_EVM_H + +#include + +#ifndef CONFIG_SPL_BUILD +# define CONFIG_TIMESTAMP +#endif + +#define CONFIG_SYS_BOOTM_LEN (16 << 20) + +/*#define CONFIG_MACH_TYPE 3589 Until the next sync */ + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#ifndef CONFIG_SPL_BUILD + +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x80000000\0" \ + "pxefile_addr_r=0x80100000\0" \ + "kernel_addr_r=0x82000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x88080000\0" \ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#define AM335XX_BOARD_FDTFILE \ + "fdtfile=am335x-sl50.dtb\0" \ + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + AM335XX_BOARD_FDTFILE \ + MEM_LAYOUT_ENV_SETTINGS \ + BOOTENV + +#endif + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ + +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* PMIC support */ +#define CONFIG_POWER_TPS65217 +#define CONFIG_POWER_TPS65910 + +/* SPL */ + +/* Bootcount using the RTC block */ +#define CONFIG_SYS_BOOTCOUNT_BE + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER) +/* Remove other SPL modes. */ +/* disable host part of MUSB in SPL */ +#undef CONFIG_MUSB_HOST +/* disable EFI partitions and partition UUID support */ +#endif + +/* Network. */ + +#endif /* ! __CONFIG_AM335X_SL50_H */ diff --git a/roms/u-boot/include/configs/am3517_evm.h b/roms/u-boot/include/configs/am3517_evm.h new file mode 100644 index 000000000..a9c14a1ce --- /dev/null +++ b/roms/u-boot/include/configs/am3517_evm.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * am3517_evm.h - Default configuration for AM3517 EVM board. + * + * Author: Vaibhav Hiremath + * + * Based on omap3_evm_config.h + * + * Copyright (C) 2010 Texas Instruments Incorporated + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_REVISION_TAG + +/* Hardware drivers */ + +/* + * USB configuration + * Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard + * Enable CONFIG_USB_MUSB_GADGET for Device functionalities. + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_USB_EHCI_OMAP +#else +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 +#endif + +/* I2C */ + +/* Ethernet */ +#define CONFIG_NET_RETRY_COUNT 10 + +/* Board NAND Info. */ +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \ + 11, 12, 13, 14, 16, 17, 18, 19, 20, \ + 21, 22, 23, 24, 25, 26, 27, 28, 30, \ + 31, 32, 33, 34, 35, 36, 37, 38, 39, \ + 40, 41, 42, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56 } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 13 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000 +/* NAND block size is 128 KiB. Synchronize these values with + * corresponding Device Tree entries in Linux: + * MLO(SPL) 4 * NAND_BLOCK_SIZE = 512 KiB @ 0x000000 + * U-Boot 15 * NAND_BLOCK_SIZE = 1920 KiB @ 0x080000 + * U-Boot environment 2 * NAND_BLOCK_SIZE = 256 KiB @ 0x260000 + * Kernel 64 * NAND_BLOCK_SIZE = 8 MiB @ 0x2A0000 + * DTB 4 * NAND_BLOCK_SIZE = 512 KiB @ 0xAA0000 + * RootFS Remaining Flash Space @ 0xB20000 + */ +#endif /* CONFIG_MTD_RAW_NAND */ + +/* Environment information */ + +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyS2,115200n8\0" \ + "fdtfile=am3517-evm.dtb\0" \ + "fdtaddr=0x82C00000\0" \ + "vram=16M\0" \ + "bootenv=uEnv.txt\0" \ + "cmdline=\0" \ + "optargs=\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext4 rootwait fixrtc\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${mtdparts} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype} " \ + "${cmdline}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${mtdparts} " \ + "${optargs} " \ + "root=ubi0:rootfs rw ubi.mtd=rootfs " \ + "rootfstype=ubifs rootwait " \ + "${cmdline}\0" \ + "loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootenv}\0"\ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootfile}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${fdtfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 2a0000 800000; " \ + "nand read ${fdtaddr} aa0000 80000; " \ + "bootm ${loadaddr} - ${fdtaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "echo SD/MMC found on device $mmcdev; " \ + "if run loadbootenv; then " \ + "run importbootenv; " \ + "fi; " \ + "echo Checking if uenvcmd is set ...; " \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi; " \ + "echo Running default loadimage ...; " \ + "setenv bootfile zImage; " \ + "if run loadimage; then " \ + "run loadfdt; " \ + "run mmcboot; " \ + "fi; " \ + "else run nandboot; fi" + +/* Miscellaneous configurable options */ + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 64 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* memtest works on */ + +/* Physical Memory Map */ +#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) + +/* FLASH and environment organization */ + +/* **** PISMO SUPPORT *** */ +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ + /* on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#if defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_FLASH_BASE NAND_BASE +#endif + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ + +/* Defines for SPL */ + +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/am43xx_evm.h b/roms/u-boot/include/configs/am43xx_evm.h new file mode 100644 index 000000000..6df6b49c8 --- /dev/null +++ b/roms/u-boot/include/configs/am43xx_evm.h @@ -0,0 +1,270 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * am43xx_evm.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef __CONFIG_AM43XX_EVM_H +#define __CONFIG_AM43XX_EVM_H + +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ + +#include + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_CLK 48000000 +#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_SERIAL +#endif + +/* I2C Configuration */ +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* Power */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#endif +#define CONFIG_POWER_TPS65218 +#define CONFIG_POWER_TPS62362 + +/* SPL defines. */ +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (128 << 20)) + +/* Enabling L2 Cache */ +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x48242000 + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_QSPI_BOOT) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * When building U-Boot such that there is no previous loader + * we need to call board_early_init_f. This is taken care of in + * s_init when we have SPL used. + */ + +/* Now bring in the rest of the common code. */ +#include + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ + +/* SPL USB Support */ + +#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD) +#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 +#define CONFIG_USB_XHCI_OMAP + +#define CONFIG_AM437X_USB2PHY2_HOST +#endif + +#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USB_ETHER) +#undef CONFIG_USB_DWC3_PHY_OMAP +#undef CONFIG_USB_DWC3_OMAP +#undef CONFIG_USB_DWC3 +#undef CONFIG_USB_DWC3_GADGET + +#undef CONFIG_USB_GADGET_DOWNLOAD +#undef CONFIG_USB_GADGET_VBUS_DRAW +#undef CONFIG_USB_GADGET_MANUFACTURER +#undef CONFIG_USB_GADGET_VENDOR_NUM +#undef CONFIG_USB_GADGET_PRODUCT_NUM +#undef CONFIG_USB_GADGET_DUALSPEED +#endif + +/* + * Disable MMC DM for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_TIMER +#endif + +#ifndef CONFIG_SPL_BUILD +/* USB Device Firmware Update support */ +#define DFUARGS \ + "dfu_bufsiz=0x10000\0" \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_EMMC \ + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_QSPI_XIP +#else +#define DFUARGS +#endif + +#ifndef CONFIG_SPL_BUILD +#include +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + DEFAULT_FIT_TI_ARGS \ + "fdtfile=undefined\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "console=ttyO0,115200n8\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ + "optargs=\0" \ + "usbroot=/dev/sda2 rw\0" \ + "usbrootfstype=ext4 rootwait\0" \ + "usbdev=0\0" \ + "ramroot=/dev/ram0 rw\0" \ + "ramrootfstype=ext2\0" \ + "usbargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${usbroot} " \ + "rootfstype=${usbrootfstype}\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \ + "usbboot=" \ + "setenv devnum ${usbdev}; " \ + "setenv devtype usb; " \ + "usb start ${usbdev}; " \ + "if usb dev ${usbdev}; then " \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt; " \ + "echo Booting from usb ${usbdev}...; " \ + "run usbargs;" \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "fi;" \ + "fi\0" \ + "fi;" \ + "usb stop ${usbdev};\0" \ + "findfdt="\ + "if test $board_name = AM43EPOS; then " \ + "setenv fdtfile am43x-epos-evm.dtb; fi; " \ + "if test $board_name = AM43__GP; then " \ + "setenv fdtfile am437x-gp-evm.dtb; fi; " \ + "if test $board_name = AM43XXHS; then " \ + "setenv fdtfile am437x-gp-evm.dtb; fi; " \ + "if test $board_name = AM43__SK; then " \ + "setenv fdtfile am437x-sk-evm.dtb; fi; " \ + "if test $board_name = AM43_IDK; then " \ + "setenv fdtfile am437x-idk-evm.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree; fi; \0" \ + NANDARGS \ + NETARGS \ + DFUARGS \ + +#define CONFIG_BOOTCOMMAND \ + "if test ${boot_fit} -eq 1; then " \ + "run update_to_fit;" \ + "fi;" \ + "run findfdt; " \ + "run envboot;" \ + "run mmcboot;" \ + "run usbboot;" \ + NANDBOOT \ + +#endif + +#ifndef CONFIG_SPL_BUILD +/* CPSW Ethernet */ +#define CONFIG_NET_RETRY_COUNT 10 +#endif + +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ + +#define CONFIG_SYS_RX_ETH_BUFFER 64 + +/* NAND support */ +#ifdef CONFIG_MTD_RAW_NAND +/* NAND: device related configs */ +#define CONFIG_SYS_NAND_PAGE_SIZE 4096 +#define CONFIG_SYS_NAND_OOBSIZE 224 +#define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +/* NAND: driver related configs */ +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ + 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ + 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \ + 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ + 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \ + 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \ + 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ + 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \ + 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \ + 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \ + 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \ + 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \ + 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \ + 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \ + 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \ + 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \ + 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ + } +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 26 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000 +/* NAND: SPL related configs */ +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */ +#endif +#define NANDARGS \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ + "nand read ${loadaddr} NAND.kernel; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" +#define NANDBOOT "run nandboot; " +#else /* !CONFIG_MTD_RAW_NAND */ +#define NANDARGS +#define NANDBOOT +#endif /* CONFIG_MTD_RAW_NAND */ + +#if defined(CONFIG_TI_SECURE_DEVICE) +/* Avoid relocating onto firewalled area at end of DRAM */ +#define CONFIG_PRAM (64 * 1024) +#endif /* CONFIG_TI_SECURE_DEVICE */ + +#endif /* __CONFIG_AM43XX_EVM_H */ diff --git a/roms/u-boot/include/configs/am57xx_evm.h b/roms/u-boot/include/configs/am57xx_evm.h new file mode 100644 index 000000000..c47ffccff --- /dev/null +++ b/roms/u-boot/include/configs/am57xx_evm.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 + * Texas Instruments Incorporated. + * Felipe Balbi + * + * Configuration settings for the TI Beagle x15 board. + * See ti_omap5_common.h for omap5 common settings. + */ + +#ifndef __CONFIG_AM57XX_EVM_H +#define __CONFIG_AM57XX_EVM_H + +#include +#include + +#define CONFIG_IODELAY_RECALIBRATION + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ + +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +#define CONFIG_SYS_OMAP_ABE_SYSCK + +#ifndef CONFIG_SPL_BUILD +#define DFUARGS \ + "dfu_bufsiz=0x10000\0" \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_EMMC \ + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_QSPI +#else +#ifdef CONFIG_SPL_DFU +#define DFUARGS \ + "dfu_bufsiz=0x10000\0" \ + DFU_ALT_INFO_RAM +#endif +#endif + +#include + +/* Enhance our eMMC support / experience. */ +#define CONFIG_HSMMC2_8BIT + +/* CPSW Ethernet */ +#define CONFIG_NET_RETRY_COUNT 10 +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ + +/* USB xHCI HOST */ +#define CONFIG_USB_XHCI_OMAP + +#define CONFIG_OMAP_USB3PHY1_HOST + +/* SATA */ +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +/* + * Default to using SPI for environment, etc. + * 0x000000 - 0x040000 : QSPI.SPL (256KiB) + * 0x040000 - 0x140000 : QSPI.u-boot (1MiB) + * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB) + * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB) + * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB) + * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) + * 0x9E0000 - 0x2000000 : USERLAND + */ +#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 +#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 +#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 + +/* SPI SPL */ + +#endif /* __CONFIG_AM57XX_EVM_H */ diff --git a/roms/u-boot/include/configs/am64x_evm.h b/roms/u-boot/include/configs/am64x_evm.h new file mode 100644 index 000000000..7c30e50c5 --- /dev/null +++ b/roms/u-boot/include/configs/am64x_evm.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for K3 AM642 SoC family + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Keerthy + */ + +#ifndef __CONFIG_AM642_EVM_H +#define __CONFIG_AM642_EVM_H + +#include +#include +#include + +/* DDR Configuration */ +#define CONFIG_SYS_SDRAM_BASE1 0x880000000 + +#ifdef CONFIG_SYS_K3_SPL_ATF +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" +#endif + +#ifndef CONFIG_CPU_V7R +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE +#if defined(CONFIG_TARGET_AM642_A53_EVM) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ + CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE - 4) +#else +/* + * Maximum size in memory allocated to the SPL BSS. Keep it as tight as + * possible (to allow the build to go through), as this directly affects + * our memory footprint. The less we use for BSS the more we have available + * for everything else. + */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 +/* + * Link BSS to be within SPL in a dedicated region located near the top of + * the MCU SRAM, this way making it available also before relocation. Note + * that we are not using the actual top of the MCU SRAM as there is a memory + * location filled in by the boot ROM that we want to read out without any + * interference from the C context. + */ +#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ + CONFIG_SPL_BSS_MAX_SIZE) +/* Set the stack right below the SPL BSS section */ +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR +/* Configure R5 SPL post-relocation malloc pool in DDR */ +#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M +#endif + +#define PARTS_DEFAULT \ + /* Linux partitions */ \ + "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" + +/* U-Boot general configuration */ +#define EXTRA_ENV_AM642_BOARD_SETTINGS \ + "findfdt=" \ + "if test $board_name = am64x_gpevm; then " \ + "setenv fdtfile k3-am642-evm.dtb; fi; " \ + "if test $board_name = am64x_skevm; then " \ + "setenv fdtfile k3-am642-sk.dtb; fi;" \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree to use; fi; \0" \ + "name_kern=Image\0" \ + "console=ttyS2,115200n8\0" \ + "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 " \ + "${mtdparts}\0" \ + "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" + +/* U-Boot MMC-specific configuration */ +#define EXTRA_ENV_AM642_BOARD_SETTINGS_MMC \ + "boot=mmc\0" \ + "mmcdev=1\0" \ + "bootpart=1:2\0" \ + "bootdir=/boot\0" \ + "rd_spec=-\0" \ + "init_mmc=run args_all args_mmc\0" \ + "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "get_overlay_mmc=" \ + "fdt address ${fdtaddr};" \ + "fdt resize 0x100000;" \ + "for overlay in $name_overlays;" \ + "do;" \ + "load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \ + "fdt apply ${dtboaddr};" \ + "done;\0" \ + "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ + "${bootdir}/${name_kern}\0" \ + "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \ + "${bootdir}/${name_fit}\0" \ + "partitions=" PARTS_DEFAULT + +/* Incorporate settings into the U-Boot environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + EXTRA_ENV_AM642_BOARD_SETTINGS \ + EXTRA_ENV_AM642_BOARD_SETTINGS_MMC + +/* Now for the remaining common defines */ +#include + +/* MMC ENV related defines */ +#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 1 +#endif + +#endif /* __CONFIG_AM642_EVM_H */ diff --git a/roms/u-boot/include/configs/am65x_evm.h b/roms/u-boot/include/configs/am65x_evm.h new file mode 100644 index 000000000..76d73086f --- /dev/null +++ b/roms/u-boot/include/configs/am65x_evm.h @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for K3 AM654 EVM + * + * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla + */ + +#ifndef __CONFIG_AM654_EVM_H +#define __CONFIG_AM654_EVM_H + +#include +#include +#include +#include +#include + +/* DDR Configuration */ +#define CONFIG_SYS_SDRAM_BASE1 0x880000000 + +/* SPL Loader Configuration */ +#ifdef CONFIG_TARGET_AM654_A53_EVM +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ + CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) +#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x20000 +#else +/* + * Maximum size in memory allocated to the SPL BSS. Keep it as tight as + * possible (to allow the build to go through), as this directly affects + * our memory footprint. The less we use for BSS the more we have available + * for everything else. + */ +#define CONFIG_SPL_BSS_MAX_SIZE 0xc00 +/* + * Link BSS to be within SPL in a dedicated region located near the top of + * the MCU SRAM, this way making it available also before relocation. Note + * that we are not using the actual top of the MCU SRAM as there is a memory + * location filled in by the boot ROM that we want to read out without any + * interference from the C context. + */ +#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ + CONFIG_SPL_BSS_MAX_SIZE) +/* Set the stack right below the SPL BSS section */ +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR +/* Configure R5 SPL post-relocation malloc pool in DDR */ +#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M +#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x5000 +#endif + +#ifdef CONFIG_SYS_K3_SPL_ATF +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" +#endif + +#ifndef CONFIG_CPU_V7R +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * If the maximum size is not declared then it is defined as + * CONFIG_SYS_DFU_DATA_BUF_SIZE. + */ +#define CONFIG_SYS_DFU_MAX_FILE_SIZE (1024 * 1024 * 8) /* 8 MiB */ + +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +#define PARTS_DEFAULT \ + /* Linux partitions */ \ + "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" + +/* U-Boot general configuration */ +#define EXTRA_ENV_AM65X_BOARD_SETTINGS \ + "findfdt=" \ + "setenv name_fdt k3-am654-base-board.dtb;" \ + "setenv fdtfile ${name_fdt}\0" \ + "name_kern=Image\0" \ + "console=ttyS2,115200n8\0" \ + "stdin=serial,usbkbd\0" \ + "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 " \ + "${mtdparts}\0" \ + "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" \ + +/* U-Boot MMC-specific configuration */ +#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC \ + "boot=mmc\0" \ + "mmcdev=1\0" \ + "bootpart=1:2\0" \ + "bootdir=/boot\0" \ + "rd_spec=-\0" \ + "init_mmc=run args_all args_mmc\0" \ + "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \ + "get_overlay_mmc=" \ + "fdt address ${fdtaddr};" \ + "fdt resize 0x100000;" \ + "for overlay in $name_overlays;" \ + "do;" \ + "load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay};" \ + "fdt apply ${dtboaddr};" \ + "done;\0" \ + "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ + "${bootdir}/${name_kern}\0" \ + "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \ + "${bootdir}/${name_fit}\0" \ + "partitions=" PARTS_DEFAULT + +#ifdef DEFAULT_RPROCS +#undef DEFAULT_RPROCS +#endif +#define DEFAULT_RPROCS "" \ + "0 /lib/firmware/am65x-mcu-r5f0_0-fw " \ + "1 /lib/firmware/am65x-mcu-r5f0_1-fw " + +#ifdef CONFIG_TARGET_AM654_A53_EVM +#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MTD \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" +#else +#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MTD +#endif + +#define EXTRA_ENV_AM65X_BOARD_SETTINGS_UBI \ + "init_ubi=run args_all args_ubi; sf probe; " \ + "ubi part ospi.rootfs; ubifsmount ubi:rootfs;\0" \ + "get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0" \ + "get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt}\0" \ + "args_ubi=setenv bootargs console=${console} ${optargs} " \ + "rootfstype=ubifs root=ubi0:rootfs rw ubi.mtd=ospi.rootfs\0" + +#define EXTRA_ENV_DFUARGS \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_EMMC \ + DFU_ALT_INFO_OSPI + +/* Incorporate settings into the U-Boot environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + DEFAULT_FIT_TI_ARGS \ + EXTRA_ENV_AM65X_BOARD_SETTINGS \ + EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC \ + EXTRA_ENV_AM65X_BOARD_SETTINGS_MTD \ + EXTRA_ENV_AM65X_BOARD_SETTINGS_UBI \ + EXTRA_ENV_RPROC_SETTINGS \ + EXTRA_ENV_DFUARGS + +#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 + +/* Now for the remaining common defines */ +#include + +#endif /* __CONFIG_AM654_EVM_H */ diff --git a/roms/u-boot/include/configs/amcore.h b/roms/u-boot/include/configs/amcore.h new file mode 100644 index 000000000..641d8fdbd --- /dev/null +++ b/roms/u-boot/include/configs/amcore.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Sysam AMCORE board configuration + * + * (C) Copyright 2016 Angelo Dureghello + */ + +#ifndef __AMCORE_CONFIG_H +#define __AMCORE_CONFIG_H + +#define CONFIG_HOSTNAME "AMCORE" + +#define CONFIG_MCFTMR +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT 0 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_BOOTCOMMAND "bootm ffc20000" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "upgrade_uboot=loady; " \ + "protect off 0xffc00000 0xffc1ffff; " \ + "erase 0xffc00000 0xffc1ffff; " \ + "cp.b 0x20000 0xffc00000 ${filesize}\0" \ + "upgrade_kernel=loady; " \ + "erase 0xffc20000 0xffefffff; " \ + "cp.b 0x20000 0xffc20000 ${filesize}\0" \ + "upgrade_jffs2=loady; " \ + "erase 0xfff00000 0xffffffff; " \ + "cp.b 0x20000 0xfff00000 ${filesize}\0" + +/* undef to save memory */ + +#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_SYS_CLK 45000000 +#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) +/* Register Base Addrs */ +#define CONFIG_SYS_MBAR 0x10000000 +/* Definitions for initial stack pointer and data area (in DPRAM) */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 +/* size of internal SRAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_SIZE 0x1000000 +#define CONFIG_SYS_FLASH_BASE 0xffc00000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 + +/* amcore design has flash data bytes wired swapped */ +#define CONFIG_SYS_WRITE_SWAPPED_DATA +/* reserve 128-4KB */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) + +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + env/embedded.o(.text*); + +/* memory map space for linux boot data */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Cache Configuration + * + * Special 8K version 3 core cache. + * This is a single unified instruction/data cache. + * sdram - single region - no masks + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ + CF_ACR_EN) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ + CF_CACR_EC) + +/* CS0 - AMD Flash, address 0xffc00000 */ +#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) +/* 4MB, AA=0,V=1 C/I BIT for errata */ +#define CONFIG_SYS_CS0_MASK 0x003f0001 +/* WS=10, AA=1, PS=16bit (10) */ +#define CONFIG_SYS_CS0_CTRL 0x1980 +/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ +#define CONFIG_SYS_CS1_BASE 0x3000 +#define CONFIG_SYS_CS1_MASK 0x00070001 +#define CONFIG_SYS_CS1_CTRL 0x0100 + +#endif /* __AMCORE_CONFIG_H */ + diff --git a/roms/u-boot/include/configs/ap121.h b/roms/u-boot/include/configs/ap121.h new file mode 100644 index 000000000..4902d0724 --- /dev/null +++ b/roms/u-boot/include/configs/ap121.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015-2016 Wills Wang + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 200 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN 0x40000 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR 0x81000000 + +#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {9600, 19200, 38400, 57600, 115200} + +#define CONFIG_BOOTCOMMAND "sf probe;" \ + "mtdparts default;" \ + "bootm 0x9f650000" + +/* Miscellaneous configurable options */ + +/* + * Diagnostics + */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/ap143.h b/roms/u-boot/include/configs/ap143.h new file mode 100644 index 000000000..c79e050dc --- /dev/null +++ b/roms/u-boot/include/configs/ap143.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015-2016 Wills Wang + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 325 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN 0x40000 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR 0x81000000 + +#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_CLK 25000000 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {9600, 19200, 38400, 57600, 115200} + +#define CONFIG_BOOTCOMMAND "sf probe;" \ + "mtdparts default;" \ + "bootm 0x9f680000" + +/* Miscellaneous configurable options */ + +/* + * Diagnostics + */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/ap152.h b/roms/u-boot/include/configs/ap152.h new file mode 100644 index 000000000..0d2c484bb --- /dev/null +++ b/roms/u-boot/include/configs/ap152.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Rosy Song + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 375 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN 0x40000 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR 0x81000000 + +#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_CLK 25000000 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {9600, 19200, 38400, 57600, 115200} + +#define CONFIG_BOOTCOMMAND "sf probe;" \ + "mtdparts default;" \ + "bootm 0x9f060000" + +#define CONFIG_ENV_SPI_MAX_HZ 25000000 + +/* Miscellaneous configurable options */ + +/* + * Diagnostics + */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/apalis-imx8.h b/roms/u-boot/include/configs/apalis-imx8.h new file mode 100644 index 000000000..8fe3226cf --- /dev/null +++ b/roms/u-boot/include/configs/apalis-imx8.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Toradex + */ + +#ifndef __APALIS_IMX8_H +#define __APALIS_IMX8_H + +#include +#include + +#define CONFIG_REMAKE_ELF + +#define CONFIG_DISPLAY_BOARDINFO_LATE + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5b010000 +#define USDHC2_BASE_ADDR 0x5b020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* Networking */ +#define CONFIG_TFTP_TSIZE + +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1 + +#define MEM_LAYOUT_ENV_SETTINGS \ + "fdt_addr_r=0x84000000\0" \ + "kernel_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x94400000\0" \ + "scriptaddr=0x87000000\0" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) +#include +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + MEM_LAYOUT_ENV_SETTINGS \ + "console=ttyLP1 earlycon\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_file=fsl-imx8qm-apalis-eval.dtb\0" \ + "fdtfile=fsl-imx8qm-apalis-eval.dtb\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "image=Image\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=PARTUUID=${uuid} rootwait " \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \ + "\0" \ + "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ + "apalis-imx8/${fdt_file}; booti ${loadaddr} - ${fdt_addr}\0" \ + "panel=NULL\0" \ + "script=boot.scr\0" \ + "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ + "if test \"$confirm\" = \"y\"; then " \ + "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ + "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ + "${blkcnt}; fi\0" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */ +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ +#define PHYS_SDRAM_2_SIZE SZ_2G /* 2 GB */ + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE SZ_2K +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#endif /* __APALIS_IMX8_H */ diff --git a/roms/u-boot/include/configs/apalis-imx8x.h b/roms/u-boot/include/configs/apalis-imx8x.h new file mode 100644 index 000000000..fdb0da34e --- /dev/null +++ b/roms/u-boot/include/configs/apalis-imx8x.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Toradex + */ + +#ifndef __APALIS_IMX8X_H +#define __APALIS_IMX8X_H + +#include +#include +#include + +#define CONFIG_REMAKE_ELF + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5b010000 +#define USDHC2_BASE_ADDR 0x5b020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_TFTP_TSIZE + +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1 + +#define MEM_LAYOUT_ENV_SETTINGS \ + "kernel_addr_r=0x80280000\0" \ + "fdt_addr_r=0x83100000\0" \ + "ramdisk_addr_r=0x8a000000\0" \ + "scriptaddr=0x83200000\0" + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#define MFG_NAND_PARTITION "" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) +#include +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs ${consoleargs} " \ + "rdinit=/linuxrc g_mass_storage.stall=0 " \ + "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \ + "g_mass_storage.idProduct=0x37FF " \ + "g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \ + "${vidargs} clk_ignore_unused\0" \ + "initrd_addr=0x83800000\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \ + "${fdt_addr};\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + AHAB_ENV \ + BOOTENV \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + MEM_LAYOUT_ENV_SETTINGS \ + "boot_file=Image\0" \ + "consoleargs=console=ttyLP3,${baudrate} earlycon\0" \ + "fdt_file=imx8qxp-apalis-eval.dtb\0" \ + "fdtfile=imx8qxp-apalis-eval.dtb\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "image=Image\0" \ + "initrd_addr=0x83800000\0" \ + "mmcargs=setenv bootargs ${consoleargs} " \ + "root=PARTUUID=${uuid} rootwait " \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "netargs=setenv bootargs ${consoleargs} " \ + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \ + "${vidargs}\0" \ + "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ + "apalis-imx8x/${fdt_file}; booti ${loadaddr} - " \ + "${fdt_addr}\0" \ + "panel=NULL\0" \ + "script=boot.scr\0" \ + "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ + "if test \"$confirm\" = \"y\"; then " \ + "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ + "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ + "${blkcnt}; fi\0" \ + "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x89000000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Environment in eMMC, before config block at the end of 1st "boot sector" */ + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On Apalis iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE SZ_2K +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* Networking */ +#define CONFIG_FEC_ENET_DEV 0 +#define IMX_FEC_BASE 0x5b040000 +#define CONFIG_FEC_MXC_PHYADDR 0x4 +#define CONFIG_ETHPRIME "eth0" +#define CONFIG_FEC_XCV_TYPE RGMII +#define PHY_ANEG_TIMEOUT 20000 + +#endif /* __APALIS_IMX8X_H */ diff --git a/roms/u-boot/include/configs/apalis-tk1.h b/roms/u-boot/include/configs/apalis-tk1.h new file mode 100644 index 000000000..981f856ef --- /dev/null +++ b/roms/u-boot/include/configs/apalis-tk1.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2017 Toradex, Inc. + * + * Configuration settings for the Toradex Apalis TK1 modules. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra124-common.h" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define FDT_MODULE "apalis-v1.2" +#define FDT_MODULE_V1_0 "apalis" + +/* PCI host support */ +#undef CONFIG_PCI_SCAN_SHOW + +/* PCI networking support */ +#define CONFIG_E1000_NO_NVM + +/* General networking support */ +#define CONFIG_TFTP_TSIZE + +/* + * Custom Distro Boot configuration: + * 1. 8bit SD port (MMC1) + * 2. 4bit SD port (MMC2) + * 3. eMMC (MMC0) + */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#undef CONFIG_IPADDR +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#undef CONFIG_SERVERIP +#define CONFIG_SERVERIP 192.168.10.1 + +#define DFU_ALT_EMMC_INFO "apalis-tk1.img raw 0x0 0x500 mmcpart 1; " \ + "boot part 0 1 mmcpart 0; " \ + "rootfs part 0 2 mmcpart 0; " \ + "zImage fat 0 1 mmcpart 0; " \ + "tegra124-apalis-eval.dtb fat 0 1 mmcpart 0" + +#define UBOOT_UPDATE \ + "uboot_hwpart=1\0" \ + "uboot_blk=0\0" \ + "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \ + "setexpr blkcnt ${blkcnt} / 0x200\0" \ + "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ + "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ + +#define NFS_BOOTCMD \ + "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ + "nfsboot=pci enum; run setup; setenv bootargs ${defargs} ${nfsargs} " \ + "${setupargs} ${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ + "run nfsdtbload; dhcp ${kernel_addr_r} " \ + "&& run fdt_fixup && bootz ${kernel_addr_r} - ${dtbparam}\0" \ + "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} " \ + "${soc}-${fdt_module}-${fdt_board}.dtb " \ + "&& setenv dtbparam ${fdt_addr_r}\0" + +#define BOARD_EXTRA_ENV_SETTINGS \ + "boot_file=zImage\0" \ + "console=ttyS0\0" \ + "defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \ + "usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 " \ + "user_debug=30 pcie_aspm=off\0" \ + "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ + "fdt_board=eval\0" \ + "fdt_fixup=;\0" \ + "fdt_module=" FDT_MODULE "\0" \ + NFS_BOOTCMD \ + UBOOT_UPDATE \ + "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ + "00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \ + "flash_eth.img && source ${loadaddr}\0" \ + "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; " \ + "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img " \ + "|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1 " \ + "${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "setup=setenv setupargs igb_mac=${ethaddr} " \ + "consoleblank=0 no_console_suspend=1 console=tty1 " \ + "console=${console},${baudrate}n8 debug_uartport=lsport,0 " \ + "${memargs}\0" \ + "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ + "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ + "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "vidargs=fbcon=map:1\0" + +/* Increase console I/O buffer size */ +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 + +/* Increase arguments buffer size */ +#undef CONFIG_SYS_BARGSIZE +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Increase maximum number of arguments */ +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 32 + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +/* Reserve top 1M for secure RAM */ +#define CONFIG_ARMV7_SECURE_BASE 0xfff00000 +#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/apalis_imx6.h b/roms/u-boot/include/configs/apalis_imx6.h new file mode 100644 index 000000000..12de0105c --- /dev/null +++ b/roms/u-boot/include/configs/apalis_imx6.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013-2019 Toradex, Inc. + * + * Configuration settings for the Toradex Apalis iMX6 + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "mx6_common.h" + +#undef CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_MACH_TYPE 4886 + +#include +#include + +#ifdef CONFIG_SPL +#include "imx6_spl.h" +#endif + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SERIAL_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* I2C Configs */ +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_MXC_I2C3_SPEED 400000 + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_LBA48 +#endif + +/* Network */ +#define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */ + +/* USB Configs */ +/* Host */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +/* Client */ +#define CONFIG_USBD_HS + +/* Framebuffer and LCD */ +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +/* Command definition */ + +#undef CONFIG_IPADDR +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#undef CONFIG_SERVERIP +#define CONFIG_SERVERIP 192.168.10.1 + +#define CONFIG_LOADADDR 0x12000000 + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" +#else /* CONFIG_SPL_BUILD */ +#define BOOTENV +#endif /* CONFIG_SPL_BUILD */ + +#define UBOOT_UPDATE \ + "uboot_hwpart=1\0" \ + "uboot_blk=8a\0" \ + "uboot_spl_blk=2\0" \ + "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \ + "setexpr blkcnt ${blkcnt} / 0x200\0" \ + "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ + "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ + "update_spl=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ + "mmc write ${loadaddr} ${uboot_spl_blk} ${blkcnt}\0" + +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x20000000\0" \ + "fdt_addr_r=0x12100000\0" \ + "kernel_addr_r=0x11000000\0" \ + "pxefile_addr_r=0x17100000\0" \ + "ramdisk_addr_r=0x12200000\0" \ + "scriptaddr=0x17000000\0" + +#define NFS_BOOTCMD \ + "nfsargs=ip=:::::eth0:on root=/dev/nfs ro\0" \ + "nfsboot=run setup; " \ + "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \ + "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ + "run nfsdtbload; dhcp ${kernel_addr_r} " \ + "&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \ + "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \ + "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + +#ifndef CONFIG_TDX_APALIS_IMX6_V1_0 +#define FDT_FILE "imx6q-apalis-eval.dtb" +#define FDT_FILE_V1_0 "imx6q-apalis_v1_0-eval.dtb" +#else +#define FDT_FILE "imx6q-apalis_v1_0-eval.dtb" +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "bootcmd=run distro_bootcmd ; " \ + "usb start ; " \ + "setenv stdout serial,vidconsole; " \ + "setenv stdin serial,usbkbd\0" \ + "boot_file=zImage\0" \ + "console=ttymxc0\0" \ + "defargs=enable_wait_mode=off vmalloc=400M\0" \ + "fdt_file=" FDT_FILE "\0" \ + "fdtfile=" FDT_FILE "\0" \ + "fdt_fixup=;\0" \ + MEM_LAYOUT_ENV_SETTINGS \ + NFS_BOOTCMD \ + UBOOT_UPDATE \ + "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ + "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ + "flash_eth.img && source ${loadaddr}\0" \ + "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; " \ + "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img " \ + "|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1" \ + " ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "setup=setenv setupargs fec_mac=${ethaddr} " \ + "consoleblank=0 no_console_suspend=1 console=tty1 " \ + "console=${console},${baudrate}n8\0 " \ + "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ + "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ + "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "splashpos=m,m\0" \ + "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "vidargs=mxc_hdmi.only_cea=1 fbmem=32M\0" + +/* Miscellaneous configurable options */ +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 48 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/apalis_t30.h b/roms/u-boot/include/configs/apalis_t30.h new file mode 100644 index 000000000..f0c003d2f --- /dev/null +++ b/roms/u-boot/include/configs/apalis_t30.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2014-2016 Marcel Ziswiler + * + * Configuration settings for the Toradex Apalis T30 modules. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra30-common.h" + +/* + * Board-specific serial config + * + * Apalis UART1: NVIDIA UARTA + * Apalis UART2: NVIDIA UARTD + * Apalis UART3: NVIDIA UARTB + * Apalis UART4: NVIDIA UARTC + */ +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_APALIS_T30 + +/* PCI networking support */ +#define CONFIG_E1000_NO_NVM + +/* General networking support */ +#define CONFIG_TFTP_TSIZE + +/* Increase console I/O buffer size */ +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 + +/* Increase arguments buffer size */ +#undef CONFIG_SYS_BARGSIZE +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Increase maximum number of arguments */ +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 32 + +#define UBOOT_UPDATE \ + "uboot_hwpart=1\0" \ + "uboot_blk=0\0" \ + "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \ + "setexpr blkcnt ${blkcnt} / 0x200\0" \ + "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ + "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ + +#define BOARD_EXTRA_ENV_SETTINGS \ + UBOOT_UPDATE + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/aristainetos2.h b/roms/u-boot/include/configs/aristainetos2.h new file mode 100644 index 000000000..78fa1a969 --- /dev/null +++ b/roms/u-boot/include/configs/aristainetos2.h @@ -0,0 +1,455 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6DL aristainetos2 board. + */ +#ifndef __ARISTAINETOS2_CONFIG_H +#define __ARISTAINETOS2_CONFIG_H + +#define CONFIG_HOSTNAME "aristainetos2" + +#if (CONFIG_SYS_BOARD_VERSION == 5) +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONSOLE_DEV "ttymxc1" +#elif (CONFIG_SYS_BOARD_VERSION == 6) +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONSOLE_DEV "ttymxc0" +#endif + +#define CONFIG_FEC_XCV_TYPE RGMII + +/* Framebuffer */ +#define CONFIG_SYS_LDB_CLOCK 28341000 + +#include "mx6_common.h" + +#define CONFIG_MACH_TYPE 4501 +#define CONFIG_MMCROOT "/dev/mmcblk0p1" + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR + +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN + +#ifdef CONFIG_IMX_HAB +#define HAB_EXTRA_SETTINGS \ + "hab_check_addr=" \ + "if hab_auth_img ${check_addr} ${filesize} ; then " \ + "true;" \ + "else " \ + "echo \"HAB checks ${hab_check_filetype} " \ + "failed!\"; " \ + "false; " \ + "fi;\0" \ + "hab_check_file_fit=" \ + "if env exists enable_hab_check && test " \ + "${enable_hab_check} -eq 1 ; then " \ + "setenv hab_check_filetype \"FIT file on SD card " \ + "or eMMC\";" \ + "env set check_addr ${fit_addr_r};" \ + "run hab_check_addr;" \ + "else " \ + "true; "\ + "fi;\0" \ + "hab_check_file_bootscript=" \ + "if env exists enable_hab_check && test " \ + "${enable_hab_check} -eq 1 ; then " \ + "setenv hab_check_filetype \"Bootscript file\";" \ + "env set check_addr ${loadaddr};" \ + "run hab_check_addr;" \ + "else " \ + "true; "\ + "fi;\0" \ + "hab_check_flash_fit=" \ + "if env exists enable_hab_check && test " \ + "${enable_hab_check} -eq 1 ; then " \ + "setenv hab_check_filetype \"FIT files on flash\";" \ + "env set check_addr ${fit_addr_r};" \ + "run hab_check_addr;" \ + "else " \ + "true; "\ + "fi;\0" \ + "enable_hab_check=1\0" +#else +#define HAB_EXTRA_SETTINGS \ + "hab_check_addr=echo HAB check addr always returns " \ + "true;true\0" \ + "hab_check_file_fit=echo HAB check FIT file always returns " \ + "true;true\0" \ + "hab_check_flash_fit=echo HAB check flash FIT always returns " \ + "true;true\0" \ + "hab_check_file_bootscript=echo HAB check bootscript always " \ + "returns true;true\0" \ + "enable_hab_check=0\0" +#endif + +#if (CONFIG_SYS_BOARD_VERSION == 5) +#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ + "dead=while true; do; " \ + "led led_red on; sleep 1;" \ + "led led_red off; sleep 1;" \ + "done\0" +#elif (CONFIG_SYS_BOARD_VERSION == 6) +#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ + "dead=while true; do; " \ + "led led_red on; led led_red2 on; sleep 1;" \ + "led led_red off; led led_red2 off;; sleep 1;" \ + "done\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "disable_giga=yes\0" \ + "usb_pgood_delay=2000\0" \ + "nor_bootdelay=-2\0" \ + "script=u-boot.scr\0" \ + "loadaddr=0x12000000\0" \ + "fit_addr_r=0x14000000\0" \ + "uboot_sz=d0000\0" \ + "panel=lb07wv8\0" \ + "splashpos=m,m\0" \ + "console=" CONSOLE_DEV "\0" \ + "emmcroot=/dev/mmcblk1p1 rootwait rw\0" \ + "mtdids=nor0=spi0.0\0" \ + "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ + "-(ubi-nor)\0" \ + "mk_fitfile_path=setenv fit_file /${sysnum}/system.itb\0" \ + "mk_rescue_fitfile_path=setenv rescue_fit_file /${rescue_sysnum}/system.itb\0" \ + "mk_uboot_path=setenv uboot /${sysnum}/u-boot.imx\0" \ + "mk_pubkey_path=setenv pubkey /${sysnum}/PCR.pem\0" \ + "mk_rescue_pubkey_path=setenv pubkey /${rescue_sysnum}/PCR.pem\0" \ + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ + "bootmode=${bootmode} rng_core.default_quality=1000 " \ + "mmcpart=${mmcpart} emmcpart=${emmcpart} sysnum=${sysnum}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "boot_board_type=bootm ${fit_addr_r}#${board_type}\0" \ + "get_env=mw ${loadaddr} 0 0x20000;" \ + "mmc rescan;" \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \ + "env import -t ${loadaddr}\0" \ + "default_env=gpio set wp_spi_nor.gpio-hog;" \ + "sf probe;" \ + "sf protect unlock 0 0x1000000;" \ + "mw ${loadaddr} 0 0x20000;" \ + "env export -t ${loadaddr} serial# ethaddr " \ + "board_type panel;" \ + "env default -a;" \ + "env import -t ${loadaddr}\0" \ + "loadbootscript=" \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${script};\0" \ + "loadbootscriptUSB=" \ + "ext4load usb 0 ${loadaddr} ${script};\0" \ + "loadbootscriptUSBf=" \ + "fatload usb 0 ${loadaddr} ${script};\0" \ + "bootscriptUSB=echo Running bootscript from usb-stick ...; " \ + "source \0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source \0" \ + "mmcpart=1\0" \ + "mmcdev=0\0" \ + "emmcpart=1\0" \ + "emmcdev=1\0" \ + "sysnum=1\0" \ + "rescue_sysnum=0\0" \ + "rreason=18\0" \ + "mainboot=echo Booting from eMMC ...; " \ + "run mainargs addmtd addmisc;" \ + "run boot_board_type;" \ + "bootm ${fit_addr_r}\0" \ + "mainargs=setenv bootargs console=${console},${baudrate} " \ + "root=${emmcroot} rootfstype=ext4\0 " \ + "main_load_fit=run mk_fitfile_path; " \ + "ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \ + "${fit_file}; " \ + "imi ${fit_addr_r}\0 " \ + "rescue_load_fit=run mk_rescue_fitfile_path; " \ + "ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \ + "${rescue_fit_file}; " \ + "imi ${fit_addr_r}\0" \ + "main_load_pubkey=run mk_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load mmc ${emmcdev}:${emmcpart} ${loadaddr} " \ + "${pubkey}\0" \ + "rescue_load_pubkey=run mk_rescue_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load mmc ${emmcdev}:${emmcpart} ${loadaddr} " \ + "${pubkey}\0" \ + "mainRargs=setenv bootargs console=${console},${baudrate} " \ + "rescue_sysnum=${rescue_sysnum} root=${emmcroot} rootfstype=ext4\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "mmcRargs=setenv bootargs console=${console},${baudrate} " \ + "rescue_sysnum=${rescue_sysnum} root=${mmcroot}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs addmtd addmisc;" \ + "run boot_board_type;" \ + "bootm ${fit_addr_r}\0" \ + "mmc_load_fit=run mk_fitfile_path; " \ + "ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ + "${fit_file}\0" \ + "imi ${fit_addr_r}\0" \ + "mmc_rescue_load_fit=run mk_rescue_fitfile_path; " \ + "ext4load mmc ${mmcdev}:${mmcpart} " \ + "${fit_addr_r} ${rescue_fit_file}\0" \ + "imi ${fit_addr_r}\0" \ + "mmc_load_uboot=run mk_uboot_path; " \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${uboot}\0" \ + "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ + "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ + "setexpr uboot_maxsize ${uboot_sz} - 400;" \ + "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \ + "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \ + "sf write ${loadaddr} 400 ${filesize};" \ + "sf read ${cmp_buf} 400 ${uboot_sz};" \ + "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ + "mmc_load_pubkey=run mk_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${pubkey}\0" \ + "mmc_rescue_load_pubkey=run mk_rescue_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${pubkey}\0" \ + "rescueboot=echo Booting rescue system ...; " \ + "run addmtd addmisc;" \ + "if test -n ${rescue_reason}; then run rescue_reason;fi;" \ + "run boot_board_type;" \ + "if bootm ${fit_addr_r}; then ; " \ + "else " \ + "run dead; " \ + "fi; \0" \ + "r_reason_syserr=setenv rescue_reason setenv bootargs " \ + "\\\\${bootargs} " \ + "rescueReason=$rreason\0 " \ + "usb_load_fit=run mk_fitfile_path; " \ + "ext4load usb 0 ${fit_addr_r} ${fit_file}\0" \ + "usb_load_fitf=run mk_fitfile_path; " \ + "fatload usb 0 ${fit_addr_r} ${fit_file}\0" \ + "usb_load_rescuefit=run mk_rescue_fitfile_path; " \ + "ext4load usb 0 ${fit_addr_r} " \ + "${rescue_fit_file}\0" \ + "usb_load_rescuefitf=run mk_rescue_fitfile_path; " \ + "fatload usb 0 ${fit_addr_r} " \ + "${rescue_fit_file}\0" \ + "usb_load_pubkey=run mk_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load usb 0 ${loadaddr} ${pubkey}\0" \ + "usb_rescue_load_pubkey=run mk_rescue_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load usb 0 ${loadaddr} ${pubkey}\0" \ + "usb_load_pubkeyf=run mk_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "fatload usb 0 ${loadaddr} ${pubkey}\0" \ + "usb_rescue_load_pubkeyf=run mk_rescue_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "fatload usb 0 ${loadaddr} ${pubkey}\0" \ + "usbroot=/dev/sda1 rootwait rw\0" \ + "usbboot=echo Booting from usb-stick ...; " \ + "run usbargs addmtd addmisc;" \ + "run boot_board_type;" \ + "bootm ${fit_addr_r}\0" \ + "usbargs=setenv bootargs console=${console},${baudrate} " \ + "root=${usbroot}\0" \ + "usbRargs=setenv bootargs console=${console},${baudrate} " \ + "rescue_sysnum=${rescue_sysnum} root=${usbroot} rw\0 " \ + "mmc_rescue_boot=" \ + "run r_reason_syserr;" \ + "if run mmc_rescue_load_pubkey hab_check_addr " \ + "mmc_rescue_load_fit hab_check_file_fit; then " \ + "run mmcRargs; run rescueboot; " \ + "else " \ + "echo RESCUE SYSTEM FROM SD-CARD BOOT FAILURE;" \ + "run dead; " \ + "fi;\0" \ + "main_rescue_boot=" \ + "if run main_load_pubkey hab_check_addr " \ + "main_load_fit hab_check_flash_fit; then " \ + "if run mainboot; then ; " \ + "else " \ + "run r_reason_syserr;" \ + "if run rescue_load_pubkey hab_check_addr " \ + "rescue_load_fit hab_check_file_fit; then " \ + "run mainRargs; run rescueboot; " \ + "else " \ + "echo RESCUE SYSTEM BOOT FAILURE;" \ + "run dead; " \ + "fi; " \ + "fi; " \ + "else " \ + "run r_reason_syserr;" \ + "if run rescue_load_pubkey hab_check_addr " \ + "rescue_load_fit hab_check_file_fit; then " \ + "run mainRargs; run rescueboot; " \ + "else " \ + "echo RESCUE SYSTEM BOOT FAILURE;" \ + "run dead; " \ + "fi; " \ + "fi;\0" \ + "usb_mmc_rescue_boot=" \ + "usb start;" \ + "if usb storage; then " \ + "if run loadbootscriptUSB " \ + "hab_check_file_bootscript;" \ + "then run bootscriptUSB; " \ + "fi; " \ + "if run loadbootscriptUSBf " \ + "hab_check_file_bootscript;" \ + "then run bootscriptUSB; " \ + "fi; " \ + "if run usb_load_pubkey hab_check_addr " \ + "usb_load_fit hab_check_file_fit; then " \ + "run usbboot; " \ + "fi; " \ + "if run usb_load_pubkeyf hab_check_addr " \ + "usb_load_fitf hab_check_file_fit; then " \ + "run usbboot; " \ + "fi; "\ + "if run usb_rescue_load_pubkey hab_check_addr " \ + "usb_load_rescuefit hab_check_file_fit; then " \ + "run r_reason_syserr usbRargs; run rescueboot;" \ + "fi; " \ + "if run usb_rescue_load_pubkeyf hab_check_addr " \ + "usb_load_rescuefitf hab_check_file_fit; then " \ + "run r_reason_syserr usbRargs; run rescueboot;" \ + "fi; " \ + "run mmc_rescue_boot;" \ + "fi; "\ + "run mmc_rescue_boot;\0" \ + "rescue_xload_boot=" \ + "run r_reason_syserr;" \ + "if test ${bootmode} -ne 0 ; then " \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run mmc_rescue_load_pubkey " \ + "hab_check_addr " \ + "mmc_rescue_load_fit " \ + "hab_check_file_fit; then " \ + "run mmcRargs; run rescueboot; " \ + "else " \ + "usb start;" \ + "if usb storage; then " \ + "if run usb_rescue_load_pubkey " \ + "hab_check_addr " \ + "usb_load_rescuefit " \ + "hab_check_file_fit; then " \ + "run usbRargs; run rescueboot;" \ + "fi; " \ + "if run usb_rescue_load_pubkeyf " \ + "hab_check_addr " \ + "usb_load_rescuefitf " \ + "hab_check_file_fit; then " \ + "run usbRargs; run rescueboot;" \ + "fi; " \ + "fi;" \ + "fi;" \ + "echo RESCUE SYSTEM ON SD OR " \ + "USB BOOT FAILURE;" \ + "run dead; " \ + "else " \ + "usb start;" \ + "if usb storage; then " \ + "if run usb_rescue_load_pubkey " \ + "hab_check_addr " \ + "usb_load_rescuefit " \ + "hab_check_file_fit; then " \ + "run usbRargs; run rescueboot;" \ + "fi; " \ + "if run usb_rescue_load_pubkeyf " \ + "hab_check_addr " \ + "usb_load_rescuefitf " \ + "hab_check_file_fit; then " \ + "run usbRargs; run rescueboot;" \ + "fi; " \ + "fi;" \ + "echo RESCUE SYSTEM ON USB BOOT FAILURE;" \ + "run dead; " \ + "fi; " \ + "else "\ + "if run rescue_load_pubkey hab_check_addr " \ + "rescue_load_fit hab_check_file_fit; then " \ + "run mainRargs; run rescueboot; " \ + "else " \ + "echo RESCUE SYSTEM ON BOARD BOOT FAILURE;" \ + "run dead; " \ + "fi; " \ + "fi;\0" \ + "ari_boot=if test ${bootmode} -ne 0 ; then " \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript hab_check_file_bootscript;" \ + "then run bootscript; " \ + "fi; " \ + "if run mmc_load_pubkey hab_check_addr " \ + "mmc_load_fit hab_check_file_fit; then " \ + "if run mmcboot; then ; " \ + "else " \ + "run mmc_rescue_boot;" \ + "fi; " \ + "else " \ + "run usb_mmc_rescue_boot;" \ + "fi; " \ + "else " \ + "run usb_mmc_rescue_boot;" \ + "fi; " \ + "else "\ + "run main_rescue_boot;" \ + "fi; \0"\ + HAB_EXTRA_SETTINGS \ + CONFIG_EXTRA_ENV_BOARD_SETTINGS + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* DMA stuff, needed for GPMI/MXS NAND support */ + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* UBI support */ + +/* Framebuffer */ +/* check this console not needed, after test remove it */ +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO + +#define CONFIG_IMX6_PWM_PER_CLK 66000000 + +#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ + "sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" + +#endif /* __ARISTAINETOS2_CONFIG_H */ diff --git a/roms/u-boot/include/configs/armadillo-800eva.h b/roms/u-boot/include/configs/armadillo-800eva.h new file mode 100644 index 000000000..06704e5e1 --- /dev/null +++ b/roms/u-boot/include/configs/armadillo-800eva.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the bonito board + * + * Copyright (C) 2012 Renesas Solutions Corp. + */ + +#ifndef __ARMADILLO_800EVA_H +#define __ARMADILLO_800EVA_H + +#define CONFIG_SH_GPIO_PFC + +#include + +#define BOARD_LATE_INIT + +#define CONFIG_TMU_TIMER +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ +#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4) + +/* STACK */ +#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000 +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define ARMADILLO_800EVA_SDRAM_BASE 0x40000000 +#define ARMADILLO_800EVA_SDRAM_SIZE (512 * 1024 * 1024) + +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } + +/* SCIF */ +#define CONFIG_CONS_SCIF1 +#define SCIF0_BASE 0xe6c40000 +#define SCIF1_BASE 0xe6c50000 +#define SCIF2_BASE 0xe6c60000 +#define SCIF4_BASE 0xe6c80000 +#define CONFIG_SCIF_A + +#undef CONFIG_SYS_LOADS_BAUD_CHANGE + +#define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE) +#define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ + 64 * 1024 * 1024) + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) + +/* FLASH */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_BASE 0x00000000 +#define CONFIG_SYS_MAX_FLASH_SECT 512 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } + +#define CONFIG_SYS_FLASH_ERASE_TOUT 3000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 3000 +#define CONFIG_SYS_FLASH_LOCK_TOUT 3000 +#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000 + +/* ENV setting */ + +/* SH Ether */ +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x0 +#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000 +#define CONFIG_SH_ETHER_SH7734_MII (0x01) +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define CONFIG_SYS_CLK_FREQ 50000000 +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ + +#endif /* __ARMADILLO_800EVA_H */ diff --git a/roms/u-boot/include/configs/arndale.h b/roms/u-boot/include/configs/arndale.h new file mode 100644 index 000000000..5109f7de5 --- /dev/null +++ b/roms/u-boot/include/configs/arndale.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG Arndale board. + */ + +#ifndef __CONFIG_ARNDALE_H +#define __CONFIG_ARNDALE_H + +#define EXYNOS_FDTFILE_SETTING \ + "fdtfile=exynos5250-arndale.dtb\0" + +#include "exynos5250-common.h" +#include + +/* MMC SPL */ +#define CONFIG_EXYNOS_SPL + +/* Miscellaneous configurable options */ +#define CONFIG_IRAM_STACK 0x02050000 + +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK + +#define CONFIG_S5P_PA_SYSRAM 0x02020000 +#define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM + +/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ +#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/aspeed-common.h b/roms/u-boot/include/configs/aspeed-common.h new file mode 100644 index 000000000..df0f5d2e7 --- /dev/null +++ b/roms/u-boot/include/configs/aspeed-common.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * Ryan Chen + * + * Copyright 2016 IBM Corporation + * (C) Copyright 2016 Google, Inc + */ + +#ifndef _ASPEED_COMMON_CONFIG_H +#define _ASPEED_COMMON_CONFIG_H + +#include + +/* Misc CPU related */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE + +#ifdef CONFIG_PRE_CON_BUF_SZ +#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ) +#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ) +#else +#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE) +#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE) +#endif + +#define SYS_INIT_RAM_END (CONFIG_SYS_INIT_RAM_ADDR \ + + CONFIG_SYS_INIT_RAM_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (SYS_INIT_RAM_END \ + - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN (32 << 20) + +/* + * NS16550 Configuration + */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=yes\0" \ + "spi_dma=yes\0" \ + "" + +#endif /* __AST_COMMON_CONFIG_H */ diff --git a/roms/u-boot/include/configs/aspenite.h b/roms/u-boot/include/configs/aspenite.h new file mode 100644 index 000000000..88e1bf177 --- /dev/null +++ b/roms/u-boot/include/configs/aspenite.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * Contributor: Mahavir Jain + */ + +#ifndef __CONFIG_ASPENITE_H +#define __CONFIG_ASPENITE_H + +/* + * High Level Configuration Options + */ +#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ +#define CONFIG_ARMADA100 1 /* SOC Family Name */ +#define CONFIG_ARMADA168 1 /* SOC Used on this Board */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * There is no internal RAM in ARMADA100, using DRAM + * TBD: dcache to be used for this + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) + +#include "mv-common.h" + +/* + * Environment variables configurations + */ + +#endif /* __CONFIG_ASPENITE_H */ diff --git a/roms/u-boot/include/configs/astro_mcf5373l.h b/roms/u-boot/include/configs/astro_mcf5373l.h new file mode 100644 index 000000000..891240c7e --- /dev/null +++ b/roms/u-boot/include/configs/astro_mcf5373l.h @@ -0,0 +1,288 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the Sentec Cobra Board. + * + * (C) Copyright 2003 Josef Baumgartner + */ + +/* + * configuration for ASTRO "Urmel" board. + * Originating from Cobra5272 configuration, messed up by + * Wolfgang Wegner + * Please do not bother the original author with bug reports + * concerning this file. + */ + +#ifndef _CONFIG_ASTRO_MCF5373L_H +#define _CONFIG_ASTRO_MCF5373L_H + +#include + +/* + * set the card type to actually compile for; either of + * the possibilities listed below has to be used! + */ +#define CONFIG_ASTRO_V532 1 + +#if CONFIG_ASTRO_V532 +#define ASTRO_ID 0xF8 +#elif CONFIG_ASTRO_V512 +#define ASTRO_ID 0xFA +#elif CONFIG_ASTRO_TWIN7S2 +#define ASTRO_ID 0xF9 +#elif CONFIG_ASTRO_V912 +#define ASTRO_ID 0xFC +#elif CONFIG_ASTRO_COFDMDUOS2 +#define ASTRO_ID 0xFB +#else +#error No card type defined! +#endif + +/* + * CONFIG_RAM defines if u-boot is loaded via BDM (or started from + * a different bootloader that has already performed RAM setup) or + * started directly from flash, which is the regular case for production + * boards. + */ +#ifdef CONFIG_RAM +#define CONFIG_MONITOR_IS_IN_RAM +#define ENABLE_JFFS 0 +#else +#define ENABLE_JFFS 1 +#endif + +#define CONFIG_MCFRTC +#undef RTC_DEBUG + +/* Timer */ +#define CONFIG_MCFTMR + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 80000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +/* + * Defines processor clock - important for correct timings concerning serial + * interface etc. + */ + +#define CONFIG_SYS_CLK 80000000 +#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) +#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ + +#define CONFIG_SYS_CORE_SRAM_SIZE 0x8000 +#define CONFIG_SYS_CORE_SRAM 0x80000000 + +#define CONFIG_SYS_UNIFY_CACHE + +/* + * Define baudrate for UART1 (console output, tftp, ...) + * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud + * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected + * in u-boot command interface + */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (2) +#define CONFIG_SYS_UART2_ALT3_GPIO + +/* + * Watchdog configuration; Watchdog is disabled for running from RAM + * and set to highest possible value else. Beware there is no check + * in the watchdog code to validate the timeout value set here! + */ + +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */ +#endif + +/* + * Configuration for environment + * Environment is located in the last sector of the flash + */ + +#ifndef CONFIG_MONITOR_IS_IN_RAM +#else +/* + * environment in RAM - This is used to use a single PC-based application + * to load an image, load U-Boot, load an environment and then start U-Boot + * to execute the commands from the environment. Feedback is done via setting + * and reading memory locations. + */ +#endif + +/* here we put our FPGA configuration... */ + +/* Define user parameters that have to be customized most likely */ + +/* AUTOBOOT settings - booting images automatically by u-boot after power on */ + +/* + * The following settings will be contained in the environment block ; if you + * want to use a neutral environment all those settings can be manually set in + * u-boot: 'set' command + */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loaderversion=11\0" \ + "card_id="__stringify(ASTRO_ID)"\0" \ + "alterafile=0\0" \ + "xilinxfile=0\0" \ + "xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\ + "fpga load 0 0x41000000 $filesize\0" \ + "alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\ + "fpga load 1 0x41000000 $filesize\0" \ + "env_default=1\0" \ + "env_check=if test $env_default -eq 1;"\ + " then setenv env_default 0;saveenv;fi\0" + +/* + * "update" is a non-standard command that has to be supplied + * by external update.c; This is not included in mainline because + * it needs non-blocking CFI routines. + */ +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */ +#else +#if CONFIG_ASTRO_V532 +#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ + "run xilinxload&&run alteraload&&bootm 0x80000;"\ + "update;reset" +#else +#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ + "run xilinxload&&bootm 0x80000;update;reset" +#endif +#endif + +/* default RAM address for user programs */ +#define CONFIG_SYS_LOAD_ADDR 0x20000 + +#define CONFIG_FPGA_COUNT 1 +#define CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_SYS_FPGA_WAIT 1000 + +/* End of user parameters to be customized */ + +/* Defines memory range for test */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/* Base register address */ + +#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ + +/* System Conf. Reg. & System Protection Reg. */ + +#define CONFIG_SYS_SCR 0x0003; +#define CONFIG_SYS_SPR 0xffff; + +/* + * Definitions for initial stack pointer and data area (in internal SRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +/* + * Chipselect bank definitions + * + * CS0 - Flash 32MB (first 16MB) + * CS1 - Flash 32MB (second half) + * CS2 - FPGA + * CS3 - FPGA + * CS4 - unused + * CS5 - unused + */ +#define CONFIG_SYS_CS0_BASE 0 +#define CONFIG_SYS_CS0_MASK 0x00ff0001 +#define CONFIG_SYS_CS0_CTRL 0x00001fc0 + +#define CONFIG_SYS_CS1_BASE 0x01000000 +#define CONFIG_SYS_CS1_MASK 0x00ff0001 +#define CONFIG_SYS_CS1_CTRL 0x00001fc0 + +#define CONFIG_SYS_CS2_BASE 0x20000000 +#define CONFIG_SYS_CS2_MASK 0x00ff0001 +#define CONFIG_SYS_CS2_CTRL 0x0000fec0 + +#define CONFIG_SYS_CS3_BASE 0x21000000 +#define CONFIG_SYS_CS3_MASK 0x00ff0001 +#define CONFIG_SYS_CS3_CTRL 0x0000fec0 + +#define CONFIG_SYS_FLASH_BASE 0x00000000 + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#else +/* This is mainly used during relocation in start.S */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif +/* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) + +#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) +/* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (128 << 10) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/* FLASH organization */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 259 +#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 + +#define CONFIG_SYS_FLASH_SIZE 0x2000000 +#define CONFIG_SYS_FLASH_CFI_NONBLOCK 1 + +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + env/embedded.o(.text*) + +#if ENABLE_JFFS +/* JFFS Partition offset set */ +#define CONFIG_SYS_JFFS2_FIRST_BANK 0 +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40 +#endif + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + +#endif /* _CONFIG_ASTRO_MCF5373L_H */ diff --git a/roms/u-boot/include/configs/at91-sama5_common.h b/roms/u-boot/include/configs/at91-sama5_common.h new file mode 100644 index 000000000..ba21149e4 --- /dev/null +++ b/roms/u-boot/include/configs/at91-sama5_common.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Common part of configuration settings for the AT91 SAMA5 board. + * + * Copyright (C) 2015 Atmel Corporation + * Josh Wu + */ + +#ifndef __AT91_SAMA5_COMMON_H +#define __AT91_SAMA5_COMMON_H + +#include + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#ifdef CONFIG_SD_BOOT +#define CONFIG_BOOTCOMMAND "if test ! -n ${dtb_name}; then " \ + "setenv dtb_name at91-${board_name}.dtb; " \ + "fi; " \ + "fatload mmc 0:1 0x21000000 ${dtb_name}; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" + +#else + +#ifdef CONFIG_NAND_BOOT +/* u-boot env in nand flash */ +#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ + "nand read 0x22000000 0x200000 0x600000;" \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_SPI_BOOT +/* u-boot env in serial flash, by default is bus 0 and cs 0 */ +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x21000000 0x60000 0xc000; " \ + "sf read 0x22000000 0x6c000 0x394000; " \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_QSPI_BOOT +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x21000000 0x180000 0x80000; " \ + "sf read 0x22000000 0x200000 0x600000; " \ + "bootz 0x22000000 - 0x21000000" +#endif + +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#endif diff --git a/roms/u-boot/include/configs/at91rm9200ek.h b/roms/u-boot/include/configs/at91rm9200ek.h new file mode 100644 index 000000000..bf6a61434 --- /dev/null +++ b/roms/u-boot/include/configs/at91rm9200ek.h @@ -0,0 +1,162 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2010 Andreas Bießmann + * + * based on previous work by + * + * Ulf Samuelsson + * Rick Bronson + * + * Configuration settings for the AT91RM9200EK board. + */ + +#ifndef __AT91RM9200EK_CONFIG_H__ +#define __AT91RM9200EK_CONFIG_H__ + +#include + +/* + * set some initial configurations depending on configure target + * + * at91rm9200ek_config -> boot from 0x0 in NOR Flash at CS0 + * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel + * initialisation was done by some preloader + */ +#ifdef CONFIG_RAMBOOT +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz + * AT91C_MAIN_CLOCK is the frequency of PLLA output + * AT91C_MASTER_CLOCK is the peripherial clock + * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely + * set in arch/arm/cpu/arm920t/at91/timer.c) + * CONFIG_SYS_HZ is the tick rate for timer tc0 + */ +#define AT91C_XTAL_CLOCK 18432000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) +#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 ) +#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) + +/* CPU configuration */ +#define CONFIG_AT91RM9200 +#define CONFIG_AT91RM9200EK +#define USE_920T_MMU + +#include /* needed for port definitions */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Memory Configuration + */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE SZ_32M + +/* + * LowLevel Init + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_USE_MAIN_OSCILLATOR +/* flash */ +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ + +/* clocks */ +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ +#define CONFIG_SYS_MCKR_VAL 0x00000202 + +/* sdram */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */ +#define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80) +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +/* + * Hardware drivers + */ +/* + * Choose a USART for serial console + * CONFIG_DBGU is DBGU unit on J10 + * CONFIG_USART1 is USART1 on J14 + */ +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID 0/* ignored in arm */ + +/* + * Network Driver Setting + */ +#define CONFIG_DRIVER_AT91EMAC +#define CONFIG_SYS_RX_ETH_BUFFER 16 +#define CONFIG_RMII + +/* + * NOR Flash + */ +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE +#define PHYS_FLASH_SIZE SZ_8M +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +/* + * USB Config + */ +#define CONFIG_USB_ATMEL 1 +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB +#define CONFIG_USB_OHCI_NEW 1 + +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_USB_HOST_BASE +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 + +/* + * Environment Settings + */ + +/* + * after u-boot.bin + */ + +/* The following #defines are needed to get flash environment right */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN SZ_256K + +/* + * Boot option + */ + +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M + +/* + * Shell Settings + */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \ + SZ_4K) + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ + - GENERATED_GBL_DATA_SIZE) + +#endif /* __AT91RM9200EK_CONFIG_H__ */ diff --git a/roms/u-boot/include/configs/at91sam9260ek.h b/roms/u-boot/include/configs/at91sam9260ek.h new file mode 100644 index 000000000..780bf0cce --- /dev/null +++ b/roms/u-boot/include/configs/at91sam9260ek.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * Configuation settings for the AT91SAM9260EK & AT91SAM9G20EK boards. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include + +/* + * Warning: changing CONFIG_SYS_TEXT_BASE requires + * adapting the initial boot program. + * Since the linker has to swallow that define, we must use a pure + * hex number here! + */ + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ + +/* Define actual evaluation board type from used processor type */ +#ifdef CONFIG_AT91SAM9G20 +# define CONFIG_AT91SAM9G20EK /* It's an Atmel AT91SAM9G20 EK */ +#else +# define CONFIG_AT91SAM9260EK /* It's an Atmel AT91SAM9260 EK */ +#endif + +/* Misc CPU related */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 + +/* + * SDRAM: 1 bank, min 32, max 128 MB + * Initialized before u-boot gets started. + */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 + +/* + * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, + * leaving the correct space for initial global data structure above + * that address while providing maximum stack area below. + */ +#ifdef CONFIG_AT91SAM9XE +# define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#else +# define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +/* + * The (arm)linux board id set by generic code depending on configured board + * (see boards.cfg for different boards) + */ +#ifdef CONFIG_AT91SAM9G20 + /* the sam9g20 variants have two different board ids */ +# ifdef CONFIG_AT91SAM9G20EK_2MMC + /* we may be setup for the 2MMC variant of at91sam9g20ek */ +# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK_2MMC +# else + /* or the normal at91sam9g20ek */ +# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK +# endif +#else + /* otherwise default to good old at91sam9260ek */ +# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9260EK +#endif + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 +#endif + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#ifdef CONFIG_SYS_USE_DATAFLASH_CS0 + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CONFIG_BOOTCOMMAND "sf probe 0:0; " \ + "sf read 0x22000000 0x84000 0x294000; " \ + "bootm 0x22000000" + +#elif CONFIG_SYS_USE_DATAFLASH_CS1 + +#define CONFIG_BOOTCOMMAND "sf probe 0:1; " \ + "sf read 0x22000000 0x84000 0x294000; " \ + "bootm 0x22000000" + +#elif defined(CONFIG_SYS_USE_NANDFLASH) + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" + +#else /* CONFIG_SYS_USE_MMC */ +/* bootstrap + u-boot + env + linux in mmc */ +/* For FAT system, most cases it should be in the reserved sector */ + +#define CONFIG_BOOTCOMMAND \ + "fatload mmc 0:1 0x22000000 uImage; bootm" +#endif + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) + +#endif diff --git a/roms/u-boot/include/configs/at91sam9261ek.h b/roms/u-boot/include/configs/at91sam9261ek.h new file mode 100644 index 000000000..c3fe41636 --- /dev/null +++ b/roms/u-boot/include/configs/at91sam9261ek.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * Configuation settings for the AT91SAM9261EK board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ + +#ifdef CONFIG_AT91SAM9G10 +#define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK*/ +#else +#define CONFIG_AT91SAM9261EK /* It's an Atmel AT91SAM9261 EK*/ +#endif + +#include + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_ATMEL_LEGACY + +/* + * Hardware drivers + */ + +/* LCD */ +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_ATMEL_LCD +#ifdef CONFIG_AT91SAM9261EK +#define CONFIG_ATMEL_LCD_BGR555 +#endif + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 +/* our ALE is AD22 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 22) +/* our CLE is AD21 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 21) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15 + +#endif + +/* Ethernet */ +#define CONFIG_DRIVER_DM9000 +#define CONFIG_DM9000_BASE 0x30000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 4) +#define CONFIG_DM9000_USE_16BIT +#define CONFIG_DM9000_NO_SROM +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ +#ifdef CONFIG_AT91SAM9G10EK +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10" +#else +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" +#endif +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#ifdef CONFIG_SYS_USE_DATAFLASH_CS0 + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x22000000 0x84000 0x294000; " \ + "bootm 0x22000000" + +#elif CONFIG_SYS_USE_DATAFLASH_CS3 + +/* bootstrap + u-boot + env + linux in dataflash on CS3 */ +#define CONFIG_BOOTCOMMAND "sf probe 0:3; " \ + "sf read 0x22000000 0x84000 0x294000; " \ + "bootm 0x22000000" + +#else /* CONFIG_SYS_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" +#endif + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) + +#endif diff --git a/roms/u-boot/include/configs/at91sam9263ek.h b/roms/u-boot/include/configs/at91sam9263ek.h new file mode 100644 index 000000000..51ecf4173 --- /dev/null +++ b/roms/u-boot/include/configs/at91sam9263ek.h @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * Configuation settings for the AT91SAM9263EK board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#ifndef CONFIG_SYS_USE_BOOT_NORFLASH +#define CONFIG_SKIP_LOWLEVEL_INIT +#else +#define CONFIG_SYS_USE_NORFLASH +#endif + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_LEGACY + +/* LCD */ +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_BGR555 1 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +/* NOR flash, if populated */ +#ifdef CONFIG_SYS_USE_NORFLASH +#define PHYS_FLASH_1 0x10000000 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#define CONFIG_SYS_MONITOR_SEC 1:0-3 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (256 << 10) + +/* Address and size of Primary Environment Sector */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ + "update=" \ + "protect off ${monitor_base} +${filesize};" \ + "erase ${monitor_base} +${filesize};" \ + "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ + "protect on ${monitor_base} +${filesize}\0" + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#define MASTER_PLL_MUL 171 +#define MASTER_PLL_DIV 14 +#define MASTER_PLL_OUT 3 + +/* clocks */ +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLAR_29 | \ + AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ + AT91_PMC_PLLXR_PLLCOUNT(63) | \ + AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ + AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) + +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +/* no pull-up for D[31:16] */ +#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 +/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ +#define CONFIG_SYS_MATRIX_EBICSA_VAL \ + (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ + AT91_MATRIX_CSA_EBI_CS1A) + +/* SDRAM */ +/* SDRAMC_MR Mode register */ +#define CONFIG_SYS_SDRC_MR_VAL1 0 +/* SDRAMC_TR - Refresh Timer register */ +#define CONFIG_SYS_SDRC_TR_VAL1 0x13C +/* SDRAMC_CR - Configuration register*/ +#define CONFIG_SYS_SDRC_CR_VAL \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_3 | \ + AT91_SDRAMC_DBW_32 | \ + (1 << 8) | /* Write Recovery Delay */ \ + (7 << 12) | /* Row Cycle Delay */ \ + (2 << 16) | /* Row Precharge Delay */ \ + (2 << 20) | /* Row to Column Delay */ \ + (5 << 24) | /* Active to Precharge Delay */ \ + (1 << 28)) /* Exit Self Refresh to Active Delay */ + +/* Memory Device Register -> SDRAM */ +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ + AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ + AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ + AT91_SMC_MODE_DBW_16 | \ + AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_MR_URSTEN | \ + AT91_RSTC_MR_ERSTL(15)) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ + AT91_WDT_MR_WDV(0xfff) | \ + AT91_WDT_MR_WDDIS | \ + AT91_WDT_MR_WDD(0xfff)) + +#endif +#include +#endif + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 +#endif + +/* Ethernet */ +#define CONFIG_RESET_PHY_R 1 +#define CONFIG_AT91_WANTS_COMMON_PHY + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#ifdef CONFIG_SYS_USE_DATAFLASH + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x22000000 0x84000 0x294000; " \ + "bootm 0x22000000" + +#elif CONFIG_SYS_USE_NANDFLASH + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" +#endif + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) + +#endif diff --git a/roms/u-boot/include/configs/at91sam9m10g45ek.h b/roms/u-boot/include/configs/at91sam9m10g45ek.h new file mode 100644 index 000000000..b4aaf5995 --- /dev/null +++ b/roms/u-boot/include/configs/at91sam9m10g45ek.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES). + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_AT91SAM9M10G45EK + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +/* LCD */ +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_ATMEL_LCD +#define CONFIG_ATMEL_LCD_RGB565 +/* board specific(not enough SRAM) */ +#define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x70000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 + +#endif + +/* Ethernet */ +#define CONFIG_RESET_PHY_R +#define CONFIG_AT91_WANTS_COMMON_PHY + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#ifdef CONFIG_NAND_BOOT +/* bootstrap + u-boot + env in nandflash */ + +#define CONFIG_BOOTCOMMAND \ + "nand read 0x70000000 0x200000 0x300000;" \ + "bootm 0x70000000" +#elif CONFIG_SD_BOOT +/* bootstrap + u-boot + env + linux in mmc */ + +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \ + "fatload mmc 0:1 0x72000000 zImage; " \ + "bootz 0x72000000 - 0x71000000" +#endif + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) + +/* Defines for SPL */ +#define CONFIG_SPL_MAX_SIZE 0x010000 +#define CONFIG_SPL_STACK 0x310000 + +#define CONFIG_SYS_MONITOR_LEN 0x80000 + +#ifdef CONFIG_SD_BOOT + +#define CONFIG_SPL_BSS_START_ADDR 0x70000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 +#define CONFIG_SYS_SPL_MALLOC_START 0x70080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 + +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +#elif CONFIG_NAND_BOOT +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } +#endif + +#define CONFIG_SPL_ATMEL_SIZE +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#endif diff --git a/roms/u-boot/include/configs/at91sam9n12ek.h b/roms/u-boot/include/configs/at91sam9n12ek.h new file mode 100644 index 000000000..fe99253e5 --- /dev/null +++ b/roms/u-boot/include/configs/at91sam9n12ek.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 Atmel Corporation. + * Josh Wu + * + * Configuation settings for the AT91SAM9N12-EK boards. + */ + +#ifndef __AT91SAM9N12_CONFIG_H_ +#define __AT91SAM9N12_CONFIG_H_ + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ + +/* Misc CPU related */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* LCD */ +#define LCD_BPP LCD_COLOR16 +#define LCD_OUTPUT_BPP 24 +#define CONFIG_LCD_LOGO +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_ATMEL_LCD_RGB565 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 + +/* + * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, + * leaving the correct space for initial global data structure above + * that address while providing maximum stack area below. + */ +# define CONFIG_SYS_INIT_SP_ADDR \ + (0x00300000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +/* DataFlash */ + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4) +#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5) +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ + "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\ + "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0" + +/* Ethernet */ +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* USB host */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9n12" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#endif + +#ifdef CONFIG_SPI_BOOT + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_nand};" \ + "sf probe 0; sf read 0x22000000 0x100000 0x300000; " \ + "bootm 0x22000000" + +#elif defined(CONFIG_NAND_BOOT) + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_nand};" \ + "nand read 0x21000000 0x180000 0x080000;" \ + "nand read 0x22000000 0x200000 0x400000;" \ + "bootm 0x22000000 - 0x21000000" + +#else /* CONFIG_SD_BOOT */ + +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_mmc};" \ + "fatload mmc 0:1 0x21000000 dtb;" \ + "fatload mmc 0:1 0x22000000 uImage;" \ + "bootm 0x22000000 - 0x21000000" + +#endif + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* SPL */ +#define CONFIG_SPL_MAX_SIZE 0x6000 +#define CONFIG_SPL_STACK 0x308000 + +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CONFIG_SYS_AT91_PLLA 0x20953f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + +#endif diff --git a/roms/u-boot/include/configs/at91sam9rlek.h b/roms/u-boot/include/configs/at91sam9rlek.h new file mode 100644 index 000000000..92b87a2b4 --- /dev/null +++ b/roms/u-boot/include/configs/at91sam9rlek.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * Configuation settings for the AT91SAM9RLEK board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_ATMEL_LEGACY + +/* + * Hardware drivers + */ + +/* LCD */ +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_RGB565 1 +/* Let board_init_f handle the framebuffer allocation */ +#undef CONFIG_FB_ADDR + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17 + +#endif + +/* Ethernet - not present */ + +/* USB - not supported */ + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#ifdef CONFIG_SYS_USE_DATAFLASH + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x22000000 0x84000 0x294000; " \ + "bootm 0x22000000" + +#elif CONFIG_SYS_USE_NANDFLASH + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x600000; " \ + "nand read 0x21000000 0x180000 0x80000; " \ + "bootz 0x22000000 - 0x21000000" + +#else /* CONFIG_SYS_USE_MMC */ + +/* bootstrap + u-boot + env + linux in mmc */ +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91sam9rlek.dtb; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#endif + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) + +#endif diff --git a/roms/u-boot/include/configs/at91sam9x5ek.h b/roms/u-boot/include/configs/at91sam9x5ek.h new file mode 100644 index 000000000..6a95b39cd --- /dev/null +++ b/roms/u-boot/include/configs/at91sam9x5ek.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Atmel Corporation + * + * Configuation settings for the AT91SAM9X5EK board. + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0) + * NB: in this case, USB 1.1 devices won't be recognized. + */ + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +/* DataFlash */ + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#ifndef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_UPLL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#endif +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#ifdef CONFIG_NAND_BOOT +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_BOOTCOMMAND "nand read " \ + "0x22000000 0x200000 0x600000; " \ + "nand read 0x21000000 0x180000 0x20000; " \ + "bootz 0x22000000 - 0x21000000" +#elif defined(CONFIG_SPI_BOOT) +/* bootstrap + u-boot + env + linux in spi flash */ +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x22000000 0x100000 0x300000; " \ + "bootm 0x22000000" +#elif defined(CONFIG_SYS_USE_DATAFLASH) +/* bootstrap + u-boot + env + linux in data flash */ +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x22000000 0x84000 0x294000; " \ + "bootm 0x22000000" +#endif + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) + +/* SPL */ +#define CONFIG_SPL_MAX_SIZE 0x6000 +#define CONFIG_SPL_STACK 0x308000 + +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + +#endif diff --git a/roms/u-boot/include/configs/ax25-ae350.h b/roms/u-boot/include/configs/ax25-ae350.h new file mode 100644 index 000000000..bd9c371f8 --- /dev/null +++ b/roms/u-boot/include/configs/ax25-ae350.h @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_SPL +#define CONFIG_SPL_MAX_SIZE 0x00100000 +#define CONFIG_SPL_BSS_START_ADDR 0x04000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 + +#ifdef CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" +#endif +#endif + +#define RISCV_MMODE_TIMERBASE 0xe6000000 +#define RISCV_MMODE_TIMER_FREQ 60000000 + +#define RISCV_SMODE_TIMER_FREQ 60000000 + +/* + * CPU and Board Configuration Options + */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* + * Print Buffer Size + */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * max number of command args + */ +#define CONFIG_SYS_MAXARGS 16 + +/* + * Boot Argument Buffer Size + */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * Size of malloc() pool + * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough + */ +#define CONFIG_SYS_MALLOC_LEN (512 << 10) + +/* DT blob (fdt) address */ +#define CONFIG_SYS_FDT_BASE 0x800f0000 + +/* + * Physical Memory Map + */ +#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1 \ + (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ +#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ +#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 + +/* + * Serial console configuration + */ +#define CONFIG_SYS_NS16550_SERIAL +#ifndef CONFIG_DM_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#endif +#define CONFIG_SYS_NS16550_CLK 19660800 + +/* Init Stack Pointer */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Load address and memory test area should agree with + * arch/riscv/config.mk. Be careful not to overwrite U-Boot itself. + */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */ + +/* + * memtest works on 512 MB in DRAM + */ + +/* + * FLASH and environment organization + */ + +/* use CFI framework */ + +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL + +/* support JEDEC */ +#ifdef CONFIG_CFI_FLASH +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#endif/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ +#define PHYS_FLASH_1 0x88000000 /* BANK 0 */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ + +/* max number of memory banks */ +/* + * There are 4 banks supported for this Controller, + * but we have only 1 bank connected to flash on board +*/ +#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#endif +#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} + +/* max number of sectors on one chip */ +#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +/* environments */ + +/* SPI FLASH */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + +/* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) +/* Increase max gunzip size */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) + +/* When we use RAM as ENV */ + +/* Enable distro boot */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x00080000\0" \ + "pxefile_addr_r=0x01f00000\0" \ + "scriptaddr=0x01f00000\0" \ + "fdt_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x02800000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/axs10x.h b/roms/u-boot/include/configs/axs10x.h new file mode 100644 index 000000000..0c5a3af4c --- /dev/null +++ b/roms/u-boot/include/configs/axs10x.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved. + */ + +#ifndef _CONFIG_AXS10X_H_ +#define _CONFIG_AXS10X_H_ + +#include +/* + * CPU configuration + */ +#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000 +#define ARC_APB_PERIPHERAL_BASE 0xF0000000 +#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000) +#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000) + +/* + * Memory configuration + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE SZ_512M + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN SZ_2M +#define CONFIG_SYS_BOOTM_LEN SZ_128M +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +/* + * UART configuration + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK 33333333 +#define CONFIG_SYS_NS16550_MEM32 + +/* + * Ethernet PHY configuration + */ + +/* + * USB 1.1 configuration + */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 + +/* + * Environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "upgrade=if mmc rescan && " \ + "fatload mmc 0:1 ${loadaddr} u-boot-update.img && " \ + "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \ + "\"Fail to upgrade.\n" \ + "Do you have u-boot-update.img and u-boot.head on first (FAT) SD card partition?\"" \ + "; fi\0" + +/* + * Environment configuration + */ +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ + +#endif /* _CONFIG_AXS10X_H_ */ diff --git a/roms/u-boot/include/configs/baltos.h b/roms/u-boot/include/configs/baltos.h new file mode 100644 index 000000000..42a5abd1b --- /dev/null +++ b/roms/u-boot/include/configs/baltos.h @@ -0,0 +1,258 @@ +/* + * am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CONFIG_BALTOS_H +#define __CONFIG_BALTOS_H + +#include +#include + +#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* FIT support */ +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +#ifdef CONFIG_MTD_RAW_NAND + +#define NANDARGS \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "${mtdparts} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=5\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "setenv loadaddr 0x84000000; " \ + "ubi part UBI; " \ + "ubifsmount ubi0:kernel; " \ + "ubifsload $loadaddr kernel-fit.itb;" \ + "ubifsumount; " \ + "bootm ${loadaddr}#conf${board_name}; " \ + "if test $? -ne 0; then echo Using default FIT config; " \ + "bootm ${loadaddr}; fi;\0" +#else +#define NANDARGS "" +#endif + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "boot_fdt=try\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "fdtfile=undefined\0" \ + "console=ttyO0,115200n8\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ + "usbroot=/dev/sda2 ro\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "usbrootfstype=ext4 rootwait\0" \ + "rootpath=/export/rootfs\0" \ + "nfsopts=nolock\0" \ + "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ + "::off\0" \ + "ramroot=/dev/ram0 rw\0" \ + "ramrootfstype=ext2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "${mtdparts} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "usbargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "${mtdparts} " \ + "root=${usbroot} " \ + "rootfstype=${usbrootfstype}\0" \ + "spiroot=/dev/mtdblock4 rw\0" \ + "spirootfstype=jffs2\0" \ + "spisrcaddr=0xe0000\0" \ + "spiimgsize=0x362000\0" \ + "spibusno=0\0" \ + "spiargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${spiroot} " \ + "rootfstype=${spirootfstype}\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "usbloadbootenv=load usb 0:1 ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "usbimportbootenv=echo Importing environment from USB ...; " \ + "env import -t $loadaddr $filesize\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "usbloadimage=load usb 0:1 ${loadaddr} kernel-fit.itb\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "usbloados=run usbargs; " \ + "bootm ${loadaddr}#conf${board_name}; " \ + "if test $? -ne 0; then " \ + "echo Using default FIT configuration; " \ + "bootm ${loadaddr}; " \ + "fi;\0" \ + "mmcloados=run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "usbboot=usb reset; " \ + "if usb storage; then " \ + "echo USB drive found;" \ + "if run usbloadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run usbimportbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run usbloadimage; then " \ + "run usbloados;" \ + "fi;" \ + "fi;\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run mmcloados;" \ + "fi;" \ + "fi;\0" \ + "spiboot=echo Booting from spi ...; " \ + "run spiargs; " \ + "sf probe ${spibusno}:0; " \ + "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \ + "bootz ${loadaddr}\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "tftp ${fdtaddr} ${fdtfile}; " \ + "run netargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "ramboot=echo Booting from ramdisk ...; " \ + "run ramargs; " \ + "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ + "findfdt=setenv fdtfile am335x-baltos.dtb\0" \ + NANDARGS + /*DFUARGS*/ +#endif + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run usbboot;" \ + "run mmcboot;" \ + "setenv mmcdev 1; " \ + "setenv bootpart 1:2; " \ + "run mmcboot;" \ + "run nandboot;" + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ + +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* PMIC support */ +#define CONFIG_POWER_TPS65910 + +/* SPL */ +#ifndef CONFIG_NOR_BOOT + +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#endif +#endif + +/* + * USB configuration. We enable MUSB support, both for host and for + * gadget. We set USB0 as peripheral and USB1 as host, based on the + * board schematic and physical port wired to each. Then for host we + * add mass storage support and for gadget we add both RNDIS ethernet + * and DFU. + */ +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_HOST +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_OTG + +/* NAND support */ +#ifdef CONFIG_MTD_RAW_NAND +#define GPMC_NAND_ECC_LP_x8_LAYOUT 1 +#endif + +#endif /* ! __CONFIG_BALTOS_H */ diff --git a/roms/u-boot/include/configs/bayleybay.h b/roms/u-boot/include/configs/bayleybay.h new file mode 100644 index 000000000..0198051bc --- /dev/null +++ b/roms/u-boot/include/configs/bayleybay.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015, Bin Meng + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +/* Environment configuration */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/bcm7260.h b/roms/u-boot/include/configs/bcm7260.h new file mode 100644 index 000000000..f72d62ec3 --- /dev/null +++ b/roms/u-boot/include/configs/bcm7260.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 Cisco Systems, Inc. + * + * Author: Thomas Fitzsimmons + * + * Configuration settings for the Broadcom BCM7260 SoC family. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_NS16550_COM1 0xf040c000 + +#define CONFIG_SYS_TEXT_BASE 0x10100000 +#define CONFIG_SYS_INIT_RAM_ADDR 0x10200000 + +#define CONFIG_SYS_MALLOC_LEN ((40 * 1024) << 10) /* 40 MiB */ + +#include "bcmstb.h" + +#define BCMSTB_TIMER_LOW 0xf0412008 +#define BCMSTB_TIMER_HIGH 0xf041200c +#define BCMSTB_TIMER_FREQUENCY 0xf0412020 +#define BCMSTB_HIF_MSPI_BASE 0xf0203c00 +#define BCMSTB_BSPI_BASE 0xf0203a00 +#define BCMSTB_HIF_SPI_INTR2 0xf0201a00 +#define BCMSTB_CS_REG 0xf0200920 + +/* + * Environment configuration for eMMC. + */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/bcm7445.h b/roms/u-boot/include/configs/bcm7445.h new file mode 100644 index 000000000..ce865cb45 --- /dev/null +++ b/roms/u-boot/include/configs/bcm7445.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 Cisco Systems, Inc. + * + * Author: Thomas Fitzsimmons + * + * Configuration settings for the Broadcom BCM7445 SoC family. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_NS16550_COM1 0xf040ab00 + +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_INIT_RAM_ADDR 0x80200000 + +#define CONFIG_SYS_MALLOC_LEN ((10 * 1024) << 10) /* 10 MiB */ + +#include "bcmstb.h" + +#define BCMSTB_TIMER_LOW 0xf0412008 +#define BCMSTB_TIMER_HIGH 0xf041200c +#define BCMSTB_TIMER_FREQUENCY 0xf0412020 +#define BCMSTB_HIF_MSPI_BASE 0xf03e3400 +#define BCMSTB_BSPI_BASE 0xf03e3200 +#define BCMSTB_HIF_SPI_INTR2 0xf03e1a00 +#define BCMSTB_CS_REG 0xf03e0920 + +/* + * Environment configuration for SPI flash. + */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/bcm_ns3.h b/roms/u-boot/include/configs/bcm_ns3.h new file mode 100644 index 000000000..14275abdc --- /dev/null +++ b/roms/u-boot/include/configs/bcm_ns3.h @@ -0,0 +1,819 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Broadcom. + * + */ + +#ifndef __BCM_NS3_H +#define __BCM_NS3_H + +#include + +#define CONFIG_HOSTNAME "NS3" + +/* Physical Memory Map */ +#define V2M_BASE 0x80000000 +#define PHYS_SDRAM_1 V2M_BASE + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x80000) + +/* + * Initial SP before reloaction is placed at end of first DRAM bank, + * which is 0x1_0000_0000. + * Just before re-loaction, new SP is updated and re-location happens. + * So pointing the initial SP to end of 2GB DDR is not a problem + */ +#define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x80000000) +/* 12MB Malloc size */ +#define CONFIG_SYS_MALLOC_LEN (SZ_8M + SZ_4M) + +/* console configuration */ +#define CONFIG_SYS_NS16550_CLK 25000000 + +#define CONFIG_SYS_CBSIZE SZ_1K +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * Increase max uncompressed/gunzip size, keeping size same as EMMC linux + * partition. + */ +#define CONFIG_SYS_BOOTM_LEN 0x01800000 + +/* Access eMMC Boot_1 and Boot_2 partitions */ +#define CONFIG_SUPPORT_EMMC_BOOT + +/* enable 64-bit PCI resources */ +#define CONFIG_SYS_PCI_64BIT 1 + +#define CONSOLE_ARGS "console_args=console=ttyS0,115200n8\0" +#define MAX_CPUS "max_cpus=maxcpus=8\0" +#define OS_LOG_LEVEL "log_level=loglevel=7\0" +#define EXTRA_ARGS "extra_args=earlycon=uart8250,mmio32,0x68A10000 " \ + "earlyelog=" __stringify(ELOG_AP_UART_LOG_BASE) ",0x10000 " \ + "crashkernel=512M reboot=w\0" + +#define PCIE_ARGS "pcie_args=pci=pcie_bus_safe pcie_ports=native vfio_pci.disable_idle_d3=1\0" + +#ifdef CONFIG_BCM_SF2_ETH +#define ETH_ADDR "ethaddr=00:0A:F7:95:65:A4\0" +#define NET_ARGS "bgmac_platform.ethaddr=${ethaddr} " \ + "ip=${ipaddr}::${gatewayip}:${netmask}::${ethif}:off" +#else +#define ETH_ADDR +#define NET_ARGS +#endif + +#define RESERVED_MEM "reserved_mem=memmap=0xff000000$0x1000000\0" + +#define BASE_ARGS "${console_args} ${extra_args} ${pcie_args}" \ + " ${max_cpus} ${log_level} ${reserved_mem}" +#define SETBOOTARGS "setbootargs=setenv bootargs " BASE_ARGS " " NET_ARGS "\0" + +#define UPDATEME_FLASH_PARAMS "bcm_compat_level=4\0" \ + "bcm_need_recovery_rootfs=0\0" \ + "bcm_bl_flash_pending_rfs_imgs=0\0" + +#define KERNEL_LOADADDR_CFG \ + "fit_image_loadaddr=0x90000000\0" \ + "dtb_loadaddr=0x82000000\0" + +#define INITRD_ARGS "initrd_args=root=/dev/ram rw\0" +#define INITRD_LOADADDR "initrd_loadaddr=0x92000000\0" +#define INITRD_IMAGE "initrd_image=rootfs-lake-bcm958742t.cpio.gz\0" +#define MMC_DEV "sd_device_number=0\0" +#define EXEC_STATE "exec_state=normal\0" + +#define EXT4RD_ARGS "ext4rd_args="\ + "root=/dev/mmcblk${sd_device_number}p${gpt_partition_entry} rw rootwait\0" + +#define WDT_CNTRL "wdt_enable=1\0" \ + "wdt_timeout_sec=0\0" + +#define ELOG_SETUP \ + "mbox0_addr=0x66424024\0"\ + "elog_setup="\ + "if logsetup -s ${mbox0_addr}; then "\ + "else "\ + "echo ELOG is not supported by this version of the MCU patch.;"\ + "exit;"\ + "fi;"\ + "if logsetup -c ${mbox0_addr}; then "\ + "echo ELOG is ready;"\ + "else "\ + "echo ELOG is supported, but is not set up.;"\ + "echo Getting setup file from the server ${serverip}...;"\ + "if tftp ${tftp_dir}elog_src.txt; then "\ + "echo Setting up ELOG. Please wait...;"\ + "if logsetup ${loadaddr} ${mbox0_addr} ${filesize}; "\ + "then "\ + "else "\ + "echo [logsetup] ERROR.;"\ + "fi;"\ + "if logsetup -c ${mbox0_addr}; then "\ + "echo ELOG is READY.;"\ + "else "\ + "echo ELOG is NOT SET UP.;"\ + "fi;"\ + "else "\ + "echo ELOG setup file is not available on the server.;"\ + "fi;"\ + "fi \0" + +/* eMMC partition for FIT images */ +#define FIT_MMC_PARTITION \ + "fit_partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=env,size=512K,uuid=${uuid_gpt_env};" \ + "name=Image_rsa.img,size=24MiB,uuid=${uuid_gpt_linux};" \ + "name=Image1_rsa.img,size=24MiB,uuid=${uuid_gpt_linux1};" \ + "name=Image2_rsa.img,size=24MiB,uuid=${uuid_gpt_linux2};" \ + "name=nitro,size=8MiB,uuid=${uuid_gpt_nitro};" \ + "name=recovery,size=940MiB,uuid=${uuid_gpt_recovery};" \ + "name=rootfs,size=-,uuid=${uuid_gpt_prootfs}\0" + +#define QSPI_FLASH_NITRO_PARAMS \ + "spi_nitro_img_bin_start=0x400000\0" \ + "spi_nitro_img_bin_mirror_start=0x580000\0" \ + "spi_nitro_bspd_cfg_start=0x700000\0" \ + "spi_nitro_bspd_mirror_cfg_start=0x710000\0" \ + +#define QSPI_ACCESS_ENABLE \ + "qspi_access_en=" \ + "mw 0x68a403e8 1;" \ + "mw 0x68a403ec 1;" \ + "mw 0x68a403f0 1;" \ + "mw 0x68a403f4 1;" \ + "mw 0x68a403f8 1;" \ + "mw 0x68a403fc 1 \0" + +#define FUNC_QSPI_PROBE \ + "func_qspi_probe="\ + "if run qspi_access_en; then "\ + "else "\ + "echo ${errstr} run qspi_access_en ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if sf probe 0; then "\ + "else "\ + "echo echo ${errstr} sf probe command ** FAILED **;"\ + "exit;"\ + "fi \0" + +#define NITRO_FW_IMAGES \ + "nitro_bin=nitro.img\0" \ + "nitro_bspd_cfg=nitro_fb_bspd_config.bin\0" + +#define FASTBOOT_NITRO_SETUP \ + "nitro_fastboot_type=1\0" \ + "nitro_fastboot_secure=1\0" \ + "nitro_fastboot_img_buffer=0\0" \ + "nitro_fit_img_loc=0x90000000\0" + +#define FASTBOOT_SETUP \ + "fastboot_nitro_setup=" \ + "setenv errstr fastboot_setup;" \ + "run func_qspi_probe;" \ + /* first load header only */ \ + "if sf read ${nitro_fit_img_loc} "\ + "${spi_nitro_img_bin_start} 0x18; then "\ + "else "\ + "echo [fastboot_nitro_setup] sf read "\ + "${spi_nitro_img_bin_start} ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if spi_nitro_images_addr ${nitro_fit_img_loc} "\ + "${spi_nitro_img_bin_start}; then "\ + "else "\ + "echo [fastboot_nitro_setup] spi_nitro_images_addr "\ + "** FAILED **;"\ + "exit;"\ + "fi \0" + +#define CHECK_CHIMP_HS\ + "check_chimp_hs=chimp_hs"\ + "\0" + +#define FASTBOOT_NITRO "fastboot_nitro=chimp_ld_secure\0" + +#define FIT_IMAGE "fit_image=Image_rsa.img\0" +#define BOOTCMD_MMC_FIT \ + "bootcmd_mmc_fit="\ + "mmc dev ${sd_device_number};"\ + "if test $exec_state = normal; then " \ + "setenv use_rootfs rootfs;"\ + "else " \ + "setenv use_rootfs recovery;"\ + "fi;" \ + "echo used filesystem :${use_rootfs};"\ + "gpt setenv mmc ${sd_device_number} ${use_rootfs};"\ + "setenv bootargs_fs ${setbootargs} ${ext4rd_args}; run bootargs_fs;"\ + "gpt setenv mmc ${sd_device_number} ${fit_image};"\ + "mmc read ${fit_image_loadaddr} ${gpt_partition_addr} "\ + "${gpt_partition_size};"\ + "bootm ${fit_image_loadaddr}\0" + +#define BOOTCMD_MMC_FITS \ + "bootcmd_mmc_fits="\ + "setenv mmc_fit0 " \ + "'setenv fit_image Image_rsa.img; run bootcmd_mmc_fit';"\ + "setenv mmc_fit1 " \ + "'setenv fit_image Image1_rsa.img; run bootcmd_mmc_fit';"\ + "setenv mmc_fit2 " \ + "'setenv fit_image Image2_rsa.img; run bootcmd_mmc_fit';"\ + "run mmc_fit0 || run mmc_fit1 || run mmc_fit2\0" + +#define USBDEV "usbdev=0\0" +#define BOOTCMD_USB\ + "bootcmd_usb="\ + "setenv usb_image_loadaddr 90000000;"\ + "setenv fit_image Image_rsa.img;"\ + "setenv bootargs_fs ${setbootargs} ${initrd_args}; run bootargs_fs;"\ + "if usb dev ${usbdev}; && usb start; then "\ + "echo Booting from USB...;"\ + "fatload usb ${usbdev} ${usb_image_loadaddr} ${fit_image};"\ + "fatload usb ${usbdev} ${initrd_loadaddr} ${initrd_image};"\ + "bootm ${usb_image_loadaddr} ${initrd_loadaddr}:${filesize};"\ + "fi;"\ + "\0" + +#define START_PCI\ + "start_pci=pci e "\ + "\0" + +#define BNXT_LOAD\ + "bnxt_load=bnxt 0 probe "\ + "\0" + +#define BOOTCMD_PXE\ + "bootcmd_pxe="\ + "run check_chimp_hs && "\ + "run start_pci && "\ + "run bnxt_load;"\ + "setenv ethact bnxt_eth0;"\ + "setenv autoload no;"\ + "setenv bootargs_fs ${setbootargs} ${initrd_args}; run bootargs_fs;"\ + "if dhcp; then "\ + "setenv pxefile_addr_r ${loadaddr};"\ + "if pxe get; then "\ + "setenv ramdisk_addr_r ${initrd_loadaddr};"\ + "setenv kernel_addr_r ${fit_image_loadaddr};"\ + "pxe boot; "\ + "fi;"\ + "fi;"\ + "\0" + +#define FLASH_PENDING_RFS_IMGS \ + "flash_pending_rfs_imgs=" \ + "if test $bcm_bl_flash_pending_rfs_imgs = 1; then " \ + "if test $bl_flash_pending_rfs_imgs = rootfs; then " \ + "dhcp;" \ + "run mmc_flash_rootfs;" \ + "fi;" \ + "if test $bl_flash_pending_rfs_imgs = recovery; then " \ + "dhcp;" \ + "run mmc_flash_recovery;" \ + "fi;" \ + "setenv bl_flash_pending_rfs_imgs;" \ + "fi; \0" + +#define CONFIG_BOOTCOMMAND "run flash_pending_rfs_imgs;" \ + "run fastboot_nitro && "\ + "run bootcmd_mmc_fits || "\ + "run bootcmd_usb || "\ + "run bootcmd_pxe" + +/* Flashing commands */ +#define TFTP_QSPI_PARAM \ + "fip_qspi_addr=0x0\0"\ + "fip_qspi_mirror_addr=0x200000\0"\ + "loadaddr=0x90000000\0"\ + "tftpblocksize=1468\0"\ + "qspi_flash_fip=fip\0"\ + +/* Flash fit_GPT partition to eMMC */ +#define MMC_FLASH_FIT_GPT \ + "mmc_flash_gpt="\ + "if mmc dev ${sd_device_number}; then "\ + "else "\ + "echo [mmc_flash_gpt] mmc dev ${sd_device_number} "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if gpt write mmc ${sd_device_number} ${fit_partitions}; then "\ + "else "\ + "echo [mmc_flash_gpt] gpt write ${fit_partitions} "\ + "** FAILED **;"\ + "exit;"\ + "fi \0" + +#define MMC_FLASH_IMAGE_RSA \ + "mmc_flash_image_rsa="\ + "if mmc dev ${sd_device_number}; then "\ + "else "\ + "echo [mmc_flash_image_rsa] mmc dev ${sd_device_number} "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if gpt setenv mmc ${sd_device_number} ${fit_image}; then "\ + "else "\ + "echo [mmc_flash_image_rsa] gpt setenv ${fit_image} "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if tftp ${loadaddr} ${tftp_dir}${fit_image}; then "\ + "if test ${fit_image} = Image_rsa.img; then "\ + "if setenv tftp_fit_image yes; then "\ + "else "\ + "echo [mmc_flash_image_rsa] "\ + "setenv tftp_fit_image to yes"\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "fi;"\ + "else "\ + "if test ${fit_image} = Image_rsa.img; then "\ + "echo [mmc_flash_image_rsa] tftp "\ + "${tftp_dir}${fit_image} ** FAILED **;"\ + "else "\ + "if test ${tftp_fit_image} = yes; then "\ + "if mmc write ${loadaddr} "\ + "${gpt_partition_addr} "\ + "${fileblocks}; then "\ + "else "\ + "echo "\ + "[mmc_flash_image_rsa] "\ + "mmc write "\ + "${gpt_partition_addr} "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "else "\ + "echo [mmc_flash_image_rsa] tftp "\ + "${tftp_dir}${fit_image} "\ + "** FAILED **;"\ + "fi;"\ + "fi;"\ + "exit;"\ + "fi;"\ + "if math add filesize filesize 1FF; then "\ + "else "\ + "echo [mmc_flash_image_rsa] math add command ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if math div fileblocks filesize 200; then "\ + "else "\ + "echo [mmc_flash_image_rsa] math div command ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if mmc write ${loadaddr} ${gpt_partition_addr} ${fileblocks}; then "\ + "else "\ + "echo [mmc_flash_image_rsa] mmc write ${gpt_partition_addr} "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if setenv image_sz_blk_cnt ${fileblocks}; then "\ + "else "\ + "echo [mmc_flash_image_rsa] setenv image_sz_blk_cnt ** "\ + "FAILED **;"\ + "exit;"\ + "fi;"\ + "if saveenv; then "\ + "else "\ + "echo [mmc_flash_image_rsa] saveenv command ** FAILED **;"\ + "exit;"\ + "fi \0" + +#define MMC_FLASH_RECOVERY \ + "mmc_flash_recovery="\ + "if mmc dev ${sd_device_number}; then "\ + "else "\ + "echo [mmc_flash_recovery] mmc dev ${sd_device_number} "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if gpt setenv mmc ${sd_device_number} recovery; then "\ + "else "\ + "echo [mmc_flash_recovery] gpt setenv recovery ** FAILED **;"\ + "exit;"\ + "fi;"\ + "setenv index 1;"\ + "while tftp ${loadaddr} "\ + "${tftp_dir}${gpt_partition_name}/chunk_00${index}; do "\ + "if math add filesize filesize 1FF; then "\ + "else "\ + "echo [mmc_flash_recovery] math add command "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if math div fileblocks filesize 200; then "\ + "else "\ + "echo [mmc_flash_recovery] math div command "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if mmc write ${loadaddr} ${gpt_partition_addr} "\ + "${fileblocks}; then "\ + "else "\ + "echo [mmc_flash_recovery] mmc write "\ + "${gpt_partition_addr} ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if math add index index 1; then "\ + "else "\ + "echo [mmc_flash_recovery] math add command "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if math add gpt_partition_addr gpt_partition_addr"\ + " ${fileblocks}; then "\ + "else "\ + "echo [mmc_flash_recovery] math add command"\ + " ** FAILED **;"\ + "exit;"\ + "fi;"\ + "done;"\ + "if itest ${index} -ne 1; then "\ + "else "\ + "echo [mmc_flash_recovery] "\ + "${tftp_dir}${gpt_partition_name}/chunk_00${index} file "\ + "not found ** FAILED **;"\ + "exit;"\ + "fi \0" + +#define MMC_FLASH_ROOTFS \ + "mmc_flash_rootfs="\ + "if mmc dev ${sd_device_number}; then "\ + "else "\ + "echo [mmc_flash_rootfs] mmc dev ${sd_device_number} "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if gpt setenv mmc ${sd_device_number} rootfs; then "\ + "else "\ + "echo [mmc_flash_rootfs] gpt setenv rootfs ** FAILED **;"\ + "exit;"\ + "fi;"\ + "setenv index 1;"\ + "while tftp ${loadaddr} "\ + "${tftp_dir}${gpt_partition_name}/chunk_00${index}; do "\ + "if math add filesize filesize 1FF; then "\ + "else "\ + "echo [mmc_flash_rootfs] math add command "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if math div fileblocks filesize 200; then "\ + "else "\ + "echo [mmc_flash_rootfs] math div command "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if mmc write ${loadaddr} ${gpt_partition_addr} "\ + "${fileblocks}; then "\ + "else "\ + "echo [mmc_flash_rootfs] mmc write "\ + "${gpt_partition_addr} ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if math add index index 1; then "\ + "else "\ + "echo [mmc_flash_rootfs] math add command "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if math add gpt_partition_addr gpt_partition_addr"\ + " ${fileblocks}; then "\ + "else "\ + "echo [mmc_flash_rootfs] math add command"\ + " ** FAILED **;"\ + "exit;"\ + "fi;"\ + "done;"\ + "if itest ${index} -ne 1; then "\ + "else "\ + "echo [mmc_flash_rootfs] "\ + "${tftp_dir}${gpt_partition_name}/chunk_00${index} file "\ + "not found ** FAILED **;"\ + "exit;"\ + "fi \0" + +/* + * For individual flash commands like mmc_flash_gpt, it is not + * necessary to check for errors. + * If any of its intermediate commands fails, then next commands + * will not execute. Script will exit from the failure command. + * For uniformity, checking for mmc_flash_gpt, mmc_flash_image_rsa + * mmc_flash_nitro and mmc_flash_rootfs + */ +#define MMC_FLASH \ + "flash_mmc="\ + "if run mmc_flash_gpt; then "\ + "else "\ + "echo [flash_mmc] run mmc_flash_gpt ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if setenv tftp_fit_image no; then "\ + "else "\ + "echo [flash_mmc] setenv tftp_fit_image to no "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if setenv fit_image Image_rsa.img; then "\ + "else "\ + "echo [flash_mmc] setenv fit_image to Image_rsa.img "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if run mmc_flash_image_rsa; then "\ + "else "\ + "echo [flash_mmc] run mmc_flash_image_rsa ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if setenv fit_image Image1_rsa.img; then "\ + "else "\ + "echo [flash_mmc] setenv fit_image to Image1_rsa.img "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if run mmc_flash_image_rsa; then "\ + "else "\ + "echo [flash_mmc] run mmc_flash_image_rsa "\ + "for Image1_rsa.img ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if setenv fit_image Image2_rsa.img; then "\ + "else "\ + "echo [flash_mmc] setenv fit_image to Image2_rsa.img "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if run mmc_flash_image_rsa; then "\ + "else "\ + "echo [flash_mmc] run mmc_flash_image_rsa "\ + "for Image2_rsa.img ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if run mmc_flash_recovery; then "\ + "else "\ + "echo [flash_mmc] run mmc_flash_recovery ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if run mmc_flash_rootfs; then "\ + "else "\ + "echo [flash_mmc] run mmc_flash_rootfs ** FAILED **;"\ + "exit;"\ + "fi \0" + +#define FUNC_ALIGN_QSPI_ERASE_BLOCK_SIZE \ + "align_erase_blk_size=" \ + "setenv fl_write_size 0;" \ + "if math add fl_write_size filesize FFFF; then "\ + "else "\ + "echo ${errstr} math add command ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if math div fl_write_size fl_write_size 10000; then "\ + "else "\ + "echo ${errstr} math div command ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if math mul fl_write_size fl_write_size 10000; then "\ + "else "\ + "echo ${errstr} math mul command ** FAILED **;"\ + "exit;"\ + "fi \0" + +#define QSPI_FLASH_FIP \ + "flash_fip="\ + "if run qspi_access_en; then "\ + "else "\ + "echo [flash_fip] run qspi_access_en ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if tftp ${loadaddr} ${tftp_dir}fip.bin; then "\ + "else "\ + "echo [flash_fip] tftp ${tftp_dir}fip.bin "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if math add tmpsize filesize FFFF; then "\ + "else "\ + "echo [flash_fip] math add command ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if math div tmpsize tmpsize 10000; then "\ + "else "\ + "echo [flash_fip] math div command ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if math mul tmpsize tmpsize 10000; then "\ + "else "\ + "echo [flash_fip] math mul command ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if sf probe 0; then "\ + "else "\ + "echo [flash_fip] sf probe command ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if sf erase ${fip_qspi_addr} ${tmpsize}; then "\ + "else "\ + "echo [flash_fip] sf erase ${fip_qspi_addr} ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if sf write ${loadaddr} ${fip_qspi_addr} ${filesize}; then "\ + "else "\ + "echo [flash_fip] sf write ${fip_qspi_addr} ** FAILED **;"\ + "exit;"\ + "fi;"\ + /* Flash mirror FIP image */ \ + "if sf erase ${fip_qspi_mirror_addr} ${tmpsize}; then "\ + "else "\ + "echo [flash_fip] sf erase ${fip_qspi_mirror_addr} "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if sf write ${loadaddr} ${fip_qspi_mirror_addr} ${filesize}; then "\ + "else "\ + "echo [flash_fip] sf write ${fip_qspi_mirror_addr} "\ + "** FAILED **;"\ + "exit;"\ + "fi \0" + +#define QSPI_FLASH_NITRO \ + "flash_nitro="\ + "run func_qspi_probe; "\ + "if tftp ${loadaddr} ${tftp_dir}${nitro_bin}; then "\ + "else "\ + "echo [flash_nitro] tftp ${tftp_dir}${nitro_bin} "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "setenv errstr flash_nitro;" \ + "run align_erase_blk_size;" \ + /* Flash Nitro fw fit + configuration */ \ + "if sf erase ${spi_nitro_img_bin_start} ${fl_write_size}; then "\ + "else "\ + "echo [flash_nitro] sf erase ${spi_nitro_img_bin_start} "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if sf write ${loadaddr} ${spi_nitro_img_bin_start}" \ + " ${fl_write_size}; then "\ + "else "\ + "echo [flash_nitro] sf write ${spi_nitro_bin_start} "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + /* Mirror of Flash Nitro fw fit + configuration */ \ + "if sf erase ${spi_nitro_img_bin_mirror_start} ${fl_write_size}; then "\ + "else "\ + "echo [flash_nitro] sf erase "\ + "${spi_nitro_img_bin_mirror_start} "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if sf write ${loadaddr} ${spi_nitro_img_bin_mirror_start}" \ + " ${fl_write_size}; then "\ + "else "\ + "echo [flash_nitro] sf write "\ + "${spi_nitro_img_bin_mirror_start} "\ + "** FAILED **;"\ + "exit;"\ + "fi \0" + +#define QSPI_FLASH_NITRO_BSPD_CONFIG \ + "flash_nitro_bspd_config="\ + "run func_qspi_probe; "\ + /* Flash BSPD configuration */ \ + "if tftp ${loadaddr} ${tftp_dir}${nitro_bspd_cfg}; then "\ + "setenv bspd_cfg_avialable 1; "\ + "setenv errstr flash_nitro_bspd_config; "\ + "run align_erase_blk_size;" \ + "if sf erase ${spi_nitro_bspd_cfg_start} "\ + "${fl_write_size}; then "\ + "else "\ + "echo [flash_nitro] sf erase "\ + "${spi_nitro_bspd_cfg_start} "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if sf write ${loadaddr} ${spi_nitro_bspd_cfg_start} "\ + "${fl_write_size}; then "\ + "else "\ + "echo [flash_nitro] sf write "\ + "${spi_nitro_bspd_cfg_start} "\ + "** FAILED **;"\ + "exit;"\ + "fi;" \ + /* Flash BSPD mirror configuration */ \ + "if sf erase ${spi_nitro_bspd_mirror_cfg_start} "\ + "${fl_write_size}; then "\ + "else "\ + "echo [flash_nitro] sf erase "\ + "${spi_nitro_bspd_mirror_cfg_start} "\ + "** FAILED **;"\ + "exit;"\ + "fi;"\ + "if sf write ${loadaddr} ${spi_nitro_bspd_mirror_cfg_start} "\ + "${fl_write_size}; then "\ + "else "\ + "echo [flash_nitro] sf write "\ + "${spi_nitro_bspd_mirror_cfg_start} "\ + "** FAILED **;"\ + "exit;"\ + "fi;" \ + "else "\ + "echo [flash_nitro] tftp ${tftp_dir}${nitro_bspd_cfg} "\ + "** Skip flashing bspd config file **;"\ + "fi \0" + +#define QSPI_FLASH \ + "flash_qspi="\ + "if run qspi_access_en; then "\ + "else "\ + "echo [flash_qspi] run qspi_access_en ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if run flash_fip; then "\ + "else "\ + "echo [flash_qspi] run flash_fip ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if run flash_nitro; then "\ + "else "\ + "echo [flash_qspi] run flash_nitro ** FAILED **;"\ + "exit;"\ + "fi \0" + +#define FLASH_IMAGES \ + "flash_images=" \ + "if run flash_qspi; then "\ + "else "\ + "echo [flash_images] run flash_qspi ** FAILED **;"\ + "exit;"\ + "fi;"\ + "if run flash_mmc; then "\ + "else "\ + "echo [flash_images] run flash_mmc ** FAILED **;"\ + "exit;"\ + "fi \0" + +#define ARCH_ENV_SETTINGS \ + CONSOLE_ARGS \ + MAX_CPUS \ + OS_LOG_LEVEL \ + EXTRA_ARGS \ + PCIE_ARGS \ + ETH_ADDR \ + RESERVED_MEM \ + SETBOOTARGS \ + UPDATEME_FLASH_PARAMS \ + KERNEL_LOADADDR_CFG\ + INITRD_ARGS \ + INITRD_LOADADDR \ + INITRD_IMAGE \ + MMC_DEV \ + EXEC_STATE \ + EXT4RD_ARGS \ + WDT_CNTRL \ + ELOG_SETUP \ + FIT_MMC_PARTITION \ + QSPI_FLASH_NITRO_PARAMS \ + QSPI_ACCESS_ENABLE \ + FUNC_QSPI_PROBE \ + NITRO_FW_IMAGES \ + FASTBOOT_NITRO_SETUP \ + FASTBOOT_SETUP \ + CHECK_CHIMP_HS \ + FASTBOOT_NITRO \ + FIT_IMAGE \ + BOOTCMD_MMC_FIT \ + BOOTCMD_MMC_FITS \ + USBDEV \ + BOOTCMD_USB \ + START_PCI \ + BNXT_LOAD \ + BOOTCMD_PXE \ + FLASH_PENDING_RFS_IMGS \ + TFTP_QSPI_PARAM \ + MMC_FLASH_FIT_GPT \ + MMC_FLASH_IMAGE_RSA \ + MMC_FLASH_RECOVERY \ + MMC_FLASH_ROOTFS \ + MMC_FLASH \ + FUNC_ALIGN_QSPI_ERASE_BLOCK_SIZE \ + QSPI_FLASH_FIP \ + QSPI_FLASH_NITRO \ + QSPI_FLASH_NITRO_BSPD_CONFIG \ + QSPI_FLASH \ + FLASH_IMAGES + +#define CONFIG_EXTRA_ENV_SETTINGS \ + ARCH_ENV_SETTINGS + +#endif /* __BCM_NS3_H */ diff --git a/roms/u-boot/include/configs/bcmstb.h b/roms/u-boot/include/configs/bcmstb.h new file mode 100644 index 000000000..2660d18f3 --- /dev/null +++ b/roms/u-boot/include/configs/bcmstb.h @@ -0,0 +1,162 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 Cisco Systems, Inc. + * + * Author: Thomas Fitzsimmons + * + * Configuration settings for the Broadcom BCMSTB SoC family. + */ + +#ifndef __BCMSTB_H +#define __BCMSTB_H + +#include "version.h" +#include + +#ifndef __ASSEMBLY__ + +#include +#include + +struct bcmstb_boot_parameters { + u32 r0; + u32 r1; + u32 r2; + u32 r3; + u32 sp; + u32 lr; +}; + +extern struct bcmstb_boot_parameters bcmstb_boot_parameters; + +extern phys_addr_t prior_stage_fdt_address; + +#endif /* __ASSEMBLY__ */ + +/* + * CPU configuration. + */ +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* + * Memory configuration. + * + * The prior stage BOLT bootloader sets up memory for us. + * + * An example boot memory layout after loading everything is: + * + * 0x0000 8000 vmlinux.bin.gz + * : [~31 MiB uncompressed max] + * 0x01ef f000 FIT containing signed public key + * : [~2 KiB in size] + * 0x01f0 0000 DTB copied from prior-stage-provided region + * : [~1 MiB max] + * 0x0200 0000 FIT containing ramdisk and device tree + * : initramfs.cpio.gz + * : [~208 MiB uncompressed max, to CMA/bmem low address] + * : [~80 MiB compressed max, to PSB low address] + * : device tree binary + * : [~60 KiB] + * 0x0700 0000 Prior stage bootloader (PSB) + * : + * 0x0761 7000 Prior-stage-provided device tree binary (DTB) + * : [~40 KiB in size] + * 0x0f00 0000 Contiguous memory allocator (CMA/bmem) low address + * : + * 0x8010 0000 U-Boot code at ELF load address + * : [~500 KiB in size, stripped] + * 0xc000 0000 Top of RAM + * + * Setting gd->relocaddr to CONFIG_SYS_TEXT_BASE in dram_init_banksize + * prevents U-Boot from relocating itself when it is run as an ELF + * program by the prior stage bootloader. + * + * We want to keep the ramdisk and FDT in the FIT image in-place, to + * accommodate stblinux's bmem and CMA regions. To accomplish this, + * we set initrd_high and fdt_high to 0xffffffff, and the load and + * entry addresses of the FIT ramdisk entry to 0x0. + * + * Overwriting the prior stage bootloader causes memory instability, + * so the compressed initramfs needs to fit between the load address + * and the PSB low address. In BOLT's default configuration this + * limits the compressed size of the initramfs to approximately 80 + * MiB. However, BOLT can be configured to allow loading larger + * initramfs images, in which case this limitation is eliminated. + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_LOAD_ADDR 0x2000000 + +/* + * CONFIG_SYS_LOAD_ADDR - 1 MiB. + */ +#define CONFIG_SYS_FDT_SAVE_ADDRESS 0x1f00000 +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 32 + +/* + * Large kernel image bootm configuration. + */ +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* + * NS16550 configuration. + */ +#define V_NS16550_CLK 81000000 + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * Serial console configuration. + */ +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ + 115200} + +/* + * Informational display configuration. + */ +#define CONFIG_REVISION_TAG + +/* + * Command configuration. + */ + +/* + * Flash configuration. + */ +#define CONFIG_ST_SMI +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_MACRONIX + +/* + * Filesystem configuration. + */ +#define CONFIG_DOS_PARTITION + +/* + * Environment configuration. + */ + +/* + * Save the prior stage provided DTB. + */ +/* + * Enable in-place RFS with this initrd_high setting. + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdtsaveaddr=" __stringify(CONFIG_SYS_FDT_SAVE_ADDRESS) "\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_high=0xffffffff\0" + +/* + * Set fdtaddr to prior stage-provided DTB in board_late_init, when + * writeable environment is available. + */ + +#endif /* __BCMSTB_H */ diff --git a/roms/u-boot/include/configs/beacon-rzg2m.h b/roms/u-boot/include/configs/beacon-rzg2m.h new file mode 100644 index 000000000..18d442e06 --- /dev/null +++ b/roms/u-boot/include/configs/beacon-rzg2m.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Compass Electronics Group, LLC + */ + +#ifndef __BEACON_RZG2M_H +#define __BEACON_RZG2M_H + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_BITBANGMII_MULTI + +#undef CONFIG_EXTRA_ENV_SETTINGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "usb_pgood_delay=2000\0" \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttySC0,115200\0" \ + "fdt_addr=0x48000000\0" \ + "loadaddr=0x48080000\0" \ + "boot_fdt=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcrootpart=2\0" \ + "finduuid=part uuid mmc ${mmcdev}:${mmcrootpart} uuid\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} " \ + " root=PARTUUID=${uuid} rootwait rw ${optargs}\0" \ + "loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run finduuid; run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +#endif /* __BEACON_RZG2M_H */ diff --git a/roms/u-boot/include/configs/beaver.h b/roms/u-boot/include/configs/beaver.h new file mode 100644 index 000000000..0daa20ed5 --- /dev/null +++ b/roms/u-boot/include/configs/beaver.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra30-common.h" + +/* VDD core PMIC */ +#define CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Beaver" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_BEAVER + +/* SPI */ +#define CONFIG_TEGRA_SLINK_CTRLS 6 +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/bg0900.h b/roms/u-boot/include/configs/bg0900.h new file mode 100644 index 000000000..b54123636 --- /dev/null +++ b/roms/u-boot/include/configs/bg0900.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Marek Vasut + */ +#ifndef __CONFIGS_BG0900_H__ +#define __CONFIGS_BG0900_H__ + +/* Memory configuration */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Environment */ + +/* FEC Ethernet on SoC */ +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#endif + +/* Boot Linux */ +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTCOMMAND "bootm" +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Extra Environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "update_spi_firmware_filename=u-boot.sb\0" \ + "update_spi_firmware_maxsz=0x80000\0" \ + "update_spi_firmware=" /* Update the SPI flash firmware */ \ + "if sf probe 2:0 ; then " \ + "if tftp ${update_spi_firmware_filename} ; then " \ + "sf erase 0x0 +${filesize} ; " \ + "sf write ${loadaddr} 0x0 ${filesize} ; " \ + "fi ; " \ + "fi\0" + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_BG0900_H__ */ diff --git a/roms/u-boot/include/configs/bitmain_antminer_s9.h b/roms/u-boot/include/configs/bitmain_antminer_s9.h new file mode 100644 index 000000000..a9f45f192 --- /dev/null +++ b/roms/u-boot/include/configs/bitmain_antminer_s9.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2018 Michal Simek + */ + +#ifndef __CONFIG_BITMAIN_ANTMINER_S9_H +#define __CONFIG_BITMAIN_ANTMINER_S9_H + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 + +#define CONFIG_BOOTP_SERVERIP + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ + "pxefile_addr_r=0x2000000\0" \ + "scriptaddr=0x3000000\0" \ + "kernel_addr_r=0x2000000\0" \ + "fdt_high=0xefff000\0" \ + "initrd_high=0xefff000\0" \ + "devnum=0\0" \ + "wdstop=mw f8005000 ABC000\0" \ + BOOTENV + +#include + +#endif /* __CONFIG_BITMAIN_ANTMINER_S9_H */ diff --git a/roms/u-boot/include/configs/bk4r1.h b/roms/u-boot/include/configs/bk4r1.h new file mode 100644 index 000000000..2abbe7b2b --- /dev/null +++ b/roms/u-boot/include/configs/bk4r1.h @@ -0,0 +1,250 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * Copyright 2016 3ADEV + * Written-by: Albert ARIBAUD + * + * Configuration settings for BK4R1. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Define the BK4r1-specific env commands */ +#define BK4_EXTRA_ENV_SETTINGS \ + "bootlimit=3\0" \ + "eraseuserdata=false\0" \ + "altbootcmd=led 5 on; " \ + "boot\0" \ + "set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \ + "set_gpio102=mw 0x400ff0c4 0x40; mw 0x40048198 0x000011bf\0" \ + "set_gpio96=mw 0x40048180 0x282; mw 0x400ff0c4 0x1\0"\ + "set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0"\ + "set_gpio6=mw 0x40048018 0x282; mw 0x400ff008 0x40\0"\ + "manage_userdata=" MANAGE_USERDATA "\0"\ + "ncenable=true\0"\ + "ncserverip=192.168.0.77\0"\ + "if_netconsole=ping $ncserverip\0"\ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10;" \ + "setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "preboot=" BK4_NET_INIT \ + "if ${ncenable}; then run if_netconsole start_netconsole; fi\0" + +/* BK4r1 boot command sets GPIO103/PTC30 to force USB hub out of reset*/ +#define BK4_BOOTCOMMAND "run set_gpio122; run set_gpio96; sf probe; " \ + "run manage_userdata; " + +/* Enable PREBOOT variable */ + +/* Set ARP_TIMEOUT to 500ms */ +#define CONFIG_ARP_TIMEOUT 500UL + +/* Set ARP_TIMEOUT_COUNT to 3 repetitions */ +#define CONFIG_NET_RETRY_COUNT 5 + +/* BK4r1 net init sets GPIO122/PTE17 to enable Ethernet */ +#define BK4_NET_INIT "run set_gpio122;" + +/* Check if userdata volume shall be erased */ +#define MANAGE_USERDATA "if ${eraseuserdata}; " \ + "then ubi part system; " \ + "ubi remove userdata; " \ + "ubi create userdata; " \ + "ubi detach; " \ + "setenv eraseuserdata false; " \ + "saveenv; " \ + "fi; " + +#include +#include + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* Enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 4 * SZ_1M) + +/* NAND support */ +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define IMX_FEC1_BASE ENET1_BASE_ADDR + +/* QSPI Configs*/ +#ifdef CONFIG_FSL_QSPI +#define FSL_QSPI_FLASH_SIZE (SZ_16M) +#define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SYS_FSL_QSPI_LE +#endif + +#define CONFIG_LOADADDR 0x82000000 + +/* We boot from the gfxRAM area of the OCRAM. */ +#define CONFIG_BOARD_SIZE_LIMIT 520192 + +/* boot command, including the target-defined one if any */ +#define CONFIG_BOOTCOMMAND BK4_BOOTCOMMAND "run bootcmd_nand" + +/* Extra env settings (including the target-defined ones if any) */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BK4_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "blimg_file=u-boot.vyb\0" \ + "blimg_addr=0x81000000\0" \ + "dtbkernel_file=fitImage\0" \ + "dtbkernel_addr=0x82000000\0" \ + "ram_file=uRamdisk\0" \ + "ram_addr=0x83000000\0" \ + "filesys=rootfs.ubifs\0" \ + "sys_addr=0x81000000\0" \ + "nfs_root=/path/to/nfs/root\0" \ + "tftptimeout=1000\0" \ + "tftptimeoutcountmax=1000000\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "ipaddr=192.168.0.60\0" \ + "serverip=192.168.0.1\0" \ + "bootargs_base=setenv bootargs rw " \ + "console=ttyLP1,115200n8\0" \ + "bootargs_sd=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootargs_nand=setenv bootargs ${bootargs} " \ + "ubi.mtd=5 rootfstype=" \ + "ubifs root=ubi0:rootfs${active_workset}\0" \ + "bootargs_ram=setenv bootargs ${bootargs} " \ + "root=/dev/ram rw initrd=${ram_addr}\0" \ + "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \ + "fatload mmc 0:2 ${dtbkernel_addr} ${dtbkernel_file}; " \ + "bootm ${dtbkernel_addr}\0" \ + "bootcmd_nand=sf probe;run bootargs_base bootargs_nand bootargs_mtd; " \ + "ubi part dtbkernel; " \ + "ubi readvol ${dtbkernel_addr} dtbkernel${active_workset}; " \ + "led 0 on; " \ + "bootm ${dtbkernel_addr}\0" \ + "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \ + "nand read ${fdt_addr} dtb; " \ + "nand read ${kernel_addr} kernel; " \ + "nand read ${ram_addr} root; " \ + "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ + "update_bootloader_from_sd=if fatload mmc 0:2 ${blimg_addr} " \ + "${blimg_file}; " \ + "then sf probe; " \ + "mtdparts default; " \ + "nand erase.part bootloader; " \ + "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ + "update_bootloader_from_tftp=if tftp ${blimg_addr} "\ + "${tftpdir}${blimg_file}; "\ + "then sf probe; " \ + "mtdparts default; " \ + "nand erase.part bootloader; " \ + "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ + "update_dtbkernel_from_sd=if fatload mmc 0:2 ${dtbkernel_addr} " \ + "${dtbkernel_file}; " \ + "then sf probe; " \ + "ubi part dtbkernel; " \ + "ubi write ${dtbkernel_addr} dtbkernel${active_workset} " \ + "${filesize}; " \ + "ubi detach; fi\0" \ + "update_dtbkernel_from_tftp=if tftp ${dtbkernel_addr} " \ + "${tftpdir}${dtbkernel_file}; " \ + "then sf probe; " \ + "ubi part dtbkernel; " \ + "ubi write ${dtbkernel_addr} dtbkernel${active_workset} " \ + "${filesize}; " \ + "ubi detach; fi\0" \ + "update_ramdisk_from_sd=if fatload mmc 0:2 ${ram_addr} " \ + "${ram_file}; " \ + "then sf probe; " \ + "mtdparts default; " \ + "nand erase.part initrd; " \ + "nand write ${ram_addr} initrd ${filesize}; fi\0" \ + "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ + "then sf probe; " \ + "nand erase.part initrd; " \ + "nand write ${ram_addr} initrd ${filesize}; fi\0" \ + "update_rootfs_from_sd=if fatload mmc 0:2 ${sys_addr} " \ + "${filesys}; " \ + "then sf probe; " \ + "ubi part system; " \ + "ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \ + "ubi detach; fi\0" \ + "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \ + "then sf probe; " \ + "ubi part system; " \ + "ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \ + "ubi detach; fi\0" \ + "setup_dtbkernel=nand erase.part dtbkernel; " \ + "ubi part dtbkernel; " \ + "ubi create dtbkernel1 972000 s; " \ + "ubi create dtbkernel2 972000 s; " \ + "ubi detach\0" \ + "setup_system=nand erase.part system; " \ + "ubi part system; " \ + "ubi create rootfs1 15E15000 d; " \ + "ubi create rootfs2 15E15000 d; " \ + "ubi create userdata; " \ + "ubi detach\0" \ + "setup_nor1=" BK4_NET_INIT \ + "if tftp ${sys_addr} ${tftpdir}ubinor1.img; " \ + "then sf probe 0:0; " \ + "sf erase 0 01000000; " \ + "mtdparts default; " \ + "ubi part nor; " \ + "ubi create nor1fs; " \ + "ubi write ${sys_addr} nor1fs ${filesize}; " \ + "ubi detach; fi\0" \ + "setup_nor2=" BK4_NET_INIT \ + "if tftp ${sys_addr} ${tftpdir}ubinor2.img; " \ + "then sf probe 0:1; " \ + "sf erase 0 01000000; " \ + "mtdparts default; " \ + "ubi part nor; " \ + "ubi create nor2fs; " \ + "ubi write ${sys_addr} nor2fs ${filesize}; " \ + "ubi detach; fi\0" \ + "prepare_install_bk4r1_envs=" \ + "echo 'Preparing envs for SD card recovery!';" \ + "setenv ipaddr 192.168.0.99;" \ + "setenv serverip 192.168.0.50;" \ + "\0" \ + "install_bk4r1rs="\ + "led 0 on; " \ + "nand erase.chip; mtdparts default; "\ + "led 1 on; "\ + "run setup_dtbkernel; " \ + "run setup_system; " \ + "led 2 on;" \ + "run update_bootloader_from_sd; "\ + "run update_dtbkernel_from_sd; "\ + "run update_rootfs_from_sd; "\ + "setenv bootcmd 'run bootcmd_nand'; "\ + "saveenv; " \ + "led 3 on; " \ + "echo Finished - Please Power off, REMOVE SDCARD and set boot" \ + "source to NAND\0" \ + "active_workset=1\0" + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Physical memory map */ +#define PHYS_SDRAM (0x80000000) +#define PHYS_SDRAM_SIZE (SZ_512M) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/blanche.h b/roms/u-boot/include/configs/blanche.h new file mode 100644 index 000000000..f048f158e --- /dev/null +++ b/roms/u-boot/include/configs/blanche.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * include/configs/blanche.h + * This file is blanche board configuration. + * + * Copyright (C) 2016 Renesas Electronics Corporation + */ + +#ifndef __BLANCHE_H +#define __BLANCHE_H + +#include "rcar-gen2-common.h" + +/* STACK */ +#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 +#define STACK_AREA_SIZE 0x00100000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) + +#undef CONFIG_SYS_LOADS_BAUD_CHANGE + +/* FLASH */ +#if !defined(CONFIG_MTD_NOR_FLASH) +#define CONFIG_SH_QSPI_BASE 0xE6B10000 +#else +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_FLASH_BASE 0x00000000 +#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } +#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) } + +#define CONFIG_SYS_FLASH_ERASE_TOUT 3000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 3000 +#define CONFIG_SYS_FLASH_LOCK_TOUT 3000 +#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000 +#endif + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK + +/* ENV setting */ + +#endif /* __BLANCHE_H */ diff --git a/roms/u-boot/include/configs/bmips_bcm3380.h b/roms/u-boot/include/configs/bmips_bcm3380.h new file mode 100644 index 000000000..573ff3e40 --- /dev/null +++ b/roms/u-boot/include/configs/bmips_bcm3380.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#ifndef __CONFIG_BMIPS_BCM3380_H +#define __CONFIG_BMIPS_BCM3380_H + +#include + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 166500000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#endif + +#endif /* __CONFIG_BMIPS_BCM3380_H */ diff --git a/roms/u-boot/include/configs/bmips_bcm6318.h b/roms/u-boot/include/configs/bmips_bcm6318.h new file mode 100644 index 000000000..45eb931c2 --- /dev/null +++ b/roms/u-boot/include/configs/bmips_bcm6318.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + */ + +#ifndef __CONFIG_BMIPS_BCM6318_H +#define __CONFIG_BMIPS_BCM6318_H + +#include + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 166500000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* USB */ +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) +#define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#endif + +#endif /* __CONFIG_BMIPS_BCM6318_H */ diff --git a/roms/u-boot/include/configs/bmips_bcm63268.h b/roms/u-boot/include/configs/bmips_bcm63268.h new file mode 100644 index 000000000..eed321eb6 --- /dev/null +++ b/roms/u-boot/include/configs/bmips_bcm63268.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#ifndef __CONFIG_BMIPS_BCM63268_H +#define __CONFIG_BMIPS_BCM63268_H + +#include + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* USB */ +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) +#define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#endif + +#endif /* __CONFIG_BMIPS_BCM63268_H */ diff --git a/roms/u-boot/include/configs/bmips_bcm6328.h b/roms/u-boot/include/configs/bmips_bcm6328.h new file mode 100644 index 000000000..c78099a49 --- /dev/null +++ b/roms/u-boot/include/configs/bmips_bcm6328.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#ifndef __CONFIG_BMIPS_BCM6328_H +#define __CONFIG_BMIPS_BCM6328_H + +#include + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 160000000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* USB */ +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) +#define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#endif + +#endif /* __CONFIG_BMIPS_BCM6328_H */ diff --git a/roms/u-boot/include/configs/bmips_bcm6338.h b/roms/u-boot/include/configs/bmips_bcm6338.h new file mode 100644 index 000000000..38dd9e3af --- /dev/null +++ b/roms/u-boot/include/configs/bmips_bcm6338.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#ifndef __CONFIG_BMIPS_BCM6338_H +#define __CONFIG_BMIPS_BCM6338_H + +#include + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 120000000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#endif + +#define CONFIG_SYS_FLASH_BASE 0xbfc00000 +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 + +#endif /* __CONFIG_BMIPS_BCM6338_H */ diff --git a/roms/u-boot/include/configs/bmips_bcm6348.h b/roms/u-boot/include/configs/bmips_bcm6348.h new file mode 100644 index 000000000..547cf857c --- /dev/null +++ b/roms/u-boot/include/configs/bmips_bcm6348.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#ifndef __CONFIG_BMIPS_BCM6348_H +#define __CONFIG_BMIPS_BCM6348_H + +#include + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 128000000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* USB */ +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) +#define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#endif + +#define CONFIG_SYS_FLASH_BASE 0xbfc00000 +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 + +#endif /* __CONFIG_BMIPS_BCM6348_H */ diff --git a/roms/u-boot/include/configs/bmips_bcm6358.h b/roms/u-boot/include/configs/bmips_bcm6358.h new file mode 100644 index 000000000..116e9705b --- /dev/null +++ b/roms/u-boot/include/configs/bmips_bcm6358.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#ifndef __CONFIG_BMIPS_BCM6358_H +#define __CONFIG_BMIPS_BCM6358_H + +#include + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 150000000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* USB */ +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) +#define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#endif + +#define CONFIG_SYS_FLASH_BASE 0xbe000000 +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 + +#endif /* __CONFIG_BMIPS_BCM6358_H */ diff --git a/roms/u-boot/include/configs/bmips_bcm6362.h b/roms/u-boot/include/configs/bmips_bcm6362.h new file mode 100644 index 000000000..e5e8b15e1 --- /dev/null +++ b/roms/u-boot/include/configs/bmips_bcm6362.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + */ + +#ifndef __CONFIG_BMIPS_BCM6362_H +#define __CONFIG_BMIPS_BCM6362_H + +#include + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* USB */ +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) +#define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#endif + +#endif /* __CONFIG_BMIPS_BCM6362_H */ diff --git a/roms/u-boot/include/configs/bmips_bcm6368.h b/roms/u-boot/include/configs/bmips_bcm6368.h new file mode 100644 index 000000000..4d4403f8d --- /dev/null +++ b/roms/u-boot/include/configs/bmips_bcm6368.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#ifndef __CONFIG_BMIPS_BCM6368_H +#define __CONFIG_BMIPS_BCM6368_H + +#include + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* USB */ +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#if defined(CONFIG_USB_OHCI_HCD) +#define CONFIG_USB_OHCI_NEW +#endif /* CONFIG_USB_OHCI_HCD */ + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#endif + +#define CONFIG_SYS_FLASH_BASE 0xb8000000 +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 + +#endif /* __CONFIG_BMIPS_BCM6368_H */ diff --git a/roms/u-boot/include/configs/bmips_bcm6838.h b/roms/u-boot/include/configs/bmips_bcm6838.h new file mode 100644 index 000000000..f1ff05414 --- /dev/null +++ b/roms/u-boot/include/configs/bmips_bcm6838.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Philippe Reynes + */ + +#ifndef __CONFIG_BMIPS_BCM6838_H +#define __CONFIG_BMIPS_BCM6838_H + +#include + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 160000000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#endif + +#endif /* __CONFIG_BMIPS_BCM6838_H */ diff --git a/roms/u-boot/include/configs/bmips_common.h b/roms/u-boot/include/configs/bmips_common.h new file mode 100644 index 000000000..3cb2d4050 --- /dev/null +++ b/roms/u-boot/include/configs/bmips_common.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#ifndef __CONFIG_BMIPS_COMMON_H +#define __CONFIG_BMIPS_COMMON_H + +#include + +/* ETH */ +#define CONFIG_PHY_RESET_DELAY 20 +#define CONFIG_SYS_RX_ETH_BUFFER 6 + +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 500000, 1500000 } + +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 24 +#define CONFIG_SYS_MALLOC_LEN SZ_2M +#define CONFIG_SYS_BOOTPARAMS_LEN SZ_128K +#define CONFIG_SYS_CBSIZE SZ_512 + +/* U-Boot */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#endif /* __CONFIG_BMIPS_COMMON_H */ diff --git a/roms/u-boot/include/configs/boston.h b/roms/u-boot/include/configs/boston.h new file mode 100644 index 000000000..b9a9965ee --- /dev/null +++ b/roms/u-boot/include/configs/boston.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Imagination Technologies + */ + +#ifndef __CONFIGS_BOSTON_H__ +#define __CONFIGS_BOSTON_H__ + +/* + * General board configuration + */ +#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) + +/* + * CPU + */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 30000000 + +/* + * PCI + */ + +/* + * Memory map + */ +#ifdef CONFIG_64BIT +# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +#else +# define CONFIG_SYS_SDRAM_BASE 0x80000000 +#endif + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) + +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) + +/* + * Console + */ + +/* + * Flash + */ +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 + +/* + * Environment + */ + +#endif /* __CONFIGS_BOSTON_H__ */ diff --git a/roms/u-boot/include/configs/broadcom_bcm963158.h b/roms/u-boot/include/configs/broadcom_bcm963158.h new file mode 100644 index 000000000..238ae9c01 --- /dev/null +++ b/roms/u-boot/include/configs/broadcom_bcm963158.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Philippe Reynes + */ + +#include + +/* + * common + */ + +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 500000, 1500000 } +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 24 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_BOOTM_LEN (16 * 1024 * 1024) + +/* + * 63158 + */ + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +/* U-Boot */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif /* CONFIG_MTD_RAW_NAND */ + +/* + * bcm963158 + */ + diff --git a/roms/u-boot/include/configs/broadcom_bcm968360bg.h b/roms/u-boot/include/configs/broadcom_bcm968360bg.h new file mode 100644 index 000000000..77690ff40 --- /dev/null +++ b/roms/u-boot/include/configs/broadcom_bcm968360bg.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Philippe Reynes + */ + +#include + +/* + * common + */ + +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 500000, 1500000 } +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 24 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + +/* + * 6858 + */ + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +/* U-Boot */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif /* CONFIG_MTD_RAW_NAND */ + +/* + * 968360bg + */ diff --git a/roms/u-boot/include/configs/broadcom_bcm968380gerg.h b/roms/u-boot/include/configs/broadcom_bcm968380gerg.h new file mode 100644 index 000000000..8d572f6b7 --- /dev/null +++ b/roms/u-boot/include/configs/broadcom_bcm968380gerg.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Philippe Reynes + */ + +#include +#include + +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif /* CONFIG_MTD_RAW_NAND */ diff --git a/roms/u-boot/include/configs/broadcom_bcm968580xref.h b/roms/u-boot/include/configs/broadcom_bcm968580xref.h new file mode 100644 index 000000000..febe6c0a0 --- /dev/null +++ b/roms/u-boot/include/configs/broadcom_bcm968580xref.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Philippe Reynes + */ + +#include + +/* + * common + */ + +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 500000, 1500000 } +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 24 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + +/* + * 6858 + */ + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +/* U-Boot */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif /* CONFIG_MTD_RAW_NAND */ + +/* + * 968580xref + */ + diff --git a/roms/u-boot/include/configs/brppt1.h b/roms/u-boot/include/configs/brppt1.h new file mode 100644 index 000000000..f9a0632e5 --- /dev/null +++ b/roms/u-boot/include/configs/brppt1.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * brtpp1.h + * + * specific parts for B&R T-Series Motherboard + * + * Copyright (C) 2013 Hannes Schmelzer - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + */ + +#ifndef __CONFIG_BRPPT1_H__ +#define __CONFIG_BRPPT1_H__ + +#include +#include +#include +/* ------------------------------------------------------------------------- */ +/* memory */ +#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) +#define CONFIG_SYS_BOOTM_LEN SZ_32M + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_POWER_TPS65217 + +/* Support both device trees and ATAGs. */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +/*#define CONFIG_MACH_TYPE 3589*/ +#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/ + +/* + * When we have NAND flash we expect to be making use of mtdparts, + * both for ease of use in U-Boot and for passing information on to + * the Linux kernel. + */ + +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 + +/* RAW SD card / eMMC */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ + +/* NAND */ +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000 +#endif /* CONFIG_MTD_RAW_NAND */ +#endif /* CONFIG_SPL_OS_BOOT */ + +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#endif /* CONFIG_MTD_RAW_NAND */ + +#ifdef CONFIG_MTD_RAW_NAND +#define NANDTGTS \ +"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ +"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ +"cfgscr=mw ${dtbaddr} 0; nand read ${cfgaddr} cfgscr && source ${cfgaddr};" \ +" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \ +"nandargs=setenv bootargs console=${console} ${optargs} ${optargs_rot} " \ + "root=mtd6 rootfstype=jffs2 b_mode=${b_mode}\0" \ +"b_nand=nand read ${loadaddr} kernel; nand read ${dtbaddr} dtb; " \ + "run nandargs; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \ +"b_tgts_std=usb0 nand net\0" \ +"b_tgts_rcy=net usb0 nand\0" \ +"b_tgts_pme=usb0 nand net\0" +#else +#define NANDTGTS "" +#endif /* CONFIG_MTD_RAW_NAND */ + +#define MMCSPI_TGTS \ +"t30args#0=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \ + "b_mode=${b_mode} root=/dev/mmcblk0p2 rootfstype=ext4\0" \ +"b_t30lgcy#0=" \ + "load ${loaddev}:2 ${loadaddr} /boot/PPTImage.md5 && " \ + "load ${loaddev}:2 ${loadaddr} /boot/zImage && " \ + "load ${loaddev}:2 ${dtbaddr} /boot/am335x-ppt30.dtb || " \ + "load ${loaddev}:1 ${dtbaddr} am335x-ppt30-legacy.dtb; "\ + "run t30args#0; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \ +"t30args#1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \ + "b_mode=${b_mode}\0" \ +"b_t30lgcy#1=" \ + "load ${loaddev}:1 ${loadaddr} zImage && " \ + "load ${loaddev}:1 ${dtbaddr} am335x-ppt30.dtb && " \ + "load ${loaddev}:1 ${ramaddr} rootfsPPT30.uboot && " \ + "run t30args#1; run cfgscr; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0" \ +"b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \ +"b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \ +"b_tgts_std=mmc0 mmc1 t30lgcy#0 t30lgcy#1 usb0 net\0" \ +"b_tgts_rcy=t30lgcy#1 usb0 net\0" \ +"b_tgts_pme=net usb0 mmc0 mmc1\0" \ +"loaddev=mmc 1\0" + +#ifdef CONFIG_ENV_IS_IN_MMC +#define MMCTGTS \ +MMCSPI_TGTS \ +"cfgscr=mw ${dtbaddr} 0;" \ +" mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr};" \ +" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" +#else +#define MMCTGTS "" +#endif /* CONFIG_MMC */ + +#ifdef CONFIG_SPI +#define SPITGTS \ +MMCSPI_TGTS \ +"cfgscr=mw ${dtbaddr} 0;" \ +" sf probe; sf read ${cfgaddr} 0xC0000 10000; source ${cfgaddr};" \ +" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" +#else +#define SPITGTS "" +#endif /* CONFIG_SPI */ + +#define LOAD_OFFSET(x) 0x8##x + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ +BUR_COMMON_ENV \ +"verify=no\0" \ +"autoload=0\0" \ +"scraddr=" __stringify(LOAD_OFFSET(0000000)) "\0" \ +"cfgaddr=" __stringify(LOAD_OFFSET(0020000)) "\0" \ +"dtbaddr=" __stringify(LOAD_OFFSET(0040000)) "\0" \ +"loadaddr=" __stringify(LOAD_OFFSET(0100000)) "\0" \ +"ramaddr=" __stringify(LOAD_OFFSET(2000000)) "\0" \ +"console=ttyO0,115200n8\0" \ +"optargs=consoleblank=0 quiet panic=2\0" \ +"b_break=0\0" \ +"b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \ +"b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \ +MMCTGTS \ +SPITGTS \ +NANDTGTS \ +"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \ +" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \ +" else setenv b_tgts ${b_tgts_std}; fi\0" \ +"b_default=run b_deftgts; for target in ${b_tgts};"\ +" do echo \"### booting ${target} ###\"; run b_${target};" \ +" if test ${b_break} = 1; then; exit; fi; done\0" +#endif /* !CONFIG_SPL_BUILD*/ + +#ifdef CONFIG_MTD_RAW_NAND +/* + * GPMC block. We support 1 device and the physical address to + * access CS0 at is 0x8000000. + */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x8000000 +/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */ +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_NAND_OMAP_GPMC_WSCFG 1 +#endif /* CONFIG_MTD_RAW_NAND */ + +#if defined(CONFIG_ENV_IS_IN_NAND) +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE +#endif + +#endif /* ! __CONFIG_BRPPT1_H__ */ diff --git a/roms/u-boot/include/configs/brppt2.h b/roms/u-boot/include/configs/brppt2.h new file mode 100644 index 000000000..333d3f44e --- /dev/null +++ b/roms/u-boot/include/configs/brppt2.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Config file for BuR BRPP2_IMX6 board + * + * Copyright (C) 2018 + * B&R Industrial Automation GmbH - http://www.br-automation.com/ + */ +#ifndef __CONFIG_BRPP2_IMX6_H +#define __CONFIG_BRPP2_IMX6_H + +#include +#include + +/* -- i.mx6 specifica -- */ +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE L2_PL310_BASE +#endif /* !CONFIG_SYS_L2CACHE_OFF */ + +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_MXC_GPT_HCLK + +#define CONFIG_LOADADDR 0x10700000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* MMC */ +#define CONFIG_FSL_USDHC + +/* Boot */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_MACH_TYPE 0xFFFFFFFF + +/* misc */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +/* Environment */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ +BUR_COMMON_ENV \ +"autoload=0\0" \ +"cfgaddr=0x106F0000\0" \ +"scraddr=0x10700000\0" \ +"loadaddr=0x10800000\0" \ +"dtbaddr=0x12000000\0" \ +"ramaddr=0x12100000\0" \ +"cfgscr=mw ${loadaddr} 0 128\0" \ +"cfgscrl=fdt addr ${dtbaddr} &&"\ +" sf probe; sf read ${cfgaddr} 0x40000 0x10000 && source ${cfgaddr}\0" \ +"console=ttymxc0,115200n8 consoleblank=0 quiet\0" \ +"t50args#0=setenv bootargs b_mode=${b_mode} console=${console} " \ + " root=/dev/mmcblk0p2 rootfstype=ext4 rootwait panic=2 \0" \ +"b_t50lgcy#0=" \ + "load ${loaddev}:2 ${loadaddr} /boot/zImage && " \ + "load ${loaddev}:2 ${dtbaddr} /boot/imx6dl-brppt50.dtb; " \ + "run t50args#0; run cfgscrl; bootz ${loadaddr} - ${dtbaddr}\0" \ +"t50args#1=setenv bootargs console=${console} b_mode=${b_mode}" \ + " rootwait panic=2\0" \ +"b_t50lgcy#1=" \ + "load ${loaddev}:1 ${loadaddr} zImage && " \ + "load ${loaddev}:1 ${dtbaddr} imx6dl-brppt50.dtb && " \ + "load ${loaddev}:1 ${ramaddr} rootfsPPT50.uboot && " \ + "run t50args#1; run cfgscrl; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0"\ +"b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \ +"b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \ +"b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \ +"b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \ +"b_tgts_std=mmc0 mmc1 t50lgcy#0 t50lgcy#1 usb0 net\0" \ +"b_tgts_rcy=t50lgcy#1 usb0 net\0" \ +"b_tgts_pme=net usb0 mmc0 mmc1\0" \ +"b_mode=4\0" \ +"b_break=0\0" \ +"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \ +" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \ +" else setenv b_tgts ${b_tgts_std}; fi\0" \ +"b_default=run b_deftgts; for target in ${b_tgts};"\ +" do echo \"### booting ${target} ###\"; run b_${target};" \ +" if test ${b_break} = 1; then; exit; fi; done\0" \ +"loaddev=mmc 0\0" \ +"altbootcmd=setenv b_mode 0; run b_default;\0" \ +"bootlimit=1\0" \ +"net2nor=sf probe && dhcp &&" \ +" tftp ${loadaddr} SPL && sf erase 0 +${filesize} &&" \ +" sf write ${loadaddr} 400 ${filesize} &&" \ +" tftp ${loadaddr} u-boot-dtb.img && sf erase 0x100000 +${filesize} &&" \ +" sf write ${loadaddr} 0x100000 ${filesize}\0" + +/* RAM */ +#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Ethernet */ +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_FIXED_SPEED _1000BASET +#define CONFIG_ARP_TIMEOUT 1500UL + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +/* SPL */ +#ifdef CONFIG_SPL +#include "imx6_spl.h" + +#endif /* CONFIG_SPL */ +#endif /* __CONFIG_BRPP2_IMX6_H */ diff --git a/roms/u-boot/include/configs/brsmarc1.h b/roms/u-boot/include/configs/brsmarc1.h new file mode 100644 index 000000000..d0cc08baa --- /dev/null +++ b/roms/u-boot/include/configs/brsmarc1.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * brsmarc1.h + * + * specific parts for B&R BRSMARC1 Motherboard + * + * Copyright (C) 2017 Hannes Schmelzer - + * B&R Industrial Automation GmbH - http://www.br-automation.com + * + */ + +#ifndef __CONFIG_BRSMARC1_H__ +#define __CONFIG_BRSMARC1_H__ + +#include +#include +#include +/* ------------------------------------------------------------------------- */ + +/* memory */ +#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) +#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_MACH_TYPE 3589 + +#ifndef CONFIG_SPL_BUILD + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ +BUR_COMMON_ENV \ +"autoload=0\0" \ +"scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ +"cfgscr=mw ${dtbaddr} 0;" \ +" sf probe && sf read ${scradr} 0xC0000 0x10000 && source ${scradr};" \ +" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \ +"dtbaddr=0x84000000\0" \ +"loadaddr=0x82000000\0" \ +"b_break=0\0" \ +"b_tgts_std=mmc0 mmc1 def net usb0\0" \ +"b_tgts_rcy=def net usb0\0" \ +"b_tgts_pme=net usb0 mmc0 mmc1\0" \ +"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \ +" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \ +" else setenv b_tgts ${b_tgts_std}; fi\0" \ +"b_mmc0=load mmc 1 ${scradr} bootscr.img && source ${scradr}\0" \ +"b_mmc1=load mmc 1 ${loadaddr} arimg.ugz && run startsys\0" \ +"b_def=sf read ${loadaddr} 100000 700000; run startsys\0" \ +"b_net=tftp ${scradr} netscript.img && source ${scradr}\0" \ +"b_usb0=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr}\0" \ +"b_default=run b_deftgts; for target in ${b_tgts};"\ +" do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0" \ +"vxargs=setenv bootargs cpsw(0,0)host:vxWorks h=${serverip}" \ +" e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks\0" \ +"vxfdt=fdt addr ${dtbaddr}; fdt resize 0x8000;" \ +" fdt boardsetup\0" \ +"startsys=run vxargs && mw 0x80001100 0 && run vxfdt &&" \ +" bootm ${loadaddr} - ${dtbaddr}\0" +#endif /* !CONFIG_SPL_BUILD*/ + +/* Support both device trees and ATAGs. */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* SPI Flash */ + +/* Environment */ +#endif /* __CONFIG_BRSMARC1_H__ */ diff --git a/roms/u-boot/include/configs/brxre1.h b/roms/u-boot/include/configs/brxre1.h new file mode 100644 index 000000000..d6a7af1a1 --- /dev/null +++ b/roms/u-boot/include/configs/brxre1.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * brxre1.h + * + * specific parts for B&R KWB Motherboard + * + * Copyright (C) 2013 Hannes Schmelzer - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + */ + +#ifndef __CONFIG_BRXRE1_H__ +#define __CONFIG_BRXRE1_H__ + +#include +#include +#include +/* ------------------------------------------------------------------------- */ +#define LCD_BPP LCD_COLOR32 + +/* memory */ +#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_MACH_TYPE 3589 + +#ifndef CONFIG_SPL_BUILD + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ +BUR_COMMON_ENV \ +"autoload=0\0" \ +"scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ +"bootaddr=0x80001100\0" \ +"bootdev=cpsw(0,0)\0" \ +"vx_romfsbase=0x800E0000\0" \ +"vx_romfssize=0x20000\0" \ +"vx_memtop=0x8FBEF000\0" \ +"loadromfs=mmc read ${vx_romfsbase} 700 100\0" \ +"loadaddr=0x80100000\0" \ +"startvx=run loadromfs; bootvx ${loadaddr}\0" \ +"b_break=0\0" \ +"b_tgts_std=mmc def net usb0\0" \ +"b_tgts_rcy=def net usb0\0" \ +"b_tgts_pme=net usb0 mmc\0" \ +"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \ +" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \ +" else setenv b_tgts ${b_tgts_std}; fi\0" \ +"b_mmc=load mmc 1 ${loadaddr} arimg && run startvx\0" \ +"b_def=mmc read ${loadaddr} 800 8000; run startvx\0" \ +"b_net=tftp ${scradr} netscript.img && source ${scradr}\0" \ +"b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr}\0" \ +"b_default=run b_deftgts; for target in ${b_tgts};"\ +" do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0" +#endif /* !CONFIG_SPL_BUILD*/ + +#define CONFIG_BOOTCOMMAND "mmc dev 1; run b_default" + +/* Support both device trees and ATAGs. */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* Environment */ + +#endif /* __CONFIG_BRXRE1_H__ */ diff --git a/roms/u-boot/include/configs/bur_am335x_common.h b/roms/u-boot/include/configs/bur_am335x_common.h new file mode 100644 index 000000000..42e3e568b --- /dev/null +++ b/roms/u-boot/include/configs/bur_am335x_common.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * bur_am335x_common.h + * + * common parts used by B&R AM335x based boards + * + * Copyright (C) 2016 Hannes Schmelzer - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + */ + +#ifndef __BUR_AM335X_COMMON_H__ +#define __BUR_AM335X_COMMON_H__ +/* ------------------------------------------------------------------------- */ + +/* legacy #defines for non DM bur-board */ +#ifndef CONFIG_DM +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x44e09000 + +#define CONFIG_I2C +#define CONFIG_SYS_I2C + +#endif /* CONFIG_DM */ + +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +/* Timer information */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CONFIG_POWER_TPS65217 + +#include + +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x402F0400 and 0x4030B800 as a download area and + * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also + * supports X-MODEM loading via UART, and we leverage this and then use + * Y-MODEM to load u-boot.img, when booted over UART. We must also include + * the scratch space that U-Boot uses in SRAM. + */ +#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ + CONFIG_SPL_TEXT_BASE) + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif /* !CONFIG_SPL_BUILD, ... */ +/* + * Our DDR memory always starts at 0x80000000 and U-Boot shall have + * relocated itself to higher in memory by the time this value is used. + */ +#define CONFIG_SYS_LOAD_ADDR 0x80000000 +/* + * ---------------------------------------------------------------------------- + * DDR information. We say (for simplicity) that we have 1 bank, + * always, even when we have more. We always start at 0x80000000, + * and we place the initial stack pointer in our SRAM. + */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Our platforms make use of SPL to initalize the hardware (primarily + * memory) enough for full U-Boot to be loaded. We also support Falcon + * Mode so that the Linux kernel can be booted directly from SPL + * instead, if desired. We make use of the general SPL framework found + * under common/spl/. Given our generally common memory map, we set a + * number of related defaults and sizes here. + */ +/* + * Place the image at the start of the ROM defined image space. + * We limit our size to the ROM-defined downloaded image area, and use the + * rest of the space for stack. We load U-Boot itself into memory at + * 0x80800000 for legacy reasons (to not conflict with older SPLs). We + * have our BSS be placed 1MiB after this, to allow for the default + * Linux kernel address of 0x80008000 to work, in the Falcon Mode case. + * We have the SPL malloc pool at the end of the BSS area. + * + * ---------------------------------------------------------------------------- + */ +#define CONFIG_SPL_BSS_START_ADDR 0x80A00000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN + +/* General parts of the framework, required. */ + +#endif /* ! __BUR_AM335X_COMMON_H__ */ diff --git a/roms/u-boot/include/configs/bur_cfg_common.h b/roms/u-boot/include/configs/bur_cfg_common.h new file mode 100644 index 000000000..05915b4cf --- /dev/null +++ b/roms/u-boot/include/configs/bur_cfg_common.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * bur_cfg_common.h + * + * common parts used over all B&R boards + * + * Copyright (C) 2016 Hannes Schmelzer - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + */ + +#ifndef __BUR_CFG_COMMON_H__ +#define __BUR_CFG_COMMON_H__ +/* ------------------------------------------------------------------------- */ +#define BUR_COMMON_ENV \ +"usbscript=usb start && fatload usb 0 ${scradr} usbscript.img &&" \ +" source ${scradr}\0" \ +"brdefaultip=if test -r ${ipaddr}; then; else" \ +" setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;" \ +" setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;\0" \ +"netconsole=echo switching to network console ...; " \ +"if dhcp; then; else run brdefaultip; fi; setenv ncip ${serverip}; " \ +"setcurs 1 9; lcdputs myip; setcurs 10 9; lcdputs ${ipaddr};" \ +"setcurs 1 10;lcdputs serverip; setcurs 10 10; lcdputs ${serverip};" \ +"setenv stdout nc;setenv stdin nc;setenv stderr nc\0" + +/* Network defines */ +#define CONFIG_NET_RETRY_COUNT 10 + +/* Network console */ +#define CONFIG_BOOTP_MAY_FAIL /* if we don't have DHCP environment */ + +/* As stated above, the following choices are optional. */ + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 64 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 + +#endif /* __BUR_CFG_COMMON_H__ */ diff --git a/roms/u-boot/include/configs/caddy2.h b/roms/u-boot/include/configs/caddy2.h new file mode 100644 index 000000000..78891fefd --- /dev/null +++ b/roms/u-boot/include/configs/caddy2.h @@ -0,0 +1,315 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * esd vme8349 U-Boot configuration file + * Copyright (c) 2008, 2009 esd gmbh Hannover Germany + * + * (C) Copyright 2006-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * reinhard.arlt@esd-electronics.de + * Based on the MPC8349EMDS config. + */ + +/* + * vme8349 board configuration file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ + +/* Don't enable PCI2 on vme834x - it doesn't exist physically. */ +#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ + +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ + +/* + * DDR Setup + */ +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +#define CONFIG_SPD_EEPROM +#define SPD_EEPROM_ADDRESS 0x54 +#define CONFIG_SYS_READ_SPD vme8349_read_spd +#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ + +/* + * 32-bit data path mode. + * + * Please note that using this mode for devices with the real density of 64-bit + * effectively reduces the amount of available memory due to the effect of + * wrapping around while translating address to row/columns, for example in the + * 256MB module the upper 128MB get aliased with contents of the lower + * 128MB); normally this define should be used for devices with real 32-bit + * data path. + */ +#undef CONFIG_DDR_32BIT + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ + | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) +#define CONFIG_DDR_2T_TIMING +#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN) + /* 0x80080001 */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ + + +#define CONFIG_SYS_WINDOW1_BASE 0xf0000000 + + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ + +#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } +/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ + +#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ + +/* TSEC */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 +#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE +#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 +#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0xFIXME +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + +/* + * TSEC configuration + */ + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_GMII /* MII PHY management */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_PHY_M88E1111 +#define TSEC1_PHY_ADDR 0x08 +#define TSEC2_PHY_ADDR 0x10 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#ifndef CONFIG_SYS_RAMBOOT +/* Address and size of Redundant Environment Sector */ +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#define CONFIG_SYS_RTC_BUS_NUM 0x01 +#define CONFIG_SYS_I2C_RTC_ADDR 0x32 + +/* Pass Ethernet MAC to VxWorks */ +#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +/* System IO Config */ +#define CONFIG_SYS_SICRH 0 +#define CONFIG_SYS_SICRL SICRL_LDP_A + +#define CONFIG_SYS_GPIO1_PRELIM +#define CONFIG_SYS_GPIO1_DIR 0x00100000 +#define CONFIG_SYS_GPIO1_DAT 0x00100000 + +#define CONFIG_SYS_GPIO2_PRELIM +#define CONFIG_SYS_GPIO2_DIR 0x78900000 +#define CONFIG_SYS_GPIO2_DAT 0x70100000 + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_HOSTNAME "VME8349" +#define CONFIG_ROOTPATH "/tftpboot/rootfs" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=vme8349\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ + "update=protect off fff00000 fff3ffff; " \ + "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ + "upd=run load update\0" \ + "fdtaddr=780000\0" \ + "fdtfile=vme8349.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ + "$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#ifndef __ASSEMBLY__ +int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len); +#endif + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/capricorn-common.h b/roms/u-boot/include/configs/capricorn-common.h new file mode 100644 index 000000000..b310e6c9e --- /dev/null +++ b/roms/u-boot/include/configs/capricorn-common.h @@ -0,0 +1,160 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2018 NXP + * Copyright 2019 Siemens AG + */ + +#ifndef __IMX8X_CAPRICORN_H +#define __IMX8X_CAPRICORN_H + +#include +#include + +#include "siemens-env-common.h" +#include "siemens-ccp-common.h" + +/* SPL config */ +#ifdef CONFIG_SPL_BUILD + +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_MALLOC_F_ADDR 0x00120000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_FACTORYSET + +#undef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07") + +#define CONFIG_REMAKE_ELF + +/* ENET Config */ +#define CONFIG_FEC_XCV_TYPE RMII + +/* ENET1 connects to base board and MUX with ESAI */ +#define CONFIG_FEC_ENET_DEV 1 +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_ETHPRIME "eth1" + +/* I2C Configuration */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_I2C_SPEED 400000 +/* EEPROM */ +#define EEPROM_I2C_BUS 0 /* I2C0 */ +#define EEPROM_I2C_ADDR 0x50 +/* PCA9552 */ +#define PCA9552_1_I2C_BUS 1 /* I2C1 */ +#define PCA9552_1_I2C_ADDR 0x60 +#endif /* !CONFIG_SPL_BUILD */ + +/* AHAB */ +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +#define MFG_ENV_SETTINGS_DEFAULT \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "clk_ignore_unused "\ + "\0" \ + "kboot=booti\0"\ + "bootcmd_mfg=run mfgtool_args;" \ + "if iminfo ${initrd_addr}; then " \ + "if test ${tee} = yes; then " \ + "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \ + "else " \ + "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \ + "fi; " \ + "else " \ + "echo \"Run fastboot ...\"; fastboot 0; " \ + "fi;\0" + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \ + "${loadaddr} ${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#define CONFIG_MFG_ENV_SETTINGS \ + MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x83100000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0" + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + AHAB_ENV \ + ENV_COMMON \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP2\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x88000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "netdev=eth0\0" \ + "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \ + "hostname=capricorn\0" \ + ENV_EMMC \ + ENV_NET + +#define CONFIG_BOOTCOMMAND \ + "if usrbutton; then " \ + "run flash_self_test; " \ + "reset; " \ + "fi;" \ + "run flash_self;" \ + "reset;" + +/* Default location for tftp and bootm */ +#define CONFIG_LOADADDR 0x80280000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* On CCP board, USDHC1 is for eMMC */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +/* DDR3 board total DDR is 1 GB */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ + +/* Console buffer and boot args */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#define BOOTAUX_RESERVED_MEM_BASE 0x88000000 +#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */ + +#endif /* __IMX8X_CAPRICORN_H */ diff --git a/roms/u-boot/include/configs/cardhu.h b/roms/u-boot/include/configs/cardhu.h new file mode 100644 index 000000000..8e8b1067b --- /dev/null +++ b/roms/u-boot/include/configs/cardhu.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra30-common.h" + +/* VDD core PMIC */ +#define CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu" + +#define BOARD_EXTRA_ENV_SETTINGS \ + "board_name=cardhu-a04\0" \ + "fdtfile=tegra30-cardhu-a04.dtb\0" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU + +/* SPI */ +#define CONFIG_TEGRA_SLINK_CTRLS 6 +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/cei-tk1-som.h b/roms/u-boot/include/configs/cei-tk1-som.h new file mode 100644 index 000000000..2c406d318 --- /dev/null +++ b/roms/u-boot/include/configs/cei-tk1-som.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (c) Copyright 2016, Data61 + * Commonwealth Scientific and Industrial Research Organisation (CSIRO) + * + * Based on jetson-tk1.h which is: + * (C) Copyright 2013-2014 + * NVIDIA Corporation + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra124-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "CEI tk1-som" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTD +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +/* SPI */ +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +/* Reserve top 1M for secure RAM */ +#define CONFIG_ARMV7_SECURE_BASE 0xfff00000 +#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/cgtqmx8.h b/roms/u-boot/include/configs/cgtqmx8.h new file mode 100644 index 000000000..15c50279a --- /dev/null +++ b/roms/u-boot/include/configs/cgtqmx8.h @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + * Copyright 2018 congatec AG + * + */ + +#ifndef __CGTQMX8_H +#define __CGTQMX8_H + +#include +#include + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_MALLOC_F_ADDR 0x00120000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#define CONFIG_OF_EMBED +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define USDHC3_BASE_ADDR 0x5B030000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "m4_1_image=m4_1.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif +#define FEC0_RESET IMX_GPIO_NR(2, 5) +#define FEC0_PDOMAIN "conn_enet0" + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + MFG_NAND_PARTITION \ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "fdt_file=imx8qm-cgt-qmx8.dtb\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* Networking */ +#define CONFIG_FEC_MXC_PHYADDR -1 +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC + +#endif /* __CGTQMX8_H */ diff --git a/roms/u-boot/include/configs/cherryhill.h b/roms/u-boot/include/configs/cherryhill.h new file mode 100644 index 000000000..6c7f9ea83 --- /dev/null +++ b/roms/u-boot/include/configs/cherryhill.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017, Bin Meng + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (2 << 20) + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \ + "stdout=vidconsole,serial\0" \ + "stderr=vidconsole,serial\0" + +/* Environment configuration */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/chiliboard.h b/roms/u-boot/include/configs/chiliboard.h new file mode 100644 index 000000000..86cac236f --- /dev/null +++ b/roms/u-boot/include/configs/chiliboard.h @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Grinn - http://grinn-global.com/ + */ + +#ifndef __CONFIG_CHILIBOARD_H +#define __CONFIG_CHILIBOARD_H + +#include + +#ifndef CONFIG_SPL_BUILD +# define CONFIG_TIMESTAMP +#endif + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define NANDARGS \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} ${optargs} " \ + "${mtdparts} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${fdt_addr} NAND.u-boot-spl-os; " \ + "nand read ${loadaddr} NAND.kernel; " \ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#define CONFIG_BOOTCOMMAND \ + "run mmcboot; " \ + "run nandboot; " \ + "run netboot" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "fdt_addr=0x87800000\0" \ + "boot_fdt=try\0" \ + "console=ttyO0,115200n8\0" \ + "image=zImage\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "ip_dyn=yes\0" \ + "optargs=\0" \ + "loadbootscript=" \ + "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${boot_dir}/${image}\0" \ + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \ + "${boot_dir}/${fdt_file}\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} ${optargs} " \ + "${mtdparts} " \ + "root=${mmcroot}\0" \ + "mmcloados=run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadimage; then " \ + "run mmcloados;" \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} ${optargs} " \ + "${mtdparts} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + NANDARGS + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ + +/* PMIC support */ +#define CONFIG_POWER_TPS65217 + +/* SPL */ +/* Bootcount using the RTC block */ +#define CONFIG_SYS_BOOTCOUNT_BE + +/* NAND: device related configs */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +/* NAND: driver related configs */ +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 +/* NAND: SPL related configs */ + +/* USB configuration */ +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +/* + * Disable MMC DM for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_MMC +#undef CONFIG_TIMER +#endif + +#if defined(CONFIG_ENV_IS_IN_NAND) +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#endif + +/* Network. */ + +#endif /* ! __CONFIG_CHILIBOARD_H */ diff --git a/roms/u-boot/include/configs/chromebook_coral.h b/roms/u-boot/include/configs/chromebook_coral.h new file mode 100644 index 000000000..00760b8a3 --- /dev/null +++ b/roms/u-boot/include/configs/chromebook_coral.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Google LLC + */ + +/* + * board/config.h - configuration options, board-specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_BOOTCOMMAND \ + "tpm init; tpm startup TPM2_SU_CLEAR; " \ + "read mmc 0:2 100000 0 80; setexpr loader *001004f0; " \ + "setexpr size *00100518; setexpr blocks $size / 200; " \ + "read mmc 0:2 100000 80 $blocks; setexpr setup $loader - 1000; " \ + "setexpr cmdline_ptr $loader - 2000; " \ + "setexpr.s cmdline *$cmdline_ptr; " \ + "setexpr cmdline gsub %U \\\\${uuid}; " \ + "if part uuid mmc 0:2 uuid; then " \ + "zboot start 100000 0 0 0 $setup cmdline; " \ + "zboot load; zboot setup; zboot dump; zboot go;" \ + "fi" + +#include +#include + +#undef CONFIG_STD_DEVICES_SETTINGS +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ + "stdout=vidconsole,serial\0" \ + "stderr=vidconsole,serial\0" + +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x003f8000 + +#define CONFIG_TPL_TEXT_BASE 0xffff8000 + +#define CONFIG_SYS_NS16550_MEM32 +#undef CONFIG_SYS_NS16550_PORT_MAPPED + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/chromebook_link.h b/roms/u-boot/include/configs/chromebook_link.h new file mode 100644 index 000000000..96d5cf1a3 --- /dev/null +++ b/roms/u-boot/include/configs/chromebook_link.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +#define CONFIG_SPL_BOARD_LOAD_IMAGE + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/chromebook_samus.h b/roms/u-boot/include/configs/chromebook_samus.h new file mode 100644 index 000000000..2fe3e7219 --- /dev/null +++ b/roms/u-boot/include/configs/chromebook_samus.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +/* We can rely on running natively, and this saves code size */ +#undef CONFIG_BIOSEMU + +#undef CONFIG_STD_DEVICES_SETTINGS +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ + "stdout=vidconsole,serial\0" \ + "stderr=vidconsole,serial\0" + +#define CONFIG_TPL_TEXT_BASE 0xfffd8000 + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/chromebox_panther.h b/roms/u-boot/include/configs/chromebox_panther.h new file mode 100644 index 000000000..a7c260624 --- /dev/null +++ b/roms/u-boot/include/configs/chromebox_panther.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/ci20.h b/roms/u-boot/include/configs/ci20.h new file mode 100644 index 000000000..6e46d29c8 --- /dev/null +++ b/roms/u-boot/include/configs/ci20.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * CI20 configuration + * + * Copyright (c) 2013 Imagination Technologies + * Author: Paul Burton + */ + +#ifndef __CONFIG_CI20_H__ +#define __CONFIG_CI20_H__ + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* Ingenic JZ4780 clock configuration. */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 1200 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +/* Memory configuration */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CONFIG_SYS_LOAD_ADDR 0x81000000 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +/* NS16550-ish UARTs */ +#define CONFIG_SYS_NS16550_CLK 48000000 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* Ethernet: davicom DM9000 */ +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0xb6000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 2) + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ + +/* Miscellaneous configuration options */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) + +/* SPL */ +#define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */ + +#define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00) + +#define CONFIG_SPL_BSS_START_ADDR 0xf4004000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 512KB, arbitrary */ + +#define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx" + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1c /* 14 KiB offset */ + +#endif /* __CONFIG_CI20_H__ */ diff --git a/roms/u-boot/include/configs/cl-som-imx7.h b/roms/u-boot/include/configs/cl-som-imx7.h new file mode 100644 index 000000000..0ef55b771 --- /dev/null +++ b/roms/u-boot/include/configs/cl-som-imx7.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 CompuLab, Ltd. + * + * Configuration settings for the CompuLab CL-SOM-iMX7 System-on-Module. + */ + +#ifndef __CL_SOM_IMX7_CONFIG_H +#define __CL_SOM_IMX7_CONFIG_H + +#include "mx7_common.h" + +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +/* Network */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 + +/* ENET1 */ +#define IMX_FEC_BASE ENET_IPS_BASE_ADDR + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + +/* I2C configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C2 /* Enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define SYS_I2C_BUS_SOM 0 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS SYS_I2C_BUS_SOM + +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } + +#undef CONFIG_SYS_AUTOLOAD +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_SYS_AUTOLOAD "no" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=off\0" \ + "script=boot.scr\0" \ + "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0" \ + "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0" \ + "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${fdtfile};\0" \ + "bootscript=echo Running bootscript from ${storagetype} ...; source ${loadaddr};\0" \ + "storagebootcmd=echo Booting from ${storagetype} ...; run ${storagetype}args; run doboot;\0" \ + "kernel=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdtfile=imx7d-sbc-imx7.dtb\0" \ + "fdtaddr=0x83000000\0" \ + "mmcdev_def="__stringify(CONFIG_SYS_MMC_DEV)"\0" \ + "usbdev_def="__stringify(CONFIG_SYS_USB_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "usbpart=" __stringify(CONFIG_SYS_USB_IMG_LOAD_PART) "\0" \ + "doboot=bootz ${loadaddr} - ${fdtaddr}\0" \ + "mmc_config=mmc dev ${mmcdev}; mmc rescan\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/mmcblk${mmcblk}p2 rootwait rw\0" \ + "mmcbootscript=" \ + "if run mmc_config; then " \ + "setenv storagetype mmc;" \ + "setenv storagedev ${mmcdev}:${mmcpart};" \ + "if run loadscript; then " \ + "run bootscript; " \ + "fi; " \ + "fi;\0" \ + "mmcboot=" \ + "if run mmc_config; then " \ + "setenv storagetype mmc;" \ + "setenv storagedev ${mmcdev}:${mmcpart};" \ + "if run loadkernel; then " \ + "if run loadfdt; then " \ + "run storagebootcmd;" \ + "fi; " \ + "fi; " \ + "fi;\0" \ + "sdbootscript=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; " \ + "run mmcbootscript\0" \ + "usbbootscript=setenv usbdev ${usbdev_def}; " \ + "setenv storagetype usb;" \ + "setenv storagedev ${usbdev}:${usbpart};" \ + "if run loadscript; then " \ + "run bootscript; " \ + "fi; " \ + "sdboot=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; run mmcboot\0" \ + "emmcbootscript=setenv mmcdev 1; setenv mmcblk 2; run mmcbootscript\0" \ + "emmcboot=setenv mmcdev 1; setenv mmcblk 2; run mmcboot\0" \ + +#define CONFIG_BOOTCOMMAND \ + "echo SD boot attempt ...; run sdbootscript; run sdboot; " \ + "echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \ + "echo USB boot attempt ...; run usbbootscript; " + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* SPI Flash support */ + +/* FLASH and environment organization */ + +/* MMC Config*/ +#ifdef CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ +#endif + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* SPL */ +#include "imx7_spl.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/clearfog.h b/roms/u-boot/include/configs/clearfog.h new file mode 100644 index 000000000..c9852a72b --- /dev/null +++ b/roms/u-boot/include/configs/clearfog.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Stefan Roese + */ + +#ifndef _CONFIG_CLEARFOG_H +#define _CONFIG_CLEARFOG_H + +#include + +/* + * High Level Configuration Options (easy to change) + */ + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +#define CONFIG_ENV_MIN_ENTRIES 128 + +/* Environment in MMC */ +/* + * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC + * boot image starts @ LBA-0. + * As result in MMC/eMMC case it will be a 1 sector gap between u-boot + * image and environment + */ + +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* SATA support */ +#ifdef CONFIG_SCSI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#endif + +/* Keep device tree and initrd in lower memory so the kernel can access them */ +#define RELOCATION_LIMITS_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +/* SPL */ + +/* Defines for SPL */ +#define CONFIG_SPL_SIZE (140 << 10) +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI) +/* SPL related SPI defines */ +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS +#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA) +/* SPL related MMC defines */ +#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS +#ifdef CONFIG_SPL_BUILD +#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ +#endif +#endif + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Include the common distro boot environment */ +#ifndef CONFIG_SPL_BUILD + +#ifdef CONFIG_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#ifdef CONFIG_USB_STORAGE +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + +#ifndef CONFIG_SCSI +#define BOOT_TARGET_DEVICES_SCSI_BUS0(func) +#define BOOT_TARGET_DEVICES_SCSI_BUS1(func) +#define BOOT_TARGET_DEVICES_SCSI_BUS2(func) +#else +/* + * With SCSI enabled, M.2 SATA is always located on bus 0 + */ +#define BOOT_TARGET_DEVICES_SCSI_BUS0(func) func(SCSI, scsi, 0) + +/* + * Either one or both mPCIe slots may be configured as mSATA interfaces. The + * SCSI bus ids are assigned based on sequence of hardware present, not always + * tied to hardware slot ids. As such, use second SCSI bus if either slot is + * set for SATA, and only use third SCSI bus if both slots are SATA enabled. + */ +#if defined (CONFIG_CLEARFOG_CON2_SATA) || defined (CONFIG_CLEARFOG_CON3_SATA) +#define BOOT_TARGET_DEVICES_SCSI_BUS1(func) func(SCSI, scsi, 1) +#else +#define BOOT_TARGET_DEVICES_SCSI_BUS1(func) +#endif + +#if defined (CONFIG_CLEARFOG_CON2_SATA) && defined (CONFIG_CLEARFOG_CON3_SATA) +#define BOOT_TARGET_DEVICES_SCSI_BUS2(func) func(SCSI, scsi, 2) +#else +#define BOOT_TARGET_DEVICES_SCSI_BUS2(func) +#endif + +#endif /* CONFIG_SCSI */ + +/* + * The SCSI buses are attempted in increasing bus order, there is no current + * mechanism to alter the default bus priority order for booting. + */ +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_USB(func) \ + BOOT_TARGET_DEVICES_SCSI_BUS0(func) \ + BOOT_TARGET_DEVICES_SCSI_BUS1(func) \ + BOOT_TARGET_DEVICES_SCSI_BUS2(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#define KERNEL_ADDR_R __stringify(0x800000) +#define FDT_ADDR_R __stringify(0x100000) +#define RAMDISK_ADDR_R __stringify(0x1800000) +#define SCRIPT_ADDR_R __stringify(0x200000) +#define PXEFILE_ADDR_R __stringify(0x300000) + +#define LOAD_ADDRESS_ENV_SETTINGS \ + "kernel_addr_r=" KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" FDT_ADDR_R "\0" \ + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ + "scriptaddr=" SCRIPT_ADDR_R "\0" \ + "pxefile_addr_r=" PXEFILE_ADDR_R "\0" + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + RELOCATION_LIMITS_ENV_SETTINGS \ + LOAD_ADDRESS_ENV_SETTINGS \ + "console=ttyS0,115200\0" \ + BOOTENV + +#endif /* CONFIG_SPL_BUILD */ + +#endif /* _CONFIG_CLEARFOG_H */ diff --git a/roms/u-boot/include/configs/cm_fx6.h b/roms/u-boot/include/configs/cm_fx6.h new file mode 100644 index 000000000..9892fb881 --- /dev/null +++ b/roms/u-boot/include/configs/cm_fx6.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Config file for Compulab CM-FX6 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Nikita Kiryanov + */ + +#ifndef __CONFIG_CM_FX6_H +#define __CONFIG_CM_FX6_H + +#include "mx6_common.h" + +/* Machine config */ +#define CONFIG_SYS_LITTLE_ENDIAN +#define CONFIG_MACH_TYPE 4273 + +/* MMC */ +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* RAM */ +#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Serial console */ +#define CONFIG_MXC_UART_BASE UART4_BASE +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* Environment */ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_addr_r=0x18000000\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=undefined\0" \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ + "panel=HDMI\0" \ + "autoload=no\0" \ + "uImage=uImage-cm-fx6\0" \ + "zImage=zImage-cm-fx6\0" \ + "kernel=uImage-cm-fx6\0" \ + "dtb=cm-fx6.dtb\0" \ + "console=ttymxc3,115200\0" \ + "ethprime=FEC0\0" \ + "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \ + "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \ + "doboot=bootm ${kernel_addr_r}\0" \ + "doloadfdt=false\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "setboottypez=setenv kernel ${zImage};" \ + "setenv doboot bootz ${kernel_addr_r} - ${fdt_addr_r};" \ + "setenv doloadfdt true;\0" \ + "setboottypem=setenv kernel ${uImage};" \ + "setenv doboot bootm ${kernel_addr_r};" \ + "setenv doloadfdt false;\0"\ + "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ + "sataroot=/dev/sda2 rw rootwait\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=ubifs\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \ + "${video} ${extrabootargs}\0" \ + "sataargs=setenv bootargs console=${console} root=${sataroot} " \ + "${video} ${extrabootargs}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype} " \ + "${video} ${extrabootargs}\0" \ + "nandboot=if run nandloadkernel; then " \ + "run nandloadfdt;" \ + "run setboottypem;" \ + "run storagebootcmd;" \ + "run setboottypez;" \ + "run storagebootcmd;" \ + "fi;\0" \ + "run_eboot=echo Starting EBOOT ...; "\ + "mmc dev 2 && " \ + "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \ + "loadkernel=load ${storagetype} ${storagedev} ${kernel_addr_r} ${kernel};\0"\ + "loadfdt=load ${storagetype} ${storagedev} ${fdt_addr_r} ${dtb};\0" \ + "nandloadkernel=nand read ${kernel_addr_r} 0 780000;\0" \ + "nandloadfdt=nand read ${fdt_addr_r} 780000 80000;\0" \ + "setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \ + "setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \ + "setupnandboot=setenv storagetype nand;\0" \ + "storagebootcmd=echo Booting from ${storagetype} ...;" \ + "run ${storagetype}args; run doboot;\0" \ + "trybootk=if run loadkernel; then " \ + "if ${doloadfdt}; then " \ + "run loadfdt;" \ + "fi;" \ + "run storagebootcmd;" \ + "fi;\0" \ + "trybootsmz=" \ + "run setboottypem;" \ + "run trybootk;" \ + "run setboottypez;" \ + "run trybootk;\0" \ + "legacy_bootcmd=" \ + "run setupmmcboot;" \ + "mmc dev ${storagedev};" \ + "if mmc rescan; then " \ + "run trybootsmz;" \ + "fi;" \ + "run setupsataboot;" \ + "if sata init; then " \ + "run trybootsmz;" \ + "fi;" \ + "run setupnandboot;" \ + "run nandboot;\0" \ + "findfdt="\ + "if test $board_name = Utilite && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-utilite-pro.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine dtb to use; fi; \0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 2) \ + func(SATA, sata, 0) + +#include +#else +#define CONFIG_EXTRA_ENV_SETTINGS +#endif + +/* NAND */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* APBH DMA is required for NAND support */ +#endif + +/* Ethernet */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_FEC_XCV_TYPE RGMII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_ETHPRIME "FEC0" +#define CONFIG_ARP_TIMEOUT 200UL +#define CONFIG_NET_RETRY_COUNT 5 + +/* USB */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_MXC_I2C3_SPEED 400000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 2 + +/* SATA */ +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_LBA48 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR + +/* Boot */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CONFIG_SERIAL_TAG + +/* misc */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +/* SPL */ +#include "imx6_spl.h" + +/* Display */ +#define CONFIG_IMX_HDMI + +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO + +/* EEPROM */ +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#define CONFIG_SYS_EEPROM_SIZE 256 + +#endif /* __CONFIG_CM_FX6_H */ diff --git a/roms/u-boot/include/configs/cm_t335.h b/roms/u-boot/include/configs/cm_t335.h new file mode 100644 index 000000000..342cc7fdd --- /dev/null +++ b/roms/u-boot/include/configs/cm_t335.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Config file for Compulab CM-T335 board + * + * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ + * + * Author: Ilya Ledvich + */ + +#ifndef __CONFIG_CM_T335_H +#define __CONFIG_CM_T335_H + +#define CONFIG_CM_T335 + +#include + +#undef CONFIG_MAX_RAM_BANK_SIZE +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */ + +#define CONFIG_MACH_TYPE MACH_TYPE_CM_T335 + +/* Clock Defines */ +#define V_OSCK 25000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#ifndef CONFIG_SPL_BUILD +#define MMCARGS \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ + "mmcrootfstype=ext4\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" + +#define NANDARGS \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "nandroot=ubi0:rootfs rw\0" \ + "nandrootfstype=ubifs\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype} " \ + "ubi.mtd=${rootfs_name}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nboot ${loadaddr} nand0 900000; " \ + "bootm ${loadaddr}\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=82000000\0" \ + "console=ttyO0,115200n8\0" \ + "rootfs_name=rootfs\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + MMCARGS \ + NANDARGS + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_TIMESTAMP +#define CONFIG_SYS_AUTOLOAD "no" + +/* Serial console configuration */ + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 0 + +/* SPL */ + +/* Network. */ + +/* NAND support */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#undef CONFIG_SYS_NAND_U_BOOT_OFFS +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_SYS_NAND_ONFI_DETECTION +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000 +#endif + +/* GPIO pin + bank to pin ID mapping */ +#define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin) + +/* Status LED */ +/* Status LED polarity is inversed, so init it in the "off" state */ + +/* EEPROM */ +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#define CONFIG_SYS_EEPROM_SIZE 256 + +#ifndef CONFIG_SPL_BUILD +/* + * Enable PCA9555 at I2C0-0x26. + * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command. + */ +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR 0x26 +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} } +#endif /* CONFIG_SPL_BUILD */ + +#endif /* __CONFIG_CM_T335_H */ + diff --git a/roms/u-boot/include/configs/cm_t43.h b/roms/u-boot/include/configs/cm_t43.h new file mode 100644 index 000000000..73205d0de --- /dev/null +++ b/roms/u-boot/include/configs/cm_t43.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * cm_t43.h + * + * Copyright (C) 2015 Compulab, Ltd. + */ + +#ifndef __CONFIG_CM_T43_H +#define __CONFIG_CM_T43_H + +#define CONFIG_CM_T43 +#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ + +#include + +/* Serial support */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK 48000000 +#define CONFIG_SYS_NS16550_COM1 0x44e09000 +#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#endif + +/* NAND support */ +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +/* CPSW Ethernet support */ +#define CONFIG_SYS_RX_ETH_BUFFER 64 + +/* USB support */ +#define CONFIG_USB_XHCI_OMAP +#define CONFIG_AM437X_USB2PHY2_HOST + +/* Power */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_TPS65218 + +/* Enabling L2 Cache */ +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x48242000 + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_HSMMC2_8BIT + +#include +#undef CONFIG_SYS_MONITOR_LEN + +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "fdtaddr=0x81200000\0" \ + "bootm_size=0x8000000\0" \ + "autoload=no\0" \ + "console=ttyO0,115200n8\0" \ + "fdtfile=am437x-sb-som-t43.dtb\0" \ + "kernel=zImage-cm-t43\0" \ + "bootscr=bootscr.img\0" \ + "emmcroot=/dev/mmcblk0p2 rw\0" \ + "emmcrootfstype=ext4 rootwait\0" \ + "emmcargs=setenv bootargs console=${console} " \ + "root=${emmcroot} " \ + "rootfstype=${emmcrootfstype}\0" \ + "loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "emmcboot=echo Booting from emmc ... && " \ + "run emmcargs && " \ + "load mmc 1 ${loadaddr} ${kernel} && " \ + "load mmc 1 ${fdtaddr} ${fdtfile} && " \ + "bootz ${loadaddr} - ${fdtaddr}\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev 0; " \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "fi; " \ + "fi; " \ + "mmc dev 1; " \ + "if mmc rescan; then " \ + "run emmcboot; " \ + "fi;" + +/* SPL defines. */ +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) + +/* EEPROM */ +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#define CONFIG_SYS_EEPROM_SIZE 256 + +#endif /* __CONFIG_CM_T43_H */ diff --git a/roms/u-boot/include/configs/cobra5272.h b/roms/u-boot/include/configs/cobra5272.h new file mode 100644 index 000000000..c859616c6 --- /dev/null +++ b/roms/u-boot/include/configs/cobra5272.h @@ -0,0 +1,311 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the Sentec Cobra Board. + * + * (C) Copyright 2003 Josef Baumgartner + */ + +/* --- + * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board + * Date: 2004-03-29 + * Author: Florian Schlote + * + * For a description of configuration options please refer also to the + * general u-boot-1.x.x/README file + * --- + */ + +/* --- + * board/config.h - configuration options, board specific + * --- + */ + +#ifndef _CONFIG_COBRA5272_H +#define _CONFIG_COBRA5272_H + +/* --- + * Defines processor clock - important for correct timings concerning serial + * interface etc. + * --- + */ + +#define CONFIG_SYS_CLK 66000000 +#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ + +/* Enable Dma Timer */ +#define CONFIG_MCFTMR + +/* --- + * Define baudrate for UART1 (console output, tftp, ...) + * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud + * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command + * interface + * --- + */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +/* --- + * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change + * timeout acc. to your needs + * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000 + * for 10 sec + * --- + */ + +#if 0 +#define CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ +#endif + +/* --- + * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different + * bootloader residing in flash ('chainloading'); if you want to use + * chainloading or want to compile a u-boot binary that can be loaded into + * RAM via BDM set + * "#if 0" to "#if 1" + * You will need a first stage bootloader then, e. g. colilo or a working BDM + * cable (Background Debug Mode) + * + * Setting #if 0: u-boot will start from flash and relocate itself to RAM + * + * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE + * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000) + * + * --- + */ + +#if 0 +#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */ +#endif + +/* --- + * Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + * --- + */ + +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + env/embedded.o(.text); + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#ifdef CONFIG_MCFFEC +# define CONFIG_MII_INIT 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +/* + *----------------------------------------------------------------------------- + * Define user parameters that have to be customized most likely + *----------------------------------------------------------------------------- + */ + +/*AUTOBOOT settings - booting images automatically by u-boot after power on*/ + +/* The following settings will be contained in the environment block ; if you +want to use a neutral environment all those settings can be manually set in +u-boot: 'set' command */ + +#if 0 + +#define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please +enter a valid image address in flash */ + +/* User network settings */ + +#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */ +#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */ + +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address +from which user programs will be started */ + +/*---*/ + +/* + *----------------------------------------------------------------------------- + * End of user parameters to be customized + *----------------------------------------------------------------------------- + */ + +/* --- + * Defines memory range for test + * --- + */ + +/* --- + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * --- + */ + +/* --- + * Base register address + * --- + */ + +#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ + +/* --- + * System Conf. Reg. & System Protection Reg. + * --- + */ + +#define CONFIG_SYS_SCR 0x0003 +#define CONFIG_SYS_SPR 0xffff + +/* --- + * Ethernet settings + * --- + */ + +#define CONFIG_SYS_DISCOVER_PHY +#define CONFIG_SYS_ENET_BD_BASE 0x780000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in internal SRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +/* + *------------------------------------------------------------------------- + * RAM SIZE (is defined above) + *----------------------------------------------------------------------- + */ + +/* #define CONFIG_SYS_SDRAM_SIZE 16 */ + +/* + *----------------------------------------------------------------------- + */ + +#define CONFIG_SYS_FLASH_BASE 0xffe00000 + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_BASE 0x20000 +#else +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif + +#define CONFIG_SYS_MONITOR_LEN 0x20000 +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + +/*----------------------------------------------------------------------- + * Memory bank definitions + * + * Please refer also to Motorola Coldfire user manual - Chapter XXX + * + */ +#define CONFIG_SYS_BR0_PRELIM 0xFFE00201 +#define CONFIG_SYS_OR0_PRELIM 0xFFE00014 + +#define CONFIG_SYS_BR1_PRELIM 0 +#define CONFIG_SYS_OR1_PRELIM 0 + +#define CONFIG_SYS_BR2_PRELIM 0 +#define CONFIG_SYS_OR2_PRELIM 0 + +#define CONFIG_SYS_BR3_PRELIM 0 +#define CONFIG_SYS_OR3_PRELIM 0 + +#define CONFIG_SYS_BR4_PRELIM 0 +#define CONFIG_SYS_OR4_PRELIM 0 + +#define CONFIG_SYS_BR5_PRELIM 0 +#define CONFIG_SYS_OR5_PRELIM 0 + +#define CONFIG_SYS_BR6_PRELIM 0 +#define CONFIG_SYS_OR6_PRELIM 0 + +#define CONFIG_SYS_BR7_PRELIM 0x00000701 +#define CONFIG_SYS_OR7_PRELIM 0xFF00007C + +/*----------------------------------------------------------------------- + * LED config + */ +#define LED_STAT_0 0xffff /*all LEDs off*/ +#define LED_STAT_1 0xfffe +#define LED_STAT_2 0xfffd +#define LED_STAT_3 0xfffb +#define LED_STAT_4 0xfff7 +#define LED_STAT_5 0xffef +#define LED_STAT_6 0xffdf +#define LED_STAT_7 0xff00 /*all LEDs on*/ + +/*----------------------------------------------------------------------- + * Port configuration (GPIO) + */ +#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external +GPIO*/ +#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs +(1^=output, 0^=input) */ +#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ +#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART +configuration */ +#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ +#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */ +#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */ + +#endif /* _CONFIG_COBRA5272_H */ diff --git a/roms/u-boot/include/configs/colibri-imx6ull.h b/roms/u-boot/include/configs/colibri-imx6ull.h new file mode 100644 index 000000000..22ee2ba03 --- /dev/null +++ b/roms/u-boot/include/configs/colibri-imx6ull.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2019 Toradex AG + * + * Configuration settings for the Colibri iMX6ULL module. + * + * based on colibri_imx7.h + */ + +#ifndef __COLIBRI_IMX6ULL_CONFIG_H +#define __COLIBRI_IMX6ULL_CONFIG_H + +#include "mx6_common.h" +#define CONFIG_IOMUX_LPSR + +#define PHYS_SDRAM_SIZE SZ_512M + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +/* Network */ +#define CONFIG_TFTP_TSIZE + +/* ENET1 */ +#define IMX_FEC_BASE ENET2_BASE_ADDR + +/* MMC Config */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +/* I2C configs */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1 + +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "fdt_addr_r=0x82100000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ + "ramdisk_addr_r=0x82200000\0" \ + "scriptaddr=0x87000000\0" + +#define UBOOT_UPDATE \ + "update_uboot=nand erase.part u-boot1 && " \ + "nand write ${loadaddr} u-boot1 ${filesize} && " \ + "nand erase.part u-boot2 && " \ + "nand write ${loadaddr} u-boot2 ${filesize}\0" + +#define NFS_BOOTCMD \ + "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ + "nfsboot=run setup; " \ + "setenv bootargs ${defargs} ${nfsargs} " \ + "${setupargs} ${vidargs}; echo Booting from NFS...;" \ + "dhcp ${kernel_addr_r} && " \ + "tftp ${fdt_addr_r} ${fdtfile} && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define UBI_BOOTCMD \ + "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rw rootfstype=ubifs " \ + "ubi.fm_autoconvert=1\0" \ + "ubiboot=run setup; " \ + "setenv bootargs ${defargs} ${ubiargs} " \ + "${setupargs} ${vidargs} ${tdxargs}; echo Booting from NAND...; " \ + "ubi part ubi &&" \ + "ubi read ${kernel_addr_r} kernel && " \ + "ubi read ${fdt_addr_r} dtb && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +/* Run Distro Boot script if ubiboot fails */ +#define CONFIG_BOOTCOMMAND "run ubiboot || run distro_bootcmd;" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include + +#define DFU_ALT_NAND_INFO "imx6ull-bcb part 0,1;u-boot1 part 0,2;u-boot2 part 0,3;u-boot-env part 0,4;ubi partubi 0,5" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + MEM_LAYOUT_ENV_SETTINGS \ + NFS_BOOTCMD \ + UBI_BOOTCMD \ + UBOOT_UPDATE \ + "bootubipart=ubi\0" \ + "console=ttymxc0\0" \ + "defargs=user_debug=30\0" \ + "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ + "fdt_board=eval-v3\0" \ + "fdt_fixup=;\0" \ + "ip_dyn=yes\0" \ + "kernel_file=zImage\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ + "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ + "${board}/flash_eth.img && source ${loadaddr}\0" \ + "setsdupdate=mmc rescan && setenv interface mmc && " \ + "fatload ${interface} 0:1 ${loadaddr} " \ + "${board}/flash_blk.img && source ${loadaddr}\0" \ + "setup=setenv setupargs " \ + "console=tty1 console=${console}" \ + ",${baudrate}n8 ${memargs} consoleblank=0\0" \ + "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ + "setusbupdate=usb start && setenv interface usb && " \ + "fatload ${interface} 0:1 ${loadaddr} " \ + "${board}/flash_blk.img && source ${loadaddr}\0" \ + "splashpos=m,m\0" \ + "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ + "vidargs=video=mxsfb:640x480M-16@60" + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */ +#define CONFIG_SYS_NAND_BASE -1 +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_USBD_HS + +/* USB Device Firmware Update support */ +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) +#define CONFIG_VIDEO_MXS +#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#endif /* __COLIBRI_IMX6ULL_CONFIG_H */ diff --git a/roms/u-boot/include/configs/colibri-imx8x.h b/roms/u-boot/include/configs/colibri-imx8x.h new file mode 100644 index 000000000..59593f6c0 --- /dev/null +++ b/roms/u-boot/include/configs/colibri-imx8x.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Toradex + */ + +#ifndef __COLIBRI_IMX8X_H +#define __COLIBRI_IMX8X_H + +#include +#include +#include + +#define CONFIG_REMAKE_ELF + +#define CONFIG_DISPLAY_BOARDINFO_LATE + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5b010000 +#define USDHC2_BASE_ADDR 0x5b020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* Networking */ +#define CONFIG_TFTP_TSIZE + +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1 + +#define MEM_LAYOUT_ENV_SETTINGS \ + "fdt_addr_r=0x83000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "ramdisk_addr_r=0x83800000\0" \ + "scriptaddr=0x80800000\0" + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#define MFG_NAND_PARTITION "" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) +#include +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs ${consoleargs} " \ + "rdinit=/linuxrc g_mass_storage.stall=0 " \ + "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \ + "g_mass_storage.idProduct=0x37FF " \ + "g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \ + "${vidargs} clk_ignore_unused\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \ + "${fdt_addr};\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + AHAB_ENV \ + BOOTENV \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + MEM_LAYOUT_ENV_SETTINGS \ + "boot_file=Image\0" \ + "consoleargs=console=ttyLP3,${baudrate} earlycon\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_file=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \ + "fdtfile=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "image=Image\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcargs=setenv bootargs ${consoleargs} " \ + "root=PARTUUID=${uuid} rootwait " \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "netargs=setenv bootargs ${consoleargs} " \ + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \ + "${vidargs}\0" \ + "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ + "colibri-imx8x/${fdt_file}; booti ${loadaddr} - " \ + "${fdt_addr}\0" \ + "panel=NULL\0" \ + "script=boot.scr\0" \ + "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ + "if test \"$confirm\" = \"y\"; then " \ + "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ + "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ + "${blkcnt}; fi\0" \ + "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Environment in eMMC, before config block at the end of 1st "boot sector" */ + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE SZ_2K +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#define BOOTAUX_RESERVED_MEM_BASE 0x88000000 +#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */ + +#endif /* __COLIBRI_IMX8X_H */ diff --git a/roms/u-boot/include/configs/colibri_imx6.h b/roms/u-boot/include/configs/colibri_imx6.h new file mode 100644 index 000000000..804a144a0 --- /dev/null +++ b/roms/u-boot/include/configs/colibri_imx6.h @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013-2019 Toradex, Inc. + * + * Configuration settings for the Toradex Colibri iMX6 + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "mx6_common.h" + +#undef CONFIG_DISPLAY_BOARDINFO + +#include +#include + +#ifdef CONFIG_SPL +#include "imx6_spl.h" +#endif + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SERIAL_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* I2C Configs */ +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_MXC_I2C3_SPEED 400000 + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* USB Configs */ +/* Host */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +/* Client */ +#define CONFIG_USBD_HS + +/* Framebuffer and LCD */ +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +/* Command definition */ + +#undef CONFIG_IPADDR +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#undef CONFIG_SERVERIP +#define CONFIG_SERVERIP 192.168.10.1 + +#define CONFIG_LOADADDR 0x12000000 + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" +#else /* CONFIG_SPL_BUILD */ +#define BOOTENV +#endif /* CONFIG_SPL_BUILD */ + +#define UBOOT_UPDATE \ + "uboot_hwpart=1\0" \ + "uboot_blk=8a\0" \ + "uboot_spl_blk=2\0" \ + "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \ + "setexpr blkcnt ${blkcnt} / 0x200\0" \ + "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ + "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ + "update_spl=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ + "mmc write ${loadaddr} ${uboot_spl_blk} ${blkcnt}\0" + +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "fdt_addr_r=0x12100000\0" \ + "kernel_addr_r=0x11000000\0" \ + "pxefile_addr_r=0x17100000\0" \ + "ramdisk_addr_r=0x12200000\0" \ + "scriptaddr=0x17000000\0" + +#define NFS_BOOTCMD \ + "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ + "nfsboot=run setup; " \ + "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \ + "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ + "run nfsdtbload; dhcp ${kernel_addr_r} " \ + "&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \ + "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \ + "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + +#define FDT_FILE "imx6dl-colibri-eval-v3.dtb" +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "bootcmd=run distro_bootcmd; " \ + "usb start ; " \ + "setenv stdout serial,vidconsole; " \ + "setenv stdin serial,usbkbd\0" \ + "boot_file=zImage\0" \ + "console=ttymxc0\0" \ + "defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \ + "fdt_file=" FDT_FILE "\0" \ + "fdtfile=" FDT_FILE "\0" \ + "fdt_fixup=;\0" \ + MEM_LAYOUT_ENV_SETTINGS \ + NFS_BOOTCMD \ + UBOOT_UPDATE \ + "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ + "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ + "flash_eth.img && source ${loadaddr}\0" \ + "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \ + "${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "setup=setenv setupargs fec_mac=${ethaddr} " \ + "consoleblank=0 no_console_suspend=1 console=tty1 " \ + "console=${console},${baudrate}n8\0 " \ + "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ + "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ + "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "splashpos=m,m\0" \ + "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "vidargs=fbmem=8M\0" + +/* Miscellaneous configurable options */ +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 48 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/colibri_imx7.h b/roms/u-boot/include/configs/colibri_imx7.h new file mode 100644 index 000000000..2fffaa39c --- /dev/null +++ b/roms/u-boot/include/configs/colibri_imx7.h @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016-2018 Toradex AG + * + * Configuration settings for the Colibri iMX7 module. + * + * based on mx7dsabresd.h: + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __COLIBRI_IMX7_CONFIG_H +#define __COLIBRI_IMX7_CONFIG_H + +#include "mx7_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#elif CONFIG_TARGET_COLIBRI_IMX7_EMMC +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +/* I2C configs */ +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1 + +#if defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) +#define UBOOT_UPDATE \ + "uboot_hwpart=1\0" \ + "uboot_blk=2\0" \ + "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \ + "setexpr blkcnt ${blkcnt} / 0x200\0" \ + "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ + "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" +#elif defined(CONFIG_TARGET_COLIBRI_IMX7_NAND) +#define UBOOT_UPDATE \ + "update_uboot=nand erase.part u-boot1 && " \ + "nand write ${loadaddr} u-boot1 ${filesize} && " \ + "nand erase.part u-boot2 && " \ + "nand write ${loadaddr} u-boot2 ${filesize}\0" +#endif + +#ifndef PARTS_DEFAULT +/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \ + /* Android partitions */ \ + "partitions_android=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=boot,start=1M,size=32M,uuid=${uuid_gpt_boot};" \ + "name=environment,size=4M,uuid=${uuid_gpt_environment};" \ + "name=recovery,size=16M,uuid=${uuid_gpt_recovery};" \ + "name=system,size=1536M,uuid=${uuid_gpt_system};" \ + "name=cache,size=512M,uuid=${uuid_gpt_cache};" \ + "name=device,size=8M,uuid=${uuid_gpt_device};" \ + "name=misc,size=4M,uuid=${uuid_gpt_misc};" \ + "name=datafooter,size=2M,uuid=${uuid_gpt_datafooter};" \ + "name=metadata,size=2M,uuid=${uuid_gpt_metadata};" \ + "name=persistdata,size=2M,uuid=${uuid_gpt_persistdata};" \ + "name=userdata,size=128M,uuid=${uuid_gpt_userdata};" \ + "name=fbmisc,size=-,uuid=${uuid_gpt_fbmisc}\0" +#endif /* PARTS_DEFAULT */ + +#define EMMC_ANDROID_BOOTCMD \ + "android_args=androidboot.storage_type=emmc\0" \ + PARTS_DEFAULT \ + "android_fdt_addr=0x83700000\0" \ + "android_mmc_dev=0\0" \ + "m4binary=rpmsg_imu_freertos.elf\0" \ + "androidboot=ext4load mmc 0:a ${loadaddr} media/0/${m4binary}; "\ + "bootaux ${loadaddr}; " \ + "setenv loadaddr 0x88000000; " \ + "setenv bootm_boot_mode sec;" \ + "setenv bootargs androidboot.serialno=${serial#} " \ + "$android_args; " \ + "part start mmc ${android_mmc_dev} boot boot_start; " \ + "part size mmc ${android_mmc_dev} boot boot_size; " \ + "mmc read ${loadaddr} ${boot_start} ${boot_size}; " \ + "part start mmc ${android_mmc_dev} environment env_start; " \ + "part size mmc ${android_mmc_dev} environment env_size; " \ + "mmc read ${android_fdt_addr} ${env_start} ${env_size}; " \ + "bootm ${loadaddr} ${loadaddr} ${android_fdt_addr}\0 " + +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "fdt_addr_r=0x82000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ + "ramdisk_addr_r=0x82100000\0" \ + "scriptaddr=0x87000000\0" + +#define NFS_BOOTCMD \ + "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ + "nfsboot=run setup; " \ + "setenv bootargs ${defargs} ${nfsargs} " \ + "${setupargs} ${vidargs}; echo Booting from NFS...;" \ + "dhcp ${kernel_addr_r} && " \ + "tftp ${fdt_addr_r} ${soc}-colibri${variant}-${fdt_board}.dtb && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define UBI_BOOTCMD \ + "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ + "ubi.fm_autoconvert=1\0" \ + "ubiboot=run setup; " \ + "setenv bootargs ${defargs} ${ubiargs} " \ + "${setupargs} ${vidargs} ${tdxargs}; echo Booting from NAND...; " \ + "ubi part ubi && run m4boot && " \ + "ubi read ${kernel_addr_r} kernel && " \ + "ubi read ${fdt_addr_r} dtb && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND) +#define CONFIG_BOOTCOMMAND "run ubiboot ; echo ; echo ubiboot failed ; " \ + "run distro_bootcmd;" +#define MODULE_EXTRA_ENV_SETTINGS \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + UBI_BOOTCMD +#elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) +#define MODULE_EXTRA_ENV_SETTINGS \ + "variant=-emmc\0" \ + EMMC_ANDROID_BOOTCMD +#endif + +#if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND) +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#endif +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + MEM_LAYOUT_ENV_SETTINGS \ + NFS_BOOTCMD \ + MODULE_EXTRA_ENV_SETTINGS \ + UBOOT_UPDATE \ + "boot_file=zImage\0" \ + "bootubipart=ubi\0" \ + "console=ttymxc0\0" \ + "defargs=\0" \ + "fdt_board=eval-v3\0" \ + "fdt_fixup=;\0" \ + "m4boot=;\0" \ + "ip_dyn=yes\0" \ + "kernel_file=zImage\0" \ + "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ + "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ + "${board}/flash_eth.img && source ${loadaddr}\0" \ + "setsdupdate=mmc rescan && setenv interface mmc && " \ + "fatload ${interface} 0:1 ${loadaddr} " \ + "${board}/flash_blk.img && source ${loadaddr}\0" \ + "setup=setenv setupargs " \ + "console=tty1 console=${console}" \ + ",${baudrate}n8 ${memargs} consoleblank=0\0" \ + "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ + "setusbupdate=usb start && setenv interface usb && " \ + "fatload ${interface} 0:1 ${loadaddr} " \ + "${board}/flash_blk.img && source ${loadaddr}\0" \ + "splashpos=m,m\0" \ + "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ + "updlevel=2\0" + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES +#endif + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_USBD_HS + +#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#endif diff --git a/roms/u-boot/include/configs/colibri_pxa270.h b/roms/u-boot/include/configs/colibri_pxa270.h new file mode 100644 index 000000000..3dedcdaad --- /dev/null +++ b/roms/u-boot/include/configs/colibri_pxa270.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Toradex Colibri PXA270 configuration file + * + * Copyright (C) 2010 Marek Vasut + * Copyright (C) 2015-2016 Marcel Ziswiler + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Board Configuration Options + */ +#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ +/* Avoid overwriting factory configuration block */ +#define CONFIG_BOARD_SIZE_LIMIT 0x40000 + +/* + * Environment settings + */ +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) +#define CONFIG_BOOTCOMMAND \ + "if fatload mmc 0 0xa0000000 uImage; then " \ + "bootm 0xa0000000; " \ + "fi; " \ + "if usb reset && fatload usb 0 0xa0000000 uImage; then " \ + "bootm 0xa0000000; " \ + "fi; " \ + "bootm 0xc0000;" +#define CONFIG_TIMESTAMP +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +/* + * Serial Console Configuration + */ + +/* + * Bootloader Components Configuration + */ + +/* I2C support */ +#ifdef CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_PXA +#define CONFIG_PXA_STD_I2C +#define CONFIG_PXA_PWR_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* LCD support */ +#ifdef CONFIG_LCD +#define CONFIG_PXA_LCD +#define CONFIG_PXA_VGA +#define CONFIG_LCD_LOGO +#endif + +/* + * Networking Configuration + */ +#ifdef CONFIG_CMD_NET + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x08000000 +#define DM9000_IO (CONFIG_DM9000_BASE) +#define DM9000_DATA (CONFIG_DM9000_BASE + 4) +#define CONFIG_NET_RETRY_COUNT 10 + +#define CONFIG_BOOTP_BOOTFILESIZE +#endif + +/* + * Clock Configuration + */ +#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ + +/* + * DRAM Map + */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ + +#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 + +/* + * NOR FLASH + */ +#ifdef CONFIG_CMD_FLASH +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT + +#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ) +#endif + +#define CONFIG_SYS_MONITOR_BASE 0x0 +#define CONFIG_SYS_MONITOR_LEN 0x40000 + +/* Skip factory configuration block */ + +/* + * GPIO settings + */ +#define CONFIG_SYS_GPSR0_VAL 0x00000000 +#define CONFIG_SYS_GPSR1_VAL 0x00020000 +#define CONFIG_SYS_GPSR2_VAL 0x0002c000 +#define CONFIG_SYS_GPSR3_VAL 0x00000000 + +#define CONFIG_SYS_GPCR0_VAL 0x00000000 +#define CONFIG_SYS_GPCR1_VAL 0x00000000 +#define CONFIG_SYS_GPCR2_VAL 0x00000000 +#define CONFIG_SYS_GPCR3_VAL 0x00000000 + +#define CONFIG_SYS_GPDR0_VAL 0xc8008000 +#define CONFIG_SYS_GPDR1_VAL 0xfc02a981 +#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff +#define CONFIG_SYS_GPDR3_VAL 0x0061e804 + +#define CONFIG_SYS_GAFR0_L_VAL 0x80100000 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010 +#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008 +#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002 +#define CONFIG_SYS_GAFR3_L_VAL 0x54000310 +#define CONFIG_SYS_GAFR3_U_VAL 0x00005401 + +#define CONFIG_SYS_PSSR_VAL 0x30 + +/* + * Clock settings + */ +#define CONFIG_SYS_CKEN 0x00500240 +#define CONFIG_SYS_CCCR 0x02000290 + +/* + * Memory settings + */ +#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2 +#define CONFIG_SYS_MSC1_VAL 0x9ee1f994 +#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1 +#define CONFIG_SYS_MDCNFG_VAL 0x090009c9 +#define CONFIG_SYS_MDREFR_VAL 0x2003a031 +#define CONFIG_SYS_MDMRS_VAL 0x00220022 +#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 +#define CONFIG_SYS_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CONFIG_SYS_MECR_VAL 0x00000000 +#define CONFIG_SYS_MCMEM0_VAL 0x00028307 +#define CONFIG_SYS_MCMEM1_VAL 0x00014307 +#define CONFIG_SYS_MCATT0_VAL 0x00038787 +#define CONFIG_SYS_MCATT1_VAL 0x0001c787 +#define CONFIG_SYS_MCIO0_VAL 0x0002830f +#define CONFIG_SYS_MCIO1_VAL 0x0001430f + +#include "pxa-common.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/colibri_t20.h b/roms/u-boot/include/configs/colibri_t20.h new file mode 100644 index 000000000..94e17bbb7 --- /dev/null +++ b/roms/u-boot/include/configs/colibri_t20.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Lucas Stach + * + * Configuration settings for the Toradex Colibri T20 modules. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra20-common.h" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_TEGRA_UARTA_SDIO1 +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_TEGRA2 + +/* General networking support */ +#define CONFIG_TFTP_TSIZE + +/* LCD support */ +#define CONFIG_LCD_LOGO + +/* NAND support */ +#define CONFIG_TEGRA_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define UBOOT_UPDATE \ + "update_uboot=nand erase.part u-boot && " \ + "nand write ${loadaddr} u-boot ${filesize}\0" \ + +/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */ +#define BOARD_EXTRA_ENV_SETTINGS \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + UBOOT_UPDATE + +/* Increase console I/O buffer size */ +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 + +/* Increase arguments buffer size */ +#undef CONFIG_SYS_BARGSIZE +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Increase maximum number of arguments */ +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 32 + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/colibri_t30.h b/roms/u-boot/include/configs/colibri_t30.h new file mode 100644 index 000000000..94802a66f --- /dev/null +++ b/roms/u-boot/include/configs/colibri_t30.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2013-2016 Stefan Agner + * + * Configuration settings for the Toradex Colibri T30 modules. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra30-common.h" + +/* High-level configuration options */ + +/* + * Board-specific serial config + * + * Colibri UART-A: NVIDIA UARTA + * Colibri UART-B: NVIDIA UARTD + * Colibri UART-C: NVIDIA UARTB + */ +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T30 + +/* General networking support */ +#define CONFIG_TFTP_TSIZE + +/* Increase console I/O buffer size */ +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 + +/* Increase arguments buffer size */ +#undef CONFIG_SYS_BARGSIZE +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Increase maximum number of arguments */ +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 32 + +#define UBOOT_UPDATE \ + "uboot_hwpart=1\0" \ + "uboot_blk=0\0" \ + "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \ + "setexpr blkcnt ${blkcnt} / 0x200\0" \ + "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ + "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ + +#define BOARD_EXTRA_ENV_SETTINGS \ + UBOOT_UPDATE + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/colibri_vf.h b/roms/u-boot/include/configs/colibri_vf.h new file mode 100644 index 000000000..cae7c14bf --- /dev/null +++ b/roms/u-boot/include/configs/colibri_vf.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015-2019 Toradex, Inc. + * + * Configuration settings for the Toradex VF50/VF61 modules. + * + * Based on vf610twr.h: + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#ifdef CONFIG_VIDEO_FSL_DCU_FB +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_SYS_FSL_DCU_LE + +#define CONFIG_SYS_DCU_ADDR DCU0_BASE_ADDR +#define DCU_LAYER_MAX_NUM 64 +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) + +/* NAND support */ +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1 + +#define CONFIG_LOADADDR 0x80008000 +#define CONFIG_FDTADDR 0x84000000 + +/* We boot from the gfxRAM area of the OCRAM. */ +#define CONFIG_BOARD_SIZE_LIMIT 520192 + +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "fdt_addr_r=0x82000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ + "ramdisk_addr_r=0x82100000\0" \ + "scriptaddr=0x87000000\0" + +#define UBOOT_UPDATE \ + "update_uboot=nand erase.part u-boot && " \ + "nand write ${loadaddr} u-boot ${filesize}\0" \ + +#define NFS_BOOTCMD \ + "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ + "nfsboot=run setup; " \ + "setenv bootargs ${defargs} ${nfsargs} ${mtdparts} " \ + "${setupargs} ${vidargs}; echo Booting from NFS...;" \ + "dhcp ${kernel_addr_r} && " \ + "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define UBI_BOOTCMD \ + "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ + "ubi.fm_autoconvert=1\0" \ + "ubiboot=run setup; " \ + "setenv bootargs ${defargs} ${ubiargs} ${mtdparts} " \ + "${setupargs} ${vidargs}; echo Booting from NAND...; " \ + "ubi part ubi && " \ + "ubi read ${kernel_addr_r} kernel && " \ + "ubi read ${fdt_addr_r} dtb && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define CONFIG_BOOTCOMMAND "run ubiboot || run distro_bootcmd;" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" + +#define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + MEM_LAYOUT_ENV_SETTINGS \ + NFS_BOOTCMD \ + UBI_BOOTCMD \ + UBOOT_UPDATE \ + "console=ttyLP0\0" \ + "defargs=user_debug=30\0" \ + "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ + "fdt_board=eval-v3\0" \ + "fdt_fixup=;\0" \ + "kernel_image=zImage\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "setsdupdate=mmc rescan && set interface mmc && " \ + "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "setup=setenv setupargs console=tty1 console=${console}" \ + ",${baudrate}n8 ${memargs}\0" \ + "setupdate=run setsdupdate || run setusbupdate\0" \ + "setusbupdate=usb start && set interface usb && " \ + "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "splashpos=m,m\0" \ + "video-mode=dcufb:640x480-16@60,monitor=lcd\0" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical memory map */ +#define PHYS_SDRAM (0x80000000) +#define PHYS_SDRAM_SIZE (256 * SZ_1M) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_RANGE (4 * 64 * 2048) +#endif + +/* USB Host Support */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +/* USB DFU */ +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/comtrend_ar5315u.h b/roms/u-boot/include/configs/comtrend_ar5315u.h new file mode 100644 index 000000000..71a1af1cd --- /dev/null +++ b/roms/u-boot/include/configs/comtrend_ar5315u.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + diff --git a/roms/u-boot/include/configs/comtrend_ar5387un.h b/roms/u-boot/include/configs/comtrend_ar5387un.h new file mode 100644 index 000000000..7b195749a --- /dev/null +++ b/roms/u-boot/include/configs/comtrend_ar5387un.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + diff --git a/roms/u-boot/include/configs/comtrend_ct5361.h b/roms/u-boot/include/configs/comtrend_ct5361.h new file mode 100644 index 000000000..2a28e6c62 --- /dev/null +++ b/roms/u-boot/include/configs/comtrend_ct5361.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + diff --git a/roms/u-boot/include/configs/comtrend_vr3032u.h b/roms/u-boot/include/configs/comtrend_vr3032u.h new file mode 100644 index 000000000..c4c7029c7 --- /dev/null +++ b/roms/u-boot/include/configs/comtrend_vr3032u.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif /* CONFIG_MTD_RAW_NAND */ diff --git a/roms/u-boot/include/configs/comtrend_wap5813n.h b/roms/u-boot/include/configs/comtrend_wap5813n.h new file mode 100644 index 000000000..c8cddaf12 --- /dev/null +++ b/roms/u-boot/include/configs/comtrend_wap5813n.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + diff --git a/roms/u-boot/include/configs/condor.h b/roms/u-boot/include/configs/condor.h new file mode 100644 index 000000000..36466f0f5 --- /dev/null +++ b/roms/u-boot/include/configs/condor.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/condor.h + * This file is Condor board configuration. + * + * Copyright (C) 2019 Renesas Electronics Corporation + */ + +#ifndef __CONDOR_H +#define __CONDOR_H + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_BITBANGMII_MULTI + +/* Environment compatibility */ + +/* SH Ether */ +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +/* XTAL_CLK : 33.33MHz */ +#define CONFIG_SYS_CLK_FREQ 33333333u + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +#endif /* __CONDOR_H */ diff --git a/roms/u-boot/include/configs/conga-qeval20-qa3-e3845.h b/roms/u-boot/include/configs/conga-qeval20-qa3-e3845.h new file mode 100644 index 000000000..01b67f7e2 --- /dev/null +++ b/roms/u-boot/include/configs/conga-qeval20-qa3-e3845.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Stefan Roese + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND \ + "load scsi 0:2 03000000 /boot/vmlinuz-${kernel-ver}-generic;" \ + "load scsi 0:2 04000000 /boot/initrd.img-${kernel-ver}-generic;" \ + "run boot" + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel-ver=4.4.0-22\0" \ + "boot=zboot 03000000 0 04000000 ${filesize}\0" \ + "upd_uboot=tftp 100000 conga/u-boot.rom;" \ + "sf probe;sf update 100000 0 800000;saveenv\0" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/controlcenterdc.h b/roms/u-boot/include/configs/controlcenterdc.h new file mode 100644 index 000000000..869b94bc9 --- /dev/null +++ b/roms/u-boot/include/configs/controlcenterdc.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Stefan Roese + * Copyright (C) 2016 Mario Six + */ + +#ifndef _CONFIG_CONTROLCENTERDC_H +#define _CONFIG_CONTROLCENTERDC_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_CUSTOMER_BOARD_SUPPORT + +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ + +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +#define CONFIG_LOADADDR 1000000 + +/* + * SATA/SCSI/AHCI configuration + */ +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +/* Environment in SPI NOR flash */ + +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* + * Software (bit-bang) MII driver configuration + */ +#define CONFIG_BITBANGMII_MULTI + +/* SPL */ +/* + * Select the boot device here + * + * Currently supported are: + * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash + * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) + */ +#define SPL_BOOT_SPI_NOR_FLASH 1 +#define SPL_BOOT_SDIO_MMC_CARD 2 +#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH + +/* Defines for SPL */ +#define CONFIG_SPL_SIZE (160 << 10) + +#if defined(CONFIG_SECURED_MODE_IMAGE) +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614) +#else +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30) +#endif + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT + +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH +/* SPL related SPI defines */ +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS +#endif + +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD +/* SPL related MMC defines */ +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 +#define CONFIG_SYS_MMC_U_BOOT_OFFS (168 << 10) +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ +#endif +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_HOSTNAME "ccdc" +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "ccdc.img" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth1\0" \ + "consoledev=ttyS1\0" \ + "u-boot=u-boot.bin\0" \ + "bootfile_addr=1000000\0" \ + "keyprogram_addr=3000000\0" \ + "keyprogram_file=keyprogram.img\0" \ + "fdtfile=controlcenterdc.dtb\0" \ + "load=tftpboot ${loadaddr} ${u-boot}\0" \ + "mmcdev=0:2\0" \ + "update=sf probe 1:0;" \ + " sf erase 0 +${filesize};" \ + " sf write ${fileaddr} 0 ${filesize}\0" \ + "upd=run load update\0" \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" \ + "loadkeyprogram=tpm flush_keys;" \ + " mmc rescan;" \ + " ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\ + " source ${keyprogram_addr}:script@1\0" \ + "gpio1=gpio@22_25\0" \ + "gpio2=A29\0" \ + "blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 " \ + "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0" \ + "bootfail=for i in ${blinkseq}; do" \ + " if test $i -eq 0; then" \ + " gpio clear ${gpio1}; gpio set ${gpio2};" \ + " elif test $i -eq 1; then" \ + " gpio clear ${gpio1}; gpio clear ${gpio2};" \ + " elif test $i -eq 2; then" \ + " gpio set ${gpio1}; gpio set ${gpio2};" \ + " else;" \ + " gpio clear ${gpio1}; gpio set ${gpio2};" \ + " fi; sleep 0.12; done\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \ + "console=${consoledev},${baudrate} ${othbootargs}; " \ + "tftpboot ${bootfile_addr} ${bootfile}; " \ + "bootm ${bootfile_addr}" + +#define CONFIG_MMCBOOTCOMMAND \ + "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ + "console=${consoledev},${baudrate} ${othbootargs}; " \ + "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \ + "bootm ${bootfile_addr}" + +#define CONFIG_BOOTCOMMAND \ + "if env exists keyprogram; then;" \ + " setenv keyprogram; run nfsboot;" \ + " fi;" \ + " run dobootfail" + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#endif /* _CONFIG_CONTROLCENTERDC_H */ diff --git a/roms/u-boot/include/configs/coreboot.h b/roms/u-boot/include/configs/coreboot.h new file mode 100644 index 000000000..1cf5c037e --- /dev/null +++ b/roms/u-boot/include/configs/coreboot.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, Bin Meng + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +/* ATA/IDE support */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 4 +#define CONFIG_SYS_ATA_BASE_ADDR 0 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 +#define CONFIG_SYS_ATA_ALT_OFFSET 0 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 +#define CONFIG_ATAPI + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/corenet_ds.h b/roms/u-boot/include/configs/corenet_ds.h new file mode 100644 index 000000000..d0843c284 --- /dev/null +++ b/roms/u-boot/include/configs/corenet_ds.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2009-2012 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + */ + +/* + * Corenet DS style board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "../board/freescale/common/ics307_clk.h" + +#ifdef CONFIG_RAMBOOT_PBL +#ifdef CONFIG_NXP_ESBC +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_RAMBOOT_NAND +#endif +#define CONFIG_BOOTSCRIPT_COPY_RAM +#else +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg +#if defined(CONFIG_TARGET_P3041DS) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg +#elif defined(CONFIG_TARGET_P4080DS) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg +#elif defined(CONFIG_TARGET_P5020DS) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg +#elif defined(CONFIG_TARGET_P5040DS) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg +#endif +#endif +#endif + +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +/* High Level Configuration Options */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#if defined(CONFIG_SPIFLASH) +#elif defined(CONFIG_SDCARD) +#define CONFIG_FSL_FIXED_MMC_LOCATION +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) +#else +#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#endif +#define CONFIG_SYS_L3_SIZE (1024 << 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD + +#define CONFIG_SYS_SPD_BUS_NUM 1 +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * Local Bus Definitions + */ + +/* Set the local bus clock 1/8 of platform clock */ +#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 + +#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_FLASH_BR_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ + | BR_PS_16 | BR_V) +#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ + | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) + +#define CONFIG_SYS_BR1_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 + +#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#ifdef CONFIG_PHYS_64BIT +#define PIXIS_BASE_PHYS 0xfffdf0000ull +#else +#define PIXIS_BASE_PHYS PIXIS_BASE +#endif + +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ + +#define PIXIS_LBMAP_SWITCH 7 +#define PIXIS_LBMAP_MASK 0xf0 +#define PIXIS_LBMAP_SHIFT 4 +#define PIXIS_LBMAP_ALTBANK 0x40 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Nand Flash */ +#ifdef CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* NAND flash config */ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | (2<> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull +#else +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#endif +#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + */ +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) +#elif defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 +#else +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) + +#ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#endif /* CONFIG_PCI */ + +/* SATA */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c +#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d +#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e +#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f +#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 + +#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c +#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d +#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e +#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f +#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 + +#define CONFIG_SYS_TBIPA_VALUE 8 +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* +* USB +*/ +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_HAS_FSL_MPH_USB + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif + +#ifdef CONFIG_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#ifdef CONFIG_TARGET_P4080DS +#define __USB_PHY_TYPE ulpi +#else +#define __USB_PHY_TYPE utmi +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ + "bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=p4080ds/ramdisk.uboot\0" \ + "fdtaddr=1e00000\0" \ + "fdtfile=p4080ds/p4080ds.dtb\0" \ + "bdev=sda3\0" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT + +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/corvus.h b/roms/u-boot/include/configs/corvus.h new file mode 100644 index 000000000..55f77e440 --- /dev/null +++ b/roms/u-boot/include/configs/corvus.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Common board functions for siemens AT91SAM9G45 based boards + * (C) Copyright 2013 Siemens AG + * + * Based on: + * U-Boot file: include/configs/at91sam9m10g45ek.h + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +/* + * Warning: changing CONFIG_SYS_TEXT_BASE requires + * adapting the initial boot program. + * Since the linker has to swallow that define, we must use a pure + * hex number here! + */ + +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ + +/* serial console */ +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS + +/* LED */ +#define CONFIG_AT91_LED +#define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */ +#define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */ + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + SZ_32K - GENERATED_GBL_DATA_SIZE) + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 +#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT +#endif + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_AT91_WANTS_COMMON_PHY + +/* DFU class support */ +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) +#define DFU_MANIFEST_POLL_TIMEOUT 25000 + +#define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6 + +/* bootstrap + u-boot + env in nandflash */ + +#define CONFIG_BOOTCOMMAND \ + "nand read 0x70000000 0x200000 0x300000;" \ + "bootm 0x70000000" + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ + SZ_4M, 0x1000) + +/* Defines for SPL */ +#define CONFIG_SPL_MAX_SIZE (12 * SZ_1K) +#define CONFIG_SPL_STACK (SZ_16K) + +#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_BSS_MAX_SIZE (SZ_2K) + +#define CONFIG_SPL_NAND_RAW_ONLY +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K +#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } + +#define CONFIG_SPL_ATMEL_SIZE +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define AT91_PLL_LOCK_TIMEOUT 1000000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO + +#endif diff --git a/roms/u-boot/include/configs/cougarcanyon2.h b/roms/u-boot/include/configs/cougarcanyon2.h new file mode 100644 index 000000000..353756193 --- /dev/null +++ b/roms/u-boot/include/configs/cougarcanyon2.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016, Bin Meng + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (2 << 20) + +#define CONFIG_SMSC_SIO1007 + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +/* Environment configuration */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/crownbay.h b/roms/u-boot/include/configs/crownbay.h new file mode 100644 index 000000000..4c118080c --- /dev/null +++ b/roms/u-boot/include/configs/crownbay.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014, Bin Meng + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_SMSC_LPC47M + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +/* Environment configuration */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/crs3xx-98dx3236.h b/roms/u-boot/include/configs/crs3xx-98dx3236.h new file mode 100644 index 000000000..e2ba7b812 --- /dev/null +++ b/roms/u-boot/include/configs/crs3xx-98dx3236.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Stefan Roese + */ + +#ifndef _CONFIG_CRS3XX_98DX3236_H +#define _CONFIG_CRS3XX_98DX3236_H + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* 64 MB */ +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg +#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +/* Environment in SPI NOR flash */ + +/* Keep device tree and initrd in lower memory so the kernel can access them */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 96 + +#endif /* _CONFIG_CRS3XX_98DX3236_H */ diff --git a/roms/u-boot/include/configs/da850evm.h b/roms/u-boot/include/configs/da850evm.h new file mode 100644 index 000000000..883cbc95d --- /dev/null +++ b/roms/u-boot/include/configs/da850evm.h @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on davinci_dvevm.h. Original Copyrights follow: + * + * Copyright (C) 2007 Sergey Kubushyn + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Board + */ + +/* + * SoC Configuration + */ +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH +#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) +#define CONFIG_SYS_OSCIN_FREQ 24000000 +#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY + +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) +#endif + +/* + * Memory Info + */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ +#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ +#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ +#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE +#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 +/* memtest start addr */ + +/* memtest will be run on 16MB */ + +#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ + DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ + DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ + DAVINCI_SYSCFG_SUSPSRC_UART2 | \ + DAVINCI_SYSCFG_SUSPSRC_EMAC | \ + DAVINCI_SYSCFG_SUSPSRC_I2C) + +/* + * PLL configuration + */ + +#define CONFIG_SYS_DA850_PLL0_PLLM 24 +#define CONFIG_SYS_DA850_PLL1_PLLM 21 + +/* + * DDR2 memory configuration + */ +#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ + DV_DDR_PHY_EXT_STRBEN | \ + (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ + (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ + (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ + (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ + (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ + (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ + (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ + (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) + +/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ +#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 + +#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ + (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ + (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ + (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ + (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ + (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ + (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ + (0 << DV_DDR_SDTMR1_WTR_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ + (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ + (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ + (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ + (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ + (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ + (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ + (0 << DV_DDR_SDTMR2_CKE_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 +#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 + +/* + * Serial Driver info + */ +#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) + +#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) + +/* + * I2C Configuration + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 +#endif + +/* + * Flash & Environment + */ +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_SYS_NAND_CS 3 +#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE +#define CONFIG_SYS_NAND_MASK_CLE 0x10 +#define CONFIG_SYS_NAND_MASK_ALE 0x8 +#undef CONFIG_SYS_NAND_HW_ECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 +#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ + CONFIG_SYS_NAND_U_BOOT_SIZE - \ + CONFIG_SYS_MALLOC_LEN - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_NAND_ECCPOS { \ + 24, 25, 26, 27, 28, \ + 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ + 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ + 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ + 59, 60, 61, 62, 63 } +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 10 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SPL_NAND_LOAD + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_NAND_SELF_INIT +#endif +#endif + +/* + * Network & Ethernet Configuration + */ +#ifdef CONFIG_DRIVER_TI_EMAC +#define CONFIG_NET_RETRY_COUNT 10 +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ +#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ +#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE +#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ +#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ + + 3) +#endif + +/* + * U-Boot general configuration + */ +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) + +/* + * Linux Information + */ +#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) +#define CONFIG_HWCONFIG /* enable hwconfig */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#define CONFIG_BOOTCOMMAND \ + "run envboot; " \ + "run mmcboot; " + +#define DEFAULT_LINUX_BOOT_ENV \ + "loadaddr=0xc0700000\0" \ + "fdtaddr=0xc0600000\0" \ + "scriptaddr=0xc0600000\0" + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "fdtfile=da850-evm.dtb\0" \ + "boot_fdt=yes\0" \ + "boot_fit=0\0" \ + "console=ttyS2,115200n8\0" \ + "hwconfig=dsp:wake=yes" + +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + +/* USB Configs */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 + +#ifndef CONFIG_MTD_NOR_FLASH +#define CONFIG_SPL_PAD_TO 32768 +#endif + +#ifdef CONFIG_SPL_BUILD +/* defines for SPL */ +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN +#define CONFIG_SPL_STACK 0x8001ff00 +#define CONFIG_SPL_MAX_FOOTPRINT 32768 + +#endif + +/* Load U-Boot Image From MMC */ + +/* additions for new relocation code, must added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0xc0000000 + +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 +#else +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ + GENERATED_GBL_DATA_SIZE) +#endif /* CONFIG_MTD_NOR_FLASH */ + +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/dalmore.h b/roms/u-boot/include/configs/dalmore.h new file mode 100644 index 000000000..18d9ba178 --- /dev/null +++ b/roms/u-boot/include/configs/dalmore.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra114-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Dalmore" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTD +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_DALMORE + +/* Environment in eMMC, at the end of 2nd "boot sector" */ + +/* SPI */ +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/dart_6ul.h b/roms/u-boot/include/configs/dart_6ul.h new file mode 100644 index 000000000..dccfa034a --- /dev/null +++ b/roms/u-boot/include/configs/dart_6ul.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Board configuration file for Variscite DART-6UL Evaluation Kit + * Copyright (C) 2019 Parthiban Nallathambi + */ +#ifndef __DART_6UL_H +#define __DART_6UL_H + +#include +#include +#include "mx6_common.h" + +/* SPL options */ +#include "imx6_spl.h" + +/* NAND pin conflicts with usdhc2 */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_ENET_DEV 0 +#if (CONFIG_FEC_ENET_DEV == 0) +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define CONFIG_ETHPRIME "eth1" +#endif +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +/* Environment settings */ + +/* Environment in SD */ +#define MMC_ROOTFS_DEV 0 +#define MMC_ROOTFS_PART 2 + +/* Console configs */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ + +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CONFIG_SUPPORT_EMMC_BOOT + +/* I2C configs */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_512M + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define ENV_MMC \ + "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ + "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ + "fitpart=1\0" \ + "bootdelay=3\0" \ + "silent=1\0" \ + "optargs=rw rootwait\0" \ + "mmcautodetect=yes\0" \ + "mmcrootfstype=ext4\0" \ + "mmcfit_name=fitImage\0" \ + "mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \ + "${mmcfit_name}\0" \ + "mmcargs=setenv bootargs " \ + "root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \ + "console=${console} rootfstype=${mmcrootfstype}\0" \ + "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \ + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0,115200n8\0" \ + "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ + "fit_addr=0x82000000\0" \ + ENV_MMC + +#define CONFIG_BOOTCOMMAND "run mmc_mmc_fit" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(DHCP, dhcp, na) + +#include +#endif /* __DART_6UL_H */ diff --git a/roms/u-boot/include/configs/db-88f6720.h b/roms/u-boot/include/configs/db-88f6720.h new file mode 100644 index 000000000..213883ef0 --- /dev/null +++ b/roms/u-boot/include/configs/db-88f6720.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Stefan Roese + */ + +#ifndef _CONFIG_DB_88F6720_H +#define _CONFIG_DB_88F6720_H + +/* + * High Level Configuration Options (easy to change) + */ + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ +#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 + +/* Environment in SPI NOR flash */ + +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * Memory layout while starting into the bin_hdr via the + * BootROM: + * + * 0x4000.4000 - 0x4003.4000 headers space (192KiB) + * 0x4000.4030 bin_hdr start address + * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) + * 0x4007.fffc BootROM stack top + * + * The address space between 0x4007.fffc and 0x400f.fff is not locked in + * L2 cache thus cannot be used. + */ + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +/* SPL related SPI defines */ +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS + +#endif /* _CONFIG_DB_88F6720_H */ diff --git a/roms/u-boot/include/configs/db-88f6820-amc.h b/roms/u-boot/include/configs/db-88f6820-amc.h new file mode 100644 index 000000000..fe9a7ab56 --- /dev/null +++ b/roms/u-boot/include/configs/db-88f6820-amc.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Stefan Roese + */ + +#ifndef _CONFIG_DB_88F6820_AMC_H +#define _CONFIG_DB_88F6820_AMC_H + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +/* Environment in SPI NOR flash */ + +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* NAND */ +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* Keep device tree and initrd in lower memory so the kernel can access them */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +/* SPL */ +/* + * Select the boot device here + * + * Currently supported are: + * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash + * + * MMC is not populated on this board. + * NAND support may be added in the future. + */ +#define SPL_BOOT_SPI_NOR_FLASH 1 +#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH + +/* Defines for SPL */ +#define CONFIG_SPL_SIZE (140 << 10) +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH +/* SPL related SPI defines */ +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS +#endif + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 96 + +#endif /* _CONFIG_DB_88F6820_AMC_H */ diff --git a/roms/u-boot/include/configs/db-88f6820-gp.h b/roms/u-boot/include/configs/db-88f6820-gp.h new file mode 100644 index 000000000..ed851bc67 --- /dev/null +++ b/roms/u-boot/include/configs/db-88f6820-gp.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Stefan Roese + */ + +#ifndef _CONFIG_DB_88F6820_GP_H +#define _CONFIG_DB_88F6820_GP_H + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* + * SATA/SCSI/AHCI configuration + */ +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +/* Environment in SPI NOR flash */ + +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* Keep device tree and initrd in lower memory so the kernel can access them */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +/* SPL */ +/* + * Select the boot device here + * + * Currently supported are: + * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash + * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) + */ +#define SPL_BOOT_SPI_NOR_FLASH 1 +#define SPL_BOOT_SDIO_MMC_CARD 2 +#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH + +/* Defines for SPL */ +#define CONFIG_SPL_SIZE (140 << 10) +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH +/* SPL related SPI defines */ +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS +#endif + +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD +/* SPL related MMC defines */ +#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS +#ifdef CONFIG_SPL_BUILD +#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ +#endif +#endif + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#endif /* _CONFIG_DB_88F6820_GP_H */ diff --git a/roms/u-boot/include/configs/db-mv784mp-gp.h b/roms/u-boot/include/configs/db-mv784mp-gp.h new file mode 100644 index 000000000..3e20516e9 --- /dev/null +++ b/roms/u-boot/include/configs/db-mv784mp-gp.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014-2015 Stefan Roese + */ + +#ifndef _CONFIG_DB_MV7846MP_GP_H +#define _CONFIG_DB_MV7846MP_GP_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_DB_784MP_GP /* Board target name for DDR training */ + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 + +/* Environment in SPI NOR flash */ + +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* SATA support */ +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_LBA48 + +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* NAND */ +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * Memory layout while starting into the bin_hdr via the + * BootROM: + * + * 0x4000.4000 - 0x4003.4000 headers space (192KiB) + * 0x4000.4030 bin_hdr start address + * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) + * 0x4007.fffc BootROM stack top + * + * The address space between 0x4007.fffc and 0x400f.fff is not locked in + * L2 cache thus cannot be used. + */ + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +/* SPL related SPI defines */ +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS + +/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ +#define CONFIG_SPD_EEPROM 0x4e +#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ + +#endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/roms/u-boot/include/configs/db-xc3-24g4xg.h b/roms/u-boot/include/configs/db-xc3-24g4xg.h new file mode 100644 index 000000000..0e9ccd9b4 --- /dev/null +++ b/roms/u-boot/include/configs/db-xc3-24g4xg.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Stefan Roese + */ + +#ifndef _CONFIG_DB_XC3_24G4G_H +#define _CONFIG_DB_XC3_24G4G_H + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg +#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +/* Environment in SPI NOR flash */ + +/* NAND */ +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* Keep device tree and initrd in lower memory so the kernel can access them */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 96 + +#endif /* _CONFIG_DB_XC3_24G4G_H */ diff --git a/roms/u-boot/include/configs/deneb.h b/roms/u-boot/include/configs/deneb.h new file mode 100644 index 000000000..a33165c1c --- /dev/null +++ b/roms/u-boot/include/configs/deneb.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Siemens AG + * + */ + +#ifndef __DENEB_H +#define __DENEB_H + +#include "capricorn-common.h" + +#undef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "06") + +/* DDR3 board total DDR is 2 GB */ +#undef PHYS_SDRAM_1_SIZE +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ + +#endif /* __DENEB_H */ diff --git a/roms/u-boot/include/configs/devkit3250.h b/roms/u-boot/include/configs/devkit3250.h new file mode 100644 index 000000000..5d2b77b4a --- /dev/null +++ b/roms/u-boot/include/configs/devkit3250.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Embest/Timll DevKit3250 board configuration file + * + * Copyright (C) 2011-2015 Vladimir Zapolskiy + */ + +#ifndef __CONFIG_DEVKIT3250_H__ +#define __CONFIG_DEVKIT3250_H__ + +/* SoC and board defines */ +#include +#include + +#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250 + +#if !defined(CONFIG_SPL_BUILD) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * Memory configurations + */ +#define CONFIG_SYS_MALLOC_LEN SZ_1M +#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CONFIG_SYS_SDRAM_SIZE SZ_64M + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ + - GENERATED_GBL_DATA_SIZE) + +/* + * Serial Driver + */ +#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */ + +/* + * DMA + */ +#if !defined(CONFIG_SPL_BUILD) +#define CONFIG_DMA_LPC32XX +#endif + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_LPC32XX +#define CONFIG_SYS_I2C_SPEED 100000 + +/* + * GPIO + */ +#define CONFIG_LPC32XX_GPIO + +/* + * Ethernet + */ +#define CONFIG_RMII +#define CONFIG_LPC32XX_ETH +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN + +/* + * NOR Flash + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 71 +#define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE +#define CONFIG_SYS_FLASH_SIZE SZ_4M + +/* + * NAND controller + */ +#define CONFIG_SYS_NAND_BASE SLC_NAND_BASE +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } + +/* + * NAND chip timings + */ +#define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14 +#define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 +#define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 +#define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 +#define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14 +#define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 +#define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000 +#define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 + +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE + +/* + * USB + */ +#define CONFIG_USB_OHCI_LPC32XX +#define CONFIG_USB_ISP1301_I2C_ADDR 0x2d + +/* + * U-Boot General Configurations + */ +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * Pass open firmware flat tree + */ + +/* + * Environment + */ + +#define CONFIG_BOOTCOMMAND \ + "dhcp; " \ + "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \ + "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \ + "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \ + "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \ + "bootm ${loadaddr} - ${dtbaddr}" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ + "ethaddr=00:01:90:00:C0:81\0" \ + "dtbaddr=0x81000000\0" \ + "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \ + "tftpdir=vladimir/oe/devkit3250\0" \ + "userargs=oops=panic\0" + +/* + * U-Boot Commands + */ + +/* + * Boot Linux + */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR 0x80008000 + +/* + * SPL specific defines + */ +/* SPL will be executed at offset 0 */ + +/* SPL will use SRAM as stack */ +#define CONFIG_SPL_STACK 0x0000FFF8 + +/* Use the framework and generic lib */ + +/* SPL will use serial */ + +/* SPL loads an image from NAND */ +#define CONFIG_SPL_NAND_RAW_ONLY + +#define CONFIG_SPL_NAND_SOFTECC + +#define CONFIG_SPL_MAX_SIZE 0x20000 +#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE + +/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE + +/* See common/spl/spl.c spl_set_header_raw_uboot() */ +#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE + +/* + * Include SoC specific configuration + */ +#include + +#endif /* __CONFIG_DEVKIT3250_H__*/ diff --git a/roms/u-boot/include/configs/devkit8000.h b/roms/u-boot/include/configs/devkit8000.h new file mode 100644 index 000000000..87da4410f --- /dev/null +++ b/roms/u-boot/include/configs/devkit8000.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments. + * Richard Woodruff + * Syed Mohammed Khasim + * + * (C) Copyright 2009 + * Frederik Kriewitz + * + * Configuration settings for the DevKit8000 board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ + +#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ + +/* Physical Memory Map */ + +#include + +#define CONFIG_REVISION_TAG 1 + +/* Size of malloc() pool */ +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) + +/* Hardware drivers */ +/* DM9000 */ +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x2c000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) +#define CONFIG_DM9000_USE_16BIT 1 +#define CONFIG_DM9000_NO_SROM 1 +#undef CONFIG_DM9000_DEBUG + +/* TWL4030 */ + +/* Board NAND Info */ +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ + /* partition */ + +/* BOOTP/DHCP options */ +#define CONFIG_BOOTP_NISDOMAIN +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_TIMEOFFSET +#undef CONFIG_BOOTP_VENDOREX + +/* Environment information */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "mmcdev=0\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \ + "kernelopts=rw\0" \ + "commonargs=" \ + "setenv bootargs console=${console} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapdss.def_disp=${defaultdisplay}\0" \ + "mmcargs=" \ + "run commonargs; " \ + "setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk0p2 " \ + "rootwait " \ + "${kernelopts}\0" \ + "nandargs=" \ + "run commonargs; " \ + "setenv bootargs ${bootargs} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=/dev/mtdblock4 " \ + "rootfstype=jffs2 " \ + "${kernelopts}\0" \ + "netargs=" \ + "run commonargs; " \ + "setenv bootargs ${bootargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ + "${kernelopts} " \ + "dnsip1=${dnsip} " \ + "dnsip2=${dnsip2}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + "netboot=echo Booting from network ...; " \ + "dhcp ${loadaddr}; " \ + "run netargs; " \ + "bootm ${loadaddr}\0" \ + "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi\0" + +#define CONFIG_BOOTCOMMAND "run autoboot" + +/* Boot Argument Buffer Size */ + +/* Defines for SPL */ + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 + +/* SPL OS boot options */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 + +#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR +#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR +#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ + +#undef CONFIG_SYS_SPL_ARGS_ADDR +#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/dfi-bt700.h b/roms/u-boot/include/configs/dfi-bt700.h new file mode 100644 index 000000000..6d0e68e5d --- /dev/null +++ b/roms/u-boot/include/configs/dfi-bt700.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Stefan Roese + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#ifndef CONFIG_INTERNAL_UART +/* Use BayTrail internal HS UART which is memory-mapped */ +#undef CONFIG_SYS_NS16550_PORT_MAPPED +#endif + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND \ + "load scsi 0:1 03000000 /boot/vmlinuz-${kernel-ver}-generic;" \ + "load scsi 0:1 04000000 /boot/initrd.img-${kernel-ver}-generic;" \ + "run boot" + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel-ver=4.4.0-24\0" \ + "boot=zboot 03000000 0 04000000 ${filesize}\0" \ + "upd_uboot=usb reset;tftp 100000 dfi/u-boot.rom;" \ + "sf probe;sf update 100000 0 800000;saveenv\0" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/dh_imx6.h b/roms/u-boot/include/configs/dh_imx6.h new file mode 100644 index 000000000..4a469af5e --- /dev/null +++ b/roms/u-boot/include/configs/dh_imx6.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * DHCOM DH-iMX6 PDK board configuration + * + * Copyright (C) 2017 Marek Vasut + */ + +#ifndef __DH_IMX6_CONFIG_H +#define __DH_IMX6_CONFIG_H + +#include + +#include "mx6_common.h" + +/* + * SPI NOR layout: + * 0x00_0000-0x00_ffff ... U-Boot SPL + * 0x01_0000-0x0f_ffff ... U-Boot + * 0x10_0000-0x10_ffff ... U-Boot env #1 + * 0x11_0000-0x11_ffff ... U-Boot env #2 + * 0x12_0000-0x1f_ffff ... UNUSED + */ + +/* SPL */ +#include "imx6_spl.h" /* common IMX6 SPL configuration */ +#define CONFIG_SPL_TARGET "u-boot-with-spl.imx" + +/* Miscellaneous configurable options */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) + +/* Bootcounter */ +#define CONFIG_SYS_BOOTCOUNT_BE + +/* FEC ethernet */ +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_ARP_TIMEOUT 200UL + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +/* SATA Configs */ +#define CONFIG_LBA48 + +/* UART */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ + +/* USB Gadget (DFU, UMS) */ +#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* USB IDs */ +#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 +#endif +#endif + +/* Watchdog */ +#if defined(CONFIG_SPL_BUILD) +#undef CONFIG_WDT +#undef CONFIG_WATCHDOG +#define CONFIG_HW_WATCHDOG +#endif + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200\0" \ + "fdt_addr=0x18000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x10008000\0" \ + "fdt_addr_r=0x13000000\0" \ + "ramdisk_addr_r=0x18000000\0" \ + "scriptaddr=0x14000000\0" \ + "fdtfile=imx6q-dhcom-pdk2.dtb\0"\ + BOOTENV + +#define CONFIG_BOOTCOMMAND "run distro_bootcmd" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 2) \ + func(USB, usb, 1) \ + func(SATA, sata, 0) \ + func(DHCP, dhcp, na) + +#include +#endif + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment */ + +#endif /* __DH_IMX6_CONFIG_H */ diff --git a/roms/u-boot/include/configs/dh_stm32mp1.h b/roms/u-boot/include/configs/dh_stm32mp1.h new file mode 100644 index 000000000..89d317ba2 --- /dev/null +++ b/roms/u-boot/include/configs/dh_stm32mp1.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2020 Marek Vasut + * + * Configuration settings for the DH STM32MP15x SoMs + */ + +#ifndef __CONFIG_DH_STM32MP1_H__ +#define __CONFIG_DH_STM32MP1_H__ + +#include + +#define CONFIG_SPL_TARGET "u-boot.itb" + +#endif diff --git a/roms/u-boot/include/configs/display5.h b/roms/u-boot/include/configs/display5.h new file mode 100644 index 000000000..40bb3b53a --- /dev/null +++ b/roms/u-boot/include/configs/display5.h @@ -0,0 +1,350 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + +/* Falcon Mode */ +#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 + +/* Falcon Mode - MMC support */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x3F00 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS \ + (CONFIG_CMD_SPL_WRITE_SIZE / 512) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x100 /* 128KiB */ + +/* + * display5 SPI-NOR memory layout + * + * The definition can be found in Kconfig's + * CONFIG_MTDIDS_DEFAULT and CONFIG_MTDPARTS_DEFAULT + * + * 0x000000 - 0x020000 : SPI.SPL (128KiB) + * 0x020000 - 0x120000 : SPI.u-boot (1MiB) + * 0x120000 - 0x130000 : SPI.u-boot-env1 (64KiB) + * 0x130000 - 0x140000 : SPI.u-boot-env2 (64KiB) + * 0x140000 - 0x740000 : SPI.swupdate-kernel-FIT (6MiB) + * 0x740000 - 0x1B40000 : SPI.swupdate-initramfs (20MiB) + * 0x1B40000 - 0x1F00000 : SPI.reserved (3840KiB) + * 0x1F00000 - 0x2000000 : SPI.factory (1MiB) + */ + +/* SPI Flash Configs */ +#if defined(CONFIG_SPL_BUILD) +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#endif + +/* Below values are "dummy" - only to avoid build break */ +#define CONFIG_SYS_SPI_KERNEL_OFFS 0x150000 +#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 +#define CONFIG_SYS_SPI_ARGS_SIZE 0x10000 + +#include "imx6_spl.h" + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) + +#define CONFIG_MXC_UART_BASE UART5_BASE + +/* I2C Configs */ +#define CONFIG_I2C_MULTI_BUS + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#ifndef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "if run check_em_pad; then " \ + "run recovery;" \ + "else if test ${BOOT_FROM} = FACTORY; then " \ + "run factory_nfs;" \ + "else " \ + "run boot_mmc;" \ + "fi;fi" +#endif + +#define PARTS_DEFAULT \ + /* Linux partitions */ \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=kernel_raw1,start=128K,size=8M,uuid=${uuid_gpt_kernel_raw1};" \ + "name=rootfs1,size=1528M,uuid=${uuid_gpt_rootfs1};" \ + "name=kernel_raw2,size=8M,uuid=${uuid_gpt_kernel_raw2};" \ + "name=rootfs2,size=512M,uuid=${uuid_gpt_rootfs2};" \ + "name=data,size=-,uuid=${uuid_gpt_data}\0" + +#define SWUPDATE_RECOVERY_PROCEDURE \ + "echo '#######################';" \ + "echo '# RECOVERY SWUupdate #';" \ + "echo '#######################';" \ + "echo '#######################';" \ + "echo '# GPT verify #';" \ + "if gpt verify mmc ${mmcdev} ${partitions}; then " \ + "echo '# OK ! #';" \ + "else " \ + "echo '# FAILED ! #';" \ + "echo '# GPT RESTORATION #';" \ + "gpt write mmc ${mmcdev} ${partitions};" \ + "fi;" \ + "echo '#######################';" \ + "setenv loadaddr_swu_initramfs 0x14000000;" \ + "setenv bootargs console=${console} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}::off root=/dev/ram rw;" \ + "sf probe;" \ + "sf read ${loadaddr} swu-kernel;" \ + "sf read ${loadaddr_swu_initramfs} swu-initramfs;" \ + "bootm ${loadaddr} ${loadaddr_swu_initramfs};reset;" + +#define SETUP_BOOTARGS \ + "run set_rootfs_part;" \ + "setenv bootargs ${bootargs} console=${console} " \ + "root=/dev/mmcblk${mmcdev}p${rootfs_part} " \ + "rootwait rootfstype=ext4 rw; " \ + "run set_kernel_part;" \ + "part start mmc ${mmcdev} ${kernel_part} lba_start; " \ + "mmc read ${loadaddr} ${lba_start} ${fitImg_fw_sz}; " \ + "setenv fdt_conf imx6q-${board}-${display}.dtb; " + +/* All the numbers are in LBAs */ +#define __TFTP_UPDATE_KERNEL \ + "tftp_mmc_fitImg=" \ + "if test ! -n ${kernel_part}; then " \ + "setenv kernel_part ${kernel_part_active};" \ + "fi;" \ + "if tftp ${loadaddr} ${kernel_file}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "part start mmc ${mmcdev} ${kernel_part} lba_start; " \ + "mmc write ${loadaddr} ${lba_start} ${fw_sz}; " \ + "; fi\0" \ + +#define TFTP_UPDATE_KERNEL \ + "setenv kernel_part ${kernel_part_active};" \ + "run tftp_mmc_fitImg;" \ + "setenv kernel_part ${kernel_part_backup};" \ + "run tftp_mmc_fitImg;" \ + +#define __TFTP_UPDATE_ROOTFS \ + "tftp_mmc_rootfs=" \ + "if test ! -n ${rootfs_part}; then " \ + "setenv rootfs_part ${rootfs_part_active};" \ + "fi;" \ + "if tftp ${loadaddr} ${rootfs_file}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "part start mmc ${mmcdev} ${rootfs_part} lba_start; " \ + "mmc write ${loadaddr} ${lba_start} ${fw_sz}; " \ + "; fi\0" \ + +#define TFTP_UPDATE_ROOTFS \ + "setenv rootfs_part ${rootfs_part_active};" \ + "run tftp_mmc_rootfs;" \ + "run tftp_mmc_rootfs_bkp;" \ + + +#define TFTP_UPDATE_RECOVERY_SWU_KERNEL \ + "tftp_sf_fitImg_SWU=" \ + "if tftp ${loadaddr} ${kernel_file}; then " \ + "sf probe;" \ + "sf erase swu-kernel +${filesize};" \ + "sf write ${loadaddr} swu-kernel ${filesize};" \ + "; fi\0" \ + +#define TFTP_UPDATE_RECOVERY_SWU_INITRAMFS \ + "swu_initramfs_file=swupdate-image-display5.ext4.gz.u-boot\0" \ + "tftp_sf_initramfs_SWU=" \ + "if tftp ${loadaddr} ${swu_initramfs_file}; then " \ + "sf probe;" \ + "sf erase swu-initramfs +${filesize};" \ + "sf write ${loadaddr} swu-initramfs ${filesize};" \ + "; fi\0" \ + +#define TFTP_UPDATE_BOOTLOADER \ + "ubootfile=u-boot.img\0" \ + "ubootfileSPL=SPL\0" \ + "tftp_sf_uboot=" \ + "if tftp ${loadaddr} ${ubootfile}; then " \ + "sf probe;" \ + "sf erase u-boot +${filesize};" \ + "sf write ${loadaddr} u-boot ${filesize}" \ + "; fi\0" \ + "tftp_sf_SPL=" \ + "if tftp ${loadaddr} ${ubootfileSPL}; then " \ + "sf probe;" \ + "setexpr uboot_SPL_size ${filesize} + 0x400;" \ + "sf erase 0x0 +${uboot_SPL_size};" \ + "sf write ${loadaddr} 0x400 ${filesize};" \ + "fi\0" \ + +#define TFTP_UPDATE_SPINOR \ + "spinorfile=core-image-lwn-display5.spinor\0" \ + "spinorsize=0x2000000\0" \ + "tftp_sf_img=" \ + "if tftp ${loadaddr} ${spinorfile}; then " \ + "sf probe;" \ + "sf erase 0x0 ${spinorsize};" \ + "sf write ${loadaddr} 0x0 ${filesize};" \ + "fi\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + PARTS_DEFAULT \ + "gpio_recovery=93\0" \ + "check_em_pad=gpio input ${gpio_recovery};test $? -eq 0;\0" \ + "display=tianma-tm070-800x480\0" \ + "board=display5\0" \ + "mmcdev=0\0" \ + "altbootcmd=run recovery\0" \ + "bootdelay=1\0" \ + "baudrate=115200\0" \ + "bootcmd=" CONFIG_BOOTCOMMAND "\0" \ + "ethact=FEC\0" \ + "netdev=eth0\0" \ + "boot_os=y\0" \ + "hostname=display5\0" \ + "loadaddr=0x12000000\0" \ + "fdtaddr=0x12800000\0" \ + "console=ttymxc4,115200 quiet cma=256M\0" \ + "fdtfile=imx6q-display5.dtb\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_file=fitImage\0" \ + "fitImg_fw_sz=0x2200\0" \ + "up=run tftp_sf_SPL; run tftp_sf_uboot\0" \ + "download_kernel=" \ + "tftpboot ${loadaddr} ${kernel_file};\0" \ + "factory_nfs=" \ + "setenv ipaddr 192.168.1.102;" \ + "setenv gatewayip 192.168.1.1;" \ + "setenv netmask 255.255.255.0;" \ + "setenv serverip 192.168.1.2;" \ + "echo BOOT: FACTORY (LEG);" \ + "run boot_nfs\0" \ + "boot_swu_recovery=" SWUPDATE_RECOVERY_PROCEDURE "\0" \ + "recovery=" \ + "echo BOOT: RECOVERY: SWU;" \ + "run boot_swu_recovery\0" \ + "boot_tftp=" \ + "if run download_kernel; then " \ + "setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rootwait;" \ + "bootm ${loadaddr} - ${fdtaddr};reset;" \ + "fi\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ + "${hostname}:eth0:on" \ + "\0" \ + "nfsargs=setenv bootargs " \ + "root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},nolock,nfsvers=3" \ + "\0" \ + "rootpath=/srv/tftp/DISP5/rootfs\0" \ + "boot_nfs=" \ + "if run download_kernel; then " \ + "run nfsargs;" \ + "run addip;" \ + "setenv bootargs ${bootargs} console=${console};" \ + "setenv fdt_conf imx6q-${board}-${display}.dtb; " \ + "bootm ${loadaddr}#conf@${fdt_conf};reset;" \ + "fi\0" \ + "falcon_setup=" \ + "if mmc dev ${mmcdev}; then " \ + SETUP_BOOTARGS \ + "spl export fdt ${loadaddr}#conf@${fdt_conf};" \ + "setexpr fw_sz ${fdtargslen} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${fdtargsaddr} " \ + __stringify(CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR)" ${fw_sz}; " \ + "fi\0" \ + "boot_mmc=" \ + "if mmc dev ${mmcdev}; then " \ + SETUP_BOOTARGS \ + "bootm ${loadaddr}#conf@${fdt_conf};reset;" \ + "fi\0" \ + "set_kernel_part=" \ + "if test ${BOOT_FROM} = ACTIVE; then " \ + "setenv kernel_part ${kernel_part_active};" \ + "echo BOOT: ACTIVE;" \ + "else if test ${BOOT_FROM} = BACKUP; then " \ + "setenv kernel_part ${kernel_part_backup};" \ + "echo BOOT: BACKUP;" \ + "else " \ + "run recovery;" \ + "fi;fi\0" \ + "set_rootfs_part=" \ + "if test ${BOOT_FROM} = ACTIVE; then " \ + "setenv rootfs_part ${rootfs_part_active};" \ + "else if test ${BOOT_FROM} = BACKUP; then " \ + "setenv rootfs_part ${rootfs_part_backup};" \ + "else " \ + "run recovery;" \ + "fi;fi\0" \ + "BOOT_FROM=ACTIVE\0" \ + TFTP_UPDATE_BOOTLOADER \ + TFTP_UPDATE_SPINOR \ + "kernel_part_active=1\0" \ + "kernel_part_backup=3\0" \ + __TFTP_UPDATE_KERNEL \ + "rootfs_part_active=2\0" \ + "rootfs_part_backup=4\0" \ + "rootfs_file=core-image-lwn-display5.ext4\0" \ + "rootfs_file_backup=core-image-lwn-backup-display5.ext4\0" \ + __TFTP_UPDATE_ROOTFS \ + "tftp_mmc_rootfs_bkp=" \ + "setenv rootfs_part ${rootfs_part_backup};" \ + "setenv rootfs_file ${rootfs_file_backup};" \ + "run tftp_mmc_rootfs\0" \ + TFTP_UPDATE_RECOVERY_SWU_KERNEL \ + TFTP_UPDATE_RECOVERY_SWU_INITRAMFS \ + "\0" \ + +/* Miscellaneous configurable options */ +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 2048 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_STANDALONE_LOAD_ADDR 0x10001000 +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Watchdog */ +#if defined(CONFIG_SPL_BUILD) +#undef CONFIG_WDT +#undef CONFIG_WATCHDOG +#define CONFIG_HW_WATCHDOG +#endif + +/* ENV config */ +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH +/* The 0x120000 value corresponds to above SPI-NOR memory MAP */ +#endif + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/dns325.h b/roms/u-boot/include/configs/dns325.h new file mode 100644 index 000000000..8990efb3f --- /dev/null +++ b/roms/u-boot/include/configs/dns325.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 + * Stefan Herbrechtsmeier + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + */ + +#ifndef _CONFIG_DNS325_H +#define _CONFIG_DNS325_H + +/* + * Machine number definition + */ +#define CONFIG_MACH_TYPE MACH_TYPE_DNS325 + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#endif + +/* + * Enable GPI0 support + */ +#define CONFIG_KIRKWOOD_GPIO + +/* + * Environment variables configurations + */ + +/* + * Default environment variables + */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "loadaddr=0x800000\0" \ + "autoload=no\0" \ + "console=ttyS0,115200\0" \ + "mtdparts="CONFIG_MTDPARTS_DEFAULT \ + "optargs=\0" \ + "bootenv=uEnv.txt\0" \ + "importbootenv=echo Importing environment ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "loadbootenv=fatload usb 0 ${loadaddr} ${bootenv}\0" \ + "setbootargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "${mtdparts} " \ + "root=${bootenvroot} " \ + "rootfstype=${bootenvrootfstype}\0" \ + "subbootcmd=run setbootargs; " \ + "if run bootenvloadimage; then " \ + "bootm ${loadaddr};" \ + "fi;\0" \ + "nandroot=ubi0:rootfs ubi.mtd=rootfs\0" \ + "nandrootfstype=ubifs\0" \ + "nandloadimage=nand read ${loadaddr} kernel\0" \ + "setnandbootenv=echo Booting from nand ...; " \ + "setenv bootenvroot ${nandroot}; " \ + "setenv bootenvrootfstype ${nandrootfstype}; " \ + "setenv bootenvloadimage ${nandloadimage}\0" + +#define CONFIG_BOOTCOMMAND \ + "if test -n ${bootenv} && usb start; then " \ + "if run loadbootenv; then " \ + "echo Loaded environment ${bootenv} from usb;" \ + "run importbootenv;" \ + "fi;" \ + "if test -n ${bootenvcmd}; then " \ + "echo Running bootenvcmd ...;" \ + "run bootenvcmd;" \ + "fi;" \ + "fi;" \ + "run setnandbootenv subbootcmd;" + +#endif /* _CONFIG_DNS325_H */ diff --git a/roms/u-boot/include/configs/dockstar.h b/roms/u-boot/include/configs/dockstar.h new file mode 100644 index 000000000..04dd0f68c --- /dev/null +++ b/roms/u-boot/include/configs/dockstar.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2010 Eric C. Cooper + * + * Based on sheevaplug.h originally written by + * Prafulla Wadaskar + * (C) Copyright 2009 + * Marvell Semiconductor + */ + +#ifndef _CONFIG_DOCKSTAR_H +#define _CONFIG_DOCKSTAR_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * Environment variables configurations + */ +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part root; " \ + "ubifsmount ubi:root; " \ + "ubifsload 0x800000 ${kernel}; " \ + "ubifsload 0x1100000 ${initrd}; " \ + "bootm 0x800000 0x1100000" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS_DEFAULT \ + "kernel=/boot/uImage\0" \ + "initrd=/boot/uInitrd\0" \ + "bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 +#endif /* CONFIG_CMD_NET */ + +/* + * File system + */ + +#endif /* _CONFIG_DOCKSTAR_H */ diff --git a/roms/u-boot/include/configs/dra7xx_evm.h b/roms/u-boot/include/configs/dra7xx_evm.h new file mode 100644 index 000000000..cc18bcece --- /dev/null +++ b/roms/u-boot/include/configs/dra7xx_evm.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated. + * Lokesh Vutla + * + * Configuration settings for the TI DRA7XX board. + * See ti_omap5_common.h for omap5 common settings. + */ + +#ifndef __CONFIG_DRA7XX_EVM_H +#define __CONFIG_DRA7XX_EVM_H + +#include + +#define CONFIG_IODELAY_RECALIBRATION + +#define CONFIG_VERY_BIG_RAM +#define CONFIG_MAX_MEM_MAPPED 0x80000000 + +#ifndef CONFIG_QSPI_BOOT +/* MMC ENV related defines */ +#endif + +#if (CONFIG_CONS_INDEX == 1) +#define CONSOLEDEV "ttyS0" +#elif (CONFIG_CONS_INDEX == 3) +#define CONSOLEDEV "ttyS2" +#endif +#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ + +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +#define CONFIG_SYS_OMAP_ABE_SYSCK + +#ifndef CONFIG_SPL_BUILD +#define DFUARGS \ + "dfu_bufsiz=0x10000\0" \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_EMMC \ + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_QSPI +#endif + +#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_SPL_DFU +#define DFUARGS \ + "dfu_bufsiz=0x10000\0" \ + DFU_ALT_INFO_RAM +#endif +#endif + +#include + +/* Enhance our eMMC support / experience. */ +#define CONFIG_HSMMC2_8BIT + +/* CPSW Ethernet */ +#define CONFIG_NET_RETRY_COUNT 10 + +/* + * Default to using SPI for environment, etc. + * 0x000000 - 0x040000 : QSPI.SPL (256KiB) + * 0x040000 - 0x140000 : QSPI.u-boot (1MiB) + * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB) + * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB) + * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB) + * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) + * 0x9E0000 - 0x2000000 : USERLAND + */ +#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 +#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 +#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 + +/* SPI SPL */ + +/* USB xHCI HOST */ +#define CONFIG_USB_XHCI_OMAP + +#define CONFIG_OMAP_USB2PHY2_HOST + +/* SATA */ +#define CONFIG_SCSI_AHCI_PLAT + +/* NAND support */ +#ifdef CONFIG_MTD_RAW_NAND +/* NAND: device related configs */ +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +/* NAND: driver related configs */ +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00140000 +/* NAND: SPL related configs */ +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ +#endif +#endif /* !CONFIG_MTD_RAW_NAND */ + +/* Parallel NOR Support */ +#if defined(CONFIG_NOR) +/* NOR: device related configs */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ +/* #define CONFIG_INIT_IGNORE_ERROR */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +/* Reduce SPL size by removing unlikey targets */ +#endif /* NOR support */ + +#endif /* __CONFIG_DRA7XX_EVM_H */ diff --git a/roms/u-boot/include/configs/draak.h b/roms/u-boot/include/configs/draak.h new file mode 100644 index 000000000..d28cc9d33 --- /dev/null +++ b/roms/u-boot/include/configs/draak.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/draak.h + * This file is Draak board configuration. + * + * Copyright (C) 2015 Renesas Electronics Corporation + */ + +#ifndef __DRAAK_H +#define __DRAAK_H + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_BITBANGMII_MULTI + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +/* Environment in eMMC, at the end of 2nd "boot sector" */ + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +#endif /* __DRAAK_H */ diff --git a/roms/u-boot/include/configs/draco.h b/roms/u-boot/include/configs/draco.h new file mode 100644 index 000000000..396eb7ded --- /dev/null +++ b/roms/u-boot/include/configs/draco.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef __CONFIG_DRACO_H +#define __CONFIG_DRACO_H + +#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DRACO + +#include "siemens-am33x-common.h" + +#define DDR_PLL_FREQ 303 + +#define BOARD_DFU_BUTTON_GPIO 27 /* Use as default */ +#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ + +#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + "button_dfu0=27\0" \ + "led0=103,1,0\0" \ + "led1=64,0,1\0" + + /* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define EEPROM_ADDR_DDR3 0x90 +#define EEPROM_ADDR_CHIP 0x120 + +#define CONFIG_FACTORYSET + +/* Define own nand partitions */ +#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) + +#ifndef CONFIG_SPL_BUILD + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=draco\0" \ + "ubi_off=2048\0"\ + "nand_img_size=0x400000\0" \ + "optargs=\0" \ + "preboot=draco_led 0\0" \ + CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + CONFIG_ENV_SETTINGS_V2 \ + CONFIG_ENV_SETTINGS_NAND_V2 + +#ifndef CONFIG_RESTORE_FLASH +/* set to negative value for no autoboot */ + +#define CONFIG_BOOTCOMMAND \ +"if dfubutton; then " \ + "run dfu_start; " \ + "reset; " \ +"fi;" \ +"run nand_boot;" \ +"run nand_boot_backup;" \ +"reset;" + +#else + +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif +#endif /* CONFIG_SPL_BUILD */ +#endif /* ! __CONFIG_DRACO_H */ diff --git a/roms/u-boot/include/configs/dragonboard410c.h b/roms/u-boot/include/configs/dragonboard410c.h new file mode 100644 index 000000000..65537e477 --- /dev/null +++ b/roms/u-boot/include/configs/dragonboard410c.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Board configuration file for Dragonboard 410C + * + * (C) Copyright 2015 Mateusz Kulikowski + */ + +#ifndef __CONFIGS_DRAGONBOARD410C_H +#define __CONFIGS_DRAGONBOARD410C_H + +#include +#include + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 0x80000000 +/* 1008 MB (the last ~30Mb are secured for TrustZone by ATF*/ +#define PHYS_SDRAM_1_SIZE 0x3da00000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* UART */ + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 19000000 + +/* Fixup - in init code we switch from device to host mode, + * it has to be done after each HCD reset */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) + +#include + +/* Does what recovery does */ +#define REFLASH(file, part) \ +"part start mmc 0 "#part" start && "\ +"part size mmc 0 "#part" size && "\ +"tftp $loadaddr "#file" && " \ +"mmc write $loadaddr $start $size && " + +#define CONFIG_ENV_REFLASH \ +"mmc dev 0 && "\ +"usb start && "\ +"dhcp && "\ +"tftp $loadaddr dragonboard/rescue/gpt_both0.bin && "\ +"mmc write $loadaddr 0 43 && " \ +"mmc rescan && "\ +REFLASH(dragonboard/rescue/NON-HLOS.bin, 1)\ +REFLASH(dragonboard/rescue/sbl1.mbn, 2)\ +REFLASH(dragonboard/rescue/rpm.mbn, 3)\ +REFLASH(dragonboard/rescue/tz.mbn, 4)\ +REFLASH(dragonboard/rescue/hyp.mbn, 5)\ +REFLASH(dragonboard/rescue/sec.dat, 6)\ +REFLASH(dragonboard/rescue/emmc_appsboot.mbn, 7)\ +REFLASH(dragonboard/u-boot.img, 8)\ +"usb stop &&"\ +"echo Reflash completed" + +/* Environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "reflash="CONFIG_ENV_REFLASH"\0"\ + "loadaddr=0x81000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "linux_image=Image\0" \ + "kernel_addr_r=0x81000000\0"\ + "fdtfile=qcom/apq8016-sbc.dtb\0" \ + "fdt_addr_r=0x83000000\0"\ + "ramdisk_addr_r=0x84000000\0"\ + "scriptaddr=0x90000000\0"\ + "pxefile_addr_r=0x90100000\0"\ + BOOTENV + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#endif diff --git a/roms/u-boot/include/configs/dragonboard820c.h b/roms/u-boot/include/configs/dragonboard820c.h new file mode 100644 index 000000000..4256e6f06 --- /dev/null +++ b/roms/u-boot/include/configs/dragonboard820c.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Board configuration file for Dragonboard 410C + * + * (C) Copyright 2017 Jorge Ramirez-Ortiz + */ + +#ifndef __CONFIGS_DRAGONBOARD820C_H +#define __CONFIGS_DRAGONBOARD820C_H + +#include +#include + +/* Physical Memory Map */ + +#define PHYS_SDRAM_SIZE 0xC0000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x60000000 +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE 0x5ea4ffff + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 19000000 + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#ifndef CONFIG_SPL_BUILD +#include +#endif + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x95000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "linux_image=uImage\0" \ + "kernel_addr_r=0x95000000\0"\ + "fdtfile=qcom/apq8096-db820c.dtb\0" \ + "fdt_addr_r=0x93000000\0"\ + "ramdisk_addr_r=0x91000000\0"\ + "scriptaddr=0x90000000\0"\ + "pxefile_addr_r=0x90100000\0"\ + BOOTENV + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 64 + +#endif diff --git a/roms/u-boot/include/configs/dreamplug.h b/roms/u-boot/include/configs/dreamplug.h new file mode 100644 index 000000000..9106203eb --- /dev/null +++ b/roms/u-boot/include/configs/dreamplug.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * Jason Cooper + * + * Based on work by: + * Marvell Semiconductor + * Written-by: Siddarth Gore + */ + +#ifndef _CONFIG_DREAMPLUG_H +#define _CONFIG_DREAMPLUG_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ +#define CONFIG_MACH_TYPE MACH_TYPE_DREAMPLUG + +#include "mv-plug-common.h" + +/* + * Environment variables configurations + */ + +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \ + "${x_bootcmd_ethernet}; setenv ethact egiga1; " \ + "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\ + "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ + "bootm 0x6400000;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "x_bootcmd_ethernet=ping 192.168.2.1\0" \ + "x_bootcmd_usb=usb start\0" \ + "x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \ + "x_bootargs=console=ttyS0,115200\0" \ + "x_bootargs_root=root=/dev/sda2 rootdelay=10\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ +#define CONFIG_PHY_BASE_ADR 0 +#endif /* CONFIG_CMD_NET */ + +#endif /* _CONFIG_DREAMPLUG_H */ diff --git a/roms/u-boot/include/configs/ds109.h b/roms/u-boot/include/configs/ds109.h new file mode 100644 index 000000000..f232abe43 --- /dev/null +++ b/roms/u-boot/include/configs/ds109.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * Jason Cooper + * + * Based on work by: + * Marvell Semiconductor + * Written-by: Siddarth Gore + */ + +#ifndef _CONFIG_DS109_H +#define _CONFIG_DS109_H + +/* Provide the MACH_TYPE value that the vendor kernel requires. */ +#define CONFIG_MACH_TYPE 527 + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ + +#include "mv-plug-common.h" + +/* + * Environment variables configurations + */ + +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \ + "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\ + "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ + "bootm 0x6400000;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "x_bootcmd_ethernet=ping 192.168.1.2\0" \ + "x_bootcmd_usb=usb start\0" \ + "x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \ + "x_bootargs=console=ttyS0,115200\0" \ + "x_bootargs_root=root=/dev/sda2 rootdelay=10\0" \ + "ipaddr=192.168.1.5\0" \ + "usb0Mode=host\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable one port */ +#define CONFIG_PHY_BASE_ADR 8 +#endif /* CONFIG_CMD_NET */ + +#endif /* _CONFIG_DS109_H */ diff --git a/roms/u-boot/include/configs/ds414.h b/roms/u-boot/include/configs/ds414.h new file mode 100644 index 000000000..c8b45066c --- /dev/null +++ b/roms/u-boot/include/configs/ds414.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Stefan Roese + */ + +#ifndef _CONFIG_SYNOLOGY_DS414_H +#define _CONFIG_SYNOLOGY_DS414_H + +/* Vendor kernel expects this MACH_TYPE */ +#define CONFIG_MACH_TYPE 3036 + +/* + * High Level Configuration Options (easy to change) + */ + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* USB/EHCI/XHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * Memory layout while starting into the bin_hdr via the + * BootROM: + * + * 0x4000.4000 - 0x4003.4000 headers space (192KiB) + * 0x4000.4030 bin_hdr start address + * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) + * 0x4007.fffc BootROM stack top + * + * The address space between 0x4007.fffc and 0x400f.fff is not locked in + * L2 cache thus cannot be used. + */ + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI) +/* SPL related SPI defines */ +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS +#endif + +/* DS414 bus width is 32bits */ +#define CONFIG_DDR_32BIT + +/* Default Environment */ +#define CONFIG_LOADADDR 0x80000 +#define CONFIG_BOOTCOMMAND \ + "sf probe; " \ + "sf read ${loadaddr} 0xd0000 0x2d0000; " \ + "sf read ${ramdisk_addr_r} 0x3a0000 0x430000; " \ + "bootm ${loadaddr} ${ramdisk_addr_r}" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "initrd_high=0xffffffff\0" \ + "ramdisk_addr_r=0x8000000\0" \ + "usb0Mode=host\0usb1Mode=host\0usb2Mode=device\0" \ + "ethmtu=1500\0eth1mtu=1500\0" \ + "update_uboot=sf probe; dhcp; " \ + "mw.b ${loadaddr} 0x0 0xd0000; " \ + "tftpboot ${loadaddr} u-boot-spl.kwb; " \ + "sf update ${loadaddr} 0x0 0xd0000\0" + + +/* increase autoneg timeout, my NIC sucks */ +#define PHY_ANEG_TIMEOUT 16000 + +#endif /* _CONFIG_SYNOLOGY_DS414_H */ diff --git a/roms/u-boot/include/configs/durian.h b/roms/u-boot/include/configs/durian.h new file mode 100644 index 000000000..fa48e5c02 --- /dev/null +++ b/roms/u-boot/include/configs/durian.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 + * shuyiqi + * liuhao + */ + +#ifndef __DURIAN_CONFIG_H__ +#define __DURIAN_CONFIG_H__ + +/* Sdram Bank #1 Address */ +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x7B000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000000) + +/* Size of Malloc Pool */ +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024 + CONFIG_ENV_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR (0x88000000 - 0x100000) + +/* PCI CONFIG */ +#define CONFIG_SYS_PCI_64BIT 1 +#define CONFIG_PCI_SCAN_SHOW + +/* SCSI */ +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE 128 +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SATA_MAX_DEVICE 4 + +/* BOOT */ +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "load_kernel=ext4load scsi 0:1 0x90100000 uImage-2004\0" \ + "load_fdt=ext4load scsi 0:1 0x95000000 ft2004-pci-64.dtb\0"\ + "boot_fdt=bootm 0x90100000 -:- 0x95000000\0" \ + "distro_bootcmd=run load_kernel; run load_fdt; run boot_fdt" + +#endif diff --git a/roms/u-boot/include/configs/eagle.h b/roms/u-boot/include/configs/eagle.h new file mode 100644 index 000000000..ee5350425 --- /dev/null +++ b/roms/u-boot/include/configs/eagle.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/eagle.h + * This file is Eagle board configuration. + * + * Copyright (C) 2015 Renesas Electronics Corporation + */ + +#ifndef __EAGLE_H +#define __EAGLE_H + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_BITBANGMII_MULTI + +/* Environment compatibility */ + +/* Board Clock */ +/* XTAL_CLK : 33.33MHz */ +#define CONFIG_SYS_CLK_FREQ 33333333u + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +#endif /* __EAGLE_H */ diff --git a/roms/u-boot/include/configs/eb_cpu5282.h b/roms/u-boot/include/configs/eb_cpu5282.h new file mode 100644 index 000000000..ab9daa407 --- /dev/null +++ b/roms/u-boot/include/configs/eb_cpu5282.h @@ -0,0 +1,236 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123) + * + * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG + */ + +#ifndef _CONFIG_EB_CPU5282_H_ +#define _CONFIG_EB_CPU5282_H_ + +#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP + +/*----------------------------------------------------------------------* + * High Level Configuration Options (easy to change) * + *----------------------------------------------------------------------*/ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) + +#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ + +#define CONFIG_BOOTCOMMAND "printenv" + +/*----------------------------------------------------------------------* + * Options * + *----------------------------------------------------------------------*/ + +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_RESET_TO_RETRY + +#define CONFIG_HW_WATCHDOG + +#define STATUS_LED_ACTIVE 0 + +/*----------------------------------------------------------------------* + * Configuration for environment * + * Environment is in the second sector of the first 256k of flash * + *----------------------------------------------------------------------*/ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#define CONFIG_MCFTMR + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR 0x20000 + +/*#define CONFIG_SYS_DRAM_TEST 1 */ +#undef CONFIG_SYS_DRAM_TEST + +/*----------------------------------------------------------------------* + * Clock and PLL Configuration * + *----------------------------------------------------------------------*/ +#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */ + +/* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */ + +#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ +#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ + +/*----------------------------------------------------------------------* + * Network * + *----------------------------------------------------------------------*/ + +#ifdef CONFIG_MCFFEC +#define CONFIG_MII_INIT 1 +#define CONFIG_SYS_DISCOVER_PHY +#define CONFIG_SYS_RX_ETH_BUFFER 8 +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif + +/*------------------------------------------------------------------------- + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + *-----------------------------------------------------------------------*/ + +#define CONFIG_SYS_MBAR 0x40000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + *-----------------------------------------------------------------------*/ + +#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE0 0x00000000 +#define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ + +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0 +#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 + +#define CONFIG_SYS_MONITOR_LEN 0x20000 +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CONFIG_FLASH_SHOW_PROGRESS 45 + +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 +#define CONFIG_SYS_INT_FLASH_ENABLE 0x21 + +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_ERASE_TOUT 10000000 + +#define CONFIG_SYS_FLASH_SIZE 16*1024*1024 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ + CF_CACR_CEIB | CF_CACR_DBWE | \ + CF_CACR_EUSP) + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ + +#define CONFIG_SYS_CS0_BASE 0xFF000000 +#define CONFIG_SYS_CS0_CTRL 0x00001980 +#define CONFIG_SYS_CS0_MASK 0x00FF0001 + +#define CONFIG_SYS_CS2_BASE 0xE0000000 +#define CONFIG_SYS_CS2_CTRL 0x00001980 +#define CONFIG_SYS_CS2_MASK 0x000F0001 + +#define CONFIG_SYS_CS3_BASE 0xE0100000 +#define CONFIG_SYS_CS3_CTRL 0x00001980 +#define CONFIG_SYS_CS3_MASK 0x000F0001 + +/*----------------------------------------------------------------------- + * Port configuration + */ +#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ +#define CONFIG_SYS_PADDR 0x0000000 +#define CONFIG_SYS_PADAT 0x0000000 + +#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ +#define CONFIG_SYS_PBDDR 0x0000000 +#define CONFIG_SYS_PBDAT 0x0000000 + +#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ +#define CONFIG_SYS_PCDDR 0x0000000 +#define CONFIG_SYS_PCDAT 0x0000000 + +#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ +#define CONFIG_SYS_PCDDR 0x0000000 +#define CONFIG_SYS_PCDAT 0x0000000 + +#define CONFIG_SYS_PASPAR 0x0F0F +#define CONFIG_SYS_PEHLPAR 0xC0 +#define CONFIG_SYS_PUAPAR 0x0F +#define CONFIG_SYS_DDRUA 0x05 +#define CONFIG_SYS_PJPAR 0xFF + +/*----------------------------------------------------------------------- + * I2C + */ + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL + +#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +#define CONFIG_SYS_FSL_I2C_SPEED 100000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0 + +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_DS1338 +#define CONFIG_I2C_RTC_ADDR 0x68 +#endif + +/*----------------------------------------------------------------------- + * VIDEO configuration + */ + +#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2 +#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1 +#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE + +#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT +#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR +#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001 + +#define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT +#define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR +#define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002 + +#define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT +#define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR +#define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004 + +#define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE +#define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE +#define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2 + +#endif /* _CONFIG_M5282EVB_H */ +/*---------------------------------------------------------------------*/ diff --git a/roms/u-boot/include/configs/ebisu.h b/roms/u-boot/include/configs/ebisu.h new file mode 100644 index 000000000..19ec74fb5 --- /dev/null +++ b/roms/u-boot/include/configs/ebisu.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/ebisu.h + * This file is Ebisu board configuration. + * + * Copyright (C) 2018 Renesas Electronics Corporation + */ + +#ifndef __EBISU_H +#define __EBISU_H + +#undef DEBUG + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_NET_MULTI +#define CONFIG_BITBANGMII_MULTI + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +/* Environment in eMMC, at the end of 2nd "boot sector" */ + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +#endif /* __EBISU_H */ diff --git a/roms/u-boot/include/configs/edb93xx.h b/roms/u-boot/include/configs/edb93xx.h new file mode 100644 index 000000000..2f302b921 --- /dev/null +++ b/roms/u-boot/include/configs/edb93xx.h @@ -0,0 +1,184 @@ +/* + * U-Boot - Configuration file for Cirrus Logic EDB93xx boards + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_MK_edb9301 +#define CONFIG_EDB9301 +#elif defined(CONFIG_MK_edb9302) +#define CONFIG_EDB9302 +#elif defined(CONFIG_MK_edb9302a) +#define CONFIG_EDB9302A +#elif defined(CONFIG_MK_edb9307) +#define CONFIG_EDB9307 +#elif defined(CONFIG_MK_edb9307a) +#define CONFIG_EDB9307A +#elif defined(CONFIG_MK_edb9312) +#define CONFIG_EDB9312 +#elif defined(CONFIG_MK_edb9315) +#define CONFIG_EDB9315 +#elif defined(CONFIG_MK_edb9315a) +#define CONFIG_EDB9315A +#else +#error "no board defined" +#endif + +/* Initial environment and monitor configuration options. */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_BOOTFILE "edb93xx.img" + +#ifdef CONFIG_EDB9301 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301 +#elif defined(CONFIG_EDB9302) +#define CONFIG_EP9302 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302 +#elif defined(CONFIG_EDB9302A) +#define CONFIG_EP9302 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A +#elif defined(CONFIG_EDB9307) +#define CONFIG_EP9307 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307 +#elif defined(CONFIG_EDB9307A) +#define CONFIG_EP9307 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A +#elif defined(CONFIG_EDB9312) +#define CONFIG_EP9312 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312 +#elif defined(CONFIG_EDB9315) +#define CONFIG_EP9315 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315 +#elif defined(CONFIG_EDB9315A) +#define CONFIG_EP9315 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A +#else +#error "no board defined" +#endif + +/* High-level configuration options */ +#define CONFIG_EP93XX 1 /* This is a Cirrus Logic 93xx SoC */ + +#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */ + +/* Monitor configuration */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ + +/* Serial port hardware configuration */ +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \ + 115200, 230400} +#define CONFIG_SYS_SERIAL0 0x808C0000 +#define CONFIG_SYS_SERIAL1 0x808D0000 +/*#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} */ + +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} + +/* Status LED */ +/* Optional value */ + +/* Network hardware configuration */ +#define CONFIG_DRIVER_EP93XX_MAC +#define CONFIG_MII_SUPPRESS_PREAMBLE + +/* SDRAM configuration */ +#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ + defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \ + defined(CONFIG_EDB9315) +/* + * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 + * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set + * the SROMLL bit on the processor, resulting in this non-contiguous memory map. + * + * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of + * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of + * 64 MB of SDRAM. + */ + +#define CONFIG_EDB93XX_SDCS3 + +#elif defined(CONFIG_EDB9302A) || \ + defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A) +/* + * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 + * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set + * the SROMLL bit on the processor, resulting in this non-contiguous memory map. + * + * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung + * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM. + */ +#define CONFIG_EDB93XX_SDCS0 + +#else +#error "no SDCS configuration for this board" +#endif + +#if defined(CONFIG_EDB93XX_SDCS3) +#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */ +#define PHYS_SDRAM_1 0x00000000 +#elif defined(CONFIG_EDB93XX_SDCS0) +#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */ +#define PHYS_SDRAM_1 0xc0000000 +#endif + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE) + +/* Must match kernel config */ +#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) + +/* Run-time memory allocatons */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) + +/* ----------------------------------------------------------------------------- + * FLASH and environment organization + * + * The EDB9301, EDB9302(a), EDB9307a, EDB9315a have 1 bank of flash memory at + * 0x60000000 consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit + * data bus, for a total of 16 MB of CFI-compatible flash. + * + * The EDB9307, EDB9312, and EDB9315 have 1 bank of flash memory at + * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit + * data bus, for a total of 32 MB of CFI-compatible flash. + * + * + * EDB9301/02(a)7a/15a EDB9307/12/15 + * 0x60000000 - 0x0003FFFF u-boot u-boot + * 0x60040000 - 0x0005FFFF environment #1 environment #1 + * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued) + * 0x60080000 - 0x0009FFFF unused environment #2 + * 0x600A0000 - 0x000BFFFF unused environment #2 (continued) + * 0x600C0000 - 0x00FFFFFF unused unused + * 0x61000000 - 0x01FFFFFF not present unused + */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT (256+8) + +#define PHYS_FLASH_1 CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) + +#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_OHCI_EP93XX +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ep93xx-ohci" +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80020000 + +/* Define to disable flash configuration*/ +/* #define CONFIG_EP93XX_NO_FLASH_CFG */ + +/* Define this for indusrial rated chips */ +/* #define CONFIG_EDB93XX_INDUSTRIAL */ + +#endif /* !defined (__CONFIG_H) */ diff --git a/roms/u-boot/include/configs/edison.h b/roms/u-boot/include/configs/edison.h new file mode 100644 index 000000000..0e1205bdb --- /dev/null +++ b/roms/u-boot/include/configs/edison.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2017 Intel Corp. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 128 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Memory */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 +#define CONFIG_PHYSMEM + +#define CONFIG_SYS_STACK_SIZE (32 * 1024) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) + +/* RTC */ +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 + +#endif diff --git a/roms/u-boot/include/configs/edminiv2.h b/roms/u-boot/include/configs/edminiv2.h new file mode 100644 index 000000000..949ff5562 --- /dev/null +++ b/roms/u-boot/include/configs/edminiv2.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2010 Albert ARIBAUD + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + */ + +#ifndef _CONFIG_EDMINIV2_H +#define _CONFIG_EDMINIV2_H + +/* + * SPL + */ + +#define CONFIG_SPL_MAX_SIZE 0x0000fff0 +#define CONFIG_SPL_STACK 0x00020000 +#define CONFIG_SPL_BSS_START_ADDR 0x00020000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff +#define CONFIG_SYS_SPL_MALLOC_START 0x00040000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff +#define CONFIG_SYS_UBOOT_BASE 0xfff90000 +#define CONFIG_SYS_UBOOT_START 0x00800000 + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_FEROCEON 1 /* CPU Core subversion */ +#define CONFIG_88F5182 1 /* SOC Name */ + +#include +/* + * CLKs configurations + */ + +/* + * Board-specific values for Orion5x MPP low level init: + * - MPPs 12 to 15 are SATA LEDs (mode 5) + * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for + * MPP16 to MPP19, mode 0 for others + */ + +#define ORION5X_MPP0_7 0x00000003 +#define ORION5X_MPP8_15 0x55550000 +#define ORION5X_MPP16_23 0x00005555 + +/* + * Board-specific values for Orion5x GPIO low level init: + * - GPIO3 is input (RTC interrupt) + * - GPIO16 is Power LED control (0 = on, 1 = off) + * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) + * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) + * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) + * - GPIO22 is SATA disk power status () + * - GPIO23 is supply status for SATA disk () + * - GPIO24 is supply control for board (write 1 to power off) + * Last GPIO is 25, further bits are supposed to be 0. + * Enable mask has ones for INPUT, 0 for OUTPUT. + * Default is LED ON, board ON :) + */ + +#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca +#define ORION5X_GPIO_OUT_VALUE 0x00000000 +#define ORION5X_GPIO_IN_POLARITY 0x000000d0 + +/* + * NS16550 Configuration + */ + +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_SYS_BAUDRATE_TABLE \ + { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } + +/* + * FLASH configuration + */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BASE 0xfff80000 + +/* auto boot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ + +/* + * Network + */ + +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ +#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ +#define CONFIG_PHY_BASE_ADR 0x8 +#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ +#endif + +/* + * IDE + */ +#ifdef CONFIG_IDE +#define __io +/* Needs byte-swapping for ATA data register */ +#define CONFIG_IDE_SWAP_IO +/* Data, registers and alternate blocks are at the same offset */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) +#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) +#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) +/* Each 8-bit ATA register is aligned to a 4-bytes address */ +#define CONFIG_SYS_ATA_STRIDE 4 +/* Controller supports 48-bits LBA addressing */ +#define CONFIG_LBA48 +/* A single bus, a single device */ +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 +/* ATA registers base is at SATA controller base */ +#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE +/* ATA bus 0 is orion5x port 1 on ED Mini V2 */ +#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET +/* end of IDE defines */ +#endif /* CMD_IDE */ + +/* + * Common USB/EHCI configuration + */ +#ifdef CONFIG_CMD_USB +#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE +#endif /* CONFIG_CMD_USB */ + +/* + * I2C related stuff + */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* + * Environment variables configurations + */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ + +/* + * Other required minimal configurations + */ + +#define CONFIG_SYS_LOAD_ADDR 0x00800000 +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 + +/* Enable command line editing */ + +/* provide extensive help */ + +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#endif /* _CONFIG_EDMINIV2_H */ diff --git a/roms/u-boot/include/configs/efi-x86_app.h b/roms/u-boot/include/configs/efi-x86_app.h new file mode 100644 index 000000000..33418cfbe --- /dev/null +++ b/roms/u-boot/include/configs/efi-x86_app.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Google, Inc + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#undef CONFIG_TPM_TIS_BASE_ADDRESS + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ + "stdout=vga,serial\0" \ + "stderr=vga,serial\0" + +#endif diff --git a/roms/u-boot/include/configs/efi-x86_payload.h b/roms/u-boot/include/configs/efi-x86_payload.h new file mode 100644 index 000000000..1cf5c037e --- /dev/null +++ b/roms/u-boot/include/configs/efi-x86_payload.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, Bin Meng + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +/* ATA/IDE support */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 4 +#define CONFIG_SYS_ATA_BASE_ADDR 0 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 +#define CONFIG_SYS_ATA_ALT_OFFSET 0 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 +#define CONFIG_ATAPI + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/el6x_common.h b/roms/u-boot/include/configs/el6x_common.h new file mode 100644 index 000000000..9ee7fee2d --- /dev/null +++ b/roms/u-boot/include/configs/el6x_common.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) Stefano Babic + * + * Configuration settings for the E+L i.MX6Q DO82 board. + */ + +#ifndef __EL6Q_COMMON_CONFIG_H +#define __EL6Q_COMMON_CONFIG_H + +#include + +#define CONFIG_BOARD_NAME EL6Q + +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +#ifdef CONFIG_SPL +#include "imx6_spl.h" +#endif + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* I2C config */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +/* Commands */ + +#define CONFIG_MXC_UART_BASE UART2_BASE + +#define CONFIG_BOARD_NAME EL6Q + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "board="__stringify(CONFIG_BOARD_NAME)"\0" \ + "cma_size="__stringify(EL6Q_CMA_SIZE)"\0" \ + "chp_size="__stringify(EL6Q_COHERENT_POOL_SIZE)"\0" \ + "console=" CONSOLE_DEV "\0" \ + "fdtfile=undefined\0" \ + "fdt_high=0xffffffff\0" \ + "fdt_addr_r=0x18000000\0" \ + "fdt_addr=0x18000000\0" \ + "findfdt=setenv fdtfile " CONFIG_DEFAULT_FDT_FILE "\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(PXE, PXE, na) \ + func(DHCP, dhcp, na) + +#include + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* environment organization */ + +#endif /* __EL6Q_COMMON_CONFIG_H */ diff --git a/roms/u-boot/include/configs/elgin_rv1108.h b/roms/u-boot/include/configs/elgin_rv1108.h new file mode 100644 index 000000000..df04892e5 --- /dev/null +++ b/roms/u-boot/include/configs/elgin_rv1108.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#endif diff --git a/roms/u-boot/include/configs/embestmx6boards.h b/roms/u-boot/include/configs/embestmx6boards.h new file mode 100644 index 000000000..a29eec00a --- /dev/null +++ b/roms/u-boot/include/configs/embestmx6boards.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Eukréa Electromatique + * Author: Eric Bénard + * + * Configuration settings for the Embest RIoTboard + * + * based on mx6*sabre*.h which are : + * Copyright (C) 2012 Freescale Semiconductor, Inc. + */ + +#ifndef __RIOTBOARD_CONFIG_H +#define __RIOTBOARD_CONFIG_H + +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONSOLE_DEV "ttymxc1" + +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ + +#if defined(CONFIG_ENV_IS_IN_MMC) +/* RiOTboard */ +#define CONFIG_FDTFILE "imx6dl-riotboard.dtb" +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +/* MarSBoard */ +#define CONFIG_FDTFILE "imx6q-marsboard.dtb" +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +/* Framebuffer */ +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +#include "mx6_common.h" + +#ifdef CONFIG_SPL +#include "imx6_spl.h" +/* RiOTboard */ +#define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000 +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6dl-riotboard.dtb" + +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* offset 69KB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* offset 69KB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* offset 69KB */ + +#endif + +/* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, + * 1M script, 1M pxe and the ramdisk at the end */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x12000000\0" \ + "fdt_addr_r=0x13000000\0" \ + "scriptaddr=0x13100000\0" \ + "pxefile_addr_r=0x13200000\0" \ + "ramdisk_addr_r=0x13300000\0" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#define CONSOLE_STDIN_SETTINGS \ + "stdin=serial\0" + +#define CONSOLE_STDOUT_SETTINGS \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define CONSOLE_ENV_SETTINGS \ + CONSOLE_STDIN_SETTINGS \ + CONSOLE_STDOUT_SETTINGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONSOLE_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + "fdtfile=" CONFIG_FDTFILE "\0" \ + "finduuid=part uuid mmc 0:1 uuid\0" \ + BOOTENV + +#endif /* __RIOTBOARD_CONFIG_H */ diff --git a/roms/u-boot/include/configs/emsdp.h b/roms/u-boot/include/configs/emsdp.h new file mode 100644 index 000000000..a872d4815 --- /dev/null +++ b/roms/u-boot/include/configs/emsdp.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Synopsys, Inc. All rights reserved. + */ + +#ifndef _CONFIG_EMSDP_H_ +#define _CONFIG_EMSDP_H_ + +#include + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_SDRAM_BASE 0x10000000 +#define CONFIG_SYS_SDRAM_SIZE SZ_16M + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_1M) + +#define CONFIG_SYS_MALLOC_LEN SZ_64K +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + +/* + * Environment + */ +#define CONFIG_BOOTFILE "app.bin" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "upgrade_image=u-boot.bin\0" \ + "upgrade=emsdp rom unlock && " \ + "fatload mmc 0 ${loadaddr} ${upgrade_image} && " \ + "cp.b ${loadaddr} 0 ${filesize} && " \ + "dcache flush && " \ + "emsdp rom lock\0" + +#endif /* _CONFIG_EMSDP_H_ */ + diff --git a/roms/u-boot/include/configs/espresso7420.h b/roms/u-boot/include/configs/espresso7420.h new file mode 100644 index 000000000..2495db93f --- /dev/null +++ b/roms/u-boot/include/configs/espresso7420.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the SAMSUNG ESPRESSO7420 board. + * Copyright (C) 2016 Samsung Electronics + * Thomas Abraham + */ + +#ifndef __CONFIG_ESPRESSO7420_H +#define __CONFIG_ESPRESSO7420_H + +#include + +#define CONFIG_BOARD_COMMON + +#define CONFIG_ESPRESSO7420 + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SPL_STACK CONFIG_IRAM_END +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_END + +/* DRAM Memory Banks */ +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ + +#endif /* __CONFIG_ESPRESSO7420_H */ diff --git a/roms/u-boot/include/configs/etamin.h b/roms/u-boot/include/configs/etamin.h new file mode 100644 index 000000000..880149fb8 --- /dev/null +++ b/roms/u-boot/include/configs/etamin.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef __CONFIG_ETAMIN_H +#define __CONFIG_ETAMIN_H + +#include "siemens-am33x-common.h" +/* NAND specific changes for etamin due to different page size */ +#undef CONFIG_SYS_NAND_PAGE_SIZE +#undef CONFIG_SYS_NAND_OOBSIZE +#undef CONFIG_SYS_NAND_BLOCK_SIZE +#undef CONFIG_SYS_NAND_ECCPOS +#undef CONFIG_SYS_NAND_U_BOOT_OFFS +#undef CONFIG_SYS_ENV_SECT_SIZE +#undef CONFIG_NAND_OMAP_ECCSCHEME +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW + +#define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */ +#define CONFIG_SYS_NAND_PAGE_SIZE 4096 +#define CONFIG_SYS_NAND_OOBSIZE 224 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ + 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ + 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \ + 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ + 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \ + 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \ + 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ + 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \ + 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \ + 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \ + 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \ + 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \ + 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \ + 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \ + 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \ + 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \ + 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ + } + +#undef CONFIG_SYS_NAND_ECCSIZE +#undef CONFIG_SYS_NAND_ECCBYTES +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 26 + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 + +#define CONFIG_SYS_NAND_MAX_CHIPS 1 + +#undef CONFIG_SYS_MAX_NAND_DEVICE +#define CONFIG_SYS_MAX_NAND_DEVICE 3 +#define CONFIG_SYS_NAND_BASE2 (0x18000000) /* physical address */ +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ + CONFIG_SYS_NAND_BASE2} + +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define DDR_PLL_FREQ 303 + +/* FWD Button = 27 + * SRV Button = 87 */ +#define BOARD_DFU_BUTTON_GPIO 27 +#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ +/* In dfu mode keep led1 on */ +#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + "button_dfu0=27\0" \ + "button_dfu1=87\0" \ + "led0=3,0,1\0" \ + "led1=4,0,0\0" \ + "led2=5,0,1\0" \ + "led3=87,0,1\0" \ + "led4=60,0,1\0" \ + "led5=63,0,1\0" + +/* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define EEPROM_ADDR_DDR3 0x90 +#define EEPROM_ADDR_CHIP 0x120 + +#define CONFIG_FACTORYSET + +/* use both define to compile a SPL compliance test */ +/* +#define CONFIG_SPL_CMT +#define CONFIG_SPL_CMT_DEBUG +*/ + +/* nedded by compliance test in read mode */ +#if defined(CONFIG_SPL_CMT) +#define CONFIG_SYS_DCACHE_OFF +#endif + +/* Define own nand partitions */ +#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) + + + +#undef COMMON_ENV_DFU_ARGS +#define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \ + "setenv bootargs ${bootargs};" \ + "mtdparts default;" \ + "draco_led 1;" \ + "dfu 0 mtd 0;" \ + "draco_led 0;\0" \ + +#undef DFU_ALT_INFO_NAND_V2 +#define DFU_ALT_INFO_NAND_V2 \ + "spl mtddev;" \ + "spl.backup1 mtddev;" \ + "spl.backup2 mtddev;" \ + "spl.backup3 mtddev;" \ + "u-boot mtddev;" \ + "u-boot.env0 mtddev;" \ + "u-boot.env1 mtddev;" \ + "rootfs mtddevubi" \ + +#undef CONFIG_ENV_SETTINGS_NAND_V2 +#define CONFIG_ENV_SETTINGS_NAND_V2 \ + "nand_active_ubi_vol=rootfs_a\0" \ + "rootfs_name=rootfs\0" \ + "kernel_name=uImage\0"\ + "nand_root_fs_type=ubifs rootwait=1\0" \ + "nand_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv ${partitionset_active} true;" \ + "if test -n ${A}; then " \ + "setenv nand_active_ubi_vol ${rootfs_name}_a;" \ + "fi;" \ + "if test -n ${B}; then " \ + "setenv nand_active_ubi_vol ${rootfs_name}_b;" \ + "fi;" \ + "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ + "ubi.mtd=rootfs,${ubi_off};" \ + "setenv bootargs ${bootargs} " \ + "root=${nand_root} noinitrd ${mtdparts} " \ + "rootfstype=${nand_root_fs_type} ip=${ip_method} " \ + "console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \ + "=mtdoops\0" \ + COMMON_ENV_DFU_ARGS \ + "dfu_alt_info=" DFU_ALT_INFO_NAND_V2 "\0" \ + COMMON_ENV_NAND_BOOT \ + "ubi part rootfs ${ubi_off};" \ + "ubifsmount ubi0:${nand_active_ubi_vol};" \ + "ubifsload ${kloadaddr} boot/${kernel_name};" \ + "ubifsload ${loadaddr} boot/${dtb_name}.dtb;" \ + "bootm ${kloadaddr} - ${loadaddr}\0" \ + "nand_boot_backup=ubifsload ${loadaddr} boot/am335x-draco.dtb;" \ + "bootm ${kloadaddr} - ${loadaddr}\0" \ + COMMON_ENV_NAND_CMDS + +#ifndef CONFIG_SPL_BUILD + +#define CONFIG_NAND_CS_INIT +#define ETAMIN_NAND_GPMC_CONFIG1 0x00000800 +#define ETAMIN_NAND_GPMC_CONFIG2 0x001e1e00 +#define ETAMIN_NAND_GPMC_CONFIG3 0x001e1e00 +#define ETAMIN_NAND_GPMC_CONFIG4 0x16051807 +#define ETAMIN_NAND_GPMC_CONFIG5 0x00151e1e +#define ETAMIN_NAND_GPMC_CONFIG6 0x16000f80 +#define CONFIG_MTD_CONCAT + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=etamin\0" \ + "ubi_off=4096\0"\ + "nand_img_size=0x400000\0" \ + "optargs=\0" \ + "preboot=draco_led 0\0" \ + CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + CONFIG_ENV_SETTINGS_V2 \ + CONFIG_ENV_SETTINGS_NAND_V2 + +#ifndef CONFIG_RESTORE_FLASH + +#define CONFIG_BOOTCOMMAND \ +"if dfubutton; then " \ + "run dfu_start; " \ + "reset; " \ +"fi;" \ +"run nand_boot;" \ +"run nand_boot_backup;" \ +"reset;" + + +#else +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif +#endif /* CONFIG_SPL_BUILD */ +#endif /* ! __CONFIG_ETAMIN_H */ diff --git a/roms/u-boot/include/configs/ethernut5.h b/roms/u-boot/include/configs/ethernut5.h new file mode 100644 index 000000000..ca249d9d2 --- /dev/null +++ b/roms/u-boot/include/configs/ethernut5.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * egnite GmbH + * + * Configuation settings for Ethernut 5 with AT91SAM9XE. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* The first stage boot loader expects u-boot running at this address. */ + +/* The first stage boot loader takes care of low level initialization. */ +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* Set our official architecture number. */ +#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 + +/* CPU information */ + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ + +/* 32kB internal SRAM */ +#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */ +#define CONFIG_SRAM_SIZE (32 << 10) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* 128MB SDRAM in 1 bank */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE (128 << 20) +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) + +/* 512kB on-chip NOR flash */ +# define CONFIG_SYS_MAX_FLASH_BANKS 1 +# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ +# define CONFIG_AT91_EFLASH +# define CONFIG_SYS_MAX_FLASH_SECT 32 +# define CONFIG_EFLASH_PROTSECTORS 1 + + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) +#endif + +/* JFFS2 */ +#ifdef CONFIG_CMD_JFFS2 +#define CONFIG_JFFS2_NAND +#endif + +/* Ethernet */ +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_PHY_ID 0 +#define CONFIG_MACB_SEARCH_PHY + +/* MMC */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#endif + +/* RTC */ +#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#endif + +/* I2C */ +#define CONFIG_SYS_MAX_I2C_BUS 1 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SOFT_SPEED 100000 +#define CONFIG_SYS_I2C_SOFT_SLAVE 0 + +#define I2C_SOFT_DECLARATIONS + +#define GPIO_I2C_SCL AT91_PIO_PORTA, 24 +#define GPIO_I2C_SDA AT91_PIO_PORTA, 23 + +#define I2C_INIT { \ + at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \ + at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ + at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \ + at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \ + at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ +} + +#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0) +#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0) +#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) +#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit) +#define I2C_DELAY udelay(100) +#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) + +/* DHCP/BOOTP options */ +#ifdef CONFIG_CMD_DHCP +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_SYS_AUTOLOAD "n" +#endif + +/* File systems */ + +/* Boot command */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_BOOTCOMMAND "sf probe 0:0; " \ + "sf read 0x22000000 0xc6000 0x294000; " \ + "bootm 0x22000000" + +/* Misc. u-boot settings */ + +#endif diff --git a/roms/u-boot/include/configs/evb_ast2500.h b/roms/u-boot/include/configs/evb_ast2500.h new file mode 100644 index 000000000..0ff01af83 --- /dev/null +++ b/roms/u-boot/include/configs/evb_ast2500.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * Ryan Chen + * + * Copyright 2016 Google Inc + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE + +/* Memory Info */ +#define CONFIG_SYS_LOAD_ADDR 0x83000000 + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/evb_ast2600.h b/roms/u-boot/include/configs/evb_ast2600.h new file mode 100644 index 000000000..e7975bf66 --- /dev/null +++ b/roms/u-boot/include/configs/evb_ast2600.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE + +/* Memory Info */ +#define CONFIG_SYS_LOAD_ADDR 0x83000000 + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/evb_px30.h b/roms/u-boot/include/configs/evb_px30.h new file mode 100644 index 000000000..27201fcfd --- /dev/null +++ b/roms/u-boot/include/configs/evb_px30.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +#ifndef __EVB_PX30_H +#define __EVB_PX30_H + +#include + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#define CONFIG_SUPPORT_EMMC_RPMB + +#endif diff --git a/roms/u-boot/include/configs/evb_px5.h b/roms/u-boot/include/configs/evb_px5.h new file mode 100644 index 000000000..13ddc18b3 --- /dev/null +++ b/roms/u-boot/include/configs/evb_px5.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIGS_PX5_EVB_H +#define __CONFIGS_PX5_EVB_H + +#include + +#endif diff --git a/roms/u-boot/include/configs/evb_rk3036.h b/roms/u-boot/include/configs/evb_rk3036.h new file mode 100644 index 000000000..b03612cfc --- /dev/null +++ b/roms/u-boot/include/configs/evb_rk3036.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#endif diff --git a/roms/u-boot/include/configs/evb_rk3128.h b/roms/u-boot/include/configs/evb_rk3128.h new file mode 100644 index 000000000..768004a43 --- /dev/null +++ b/roms/u-boot/include/configs/evb_rk3128.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +#ifndef __EVB_RK3128_H +#define __EVB_RK3128_H + +#include + +#endif diff --git a/roms/u-boot/include/configs/evb_rk3229.h b/roms/u-boot/include/configs/evb_rk3229.h new file mode 100644 index 000000000..77d99d0a4 --- /dev/null +++ b/roms/u-boot/include/configs/evb_rk3229.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#endif diff --git a/roms/u-boot/include/configs/evb_rk3288.h b/roms/u-boot/include/configs/evb_rk3288.h new file mode 100644 index 000000000..053c9032e --- /dev/null +++ b/roms/u-boot/include/configs/evb_rk3288.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#endif diff --git a/roms/u-boot/include/configs/evb_rk3308.h b/roms/u-boot/include/configs/evb_rk3308.h new file mode 100644 index 000000000..e8893eb7d --- /dev/null +++ b/roms/u-boot/include/configs/evb_rk3308.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd + */ + +#ifndef __EVB_RK3308_H +#define __EVB_RK3308_H + +#include + +#define CONFIG_SUPPORT_EMMC_RPMB + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif diff --git a/roms/u-boot/include/configs/evb_rk3328.h b/roms/u-boot/include/configs/evb_rk3328.h new file mode 100644 index 000000000..cac613d02 --- /dev/null +++ b/roms/u-boot/include/configs/evb_rk3328.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __EVB_RK3328_H +#define __EVB_RK3328_H + +#include + +#define SDRAM_BANK_SIZE (2UL << 30) + +#endif diff --git a/roms/u-boot/include/configs/evb_rk3399.h b/roms/u-boot/include/configs/evb_rk3399.h new file mode 100644 index 000000000..b7e850370 --- /dev/null +++ b/roms/u-boot/include/configs/evb_rk3399.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __EVB_RK3399_H +#define __EVB_RK3399_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#define SDRAM_BANK_SIZE (2UL << 30) + +#endif diff --git a/roms/u-boot/include/configs/evb_rv1108.h b/roms/u-boot/include/configs/evb_rv1108.h new file mode 100644 index 000000000..b742d9870 --- /dev/null +++ b/roms/u-boot/include/configs/evb_rv1108.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * Default environment settings + */ +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ipaddr=172.16.12.50\0" \ + "serverip=172.16.12.69\0" \ + "" + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND \ + "sf probe;" \ + "sf read 0x62000000 0x140800 0x500000;" \ + "dcache off;" \ + "go 0x62000000" + +#endif diff --git a/roms/u-boot/include/configs/exynos-common.h b/roms/u-boot/include/configs/exynos-common.h new file mode 100644 index 000000000..8adaf297f --- /dev/null +++ b/roms/u-boot/include/configs/exynos-common.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Common configuration settings for the SAMSUNG EXYNOS boards. + */ + +#ifndef __EXYNOS_COMMON_H +#define __EXYNOS_COMMON_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ + +#include /* get chip and board defs */ +#include +#include + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* Keep L2 Cache Disabled */ + +/* input clock of PLL: 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 +#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG + +/* Size of malloc() pool before and after relocation */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) + +/* select serial console configuration */ + +/* PWM */ +#define CONFIG_PWM + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/exynos4-common.h b/roms/u-boot/include/configs/exynos4-common.h new file mode 100644 index 000000000..005f65d4e --- /dev/null +++ b/roms/u-boot/include/configs/exynos4-common.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5 board. + */ + +#ifndef __CONFIG_EXYNOS4_COMMON_H +#define __CONFIG_EXYNOS4_COMMON_H + +#define CONFIG_EXYNOS4 /* Exynos4 Family */ + +#include "exynos-common.h" + +#define CONFIG_BOARD_COMMON + +#define CONFIG_REVISION_TAG + +/* SD/MMC configuration */ +#define CONFIG_MMC_DEFAULT_DEV 0 + +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* USB Samsung's IDs */ +#define CONFIG_G_DNL_THOR_VENDOR_NUM 0x04E8 +#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D +#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_USB_GADGET_DWC2_OTG_PHY + +/* Common environment variables */ +#define CONFIG_EXTRA_ENV_ITB \ + "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ + "${kernelname}\0" \ + "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \ + "${initrdname}\0" \ + "loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \ + "${fdtfile}\0" \ + "check_ramdisk=" \ + "if run loadinitrd; then " \ + "setenv initrd_addr ${initrdaddr};" \ + "else " \ + "setenv initrd_addr -;" \ + "fi;\0" \ + "check_dtb=" \ + "if run loaddtb; then " \ + "setenv fdt_addr ${fdtaddr};" \ + "else " \ + "setenv fdt_addr;" \ + "fi;\0" \ + "kernel_args=" \ + "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart}" \ + " ${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};\0" \ + "boot_fit=" \ + "setenv kerneladdr 0x42000000;" \ + "setenv kernelname Image.itb;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootm ${kerneladdr}#${board_name}\0" \ + "boot_uimg=" \ + "setenv kerneladdr 0x40007FC0;" \ + "setenv kernelname uImage;" \ + "run check_dtb;" \ + "run check_ramdisk;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ + "boot_zimg=" \ + "setenv kerneladdr 0x40007FC0;" \ + "setenv kernelname zImage;" \ + "run check_dtb;" \ + "run check_ramdisk;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ + "autoboot=" \ + "if test -e mmc ${mmcdev}:${mmcbootpart} Image.itb; then; " \ + "run boot_fit;" \ + "elif test -e mmc ${mmcdev}:${mmcbootpart} zImage; then; " \ + "run boot_zimg;" \ + "elif test -e mmc ${mmcdev}:${mmcbootpart} uImage; then; " \ + "run boot_uimg;" \ + "fi;\0" + +#endif /* __CONFIG_EXYNOS4_COMMON_H */ diff --git a/roms/u-boot/include/configs/exynos5-common.h b/roms/u-boot/include/configs/exynos5-common.h new file mode 100644 index 000000000..9297fbdc0 --- /dev/null +++ b/roms/u-boot/include/configs/exynos5-common.h @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5 board. + */ + +#ifndef __CONFIG_EXYNOS5_COMMON_H +#define __CONFIG_EXYNOS5_COMMON_H + +#define CONFIG_EXYNOS5 /* Exynos5 Family */ + +#include "exynos-common.h" + +#define CONFIG_EXYNOS_SPL + +#ifdef FTRACE +#define CONFIG_TRACE +#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) +#define CONFIG_TRACE_EARLY_SIZE (8 << 20) +#define CONFIG_TRACE_EARLY +#define CONFIG_TRACE_EARLY_ADDR 0x50000000 +#endif + +/* Enable ACE acceleration for SHA1 and SHA256 */ +#define CONFIG_EXYNOS_ACE_SHA + +/* Power Down Modes */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +/* Offset for inform registers */ +#define INFORM0_OFFSET 0x800 +#define INFORM1_OFFSET 0x804 +#define INFORM2_OFFSET 0x808 +#define INFORM3_OFFSET 0x80c + +/* select serial console configuration */ +#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 + +/* Thermal Management Unit */ +#define CONFIG_EXYNOS_TMU + +/* MMC SPL */ +#define COPY_BL2_FNPTR_ADDR 0x02020030 + +/* specific .lds file */ + +/* Boot Argument Buffer Size */ +/* memtest works on */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + +#define CONFIG_RD_LVL + +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +#define CONFIG_SECURE_BL1_ONLY + +/* Secure FW size configuration */ +#ifdef CONFIG_SECURE_BL1_ONLY +#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ +#else +#define CONFIG_SEC_FW_SIZE 0 +#endif + +/* Configuration of BL1, BL2, ENV Blocks on mmc */ +#define CONFIG_RES_BLOCK_SIZE (512) +#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ +#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ + +#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) +#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) + +/* U-Boot copy size from boot Media to DRAM.*/ +#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) +#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) + +#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 +#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) + +/* I2C */ +#define CONFIG_SYS_I2C_S3C24X0 +#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ +#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 + +/* SPI */ + +/* Ethernet Controllor Driver */ +#ifdef CONFIG_CMD_NET +#define CONFIG_ENV_SROM_BANK 1 +#endif /*CONFIG_CMD_NET*/ + +/* Enable Time Command */ + +/* USB */ + +/* USB boot mode */ +#define CONFIG_USB_BOOTING +#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 +#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 +#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 2) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#ifndef MEM_LAYOUT_ENV_SETTINGS +/* 2GB RAM, bootm size of 256M, load scripts after that */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x42000000\0" \ + "fdt_addr_r=0x43000000\0" \ + "ramdisk_addr_r=0x43300000\0" \ + "scriptaddr=0x50000000\0" \ + "pxefile_addr_r=0x51000000\0" +#endif + +#ifndef EXYNOS_DEVICE_SETTINGS +#define EXYNOS_DEVICE_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" +#endif + +#ifndef EXYNOS_FDTFILE_SETTING +#define EXYNOS_FDTFILE_SETTING +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS \ + EXYNOS_FDTFILE_SETTING \ + MEM_LAYOUT_ENV_SETTINGS \ + BOOTENV + +#endif /* __CONFIG_EXYNOS5_COMMON_H */ diff --git a/roms/u-boot/include/configs/exynos5-dt-common.h b/roms/u-boot/include/configs/exynos5-dt-common.h new file mode 100644 index 000000000..cc9ffda66 --- /dev/null +++ b/roms/u-boot/include/configs/exynos5-dt-common.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Google, Inc + * + * Configuration settings for generic Exynos 5 board + */ + +#ifndef __CONFIG_EXYNOS5_DT_COMMON_H +#define __CONFIG_EXYNOS5_DT_COMMON_H + +/* Console configuration */ +#undef EXYNOS_DEVICE_SETTINGS +#define EXYNOS_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#define CONFIG_EXYNOS5_DT + +#define CONFIG_SYS_SPI_BASE 0x12D30000 +#define FLASH_SIZE (4 << 20) +#define CONFIG_SPI_BOOTING + +#define CONFIG_BOARD_COMMON + +/* Display */ +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPP LCD_COLOR16 +#endif + +/* Enable keyboard */ +#define CONFIG_KEYBOARD + +#endif diff --git a/roms/u-boot/include/configs/exynos5250-common.h b/roms/u-boot/include/configs/exynos5250-common.h new file mode 100644 index 000000000..65da3815f --- /dev/null +++ b/roms/u-boot/include/configs/exynos5250-common.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* + * Copyright (C) 2012 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5250 board. + */ + +#ifndef __CONFIG_5250_H +#define __CONFIG_5250_H + +#define CONFIG_EXYNOS5250 + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 + +#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) + +#define CONFIG_IRAM_STACK 0x02050000 + +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK + +/* USB */ +#define CONFIG_USB_EHCI_EXYNOS + +#define CONFIG_USB_XHCI_EXYNOS + +/* DRAM Memory Banks */ +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ + +#endif /* __CONFIG_5250_H */ diff --git a/roms/u-boot/include/configs/exynos5420-common.h b/roms/u-boot/include/configs/exynos5420-common.h new file mode 100644 index 000000000..2d362f396 --- /dev/null +++ b/roms/u-boot/include/configs/exynos5420-common.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5420 SoC + */ + +#ifndef __CONFIG_EXYNOS5420_H +#define __CONFIG_EXYNOS5420_H + +#define CONFIG_EXYNOS5420 + +#define CONFIG_EXYNOS5_DT + +/* Provide the MACH_TYPE value that the vendor kernel requires. */ +#define CONFIG_MACH_TYPE 8002 + +#define CONFIG_VAR_SIZE_SPL + +#define CONFIG_IRAM_TOP 0x02074000 + +#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024) + +#define CONFIG_DEVICE_TREE_LIST "exynos5800-peach-pi" \ + "exynos5420-peach-pit exynos5420-smdk5420" + +#define CONFIG_PHY_IRAM_BASE 0x02020000 + +/* Address for relocating helper code (Last 4 KB of IRAM) */ +#define CONFIG_EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000) + +/* + * Low Power settings + */ +#define CONFIG_LOWPOWER_FLAG 0x02020028 +#define CONFIG_LOWPOWER_ADDR 0x0202002C + +#define CONFIG_USB_XHCI_EXYNOS + +#endif /* __CONFIG_EXYNOS5420_H */ diff --git a/roms/u-boot/include/configs/exynos7420-common.h b/roms/u-boot/include/configs/exynos7420-common.h new file mode 100644 index 000000000..6c0aa9bcd --- /dev/null +++ b/roms/u-boot/include/configs/exynos7420-common.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the Espresso7420 board. + * Copyright (C) 2016 Samsung Electronics + * Thomas Abraham + */ + +#ifndef __CONFIG_EXYNOS7420_COMMON_H +#define __CONFIG_EXYNOS7420_COMMON_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_EXYNOS7420 /* Exynos7 Family */ +#define CONFIG_S5P + +#include /* get chip and board defs */ +#include + +/* Size of malloc() pool before and after relocation */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* select serial console configuration */ + +/* Timer input clock frequency */ +#define COUNTER_FREQUENCY 24000000 + +/* Device Tree */ +#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420" + +/* IRAM Layout */ +#define CONFIG_IRAM_BASE 0x02100000 +#define CONFIG_IRAM_SIZE 0x58000 +#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE) +#define CPU_RELEASE_ADDR secondary_boot_addr + +/* select serial console configuration */ + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE + +/* Configuration of ENV Blocks */ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + +#ifndef MEM_LAYOUT_ENV_SETTINGS +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x42000000\0" \ + "fdt_addr_r=0x43000000\0" \ + "ramdisk_addr_r=0x43300000\0" \ + "scriptaddr=0x50000000\0" \ + "pxefile_addr_r=0x51000000\0" +#endif + +#ifndef EXYNOS_DEVICE_SETTINGS +#define EXYNOS_DEVICE_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" +#endif + +#ifndef EXYNOS_FDTFILE_SETTING +#define EXYNOS_FDTFILE_SETTING +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS \ + EXYNOS_FDTFILE_SETTING \ + MEM_LAYOUT_ENV_SETTINGS + +#endif /* __CONFIG_EXYNOS7420_COMMON_H */ diff --git a/roms/u-boot/include/configs/firefly-rk3288.h b/roms/u-boot/include/configs/firefly-rk3288.h new file mode 100644 index 000000000..df96c3295 --- /dev/null +++ b/roms/u-boot/include/configs/firefly-rk3288.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#endif diff --git a/roms/u-boot/include/configs/firefly_rk3308.h b/roms/u-boot/include/configs/firefly_rk3308.h new file mode 100644 index 000000000..3af249304 --- /dev/null +++ b/roms/u-boot/include/configs/firefly_rk3308.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __FIREFLY_RK3308_H +#define __FIREFLY_RK3308_H + +#include + +#define CONFIG_SUPPORT_EMMC_RPMB + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif diff --git a/roms/u-boot/include/configs/flea3.h b/roms/u-boot/include/configs/flea3.h new file mode 100644 index 000000000..f4753cf7c --- /dev/null +++ b/roms/u-boot/include/configs/flea3.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011, Stefano Babic + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * Copyright (C) 2007, Guennadi Liakhovetski + * + * Configuration for the flea3 board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + /* High Level Configuration Options */ +#define CONFIG_MX35 + +#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3 + +/* Set TEXT at the beginning of the NOR flash */ + +/* This is required to setup the ESDC controller */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) + +/* + * Hardware drivers + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */ +#define CONFIG_SYS_MXC_I2C3_SLAVE 0xfe + +/* + * UART (console) + */ +#define CONFIG_MXC_UART_BASE UART3_BASE + +/* + * Command definition + */ + +#define CONFIG_NET_RETRY_COUNT 100 + + +#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ + +/* + * Ethernet on SOC (FEC) + */ +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * Physical Memory Map + */ +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_GBL_DATA_OFFSET) + +/* + * MTD Command for mtdparts + */ + +/* + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +/* Monitor at beginning of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) + +/* Address and size of Redundant Environment Sector */ + +/* + * CFI FLASH driver setup + */ + +/* A non-standard buffered write algorithm */ + +/* + * NAND FLASH driver setup + */ +#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_NAND_LARGEPAGE + +/* + * Default environment and default scripts + * to update uboot and load kernel + */ + +#define CONFIG_HOSTNAME "flea3" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip_sta=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ + "addip=if test -n ${ipdyn};then run addip_dyn;" \ + "else run addip_sta;fi\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttymxc2,${baudrate}\0" \ + "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ + "loadaddr=80800000\0" \ + "kernel_addr_r=80800000\0" \ + "hostname=" CONFIG_HOSTNAME "\0" \ + "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ + "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \ + "flash_self=run ramargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr_r}\0" \ + "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ + "net_self=if run net_self_load;then " \ + "run ramargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ + "else echo Images not loades;fi\0" \ + "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ + "update=protect off ${uboot_addr} +80000;" \ + "erase ${uboot_addr} +80000;" \ + "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ + "upd=if run load;then echo Updating u-boot;if run update;" \ + "then echo U-Boot updated;" \ + "else echo Error updating u-boot !;" \ + "echo Board without bootloader !!;" \ + "fi;" \ + "else echo U-Boot not downloaded..exiting;fi\0" \ + "bootcmd=run net_nfs\0" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/galileo.h b/roms/u-boot/include/configs/galileo.h new file mode 100644 index 000000000..57483a2af --- /dev/null +++ b/roms/u-boot/include/configs/galileo.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015, Bin Meng + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +/* ns16550 UART is memory-mapped in Quark SoC */ +#undef CONFIG_SYS_NS16550_PORT_MAPPED + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +/* 10/100M Ethernet support */ +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_ALTDESCRIPTOR + +/* Environment configuration */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/gardena-smart-gateway-at91sam.h b/roms/u-boot/include/configs/gardena-smart-gateway-at91sam.h new file mode 100644 index 000000000..007cbb043 --- /dev/null +++ b/roms/u-boot/include/configs/gardena-smart-gateway-at91sam.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Atmel Corporation + * Copyright (C) 2019 Stefan Roese + * + * Configuation settings for the GARDENA smart Gateway (AT91SAM9G25) + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +#ifndef __ASSEMBLY__ +#include +#endif + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) + +/* NAND flash */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* SPL */ +#define CONFIG_SPL_MAX_SIZE 0x7000 +#define CONFIG_SPL_STACK 0x308000 + +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#define CONFIG_SPL_NAND_RAW_ONLY +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + +#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO + +#endif diff --git a/roms/u-boot/include/configs/gardena-smart-gateway-mt7688.h b/roms/u-boot/include/configs/gardena-smart-gateway-mt7688.h new file mode 100644 index 000000000..1b26466ed --- /dev/null +++ b/roms/u-boot/include/configs/gardena-smart-gateway-mt7688.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Stefan Roese + */ + +#ifndef __CONFIG_GARDENA_SMART_GATEWAY_H +#define __CONFIG_GARDENA_SMART_GATEWAY_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +/* SPL */ +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SPL_BSS_START_ADDR 0x80010000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_PAD_TO 0 + +/* Dummy value */ +#define CONFIG_SYS_UBOOT_BASE 0 + +/* Serial SPL */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_CLK 40000000 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 0xb0000c00 +#endif + +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 460800, 921600 } + +/* RAM */ + +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_CBSIZE 512 + +/* U-Boot */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +/* Environment settings */ + +/* + * Environment is right behind U-Boot in flash. Make sure U-Boot + * doesn't grow into the environment area. + */ +#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET + +#endif /* __CONFIG_GARDENA_SMART_GATEWAY_H */ diff --git a/roms/u-boot/include/configs/gazerbeam.h b/roms/u-boot/include/configs/gazerbeam.h new file mode 100644 index 000000000..560d6a3d1 --- /dev/null +++ b/roms/u-boot/include/configs/gazerbeam.h @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * DDR Setup + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +/* TODO: Check: Can this be unified with CONFIG_SYS_SDRAM_BASE? */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE + +/* + * Memory test + * TODO: Migrate! + */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/* + * Environment + */ + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ + +/* + * Environment Configuration + */ + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +/* TODO: Turn into string option and migrate to Kconfig */ +#define CONFIG_HOSTNAME "gazerbeam" +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS1\0" \ + "u-boot=u-boot.bin\0" \ + "kernel_addr=1000000\0" \ + "fdt_addr=C00000\0" \ + "fdtfile=hrcon.dtb\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ + " +${filesize};cp.b ${fileaddr} " \ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp ${kernel_addr} $bootfile;" \ + "tftp ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_MMCBOOTCOMMAND \ + "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ + "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/ge_b1x5v2.h b/roms/u-boot/include/configs/ge_b1x5v2.h new file mode 100644 index 000000000..7db6afd88 --- /dev/null +++ b/roms/u-boot/include/configs/ge_b1x5v2.h @@ -0,0 +1,127 @@ +/* + * GE B1x5v2 + * + * Copyright 2018-2020 GE Inc. + * Copyright 2018-2020 Collabora Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __GE_B1X5V2_CONFIG_H +#define __GE_B1X5V2_CONFIG_H + +#include "mx6_common.h" + +#include "imx6_spl.h" +#define CONFIG_SPL_TARGET "u-boot-with-spl.imx" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +/* PWM */ +#define CONFIG_IMX6_PWM_PER_CLK 66000000 + +/* UART */ +#define CONFIG_MXC_UART_BASE UART3_BASE + +#if CONFIG_MXC_UART_BASE == UART2_BASE +/* UART2 requires CONFIG_DEBUG_UART_BASE=0x21e8000 */ +#define CONSOLE_DEVICE "ttymxc1" /* System on Module debug connector */ +#else +/* UART3 requires CONFIG_DEBUG_UART_BASE=0x21ec000 */ +#define CONSOLE_DEVICE "ttymxc2" /* Base board debug connector */ +#endif + +/* USB */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ +#define CONFIG_USBD_HS + +/* Video */ +#define CONFIG_HIDE_LOGO_VERSION +#define CONFIG_IMX_VIDEO_SKIP + +/* Memory */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Command definition */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "image=/boot/fitImage\0" \ + "fdt_addr_r=0x18000000\0" \ + "splash_addr_r=0x20000000\0" \ + "mmcdev=2\0" \ + "mmcpart=1\0" \ + "console=console="CONSOLE_DEVICE",115200\0" \ + "quiet=quiet loglevel=0\0" \ + "rootdev=/dev/mmcblk1p\0" \ + "setargs=setenv bootargs ${console} ${quiet} ${fsckforcerepair} " \ + "bootcause=${bootcause} vt.global_cursor_default=0 vt.cur_default=1 " \ + "root=${rootdev}${mmcpart} video=HDMI-A-1:${resolution} rootwait ro\0" \ + "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "showsplashscreen=load mmc ${mmcdev}:${mmcpart} ${splash_addr_r} /boot/splashscreen-${resolution}.bmp; " \ + "bmp display ${splash_addr_r};\0" \ + "setconfidx=" \ + "if test \"${devicetype}\" = \"B105v2\"; then " \ + "setenv confidx 1; " \ + "elif test \"${devicetype}\" = \"B125v2\"; then " \ + "setenv confidx 2; " \ + "elif test \"${devicetype}\" = \"B155v2\"; then " \ + "setenv confidx 3; " \ + "elif test \"${devicetype}\" = \"B105Pv2\"; then " \ + "setenv confidx 4; " \ + "elif test \"${devicetype}\" = \"B125Pv2\"; then " \ + "setenv confidx 5; " \ + "fi;\0" \ + "set_default_type=setenv devicetype B155v2; setenv resolution 1366x768;" \ + "setenv fdtfile imx6dl-b155v2.dtb; run setconfidx;\0" \ + "checkconfidx=env exists confidx || run set_default_type;\0" \ + "checkfsckforcerepair=" \ + "if test \"${bootcount}\" > \"3\" ; then " \ + "setenv fsckforcerepair fsck.repair=1; " \ + "fi;\0" \ + "helix=run setconfidx; run checkconfidx; run checkfsckforcerepair; run setargs; " \ + "regulator dev LED_VCC; regulator enable; " \ + "regulator dev 5V0_AUDIO; regulator enable; " \ + "bootm ${loadaddr}#conf@${confidx};\0" \ + "failbootcmd=" \ + "echo reached failbootcmd;" \ + "cls; setcurs 5 4; " \ + "lcdputs \"Monitor failed to start. Try again, or contact GE Service for support.\"; " \ + "bootcount reset; \0" \ + "hasfirstboot=" \ + "load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "/boot/bootcause/firstboot;\0" \ + "swappartitions=" \ + "setexpr mmcpart 3 - ${mmcpart};\0" \ + "doboot=" \ + "echo Booting from mmc:${mmcdev}:${mmcpart} ...; " \ + "run helix;\0" \ + "altbootcmd=" \ + "setenv mmcpart 1; run hasfirstboot || setenv mmcpart 2; " \ + "run hasfirstboot || setenv mmcpart 0; " \ + "if test ${mmcpart} != 0; then " \ + "setenv bootcause REVERT; " \ + "run swappartitions loadimage doboot; " \ + "fi; " \ + "run failbootcmd\0" \ + "tryboot=" \ + "setenv mmcpart 1; run hasfirstboot || setenv mmcpart 2; " \ + "run loadimage || run swappartitions && run loadimage || " \ + "setenv mmcpart 0 && echo MISSING IMAGE;" \ + "run showsplashscreen; sleep 1; " \ + "run doboot; run failbootcmd;\0" \ + +#define CONFIG_BOOTCOMMAND "run tryboot;" + +#endif /* __GE_B1X5V2_CONFIG_H */ diff --git a/roms/u-boot/include/configs/ge_bx50v3.h b/roms/u-boot/include/configs/ge_bx50v3.h new file mode 100644 index 000000000..c8e9d3b17 --- /dev/null +++ b/roms/u-boot/include/configs/ge_bx50v3.h @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Timesys Corporation + * Copyright (C) 2015 General Electric Company + * Copyright (C) 2014 Advantech + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Configuration settings for the GE MX6Q Bx50v3 boards. + */ + +#ifndef __GE_BX50V3_CONFIG_H +#define __GE_BX50V3_CONFIG_H + +#include +#include + +#define CONFIG_BOARD_NAME "General Electric Bx50v3" + +#include "mx6_common.h" +#include + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +/* SATA Configs */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#endif + +/* USB Configs */ +#ifdef CONFIG_USB +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_MASS_STORAGE +#endif + +/* Serial Flash */ + +#define CONFIG_LOADADDR 0x12000000 + +#ifdef CONFIG_CMD_NFS +#define NETWORKBOOT \ + "setnetworkboot=" \ + "setenv ipaddr 172.16.2.10; setenv serverip 172.16.2.20; " \ + "setenv gatewayip 172.16.2.20; setenv nfsserver 172.16.2.20; " \ + "setenv netmask 255.255.255.0; setenv ethaddr ca:fe:de:ca:f0:11; " \ + "setenv bootargs root=/dev/nfs nfsroot=${nfsserver}:/srv/nfs/,v3,tcp rw rootwait" \ + "setenv bootargs $bootargs ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off " \ + "setenv bootargs $bootargs cma=128M bootcause=${bootcause} ${videoargs} " \ + "setenv bootargs $bootargs systemd.mask=helix-network-defaults.service " \ + "setenv bootargs $bootargs watchdog.handle_boot_enabled=1\0" \ + "networkboot=" \ + "run setnetworkboot; " \ + "nfs ${loadaddr} /srv/nfs/fitImage; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_NETWORKBOOTCOMMAND \ + "run networkboot; " \ + +#else +#define NETWORKBOOT \ + +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + NETWORKBOOT \ + "image=/boot/fitImage\0" \ + "dev=mmc\0" \ + "devnum=2\0" \ + "rootdev=mmcblk0p\0" \ + "quiet=quiet loglevel=0\0" \ + "setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \ + "ro rootwait cma=128M " \ + "bootcause=${bootcause} " \ + "${quiet} " \ + "${videoargs}" "\0" \ + "doquiet=" \ + "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \ + "then setenv quiet; fi\0" \ + "hasfirstboot=" \ + "test -e ${dev} ${devnum}:${partnum} /boot/bootcause/firstboot\0" \ + "swappartitions=" \ + "setexpr partnum 3 - ${partnum}\0" \ + "failbootcmd=" \ + "cls; " \ + "setcurs 5 4; " \ + "lcdputs \"Monitor failed to start. " \ + "Try again, or contact GE Service for support.\"; " \ + "bootcount reset; " \ + "while true; do sleep 1; done; \0" \ + "altbootcmd=" \ + "run doquiet; " \ + "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ + "run hasfirstboot || setenv partnum 0; " \ + "if test ${partnum} != 0; then " \ + "run swappartitions loadimage doboot; " \ + "fi; " \ + "run failbootcmd\0" \ + "loadimage=" \ + "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ + "doboot=" \ + "echo Booting from ${dev}:${devnum}:${partnum} ...; " \ + "run setargs; " \ + "bootm ${loadaddr}\0" \ + "tryboot=" \ + "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ + "run loadimage || run swappartitions && run loadimage || " \ + "setenv partnum 0 && echo MISSING IMAGE;" \ + "run doboot; " \ + "run failbootcmd\0" \ + +#define CONFIG_MMCBOOTCOMMAND \ + "run doquiet; " \ + "run tryboot; " \ + +#ifdef CONFIG_CMD_NFS +#define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND +#else +#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND +#endif + + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* environment organization */ + +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +/* Framebuffer */ +#define CONFIG_HIDE_LOGO_VERSION +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +#define CONFIG_IMX6_PWM_PER_CLK 66000000 + +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5) + +#endif /* __GE_BX50V3_CONFIG_H */ diff --git a/roms/u-boot/include/configs/geekbox.h b/roms/u-boot/include/configs/geekbox.h new file mode 100644 index 000000000..4b12eb7af --- /dev/null +++ b/roms/u-boot/include/configs/geekbox.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2016 Andreas Färber + */ + +#ifndef __CONFIGS_GEEKBOX_H +#define __CONFIGS_GEEKBOX_H + +#include + +#endif diff --git a/roms/u-boot/include/configs/giedi.h b/roms/u-boot/include/configs/giedi.h new file mode 100644 index 000000000..dabb1fb17 --- /dev/null +++ b/roms/u-boot/include/configs/giedi.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Siemens AG + * + */ + +#ifndef __GIEDI_H +#define __GIEDI_H + +#include "capricorn-common.h" + +#undef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07") + +/* DDR3 board total DDR is 1 GB */ +#undef PHYS_SDRAM_1_SIZE +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ + +#endif /* __GIEDI_H */ diff --git a/roms/u-boot/include/configs/goflexhome.h b/roms/u-boot/include/configs/goflexhome.h new file mode 100644 index 000000000..a18e7869b --- /dev/null +++ b/roms/u-boot/include/configs/goflexhome.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Suriyan Ramasami + * + * Based on dockstar.h originally written by + * Copyright (C) 2010 Eric C. Cooper + * + * Based on sheevaplug.h originally written by + * Prafulla Wadaskar + * (C) Copyright 2009 + * Marvell Semiconductor + */ + +#ifndef _CONFIG_GOFLEXHOME_H +#define _CONFIG_GOFLEXHOME_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Default GPIO configuration and LED status + */ +#define GOFLEXHOME_OE_LOW (~(0)) +#define GOFLEXHOME_OE_HIGH (~(0)) +#define GOFLEXHOME_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ +#define GOFLEXHOME_OE_VAL_HIGH (1 << 17) /* LED pin high */ + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#include "mv-common.h" + +/* + * Environment variables configurations + */ +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part root; " \ + "ubifsmount ubi:root; " \ + "ubifsload 0x800000 ${kernel}; " \ + "bootm 0x800000" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS_DEFAULT \ + "kernel=/boot/uImage\0" \ + "bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 +#endif /* CONFIG_CMD_NET */ + +#endif /* _CONFIG_GOFLEXHOME_H */ diff --git a/roms/u-boot/include/configs/gose.h b/roms/u-boot/include/configs/gose.h new file mode 100644 index 000000000..60a89e002 --- /dev/null +++ b/roms/u-boot/include/configs/gose.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * include/configs/gose.h + * + * Copyright (C) 2014 Renesas Electronics Corporation + */ + +#ifndef __GOSE_H +#define __GOSE_H + +#include "rcar-gen2-common.h" + +#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 +#define STACK_AREA_SIZE 0x00100000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024) + +/* SH Ether */ +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" + +/* SPL support */ +#define CONFIG_SPL_STACK 0xe6340000 +#define CONFIG_SPL_MAX_SIZE 0x4000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIF0 +#define CONFIG_SH_SCIF_CLK_FREQ 65000000 +#endif + +#endif /* __GOSE_H */ diff --git a/roms/u-boot/include/configs/gplugd.h b/roms/u-boot/include/configs/gplugd.h new file mode 100644 index 000000000..a0554d7f8 --- /dev/null +++ b/roms/u-boot/include/configs/gplugd.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * eInfochips Ltd. + * Written-by: Ajay Bhargav + * + * Based on Aspenite: + * (C) Copyright 2010 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * Contributor: Mahavir Jain + */ + +#ifndef __CONFIG_GPLUGD_H +#define __CONFIG_GPLUGD_H + +/* + * High Level Configuration Options + */ +#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ +#define CONFIG_ARMADA100 1 /* SOC Family Name */ +#define CONFIG_ARMADA168 1 /* SOC Used on this Board */ +#define CONFIG_MACH_TYPE MACH_TYPE_GPLUGD /* Machine type */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * There is no internal RAM in ARMADA100, using DRAM + * TBD: dcache to be used for this + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) + +/* Network configuration */ +#ifdef CONFIG_CMD_NET +#define CONFIG_ARMADA100_FEC + +/* DHCP Support */ +#define CONFIG_BOOTP_DHCP_REQUEST_DELAY 50000 +#endif /* CONFIG_CMD_NET */ + +/* GPIO Support */ +#define CONFIG_MARVELL_GPIO + +/* PHY configuration */ +#define CONFIG_RESET_PHY_R +/* 88E3015 register definition */ +#define PHY_LED_PAR_SEL_REG 22 +#define PHY_LED_MAN_REG 25 +#define PHY_LED_VAL 0x5b /* LINK LED1, ACT LED2 */ +/* GPIO Configuration for PHY */ +#define CONFIG_SYS_GPIO_PHY_RST 104 /* GPIO104 */ + +/* Flash Support */ + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#ifdef CONFIG_SYS_NS16550_COM1 +#undef CONFIG_SYS_NS16550_COM1 +#endif /* CONFIG_SYS_NS16550_COM1 */ + +#define CONFIG_SYS_NS16550_COM1 ARMD1_UART3_BASE + +/* + * Environment variables configurations + */ + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI_ARMADA100 +#define CONFIG_EHCI_IS_TDI +#endif /* CONFIG_CMD_USB */ + +#endif /* __CONFIG_GPLUGD_H */ diff --git a/roms/u-boot/include/configs/grpeach.h b/roms/u-boot/include/configs/grpeach.h new file mode 100644 index 000000000..4d5eab09f --- /dev/null +++ b/roms/u-boot/include/configs/grpeach.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the Renesas GRPEACH board + * + * Copyright (C) 2017-2019 Renesas Electronics + */ + +#ifndef __GRPEACH_H +#define __GRPEACH_H + +/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */ +#define CONFIG_SYS_CLK_FREQ 66666666 + +/* Miscellaneous */ +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_CMDLINE_TAG + +/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024) +#define CONFIG_SYS_LOAD_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) + +/* Malloc */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) + +/* Network interface */ +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_BITBANGMII_MULTI + +#endif /* __GRPEACH_H */ diff --git a/roms/u-boot/include/configs/gru.h b/roms/u-boot/include/configs/gru.h new file mode 100644 index 000000000..be2dc7996 --- /dev/null +++ b/roms/u-boot/include/configs/gru.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#endif diff --git a/roms/u-boot/include/configs/guruplug.h b/roms/u-boot/include/configs/guruplug.h new file mode 100644 index 000000000..8de888fe7 --- /dev/null +++ b/roms/u-boot/include/configs/guruplug.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009-2014 + * Gerald Kerma + * Marvell Semiconductor + * Written-by: Siddarth Gore + */ + +#ifndef _CONFIG_GURUPLUG_H +#define _CONFIG_GURUPLUG_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ + +/* + * Standard filesystems + */ + +/* + * mv-plug-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-plug-common.h" + +/* + * Environment variables configurations + */ +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +/* + * Environment is right behind U-Boot in flash. Make sure U-Boot + * doesn't grow into the environment area. + */ +#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part root; " \ + "ubifsmount ubi:rootfs; " \ + "ubifsload 0x800000 ${kernel}; " \ + "ubifsload 0x700000 ${fdt}; " \ + "ubifsumount; " \ + "fdt addr 0x700000; fdt resize; fdt chosen; " \ + "bootz 0x800000 - 0x700000" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS_DEFAULT \ + "kernel=/boot/zImage\0" \ + "fdt=/boot/guruplug-server-plus.dtb\0" \ + "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ +#define CONFIG_PHY_BASE_ADR 0 +#endif /* CONFIG_CMD_NET */ + +#endif /* _CONFIG_GURUPLUG_H */ diff --git a/roms/u-boot/include/configs/gw_ventana.h b/roms/u-boot/include/configs/gw_ventana.h new file mode 100644 index 000000000..4f2f323b7 --- /dev/null +++ b/roms/u-boot/include/configs/gw_ventana.h @@ -0,0 +1,277 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Gateworks Corporation + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* SPL */ +/* Location in NAND to read U-Boot from */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * SZ_1M) + +/* Falcon Mode */ +#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 + +/* Falcon Mode - NAND support: args@17MB kernel@18MB */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS (18 * SZ_1M) + +/* Falcon Mode - MMC support: args@1MB kernel@2MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ + +#include "imx6_spl.h" /* common IMX6 SPL configuration */ +#include "mx6_common.h" + +#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */ + +/* Serial ATAG */ +#define CONFIG_SERIAL_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +/* Serial */ +#define CONFIG_MXC_UART_BASE UART2_BASE + +/* NAND */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_I2C_GSC 0 +#define CONFIG_I2C_EDID + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_DWC_AHSATA_PORT_ID 0 + #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR + #define CONFIG_LBA48 +#endif + +/* + * PCI express + */ +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCIE_IMX +#endif + +/* + * PMIC + */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CONFIG_POWER_LTC3676 +#define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c + +/* Various command support */ + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USBD_HS + +/* Framebuffer and LCD */ +#define CONFIG_VIDEO_LOGO +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_HIDE_LOGO_VERSION /* Custom config to hide U-boot version */ + +/* Miscellaneous configurable options */ +#define CONFIG_HWCONFIG + +/* Memory configuration */ + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* + * MTD Command for mtdparts + */ + +/* Persistent Environment Config */ + +/* Environment */ +#define CONFIG_IPADDR 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.146 + +#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "splashpos=m,m\0" \ + "usb_pgood_delay=2000\0" \ + "console=ttymxc1\0" \ + "bootdevs=usb mmc sata flash\0" \ + "hwconfig=_UNKNOWN_\0" \ + "video=\0" \ + \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "disk=0\0" \ + "part=1\0" \ + \ + "fdt_high=0xffffffff\0" \ + "fdt_addr=0x18000000\0" \ + "initrd_high=0xffffffff\0" \ + "fixfdt=" \ + "fdt addr ${fdt_addr}\0" \ + "bootdir=boot\0" \ + "loadfdt=" \ + "if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \ + "echo Loaded DTB from ${bootdir}/${fdt_file}; " \ + "run fixfdt; " \ + "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \ + "echo Loaded DTB from ${bootdir}/${fdt_file1}; " \ + "run fixfdt; " \ + "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \ + "echo Loaded DTB from ${bootdir}/${fdt_file2}; " \ + "run fixfdt; " \ + "fi\0" \ + \ + "fs=ext4\0" \ + "script=6x_bootscript-ventana\0" \ + "loadscript=" \ + "if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \ + "source ${loadaddr}; " \ + "fi\0" \ + \ + "uimage=uImage\0" \ + "mmc_root=mmcblk0p1\0" \ + "mmc_boot=" \ + "setenv fsload \"${fs}load mmc ${disk}:${part}\"; " \ + "mmc dev ${disk} && mmc rescan && " \ + "setenv dtype mmc; run loadscript; " \ + "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/${mmc_root} rootfstype=${fs} " \ + "rootwait rw ${video} ${extra}; " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "bootm; " \ + "fi; " \ + "fi\0" \ + \ + "sata_boot=" \ + "setenv fsload \"${fs}load sata ${disk}:${part}\"; " \ + "sata init && " \ + "setenv dtype sata; run loadscript; " \ + "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/sda1 rootfstype=${fs} " \ + "rootwait rw ${video} ${extra}; " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "bootm; " \ + "fi; " \ + "fi\0" \ + "usb_boot=" \ + "setenv fsload \"${fs}load usb ${disk}:${part}\"; " \ + "usb start && usb dev ${disk} && " \ + "setenv dtype usb; run loadscript; " \ + "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/sda1 rootfstype=${fs} " \ + "rootwait rw ${video} ${extra}; " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "bootm; " \ + "fi; " \ + "fi\0" + +#ifdef CONFIG_SPI_FLASH + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \ + "image_uboot=ventana/u-boot_spi.imx\0" \ + \ + "spi_koffset=0x90000\0" \ + "spi_klen=0x200000\0" \ + \ + "spi_updateuboot=echo Updating uboot from " \ + "${serverip}:${image_uboot}...; " \ + "tftpboot ${loadaddr} ${image_uboot} && " \ + "sf probe && sf erase 0 80000 && " \ + "sf write ${loadaddr} 400 ${filesize}\0" \ + "spi_update=echo Updating OS from ${serverip}:${image_os} " \ + "to ${spi_koffset} ...; " \ + "tftp ${loadaddr} ${image_os} && " \ + "sf probe && " \ + "sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \ + \ + "flash_boot=" \ + "if sf probe && " \ + "sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/mtdblock3 " \ + "rootfstype=squashfs,jffs2 " \ + "${video} ${extra}; " \ + "bootm; " \ + "fi\0" +#else + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + \ + "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ + "nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \ + "tftp ${loadaddr} ${image_rootfs} && " \ + "nand erase.part rootfs && " \ + "nand write ${loadaddr} rootfs ${filesize}\0" \ + \ + "flash_boot=" \ + "setenv fsload 'ubifsload'; " \ + "ubi part rootfs; " \ + "if ubi check boot; then " \ + "ubifsmount ubi0:boot; " \ + "setenv root ubi0:rootfs ubi.mtd=2 " \ + "rootfstype=squashfs,ubifs; " \ + "setenv bootdir; " \ + "elif ubi check rootfs; then " \ + "ubifsmount ubi0:rootfs; " \ + "setenv root ubi0:rootfs ubi.mtd=2 " \ + "rootfstype=ubifs; " \ + "fi; " \ + "setenv dtype nand; run loadscript; " \ + "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=${root} ${video} ${extra}; " \ + "if run loadfdt; then " \ + "ubifsumount; " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "ubifsumount; bootm; " \ + "fi; " \ + "fi\0" +#endif + +#define CONFIG_BOOTCOMMAND \ + "for btype in ${bootdevs}; do " \ + "echo; echo Attempting ${btype} boot...; " \ + "if run ${btype}_boot; then; fi; " \ + "done" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/harmony.h b/roms/u-boot/include/configs/harmony.h new file mode 100644 index 000000000..b2464f90d --- /dev/null +++ b/roms/u-boot/include/configs/harmony.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include "tegra20-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTD + +/* UARTD: keyboard satellite board UART, default */ +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#ifdef CONFIG_TEGRA_ENABLE_UARTA +/* UARTA: debug board UART */ +#define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE +#endif + +#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY + +/* NAND support */ +#define CONFIG_TEGRA_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Environment in NAND (which is 512M), aligned to start of last sector */ + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/helios4.h b/roms/u-boot/include/configs/helios4.h new file mode 100644 index 000000000..2cda05c85 --- /dev/null +++ b/roms/u-boot/include/configs/helios4.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Dennis Gilmore + */ + +#ifndef _CONFIG_HELIOS4_H +#define _CONFIG_HELIOS4_H + +#include + +/* + * High Level Configuration Options (easy to change) + */ + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +#define CONFIG_ENV_MIN_ENTRIES 128 + +/* Environment in MMC */ +/* + * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC + * boot image starts @ LBA-0. + * As result in MMC/eMMC case it will be a 1 sector gap between u-boot + * image and environment + */ + +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* SATA support */ +#ifdef CONFIG_SCSI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#endif + +/* Keep device tree and initrd in lower memory so the kernel can access them */ +#define RELOCATION_LIMITS_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +/* SPL */ + +/* Defines for SPL */ +#define CONFIG_SPL_SIZE (140 << 10) +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI) +/* SPL related SPI defines */ +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS +#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA) +/* SPL related MMC defines */ +#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS +#ifdef CONFIG_SPL_BUILD +#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ +#endif +#endif + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Include the common distro boot environment */ +#ifndef CONFIG_SPL_BUILD + +#ifdef CONFIG_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#ifdef CONFIG_USB_STORAGE +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + +#ifndef CONFIG_SCSI +#define BOOT_TARGET_DEVICES_SCSI_BUS0(func) +#define BOOT_TARGET_DEVICES_SCSI_BUS1(func) +#define BOOT_TARGET_DEVICES_SCSI_BUS2(func) +#else +/* + * With SCSI enabled, M.2 SATA is always located on bus 0 + */ +#define BOOT_TARGET_DEVICES_SCSI_BUS0(func) func(SCSI, scsi, 0) + +/* + * Either one or both mPCIe slots may be configured as mSATA interfaces. The + * SCSI bus ids are assigned based on sequence of hardware present, not always + * tied to hardware slot ids. As such, use second SCSI bus if either slot is + * set for SATA, and only use third SCSI bus if both slots are SATA enabled. + */ +#if defined (CONFIG_HELIOS4_CON2_SATA) || defined (CONFIG_HELIOS4_CON3_SATA) +#define BOOT_TARGET_DEVICES_SCSI_BUS1(func) func(SCSI, scsi, 1) +#else +#define BOOT_TARGET_DEVICES_SCSI_BUS1(func) +#endif + +#if defined (CONFIG_HELIOS4_CON2_SATA) && defined (CONFIG_HELIOS4_CON3_SATA) +#define BOOT_TARGET_DEVICES_SCSI_BUS2(func) func(SCSI, scsi, 2) +#else +#define BOOT_TARGET_DEVICES_SCSI_BUS2(func) +#endif + +#endif /* CONFIG_SCSI */ + +/* + * The SCSI buses are attempted in increasing bus order, there is no current + * mechanism to alter the default bus priority order for booting. + */ +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_USB(func) \ + BOOT_TARGET_DEVICES_SCSI_BUS0(func) \ + BOOT_TARGET_DEVICES_SCSI_BUS1(func) \ + BOOT_TARGET_DEVICES_SCSI_BUS2(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#define KERNEL_ADDR_R __stringify(0x800000) +#define FDT_ADDR_R __stringify(0x100000) +#define RAMDISK_ADDR_R __stringify(0x1800000) +#define SCRIPT_ADDR_R __stringify(0x200000) +#define PXEFILE_ADDR_R __stringify(0x300000) + +#define LOAD_ADDRESS_ENV_SETTINGS \ + "kernel_addr_r=" KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" FDT_ADDR_R "\0" \ + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ + "scriptaddr=" SCRIPT_ADDR_R "\0" \ + "pxefile_addr_r=" PXEFILE_ADDR_R "\0" + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + RELOCATION_LIMITS_ENV_SETTINGS \ + LOAD_ADDRESS_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "console=ttyS0,115200\0" \ + BOOTENV + +#endif /* CONFIG_SPL_BUILD */ + +#endif /* _CONFIG_HELIOS4_H */ diff --git a/roms/u-boot/include/configs/highbank.h b/roms/u-boot/include/configs/highbank.h new file mode 100644 index 000000000..ff92c4f55 --- /dev/null +++ b/roms/u-boot/include/configs/highbank.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2010-2011 Calxeda, Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) + +#define CONFIG_SYS_TIMER_RATE (150000000/256) +#define CONFIG_SYS_TIMER_COUNTER (0xFFF34000 + 0x4) +#define CONFIG_SYS_TIMER_COUNTS_DOWN + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) + +#define CONFIG_PL011_CLOCK 150000000 + +#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ + +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 5 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_RESET_TO_RETRY + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR 0x800000 +#define CONFIG_SYS_64BIT_LBA + +/* Environment data setup +*/ +#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */ +#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x01000000 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x20000000\0" \ + "initrd_high=0x20000000\0" + +#endif diff --git a/roms/u-boot/include/configs/hihope-rzg2.h b/roms/u-boot/include/configs/hihope-rzg2.h new file mode 100644 index 000000000..68a51176e --- /dev/null +++ b/roms/u-boot/include/configs/hihope-rzg2.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/hihope-rzg2.h + * This file is HOPERUN HiHope RZ/G2 board configuration. + * + * Copyright (C) 2020 Renesas Electronics Corporation + */ + +#ifndef __HIHOPE_RZG2_H +#define __HIHOPE_RZG2_H + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_BITBANGMII_MULTI + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +#endif /* __HIHOPE_RZG2_H */ diff --git a/roms/u-boot/include/configs/hikey.h b/roms/u-boot/include/configs/hikey.h new file mode 100644 index 000000000..659fbee05 --- /dev/null +++ b/roms/u-boot/include/configs/hikey.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Linaro + * + * Peter Griffin + * + * Configuration for HiKey 96boards CE. Parts were derived from other ARM + * configurations. + */ + +#ifndef __HIKEY_H +#define __HIKEY_H + +#include + +#define CONFIG_POWER +#define CONFIG_POWER_HI6553 + +#define CONFIG_REMAKE_ELF + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* Physical Memory Map */ + +/* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */ + +#define PHYS_SDRAM_1 0x00000000 + +/* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/ +#define PHYS_SDRAM_1_SIZE 0x3EFFFFFF + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 19000000 + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0xf6801000 +#define GICC_BASE 0xf6802000 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) + +#ifdef CONFIG_USB_DWC2 +#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO +#endif + +#define CONFIG_HIKEY_GPIO + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* Initial environment variables */ + +/* + * Defines where the kernel and FDT will be put in RAM + */ + +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 1) \ + func(DHCP, dhcp, na) +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_name=Image\0" \ + "kernel_addr_r=0x00080000\0" \ + "fdtfile=hi6220-hikey.dtb\0" \ + "fdt_addr_r=0x02000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + BOOTENV + +/* Preserve environment on eMMC */ + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#endif /* __HIKEY_H */ diff --git a/roms/u-boot/include/configs/hikey960.h b/roms/u-boot/include/configs/hikey960.h new file mode 100644 index 000000000..04d458798 --- /dev/null +++ b/roms/u-boot/include/configs/hikey960.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Linaro + * Author: Manivannan Sadhasivam + */ + +#ifndef __HIKEY_H +#define __HIKEY_H + +#include + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* Physical Memory Map */ + +/* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */ + +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_SIZE 0xC0000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 19000000 + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0xe82b1000 +#define GICC_BASE 0xe82b2000 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "image=Image\0" \ + "fdtfile=hi3660-hikey960.dtb\0" \ + "fdt_addr_r=0x10000000\0" \ + "kernel_addr_r=0x11000000\0" \ + "scriptaddr=0x00020000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + BOOTENV + +/* TODO: Remove this once the SD clock is fixed */ +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1024 + +#endif /* __HIKEY_H */ diff --git a/roms/u-boot/include/configs/hsdk-4xd.h b/roms/u-boot/include/configs/hsdk-4xd.h new file mode 100644 index 000000000..5678f0a77 --- /dev/null +++ b/roms/u-boot/include/configs/hsdk-4xd.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Synopsys, Inc. All rights reserved. + * Author: Eugeniy Paltsev + */ + +#ifndef _CONFIG_HSDK_H_ +#define _CONFIG_HSDK_H_ + +#include + +/* + * CPU configuration + */ +#define NR_CPUS 4 +#define ARC_PERIPHERAL_BASE 0xF0000000 +#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000) +#define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000) + +/* + * Memory configuration + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE SZ_1G + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN SZ_2M +#define CONFIG_SYS_BOOTM_LEN SZ_128M +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +/* + * UART configuration + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK 33330000 +#define CONFIG_SYS_NS16550_MEM32 + +/* + * Ethernet PHY configuration + */ + +/* + * USB 1.1 configuration + */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 + +/* + * Environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "upgrade=if mmc rescan && " \ + "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \ + "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \ + "\"Fail to upgrade.\n" \ + "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \ + "; fi\0" \ + "core_mask=0xF\0" \ + "hsdk_hs45d=setenv core_mask 0x2; setenv haps_apb_location 0x1; \ +setenv l2_cache_ena 0x0; setenv icache_ena 0x0; setenv csm_location 0x10; \ +setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \ +setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \ + "hsdk_hs47d=setenv core_mask 0x1; setenv haps_apb_location 0x1; \ +setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \ +setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ +setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \ + "hsdk_hs47d_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \ +setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \ +setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \ +setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \ + "hsdk_hs48=setenv core_mask 0x1; setenv haps_apb_location 0x1; \ +setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \ +setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ +setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \ + "hsdk_hs48_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \ +setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \ +setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \ +setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \ + "hsdk_hs48x2=run hsdk_hs47dx2;\0" \ + "hsdk_hs47dx2=setenv core_mask 0x3; setenv haps_apb_location 0x1; \ +setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \ +setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ +setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \ +setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \ + "hsdk_hs48x3=run hsdk_hs47dx3;\0" \ + "hsdk_hs47dx3=setenv core_mask 0x7; setenv haps_apb_location 0x1; \ +setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \ +setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ +setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \ +setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \ +setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \ + "hsdk_hs48x4=run hsdk_hs47dx4;\0" \ + "hsdk_hs47dx4=setenv core_mask 0xF; setenv haps_apb_location 0x1; \ +setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \ +setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ +setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \ +setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \ +setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \ +setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0" + +/* + * Environment configuration + */ +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* Cli configuration */ +#define CONFIG_SYS_CBSIZE SZ_2K + +/* + * Callback configuration + */ + +#endif /* _CONFIG_HSDK_H_ */ diff --git a/roms/u-boot/include/configs/hsdk.h b/roms/u-boot/include/configs/hsdk.h new file mode 100644 index 000000000..3cc3b8c0a --- /dev/null +++ b/roms/u-boot/include/configs/hsdk.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Synopsys, Inc. All rights reserved. + */ + +#ifndef _CONFIG_HSDK_H_ +#define _CONFIG_HSDK_H_ + +#include + +/* + * CPU configuration + */ +#define NR_CPUS 4 +#define ARC_PERIPHERAL_BASE 0xF0000000 +#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000) +#define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000) + +/* + * Memory configuration + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE SZ_1G + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN SZ_2M +#define CONFIG_SYS_BOOTM_LEN SZ_128M +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +/* + * UART configuration + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK 33330000 +#define CONFIG_SYS_NS16550_MEM32 + +/* + * Ethernet PHY configuration + */ + +/* + * USB 1.1 configuration + */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 + +/* + * Environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "upgrade=if mmc rescan && " \ + "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \ + "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \ + "\"Fail to upgrade.\n" \ + "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \ + "; fi\0" \ + "core_dccm_0=0x10\0" \ + "core_dccm_1=0x6\0" \ + "core_dccm_2=0x10\0" \ + "core_dccm_3=0x6\0" \ + "core_iccm_0=0x10\0" \ + "core_iccm_1=0x6\0" \ + "core_iccm_2=0x10\0" \ + "core_iccm_3=0x6\0" \ + "core_mask=0xF\0" \ + "dcache_ena=0x1\0" \ + "icache_ena=0x1\0" \ + "non_volatile_limit=0xE\0" \ + "hsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; \ +setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \ +setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0;\0" \ + "hsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; \ +setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ +setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \ + "hsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \ +setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \ +setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \ + "hsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; \ +setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ +setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \ + "hsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \ +setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \ +setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \ + "hsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; \ +setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ +setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \ +setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \ + "hsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; \ +setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ +setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \ +setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \ +setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \ + "hsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; \ +setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ +setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \ +setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \ +setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \ +setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0" + +/* + * Environment configuration + */ +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* Cli configuration */ +#define CONFIG_SYS_CBSIZE SZ_2K + +/* + * Callback configuration + */ + +#endif /* _CONFIG_HSDK_H_ */ diff --git a/roms/u-boot/include/configs/huawei_hg556a.h b/roms/u-boot/include/configs/huawei_hg556a.h new file mode 100644 index 000000000..529fc9495 --- /dev/null +++ b/roms/u-boot/include/configs/huawei_hg556a.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + diff --git a/roms/u-boot/include/configs/ib62x0.h b/roms/u-boot/include/configs/ib62x0.h new file mode 100644 index 000000000..ba859a9a2 --- /dev/null +++ b/roms/u-boot/include/configs/ib62x0.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011-2012 + * Gerald Kerma + * Luka Perkov + */ + +#ifndef _CONFIG_IB62x0_H +#define _CONFIG_IB62x0_H + +/* + * High level configuration options + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +#include "mv-common.h" + +/* + * Environment variables configuration + */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part root; " \ + "ubifsmount ubi:rootfs; " \ + "ubifsload 0x800000 ${kernel}; " \ + "ubifsload 0x700000 ${fdt}; " \ + "ubifsumount; " \ + "fdt addr 0x700000; fdt resize; fdt chosen; " \ + "bootz 0x800000 - 0x700000" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS_DEFAULT \ + "kernel=/boot/zImage\0" \ + "fdt=/boot/ib62x0.dtb\0" \ + "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" + +/* + * Ethernet driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 +#undef CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +/* + * SATA driver configuration + */ +#ifdef CONFIG_IDE +#define __io +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /* CONFIG_IDE */ + +/* + * RTC driver configuration + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + +#endif /* _CONFIG_IB62x0_H */ diff --git a/roms/u-boot/include/configs/iconnect.h b/roms/u-boot/include/configs/iconnect.h new file mode 100644 index 000000000..c99490b85 --- /dev/null +++ b/roms/u-boot/include/configs/iconnect.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009-2012 + * Wojciech Dubowik + * Luka Perkov + */ + +#ifndef _CONFIG_ICONNECT_H +#define _CONFIG_ICONNECT_H + +/* + * High level configuration options + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Machine type + */ +#define CONFIG_MACH_TYPE MACH_TYPE_ICONNECT + +#include "mv-common.h" + +/* + * Environment variables configuration + */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part rootfs; " \ + "ubifsmount ubi:rootfs; " \ + "ubifsload 0x800000 ${kernel}; " \ + "bootm 0x800000" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS_DEFAULT \ + "kernel=/boot/uImage\0" \ + "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" + +/* + * Ethernet driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 11 +#undef CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +/* + * File system + */ + +#endif /* _CONFIG_ICONNECT_H */ diff --git a/roms/u-boot/include/configs/ids8313.h b/roms/u-boot/include/configs/ids8313.h new file mode 100644 index 000000000..362e2892d --- /dev/null +++ b/roms/u-boot/include/configs/ids8313.h @@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (c) 2011 IDS GmbH, Germany + * Sergej Stepanov + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * High Level Configuration Options + */ +#define CONFIG_BOOT_RETRY_TIME 900 +#define CONFIG_BOOT_RETRY_MIN 30 +#define CONFIG_RESET_TO_RETRY + +#define CONFIG_SYS_SICRH 0x00000000 +#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D) + +#define CONFIG_HWCONFIG + +/* + * Definitions for initial stack pointer and data area (in DCACHE ) + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ + - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Internal Definitions + */ +/* + * DDR Setup + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +/* + * Manually set up DDR parameters, + * as this board has not the SPD connected to I2C. + */ +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\ + 0x00010000 |\ + CSCONFIG_ROW_BIT_13 |\ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \ + CSCONFIG_BANK_BIT_3) + +#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */ +#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\ + (3 << TIMING_CFG0_WRT_SHIFT) |\ + (3 << TIMING_CFG0_RRT_SHIFT) |\ + (3 << TIMING_CFG0_WWT_SHIFT) |\ + (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_MRS_CYC_SHIFT)) +#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\ + (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\ + (4 << TIMING_CFG1_ACTTORW_SHIFT) |\ + (7 << TIMING_CFG1_CASLAT_SHIFT) |\ + (4 << TIMING_CFG1_REFREC_SHIFT) |\ + (4 << TIMING_CFG1_WRREC_SHIFT) |\ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\ + (2 << TIMING_CFG1_WRTORD_SHIFT)) +#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\ + (5 << TIMING_CFG2_CPO_SHIFT) |\ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\ + (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\ + (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\ + (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) + +#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\ + (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + +#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\ + SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\ + SDRAM_CFG_DBW_32 |\ + SDRAM_CFG_SDRAM_TYPE_DDR2) + +#define CONFIG_SYS_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\ + (0x0242 << SDRAM_MODE_SD_SHIFT)) +#define CONFIG_SYS_DDR_MODE_2 0x00000000 +#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\ + DDRCDR_PZ_NOMZ |\ + DDRCDR_NZ_NOMZ |\ + DDRCDR_ODT |\ + DDRCDR_M_ODR |\ + DDRCDR_Q_DRN) + +/* + * on-board devices + */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC2 + +/* + * NOR FLASH setup + */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CONFIG_FLASH_SHOW_PROGRESS 50 + +#define CONFIG_SYS_FLASH_BASE 0xFF800000 +#define CONFIG_SYS_FLASH_SIZE 8 + + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 + +/* + * NAND FLASH setup + */ +#define CONFIG_SYS_NAND_BASE 0xE1000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_PAGE_SIZE (2048) +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) +#define NAND_CACHE_PAGES 64 + + +/* + * MRAM setup + */ +#define CONFIG_SYS_MRAM_BASE 0xE2000000 +#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */ + +#define CONFIG_SYS_OR_TIMING_MRAM + + +/* + * CPLD setup + */ +#define CONFIG_SYS_CPLD_BASE 0xE3000000 +#define CONFIG_SYS_CPLD_SIZE 0x8000 + +#define CONFIG_SYS_OR_TIMING_MRAM + + +/* + * HW-Watchdog + */ +#define CONFIG_WATCHDOG 1 +#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF + +/* + * I2C setup + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 + +/* + * Ethernet setup + */ +#ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x1 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC1_PHYIDX 0 +#endif + +#ifdef CONFIG_TSEC2 +#define CONFIG_HAS_ETH1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define TSEC2_PHY_ADDR 0x3 +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC2_PHYIDX 0 +#endif +#define CONFIG_ETHPRIME "TSEC1" + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) + +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_SYS_SCCR_USBDRCM 3 + +/* + * U-Boot environment setup + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024) + +/* + * Environment Configuration + */ + +#define CONFIG_NETDEV eth1 +#define CONFIG_HOSTNAME "ids8313" +#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx" +#define CONFIG_BOOTFILE "ids8313/uImage" +#define CONFIG_UBOOTPATH "ids8313/u-boot.bin" +#define CONFIG_FDTFILE "ids8313/ids8313.dtb" +#define CONFIG_LOADADDR 0x400000 +#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" + +/* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR 0x100000 +#define CONFIG_LOADS_ECHO +#define CONFIG_TIMESTAMP +#define CONFIG_BOOTCOMMAND "run boot_cramfs" +#undef CONFIG_SYS_LOADS_BAUD_CHANGE + +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_DEV "0" + +/* mtdparts command line support */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" __stringify(CONFIG_NETDEV) "\0" \ + "ethprime=TSEC1\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot ${loadaddr} ${uboot}; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +${filesize}; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +${filesize}; " \ + "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ + " ${filesize}; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +${filesize}; " \ + "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ + " ${filesize}\0" \ + "console=ttyS0\0" \ + "fdtaddr=0x780000\0" \ + "kernel_addr=ff800000\0" \ + "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \ + "setbootargs=setenv bootargs " \ + "root=${rootdev} rw console=${console}," \ + "${baudrate} ${othbootargs}\0" \ + "setipargs=setenv bootargs root=${rootdev} rw " \ + "nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off " \ + "console=${console},${baudrate} ${othbootargs}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setipargs;run addmtd;" \ + "tftp ${loadaddr} ${bootfile};" \ + "tftp ${fdtaddr} ${fdtfile};" \ + "fdt addr ${fdtaddr};" \ + "bootm ${loadaddr} - ${fdtaddr}" + +/* UBI Support */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/imgtec_xilfpga.h b/roms/u-boot/include/configs/imgtec_xilfpga.h new file mode 100644 index 000000000..fcf1b7f99 --- /dev/null +++ b/roms/u-boot/include/configs/imgtec_xilfpga.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016, Imagination Technologies Ltd. + * + * Zubair Lutfullah Kakakhel + * + * Imagination Technologies Ltd. MIPSfpga + */ + +#ifndef __XILFPGA_CONFIG_H +#define __XILFPGA_CONFIG_H + +/* BootROM + MIG is pretty smart. DDR and Cache initialized */ +#define CONFIG_SKIP_LOWLEVEL_INIT + +/*-------------------------------------------- + * CPU configuration + */ +/* CPU Timer rate */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 50000000 + +/*---------------------------------------------------------------------- + * Memory Layout + */ + +/* SDRAM Configuration (for final code, data, stack, heap) */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000) + +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */ + +/*---------------------------------------------------------------------- + * Commands + */ + +/*------------------------------------------------------------ + * Console Configuration + */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* ------------------------------------------------- + * Environment + */ + +/* --------------------------------------------------------------------- + * Board boot configuration + */ +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#endif /* __XILFPGA_CONFIG_H */ diff --git a/roms/u-boot/include/configs/imx27lite-common.h b/roms/u-boot/include/configs/imx27lite-common.h new file mode 100644 index 000000000..8c5c06162 --- /dev/null +++ b/roms/u-boot/include/configs/imx27lite-common.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2010 Heiko Schocher + * + * based on: + * Copyright (C) 2009 Ilya Yanok + */ + +#ifndef __IMX27LITE_COMMON_CONFIG_H +#define __IMX27LITE_COMMON_CONFIG_H + +/* + * SoC Configuration + */ +#define CONFIG_MX27 +#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Lowlevel configuration + */ +#define SDRAM_ESDCFG_REGISTER_VAL(cas) \ + (ESDCFG_TRC(10) | \ + ESDCFG_TRCD(3) | \ + ESDCFG_TCAS(cas) | \ + ESDCFG_TRRD(1) | \ + ESDCFG_TRAS(5) | \ + ESDCFG_TWR | \ + ESDCFG_TMRD(2) | \ + ESDCFG_TRP(2) | \ + ESDCFG_TXP(3)) + +#define SDRAM_ESDCTL_REGISTER_VAL \ + (ESDCTL_PRCT(0) | \ + ESDCTL_BL | \ + ESDCTL_PWDT(0) | \ + ESDCTL_SREFR(3) | \ + ESDCTL_DSIZ_32 | \ + ESDCTL_COL10 | \ + ESDCTL_ROW13 | \ + ESDCTL_SDE) + +#define SDRAM_ALL_VAL 0xf00 + +#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ +#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000 + +#define MPCTL0_VAL 0x1ef15d5 + +#define SPCTL0_VAL 0x043a1c09 + +#define CSCR_VAL 0x33f08107 + +#define PCDR0_VAL 0x120470c3 +#define PCDR1_VAL 0x03030303 +#define PCCR0_VAL 0xffffffff +#define PCCR1_VAL 0xfffffffc + +#define AIPI1_PSR0_VAL 0x20040304 +#define AIPI1_PSR1_VAL 0xdffbfcfb +#define AIPI2_PSR0_VAL 0x07ffc200 +#define AIPI2_PSR1_VAL 0xffffffff + +/* + * Memory Info + */ +/* malloc() len */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024) +/* memtest start address */ +#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ + +/* + * Serial Driver info + */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* + * Flash & Environment + */ +/* Use buffered writes (~10x faster) */ +/* Use hardware sector protection */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ +/* CS2 Base address */ +#define PHYS_FLASH_1 0xc0000000 +/* Flash Base for U-Boot */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \ + CONFIG_SYS_FLASH_SECT_SZ) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ +/* Address and size of Redundant Environment Sector */ + +/* + * Ethernet + */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0x1f + +/* + * MTD + */ + +/* + * NAND + */ +#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0xd8000000 +#define CONFIG_JFFS2_NAND +#define CONFIG_MXC_NAND_HWECC + +/* + * U-Boot general configuration + */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttymxc0,${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ + "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ + "kernel_addr_r=a0800000\0" \ + "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ + "rootpath=/opt/eldk-4.2-arm/arm\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm\0" \ + "bootcmd=run net_nfs\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ + " +${filesize};cp.b ${fileaddr} " \ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ + GENERATED_GBL_DATA_SIZE) +#endif /* __IMX27LITE_COMMON_CONFIG_H */ diff --git a/roms/u-boot/include/configs/imx6-engicam.h b/roms/u-boot/include/configs/imx6-engicam.h new file mode 100644 index 000000000..bfe83b8cb --- /dev/null +++ b/roms/u-boot/include/configs/imx6-engicam.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * Configuration settings for the Engicam i.MX6 SOM Starter Kits. + */ + +#ifndef __IMX6_ENGICAM_CONFIG_H +#define __IMX6_ENGICAM_CONFIG_H + +#include +#include +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +/* Total Size of Environment Sector */ + +/* Environment */ +#ifndef CONFIG_ENV_IS_NOWHERE +/* Environment in MMC */ +# if defined(CONFIG_ENV_IS_IN_MMC) +/* Environment in NAND */ +# endif +#endif + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "splashpos=m,m\0" \ + "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "image=uImage\0" \ + "fit_image=fit.itb\0" \ + "fdt_high=0xffffffff\0" \ + "fdt_addr=" FDT_ADDR "\0" \ + "boot_fdt=try\0" \ + "mmcpart=1\0" \ + "nandroot=ubi0:rootfs rootfstype=ubifs\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "ubiargs=setenv bootargs console=${console},${baudrate} " \ + "ubi.mtd=5 root=${nandroot} ${mtdparts}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadfit=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${fit_image}\0" \ + "altbootcmd=run recoveryboot\0"\ + "fitboot=echo Booting FIT image from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "_mmcboot=run mmcargs; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadfit; then " \ + "run fitboot; " \ + "else " \ + "if run loadimage; then " \ + "run _mmcboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi\0" \ + "nandboot=echo Booting from nand ...; " \ + "if mtdparts; then " \ + "echo Starting nand boot ...; " \ + "else " \ + "mtdparts default; " \ + "fi; " \ + "run ubiargs; " \ + "nand read ${loadaddr} kernel 0x800000; " \ + "nand read ${fdt_addr} dtb 0x100000; " \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "recoveryboot=if test ${modeboot} = mmcboot; then " \ + "run mmcboot; " \ + "else " \ + "run nandboot; " \ + "fi\0" + +#define CONFIG_BOOTCOMMAND "run $modeboot" + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#ifdef CONFIG_MX6UL +# define DRAM_OFFSET(x) 0x87##x +# define FDT_ADDR __stringify(DRAM_OFFSET(800000)) +#else +# define DRAM_OFFSET(x) 0x1##x +# define FDT_ADDR __stringify(DRAM_OFFSET(8000000)) +#endif + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_SP_OFFSET) + +/* UART */ +#ifdef CONFIG_MXC_UART +# ifdef CONFIG_MX6UL +# define CONFIG_MXC_UART_BASE UART1_BASE +# else +# define CONFIG_MXC_UART_BASE UART4_BASE +# endif +#endif + +/* MMC */ + +/* NAND */ +#ifdef CONFIG_NAND_MXS +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_BASE 0x40000000 +# define CONFIG_SYS_NAND_5_ADDR_CYCLE +# define CONFIG_SYS_NAND_ONFI_DETECTION +# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 + +/* MTD device */ +#endif + +/* Falcon Mode */ +#ifdef CONFIG_SPL_OS_BOOT +# define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" +# define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +# define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 + +/* MMC support: args@1MB kernel@2MB */ +# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ +# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +# define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ +#endif + +/* Framebuffer */ +#ifdef CONFIG_VIDEO_IPUV3 +# define CONFIG_IMX_VIDEO_SKIP + +# define CONFIG_VIDEO_LOGO +# define CONFIG_VIDEO_BMP_LOGO +#endif + +/* SPL */ +#ifdef CONFIG_SPL +# ifdef CONFIG_ENV_IS_IN_NAND +# define CONFIG_SPL_NAND_SUPPORT +# else +# define CONFIG_SPL_MMC_SUPPORT +# endif + +# include "imx6_spl.h" +#endif + +#endif /* __IMX6_ENGICAM_CONFIG_H */ diff --git a/roms/u-boot/include/configs/imx6_logic.h b/roms/u-boot/include/configs/imx6_logic.h new file mode 100644 index 000000000..6b992f9ab --- /dev/null +++ b/roms/u-boot/include/configs/imx6_logic.h @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Logic PD, Inc. + * + * Configuration settings for the LogicPD i.MX6 SOM. + */ + +#ifndef __IMX6LOGIC_CONFIG_H +#define __IMX6LOGIC_CONFIG_H + +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONSOLE_DEV "ttymxc0" + +#ifdef CONFIG_SPL +#include "imx6_spl.h" +#endif + +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + + +/* Ethernet Configs */ +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "bootm_size=0x10000000\0" \ + "fdt_addr_r=0x14000000\0" \ + "ramdisk_addr_r=0x14080000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_file=rootfs.cpio.uboot\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "console=" CONSOLE_DEV "\0" \ + "mmcdev=1\0" \ + "mmcpart=1\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "nandroot=ubi0:rootfs rootfstype=ubifs\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate}" \ + " root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \ + "nandargs=setenv bootargs console=${console},${baudrate}" \ + " ubi.mtd=fs root=${nandroot} ${mtdparts} ${optargs}\0" \ + "ramargs=setenv bootargs console=${console},${baudrate}" \ + " root=/dev/ram rw ${mtdparts} ${optargs}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...;" \ + " source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};" \ + " setenv kernelsize ${filesize}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdt_file}\0" \ + "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr_r}" \ + " ${ramdisk_file}; setenv ramdisksize ${filesize}\0" \ + "mmcboot=echo Booting from mmc...; run finduuid; run mmcargs;" \ + "run loadimage; run loadfdt; bootz ${loadaddr} - ${fdt_addr_r}\0" \ + "mmcramboot=run ramargs; run loadimage;" \ + " run loadfdt; run loadramdisk;" \ + " bootz ${loadaddr} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ + "nandboot=echo Booting from nand ...; " \ + " run nandargs;" \ + " nand read ${loadaddr} kernel ${kernelsize};" \ + " nand read ${fdt_addr_r} dtb;" \ + " bootz ${loadaddr} - ${fdt_addr_r}\0" \ + "nandramboot=echo Booting RAMdisk from nand ...; " \ + " nand read ${ramdisk_addr_r} fs ${ramdisksize};" \ + " nand read ${loadaddr} kernel ${kernelsize};" \ + " nand read ${fdt_addr_r} dtb;" \ + " run ramargs;" \ + " bootz ${loadaddr} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs" \ + " ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr_r} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "autoboot=mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#define CONFIG_BOOTCOMMAND \ + "run autoboot" + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000 + +/* MTD device */ + +/* DMA stuff, needed for GPMI/MXS NAND support */ + +/* EEPROM contains serial no, MAC addr and other Logic PD info */ +#define CONFIG_I2C_EEPROM + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ +#endif + +/* Falcon Mode */ +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 + +/* Falcon Mode - MMC support: args@1MB kernel@2MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ + +#endif /* __IMX6LOGIC_CONFIG_H */ diff --git a/roms/u-boot/include/configs/imx6_spl.h b/roms/u-boot/include/configs/imx6_spl.h new file mode 100644 index 000000000..ede81cca1 --- /dev/null +++ b/roms/u-boot/include/configs/imx6_spl.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Gateworks Corporation + * Author: Tim Harvey + */ +#ifndef __IMX6_SPL_CONFIG_H +#define __IMX6_SPL_CONFIG_H + +#ifdef CONFIG_SPL + +#ifdef CONFIG_MX6_OCRAM_256KB +/* + * see Figure 8.4.1 in IMX6DQ Reference manuals: + * - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF + * - BOOT ROM stack is at 0x0093FFB8 + * - if icache/dcache is enabled (eFuse/strapping controlled) then the + * IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to + * fit between 0x00907000 and 0x00938000. + * - Additionally the BOOT ROM loads what they consider the firmware image + * which consists of a 4K header in front of us that contains the IVT, DCD + * and some padding thus 'our' max size is really 0x00908000 - 0x00938000 + * or 192KB + */ +#define CONFIG_SPL_MAX_SIZE 0x30000 +#define CONFIG_SPL_STACK 0x0093FFB8 +/* + * Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the + * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a + * boot media (given that boot media specific offset is configured properly). + */ +#define CONFIG_SPL_PAD_TO 0x31000 +#else +/* + * see Figure 8-3 in IMX6SDL Reference manuals: + * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF + * - BOOT ROM stack is at 0x0091FFB8 + * - if icache/dcache is enabled (eFuse/strapping controlled) then the + * IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to + * fit between 0x00907000 and 0x00918000. + * - Additionally the BOOT ROM loads what they consider the firmware image + * which consists of a 4K header in front of us that contains the IVT, DCD + * and some padding thus 'our' max size is really 0x00908000 - 0x00918000 + * or 64KB + */ +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_STACK 0x0091FFB8 +/* + * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the + * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a + * boot media (given that boot media specific offset is configured properly). + */ +#define CONFIG_SPL_PAD_TO 0x11000 + +#endif + +/* MMC support */ +#if defined(CONFIG_SPL_MMC_SUPPORT) +#define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ +#endif + +/* SATA support */ +#if defined(CONFIG_SPL_SATA_SUPPORT) +#define CONFIG_SPL_SATA_BOOT_DEVICE 0 +#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 +#endif + +/* Define the payload for FAT/EXT support */ +#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) +# ifdef CONFIG_OF_CONTROL +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" +# else +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +# endif +#endif + +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) +#define CONFIG_SPL_BSS_START_ADDR 0x88200000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x88300000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ +#else +#define CONFIG_SPL_BSS_START_ADDR 0x18200000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x18300000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ +#endif +#endif + +#endif diff --git a/roms/u-boot/include/configs/imx6dl-mamoj.h b/roms/u-boot/include/configs/imx6dl-mamoj.h new file mode 100644 index 000000000..4027f329d --- /dev/null +++ b/roms/u-boot/include/configs/imx6dl-mamoj.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Simone CIANNI + * Copyright (C) 2018 Raffaele RECALCATI + * Copyright (C) 2018 Jagan Teki + * + * Configuration settings for the BTicion i.MX6DL Mamoj board. + */ + +#ifndef __IMX6DL_MAMOJ_CONFIG_H +#define __IMX6DL_MAMOJ_CONFIG_H + +#include +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) + +/* Total Size of Environment Sector */ + +/* Environment */ +#ifndef CONFIG_ENV_IS_NOWHERE +/* Environment in MMC */ +#endif + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "scriptaddr=0x14000000\0" \ + "fdt_addr_r=0x13000000\0" \ + "kernel_addr_r=0x10008000\0" \ + "fdt_high=0xffffffff\0" \ + "dfu_alt_info_spl=spl raw 0x2 0x400\0" \ + "dfu_alt_info_uboot=u-boot raw 0x8a 0x11400\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 2) + +#include +#endif + +/* UART */ +#define CONFIG_MXC_UART_BASE UART3_BASE + +/* MMC */ + +/* Ethernet */ +#define CONFIG_FEC_MXC_PHYADDR 1 + +/* USB */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* Falcon */ +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000 + +/* MMC support: args@1MB kernel@2MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_SP_OFFSET) + +/* SPL */ +#include "imx6_spl.h" + +#endif /* __IMX6DL_MAMOJ_CONFIG_H */ diff --git a/roms/u-boot/include/configs/imx7-cm.h b/roms/u-boot/include/configs/imx7-cm.h new file mode 100644 index 000000000..4a3706d99 --- /dev/null +++ b/roms/u-boot/include/configs/imx7-cm.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 Ronetix GmbH + * + * Configuration settings for the Ronetix's iMX7-CM System-on-Module. + */ + +#ifndef __IMX7_CM_CONFIG_H +#define __IMX7_CM_CONFIG_H + +#include "mx7_common.h" + +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +#define CONFIG_ETHPRIME "FEC" + +#undef CONFIG_SYS_AUTOLOAD +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +/* + * Use: + * boot-mode=mix + * boot-mode=sd + * boot-mode=net + */ +#define MY_CONFIG_BOOT_MODE "boot-mode=sd\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + MY_CONFIG_BOOT_MODE \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_file=imx7-cm.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + \ + "bootsd=" \ + "echo Booting from SD card ...; " \ + "run mmcargs; " \ + "mmc dev ${mmcdev};" \ + "run loadimage; " \ + "run loadfdt; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "\0" \ + \ + "bootmix=" \ + "echo Boot Kernel and FDT from TFTP, RootFs from SD card ...; " \ + "run mmcargs; " \ + "mmc dev ${mmcdev};" \ + "tftp ${fdt_addr} ${fdt_file}; " \ + "tftp ${image}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "\0" \ + \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \ + "\0" \ + "bootnet=" \ + "echo Booting from net ...; " \ + "run netargs; " \ + "tftp ${image}; " \ + "tftp ${fdt_addr} ${fdt_file}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "\0" + +#define CONFIG_BOOTCOMMAND "run boot${boot-mode}" + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +/* USB Configs */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +#define CONFIG_USBD_HS + +/* SPL */ +#include "imx7_spl.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/imx7_spl.h b/roms/u-boot/include/configs/imx7_spl.h new file mode 100644 index 000000000..abf3dd57c --- /dev/null +++ b/roms/u-boot/include/configs/imx7_spl.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * SPL definitions for the i.MX7 SPL + * + * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com + * + * Author: Uri Mashiach + */ + +#ifndef __IMX7_SPL_CONFIG_H +#define __IMX7_SPL_CONFIG_H + +#ifdef CONFIG_SPL +/* + * see figure 6-22 in i.MX 7Dual/Solo Reference manuals: + * - IMX7D/S OCRAM free area RAM (OCRAM) is from 0x00910000 to + * 0x00946C00. + * - Set the stack at the end of the free area section, at 0x00946BB8. + * - The BOOT ROM loads what they consider the firmware image + * which consists of a 4K header in front of us that contains the IVT, DCD + * and some padding thus 'our' max size is really 0x00946BB8 - 0x00911000. + * 64KB is more then enough for the SPL. + */ +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_STACK 0x00946BB8 +/* + * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the + * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a + * boot media (given that boot media specific offset is configured properly). + */ +#define CONFIG_SPL_PAD_TO 0x11000 + +/* MMC support */ +#if defined(CONFIG_SPL_MMC_SUPPORT) +#define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ +#endif + +/* Define the payload for FAT/EXT support */ +#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) +# ifdef CONFIG_OF_CONTROL +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" +# else +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +# endif +#endif + +#define CONFIG_SPL_BSS_START_ADDR 0x88200000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x88300000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ + +#endif /* CONFIG_SPL */ + +#endif /* __IMX7_SPL_CONFIG_H */ diff --git a/roms/u-boot/include/configs/imx8mm-cl-iot-gate.h b/roms/u-boot/include/configs/imx8mm-cl-iot-gate.h new file mode 100644 index 000000000..faeee2178 --- /dev/null +++ b/roms/u-boot/include/configs/imx8mm-cl-iot-gate.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __IMX8MM_CL_IOT_GATE_H +#define __IMX8MM_CL_IOT_GATE_H + +#include +#include +#include +#include + +#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x920000 +#define CONFIG_SPL_BSS_START_ADDR 0x910000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x912000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +#if CONFIG_IS_ENABLED(CMD_MMC) +# define BOOT_TARGET_MMC(func) \ + func(MMC, mmc, 2) \ + func(MMC, mmc, 0) +#else +# define BOOT_TARGET_MMC(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_USB) +# define BOOT_TARGET_USB(func) func(USB, usb, 0) +#else +# define BOOT_TARGET_USB(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_PXE) +# define BOOT_TARGET_PXE(func) func(PXE, pxe, na) +#else +# define BOOT_TARGET_PXE(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_DHCP) +# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) +#else +# define BOOT_TARGET_DHCP(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_USB(func) \ + BOOT_TARGET_MMC(func) \ + BOOT_TARGET_PXE(func) \ + BOOT_TARGET_DHCP(func) + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_addr_r=0x43000000\0" \ + "boot_fit=no\0" \ + "dfu_alt_info=mmc 2=flash-bin raw 0x42 0x250 mmcpart 1;" \ + "u-boot-itb raw 0x300 0x1B00 mmcpart 1\0" \ + "fdt_file=sb-iotgimx8.dtb\0" \ + "fdtfile=sb-iotgimx8.dtb\0" \ + "initrd_addr=0x43800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "kernel_addr_r=0x40480000\0" \ + "pxefile_addr_r=0x40480000\0" \ + "ramdisk_addr_r=0x43800000\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" + +#ifndef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi;" +#endif + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* USDHC */ +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC + +#define IMX_FEC_BASE 0x30BE0000 + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#endif /*__IMX8MM_CL_IOT_GATE_H*/ diff --git a/roms/u-boot/include/configs/imx8mm_beacon.h b/roms/u-boot/include/configs/imx8mm_beacon.h new file mode 100644 index 000000000..94f4a1232 --- /dev/null +++ b/roms/u-boot/include/configs/imx8mm_beacon.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +#ifndef __IMX8MM_BEACON_H +#define __IMX8MM_BEACON_H + +#include +#include + +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x920000 +#define CONFIG_SPL_BSS_START_ADDR 0x910000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x930000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr=0x43000000\0" \ + "boot_fit=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate}" \ + " root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \ + " ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run finduuid; " \ + "run mmcargs; " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi;" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* USDHC */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* I2C */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* FEC*/ +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC +#define IMX_FEC_BASE 0x30BE0000 + +#endif diff --git a/roms/u-boot/include/configs/imx8mm_evk.h b/roms/u-boot/include/configs/imx8mm_evk.h new file mode 100644 index 000000000..8f3dd8fb6 --- /dev/null +++ b/roms/u-boot/include/configs/imx8mm_evk.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __IMX8MM_EVK_H +#define __IMX8MM_EVK_H + +#include +#include +#include + +#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x920000 +#define CONFIG_SPL_BSS_START_ADDR 0x910000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x930000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(DHCP, dhcp, na) + +#include +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "image=Image\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "boot_fit=no\0" \ + "fdtfile=imx8mm-evk.dtb\0" \ + "initrd_addr=0x43800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* USDHC */ +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC + +#define IMX_FEC_BASE 0x30BE0000 + +#endif diff --git a/roms/u-boot/include/configs/imx8mm_icore_mx8mm.h b/roms/u-boot/include/configs/imx8mm_icore_mx8mm.h new file mode 100644 index 000000000..af5be6889 --- /dev/null +++ b/roms/u-boot/include/configs/imx8mm_icore_mx8mm.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#ifndef __IMX8MM_ICORE_MX8MM_H +#define __IMX8MM_ICORE_MX8MM_H + +#include +#include + +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +# define CONFIG_SPL_STACK 0x920000 +# define CONFIG_SPL_BSS_START_ADDR 0x910000 +# define CONFIG_SPL_BSS_MAX_SIZE SZ_8K +# define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +# define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +# define CONFIG_MALLOC_F_ADDR 0x930000 +/* For RAW image gives a error info not panic */ +# define CONFIG_SPL_ABORT_ON_RAW_IMAGE +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 2) \ + func(MMC, mmc, 0) +#include +#undef CONFIG_ISO_PARTITION +#else +#define BOOTENV +#endif + +#define ENV_MEM_LAYOUT_SETTINGS \ + "fdt_addr_r=0x44000000\0" \ + "kernel_addr_r=0x42000000\0" \ + "ramdisk_addr_r=0x46400000\0" \ + "scriptaddr=0x46000000\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "console=ttymxc1,115200\0" \ + BOOTENV + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +/* SDRAM configuration */ +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ +#define CONFIG_SYS_BOOTM_LEN SZ_256M + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END \ + (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +/* UART */ +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* USDHC */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* I2C */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#endif /* __IMX8MM_ICORE_MX8MM_H */ diff --git a/roms/u-boot/include/configs/imx8mm_venice.h b/roms/u-boot/include/configs/imx8mm_venice.h new file mode 100644 index 000000000..91669255e --- /dev/null +++ b/roms/u-boot/include/configs/imx8mm_venice.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 Gateworks Corporation + */ + +#ifndef __IMX8MM_VENICE_H +#define __IMX8MM_VENICE_H + +#include +#include + +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x920000 +#define CONFIG_SPL_BSS_START_ADDR 0x910000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_1M + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x930000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +#define MEM_LAYOUT_ENV_SETTINGS \ + "fdt_addr_r=0x44000000\0" \ + "kernel_addr_r=0x42000000\0" \ + "ramdisk_addr_r=0x46400000\0" \ + "scriptaddr=0x46000000\0" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Enable Distro Boot */ +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(DHCP, dhcp, na) +#include +#undef CONFIG_ISO_PARTITION +#else +#define BOOTENV +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + MEM_LAYOUT_ENV_SETTINGS \ + "script=boot.scr\0" \ + "bootm_size=0x10000000\0" \ + "ipaddr=192.168.1.22\0" \ + "serverip=192.168.1.146\0" \ + "dev=2\0" \ + "preboot=gsc wd-disable\0" \ + "console=ttymxc1,115200\0" \ + "update_firmware=" \ + "tftpboot $loadaddr $image && " \ + "setexpr blkcnt $filesize + 0x1ff && " \ + "setexpr blkcnt $blkcnt / 0x200 && " \ + "mmc dev $dev && " \ + "mmc write $loadaddr 0x42 $blkcnt\0" \ + "boot_net=" \ + "tftpboot $kernel_addr_r $image && " \ + "booti $kernel_addr_r - $fdtcontroladdr\0" \ + "update_rootfs=" \ + "tftpboot $loadaddr $image && " \ + "gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \ + "update_all=" \ + "tftpboot $loadaddr $image && " \ + "gzwrite mmc $dev $loadaddr $filesize\0" \ + "erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0" + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +/* SDRAM configuration */ +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */ +#define CONFIG_SYS_BOOTM_LEN SZ_256M + +/* UART */ +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE SZ_2K +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* USDHC */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* I2C */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* FEC */ +#define CONFIG_ETHPRIME "eth0" +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC +#define IMX_FEC_BASE 0x30BE0000 + +#endif diff --git a/roms/u-boot/include/configs/imx8mn_beacon.h b/roms/u-boot/include/configs/imx8mn_beacon.h new file mode 100644 index 000000000..9ce60fd51 --- /dev/null +++ b/roms/u-boot/include/configs/imx8mn_beacon.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +#ifndef __IMX8MN_BEACON_H +#define __IMX8MN_BEACON_H + +#include +#include + +#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_BSS_START_ADDR 0x0095e000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x184000 + +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_REMAKE_ELF + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "ramdiskimage=rootfs.cpio.uboot\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr=0x43000000\0" \ + "ramdisk_addr=0x44000000\0" \ + "boot_fdt=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} " \ + " root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \ + "ramargs=setenv bootargs console=${console} root=/dev/ram rw " \ + " ${optargs}\0" \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadramdisk=load mmc ${mmcdev} ${ramdisk_addr} ${ramdiskimage}\0"\ + "mmcboot=echo Booting from mmc ...; " \ + "run finduuid; run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" \ + "ramboot=echo Booting from RAMdisk...; "\ + "run loadimage; run loadfdt; fdt addr $fdt_addr; "\ + "run loadramdisk; run ramargs; " \ + "booti ${loadaddr} ${ramdisk_addr} ${fdt_addr} ${optargs}\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR) +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +#else +#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ +#endif + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* USDHC */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* ENET Config */ +#if defined(CONFIG_FEC_MXC) +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC +#define IMX_FEC_BASE 0x30BE0000 +#endif /* CONFIG_FEC_MXC */ + +#endif diff --git a/roms/u-boot/include/configs/imx8mn_evk.h b/roms/u-boot/include/configs/imx8mn_evk.h new file mode 100644 index 000000000..985bec803 --- /dev/null +++ b/roms/u-boot/include/configs/imx8mn_evk.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8MN_EVK_H +#define __IMX8MN_EVK_H + +#include +#include +#include + +#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) + +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x980000 +#define CONFIG_SPL_BSS_START_ADDR 0x950000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(DHCP, dhcp, na) + +#include +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "image=Image\0" \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "boot_fit=no\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* USDHC */ +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_SYS_I2C_SPEED 100000 + +#endif diff --git a/roms/u-boot/include/configs/imx8mp_evk.h b/roms/u-boot/include/configs/imx8mp_evk.h new file mode 100644 index 000000000..d1bc09e82 --- /dev/null +++ b/roms/u-boot/include/configs/imx8mp_evk.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __IMX8MP_EVK_H +#define __IMX8MP_EVK_H + +#include +#include +#include + +#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) + +#define CONFIG_SPL_MAX_SIZE (152 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x960000 +#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 +#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PCA9450 + +#define CONFIG_SYS_I2C + +#endif + +#if defined(CONFIG_CMD_NET) +#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */ + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 1 +#define FEC_QUIRK_ENET_MAC + +#define DWC_NET_PHYADDR 1 +#ifdef CONFIG_DWC_ETH_QOS +#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */ +#endif + +#define PHY_ANEG_TIMEOUT 20000 + +#endif + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) + +#include +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "image=Image\0" \ + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "boot_fdt=try\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +/* Totally 6GB DDR */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */ + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_SYS_I2C_SPEED 100000 + +#endif diff --git a/roms/u-boot/include/configs/imx8mq_cm.h b/roms/u-boot/include/configs/imx8mq_cm.h new file mode 100644 index 000000000..9db3bd5f5 --- /dev/null +++ b/roms/u-boot/include/configs/imx8mq_cm.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8M_CM_H +#define __IMX8M_CM_H + +#include +#include +#include + +#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) + +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x182000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +#define CONFIG_REMAKE_ELF + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_ETHPRIME "FEC" +#endif + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(DHCP, dhcp, na) + +#include +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "scriptaddr=0x43500000\0" \ + "kernel_addr_r=0x40880000\0" \ + "image=Image\0" \ + "console=ttymxc0,115200\0" \ + "fdt_addr=0x43000000\0" \ + "boot_fdt=try\0" \ + "fdt_file=imx8mq-cm.dtb\0" \ + "initrd_addr=0x43800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */ + +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#endif diff --git a/roms/u-boot/include/configs/imx8mq_evk.h b/roms/u-boot/include/configs/imx8mq_evk.h new file mode 100644 index 000000000..1861ebad1 --- /dev/null +++ b/roms/u-boot/include/configs/imx8mq_evk.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8M_EVK_H +#define __IMX8M_EVK_H + +#include +#include +#include + +#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) + +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x182000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif + +#define CONFIG_REMAKE_ELF + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE +#define IMX_FEC_BASE 0x30BE0000 +#endif + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(DHCP, dhcp, na) + +#include +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "scriptaddr=0x43500000\0" \ + "kernel_addr_r=0x40880000\0" \ + "image=Image\0" \ + "console=ttymxc0,115200\0" \ + "fdt_addr=0x43000000\0" \ + "boot_fdt=try\0" \ + "fdt_file=imx8mq-evk.dtb\0" \ + "initrd_addr=0x43800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ + +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR + +/* Monitor Command Prompt */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "u-boot=> " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MXC_GPIO + +/* I2C Configs */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_OF_SYSTEM_SETUP + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DM_PMIC +#endif + +#endif diff --git a/roms/u-boot/include/configs/imx8mq_phanbell.h b/roms/u-boot/include/configs/imx8mq_phanbell.h new file mode 100644 index 000000000..66c2c3a8d --- /dev/null +++ b/roms/u-boot/include/configs/imx8mq_phanbell.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __IMX8M_PHANBELL_H +#define __IMX8M_PHANBELL_H + +#include +#include + +#define CONFIG_SPL_MAX_SIZE (172 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x182000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#endif + +#define CONFIG_REMAKE_ELF + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE +#define IMX_FEC_BASE 0x30BE0000 + +#define CONFIG_PHYLIB +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffff\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc0,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=imx8mq-phanbell.dtb\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MXC_GPIO + +/* I2C Configs */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_OF_SYSTEM_SETUP + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DM_PMIC +#endif + +#endif diff --git a/roms/u-boot/include/configs/imx8qm_mek.h b/roms/u-boot/include/configs/imx8qm_mek.h new file mode 100644 index 000000000..99e73a944 --- /dev/null +++ b/roms/u-boot/include/configs/imx8qm_mek.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8QM_MEK_H +#define __IMX8QM_MEK_H + +#include +#include +#include + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_MALLOC_F_ADDR 0x00120000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#define CONFIG_OF_EMBED +#endif + +#define CONFIG_REMAKE_ELF + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + AHAB_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=undefined\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;" \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Default environment is in SD */ + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* Networking */ +#define CONFIG_FEC_XCV_TYPE RGMII + +#endif /* __IMX8QM_MEK_H */ diff --git a/roms/u-boot/include/configs/imx8qm_rom7720.h b/roms/u-boot/include/configs/imx8qm_rom7720.h new file mode 100644 index 000000000..fcbf8eeb3 --- /dev/null +++ b/roms/u-boot/include/configs/imx8qm_rom7720.h @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + */ + +#ifndef __IMX8QM_ROM7720_H +#define __IMX8QM_ROM7720_H + +#include +#include +#include +#define CONFIG_REMAKE_ELF + +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ + +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define USDHC3_BASE_ADDR 0x5B030000 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +/* FUSE command */ + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "m4_1_image=m4_1.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + MFG_NAND_PARTITION \ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "fdt_file=imx8qm-rom7720-a1.dtb\0" \ + "initrd_addr=0x83800000\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Default environment is in SD */ + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board, + * USDHC3 is for SD on base board On DDR4 board, USDHC1 is mux for NAND, + * USDHC2 is for SD, USDHC3 is for SD on base board + */ +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +/* LPDDR4 board total DDR is 6GB, DDR4 board total DDR is 4 GB */ +#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* Networking */ +#define CONFIG_FEC_XCV_TYPE RGMII + +#include +#endif /* __IMX8QM_ROM7720_H */ diff --git a/roms/u-boot/include/configs/imx8qxp_mek.h b/roms/u-boot/include/configs/imx8qxp_mek.h new file mode 100644 index 000000000..a7d623a9b --- /dev/null +++ b/roms/u-boot/include/configs/imx8qxp_mek.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8QXP_MEK_H +#define __IMX8QXP_MEK_H + +#include +#include +#include + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_MALLOC_F_ADDR 0x00120000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#define CONFIG_OF_EMBED +#endif + +#define CONFIG_REMAKE_ELF + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + AHAB_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=undefined\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;" \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Default environment is in SD */ + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +/* LPDDR4 board total DDR is 3GB */ +#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#ifndef CONFIG_DM_PCA953X +#define CONFIG_PCA953X +#endif + +/* Networking */ +#define CONFIG_FEC_XCV_TYPE RGMII + +/* Misc configuration */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#endif /* __IMX8QXP_MEK_H */ diff --git a/roms/u-boot/include/configs/imxrt1020-evk.h b/roms/u-boot/include/configs/imxrt1020-evk.h new file mode 100644 index 000000000..4fb44774b --- /dev/null +++ b/roms/u-boot/include/configs/imxrt1020-evk.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 + * Author(s): Giulio Benetti + */ + +#ifndef __IMXRT1020_EVK_H +#define __IMXRT1020_EVK_H + +#include + +#define CONFIG_SYS_INIT_SP_ADDR 0x20240000 + +#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SYS_LOAD_ADDR 0x20209000 +#else +#define CONFIG_SYS_LOAD_ADDR 0x80000000 +#define CONFIG_LOADADDR 0x80000000 +#endif + +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 + +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE (32 * 1024 * 1024) + +#define DMAMEM_SZ_ALL (1 * 1024 * 1024) +#define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \ + DMAMEM_SZ_ALL) + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + +/* For SPL */ +#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_SPL_LEN 0x00008000 +#define CONFIG_SYS_UBOOT_START 0x800023FD +#endif +/* For SPL ends */ + +#endif /* __IMXRT1020_EVK_H */ diff --git a/roms/u-boot/include/configs/imxrt1050-evk.h b/roms/u-boot/include/configs/imxrt1050-evk.h new file mode 100644 index 000000000..c8d661fb3 --- /dev/null +++ b/roms/u-boot/include/configs/imxrt1050-evk.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#ifndef __IMXRT1050_EVK_H +#define __IMXRT1050_EVK_H + +#include + +#define CONFIG_SYS_INIT_SP_ADDR 0x20280000 + +#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SYS_LOAD_ADDR 0x20209000 +#else +#define CONFIG_SYS_LOAD_ADDR 0x80000000 +#define CONFIG_LOADADDR 0x80000000 +#endif + +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 + +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE (32 * 1024 * 1024) + +#define DMAMEM_SZ_ALL (1 * 1024 * 1024) +#define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \ + DMAMEM_SZ_ALL) + +#ifdef CONFIG_DM_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" +#endif + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + +/* For SPL */ +#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_SPL_LEN 0x00008000 +#define CONFIG_SYS_UBOOT_START 0x800023FD +#endif +/* For SPL ends */ + +#endif /* __IMXRT1050_EVK_H */ diff --git a/roms/u-boot/include/configs/integrator-common.h b/roms/u-boot/include/configs/integrator-common.h new file mode 100644 index 000000000..89ab0da50 --- /dev/null +++ b/roms/u-boot/include/configs/integrator-common.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Linaro + * Linus Walleij + * Common ARM Integrator configuration settings + */ + +#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ +#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS + +/* + * There are various dependencies on the core module (CM) fitted + * Users should refer to their CM user guide + */ +#include "armcoremodule.h" + +/* + * Initialize and remap the core module, use SPD to detect memory size + * If CONFIG_SKIP_LOWLEVEL_INIT is not defined & + * the core module has a CM_INIT register + * then the U-Boot initialisation code will + * e.g. ARM Boot Monitor or pre-loader is repeated once + * (to re-initialise any existing CM_INIT settings to safe values). + * + * This is usually not the desired behaviour since the platform + * will either reboot into the ARM monitor (or pre-loader) + * or continuously cycle thru it without U-Boot running, + * depending upon the setting of Integrator/CP switch S2-4. + * + * However it may be needed if Integrator/CP switch S2-1 + * is set OFF to boot direct into U-Boot. + * In that case comment out the line below. + */ +#define CONFIG_CM_INIT +#define CONFIG_CM_REMAP +#define CONFIG_CM_SPD_DETECT + +/* + * The ARM boot monitor initializes the board. + * However, the default U-Boot code also performs the initialization. + * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT + * - see documentation supplied with board for details of how to choose the + * image to run at reset/power up + * e.g. whether the ARM Boot Monitor runs before U-Boot + */ +/* #define CONFIG_SKIP_LOWLEVEL_INIT */ + +/* + * The ARM boot monitor does not relocate U-Boot. + * However, the default U-Boot code performs the relocation check, + * and may relocate the code if the memory map is changed. + * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT + */ +/* #define SKIP_CONFIG_RELOCATE_UBOOT */ + +/* + * Physical Memory Map + */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET + +/* + * FLASH and environment organization + * Top varies according to amount fitted + * Reserve top 4 blocks of flash + * - ARM Boot Monitor + * - Unused + * - SIB block + * - U-Boot environment + */ +#define CONFIG_SYS_FLASH_BASE 0x24000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* Timeout values in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ diff --git a/roms/u-boot/include/configs/integratorap.h b/roms/u-boot/include/configs/integratorap.h new file mode 100644 index 000000000..2f8ac20a7 --- /dev/null +++ b/roms/u-boot/include/configs/integratorap.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2003 + * Texas Instruments. + * Kshitij Gupta + * Configuation settings for the TI OMAP Innovator board. + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * Configuration for Integrator AP board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "integrator-common.h" + +/* Integrator/AP-specific configuration */ +#define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#define CONFIG_BOOTCOMMAND "" + +/* Flash settings */ +#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +/*----------------------------------------------------------------------- + * PCI definitions + */ + +#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ + +/*----------------------------------------------------------------------- + * There are various dependencies on the core module (CM) fitted + * Users should refer to their CM user guide + * - when porting adjust u-boot/Makefile accordingly + * to define the necessary CONFIG_ s for the CM involved + * see e.g. integratorcp_CM926EJ-S_config + */ +#include "armcoremodule.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/integratorcp.h b/roms/u-boot/include/configs/integratorcp.h new file mode 100644 index 000000000..c4203ce57 --- /dev/null +++ b/roms/u-boot/include/configs/integratorcp.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2003 + * Texas Instruments. + * Kshitij Gupta + * Configuation settings for the TI OMAP Innovator board. + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * Configuration for Compact Integrator board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "integrator-common.h" + +/* Integrator CP-specific configuration */ +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ + +/* + * Hardware drivers + */ +#define CONFIG_SMC91111 +#define CONFIG_SMC_USE_32_BIT +#define CONFIG_SMC91111_BASE 0xC8000000 +#undef CONFIG_SMC91111_EXT_PHY + +#define CONFIG_BOOTCOMMAND "tftpboot ; bootm" +#define CONFIG_SERVERIP 192.168.1.100 +#define CONFIG_IPADDR 192.168.1.104 +#define CONFIG_BOOTFILE "uImage" + +/* + * Miscellaneous configurable options + */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ +#define CONFIG_SYS_MAX_FLASH_SECT 64 +#define CONFIG_SYS_MONITOR_LEN 0x00100000 + +/* + * Move up the U-Boot & monitor area if more flash is fitted. + * If this U-Boot is to be run on Integrators with varying flash sizes, + * drivers/mtd/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG + * register and dynamically assign CONFIG_ENV_ADDR & CONFIG_SYS_MONITOR_BASE + * - CONFIG_SYS_MONITOR_BASE is set to indicate that the environment is not + * embedded in the boot monitor(s) area + */ +#if ( PHYS_FLASH_SIZE == 0x04000000 ) + +#define CONFIG_SYS_MONITOR_BASE 0x27F40000 + +#elif (PHYS_FLASH_SIZE == 0x02000000 ) + +#define CONFIG_SYS_MONITOR_BASE 0x25F40000 + +#else + +#define CONFIG_SYS_MONITOR_BASE 0x27F40000 + +#endif + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/iot_devkit.h b/roms/u-boot/include/configs/iot_devkit.h new file mode 100644 index 000000000..1ba69d9a5 --- /dev/null +++ b/roms/u-boot/include/configs/iot_devkit.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Synopsys, Inc. All rights reserved. + */ + +#ifndef _CONFIG_IOT_DEVKIT_H_ +#define _CONFIG_IOT_DEVKIT_H_ + +#include + +/* + * MEMORY MAP + * + * eFlash: 0x0000_0000 - 0x0008_0000 (512K) + * ICCM: 0x2000_0000 - 0x2004_0000 (256K) + * SRAM: 0x3000_0000 - 0x3002_0000 (128K) + * DCCM: 0x8000_0000 - 0x8002_0000 (128K) + * Note: only data goes here, as IFQ cannot fetch instructions from DCCM + * + * + * RAM PARTITIONING + * + * +-----------+----------+---------------------+-------------+ + * | <-- Stack | .data | Malloc | Environment | + * +-----------+----------+---------------------+-------------+ + * : : : :\___________/ + * : : : : | + * : : : : CONFIG_ENV_SIZE + * : : \____________________/ + * : : | + * : : CONFIG_SYS_MALLOC_LEN + * : : + * : Specified explicitly by CONFIG_SYS_INIT_SP_ADDR + * : + * Specified explicitly by CONFIG_SYS_SDRAM_BASE + * + * NOTES: + * - Stack starts from CONFIG_SYS_INIT_SP_ADDR and grows down, + * i.e. towards CONFIG_SYS_SDRAM_BASE but nothing stops it from crossing + * that CONFIG_SYS_SDRAM_BASE in which case data won't be really saved on + * stack any longer and values popped from stack will contain garbage + * leading to unexpected behavior, typically but not limited to: + * - "Returning" back to bogus caller function + * - Reading data from weird addresses + */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define SRAM_BASE 0x30000000 +#define SRAM_SIZE SZ_128K + +#define DCCM_BASE 0x80000000 +#define DCCM_SIZE SZ_128K + +#define CONFIG_SYS_SDRAM_BASE DCCM_BASE +#define CONFIG_SYS_SDRAM_SIZE DCCM_SIZE + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) + +#define CONFIG_SYS_MALLOC_LEN SZ_64K +#define CONFIG_SYS_BOOTM_LEN SZ_128K +#define CONFIG_SYS_LOAD_ADDR SRAM_BASE + +#define ROM_BASE CONFIG_SYS_MONITOR_BASE +#define ROM_SIZE SZ_256K + +#define RAM_DATA_BASE CONFIG_SYS_INIT_SP_ADDR +#define RAM_DATA_SIZE CONFIG_SYS_SDRAM_SIZE - \ + (CONFIG_SYS_INIT_SP_ADDR - \ + CONFIG_SYS_SDRAM_BASE) - \ + CONFIG_SYS_MALLOC_LEN - \ + CONFIG_ENV_SIZE + +/* + * Environment + */ +#define CONFIG_BOOTFILE "app.bin" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +#endif /* _CONFIG_IOT_DEVKIT_H_ */ diff --git a/roms/u-boot/include/configs/j721e_evm.h b/roms/u-boot/include/configs/j721e_evm.h new file mode 100644 index 000000000..b707fc4e8 --- /dev/null +++ b/roms/u-boot/include/configs/j721e_evm.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for K3 J721E EVM + * + * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Lokesh Vutla + */ + +#ifndef __CONFIG_J721E_EVM_H +#define __CONFIG_J721E_EVM_H + +#include +#include +#include +#include +#include +#include + +/* DDR Configuration */ +#define CONFIG_SYS_SDRAM_BASE1 0x880000000 + +/* SPL Loader Configuration */ +#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ + CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) +#define CONFIG_SYS_UBOOT_BASE 0x50280000 +/* Image load address in RAM for DFU boot*/ +#else +#define CONFIG_SYS_UBOOT_BASE 0x50080000 +/* + * Maximum size in memory allocated to the SPL BSS. Keep it as tight as + * possible (to allow the build to go through), as this directly affects + * our memory footprint. The less we use for BSS the more we have available + * for everything else. + */ +#define CONFIG_SPL_BSS_MAX_SIZE 0xA000 +/* + * Link BSS to be within SPL in a dedicated region located near the top of + * the MCU SRAM, this way making it available also before relocation. Note + * that we are not using the actual top of the MCU SRAM as there is a memory + * location filled in by the boot ROM that we want to read out without any + * interference from the C context. + */ +#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ + CONFIG_SPL_BSS_MAX_SIZE) +/* Set the stack right below the SPL BSS section */ +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR +/* Configure R5 SPL post-relocation malloc pool in DDR */ +#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M +/* Image load address in RAM for DFU boot*/ +#endif + +#ifdef CONFIG_SYS_K3_SPL_ATF +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" +#endif + +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE + +#define CONFIG_SYS_BOOTM_LEN SZ_64M +#define CONFIG_CQSPI_REF_CLK 133333333 + +/* HyperFlash related configuration */ +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 + +/* U-Boot general configuration */ +#define EXTRA_ENV_J721E_BOARD_SETTINGS \ + "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "findfdt=" \ + "setenv name_fdt ${default_device_tree};" \ + "setenv fdtfile ${name_fdt}\0" \ + "name_kern=Image\0" \ + "console=ttyS2,115200n8\0" \ + "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 " \ + "${mtdparts}\0" \ + "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" + +#define PARTS_DEFAULT \ + /* Linux partitions */ \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" + +#ifdef CONFIG_SYS_K3_SPL_ATF +#if defined(CONFIG_TARGET_J721E_R5_EVM) +#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \ + "addr_mainr5f0_0load=0x88000000\0" \ + "name_mainr5f0_0fw=/lib/firmware/j7-main-r5f0_0-fw\0" \ + "addr_mcur5f0_0load=0x89000000\0" \ + "name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0" +#elif defined(CONFIG_TARGET_J7200_R5_EVM) +#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \ + "addr_mcur5f0_0load=0x89000000\0" \ + "name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw\0" +#endif /* CONFIG_TARGET_J721E_R5_EVM */ +#else +#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC "" +#endif /* CONFIG_SYS_K3_SPL_ATF */ + +/* U-Boot MMC-specific configuration */ +#define EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \ + "boot=mmc\0" \ + "mmcdev=1\0" \ + "bootpart=1:2\0" \ + "bootdir=/boot\0" \ + EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \ + "rd_spec=-\0" \ + "init_mmc=run args_all args_mmc\0" \ + "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \ + "get_overlay_mmc=" \ + "fdt address ${fdtaddr};" \ + "fdt resize 0x100000;" \ + "for overlay in $name_overlays;" \ + "do;" \ + "load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \ + "fdt apply ${dtboaddr};" \ + "done;\0" \ + "partitions=" PARTS_DEFAULT \ + "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ + "${bootdir}/${name_kern}\0" \ + "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \ + "${bootdir}/${name_fit}\0" \ + "partitions=" PARTS_DEFAULT + +/* Set the default list of remote processors to boot */ +#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) +#ifdef DEFAULT_RPROCS +#undef DEFAULT_RPROCS +#endif +#endif + +#ifdef CONFIG_TARGET_J721E_A72_EVM +#define DEFAULT_RPROCS "" \ + "3 /lib/firmware/j7-main-r5f0_1-fw " \ + "4 /lib/firmware/j7-main-r5f1_0-fw " \ + "5 /lib/firmware/j7-main-r5f1_1-fw " \ + "6 /lib/firmware/j7-c66_0-fw " \ + "7 /lib/firmware/j7-c66_1-fw " \ + "8 /lib/firmware/j7-c71_0-fw " +#endif /* CONFIG_TARGET_J721E_A72_EVM */ + +#ifdef CONFIG_TARGET_J7200_A72_EVM +#define DEFAULT_RPROCS "" \ + "2 /lib/firmware/j7200-main-r5f0_0-fw " \ + "3 /lib/firmware/j7200-main-r5f0_1-fw " +#endif /* CONFIG_TARGET_J7200_A72_EVM */ + +/* set default dfu_bufsiz to 128KB (sector size of OSPI) */ +#define EXTRA_ENV_DFUARGS \ + "dfu_bufsiz=0x20000\0" \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_EMMC \ + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_OSPI + +#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) +#define EXTRA_ENV_J721E_BOARD_SETTINGS_MTD \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" +#else +#define EXTRA_ENV_J721E_BOARD_SETTINGS_MTD +#endif + +/* Incorporate settings into the U-Boot environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + DEFAULT_FIT_TI_ARGS \ + EXTRA_ENV_J721E_BOARD_SETTINGS \ + EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \ + EXTRA_ENV_RPROC_SETTINGS \ + EXTRA_ENV_DFUARGS \ + DEFAULT_UFS_TI_ARGS \ + EXTRA_ENV_J721E_BOARD_SETTINGS_MTD + +/* Now for the remaining common defines */ +#include + +/* MMC ENV related defines */ + +#endif /* __CONFIG_J721E_EVM_H */ diff --git a/roms/u-boot/include/configs/jetson-tk1.h b/roms/u-boot/include/configs/jetson-tk1.h new file mode 100644 index 000000000..a3c385b6e --- /dev/null +++ b/roms/u-boot/include/configs/jetson-tk1.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2013-2014 + * NVIDIA Corporation + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra124-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTD +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +/* Environment in eMMC, at the end of 2nd "boot sector" */ + +/* SPI */ +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +/* Reserve top 1M for secure RAM */ +#define CONFIG_ARMV7_SECURE_BASE 0xfff00000 +#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/k2e_evm.h b/roms/u-boot/include/configs/k2e_evm.h new file mode 100644 index 000000000..716ae3b0d --- /dev/null +++ b/roms/u-boot/include/configs/k2e_evm.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for TI's k2e-evm + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + */ + +#ifndef __CONFIG_K2E_EVM_H +#define __CONFIG_K2E_EVM_H + +#include + +/* Platform type */ +#define CONFIG_SOC_K2E + +#ifdef CONFIG_TI_SECURE_DEVICE +#define DEFAULT_SEC_BOOT_ENV \ + DEFAULT_FIT_TI_ARGS \ + "findfdt=setenv fdtfile ${name_fdt}\0" +#else +#define DEFAULT_SEC_BOOT_ENV +#endif + +/* U-Boot general configuration */ +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + DEFAULT_FW_INITRAMFS_BOOT_ENV \ + DEFAULT_SEC_BOOT_ENV \ + "boot=ubi\0" \ + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ + "name_fdt=keystone-k2e-evm.dtb\0" \ + "name_mon=skern-k2e.bin\0" \ + "name_ubi=k2e-evm-ubifs.ubi\0" \ + "name_uboot=u-boot-spi-k2e-evm.gph\0" \ + "name_fs=arago-console-image-k2e-evm.cpio.gz\0" + +#include + +#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS + +/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_2K + +/* Network */ +#define CONFIG_KSNET_NETCP_V1_5 +#define CONFIG_KSNET_CPSW_NUM_PORTS 9 +#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE + +#define CONFIG_DDR_SPD + +#endif /* __CONFIG_K2E_EVM_H */ diff --git a/roms/u-boot/include/configs/k2g_evm.h b/roms/u-boot/include/configs/k2g_evm.h new file mode 100644 index 000000000..4471eb4f6 --- /dev/null +++ b/roms/u-boot/include/configs/k2g_evm.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for TI's k2g-evm + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, + */ + +#ifndef __CONFIG_K2G_EVM_H +#define __CONFIG_K2G_EVM_H + +#include +#include + +/* Platform type */ +#define CONFIG_SOC_K2G + +/* U-Boot general configuration */ +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + DEFAULT_MMC_TI_ARGS \ + DEFAULT_PMMC_BOOT_ENV \ + DEFAULT_FW_INITRAMFS_BOOT_ENV \ + DEFAULT_FIT_TI_ARGS \ + "boot=mmc\0" \ + "console=ttyS0,115200n8\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "rd_spec=-\0" \ + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ + "findfdt="\ + "if test $board_name = 66AK2GGP; then " \ + "setenv name_fdt keystone-k2g-evm.dtb; " \ + "else if test $board_name = 66AK2GG1; then " \ + "setenv name_fdt keystone-k2g-evm.dtb; " \ + "else if test $board_name = 66AK2GIC; then " \ + "setenv name_fdt keystone-k2g-ice.dtb; " \ + "else if test $board_name = 66AK2GI1; then " \ + "setenv name_fdt keystone-k2g-ice.dtb; " \ + "else if test $name_fdt = undefined; then " \ + "echo WARNING: Could not determine device tree to use;"\ + "fi;fi;fi;fi; setenv fdtfile ${name_fdt}\0" \ + "name_mon=skern-k2g.bin\0" \ + "name_ubi=k2g-evm-ubifs.ubi\0" \ + "name_uboot=u-boot-spi-k2g-evm.gph\0" \ + "init_mmc=run args_all args_mmc\0" \ + "init_fw_rd_mmc=load mmc ${bootpart} ${rdaddr} " \ + "${bootdir}/${name_fw_rd}; run set_rd_spec\0" \ + "soc_variant=k2g\0" \ + "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0"\ + "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ + "${bootdir}/${name_kern}\0" \ + "get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\ + "name_fs=arago-base-tisdk-image-k2g-evm.cpio\0" + +#ifndef CONFIG_TI_SECURE_DEVICE +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run envboot; " \ + "run init_${boot}; " \ + "run get_mon_${boot} run_mon; " \ + "run set_name_pmmc get_pmmc_${boot} run_pmmc; " \ + "run get_kern_${boot}; " \ + "run init_fw_rd_${boot}; " \ + "run get_fdt_${boot}; " \ + "run run_kern" +#else +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run envboot; " \ + "run run_mon_hs; " \ + "run init_${boot}; " \ + "run get_fit_${boot}; " \ + "bootm ${addr_fit}#${name_fdt}" +#endif + +/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_2K + +/* Network */ +#define CONFIG_KSNET_NETCP_V1_5 +#define CONFIG_KSNET_CPSW_NUM_PORTS 2 +#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE +#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CQSPI_REF_CLK 384000000 +#endif + +#define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS + +#include + +#endif /* __CONFIG_K2G_EVM_H */ diff --git a/roms/u-boot/include/configs/k2hk_evm.h b/roms/u-boot/include/configs/k2hk_evm.h new file mode 100644 index 000000000..d90b26481 --- /dev/null +++ b/roms/u-boot/include/configs/k2hk_evm.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for TI's k2hk-evm + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + */ + +#ifndef __CONFIG_K2HK_EVM_H +#define __CONFIG_K2HK_EVM_H + +#include + +/* Platform type */ +#define CONFIG_SOC_K2HK + +#ifdef CONFIG_TI_SECURE_DEVICE +#define DEFAULT_SEC_BOOT_ENV \ + DEFAULT_FIT_TI_ARGS \ + "findfdt=setenv fdtfile ${name_fdt}\0" +#else +#define DEFAULT_SEC_BOOT_ENV +#endif + +/* U-Boot general configuration */ +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + DEFAULT_FW_INITRAMFS_BOOT_ENV \ + DEFAULT_SEC_BOOT_ENV \ + "boot=ubi\0" \ + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ + "name_fdt=keystone-k2hk-evm.dtb\0" \ + "name_mon=skern-k2hk.bin\0" \ + "name_ubi=k2hk-evm-ubifs.ubi\0" \ + "name_uboot=u-boot-spi-k2hk-evm.gph\0" \ + "name_fs=arago-console-image-k2hk-evm.cpio.gz\0" + +#include + +#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS + +/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_2K + +/* Network */ +#define CONFIG_KSNET_NETCP_V1_0 +#define CONFIG_KSNET_CPSW_NUM_PORTS 5 + +#define CONFIG_DDR_SPD + +#endif /* __CONFIG_K2HK_EVM_H */ diff --git a/roms/u-boot/include/configs/k2l_evm.h b/roms/u-boot/include/configs/k2l_evm.h new file mode 100644 index 000000000..152cea01b --- /dev/null +++ b/roms/u-boot/include/configs/k2l_evm.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for TI's k2l-evm + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + */ + +#ifndef __CONFIG_K2L_EVM_H +#define __CONFIG_K2L_EVM_H + +#include + +/* Platform type */ +#define CONFIG_SOC_K2L + +#ifdef CONFIG_TI_SECURE_DEVICE +#define DEFAULT_SEC_BOOT_ENV \ + DEFAULT_FIT_TI_ARGS \ + "findfdt=setenv fdtfile ${name_fdt}\0" +#else +#define DEFAULT_SEC_BOOT_ENV +#endif + +/* U-Boot general configuration */ +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + DEFAULT_FW_INITRAMFS_BOOT_ENV \ + DEFAULT_SEC_BOOT_ENV \ + "boot=ubi\0" \ + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096\0" \ + "name_fdt=keystone-k2l-evm.dtb\0" \ + "name_mon=skern-k2l.bin\0" \ + "name_ubi=k2l-evm-ubifs.ubi\0" \ + "name_uboot=u-boot-spi-k2l-evm.gph\0" \ + "name_fs=arago-console-image-k2l-evm.cpio.gz\0" + +#include + +#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS + +/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_4K + +/* Network */ +#define CONFIG_KSNET_NETCP_V1_5 +#define CONFIG_KSNET_CPSW_NUM_PORTS 5 +#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE + +#endif /* __CONFIG_K2L_EVM_H */ diff --git a/roms/u-boot/include/configs/km/keymile-common.h b/roms/u-boot/include/configs/km/keymile-common.h new file mode 100644 index 000000000..d321ebdb6 --- /dev/null +++ b/roms/u-boot/include/configs/km/keymile-common.h @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2008-2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + */ + +#ifndef __CONFIG_KEYMILE_H +#define __CONFIG_KEYMILE_H + +#include + +/* + * Miscellaneous configurable options + */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_HUSH_INIT_VAR + +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CONFIG_LOADS_ECHO +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS +#define CONFIG_KM_DEF_ENV_BOOTPARAMS \ + "actual_bank=0\0" +#endif + +#ifndef CONFIG_KM_UBI_PARTITION_NAME_BOOT +#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" +#endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */ + +#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS +#define CONFIG_KM_UBI_PART_BOOT_OPTS "" +#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */ + +#ifndef CONFIG_KM_UBI_PARTITION_NAME_APP +/* one flash chip only called boot */ +/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ +# define CONFIG_KM_UBI_LINUX_MTD \ + "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ + CONFIG_KM_UBI_PART_BOOT_OPTS +# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ + "ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0" +#else /* CONFIG_KM_UBI_PARTITION_NAME_APP */ +/* two flash chips called boot and app */ +/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ +/* app: CONFIG_KM_UBI_PARTITION_NAME_APP */ +# define CONFIG_KM_UBI_LINUX_MTD \ + "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ + CONFIG_KM_UBI_PART_BOOT_OPTS " " \ + "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP +# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ + "ubiattach=if test ${boot_bank} -eq 0; then; " \ + "ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "; else; " \ + "ubi part " CONFIG_KM_UBI_PARTITION_NAME_APP "; fi\0" +#endif /* CONFIG_KM_UBI_PARTITION_NAME_APP */ + +#ifdef CONFIG_NAND_ECC_BCH +#define CONFIG_KM_UIMAGE_NAME "ecc_bch_uImage\0" +#define CONFIG_KM_ECC_MODE " eccmode=bch" +#else +#define CONFIG_KM_UIMAGE_NAME "uImage\0" +#define CONFIG_KM_ECC_MODE +#endif + +/* + * boottargets + * - set 'subbootcmds' + * - set 'bootcmd' and 'altbootcmd' + * available targets: + * - 'release': for a standalone system kernel/rootfs from flash + */ +#define CONFIG_KM_DEF_ENV_BOOTTARGETS \ + "subbootcmds=ubiattach ubicopy checkfdt cramfsloadfdt " \ + "set_fdthigh cramfsloadkernel flashargs add_default " \ + "addpanic boot\0" \ + "develop=" \ + "tftp ${load_addr_r} scripts/develop-${arch}.txt && " \ + "env import -t ${load_addr_r} ${filesize} && " \ + "run setup_debug_env\0" \ + "ramfs=" \ + "tftp ${load_addr_r} scripts/ramfs-${arch}.txt && " \ + "env import -t ${load_addr_r} ${filesize} && " \ + "run setup_debug_env\0" \ + "" + +/* + * bootargs + * - modify 'bootargs' + * + * - 'add_default': default bootargs common for all arm/ppc boards + * - 'addpanic': add kernel panic options + * - 'flashargs': defaults arguments for flash base boot + * + */ +#define CONFIG_KM_DEF_ENV_BOOTARGS \ + "add_default=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off:" \ + " console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}" \ + " mem=${kernelmem} init=${init}" \ + CONFIG_KM_ECC_MODE \ + " phram.phram=phvar,${varaddr}," __stringify(CONFIG_KM_PHRAM)\ + " " CONFIG_KM_UBI_LINUX_MTD " " \ + CONFIG_KM_DEF_BOOT_ARGS_CPU \ + "\0" \ + "addpanic=" \ + "setenv bootargs ${bootargs} panic=1 panic_on_oops=1\0" \ + "flashargs=" \ + "setenv bootargs " \ + "root=mtdblock:rootfs${boot_bank} " \ + "rootfstype=squashfs ro\0" \ + "" + +/* + * flash_boot + * - commands for booting from flash + * + * - 'cramfsloadkernel': copy kernel from a cramfs to ram + * - 'ubiattach': attach ubi partition + * - 'ubicopy': copy ubi volume to ram + * - volume names: bootfs0, bootfs1, bootfs2, ... + * + * processor specific settings + * - 'cramfsloadfdt': copy fdt from a cramfs to ram + */ +#define CONFIG_KM_DEF_ENV_FLASH_BOOT \ + "cramfsaddr=" __stringify(CONFIG_KM_CRAMFS_ADDR) "\0" \ + "cramfsloadkernel=cramfsload ${load_addr_r} ${uimage}\0" \ + "ubicopy=ubi read ${cramfsaddr} bootfs${boot_bank}\0" \ + "uimage=" CONFIG_KM_UIMAGE_NAME \ + CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI + +/* + * constants + * - KM specific constants and commands + * + * - 'default': setup default environment + */ +#define CONFIG_KM_DEF_ENV_CONSTANTS \ + "backup_bank=0\0" \ + "release=run newenv; reset\0" \ + "pnvramsize=" __stringify(CONFIG_KM_PNVRAM) "\0" \ + "testbootcmd=setenv boot_bank ${test_bank}; " \ + "run ${subbootcmds}; reset\0" \ + "env_version=1\0" \ + "" + +#ifndef CONFIG_KM_DEF_ENV +#define CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ENV_BOOTPARAMS \ + "netdev=" __stringify(CONFIG_KM_DEF_NETDEV) "\0" \ + CONFIG_KM_DEF_ENV_CPU \ + CONFIG_KM_DEF_ENV_BOOTTARGETS \ + CONFIG_KM_DEF_ENV_BOOTARGS \ + CONFIG_KM_DEF_ENV_FLASH_BOOT \ + CONFIG_KM_DEF_ENV_CONSTANTS \ + "altbootcmd=run bootcmd\0" \ + "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ + "bootcmd=km_checkbidhwk && " \ + "setenv bootcmd \'if km_checktestboot; then; " \ + "setenv boot_bank ${test_bank}; else; " \ + "setenv boot_bank ${actual_bank}; fi;" \ + "run ${subbootcmds}; reset\' && " \ + "setenv altbootcmd \'setenv boot_bank ${backup_bank}; " \ + "run ${subbootcmds}; reset\' && " \ + "saveenv && saveenv && boot\0" \ + "cramfsloadfdt=" \ + "cramfsload ${fdt_addr_r} " \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ + "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ + "init=/sbin/init-overlay.sh\0" \ + "load_addr_r=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ + "load=tftpboot ${load_addr_r} ${u-boot}\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "" +#endif /* CONFIG_KM_DEF_ENV */ + +#endif /* __CONFIG_KEYMILE_H */ diff --git a/roms/u-boot/include/configs/km/km-mpc8309.h b/roms/u-boot/include/configs/km/km-mpc8309.h new file mode 100644 index 000000000..e710c0449 --- /dev/null +++ b/roms/u-boot/include/configs/km/km-mpc8309.h @@ -0,0 +1,137 @@ +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* QE microcode/firmware address */ +/* between the u-boot partition and env */ +#ifndef CONFIG_SYS_QE_FW_ADDR +#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 +#endif + +/* + * System IO Config + */ +/* 0x14000180 SICR_1 */ +#ifndef CONFIG_SYS_SICRL +#define CONFIG_SYS_SICRL (0 \ + | SICR_1_UART1_UART1RTS \ + | SICR_1_I2C_CKSTOP \ + | SICR_1_IRQ_A_IRQ \ + | SICR_1_IRQ_B_IRQ \ + | SICR_1_GPIO_A_GPIO \ + | SICR_1_GPIO_B_GPIO \ + | SICR_1_GPIO_C_GPIO \ + | SICR_1_GPIO_D_GPIO \ + | SICR_1_GPIO_E_GPIO \ + | SICR_1_GPIO_F_GPIO \ + | SICR_1_USB_A_UART2S \ + | SICR_1_USB_B_UART2RTS \ + | SICR_1_FEC1_FEC1 \ + | SICR_1_FEC2_FEC2 \ + ) +#endif + +/* 0x00080400 SICR_2 */ +#define CONFIG_SYS_SICRH (0 \ + | SICR_2_FEC3_FEC3 \ + | SICR_2_HDLC1_A_HDLC1 \ + | SICR_2_ELBC_A_LA \ + | SICR_2_ELBC_B_LCLK \ + | SICR_2_HDLC2_A_HDLC2 \ + | SICR_2_USB_D_GPIO \ + | SICR_2_PCI_PCI \ + | SICR_2_HDLC1_B_HDLC1 \ + | SICR_2_HDLC1_C_HDLC1 \ + | SICR_2_HDLC2_B_GPIO \ + | SICR_2_HDLC2_C_HDLC2 \ + | SICR_2_QUIESCE_B \ + ) + +/* GPR_1 */ +#define CONFIG_SYS_GPR1 0x50008060 + +#define CONFIG_SYS_GP1DIR 0x00000000 +#define CONFIG_SYS_GP1ODR 0x00000000 +#define CONFIG_SYS_GP2DIR 0xFF000000 +#define CONFIG_SYS_GP2ODR 0x00000000 + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_RD_NEVER | \ + CSCONFIG_ODT_WR_ONLY_CURRENT | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* ethernet port connected to piggy (UEC2) */ +#define CONFIG_HAS_ETH1 +#define CONFIG_UEC_ETH2 +#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ +#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 +#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC2_PHY_ADDR 0 +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 diff --git a/roms/u-boot/include/configs/km/km-mpc832x.h b/roms/u-boot/include/configs/km/km-mpc832x.h new file mode 100644 index 000000000..22dfb5da6 --- /dev/null +++ b/roms/u-boot/include/configs/km/km-mpc832x.h @@ -0,0 +1,76 @@ +/* + * High Level Configuration Options + */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + diff --git a/roms/u-boot/include/configs/km/km-mpc8360.h b/roms/u-boot/include/configs/km/km-mpc8360.h new file mode 100644 index 000000000..798b12696 --- /dev/null +++ b/roms/u-boot/include/configs/km/km-mpc8360.h @@ -0,0 +1,76 @@ +/* KMBEC FPGA (PRIO) */ +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 64 + +/* + * High Level Configuration Options + */ + +/* + * System IO Setup + */ +#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) + +/** + * DDR RAM settings + */ +#define CONFIG_SYS_DDR_SDRAM_CFG (\ + SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 + +#define CONFIG_SYS_DDR_CLK_CNTL (\ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CONFIG_SYS_DDR_INTERVAL (\ + (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_Q_DRN) +#define CONFIG_SYS_DDR_MODE 0x47860452 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 (\ + (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 (\ + (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* + * PAXE on the local bus CS3 + */ +#define CONFIG_SYS_PAXE_BASE 0xA0000000 +#define CONFIG_SYS_PAXE_SIZE 256 diff --git a/roms/u-boot/include/configs/km/km-mpc83xx.h b/roms/u-boot/include/configs/km/km-mpc83xx.h new file mode 100644 index 000000000..7aacd37c8 --- /dev/null +++ b/roms/u-boot/include/configs/km/km-mpc83xx.h @@ -0,0 +1,130 @@ +/* + * Internal Definitions + */ +#include +#define BOOTFLASH_START 0xF0000000 + +/* + * DDR Setup + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +/* Address and size of Redundant Environment Sector */ +#endif /* CFG_SYS_RAMBOOT */ + +/* + * Environment Configuration + */ +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off " __stringify(CONFIG_ENV_ADDR) " +0x40000 && " \ + "era " __stringify(CONFIG_ENV_ADDR) " +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" diff --git a/roms/u-boot/include/configs/km/km-powerpc.h b/roms/u-boot/include/configs/km/km-powerpc.h new file mode 100644 index 000000000..3be926c10 --- /dev/null +++ b/roms/u-boot/include/configs/km/km-powerpc.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + */ + +#ifndef __CONFIG_KEYMILE_POWERPC_H +#define __CONFIG_KEYMILE_POWERPC_H + +/* Do boardspecific init for all boards */ + +/* EEprom support 24C08, 24C16, 24C64 */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ + +/* Reserve 4 MB for malloc */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* Increase max size of compressed kernel */ +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ + +/****************************************************************************** + * (PRAM usage) + * ... ------------------------------------------------------- + * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM + * ... |<------------------- pram -------------------------->| + * ... ------------------------------------------------------- + * @END_OF_RAM: + * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose + * @CONFIG_KM_PHRAM: address for /var + * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) + * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM + */ + +/* size of rootfs in RAM */ +#define CONFIG_KM_ROOTFSSIZE 0x0 +/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable + * is not valid yet, which is the case for when u-boot copies itself to RAM */ +#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) + +/* architecture specific default bootargs */ +#define CONFIG_KM_DEF_BOOT_ARGS_CPU "" + +#define CONFIG_KM_DEF_ENV_CPU \ + "u-boot="CONFIG_HOSTNAME "/u-boot.bin\0" \ + "update=" \ + "protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\ + "erase " __stringify(BOOTFLASH_START) " +${filesize} && "\ + "cp.b ${load_addr_r} " __stringify(BOOTFLASH_START) \ + " ${filesize} && " \ + "protect on " __stringify(BOOTFLASH_START) " +${filesize}\0"\ + "set_fdthigh=true\0" \ + "checkfdt=true\0" \ + "bootm_mapsize=" __stringify(CONFIG_SYS_BOOTM_LEN) "\0" \ + "" + +#endif /* __CONFIG_KEYMILE_POWERPC_H */ diff --git a/roms/u-boot/include/configs/km/km_arm.h b/roms/u-boot/include/configs/km/km_arm.h new file mode 100644 index 000000000..4115906c5 --- /dev/null +++ b/roms/u-boot/include/configs/km/km_arm.h @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Prafulla Wadaskar + * + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2010-2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + */ + +/* + * for linking errors see + * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html + */ + +#ifndef _CONFIG_KM_ARM_H +#define _CONFIG_KM_ARM_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KW88F6281 /* SOC Name */ + +#define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD + +#define CONFIG_NAND_ECC_BCH + +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" + +/* Reserve 4 MB for malloc */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* Increase max size of compressed kernel */ +#define CONFIG_SYS_BOOTM_LEN (32 << 20) + +#include "asm/arch/config.h" + +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ + +/* architecture specific default bootargs */ +#define CONFIG_KM_DEF_BOOT_ARGS_CPU \ + "bootcountaddr=${bootcountaddr} ${mtdparts}" \ + " boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}" + +#define CONFIG_KM_DEF_ENV_CPU \ + "u-boot=" CONFIG_HOSTNAME "/u-boot.kwb\0" \ + CONFIG_KM_UPDATE_UBOOT \ + "set_fdthigh=setenv fdt_high ${kernelmem}\0" \ + "checkfdt=" \ + "if cramfsls fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; " \ + "then true; else setenv cramfsloadfdt true; " \ + "setenv boot bootm ${load_addr_r}; " \ + "echo No FDT found, booting with the kernel " \ + "appended one; fi\0" \ + "" + +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ + +/* + * NAND Flash configuration + */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* + * Other required minimal configurations + */ + +/* + * Ethernet Driver configuration + */ +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer autoneg timeout */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 + +/* + * I2C related stuff + */ +#undef CONFIG_I2C_MVTWSI +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ +#define CONFIG_SYS_I2C_INIT_BOARD + +#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */ +#define CONFIG_SYS_NUM_I2C_BUSES 6 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \ + } + +#ifndef __ASSEMBLY__ +#include +#include +#include +extern void __set_direction(unsigned pin, int high); +#define KM_KIRKWOOD_SDA_PIN 8 +#define KM_KIRKWOOD_SCL_PIN 9 +#define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300 +#define KM_KIRKWOOD_ENV_WP 38 + +#define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0) +#define I2C_TRISTATE __set_direction(KM_KIRKWOOD_SDA_PIN, 1) +#define I2C_READ (kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0) +#define I2C_SDA(bit) kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit) +#define I2C_SCL(bit) kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit) +#endif + +#define I2C_DELAY udelay(1) +#define I2C_SOFT_DECLARATIONS + +#define CONFIG_SYS_I2C_SOFT_SLAVE 0x0 +#define CONFIG_SYS_I2C_SOFT_SPEED 100000 + +/* EEprom support 24C128, 24C256 valid for environment eeprom */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* + * Environment variables configurations + */ +#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */ +#else +#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_EEPROM_WREN +#define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */ +#endif + +#define KM_FLASH_GPIO_PIN 16 + +#define CONFIG_KM_UPDATE_UBOOT \ + "update=" \ + "sf probe 0;sf erase 0 +${filesize};" \ + "sf write ${load_addr_r} 0 ${filesize};\0" + +#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_KM_NEW_ENV \ + "newenv=sf probe 0;" \ + "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ + __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" +#else +#define CONFIG_KM_NEW_ENV \ + "newenv=setenv addr 0x100000 && " \ + "i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; " \ + "mw.b ${addr} 0 4 && " \ + "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && " \ + "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0" +#endif + +#ifndef CONFIG_KM_BOARD_EXTRA_ENV +#define CONFIG_KM_BOARD_EXTRA_ENV "" +#endif + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_BOARD_EXTRA_ENV \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_NEW_ENV \ + "arch=arm\0" \ + "" + +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +/* address for the bootcount (taken from end of RAM) */ +#define BOOTCOUNT_ADDR (CONFIG_KM_RESERVED_PRAM) + +/* enable POST tests */ +#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS) +#define CONFIG_POST_SKIP_ENV_FLAGS +#define CONFIG_POST_EXTERNAL_WORD_FUNCS + +#endif /* _CONFIG_KM_ARM_H */ diff --git a/roms/u-boot/include/configs/km/pg-wcom-ls102xa.h b/roms/u-boot/include/configs/km/pg-wcom-ls102xa.h new file mode 100644 index 000000000..eb480a34a --- /dev/null +++ b/roms/u-boot/include/configs/km/pg-wcom-ls102xa.h @@ -0,0 +1,307 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Hitachi Power Grids. All rights reserved. + */ + +#ifndef __CONFIG_PG_WCOM_LS102XA_H +#define __CONFIG_PG_WCOM_LS102XA_H + +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) + +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \ + CONFIG_KM_PHRAM + \ + CONFIG_KM_RESERVED_PRAM) >> 10) + +#define CONFIG_SYS_CLK_FREQ 66666666 +/* + * Take into account default implementation where DDR_FDBK_MULTI is consider as + * configured for DDR_PLL = 2*MEM_PLL_RAT. + * In our case DDR_FDBK_MULTI is 2, means DDR_PLL = MEM_PLL_RAT. + */ +#define CONFIG_DDR_CLK_FREQ (100000000 >> 1) + +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_DDR_SPD + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x54 + +/* POST memory regions test */ +#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS) +#define CONFIG_POST_EXTERNAL_WORD_FUNCS + +/* + * IFC Definitions + */ +/* NOR Flash Definitions */ +#define CONFIG_FSL_IFC +#define CONFIG_SYS_FLASH_BASE 0x60000000 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_TE | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) + +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \ + CSOR_NOR_ADM_SHIFT(0x4) | \ + CSOR_NOR_NOR_MODE_ASYNC_NOR | \ + CSOR_NOR_TRHZ_20 | \ + CSOR_NOR_BCTLD) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ + FTIM0_NOR_TEADC(0x7) | \ + FTIM0_NOR_TAVDS(0x0) | \ + FTIM0_NOR_TEAHC(0x1)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ + FTIM1_NOR_TRAD_NOR(0x21) | \ + FTIM1_NOR_TSEQRAD_NOR(0x21)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ + FTIM2_NOR_TCH(0x1) | \ + FTIM2_NOR_TWPH(0x6) | \ + FTIM2_NOR_TWP(0xb)) +#define CONFIG_SYS_NOR_FTIM3 0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +/* NAND Flash Definitions */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0x68000000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_TE | \ + CSPR_MSEL_NAND | \ + CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \ + | CSOR_NAND_ECC_DEC_EN \ + | CSOR_NAND_ECC_MODE_4 \ + | CSOR_NAND_RAL_3 \ + | CSOR_NAND_PGS_2K \ + | CSOR_NAND_SPRZ_64 \ + | CSOR_NAND_PB(64) \ + | CSOR_NAND_TRHZ_40 \ + | CSOR_NAND_BCTLD) + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ + FTIM0_NAND_TWP(0x8) | \ + FTIM0_NAND_TWCHT(0x3) | \ + FTIM0_NAND_TWH(0x5)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ + FTIM1_NAND_TWBE(0x1e) | \ + FTIM1_NAND_TRR(0x6) | \ + FTIM1_NAND_TRP(0x8)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ + FTIM2_NAND_TREH(0x5) | \ + FTIM2_NAND_TWHRE(0x3c)) +#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* QRIO FPGA Definitions */ +#define CONFIG_SYS_QRIO_BASE 0x70000000 +#define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE + +#define CONFIG_SYS_CSPR2_EXT (0x00) +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_TE | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024) +#define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \ + CSOR_GPCM_TRHZ_20 | \ + CSOR_GPCM_BCTLD) +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ + FTIM0_GPCM_TEADC(0x8) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x6)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x7)) +#define CONFIG_SYS_CS2_FTIM3 0x04000000 + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_NUM_I2C_BUSES 3 +#define I2C_MUX_PCA_ADDR 0x70 +#define I2C_MUX_CH_DEFAULT 0x0 +#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ + {1, {I2C_NULL_HOP} }, \ + } + +/* + * eTSEC + */ +#ifdef CONFIG_TSEC_ENET +#define CONFIG_ETHPRIME "ethernet@2d90000" +#endif + +#define CONFIG_LAYERSCAPE_NS_ACCESS +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define COUNTER_FREQUENCY 8333333 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 256 +#define CONFIG_FSL_DEVICE_DISABLE + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_LS102XA_STREAM_ID + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */ +#define CONFIG_SYS_QE_FW_ADDR 0x60020000 + +#define CONFIG_SYS_BOOTCOUNT_BE + +/* + * Environment + */ + +#define CONFIG_ENV_TOTAL_SIZE 0x40000 +#define ENV_DEL_ADDR CONFIG_ENV_ADDR_REDUND /* direct for newenv */ + +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV +#endif + +#ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU +#define CONFIG_KM_DEF_BOOT_ARGS_CPU "" +#endif + +#define CONFIG_KM_DEF_ENV_CPU \ + "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ + "cramfsloadfdt=" \ + "cramfsload ${fdt_addr_r} " \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ + "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize} && " \ + "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize} && " \ + "cp.b ${load_addr_r} " \ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ + "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize}\0" \ + "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ + " +${filesize} && " \ + "erase " __stringify(CONFIG_SYS_FLASH_BASE) \ + " +${filesize} && " \ + "cp.b ${load_addr_r} " \ + __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \ + "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \ + "set_fdthigh=true\0" \ + "checkfdt=true\0" \ + "" + +#define CONFIG_KM_NEW_ENV \ + "newenv=protect off " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ + "erase " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ + "protect on " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0" + +#define CONFIG_HW_ENV_SETTINGS \ + "hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi," \ + "can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6," \ + "asrc,spdif,lpuart1,ftm1\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_NEW_ENV \ + CONFIG_KM_DEF_ENV \ + CONFIG_HW_ENV_SETTINGS \ + "EEprom_ivm=pca9547:70:9\0" \ + "ethrotate=no\0" \ + "" + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ + +#endif diff --git a/roms/u-boot/include/configs/km_kirkwood.h b/roms/u-boot/include/configs/km_kirkwood.h new file mode 100644 index 000000000..82c2a1292 --- /dev/null +++ b/roms/u-boot/include/configs/km_kirkwood.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Prafulla Wadaskar + * + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2011-2012 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com + * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com + */ + +/* + * for linking errors see + * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html + */ + +#ifndef _CONFIG_KM_KIRKWOOD_H +#define _CONFIG_KM_KIRKWOOD_H + +/* KM_KIRKWOOD */ +#if defined(CONFIG_KM_KIRKWOOD) +#define CONFIG_HOSTNAME "km_kirkwood" +#define CONFIG_KM_DISABLE_PCIE + +/* KM_KIRKWOOD_PCI */ +#elif defined(CONFIG_KM_KIRKWOOD_PCI) +#define CONFIG_HOSTNAME "km_kirkwood_pci" +#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" +#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE + +/* KM_KIRKWOOD_128M16 */ +#elif defined(CONFIG_KM_KIRKWOOD_128M16) +#define CONFIG_HOSTNAME "km_kirkwood_128m16" +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg +#define CONFIG_KM_DISABLE_PCIE + +/* KM_NUSA */ +#elif defined(CONFIG_KM_NUSA) + +#define CONFIG_HOSTNAME "kmnusa" + +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg + +/* KMCOGE5UN */ +#elif defined(CONFIG_KM_COGE5UN) +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg +#define CONFIG_HOSTNAME "kmcoge5un" +#define CONFIG_KM_DISABLE_PCIE + +/* KM_SUSE2 */ +#elif defined(CONFIG_KM_SUSE2) +#define CONFIG_HOSTNAME "kmsuse2" +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg +#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" +#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE +#else +#error ("Board unsupported") +#endif + +/* include common defines/options for all arm based Keymile boards */ +#include "km/km_arm.h" + +#if defined(CONFIG_KM_PIGGY4_88E6352) +/* + * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via + * an Marvell 88E6352 simple switch. + * In this case we have to change the default settings for the etherent mac. + * There is NO ethernet phy. The ARM and Switch are conencted directly over + * RGMII in MAC-MAC mode + * In this case 1GBit full duplex and autoneg off + */ +#define PORT_SERIAL_CONTROL_VALUE ( \ + MVGBE_FORCE_LINK_PASS | \ + MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ + MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ + MVGBE_ADV_NO_FLOW_CTRL | \ + MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + MVGBE_FORCE_BP_MODE_NO_JAM | \ + (1 << 9) /* Reserved bit has to be 1 */ | \ + MVGBE_DO_NOT_FORCE_LINK_FAIL | \ + MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ + MVGBE_DTE_ADV_0 | \ + MVGBE_MIIPHY_MAC_MODE | \ + MVGBE_AUTO_NEG_NO_CHANGE | \ + MVGBE_MAX_RX_PACKET_1552BYTE | \ + MVGBE_CLR_EXT_LOOPBACK | \ + MVGBE_SET_FULL_DUPLEX_MODE | \ + MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ + MVGBE_SET_GMII_SPEED_TO_1000 |\ + MVGBE_SET_MII_SPEED_TO_100) + +#endif + +#ifdef CONFIG_KM_PIGGY4_88E6061 +/* + * Some keymile boards like mgcoge5un have their PIGGY4 connected via + * an Marvell 88E6061 simple switch. + * In this case we have to change the default settings for the + * ethernet phy connected to the kirkwood. + * In this case 100MB full duplex and autoneg off + */ +#define PORT_SERIAL_CONTROL_VALUE ( \ + MVGBE_FORCE_LINK_PASS | \ + MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ + MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ + MVGBE_ADV_NO_FLOW_CTRL | \ + MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + MVGBE_FORCE_BP_MODE_NO_JAM | \ + (1 << 9) /* Reserved bit has to be 1 */ | \ + MVGBE_DO_NOT_FORCE_LINK_FAIL | \ + MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ + MVGBE_DTE_ADV_0 | \ + MVGBE_MIIPHY_MAC_MODE | \ + MVGBE_AUTO_NEG_NO_CHANGE | \ + MVGBE_MAX_RX_PACKET_1552BYTE | \ + MVGBE_CLR_EXT_LOOPBACK | \ + MVGBE_SET_FULL_DUPLEX_MODE | \ + MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ + MVGBE_SET_GMII_SPEED_TO_10_100 |\ + MVGBE_SET_MII_SPEED_TO_100) +#endif + +#ifdef CONFIG_KM_DISABLE_PCIE +#undef CONFIG_KIRKWOOD_PCIE_INIT +#endif + +#endif /* _CONFIG_KM_KIRKWOOD */ diff --git a/roms/u-boot/include/configs/kmcent2.h b/roms/u-boot/include/configs/kmcent2.h new file mode 100644 index 000000000..51a01d860 --- /dev/null +++ b/roms/u-boot/include/configs/kmcent2.h @@ -0,0 +1,513 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Keymile AG + * Rainer Boschung + * + */ + +#ifndef __KMCENT2_H +#define __KMCENT2_H + +#define CONFIG_HOSTNAME "kmcent2" +#define KM_BOARD_NAME CONFIG_HOSTNAME + +/* + * The Linux fsl_fman driver needs to be able to process frames with more + * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot + * parameters + */ +#define CONFIG_KM_DEF_BOOT_ARGS_CPU "fsl_dpaa_fman.fsl_fm_max_frm=1558" + +#include "km/keymile-common.h" + +/* Application IFC chip selects */ +#define SYS_LAWAPP_BASE 0xc0000000 +#define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE) + +/* Application IFC CS4 MRAM */ +#define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE +#define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS +#define SYS_MRAM_CSPR_EXT (0x0f) +#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \ + CSPR_PORT_SIZE_8 | /* 8 bit */ \ + CSPR_MSEL_GPCM | /* msel = gpcm */ \ + CSPR_V /* bank is valid */) +#define SYS_MRAM_AMASK IFC_AMASK(2 * 1024 * 1024) /* 2 MiB */ +#define SYS_MRAM_CSOR CSOR_GPCM_TRHZ_40 +/* MRAM Timing parameters for IFC CS4 */ +#define SYS_MRAM_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ + FTIM0_GPCM_TEADC(0x8) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define SYS_MRAM_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0xe)) +#define SYS_MRAM_FTIM2 (FTIM2_GPCM_TCS(0x2) | \ + FTIM2_GPCM_TCH(0x2) | \ + FTIM2_GPCM_TWP(0x8)) +#define SYS_MRAM_FTIM3 0x04000000 +#define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT +#define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR +#define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK +#define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR +#define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0 +#define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1 +#define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2 +#define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3 + +/* Application IFC CS6: BFTIC */ +#define SYS_BFTIC_BASE 0xd0000000 +#define SYS_BFTIC_BASE_PHYS (0xf00000000ull | SYS_BFTIC_BASE) +#define SYS_BFTIC_CSPR_EXT (0x0f) +#define SYS_BFTIC_CSPR (CSPR_PHYS_ADDR(SYS_BFTIC_BASE) | \ + CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ + CSPR_MSEL_GPCM | /* MSEL = GPCM */\ + CSPR_V) /* valid */ +#define SYS_BFTIC_AMASK IFC_AMASK(64 * 1024) /* 64kB */ +#define SYS_BFTIC_CSOR CSOR_GPCM_TRHZ_40 +/* BFTIC Timing parameters for IFC CS6 */ +#define SYS_BFTIC_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ + FTIM0_GPCM_TEADC(0x8) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define SYS_BFTIC_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x12)) +#define SYS_BFTIC_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x12)) +#define SYS_BFTIC_FTIM3 0x04000000 +#define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT +#define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR +#define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK +#define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR +#define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0 +#define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1 +#define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2 +#define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3 + +/* Application IFC CS7 PAXE */ +#define CONFIG_SYS_PAXE_BASE 0xd8000000 +#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE) +#define SYS_PAXE_CSPR_EXT (0x0f) +#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \ + CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ + CSPR_MSEL_GPCM | /* MSEL = GPCM */\ + CSPR_V) /* valid */ +#define SYS_PAXE_AMASK IFC_AMASK(64 * 1024) /* 64kB */ +#define SYS_PAXE_CSOR CSOR_GPCM_TRHZ_40 +/* PAXE Timing parameters for IFC CS7 */ +#define SYS_PAXE_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ + FTIM0_GPCM_TEADC(0x8) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define SYS_PAXE_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x12)) +#define SYS_PAXE_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x12)) +#define SYS_PAXE_FTIM3 0x04000000 +#define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT +#define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR +#define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK +#define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR +#define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0 +#define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1 +#define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2 +#define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3 + +/* PRST */ +#define KM_BFTIC4_RST 0 +#define KM_DPAXE_RST 1 +#define KM_FEMT_RST 3 +#define KM_FOAM_RST 4 +#define KM_EFE_RST 5 +#define KM_ES_PHY_RST 6 +#define KM_XES_PHY_RST 7 +#define KM_ZL30158_RST 8 +#define KM_ZL30364_RST 9 +#define KM_BOBCAT_RST 10 +#define KM_ETHSW_DDR_RST 12 +#define KM_CFE_RST 13 +#define KM_PEXSW_RST 14 +#define KM_PEXSW_NT_RST 15 + +/* QRIO GPIOs used for deblocking */ +#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A +#define KM_I2C_DEBLOCK_SCL 20 +#define KM_I2C_DEBLOCK_SDA 21 + +/* High Level Configuration Options */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ + +#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +/* Environment in parallel NOR-Flash */ +#define CONFIG_ENV_TOTAL_SIZE 0x040000 +#define ENV_DEL_ADDR 0xebf00000 /*direct for newenv*/ + +#define CONFIG_SYS_CLK_FREQ 66666666 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_ENABLE_36BIT_PHYS + +/* POST memory regions test */ +#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE 256 << 10 + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_DDR_CLK_FREQ 66666666 + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x54 +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR CONFIG_SYS_IVM_EEPROM_ADR +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/****************************************************************************** + * (PRAM usage) + * ... ------------------------------------------------------- + * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM + * ... |<------------------- pram -------------------------->| + * ... ------------------------------------------------------- + * @END_OF_RAM: + * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose + * @CONFIG_KM_PHRAM: address for /var + * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) + * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM + */ + +/* size of rootfs in RAM */ +#define CONFIG_KM_ROOTFSSIZE 0x0 +/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable + * is not valid yet, which is the case for when u-boot copies itself to RAM + */ +#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10) + +/* + * IFC Definitions + */ +/* NOR flash on IFC CS0 */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \ + CONFIG_SYS_FLASH_BASE) + +#define CONFIG_SYS_NOR_CSPR_EXT (0x0f) +#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ + CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\ + 0x00000010 | /* drive TE high */\ + CSPR_MSEL_NOR | /* MSEL = NOR */\ + CSPR_V) /* valid */ +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */ +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\ + CSOR_NOR_TRHZ_20 | \ + CSOR_NOR_BCTLD) + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ + FTIM0_NOR_TEADC(0x7) | \ + FTIM0_NOR_TEAHC(0x1)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ + FTIM1_NOR_TRAD_NOR(0x21) | \ + FTIM1_NOR_TSEQRAD_NOR(0x21)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) | \ + FTIM2_NOR_TCS(0x1) | \ + FTIM2_NOR_TWP(0xb) | \ + FTIM2_NOR_TWPH(0x6)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +/* More NOR Flash params */ +#define CONFIG_SYS_FLASH_QUIET_TEST + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + +/* NAND Flash on IFC CS1*/ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xfa000000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0f) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \ + CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\ + 0x00000010 | /* drive TE high */\ + CSPR_MSEL_NAND | /* MSEL = NAND */\ + CSPR_V) /* valid */ +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */ + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \ + CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */ \ + CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \ + CSOR_NAND_RAL_3 | /* RAL = 3Bytes */ \ + CSOR_NAND_PGS_2K | /* Page size = 2K */ \ + CSOR_NAND_SPRZ_128 | /* Spare size = 128 */ \ + CSOR_NAND_PB(64) | /* 64 Pages/Block */ \ + CSOR_NAND_TRHZ_40 | /**/ \ + CSOR_NAND_BCTLD) /**/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ + FTIM0_NAND_TWP(0x8) | \ + FTIM0_NAND_TWCHT(0x3) | \ + FTIM0_NAND_TWH(0x5)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ + FTIM1_NAND_TWBE(0x1e) | \ + FTIM1_NAND_TRR(0x6) | \ + FTIM1_NAND_TRP(0x8)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ + FTIM2_NAND_TREH(0x5) | \ + FTIM2_NAND_TWHRE(0x3c)) +#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 + +/* More NAND Flash Params */ +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* QRIO on IFC CS2 */ +#define CONFIG_SYS_QRIO_BASE 0xfb000000 +#define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE) +#define SYS_QRIO_CSPR_EXT (0x0f) +#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \ + CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ + 0x00000010 | /* drive TE high */\ + CSPR_MSEL_GPCM | /* MSEL = GPCM */\ + CSPR_V) /* valid */ +#define SYS_QRIO_AMASK IFC_AMASK(64 * 1024) /* 64kB */ +#define SYS_QRIO_CSOR (CSOR_GPCM_TRHZ_20 |\ + CSOR_GPCM_BCTLD) +/* QRIO Timing parameters for IFC CS2 */ +#define SYS_QRIO_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ + FTIM0_GPCM_TEADC(0x8) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define SYS_QRIO_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x6)) +#define SYS_QRIO_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x7)) +#define SYS_QRIO_FTIM3 0x04000000 +#define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT +#define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR +#define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK +#define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR +#define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3 + +#define CONFIG_MISC_INIT_F +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */ + +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* + * Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + * Retain non-DM serial port for debug purposes. + */ +#if !defined(CONFIG_DM_SERIAL) +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) +#endif + +#ifndef __ASSEMBLY__ +void set_sda(int state); +void set_scl(int state); +int get_sda(void); +int get_scl(void); +#endif + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* controller 1 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull + +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME + +/* Default address of microcode for the Linux Fman driver */ +#define CONFIG_SYS_FMAN_FW_ADDR 0xE8020000 +#define CONFIG_SYS_QE_FW_ADDR 0xE8040000 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) + +/* Qman / Bman */ +/* RGMII (FM1@DTESC5) is local managemant interface */ +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x11 +#define CONFIG_ETHPRIME "fm1-mac5" + +/* + * Hardware Watchdog + */ +#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) ~10min */ +#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* + * Environment Configuration + */ +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV +#endif + +#define __USB_PHY_TYPE utmi + +#define CONFIG_KM_DEF_ENV_CPU \ + "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ + "cramfsloadfdt=" \ + "cramfsload ${fdt_addr_r} " \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ + "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize} && " \ + "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize} && " \ + "cp.b ${load_addr_r} " \ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ + "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize}\0" \ + "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ + " +${filesize} && " \ + "erase " __stringify(CONFIG_SYS_FLASH_BASE) \ + " +${filesize} && " \ + "cp.b ${load_addr_r} " \ + __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \ + "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \ + "set_fdthigh=true\0" \ + "checkfdt=true\0" \ + "fpgacfg=true\0" \ + "" + +#define CONFIG_HW_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ + "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ + "usb_dr_mode=host\0" + +#define CONFIG_KM_NEW_ENV \ + "newenv=protect off " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ + "erase " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ + "protect on " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0" + +/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + CONFIG_KM_NEW_ENV \ + CONFIG_HW_ENV_SETTINGS \ + "EEprom_ivm=pca9547:70:9\0" \ + "" + +#endif /* __KMCENT2_H */ diff --git a/roms/u-boot/include/configs/kmcoge5ne.h b/roms/u-boot/include/configs/kmcoge5ne.h new file mode 100644 index 000000000..cdfb280ae --- /dev/null +++ b/roms/u-boot/include/configs/kmcoge5ne.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Holger Brunck, Keymile GmbH Hannover, + * Christian Herzig, Keymile AG Switzerland, + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_HOSTNAME "kmcoge5ne" +#define CONFIG_NAND_ECC_BCH +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ + +#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" +#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" + +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" +#include "km/km-mpc83xx.h" +#include "km/km-mpc8360.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/** + * KMCOGE5NE has 512 MB RAM + */ +#define CONFIG_SYS_DDR_CS0_CONFIG (\ + CSCONFIG_EN | \ + CSCONFIG_AP | \ + CSCONFIG_ODT_WR_ONLY_CURRENT | \ + CSCONFIG_BANK_BIT_3 | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +/* + * BFTIC3 on the local bus CS4 + */ +#define CONFIG_SYS_BFTIC3_BASE 0xB0000000 +#define CONFIG_SYS_BFTIC3_SIZE 256 + +/* enable POST tests */ +#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) +#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ +#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END +#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ +#define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ + +#endif /* CONFIG */ diff --git a/roms/u-boot/include/configs/kmeter1.h b/roms/u-boot/include/configs/kmeter1.h new file mode 100644 index 000000000..4245875e3 --- /dev/null +++ b/roms/u-boot/include/configs/kmeter1.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Holger Brunck, Keymile GmbH Hannover, + * Christian Herzig, Keymile AG Switzerland, + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_HOSTNAME "kmeter1" + +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" +#include "km/km-mpc83xx.h" +#include "km/km-mpc8360.h" + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10 | \ + CSCONFIG_ODT_WR_ONLY_CURRENT) +#endif /* CONFIG */ diff --git a/roms/u-boot/include/configs/kmopti2.h b/roms/u-boot/include/configs/kmopti2.h new file mode 100644 index 000000000..5050c7030 --- /dev/null +++ b/roms/u-boot/include/configs/kmopti2.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2013 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_HOSTNAME "kmopti2" + +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/kmp204x.h b/roms/u-boot/include/configs/kmp204x.h new file mode 100644 index 000000000..af3b03be4 --- /dev/null +++ b/roms/u-boot/include/configs/kmp204x.h @@ -0,0 +1,416 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#if defined(CONFIG_KMCOGE4) +#define CONFIG_HOSTNAME "kmcoge4" + +#else +#error ("Board not supported") +#endif + +#define CONFIG_KMP204X + +/* an additionnal option is required for UBI as subpage access is + * supported in u-boot + */ +#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" + +#define CONFIG_NAND_ECC_BCH + +/* common KM defines */ +#include "km/keymile-common.h" + +#define CONFIG_SYS_RAMBOOT +#define CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg + +/* High Level Configuration Options */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_SYS_DPAA_RMAN /* RMan */ + +/* Environment in SPI Flash */ +#define CONFIG_ENV_TOTAL_SIZE 0x020000 + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(unsigned long dummy); +#endif +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ + CONFIG_RAMBOOT_TEXT_BASE) +#define CONFIG_SYS_L3_SIZE (1024 << 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x54 +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/****************************************************************************** + * (PRAM usage) + * ... ------------------------------------------------------- + * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM + * ... |<------------------- pram -------------------------->| + * ... ------------------------------------------------------- + * @END_OF_RAM: + * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose + * @CONFIG_KM_PHRAM: address for /var + * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) + * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM + */ + +/* size of rootfs in RAM */ +#define CONFIG_KM_ROOTFSSIZE 0x0 +/* pseudo-non volatile RAM [hex] */ +#define CONFIG_KM_PNVRAM 0x80000 +/* physical RAM MTD size [hex] */ +#define CONFIG_KM_PHRAM 0x100000 +/* reserved pram area at the end of memory [hex] + * u-boot reserves some memory for the MP boot page + */ +#define CONFIG_KM_RESERVED_PRAM 0x1000 +/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable + * is not valid yet, which is the case for when u-boot copies itself to RAM + */ +#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10) + +/* + * Local Bus Definitions + */ + +/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) + +/* Nand Flash */ +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull + +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* NAND flash config */ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ + +#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ + | OR_FCM_BCTLD /* LBCTL not ass */ \ + | OR_FCM_SCY_1 /* 1 clk wait cycle */ \ + | OR_FCM_RST /* 1 clk read setup */ \ + | OR_FCM_PGS /* Large page size */ \ + | OR_FCM_CST) /* 0.25 command setup */ + +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ + +/* QRIO FPGA */ +#define CONFIG_SYS_QRIO_BASE 0xfb000000 +#define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull + +#define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ + | BR_PS_8 /* Port Size 8 bits */ \ + | BR_DECC_OFF /* no error corr */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ + +#define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ + | OR_GPCM_BCTLD /* no LCTL assert */ \ + | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \ + | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ + | OR_GPCM_TRLX /* relaxed tmgs */ \ + | OR_GPCM_EAD) /* extra bus clk cycles */ + +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x11D600) + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* I2C */ +/* QRIO GPIOs used for deblocking */ +#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A +#define KM_I2C_DEBLOCK_SCL 20 +#define KM_I2C_DEBLOCK_SDA 21 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ +#define CONFIG_SYS_NUM_I2C_BUSES 3 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ + } + +#define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ + +/* + * eSPI - Enhanced SPI + */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* Qman/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +/* Default address of microcode for the Linux Fman driver + * env is stored at 0x100000, sector size is 0x10000, x2 (redundant) + * ucode is stored after env, so we got 0x120000. + */ +#define CONFIG_SYS_FMAN_FW_ADDR 0x120000 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) + +#define CONFIG_PCI_INDIRECT_BRIDGE + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ +#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 +#define CONFIG_SYS_TBIPA_VALUE 8 +#define CONFIG_ETHPRIME "FM1@DTSEC5" + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Hardware Watchdog + */ +#define CONFIG_WATCHDOG /* enable CPU watchdog */ +#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ +#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ + +/* + * additionnal command line configuration. + */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +#define __USB_PHY_TYPE utmi +#define CONFIG_USB_EHCI_FSL + +/* + * Environment Configuration + */ +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +/* architecture specific default bootargs */ +#define CONFIG_KM_DEF_BOOT_ARGS_CPU "" + +/* FIXME: FDT_ADDR is unspecified */ +#define CONFIG_KM_DEF_ENV_CPU \ + "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ + "cramfsloadfdt=" \ + "cramfsload ${fdt_addr_r} " \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ + "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ + "u-boot=" CONFIG_HOSTNAME "/u-boot.pbl\0" \ + "update=" \ + "sf probe 0;sf erase 0 +${filesize};" \ + "sf write ${load_addr_r} 0 ${filesize};\0" \ + "set_fdthigh=true\0" \ + "checkfdt=true\0" \ + "" + +#define CONFIG_HW_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ + "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ + "usb_dr_mode=host\0" + +#define CONFIG_KM_NEW_ENV \ + "newenv=sf probe 0;" \ + "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ + __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" + +/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + CONFIG_KM_NEW_ENV \ + CONFIG_HW_ENV_SETTINGS \ + "EEprom_ivm=pca9547:70:9\0" \ + "" + +/* App2 Local bus */ +#define CONFIG_SYS_LBAPP2_BASE 0xE0000000 +#define CONFIG_SYS_LBAPP2_BASE_PHYS 0xFE0000000ull + +#define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \ + | BR_PS_8 /* Port Size 8 bits */ \ + | BR_DECC_OFF /* no error corr */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ + +#define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB /* length 256MB */ \ + | OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \ + | OR_GPCM_CSNT /* LCS 1/4 clk before */ \ + | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ + | OR_GPCM_TRLX /* relaxed tmgs */ \ + | OR_GPCM_EAD) /* extra bus clk cycles */ +/* Local bus app2 Base Address */ +#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM +/* Local bus app2 Options */ +#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/kmsupx5.h b/roms/u-boot/include/configs/kmsupx5.h new file mode 100644 index 000000000..e3de6c61e --- /dev/null +++ b/roms/u-boot/include/configs/kmsupx5.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2013 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_HOSTNAME "kmsupx5" + +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/kmtegr1.h b/roms/u-boot/include/configs/kmtegr1.h new file mode 100644 index 000000000..bdd35cc7f --- /dev/null +++ b/roms/u-boot/include/configs/kmtegr1.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ + +#define CONFIG_HOSTNAME "kmtegr1" +#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" +#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" + +#define CONFIG_NAND_ECC_BCH +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 + +#define CONFIG_SYS_SICRL (0 \ + | SICR_1_UART1_UART1RTS \ + | SICR_1_I2C_CKSTOP \ + | SICR_1_IRQ_A_IRQ \ + | SICR_1_IRQ_B_IRQ \ + | SICR_1_GPIO_A_GPIO \ + | SICR_1_GPIO_B_GPIO \ + | SICR_1_GPIO_C_GPIO \ + | SICR_1_GPIO_D_GPIO \ + | SICR_1_GPIO_E_LCS \ + | SICR_1_GPIO_F_GPIO \ + | SICR_1_USB_A_UART2S \ + | SICR_1_USB_B_UART2RTS \ + | SICR_1_FEC1_FEC1 \ + | SICR_1_FEC2_FEC2 \ + ) + +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" +#include "km/km-mpc83xx.h" +#include "km/km-mpc8309.h" + +/* must be after the include because KMBEC_FPGA is otherwise undefined */ +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/kmtepr2.h b/roms/u-boot/include/configs/kmtepr2.h new file mode 100644 index 000000000..a4ceb1c50 --- /dev/null +++ b/roms/u-boot/include/configs/kmtepr2.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2013 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_HOSTNAME "kmtepr2" + +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/koelsch.h b/roms/u-boot/include/configs/koelsch.h new file mode 100644 index 000000000..65a38c575 --- /dev/null +++ b/roms/u-boot/include/configs/koelsch.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * include/configs/koelsch.h + * + * Copyright (C) 2013 Renesas Electronics Corporation + */ + +#ifndef __KOELSCH_H +#define __KOELSCH_H + +#include "rcar-gen2-common.h" + +#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 +#define STACK_AREA_SIZE 0x00100000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) + +/* SH Ether */ +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" + +/* SPL support */ +#define CONFIG_SPL_STACK 0xe6340000 +#define CONFIG_SPL_MAX_SIZE 0x4000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIF0 +#define CONFIG_SH_SCIF_CLK_FREQ 65000000 +#endif + +#endif /* __KOELSCH_H */ diff --git a/roms/u-boot/include/configs/kontron_sl28.h b/roms/u-boot/include/configs/kontron_sl28.h new file mode 100644 index 000000000..bfb4e67c8 --- /dev/null +++ b/roms/u-boot/include/configs/kontron_sl28.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __SL28_H +#define __SL28_H + +#include +#include +#include + +/* we don't use hwconfig but this has to be defined.. */ +#define HWCONFIG_BUFFER_SIZE 256 + +/* we don't have secure memory unless we have a BL31 */ +#ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#undef CONFIG_SYS_MEM_RESERVE_SECURE +#endif + +/* DDR */ +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef + +#define CONFIG_VERY_BIG_RAM +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 + +/* early stack pointer */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xeff0) + +/* memtest command */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +/* SMP */ +#define CPU_RELEASE_ADDR secondary_boot_addr + +/* generic timer */ +#define COUNTER_FREQUENCY 25000000 + +/* size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) + +/* early heap for SPL DM */ +#define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE + +/* serial port */ +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) + +/* ethernet */ +#define CONFIG_SYS_RX_ETH_BUFFER 8 + +/* SPL */ +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SPL_MAX_SIZE 0x20000 +#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) + +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) + +/* environment */ +/* see include/configs/ti_armv7_common.h */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 +#define ENV_MEM_LAYOUT_SETTINGS \ + "loadaddr=0x82000000\0" \ + "kernel_addr_r=0x82000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "bootm_size=0x10000000\0" \ + "pxefile_addr_r=0x80100000\0" \ + "scriptaddr=0x80000000\0" \ + "ramdisk_addr_r=0x88080000\0" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(NVME, nvme, 0) \ + func(USB, usb, 0) \ + func(SCSI, scsi, 0) \ + func(DHCP, dhcp, 0) \ + func(PXE, pxe, 0) +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "env_addr=0x203e0004\0" \ + "envload=env import -d -b ${env_addr}\0" \ + "install_rcw=source 20200000\0" \ + "fdtfile=freescale/fsl-ls1028a-kontron-sl28.dtb\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV + +#endif /* __SL28_H */ diff --git a/roms/u-boot/include/configs/kp_imx53.h b/roms/u-boot/include/configs/kp_imx53.h new file mode 100644 index 000000000..c94882846 --- /dev/null +++ b/roms/u-boot/include/configs/kp_imx53.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#ifndef __CONFIG_H_ +#define __CONFIG_H_ + +#include +#include + +#define CONFIG_SYS_FSL_CLK + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +/* USB Configs */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_BUS_NUM 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* Command definition */ +#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc1,115200\0" \ + "fdt_addr=0x75000000\0" \ + "fdt_high=0xffffffff\0" \ + "scriptaddr=0x74000000\0" \ + "kernel_file=fitImage\0"\ + "silent=1\0"\ + "rdinit=/sbin/init\0" \ + "addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \ + "upd_image=st.4k\0" \ + "uboot_file=u-boot.imx\0" \ + "updargs=setenv bootargs console=${console} ${smp} ${displayargs}\0" \ + "initrd_ram_dev=/dev/ram\0" \ + "addswupdate=setenv bootargs ${bootargs} root=${initrd_ram_dev} rw\0" \ + "addkeys=setenv bootargs ${bootargs} di=${dig_in} key1=${key1}\0" \ + "loadusb=usb start; " \ + "fatload usb 0 ${loadaddr} ${upd_image}\0" \ + "up=if tftp ${loadaddr} ${uboot_file}; then " \ + "setexpr blkc ${filesize} / 0x200; " \ + "setexpr blkc ${blkc} + 1; " \ + "mmc write ${loadaddr} 0x2 ${blkc}" \ + "; fi\0" \ + "upwic=setenv wic_file kp-image-kp${boardsoc}.wic; "\ + "if tftp ${loadaddr} ${wic_file}; then " \ + "setexpr blkc ${filesize} / 0x200; " \ + "setexpr blkc ${blkc} + 1; " \ + "mmc write ${loadaddr} 0x0 ${blkc}" \ + "; fi\0" \ + "usbupd=echo Booting update from usb ...; " \ + "setenv bootargs; " \ + "run updargs; " \ + "run addinitrd; " \ + "run addswupdate; " \ + "run addkeys; " \ + "run loadusb; " \ + "bootm ${loadaddr}#${fit_config}\0" \ + BOOTENV + +#define CONFIG_BOOTCOMMAND "run usbupd; run distro_bootcmd" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) + +#include + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * SZ_1M) +#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* environment organization */ + +#endif /* __CONFIG_H_ */ diff --git a/roms/u-boot/include/configs/kp_imx6q_tpc.h b/roms/u-boot/include/configs/kp_imx6q_tpc.h new file mode 100644 index 000000000..749e880f3 --- /dev/null +++ b/roms/u-boot/include/configs/kp_imx6q_tpc.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K+P iMX6Q KP_IMX6Q_TPC board configuration + * + * Copyright (C) 2018 Lukasz Majewski + */ + +#ifndef __KP_IMX6Q_TPC_IMX6_CONFIG_H_ +#define __KP_IMX6Q_TPC_IMX6_CONFIG_H_ + +#include + +#include "mx6_common.h" + +/* SPL */ +#include "imx6_spl.h" /* common IMX6 SPL configuration */ + +/* Miscellaneous configurable options */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) + +/* FEC ethernet */ +#define CONFIG_ARP_TIMEOUT 200UL + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ +#endif + +/* Watchdog */ + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200\0" \ + "fdt_addr=0x18000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x10008000\0" \ + "fdt_addr_r=0x13000000\0" \ + "ramdisk_addr_r=0x18000000\0" \ + "scriptaddr=0x14000000\0" \ + "kernel_file=fitImage\0"\ + "rdinit=/sbin/init\0" \ + "addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \ + "fit_config=mx6q_tpc70_conf\0" \ + "uboot_file=u-boot.img\0" \ + "SPL_file=SPL\0" \ + "wic_file=kp-image-kpimx6qtpc.wic\0" \ + "upd_image=st.4k\0" \ + "updargs=setenv bootargs console=${console} ${smp} ${displayargs}\0" \ + "initrd_ram_dev=/dev/ram\0" \ + "addswupdate=setenv bootargs ${bootargs} root=${initrd_ram_dev} rw\0" \ + "loadusb=usb start; " \ + "fatload usb 0 ${loadaddr} ${upd_image}\0" \ + "upd_uboot_sd=" \ + "if tftp ${loadaddr} ${uboot_file}; then " \ + "setexpr blkc ${filesize} / 0x200;" \ + "setexpr blkc ${blkc} + 1;" \ + "mmc write ${loadaddr} 0x8A ${blkc};" \ + "fi;\0" \ + "upd_SPL_sd=" \ + "if tftp ${loadaddr} ${SPL_file}; then " \ + "setexpr blkc ${filesize} / 0x200;" \ + "setexpr blkc ${blkc} + 1;" \ + "mmc write ${loadaddr} 0x2 ${blkc};" \ + "fi;\0" \ + "upd_SPL_mmc=mmc dev 1; mmc partconf 1 0 1 1; run upd_SPL_sd\0" \ + "upd_uboot_mmc=mmc dev 1; mmc partconf 1 0 1 1; run upd_uboot_sd\0" \ + "up_mmc=run upd_SPL_mmc; run upd_uboot_mmc\0" \ + "up_sd=run upd_SPL_sd; run upd_uboot_sd\0" \ + "upd_wic=" \ + "if tftp ${loadaddr} ${wic_file}; then " \ + "setexpr blkc ${filesize} / 0x200;" \ + "setexpr blkc ${blkc} + 1;" \ + "mmc write ${loadaddr} 0x0 ${blkc};" \ + "fi;\0" \ + "usbupd=echo Booting update from usb ...; " \ + "setenv bootargs; " \ + "run updargs; " \ + "run addinitrd; " \ + "run addswupdate; " \ + "run loadusb; " \ + "bootm ${loadaddr}#${fit_config}\0" \ + BOOTENV + +#define CONFIG_BOOTCOMMAND "run usbupd; run distro_bootcmd" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) + +#include +#endif + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment */ + +#endif /* __KP_IMX6Q_TPC_IMX6_CONFIG_H_ */ diff --git a/roms/u-boot/include/configs/kylin_rk3036.h b/roms/u-boot/include/configs/kylin_rk3036.h new file mode 100644 index 000000000..75fc03f14 --- /dev/null +++ b/roms/u-boot/include/configs/kylin_rk3036.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +#ifndef CONFIG_SPL_BUILD + +/* Store env in emmc */ + +#endif + +#endif diff --git a/roms/u-boot/include/configs/kzm9g.h b/roms/u-boot/include/configs/kzm9g.h new file mode 100644 index 000000000..0724df154 --- /dev/null +++ b/roms/u-boot/include/configs/kzm9g.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Nobuhiro Iwamatsu + * Copyright (C) 2012 Renesas Solutions Corp. + */ + +#ifndef __KZM9G_H +#define __KZM9G_H + +#define CONFIG_SH73A0 +#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G + +#include + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* MEMORY */ +#define KZM_SDRAM_BASE (0x40000000) +#define PHYS_SDRAM KZM_SDRAM_BASE +#define PHYS_SDRAM_SIZE (512 * 1024 * 1024) + +/* NOR Flash */ +#define KZM_FLASH_BASE (0x00000000) +#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE) +#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) +#define CONFIG_SYS_MAX_FLASH_BANKS (1) +#define CONFIG_SYS_MAX_FLASH_SECT (512) + +/* prompt */ +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } + +/* SCIF */ +#define CONFIG_CONS_SCIF4 + +#undef CONFIG_SYS_LOADS_BAUD_CHANGE + +#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */ +#define CONFIG_SYS_INIT_RAM_SIZE (0x10000) +#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024) +#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) +#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) + +#define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) + +#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000 + +/* FLASH */ +#undef CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */ + +/* Timeout for Flash erase operations (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) +/* Timeout for Flash write operations (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) +/* Timeout for Flash set sector lock bit operations (in ms) */ +#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) +/* Timeout for Flash clear lock bit operations (in ms) */ +#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) + +#undef CONFIG_SYS_DIRECT_FLASH_TFTP + +/* GPIO / PFC */ +#define CONFIG_SH_GPIO_PFC + +/* Clock */ +#define CONFIG_GLOBAL_TIMER +#define CONFIG_SYS_CLK_FREQ (48000000) +#define CONFIG_SYS_CPU_CLK (1196000000) +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ + +#define CONFIG_NFS_TIMEOUT 10000UL + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5 +#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000 +#define CONFIG_SYS_I2C_SH_SPEED0 100000 +#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000 +#define CONFIG_SYS_I2C_SH_SPEED1 100000 +#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000 +#define CONFIG_SYS_I2C_SH_SPEED2 100000 +#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000 +#define CONFIG_SYS_I2C_SH_SPEED3 100000 +#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000 +#define CONFIG_SYS_I2C_SH_SPEED4 100000 +#define CONFIG_SH_I2C_8BIT +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */ + +#endif /* __KZM9G_H */ diff --git a/roms/u-boot/include/configs/lacie_kw.h b/roms/u-boot/include/configs/lacie_kw.h new file mode 100644 index 000000000..420c1d49b --- /dev/null +++ b/roms/u-boot/include/configs/lacie_kw.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 Simon Guinot + */ + +#ifndef _CONFIG_LACIE_KW_H +#define _CONFIG_LACIE_KW_H + +/* + * Machine number definition + */ +#if defined(CONFIG_INETSPACE_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2 +#elif defined(CONFIG_NETSPACE_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2 +#elif defined(CONFIG_NETSPACE_LITE_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2 +#elif defined(CONFIG_NETSPACE_MINI_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2 +#elif defined(CONFIG_NETSPACE_MAX_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2 +#elif defined(CONFIG_D2NET_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2 +#elif defined(CONFIG_NET2BIG_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2 +#else +#error "Unknown board" +#endif + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +/* SoC name */ +#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2) +#define CONFIG_KW88F6192 +#else +#define CONFIG_KW88F6281 +#endif +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Core clock definition + */ +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ + +/* + * SDRAM configuration + */ + +/* + * Different SDRAM configuration and size for some of the boards derived + * from the Network Space v2 + */ +#if defined(CONFIG_INETSPACE_V2) +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-is2.cfg +#elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2) +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg +#endif + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_SYS_IDE_MAXBUS +#undef CONFIG_SYS_IDE_MAXDEVICE + +/* + * Enable platform initialisation via misc_init_r() function + */ + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#endif + +/* + * SATA Driver configuration + */ + +#ifdef CONFIG_SATA +#define CONFIG_SYS_64BIT_LBA +#define CONFIG_LBA48 +#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \ + defined(CONFIG_NET2BIG_V2) +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#else +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#endif +#endif /* CONFIG_SATA */ + +/* + * Enable GPI0 support + */ +#define CONFIG_KIRKWOOD_GPIO + +/* + * Enable I2C support + */ +#ifdef CONFIG_CMD_I2C +/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ +#if defined(CONFIG_NET2BIG_V2) +#define CONFIG_SYS_I2C_G762_ADDR 0x3e +#endif +#endif /* CONFIG_CMD_I2C */ + +/* + * Partition support + */ + +/* + * File systems support + */ + +/* + * Environment variables configurations + */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "dhcp && run netconsole; " \ + "if run usbload || run diskload; then bootm; fi" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "bootfile=uImage\0" \ + "loadaddr=0x800000\0" \ + "autoload=no\0" \ + "netconsole=" \ + "set stdin $stdin,nc; " \ + "set stdout $stdout,nc; " \ + "set stderr $stderr,nc;\0" \ + "diskload=sata init && " \ + "ext2load sata 0:1 $loadaddr /boot/$bootfile\0" \ + "usbload=usb start && " \ + "fatload usb 0:1 $loadaddr /boot/$bootfile\0" + +#endif /* _CONFIG_LACIE_KW_H */ diff --git a/roms/u-boot/include/configs/lager.h b/roms/u-boot/include/configs/lager.h new file mode 100644 index 000000000..c5001e3ec --- /dev/null +++ b/roms/u-boot/include/configs/lager.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * include/configs/lager.h + * This file is lager board configuration. + * + * Copyright (C) 2013, 2014 Renesas Electronics Corporation + */ + +#ifndef __LAGER_H +#define __LAGER_H + +#include "rcar-gen2-common.h" + +#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 +#define STACK_AREA_SIZE 0x00100000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) + +/* SH Ether */ +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" + +/* SPL support */ +#define CONFIG_SPL_STACK 0xe6340000 +#define CONFIG_SPL_MAX_SIZE 0x4000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIF0 +#define CONFIG_SH_SCIF_CLK_FREQ 65000000 +#endif + +#endif /* __LAGER_H */ diff --git a/roms/u-boot/include/configs/legoev3.h b/roms/u-boot/include/configs/legoev3.h new file mode 100644 index 000000000..ca96683a3 --- /dev/null +++ b/roms/u-boot/include/configs/legoev3.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 David Lechner + * + * Based on da850evm.h + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on davinci_dvevm.h. Original Copyrights follow: + * + * Copyright (C) 2007 Sergey Kubushyn + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * SoC Configuration + */ +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH +#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) +#define CONFIG_SYS_OSCIN_FREQ 24000000 +#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* + * Memory Info + */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ +#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ +#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ + +/* memtest start addr */ + +/* memtest will be run on 16MB */ + +/* + * Serial Driver info + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) + +#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) + +/* + * I2C Configuration + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ + +/* + * U-Boot general configuration + */ +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) + +/* + * Linux Information + */ +#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) +#define CONFIG_HWCONFIG /* enable hwconfig */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_SETUP_INITRD_TAG +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan; then " \ + "if run loadbootscr; then " \ + "run bootscript; " \ + "else " \ + "if run loadbootenv; then " \ + "echo Loaded env from ${bootenvfile};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run mmcargs; " \ + "if run loadfdt; then " \ + "echo Using ${fdtfile}...;" \ + "run fdtfixup; " \ + "run fdtboot; "\ + "fi; " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi; "\ + "run flashargs; " \ + "run flashboot" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootenvfile=uEnv.txt\0" \ + "fdtfile=da850-lego-ev3.dtb\0" \ + "memsize=64M\0" \ + "filesyssize=10M\0" \ + "verify=n\0" \ + "console=ttyS1,115200n8\0" \ + "bootscraddr=0xC0600000\0" \ + "fdtaddr=0xC0600000\0" \ + "loadaddr=0xC0007FC0\0" \ + "filesysaddr=0xC1180000\0" \ + "fwupdateboot=mw 0xFFFF1FFC 0x5555AAAA; reset\0" \ + "importbootenv=echo Importing environment...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "loadbootenv=fatload mmc 0 ${loadaddr} ${bootenvfile}\0" \ + "mmcargs=setenv bootargs console=${console} root=/dev/mmcblk0p2 rw " \ + "rootwait ${optargs}\0" \ + "mmcboot=bootm ${loadaddr}\0" \ + "flashargs=setenv bootargs initrd=${filesysaddr},${filesyssize} " \ + "root=/dev/ram0 rw rootfstype=squashfs console=${console} " \ + "${optargs}\0" \ + "flashboot=sf probe 0; " \ + "sf read ${fdtaddr} 0x40000 0x10000; " \ + "sf read ${loadaddr} 0x50000 0x400000; " \ + "sf read ${filesysaddr} 0x450000 0xA00000; " \ + "run fdtfixup; " \ + "run fdtboot\0" \ + "loadimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "loadfdt=fatload mmc 0 ${fdtaddr} ${fdtfile}\0" \ + "fdtfixup=fdt addr ${fdtaddr}; fdt resize; fdt chosen\0" \ + "fdtboot=bootm ${loadaddr} - ${fdtaddr}\0" \ + "loadbootscr=fatload mmc 0 ${bootscraddr} boot.scr\0" \ + "bootscript=source ${bootscraddr}\0" + +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + +/* additions for new relocation code, must added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0xc0000000 + +#define CONFIG_SYS_INIT_SP_ADDR 0x80010000 + +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/libretech-ac.h b/roms/u-boot/include/configs/libretech-ac.h new file mode 100644 index 000000000..bf20d3154 --- /dev/null +++ b/roms/u-boot/include/configs/libretech-ac.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for LibreTech AC + * + * Copyright (C) 2017 Baylibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define BOOT_TARGET_DEVICES(func) \ + func(ROMUSB, romusb, na) \ + func(MMC, mmc, 0) \ + BOOT_TARGET_DEVICES_USB(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/linkit-smart-7688.h b/roms/u-boot/include/configs/linkit-smart-7688.h new file mode 100644 index 000000000..e7a7ae319 --- /dev/null +++ b/roms/u-boot/include/configs/linkit-smart-7688.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Stefan Roese + */ + +#ifndef __CONFIG_LINKIT_SMART_7688_H +#define __CONFIG_LINKIT_SMART_7688_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +/* SPL */ +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SPL_BSS_START_ADDR 0x80010000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_PAD_TO 0 + +/* Dummy value */ +#define CONFIG_SYS_UBOOT_BASE 0 + +/* Serial SPL */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_CLK 40000000 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM3 0xb0000e00 + +#endif + +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 460800, 921600 } + +/* RAM */ + +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_CBSIZE 512 + +/* U-Boot */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +/* Environment settings */ + +/* + * Environment is right behind U-Boot in flash. Make sure U-Boot + * doesn't grow into the environment area. + */ +#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET + +#endif /* __CONFIG_LINKIT_SMART_7688_H */ diff --git a/roms/u-boot/include/configs/lion_rk3368.h b/roms/u-boot/include/configs/lion_rk3368.h new file mode 100644 index 000000000..c5b78f9c8 --- /dev/null +++ b/roms/u-boot/include/configs/lion_rk3368.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH + */ + +#ifndef __CONFIGS_LION_RK3368_H +#define __CONFIGS_LION_RK3368_H + +#include + +#define KERNEL_LOAD_ADDR 0x280000 +#define DTB_LOAD_ADDR 0x5600000 +#define INITRD_LOAD_ADDR 0x5bf0000 +/* PHY needs longer aneg time at 1G */ +#define PHY_ANEG_TIMEOUT 8000 + +#endif diff --git a/roms/u-boot/include/configs/liteboard.h b/roms/u-boot/include/configs/liteboard.h new file mode 100644 index 000000000..5adbe1ca3 --- /dev/null +++ b/roms/u-boot/include/configs/liteboard.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2016 Grinn + * + * Configuration settings for the Grinn liteBoard (i.MX6UL). + */ +#ifndef __LITEBOARD_CONFIG_H +#define __LITEBOARD_CONFIG_H + +#include +#include +#include +#include "mx6_common.h" + +/* SPL options */ +#include "imx6_spl.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#ifdef CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_FEC_ENET_DEV 0 + +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#endif + +#endif diff --git a/roms/u-boot/include/configs/ls1012a2g5rdb.h b/roms/u-boot/include/configs/ls1012a2g5rdb.h new file mode 100644 index 000000000..44f9da730 --- /dev/null +++ b/roms/u-boot/include/configs/ls1012a2g5rdb.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017, 2021 NXP + */ + +#ifndef __LS1012A2G5RDB_H__ +#define __LS1012A2G5RDB_H__ + +#include "ls1012a_common.h" + +/* DDR */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 + +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT + +#define CONFIG_SYS_SATA AHCI_BASE_ADDR + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=no\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "kernelheader_addr=0x800000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ + "bootm_size=0x10000000\0" \ + "console=ttyS0,115200\0" \ + BOOTENV \ + "boot_scripts=ls1012ardb_boot.scr\0" \ + "boot_script_hdr=hdr_ls1012ardb_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "installer=load mmc 0:2 $load_addr " \ + "/flex_installer_arm64.itb; " \ + "bootm $load_addr#$board\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_addr $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#endif +#endif + +#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" +#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1" + +#include + +#endif /* __LS1012A2G5RDB_H__ */ diff --git a/roms/u-boot/include/configs/ls1012a_common.h b/roms/u-boot/include/configs/ls1012a_common.h new file mode 100644 index 000000000..6f55acc7d --- /dev/null +++ b/roms/u-boot/include/configs/ls1012a_common.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Freescale Semiconductor + */ + +#ifndef __LS1012A_COMMON_H +#define __LS1012A_COMMON_H + +#define CONFIG_GICV2 + +#include +#include +#include + +#define CONFIG_SYS_CLK_FREQ 125000000 + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +/* CSU */ +#define CONFIG_LAYERSCAPE_NS_ACCESS + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (5 * SZ_1M) + +/* PFE */ +#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x300000 + +/*SPI device */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 + +/* SATA */ +#define CONFIG_SCSI_AHCI_PLAT + +#define CONFIG_SYS_SATA AHCI_BASE_ADDR + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +/* I2C */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) + +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(SCSI, scsi, 0) \ + func(DHCP, dhcp, na) +#include +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=no\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x1000000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "bootm_size=0x10000000\0" \ + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ + "$kernel_start $kernel_size && "\ + "bootm $kernel_load" +#else +#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ + "$kernel_start $kernel_size && "\ + "bootm $kernel_load" +#endif + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#include + +#endif /* __LS1012A_COMMON_H */ diff --git a/roms/u-boot/include/configs/ls1012afrdm.h b/roms/u-boot/include/configs/ls1012afrdm.h new file mode 100644 index 000000000..2711f651d --- /dev/null +++ b/roms/u-boot/include/configs/ls1012afrdm.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __LS1012ARDB_H__ +#define __LS1012ARDB_H__ + +#include "ls1012a_common.h" + +/* DDR */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 + +#ifndef CONFIG_SPL_BUILD +#undef BOOT_TARGET_DEVICES +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) +#endif + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=no\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "scriptaddr=0x80000000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x96000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0x96000000\0" \ + "kernel_size=0x2800000\0" \ + "bootm_size=0x10000000\0" \ + "console=ttyS0,115200\0" \ + BOOTENV \ + "boot_scripts=ls1012afrdm_boot.scr\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "installer=load usb 0:2 $load_addr " \ + "/flex_installer_arm64.itb; " \ + "bootm $load_addr#$board\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_addr $kernel_size && bootm $load_addr#$board\0" + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd" +#else +#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd" +#endif + +#endif /* __LS1012ARDB_H__ */ diff --git a/roms/u-boot/include/configs/ls1012afrwy.h b/roms/u-boot/include/configs/ls1012afrwy.h new file mode 100644 index 000000000..f8b386125 --- /dev/null +++ b/roms/u-boot/include/configs/ls1012afrwy.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018, 2021 NXP + */ + +#ifndef __LS1012AFRWY_H__ +#define __LS1012AFRWY_H__ + +#include "ls1012a_common.h" + +#undef CONFIG_SYS_BOARD +#define CONFIG_SYS_BOARD "ls1012afrwy" + +/* Board Rev*/ +#define BOARD_REV_A_B 0x0 +#define BOARD_REV_C 0x00080000 +#define BOARD_REV_MASK 0x001A0000 +/* DDR */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define SYS_SDRAM_SIZE_512 0x20000000 +#define SYS_SDRAM_SIZE_1024 0x40000000 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 + +/* ENV */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 + +#ifndef CONFIG_SPL_BUILD +#undef BOOT_TARGET_DEVICES +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#endif + +#define CONFIG_PCIE1 /* PCIE controller 1 */ + +#define CONFIG_PCI_SCAN_SHOW + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=no\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "kernel_size_sd=0x16000\0" \ + "kernelhdr_size_sd=0x10\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernelhdr_addr_sd=0x4000\0" \ + "kernelheader_addr=0x1fc000\0" \ + "kernelheader_addr=0x1fc000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernelheader_size=0x40000\0" \ + "kernel_addr_r=0x92000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0x92000000\0" \ + "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ + "bootm_size=0x10000000\0" \ + "console=ttyS0,115200\0" \ + "BOARD=ls1012afrwy\0" \ + BOOTENV \ + "boot_scripts=ls1012afrwy_boot.scr\0" \ + "boot_script_hdr=hdr_ls1012afrwy_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ + "env exists secureboot " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "sd_bootcmd=echo Trying load from sd card..;" \ + "mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#else +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#endif + +#include + +#include +#endif /* __LS1012AFRWY_H__ */ diff --git a/roms/u-boot/include/configs/ls1012aqds.h b/roms/u-boot/include/configs/ls1012aqds.h new file mode 100644 index 000000000..3e5fdadc4 --- /dev/null +++ b/roms/u-boot/include/configs/ls1012aqds.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP + */ + +#ifndef __LS1012AQDS_H__ +#define __LS1012AQDS_H__ + +#include "ls1012a_common.h" + +/* DDR */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 + +/* + * QIXIS Definitions + */ +#define CONFIG_FSL_QIXIS + +#ifdef CONFIG_FSL_QIXIS +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_BRDCFG_REG 0x04 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x08 +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x08 +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#endif + +/* + * I2C bus multiplexer + */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ +#define I2C_RETIMER_ADDR 0x18 +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_CH7301 0xC +#define I2C_MUX_CH5 0xD +#define I2C_MUX_CH7 0xF + +#define I2C_MUX_CH_VOL_MONITOR 0xa + +/* +* RTC configuration +*/ +#define RTC +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +/* DSPI */ +#define CONFIG_FSL_DSPI1 + +#define MMAP_DSPI DSPI1_BASE_ADDR + +#define CONFIG_SYS_DSPI_CTAR0 1 + +#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ + DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ + DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ + DSPI_CTAR_DT(0)) +#define CONFIG_SPI_FLASH_SST /* cs1 */ + +#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ + DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ + DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \ + DSPI_CTAR_DT(0)) +#define CONFIG_SPI_FLASH_STMICRO /* cs2 */ + +#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ + DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ + DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ + DSPI_CTAR_DT(0)) +#define CONFIG_SPI_FLASH_EON /* cs3 */ + +#define CONFIG_PCIE1 /* PCIE controller 1 */ + +#define CONFIG_PCI_SCAN_SHOW + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=no\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "kernelheader_addr=0x600000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x96000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ + "console=ttyS0,115200\0" \ + BOOTENV \ + "boot_scripts=ls1012aqds_boot.scr\0" \ + "boot_script_hdr=hdr_ls1012aqds_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ + "env exists secureboot " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe 0:0 && sf read $load_addr " \ + "$kernel_addr $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#else +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#endif + +#include +#endif /* __LS1012AQDS_H__ */ diff --git a/roms/u-boot/include/configs/ls1012ardb.h b/roms/u-boot/include/configs/ls1012ardb.h new file mode 100644 index 000000000..c8a2f120d --- /dev/null +++ b/roms/u-boot/include/configs/ls1012ardb.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020-2021 NXP + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __LS1012ARDB_H__ +#define __LS1012ARDB_H__ + +#include "ls1012a_common.h" + +/* DDR */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 + +/* + * I2C IO expander + */ + +#define I2C_MUX_IO_ADDR 0x24 +#define I2C_MUX_IO2_ADDR 0x25 +#define I2C_MUX_IO_0 0 +#define I2C_MUX_IO_1 1 +#define SW_BOOT_MASK 0x03 +#define SW_BOOT_EMU 0x02 +#define SW_BOOT_BANK1 0x00 +#define SW_BOOT_BANK2 0x01 +#define SW_REV_MASK 0xF8 +#define SW_REV_A 0xF8 +#define SW_REV_B 0xF0 +#define SW_REV_C 0xE8 +#define SW_REV_C1 0xE0 +#define SW_REV_C2 0xD8 +#define SW_REV_D 0xD0 +#define SW_REV_E 0xC8 +#define __PHY_MASK 0xF9 +#define __PHY_ETH2_MASK 0xFB +#define __PHY_ETH1_MASK 0xFD + +#define CONFIG_PCIE1 /* PCIE controller 1 */ + +#define CONFIG_PCI_SCAN_SHOW + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=no\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "kernelheader_addr=0x600000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x96000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ + "bootm_size=0x10000000\0" \ + "console=ttyS0,115200\0" \ + BOOTENV \ + "boot_scripts=ls1012ardb_boot.scr\0" \ + "boot_script_hdr=hdr_ls1012ardb_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ + "env exists secureboot " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "installer=load mmc 0:2 $load_addr " \ + "/flex_installer_arm64.itb; " \ + "bootm $load_addr#$board\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_addr $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#else +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#endif + +#include + +#endif /* __LS1012ARDB_H__ */ diff --git a/roms/u-boot/include/configs/ls1021aiot.h b/roms/u-boot/include/configs/ls1021aiot.h new file mode 100644 index 000000000..e2ae6e46c --- /dev/null +++ b/roms/u-boot/include/configs/ls1021aiot.h @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + +#define CONFIG_SYS_FSL_CLK + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) + +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +/* + * DDR: 800 MHz ( 1600 MT/s data rate ) + */ + +#define DDR_SDRAM_CFG 0x470c0008 +#define DDR_CS0_BNDS 0x008000bf +#define DDR_CS0_CONFIG 0x80014302 +#define DDR_TIMING_CFG_0 0x50550004 +#define DDR_TIMING_CFG_1 0xbcb38c56 +#define DDR_TIMING_CFG_2 0x0040d120 +#define DDR_TIMING_CFG_3 0x010e1000 +#define DDR_TIMING_CFG_4 0x00000001 +#define DDR_TIMING_CFG_5 0x03401400 +#define DDR_SDRAM_CFG_2 0x00401010 +#define DDR_SDRAM_MODE 0x00061c60 +#define DDR_SDRAM_MODE_2 0x00180000 +#define DDR_SDRAM_INTERVAL 0x18600618 +#define DDR_DDR_WRLVL_CNTL 0x8655f605 +#define DDR_DDR_WRLVL_CNTL_2 0x05060607 +#define DDR_DDR_WRLVL_CNTL_3 0x05050505 +#define DDR_DDR_CDR1 0x80040000 +#define DDR_DDR_CDR2 0x00000001 +#define DDR_SDRAM_CLK_CNTL 0x02000000 +#define DDR_DDR_ZQ_CNTL 0x89080600 +#define DDR_CS0_CONFIG_2 0 +#define DDR_SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG2_D_INIT 0x00000010 +#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 +#define SDRAM_CFG2_FRC_SR 0x80000000 +#define SDRAM_CFG_BI 0x00000001 + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI \ + board/freescale/ls1021aiot/ls102xa_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 + +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + +/* + * I2C + */ + +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* + * MMC + */ + +/* SATA */ +#define CONFIG_SCSI_AHCI_PLAT +#ifndef PCI_DEVICE_ID_FREESCALE_AHCI +#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 +#endif +#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ + PCI_DEVICE_ID_FREESCALE_AHCI} + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +/* SPI */ +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SPI_FLASH_SPANSION +#endif + +/* + * eTSEC + */ + +#ifdef CONFIG_TSEC_ENET +#define CONFIG_MII_DEFAULT_TSEC 1 +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" + +#define TSEC1_PHY_ADDR 1 +#define TSEC2_PHY_ADDR 3 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC2" + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#endif + +/* PCIe */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ + +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" + +#ifdef CONFIG_PCI +#define CONFIG_PCI_SCAN_SHOW +#endif + +#define CONFIG_CMDLINE_TAG + +#define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_LAYERSCAPE_NS_ACCESS +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define COUNTER_FREQUENCY 12500000 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 256 + +#define CONFIG_FSL_DEVICE_DISABLE + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ +"initrd_high=0xffffffff\0" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_LS102XA_STREAM_ID + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +/* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif + +#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 + +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +#include + +#endif diff --git a/roms/u-boot/include/configs/ls1021aqds.h b/roms/u-boot/include/configs/ls1021aqds.h new file mode 100644 index 000000000..7f6584528 --- /dev/null +++ b/roms/u-boot/include/configs/ls1021aqds.h @@ -0,0 +1,486 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_DEEP_SLEEP + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) + +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#define CONFIG_QIXIS_I2C_ACCESS +#else +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#endif + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg +#else +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg +#endif + +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0xc0000 +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg + +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + +#define CONFIG_DDR_SPD +#define SPD_EEPROM_ADDRESS 0x51 +#define CONFIG_SYS_SPD_BUS_NUM 0 + +#ifndef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_DDR_RAW_TIMING +#endif +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +/* + * IFC Definitions + */ +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_FSL_IFC +#define CONFIG_SYS_FLASH_BASE 0x60000000 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) + +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_TRHZ_80) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1a) | \ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0xe) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ + CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} + +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#endif + +/* + * QIXIS Definitions + */ +#define CONFIG_FSL_QIXIS + +#ifdef CONFIG_FSL_QIXIS +#define QIXIS_BASE 0x7fb00000 +#define QIXIS_BASE_PHYS QIXIS_BASE +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_PWR_CTL 0x21 +#define QIXIS_PWR_CTL_POWEROFF 0x80 +#define QIXIS_RST_CTL_RESET 0x44 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_CTL_SYS 0x5 +#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c +#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 +#define QIXIS_RST_FORCE_3 0x45 +#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 +#define QIXIS_PWR_CTL2 0x21 +#define QIXIS_PWR_CTL2_PCTL 0x2 + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* + * QIXIS Timing parameters for IFC GPCM + */ +#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ + FTIM0_GPCM_TEADC(0xe) | \ + FTIM0_GPCM_TEAHC(0xe)) +#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ + FTIM2_GPCM_TCH(0xe) | \ + FTIM2_GPCM_TWP(0xf0)) +#define CONFIG_SYS_FPGA_FTIM3 0x0 +#endif + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#endif + +/* + * Serial Port + */ +#ifdef CONFIG_LPUART +#define CONFIG_LPUART_32B_REG +#else +#define CONFIG_SYS_NS16550_SERIAL +#ifndef CONFIG_DM_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#endif +#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif + +/* + * I2C + */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* + * I2C bus multiplexer + */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_CH7301 0xC + +/* + * MMC + */ + +/* + * Video + */ +#ifdef CONFIG_VIDEO_FSL_DCU_FB +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO + +#define CONFIG_FSL_DIU_CH7301 +#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 +#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 +#define CONFIG_SYS_I2C_DVI_ADDR 0x75 +#endif + +/* + * eTSEC + */ + +#ifdef CONFIG_TSEC_ENET +#define CONFIG_MII_DEFAULT_TSEC 3 +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define TSEC1_PHY_ADDR 1 +#define TSEC2_PHY_ADDR 2 +#define TSEC3_PHY_ADDR 3 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 + +#define CONFIG_FSL_SGMII_RISER 1 +#define SGMII_RISER_PHY_OFFSET 0x1b + +#ifdef CONFIG_FSL_SGMII_RISER +#define CONFIG_SYS_TBIPA_VALUE 8 +#endif + +#endif + +/* PCIe */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_SCAN_SHOW +#endif + +#define CONFIG_CMDLINE_TAG + +#define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_LAYERSCAPE_NS_ACCESS +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define COUNTER_FREQUENCY 12500000 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 256 + +#define CONFIG_FSL_DEVICE_DISABLE + + +#define CONFIG_SYS_QE_FW_ADDR 0x60940000 + +#ifdef CONFIG_LPUART +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ + "initrd_high=0xffffffff\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ + "initrd_high=0xffffffff\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_LS102XA_STREAM_ID + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* + * Environment + */ + +#include +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#endif diff --git a/roms/u-boot/include/configs/ls1021atsn.h b/roms/u-boot/include/configs/ls1021atsn.h new file mode 100644 index 000000000..f76d5a1bd --- /dev/null +++ b/roms/u-boot/include/configs/ls1021atsn.h @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: GPL-2.0 + * Copyright 2016-2019 NXP Semiconductors + * Copyright 2019 Vladimir Oltean + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_DEEP_SLEEP + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) + +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +/* XHCI Support - enabled by default */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define DDR_SDRAM_CFG 0x470c0008 +#define DDR_CS0_BNDS 0x008000bf +#define DDR_CS0_CONFIG 0x80014302 +#define DDR_TIMING_CFG_0 0x50550004 +#define DDR_TIMING_CFG_1 0xbcb38c56 +#define DDR_TIMING_CFG_2 0x0040d120 +#define DDR_TIMING_CFG_3 0x010e1000 +#define DDR_TIMING_CFG_4 0x00000001 +#define DDR_TIMING_CFG_5 0x03401400 +#define DDR_SDRAM_CFG_2 0x00401010 +#define DDR_SDRAM_MODE 0x00061c60 +#define DDR_SDRAM_MODE_2 0x00180000 +#define DDR_SDRAM_INTERVAL 0x18600618 +#define DDR_DDR_WRLVL_CNTL 0x8655f605 +#define DDR_DDR_WRLVL_CNTL_2 0x05060607 +#define DDR_DDR_WRLVL_CNTL_3 0x05050505 +#define DDR_DDR_CDR1 0x80040000 +#define DDR_DDR_CDR2 0x00000001 +#define DDR_SDRAM_CLK_CNTL 0x02000000 +#define DDR_DDR_ZQ_CNTL 0x89080600 +#define DDR_CS0_CONFIG_2 0 +#define DDR_SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG2_D_INIT 0x00000010 +#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 +#define SDRAM_CFG2_FRC_SR 0x80000000 +#define SDRAM_CFG_BI 0x00000001 + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI \ + "board/freescale/ls1021atsn/ls102xa_pbi.cfg" +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW \ + "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg" + +#ifdef CONFIG_NXP_ESBC +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +#endif /* ifdef CONFIG_NXP_ESBC */ + +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#ifdef CONFIG_U_BOOT_HDR_SIZE +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. Here u-boot max. size is 512K. So if binary + * size increases then increase this size in case of secure boot as + * it uses raw U-Boot image instead of FIT image. + */ +#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) +#else +#define CONFIG_SYS_MONITOR_LEN 0x100000 +#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ +#endif + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +/* Serial Port */ +#define CONFIG_SYS_NS16550_SERIAL +#ifndef CONFIG_DM_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#endif +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + +/* I2C */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* QSPI */ +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 + +/* PCIe */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" +#ifdef CONFIG_PCI +#define CONFIG_PCI_SCAN_SHOW +#endif + +#define CONFIG_LAYERSCAPE_NS_ACCESS +#define COUNTER_FREQUENCY 12500000 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 256 + +#define CONFIG_FSL_DEVICE_DISABLE + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_addr=0x64f00000\0" \ + "kernel_addr=0x61000000\0" \ + "kernelheader_addr=0x60800000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x80008000\0" \ + "kernelheader_size=0x40000\0" \ + "fdt_addr_r=0x8f000000\0" \ + "ramdisk_addr_r=0xa0000000\0" \ + "load_addr=0x80008000\0" \ + "kernel_size=0x2800000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernel_size_sd=0x14000\0" \ + "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_size_sd=0x10\0" \ + BOOTENV \ + "boot_scripts=ls1021atsn_boot.scr\0" \ + "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_scripts; " \ + "run scan_dev_for_extlinux; " \ + "done;" \ + "\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_addr $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ + "sd_bootcmd=echo Trying load from SD ..;" \ + "mmcinfo && mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) + +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_LS102XA_STREAM_ID + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* Environment */ + +#define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */ + +#endif diff --git a/roms/u-boot/include/configs/ls1021atwr.h b/roms/u-boot/include/configs/ls1021atwr.h new file mode 100644 index 000000000..d6783db2c --- /dev/null +++ b/roms/u-boot/include/configs/ls1021atwr.h @@ -0,0 +1,458 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_DEEP_SLEEP + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) + +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define DDR_SDRAM_CFG 0x470c0008 +#define DDR_CS0_BNDS 0x008000bf +#define DDR_CS0_CONFIG 0x80014302 +#define DDR_TIMING_CFG_0 0x50550004 +#define DDR_TIMING_CFG_1 0xbcb38c56 +#define DDR_TIMING_CFG_2 0x0040d120 +#define DDR_TIMING_CFG_3 0x010e1000 +#define DDR_TIMING_CFG_4 0x00000001 +#define DDR_TIMING_CFG_5 0x03401400 +#define DDR_SDRAM_CFG_2 0x00401010 +#define DDR_SDRAM_MODE 0x00061c60 +#define DDR_SDRAM_MODE_2 0x00180000 +#define DDR_SDRAM_INTERVAL 0x18600618 +#define DDR_DDR_WRLVL_CNTL 0x8655f605 +#define DDR_DDR_WRLVL_CNTL_2 0x05060607 +#define DDR_DDR_WRLVL_CNTL_3 0x05050505 +#define DDR_DDR_CDR1 0x80040000 +#define DDR_DDR_CDR2 0x00000001 +#define DDR_SDRAM_CLK_CNTL 0x02000000 +#define DDR_DDR_ZQ_CNTL 0x89080600 +#define DDR_CS0_CONFIG_2 0 +#define DDR_SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG2_D_INIT 0x00000010 +#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 +#define SDRAM_CFG2_FRC_SR 0x80000000 +#define SDRAM_CFG_BI 0x00000001 + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg +#else +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg +#endif + +#ifdef CONFIG_NXP_ESBC +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. + */ +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +#endif /* ifdef CONFIG_NXP_ESBC */ + +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#ifdef CONFIG_U_BOOT_HDR_SIZE +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. Here u-boot max. size is 512K. So if binary + * size increases then increase this size in case of secure boot as + * it uses raw u-boot image instead of fit image. + */ +#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) +#else +#define CONFIG_SYS_MONITOR_LEN 0x100000 +#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ +#endif + +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +/* + * IFC Definitions + */ +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_FSL_IFC +#define CONFIG_SYS_FLASH_BASE 0x60000000 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_TRHZ_80) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TAVDS(0x0) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) | \ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWP(0x1c) | \ + FTIM2_NOR_TWPH(0x0e)) +#define CONFIG_SYS_NOR_FTIM3 0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA +#endif + +/* CPLD */ + +#define CONFIG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* CPLD Timing parameters for IFC GPCM */ +#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ + FTIM0_GPCM_TEADC(0xf) | \ + FTIM0_GPCM_TEAHC(0xf)) +#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0xff)) +#define CONFIG_SYS_FPGA_FTIM3 0x0 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 + +/* + * Serial Port + */ +#ifdef CONFIG_LPUART +#define CONFIG_LPUART_32B_REG +#else +#define CONFIG_SYS_NS16550_SERIAL +#ifndef CONFIG_DM_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#endif +#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif + +/* + * I2C + */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* + * MMC + */ + +/* + * Video + */ +#ifdef CONFIG_VIDEO_FSL_DCU_FB +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO + +#define CONFIG_FSL_DCU_SII9022A +#define CONFIG_SYS_I2C_DVI_BUS_NUM 1 +#define CONFIG_SYS_I2C_DVI_ADDR 0x39 +#endif + +/* + * eTSEC + */ + +#ifdef CONFIG_TSEC_ENET +#define CONFIG_ETHPRIME "ethernet@2d10000" +#endif + +/* PCIe */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_SCAN_SHOW +#endif + +#define CONFIG_CMDLINE_TAG + +#define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_LAYERSCAPE_NS_ACCESS +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define COUNTER_FREQUENCY 12500000 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 256 + +#define CONFIG_FSL_DEVICE_DISABLE + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include + +#ifdef CONFIG_LPUART +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \ + "cma=64M@0x0-0xb0000000\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_addr=0x64f00000\0" \ + "kernel_addr=0x65000000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "ramdisk_addr_r=0xa0000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernel_size_sd=0x14000\0" \ + "othbootargs=cma=64M@0x0-0xb0000000\0" \ + BOOTENV \ + "boot_scripts=ls1021atwr_boot.scr\0" \ + "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_scripts; " \ + "done;" \ + "\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ + "env exists secureboot " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "installer=load mmc 0:2 $load_addr " \ + "/flex_installer_arm32.itb; " \ + "bootm $load_addr#ls1021atwr\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ + "nor_bootcmd=echo Trying load from nor..;" \ + "cp.b $kernel_addr $load_addr " \ + "$kernel_size && bootm $load_addr#$board\0" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \ + "cma=64M@0x0-0xb0000000\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_addr=0x64f00000\0" \ + "kernel_addr=0x61000000\0" \ + "kernelheader_addr=0x60800000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x81000000\0" \ + "kernelheader_size=0x40000\0" \ + "fdt_addr_r=0x90000000\0" \ + "ramdisk_addr_r=0xa0000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernel_size_sd=0x14000\0" \ + "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_size_sd=0x10\0" \ + "othbootargs=cma=64M@0x0-0xb0000000\0" \ + BOOTENV \ + "boot_scripts=ls1021atwr_boot.scr\0" \ + "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_scripts; " \ + "done;" \ + "\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_addr $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ + "nor_bootcmd=echo Trying load from nor..;" \ + "cp.b $kernel_addr $load_addr " \ + "$kernel_size; env exists secureboot " \ + "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ + "sd_bootcmd=echo Trying load from SD ..;" \ + "mmcinfo && mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" +#endif + +#undef CONFIG_BOOTCOMMAND +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt" +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \ + "env exists secureboot && esbc_halt;" +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_LS102XA_STREAM_ID + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#define CONFIG_SYS_QE_FW_ADDR 0x60940000 + +/* + * Environment + */ + +#include +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#endif diff --git a/roms/u-boot/include/configs/ls1028a_common.h b/roms/u-boot/include/configs/ls1028a_common.h new file mode 100644 index 000000000..5900b8f0e --- /dev/null +++ b/roms/u-boot/include/configs/ls1028a_common.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019-2021 NXP + */ + +#ifndef __L1028A_COMMON_H +#define __L1028A_COMMON_H + +#define CONFIG_REMAKE_ELF +#define CONFIG_MP + +#include +#include +#include + +/* Link Definitions */ +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 + +/* + * SMP Definitinos + */ +#define CPU_RELEASE_ADDR secondary_boot_addr + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) + +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + +/* I2C */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#endif + +/* Serial Port */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) + +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + +/* Physical Memory Map */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include + +#undef CONFIG_BOOTCOMMAND + +#define XSPI_NOR_BOOTCOMMAND \ + "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define SD_BOOTCOMMAND \ + "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#define SD2_BOOTCOMMAND \ + "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \ + "env exists secureboot && esbc_halt;" + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ + +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#define OCRAM_NONSECURE_SIZE 0x00010000 +#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ +#define I2C_MUX_CH_DEFAULT 0x8 + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* DisplayPort */ +#define DP_PWD_EN_DEFAULT_MASK 0x8 + +#ifdef CONFIG_NXP_ESBC +#include +#endif + +/* Ethernet */ +/* smallest ENETC BD ring has 8 entries */ +#define CONFIG_SYS_RX_ETH_BUFFER 8 + +#endif /* __L1028A_COMMON_H */ diff --git a/roms/u-boot/include/configs/ls1028aqds.h b/roms/u-boot/include/configs/ls1028aqds.h new file mode 100644 index 000000000..9ae37b96c --- /dev/null +++ b/roms/u-boot/include/configs/ls1028aqds.h @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019-2020 NXP + */ + +#ifndef __LS1028A_QDS_H +#define __LS1028A_QDS_H + +#include "ls1028a_common.h" + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) + +/* DDR */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 + +#define CONFIG_QIXIS_I2C_ACCESS + +/* + * QIXIS Definitions + */ +#define CONFIG_FSL_QIXIS + +#ifdef CONFIG_FSL_QIXIS +#define QIXIS_BASE 0x7fb00000 +#define QIXIS_BASE_PHYS QIXIS_BASE +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_SWITCH 1 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 5 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x00 +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_EMMC 0x00 +#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_RCW_SRC_SD 0x8 +#define QIXIS_RCW_SRC_EMMC 0x9 +#define QIXIS_RCW_SRC_QSPI 0xf +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RST_FORCE_MEM 0x01 + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) +#endif + +/* RTC */ +#define CONFIG_SYS_RTC_BUS_NUM 1 +#define I2C_MUX_CH_RTC 0xB + +/* Store environment at top of flash */ + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif + +/* LPUART */ +#ifdef CONFIG_LPUART +#define CONFIG_LPUART_32B_REG +#define CFG_LPUART_MUX_MASK 0xf0 +#define CFG_LPUART_EN 0xf0 +#endif + +/* SATA */ +#define CONFIG_SCSI_AHCI_PLAT + +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#ifndef SPL_NO_ENV +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "board=ls1028aqds\0" \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "fdt2_addr_r=0x90010000\0" \ + "ramdisk_addr_r=0xa0000000\0" \ + "kernel_start=0x1000000\0" \ + "kernelheader_start=0x600000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernel_size_sd=0x14000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ + "kernelhdr_size_sd=0x10\0" \ + "console=ttyS0,115200\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + BOOTENV \ + "boot_scripts=ls1028aqds_boot.scr\0" \ + "boot_script_hdr=hdr_ls1028aqds_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \ + "sf probe 0:0 && sf read $load_addr " \ + "$kernel_start $kernel_size ; env exists secureboot &&" \ + "sf read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + " bootm $load_addr#$board\0" \ + "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \ + "sf probe 0:0 && sf read $load_addr 0x940000 0x30000 " \ + "&& hdp load $load_addr 0x2000\0" \ + "sd_bootcmd=echo Trying load from SD ...;" \ + "mmc dev 0; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" \ + "sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \ + "mmc dev 0;mmcinfo; mmc read $load_addr 0x4a00 0x200 " \ + "&& hdp load $load_addr 0x2000\0" \ + "emmc_bootcmd=echo Trying load from EMMC ..;" \ + "mmc dev 1; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" \ + "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \ + "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \ + "&& hdp load $load_addr 0x2000\0" + +#endif +#endif /* __LS1028A_QDS_H */ diff --git a/roms/u-boot/include/configs/ls1028ardb.h b/roms/u-boot/include/configs/ls1028ardb.h new file mode 100644 index 000000000..1a80cb945 --- /dev/null +++ b/roms/u-boot/include/configs/ls1028ardb.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __LS1028A_RDB_H +#define __LS1028A_RDB_H + +#include "ls1028a_common.h" + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) + +#define CONFIG_SYS_RTC_BUS_NUM 0 + +/* Store environment at top of flash */ + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_QIXIS_I2C_ACCESS + +/* + * QIXIS Definitions + */ +#define CONFIG_FSL_QIXIS + +#ifdef CONFIG_FSL_QIXIS +#define QIXIS_BASE 0x7fb00000 +#define QIXIS_BASE_PHYS QIXIS_BASE +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_SWITCH 2 +#define QIXIS_LBMAP_MASK 0xe0 +#define QIXIS_LBMAP_SHIFT 0x5 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x00 +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_EMMC 0x00 +#define QIXIS_LBMAP_XSPI 0x00 +#define QIXIS_RCW_SRC_SD 0xf8 +#define QIXIS_RCW_SRC_EMMC 0xf9 +#define QIXIS_RCW_SRC_XSPI 0xff +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x10 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x11 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RST_FORCE_MEM 0x01 + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) +#endif + +/* SATA */ +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define SCSI_VEND_ID 0x1b4b +#define SCSI_DEV_ID 0x9170 +#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 + +/* Initial environment variables */ +#ifndef SPL_NO_ENV +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "board=ls1028ardb\0" \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "bootm_size=0x10000000\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "ramdisk_addr_r=0xa0000000\0" \ + "kernel_start=0x1000000\0" \ + "kernelheader_start=0x600000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernel_size_sd=0x14000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ + "kernelhdr_size_sd=0x20\0" \ + "console=ttyS0,115200\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + BOOTENV \ + "boot_scripts=ls1028ardb_boot.scr\0" \ + "boot_script_hdr=hdr_ls1028ardb_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \ + "sf probe 0:0 && sf read $load_addr " \ + "$kernel_start $kernel_size ; env exists secureboot &&" \ + "sf read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + " bootm $load_addr#$board\0" \ + "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \ + "sf probe 0:0 && sf read $load_addr 0x940000 0x30000 " \ + "&& hdp load $load_addr 0x2000\0" \ + "sd_bootcmd=echo Trying load from SD ...;" \ + "mmc dev 0;mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" \ + "sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \ + "mmc dev 0;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \ + "&& hdp load $load_addr 0x2000\0" \ + "emmc_bootcmd=echo Trying load from EMMC ..;" \ + "mmc dev 1;mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" \ + "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \ + "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \ + "&& hdp load $load_addr 0x2000\0" +#endif +#endif /* __LS1028A_RDB_H */ diff --git a/roms/u-boot/include/configs/ls1043a_common.h b/roms/u-boot/include/configs/ls1043a_common.h new file mode 100644 index 000000000..65d63e2fc --- /dev/null +++ b/roms/u-boot/include/configs/ls1043a_common.h @@ -0,0 +1,342 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor + * Copyright 2019-2021 NXP + */ + +#ifndef __LS1043A_COMMON_H +#define __LS1043A_COMMON_H + +/* SPL build */ +#ifdef CONFIG_SPL_BUILD +#define SPL_NO_FMAN +#define SPL_NO_DSPI +#define SPL_NO_PCIE +#define SPL_NO_ENV +#define SPL_NO_MISC +#define SPL_NO_USB +#define SPL_NO_SATA +#define SPL_NO_QE +#define SPL_NO_EEPROM +#endif +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) +#define SPL_NO_MMC +#endif +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI)) +#define SPL_NO_IFC +#endif + +#define CONFIG_REMAKE_ELF +#define CONFIG_GICV2 + +#include +#include + +/* Link Definitions */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL + +#define CPU_RELEASE_ADDR secondary_boot_addr + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) + +/* Serial Port */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) + +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* SD boot SPL */ +#ifdef CONFIG_SD_BOOT + +#define CONFIG_SPL_MAX_SIZE 0x17000 +#define CONFIG_SPL_STACK 0x1001e000 +#define CONFIG_SPL_PAD_TO 0x1d000 + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#ifdef CONFIG_NXP_ESBC +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. Here u-boot max. size is 512K. So if binary + * size increases then increase this size in case of secure boot as + * it uses raw u-boot image instead of fit image. + */ +#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) +#else +#define CONFIG_SYS_MONITOR_LEN 0x100000 +#endif /* ifdef CONFIG_NXP_ESBC */ +#endif + +/* NAND SPL */ +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SPL_PBL_PAD +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#ifdef CONFIG_NXP_ESBC +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +#endif /* ifdef CONFIG_NXP_ESBC */ + +#ifdef CONFIG_U_BOOT_HDR_SIZE +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. Here u-boot max. size is 512K. So if binary + * size increases then increase this size in case of secure boot as + * it uses raw u-boot image instead of fit image. + */ +#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) +#else +#define CONFIG_SYS_MONITOR_LEN 0x100000 +#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ + +#endif + +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + +/* IFC */ +#ifndef SPL_NO_IFC +#if defined(CONFIG_TFABOOT) || \ + (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)) +#define CONFIG_FSL_IFC +/* + * CONFIG_SYS_FLASH_BASE has the final address (core view) + * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting + */ +#define CONFIG_SYS_FLASH_BASE 0x60000000 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 + +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ +#endif +#endif +#endif + +/* I2C */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +/* PCIe */ +#ifndef SPL_NO_PCIE +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_SCAN_SHOW +#endif +#endif + +/* DSPI */ +#ifndef SPL_NO_DSPI +#ifdef CONFIG_FSL_DSPI +#define CONFIG_SPI_FLASH_STMICRO /* cs0 */ +#define CONFIG_SPI_FLASH_SST /* cs1 */ +#define CONFIG_SPI_FLASH_EON /* cs2 */ +#endif +#endif + +/* FMan ucode */ +#ifndef SPL_NO_FMAN +#define CONFIG_SYS_DPAA_FMAN +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 + +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_FMAN_FW_ADDR 0x900000 +#define CONFIG_SYS_QE_FW_ADDR 0x940000 + + +#else +#ifdef CONFIG_NAND_BOOT +/* Store Fman ucode at offeset 0x900000(72 blocks). */ +#define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SD_BOOT) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2040 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800). + */ +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00) +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 +#else +/* FMan fireware Pre-load address */ +#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 +#define CONFIG_SYS_QE_FW_ADDR 0x60940000 +#endif +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +#ifndef SPL_NO_MISC +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr=0x64f00000\0" \ + "kernel_addr=0x61000000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x81000000\0" \ + "kernel_start=0x1000000\0" \ + "kernelheader_start=0x800000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" \ + "kernelheader_addr=0x60600000\0" \ + "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernel_size_sd=0x14000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ + "kernelhdr_size_sd=0x10\0" \ + "console=ttyS0,115200\0" \ + "boot_os=y\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + BOOTENV \ + "boot_scripts=ls1043ardb_boot.scr\0" \ + "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ + "env exists secureboot " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_start $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ + "nor_bootcmd=echo Trying load from nor..;" \ + "cp.b $kernel_addr $load_addr " \ + "$kernel_size; env exists secureboot " \ + "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ + "nand_bootcmd=echo Trying load from NAND..;" \ + "nand info; nand read $load_addr " \ + "$kernel_start $kernel_size; env exists secureboot " \ + "&& nand read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ + "sd_bootcmd=echo Trying load from SD ..;" \ + "mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" + + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#endif +#endif +#endif + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#include + +#endif /* __LS1043A_COMMON_H */ diff --git a/roms/u-boot/include/configs/ls1043aqds.h b/roms/u-boot/include/configs/ls1043aqds.h new file mode 100644 index 000000000..1636f0bb8 --- /dev/null +++ b/roms/u-boot/include/configs/ls1043aqds.h @@ -0,0 +1,402 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __LS1043AQDS_H__ +#define __LS1043AQDS_H__ + +#include "ls1043a_common.h" + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_LAYERSCAPE_NS_ACCESS + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +/* Physical Memory Map */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_DDR_SPD +#define SPD_EEPROM_ADDRESS 0x51 +#define CONFIG_SYS_SPD_BUS_NUM 0 + +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +/* PHY address on QSGMII riser card on slot 1 */ +#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 +#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 +#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 +#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 +/* PHY address on QSGMII riser card on slot 2 */ +#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 +#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 +#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA +#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB +#endif + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg +#else +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg +#endif +#endif + +/* LPUART */ +#ifdef CONFIG_LPUART +#define CONFIG_LPUART_32B_REG +#endif + +/* SATA */ +#define CONFIG_SCSI_AHCI_PLAT + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +#define CONFIG_SYS_SATA AHCI_BASE_ADDR + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +/* + * IFC Definitions + */ +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) + +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_TRHZ_80) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1a) | \ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0xe) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0 + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ + CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) +#endif + +#if defined(CONFIG_TFABOOT) || \ + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_I2C_EARLY_INIT +#endif + +/* + * QIXIS Definitions + */ +#define CONFIG_FSL_QIXIS + +#ifdef CONFIG_FSL_QIXIS +#define QIXIS_BASE 0x7fb00000 +#define QIXIS_BASE_PHYS QIXIS_BASE +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_SD_QSPI 0xff +#define QIXIS_LBMAP_QSPI 0xff +#define QIXIS_RCW_SRC_NAND 0x106 +#define QIXIS_RCW_SRC_SD 0x040 +#define QIXIS_RCW_SRC_QSPI 0x045 +#define QIXIS_RST_CTL_RESET 0x41 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* + * QIXIS Timing parameters for IFC GPCM + */ +#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ + FTIM0_GPCM_TEADC(0x20) | \ + FTIM0_GPCM_TEAHC(0x10)) +#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0xf0)) +#define CONFIG_SYS_FPGA_FTIM3 0x0 +#endif + +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#endif +#endif + +/* + * I2C bus multiplexer + */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ +#define I2C_RETIMER_ADDR 0x18 +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_CH7301 0xC +#define I2C_MUX_CH5 0xD +#define I2C_MUX_CH7 0xF + +#define I2C_MUX_CH_VOL_MONITOR 0xa + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +#define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_VID +#endif +#define CONFIG_VOL_MONITOR_IR36021_SET +#define CONFIG_VOL_MONITOR_INA220 +/* The lowest and highest voltage allowed for LS1043AQDS */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* + * Environment + */ + +#define CONFIG_CMDLINE_TAG + +#include + +#endif /* __LS1043AQDS_H__ */ diff --git a/roms/u-boot/include/configs/ls1043ardb.h b/roms/u-boot/include/configs/ls1043ardb.h new file mode 100644 index 000000000..84b83e625 --- /dev/null +++ b/roms/u-boot/include/configs/ls1043ardb.h @@ -0,0 +1,276 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor + */ + +#ifndef __LS1043ARDB_H__ +#define __LS1043ARDB_H__ + +#include "ls1043a_common.h" + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define CONFIG_LAYERSCAPE_NS_ACCESS + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +/* Physical Memory Map */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_SYS_SPD_BUS_NUM 0 + +#ifndef CONFIG_SPL +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg +#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30 +#endif + +/* + * NOR Flash Definitions + */ +#define CONFIG_SYS_NOR_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CONFIG_SYS_NOR_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_TRHZ_80) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ + FTIM0_NOR_TEADC(0x1) | \ + FTIM0_NOR_TAVDS(0x0) | \ + FTIM0_NOR_TEAHC(0xc)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ + FTIM1_NOR_TRAD_NOR(0xb) | \ + FTIM1_NOR_TSEQRAD_NOR(0x9)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x8) | \ + FTIM2_NOR_TWP(0x10)) +#define CONFIG_SYS_NOR_FTIM3 0 +#define CONFIG_SYS_IFC_CCR 0x01000000 + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +/* + * NAND Flash Definitions + */ +#ifndef SPL_NO_IFC +#define CONFIG_NAND_FSL_IFC +#endif + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10) +#endif + +/* + * CPLD + */ +#define CONFIG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE + +#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) +#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* CPLD Timing parameters for IFC GPCM */ +#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ + FTIM0_GPCM_TEADC(0xf) | \ + FTIM0_GPCM_TEAHC(0xf)) +#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0xff)) +#define CONFIG_SYS_CPLD_FTIM3 0x0 + +/* IFC Timing Params */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#else +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif +#endif + +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 + +/* EEPROM */ +#ifndef SPL_NO_EEPROM +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#endif + +/* + * Environment + */ + +/* FMan */ +#ifndef SPL_NO_FMAN +#define AQR105_IRQ_MASK 0x40000000 + +#ifdef CONFIG_SYS_DPAA_FMAN +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 + +#define QSGMII_PORT1_PHY_ADDR 0x4 +#define QSGMII_PORT2_PHY_ADDR 0x5 +#define QSGMII_PORT3_PHY_ADDR 0x6 +#define QSGMII_PORT4_PHY_ADDR 0x7 + +#define FM1_10GEC1_PHY_ADDR 0x1 + +#define CONFIG_ETHPRIME "FM1@DTSEC3" +#endif +#endif + +/* SATA */ +#ifndef SPL_NO_SATA +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 2 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define SCSI_VEND_ID 0x1b4b +#define SCSI_DEV_ID 0x9170 +#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} +#endif + +#include + +#endif /* __LS1043ARDB_H__ */ diff --git a/roms/u-boot/include/configs/ls1046a_common.h b/roms/u-boot/include/configs/ls1046a_common.h new file mode 100644 index 000000000..11e1a184c --- /dev/null +++ b/roms/u-boot/include/configs/ls1046a_common.h @@ -0,0 +1,311 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Freescale Semiconductor + * Copyright 2019-2021 NXP + */ + +#ifndef __LS1046A_COMMON_H +#define __LS1046A_COMMON_H + +/* SPL build */ +#ifdef CONFIG_SPL_BUILD +#define SPL_NO_QBMAN +#define SPL_NO_FMAN +#define SPL_NO_ENV +#define SPL_NO_MISC +#define SPL_NO_QSPI +#define SPL_NO_USB +#define SPL_NO_SATA +#endif +#if defined(CONFIG_SPL_BUILD) && \ + (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT)) +#define SPL_NO_MMC +#endif +#if defined(CONFIG_SPL_BUILD) && \ + !defined(CONFIG_SPL_FSL_LS_PPA) +#define SPL_NO_IFC +#endif + +#define CONFIG_REMAKE_ELF +#define CONFIG_GICV2 + +#include +#include + +/* Link Definitions */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL + +#define CPU_RELEASE_ADDR secondary_boot_addr + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) + +/* Serial Port */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) + +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* SD boot SPL */ +#ifdef CONFIG_SD_BOOT +#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ +#define CONFIG_SPL_STACK 0x10020000 +#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */ +#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +#ifdef CONFIG_NXP_ESBC +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. Here u-boot max. size is 512K. So if binary + * size increases then increase this size in case of secure boot as + * it uses raw u-boot image instead of fit image. + */ +#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) +#else +#define CONFIG_SYS_MONITOR_LEN 0x100000 +#endif /* ifdef CONFIG_NXP_ESBC */ +#endif + +#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL) +#define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl" +#define CONFIG_SPL_MAX_SIZE 0x1f000 +#define CONFIG_SPL_STACK 0x10020000 +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SYS_MONITOR_LEN 0x100000 +#endif + +/* NAND SPL */ +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SPL_PBL_PAD +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT + +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */ +#define CONFIG_SPL_STACK 0x1001f000 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SYS_MONITOR_LEN 0xa0000 +#endif + +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + +/* I2C */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +/* PCIe */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* SATA */ +#ifndef SPL_NO_SATA +#define CONFIG_SCSI_AHCI_PLAT + +#define CONFIG_SYS_SATA AHCI_BASE_ADDR + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#endif + +/* FMan ucode */ +#ifndef SPL_NO_FMAN +#define CONFIG_SYS_DPAA_FMAN +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#endif + +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_FMAN_FW_ADDR 0x900000 +#else +#ifdef CONFIG_SD_BOOT +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800). + */ +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 +#elif defined(CONFIG_NAND_BOOT) +#define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 +#endif +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(SCSI, scsi, 0) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include +#endif + +#if defined(CONFIG_TARGET_LS1046AFRWY) +#define LS1046A_BOOT_SRC_AND_HDR\ + "boot_scripts=ls1046afrwy_boot.scr\0" \ + "boot_script_hdr=hdr_ls1046afrwy_bs.out\0" +#elif defined(CONFIG_TARGET_LS1046AQDS) +#define LS1046A_BOOT_SRC_AND_HDR\ + "boot_scripts=ls1046aqds_boot.scr\0" \ + "boot_script_hdr=hdr_ls1046aqds_bs.out\0" +#else +#define LS1046A_BOOT_SRC_AND_HDR\ + "boot_scripts=ls1046ardb_boot.scr\0" \ + "boot_script_hdr=hdr_ls1046ardb_bs.out\0" +#endif +#ifndef SPL_NO_MISC +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "bootm_size=0x10000000\0" \ + "fdt_addr=0x64f00000\0" \ + "kernel_addr=0x61000000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "ramdisk_addr_r=0xa0000000\0" \ + "kernel_start=0x1000000\0" \ + "kernelheader_start=0x600000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernel_size_sd=0x14000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ + "kernelhdr_size_sd=0x10\0" \ + "console=ttyS0,115200\0" \ + CONFIG_MTDPARTS_DEFAULT "\0" \ + BOOTENV \ + LS1046A_BOOT_SRC_AND_HDR \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ + "env exists secureboot " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_start $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ + "nand_bootcmd=echo Trying load from nand..;" \ + "nand info; nand read $load_addr " \ + "$kernel_start $kernel_size; env exists secureboot " \ + "&& nand read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ + "nor_bootcmd=echo Trying load from nor..;" \ + "cp.b $kernel_addr $load_addr " \ + "$kernel_size; env exists secureboot " \ + "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ + "sd_bootcmd=echo Trying load from SD ..;" \ + "mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" + +#endif + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#include + +#endif /* __LS1046A_COMMON_H */ diff --git a/roms/u-boot/include/configs/ls1046afrwy.h b/roms/u-boot/include/configs/ls1046afrwy.h new file mode 100644 index 000000000..fade815f2 --- /dev/null +++ b/roms/u-boot/include/configs/ls1046afrwy.h @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019-2020 NXP + */ + +#ifndef __LS1046AFRWY_H__ +#define __LS1046AFRWY_H__ + +#include "ls1046a_common.h" + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define CONFIG_LAYERSCAPE_NS_ACCESS + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_SYS_UBOOT_BASE 0x40100000 + +/* IFC */ +#define CONFIG_FSL_IFC +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* IFC Timing Params */ +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#define I2C_RETIMER_ADDR 0x18 + +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ +#define I2C_MUX_CH_DEFAULT 0x1 /* Channel 0*/ +#define I2C_MUX_CH_RTC 0x1 /* Channel 0*/ + +/* RTC */ +#define RTC +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ +#define CONFIG_SYS_RTC_BUS_NUM 0 + +/* + * Environment + */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 + +#ifndef CONFIG_SPL_BUILD +#undef BOOT_TARGET_DEVICES +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#endif + +/* FMan */ +#ifdef CONFIG_SYS_DPAA_FMAN + +#define QSGMII_PORT1_PHY_ADDR 0x1c +#define QSGMII_PORT2_PHY_ADDR 0x1d +#define QSGMII_PORT3_PHY_ADDR 0x1e +#define QSGMII_PORT4_PHY_ADDR 0x1f + +#define FDT_SEQ_MACADDR_FROM_ENV + +#define CONFIG_ETHPRIME "FM1@DTSEC3" + +#endif + +#undef CONFIG_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" + +#include + +#endif /* __LS1046AFRWY_H__ */ diff --git a/roms/u-boot/include/configs/ls1046aqds.h b/roms/u-boot/include/configs/ls1046aqds.h new file mode 100644 index 000000000..9102c812b --- /dev/null +++ b/roms/u-boot/include/configs/ls1046aqds.h @@ -0,0 +1,443 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __LS1046AQDS_H__ +#define __LS1046AQDS_H__ + +#include "ls1046a_common.h" + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_LAYERSCAPE_NS_ACCESS + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +/* Physical Memory Map */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_DDR_SPD +#define SPD_EEPROM_ADDRESS 0x51 +#define CONFIG_SYS_SPD_BUS_NUM 0 + +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +/* DSPI */ +#ifdef CONFIG_FSL_DSPI +#define CONFIG_SPI_FLASH_STMICRO /* cs0 */ +#define CONFIG_SPI_FLASH_SST /* cs1 */ +#define CONFIG_SPI_FLASH_EON /* cs2 */ +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +/* PHY address on QSGMII riser card on slot 2 */ +#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 +#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 +#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA +#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB +#endif + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI \ + board/freescale/ls1046aqds/ls1046aqds_pbi.cfg +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg +#else +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg +#endif +#endif + +/* IFC */ +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_FSL_IFC +/* + * CONFIG_SYS_FLASH_BASE has the final address (core view) + * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting + */ +#define CONFIG_SYS_FLASH_BASE 0x60000000 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 + +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ +#endif +#endif + +/* LPUART */ +#ifdef CONFIG_LPUART +#define CONFIG_LPUART_32B_REG +#define CFG_UART_MUX_MASK 0x6 +#define CFG_UART_MUX_SHIFT 1 +#define CFG_LPUART_EN 0x2 +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* + * IFC Definitions + */ +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) + +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_TRHZ_80) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TAVDS(0x6) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1a) | \ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ + FTIM2_NOR_TCH(0x8) | \ + FTIM2_NOR_TWPH(0xe) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0 + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ + CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#endif + +#if defined(CONFIG_TFABOOT) || \ + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_I2C_EARLY_INIT +#endif + +/* + * QIXIS Definitions + */ +#define CONFIG_FSL_QIXIS + +#ifdef CONFIG_FSL_QIXIS +#define QIXIS_BASE 0x7fb00000 +#define QIXIS_BASE_PHYS QIXIS_BASE +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_SD_QSPI 0xff +#define QIXIS_LBMAP_QSPI 0xff +#define QIXIS_RCW_SRC_NAND 0x110 +#define QIXIS_RCW_SRC_SD 0x040 +#define QIXIS_RCW_SRC_QSPI 0x045 +#define QIXIS_RST_CTL_RESET 0x41 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* + * QIXIS Timing parameters for IFC GPCM + */ +#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ + FTIM0_GPCM_TEADC(0x20) | \ + FTIM0_GPCM_TEAHC(0x10)) +#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0xf0)) +#define CONFIG_SYS_FPGA_FTIM3 0x0 +#endif + +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#endif +#endif + +/* + * I2C bus multiplexer + */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ +#define I2C_RETIMER_ADDR 0x18 +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_CH7301 0xC +#define I2C_MUX_CH5 0xD +#define I2C_MUX_CH6 0xE +#define I2C_MUX_CH7 0xF + +#define I2C_MUX_CH_VOL_MONITOR 0xa + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +#define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_VID +#endif +#define CONFIG_VOL_MONITOR_IR36021_SET +#define CONFIG_VOL_MONITOR_INA220 +/* The lowest and highest voltage allowed for LS1046AQDS */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +/* + * Environment + */ + +#define CONFIG_CMDLINE_TAG + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd" \ + "env exists secureboot && esbc_halt;;" +#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#else +#if defined(CONFIG_QSPI_BOOT) +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#elif defined(CONFIG_NAND_BOOT) +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#else +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#endif +#endif + +#include + +#endif /* __LS1046AQDS_H__ */ diff --git a/roms/u-boot/include/configs/ls1046ardb.h b/roms/u-boot/include/configs/ls1046ardb.h new file mode 100644 index 000000000..dddaa2541 --- /dev/null +++ b/roms/u-boot/include/configs/ls1046ardb.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Freescale Semiconductor + * Copyright 2019 NXP + */ + +#ifndef __LS1046ARDB_H__ +#define __LS1046ARDB_H__ + +#include "ls1046a_common.h" + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define CONFIG_LAYERSCAPE_NS_ACCESS + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +/* Physical Memory Map */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_DDR_SPD +#define SPD_EEPROM_ADDRESS 0x51 +#define CONFIG_SYS_SPD_BUS_NUM 0 + +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg +#ifdef CONFIG_EMMC_BOOT +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg +#else +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg +#endif +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg +#define CONFIG_SYS_FSL_PBL_PBI \ + board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg +#define CONFIG_SYS_UBOOT_BASE 0x40100000 +#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 +#endif + +#ifndef SPL_NO_IFC +/* IFC */ +#define CONFIG_FSL_IFC +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC +#endif + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* + * CPLD + */ +#define CONFIG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE + +#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) +#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) + +/* CPLD Timing parameters for IFC GPCM */ +#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0x3E)) +#define CONFIG_SYS_CPLD_FTIM3 0x0 + +/* IFC Timing Params */ +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#define I2C_RETIMER_ADDR 0x18 + +/* PMIC */ +#define CONFIG_POWER +#ifdef CONFIG_POWER +#define CONFIG_POWER_I2C +#endif + +/* + * Environment + */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 + +#define AQR105_IRQ_MASK 0x80000000 +/* FMan */ +#ifndef SPL_NO_FMAN +#ifdef CONFIG_SYS_DPAA_FMAN +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 + +#define SGMII_PHY1_ADDR 0x3 +#define SGMII_PHY2_ADDR 0x4 + +#define FM1_10GEC1_PHY_ADDR 0x0 + +#define FDT_SEQ_MACADDR_FROM_ENV + +#define CONFIG_ETHPRIME "FM1@DTSEC3" +#endif + +#endif + +#ifndef SPL_NO_MISC +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else +#if defined(CONFIG_QSPI_BOOT) +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#endif +#endif +#endif + +#include + +#endif /* __LS1046ARDB_H__ */ diff --git a/roms/u-boot/include/configs/ls1088a_common.h b/roms/u-boot/include/configs/ls1088a_common.h new file mode 100644 index 000000000..d574e7e59 --- /dev/null +++ b/roms/u-boot/include/configs/ls1088a_common.h @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2018 NXP + */ + +#ifndef __LS1088_COMMON_H +#define __LS1088_COMMON_H + +/* SPL build */ +#ifdef CONFIG_SPL_BUILD +#define SPL_NO_BOARDINFO +#define SPL_NO_QIXIS +#define SPL_NO_PCI +#define SPL_NO_ENV +#define SPL_NO_RTC +#define SPL_NO_USB +#define SPL_NO_SATA +#define SPL_NO_QSPI +#define SPL_NO_IFC +#undef CONFIG_DISPLAY_CPUINFO +#endif + +#define CONFIG_REMAKE_ELF + +#include +#include +#include + +#define LS1088ARDB_PB_BOARD 0x4A +/* Link Definitions */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif + +/* Link Definitions */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 +/* + * SMP Definitinos + */ +#define CPU_RELEASE_ADDR secondary_boot_addr + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) + +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + +/* I2C */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#endif + + +/* Serial Port */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) + +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS) +/* IFC */ +#define CONFIG_FSL_IFC +#endif + +/* + * During booting, IFC is mapped at the region of 0x30000000. + * But this region is limited to 256MB. To accommodate NOR, promjet + * and FPGA. This region is divided as below: + * 0x30000000 - 0x37ffffff : 128MB : NOR flash + * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet + * 0x3C000000 - 0x40000000 : 64MB : FPGA etc + * + * To accommodate bigger NOR flash and other devices, we will map IFC + * chip selects to as below: + * 0x5_1000_0000..0x5_1fff_ffff Memory Hole + * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) + * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB + * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) + * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) + * + * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. + * CONFIG_SYS_FLASH_BASE has the final address (core view) + * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting + */ + +#define CONFIG_SYS_FLASH_BASE 0x580000000ULL +#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 +#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 + +#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 +#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 + +#ifndef __ASSEMBLY__ +unsigned long long get_qixis_addr(void); +#endif + +#define QIXIS_BASE get_qixis_addr() +#define QIXIS_BASE_PHYS 0x20000000 +#define QIXIS_BASE_PHYS_EARLY 0xC000000 + + +#define CONFIG_SYS_NAND_BASE 0x530000000ULL +#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 + + +/* MC firmware */ +/* TODO Actual DPL max length needs to be confirmed with the MC FW team */ +#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 +#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 + +/* Define phy_reset function to boot the MC based on mcinitcmd. + * This happens late enough to properly fixup u-boot env MAC addresses. + */ +#define CONFIG_RESET_PHY_R + +/* + * Carve out a DDR region which will not be used by u-boot/Linux + * + * It will be used by MC and Debug Server. The MC region must be + * 512MB aligned, so the min size to hide is 512MB. + */ + +#if defined(CONFIG_FSL_MC_ENET) +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + +/* SATA */ +#ifdef CONFIG_SCSI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#endif + +/* Physical Memory Map */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +/* #define CONFIG_DISPLAY_CPUINFO */ + +#ifndef SPL_NO_ENV +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x581000000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "console=ttyAMA0,38400n8\0" \ + "mcinitcmd=fsl_mc start mc 0x580a00000" \ + " 0x580e00000 \0" + +#ifndef CONFIG_TFABOOT +#if defined(CONFIG_QSPI_BOOT) +#define CONFIG_BOOTCOMMAND "sf probe 0:0;" \ + "sf read 0x80001000 0xd00000 0x100000;"\ + " fsl_mc lazyapply dpl 0x80001000 &&" \ + " sf read $kernel_load $kernel_start" \ + " $kernel_size && bootm $kernel_load" +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\ + " fsl_mc lazyapply dpl 0x80001000 &&" \ + " mmc read $kernel_load $kernel_start" \ + " $kernel_size && bootm $kernel_load" +#else /* NOR BOOT*/ +#define CONFIG_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \ + " cp.b $kernel_start $kernel_load" \ + " $kernel_size && bootm $kernel_load" +#endif +#endif /* CONFIG_TFABOOT */ +#endif + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#ifdef CONFIG_SPL +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_MAX_SIZE 0x16000 +#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" + +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 + +#ifdef CONFIG_NXP_ESBC +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. Here u-boot max. size is 512K. So if binary + * size increases then increase this size in case of secure boot as + * it uses raw u-boot image instead of fit image. + */ +#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) +#else +#define CONFIG_SYS_MONITOR_LEN 0x100000 +#endif /* ifdef CONFIG_NXP_ESBC */ + +#endif +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#endif /* __LS1088_COMMON_H */ diff --git a/roms/u-boot/include/configs/ls1088aqds.h b/roms/u-boot/include/configs/ls1088aqds.h new file mode 100644 index 000000000..d032a3d11 --- /dev/null +++ b/roms/u-boot/include/configs/ls1088aqds.h @@ -0,0 +1,574 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017, 2020-2021 NXP + */ + +#ifndef __LS1088A_QDS_H +#define __LS1088A_QDS_H + +#include "ls1088a_common.h" + + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#ifdef CONFIG_TFABOOT +#define CONFIG_MISC_INIT_R +#endif + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_QIXIS_I2C_ACCESS +#define SYS_NO_FLASH + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#else +#define CONFIG_QIXIS_I2C_ACCESS +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C_EARLY_INIT +#endif +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#endif + +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +#define CONFIG_DDR_SPD +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS 0x51 +#define CONFIG_SYS_SPD_BUS_NUM 0 + + +/* + * IFC Definitions + */ +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) + +#define CONFIG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TAVDS(0x6) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1a) | \ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ + FTIM2_NOR_TCH(0x8) | \ + FTIM2_NOR_TWPH(0xe) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CONFIG_SYS_IFC_CCR 0x01000000 + +#ifndef SYS_NO_FLASH +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ + CONFIG_SYS_FLASH_BASE + 0x40000000} +#endif +#endif + +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#define CONFIG_FSL_QIXIS +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_QMAP_MASK 0xe0 +#define QIXIS_QMAP_SHIFT 5 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x0e +#define QIXIS_LBMAP_ALTBANK 0x2e +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_EMMC 0x00 +#define QIXIS_LBMAP_IFC 0x00 +#define QIXIS_LBMAP_SD_QSPI 0x0e +#define QIXIS_LBMAP_QSPI 0x0e +#define QIXIS_RCW_SRC_IFC 0x25 +#define QIXIS_RCW_SRC_SD 0x40 +#define QIXIS_RCW_SRC_EMMC 0x41 +#define QIXIS_RCW_SRC_QSPI 0x62 +#define QIXIS_RST_CTL_RESET 0x41 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RST_FORCE_MEM 0x01 +#define QIXIS_STAT_PRES1 0xb +#define QIXIS_SDID_MASK 0x07 +#define QIXIS_ESDHC_NO_ADAPTER 0x7 + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) + +#define SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) +#else +#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) +#endif +/* QIXIS Timing parameters*/ +#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0x3E)) +#define SYS_FPGA_CS_FTIM3 0x0 + +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY +#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY +#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL +#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 +#else +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL +#define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY +#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY +#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL +#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 +#endif +#endif + +#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 + +/* + * I2C bus multiplexer + */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ +#define I2C_RETIMER_ADDR 0x18 +#define I2C_RETIMER_ADDR2 0x19 +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH5 0xD + +#define I2C_MUX_CH_VOL_MONITOR 0xA + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x63 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 +#define I2C_SVDD_MONITOR_ADDR 0x4F + +#define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv" +#define CONFIG_VID + +/* The lowest and highest voltage allowed for LS1088AQDS */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + +#define CONFIG_VOL_MONITOR_LTC3882_SET +#define CONFIG_VOL_MONITOR_LTC3882_READ + +#define PWM_CHANNEL0 0x0 + +/* +* RTC configuration +*/ +#define RTC +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +#ifdef CONFIG_FSL_DSPI +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_EON +#if !defined(CONFIG_TFABOOT) && \ + !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#endif +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif + +#define CONFIG_FSL_MEMAC + +/* MMC */ +#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ + QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) + +#define COMMON_ENV \ + "kernelheader_addr_r=0x80200000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" + +/* Initial environment variables */ +#ifdef CONFIG_NXP_ESBC +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x90100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x1000000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ + "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \ + "sf read 0xa0e00000 0xe00000 0x100000;" \ + "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \ + "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \ + "mcmemsize=0x70000000 \0" +#else /* if !(CONFIG_NXP_ESBC) */ +#ifdef CONFIG_TFABOOT +#define QSPI_MC_INIT_CMD \ + "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ + "sf read 0x80100000 0xE00000 0x100000;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" +#define SD_MC_INIT_CMD \ + "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ + "mmc read 0x80100000 0x7000 0x800;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" +#define IFC_MC_INIT_CMD \ + "fsl_mc start mc 0x580A00000 0x580E00000\0" + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x90100000\0" \ + "kernel_addr=0x100000\0" \ + "kernel_addr_sd=0x800\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x1000000\0" \ + "kernel_start_sd=0x8000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernel_size_sd=0x14000\0" \ + "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ + "sf read 0x80100000 0xE00000 0x100000;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" \ + "mcmemsize=0x70000000 \0" \ + "BOARD=ls1088aqds\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + BOOTENV \ + "boot_scripts=ls1088aqds_boot.scr\0" \ + "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr}; "\ + "env exists secureboot " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "qspi_bootcmd=echo Trying load from qspi..; " \ + "sf probe 0:0; " \ + "sf read 0x80001000 0xd00000 0x100000; " \ + "fsl_mc lazyapply dpl 0x80001000 && " \ + "sf read $kernel_load $kernel_start " \ + "$kernel_size && bootm $kernel_load#$BOARD\0" \ + "sd_bootcmd=echo Trying load from sd card..; " \ + "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\ + "fsl_mc lazyapply dpl 0x80001000 && " \ + "mmc read $kernel_load $kernel_start_sd " \ + "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \ + "nor_bootcmd=echo Trying load from nor..; " \ + "fsl_mc lazyapply dpl 0x580d00000 && " \ + "cp.b $kernel_start $kernel_load " \ + "$kernel_size && bootm $kernel_load#$BOARD\0" +#else +#if defined(CONFIG_QSPI_BOOT) +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x90100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x1000000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ + "sf read 0x80100000 0xE00000 0x100000;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" \ + "mcmemsize=0x70000000 \0" +#elif defined(CONFIG_SD_BOOT) +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x90100000\0" \ + "kernel_addr=0x800\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x8000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x14000\0" \ + "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ + "mmc read 0x80100000 0x7000 0x800;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" \ + "mcmemsize=0x70000000 \0" +#else /* NOR BOOT */ +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x90100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x1000000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ + "mcmemsize=0x70000000 \0" +#endif +#endif /* CONFIG_TFABOOT */ +#endif /* CONFIG_NXP_ESBC */ + +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#endif + +#ifdef CONFIG_FSL_MC_ENET +#define CONFIG_FSL_MEMAC +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1d +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F + +#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 +#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 +#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 +#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 +#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 +#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 +#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 +#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 +#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 +#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 +#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa +#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb +#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc +#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd +#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe +#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf + +#define CONFIG_ETHPRIME "DPMAC1@xgmii" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +#endif + +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 0) \ + func(SCSI, scsi, 0) \ + func(DHCP, dhcp, na) +#include + +#include + +#endif /* __LS1088A_QDS_H */ diff --git a/roms/u-boot/include/configs/ls1088ardb.h b/roms/u-boot/include/configs/ls1088ardb.h new file mode 100644 index 000000000..5ade0eb43 --- /dev/null +++ b/roms/u-boot/include/configs/ls1088ardb.h @@ -0,0 +1,522 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017, 2020-2021 NXP + */ + +#ifndef __LS1088A_RDB_H +#define __LS1088A_RDB_H + +#include "ls1088a_common.h" + +#if defined(CONFIG_TFABOOT) || \ + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#ifndef CONFIG_SPL_BUILD +#define CONFIG_QIXIS_I2C_ACCESS +#endif +#define SYS_NO_FLASH +#endif + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +#define CONFIG_DDR_SPD +#ifdef CONFIG_EMU +#define CONFIG_SYS_FSL_DDR_EMU +#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 +#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 +#else +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif +#define SPD_EEPROM_ADDRESS 0x51 +#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + + +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) + +#define CONFIG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ + FTIM0_NOR_TEADC(0x1) | \ + FTIM0_NOR_TEAHC(0x1)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ + FTIM1_NOR_TRAD_NOR(0x1)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ + FTIM2_NOR_TCH(0x0) | \ + FTIM2_NOR_TWP(0x1)) +#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CONFIG_SYS_IFC_CCR 0x01000000 + +#ifndef SYS_NO_FLASH +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#endif +#endif + +#ifndef SPL_NO_IFC +#define CONFIG_NAND_FSL_IFC +#endif + +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#ifndef SPL_NO_QIXIS +#define CONFIG_FSL_QIXIS +#endif + +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_BRDCFG4_OFFSET 0x54 +#define QIXIS_LBMAP_SWITCH 2 +#define QIXIS_QMAP_MASK 0xe0 +#define QIXIS_QMAP_SHIFT 5 +#define QIXIS_LBMAP_MASK 0x1f +#define QIXIS_LBMAP_SHIFT 5 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x20 +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_EMMC 0x00 +#define QIXIS_LBMAP_SD_QSPI 0x00 +#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_RCW_SRC_SD 0x40 +#define QIXIS_RCW_SRC_EMMC 0x41 +#define QIXIS_RCW_SRC_QSPI 0x62 +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RST_FORCE_MEM 0x01 + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) + +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) +/* QIXIS Timing parameters*/ +#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0x3E)) +#define SYS_FPGA_CS_FTIM3 0x0 + +#if defined(CONFIG_TFABOOT) || \ + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL +#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#endif + +#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 + +#define I2C_MUX_CH_VOL_MONITOR 0xA +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x63 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 +#define I2C_SVDD_MONITOR_ADDR 0x4F + +#define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv" +#define CONFIG_VID + +/* The lowest and highest voltage allowed for LS1088ARDB */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + +#define CONFIG_VOL_MONITOR_LTC3882_SET +#define CONFIG_VOL_MONITOR_LTC3882_READ + +#define PWM_CHANNEL0 0x0 + +/* + * I2C bus multiplexer + */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ +#define I2C_RETIMER_ADDR 0x18 +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH5 0xD + +#ifndef SPL_NO_RTC +/* +* RTC configuration +*/ +#define RTC +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif + +#define CONFIG_FSL_MEMAC + +#ifndef SPL_NO_ENV +/* Initial environment variables */ +#ifdef CONFIG_TFABOOT +#define QSPI_MC_INIT_CMD \ + "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ + "sf read 0x80100000 0xE00000 0x100000;" \ + "env exists secureboot && " \ + "sf read 0x80640000 0x640000 0x40000 && " \ + "sf read 0x80680000 0x680000 0x40000 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" +#define SD_MC_INIT_CMD \ + "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ + "mmc read 0x80100000 0x7000 0x800;" \ + "env exists secureboot && " \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" +#else +#if defined(CONFIG_QSPI_BOOT) +#define MC_INIT_CMD \ + "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ + "sf read 0x80100000 0xE00000 0x100000;" \ + "env exists secureboot && " \ + "sf read 0x80640000 0x640000 0x40000 && " \ + "sf read 0x80680000 0x680000 0x40000 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" \ + "mcmemsize=0x70000000\0" +#elif defined(CONFIG_SD_BOOT) +#define MC_INIT_CMD \ + "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ + "mmc read 0x80100000 0x7000 0x800;" \ + "env exists secureboot && " \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" \ + "mcmemsize=0x70000000\0" +#endif +#endif /* CONFIG_TFABOOT */ + +#undef CONFIG_EXTRA_ENV_SETTINGS +#ifdef CONFIG_TFABOOT +#define CONFIG_EXTRA_ENV_SETTINGS \ + "BOARD=ls1088ardb\0" \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr=0x64f00000\0" \ + "kernel_addr=0x1000000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ + "kernel_start=0x580100000\0" \ + "kernelheader_start=0x580600000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr=0x600000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x81000000\0" \ + "kernelheader_size=0x40000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernel_size_sd=0x14000\0" \ + "kernelhdr_size_sd=0x20\0" \ + QSPI_MC_INIT_CMD \ + "mcmemsize=0x70000000\0" \ + BOOTENV \ + "boot_scripts=ls1088ardb_boot.scr\0" \ + "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr}; "\ + "env exists secureboot " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "installer=load mmc 0:2 $load_addr " \ + "/flex_installer_arm64.itb; " \ + "env exists mcinitcmd && run mcinitcmd && " \ + "mmc read 0x80001000 0x6800 0x800;" \ + "fsl_mc lazyapply dpl 0x80001000;" \ + "bootm $load_addr#ls1088ardb\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_addr $kernel_size ; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + "bootm $load_addr#$BOARD\0" \ + "sd_bootcmd=echo Trying load from sd card..;" \ + "mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "BOARD=ls1088ardb\0" \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr=0x64f00000\0" \ + "kernel_addr=0x1000000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ + "kernel_start=0x580100000\0" \ + "kernelheader_start=0x580800000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr=0x600000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x81000000\0" \ + "kernelheader_size=0x40000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernel_size_sd=0x14000\0" \ + "kernelhdr_size_sd=0x20\0" \ + MC_INIT_CMD \ + BOOTENV \ + "boot_scripts=ls1088ardb_boot.scr\0" \ + "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "installer=load mmc 0:2 $load_addr " \ + "/flex_installer_arm64.itb; " \ + "env exists mcinitcmd && run mcinitcmd && " \ + "mmc read 0x80001000 0x6800 0x800;" \ + "fsl_mc lazyapply dpl 0x80001000;" \ + "bootm $load_addr#ls1088ardb\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_addr $kernel_size ; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + "bootm $load_addr#$BOARD\0" \ + "sd_bootcmd=echo Trying load from sd card..;" \ + "mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" +#endif /* CONFIG_TFABOOT */ + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND \ + "sf read 0x80001000 0xd00000 0x100000;" \ + "env exists mcinitcmd && env exists secureboot " \ + " && sf read 0x806C0000 0x6C0000 0x100000 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ + "&& fsl_mc lazyapply dpl 0x80001000;" \ + "run distro_bootcmd;run qspi_bootcmd;" \ + "env exists secureboot && esbc_halt;" +#define SD_BOOTCOMMAND \ + "env exists mcinitcmd && mmcinfo; " \ + "mmc read 0x80001000 0x6800 0x800; " \ + "env exists mcinitcmd && env exists secureboot " \ + " && mmc read 0x806C0000 0x3600 0x20 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ + "&& fsl_mc lazyapply dpl 0x80001000;" \ + "run distro_bootcmd;run sd_bootcmd;" \ + "env exists secureboot && esbc_halt;" +#else +#if defined(CONFIG_QSPI_BOOT) +/* Try to boot an on-QSPI kernel first, then do normal distro boot */ +#define CONFIG_BOOTCOMMAND \ + "sf read 0x80001000 0xd00000 0x100000;" \ + "env exists mcinitcmd && env exists secureboot " \ + " && sf read 0x806C0000 0x6C0000 0x100000 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ + "&& fsl_mc lazyapply dpl 0x80001000;" \ + "run distro_bootcmd;run qspi_bootcmd;" \ + "env exists secureboot && esbc_halt;" + +/* Try to boot an on-SD kernel first, then do normal distro boot */ +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_BOOTCOMMAND \ + "env exists mcinitcmd && mmcinfo; " \ + "mmc read 0x80001000 0x6800 0x800; " \ + "env exists mcinitcmd && env exists secureboot " \ + " && mmc read 0x806C0000 0x3600 0x20 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ + "&& fsl_mc lazyapply dpl 0x80001000;" \ + "run distro_bootcmd;run sd_bootcmd;" \ + "env exists secureboot && esbc_halt;" +#endif +#endif /* CONFIG_TFABOOT */ + +/* MAC/PHY configuration */ +#ifdef CONFIG_FSL_MC_ENET +#define AQ_PHY_ADDR1 0x00 +#define AQR105_IRQ_MASK 0x00000004 + +#define QSGMII1_PORT1_PHY_ADDR 0x0c +#define QSGMII1_PORT2_PHY_ADDR 0x0d +#define QSGMII1_PORT3_PHY_ADDR 0x0e +#define QSGMII1_PORT4_PHY_ADDR 0x0f +#define QSGMII2_PORT1_PHY_ADDR 0x1c +#define QSGMII2_PORT2_PHY_ADDR 0x1d +#define QSGMII2_PORT3_PHY_ADDR 0x1e +#define QSGMII2_PORT4_PHY_ADDR 0x1f + +#define CONFIG_ETHPRIME "DPMAC1@xgmii" +#define CONFIG_PHY_GIGE +#endif +#endif + +#ifndef SPL_NO_ENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(SCSI, scsi, 0) \ + func(DHCP, dhcp, na) +#include +#endif + +#include + +#endif /* __LS1088A_RDB_H */ diff --git a/roms/u-boot/include/configs/ls2080a_common.h b/roms/u-boot/include/configs/ls2080a_common.h new file mode 100644 index 000000000..2ed658407 --- /dev/null +++ b/roms/u-boot/include/configs/ls2080a_common.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + * Copyright (C) 2014 Freescale Semiconductor + */ + +#ifndef __LS2_COMMON_H +#define __LS2_COMMON_H + +#define CONFIG_REMAKE_ELF +#define CONFIG_GICV3 + +#include +#include + +/* Link Definitions */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif + +/* We need architecture specific misc initializations */ + +/* Link Definitions */ + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#ifndef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_DDR_RAW_TIMING +#endif + +#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ + +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 + +/* + * SMP Definitinos + */ +#define CPU_RELEASE_ADDR secondary_boot_addr + +#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR +#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL +/* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ +#define CONFIG_SYS_DP_DDR_BASE_PHY 0 +#define CONFIG_DP_DDR_CTRL 2 +#define CONFIG_DP_DDR_NUM_CTRLS 1 +#endif + +/* Generic Timer Definitions */ +/* + * This is not an accurate number. It is used in start.S. The frequency + * will be udpated later when get_bus_freq(0) is available. + */ +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) + +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + +/* I2C */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#endif + +/* Serial Port */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) + +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* IFC */ +#define CONFIG_FSL_IFC + +/* + * During booting, IFC is mapped at the region of 0x30000000. + * But this region is limited to 256MB. To accommodate NOR, promjet + * and FPGA. This region is divided as below: + * 0x30000000 - 0x37ffffff : 128MB : NOR flash + * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet + * 0x3C000000 - 0x40000000 : 64MB : FPGA etc + * + * To accommodate bigger NOR flash and other devices, we will map IFC + * chip selects to as below: + * 0x5_1000_0000..0x5_1fff_ffff Memory Hole + * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) + * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB + * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) + * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) + * + * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. + * CONFIG_SYS_FLASH_BASE has the final address (core view) + * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting + */ + +#define CONFIG_SYS_FLASH_BASE 0x580000000ULL +#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 +#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 + +#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 +#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 + +#ifndef __ASSEMBLY__ +unsigned long long get_qixis_addr(void); +#endif +#define QIXIS_BASE get_qixis_addr() +#define QIXIS_BASE_PHYS 0x20000000 +#define QIXIS_BASE_PHYS_EARLY 0xC000000 +#define QIXIS_STAT_PRES1 0xb +#define QIXIS_SDID_MASK 0x07 +#define QIXIS_ESDHC_NO_ADAPTER 0x7 + +#define CONFIG_SYS_NAND_BASE 0x530000000ULL +#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 + +/* MC firmware */ +/* TODO Actual DPL max length needs to be confirmed with the MC FW team */ +#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +/* For LS2085A */ +#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 +#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 + +/* Define phy_reset function to boot the MC based on mcinitcmd. + * This happens late enough to properly fixup u-boot env MAC addresses. + */ +#define CONFIG_RESET_PHY_R + +/* + * Carve out a DDR region which will not be used by u-boot/Linux + * + * It will be used by MC and Debug Server. The MC region must be + * 512MB aligned, so the min size to hide is 512MB. + */ +#ifdef CONFIG_FSL_MC_ENET +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + +/* Physical Memory Map */ +/* fixme: these need to be checked against the board */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x581000000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "console=ttyAMA0,38400n8\0" \ + "mcinitcmd=fsl_mc start mc 0x580a00000" \ + " 0x580e00000 \0" + +#ifndef CONFIG_TFABOOT +#ifdef CONFIG_SD_BOOT +#define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\ + " fsl_mc apply dpl 0x80200000 &&" \ + " mmc read $kernel_load $kernel_start" \ + " $kernel_size && bootm $kernel_load" +#else +#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \ + " cp.b $kernel_start $kernel_load" \ + " $kernel_size && bootm $kernel_load" +#endif +#endif + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SPL_MAX_SIZE 0x16000 +#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +#endif +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#include + +#endif /* __LS2_COMMON_H */ diff --git a/roms/u-boot/include/configs/ls2080aqds.h b/roms/u-boot/include/configs/ls2080aqds.h new file mode 100644 index 000000000..41c1a8674 --- /dev/null +++ b/roms/u-boot/include/configs/ls2080aqds.h @@ -0,0 +1,494 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017, 2019-2021 NXP + * Copyright 2015 Freescale Semiconductor + */ + +#ifndef __LS2_QDS_H +#define __LS2_QDS_H + +#include "ls2080a_common.h" + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_QIXIS_I2C_ACCESS +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C_EARLY_INIT +#endif +#define CONFIG_SYS_I2C_IFDR_DIV 0x7e +#endif + +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) + +#define CONFIG_DDR_SPD +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS3 0x53 +#define SPD_EEPROM_ADDRESS4 0x54 +#define SPD_EEPROM_ADDRESS5 0x55 +#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR +#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 +#endif + +/* SATA */ +#define CONFIG_SCSI_AHCI_PLAT + +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) + +#define CONFIG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1a) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CONFIG_SYS_IFC_CCR 0x01000000 + +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ + CONFIG_SYS_FLASH_BASE + 0x40000000} +#endif + +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define QIXIS_LBMAP_SWITCH 0x06 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_QSPI 0x0f +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RCW_SRC_NAND 0x107 +#define QIXIS_RCW_SRC_SD 0x40 +#define QIXIS_RCW_SRC_QSPI 0x62 +#define QIXIS_RST_FORCE_MEM 0x01 + +#define CONFIG_SYS_CSPR3_EXT (0x0) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) + +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) +/* QIXIS Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0x3E)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +#if defined(CONFIG_SPL) +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY +#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY +#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) +#endif +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY +#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY +#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +/* Debug Server firmware */ +#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR +#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL + +#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 + +/* + * I2C + */ +#define I2C_MUX_PCA_ADDR 0x77 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ + +/* I2C bus multiplexer */ +#define I2C_MUX_CH_DEFAULT 0x8 + +/* SPI */ +#ifdef CONFIG_FSL_DSPI +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_EON +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SPI_FLASH_SPANSION +#endif +/* + * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. + * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 + * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 + */ +#define FSL_QIXIS_BRDCFG9_QSPI 0x1 + +/* + * MMC + */ +#ifdef CONFIG_MMC +#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ + QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) +#endif + +/* + * RTC configuration + */ +#define RTC +#define CONFIG_RTC_DS3231 1 +#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +#define CONFIG_FSL_MEMAC + +#ifdef CONFIG_PCI +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* Initial environment variables */ +#undef CONFIG_EXTRA_ENV_SETTINGS +#ifdef CONFIG_NXP_ESBC +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x581000000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "mcmemsize=0x40000000\0" \ + "mcinitcmd=esbc_validate 0x580640000;" \ + "esbc_validate 0x580680000;" \ + "fsl_mc start mc 0x580a00000" \ + " 0x580e00000 \0" +#else +#ifdef CONFIG_TFABOOT +#define SD_MC_INIT_CMD \ + "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ + "mmc read 0x80e00000 0x7000 0x800;" \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" +#define IFC_MC_INIT_CMD \ + "fsl_mc start mc 0x580a00000" \ + " 0x580e00000 \0" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "loadaddr_sd=0x90100000\0" \ + "kernel_addr=0x581000000\0" \ + "kernel_addr_sd=0x8000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x581000000\0" \ + "kernel_start_sd=0x8000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernel_size_sd=0x14000\0" \ + "load_addr=0xa0000000\0" \ + "kernelheader_addr=0x580600000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernelheader_size=0x40000\0" \ + "BOARD=ls2088aqds\0" \ + "mcmemsize=0x70000000 \0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + IFC_MC_INIT_CMD \ + BOOTENV \ + "boot_scripts=ls2088aqds_boot.scr\0" \ + "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "nor_bootcmd=echo Trying load from nor..;" \ + "cp.b $kernel_addr $load_addr " \ + "$kernel_size ; env exists secureboot && " \ + "cp.b $kernelheader_addr $kernelheader_addr_r " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + "bootm $load_addr#$BOARD\0" \ + "sd_bootcmd=echo Trying load from SD ..;" \ + "mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "bootm $load_addr#$BOARD\0" +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x90100000\0" \ + "kernel_addr=0x800\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x8000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x14000\0" \ + "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ + "mmc read 0x80100000 0x7000 0x800;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" \ + "mcmemsize=0x70000000 \0" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x581000000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "mcmemsize=0x40000000\0" \ + "mcinitcmd=fsl_mc start mc 0x580a00000" \ + " 0x580e00000 \0" +#endif /* CONFIG_TFABOOT */ +#endif /* CONFIG_NXP_ESBC */ + +#ifdef CONFIG_TFABOOT +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 0) \ + func(SCSI, scsi, 0) \ + func(DHCP, dhcp, na) +#include + +#define SD_BOOTCOMMAND \ + "env exists mcinitcmd && env exists secureboot "\ + "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ + "&& esbc_validate $load_addr; " \ + "env exists mcinitcmd && run mcinitcmd " \ + "&& mmc read 0x80d00000 0x6800 0x800 " \ + "&& fsl_mc lazyapply dpl 0x80d00000; " \ + "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" + +#define IFC_NOR_BOOTCOMMAND \ + "env exists mcinitcmd && env exists secureboot "\ + "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ + "&& fsl_mc lazyapply dpl 0x580d00000;" \ + "run distro_bootcmd;run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#endif + +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#define CONFIG_FSL_MEMAC +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1d +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F + +#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 +#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 +#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 +#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 +#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 +#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 +#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 +#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 +#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 +#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 +#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa +#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb +#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc +#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd +#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe +#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf + +#define CONFIG_ETHPRIME "DPMAC1@xgmii" + +#endif + +#include + +#endif /* __LS2_QDS_H */ diff --git a/roms/u-boot/include/configs/ls2080ardb.h b/roms/u-boot/include/configs/ls2080ardb.h new file mode 100644 index 000000000..f2dc495fb --- /dev/null +++ b/roms/u-boot/include/configs/ls2080ardb.h @@ -0,0 +1,586 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017, 2019-2021 NXP + * Copyright 2015 Freescale Semiconductor + */ + +#ifndef __LS2_RDB_H +#define __LS2_RDB_H + +#include "ls2080a_common.h" + +#ifdef CONFIG_FSL_QSPI +#ifdef CONFIG_TARGET_LS2081ARDB +#define CONFIG_QIXIS_I2C_ACCESS +#endif +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C_EARLY_INIT +#endif +#endif + +#define I2C_MUX_CH_VOL_MONITOR 0xa +#define I2C_VOL_MONITOR_ADDR 0x38 +#define CONFIG_VOL_MONITOR_IR36021_READ +#define CONFIG_VOL_MONITOR_IR36021_SET + +#define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_VID +#endif +/* step the IR regulator in 5mV increments */ +#define IR_VDD_STEP_DOWN 5 +#define IR_VDD_STEP_UP 5 +/* The lowest and highest voltage allowed for LS2080ARDB */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ 133333333 +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) + +#define CONFIG_DDR_SPD +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS3 0x53 +#define SPD_EEPROM_ADDRESS4 0x54 +#define SPD_EEPROM_ADDRESS5 0x55 +#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR +#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 +#endif + +/* SATA */ +#define CONFIG_SCSI_AHCI_PLAT + +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT) + +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) + +#define CONFIG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1a) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CONFIG_SYS_IFC_CCR 0x01000000 + +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ + CONFIG_SYS_FLASH_BASE + 0x40000000} +#endif + +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ + FTIM0_NAND_TWP(0x30) | \ + FTIM0_NAND_TWCHT(0x0e) | \ + FTIM0_NAND_TWH(0x14)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ + FTIM1_NAND_TWBE(0xab) | \ + FTIM1_NAND_TRR(0x1c) | \ + FTIM1_NAND_TRP(0x30)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ + FTIM2_NAND_TREH(0x14) | \ + FTIM2_NAND_TWHRE(0x3c)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define QIXIS_LBMAP_SWITCH 0x06 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RST_CTL_RESET_EN 0x30 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RCW_SRC_NAND 0x119 +#define QIXIS_RST_FORCE_MEM 0x01 + +#define CONFIG_SYS_CSPR3_EXT (0x0) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) + +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) +/* QIXIS Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0x3E)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +#if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_SPL_PAD_TO 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +/* Debug Server firmware */ +#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR +#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL +#endif +#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 + +#ifdef CONFIG_TARGET_LS2081ARDB +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define QIXIS_QMAP_MASK 0x07 +#define QIXIS_QMAP_SHIFT 5 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_RCW_SRC_QSPI 0x62 +#define QIXIS_LBMAP_ALTBANK 0x20 +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_RST_CTL_RESET_EN 0x30 +#endif + +/* + * I2C + */ +#ifdef CONFIG_TARGET_LS2081ARDB +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#endif +#define I2C_MUX_PCA_ADDR 0x75 +#define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ + +/* I2C bus multiplexer */ +#define I2C_MUX_CH_DEFAULT 0x8 + +/* SPI */ +#if defined(CONFIG_FSL_DSPI) +#define CONFIG_SPI_FLASH_STMICRO +#endif + +/* + * RTC configuration + */ +#define RTC +#ifdef CONFIG_TARGET_LS2081ARDB +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#else +#define CONFIG_RTC_DS3231 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +#define CONFIG_FSL_MEMAC + +#ifdef CONFIG_PCI +#define CONFIG_PCI_SCAN_SHOW +#endif + +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 0) \ + func(SCSI, scsi, 0) \ + func(DHCP, dhcp, na) +#include + +#ifdef CONFIG_TFABOOT +#define QSPI_MC_INIT_CMD \ + "sf probe 0:0; " \ + "sf read 0x80640000 0x640000 0x80000; " \ + "env exists secureboot && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000; " \ + "sf read 0x80a00000 0xa00000 0x300000; " \ + "sf read 0x80e00000 0xe00000 0x100000; " \ + "fsl_mc start mc 0x80a00000 0x80e00000 \0" +#define SD_MC_INIT_CMD \ + "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ + "mmc read 0x80e00000 0x7000 0x800;" \ + "env exists secureboot && " \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" +#define IFC_MC_INIT_CMD \ + "env exists secureboot && " \ + "esbc_validate 0x580640000 && " \ + "esbc_validate 0x580680000; " \ + "fsl_mc start mc 0x580a00000 0x580e00000 \0" +#else +#ifdef CONFIG_QSPI_BOOT +#define MC_INIT_CMD \ + "mcinitcmd=sf probe 0:0; " \ + "sf read 0x80640000 0x640000 0x80000; " \ + "env exists secureboot && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000; " \ + "sf read 0x80a00000 0xa00000 0x300000; " \ + "sf read 0x80e00000 0xe00000 0x100000; " \ + "fsl_mc start mc 0x80a00000 0x80e00000 \0" +#elif defined(CONFIG_SD_BOOT) +#define MC_INIT_CMD \ + "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ + "mmc read 0x80100000 0x7000 0x800;" \ + "env exists secureboot && " \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" \ + "mcmemsize=0x70000000\0" +#else +#define MC_INIT_CMD \ + "mcinitcmd=env exists secureboot && " \ + "esbc_validate 0x580640000 && " \ + "esbc_validate 0x580680000; " \ + "fsl_mc start mc 0x580a00000 0x580e00000 \0" +#endif +#endif + +/* Initial environment variables */ +#undef CONFIG_EXTRA_ENV_SETTINGS +#ifdef CONFIG_TFABOOT +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr=0x64f00000\0" \ + "kernel_addr=0x581000000\0" \ + "kernel_start=0x1000000\0" \ + "kernelheader_start=0x800000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernelheader_addr=0x580600000\0" \ + "kernel_addr_r=0x81000000\0" \ + "kernelheader_size=0x40000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernel_size_sd=0x14000\0" \ + "console=ttyAMA0,38400n8\0" \ + "mcmemsize=0x70000000\0" \ + "sd_bootcmd=echo Trying load from SD ..;" \ + "mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "bootm $load_addr#$board\0" \ + QSPI_MC_INIT_CMD \ + BOOTENV \ + "boot_scripts=ls2088ardb_boot.scr\0" \ + "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_start $kernel_size ; env exists secureboot &&" \ + "sf read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + " bootm $load_addr#$board\0" \ + "nor_bootcmd=echo Trying load from nor..;" \ + "cp.b $kernel_addr $load_addr " \ + "$kernel_size ; env exists secureboot && " \ + "cp.b $kernelheader_addr $kernelheader_addr_r " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + "bootm $load_addr#$board\0" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr=0x64f00000\0" \ + "kernel_addr=0x581000000\0" \ + "kernel_start=0x1000000\0" \ + "kernelheader_start=0x600000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernelheader_addr=0x580600000\0" \ + "kernel_addr_r=0x81000000\0" \ + "kernelheader_size=0x40000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernel_size_sd=0x14000\0" \ + "console=ttyAMA0,38400n8\0" \ + "mcmemsize=0x70000000\0" \ + "sd_bootcmd=echo Trying load from SD ..;" \ + "mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "bootm $load_addr#$board\0" \ + MC_INIT_CMD \ + BOOTENV \ + "boot_scripts=ls2088ardb_boot.scr\0" \ + "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ + "env exists secureboot " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_start $kernel_size ; env exists secureboot &&" \ + "sf read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + " bootm $load_addr#$board\0" \ + "nor_bootcmd=echo Trying load from nor..;" \ + "cp.b $kernel_addr $load_addr " \ + "$kernel_size ; env exists secureboot && " \ + "cp.b $kernelheader_addr $kernelheader_addr_r " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + "bootm $load_addr#$board\0" +#endif + +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND \ + "sf probe 0:0; " \ + "sf read 0x806c0000 0x6c0000 0x40000; " \ + "env exists mcinitcmd && env exists secureboot "\ + "&& esbc_validate 0x806c0000; " \ + "sf read 0x80d00000 0xd00000 0x100000; " \ + "env exists mcinitcmd && " \ + "fsl_mc lazyapply dpl 0x80d00000; " \ + "run distro_bootcmd;run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" + +/* Try to boot an on-SD kernel first, then do normal distro boot */ +#define SD_BOOTCOMMAND \ + "env exists mcinitcmd && env exists secureboot "\ + "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ + "&& esbc_validate $load_addr; " \ + "env exists mcinitcmd && run mcinitcmd " \ + "&& mmc read 0x80d00000 0x6800 0x800 " \ + "&& fsl_mc lazyapply dpl 0x80d00000; " \ + "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" + +/* Try to boot an on-NOR kernel first, then do normal distro boot */ +#define IFC_NOR_BOOTCOMMAND \ + "env exists mcinitcmd && env exists secureboot "\ + "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ + "&& fsl_mc lazyapply dpl 0x580d00000;" \ + "run distro_bootcmd;run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_QSPI_BOOT +/* Try to boot an on-QSPI kernel first, then do normal distro boot */ +#define CONFIG_BOOTCOMMAND \ + "sf probe 0:0; " \ + "sf read 0x806c0000 0x6c0000 0x40000; " \ + "env exists mcinitcmd && env exists secureboot "\ + "&& esbc_validate 0x806C0000; " \ + "sf read 0x80d00000 0xd00000 0x100000; " \ + "env exists mcinitcmd && " \ + "fsl_mc lazyapply dpl 0x80d00000; " \ + "run distro_bootcmd;run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#elif defined(CONFIG_SD_BOOT) +/* Try to boot an on-SD kernel first, then do normal distro boot */ +#define CONFIG_BOOTCOMMAND \ + "env exists mcinitcmd && env exists secureboot "\ + "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ + "&& esbc_validate $load_addr; " \ + "env exists mcinitcmd && run mcinitcmd " \ + "&& mmc read 0x88000000 0x6800 0x800 " \ + "&& fsl_mc lazyapply dpl 0x88000000; " \ + "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else +/* Try to boot an on-NOR kernel first, then do normal distro boot */ +#define CONFIG_BOOTCOMMAND \ + "env exists mcinitcmd && env exists secureboot "\ + "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ + "&& fsl_mc lazyapply dpl 0x580d00000;" \ + "run distro_bootcmd;run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#endif +#endif + +/* MAC/PHY configuration */ +#ifdef CONFIG_FSL_MC_ENET +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_CORTINA_FW_ADDR 0x20980000 +#else +#define CONFIG_CORTINA_FW_ADDR 0x580980000 +#endif +#define CONFIG_CORTINA_FW_LENGTH 0x40000 + +#define CORTINA_PHY_ADDR1 0x10 +#define CORTINA_PHY_ADDR2 0x11 +#define CORTINA_PHY_ADDR3 0x12 +#define CORTINA_PHY_ADDR4 0x13 +#define AQ_PHY_ADDR1 0x00 +#define AQ_PHY_ADDR2 0x01 +#define AQ_PHY_ADDR3 0x02 +#define AQ_PHY_ADDR4 0x03 +#define AQR405_IRQ_MASK 0x36 + +#define CONFIG_ETHPRIME "DPMAC1@xgmii" +#endif + +#include + +#endif /* __LS2_RDB_H */ diff --git a/roms/u-boot/include/configs/lsxl.h b/roms/u-boot/include/configs/lsxl.h new file mode 100644 index 000000000..0c0ab2486 --- /dev/null +++ b/roms/u-boot/include/configs/lsxl.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2012 Michael Walle + * Michael Walle + */ + +#ifndef _CONFIG_LSXL_H +#define _CONFIG_LSXL_H + +/* + * Version number information + */ +#if defined(CONFIG_LSCHLV2) +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg +#define CONFIG_MACH_TYPE 3006 +#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */ +#elif defined(CONFIG_LSXHL) +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg +#define CONFIG_MACH_TYPE 2663 +/* CONFIG_SYS_TCLK is 200000000 by default */ +#else +#error "unknown board" +#endif + +/* + * General configuration options + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KW88F6281 /* SOC Name */ + +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +#define CONFIG_KIRKWOOD_GPIO + +#include "mv-common.h" + +/* loading initramfs images without uimage header */ + +/* + * Environment variables configurations + */ +#ifdef CONFIG_SPI_FLASH +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 8 +#endif + +/* + * Default environment variables + */ +#define CONFIG_LOADADDR 0x00800000 + +#if defined(CONFIG_LSXHL) +#define CONFIG_FDTFILE "kirkwood-lsxhl.dtb" +#elif defined(CONFIG_LSCHLV2) +#define CONFIG_FDTFILE "kirkwood-lschlv2.dtb" +#else +#error "Unsupported board" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootsource=legacy\0" \ + "hdpart=0:1\0" \ + "kernel_addr=0x00800000\0" \ + "ramdisk_addr=0x01000000\0" \ + "fdt_addr=0x00ff0000\0" \ + "bootcmd_legacy=sata init " \ + "&& load sata ${hdpart} ${kernel_addr} /uImage.buffalo "\ + "&& load sata ${hdpart} ${ramdisk_addr} /initrd.buffalo "\ + "&& bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "bootcmd_net=bootp ${kernel_addr} vmlinuz " \ + "&& tftpboot ${ramdisk_addr} initrd.img " \ + "&& setenv ramdisk_len ${filesize} " \ + "&& tftpboot ${fdt_addr} " CONFIG_FDTFILE " " \ + "&& bootz ${kernel_addr} " \ + "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \ + "bootcmd_hdd=sata init " \ + "&& load sata ${hdpart} ${kernel_addr} /vmlinuz " \ + "&& load sata ${hdpart} ${ramdisk_addr} /initrd.img " \ + "&& setenv ramdisk_len ${filesize} " \ + "&& load sata ${hdpart} ${fdt_addr} /dtb " \ + "&& bootz ${kernel_addr} " \ + "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \ + "bootcmd_usb=usb start " \ + "&& load usb 0:1 ${kernel_addr} /vmlinuz " \ + "&& load usb 0:1 ${ramdisk_addr} /initrd.img " \ + "&& setenv ramdisk_len ${filesize} " \ + "&& load usb 0:1 ${fdt_addr} " CONFIG_FDTFILE " " \ + "&& bootz ${kernel_addr} " \ + "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \ + "bootcmd_rescue=run config_nc_dhcp; run nc\0" \ + "eraseenv=sf probe 0 " \ + "&& sf erase " __stringify(CONFIG_ENV_OFFSET) \ + " +" __stringify(CONFIG_ENV_SIZE) "\0" \ + "config_nc_dhcp=setenv autoload_old ${autoload}; " \ + "setenv autoload no " \ + "&& bootp " \ + "&& setenv ncip " \ + "&& setenv autoload ${autoload_old}; " \ + "setenv autoload_old\0" \ + "standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \ + "setenv ncip; setenv gatewayip; setenv ethact; " \ + "setenv bootfile; setenv dnsip; " \ + "setenv bootsource legacy; run ser\0" \ + "restore_env=run standard_env; saveenv; reset\0" \ + "ser=setenv stdin serial; setenv stdout serial; " \ + "setenv stderr serial\0" \ + "nc=setenv stdin nc; setenv stdout nc; setenv stderr nc\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {0, 1} /* enable port 1 only */ +#define CONFIG_PHY_BASE_ADR 7 +#undef CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +#ifdef CONFIG_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_SYS_64BIT_LBA +#define CONFIG_LBA48 +#endif + +#endif /* _CONFIG_LSXL_H */ diff --git a/roms/u-boot/include/configs/lx2160a_common.h b/roms/u-boot/include/configs/lx2160a_common.h new file mode 100644 index 000000000..15ea0e4ce --- /dev/null +++ b/roms/u-boot/include/configs/lx2160a_common.h @@ -0,0 +1,295 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2021 NXP + */ + +#ifndef __LX2_COMMON_H +#define __LX2_COMMON_H + +#include +#include +#include + +#define CONFIG_REMAKE_ELF +#define CONFIG_FSL_LAYERSCAPE +#define CONFIG_GICV3 +#define CONFIG_FSL_TZPC_BP147 +#define CONFIG_FSL_MEMAC + +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_FLASH_BASE 0x20000000 + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* DDR */ +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 +#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL +#define CONFIG_DDR_SPD +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS3 0x53 +#define SPD_EEPROM_ADDRESS4 0x54 +#define SPD_EEPROM_ADDRESS5 0x55 +#define SPD_EEPROM_ADDRESS6 0x56 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ +#define CONFIG_SYS_MONITOR_LEN (936 * 1024) + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_addr + +/* Generic Timer Definitions */ +/* + * This is not an accurate number. It is used in start.S. The frequency + * will be udpated later when get_bus_freq(0) is available. + */ + +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) + +/* Serial Port */ +#define CONFIG_PL01X_SERIAL +#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) +#define CONFIG_SYS_SERIAL0 0x21c0000 +#define CONFIG_SYS_SERIAL1 0x21d0000 +#define CONFIG_SYS_SERIAL2 0x21e0000 +#define CONFIG_SYS_SERIAL3 0x21f0000 +/*below might needs to be removed*/ +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1, \ + (void *)CONFIG_SYS_SERIAL2, \ + (void *)CONFIG_SYS_SERIAL3 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* MC firmware */ +#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 + +/* Define phy_reset function to boot the MC based on mcinitcmd. + * This happens late enough to properly fixup u-boot env MAC addresses. + */ +#define CONFIG_RESET_PHY_R + +/* + * Carve out a DDR region which will not be used by u-boot/Linux + * + * It will be used by MC and Debug Server. The MC region must be + * 512MB aligned, so the min size to hide is 512MB. + */ +#ifdef CONFIG_FSL_MC_ENET +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) +#endif + +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ +#define I2C_MUX_CH_DEFAULT 0x8 + +/* RTC */ +#define RTC +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* Qixis */ +#define CONFIG_FSL_QIXIS +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 + +/* PCI */ +#ifdef CONFIG_PCI +#define CONFIG_SYS_PCI_64BIT +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* SATA */ + +#ifdef CONFIG_SCSI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#endif + +/* USB */ +#ifdef CONFIG_USB +#define CONFIG_HAS_FSL_XHCI_USB +#ifndef CONFIG_TARGET_LX2162AQDS +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif +#endif + +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* Initial environment variables */ +#define XSPI_MC_INIT_CMD \ + "sf probe 0:0 && " \ + "sf read 0x80640000 0x640000 0x80000 && " \ + "env exists secureboot && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000; " \ + "sf read 0x80a00000 0xa00000 0x300000 && " \ + "sf read 0x80e00000 0xe00000 0x100000; " \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" + +#define SD_MC_INIT_CMD \ + "mmc read 0x80a00000 0x5000 0x1200;" \ + "mmc read 0x80e00000 0x7000 0x800;" \ + "env exists secureboot && " \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" + +#define SD2_MC_INIT_CMD \ + "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \ + "mmc read 0x80e00000 0x7000 0x800;" \ + "env exists secureboot && " \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" + +#define EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr=0x64f00000\0" \ + "kernel_start=0x1000000\0" \ + "kernelheader_start=0x600000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x81000000\0" \ + "kernelheader_size=0x40000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ + "kernel_size_sd=0x14000\0" \ + "kernelhdr_size_sd=0x20\0" \ + "console=ttyAMA0,38400n8\0" \ + BOOTENV \ + "mcmemsize=0x70000000\0" \ + XSPI_MC_INIT_CMD \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" + +#define XSPI_NOR_BOOTCOMMAND \ + "sf probe 0:0; " \ + "sf read 0x806c0000 0x6c0000 0x40000; " \ + "env exists mcinitcmd && env exists secureboot" \ + " && esbc_validate 0x806c0000; " \ + "sf read 0x80d00000 0xd00000 0x100000; " \ + "env exists mcinitcmd && " \ + "fsl_mc lazyapply dpl 0x80d00000; " \ + "run distro_bootcmd;run xspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" + +#define SD_BOOTCOMMAND \ + "env exists mcinitcmd && mmcinfo; " \ + "mmc read 0x80d00000 0x6800 0x800; " \ + "env exists mcinitcmd && env exists secureboot " \ + " && mmc read 0x806C0000 0x3600 0x20 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ + "&& fsl_mc lazyapply dpl 0x80d00000;" \ + "run distro_bootcmd;run sd_bootcmd;" \ + "env exists secureboot && esbc_halt;" + +#define SD2_BOOTCOMMAND \ + "mmc dev 1; env exists mcinitcmd && mmcinfo; " \ + "mmc read 0x80d00000 0x6800 0x800; " \ + "env exists mcinitcmd && env exists secureboot " \ + " && mmc read 0x806C0000 0x3600 0x20 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ + "&& fsl_mc lazyapply dpl 0x80d00000;" \ + "run distro_bootcmd;run sd2_bootcmd;" \ + "env exists secureboot && esbc_halt;" + +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(SCSI, scsi, 0) \ + func(DHCP, dhcp, na) +#include + +#endif /* __LX2_COMMON_H */ diff --git a/roms/u-boot/include/configs/lx2160aqds.h b/roms/u-boot/include/configs/lx2160aqds.h new file mode 100644 index 000000000..ea1b1635f --- /dev/null +++ b/roms/u-boot/include/configs/lx2160aqds.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2020 NXP + */ + +#ifndef __LX2_QDS_H +#define __LX2_QDS_H + +#include "lx2160a_common.h" + +/* VID */ +#define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv" +#define CONFIG_VID +#define CONFIG_VOL_MONITOR_LTC3882_SET +#define CONFIG_VOL_MONITOR_LTC3882_READ + +/* RTC */ +#define CONFIG_SYS_RTC_BUS_NUM 0 + +/* + * MMC + */ +#ifdef CONFIG_MMC +#ifndef __ASSEMBLY__ +u8 qixis_esdhc_detect_quirk(void); +#endif +#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk() +#endif + +/* MAC/PHY configuration */ +#if defined(CONFIG_FSL_MC_ENET) +#define CONFIG_MII +#define CONFIG_ETHPRIME "DPMAC17@rgmii-id" +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXTRA_ENV_SETTINGS \ + "boot_scripts=lx2160aqds_boot.scr\0" \ + "boot_script_hdr=hdr_lx2160aqds_bs.out\0" \ + "BOARD=lx2160aqds\0" \ + "xspi_bootcmd=echo Trying load from flexspi..;" \ + "sf probe 0:0 && sf read $load_addr " \ + "$kernel_start $kernel_size ; env exists secureboot &&" \ + "sf read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + " bootm $load_addr#$BOARD\0" \ + "sd_bootcmd=echo Trying load from sd card..;" \ + "mmc dev 0; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" \ + "sd2_bootcmd=echo Trying load from emmc card..;" \ + "mmc dev 1; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" + +#include + +#endif /* __LX2_QDS_H */ diff --git a/roms/u-boot/include/configs/lx2160ardb.h b/roms/u-boot/include/configs/lx2160ardb.h new file mode 100644 index 000000000..097f1224c --- /dev/null +++ b/roms/u-boot/include/configs/lx2160ardb.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018,2020 NXP + */ + +#ifndef __LX2_RDB_H +#define __LX2_RDB_H + +#include "lx2160a_common.h" + +/* VID */ +#define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv" +#define CONFIG_VID +#define CONFIG_VOL_MONITOR_LTC3882_SET +#define CONFIG_VOL_MONITOR_LTC3882_READ + +/* RTC */ +#define CONFIG_SYS_RTC_BUS_NUM 4 + +/* MAC/PHY configuration */ +#if defined(CONFIG_FSL_MC_ENET) +#define CONFIG_MII +#define CONFIG_ETHPRIME "DPMAC1@xgmii" +#endif + +/* EMC2305 */ +#define I2C_MUX_CH_EMC2305 0x09 +#define I2C_EMC2305_ADDR 0x4D +#define I2C_EMC2305_CMD 0x40 +#define I2C_EMC2305_PWM 0x80 + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXTRA_ENV_SETTINGS \ + "boot_scripts=lx2160ardb_boot.scr\0" \ + "boot_script_hdr=hdr_lx2160ardb_bs.out\0" \ + "BOARD=lx2160ardb\0" \ + "xspi_bootcmd=echo Trying load from flexspi..;" \ + "sf probe 0:0 && sf read $load_addr " \ + "$kernel_start $kernel_size ; env exists secureboot &&" \ + "sf read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + " bootm $load_addr#$BOARD\0" \ + "sd_bootcmd=echo Trying load from sd card..;" \ + "mmc dev 0; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" \ + "sd2_bootcmd=echo Trying load from emmc card..;" \ + "mmc dev 1; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" + +#include + +#endif /* __LX2_RDB_H */ diff --git a/roms/u-boot/include/configs/lx2162aqds.h b/roms/u-boot/include/configs/lx2162aqds.h new file mode 100644 index 000000000..847534c55 --- /dev/null +++ b/roms/u-boot/include/configs/lx2162aqds.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __LX2162_QDS_H +#define __LX2162_QDS_H + +#include "lx2160a_common.h" + +/* USB */ +#undef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +/* Voltage monitor on channel 2*/ +#define CONFIG_VID_FLS_ENV "lx2162aqds_vdd_mv" +#define CONFIG_VID +#define CONFIG_VOL_MONITOR_LTC3882_SET +#define CONFIG_VOL_MONITOR_LTC3882_READ + +/* RTC */ +#define CONFIG_SYS_RTC_BUS_NUM 0 + +/* + * MMC + */ +#ifdef CONFIG_MMC +#ifndef __ASSEMBLY__ +u8 qixis_esdhc_detect_quirk(void); +#endif +#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk() +#endif + +/* MAC/PHY configuration */ +#if defined(CONFIG_FSL_MC_ENET) +#define CONFIG_MII +#define CONFIG_ETHPRIME "DPMAC17@rgmii-id" +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXTRA_ENV_SETTINGS \ + "boot_scripts=lx2162aqds_boot.scr\0" \ + "boot_script_hdr=hdr_lx2162aqds_bs.out\0" \ + "BOARD=lx2162aqds\0" \ + "xspi_bootcmd=echo Trying load from flexspi..;" \ + "sf probe 0:0 && sf read $load_addr " \ + "$kernel_start $kernel_size ; env exists secureboot &&" \ + "sf read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + " bootm $load_addr#$BOARD\0" \ + "sd_bootcmd=echo Trying load from sd card..;" \ + "mmc dev 0; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" \ + "emmc_bootcmd=echo Trying load from emmc card..;" \ + "mmc dev 1; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" + +#include + +#endif /* __LX2162_QDS_H */ diff --git a/roms/u-boot/include/configs/m53menlo.h b/roms/u-boot/include/configs/m53menlo.h new file mode 100644 index 000000000..52c95de52 --- /dev/null +++ b/roms/u-boot/include/configs/m53menlo.h @@ -0,0 +1,231 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* + * Menlosystems M53Menlo configuration + * Copyright (C) 2012-2017 Marek Vasut + * Copyright (C) 2014-2017 Olaf Mandel + */ + +#ifndef __M53MENLO_CONFIG_H__ +#define __M53MENLO_CONFIG_H__ + +#include + +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * Memory configurations + */ +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_SIZE (gd->ram_size) +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ + +/* + * Serial Driver + */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* + * MMC Driver + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 +#endif + +/* + * NAND + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI +#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI +#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_MXC_NAND_HWECC + +/* Environment is in NAND */ +#define CONFIG_ENV_RANGE (0x00080000) /* 512 KiB */ +#endif + +/* + * Ethernet on SOC (FEC) + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC0" +#endif + +/* + * I2C + */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ +#endif + +/* + * RTC + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 +#endif + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#endif + +/* + * SATA + */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR +#define CONFIG_LBA48 +#endif + +/* + * LCD + */ +#define CONFIG_VIDEO_LOGO +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) + +/* LVDS display */ +#define CONFIG_SYS_LDB_CLOCK 33260000 +#define CONFIG_IMX_VIDEO_SKIP + +/* IIM Fuses */ +#define CONFIG_FSL_IIM + +/* Watchdog */ + +/* + * Boot Linux + */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTFILE "boot/fitImage" +#define CONFIG_LOADADDR 0x70800000 +#define CONFIG_BOOTCOMMAND "run mmc_mmc" +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * NAND SPL + */ +#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx" +#define CONFIG_SPL_PAD_TO 0x8000 +#define CONFIG_SPL_STACK 0x70004000 + +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + +/* + * Extra Environments + */ +#define CONFIG_HOSTNAME "m53menlo" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "consdev=ttymxc0\0" \ + "baudrate=115200\0" \ + "bootscript=boot.scr\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "rootpath=/srv/\0" \ + "kernel_addr_r=0x72000000\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "netdev=eth0\0" \ + "splashsource=mmc_fs\0" \ + "splashfile=boot/usplash.bmp.gz\0" \ + "splashimage=0x88000000\0" \ + "splashpos=m,m\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ + "addcons=" \ + "setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addmisc=" \ + "setenv bootargs ${bootargs} ${miscargs}\0" \ + "addargs=run addcons addmisc addmtd\0" \ + "mmcload=" \ + "mmc rescan ; load mmc ${mmcdev}:${mmcpart} " \ + "${kernel_addr_r} ${bootfile}\0" \ + "miscargs=nohlt panic=1\0" \ + "mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \ + "rootwait\0" \ + "mmc_mmc=" \ + "run mmcload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "netload=tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ + "net_nfs=" \ + "run netload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "nfsargs=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}${hostname},v3,tcp\0" \ + "try_bootscript=" \ + "mmc rescan;" \ + "if test -e mmc 0:1 ${bootscript} ; then " \ + "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \ + "then ; " \ + "echo Running bootscript... ; " \ + "source ${kernel_addr_r} ; " \ + "fi ; " \ + "fi\0" + +#if defined(CONFIG_SPL_BUILD) +#undef CONFIG_WATCHDOG +#define CONFIG_HW_WATCHDOG +#endif + +#endif /* __M53MENLO_CONFIG_H__ */ diff --git a/roms/u-boot/include/configs/malta.h b/roms/u-boot/include/configs/malta.h new file mode 100644 index 000000000..9602773ff --- /dev/null +++ b/roms/u-boot/include/configs/malta.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2013 Gabor Juhos + */ + +#ifndef _MALTA_CONFIG_H +#define _MALTA_CONFIG_H + +/* + * System configuration + */ +#define CONFIG_MALTA + +#define CONFIG_MEMSIZE_IN_BYTES + +#define CONFIG_PCI_GT64120 +#define CONFIG_PCI_MSC01 + +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 + +/* + * CPU Configuration + */ +#define CONFIG_SYS_MHZ 250 /* arbitrary value */ +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +/* + * Memory map + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#ifdef CONFIG_64BIT +# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +#else +# define CONFIG_SYS_SDRAM_BASE 0x80000000 +#endif +#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000) + +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) + +/* + * Serial driver + */ +#define CONFIG_SYS_NS16550_PORT_MAPPED + +/* + * Flash configuration + */ +#ifdef CONFIG_64BIT +# define CONFIG_SYS_FLASH_BASE 0xffffffffbe000000 +#else +# define CONFIG_SYS_FLASH_BASE 0xbe000000 +#endif +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +/* + * Environment + */ + +/* + * IDE/ATA + */ +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 2 +#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 + +/* + * Commands + */ + +#endif /* _MALTA_CONFIG_H */ diff --git a/roms/u-boot/include/configs/maxbcm.h b/roms/u-boot/include/configs/maxbcm.h new file mode 100644 index 000000000..0c2185c52 --- /dev/null +++ b/roms/u-boot/include/configs/maxbcm.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Stefan Roese + */ + +#ifndef _CONFIG_DB_MV7846MP_GP_H +#define _CONFIG_DB_MV7846MP_GP_H + +/* + * High Level Configuration Options (easy to change) + */ + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* SPI NOR flash default params, used by sf commands */ + +/* Environment in SPI NOR flash */ + +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * Memory layout while starting into the bin_hdr via the + * BootROM: + * + * 0x4000.4000 - 0x4003.4000 headers space (192KiB) + * 0x4000.4030 bin_hdr start address + * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) + * 0x4007.fffc BootROM stack top + * + * The address space between 0x4007.fffc and 0x400f.fff is not locked in + * L2 cache thus cannot be used. + */ + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +/* SPL related SPI defines */ + +/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ +#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ +#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ + +#endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/roms/u-boot/include/configs/mccmon6.h b/roms/u-boot/include/configs/mccmon6.h new file mode 100644 index 000000000..0c383e94c --- /dev/null +++ b/roms/u-boot/include/configs/mccmon6.h @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016-2017 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#include "imx6_spl.h" + +#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000) +#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 + +/* + * Below defines are set but NOT really used since we by + * design force U-Boot run when we boot in development + * mode from SD card (SD2) + */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (0x800) +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (0x80) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000) +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "fitImage" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +/* NOR 16-bit mode */ +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_FLASH_VERIFY + +/* NOR Flash MTD */ +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } +#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } + +/* Ethernet Configuration */ +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200 quiet\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "boot_os=yes\0" \ + "kernelsize=0x300000\0" \ + "disable_giga=yes\0" \ + "download_kernel=" \ + "tftpboot ${loadaddr} ${kernel_file};\0" \ + "get_boot_medium=" \ + "setenv boot_medium nor;" \ + "setexpr.l _src_sbmr1 *0x020d8004;" \ + "setexpr _b_medium ${_src_sbmr1} '&' 0x00000040;" \ + "if test ${_b_medium} = 40; then " \ + "setenv boot_medium sdcard;" \ + "fi\0" \ + "kernel_file=fitImage\0" \ + "boot_sd=" \ + "echo '#######################';" \ + "echo '# Factory SDcard Boot #';" \ + "echo '#######################';" \ + "setenv mmcdev 1;" \ + "setenv mmcfactorydev 0;" \ + "setenv mmcfactorypart 1;" \ + "run factory_flash_img;\0" \ + "boot_nor=" \ + "setenv kernelnor 0x08180000;" \ + "setenv bootargs console=${console} " \ + CONFIG_MTDPARTS_DEFAULT " " \ + "root=/dev/mmcblk1 rootfstype=ext4 rw rootwait noinitrd;" \ + "cp.l ${kernelnor} ${loadaddr} ${kernelsize};" \ + "bootm ${loadaddr};reset;\0" \ + "boot_recovery=" \ + "echo '#######################';" \ + "echo '# RECOVERY SWU Boot #';" \ + "echo '#######################';" \ + "setenv rootfsloadaddr 0x13000000;" \ + "setenv swukernelnor 0x08980000;" \ + "setenv swurootfsnor 0x09180000;" \ + "setenv bootargs console=${console} " \ + CONFIG_MTDPARTS_DEFAULT " " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}::off root=/dev/ram rw;" \ + "cp.l ${swurootfsnor} ${rootfsloadaddr} 0x200000;" \ + "cp.l ${swukernelnor} ${loadaddr} ${kernelsize};" \ + "bootm ${loadaddr} ${rootfsloadaddr};reset;\0" \ + "boot_tftp=" \ + "echo '#######################';" \ + "echo '# TFTP Boot #';" \ + "echo '#######################';" \ + "if run download_kernel; then " \ + "setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rootwait;" \ + "bootm $loadaddr};reset;" \ + "fi\0" \ + "bootcmd=" \ + "if test -n ${recovery_status}; then " \ + "run boot_recovery;" \ + "else " \ + "if test ! -n ${boot_medium}; then " \ + "run get_boot_medium;" \ + "if test ${boot_medium} = sdcard; then " \ + "run boot_sd;" \ + "else " \ + "run boot_nor;" \ + "fi;" \ + "else " \ + "if test ${boot_medium} = tftp; then " \ + "run boot_tftp;" \ + "fi;" \ + "fi;" \ + "fi\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "bootdev=1\0" \ + "bootpart=1\0" \ + "netdev=eth0\0" \ + "load_addr=0x11000000\0" \ + "uboot_file=u-boot.img\0" \ + "SPL_file=SPL\0" \ + "load_uboot=tftp ${load_addr} ${uboot_file}\0" \ + "nor_img_addr=0x11000000\0" \ + "nor_img_file=core-image-lwn-mccmon6.nor\0" \ + "emmc_img_file=core-image-lwn-mccmon6.ext4\0" \ + "nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ + "nor_img_size=0x02000000\0" \ + "factory_script_file=factory.scr\0" \ + "factory_load_script=" \ + "if test -e mmc ${mmcdev}:${mmcfactorypart} " \ + "${factory_script_file}; then " \ + "load mmc ${mmcdev}:${mmcfactorypart} " \ + "${loadaddr} ${factory_script_file};" \ + "fi\0" \ + "factory_script=echo Running factory script from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ + "factory_flash_img="\ + "echo 'Flash mccmon6 with factory images'; " \ + "if run factory_load_script; then " \ + "run factory_script;" \ + "else " \ + "echo No factory script: ${factory_script_file} found on " \ + "device ${mmcdev};" \ + "run factory_nor_img;" \ + "run factory_eMMC_img;" \ + "run factory_SPL_falcon_setup;" \ + "fi\0" \ + "factory_eMMC_img="\ + "echo 'Update mccmon6 eMMC image'; " \ + "if load mmc ${mmcdev}:${mmcfactorypart} " \ + "${loadaddr} ${emmc_img_file}; then " \ + "setexpr fw_sz ${filesize} / 0x200;" \ + "setexpr fw_sz ${fw_sz} + 1;" \ + "mmc dev ${mmcfactorydev};" \ + "mmc write ${loadaddr} 0x0 ${fw_sz};" \ + "fi\0" \ + "factory_nor_img="\ + "echo 'Update mccmon6 NOR image'; " \ + "if load mmc ${mmcdev}:${mmcfactorypart} " \ + "${nor_img_addr} ${nor_img_file}; then " \ + "run nor_update;" \ + "fi\0" \ + "nor_update=" \ + "protect off ${nor_bank_start} +${nor_img_size};" \ + "erase ${nor_bank_start} +${nor_img_size};" \ + "setexpr nor_img_size ${nor_img_size} / 4; " \ + "cp.l ${nor_img_addr} ${nor_bank_start} ${nor_img_size}\0" \ + "factory_SPL_falcon_setup="\ + "echo 'Write Falcon boot data'; " \ + "setenv kernelnor 0x08180000;" \ + "cp.l ${kernelnor} ${loadaddr} ${kernelsize};" \ + "spl export fdt ${loadaddr};" \ + "setenv nor_img_addr ${fdtargsaddr};" \ + "setenv nor_img_size 0x20000;" \ + "setenv nor_bank_start " \ + __stringify(CONFIG_CMD_SPL_NOR_OFS)";" \ + "run nor_update\0" \ + "tftp_nor_uboot="\ + "echo 'Update mccmon6 NOR U-BOOT via TFTP'; " \ + "setenv nor_img_file u-boot.img; " \ + "setenv nor_img_size 0x80000; " \ + "setenv nor_bank_start 0x08080000; " \ + "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ + "run nor_update;" \ + "fi\0" \ + "tftp_nor_fitImg="\ + "echo 'Update mccmon6 NOR fitImage via TFTP'; " \ + "setenv nor_img_file fitImage; " \ + "setenv nor_img_size 0x500000; " \ + "setenv nor_bank_start 0x08180000; " \ + "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ + "run nor_update;" \ + "fi\0" \ + "tftp_nor_img="\ + "echo 'Update mccmon6 NOR image via TFTP'; " \ + "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ + "run nor_update;" \ + "fi\0" \ + "tftp_nor_SPL="\ + "if tftp ${load_addr} SPL_padded; then " \ + "erase 0x08000000 +0x20000;" \ + "cp.b ${load_addr} 0x08000000 0x20000;" \ + "fi;\0" \ + "tftp_sd_SPL="\ + "if mmc dev 1; then " \ + "if tftp ${load_addr} ${SPL_file}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${load_addr} 0x2 ${fw_sz};" \ + "fi;" \ + "fi;\0" \ + "tftp_sd_uboot="\ + "if mmc dev 1; then " \ + "if run load_uboot; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${load_addr} 0x8A ${fw_sz};" \ + "fi;" \ + "fi;\0" + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ + +/* Envs are stored in NOR flash */ + +#endif /* __CONFIG_H * */ diff --git a/roms/u-boot/include/configs/medcom-wide.h b/roms/u-boot/include/configs/medcom-wide.h new file mode 100644 index 000000000..84b998e23 --- /dev/null +++ b/roms/u-boot/include/configs/medcom-wide.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + * (C) Copyright 2011-2012 + * Avionic Design GmbH + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra20-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +/* NAND support */ +#define CONFIG_TEGRA_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Environment in NAND, aligned to start of last sector */ + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/meerkat96.h b/roms/u-boot/include/configs/meerkat96.h new file mode 100644 index 000000000..f43a8415e --- /dev/null +++ b/roms/u-boot/include/configs/meerkat96.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Linaro Ltd. + * Copyright (C) 2016 NXP Semiconductors + * + * Configuration settings for Meerkat96 board. + */ + +#ifndef __MEERKAT96_CONFIG_H +#define __MEERKAT96_CONFIG_H + +#include "mx7_common.h" +#include + +#define PHYS_SDRAM_SIZE SZ_512M + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment configs */ + +/* USB configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +#endif diff --git a/roms/u-boot/include/configs/meesc.h b/roms/u-boot/include/configs/meesc.h new file mode 100644 index 000000000..bd4bac7aa --- /dev/null +++ b/roms/u-boot/include/configs/meesc.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * (C) Copyright 2009-2015 + * Daniel Gorsulowski + * esd electronic system design gmbh + * + * Configuation settings for the esd MEESC board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include + +/* + * Warning: changing CONFIG_SYS_TEXT_BASE requires + * adapting the initial boot program. + * Since the linker has to swallow that define, we must use a pure + * hex number here! + */ + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ + +/* Misc CPU related */ +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SERIAL_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ + +/* + * Hardware drivers + */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * SDRAM: 1 bank, min 32, max 128 MB + * Initialized before u-boot gets started. + */ +#define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */ +#define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000) + +/* + * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, + * leaving the correct space for initial global data structure above + * that address while providing maximum stack area below. + */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ +# define CONFIG_SYS_NAND_DBW_8 +# define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +# define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) +# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) +#endif + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#undef CONFIG_RESET_PHY_R + +/* hw-controller addresses */ +#define CONFIG_ET1100_BASE 0x70000000 + +#ifdef CONFIG_SYS_USE_DATAFLASH + +/* bootstrap + u-boot + env in dataflash on CS0 */ + +#elif CONFIG_SYS_USE_NANDFLASH + +/* bootstrap + u-boot + env + linux in nandflash */ + +#endif + +#define CONFIG_SYS_CBSIZE 512 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ + 128*1024, 0x1000) + +#endif diff --git a/roms/u-boot/include/configs/meson64.h b/roms/u-boot/include/configs/meson64.h new file mode 100644 index 000000000..17ebccd2c --- /dev/null +++ b/roms/u-boot/include/configs/meson64.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for Amlogic Meson 64bits SoCs + * (C) Copyright 2016 Beniamino Galvani + */ + +#ifndef __MESON64_CONFIG_H +#define __MESON64_CONFIG_H + +/* Generic Interrupt Controller Definitions */ +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A)) +#define GICD_BASE 0xffc01000 +#define GICC_BASE 0xffc02000 +#else /* MESON GXL and GXBB */ +#define GICD_BASE 0xc4301000 +#define GICC_BASE 0xc4302000 +#endif + +/* For splashscreen */ +#ifdef CONFIG_DM_VIDEO +#define STDOUT_CFG "vidconsole,serial" +#else +#define STDOUT_CFG "serial" +#endif + +#ifdef CONFIG_USB_KEYBOARD +#define STDIN_CFG "usbkbd,serial" +#else +#define STDIN_CFG "serial" +#endif + +#define CONFIG_CPU_ARMV8 +#define CONFIG_REMAKE_ELF +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 + +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_INIT_SP_ADDR 0x20000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */ + +/* ROM USB boot support, auto-execute boot.scr at scriptaddr */ +#define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \ + "bootcmd_romusb=" \ + "if test \"${boot_source}\" = \"usb\" && " \ + "test -n \"${scriptaddr}\"; then " \ + "echo '(ROM USB boot)'; " \ + "source ${scriptaddr}; " \ + "fi\0" + +#define BOOTENV_DEV_NAME_ROMUSB(devtypeu, devtypel, instance) \ + "romusb " + +#ifdef CONFIG_CMD_USB +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + +#ifdef CONFIG_CMD_NVME + #define BOOT_TARGET_NVME(func) func(NVME, nvme, 0) +#else + #define BOOT_TARGET_NVME(func) +#endif + +#ifndef BOOT_TARGET_DEVICES +#define BOOT_TARGET_DEVICES(func) \ + func(ROMUSB, romusb, na) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + BOOT_TARGET_DEVICES_USB(func) \ + BOOT_TARGET_NVME(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) +#endif + +#include + +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=" STDIN_CFG "\0" \ + "stdout=" STDOUT_CFG "\0" \ + "stderr=" STDOUT_CFG "\0" \ + "fdt_addr_r=0x08008000\0" \ + "scriptaddr=0x08000000\0" \ + "kernel_addr_r=0x08080000\0" \ + "pxefile_addr_r=0x01080000\0" \ + "fdtoverlay_addr_r=0x01000000\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + BOOTENV +#endif + + +#endif /* __MESON64_CONFIG_H */ diff --git a/roms/u-boot/include/configs/meson64_android.h b/roms/u-boot/include/configs/meson64_android.h new file mode 100644 index 000000000..c47d51c85 --- /dev/null +++ b/roms/u-boot/include/configs/meson64_android.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for Android Amlogic Meson 64bits SoCs + * + * Copyright (C) 2019 Baylibre, SAS + * Author: Jerome Brunet + */ + +#ifndef __MESON64_ANDROID_CONFIG_H +#define __MESON64_ANDROID_CONFIG_H + + +#define BOOTENV_DEV_FASTBOOT(devtypeu, devtypel, instance) \ + "bootcmd_fastboot=" \ + "sm reboot_reason reason;" \ + "setenv run_fastboot 0;" \ + "if test \"${boot_source}\" = \"usb\"; then " \ + "echo Fastboot forced by usb rom boot;" \ + "setenv run_fastboot 1;" \ + "fi;" \ + "if gpt verify mmc ${mmcdev} ${partitions}; then; " \ + "else " \ + "echo Broken MMC partition scheme;" \ + "setenv run_fastboot 1;" \ + "fi;" \ + "if test \"${reason}\" = \"bootloader\" -o " \ + "\"${reason}\" = \"fastboot\"; then " \ + "echo Fastboot asked by reboot reason;" \ + "setenv run_fastboot 1;" \ + "fi;" \ + "if test \"${skip_fastboot}\" -eq 1; then " \ + "echo Fastboot skipped by environment;" \ + "setenv run_fastboot 0;" \ + "fi;" \ + "if test \"${force_fastboot}\" -eq 1; then " \ + "echo Fastboot forced by environment;" \ + "setenv run_fastboot 1;" \ + "fi;" \ + "if test \"${run_fastboot}\" -eq 1; then " \ + "echo Running Fastboot...;" \ + "fastboot 0;" \ + "fi\0" + +#define BOOTENV_DEV_NAME_FASTBOOT(devtypeu, devtypel, instance) \ + "fastboot " + +/* TOFIX: Run actual recovery instead of fastboot */ +#define BOOTENV_DEV_RECOVERY(devtypeu, devtypel, instance) \ + "bootcmd_recovery=" \ + "pinmux dev pinctrl@14;" \ + "pinmux dev pinctrl@40;" \ + "sm reboot_reason reason;" \ + "setenv run_recovery 0;" \ + "if run check_button; then " \ + "echo Recovery button is pressed;" \ + "setenv run_recovery 1;" \ + "elif test \"${reason}\" = \"recovery\" -o " \ + "\"${reason}\" = \"update\"; then " \ + "echo Recovery asked by reboot reason;" \ + "setenv run_recovery 1;" \ + "fi;" \ + "if test \"${skip_recovery}\" -eq 1; then " \ + "echo Recovery skipped by environment;" \ + "setenv run_recovery 0;" \ + "fi;" \ + "if test \"${force_recovery}\" -eq 1; then " \ + "echo Recovery forced by environment;" \ + "setenv run_recovery 1;" \ + "fi;" \ + "if test \"${run_recovery}\" -eq 1; then " \ + "echo Running Recovery...;" \ + "fastboot 0;" \ + "fi\0" + +#define BOOTENV_DEV_NAME_RECOVERY(devtypeu, devtypel, instance) \ + "recovery " + +#define BOOTENV_DEV_SYSTEM(devtypeu, devtypel, instance) \ + "bootcmd_system=" \ + "echo Loading Android boot partition...;" \ + "mmc dev ${mmcdev};" \ + "setenv bootargs ${bootargs} console=${console} androidboot.serialno=${serial#};" \ + "part start mmc ${mmcdev} ${bootpart} boot_start;" \ + "part size mmc ${mmcdev} ${bootpart} boot_size;" \ + "if mmc read ${loadaddr} ${boot_start} ${boot_size}; then " \ + "echo Running Android...;" \ + "bootm ${loadaddr};" \ + "fi;" \ + "echo Failed to boot Android...;" \ + "reset\0" + +#define BOOTENV_DEV_NAME_SYSTEM(devtypeu, devtypel, instance) \ + "system " + +#define BOOT_TARGET_DEVICES(func) \ + func(FASTBOOT, fastboot, na) \ + func(RECOVERY, recovery, na) \ + func(SYSTEM, system, na) \ + +#define PREBOOT_LOAD_LOGO \ + "if test \"${boot_source}\" != \"usb\" && " \ + "gpt verify mmc ${mmcdev} ${partitions}; then; " \ + "mmc dev ${mmcdev};" \ + "part start mmc ${mmcdev} ${logopart} boot_start;" \ + "part size mmc ${mmcdev} ${logopart} boot_size;" \ + "if mmc read ${loadaddr} ${boot_start} ${boot_size}; then " \ + "bmp display ${loadaddr} m m;" \ + "fi;" \ + "fi;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "partitions=" PARTS_DEFAULT "\0" \ + "mmcdev=2\0" \ + "bootpart=1\0" \ + "logopart=2\0" \ + "gpio_recovery=88\0" \ + "check_button=gpio input ${gpio_recovery};test $? -eq 0;\0" \ + "load_logo=" PREBOOT_LOAD_LOGO "\0" \ + "console=/dev/ttyAML0\0" \ + "bootargs=no_console_suspend\0" \ + "stdin=" STDIN_CFG "\0" \ + "stdout=" STDOUT_CFG "\0" \ + "stderr=" STDOUT_CFG "\0" \ + "loadaddr=0x01000000\0" \ + "fdt_addr_r=0x01000000\0" \ + "scriptaddr=0x08000000\0" \ + "kernel_addr_r=0x01080000\0" \ + "pxefile_addr_r=0x01080000\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" BOOTENV + +#include + +#endif /* __MESON64_ANDROID_CONFIG_H */ diff --git a/roms/u-boot/include/configs/microblaze-generic.h b/roms/u-boot/include/configs/microblaze-generic.h new file mode 100644 index 000000000..59b20cf11 --- /dev/null +++ b/roms/u-boot/include/configs/microblaze-generic.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2010 Michal Simek + * + * Michal SIMEK + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Microblaze is microblaze_0 */ +#define XILINX_FSL_NUMBER 3 + +/* MicroBlaze CPU */ +#define MICROBLAZE_V5 1 + +#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) + +/* uart */ +/* The following table includes the supported baudrates */ +# define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/* setting reset address */ +/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ + +#define CONFIG_SYS_MALLOC_LEN 0xC0000 + +/* Stack location before relocation */ +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SYS_MALLOC_F_LEN) + +#ifdef CONFIG_CFI_FLASH +/* ?empty sector */ +# define CONFIG_SYS_FLASH_EMPTY_INFO 1 +/* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_BANKS 1 +/* max number of sectors on one chip */ +# define CONFIG_SYS_MAX_FLASH_SECT 2048 +#endif + +#define CONFIG_ICACHE +#define CONFIG_DCACHE + +#ifndef XILINX_DCACHE_BYTE_SIZE +#define XILINX_DCACHE_BYTE_SIZE 32768 +#endif + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* size of console buffer */ +#define CONFIG_SYS_CBSIZE 512 +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 15 +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0 + +#define CONFIG_HOSTNAME "microblaze-generic" + +/* architecture dependent code */ +#define CONFIG_SYS_USR_EXCEP /* user exception */ + +#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) +#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) +#else +#define BOOT_TARGET_DEVICES_PXE(func) +#endif + +#if defined(CONFIG_CMD_DHCP) +#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +#define BOOT_TARGET_DEVICES_DHCP(func) +#endif + +#if defined(CONFIG_SPI_FLASH) +# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) +#else +# define BOOT_TARGET_DEVICES_QSPI(func) +#endif + +#if defined(CONFIG_MTD_NOR_FLASH) +# define BOOT_TARGET_DEVICES_NOR(func) func(NOR, nor, na) +#else +# define BOOT_TARGET_DEVICES_NOR(func) +#endif + +#define BOOTENV_DEV_NOR(devtypeu, devtypel, instance) \ + "bootcmd_nor=cp.b ${script_offset_nor} ${scriptaddr} ${script_size_f} && " \ + "echo NOR: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo NOR: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_NOR(devtypeu, devtypel, instance) \ + "nor " + +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_qspi=sf probe 0 0 0 && " \ + "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + "qspi " + +#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) + +#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ + "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ + "jtag " + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_JTAG(func) \ + BOOT_TARGET_DEVICES_QSPI(func) \ + BOOT_TARGET_DEVICES_NOR(func) \ + BOOT_TARGET_DEVICES_DHCP(func) \ + BOOT_TARGET_DEVICES_PXE(func) + +#include + +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "unlock=yes\0"\ + "nor0=flash-0\0"\ + "mtdparts=mtdparts=flash-0:"\ + "256k(u-boot),256k(env),3m(kernel),"\ + "1m(romfs),1m(cramfs),-(jffs2)\0"\ + "nc=setenv stdout nc;"\ + "setenv stdin nc\0" \ + "serial=setenv stdout serial;"\ + "setenv stdin serial\0"\ + "script_size_f=0x40000\0"\ + BOOTENV +#endif + +#if defined(CONFIG_XILINX_AXIEMAC) +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 +#endif + +/* SPL part */ + +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE + +/* for booting directly linux */ +#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_TEXT_BASE + \ + 0x40000) + +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ + 0x1000000) + +/* SP location before relocation, must use scratch RAM */ +/* BRAM start */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x0 +/* BRAM size - will be generated */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 + +# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE) + +/* Just for sure that there is a space for stack */ +#define CONFIG_SPL_STACK_SIZE 0x100 + +#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ + CONFIG_SYS_INIT_RAM_ADDR - \ + CONFIG_SYS_MALLOC_F_LEN - \ + CONFIG_SPL_STACK_SIZE) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/microchip_mpfs_icicle.h b/roms/u-boot/include/configs/microchip_mpfs_icicle.h new file mode 100644 index 000000000..24990370c --- /dev/null +++ b/roms/u-boot/include/configs/microchip_mpfs_icicle.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Microchip Technology Inc. + * Padmarao Begari + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +#define CONFIG_SYS_MALLOC_LEN SZ_8M + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 + +/* Environment options */ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/minnowmax.h b/roms/u-boot/include/configs/minnowmax.h new file mode 100644 index 000000000..6bcae31cb --- /dev/null +++ b/roms/u-boot/include/configs/minnowmax.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Google, Inc + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \ + "stdout=vidconsole,serial\0" \ + "stderr=vidconsole,serial\0" \ + "usb_pgood_delay=40\0" + +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/miqi_rk3288.h b/roms/u-boot/include/configs/miqi_rk3288.h new file mode 100644 index 000000000..053c9032e --- /dev/null +++ b/roms/u-boot/include/configs/miqi_rk3288.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#endif diff --git a/roms/u-boot/include/configs/mpc8308_p1m.h b/roms/u-boot/include/configs/mpc8308_p1m.h new file mode 100644 index 000000000..489200996 --- /dev/null +++ b/roms/u-boot/include/configs/mpc8308_p1m.h @@ -0,0 +1,307 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ + +/* + * On-board devices + * + * TSECs + */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC2 + +#define CONFIG_SYS_GPIO1_PRELIM +/* GPIO Default input/output settings */ +#define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00 +/* + * Default GPIO values: + * LED#1 enabled; WLAN enabled; Both COM LED on (orange) + */ +#define CONFIG_SYS_GPIO1_DAT 0x08008C00 + +/* + * SERDES + */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 + +/* + * DDR Setup + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ + | DDRCDR_PZ_LOZ \ + | DDRCDR_NZ_LOZ \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN) + /* 0x7b880001 */ +/* + * Manually set up DDR parameters + * consist of two chips HY5PS12621BFP-C4 from HYNIX + */ + +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ + +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ODT_RD_NEVER \ + | CSCONFIG_ODT_WR_ONLY_CURRENT \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) + /* 0x80010102 */ +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00220802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (6 << TIMING_CFG1_REFREC_SHIFT) \ + | (2 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x27256222 */ +#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (4 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x121048c5 */ +#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x03600100 */ +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_32) + /* 0x43080000 */ + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ +#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0232 << SDRAM_MODE_SD_SHIFT)) + /* ODT 150ohm CL=3, AL=1 on SDRAM */ +#define CONFIG_SYS_DDR_MODE2 0x00000000 + +/* + * Memory test + */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ + + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +/* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024) +/* Flash Write Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024) + +/* + * SJA1000 CAN controller on Local Bus + */ +#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000 + + +/* + * CPLD on Local Bus + */ +#define CONFIG_SYS_CPLD_BASE 0xFBFF8000 + + +/* + * Serial Port + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + +/* enable PCIE clock */ +#define CONFIG_SYS_SCCR_PCIEXP1CM 1 + +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_PCIE + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 + +/* + * TSEC + */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) + +/* + * TSEC ethernet configuration + */ +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2_NAME "eTSEC1" +#define TSEC1_PHY_ADDR 1 +#define TSEC2_PHY_ADDR 2 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS 0 +#define TSEC2_FLAGS 0 + +/* Options are: eTSEC[0-1] */ +#define CONFIG_ETHPRIME "eTSEC0" + +/* + * Environment + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=${consoledev},${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ + "kernel_addr=FC0A0000\0" \ + "fdt_addr=FC2A0000\0" \ + "ramdisk_addr=FC2C0000\0" \ + "u-boot=mpc8308_p1m/u-boot.bin\0" \ + "kernel_addr_r=1000000\0" \ + "fdt_addr_r=C00000\0" \ + "hostname=mpc8308_p1m\0" \ + "bootfile=mpc8308_p1m/uImage\0" \ + "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \ + "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ + "flash_self=run ramargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "bootcmd=run flash_self\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ + " +${filesize};cp.b ${fileaddr} " \ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/mt7620.h b/roms/u-boot/include/configs/mt7620.h new file mode 100644 index 000000000..4d074a368 --- /dev/null +++ b/roms/u-boot/include/configs/mt7620.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao + */ + +#ifndef __CONFIG_MT7620_H +#define __CONFIG_MT7620_H + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN 0x100000 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR 0x80010000 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_CBSIZE 1024 + +/* Serial common */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* SPL */ +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SPL_BSS_START_ADDR 0x80010000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_PAD_TO 0 + +/* Dummy value */ +#define CONFIG_SYS_UBOOT_BASE 0 + +#endif /* __CONFIG_MT7620_H */ diff --git a/roms/u-boot/include/configs/mt7622.h b/roms/u-boot/include/configs/mt7622.h new file mode 100644 index 000000000..f015d10d9 --- /dev/null +++ b/roms/u-boot/include/configs/mt7622.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for MediaTek MT7629 SoC + * + * Copyright (C) 2019 MediaTek Inc. + * Author: Sam Shih + */ + +#ifndef __MT7622_H +#define __MT7622_H + +#include + +#define CONFIG_SYS_MAXARGS 8 +#define CONFIG_SYS_BOOTM_LEN SZ_64M +#define CONFIG_SYS_CBSIZE SZ_1K +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_4M +#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M + +/* Uboot definition */ +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE + +/* SPL -> Uboot */ +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ + GENERATED_GBL_DATA_SIZE) +/* UBoot -> Kernel */ +#define CONFIG_LOADADDR 0x4007ff28 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* DRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +/* Ethernet */ +#define CONFIG_IPADDR 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.3 + +#endif diff --git a/roms/u-boot/include/configs/mt7623.h b/roms/u-boot/include/configs/mt7623.h new file mode 100644 index 000000000..989527974 --- /dev/null +++ b/roms/u-boot/include/configs/mt7623.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for MediaTek MT7623 SoC + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Weijie Gao + */ + +#ifndef __MT7623_H +#define __MT7623_H + +#include + +/* Miscellaneous configurable options */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG + +#define CONFIG_SYS_MAXARGS 8 +#define CONFIG_SYS_BOOTM_LEN SZ_64M +#define CONFIG_SYS_CBSIZE SZ_1K +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_4M +#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M + +/* Environment */ + +/* Preloader -> Uboot */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ + GENERATED_GBL_DATA_SIZE) + +/* UBoot -> Kernel */ +#define CONFIG_LOADADDR 0x84000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* MMC */ +#define MMC_SUPPORTS_TUNING + +/* DRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* This is needed for kernel booting */ +#define FDT_HIGH "0xac000000" + +#define ENV_MEM_LAYOUT_SETTINGS \ + "fdt_high=" FDT_HIGH "\0" \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=" FDT_HIGH "\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" + +/* Ethernet */ +#define CONFIG_IPADDR 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.2 + +#ifdef CONFIG_DISTRO_DEFAULTS + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) + +#include + +/* Extra environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV + +#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ + +#endif diff --git a/roms/u-boot/include/configs/mt7628.h b/roms/u-boot/include/configs/mt7628.h new file mode 100644 index 000000000..c6752f4ac --- /dev/null +++ b/roms/u-boot/include/configs/mt7628.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao + */ + +#ifndef __CONFIG_MT7628_H +#define __CONFIG_MT7628_H + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN 0x100000 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR 0x80010000 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x80000 + +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_CBSIZE 1024 + +/* Serial SPL */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_CLK 40000000 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 0xb0000c00 +#endif + +/* Serial common */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 460800, 921600 } + +/* SPL */ +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SPL_BSS_START_ADDR 0x80010000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_PAD_TO 0 + +/* Dummy value */ +#define CONFIG_SYS_UBOOT_BASE 0 + +#endif /* __CONFIG_MT7628_H */ diff --git a/roms/u-boot/include/configs/mt7629.h b/roms/u-boot/include/configs/mt7629.h new file mode 100644 index 000000000..08a4d01f5 --- /dev/null +++ b/roms/u-boot/include/configs/mt7629.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for MediaTek MT7629 SoC + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + */ + +#ifndef __MT7629_H +#define __MT7629_H + +#include + +/* Miscellaneous configurable options */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG + +#define CONFIG_SYS_MAXARGS 8 +#define CONFIG_SYS_BOOTM_LEN SZ_64M +#define CONFIG_SYS_CBSIZE SZ_1K +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_4M +#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M + +/* Environment */ + +/* Defines for SPL */ +#define CONFIG_SPL_STACK 0x106000 +#define CONFIG_SPL_MAX_SIZE SZ_64K +#define CONFIG_SPL_MAX_FOOTPRINT SZ_64K +#define CONFIG_SPL_PAD_TO 0x10000 + +#define CONFIG_SPI_ADDR 0x30000000 +#define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) + +/* SPL -> Uboot */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ + GENERATED_GBL_DATA_SIZE) + +/* UBoot -> Kernel */ +#define CONFIG_SYS_SPL_ARGS_ADDR 0x40000000 +#define CONFIG_LOADADDR 0x42007f1c +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* DRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +/* Ethernet */ +#define CONFIG_IPADDR 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.2 + +#endif diff --git a/roms/u-boot/include/configs/mt8183.h b/roms/u-boot/include/configs/mt8183.h new file mode 100644 index 000000000..8e7afbb48 --- /dev/null +++ b/roms/u-boot/include/configs/mt8183.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for MT8183 based boards + * + * Copyright (C) 2021 BayLibre, SAS + * Author: Fabien Parent + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MALLOC_LEN SZ_4M + +#define CONFIG_CPU_ARMV8 +#define COUNTER_FREQUENCY 13000000 + +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_COM1 0x11005200 +#define CONFIG_SYS_NS16550_CLK 26000000 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* Environment settings */ +#include + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "scriptaddr=0x40000000\0" \ + BOOTENV + +#endif diff --git a/roms/u-boot/include/configs/mt8512.h b/roms/u-boot/include/configs/mt8512.h new file mode 100644 index 000000000..7cd388fa1 --- /dev/null +++ b/roms/u-boot/include/configs/mt8512.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for MediaTek MT8512 SoC + * + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee + */ + +#ifndef __MT8512_H +#define __MT8512_H + +#include + +#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M + +#define CONFIG_CPU_ARMV8 + +#define COUNTER_FREQUENCY 13000000 + +#define CONFIG_SYS_LOAD_ADDR 0x41000000 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +#define CONFIG_SYS_MALLOC_LEN SZ_32M +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* Uboot definition */ +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + \ + SZ_2M - \ + GENERATED_GBL_DATA_SIZE) + +#define ENV_BOOT_READ_IMAGE \ + "boot_rd_img=mmc dev 0" \ + ";mmc read ${loadaddr} 0x27000 0x8000" \ + ";iminfo ${loadaddr}\0" + +/* Console configuration */ +#define ENV_DEVICE_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define ENV_BOOT_CMD \ + "mtk_boot=run boot_rd_img;bootm;\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x6c000000\0" \ + ENV_DEVICE_SETTINGS \ + ENV_BOOT_READ_IMAGE \ + ENV_BOOT_CMD \ + "bootcmd=run mtk_boot;\0" \ + +#endif diff --git a/roms/u-boot/include/configs/mt8516.h b/roms/u-boot/include/configs/mt8516.h new file mode 100644 index 000000000..a1c5d8174 --- /dev/null +++ b/roms/u-boot/include/configs/mt8516.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for Pumpkin board + * + * Copyright (C) 2019 BayLibre, SAS + * Author: Fabien Parent + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MALLOC_LEN SZ_4M + +#define CONFIG_CPU_ARMV8 +#define COUNTER_FREQUENCY 13000000 + +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_COM1 0x11005000 +#define CONFIG_SYS_NS16550_CLK 26000000 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* Environment settings */ +#include + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "scriptaddr=0x40000000\0" \ + BOOTENV + +#endif diff --git a/roms/u-boot/include/configs/mt8518.h b/roms/u-boot/include/configs/mt8518.h new file mode 100644 index 000000000..4e32442bb --- /dev/null +++ b/roms/u-boot/include/configs/mt8518.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for MediaTek MT8518 SoC + * + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee + */ + +#ifndef __MT8518_H +#define __MT8518_H + +#include + +#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M + +#define CONFIG_CPU_ARMV8 + +#define COUNTER_FREQUENCY 13000000 + +/* DRAM definition */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_LOAD_ADDR 0x41000000 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +#define CONFIG_SYS_MALLOC_LEN SZ_32M +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* Uboot definition */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + \ + SZ_2M - \ + GENERATED_GBL_DATA_SIZE) + +#define ENV_BOOT_READ_IMAGE \ + "boot_rd_img=mmc dev 0" \ + ";mmc read ${loadaddr} 0x27400 0x4000" \ + ";iminfo ${loadaddr}\0" + +/* Console configuration */ +#define ENV_DEVICE_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define ENV_BOOT_CMD \ + "mtk_boot=run boot_rd_img;bootm;\0" + +#define ENV_FASTBOOT \ + "serial#=1234567890ABCDEF\0" \ + "board=mt8518\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x6c000000\0" \ + ENV_DEVICE_SETTINGS \ + ENV_BOOT_READ_IMAGE \ + ENV_FASTBOOT \ + ENV_BOOT_CMD \ + "bootcmd=run mtk_boot;\0" \ + +#endif diff --git a/roms/u-boot/include/configs/mv-common.h b/roms/u-boot/include/configs/mv-common.h new file mode 100644 index 000000000..d61c90a43 --- /dev/null +++ b/roms/u-boot/include/configs/mv-common.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + */ + +/* + * This file contains Marvell Board Specific common defincations. + * This file should be included in board config header file. + * + * It supports common definations for Kirkwood platform + * TBD: support for Orion5X platforms + */ + +#ifndef _MV_COMMON_H +#define _MV_COMMON_H + +#include + +/* + * High Level Configuration Options (easy to change) + */ + +/* + * Custom CONFIG_SYS_TEXT_BASE can be done in .h + */ + +/* additions for new ARM relocation support */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#if !defined(CONFIG_DM_SERIAL) +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE +#endif + +/* auto boot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 * 4) /* 4MiB for malloc() */ + +/* + * Other required minimal configurations + */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ + +/* ====> Include platform Common Definitions */ +#include + +/* ====> Include driver Common Definitions */ +/* + * Common NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#endif + +#endif /* _MV_COMMON_H */ diff --git a/roms/u-boot/include/configs/mv-plug-common.h b/roms/u-boot/include/configs/mv-plug-common.h new file mode 100644 index 000000000..486650f18 --- /dev/null +++ b/roms/u-boot/include/configs/mv-plug-common.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009-2015 + * Marvell Semiconductor + */ + +#ifndef _CONFIG_MARVELL_PLUG_H +#define _CONFIG_MARVELL_PLUG_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#endif /* _CONFIG_MARVELL_PLUG_H */ diff --git a/roms/u-boot/include/configs/mvebu_armada-37xx.h b/roms/u-boot/include/configs/mvebu_armada-37xx.h new file mode 100644 index 000000000..2ad4325ea --- /dev/null +++ b/roms/u-boot/include/configs/mvebu_armada-37xx.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Stefan Roese + */ + +#ifndef _CONFIG_MVEBU_ARMADA_37XX_H +#define _CONFIG_MVEBU_ARMADA_37XX_H + +#include + +/* + * High Level Configuration Options (easy to change) + */ + +/* additions for new ARM relocation support */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ + +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200, 230400, 460800, 921600 } + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ + +/* + * Other required minimal configurations + */ +#define CONFIG_SYS_LOAD_ADDR 0x06000000 /* default load adr */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ + +/* End of 16M scrubbed by training in bootrom */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) + +/* + * I2C + */ +#define CONFIG_I2C_MV +#define CONFIG_SYS_I2C_SLAVE 0x0 + +/* + * SPI Flash configuration + */ +#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ + +/* + * Environment + */ +#define DEFAULT_ENV_IS_RW /* required for configuring default fdtfile= */ + +/* + * Ethernet Driver configuration + */ +#define CONFIG_ARP_TIMEOUT 200 +#define CONFIG_NET_RETRY_COUNT 50 + +#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3) + +/* + * SATA/SCSI/AHCI configuration + */ +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_LBA48 +#define CONFIG_SYS_64BIT_LBA + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(SCSI, scsi, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +/* filler for default values filled by board_early_init_f() */ +#define ENV_RW_FILLER \ + "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" /* for ethaddr= */ \ + "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" /* for eth1addr= */ \ + "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" /* for eth2addr= */ \ + "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" /* for eth3addr= */ \ + "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" /* for fdtfile= */ \ + "" + +/* fdt_addr and kernel_addr are needed for existing distribution boot scripts */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "scriptaddr=0x6d00000\0" \ + "pxefile_addr_r=0x6e00000\0" \ + "fdt_addr=0x6f00000\0" \ + "fdt_addr_r=0x6f00000\0" \ + "kernel_addr=0x7000000\0" \ + "kernel_addr_r=0x7000000\0" \ + "ramdisk_addr_r=0xa000000\0" \ + BOOTENV \ + ENV_RW_FILLER + +#endif /* _CONFIG_MVEBU_ARMADA_37XX_H */ diff --git a/roms/u-boot/include/configs/mvebu_armada-8k.h b/roms/u-boot/include/configs/mvebu_armada-8k.h new file mode 100644 index 000000000..493e3de9b --- /dev/null +++ b/roms/u-boot/include/configs/mvebu_armada-8k.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Stefan Roese + */ + +#ifndef _CONFIG_MVEBU_ARMADA_8K_H +#define _CONFIG_MVEBU_ARMADA_8K_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* additions for new ARM relocation support */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +/* auto boot */ + +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200, 230400, 460800, 921600 } + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ + +/* + * Other required minimal configurations + */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ + +/* End of 16M scrubbed by training in bootrom */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) + +/* When runtime detection fails this is the default */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* + * Ethernet Driver configuration + */ +#define CONFIG_ARP_TIMEOUT 200 +#define CONFIG_NET_RETRY_COUNT 50 + +#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3) + +/* USB ethernet */ + +/* + * SATA/SCSI/AHCI configuration + */ +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_LBA48 +#define CONFIG_SYS_64BIT_LBA + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +/* + * PCI configuration + */ +#ifdef CONFIG_PCIE_DW_MVEBU +#define CONFIG_E1000 +#endif + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(SCSI, scsi, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "scriptaddr=0x6d00000\0" \ + "pxefile_addr_r=0x6e00000\0" \ + "fdt_addr_r=0x6f00000\0" \ + "kernel_addr_r=0x7000000\0" \ + "ramdisk_addr_r=0xa000000\0" \ + "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + BOOTENV + +#endif /* _CONFIG_MVEBU_ARMADA_8K_H */ diff --git a/roms/u-boot/include/configs/mx23_olinuxino.h b/roms/u-boot/include/configs/mx23_olinuxino.h new file mode 100644 index 000000000..2ee41aeff --- /dev/null +++ b/roms/u-boot/include/configs/mx23_olinuxino.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Marek Vasut + */ +#ifndef __CONFIGS_MX23_OLINUXINO_H__ +#define __CONFIGS_MX23_OLINUXINO_H__ + +/* System configurations */ +#define CONFIG_MACH_TYPE 4105 + +/* U-Boot Commands */ + +/* Memory configuration */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Status LED */ + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_MXS_PORT0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + +/* Ethernet */ + +/* Booting Linux */ +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Extra Environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "update_sd_firmware_filename=u-boot.sd\0" \ + "update_sd_firmware=" /* Update the SD firmware partition */ \ + "if mmc rescan ; then " \ + "if tftp ${update_sd_firmware_filename} ; then " \ + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ + "setexpr fw_sz ${fw_sz} + 1 ; " \ + "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ + "fi ; " \ + "fi\0" \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "console=ttyAMA0\0" \ + "fdt_file=imx23-olinuxino.dtb\0" \ + "fdt_addr=0x41000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "usb start; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${uimage}; " \ + "if test ${boot_fdt} = yes; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi;" \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_MX23_OLINUXINO_H__ */ diff --git a/roms/u-boot/include/configs/mx23evk.h b/roms/u-boot/include/configs/mx23evk.h new file mode 100644 index 000000000..3f13e6053 --- /dev/null +++ b/roms/u-boot/include/configs/mx23evk.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale i.MX23 EVK board config + * + * Copyright (C) 2013 Otavio Salvador + * on behalf of O.S. Systems Software LTDA. + */ +#ifndef __CONFIGS_MX23EVK_H__ +#define __CONFIGS_MX23EVK_H__ + +/* System configurations */ +#define CONFIG_MACH_TYPE MACH_TYPE_MX23EVK + +/* U-Boot Commands */ + +/* Memory configuration */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Environment */ + +/* Environment is in MMC */ + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_MXS_PORT0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + +/* Framebuffer support */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_LOGO +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) +#endif + +/* Boot Linux */ +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Extra Environments */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "update_sd_firmware_filename=u-boot.sd\0" \ + "update_sd_firmware=" /* Update the SD firmware partition */ \ + "if mmc rescan ; then " \ + "if tftp ${update_sd_firmware_filename} ; then " \ + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ + "setexpr fw_sz ${fw_sz} + 1 ; " \ + "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ + "fi ; " \ + "fi\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttyAMA0\0" \ + "fdt_file=imx23-evk.dtb\0" \ + "fdt_addr=0x41000000\0" \ + "boot_fdt=try\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else " \ + "echo ERR: Fail to boot from MMC; " \ + "fi; " \ + "fi; " \ + "else exit; fi" + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_MX23EVK_H__ */ diff --git a/roms/u-boot/include/configs/mx28evk.h b/roms/u-boot/include/configs/mx28evk.h new file mode 100644 index 000000000..a65df4860 --- /dev/null +++ b/roms/u-boot/include/configs/mx28evk.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 Freescale Semiconductor, Inc. + * Author: Fabio Estevam + * + * Based on m28evk.h: + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ +#ifndef __CONFIGS_MX28EVK_H__ +#define __CONFIGS_MX28EVK_H__ + +/* System configurations */ +#define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK + +/* Memory configuration */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Environment */ + +/* Environment is in MMC */ + +/* Environment is in NAND */ +#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) +#define CONFIG_ENV_RANGE (512 * 1024) +#endif + +/* Environment is in SPI flash */ + +/* UBI and NAND partitioning */ + +/* FEC Ethernet on SoC */ +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_MDIO_BASE MXS_ENET0_BASE +#define CONFIG_MX28_FEC_MAC_IN_OCOTP +#endif + +/* RTC */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MXS +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_MXS_PORT1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + +/* Framebuffer support */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_LOGO +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) +#endif + +/* Boot Linux */ +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Extra Environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ubifs_file=filesystem.ubifs\0" \ + "update_nand_full_filename=u-boot.nand\0" \ + "update_nand_firmware_filename=u-boot.sb\0" \ + "update_nand_firmware_maxsz=0x100000\0" \ + "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \ + "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \ + "update_nand_get_fcb_size=" /* Get size of FCB blocks */ \ + "nand device 0 ; " \ + "nand info ; " \ + "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \ + "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \ + "update_nand_firmware_full=" /* Update FCB, DBBT and FW */ \ + "if tftp ${update_nand_full_filename} ; then " \ + "run update_nand_get_fcb_size ; " \ + "nand scrub -y 0x0 ${filesize} ; " \ + "nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \ + "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \ + "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \ + "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \ + "fi\0" \ + "update_nand_firmware=" /* Update only firmware */ \ + "if tftp ${update_nand_firmware_filename} ; then " \ + "run update_nand_get_fcb_size ; " \ + "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \ + "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \ + "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \ + "nand erase ${fcb_sz} ${fw_sz} ; " \ + "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ + "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ + "fi\0" \ + "update_nand_kernel=" /* Update kernel */ \ + "mtdparts default; " \ + "nand erase.part kernel; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "nand write ${loadaddr} kernel ${filesize}\0" \ + "update_nand_fdt=" /* Update fdt */ \ + "mtdparts default; " \ + "nand erase.part fdt; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${fdt_file}; " \ + "nand write ${loadaddr} fdt ${filesize}\0" \ + "update_nand_filesystem=" /* Update filesystem */ \ + "mtdparts default; " \ + "nand erase.part filesystem; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${ubifs_file}; " \ + "ubi part filesystem; " \ + "ubi create filesystem; " \ + "ubi write ${loadaddr} filesystem ${filesize}\0" \ + "nandargs=setenv bootargs console=${console_mainline},${baudrate} " \ + "rootfstype=ubifs ubi.mtd=6 root=ubi0_0 ${mtdparts}\0" \ + "nandboot=" /* Boot from NAND */ \ + "mtdparts default; " \ + "run nandargs; " \ + "nand read ${loadaddr} kernel 0x00400000; " \ + "if test ${boot_fdt} = yes; then " \ + "nand read ${fdt_addr} fdt 0x00080000; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = no; then " \ + "bootz; " \ + "else " \ + "echo \"ERROR: Set boot_fdt to yes or no.\"; " \ + "fi; " \ + "fi\0" \ + "update_sd_firmware_filename=u-boot.sd\0" \ + "update_sd_firmware=" /* Update the SD firmware partition */ \ + "if mmc rescan ; then " \ + "if tftp ${update_sd_firmware_filename} ; then " \ + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ + "setexpr fw_sz ${fw_sz} + 1 ; " \ + "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ + "fi ; " \ + "fi\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console_fsl=ttyAM0\0" \ + "console_mainline=ttyAMA0\0" \ + "fdt_file=imx28-evk.dtb\0" \ + "fdt_addr=0x41000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \ + "mmcargs=setenv bootargs console=${console_mainline},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console_mainline},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi;" \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_MX28EVK_H__ */ diff --git a/roms/u-boot/include/configs/mx51evk.h b/roms/u-boot/include/configs/mx51evk.h new file mode 100644 index 000000000..3574d6545 --- /dev/null +++ b/roms/u-boot/include/configs/mx51evk.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX51EVK Board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + /* High Level Configuration Options */ + +#define CONFIG_SYS_FSL_CLK + +#include + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_MACH_TYPE MACH_TYPE_MX51_BABBAGE +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +/* + * Hardware drivers + */ +#define CONFIG_FSL_IIM + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* PMIC Controller */ +#define CONFIG_POWER +#define CONFIG_POWER_SPI +#define CONFIG_POWER_FSL +#define CONFIG_FSL_PMIC_BUS 0 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 2500000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_BITLEN 32 +#define CONFIG_RTC_MC13XXX + +/* + * MMC Configs + * */ +#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR +#define CONFIG_SYS_FSL_ESDHC_NUM 2 + +/* USB Configs */ +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI +#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED + +/* Framebuffer and LCD */ +#define CONFIG_VIDEO_LOGO + +#define CONFIG_ETHPRIME "FEC0" + +#define CONFIG_LOADADDR 0x92000000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "fdt_file=imx51-babbage.dtb\0" \ + "fdt_addr=0x91000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo ERROR: Cannot load the DT; " \ + "exit; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_DDR_CLKSEL 0 +#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 +#define CONFIG_SYS_MAIN_PWR_ON + +/*----------------------------------------------------------------------- + * environment organization + */ + +/* + * Environment starts at CONFIG_ENV_OFFSET=0xC0000 = 768k = 768 * 1024 = 786432 + * + * Detect overlap between U-Boot image and environment area in build-time + * + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset + * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408 + * + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so + * write the direct value here + */ +#define CONFIG_BOARD_SIZE_LIMIT 785408 + +#endif diff --git a/roms/u-boot/include/configs/mx53cx9020.h b/roms/u-boot/include/configs/mx53cx9020.h new file mode 100644 index 000000000..93158fb46 --- /dev/null +++ b/roms/u-boot/include/configs/mx53cx9020.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG + * Patrick Bruenn + * + * Configuration settings for Beckhoff CX9020. + * + * Based on Freescale's Linux i.MX mx53loco.h file: + * Copyright (C) 2010-2011 Freescale Semiconductor. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_SYS_FSL_CLK + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) + +#define CONFIG_REVISION_TAG + +#define CONFIG_MXC_UART_BASE UART2_BASE + +#define CONFIG_FPGA_COUNT 1 + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 2 + +/* bootz: zImage/initrd.img support */ + + +/* USB Configs */ +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* Command definition */ + +#define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr_r=0x75000000\0" \ + "pxefile_addr_r=0x73000000\0" \ + "scriptaddr=0x74000000\0" \ + "ramdisk_addr_r=0x80000000\0" \ + "kernel_addr_r=0x72000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc1,115200\0" \ + "stdin=serial\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ + "fdtfile=imx53-cx9020.dtb\0" \ + BOOTENV + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_SIZE (gd->ram_size) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* environment organization */ + +/* Framebuffer and LCD */ +#define CONFIG_IMX_VIDEO_SKIP + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/mx53loco.h b/roms/u-boot/include/configs/mx53loco.h new file mode 100644 index 000000000..e5dc9ac1d --- /dev/null +++ b/roms/u-boot/include/configs/mx53loco.h @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu + * + * Configuration settings for Freescale MX53 low cost board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO + +#include + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_SYS_FSL_CLK + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#define CONFIG_REVISION_TAG + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 2 + +/* USB Configs */ +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +/* PMIC Controller */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_DIALOG_POWER +#define CONFIG_POWER_FSL +#define CONFIG_POWER_FSL_MC13892 +#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 +#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 + +/* Command definition */ + + +#define CONFIG_ETHPRIME "FEC0" + +#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "fdt_addr=0x71000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ + "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \ + "loadbootscript=" \ + "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo ERROR: Cannot load the DT; " \ + "exit; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_SIZE (gd->ram_size) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment starts at 768k = 768 * 1024 = 786432 */ +/* + * Detect overlap between U-Boot image and environment area in build-time + * + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset + * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408 + * + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so + * write the direct value here + */ +#define CONFIG_BOARD_SIZE_LIMIT 785408 + +#ifdef CONFIG_CMD_SATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_DWC_AHSATA_PORT_ID 0 + #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR + #define CONFIG_LBA48 +#endif + +/* Framebuffer and LCD */ +#define CONFIG_VIDEO_LOGO + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/mx53ppd.h b/roms/u-boot/include/configs/mx53ppd.h new file mode 100644 index 000000000..b1e6a5638 --- /dev/null +++ b/roms/u-boot/include/configs/mx53ppd.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu + * + * Configuration settings for Freescale MX53 low cost board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_SYS_FSL_CLK + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#define CONFIG_REVISION_TAG + +/* USB Configs */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* Command definition */ + +#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ + +#define PPD_CONFIG_NFS \ + "nfsserver=192.168.252.95\0" \ + "gatewayip=192.168.252.95\0" \ + "netmask=255.255.255.0\0" \ + "ipaddr=192.168.252.99\0" \ + "kernsize=0x2000\0" \ + "use_dhcp=0\0" \ + "nfsroot=/opt/springdale/rd\0" \ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ + "${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \ + "choose_ip=if test $use_dhcp = 1; then setenv kern_ipconf ip=dhcp; " \ + "setenv getcmd dhcp; else setenv kern_ipconf " \ + "ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; " \ + "setenv getcmd tftp; fi\0" \ + "nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \ + "${nfsserver}:${image}; bootm ${loadaddr}\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + PPD_CONFIG_NFS \ + "image=/boot/fitImage\0" \ + "dev=mmc\0" \ + "devnum=2\0" \ + "rootdev=mmcblk0p\0" \ + "quiet=quiet loglevel=0\0" \ + "lvds=ldb\0" \ + "setargs=setenv bootargs ${lvds} jtag=on mem=2G " \ + "vt.global_cursor_default=0 bootcause=${bootcause} ${quiet}\0" \ + "bootargs_emmc=setenv bootargs root=/dev/${rootdev}${partnum} ro " \ + "rootwait ${bootargs}\0" \ + "doquiet=" \ + "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \ + "then setenv quiet; fi\0" \ + "hasfirstboot=" \ + "test -e ${dev} ${devnum}:${partnum} /boot/bootcause/firstboot\0" \ + "swappartitions=" \ + "setexpr partnum 3 - ${partnum}\0" \ + "failbootcmd=" \ + "cls; " \ + "setcurs 5 4; " \ + "lcdputs \"Monitor failed to start. " \ + "Try again, or contact GE Service for support.\"; " \ + "bootcount reset; " \ + "while true; do sleep 1; done; \0" \ + "altbootcmd=" \ + "run doquiet; " \ + "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ + "run hasfirstboot || setenv partnum 0; " \ + "if test ${partnum} != 0; then " \ + "run swappartitions loadimage doboot; " \ + "fi; " \ + "run failbootcmd\0" \ + "loadimage=" \ + "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ + "doboot=" \ + "echo Booting from ${dev}:${devnum}:${partnum} ...; " \ + "run setargs; " \ + "run bootargs_emmc; " \ + "bootm ${loadaddr}\0" \ + "tryboot=" \ + "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ + "run loadimage || run swappartitions && run loadimage || " \ + "setenv partnum 0 && echo MISSING IMAGE;" \ + "run doboot; " \ + "run failbootcmd\0" \ + "video-mode=" \ + "lcd:800x480-24@60,monitor=lcd\0" \ + +#define CONFIG_MMCBOOTCOMMAND \ + "run doquiet; " \ + "run tryboot; " \ + +#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_MAXARGS 48 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_SIZE (gd->ram_size) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ + +#define CONFIG_FSL_IIM + +/* Backlight Control */ +#define CONFIG_IMX6_PWM_PER_CLK 66666000 + +#define CONFIG_IMX_VIDEO_SKIP + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/mx6_common.h b/roms/u-boot/include/configs/mx6_common.h new file mode 100644 index 000000000..83895ab9d --- /dev/null +++ b/roms/u-boot/include/configs/mx6_common.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef __MX6_COMMON_H +#define __MX6_COMMON_H + +#include + +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ +#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK +#else +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE L2_PL310_BASE +#endif + +#endif +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_MXC_GPT_HCLK + +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + +#include +#include +#include + +#ifndef CONFIG_MX6 +#define CONFIG_MX6 +#endif + +#define CONFIG_SYS_FSL_CLK + +/* ATAGs */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Boot options */ +#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ + defined(CONFIG_MX6SX) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) +#define CONFIG_LOADADDR 0x82000000 +#else +#define CONFIG_LOADADDR 0x12000000 +#endif +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 32 + +/* MMC */ + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#endif + +#endif diff --git a/roms/u-boot/include/configs/mx6cuboxi.h b/roms/u-boot/include/configs/mx6cuboxi.h new file mode 100644 index 000000000..55717c77a --- /dev/null +++ b/roms/u-boot/include/configs/mx6cuboxi.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the SolidRun mx6 based boards + */ +#ifndef __MX6CUBOXI_CONFIG_H +#define __MX6CUBOXI_CONFIG_H + +#include + +#include "mx6_common.h" + +#include "imx6_spl.h" + +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* SATA Configuration */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#endif + +/* Framebuffer */ +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +/* USB */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +/* Command definition */ + +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONSOLE_DEV "ttymxc0" + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "som_rev=undefined\0" \ + "has_emmc=undefined\0" \ + "fdtfile=undefined\0" \ + "fdt_addr_r=0x18000000\0" \ + "fdt_addr=0x18000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "ramdiskaddr=0x13000000\0" \ + "initrd_high=0xffffffff\0" \ + "ip_dyn=yes\0" \ + "console=" CONSOLE_DEV ",115200\0" \ + "bootm_size=0x10000000\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "finduuid=part uuid mmc 0:1 uuid\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + "findfdt="\ + "if test ${board_rev} = MX6Q; then " \ + "setenv fdtprefix imx6q; fi; " \ + "if test ${board_rev} = MX6DL; then " \ + "setenv fdtprefix imx6dl; fi; " \ + "if test ${som_rev} = V15; then " \ + "setenv fdtsuffix -som-v15; fi; " \ + "if test ${has_emmc} = yes; then " \ + "setenv emmcsuffix -emmc; fi; " \ + "if test ${board_name} = HUMMINGBOARD2 ; then " \ + "setenv fdtfile ${fdtprefix}-hummingboard2${emmcsuffix}${fdtsuffix}.dtb; fi; " \ + "if test ${board_name} = HUMMINGBOARD ; then " \ + "setenv fdtfile ${fdtprefix}-hummingboard${emmcsuffix}${fdtsuffix}.dtb; fi; " \ + "if test ${board_name} = CUBOXI ; then " \ + "setenv fdtfile ${fdtprefix}-cubox-i${emmcsuffix}${fdtsuffix}.dtb; fi; " \ + "if test ${fdtfile} = undefined; then " \ + "echo WARNING: Could not determine dtb to use; fi; \0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(SATA, sata, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#else +#define CONFIG_EXTRA_ENV_SETTINGS +#endif /* CONFIG_SPL_BUILD */ + +/* Physical Memory Map */ +#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ + +#endif /* __MX6CUBOXI_CONFIG_H */ diff --git a/roms/u-boot/include/configs/mx6memcal.h b/roms/u-boot/include/configs/mx6memcal.h new file mode 100644 index 000000000..120297dac --- /dev/null +++ b/roms/u-boot/include/configs/mx6memcal.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2010-2018 Freescale Semiconductor, Inc. + * + * Configuration settings for the virtual mx6memcal board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* SPL */ + +#include "mx6_common.h" +#include "imx6_spl.h" + +#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) + +#ifdef CONFIG_SERIAL_CONSOLE_UART1 +#if defined(CONFIG_MX6SL) +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR +#else +#define CONFIG_MXC_UART_BASE UART1_BASE +#endif +#elif defined(CONFIG_SERIAL_CONSOLE_UART2) +#define CONFIG_MXC_UART_BASE UART2_BASE +#else +#error please define serial console (CONFIG_SERIAL_CONSOLE_UARTx) +#endif + +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16) + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MXC_USB_PORTSC PORT_PTS_UTMI + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/mx6sabre_common.h b/roms/u-boot/include/configs/mx6sabre_common.h new file mode 100644 index 000000000..ac579f333 --- /dev/null +++ b/roms/u-boot/include/configs/mx6sabre_common.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6Q SabreSD board. + */ + +#ifndef __MX6QSABRE_COMMON_CONFIG_H +#define __MX6QSABRE_COMMON_CONFIG_H + +#include + +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#ifdef CONFIG_SUPPORT_EMMC_BOOT +#define EMMC_ENV \ + "emmcdev=2\0" \ + "update_emmc_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "if mmc dev ${emmcdev} 1; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" +#else +#define EMMC_ENV "" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "fdtfile=undefined\0" \ + "fdt_addr=0x18000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "console=" CONSOLE_DEV "\0" \ + "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ + "dfu_alt_info_spl=spl raw 0x400\0" \ + "dfu_alt_info_img=u-boot raw 0x10000\0" \ + "dfu_alt_info=spl raw 0x400\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=1\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + EMMC_ENV \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=PARTUUID=${uuid} rootwait rw\0" \ + "loadbootscript=" \ + "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script} || " \ + "load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} || " \ + "load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \ + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile} || " \ + "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run finduuid; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "findfdt="\ + "if test $fdtfile = undefined; then " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \ + "setenv fdtfile imx6qp-sabreauto.dtb; fi; " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \ + "setenv fdtfile imx6q-sabreauto.dtb; fi; " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \ + "setenv fdtfile imx6dl-sabreauto.dtb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6QP; then " \ + "setenv fdtfile imx6qp-sabresd.dtb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6Q; then " \ + "setenv fdtfile imx6q-sabresd.dtb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \ + "setenv fdtfile imx6dl-sabresd.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine dtb to use; fi; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "run findfdt;" \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ + +/* Framebuffer */ +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +#define CONFIG_USBD_HS + +#endif /* __MX6QSABRE_COMMON_CONFIG_H */ diff --git a/roms/u-boot/include/configs/mx6sabreauto.h b/roms/u-boot/include/configs/mx6sabreauto.h new file mode 100644 index 000000000..118967771 --- /dev/null +++ b/roms/u-boot/include/configs/mx6sabreauto.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6Q SabreAuto board. + */ + +#ifndef __MX6SABREAUTO_CONFIG_H +#define __MX6SABREAUTO_CONFIG_H + +#ifdef CONFIG_SPL +#include "imx6_spl.h" +#endif + +#define CONFIG_MACH_TYPE 3529 +#define CONFIG_MXC_UART_BASE UART4_BASE +#define CONSOLE_DEV "ttymxc3" + +/* USB Configs */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } + +#include "mx6sabre_common.h" + +/* Falcon Mode */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 + +/* Falcon Mode - MMC support: args@1MB kernel@2MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#endif + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +#endif /* __MX6SABREAUTO_CONFIG_H */ diff --git a/roms/u-boot/include/configs/mx6sabresd.h b/roms/u-boot/include/configs/mx6sabresd.h new file mode 100644 index 000000000..e8f52cee2 --- /dev/null +++ b/roms/u-boot/include/configs/mx6sabresd.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6Q SabreSD board. + */ + +#ifndef __MX6SABRESD_CONFIG_H +#define __MX6SABRESD_CONFIG_H + +#ifdef CONFIG_SPL +#include "imx6_spl.h" +#endif + +#define CONFIG_MACH_TYPE 3980 +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONSOLE_DEV "ttymxc0" + +#include "mx6sabre_common.h" + +/* Falcon Mode */ +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 + +/* Falcon Mode - MMC support: args@1MB kernel@2MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ + +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) +#endif + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ +#endif + +#endif /* __MX6SABRESD_CONFIG_H */ diff --git a/roms/u-boot/include/configs/mx6slevk.h b/roms/u-boot/include/configs/mx6slevk.h new file mode 100644 index 000000000..ab32f4e15 --- /dev/null +++ b/roms/u-boot/include/configs/mx6slevk.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SL EVK board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + +#ifdef CONFIG_SPL +#include "imx6_spl.h" +#endif + +#define CONFIG_MACH_TYPE MACH_TYPE_MX6SL_EVK + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* I2C Configs */ +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx6sl-evk.dtb\0" \ + "fdt_addr=0x88000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=1\0" \ + "mmcpart=1\0" \ + "finduuid=part uuid mmc 1:2 uuid\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=PARTUUID=${uuid} rootwait rw\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run finduuid; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/mx6sllevk.h b/roms/u-boot/include/configs/mx6sllevk.h new file mode 100644 index 000000000..a38ce4d09 --- /dev/null +++ b/roms/u-boot/include/configs/mx6sllevk.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SL EVK board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* I2C Configs */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "epdc_waveform=epdc_splash.bin\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx6sll-evk.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=1\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "usb start; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_2G + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +#define CONFIG_IOMUX_LPSR + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +#include +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/mx6sxsabreauto.h b/roms/u-boot/include/configs/mx6sxsabreauto.h new file mode 100644 index 000000000..58cc3f0ee --- /dev/null +++ b/roms/u-boot/include/configs/mx6sxsabreauto.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SX Sabreauto board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_BASE + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx6sx-sabreauto.dtb\0" \ + "fdt_addr=0x88000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR + +/* I2C Configs */ +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ + +/* Network */ + +#define CONFIG_FEC_MXC + +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0 + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" + +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/mx6sxsabresd.h b/roms/u-boot/include/configs/mx6sxsabresd.h new file mode 100644 index 000000000..036881f6e --- /dev/null +++ b/roms/u-boot/include/configs/mx6sxsabresd.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SX Sabresd board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "mx6_common.h" + +#ifdef CONFIG_SPL +#include "imx6_spl.h" +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_BASE + +#ifdef CONFIG_IMX_BOOTAUX +/* Set to QSPI2 B flash at default */ +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 + +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe 1:0; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x0 ${fw_sz}; " \ + "sf write ${loadaddr} 0x0 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV "" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + UPDATE_M4_ENV \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx6sx-sdb.dtb\0" \ + "fdt_addr=0x88000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \ + "mmcdev=3\0" \ + "mmcpart=1\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=PARTUUID=${uuid} rootwait rw\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run finduuid; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "findfdt="\ + "if test test $board_rev = REVA ; then " \ + "setenv fdt_file imx6sx-sdb-reva.dtb; fi; " \ + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR + +/* I2C Configs */ +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* Network */ +#define CONFIG_FEC_MXC + +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" + +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) +#endif + +#ifndef CONFIG_SPL_BUILD +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR +#endif +#endif + +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/mx6ul_14x14_evk.h b/roms/u-boot/include/configs/mx6ul_14x14_evk.h new file mode 100644 index 000000000..7d36c1e4d --- /dev/null +++ b/roms/u-boot/include/configs/mx6ul_14x14_evk.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL 14x14 EVK board. + */ +#ifndef __MX6UL_14X14_EVK_CONFIG_H +#define __MX6UL_14X14_EVK_CONFIG_H + +#include +#include +#include +#include "mx6_common.h" +#include + +#define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) + +/* SPL options */ +#include "imx6_spl.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#ifdef CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* NAND pin conflicts with usdhc2 */ +#ifdef CONFIG_NAND_MXS +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +#endif + +/* I2C configs */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=undefined\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "if test $board_name = EVK && test $board_rev = 9X9; then " \ + "setenv fdt_file imx6ul-9x9-evk.dtb; fi; " \ + "if test $board_name = EVK && test $board_rev = 14X14; then " \ + "setenv fdt_file imx6ul-14x14-evk.dtb; fi; " \ + "if test $fdt_file = undefined; then " \ + "echo WARNING: Could not determine dtb to use; fi; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "run findfdt;" \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* environment organization */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_ENET_DEV 1 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth1" +#endif +#endif + +#ifndef CONFIG_SPL_BUILD +#if defined(CONFIG_DM_VIDEO) +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR +#endif +#endif + +#endif diff --git a/roms/u-boot/include/configs/mx6ullevk.h b/roms/u-boot/include/configs/mx6ullevk.h new file mode 100644 index 000000000..23f6de905 --- /dev/null +++ b/roms/u-boot/include/configs/mx6ullevk.h @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL 14x14 EVK board. + */ +#ifndef __MX6ULLEVK_CONFIG_H +#define __MX6ULLEVK_CONFIG_H + + +#include +#include +#include +#include "mx6_common.h" +#include + +#define PHYS_SDRAM_SIZE SZ_512M + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#ifdef CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* NAND pin conflicts with usdhc2 */ +#ifdef CONFIG_SYS_USE_NAND +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif +#endif + +/* I2C configs */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=undefined\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \ + "setenv fdt_file imx6ulz-14x14-evk.dtb; fi; " \ + "if test $board_name = EVK && test $board_rev = 14X14; then " \ + "setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \ + "if test $fdt_file = undefined; then " \ + "echo WARNING: Could not determine dtb to use; " \ + "fi; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "run findfdt;" \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* environment organization */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#define CONFIG_IOMUX_LPSR + +#define CONFIG_SOFT_SPI + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_ENET_DEV 1 +#if (CONFIG_FEC_ENET_DEV == 0) +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define CONFIG_ETHPRIME "eth1" +#endif +#endif + +#endif diff --git a/roms/u-boot/include/configs/mx7_common.h b/roms/u-boot/include/configs/mx7_common.h new file mode 100644 index 000000000..bd779aecd --- /dev/null +++ b/roms/u-boot/include/configs/mx7_common.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7. + */ + +#ifndef __MX7_COMMON_H +#define __MX7_COMMON_H + +#include +#include +#include +#include + +#ifndef CONFIG_MX7 +#define CONFIG_MX7 +#endif + +/* Timer settings */ +#define CONFIG_MXC_GPT_HCLK +#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ +#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + +/* Enable iomux-lpsr support */ +#define CONFIG_IOMUX_LPSR + +#define CONFIG_LOADADDR 0x80800000 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 32 + +/* UART */ + +/* MMC */ + +#define CONFIG_ARMV7_SECURE_BASE 0x00900000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#endif + +/* + * If we have defined the OPTEE ram size and not OPTEE it means that we were + * launched by OPTEE, because of that we shall skip all the low level + * initialization since it was already done by ATF or OPTEE + */ +#if (CONFIG_OPTEE_TZDRAM_SIZE != 0) +#ifndef CONFIG_OPTEE +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif +#endif + +#endif diff --git a/roms/u-boot/include/configs/mx7dsabresd.h b/roms/u-boot/include/configs/mx7dsabresd.h new file mode 100644 index 000000000..5801da0cf --- /dev/null +++ b/roms/u-boot/include/configs/mx7dsabresd.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D SABRESD board. + */ + +#ifndef __MX7D_SABRESD_CONFIG_H +#define __MX7D_SABRESD_CONFIG_H + +#include "mx7_common.h" + +#define PHYS_SDRAM_SIZE SZ_1G + +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +/* I2C configs */ +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#ifdef CONFIG_IMX_BOOTAUX +/* Set to QSPI1 A flash at default */ +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000 + +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe 0:0; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x0 ${fw_sz}; " \ + "sf write ${loadaddr} 0x0 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#define CONFIG_DFU_ENV_SETTINGS \ + "dfu_alt_info=image raw 0 0x800000;"\ + "u-boot raw 0 0x4000;"\ + "bootimg part 0 1;"\ + "rootfs part 0 2\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + UPDATE_M4_ENV \ + CONFIG_MFG_ENV_SETTINGS \ + CONFIG_DFU_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "finduuid=part uuid mmc 0:1 uuid\0" \ + "initrd_high=0xffffffff\0" \ + "fdtfile=imx7d-sdb.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_addr_r=0x83000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x83100000\0" \ + "ramdiskaddr=0x83100000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) \ + func(PXE, pxe, na) + +#include + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* environment organization */ + +/* + * If want to use nand, define CONFIG_NAND_MXS and rework board + * to support nand, since emmc has pin conflicts with nand + */ +#ifdef CONFIG_NAND_MXS +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#endif + +#ifdef CONFIG_NAND_MXS +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +/* USB Configs */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +#define CONFIG_USBD_HS + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/mx7ulp_com.h b/roms/u-boot/include/configs/mx7ulp_com.h new file mode 100644 index 000000000..28672c4f9 --- /dev/null +++ b/roms/u-boot/include/configs/mx7ulp_com.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Embedded Artists i.MX7ULP COM board. + */ + +#ifndef __MX7ULP_COM_CONFIG_H +#define __MX7ULP_COM_CONFIG_H + +#include +#include + +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + +/* + * Detect overlap between U-Boot image and environment area in build-time + * + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot-dtb.imx offset + * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408 + * + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so + * write the direct value here + */ +#define CONFIG_BOARD_SIZE_LIMIT 785408 +#define CONFIG_MMCROOT "/dev/mmcblk0p2" +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG1_RBASE + +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */ + +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) + +/* UART */ +#define LPUART_BASE LPUART4_RBASE + +/* Physical Memory Map */ + +#define PHYS_SDRAM 0x60000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + +#define CONFIG_LOADADDR 0x60800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "image=zImage\0" \ + "console=ttyLP0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx7ulp-com.dtb\0" \ + "fdt_addr=0x63000000\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if run loadimage; then " \ + "run mmcboot; " \ + "fi; " \ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/mx7ulp_evk.h b/roms/u-boot/include/configs/mx7ulp_evk.h new file mode 100644 index 000000000..0c3103082 --- /dev/null +++ b/roms/u-boot/include/configs/mx7ulp_evk.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7ULP EVK board. + */ + +#ifndef __MX7ULP_EVK_CONFIG_H +#define __MX7ULP_EVK_CONFIG_H + +#include +#include + +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG1_RBASE + +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ + +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +/*#define CONFIG_REVISION_TAG*/ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) + +/* UART */ +#define LPUART_BASE LPUART4_RBASE + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 512 + +#define CONFIG_SYS_MAXARGS 256 + +/* Physical Memory Map */ + +#define PHYS_SDRAM 0x60000000 +#define PHYS_SDRAM_SIZE SZ_1G +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + +#define CONFIG_LOADADDR 0x60800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttyLP0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx7ulp-evk.dtb\0" \ + "fdt_addr=0x63000000\0" \ + "boot_fdt=try\0" \ + "earlycon=lpuart32,0x402D0010\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "usb start; "\ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi" + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/mxs.h b/roms/u-boot/include/configs/mxs.h new file mode 100644 index 000000000..325c3ee00 --- /dev/null +++ b/roms/u-boot/include/configs/mxs.h @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2013 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIGS_MXS_H__ +#define __CONFIGS_MXS_H__ + +/* + * Includes + */ + +#if defined(CONFIG_MX23) && defined(CONFIG_MX28) +#error Select either CONFIG_MX23 or CONFIG_MX28 , never both! +#elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28) +#error Select one of CONFIG_MX23 or CONFIG_MX28 ! +#endif + +#include + +#if defined(CONFIG_MX23) +#include +#elif defined(CONFIG_MX28) +#include +#endif + +/* + * CPU specifics + */ + +/* Startup hooks */ + +/* SPL */ +#ifndef CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_NO_CPU_SUPPORT +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" +#endif + +/* Memory sizes */ +#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ + +/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 +#if defined(CONFIG_MX23) +#define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024) +#elif defined(CONFIG_MX28) +#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) +#endif + +/* Point initial SP in SRAM so SPL can use it too. */ +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* + * We need to sacrifice first 4 bytes of RAM here to avoid triggering some + * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot + * binary. In case there was more of this mess, 0x100 bytes are skipped. + * + * In case of a HAB boot, we cannot for some weird reason use the first 4KiB + * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST + * blocks, thus U-Boot starts at offset +8 KiB of DRAM start. + * + * As for the SPL, we must avoid the first 4 KiB as well, but we load the + * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB. + */ + +/* U-Boot general configuration */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ + +/* Booting Linux */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +/* + * Drivers + */ +/* + * DUART Serial Driver. + * Conflicts with AUART driver which can be set by board. + */ +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } +/* Default baudrate can be overridden by board! */ + +/* FEC Ethernet on SoC */ +#ifdef CONFIG_FEC_MXC +#ifndef CONFIG_ETHPRIME +#define CONFIG_ETHPRIME "FEC0" +#endif +#ifndef CONFIG_FEC_XCV_TYPE +#define CONFIG_FEC_XCV_TYPE RMII +#endif +#endif + +/* LCD */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#endif + +/* NAND */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x60000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#endif + +/* OCOTP */ +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXS_OCOTP +#endif + +/* SPI */ +#ifdef CONFIG_CMD_SPI +#define CONFIG_SPI_HALF_DUPLEX +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI_MXS +#define CONFIG_EHCI_IS_TDI +#endif + +#endif /* __CONFIGS_MXS_H__ */ diff --git a/roms/u-boot/include/configs/mys_6ulx.h b/roms/u-boot/include/configs/mys_6ulx.h new file mode 100644 index 000000000..5ef16fb27 --- /dev/null +++ b/roms/u-boot/include/configs/mys_6ulx.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi + */ + +#ifndef __MYS_6ULX_H +#define __MYS_6ULX_H + +#include +#include "mx6_common.h" + +/* SPL options */ +#include "imx6_spl.h" + +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +/* Console configs */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_256M + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* NAND */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200n8\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "fdt_addr_r=0x82000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ + "ramdisk_addr_r=0x82100000\0" \ + "scriptaddr=0x87000000\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(UBIFS, ubifs, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#endif /* __MYS_6ULX_H */ diff --git a/roms/u-boot/include/configs/nas220.h b/roms/u-boot/include/configs/nas220.h new file mode 100644 index 000000000..1fd5471ac --- /dev/null +++ b/roms/u-boot/include/configs/nas220.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Evgeni Dobrev + * + * based on work from: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + */ + +#ifndef _CONFIG_NAS220_H +#define _CONFIG_NAS220_H + +/* + * Machine type ID + */ +#define CONFIG_MACH_TYPE MACH_TYPE_RD88F6192_NAS + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */ +#define CONFIG_KW88F6192 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* power-on led, regulator, sata0, sata1 */ +#define NAS220_GE_OE_VAL_LOW ((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28)) +#define NAS220_GE_OE_VAL_HIGH (0) +#define NAS220_GE_OE_LOW (~((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28))) +#define NAS220_GE_OE_HIGH (~(0)) + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#include "mv-common.h" + +/* + * Environment variables configurations + */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=console=ttyS0,115200\0" \ + "mtdparts=mtdparts=orion_nand:0xa0000@0x0(uboot),"\ + "0x010000@0xa0000(env),"\ + "0x500000@0xc0000(uimage),"\ + "0x1a40000@0x5c0000(rootfs)\0" \ + "mtdids=nand0=orion_nand\0"\ + "autostart=no\0"\ + "autoload=no\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 8 +#endif /* CONFIG_CMD_NET */ + +/* + * USB/EHCI + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ +#define CONFIG_EHCI_IS_TDI +#endif /* CONFIG_CMD_USB */ + +/* + * File system + */ +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_LZO + +/* + * EFI partition + */ + +#define CONFIG_KIRKWOOD_GPIO + +#endif /* _CONFIG_NAS220_H */ + diff --git a/roms/u-boot/include/configs/netgear_cg3100d.h b/roms/u-boot/include/configs/netgear_cg3100d.h new file mode 100644 index 000000000..8d2b3e73a --- /dev/null +++ b/roms/u-boot/include/configs/netgear_cg3100d.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#include +#include + diff --git a/roms/u-boot/include/configs/netgear_dgnd3700v2.h b/roms/u-boot/include/configs/netgear_dgnd3700v2.h new file mode 100644 index 000000000..779c20700 --- /dev/null +++ b/roms/u-boot/include/configs/netgear_dgnd3700v2.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + diff --git a/roms/u-boot/include/configs/nitrogen6x.h b/roms/u-boot/include/configs/nitrogen6x.h new file mode 100644 index 000000000..6448ea891 --- /dev/null +++ b/roms/u-boot/include/configs/nitrogen6x.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * + * Configuration settings for the Boundary Devices Nitrogen6X + * and Freescale i.MX6Q Sabre Lite boards. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + +#define CONFIG_MACH_TYPE 3769 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#define CONFIG_USBD_HS + +#define CONFIG_MXC_UART_BASE UART2_BASE + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_I2C_EDID + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#endif + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 6 + +/* USB Configs */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* Framebuffer and LCD */ +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024) +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +#ifdef CONFIG_CMD_MMC +#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) +#else +#define DISTRO_BOOT_DEV_MMC(func) +#endif + +#ifdef CONFIG_CMD_SATA +#define DISTRO_BOOT_DEV_SATA(func) func(SATA, sata, 0) +#else +#define DISTRO_BOOT_DEV_SATA(func) +#endif + +#ifdef CONFIG_USB_STORAGE +#define DISTRO_BOOT_DEV_USB(func) func(USB, usb, 0) +#else +#define DISTRO_BOOT_DEV_USB(func) +#endif + +#ifdef CONFIG_CMD_PXE +#define DISTRO_BOOT_DEV_PXE(func) func(PXE, pxe, na) +#else +#define DISTRO_BOOT_DEV_PXE(func) +#endif + +#ifdef CONFIG_CMD_DHCP +#define DISTRO_BOOT_DEV_DHCP(func) func(DHCP, dhcp, na) +#else +#define DISTRO_BOOT_DEV_DHCP(func) +#endif + + +#if defined(CONFIG_SABRELITE) +#define FDTFILE "fdtfile=imx6q-sabrelite.dtb\0" +#else +/* FIXME: nitrogen6x covers multiple configs. Define fdtfile for each supported config. */ +#define FDTFILE +#endif + +#define BOOT_TARGET_DEVICES(func) \ + DISTRO_BOOT_DEV_MMC(func) \ + DISTRO_BOOT_DEV_SATA(func) \ + DISTRO_BOOT_DEV_USB(func) \ + DISTRO_BOOT_DEV_PXE(func) \ + DISTRO_BOOT_DEV_DHCP(func) + +#include +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc1\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_addr_r=0x18000000\0" \ + FDTFILE \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "ramdiskaddr=0x13000000\0" \ + "ip_dyn=yes\0" \ + "usb_pgood_delay=2000\0" \ + BOOTENV + +/* Miscellaneous configurable options */ + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ + +/* + * PCI express + */ +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#endif + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/nokia_rx51.h b/roms/u-boot/include/configs/nokia_rx51.h new file mode 100644 index 000000000..23368de62 --- /dev/null +++ b/roms/u-boot/include/configs/nokia_rx51.h @@ -0,0 +1,249 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011-2012 + * Pali Rohár + * + * (C) Copyright 2010 + * Alistair Buxton + * + * Derived from Beagle Board code: + * (C) Copyright 2006-2008 + * Texas Instruments. + * Richard Woodruff + * Syed Mohammed Khasim + * + * Configuration settings for the Nokia RX-51 aka N900. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */ + +#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51 + +#include /* get chip and board defs */ +#include +#include +#include + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_SKIP_LOWLEVEL_INIT /* X-Loader set everything up */ + +#define CONFIG_CMDLINE_TAG /* enable passing kernel command line string */ +#define CONFIG_INITRD_TAG /* enable passing initrd */ +#define CONFIG_REVISION_TAG /* enable passing revision tag*/ +#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ + +/* + * Size of malloc() pool + */ +#define CONFIG_UBI_SIZE (512 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_UBI_SIZE + \ + (128 << 10)) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 + +#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } + +/* USB device configuration */ +#define CONFIG_USB_DEVICE +#define CONFIG_USB_TTY +#define CONFIG_USBD_VENDORID 0x0421 +#define CONFIG_USBD_PRODUCTID_CDCACM 0x01c8 +#define CONFIG_USBD_PRODUCTID_GSERIAL 0x01c8 +#define CONFIG_USBD_MANUFACTURER "Nokia" +#define CONFIG_USBD_PRODUCT_NAME "N900 (U-Boot)" + +#define GPIO_SLIDE 71 + +/* + * Board ONENAND Info. + */ + +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +/* Watchdog support */ +#define CONFIG_HW_WATCHDOG + +/* + * Framebuffer + */ +/* Video console */ +#define CONFIG_VIDEO_LOGO +#define VIDEO_FB_16BPP_PIXEL_SWAP +#define VIDEO_FB_16BPP_WORD_SWAP + +/* functions for cfb_console */ +#define VIDEO_KBD_INIT_FCT rx51_kp_init() +#define VIDEO_TSTC_FCT rx51_kp_tstc +#define VIDEO_GETC_FCT rx51_kp_getc +#ifndef __ASSEMBLY__ +struct stdio_dev; +int rx51_kp_init(void); +int rx51_kp_tstc(struct stdio_dev *sdev); +int rx51_kp_getc(struct stdio_dev *sdev); +#endif + +/* Environment information */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "usbtty=cdc_acm\0" \ + "stdin=usbtty,serial,vga\0" \ + "stdout=usbtty,serial,vga\0" \ + "stderr=usbtty,serial,vga\0" \ + "slide=gpio input " __stringify(GPIO_SLIDE) "\0" \ + "switchmmc=mmc dev ${mmcnum}\0" \ + "kernaddr=0x82008000\0" \ + "initrdaddr=0x84008000\0" \ + "scriptaddr=0x86008000\0" \ + "fileload=${mmctype}load mmc ${mmcnum}:${mmcpart} " \ + "${loadaddr} ${mmcfile}\0" \ + "kernload=setenv loadaddr ${kernaddr};" \ + "setenv mmcfile ${mmckernfile};" \ + "run fileload\0" \ + "initrdload=setenv loadaddr ${initrdaddr};" \ + "setenv mmcfile ${mmcinitrdfile};" \ + "run fileload\0" \ + "scriptload=setenv loadaddr ${scriptaddr};" \ + "setenv mmcfile ${mmcscriptfile};" \ + "run fileload\0" \ + "scriptboot=echo Running ${mmcscriptfile} from mmc " \ + "${mmcnum}:${mmcpart} ...; source ${scriptaddr}\0" \ + "kernboot=echo Booting ${mmckernfile} from mmc " \ + "${mmcnum}:${mmcpart} ...; bootm ${kernaddr}\0" \ + "kerninitrdboot=echo Booting ${mmckernfile} ${mmcinitrdfile} from mmc "\ + "${mmcnum}:${mmcpart} ...; bootm ${kernaddr} ${initrdaddr}\0" \ + "attachboot=echo Booting attached kernel image ...;" \ + "setenv setup_omap_atag 1;" \ + "bootm ${attkernaddr};" \ + "setenv setup_omap_atag\0" \ + "trymmcscriptboot=if run switchmmc; then " \ + "if run scriptload; then " \ + "run scriptboot;" \ + "fi;" \ + "fi\0" \ + "trymmckernboot=if run switchmmc; then " \ + "if run kernload; then " \ + "run kernboot;" \ + "fi;" \ + "fi\0" \ + "trymmckerninitrdboot=if run switchmmc; then " \ + "if run initrdload; then " \ + "if run kernload; then " \ + "run kerninitrdboot;" \ + "fi;" \ + "fi; " \ + "fi\0" \ + "trymmcpartboot=setenv mmcscriptfile boot.scr; run trymmcscriptboot;" \ + "setenv mmckernfile uImage; run trymmckernboot\0" \ + "trymmcallpartboot=setenv mmcpart 1; run trymmcpartboot;" \ + "setenv mmcpart 2; run trymmcpartboot;" \ + "setenv mmcpart 3; run trymmcpartboot;" \ + "setenv mmcpart 4; run trymmcpartboot\0" \ + "trymmcboot=if run switchmmc; then " \ + "setenv mmctype fat;" \ + "run trymmcallpartboot;" \ + "setenv mmctype ext4;" \ + "run trymmcallpartboot;" \ + "fi\0" \ + "emmcboot=setenv mmcnum 1; run trymmcboot\0" \ + "sdboot=setenv mmcnum 0; run trymmcboot\0" \ + "preboot=setenv mmcnum 1; setenv mmcpart 1;" \ + "setenv mmcscriptfile bootmenu.scr;" \ + "if run switchmmc; then " \ + "setenv mmctype fat;" \ + "if run scriptload; then run scriptboot; else " \ + "setenv mmctype ext4;" \ + "if run scriptload; then run scriptboot; fi;" \ + "fi;" \ + "fi;" \ + "if run slide; then true; else " \ + "setenv bootmenu_delay 0;" \ + "setenv bootdelay 0;" \ + "fi\0" \ + "menucmd=bootmenu\0" \ + "bootmenu_0=Attached kernel=run attachboot\0" \ + "bootmenu_1=Internal eMMC=run emmcboot\0" \ + "bootmenu_2=External SD card=run sdboot\0" \ + "bootmenu_3=U-Boot boot order=boot\0" \ + "bootmenu_delay=30\0" \ + "" + +#define CONFIG_POSTBOOTMENU \ + "echo;" \ + "echo Extra commands:;" \ + "echo run sdboot - Boot from SD card slot.;" \ + "echo run emmcboot - Boot internal eMMC memory.;" \ + "echo run attachboot - Boot attached kernel image.;" \ + "echo" + +#define CONFIG_BOOTCOMMAND \ + "run sdboot;" \ + "run emmcboot;" \ + "run attachboot;" \ + "echo" + +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +/* + * Physical Memory Map + */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 + +/* + * FLASH and environment organization + */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * Attached kernel image + */ + +#define SDRAM_SIZE 0x10000000 /* 256 MB */ +#define SDRAM_END (CONFIG_SYS_SDRAM_BASE + SDRAM_SIZE) + +#define IMAGE_MAXSIZE 0x1FF800 /* 2 MB - 2 kB */ +#define KERNEL_OFFSET 0x40000 /* 256 kB */ +#define KERNEL_MAXSIZE (IMAGE_MAXSIZE-KERNEL_OFFSET) +#define KERNEL_ADDRESS (SDRAM_END-KERNEL_MAXSIZE) + +/* Reserve protected RAM for attached kernel */ +#define CONFIG_PRAM ((KERNEL_MAXSIZE >> 10)+1) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/novena.h b/roms/u-boot/include/configs/novena.h new file mode 100644 index 000000000..2b0a7631c --- /dev/null +++ b/roms/u-boot/include/configs/novena.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the Novena U-Boot. + * + * Copyright (C) 2014 Marek Vasut + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* System configurations */ +#define CONFIG_KEYBOARD + +#include "mx6_common.h" + +/* U-Boot Commands */ + +/* U-Boot general configurations */ + +/* U-Boot environment */ +/* + * Environment is on MMC, starting at offset 512KiB from start of the card. + * Please place first partition at offset 1MiB from the start of the card + * as recommended by GNU/fdisk. See below for details: + * http://homepage.ntlworld.com./jonathan.deboynepollard/FGA/disc-partition-alignment.html + */ + +/* Booting Linux */ +#define CONFIG_BOOTFILE "fitImage" +#define CONFIG_HOSTNAME "novena" + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) + +/* SPL */ +#include "imx6_spl.h" /* common IMX6 SPL configuration */ + +/* Ethernet Configuration */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_ETH +#endif + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_SPD_BUS_NUM 0 + +/* I2C EEPROM */ +#ifdef CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_BUS 2 +#endif + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* PCI express */ +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29) +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12) +#endif + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +/* SATA Configs */ +#define CONFIG_LBA48 + +/* UART */ +#define CONFIG_MXC_UART_BASE UART2_BASE + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +/* Gadget part */ +#define CONFIG_USBD_HS +#endif + +/* Video output */ +#define CONFIG_VIDEO_LOGO +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +/* Extra U-Boot environment. */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "consdev=ttymxc1\0" \ + "baudrate=115200\0" \ + "bootdev=/dev/mmcblk0p1\0" \ + "rootdev=/dev/mmcblk0p2\0" \ + "netdev=eth0\0" \ + "kernel_addr_r="__stringify(CONFIG_LOADADDR)"\0" \ + "pxefile_addr_r="__stringify(CONFIG_LOADADDR)"\0" \ + "scriptaddr="__stringify(CONFIG_LOADADDR)"\0" \ + "ramdisk_addr_r=0x28000000\0" \ + "fdt_addr_r=0x18000000\0" \ + "fdtfile=imx6q-novena.dtb\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ + "addcons=" \ + "setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off\0" \ + "addmisc=" \ + "setenv bootargs ${bootargs} ${miscargs}\0" \ + "addargs=run addcons addmisc\0" \ + "mmcload=" \ + "mmc rescan ; " \ + "ext4load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \ + "netload=" \ + "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ + "miscargs=nohlt panic=1\0" \ + "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ + "nfsargs=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ + "mmc_mmc=" \ + "run mmcload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "mmc_nfs=" \ + "run mmcload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_mmc=" \ + "run netload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_nfs=" \ + "run netload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "update_sd_spl_filename=SPL\0" \ + "update_sd_uboot_filename=u-boot.img\0" \ + "update_sd_firmware=" /* Update the SD firmware partition */ \ + "if mmc rescan ; then " \ + "if dhcp ${update_sd_spl_filename} ; then " \ + "mmc write ${loadaddr} 2 0x200 ; " \ + "fi ; " \ + "if dhcp ${update_sd_uboot_filename} ; then " \ + "fatwrite mmc 0:1 ${loadaddr} u-boot.img ${filesize} ; "\ + "fi ; " \ + "fi\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(SATA, sata, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#else +#define CONFIG_EXTRA_ENV_SETTINGS +#endif /* CONFIG_SPL_BUILD */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/npi_imx6ull.h b/roms/u-boot/include/configs/npi_imx6ull.h new file mode 100644 index 000000000..3be9b8ff5 --- /dev/null +++ b/roms/u-boot/include/configs/npi_imx6ull.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (c) 2021 Linumiz + * Author: Navin Sankar Velliangiri + */ + +#ifndef _NPI_IMX6ULL_H +#define _NPI_IMX6ULL_H + +#include +#include "mx6_common.h" + +/* SPL options */ +#include "imx6_spl.h" + +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +/* Size of malloc() poll */ +#define CONFIG_SYS_MALLOC_LEN SZ_2M + +/* Console configs */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* environment settings */ +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +/* NAND */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#ifdef CONFIG_CMD_NET +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth0" +#endif + +#define CONFIG_IMX_THERMAL + +#define CONFIG_FEC_ENET_DEV 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200n8\0" \ + "image=zImage\0" \ + "fdtfile=imx6ull-seeed-npi-dev-board.dtb\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "fdt_addr_r=0x82000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ + "ramdisk_addr_r=0x82100000\0" \ + "scriptaddr=0x87000000\0" \ + "root=/dev/mmcblk0p2 rootwait\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(UBIFS, ubifs, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#endif /* _NPI_IMX6ULL_H */ diff --git a/roms/u-boot/include/configs/nsa310s.h b/roms/u-boot/include/configs/nsa310s.h new file mode 100644 index 000000000..e38c65a48 --- /dev/null +++ b/roms/u-boot/include/configs/nsa310s.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 + * Gerald Kerma + * Tony Dinh + * Luka Perkov + */ + +#ifndef _CONFIG_NSA310S_H +#define _CONFIG_NSA310S_H + +/* high level configuration options */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KW88F6192 1 /* SOC Name */ +#define CONFIG_KW88F6702 1 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +#include "mv-common.h" + +/* environment variables configuration */ + +/* default environment variables */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part root; " \ + "ubifsmount ubi:rootfs; " \ + "ubifsload 0x800000 ${kernel}; " \ + "ubifsload 0x700000 ${fdt}; " \ + "ubifsumount; " \ + "fdt addr 0x700000; fdt resize; fdt chosen; " \ + "bootz 0x800000 - 0x700000" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS_DEFAULT \ + "kernel=/boot/zImage\0" \ + "fdt=/boot/nsa310s.dtb\0" \ + "bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0" + +/* Ethernet driver configuration */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 1 +#define CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +/* SATA driver configuration */ +#ifdef CONFIG_IDE +#define __io +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#endif /* CONFIG_IDE */ + +/* RTC driver configuration */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + +#endif /* _CONFIG_NSA310S_H */ diff --git a/roms/u-boot/include/configs/nsim.h b/roms/u-boot/include/configs/nsim.h new file mode 100644 index 000000000..61217bbe7 --- /dev/null +++ b/roms/u-boot/include/configs/nsim.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved. + */ + +#ifndef _CONFIG_NSIM_H_ +#define _CONFIG_NSIM_H_ + +#include + +/* + * Memory configuration + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE SZ_256M + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN SZ_2M +#define CONFIG_SYS_BOOTM_LEN SZ_32M +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +/* + * Environment configuration + */ +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ + +#endif /* _CONFIG_NSIM_H_ */ diff --git a/roms/u-boot/include/configs/nyan-big.h b/roms/u-boot/include/configs/nyan-big.h new file mode 100644 index 000000000..394fb15f3 --- /dev/null +++ b/roms/u-boot/include/configs/nyan-big.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 + * NVIDIA Corporation + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra124-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +/* Environment in eMMC, at the end of 2nd "boot sector" */ + +/* Align LCD to 1MB boundary */ +#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE + +/* SPI */ +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +#undef CONFIG_LOADADDR +#define CONFIG_LOADADDR 0x82408000 + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/o4-imx6ull-nano.h b/roms/u-boot/include/configs/o4-imx6ull-nano.h new file mode 100644 index 000000000..b9746b9b1 --- /dev/null +++ b/roms/u-boot/include/configs/o4-imx6ull-nano.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (C) 2021 Oleh Kravchenko */ + +#ifndef __O4_IMX6ULL_NANO_CONFIG_H +#define __O4_IMX6ULL_NANO_CONFIG_H + +#include "mx6_common.h" + +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#if IS_ENABLED(CONFIG_CMD_USB) +# define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif /* CONFIG_CMD_USB */ + +#if IS_ENABLED(CONFIG_FEC_MXC) +# define CONFIG_FEC_XCV_TYPE RMII +#endif /* CONFIG_FEC_MXC */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcargs=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcpart} console=ttymxc0,${baudrate} panic=30\0" \ + "mmcboot=run mmcargs && ext4load mmc ${mmcdev}:${mmcpart} $loadaddr /boot/zImage && bootz $loadaddr - $fdtcontroladdr\0" \ + "bootcmd=run mmcboot\0" \ + "bootcmd_mfg=fastboot usb 0\0" + +#endif /* __O4_IMX6ULL_NANO_CONFIG_H */ diff --git a/roms/u-boot/include/configs/octeon_common.h b/roms/u-boot/include/configs/octeon_common.h new file mode 100644 index 000000000..109ef4064 --- /dev/null +++ b/roms/u-boot/include/configs/octeon_common.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-2020 + * Marvell + */ + +#ifndef __OCTEON_COMMON_H__ +#define __OCTEON_COMMON_H__ + +#if defined(CONFIG_RAM_OCTEON) +#define CONFIG_SYS_MALLOC_LEN (16 << 20) +#define CONFIG_SYS_INIT_SP_OFFSET 0x20100000 +#else +/* No DDR init -> run in L2 cache with limited resources */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_INIT_SP_OFFSET 0x00180000 +#endif + +#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20)) + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#endif /* __OCTEON_COMMON_H__ */ diff --git a/roms/u-boot/include/configs/octeon_ebb7304.h b/roms/u-boot/include/configs/octeon_ebb7304.h new file mode 100644 index 000000000..04fe4dfe2 --- /dev/null +++ b/roms/u-boot/include/configs/octeon_ebb7304.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-2020 + * Marvell + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +#include "octeon_common.h" + +/* + * CFI flash + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ + +#endif /* __CONFIG_H__ */ diff --git a/roms/u-boot/include/configs/octeon_nic23.h b/roms/u-boot/include/configs/octeon_nic23.h new file mode 100644 index 000000000..0a7b4d8f9 --- /dev/null +++ b/roms/u-boot/include/configs/octeon_nic23.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-2020 + * Marvell + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +/* + * SATA/SCSI/AHCI configuration + */ +/* AHCI support Definitions */ +/** Enable 48-bit SATA addressing */ +#define CONFIG_LBA48 +/** Enable 64-bit addressing */ +#define CONFIG_SYS_64BIT_LBA + +#include "octeon_common.h" + +#endif /* __CONFIG_H__ */ diff --git a/roms/u-boot/include/configs/octeontx2_common.h b/roms/u-boot/include/configs/octeontx2_common.h new file mode 100644 index 000000000..7c585ad9e --- /dev/null +++ b/roms/u-boot/include/configs/octeontx2_common.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#ifndef __OCTEONTX2_COMMON_H__ +#define __OCTEONTX2_COMMON_H__ + +#define CONFIG_SUPPORT_RAW_INITRD + +/** Maximum size of image supported for bootm (and bootable FIT images) */ +#define CONFIG_SYS_BOOTM_LEN (256 << 20) + +/** Memory base address */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_TEXT_BASE + +/** Stack starting address */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0) + +/** Heap size for U-Boot */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64 * 1024 * 1024) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + +#define CONFIG_LAST_STAGE_INIT + +/* Allow environment variable to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +/** Reduce hashes printed out */ +#define CONFIG_TFTP_TSIZE + +/* Autoboot options */ +#define CONFIG_RESET_TO_RETRY +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_BOOT_RETRY_MIN 30 + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/** Extra environment settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=20080000\0" \ + "ethrotate=yes\0" \ + "autoload=0\0" + +/** Environment defines */ +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /** Console I/O Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MAXARGS 64 /** max command args */ + +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192 + +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT env_get("prompt") + +#if defined(CONFIG_MMC_OCTEONTX) +#define MMC_SUPPORTS_TUNING +/** EMMC specific defines */ +#define CONFIG_SUPPORT_EMMC_BOOT +#define CONFIG_SUPPORT_EMMC_RPMB +#endif + +#endif /* __OCTEONTX2_COMMON_H__ */ diff --git a/roms/u-boot/include/configs/octeontx_common.h b/roms/u-boot/include/configs/octeontx_common.h new file mode 100644 index 000000000..434e54442 --- /dev/null +++ b/roms/u-boot/include/configs/octeontx_common.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#ifndef __OCTEONTX_COMMON_H__ +#define __OCTEONTX_COMMON_H__ + +#ifdef CONFIG_DISTRO_DEFAULTS +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) \ + func(SCSI, scsi, 0) + +#include +/* Extra environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=0\0" \ + "loadaddr=0x20080000\0" \ + "kernel_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x03000000\0" \ + "scriptaddr=0x04000000\0" \ + BOOTENV + +#else + +/** Extra environment settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=20080000\0" \ + "autoload=0\0" + +#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ + +/** Maximum size of image supported for bootm (and bootable FIT images) */ +#define CONFIG_SYS_BOOTM_LEN (256 << 20) + +/** Memory base address */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_TEXT_BASE + +/** Stack starting address */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0) + +/** Heap size for U-Boot */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64 * 1024 * 1024) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + +/* Allow environment variable to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +/** Reduce hashes printed out */ +#define CONFIG_TFTP_TSIZE + +/* Autoboot options */ +#define CONFIG_RESET_TO_RETRY +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_BOOT_RETRY_MIN 30 + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* AHCI support Definitions */ +#ifdef CONFIG_DM_SCSI +/** Enable 48-bit SATA addressing */ +# define CONFIG_LBA48 +/** Enable 64-bit addressing */ +# define CONFIG_SYS_64BIT_LBA +#endif + +/***** SPI Defines *********/ +#ifdef CONFIG_DM_SPI_FLASH +# define CONFIG_SF_DEFAULT_BUS 0 +# define CONFIG_SF_DEFAULT_CS 0 +#endif + +/** Environment defines */ +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /** Console I/O Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MAXARGS 64 /** max command args */ + +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192 + +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT env_get("prompt") + +/** EMMC specific defines */ +#if defined(CONFIG_MMC_OCTEONTX) +#define CONFIG_SUPPORT_EMMC_BOOT +#define CONFIG_SUPPORT_EMMC_RPMB +#endif + +#if defined(CONFIG_NAND_OCTEONTX) +/*#define CONFIG_MTD_CONCAT */ +#define CONFIG_SYS_MAX_NAND_DEVICE 8 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif + +#endif /* __OCTEONTX_COMMON_H__ */ diff --git a/roms/u-boot/include/configs/odroid.h b/roms/u-boot/include/configs/odroid.h new file mode 100644 index 000000000..1367d1389 --- /dev/null +++ b/roms/u-boot/include/configs/odroid.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Samsung Electronics + * Sanghee Kim + * Piotr Wilczek + * Przemyslaw Marczak + * + * Configuation settings for the Odroid-U3 (EXYNOS4412) board. + */ + +#ifndef __CONFIG_ODROID_U3_H +#define __CONFIG_ODROID_U3_H + +#include + +#define CONFIG_SYS_L2CACHE_OFF +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x10502000 +#endif + +#define CONFIG_MACH_TYPE 4289 + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +/* Reserve the last 1 MiB for the secure firmware */ +#define CONFIG_SYS_MEM_TOP_HIDE (1UL << 20UL) +#define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE + +/* memtest works on */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + +#include + +#define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run autoboot" + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ + - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +/* Partitions name */ +#define PARTS_BOOT "boot" +#define PARTS_ROOT "platform" + +#define CONFIG_DFU_ALT \ + "uImage fat 0 1;" \ + "zImage fat 0 1;" \ + "Image.itb fat 0 1;" \ + "uInitrd fat 0 1;" \ + "exynos4412-odroidu3.dtb fat 0 1;" \ + "exynos4412-odroidx2.dtb fat 0 1;" \ + ""PARTS_BOOT" part 0 1;" \ + ""PARTS_ROOT" part 0 2\0" \ + +#define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) + +#define CONFIG_DFU_ALT_BOOT_EMMC \ + "u-boot raw 0x3e 0x800 mmcpart 1;" \ + "bl1 raw 0x0 0x1e mmcpart 1;" \ + "bl2 raw 0x1e 0x1d mmcpart 1;" \ + "tzsw raw 0x83e 0x138 mmcpart 1\0" + +#define CONFIG_DFU_ALT_BOOT_SD \ + "u-boot raw 0x3f 0x800;" \ + "bl1 raw 0x1 0x1e;" \ + "bl2 raw 0x1f 0x1d;" \ + "tzsw raw 0x83f 0x138\0" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 2) \ + func(MMC, mmc, 0) + +#include + +/* + * Bootable media layout: + * dev: SD eMMC(part boot) + * BL1 1 0 + * BL2 31 30 + * UBOOT 63 62 + * TZSW 2111 2110 + * ENV 2560 2560(part user) + * + * MBR Primary partiions: + * Num Name Size Offset + * 1. BOOT: 100MiB 2MiB + * 2. ROOT: - +*/ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadbootscript=load mmc ${mmcbootdev}:${mmcbootpart} ${scriptaddr} " \ + "boot.scr\0" \ + "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kernel_addr_r} " \ + "${kernelname}\0" \ + "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${ramdisk_addr_r} " \ + "${initrdname}\0" \ + "loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdt_addr_r} " \ + "${fdtfile}\0" \ + "check_ramdisk=" \ + "if run loadinitrd; then " \ + "setenv initrd_addr ${ramdisk_addr_r};" \ + "else " \ + "setenv initrd_addr -;" \ + "fi;\0" \ + "check_dtb=" \ + "if run loaddtb; then " \ + "setenv fdt_addr ${fdt_addr_r};" \ + "else " \ + "setenv fdt_addr;" \ + "fi;\0" \ + "kernel_args=" \ + "setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \ + " rootwait ${console} ${opts}\0" \ + "boot_script=" \ + "run loadbootscript;" \ + "source ${scriptaddr}\0" \ + "boot_fit=" \ + "setenv kernelname Image.itb;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootm ${kernel_addr_r}#${board_name}\0" \ + "boot_uimg=" \ + "setenv kernelname uImage;" \ + "run check_dtb;" \ + "run check_ramdisk;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootm ${kernel_addr_r} ${initrd_addr} ${fdt_addr};\0" \ + "boot_zimg=" \ + "setenv kernelname zImage;" \ + "run check_dtb;" \ + "run check_ramdisk;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootz ${kernel_addr_r} ${initrd_addr} ${fdt_addr};\0" \ + "autoboot=" \ + "if test -e mmc ${mmcbootdev} boot.scr; then; " \ + "run boot_script; " \ + "elif test -e mmc ${mmcbootdev} Image.itb; then; " \ + "run boot_fit;" \ + "elif test -e mmc ${mmcbootdev} zImage; then; " \ + "run boot_zimg;" \ + "elif test -e mmc ${mmcbootdev} uImage; then; " \ + "run boot_uimg;" \ + "fi;\0" \ + "console=console=ttySAC1,115200n8\0" \ + "mmcbootdev=0\0" \ + "mmcbootpart=1\0" \ + "mmcrootdev=0\0" \ + "mmcrootpart=2\0" \ + "dfu_alt_system="CONFIG_DFU_ALT \ + "dfu_alt_info=Please reset the board\0" \ + "consoleon=set console console=ttySAC1,115200n8; save; reset\0" \ + "consoleoff=set console console=ram; save; reset\0" \ + "initrdname=uInitrd\0" \ + "ramdisk_addr_r=0x42000000\0" \ + "scriptaddr=0x42000000\0" \ + "fdt_addr_r=0x40800000\0" \ + "kernel_addr_r=0x41000000\0" \ + BOOTENV + +/* GPT */ + +/* Security subsystem - enable hw_rand() */ +#define CONFIG_EXYNOS_ACE_SHA + +/* USB */ +#define CONFIG_USB_EHCI_EXYNOS + +/* + * Supported Odroid boards: X3, U3 + * TODO: Add Odroid X support + */ +#define CONFIG_MISC_COMMON + +#undef CONFIG_REVISION_TAG + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/odroid_go2.h b/roms/u-boot/include/configs/odroid_go2.h new file mode 100644 index 000000000..53781ba7a --- /dev/null +++ b/roms/u-boot/include/configs/odroid_go2.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +#ifndef __EVB_PX30_H +#define __EVB_PX30_H + +#include + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif diff --git a/roms/u-boot/include/configs/odroid_xu3.h b/roms/u-boot/include/configs/odroid_xu3.h new file mode 100644 index 000000000..0c8619615 --- /dev/null +++ b/roms/u-boot/include/configs/odroid_xu3.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Samsung Electronics + * Hyungwon Hwang + */ + +#ifndef __CONFIG_ODROID_XU3_H +#define __CONFIG_ODROID_XU3_H + +#include +#include + +#define CONFIG_BOARD_COMMON + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +#define TZPC_BASE_OFFSET 0x10000 + +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ +/* Reserve the last 22 MiB for the secure firmware */ +#define CONFIG_SYS_MEM_TOP_HIDE (22UL << 20UL) +#define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) + +/* USB */ +#define CONFIG_USB_EHCI_EXYNOS + +/* DFU */ +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M +#define DFU_DEFAULT_POLL_TIMEOUT 300 +#define DFU_MANIFEST_POLL_TIMEOUT 25000 + +/* THOR */ +#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_USB_GADGET_VENDOR_NUM +#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D + +/* UMS */ +#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 + +/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ +#undef CONFIG_EXYNOS_TMU + +#define CONFIG_DFU_ALT_SYSTEM \ + "uImage fat 0 1;" \ + "zImage fat 0 1;" \ + "Image.itb fat 0 1;" \ + "uInitrd fat 0 1;" \ + "boot.scr fat 0 1;" \ + "boot.cmd fat 0 1;" \ + "exynos5422-odroidxu3.dtb fat 0 1;" \ + "exynos5422-odroidxu3-lite.dtb fat 0 1;" \ + "exynos5422-odroidxu4.dtb fat 0 1;" \ + "exynos5422-odroidhc1.dtb fat 0 1;" \ + "boot part 0 1;" \ + "root part 0 2\0" + +#define CONFIG_DFU_ALT_BOOT_EMMC \ + "u-boot raw 0x3e 0x800 mmcpart 1;" \ + "bl1 raw 0x0 0x1e mmcpart 1;" \ + "bl2 raw 0x1e 0x1d mmcpart 1;" \ + "tzsw raw 0x83e 0x200 mmcpart 1;" \ + "params.bin raw 0x1880 0x20\0" + +#define CONFIG_DFU_ALT_BOOT_SD \ + "u-boot raw 0x3f 0x800;" \ + "bl1 raw 0x1 0x1e;" \ + "bl2 raw 0x1f 0x1d;" \ + "tzsw raw 0x83f 0x200;" \ + "params.bin raw 0x1880 0x20\0" + +/* Enable: board/samsung/common/misc.c to use set_dfu_alt_info() */ +#define CONFIG_MISC_COMMON +#define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) + +/* Set soc_rev, soc_id, board_rev, board_name, fdtfile */ +#define CONFIG_ODROID_REV_AIN 9 +#define CONFIG_REVISION_TAG + +/* + * Need to override existing one (smdk5420) with odroid so set_board_info will + * use proper prefix when creating full board_name (SYS_BOARD + type) + */ +#undef CONFIG_SYS_BOARD +#define CONFIG_SYS_BOARD "odroid" + +/* Define new extra env settings, including DFU settings */ +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS \ + EXYNOS_FDTFILE_SETTING \ + MEM_LAYOUT_ENV_SETTINGS \ + BOOTENV \ + "rootfstype=ext4\0" \ + "console=console=ttySAC2,115200n8\0" \ + "fdtfile=exynos5422-odroidxu3.dtb\0" \ + "board_name=odroidxu3\0" \ + "mmcbootdev=0\0" \ + "mmcrootdev=0\0" \ + "mmcbootpart=1\0" \ + "mmcrootpart=2\0" \ + "dfu_alt_system="CONFIG_DFU_ALT_SYSTEM \ + "dfu_alt_info=Autoset by THOR/DFU command run.\0" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/omap3_beagle.h b/roms/u-boot/include/configs/omap3_beagle.h new file mode 100644 index 000000000..6563335f9 --- /dev/null +++ b/roms/u-boot/include/configs/omap3_beagle.h @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments. + * Richard Woodruff + * Syed Mohammed Khasim + * + * Configuration settings for the TI OMAP3530 Beagle board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * We are only ever GP parts and will utilize all of the "downloaded image" + * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). + */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* NAND */ +#if defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K +/* NAND: SPL falcon mode configs */ +#if defined(CONFIG_SPL_OS_BOOT) +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000 +#endif /* CONFIG_SPL_OS_BOOT */ +#endif /* CONFIG_MTD_RAW_NAND */ + +/* USB EHCI */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 + +/* Enable Multi Bus support for I2C */ +#define CONFIG_I2C_MULTI_BUS + +/* DSS Support */ + +/* TWL4030 LED Support */ + +#define MEM_LAYOUT_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV + +#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv mmcdev " #instance "; " \ + "run mmcboot\0" +#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#if defined(CONFIG_MTD_RAW_NAND) + +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "if test ${mtdids} = '' || test ${mtdparts} = '' ; then " \ + "echo NAND boot disabled: No mtdids and/or mtdparts; " \ + "else " \ + "run nandboot; " \ + "fi\0" +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(LEGACY_MMC, legacy_mmc, 0) \ + func(UBIFS, ubifs, 0) \ + func(NAND, nand, 0) + +#else /* !CONFIG_MTD_RAW_NAND */ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(LEGACY_MMC, legacy_mmc, 0) + +#endif /* CONFIG_MTD_RAW_NAND */ + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttyO2,115200n8\0" \ + "bootdir=/boot\0" \ + "bootenv=uEnv.txt\0" \ + "bootfile=zImage\0" \ + "bootpart=0:2\0" \ + "bootubivol=rootfs\0" \ + "bootubipart=rootfs\0" \ + "usbtty=cdc_acm\0" \ + "mpurate=auto\0" \ + "buddy=none\0" \ + "camera=none\0" \ + "vram=12M\0" \ + "dvimode=640x480MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "defaultargs=setenv defargs " \ + "mpurate=${mpurate} " \ + "buddy=${buddy} "\ + "camera=${camera} "\ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapdss.def_disp=${defaultdisplay}\0" \ + "optargs=\0" \ + "findfdt=" \ + "if test $beaglerev = AxBx; then " \ + "setenv fdtfile omap3-beagle.dtb; fi; " \ + "if test $beaglerev = Cx; then " \ + "setenv fdtfile omap3-beagle.dtb; fi; " \ + "if test $beaglerev = C4; then " \ + "setenv fdtfile omap3-beagle.dtb; fi; " \ + "if test $beaglerev = xMAB; then " \ + "setenv fdtfile omap3-beagle-xm-ab.dtb; fi; " \ + "if test $beaglerev = xMC; then " \ + "setenv fdtfile omap3-beagle-xm.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree to use; fi\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "mmcargs=run defaultargs; setenv bootargs console=${console} " \ + "${mtdparts} " \ + "${defargs} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "userbutton_xm=gpio input 4;\0" \ + "userbutton_nonxm=gpio input 7;\0" \ + "userbutton=if gpio input 173; then " \ + "run userbutton_xm; " \ + "else " \ + "run userbutton_nonxm; " \ + "fi;\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "ext4bootenv=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "mmcbootenv=setenv bootpart ${mmcdev}:${mmcpart}; " \ + "mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "if run userbutton; then " \ + "setenv bootenv uEnv.txt;" \ + "else " \ + "setenv bootenv user.txt;" \ + "fi;" \ + "run loadbootenv && run importbootenv; " \ + "run ext4bootenv && run importbootenv; " \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi; " \ + "fi\0" \ + "validatefdt=" \ + "if test $beaglerev = xMAB; then " \ + "if test ! -e mmc ${bootpart} ${bootdir}/${fdtfile}; then " \ + "setenv fdtfile omap3-beagle-xm.dtb; " \ + "fi; " \ + "fi; \0" \ + "loadimage=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loaddtb=run validatefdt; ext4load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcboot=run mmcbootenv; " \ + "if run loadimage && run loaddtb; then " \ + "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} ...; " \ + "run mmcargs; " \ + "if test ${bootfile} = uImage; then " \ + "bootm ${loadaddr} - ${fdtaddr}; " \ + "fi; " \ + "if test ${bootfile} = zImage; then " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "fi; " \ + "fi\0" \ + "nandroot=ubi0:rootfs ubi.mtd=rootfs rw\0" \ + "nandrootfstype=ubifs rootwait\0" \ + "nandargs=run defaultargs; setenv bootargs console=${console} " \ + "${mtdparts} " \ + "${defargs} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandboot=if nand read ${loadaddr} kernel && nand read ${fdtaddr} dtb; then " \ + "echo Booting uImage from NAND MTD 'kernel' partition ...; " \ + "run nandargs; " \ + "bootm ${loadaddr} - ${fdtaddr}; " \ + "fi\0" \ + "loadramdisk=ext4load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \ + "ramdisk=rootfs.ext2.gz.uboot\0" \ + "ramdisk_size=16384\0" \ + "ramroot=/dev/ram rw\0" \ + "ramrootfstype=ext2\0" \ + "ramargs=run defaultargs; setenv bootargs console=${console} " \ + "${mtdparts} " \ + "${defargs} " \ + "${optargs} " \ + "root=${ramroot} ramdisk_size=${ramdisk_size} " \ + "rootfstype=${ramrootfstype}\0" \ + "ramboot=run mmcbootenv; " \ + "if run loadimage && run loaddtb && run loadramdisk; then " \ + "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} w/ramdisk ...; " \ + "run ramargs; " \ + "bootz ${loadaddr} ${rdaddr} ${fdtaddr}; " \ + "fi\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/omap3_evm.h b/roms/u-boot/include/configs/omap3_evm.h new file mode 100644 index 000000000..e2e871a9c --- /dev/null +++ b/roms/u-boot/include/configs/omap3_evm.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the TI OMAP3 EVM board. + * + * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * Author : + * Manikandan Pillai + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff + * Syed Mohammed Khasim + * + * Manikandan Pillai + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * We are only ever GP parts and will utilize all of the "downloaded image" + * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). + */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* NAND */ +#if defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW +#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K +/* NAND: SPL falcon mode configs */ +#if defined(CONFIG_SPL_OS_BOOT) +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000 +#endif /* CONFIG_SPL_OS_BOOT */ +#endif /* CONFIG_MTD_RAW_NAND */ + +#define MEM_LAYOUT_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV + +#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv mmcdev " #instance "; " \ + "run mmcboot\0" +#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#if defined(CONFIG_MTD_RAW_NAND) + +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "if test ${mtdids} = '' || test ${mtdparts} = '' ; then " \ + "echo NAND boot disabled: No mtdids and/or mtdparts; " \ + "else " \ + "run nandboot; " \ + "fi\0" +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(LEGACY_MMC, legacy_mmc, 0) \ + func(UBIFS, ubifs, 0) \ + func(NAND, nand, 0) + +#else /* !CONFIG_MTD_RAW_NAND */ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(LEGACY_MMC, legacy_mmc, 0) + +#endif /* CONFIG_MTD_RAW_NAND */ + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttyO0,115200n8\0" \ + "bootdir=/boot\0" \ + "bootenv=uEnv.txt\0" \ + "bootfile=zImage\0" \ + "bootpart=0:2\0" \ + "bootubivol=rootfs\0" \ + "bootubipart=rootfs\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${mtdparts} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "ext4bootenv=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "mmcbootenv=setenv bootpart ${mmcdev}:${mmcpart}; " \ + "mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "run loadbootenv && run importbootenv; " \ + "run ext4bootenv && run importbootenv; " \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi; " \ + "fi\0" \ + "loadimage=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loaddtb=ext4load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcboot=run mmcbootenv; " \ + "if run loadimage && run loaddtb; then " \ + "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} ...; " \ + "run mmcargs; " \ + "if test ${bootfile} = uImage; then " \ + "bootm ${loadaddr} - ${fdtaddr}; " \ + "fi; " \ + "if test ${bootfile} = zImage; then " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "fi; " \ + "fi\0" \ + "nandroot=ubi0:rootfs ubi.mtd=rootfs rw noinitrd\0" \ + "nandrootfstype=ubifs rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${mtdparts} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandboot=if nand read ${loadaddr} kernel && nand read ${fdtaddr} dtb; then " \ + "echo Booting uImage from NAND MTD 'kernel' partition ...; " \ + "run nandargs; " \ + "bootm ${loadaddr} - ${fdtaddr}; " \ + "fi\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/omap3_igep00x0.h b/roms/u-boot/include/configs/omap3_igep00x0.h new file mode 100644 index 000000000..8dc30be8b --- /dev/null +++ b/roms/u-boot/include/configs/omap3_igep00x0.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Common configuration settings for IGEP technology based boards + * + * (C) Copyright 2012 + * ISEE 2007 SL, + */ + +#ifndef __IGEP00X0_H +#define __IGEP00X0_H + +#include + +/* + * We are only ever GP parts and will utilize all of the "downloaded image" + * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). + */ + +#define CONFIG_REVISION_TAG 1 + +/* TPS65950 */ +#define PBIASLITEVMODE1 (1 << 8) + +/* LED */ +#define IGEP0020_GPIO_LED 27 +#define IGEP0030_GPIO_LED 16 + +/* Board and revision detection GPIOs */ +#define IGEP0030_USB_TRANSCEIVER_RESET 54 +#define GPIO_IGEP00X0_BOARD_DETECTION 28 +#define GPIO_IGEP00X0_REVISION_DETECTION 129 + +#ifndef CONFIG_SPL_BUILD + +/* Environment */ +#define ENV_DEVICE_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define MEM_LAYOUT_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "scriptaddr=0x87E00000\0" \ + "pxefile_addr_r=0x87F00000\0" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#include + +#define ENV_FINDFDT \ + "findfdt="\ + "if test ${board_name} = igep0020; then " \ + "if test ${board_rev} = F; then " \ + "setenv fdtfile omap3-igep0020-rev-f.dtb; " \ + "else " \ + "setenv fdtfile omap3-igep0020.dtb; fi; fi; " \ + "if test ${board_name} = igep0030; then " \ + "if test ${board_rev} = G; then " \ + "setenv fdtfile omap3-igep0030-rev-g.dtb; " \ + "else " \ + "setenv fdtfile omap3-igep0030.dtb; fi; fi; " \ + "if test ${fdtfile} = ''; then " \ + "echo WARNING: Could not determine device tree to use; fi; \0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_FINDFDT \ + ENV_DEVICE_SETTINGS \ + MEM_LAYOUT_SETTINGS \ + BOOTENV + +#endif + +/* OneNAND config */ +#define CONFIG_USE_ONENAND_BOARD_INIT +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP +#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) + +/* NAND config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW + +#endif /* __IGEP00X0_H */ diff --git a/roms/u-boot/include/configs/omap3_logic.h b/roms/u-boot/include/configs/omap3_logic.h new file mode 100644 index 000000000..dd0ea2dbd --- /dev/null +++ b/roms/u-boot/include/configs/omap3_logic.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 Logic Product Development + * Peter Barada + * + * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo + * reference boards. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ + +#include + +/* + * We are only ever GP parts and will utilize all of the "downloaded image" + * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB) in + * order to allow for BCH8 to fit in. + */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Hardware drivers */ + +/* I2C */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_USB_EHCI_OMAP +#endif +#ifdef CONFIG_USB_EHCI_OMAP +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 4 +#endif + +/* Board NAND Info. */ +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ + 13, 14, 16, 17, 18, 19, 20, 21, 22, \ + 23, 24, 25, 26, 27, 28, 30, 31, 32, \ + 33, 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 44, 45, 46, 47, 48, 49, 50, 51, \ + 52, 53, 54, 55, 56} + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 13 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 +#endif + +/* Environment information */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "mmcdev=0\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=fs noinitrd\0" \ + "nandrootfstype=ubifs rootwait\0" \ + "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "run defaultboot;" \ + "fi; " \ + "else run defaultboot; fi\0" \ + "defaultboot=run mmcramboot\0" \ + "consoledevice=ttyS0\0" \ + "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \ + "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \ + "rotation=0\0" \ + "vrfb_arg=if itest ${rotation} -ne 0; then " \ + "setenv bootargs ${bootargs} omapfb.vrfb=y " \ + "omapfb.rotate=${rotation}; " \ + "fi\0" \ + "optargs=ignore_loglevel early_printk no_console_suspend\0" \ + "common_bootargs=run setconsole; setenv bootargs " \ + "${bootargs} "\ + "console=${console} " \ + "${mtdparts} "\ + "${optargs}; " \ + "run vrfb_arg\0" \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo 'Running bootscript from mmc ...'; " \ + "source ${loadaddr}\0" \ + "loadimage=mmc rescan; " \ + "load mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ + "ramdisksize=64000\0" \ + "ramdiskimage=rootfs.ext2.gz.uboot\0" \ + "loadramdisk=mmc rescan; " \ + "load mmc ${mmcdev} ${rdaddr} ${ramdiskimage}\0" \ + "ramargs=setenv bootargs "\ + "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \ + "mmcargs=setenv bootargs "\ + "root=PARTUUID=${uuid} " \ + "rootfstype=${mmcrootfstype} rw\0" \ + "nandargs=setenv bootargs "\ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nfsargs=setenv serverip ${tftpserver}; " \ + "setenv bootargs root=/dev/nfs " \ + "nfsroot=${nfsrootpath} " \ + "ip=${ipaddr}:${tftpserver}:${gatewayip}:${netmask}::eth0:off\0" \ + "nfsrootpath=/opt/nfs-exports/omap\0" \ + "autoload=no\0" \ + "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "loadfdt=mmc rescan; " \ + "load mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \ + "mmcbootcommon=echo Booting with DT from mmc${mmcdev} ...; " \ + "run finduuid; "\ + "run mmcargs; " \ + "run common_bootargs; " \ + "run dump_bootargs; " \ + "run loadimage; " \ + "run loadfdt;\0 " \ + "mmcbootz=setenv bootfile zImage; " \ + "run mmcbootcommon; "\ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "mmcboot=setenv bootfile uImage; "\ + "run mmcbootcommon; "\ + "bootm ${loadaddr} - ${fdtaddr}\0" \ + "mmcrambootcommon=echo 'Booting kernel from MMC w/ramdisk...'; " \ + "run ramargs; " \ + "run common_bootargs; " \ + "run dump_bootargs; " \ + "run loadimage; " \ + "run loadfdt; " \ + "run loadramdisk\0" \ + "mmcramboot=setenv bootfile uImage; " \ + "run mmcrambootcommon; " \ + "bootm ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ + "mmcrambootz=setenv bootfile zImage; " \ + "run mmcrambootcommon; " \ + "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ + "tftpboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \ + "run ramargs; " \ + "run common_bootargs; " \ + "run dump_bootargs; " \ + "tftpboot ${loadaddr} ${zimage}; " \ + "tftpboot ${rdaddr} ${ramdiskimage}; " \ + "bootm ${loadaddr} ${rdaddr}\0" \ + "tftpbootz=echo 'Booting kernel NFS rootfs...'; " \ + "dhcp;" \ + "run nfsargs;" \ + "run common_bootargs;" \ + "run dump_bootargs;" \ + "tftpboot $loadaddr zImage;" \ + "bootz $loadaddr\0" \ + "nandbootcommon=echo 'Booting kernel from NAND...';" \ + "run nandargs;" \ + "run common_bootargs;" \ + "run dump_bootargs;" \ + "nand read ${loadaddr} kernel;" \ + "nand read ${fdtaddr} spl-os;\0" \ + "nandbootz=run nandbootcommon; "\ + "bootz ${loadaddr} - ${fdtaddr}\0"\ + "nandboot=run nandbootcommon; "\ + "bootm ${loadaddr} - ${fdtaddr}\0"\ + +#define CONFIG_BOOTCOMMAND \ + "run autoboot" + +/* Miscellaneous configurable options */ + +/* memtest works on */ + +/* FLASH and environment organization */ + +/* **** PISMO SUPPORT *** */ +#if defined(CONFIG_CMD_NAND) +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#endif + +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_SIZE 0x4000000 + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ + +/* Defines for SPL */ + +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#endif + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/omap4_panda.h b/roms/u-boot/include/configs/omap4_panda.h new file mode 100644 index 000000000..14eb36381 --- /dev/null +++ b/roms/u-boot/include/configs/omap4_panda.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments Incorporated. + * Steve Sakoman + * + * Configuration settings for the TI OMAP4 Panda board. + * See ti_omap4_common.h for OMAP4 common part + */ + +#ifndef __CONFIG_PANDA_H +#define __CONFIG_PANDA_H + +/* + * High Level Configuration Options + */ + +/* USB UHH support options */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62 + +/* USB Networking options */ + +#define CONFIG_UBOOT_ENABLE_PADS_ALL + +#include + +/* GPIO */ + +/* ENV related config options */ + +#endif /* __CONFIG_PANDA_H */ diff --git a/roms/u-boot/include/configs/omap4_sdp4430.h b/roms/u-boot/include/configs/omap4_sdp4430.h new file mode 100644 index 000000000..462aa4a5b --- /dev/null +++ b/roms/u-boot/include/configs/omap4_sdp4430.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments Incorporated. + * Aneesh V + * Steve Sakoman + * + * Configuration settings for the TI SDP4430 board. + * See ti_omap4_common.h for OMAP4 common part + */ + +#ifndef __CONFIG_SDP4430_H +#define __CONFIG_SDP4430_H + +/* + * High Level Configuration Options + */ +#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_4430SDP + +#include + +/* ENV related config options */ + +#endif /* __CONFIG_SDP4430_H */ diff --git a/roms/u-boot/include/configs/omap5_uevm.h b/roms/u-boot/include/configs/omap5_uevm.h new file mode 100644 index 000000000..a1f1dafad --- /dev/null +++ b/roms/u-boot/include/configs/omap5_uevm.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated. + * Sricharan R + * + * Configuration settings for the TI EVM5430 board. + * See ti_omap5_common.h for omap5 common settings. + */ + +#ifndef __CONFIG_OMAP5_EVM_H +#define __CONFIG_OMAP5_EVM_H + +#include + +#ifndef CONFIG_SPL_BUILD +/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" +#endif + +#define DFUARGS \ + "dfu_bufsiz=0x10000\0" \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_EMMC \ + DFU_ALT_INFO_RAM + +#include + +#define CONFIG_SYS_NS16550_COM3 UART3_BASE + +/* MMC ENV related defines */ + +/* Enhance our eMMC support / experience. */ +#define CONFIG_HSMMC2_8BIT + +/* Required support for the TCA642X GPIO we have on the uEVM */ +#define CONFIG_TCA642X +#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4 +#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 + +/* USB UHH support options */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80 +#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79 + +/* Enabled commands */ + +/* USB Networking options */ + +#define CONSOLEDEV "ttyS2" + +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +#endif /* __CONFIG_OMAP5_EVM_H */ diff --git a/roms/u-boot/include/configs/omapl138_lcdk.h b/roms/u-boot/include/configs/omapl138_lcdk.h new file mode 100644 index 000000000..a37359e6c --- /dev/null +++ b/roms/u-boot/include/configs/omapl138_lcdk.h @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on davinci_dvevm.h. Original Copyrights follow: + * + * Copyright (C) 2007 Sergey Kubushyn + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Board + */ + +/* + * SoC Configuration + */ +#define CONFIG_MACH_OMAPL138_LCDK +#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) +#define CONFIG_SYS_OSCIN_FREQ 24000000 +#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY + +/* + * Memory Info + */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ +#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ +#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ + +#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE +#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 + +/* memtest start addr */ + +/* memtest will be run on 16MB */ + +#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ + DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ + DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ + DAVINCI_SYSCFG_SUSPSRC_UART2 | \ + DAVINCI_SYSCFG_SUSPSRC_EMAC | \ + DAVINCI_SYSCFG_SUSPSRC_I2C) + +/* + * PLL configuration + */ + +/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */ +#define CONFIG_SYS_DA850_PLL0_PLLM 18 +#define CONFIG_SYS_DA850_PLL1_PLLM 21 + +/* + * DDR2 memory configuration + */ +#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ + DV_DDR_PHY_EXT_STRBEN | \ + (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ + (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ + (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ + (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ + (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ + (4 << DV_DDR_SDCR_CL_SHIFT) | \ + (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ + (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) + +/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ +#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 + +#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ + (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ + (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ + (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \ + (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ + (1 << DV_DDR_SDTMR1_WTR_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ + (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ + (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ + (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ + (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ + (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ + (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ + (2 << DV_DDR_SDTMR2_CKE_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 +#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 + +/* + * Serial Driver info + */ +#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) + +#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE +#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) + +/* + * I2C Configuration + */ +#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 + +/* + * Flash & Environment + */ +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_SYS_NAND_CS 3 +#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE +#define CONFIG_SYS_NAND_MASK_CLE 0x10 +#define CONFIG_SYS_NAND_MASK_ALE 0x8 +#undef CONFIG_SYS_NAND_HW_ECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST +#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K +#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ + CONFIG_SYS_NAND_U_BOOT_SIZE - \ + CONFIG_SYS_MALLOC_LEN - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_NAND_ECCPOS { \ + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 } +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 10 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SPL_NAND_LOAD +#endif + +/* + * Network & Ethernet Configuration + */ +#ifdef CONFIG_DRIVER_TI_EMAC +#define CONFIG_NET_RETRY_COUNT 10 +#endif + +/* + * U-Boot general configuration + */ +#define CONFIG_BOOTFILE "zImage" /* Boot file name */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) + +/* + * USB Configs + */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 + +/* + * Linux Information + */ +#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) +#define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTCOMMAND \ + "run envboot; " \ + "run mmcboot; " + +#define DEFAULT_LINUX_BOOT_ENV \ + "loadaddr=0xc0700000\0" \ + "fdtaddr=0xc0600000\0" \ + "scriptaddr=0xc0600000\0" + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "fdtfile=da850-lcdk.dtb\0" \ + "boot_fdt=yes\0" \ + "boot_fit=0\0" \ + "console=ttyS2,115200n8\0" + +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + +/* SD/MMC */ + +/* defines for SPL */ +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN +#define CONFIG_SPL_STACK 0x8001ff00 +#define CONFIG_SPL_MAX_FOOTPRINT 32768 +#define CONFIG_SPL_PAD_TO 32768 + +/* additions for new relocation code, must added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ + GENERATED_GBL_DATA_SIZE) + +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/openrd.h b/roms/u-boot/include/configs/openrd.h new file mode 100644 index 000000000..03b9393c9 --- /dev/null +++ b/roms/u-boot/include/configs/openrd.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Net Insight + * Written-by: Simon Kagstrom + * + * Based on sheevaplug.h: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + */ + +#ifndef _CONFIG_OPENRD_H +#define _CONFIG_OPENRD_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +#include "mv-common.h" + +/* + * Environment variables configurations + */ +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +/* + * Environment is right behind U-Boot in flash. Make sure U-Boot + * doesn't grow into the environment area. + */ +#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ + "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ + "${x_bootcmd_usb}; bootm 0x6400000;" + +#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console=ttyS0,115200 " \ + CONFIG_MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ + "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ + "x_bootcmd_usb=usb start\0" \ + "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +# ifdef CONFIG_BOARD_IS_OPENRD_BASE +# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +# else +# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ +# endif +# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE +# define CONFIG_PHY_BASE_ADR 0x0 +# define PHY_NO "88E1121" +# else +# define CONFIG_PHY_BASE_ADR 0x8 +# define PHY_NO "88E1116" +# endif +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /*CONFIG_MVSATA_IDE*/ + +#endif /* _CONFIG_OPENRD_BASE_H */ diff --git a/roms/u-boot/include/configs/opos6uldev.h b/roms/u-boot/include/configs/opos6uldev.h new file mode 100644 index 000000000..2fb1634a7 --- /dev/null +++ b/roms/u-boot/include/configs/opos6uldev.h @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Armadeus Systems + * + * Configuration settings for the OPOS6ULDev board + */ + +#ifndef __OPOS6ULDEV_CONFIG_H +#define __OPOS6ULDEV_CONFIG_H + +#include "mx6_common.h" + +#ifdef CONFIG_SPL +#include "imx6_spl.h" + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_REGULATOR +#endif +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 << 20) + +/* Miscellaneous configurable options */ +#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR + +/* Physical Memory Map */ +#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* USB */ +#ifdef CONFIG_USB_EHCI_MX6 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +/* LCD */ +#ifndef CONFIG_SPL_BUILD +#ifdef CONFIG_DM_VIDEO +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_VIDEO_MXS +#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR +#endif +#endif + +/* Environment is stored in the eMMC boot partition */ + +#define CONFIG_ENV_VERSION 100 +#define CONFIG_BOARD_NAME opos6ul +#define ACFG_CONSOLE_DEV ttymxc0 +#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" +#define CONFIG_BOOTCOMMAND "run emmcboot" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ + "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ + "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ + "fdt_addr=0x88000000\0" \ + "fdt_high=0xffffffff\0" \ + "fdt_name=" __stringify(CONFIG_BOARD_NAME) "dev\0" \ + "initrd_high=0xffffffff\0" \ + "ip_dyn=yes\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "kernelimg=" __stringify(CONFIG_BOARD_NAME) "-linux.bin\0" \ + "splashpos=0,0\0" \ + "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0\0" \ + "check_env=if test -n ${flash_env_version}; " \ + "then env default env_version; " \ + "else env set flash_env_version ${env_version}; env save; " \ + "fi; " \ + "if itest ${flash_env_version} != ${env_version}; then " \ + "echo \"*** Warning - Environment version" \ + " change suggests: run flash_reset_env; reset\"; " \ + "env default flash_reset_env; " \ + "else exit; fi; \0" \ + "flash_reset_env=env default -f -a && saveenv && " \ + "echo Environment variables erased!\0" \ + "download_uboot_spl=tftpboot ${loadaddr} ${board_name}-u-boot.spl\0" \ + "flash_uboot_spl=" \ + "if mmc dev 0 1; then " \ + "setexpr sz ${filesize} / 0x200; " \ + "setexpr sz ${sz} + 1; " \ + "if mmc write ${loadaddr} 0x2 ${sz}; then " \ + "echo Flashing of U-boot SPL succeed; " \ + "else echo Flashing of U-boot SPL failed; " \ + "fi; " \ + "fi;\0" \ + "download_uboot_img=tftpboot ${loadaddr} ${board_name}-u-boot.img\0" \ + "flash_uboot_img=" \ + "if mmc dev 0 1; then " \ + "setexpr sz ${filesize} / 0x200; " \ + "setexpr sz ${sz} + 1; " \ + "if mmc write ${loadaddr} 0x8a ${sz}; then " \ + "echo Flashing of U-boot image succeed; " \ + "else echo Flashing of U-boot image failed; " \ + "fi; " \ + "fi;\0" \ + "update_uboot=run download_uboot_spl flash_uboot_spl " \ + "download_uboot_img flash_uboot_img\0" \ + "download_kernel=tftpboot ${loadaddr} ${kernelimg}\0" \ + "flash_kernel=" \ + "if ext4write mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} ${filesize}; then " \ + "echo kernel update succeed; " \ + "else echo kernel update failed; " \ + "fi;\0" \ + "update_kernel=run download_kernel flash_kernel\0" \ + "download_dtb=tftpboot ${fdt_addr} imx6ul-${fdt_name}.dtb\0" \ + "flash_dtb=" \ + "if ext4write mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb ${filesize}; then " \ + "echo dtb update succeed; " \ + "else echo dtb update in failed; " \ + "fi;\0" \ + "update_dtb=run download_dtb flash_dtb\0" \ + "download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ext4\0" \ + "flash_rootfs=" \ + "if mmc dev 0 0; then " \ + "setexpr nbblocks ${filesize} / 0x200; " \ + "setexpr nbblocks ${nbblocks} + 1; " \ + "if mmc write ${loadaddr} 0x40800 ${nbblocks}; then " \ + "echo Flashing of rootfs image succeed; " \ + "else echo Flashing of rootfs image failed; " \ + "fi; " \ + "fi;\0" \ + "update_rootfs=run download_rootfs flash_rootfs\0" \ + "flash_failsafe=" \ + "if mmc dev 0 0; then " \ + "setexpr nbblocks ${filesize} / 0x200; " \ + "setexpr nbblocks ${nbblocks} + 1; " \ + "if mmc write ${loadaddr} 0x800 ${nbblocks}; then " \ + "echo Flashing of rootfs image in failsafe partition succeed; " \ + "else echo Flashing of rootfs image in failsafe partition failed; " \ + "fi; " \ + "fi;\0" \ + "update_failsafe=run download_rootfs flash_failsafe\0" \ + "download_userdata=tftpboot ${loadaddr} ${board_name}-user_data.ext4\0" \ + "flash_userdata=" \ + "if mmc dev 0 0; then " \ + "setexpr nbblocks ${filesize} / 0x200; " \ + "setexpr nbblocks ${nbblocks} + 1; " \ + "if mmc write ${loadaddr} 0 ${nbblocks}; then " \ + "echo Flashing of user_data image succeed; " \ + "else echo Flashing of user_data image failed; " \ + "fi; " \ + "fi;\0" \ + "update_userdata=run download_userdata flash_userdata; mmc rescan\0" \ + "erase_userdata=" \ + "if mmc dev 0 0; then " \ + "echo Erasing eMMC User Data partition, no way out...; " \ + "mw ${loadaddr} 0 0x200000; " \ + "mmc write ${loadaddr} 0 0x1000; " \ + "mmc write ${loadaddr} 0x800 0x1000; " \ + "mmc write ${loadaddr} 0x40800 0x1000; " \ + "mmc write ${loadaddr} 0x440800 0x1000; " \ + "fi;" \ + "mmc rescan\0" \ + "update_all=run update_rootfs update_uboot\0" \ + "initargs=setenv bootargs console=${consoledev},${baudrate} ${extrabootargs}\0" \ + "addipargs=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ + "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ + "addmmcargs=setenv bootargs ${bootargs} root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "emmcboot=run initargs; run addmmcargs; " \ + "load mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} && " \ + "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb && " \ + "bootz ${loadaddr} - ${fdt_addr};\0" \ + "emmcsafeboot=setenv mmcpart 1; setenv mmcroot /dev/mmcblk0p1 ro; run emmcboot;\0" \ + "addnfsargs=setenv bootargs ${bootargs} root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "nfsboot=run initargs; run addnfsargs addipargs; " \ + "nfs ${loadaddr} ${serverip}:${rootpath}/boot/${kernelimg} && " \ + "nfs ${fdt_addr} ${serverip}:${rootpath}/boot/imx6ul-${fdt_name}.dtb && " \ + "bootz ${loadaddr} - ${fdt_addr};\0" + +#endif /* __OPOS6ULDEV_CONFIG_H */ diff --git a/roms/u-boot/include/configs/origen.h b/roms/u-boot/include/configs/origen.h new file mode 100644 index 000000000..8a0e145c7 --- /dev/null +++ b/roms/u-boot/include/configs/origen.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 Samsung Electronics + * + * Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board. + */ + +#ifndef __CONFIG_ORIGEN_H +#define __CONFIG_ORIGEN_H + +#include + +/* High Level Configuration Options */ +#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ +#define CONFIG_ORIGEN 1 /* working with ORIGEN*/ + +/* ORIGEN has 4 bank of DRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ + +/* memtest works on */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + +#define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN + +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +/* Power Down Modes */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +/* MMC SPL */ +#define COPY_BL2_FNPTR_ADDR 0x02020030 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x40007000\0" \ + "rdaddr=0x48000000\0" \ + "kerneladdr=0x40007000\0" \ + "ramdiskaddr=0x48000000\0" \ + "console=ttySAC2,115200n8\0" \ + "mmcdev=0\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "fi; " \ + "fi;" \ + "load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} " + +#define CONFIG_CLK_1000_400_200 + +/* MIU (Memory Interleaving Unit) */ +#define CONFIG_MIU_2BIT_21_7_INTERLEAVED + +#define RESERVE_BLOCK_SIZE (512) +#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ + +#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) + +#define CONFIG_SYS_INIT_SP_ADDR 0x02040000 + +/* U-Boot copy size from boot Media to DRAM.*/ +#define COPY_BL2_SIZE 0x80000 +#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) +#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/owl-common.h b/roms/u-boot/include/configs/owl-common.h new file mode 100644 index 000000000..4ef9e8ed5 --- /dev/null +++ b/roms/u-boot/include/configs/owl-common.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Board configuration file for Actions Semi Owl SoCs. + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + * + */ + +#ifndef _OWL_COMMON_CONFIG_H_ +#define _OWL_COMMON_CONFIG_H_ + +/* SDRAM Definitions */ +#define CONFIG_SYS_SDRAM_BASE 0x0 + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (24000000) /* 24MHz */ + +#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) + +/* Some commands use this as the default load address */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7ffc0) + +/* + * This is the initial SP which is used only briefly for relocating the u-boot + * image to the top of SDRAM. After relocation u-boot moves the stack to the + * proper place. + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7ff00) + +/* Console configuration */ +#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#endif diff --git a/roms/u-boot/include/configs/p1_p2_rdb_pc.h b/roms/u-boot/include/configs/p1_p2_rdb_pc.h new file mode 100644 index 000000000..066311a97 --- /dev/null +++ b/roms/u-boot/include/configs/p1_p2_rdb_pc.h @@ -0,0 +1,771 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + */ + +/* + * QorIQ RDB boards configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#if defined(CONFIG_TARGET_P1020RDB_PC) +#define CONFIG_BOARDNAME "P1020RDB-PC" +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_VSC7385_ENET +#define CONFIG_SLIC +#define __SW_BOOT_MASK 0x03 +#define __SW_BOOT_NOR 0x5c +#define __SW_BOOT_SPI 0x1c +#define __SW_BOOT_SD 0x9c +#define __SW_BOOT_NAND 0xec +#define __SW_BOOT_PCIE 0x6c +#define CONFIG_SYS_L2_SIZE (256 << 10) +#endif + +/* + * P1020RDB-PD board has user selectable switches for evaluating different + * frequency and boot options for the P1020 device. The table that + * follow describe the available options. The front six binary number was in + * accordance with SW3[1:6]. + * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off + * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off + * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off + * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off + * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off + * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off + * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off + */ +#if defined(CONFIG_TARGET_P1020RDB_PD) +#define CONFIG_BOARDNAME "P1020RDB-PD" +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_VSC7385_ENET +#define CONFIG_SLIC +#define __SW_BOOT_MASK 0x03 +#define __SW_BOOT_NOR 0x64 +#define __SW_BOOT_SPI 0x34 +#define __SW_BOOT_SD 0x24 +#define __SW_BOOT_NAND 0x44 +#define __SW_BOOT_PCIE 0x74 +#define CONFIG_SYS_L2_SIZE (256 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#endif + +#if defined(CONFIG_TARGET_P2020RDB) +#define CONFIG_BOARDNAME "P2020RDB-PC" +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_VSC7385_ENET +#define __SW_BOOT_MASK 0x03 +#define __SW_BOOT_NOR 0xc8 +#define __SW_BOOT_SPI 0x28 +#define __SW_BOOT_SD 0x68 /* or 0x18 */ +#define __SW_BOOT_NAND 0xe8 +#define __SW_BOOT_PCIE 0xa8 +#define CONFIG_SYS_L2_SIZE (512 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SPL_MAX_SIZE (128 * 1024) +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SPL_MAX_SIZE (128 * 1024) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif +#endif + +#ifdef CONFIG_MTD_RAW_NAND +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_NAND_INIT +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SPL_MAX_SIZE (128 << 10) +#define CONFIG_TPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) +#elif defined(CONFIG_SPL_BUILD) +#define CONFIG_SPL_INIT_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_MAX_SIZE 4096 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) +#endif /* not CONFIG_TPL_BUILD */ + +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_TPL_PAD_TO 0x20000 +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE +#elif defined(CONFIG_SPL_BUILD) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif +#endif + +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_LBA48 + +#if defined(CONFIG_TARGET_P2020RDB) +#define CONFIG_SYS_CLK_FREQ 100000000 +#else +#define CONFIG_SYS_CLK_FREQ 66666666 +#endif +#define CONFIG_DDR_CLK_FREQ 66666666 + +#define CONFIG_HWCONFIG +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE +#define CONFIG_BTB + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k + SPL code*/ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif + +/* DDR Setup */ +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_DDR_SPD +#define CONFIG_SYS_SPD_BUS_NUM 1 +#define SPD_EEPROM_ADDRESS 0x52 + +#if defined(CONFIG_TARGET_P1020RDB_PD) +#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 +#else +#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#endif +#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +/* Default settings for DDR3 */ +#ifndef CONFIG_TARGET_P2020RDB +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 + +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 + +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ +#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 +#define CONFIG_SYS_DDR_TIMING_4 0x00220001 +#define CONFIG_SYS_DDR_TIMING_5 0x03402400 + +#define CONFIG_SYS_DDR_TIMING_3 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0 0x00330004 +#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 +#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF +#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 +#define CONFIG_SYS_DDR_MODE_1 0x40461520 +#define CONFIG_SYS_DDR_MODE_2 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL 0x0C300000 +#endif + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable + * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) + * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 + * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable + * (early boot only) + * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 + * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 + * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 + * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 + * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* + * Local Bus Definitions + */ +#if defined(CONFIG_TARGET_P1020RDB_PD) +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ +#define CONFIG_SYS_FLASH_BASE 0xec000000 +#else +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ +#define CONFIG_SYS_FLASH_BASE 0xef000000 +#endif + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ + | BR_PS_16 | BR_V) + +#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO + +/* Nand Flash */ +#ifdef CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#if defined(CONFIG_TARGET_P1020RDB_PD) +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#else +#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) +#endif + +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | (2< + */ + +#ifndef _P2371_0000_H +#define _P2371_0000_H + +#include + +#include "tegra210-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-0000" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA + +/* Environment in eMMC, at the end of 2nd "boot sector" */ + +/* SPI */ +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#endif /* _P2371_0000_H */ diff --git a/roms/u-boot/include/configs/p2371-2180.h b/roms/u-boot/include/configs/p2371-2180.h new file mode 100644 index 000000000..5e1d50b25 --- /dev/null +++ b/roms/u-boot/include/configs/p2371-2180.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation + */ + +#ifndef _P2371_2180_H +#define _P2371_2180_H + +#include + +#include "tegra210-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-2180" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA + +/* Environment in eMMC, at the end of 2nd "boot sector" */ + +/* SPI */ +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +/* Crystal is 38.4MHz. clk_m runs at half that rate */ +#define COUNTER_FREQUENCY 19200000 + +#endif /* _P2371_2180_H */ diff --git a/roms/u-boot/include/configs/p2571.h b/roms/u-boot/include/configs/p2571.h new file mode 100644 index 000000000..0b3183a67 --- /dev/null +++ b/roms/u-boot/include/configs/p2571.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation + */ + +#ifndef _P2571_H +#define _P2571_H + +#include + +#include "tegra210-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA + +/* Environment in eMMC, at the end of 2nd "boot sector" */ + +/* SPI */ +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#endif /* _P2571_H */ diff --git a/roms/u-boot/include/configs/p2771-0000.h b/roms/u-boot/include/configs/p2771-0000.h new file mode 100644 index 000000000..4c3da224c --- /dev/null +++ b/roms/u-boot/include/configs/p2771-0000.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2013-2016, NVIDIA CORPORATION. + */ + +#ifndef _P2771_0000_H +#define _P2771_0000_H + +#include + +#include "tegra186-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" + +/* Environment in eMMC, at the end of 2nd "boot sector" */ + +#define BOARD_EXTRA_ENV_SETTINGS \ + "calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \ + "ramdisk_addr_r\0" \ + "kernel_addr_r_align=00200000\0" \ + "kernel_addr_r_offset=00080000\0" \ + "kernel_addr_r_size=02000000\0" \ + "kernel_addr_r_aliases=loadaddr\0" \ + "fdt_addr_r_align=00200000\0" \ + "fdt_addr_r_offset=00000000\0" \ + "fdt_addr_r_size=00200000\0" \ + "scriptaddr_align=00200000\0" \ + "scriptaddr_offset=00000000\0" \ + "scriptaddr_size=00200000\0" \ + "pxefile_addr_r_align=00200000\0" \ + "pxefile_addr_r_offset=00000000\0" \ + "pxefile_addr_r_size=00200000\0" \ + "ramdisk_addr_r_align=00200000\0" \ + "ramdisk_addr_r_offset=00000000\0" \ + "ramdisk_addr_r_size=02000000\0" + +#include "tegra-common-post.h" + +/* Crystal is 38.4MHz. clk_m runs at half that rate */ +#define COUNTER_FREQUENCY 19200000 + +#endif diff --git a/roms/u-boot/include/configs/p3450-0000.h b/roms/u-boot/include/configs/p3450-0000.h new file mode 100644 index 000000000..7f05bebbc --- /dev/null +++ b/roms/u-boot/include/configs/p3450-0000.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018-2019 NVIDIA Corporation. + */ + +#ifndef _P3450_0000_H +#define _P3450_0000_H + +#include + +#include "tegra210-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P3450-0000" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA + +/* Only MMC/PXE/DHCP for now, add USB back in later when supported */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +/* Environment at end of QSPI, in the VER partition */ +#define CONFIG_ENV_SPI_MAX_HZ 48000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +#define CONFIG_PREBOOT + +#define BOARD_EXTRA_ENV_SETTINGS \ + "preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \ + "load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \ + "source ${scriptaddr}; " \ + "fi\0" + +/* General networking support */ +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +/* Crystal is 38.4MHz. clk_m runs at half that rate */ +#define COUNTER_FREQUENCY 19200000 + +#endif /* _P3450_0000_H */ diff --git a/roms/u-boot/include/configs/paz00.h b/roms/u-boot/include/configs/paz00.h new file mode 100644 index 000000000..7a09ac0de --- /dev/null +++ b/roms/u-boot/include/configs/paz00.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include "tegra20-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "Compal Paz00" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00 + +/* Environment in eMMC, at the end of 2nd "boot sector" */ + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/pcl063.h b/roms/u-boot/include/configs/pcl063.h new file mode 100644 index 000000000..4f4d50131 --- /dev/null +++ b/roms/u-boot/include/configs/pcl063.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Collabora Ltd. + * + * Based on include/configs/xpress.h: + * Copyright (C) 2015-2016 Stefan Roese + */ +#ifndef __PCL063_H +#define __PCL063_H + +#include +#include "mx6_common.h" + +/* SPL options */ +#include "imx6_spl.h" + +/* + * There is a bug in some i.MX6UL processors that results in the initial + * portion of OCRAM being unavailable when booting from (at least) an SD + * card. + * + * Tweak the SPL text base address to avoid this. + */ + +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +/* Console configs */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ + +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_256M + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* NAND */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200n8\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "fdt_addr_r=0x82000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ + "ramdisk_addr_r=0x82100000\0" \ + "scriptaddr=0x87000000\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(UBIFS, ubifs, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#endif /* __PCL063_H */ diff --git a/roms/u-boot/include/configs/pcl063_ull.h b/roms/u-boot/include/configs/pcl063_ull.h new file mode 100644 index 000000000..6009521c9 --- /dev/null +++ b/roms/u-boot/include/configs/pcl063_ull.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Board configuration file for Phytec phyBOARD-i.MX6ULL-Segin SBC + * Copyright (C) 2019 Parthiban Nallathambi + * + * Based on include/configs/xpress.h: + * Copyright (C) 2015-2016 Stefan Roese + */ +#ifndef __PCL063_ULL_H +#define __PCL063_ULL_H + +#include +#include +#include "mx6_common.h" + +/* SPL options */ +#include "imx6_spl.h" + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +/* Environment settings */ + +/* Environment in SD */ +#define MMC_ROOTFS_DEV 0 +#define MMC_ROOTFS_PART 2 + +/* Console configs */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ + +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CONFIG_SUPPORT_EMMC_BOOT + +/* I2C configs */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_256M + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* NAND */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define ENV_MMC \ + "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ + "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ + "fitpart=1\0" \ + "bootdelay=3\0" \ + "silent=1\0" \ + "optargs=rw rootwait\0" \ + "mmcautodetect=yes\0" \ + "mmcrootfstype=ext4\0" \ + "mmcfit_name=fitImage\0" \ + "mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \ + "${mmcfit_name}\0" \ + "mmcargs=setenv bootargs " \ + "root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \ + "console=${console} rootfstype=${mmcrootfstype}\0" \ + "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \ + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0,115200n8\0" \ + "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ + "fit_addr=0x82000000\0" \ + ENV_MMC + +#define CONFIG_BOOTCOMMAND "run mmc_mmc_fit" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(DHCP, dhcp, na) + +#include + +#endif /* __PCL063_ULL_H */ diff --git a/roms/u-boot/include/configs/pcm052.h b/roms/u-boot/include/configs/pcm052.h new file mode 100644 index 000000000..960ff982d --- /dev/null +++ b/roms/u-boot/include/configs/pcm052.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for the phytec PCM-052 SoM. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include +#include + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* Enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) + +/* NAND support */ +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define CONFIG_LOADADDR 0x82000000 + +/* We boot from the gfxRAM area of the OCRAM. */ +#define CONFIG_BOARD_SIZE_LIMIT 520192 + +/* if no target-specific extra environment settings were defined by the + target, define an empty one */ +#ifndef PCM052_EXTRA_ENV_SETTINGS +#define PCM052_EXTRA_ENV_SETTINGS +#endif + +/* if no target-specific boot command was defined by the target, + define an empty one */ +#ifndef PCM052_BOOTCOMMAND +#define PCM052_BOOTCOMMAND +#endif + +/* if no target-specific extra environment settings were defined by the + target, define an empty one */ +#ifndef PCM052_NET_INIT +#define PCM052_NET_INIT +#endif + +/* boot command, including the target-defined one if any */ +#define CONFIG_BOOTCOMMAND PCM052_BOOTCOMMAND "run bootcmd_nand" + +/* Extra env settings (including the target-defined ones if any) */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + PCM052_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "blimg_file=u-boot.vyb\0" \ + "blimg_addr=0x81000000\0" \ + "kernel_file=zImage\0" \ + "kernel_addr=0x82000000\0" \ + "fdt_file=zImage.dtb\0" \ + "fdt_addr=0x81000000\0" \ + "ram_file=uRamdisk\0" \ + "ram_addr=0x83000000\0" \ + "filesys=rootfs.ubifs\0" \ + "sys_addr=0x81000000\0" \ + "tftploc=/path/to/tftp/directory/\0" \ + "nfs_root=/path/to/nfs/root\0" \ + "tftptimeout=1000\0" \ + "tftptimeoutcountmax=1000000\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "bootargs_base=setenv bootargs rw " \ + " mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \ + "console=ttyLP1,115200n8\0" \ + "bootargs_sd=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \ + "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \ + "bootargs_nand=setenv bootargs ${bootargs} " \ + "ubi.mtd=5 rootfstype=ubifs root=ubi0:rootfs\0" \ + "bootargs_ram=setenv bootargs ${bootargs} " \ + "root=/dev/ram rw initrd=${ram_addr}\0" \ + "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \ + "fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \ + "fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \ + "bootz ${kernel_addr} - ${fdt_addr}\0" \ + "bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \ + "tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \ + "tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \ + "bootz ${kernel_addr} - ${fdt_addr}\0" \ + "bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \ + "nand read ${fdt_addr} dtb; " \ + "nand read ${kernel_addr} kernel; " \ + "bootz ${kernel_addr} - ${fdt_addr}\0" \ + "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \ + "nand read ${fdt_addr} dtb; " \ + "nand read ${kernel_addr} kernel; " \ + "nand read ${ram_addr} root; " \ + "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ + "update_bootloader_from_tftp=" PCM052_NET_INIT \ + "if tftp ${blimg_addr} "\ + "${tftpdir}${blimg_file}; then " \ + "mtdparts default; " \ + "nand erase.part bootloader; " \ + "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ + "update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \ + "${kernel_file}; " \ + "then mtdparts default; " \ + "nand erase.part kernel; " \ + "nand write ${kernel_addr} kernel ${filesize}; " \ + "if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \ + "nand erase.part dtb; " \ + "nand write ${fdt_addr} dtb ${filesize}; fi\0" \ + "update_kernel_from_tftp=" PCM052_NET_INIT \ + "if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \ + "then setenv fdtsize ${filesize}; " \ + "if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \ + "mtdparts default; " \ + "nand erase.part dtb; " \ + "nand write ${fdt_addr} dtb ${fdtsize}; " \ + "nand erase.part kernel; " \ + "nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \ + "update_rootfs_from_tftp=" PCM052_NET_INIT \ + "if tftp ${sys_addr} ${tftpdir}${filesys}; " \ + "then mtdparts default; " \ + "nand erase.part root; " \ + "ubi part root; " \ + "ubi create rootfs; " \ + "ubi write ${sys_addr} rootfs ${filesize}; fi\0" \ + "update_ramdisk_from_tftp=" PCM052_NET_INIT \ + "if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ + "then mtdparts default; " \ + "nand erase.part root; " \ + "nand write ${ram_addr} root ${filesize}; fi\0" + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Physical memory map */ +#define PHYS_SDRAM (0x80000000) +#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* environment organization */ + +#endif diff --git a/roms/u-boot/include/configs/pcm058.h b/roms/u-boot/include/configs/pcm058.h new file mode 100644 index 000000000..bc48e8094 --- /dev/null +++ b/roms/u-boot/include/configs/pcm058.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) Stefano Babic + */ + +#ifndef __PCM058_CONFIG_H +#define __PCM058_CONFIG_H + +#ifdef CONFIG_SPL +#include "imx6_spl.h" +#endif + +#include "mx6_common.h" + +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) + +/* Enable NAND support */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define ENV_MMC \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "fitpart=1\0" \ + "mmcrootfstype=ext4\0" \ + "fitname=fitImage\0" \ + "mmcloadfit=load mmc ${mmcdev}:${fitpart} ${loadaddr} ${fitname}\0" \ + "mmcargs=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcpart} " \ + "rootfstype=${mmcrootfstype} ${optargs}\0" \ + "mmcboot=run mmcloadfit;run mmcargs;bootm ${loadaddr}\0" + +#define ENV_NAND \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "nandroot=ubi0:root ubi.mtd=rootfs\0" \ + "nandrootfstype=ubifs\0" \ + "nandargs=setenv bootargs root=${nandroot} " \ + "rootfstype=${nandrootfstype} ${mtdparts} ${optargs}\0" \ + "nandloadfit=ubi part rootfs;ubi readvol ${loadaddr} fit\0" \ + "nandboot=run nandloadfit;run nandargs;bootm ${loadaddr}\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x30000000\0" \ + "optargs=rw rootwait\0" \ + ENV_MMC \ + ENV_NAND + +#define CONFIG_BOOTCOMMAND "run mmcboot;run nandboot" +#endif diff --git a/roms/u-boot/include/configs/pdu001.h b/roms/u-boot/include/configs/pdu001.h new file mode 100644 index 000000000..53342ce19 --- /dev/null +++ b/roms/u-boot/include/configs/pdu001.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * pdu001.h + * + * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef __CONFIG_PDU001_H +#define __CONFIG_PDU001_H + +#include + +/* Using 32K of volatile storage for environment */ + +#define MACH_TYPE_PDU001 5075 +#define CONFIG_MACH_TYPE MACH_TYPE_PDU001 + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#if CONFIG_CONS_INDEX == 1 + #define CONSOLE_DEV "ttyO0" +#elif CONFIG_CONS_INDEX == 2 + #define CONSOLE_DEV "ttyO1" +#elif CONFIG_CONS_INDEX == 3 + #define CONSOLE_DEV "ttyO2" +#elif CONFIG_CONS_INDEX == 4 + #define CONSOLE_DEV "ttyO3" +#elif CONFIG_CONS_INDEX == 5 + #define CONSOLE_DEV "ttyO4" +#elif CONFIG_CONS_INDEX == 6 + #define CONSOLE_DEV "ttyO5" +#endif + +#define CONFIG_BOOTCOMMAND \ + "run eval_boot_device;" \ + "part uuid mmc ${mmc_boot}:${root_fs_partition} root_fs_partuuid;" \ + "setenv bootargs console=${console} " \ + "vt.global_cursor_default=0 " \ + "root=PARTUUID=${root_fs_partuuid} " \ + "rootfstype=ext4 " \ + "rootwait " \ + "rootdelay=1;" \ + "fatload mmc ${mmc_boot} ${fdtaddr} ${fdtfile};" \ + "fatload mmc ${mmc_boot} ${loadaddr} ${bootfile};" \ + "bootz ${loadaddr} - ${fdtaddr}" + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "fdtfile=am335x-pdu001.dtb\0" \ + "bootfile=zImage\0" \ + "console=" CONSOLE_DEV ",115200n8\0" \ + "root_fs_partition=2\0" \ + "eval_boot_device=" \ + "if test $boot_device = emmc; then " \ + "setenv mmc_boot 0;" \ + "elif test $boot_device = sdcard; then " \ + "setenv mmc_boot 1;" \ + "else " \ + "echo Bootdevice is neither MMC0 nor MMC1;" \ + "reset;" \ + "fi;" \ + "\0" +#endif + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 UART0_BASE +#define CONFIG_SYS_NS16550_COM2 UART1_BASE +#define CONFIG_SYS_NS16550_COM3 UART2_BASE +#define CONFIG_SYS_NS16550_COM4 UART3_BASE +#define CONFIG_SYS_NS16550_COM5 UART4_BASE +#define CONFIG_SYS_NS16550_COM6 UART5_BASE + +#endif /* ! __CONFIG_PDU001_H */ diff --git a/roms/u-boot/include/configs/peach-pi.h b/roms/u-boot/include/configs/peach-pi.h new file mode 100644 index 000000000..ba82aaf65 --- /dev/null +++ b/roms/u-boot/include/configs/peach-pi.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Samsung Electronics + * + * Configuration settings for the SAMSUNG/GOOGLE PEACH-PI board. + */ + +#ifndef __CONFIG_PEACH_PI_H +#define __CONFIG_PEACH_PI_H + +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x22000000\0" \ + "fdt_addr_r=0x23000000\0" \ + "ramdisk_addr_r=0x23300000\0" \ + "scriptaddr=0x30000000\0" \ + "pxefile_addr_r=0x31000000\0" + +#include +#include +#include + +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) + +/* Display */ +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPP LCD_COLOR16 +#endif + +#define CONFIG_POWER_TPS65090_EC + +/* DRAM Memory Banks */ +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + +#endif /* __CONFIG_PEACH_PI_H */ diff --git a/roms/u-boot/include/configs/peach-pit.h b/roms/u-boot/include/configs/peach-pit.h new file mode 100644 index 000000000..16fb2f3a0 --- /dev/null +++ b/roms/u-boot/include/configs/peach-pit.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG/GOOGLE PEACH-PIT board. + */ + +#ifndef __CONFIG_PEACH_PIT_H +#define __CONFIG_PEACH_PIT_H + +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x22000000\0" \ + "fdt_addr_r=0x23000000\0" \ + "ramdisk_addr_r=0x23300000\0" \ + "scriptaddr=0x30000000\0" \ + "pxefile_addr_r=0x31000000\0" + +#include +#include +#include + +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) + +/* DRAM Memory Banks */ +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + +#endif /* __CONFIG_PEACH_PIT_H */ diff --git a/roms/u-boot/include/configs/pg-wcom-expu1.h b/roms/u-boot/include/configs/pg-wcom-expu1.h new file mode 100644 index 000000000..e08d94141 --- /dev/null +++ b/roms/u-boot/include/configs/pg-wcom-expu1.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Hitachi ABB Power Grids + */ + +#ifndef __CONFIG_PG_WCOM_EXPU1_H +#define __CONFIG_PG_WCOM_EXPU1_H + +#define WCOM_EXPU1 +#define CONFIG_HOSTNAME "EXPU1" + +#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" +#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" + +/* CLIPS FPGA Definitions */ +#define CONFIG_SYS_CSPR3_EXT (0x00) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ + CSOR_GPCM_TRHZ_40) +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ + FTIM0_GPCM_TEADC(0x7) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x12)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x12)) +#define CONFIG_SYS_CS3_FTIM3 0x04000000 + +/* PRST */ +#define WCOM_CLIPS_RST 0 +#define WCOM_QSFP_RST 1 +#define WCOM_PHY_RST 2 +#define WCOM_TMG_RST 3 +#define KM_DBG_ETH_RST 15 + +/* QRIO GPIOs used for deblocking */ +#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A +#define KM_I2C_DEBLOCK_SCL 20 +#define KM_I2C_DEBLOCK_SDA 21 + +/* ZL30343 on SPI */ +#define WCOM_ZL30343_CFG_ADDR 0xe8070000 +#define WCOM_ZL30343_SPI_BUS 0 +#define WCOM_ZL30343_CS 0 + +#include "km/pg-wcom-ls102xa.h" + +#endif /* __CONFIG_PG_WCOM_EXPU1_H */ diff --git a/roms/u-boot/include/configs/pg-wcom-seli8.h b/roms/u-boot/include/configs/pg-wcom-seli8.h new file mode 100644 index 000000000..9a7669c94 --- /dev/null +++ b/roms/u-boot/include/configs/pg-wcom-seli8.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Hitachi Power Grids. All rights reserved. + */ + +#ifndef __CONFIG_PG_WCOM_SELI8_H +#define __CONFIG_PG_WCOM_SELI8_H + +#define CONFIG_HOSTNAME "SELI8" + +#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" +#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" + +/* PAXK FPGA Definitions */ +#define CONFIG_SYS_CSPR3_EXT (0x00) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ + CSOR_GPCM_TRHZ_40) +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ + FTIM0_GPCM_TEADC(0x7) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x12)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x12)) +#define CONFIG_SYS_CS3_FTIM3 0x04000000 + +/* PRST */ +#define KM_LIU_RST 0 +#define KM_PAXK_RST 1 +#define KM_DBG_ETH_RST 15 + +/* QRIO GPIOs used for deblocking */ +#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A +#define KM_I2C_DEBLOCK_SCL 20 +#define KM_I2C_DEBLOCK_SDA 21 + +#include "km/pg-wcom-ls102xa.h" + +#endif /* __CONFIG_PG_WCOM_SELI8_H */ diff --git a/roms/u-boot/include/configs/phycore_am335x_r2.h b/roms/u-boot/include/configs/phycore_am335x_r2.h new file mode 100644 index 000000000..4a347fe15 --- /dev/null +++ b/roms/u-boot/include/configs/phycore_am335x_r2.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * phycore_am335x_r2.h + * + * Phytec phyCORE-AM335x R2 (PCL060 / PCM060) boards information header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH + * Copyright (C) 2019 DENX Software Engineering GmbH + */ + +#ifndef __CONFIG_PHYCORE_AM335x_R2_H +#define __CONFIG_PHYCORE_AM335x_R2_H + +#include + +#define CONFIG_MACH_TYPE MACH_TYPE_SBC_PHYCORE_AM335X + +#ifdef CONFIG_MTD_RAW_NAND +#define NANDARGS \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:root ubi.mtd=NAND.UBI\0" \ + "nandrootfstype=ubifs rootwait rw fsck.repair=yes\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "ubi part NAND.UBI; " \ + "ubi readvol ${fdtaddr} oftree; " \ + "ubi readvol ${loadaddr} kernel; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" + +#else +#define NANDARGS "" +#endif + +/* set to negative value for no autoboot */ +#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv mmcdev " #instance "; "\ + "setenv bootpart " #instance ":1 ; "\ + "setenv rootpart " #instance ":2 ; "\ + "run mmcboot\0" + +#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "run nandboot\0" + +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(LEGACY_MMC, legacy_mmc, 0) \ + func(MMC, mmc, 1) \ + func(LEGACY_MMC, legacy_mmc, 1) \ + func(NAND, nand, 0) + +#include +#include +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_MMC_TI_ARGS \ + DEFAULT_LINUX_BOOT_ENV \ + "bootfile=zImage\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "console=ttyS0,115200\0" \ + "optargs=\0" \ + "mmcrootfstype=ext2 rootwait\0" \ + "finduuid=part uuid mmc ${rootpart} uuid\0" \ + "boot_fit=0\0" \ + NANDARGS \ + BOOTENV + +/* Clock Macros */ +#define V_OSCK 25000000 /* Clock output from T2 */ +#define V_SCLK V_OSCK + +#define CONFIG_POWER_TPS65910 + +#ifdef CONFIG_MTD_RAW_NAND +/* NAND: device related configs */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +/* NAND: driver related configs */ +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW + +/* NAND: SPL related configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ +#endif +#endif /* !CONFIG_MTD_RAW_NAND */ + +/* CPU */ + +#ifdef CONFIG_SPI_BOOT +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 +#elif defined(CONFIG_ENV_IS_IN_NAND) +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#endif + +#endif /* ! __CONFIG_PHYCORE_AM335x_R2_H */ diff --git a/roms/u-boot/include/configs/phycore_imx8mm.h b/roms/u-boot/include/configs/phycore_imx8mm.h new file mode 100644 index 000000000..fd69dc41a --- /dev/null +++ b/roms/u-boot/include/configs/phycore_imx8mm.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +#ifndef __PHYCORE_IMX8MM_H +#define __PHYCORE_IMX8MM_H + +#include +#include +#include + +#define CONFIG_SYS_BOOTM_LEN SZ_64M +#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x920000 +#define CONFIG_SPL_BSS_START_ADDR 0x910000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x930000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "image=Image\0" \ + "console=ttymxc2,115200\0" \ + "fdt_addr=0x48000000\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "ipaddr=192.168.3.11\0" \ + "serverip=192.168.3.10\0" \ + "netmask=255.225.255.0\0" \ + "ip_dyn=no\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=2\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi;\0 " \ + "nfsroot=/nfs\0" \ + "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \ + "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi;" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +#define PHYS_SDRAM SZ_1G +#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ + +/* UART */ +#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE SZ_2K +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* USDHC */ +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* I2C */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* ENET1 */ +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC +#define IMX_FEC_BASE 0x30BE0000 + +#endif /* __PHYCORE_IMX8MM_H */ diff --git a/roms/u-boot/include/configs/phycore_imx8mp.h b/roms/u-boot/include/configs/phycore_imx8mp.h new file mode 100644 index 000000000..049004985 --- /dev/null +++ b/roms/u-boot/include/configs/phycore_imx8mp.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (C) 2020 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +#ifndef __PHYCORE_IMX8MP_H +#define __PHYCORE_IMX8MP_H + +#include +#include + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +#define CONFIG_SPL_MAX_SIZE (152 * SZ_1K) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x960000 +#define CONFIG_SPL_BSS_START_ADDR 0x98FC00 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PCA9450 + +#define CONFIG_SYS_I2C + +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "image=Image\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr=0x48000000\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=2\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi;\0 " \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi;" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 + +/* UART */ +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE SZ_2K +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* USDHC */ +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* I2C */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#endif /* __PHYCORE_IMX8MP_H */ diff --git a/roms/u-boot/include/configs/phycore_rk3288.h b/roms/u-boot/include/configs/phycore_rk3288.h new file mode 100644 index 000000000..2b7a0670c --- /dev/null +++ b/roms/u-boot/include/configs/phycore_rk3288.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include + +#undef BOOT_TARGET_DEVICES + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#endif diff --git a/roms/u-boot/include/configs/pic32mzdask.h b/roms/u-boot/include/configs/pic32mzdask.h new file mode 100644 index 000000000..d50edc771 --- /dev/null +++ b/roms/u-boot/include/configs/pic32mzdask.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (c) 2015 Purna Chandra Mandal + * + * Microchip PIC32MZ[DA] Starter Kit. + */ + +#ifndef __PIC32MZDASK_CONFIG_H +#define __PIC32MZDASK_CONFIG_H + +/* System Configuration */ + +/*-------------------------------------------- + * CPU configuration + */ +/* CPU Timer rate */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 100000000 + +/*---------------------------------------------------------------------- + * Memory Layout + */ +/* Initial RAM for temporary stack, global data */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_RAM_ADDR \ + (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) + +/* SDRAM Configuration (for final code, data, stack, heap) */ +#define CONFIG_SYS_SDRAM_BASE 0x88000000 +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_BOOTPARAMS_LEN (4 << 10) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (192 << 10) + +#define CONFIG_SYS_LOAD_ADDR 0x88500000 /* default load address */ +#define CONFIG_SYS_ENV_ADDR 0x88300000 +#define CONFIG_SYS_FDT_ADDR 0x89d00000 + +/* Memory Test */ + +/*---------------------------------------------------------------------- + * Commands + */ + +/*------------------------------------------------------------ + * Console Configuration + */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/*----------------------------------------------------------------------- + * Networking Configuration + */ +#define CONFIG_SYS_RX_ETH_BUFFER 8 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_ARP_TIMEOUT 500 /* millisec */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/*-------------------------------------------------- + * USB Configuration + */ + +/* ------------------------------------------------- + * Environment + */ + +/* --------------------------------------------------------------------- + * Board boot configuration + */ +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define MEM_LAYOUT_ENV_SETTINGS \ + "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ + "fdt_addr_r="__stringify(CONFIG_SYS_FDT_ADDR)"\0" \ + "scriptaddr="__stringify(CONFIG_SYS_ENV_ADDR)"\0" + +#define CONFIG_LEGACY_BOOTCMD_ENV \ + "legacy_bootcmd= " \ + "if load mmc 0 ${scriptaddr} uEnv.txt; then " \ + "env import -tr ${scriptaddr} ${filesize}; " \ + "if test -n \"${bootcmd_uenv}\" ; then " \ + "echo Running bootcmd_uenv ...; " \ + "run bootcmd_uenv; " \ + "fi; " \ + "fi; \0" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + CONFIG_LEGACY_BOOTCMD_ENV \ + BOOTENV + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "run distro_bootcmd || run legacy_bootcmd" + +#endif /* __PIC32MZDASK_CONFIG_H */ diff --git a/roms/u-boot/include/configs/pico-imx6.h b/roms/u-boot/include/configs/pico-imx6.h new file mode 100644 index 000000000..19c8aeb71 --- /dev/null +++ b/roms/u-boot/include/configs/pico-imx6.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for the pico-imx6 board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + +#include "imx6_spl.h" + +#ifdef CONFIG_SPL_OS_BOOT +/* Falcon Mode */ +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 + +/* Falcon Mode - MMC support: args@1MB kernel@2MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR +#define CONFIG_SUPPORT_EMMC_BOOT +#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE + +/* USB Configs */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +#define CONFIG_DFU_ENV_SETTINGS \ + "dfu_alt_info=" \ + "spl raw 0x2 0x400;" \ + "u-boot raw 0x8a 0x1000;" \ + "/boot/zImage ext4 0 1;" \ + "rootfs part 0 1\0" \ + +#define BOOTMENU_ENV \ + "bootmenu_0=Boot using PICO-Hobbit baseboard=" \ + "setenv baseboard hobbit; saveenv; run base_boot\0" \ + "bootmenu_1=Boot using PICO-Pi baseboard=" \ + "setenv baseboard pi; saveenv; run base_boot\0" \ + "bootmenu_2=Boot using PICO-Dwarf baseboard=" \ + "setenv baseboard dwarf; saveenv; run base_boot\0" \ + "bootmenu_3=Boot using PICO-Nymph baseboard=" \ + "setenv baseboard nymph; saveenv; run base_boot\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + BOOTMENU_ENV \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_addr_r=0x18000000\0" \ + "fdt_addr=0x18000000\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + CONFIG_DFU_ENV_SETTINGS \ + "finduuid=part uuid mmc 0:1 uuid\0" \ + "findfdt="\ + "if test $baseboard = hobbit && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-pico-hobbit.dtb; fi; " \ + "if test $baseboard = pi && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-pico-pi.dtb; fi; " \ + "if test $baseboard = dwarf && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-pico-dwarf.dtb; fi; " \ + "if test $baseboard = nymph && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-pico-nymph.dtb; fi; " \ + "if test $baseboard = hobbit && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-pico-hobbit.dtb; fi; " \ + "if test $baseboard = pi && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-pico-pi.dtb; fi; " \ + "if test $baseboard = dwarf && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-pico-dwarf.dtb; fi; " \ + "if test $baseboard = nymph && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-pico-nymph.dtb; fi; " \ + "if test $fdtfile = ask; then " \ + "echo WARNING: Could not determine dtb to use; fi; \0" \ + "default_boot=" \ + "if test $baseboard = ask ; then " \ + "bootmenu -1; " \ + "else " \ + "run base_boot;" \ + "fi; \0" \ + "base_boot=run findfdt; run finduuid; run distro_bootcmd\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "ramdiskaddr=0x13000000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) + +#include + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ + +/* Environment starts at 768k = 768 * 1024 = 786432 */ +/* + * Detect overlap between U-Boot image and environment area in build-time + * + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset + * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776 + * + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so + * write the direct value here + */ +#define CONFIG_BOARD_SIZE_LIMIT 715776 + +/* Ethernet Configuration */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 1 + +/* Framebuffer */ +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +#endif /* __CONFIG_H * */ diff --git a/roms/u-boot/include/configs/pico-imx6ul.h b/roms/u-boot/include/configs/pico-imx6ul.h new file mode 100644 index 000000000..747ef09f3 --- /dev/null +++ b/roms/u-boot/include/configs/pico-imx6ul.h @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Technexion Ltd. + * + * Configuration settings for the Technexion PICO-IMX6UL-EMMC board. + */ +#ifndef __PICO_IMX6UL_CONFIG_H +#define __PICO_IMX6UL_CONFIG_H + + +#include +#include +#include "mx6_common.h" +#include +#include "imx6_spl.h" + +#ifdef CONFIG_SPL_OS_BOOT +/* Falcon Mode */ +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SYS_SPL_ARGS_ADDR 0x88000000 + +/* Falcon Mode - MMC support: args@1MB kernel@2MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ +#endif + +/* Network support */ + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ + +#define CONFIG_MXC_UART_BASE UART6_BASE_ADDR + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_USBD_HS + +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +#define CONFIG_DFU_ENV_SETTINGS \ + "dfu_alt_info=" \ + "spl raw 0x2 0x400;" \ + "u-boot raw 0x8a 0x400;" \ + "/boot/zImage ext4 0 1;" \ + "/boot/imx6ul-pico-hobbit.dtb ext4 0 1;" \ + "/boot/imx6ul-pico-pi.dtb ext4 0 1;" \ + "rootfs part 0 1\0" \ + +#define BOOTMENU_ENV \ + "bootmenu_0=Boot using PICO-Dwarf baseboard=" \ + "setenv fdtfile imx6ul-pico-dwarf.dtb\0" \ + "bootmenu_1=Boot using PICO-Hobbit baseboard=" \ + "setenv fdtfile imx6ul-pico-hobbit.dtb\0" \ + "bootmenu_2=Boot using PICO-Pi baseboard=" \ + "setenv fdtfile imx6ul-pico-pi.dtb\0" \ + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "splashpos=m,m\0" \ + "console=ttymxc5\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "videomode=video=ctfb:x:800,y:480,depth:24,mode:0,pclk:30000,le:46,ri:210,up:22,lo:23,hs:20,vs:10,sync:0,vmode:0\0" \ + BOOTMENU_ENV \ + "fdt_addr=0x83000000\0" \ + "fdt_addr_r=0x83000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x83000000\0" \ + "ramdiskaddr=0x83000000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "mmcautodetect=yes\0" \ + CONFIG_DFU_ENV_SETTINGS \ + "findfdt=" \ + "if test $fdtfile = ask ; then " \ + "bootmenu -1; fi;" \ + "if test $fdtfile != ask ; then " \ + "saveenv; fi;\0" \ + "finduuid=part uuid mmc 0:1 uuid\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \ + "fastboot_partition_alias_system=rootfs\0" \ + "setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include +#include + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* I2C configs */ +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* environment organization */ +/* Environment starts at 768k = 768 * 1024 = 786432 */ +/* + * Detect overlap between U-Boot image and environment area in build-time + * + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset + * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776 + * + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so + * write the direct value here + */ +#define CONFIG_BOARD_SIZE_LIMIT 715776 + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR +#endif + +#endif /* __PICO_IMX6UL_CONFIG_H */ diff --git a/roms/u-boot/include/configs/pico-imx7d.h b/roms/u-boot/include/configs/pico-imx7d.h new file mode 100644 index 000000000..80de1158a --- /dev/null +++ b/roms/u-boot/include/configs/pico-imx7d.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 NXP Semiconductors + * + * Configuration settings for the i.MX7D Pico board. + */ + +#ifndef __PICO_IMX7D_CONFIG_H +#define __PICO_IMX7D_CONFIG_H + +#include "mx7_common.h" + +#include "imx7_spl.h" + +#ifdef CONFIG_SPL_OS_BOOT +/* Falcon Mode */ +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SYS_SPL_ARGS_ADDR 0x88000000 + +/* Falcon Mode - MMC support: args@1MB kernel@2MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR + +/* MMC Config */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_DFU_ENV_SETTINGS \ + "dfu_alt_info=" \ + "spl raw 0x2 0x400;" \ + "u-boot raw 0x8a 0x1000;" \ + "/boot/zImage ext4 0 1;" \ + "/boot/imx7d-pico-hobbit.dtb ext4 0 1;" \ + "/boot/imx7d-pico-pi.dtb ext4 0 1;" \ + "rootfs part 0 1\0" \ + +/* When booting with FIT specify the node entry containing boot.scr */ +#if defined(CONFIG_FIT) +#define PICO_BOOT_ENV \ + BOOTENV \ + "fdtovaddr=0x83100000\0" \ + "scriptaddr=0x83200000\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "rootwait rw\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "iminfo ${scriptaddr};" \ + "if test $? -eq 1; then hab_failsafe; fi;" \ + "source ${scriptaddr}:bootscr\0" +#else +#define PICO_BOOT_ENV \ + "bootmenu_0=Boot using PICO-Hobbit baseboard=" \ + "setenv fdtfile imx7d-pico-hobbit.dtb\0" \ + "bootmenu_1=Boot using PICO-Dwarf baseboard=" \ + "setenv fdtfile imx7d-pico-dwarf.dtb\0" \ + "bootmenu_2=Boot using PICO-Nymph baseboard=" \ + "setenv fdtfile imx7d-pico-nymph.dtb\0" \ + "bootmenu_3=Boot using PICO-Pi baseboard=" \ + "setenv fdtfile imx7d-pico-pi.dtb\0" \ + BOOTENV +#endif + + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "image=zImage\0" \ + "splashpos=m,m\0" \ + "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "console=ttymxc4\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "videomode=video=ctfb:x:800,y:480,depth:24,mode:0,pclk:30000,le:46,ri:210,up:22,lo:23,hs:20,vs:10,sync:0,vmode:0\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_addr_r=0x83000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x83000000\0" \ + "ramdiskaddr=0x83000000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + CONFIG_DFU_ENV_SETTINGS \ + "findfdt=" \ + "if test $fdtfile = ask ; then " \ + "bootmenu -1; fi;" \ + "if test $fdtfile != ask ; then " \ + "saveenv; fi;\0" \ + "finduuid=part uuid mmc 0:1 uuid\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \ + "fastboot_partition_alias_system=rootfs\0" \ + "setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \ + PICO_BOOT_ENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include +#include + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* I2C configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 +#define CONFIG_SYS_I2C_MXC_I2C2 +#define CONFIG_SYS_I2C_MXC_I2C3 +#define CONFIG_SYS_I2C_MXC_I2C4 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + +#ifdef CONFIG_DM_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#endif + +/* FLASH and environment organization */ + +/* Environment starts at 768k = 768 * 1024 = 786432 */ +/* + * Detect overlap between U-Boot image and environment area in build-time + * + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset + * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776 + * + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so + * write the direct value here + */ +#define CONFIG_BOARD_SIZE_LIMIT 715776 + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#endif diff --git a/roms/u-boot/include/configs/pico-imx8mq.h b/roms/u-boot/include/configs/pico-imx8mq.h new file mode 100644 index 000000000..7a5891652 --- /dev/null +++ b/roms/u-boot/include/configs/pico-imx8mq.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8M_PICOPI_H +#define __IMX8M_PICOPI_H + +#include +#include + +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x182000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#endif + +#define CONFIG_REMAKE_ELF + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 1 +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE +#define IMX_FEC_BASE 0x30BE0000 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc0,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "fdt_file=imx8mq-pico-pi.dtb\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "booti; " + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MXC_GPIO + +/* I2C Configs */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_OF_SYSTEM_SETUP + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DM_PMIC +#endif + +#define CONFIG_SYS_BOOTM_LEN SZ_128M + +#endif diff --git a/roms/u-boot/include/configs/pinebook-pro-rk3399.h b/roms/u-boot/include/configs/pinebook-pro-rk3399.h new file mode 100644 index 000000000..d478b1991 --- /dev/null +++ b/roms/u-boot/include/configs/pinebook-pro-rk3399.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Rockchip Electronics Co., Ltd + * Copyright (C) 2020 Peter Robinson + */ + +#ifndef __PINEBOOK_PRO_RK3399_H +#define __PINEBOOK_PRO_RK3399_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +#endif diff --git a/roms/u-boot/include/configs/plutux.h b/roms/u-boot/include/configs/plutux.h new file mode 100644 index 000000000..7fc06e832 --- /dev/null +++ b/roms/u-boot/include/configs/plutux.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + * (C) Copyright 2011-2012 + * Avionic Design GmbH + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra20-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Plutux" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +/* NAND support */ +#define CONFIG_TEGRA_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Environment in NAND, aligned to start of last sector */ + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/pm9261.h b/roms/u-boot/include/configs/pm9261.h new file mode 100644 index 000000000..2cc47d123 --- /dev/null +++ b/roms/u-boot/include/configs/pm9261.h @@ -0,0 +1,255 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * Ilko Iliev + * + * Configuation settings for the RONETIX PM9261 board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ + +#include +/* ARM asynchronous clock */ + +#define MASTER_PLL_DIV 15 +#define MASTER_PLL_MUL 162 +#define MAIN_PLL_DIV 2 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 + +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" + +#define CONFIG_MACH_TYPE MACH_TYPE_PM9261 + +/* clocks */ +/* CKGR_MOR - enable main osc. */ +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOR_MOSCEN | \ + (255 << 8)) /* Main Oscillator Start-up Time */ +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_PLLXR_OUT(3) | \ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_MCKR_CSS_SLOW | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_MCKR_CSS_PLLA | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) + +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 +/* no pull-up for D[31:16] */ +#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 + +/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ +#define CONFIG_SYS_MATRIX_EBICSA_VAL \ + (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A) + +/* SDRAM */ +/* SDRAMC_MR Mode register */ +#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL +/* SDRAMC_TR - Refresh Timer register */ +#define CONFIG_SYS_SDRC_TR_VAL1 0x13C +/* SDRAMC_CR - Configuration register*/ +#define CONFIG_SYS_SDRC_CR_VAL \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_3 | \ + AT91_SDRAMC_DBW_32 | \ + (1 << 8) | /* Write Recovery Delay */ \ + (7 << 12) | /* Row Cycle Delay */ \ + (3 << 16) | /* Row Precharge Delay */ \ + (2 << 20) | /* Row to Column Delay */ \ + (5 << 24) | /* Active to Precharge Delay */ \ + (1 << 28)) /* Exit Self Refresh to Active Delay */ + +/* Memory Device Register -> SDRAM */ +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ + AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ + AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ + AT91_SMC_MODE_DBW_16 | \ + AT91_SMC_MODE_TDF | \ + AT91_SMC_MODE_TDF_CYCLE(6)) + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_CR_PROCRST | \ + AT91_RSTC_MR_ERSTL(1) | \ + AT91_RSTC_MR_ERSTL(2)) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ + AT91_WDT_MR_WDV(0xfff) | \ + AT91_WDT_MR_WDDIS | \ + AT91_WDT_MR_WDD(0xfff)) + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#undef CONFIG_SKIP_LOWLEVEL_INIT + +/* + * Hardware drivers + */ + +/* LCD */ +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_BGR555 1 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 + +/* SDRAM */ +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* NAND flash */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD22 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 22) +/* our CLE is AD21 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 21) +#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) +#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16) + +/* NOR flash */ +#define PHYS_FLASH_1 0x10000000 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* Ethernet */ +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x30000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 4) +#define CONFIG_DM9000_USE_16BIT 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 + +#undef CONFIG_SYS_USE_DATAFLASH_CS0 +#undef CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SYS_USE_FLASH 1 + +#ifdef CONFIG_SYS_USE_DATAFLASH_CS0 + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x22000000 0x84000 0x210000; " \ + "bootm 0x22000000" + +#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" + +#elif defined (CONFIG_SYS_USE_FLASH) +/* JFFS Partition offset set */ +#define CONFIG_SYS_JFFS2_FIRST_BANK 0 +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +/* 512k reserved for u-boot */ +#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 + +#define CONFIG_BOOTCOMMAND "run flashboot" + +#define CONFIG_CON_ROT "fbcon=rotate:3 " + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "partition=nand0,0\0" \ + "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + CONFIG_CON_ROT \ + "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot 0x22000000 vmImage;" \ + "run ramargs;run addip;bootm 22000000\0" \ + "nfsboot=tftpboot 0x22000000 vmImage;" \ + "run nfsargs;run addip;bootm 22000000\0" \ + "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ + "" +#else +#error "Undefined memory device" +#endif + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN \ + ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ + GENERATED_GBL_DATA_SIZE) + +#endif diff --git a/roms/u-boot/include/configs/pm9263.h b/roms/u-boot/include/configs/pm9263.h new file mode 100644 index 000000000..6c882b6ff --- /dev/null +++ b/roms/u-boot/include/configs/pm9263.h @@ -0,0 +1,284 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * Ilko Iliev + * + * Configuation settings for the RONETIX PM9263 board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include + +/* ARM asynchronous clock */ + +#define MASTER_PLL_DIV 6 +#define MASTER_PLL_MUL 65 +#define MAIN_PLL_DIV 2 /* 2 or 4 */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ + +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" + +#define CONFIG_MACH_TYPE MACH_TYPE_PM9263 + +/* clocks */ +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOR_MOSCEN | \ + (255 << 8)) /* Main Oscillator Start-up Time */ +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_PLLXR_OUT(3) | \ + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ + (2 << 28) | /* PLL Clock Frequency Range */ \ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) + +#if (MAIN_PLL_DIV == 2) +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_MCKR_CSS_SLOW | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_MCKR_CSS_PLLA | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) +#else +/* PCK/4 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_MCKR_CSS_SLOW | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_4) +/* PCK/4 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_MCKR_CSS_PLLA | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_4) +#endif +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +/* no pull-up for D[31:16] */ +#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 +/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ +#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ + (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ + AT91_MATRIX_CSA_EBI_CS1A) + +/* SDRAM */ +/* SDRAMC_MR Mode register */ +#define CONFIG_SYS_SDRC_MR_VAL1 0 +/* SDRAMC_TR - Refresh Timer register */ +#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA +/* SDRAMC_CR - Configuration register*/ +#define CONFIG_SYS_SDRC_CR_VAL \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_2 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* tWR - Write Recovery Delay */ \ + (7 << 12) | /* tRC - Row Cycle Delay */ \ + (2 << 16) | /* tRP - Row Precharge Delay */ \ + (2 << 20) | /* tRCD - Row to Column Delay */ \ + (5 << 24) | /* tRAS - Active to Precharge Delay */ \ + (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ + +/* Memory Device Register -> SDRAM */ +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ + AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ + AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ + AT91_SMC_MODE_DBW_16 | \ + AT91_SMC_MODE_TDF | \ + AT91_SMC_MODE_TDF_CYCLE(6)) + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_CR_PROCRST | \ + AT91_RSTC_MR_ERSTL(1) | \ + AT91_RSTC_MR_ERSTL(2)) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ + AT91_WDT_MR_WDV(0xfff) | \ + AT91_WDT_MR_WDDIS | \ + AT91_WDT_MR_WDD(0xfff)) + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#undef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_USER_LOWLEVEL_INIT 1 + +/* + * Hardware drivers + */ +/* LCD */ +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_BGR555 1 + +#define CONFIG_LCD_IN_PSRAM 1 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 + +/* SDRAM */ +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* NOR flash, if populated */ +#define PHYS_FLASH_1 0x10000000 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) +#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30) + +#endif + +#define CONFIG_JFFS2_NAND 1 +#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ +#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/ + +/* PSRAM */ +#define PHYS_PSRAM 0x70000000 +#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ +/* Slave EBI1, PSRAM connected */ +#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \ + AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \ + AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \ + AT91_MATRIX_SCFG_SLOT_CYCLE(255)) + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#define CONFIG_SYS_USE_FLASH 1 +#undef CONFIG_SYS_USE_DATAFLASH +#undef CONFIG_SYS_USE_NANDFLASH + +#ifdef CONFIG_SYS_USE_DATAFLASH + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x22000000 0x84000 0x294000; " \ + "bootm 0x22000000" + +#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" + +#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */ +/* JFFS Partition offset set */ +#define CONFIG_SYS_JFFS2_FIRST_BANK 0 +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +/* 512k reserved for u-boot */ +#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 + +#define CONFIG_BOOTCOMMAND "run flashboot" +#define CONFIG_ROOTPATH "/ronetix/rootfs" + +#define CONFIG_CON_ROT "fbcon=rotate:3 " + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "partition=nand0,0\0" \ + "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + CONFIG_CON_ROT \ + "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot 0x22000000 vmImage;" \ + "run ramargs;run addip;bootm 22000000\0" \ + "nfsboot=tftpboot 0x22000000 vmImage;" \ + "run nfsargs;run addip;bootm 22000000\0" \ + "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ + "" + +#else +#error "Undefined memory device" +#endif + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ + GENERATED_GBL_DATA_SIZE) + +#endif diff --git a/roms/u-boot/include/configs/pm9g45.h b/roms/u-boot/include/configs/pm9g45.h new file mode 100644 index 000000000..452fbda06 --- /dev/null +++ b/roms/u-boot/include/configs/pm9g45.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Ilko Iliev + * Asen Dimov + * Ronetix GmbH + * + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * Configuation settings for the PM9G45 board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x70000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD3 +#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT +#endif + +/* Ethernet */ +#define CONFIG_RESET_PHY_R +#define CONFIG_AT91_WANTS_COMMON_PHY + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#ifdef CONFIG_NAND_BOOT +/* bootstrap + u-boot + env in nandflash */ + +#define CONFIG_BOOTCOMMAND \ + "nand read 0x70000000 0x200000 0x300000;" \ + "bootm 0x70000000" +#elif CONFIG_SD_BOOT +/* bootstrap + u-boot + env + linux in mmc */ + +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \ + "fatload mmc 0:1 0x72000000 zImage; " \ + "bootz 0x72000000 - 0x71000000" +#endif + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ + 128 * 1024, 0x1000) + +/* Defines for SPL */ +#define CONFIG_SPL_MAX_SIZE 0x010000 +#define CONFIG_SPL_STACK 0x310000 + +#define CONFIG_SYS_MONITOR_LEN 0x80000 + +#ifdef CONFIG_SD_BOOT + +#define CONFIG_SPL_BSS_START_ADDR 0x70000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 +#define CONFIG_SYS_SPL_MALLOC_START 0x70080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 + +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +#elif CONFIG_NAND_BOOT +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } +#endif + +#define CONFIG_SPL_ATMEL_SIZE +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#endif diff --git a/roms/u-boot/include/configs/pogo_e02.h b/roms/u-boot/include/configs/pogo_e02.h new file mode 100644 index 000000000..cbe502229 --- /dev/null +++ b/roms/u-boot/include/configs/pogo_e02.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 + * David Purdy + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + */ + +#ifndef _CONFIG_POGO_E02_H +#define _CONFIG_POGO_E02_H + +/* + * Machine type definition and ID + */ +#define CONFIG_MACH_TYPE MACH_TYPE_POGO_E02 + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +#include "mv-common.h" + +/* + * Environment variables configurations + */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs $(bootargs_console); " \ + "run bootcmd_usb; " \ + "bootm 0x00800000 0x01100000" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage)," \ + "32M(rootfs),-(data)\0"\ + "mtdids=nand0=orion_nand\0"\ + "bootargs_console=console=ttyS0,115200\0" \ + "bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \ + "ext2load usb 0:1 0x01100000 /uInitrd\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 +#endif /* CONFIG_CMD_NET */ + +/* + * File system + */ + +#endif /* _CONFIG_POGO_E02_H */ diff --git a/roms/u-boot/include/configs/poplar.h b/roms/u-boot/include/configs/poplar.h new file mode 100644 index 000000000..9763218ec --- /dev/null +++ b/roms/u-boot/include/configs/poplar.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Linaro + * + * Jorge Ramirez-Ortiz + * + * Configuration for Poplar 96boards CE. Parts were derived from other ARM + * configurations. + */ + +#ifndef _POPLAR_H_ +#define _POPLAR_H_ + +#include + +/* DRAM banks */ + +/* SYS */ +#define CONFIG_SYS_BOOTM_LEN SZ_64M +#define CONFIG_SYS_INIT_SP_ADDR 0x200000 +#define CONFIG_SYS_LOAD_ADDR 0x800000 +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +/* ATF bl33.bin load address (must match) */ + +/* USB configuration */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/***************************************************************************** + * Initial environment variables + *****************************************************************************/ + +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) +#ifndef CONFIG_SPL_BUILD +#include +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loader_mmc_blknum=0x0\0" \ + "loader_mmc_nblks=0x780\0" \ + "env_mmc_blknum=0xf80\0" \ + "env_mmc_nblks=0x80\0" \ + "kernel_addr_r=0x30000000\0" \ + "pxefile_addr_r=0x32000000\0" \ + "scriptaddr=0x32000000\0" \ + "fdt_addr_r=0x32200000\0" \ + "fdtfile=hisilicon/hi3798cv200-poplar.dtb\0" \ + "ramdisk_addr_r=0x32400000\0" \ + BOOTENV + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 64 + +#endif /* _POPLAR_H_ */ diff --git a/roms/u-boot/include/configs/popmetal_rk3288.h b/roms/u-boot/include/configs/popmetal_rk3288.h new file mode 100644 index 000000000..222e5aae7 --- /dev/null +++ b/roms/u-boot/include/configs/popmetal_rk3288.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include + +#endif diff --git a/roms/u-boot/include/configs/porter.h b/roms/u-boot/include/configs/porter.h new file mode 100644 index 000000000..7ffcf5fc3 --- /dev/null +++ b/roms/u-boot/include/configs/porter.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * include/configs/porter.h + * This file is Porter board configuration. + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + */ + +#ifndef __PORTER_H +#define __PORTER_H + +#include "rcar-gen2-common.h" + +#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 +#define STACK_AREA_SIZE 0x00100000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) + +/* FLASH */ +#define CONFIG_SPI_FLASH_QUAD + +/* SH Ether */ +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" + +/* SPL support */ +#define CONFIG_SPL_STACK 0xe6340000 +#define CONFIG_SPL_MAX_SIZE 0x4000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIF0 +#define CONFIG_SH_SCIF_CLK_FREQ 65000000 +#endif + +#endif /* __PORTER_H */ diff --git a/roms/u-boot/include/configs/presidio_asic.h b/roms/u-boot/include/configs/presidio_asic.h new file mode 100644 index 000000000..3f9262128 --- /dev/null +++ b/roms/u-boot/include/configs/presidio_asic.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Cortina Access Inc. + * + * Configuration for Cortina-Access Presidio board + */ + +#ifndef __PRESIDIO_ASIC_H +#define __PRESIDIO_ASIC_H + +#define CONFIG_REMAKE_ELF + +#define CONFIG_SUPPORT_RAW_INITRD + +#define CONFIG_SYS_INIT_SP_ADDR 0x00100000 +#define CONFIG_SYS_BOOTM_LEN 0x00c00000 + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 25000000 +#define CONFIG_SYS_TIMER_RATE COUNTER_FREQUENCY +#define CONFIG_SYS_TIMER_COUNTER 0xf4321008 + +/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE + * does not yet support DT. Thus define it here. + */ +#define CONFIG_GICV2 +#define GICD_BASE 0xf7011000 +#define GICC_BASE 0xf7012000 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) + +#define CONFIG_SYS_TIMER_BASE 0xf4321000 + +/* Use external clock source */ +#define PRESIDIO_APB_CLK 125000000 +#define CORTINA_PER_IO_FREQ PRESIDIO_APB_CLK + +/* Cortina Serial Configuration */ +#define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK) +#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} + +#define CONFIG_SYS_SERIAL0 PER_UART0_CFG +#define CONFIG_SYS_SERIAL1 PER_UART1_CFG + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (DDR_BASE + 0x10000000) +#define CONFIG_LAST_STAGE_INIT + +/* SDRAM Bank #1 */ +#define DDR_BASE 0x00000000 +#define PHYS_SDRAM_1 DDR_BASE +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define KSEG1_ATU_XLAT(x) (x) + +/* HW REG ADDR */ +#define NI_READ_POLL_COUNT 1000 +#define CA_NI_MDIO_REG_BASE 0xF4338 +#define NI_HV_GLB_MAC_ADDR_CFG0_OFFSET 0x010 +#define NI_HV_GLB_MAC_ADDR_CFG1_OFFSET 0x014 +#define NI_HV_PT_BASE 0x400 +#define NI_HV_XRAM_BASE 0x820 +#define GLOBAL_BLOCK_RESET_OFFSET 0x04 +#define GLOBAL_GLOBAL_CONFIG_OFFSET 0x20 +#define GLOBAL_IO_DRIVE_CONTROL_OFFSET 0x4c + +/* max command args */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0" + +/* nand driver parameters */ +#ifdef CONFIG_TARGET_PRESIDIO_ASIC + #define CONFIG_SYS_NAND_ONFI_DETECTION + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_MAX_CHIPS 1 + #define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE + #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#endif + +#endif /* __PRESIDIO_ASIC_H */ diff --git a/roms/u-boot/include/configs/puma_rk3399.h b/roms/u-boot/include/configs/puma_rk3399.h new file mode 100644 index 000000000..f52ea014b --- /dev/null +++ b/roms/u-boot/include/configs/puma_rk3399.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + */ + +#ifndef __PUMA_RK3399_H +#define __PUMA_RK3399_H + +#include + +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_SERIAL_TAG + +#endif diff --git a/roms/u-boot/include/configs/px30_common.h b/roms/u-boot/include/configs/px30_common.h new file mode 100644 index 000000000..76d6ab1c8 --- /dev/null +++ b/roms/u-boot/include/configs/px30_common.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_PX30_COMMON_H +#define __CONFIG_PX30_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020 +#define COUNTER_FREQUENCY 24000000 + +/* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ +#define CONFIG_IRAM_BASE 0xff020000 + +#define CONFIG_SYS_INIT_SP_ADDR 0x00400000 +#define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x20000 +#define CONFIG_SPL_BSS_START_ADDR 0x4000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x4000 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#define GICD_BASE 0xff131000 +#define GICC_BASE 0xff132000 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#define CONFIG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xff000000 +#define SDRAM_BANK_SIZE (2UL << 30) + +#ifndef CONFIG_SPL_BUILD + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x08300000\0" \ + "kernel_addr_r=0x00280000\0" \ + "kernel_addr_c=0x03e80000\0" \ + "ramdisk_addr_r=0x0a200000\0" + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV + +#endif + +#endif diff --git a/roms/u-boot/include/configs/px30_core.h b/roms/u-boot/include/configs/px30_core.h new file mode 100644 index 000000000..01b499559 --- /dev/null +++ b/roms/u-boot/include/configs/px30_core.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#ifndef __PX30_CORE_H +#define __PX30_CORE_H + +#include + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif /* __PX30_CORE_H */ diff --git a/roms/u-boot/include/configs/pxa-common.h b/roms/u-boot/include/configs/pxa-common.h new file mode 100644 index 000000000..52d77e06a --- /dev/null +++ b/roms/u-boot/include/configs/pxa-common.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Toradex Colibri PXA270 configuration file + * + * Copyright (C) 2010 Marek Vasut + */ + +#ifndef __CONFIG_PXA_COMMON_H__ +#define __CONFIG_PXA_COMMON_H__ + +/* + * KGDB + */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 +#endif + +/* + * OHCI USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_BOARD_INIT +#ifdef CONFIG_CPU_PXA27X +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#else +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#endif +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4c000000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "pxa-ohci" +#endif + +#endif /* __CONFIG_PXA_COMMON_H__ */ diff --git a/roms/u-boot/include/configs/pxm2.h b/roms/u-boot/include/configs/pxm2.h new file mode 100644 index 000000000..4673390c1 --- /dev/null +++ b/roms/u-boot/include/configs/pxm2.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * siemens pxm2 + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef __CONFIG_PXM2_H +#define __CONFIG_PXM2_H + +#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_PXM2 + +#include "siemens-am33x-common.h" + +#define DDR_IOCTRL_VAL 0x18b +#define DDR_PLL_FREQ 266 + +#define BOARD_DFU_BUTTON_GPIO 59 +#define BOARD_LCD_POWER 111 +#define BOARD_BACK_LIGHT 112 +#define BOARD_TOUCH_POWER 57 + +#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + "button_dfu0=59\0" \ + "led0=117,0,1\0" \ + + /* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 + +#define CONFIG_FACTORYSET + +#ifndef CONFIG_SPL_BUILD + +/* Use common default */ + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=pxm2\0" \ + "ubi_off=2048\0"\ + "nand_img_size=0x500000\0" \ + "optargs=\0" \ + "preboot=draco_led 0\0" \ + CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + "splashpos=m,m\0" \ + CONFIG_ENV_SETTINGS_V1 \ + CONFIG_ENV_SETTINGS_NAND_V1 \ + "mmc_dev=0\0" \ + "mmc_root=/dev/mmcblk0p2 rw\0" \ + "mmc_root_fs_type=ext4 rootwait\0" \ + "mmc_load_uimage=" \ + "mmc rescan; " \ + "setenv bootfile uImage;" \ + "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \ + "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "mmc_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv bootargs ${bootargs} " \ + "root=${mmc_root} ${mtdparts}" \ + "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \ + "eth=${ethaddr} " \ + "\0" \ + "mmc_boot=run mmc_args; " \ + "run mmc_load_uimage; " \ + "bootm ${kloadaddr}\0" \ + "" + +#ifndef CONFIG_RESTORE_FLASH +/* set to negative value for no autoboot */ + +#define CONFIG_BOOTCOMMAND \ + "if dfubutton; then " \ + "run dfu_start; " \ + "reset; " \ + "fi; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmc_dev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run mmc_load_uimage; then " \ + "run mmc_args;" \ + "bootm ${kloadaddr};" \ + "fi;" \ + "fi;" \ + "run nand_boot;" \ + "reset;" + +#else + +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif +#endif /* CONFIG_SPL_BUILD */ + +#if defined(CONFIG_VIDEO) +#define CONFIG_VIDEO_DA8XX +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE +#define PWM_TICKS 0x1388 +#define PWM_DUTY 0x200 +#endif + +#endif /* ! __CONFIG_PXM2_H */ diff --git a/roms/u-boot/include/configs/qemu-arm.h b/roms/u-boot/include/configs/qemu-arm.h new file mode 100644 index 000000000..273fa1a7d --- /dev/null +++ b/roms/u-boot/include/configs/qemu-arm.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2017 Tuomas Tynkkynen + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* Physical memory map */ + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +/* The DTB generated by QEMU is placed at start of RAM, stay away from there */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) +#define CONFIG_SYS_MALLOC_LEN SZ_16M + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* For timer, QEMU emulates an ARMv7/ARMv8 architected timer */ +#define CONFIG_SYS_HZ 1000 + +/* Environment options */ + +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(SCSI, scsi, 0) \ + func(VIRTIO, virtio, 0) \ + func(DHCP, dhcp, na) + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_addr=0x40000000\0" \ + "scriptaddr=0x40200000\0" \ + "pxefile_addr_r=0x40300000\0" \ + "kernel_addr_r=0x40400000\0" \ + "ramdisk_addr_r=0x44000000\0" \ + BOOTENV + +#define CONFIG_SYS_CBSIZE 512 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* Sector: 256K, Bank: 64M */ +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/qemu-ppce500.h b/roms/u-boot/include/configs/qemu-ppce500.h new file mode 100644 index 000000000..b2e1204e0 --- /dev/null +++ b/roms/u-boot/include/configs/qemu-ppce500.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2011-2014 Freescale Semiconductor, Inc. + */ + +/* + * Corenet DS style board configuration file + */ +#ifndef __QEMU_PPCE500_H +#define __QEMU_PPCE500_H + +#define CONFIG_SYS_MPC85XX_NO_RESETVEC + +#define CONFIG_SYS_RAMBOOT + +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_ENABLE_36BIT_PHYS + +/* Needed to fill the ccsrbar pointer */ + +/* Virtual address to CCSRBAR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +/* Physical address should be a function call */ +#ifndef __ASSEMBLY__ +extern unsigned long long get_phys_ccsrbar_addr_early(void); +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32) +#define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early() +#else +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#endif + +/* Virtual address range for PCI region maps */ +#define CONFIG_SYS_PCI_MAP_START 0x80000000 +#define CONFIG_SYS_PCI_MAP_END 0xe0000000 + +/* Virtual address to a temporary map if we need it (max 128MB) */ +#define CONFIG_SYS_TMPVIRT 0xe8000000 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_CHIP_SELECTS_PER_CTRL 0 + +#define CONFIG_SYS_CLK_FREQ 33000000 + +#define CONFIG_SYS_BOOT_BLOCK 0x00000000 /* boot TLB */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_HWCONFIG + +#define CONFIG_SYS_INIT_RAM_ADDR 0x00100000 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#define CONFIG_LBA48 + +/* RTC */ +#define CONFIG_RTC_PT7C4338 + +/* + * Environment + */ + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTCOMMAND \ + "test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdtcontroladdr\0" + +#endif /* __QEMU_PPCE500_H */ diff --git a/roms/u-boot/include/configs/qemu-riscv.h b/roms/u-boot/include/configs/qemu-riscv.h new file mode 100644 index 000000000..5291de83f --- /dev/null +++ b/roms/u-boot/include/configs/qemu-riscv.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, Bin Meng + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#ifdef CONFIG_SPL + +#define CONFIG_SPL_MAX_SIZE 0x00100000 +#define CONFIG_SPL_BSS_START_ADDR 0x84000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 + +#endif + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +#define CONFIG_SYS_MALLOC_LEN SZ_8M + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 + +#define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMER_FREQ 1000000 + +#define RISCV_SMODE_TIMER_FREQ 1000000 + +/* Environment options */ + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(QEMU, qemu, na) \ + func(VIRTIO, virtio, 0) \ + func(SCSI, scsi, 0) \ + func(DHCP, dhcp, na) + +#include + +#define BOOTENV_DEV_QEMU(devtypeu, devtypel, instance) \ + "bootcmd_qemu=" \ + "if env exists kernel_start; then " \ + "bootm ${kernel_start} - ${fdtcontroladdr};" \ + "fi;\0" + +#define BOOTENV_DEV_NAME_QEMU(devtypeu, devtypel, instance) \ + "qemu " + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ + BOOTENV +#endif + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/qemu-x86.h b/roms/u-boot/include/configs/qemu-x86.h new file mode 100644 index 000000000..52c33600b --- /dev/null +++ b/roms/u-boot/include/configs/qemu-x86.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015, Bin Meng + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(SCSI, scsi, 0) \ + func(VIRTIO, virtio, 0) \ + func(IDE, ide, 0) \ + func(DHCP, dhcp, na) + +#include +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +/* + * ATA/SATA support for QEMU x86 targets + * - Only legacy IDE controller is supported for QEMU '-M pc' target + * - AHCI controller is supported for QEMU '-M q35' target + */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 4 +#define CONFIG_SYS_ATA_BASE_ADDR 0 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 +#define CONFIG_SYS_ATA_ALT_OFFSET 0 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 +#define CONFIG_ATAPI + +#define CONFIG_SPL_BOARD_LOAD_IMAGE + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/r2dplus.h b/roms/u-boot/include/configs/r2dplus.h new file mode 100644 index 000000000..61b6fb484 --- /dev/null +++ b/roms/u-boot/include/configs/r2dplus.h @@ -0,0 +1,59 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_CPU_SH7751 1 +#define __LITTLE_ENDIAN__ 1 + +#define CONFIG_DISPLAY_BOARDINFO + +/* SCIF */ +#define CONFIG_CONS_SCIF1 1 + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x8C000000 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 + +#define CONFIG_SYS_PBSIZE 256 + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) +/* Address of u-boot image in Flash */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +/* Size of DRAM reserved for malloc() use */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) + +/* + * NOR Flash ( Spantion S29GL256P ) + */ +#define CONFIG_SYS_FLASH_BASE (0xA0000000) +#define CONFIG_SYS_MAX_FLASH_BANKS (1) +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * SuperH Clock setting + */ +#define CONFIG_SYS_CLK_FREQ 60000000 +#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ + +/* + * IDE support + */ +#define CONFIG_IDE_RESET 1 +#define CONFIG_SYS_PIO_MODE 1 +#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ +#define CONFIG_SYS_IDE_MAXDEVICE 1 +#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 +#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ +#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ +#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ +#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ +#define CONFIG_IDE_SWAP_IO + +/* + * SuperH PCI Bridge Configration + */ +#define CONFIG_SH7751_PCI + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/rastaban.h b/roms/u-boot/include/configs/rastaban.h new file mode 100644 index 000000000..7f1284448 --- /dev/null +++ b/roms/u-boot/include/configs/rastaban.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef __CONFIG_RASTABAN_H +#define __CONFIG_RASTABAN_H + +#include "siemens-am33x-common.h" + +#define DDR_PLL_FREQ 303 + +/* FWD Button = 27 + * SRV Button = 87 */ +#define BOARD_DFU_BUTTON_GPIO 27 +#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ +/* In dfu mode keep led1 on */ +#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + "button_dfu0=27\0" \ + "button_dfu1=87\0" \ + "led0=3,0,1\0" \ + "led1=4,0,0\0" \ + "led2=5,0,1\0" \ + "led3=62,0,1\0" \ + "led4=60,0,1\0" \ + "led5=63,0,1\0" + + /* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define EEPROM_ADDR_DDR3 0x90 +#define EEPROM_ADDR_CHIP 0x120 + +#define CONFIG_FACTORYSET + +/* Define own nand partitions */ +#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) + +#ifndef CONFIG_SPL_BUILD + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=rastaban\0" \ + "ubi_off=2048\0"\ + "nand_img_size=0x400000\0" \ + "optargs=\0" \ + "preboot=draco_led 0\0" \ + CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + CONFIG_ENV_SETTINGS_V2 \ + CONFIG_ENV_SETTINGS_NAND_V2 + +#ifndef CONFIG_RESTORE_FLASH +/* set to negative value for no autoboot */ + +#define CONFIG_BOOTCOMMAND \ +"if dfubutton; then " \ + "run dfu_start; " \ + "reset; " \ +"fi;" \ +"run nand_boot;" \ +"run nand_boot_backup;" \ +"reset;" + +#else + +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif +#endif /* CONFIG_SPL_BUILD */ +#endif /* ! __CONFIG_RASTABAN_H */ diff --git a/roms/u-boot/include/configs/rcar-gen2-common.h b/roms/u-boot/include/configs/rcar-gen2-common.h new file mode 100644 index 000000000..f94e9d897 --- /dev/null +++ b/roms/u-boot/include/configs/rcar-gen2-common.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * include/configs/rcar-gen2-common.h + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + */ + +#ifndef __RCAR_GEN2_COMMON_H +#define __RCAR_GEN2_COMMON_H + +#include + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#ifdef CONFIG_SPL +#define CONFIG_SPL_TARGET "spl/u-boot-spl.srec" +#endif + +#ifndef CONFIG_PINCTRL_PFC +#define CONFIG_SH_GPIO_PFC +#endif + +/* console */ +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } + +#define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) +#define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) +#define CONFIG_SYS_LOAD_ADDR 0x50000000 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + +/* ENV setting */ + +/* Common ENV setting */ + +/* SF MTD */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#endif + +/* Timer */ +#define CONFIG_TMU_TIMER +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ +#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 8) + +#endif /* __RCAR_GEN2_COMMON_H */ diff --git a/roms/u-boot/include/configs/rcar-gen3-common.h b/roms/u-boot/include/configs/rcar-gen3-common.h new file mode 100644 index 000000000..b9762f5be --- /dev/null +++ b/roms/u-boot/include/configs/rcar-gen3-common.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/rcar-gen3-common.h + * This file is R-Car Gen3 common configuration file. + * + * Copyright (C) 2015-2017 Renesas Electronics Corporation + */ + +#ifndef __RCAR_GEN3_COMMON_H +#define __RCAR_GEN3_COMMON_H + +#include + +#define CONFIG_REMAKE_ELF + +#ifdef CONFIG_SPL +#define CONFIG_SPL_TARGET "spl/u-boot-spl.scif" +#endif + +/* boot option */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* Generic Interrupt Controller Definitions */ +#define CONFIG_GICV2 +#define GICD_BASE 0xF1010000 +#define GICC_BASE 0xF1020000 + +/* console */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 } + +/* PHY needs a longer autoneg timeout */ +#define PHY_ANEG_TIMEOUT 20000 + +/* MEMORY */ +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE + +#define DRAM_RSV_SIZE 0x08000000 +#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) +#define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) +#define CONFIG_SYS_LOAD_ADDR 0x58000000 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_VERY_BIG_RAM +#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN (1 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) + +/* The HF/QSPI layout permits up to 1 MiB large bootloader blob */ +#define CONFIG_BOARD_SIZE_LIMIT 1048576 + +/* ENV setting */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" + +#define CONFIG_BOOTCOMMAND \ + "tftp 0x48080000 Image; " \ + "tftp 0x48000000 Image-"CONFIG_DEFAULT_FDT_FILE"; " \ + "booti 0x48080000 - 0x48000000" + +/* SPL support */ +#if defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796) || defined(CONFIG_R8A77965) +#define CONFIG_SPL_BSS_START_ADDR 0xe633f000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 +#else +#define CONFIG_SPL_BSS_START_ADDR 0xe631f000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 +#endif +#define CONFIG_SPL_STACK 0xe6304000 +#define CONFIG_SPL_MAX_SIZE 0x7000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIF2 +#define CONFIG_SH_SCIF_CLK_FREQ 65000000 +#endif + +#endif /* __RCAR_GEN3_COMMON_H */ diff --git a/roms/u-boot/include/configs/rk3036_common.h b/roms/u-boot/include/configs/rk3036_common.h new file mode 100644 index 000000000..7f148eff8 --- /dev/null +++ b/roms/u-boot/include/configs/rk3036_common.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + */ +#ifndef __CONFIG_RK3036_COMMON_H +#define __CONFIG_RK3036_COMMON_H + +#include +#include "rockchip-common.h" + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 +#define COUNTER_FREQUENCY 24000000 +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ_CLOCK 24000000 + +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +#define CONFIG_SYS_LOAD_ADDR 0x60800800 +#define CONFIG_SPL_STACK 0x10081fff + +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10) +#define CONFIG_ROCKCHIP_CHIP_TAG "RK30" + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define SDRAM_BANK_SIZE (512UL << 20UL) +#define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE) + +#ifndef CONFIG_SPL_BUILD + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60000000\0" \ + "pxefile_addr_r=0x60100000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +#include + +/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board, + * so limit the fdt reallocation to that */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_high=0x7fffffff\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV +#endif + +#endif diff --git a/roms/u-boot/include/configs/rk3128_common.h b/roms/u-boot/include/configs/rk3128_common.h new file mode 100644 index 000000000..7c064a070 --- /dev/null +++ b/roms/u-boot/include/configs/rk3128_common.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_RK3128_COMMON_H +#define __CONFIG_RK3128_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 +#define COUNTER_FREQUENCY 24000000 +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ_CLOCK 24000000 + +#define CONFIG_IRAM_BASE 0x10080000 + +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +#define CONFIG_SYS_LOAD_ADDR 0x60800800 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +/* RAW SD card / eMMC locations. */ + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define SDRAM_MAX_SIZE 0x80000000 + +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 + +#ifndef CONFIG_SPL_BUILD + +/* usb mass storage */ + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60500000\0" \ + "pxefile_addr_r=0x60600000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + BOOTENV + +#endif + +#endif diff --git a/roms/u-boot/include/configs/rk3188_common.h b/roms/u-boot/include/configs/rk3188_common.h new file mode 100644 index 000000000..3bcc04808 --- /dev/null +++ b/roms/u-boot/include/configs/rk3188_common.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef __CONFIG_RK3188_COMMON_H +#define __CONFIG_RK3188_COMMON_H + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#include +#include "rockchip-common.h" + +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#define CONFIG_SYS_CBSIZE 1024 + +#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM +/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ +#endif +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +#define CONFIG_SYS_LOAD_ADDR 0x60800800 + +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800) +#define CONFIG_ROCKCHIP_CHIP_TAG "RK31" +#define CONFIG_IRAM_BASE 0x10080000 + +/* spl size 32kb sram - 2kb bootrom */ +#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800) +#define CONFIG_ROCKCHIP_SERIAL 1 + +#define CONFIG_SPL_STACK 0x10087fff + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define SDRAM_BANK_SIZE (2UL << 30) +#define SDRAM_MAX_SIZE 0x80000000 + +#ifndef CONFIG_SPL_BUILD +/* usb otg */ + +/* usb host support */ +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60000000\0" \ + "pxefile_addr_r=0x60100000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +#include + +/* Linux fails to load the fdt if it's loaded above 256M on a Rock board, + * so limit the fdt reallocation to that */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_high=0x6fffffff\0" \ + "initrd_high=0x6fffffff\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV + +#endif /* CONFIG_SPL_BUILD */ + +#endif diff --git a/roms/u-boot/include/configs/rk322x_common.h b/roms/u-boot/include/configs/rk322x_common.h new file mode 100644 index 000000000..7e0c83117 --- /dev/null +++ b/roms/u-boot/include/configs/rk322x_common.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ +#ifndef __CONFIG_RK322X_COMMON_H +#define __CONFIG_RK322X_COMMON_H + +#include +#include "rockchip-common.h" + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#define CONFIG_ROCKCHIP_STIMER_BASE 0x110d0020 +#define COUNTER_FREQUENCY 24000000 +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ_CLOCK 24000000 + +#define CONFIG_SYS_INIT_SP_ADDR 0x61100000 +#define CONFIG_SYS_LOAD_ADDR 0x61800800 +#define CONFIG_SPL_MAX_SIZE 0x100000 + +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10) +#define CONFIG_ROCKCHIP_CHIP_TAG "RK32" +#define CONFIG_IRAM_BASE 0x10080000 + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define SDRAM_BANK_SIZE (512UL << 20UL) +#define SDRAM_MAX_SIZE 0x80000000 + +#ifndef CONFIG_SPL_BUILD + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60000000\0" \ + "pxefile_addr_r=0x60100000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +#include + +/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board, + * so limit the fdt reallocation to that */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_high=0x7fffffff\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV +#endif + +#endif diff --git a/roms/u-boot/include/configs/rk3288_common.h b/roms/u-boot/include/configs/rk3288_common.h new file mode 100644 index 000000000..addad7a16 --- /dev/null +++ b/roms/u-boot/include/configs/rk3288_common.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef __CONFIG_RK3288_COMMON_H +#define __CONFIG_RK3288_COMMON_H + +#include +#include "rockchip-common.h" + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64MB */ + +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#define CONFIG_SYS_CBSIZE 1024 + +#define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020 +#define COUNTER_FREQUENCY 24000000 +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ_CLOCK 24000000 + +#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM +/* Bootrom will load u-boot binary to 0x0 once return from SPL */ +#endif +#define CONFIG_SYS_INIT_SP_ADDR 0x00100000 +#define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0xff718000 + +#define CONFIG_IRAM_BASE 0xff700000 + +/* RAW SD card / eMMC locations. */ + +/* FAT sd card locations. */ +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SYS_SDRAM_BASE 0 +#define SDRAM_BANK_SIZE (2UL << 30) +#define SDRAM_MAX_SIZE 0xfe000000 + +#define CONFIG_SYS_MONITOR_LEN (600 * 1024) + +#ifndef CONFIG_SPL_BUILD + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00000000\0" \ + "pxefile_addr_r=0x00100000\0" \ + "fdt_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x04000000\0" + +#include + +/* Linux fails to load the fdt if it's loaded above 256M on a Rock 2 board, so + * limit the fdt reallocation to that */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x0fffffff\0" \ + "initrd_high=0x0fffffff\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV +#endif + +#endif diff --git a/roms/u-boot/include/configs/rk3308_common.h b/roms/u-boot/include/configs/rk3308_common.h new file mode 100644 index 000000000..bd9ac826f --- /dev/null +++ b/roms/u-boot/include/configs/rk3308_common.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_RK3308_COMMON_H +#define __CONFIG_RK3308_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) +#define CONFIG_SPL_MAX_SIZE 0x20000 +#define CONFIG_SPL_BSS_START_ADDR 0x00400000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0 +#define CONFIG_IRAM_BASE 0xfff80000 +#define CONFIG_SYS_INIT_SP_ADDR 0x00800000 +#define CONFIG_SYS_LOAD_ADDR 0x00C00800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#define COUNTER_FREQUENCY 24000000 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#define CONFIG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xff000000 +#define SDRAM_BANK_SIZE (2UL << 30) + +#ifndef CONFIG_SPL_BUILD + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x02800000\0" \ + "kernel_addr_r=0x00680000\0" \ + "ramdisk_addr_r=0x04000000\0" + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "partitions=" PARTS_DEFAULT \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV + +#endif + +#endif diff --git a/roms/u-boot/include/configs/rk3328_common.h b/roms/u-boot/include/configs/rk3328_common.h new file mode 100644 index 000000000..0538da751 --- /dev/null +++ b/roms/u-boot/include/configs/rk3328_common.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_RK3328_COMMON_H +#define __CONFIG_RK3328_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_IRAM_BASE 0xff090000 + +#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020 +#define COUNTER_FREQUENCY 24000000 + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +#define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x40000 +#define CONFIG_SPL_BSS_START_ADDR 0x2000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +/* FAT sd card locations. */ +#define CONFIG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xff000000 + +#ifndef CONFIG_SPL_BUILD + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x02080000\0" \ + "ramdisk_addr_r=0x06000000\0" + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + BOOTENV + +#endif + +/* rockchip ohci host driver */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 + +#endif diff --git a/roms/u-boot/include/configs/rk3368_common.h b/roms/u-boot/include/configs/rk3368_common.h new file mode 100644 index 000000000..fbbb8cf26 --- /dev/null +++ b/roms/u-boot/include/configs/rk3368_common.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2016 Andreas Färber + */ + +#ifndef __CONFIG_RK3368_COMMON_H +#define __CONFIG_RK3368_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#include +#include + +#define CONFIG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xff000000 +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020 +#define COUNTER_FREQUENCY 24000000 + +#define CONFIG_IRAM_BASE 0xff8c0000 + +#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +#define CONFIG_SYS_LOAD_ADDR 0x00800800 + +#define CONFIG_SPL_MAX_SIZE 0x40000 +#define CONFIG_SPL_BSS_START_ADDR 0x400000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x20000 +#define CONFIG_SPL_STACK 0x00188000 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#ifndef CONFIG_SPL_BUILD +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x5600000\0" \ + "kernel_addr_r=0x280000\0" \ + "ramdisk_addr_r=0x5bf0000\0" + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV + +#endif + +#endif diff --git a/roms/u-boot/include/configs/rk3399_common.h b/roms/u-boot/include/configs/rk3399_common.h new file mode 100644 index 000000000..b37ed5cce --- /dev/null +++ b/roms/u-boot/include/configs/rk3399_common.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_RK3399_COMMON_H +#define __CONFIG_RK3399_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define COUNTER_FREQUENCY 24000000 +#define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0 + +#define CONFIG_IRAM_BASE 0xff8c0000 + +#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +#define CONFIG_SYS_LOAD_ADDR 0x00800800 + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x40000 +#define CONFIG_SPL_BSS_START_ADDR 0x00400000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 +#else +#define CONFIG_SPL_STACK 0xff8effff +#define CONFIG_SPL_MAX_SIZE 0x30000 - 0x2000 +/* BSS setup */ +#define CONFIG_SPL_BSS_START_ADDR 0xff8e0000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 +#endif + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +/* MMC/SD IP block */ +#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000 + +/* RAW SD card / eMMC locations. */ + +/* FAT sd card locations. */ +#define CONFIG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xf8000000 + +#ifndef CONFIG_SPL_BUILD + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x02080000\0" \ + "ramdisk_addr_r=0x06000000\0" \ + "kernel_comp_addr_r=0x08000000\0" \ + "kernel_comp_size=0x2000000\0" + +#ifndef ROCKCHIP_DEVICE_SETTINGS +#define ROCKCHIP_DEVICE_SETTINGS +#endif + +#include +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV \ + BOOTENV_SF \ + "altbootcmd=" \ + "setenv boot_syslinux_conf extlinux/extlinux-rollback.conf;" \ + "run distro_bootcmd\0" + +#endif + +#endif diff --git a/roms/u-boot/include/configs/roc-pc-rk3399.h b/roms/u-boot/include/configs/roc-pc-rk3399.h new file mode 100644 index 000000000..59fe22289 --- /dev/null +++ b/roms/u-boot/include/configs/roc-pc-rk3399.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __ROC_PC_RK3399_H +#define __ROC_PC_RK3399_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#define SDRAM_BANK_SIZE (2UL << 30) + +#endif diff --git a/roms/u-boot/include/configs/rock.h b/roms/u-boot/include/configs/rock.h new file mode 100644 index 000000000..96aefc194 --- /dev/null +++ b/roms/u-boot/include/configs/rock.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include + +#endif diff --git a/roms/u-boot/include/configs/rock2.h b/roms/u-boot/include/configs/rock2.h new file mode 100644 index 000000000..df96c3295 --- /dev/null +++ b/roms/u-boot/include/configs/rock2.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#endif diff --git a/roms/u-boot/include/configs/rock960_rk3399.h b/roms/u-boot/include/configs/rock960_rk3399.h new file mode 100644 index 000000000..2edad7102 --- /dev/null +++ b/roms/u-boot/include/configs/rock960_rk3399.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +#ifndef __ROCK960_RK3399_H +#define __ROCK960_RK3399_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#endif diff --git a/roms/u-boot/include/configs/rockchip-common.h b/roms/u-boot/include/configs/rockchip-common.h new file mode 100644 index 000000000..0b9e24d1d --- /dev/null +++ b/roms/u-boot/include/configs/rockchip-common.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef _ROCKCHIP_COMMON_H_ +#define _ROCKCHIP_COMMON_H_ +#include + +#define CONFIG_SYS_NS16550_MEM32 + +/* ((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512) */ +#define CONFIG_SPL_PAD_TO 8355840 + +#ifndef CONFIG_SPL_BUILD + +/* First try to boot from SD (index 0), then eMMC (index 1) */ +#if CONFIG_IS_ENABLED(CMD_MMC) + #define BOOT_TARGET_MMC(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) +#else + #define BOOT_TARGET_MMC(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_NVME) + #define BOOT_TARGET_NVME(func) func(NVME, nvme, 0) +#else + #define BOOT_TARGET_NVME(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_USB) + #define BOOT_TARGET_USB(func) func(USB, usb, 0) +#else + #define BOOT_TARGET_USB(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_PXE) + #define BOOT_TARGET_PXE(func) func(PXE, pxe, na) +#else + #define BOOT_TARGET_PXE(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_DHCP) + #define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) +#else + #define BOOT_TARGET_DHCP(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_SF) + #define BOOT_TARGET_SF(func) func(SF, sf, 0) +#else + #define BOOT_TARGET_SF(func) +#endif + +#ifdef CONFIG_ROCKCHIP_RK3399 +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_MMC(func) \ + BOOT_TARGET_NVME(func) \ + BOOT_TARGET_USB(func) \ + BOOT_TARGET_PXE(func) \ + BOOT_TARGET_DHCP(func) \ + BOOT_TARGET_SF(func) +#else +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_MMC(func) \ + BOOT_TARGET_USB(func) \ + BOOT_TARGET_PXE(func) \ + BOOT_TARGET_DHCP(func) +#endif + +#ifdef CONFIG_ARM64 +#define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0" +#else +#define ROOT_UUID "69DAD710-2CE4-4E3C-B16C-21A1D49ABED3;\0" +#endif +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=loader1,start=32K,size=4000K,uuid=${uuid_gpt_loader1};" \ + "name=loader2,start=8MB,size=4MB,uuid=${uuid_gpt_loader2};" \ + "name=trust,size=4M,uuid=${uuid_gpt_atf};" \ + "name=boot,size=112M,bootable,uuid=${uuid_gpt_boot};" \ + "name=rootfs,size=-,uuid="ROOT_UUID + +#endif + +#endif /* _ROCKCHIP_COMMON_H_ */ diff --git a/roms/u-boot/include/configs/rockpro64_rk3399.h b/roms/u-boot/include/configs/rockpro64_rk3399.h new file mode 100644 index 000000000..903e9df52 --- /dev/null +++ b/roms/u-boot/include/configs/rockpro64_rk3399.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Vasily Khoruzhick + */ + +#ifndef __ROCKPRO64_RK3399_H +#define __ROCKPRO64_RK3399_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#endif diff --git a/roms/u-boot/include/configs/rpi.h b/roms/u-boot/include/configs/rpi.h new file mode 100644 index 000000000..834f1cd23 --- /dev/null +++ b/roms/u-boot/include/configs/rpi.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2012-2016 Stephen Warren + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +#ifndef __ASSEMBLY__ +#include +#endif + +#if defined(CONFIG_TARGET_RPI_2) || defined(CONFIG_TARGET_RPI_3_32B) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* Architecture, CPU, etc.*/ + +/* Use SoC timer for AArch32, but architected timer for AArch64 */ +#ifndef CONFIG_ARM64 +#define CONFIG_SYS_TIMER_RATE 1000000 +#define CONFIG_SYS_TIMER_COUNTER \ + (&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo) +#endif + +/* + * 2835 is a SKU in a series for which the 2708 is the first or primary SoC, + * so 2708 has historically been used rather than a dedicated 2835 ID. + * + * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation + * chose to use someone else's previously registered machine ID (3139, MX51_GGC) + * rather than obtaining a valid ID:-/ + * + * For the bcm2837, hopefully a machine type is not needed, since everything + * is DT. + */ +#ifdef CONFIG_BCM2835 +#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708 +#endif + +/* Memory layout */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE +/* + * The board really has 256M. However, the VC (VideoCore co-processor) shares + * the RAM, and uses a configurable portion at the top. We tell U-Boot that a + * smaller amount of RAM is present in order to avoid stomping on the area + * the VC uses. + */ +#define CONFIG_SYS_SDRAM_SIZE SZ_128M +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_MALLOC_LEN SZ_4M +#define CONFIG_LOADADDR 0x00200000 + +#ifdef CONFIG_ARM64 +#define CONFIG_SYS_BOOTM_LEN SZ_64M +#endif + +/* Devices */ +/* GPIO */ +#define CONFIG_BCM2835_GPIO +/* LCD */ +#define CONFIG_LCD_DT_SIMPLEFB +#define CONFIG_VIDEO_BCM2835 + +#ifdef CONFIG_CMD_USB +#define CONFIG_TFTP_TSIZE +#endif + +/* DFU over USB/UDC */ +#ifdef CONFIG_CMD_DFU +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M +#define CONFIG_SYS_DFU_MAX_FILE_SIZE SZ_2M + +#ifdef CONFIG_ARM64 +#define KERNEL_FILENAME "Image" +#else +#define KERNEL_FILENAME "zImage" +#endif + +#define ENV_DFU_SETTINGS \ + "dfu_alt_info=u-boot.bin fat 0 1;uboot.env fat 0 1;" \ + "config.txt fat 0 1;" \ + KERNEL_FILENAME " fat 0 1\0" +#else +#define ENV_DFU_SETTINGS "" +#endif + +/* Console configuration */ +#define CONFIG_SYS_CBSIZE 1024 + +/* Environment */ +#define CONFIG_SYS_LOAD_ADDR 0x1000000 + +/* Shell */ + +/* ATAGs support for bootm/bootz */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG + +/* Environment */ +#define ENV_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#ifdef CONFIG_ARM64 +#define FDT_HIGH "ffffffffffffffff" +#define INITRD_HIGH "ffffffffffffffff" +#else +#define FDT_HIGH "ffffffff" +#define INITRD_HIGH "ffffffff" +#endif + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * I suspect address 0 is used as the SMP pen on the RPi2, so avoid this. + * + * Older versions of the boot firmware place the firmware-loaded DTB at 0x100, + * newer versions place it in high memory. So prevent U-Boot from doing its own + * DTB + initrd relocation so that we won't accidentally relocate the initrd + * over the firmware-loaded DTB and generally try to lay out things starting + * from the bottom of RAM. + * + * kernel_addr_r has different constraints on ARM and Aarch64. For 32-bit ARM, + * it must be within the first 128M of RAM in order for the kernel's + * CONFIG_AUTO_ZRELADDR option to work. The kernel itself will be decompressed + * to 0x8000 but the decompressor clobbers 0x4000-0x8000 as well. The + * decompressor also likes to relocate itself to right past the end of the + * decompressed kernel, so in total the sum of the compressed and and + * decompressed kernel needs to be reserved. + * + * For Aarch64, the kernel image is uncompressed and must be loaded at + * text_offset bytes (specified in the header of the Image) into a 2MB + * boundary. The 'booti' command relocates the image if necessary. Linux uses + * a default text_offset of 0x80000. In summary, loading at 0x80000 + * satisfies all these constraints and reserving memory up to 0x02400000 + * permits fairly large (roughly 36M) kernels. + * + * scriptaddr and pxefile_addr_r can be pretty much anywhere that doesn't + * conflict with something else. Reserving 1M for each of them at + * 0x02400000-0x02500000 and 0x02500000-0x02600000 should be plenty. + * + * On ARM, both the DTB and any possible initrd must be loaded such that they + * fit inside the lowmem mapping in Linux. In practice, this usually means not + * more than ~700M away from the start of the kernel image but this number can + * be larger OR smaller depending on e.g. the 'vmalloc=xxxM' command line + * parameter given to the kernel. So reserving memory from low to high + * satisfies this constraint again. Reserving 1M at 0x02600000-0x02700000 for + * the DTB leaves rest of the free RAM to the initrd starting at 0x02700000. + * Even with the smallest possible CPU-GPU memory split of the CPU getting + * only 64M, the remaining 25M starting at 0x02700000 should allow quite + * large initrds before they start colliding with U-Boot. + */ +#define ENV_MEM_LAYOUT_SETTINGS \ + "fdt_high=" FDT_HIGH "\0" \ + "initrd_high=" INITRD_HIGH "\0" \ + "kernel_addr_r=0x00080000\0" \ + "scriptaddr=0x02400000\0" \ + "pxefile_addr_r=0x02500000\0" \ + "fdt_addr_r=0x02600000\0" \ + "ramdisk_addr_r=0x02700000\0" + +#if CONFIG_IS_ENABLED(CMD_MMC) + #define BOOT_TARGET_MMC(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) +#else + #define BOOT_TARGET_MMC(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_USB) + #define BOOT_TARGET_USB(func) func(USB, usb, 0) +#else + #define BOOT_TARGET_USB(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_PXE) + #define BOOT_TARGET_PXE(func) func(PXE, pxe, na) +#else + #define BOOT_TARGET_PXE(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_DHCP) + #define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) +#else + #define BOOT_TARGET_DHCP(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_MMC(func) \ + BOOT_TARGET_USB(func) \ + BOOT_TARGET_PXE(func) \ + BOOT_TARGET_DHCP(func) + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "dhcpuboot=usb start; dhcp u-boot.uimg; bootm\0" \ + ENV_DEVICE_SETTINGS \ + ENV_DFU_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV + + +#endif diff --git a/roms/u-boot/include/configs/rut.h b/roms/u-boot/include/configs/rut.h new file mode 100644 index 000000000..66940033a --- /dev/null +++ b/roms/u-boot/include/configs/rut.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * siemens rut + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef __CONFIG_RUT_H +#define __CONFIG_RUT_H + +#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT + +#include "siemens-am33x-common.h" + +#define RUT_IOCTRL_VAL 0x18b +#define DDR_PLL_FREQ 303 + + /* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ + +#define CONFIG_FACTORYSET + +/* Watchdog */ +#define WATCHDOG_TRIGGER_GPIO 14 + +#ifndef CONFIG_SPL_BUILD + +/* Use common default */ + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=rut\0" \ + "ubi_off=2048\0"\ + "nand_img_size=0x500000\0" \ + "splashpos=m,m\0" \ + "optargs=fixrtc --no-log consoleblank=0 \0" \ + CONFIG_ENV_SETTINGS_V1 \ + CONFIG_ENV_SETTINGS_NAND_V1 \ + "mmc_dev=0\0" \ + "mmc_root=/dev/mmcblk0p2 rw\0" \ + "mmc_root_fs_type=ext4 rootwait\0" \ + "mmc_load_uimage=" \ + "mmc rescan; " \ + "setenv bootfile uImage;" \ + "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \ + "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "mmc_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv bootargs ${bootargs} " \ + "root=${mmc_root} ${mtdparts}" \ + "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \ + "eth=${ethaddr} " \ + "\0" \ + "mmc_boot=run mmc_args; " \ + "run mmc_load_uimage; " \ + "bootm ${kloadaddr}\0" \ + "" + +#ifndef CONFIG_RESTORE_FLASH +/* set to negative value for no autoboot */ + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmc_dev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run mmc_load_uimage; then " \ + "run mmc_args;" \ + "bootm ${kloadaddr};" \ + "fi;" \ + "fi;" \ + "run nand_boot;" \ + "reset;" + +#else + +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif + +#endif /* CONFIG_SPL_BUILD */ + +#if defined(CONFIG_VIDEO) +#define CONFIG_VIDEO_DA8XX +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE + +#define BOARD_LCD_RESET 115 /* Bank 3 pin 19 */ +#define CONFIG_FORMIKE +#define DISPL_PLL_SPREAD_SPECTRUM +#endif + +#endif /* ! __CONFIG_RUT_H */ diff --git a/roms/u-boot/include/configs/rv1108_common.h b/roms/u-boot/include/configs/rv1108_common.h new file mode 100644 index 000000000..758e85e89 --- /dev/null +++ b/roms/u-boot/include/configs/rv1108_common.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ +#ifndef __CONFIG_RV1108_COMMON_H +#define __CONFIG_RV1108_COMMON_H + +#include +#include "rockchip-common.h" + +#define CONFIG_IRAM_BASE 0x10080000 + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +/* TIMER1,initialized by ddr initialize code */ +#define CONFIG_SYS_TIMER_BASE 0x10350020 +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000) + +/* rockchip ohci host driver */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#endif + +#ifndef CONFIG_SPL_BUILD +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60000000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + BOOTENV +#endif diff --git a/roms/u-boot/include/configs/s5p4418_nanopi2.h b/roms/u-boot/include/configs/s5p4418_nanopi2.h new file mode 100644 index 000000000..1e2180b97 --- /dev/null +++ b/roms/u-boot/include/configs/s5p4418_nanopi2.h @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) Guangzhou FriendlyARM Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * (C) Copyright 2016 Nexell + * Hyejung Kwon + * + * Copyright (C) 2019 Stefan Bosch + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +#include +#include + +/*----------------------------------------------------------------------- + * System memory Configuration + */ +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MEM_SIZE 0x40000000 +#define CONFIG_SYS_SDRAM_BASE 0x71000000 + +/* + * "(CONFIG_SYS_MEM_SIZE - CONFIG_SYS_RESERVE_MEM_SIZE)" has been used in + * u-boot nanopi2-v2016.01. + * This is not working anymore because boot_fdt_add_mem_rsv_regions() in + * common/image-fdt.c has been extended: + * Also reserved-memory sections are marked as unusable. + * + * In friendlyArm Ubuntu 16.04 source arch/arm/boot/dts/s5p4418.dtsi: + * reserved-memory { + * #address-cells = <1>; + * #size-cells = <1>; + * ranges; + * + * secure_memory@b0000000 { + * reg = <0xB0000000 0x1000000>; + * nop-map; + * }; + * }; + * + * arch_lmb_reserve() of arch/arm/lib/bootm.c: + * "Allocate space for command line and board info - ... below the current + * stack pointer." + * --> Memory allocated would overlap with "secure_memory@b0000000" + * --> lmb_add_region(rgn, base==0xb0000000, size==0x1000000) fails, + * boot output: + * ... + * Kernel image @ 0x71080000 [ 0x000000 - 0x60e628 ] + * ## Flattened Device Tree blob at 7a000000 + * Booting using the fdt blob at 0x7a000000 + * ERROR: reserving fdt memory region failed (addr=b0000000 size=1000000) + * Using Device Tree in place at 7a000000, end 7a00fbf0 + * + * Starting kernel ... + * ... + */ +#define CONFIG_SYS_SDRAM_SIZE (0xb0000000 - CONFIG_SYS_SDRAM_BASE) + +#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) + +#define BMP_LOAD_ADDR 0x78000000 + +/* kernel load address */ +#define CONFIG_SYS_LOAD_ADDR 0x71080000 +#define INITRD_START 0x79000000 +#define KERNEL_DTB_ADDR 0x7A000000 + +/*----------------------------------------------------------------------- + * High Level System Configuration + */ +/* Not used: not need IRQ/FIQ stuff */ +#undef CONFIG_USE_IRQ +/* decrementer freq: 1ms ticks */ +#define CONFIG_SYS_HZ 1000 + +/*----------------------------------------------------------------------- + * System initialize options (board_init_f) + */ +/* board_init_f->init_sequence, call arch_cpu_init */ +#define CONFIG_ARCH_CPU_INIT + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#ifdef CONFIG_SYS_PROMPT +#undef CONFIG_SYS_PROMPT +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "nanopi2# " +#endif + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/*----------------------------------------------------------------------- + * Etc Command definition + */ +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_RTEMS + +/*----------------------------------------------------------------------- + * serial console configuration + */ +#define CONFIG_PL011_CLOCK 50000000 +#define CONFIG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \ + (void *)PHY_BASEADDR_UART1, \ + (void *)PHY_BASEADDR_UART2, \ + (void *)PHY_BASEADDR_UART3} +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * PLL + */ +#define CONFIG_SYS_PLLFIN 24000000UL + +/*----------------------------------------------------------------------- + * Timer + */ +#define CONFIG_TIMER_SYS_TICK_CH 0 + +/*----------------------------------------------------------------------- + * BACKLIGHT + */ +#ifndef CONFIG_S5P4418_ONEWIRE +#ifdef CONFIG_PWM_NX +/* fallback to pwm */ +#define BACKLIGHT_CH 0 +#define BACKLIGHT_DIV 0 +#define BACKLIGHT_INV 0 +#define BACKLIGHT_DUTY 50 +#define BACKLIGHT_HZ 1000 +#endif +#endif + +/*----------------------------------------------------------------------- + * VIDEO + */ + +#define CONFIG_VIDEO_LOGO + +#ifdef CONFIG_VIDEO_LOGO +#ifdef CONFIG_SPLASH_SCREEN +#define SPLASH_FILE logo.bmp +#endif + +#endif + +/*----------------------------------------------------------------------- + * ENV + */ +#define BLOADER_MMC \ + "ext4load mmc ${rootdev}:${bootpart} " + +#ifdef CONFIG_OF_BOARD_SETUP +#define EXTRA_ENV_DTB_RESERVE \ + "dtb_reserve=" \ + "if test -n \"$dtb_addr\"; then fdt addr $dtb_addr; fi\0" +#else +#define EXTRA_ENV_DTB_RESERVE \ + "dtb_reserve=" \ + "if test -n \"$fb_addr\"; then " \ + "fdt addr $dtb_addr;" \ + "fdt resize;" \ + "fdt mk /reserved-memory display_reserved;" \ + "fdt set /reserved-memory/display_reserved " \ + "reg <$fb_addr 0x800000>;" \ + "fi;\0" +#endif + +#ifdef CONFIG_SPLASH_SCREEN +#define EXTRA_ENV_BOOT_LOGO \ + "splashimage=" __stringify(BMP_LOAD_ADDR)"\0" \ + "splashfile=" __stringify(SPLASH_FILE)"\0" \ + "splashpos=m,m\0" \ + "fb_addr=\0" \ + EXTRA_ENV_DTB_RESERVE +#else + #define EXTRA_ENV_BOOT_LOGO EXTRA_ENV_DTB_RESERVE +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "rootdev=" __stringify(CONFIG_ROOT_DEV) "\0" \ + "rootpart=" __stringify(CONFIG_ROOT_PART) "\0" \ + "bootpart=" __stringify(CONFIG_BOOT_PART) "\0" \ + "kernel=zImage\0" \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "dtb_name=s5p4418-nanopi2-rev01.dtb\0" \ + "dtb_addr=" __stringify(KERNEL_DTB_ADDR) "\0" \ + "initrd_name=ramdisk.img\0" \ + "initrd_addr=" __stringify(INITRD_START) "\0" \ + "initrd_size=0x600000\0" \ + "load_dtb=" \ + BLOADER_MMC "${dtb_addr} ${dtb_name}; " \ + "run dtb_reserve\0" \ + "load_kernel=" \ + BLOADER_MMC "${loadaddr} ${kernel}\0" \ + "load_initrd=" \ + BLOADER_MMC "${initrd_addr} ${initrd_name}; " \ + "setenv initrd_size 0x${filesize}\0" \ + "mmcboot=" \ + "run load_kernel; run load_initrd; run load_dtb; " \ + "bootz ${loadaddr} ${initrd_addr}:${initrd_size} " \ + "${dtb_addr}\0" \ + "bootcmd=run mmcboot\0" \ + EXTRA_ENV_BOOT_LOGO + +#endif /* __CONFIG_H__ */ diff --git a/roms/u-boot/include/configs/s5p_goni.h b/roms/u-boot/include/configs/s5p_goni.h new file mode 100644 index 000000000..9688bdc4c --- /dev/null +++ b/roms/u-boot/include/configs/s5p_goni.h @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang + * Kyungmin Park + * + * Configuation settings for the SAMSUNG Universal (s5pc100) board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ +#define CONFIG_S5P 1 /* which is in a S5P Family */ +#define CONFIG_S5PC110 1 /* which is in a S5PC110 */ + +#include +#include /* get chip and board defs */ + +/* input clock of PLL: has 24MHz input clock at S5PC110 */ +#define CONFIG_SYS_CLK_FREQ_C110 24000000 + +/* DRAM Base */ +#define CONFIG_SYS_SDRAM_BASE 0x30000000 + +/* Text Base */ + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_INITRD_TAG + +/* Size of malloc() pool before and after relocation */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) + +/* MMC */ +#define SDHCI_MAX_HOSTS 4 + +/* PWM */ +#define CONFIG_PWM 1 + +/* USB Composite download gadget - g_dnl */ +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* USB Samsung's IDs */ + +#define CONFIG_G_DNL_THOR_VENDOR_NUM 0x04E8 +#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D +#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 + +/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ + +/* partitions definitions */ +#define PARTS_CSA "csa-mmc" +#define PARTS_BOOTLOADER "u-boot" +#define PARTS_BOOT "boot" +#define PARTS_ROOT "platform" +#define PARTS_DATA "data" +#define PARTS_CSC "csc" +#define PARTS_UMS "ums" + +#define CONFIG_DFU_ALT \ + "u-boot raw 0x80 0x400;" \ + "uImage ext4 0 2;" \ + "exynos3-goni.dtb ext4 0 2;" \ + ""PARTS_ROOT" part 0 5\0" + +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ + "name="PARTS_BOOTLOADER",size=60MiB," \ + "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \ + "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ + "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ + "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ + "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ + "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ + +#define CONFIG_BOOTCOMMAND "run mmcboot" + +#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext4" \ + " ${console} ${meminfo}" + +#define CONFIG_COMMON_BOOT "${console} ${meminfo} ${mtdparts}" + +#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x100000;" \ + " onenand write 0x32008000 0x0 0x100000\0" + +#define CONFIG_MISC_COMMON + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_UPDATEB \ + "updatek=" \ + "onenand erase 0xc00000 0x600000;" \ + "onenand write 0x31008000 0xc00000 0x600000\0" \ + "updateu=" \ + "onenand erase 0x01560000 0x1eaa0000;" \ + "onenand write 0x32000000 0x1260000 0x8C0000\0" \ + "bootk=" \ + "run loaduimage;" \ + "bootm 0x30007FC0\0" \ + "flashboot=" \ + "set bootargs root=/dev/mtdblock${bootblock} " \ + "rootfstype=${rootfstype} ${opts} " \ + "${lcdinfo} " CONFIG_COMMON_BOOT "; run bootk\0" \ + "ubifsboot=" \ + "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ + "${opts} ${lcdinfo} " \ + CONFIG_COMMON_BOOT "; run bootk\0" \ + "tftpboot=" \ + "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ + "${opts} ${lcdinfo} " CONFIG_COMMON_BOOT \ + "; tftp 0x30007FC0 uImage; bootm 0x30007FC0\0" \ + "ramboot=" \ + "set bootargs " CONFIG_RAMDISK_BOOT \ + "initrd=0x33000000,8M ramdisk=8192\0" \ + "mmcboot=" \ + "set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ + "rootfstype=${rootfstype} ${opts} ${lcdinfo} " \ + CONFIG_COMMON_BOOT "; run bootk\0" \ + "boottrace=setenv opts initcall_debug; run bootcmd\0" \ + "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ + "verify=n\0" \ + "rootfstype=ext4\0" \ + "console=console=ttySAC2,115200n8\0" \ + "meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \ + "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x30007FC0 uImage\0" \ + "mmcdev=0\0" \ + "mmcbootpart=2\0" \ + "mmcrootpart=5\0" \ + "partitions=" PARTS_DEFAULT \ + "bootblock=9\0" \ + "ubiblock=8\0" \ + "ubi=enabled\0" \ + "opts=always_resume=1\0" \ + "dfu_alt_info=" CONFIG_DFU_ALT "\0" + +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +/* memtest works on */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000) + +/* Goni has 3 banks of DRAM, but swap the bank */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ +#define PHYS_SDRAM_1_SIZE (80 << 20) /* 80 MB in Bank #0 */ +#define PHYS_SDRAM_2 0x40000000 /* mDDR DMC1 Bank #1 */ +#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in Bank #1 */ +#define PHYS_SDRAM_3 0x50000000 /* mDDR DMC2 Bank #2 */ +#define PHYS_SDRAM_3_SIZE (128 << 20) /* 128 MB in Bank #2 */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */ + +/* FLASH and environment organization */ +#define CONFIG_MMC_DEFAULT_DEV 0 + +#define CONFIG_USE_ONENAND_BOARD_INIT +#define CONFIG_SAMSUNG_ONENAND 1 +#define CONFIG_SYS_ONENAND_BASE 0xB0000000 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) + +#define CONFIG_USB_GADGET_DWC2_OTG_PHY + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/s5pc210_universal.h b/roms/u-boot/include/configs/s5pc210_universal.h new file mode 100644 index 000000000..0b679f437 --- /dev/null +++ b/roms/u-boot/include/configs/s5pc210_universal.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2010 Samsung Electronics + * Minkyu Kang + * + * Configuation settings for the SAMSUNG Universal (EXYNOS4210) board. + */ + +#ifndef __CONFIG_UNIVERSAL_H +#define __CONFIG_UNIVERSAL_H + +#include + +#define CONFIG_TIZEN /* TIZEN lib */ + +/* Keep L2 Cache Disabled */ +#define CONFIG_SYS_L2CACHE_OFF 1 + +/* Universal has 2 banks of DRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE + +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ + +#define CONFIG_BOOTCOMMAND "run mmcboot" + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ + - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +/* memtest works on */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) + +/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ + +#define NORMAL_MTDPARTS_DEFAULT CONFIG_MTDPARTS_DEFAULT + +#define MBRPARTS_DEFAULT "20M(permanent)"\ + ",20M(boot)"\ + ",1G(system)"\ + ",100M(swap)"\ + ",-(UMS)\0" + +#define CONFIG_ENV_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7" +#define CONFIG_BOOTBLOCK "10" +#define CONFIG_UBIBLOCK "9" + +#define CONFIG_ENV_UBIFS_OPTION " rootflags=bulk_read,no_chk_data_crc " +#define CONFIG_ENV_FLASHBOOT CONFIG_ENV_UBI_MTD CONFIG_ENV_UBIFS_OPTION \ + "${mtdparts}" + +#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "updateb=" \ + "onenand erase 0x0 0x100000;" \ + "onenand write 0x42008000 0x0 0x100000\0" \ + "updatek=" \ + "onenand erase 0xc00000 0x500000;" \ + "onenand write 0x41008000 0xc00000 0x500000\0" \ + "bootk=" \ + "run loaduimage; bootm 0x40007FC0\0" \ + "updatebackup=" \ + "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ + "mmc dev 0 0\0" \ + "updatebootb=" \ + "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ + "lpj=lpj=3981312\0" \ + "ubifsboot=" \ + "set bootargs root=ubi0!rootfs rootfstype=ubifs ${lpj} " \ + CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \ + CONFIG_ENV_COMMON_BOOT "; run bootk\0" \ + "tftpboot=" \ + "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ + CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \ + CONFIG_ENV_COMMON_BOOT \ + "; tftp 0x40007FC0 uImage; bootm 0x40007FC0\0" \ + "nfsboot=" \ + "set bootargs root=/dev/nfs rw " \ + "nfsroot=${nfsroot},nolock,tcp " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ + "; run bootk\0" \ + "ramfsboot=" \ + "set bootargs root=/dev/ram0 rw rootfstype=ext2 " \ + "${console} ${meminfo} " \ + "initrd=0x43000000,8M ramdisk=8192\0" \ + "mmcboot=" \ + "set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ + "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ + "run loaduimage; bootm 0x40007FC0\0" \ + "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ + "boottrace=setenv opts initcall_debug; run bootcmd\0" \ + "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ + "verify=n\0" \ + "rootfstype=ext4\0" \ + "console=console=ttySAC1,115200n8\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ + "mbrparts=" MBRPARTS_DEFAULT \ + "meminfo=crashkernel=32M@0x50000000\0" \ + "nfsroot=/nfsroot/arm\0" \ + "bootblock=" CONFIG_BOOTBLOCK "\0" \ + "ubiblock=" CONFIG_UBIBLOCK" \0" \ + "ubi=enabled\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ + "mmcdev=0\0" \ + "mmcbootpart=2\0" \ + "mmcrootpart=3\0" \ + "opts=always_resume=1" + +#define CONFIG_USE_ONENAND_BOARD_INIT +#define CONFIG_SAMSUNG_ONENAND +#define CONFIG_SYS_ONENAND_BASE 0x0C000000 + +#define CONFIG_USB_GADGET_DWC2_OTG_PHY + +/* + * SPI Settings + */ +#define CONFIG_SOFT_SPI + +#ifndef __ASSEMBLY__ +void universal_spi_scl(int bit); +void universal_spi_sda(int bit); +int universal_spi_read(void); +#endif + +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +/* Download menu - Samsung common */ +#define CONFIG_LCD_MENU + +/* Download menu - definitions for check keys */ +#ifndef __ASSEMBLY__ + +#define KEY_PWR_PMIC_NAME "MAX8998_PMIC" +#define KEY_PWR_STATUS_REG MAX8998_REG_STATUS1 +#define KEY_PWR_STATUS_MASK (1 << 7) +#define KEY_PWR_INTERRUPT_REG MAX8998_REG_IRQ1 +#define KEY_PWR_INTERRUPT_MASK (1 << 7) + +#define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 +#define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 +#endif /* __ASSEMBLY__ */ + +/* LCD console */ +#define LCD_BPP LCD_COLOR16 + +/* + * LCD Settings + */ +#define CONFIG_LD9040 +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sagem_f@st1704.h b/roms/u-boot/include/configs/sagem_f@st1704.h new file mode 100644 index 000000000..e5bb4e50d --- /dev/null +++ b/roms/u-boot/include/configs/sagem_f@st1704.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#include +#include + diff --git a/roms/u-boot/include/configs/salvator-x.h b/roms/u-boot/include/configs/salvator-x.h new file mode 100644 index 000000000..1eafff10f --- /dev/null +++ b/roms/u-boot/include/configs/salvator-x.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/salvator-x.h + * This file is Salvator-X board configuration. + * + * Copyright (C) 2015 Renesas Electronics Corporation + */ + +#ifndef __SALVATOR_X_H +#define __SALVATOR_X_H + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_BITBANGMII_MULTI + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +/* Environment in eMMC, at the end of 2nd "boot sector" */ + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +#endif /* __SALVATOR_X_H */ diff --git a/roms/u-boot/include/configs/sam9x60ek.h b/roms/u-boot/include/configs/sam9x60ek.h new file mode 100644 index 000000000..6a6f1de41 --- /dev/null +++ b/roms/u-boot/include/configs/sam9x60ek.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the SAM9X60EK board. + * + * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries + * + * Author: Sandeep Sheriker M + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID 0 /* ignored in arm */ + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0) + * NB: in this case, USB 1.1 devices won't be recognized. + */ + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 + CONFIG_SYS_MALLOC_F_LEN - \ + GENERATED_GBL_DATA_SIZE) + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#ifdef CONFIG_SD_BOOT +/* bootstrap + u-boot + env + linux in sd card */ +#define CONFIG_BOOTCOMMAND \ + "fatload mmc 0:1 0x21000000 at91-sam9x60ek.dtb;" \ + "fatload mmc 0:1 0x22000000 zImage;" \ + "bootz 0x22000000 - 0x21000000" + +#elif defined(CONFIG_NAND_BOOT) +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_BOOTCOMMAND "nand read " \ + "0x22000000 0x200000 0x600000; " \ + "nand read 0x21000000 0x180000 0x20000; " \ + "bootz 0x22000000 - 0x21000000" + +#elif defined(CONFIG_QSPI_BOOT) +/* bootstrap + u-boot + env + linux in SPI NOR flash */ +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x21000000 0x180000 0x80000; " \ + "sf read 0x22000000 0x200000 0x600000; " \ + "bootz 0x22000000 - 0x21000000" +#endif + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) + +#endif diff --git a/roms/u-boot/include/configs/sama5d27_som1_ek.h b/roms/u-boot/include/configs/sama5d27_som1_ek.h new file mode 100644 index 000000000..8942d1593 --- /dev/null +++ b/roms/u-boot/include/configs/sama5d27_som1_ek.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for the SAMA5D27 SOM1 EK Board. + * + * Copyright (C) 2017 Microchip Corporation + * Wenyou Yang + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +#undef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x8000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_SD_BOOT +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 " \ + CONFIG_DEFAULT_DEVICE_TREE ".dtb; " \ + "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#endif + +/* SPL */ +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif + +#endif diff --git a/roms/u-boot/include/configs/sama5d27_wlsom1_ek.h b/roms/u-boot/include/configs/sama5d27_wlsom1_ek.h new file mode 100644 index 000000000..8bea76458 --- /dev/null +++ b/roms/u-boot/include/configs/sama5d27_wlsom1_ek.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for the SAMA5D27 WLSOM1 EK Board. + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Nicolas Ferre + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +#undef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* SPL */ +#define CONFIG_SPL_TEXT_BASE 0x200000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif + +#endif diff --git a/roms/u-boot/include/configs/sama5d2_icp.h b/roms/u-boot/include/configs/sama5d2_icp.h new file mode 100644 index 000000000..9be6d4f33 --- /dev/null +++ b/roms/u-boot/include/configs/sama5d2_icp.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for the SAMA5D2 ICP Board. + * + * Copyright (C) 2018 Microchip Corporation + * Eugen Hristev + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +#undef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_MISC_INIT_R + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* NAND flash */ + +/* SPI flash */ +#define CONFIG_SF_DEFAULT_SPEED 66000000 + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_SD_BOOT +/* u-boot env in sd/mmc card */ +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0" +#define FAT_ENV_FILE "uboot.env" +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#endif + +/* SPL */ +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif + +#endif diff --git a/roms/u-boot/include/configs/sama5d2_ptc_ek.h b/roms/u-boot/include/configs/sama5d2_ptc_ek.h new file mode 100644 index 000000000..f42e26a0e --- /dev/null +++ b/roms/u-boot/include/configs/sama5d2_ptc_ek.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for the SAMA5D2 PTC EK Board. + * + * Copyright (C) 2017 Microchip Technology Inc. + * Wenyou Yang + * Ludovic Desroches + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +#undef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* NAND Flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sama5d2_xplained.h b/roms/u-boot/include/configs/sama5d2_xplained.h new file mode 100644 index 000000000..4f5ceca78 --- /dev/null +++ b/roms/u-boot/include/configs/sama5d2_xplained.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for the SAMA5D2 Xplained Board. + * + * Copyright (C) 2015 Atmel Corporation + * Wenyou Yang + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* SerialFlash */ + +#ifdef CONFIG_SD_BOOT + +/* bootstrap + u-boot + env in sd card */ +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 at91-sama5d2_xplained.dtb; " \ + "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" + +#elif CONFIG_SPI_BOOT + +/* bootstrap + u-boot + env in sd card, but kernel + dtb in eMMC */ +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_BOOTCOMMAND "ext4load mmc 0:1 0x21000000 /boot/at91-sama5d2_xplained.dtb; " \ + "ext4load mmc 0:1 0x22000000 /boot/zImage; " \ + "bootz 0x22000000 - 0x21000000" + +#endif + +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_ENV_SPI_BUS +#undef CONFIG_BOOTCOMMAND +#define CONFIG_ENV_SPI_BUS 1 +#define CONFIG_BOOTCOMMAND "sf probe 1:0; " \ + "sf read 0x21000000 0x180000 0x80000; " \ + "sf read 0x22000000 0x200000 0x600000; "\ + "bootz 0x22000000 - 0x21000000" + +#endif + +/* SPL */ +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif + +#endif diff --git a/roms/u-boot/include/configs/sama5d3_xplained.h b/roms/u-boot/include/configs/sama5d3_xplained.h new file mode 100644 index 000000000..1113214bc --- /dev/null +++ b/roms/u-boot/include/configs/sama5d3_xplained.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the SAMA5D3 Xplained board. + * + * Copyright (C) 2014 Atmel Corporation + * Bo Shen + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include "at91-sama5_common.h" + +/* + * This needs to be defined for the OHCI code to work but it is defined as + * ATMEL_ID_UHPHS in the CPU specific header files. + */ +#define ATMEL_ID_UHP 32 + +/* + * Specify the clock enable bit in the PMC_SCER register. + */ +#define ATMEL_PMC_UHP (1 << 6) + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x318000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x60000000 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_UPLL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* SPL */ +#define CONFIG_SPL_MAX_SIZE 0x18000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +/* size of u-boot.bin to load */ +#define CONFIG_SYS_MONITOR_LEN (2 * SZ_512K) + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + +#endif diff --git a/roms/u-boot/include/configs/sama5d3xek.h b/roms/u-boot/include/configs/sama5d3xek.h new file mode 100644 index 000000000..44c1952b5 --- /dev/null +++ b/roms/u-boot/include/configs/sama5d3xek.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the SAMA5D3xEK board. + * + * Copyright (C) 2012 - 2013 Atmel + * + * based on at91sam9m10g45ek.h by: + * Stelian Pop + * Lead Tech Design + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +/* + * This needs to be defined for the OHCI code to work but it is defined as + * ATMEL_ID_UHPHS in the CPU specific header files. + */ +#define ATMEL_ID_UHP 32 + +/* + * Specify the clock enable bit in the PMC_SCER register. + */ +#define ATMEL_PMC_UHP (1 << 6) + +/* board specific (not enough SRAM) */ +#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000 + +/* NOR flash */ +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CONFIG_SYS_MAX_FLASH_SECT 131 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#endif + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x318000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +/* SerialFlash */ + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x60000000 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_ATMEL_CLK_SEL_UPLL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* SPL */ +#define CONFIG_SPL_MAX_SIZE 0x18000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + +#endif diff --git a/roms/u-boot/include/configs/sama5d4_xplained.h b/roms/u-boot/include/configs/sama5d4_xplained.h new file mode 100644 index 000000000..80809df63 --- /dev/null +++ b/roms/u-boot/include/configs/sama5d4_xplained.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the SAMA5D4 Xplained ultra board. + * + * Copyright (C) 2014 Atmel + * Bo Shen + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x80000000 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif + +/* SPL */ +#define CONFIG_SPL_MAX_SIZE 0x18000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 224 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + +#endif diff --git a/roms/u-boot/include/configs/sama5d4ek.h b/roms/u-boot/include/configs/sama5d4ek.h new file mode 100644 index 000000000..2fb4764f7 --- /dev/null +++ b/roms/u-boot/include/configs/sama5d4ek.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the SAMA5D4EK board. + * + * Copyright (C) 2014 Atmel + * Bo Shen + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x80000000 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif + +/* SPL */ +#define CONFIG_SPL_MAX_SIZE 0x18000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 224 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + +#endif diff --git a/roms/u-boot/include/configs/sama7g5ek.h b/roms/u-boot/include/configs/sama7g5ek.h new file mode 100644 index 000000000..ef3bfa36f --- /dev/null +++ b/roms/u-boot/include/configs/sama7g5ek.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for the SAMA7G5EK Board. + * + * Copyright (C) 2020 Microchip Corporation + * Eugen Hristev + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 + CONFIG_SYS_MALLOC_F_LEN - \ + GENERATED_GBL_DATA_SIZE) +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x62000000 /* load address */ + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_SD_BOOT +/* u-boot env in sd/mmc card */ + +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x61000000 at91-sama7g5ek.dtb; " \ + "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x62000000 zImage; " \ + "bootz 0x62000000 - 0x61000000" +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#define CONFIG_ARP_TIMEOUT 200 +#define CONFIG_NET_RETRY_COUNT 50 + +#endif diff --git a/roms/u-boot/include/configs/sandbox.h b/roms/u-boot/include/configs/sandbox.h new file mode 100644 index 000000000..8eeccdd42 --- /dev/null +++ b/roms/u-boot/include/configs/sandbox.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef FTRACE +#define CONFIG_TRACE +#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) +#define CONFIG_TRACE_EARLY_SIZE (16 << 20) +#define CONFIG_TRACE_EARLY +#define CONFIG_TRACE_EARLY_ADDR 0x00100000 +#endif + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_IO_TRACE +#endif + +#ifndef CONFIG_TIMER +#define CONFIG_SYS_TIMER_RATE 1000000 +#endif + +#define CONFIG_HOST_MAX_DEVICES 4 + +/* + * Size of malloc() pool, before and after relocation + */ +#define CONFIG_MALLOC_F_ADDR 0x0010000 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* turn on command-line edit/c/auto */ + +/* SPI - enable all SPI flash types for testing purposes */ + +#define CONFIG_I2C_EDID + +/* Memory things - we don't really want a memory test */ +#define CONFIG_SYS_LOAD_ADDR 0x00000000 +#define CONFIG_SYS_FDT_LOAD_ADDR 0x100 + +#define CONFIG_PHYSMEM + +/* Size of our emulated memory */ +#define SB_CONCAT(x, y) x ## y +#define SB_TO_UL(s) SB_CONCAT(s, UL) +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_SDRAM_SIZE \ + (SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20) +#define CONFIG_SYS_MONITOR_BASE 0 + +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} + +#define BOOT_TARGET_DEVICES(func) \ + func(HOST, host, 1) \ + func(HOST, host, 0) + +#ifdef __ASSEMBLY__ +#define BOOTENV +#else +#include +#endif + +#define CONFIG_KEEP_SERVERADDR +#define CONFIG_UDP_CHECKSUM +#define CONFIG_TIMESTAMP +#define CONFIG_BOOTP_SERVERIP + +#ifndef SANDBOX_NO_SDL +#define CONFIG_SANDBOX_SDL +#endif + +/* LCD and keyboard require SDL support */ +#ifdef CONFIG_SANDBOX_SDL +#define LCD_BPP LCD_COLOR16 +#define CONFIG_LCD_BMP_RLE8 + +#define CONFIG_KEYBOARD + +#define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" +#else +#define SANDBOX_SERIAL_SETTINGS "stdin=serial\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" +#endif + +#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \ + "eth2addr=00:00:11:22:33:48\0" \ + "eth3addr=00:00:11:22:33:45\0" \ + "eth4addr=00:00:11:22:33:48\0" \ + "eth5addr=00:00:11:22:33:46\0" \ + "eth6addr=00:00:11:22:33:47\0" \ + "ipaddr=1.2.3.4\0" + +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x1000000\0" \ + "fdt_addr_r=0xc00000\0" \ + "ramdisk_addr_r=0x2000000\0" \ + "scriptaddr=0x1000\0" \ + "pxefile_addr_r=0x2000\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + SANDBOX_SERIAL_SETTINGS \ + SANDBOX_ETH_SETTINGS \ + BOOTENV \ + MEM_LAYOUT_ENV_SETTINGS + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0 +#define CONFIG_SYS_IDE_MAXDEVICE 2 +#define CONFIG_SYS_ATA_BASE_ADDR 0x100 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 1 +#define CONFIG_SYS_ATA_ALT_OFFSET 2 +#define CONFIG_SYS_ATA_STRIDE 4 +#endif + +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_DEVICE 2 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 8 +#define CONFIG_SYS_SCSI_MAX_LUN 4 + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 + +#endif diff --git a/roms/u-boot/include/configs/sandbox_spl.h b/roms/u-boot/include/configs/sandbox_spl.h new file mode 100644 index 000000000..f53688268 --- /dev/null +++ b/roms/u-boot/include/configs/sandbox_spl.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2016 Google, Inc + */ + +#ifndef __SANDBOX_SPL_CONFIG_H +#define __SANDBOX_SPL_CONFIG_H + +#include + +#endif diff --git a/roms/u-boot/include/configs/sbc8349.h b/roms/u-boot/include/configs/sbc8349.h new file mode 100644 index 000000000..929579efe --- /dev/null +++ b/roms/u-boot/include/configs/sbc8349.h @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * WindRiver SBC8349 U-Boot configuration file. + * Copyright (c) 2006, 2007 Wind River Systems, Inc. + * + * Paul Gortmaker + * Based on the MPC8349EMDS config. + */ + +/* + * sbc8349 board configuration file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ + +/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ +#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ + +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ + +/* + * DDR Setup + */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ +#define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ + +/* + * 32-bit data path mode. + * + * Please note that using this mode for devices with the real density of 64-bit + * effectively reduces the amount of available memory due to the effect of + * wrapping around while translating address to row/columns, for example in the + * 256MB module the upper 128MB get aliased with contents of the lower + * 128MB); normally this define should be used for devices with real 32-bit + * data path. + */ +#undef CONFIG_DDR_32BIT + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) +#define CONFIG_DDR_2T_TIMING + +#if defined(CONFIG_SPD_EEPROM) +/* + * Determine DDR configuration from I2C interface. + */ +#define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ + +#else +/* + * Manually set up DDR parameters + * NB: manual DDR setup untested on sbc834x + */ +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) +#define CONFIG_SYS_DDR_TIMING_1 0x36332321 +#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ + +#if defined(CONFIG_DDR_32BIT) +/* set burst length to 8 for 32-bit data path */ + /* DLL,normal,seq,4/2.5, 8 burst len */ +#define CONFIG_SYS_DDR_MODE 0x00000023 +#else +/* the default burst length is 4 - for 64-bit data path */ + /* DLL,normal,seq,4/2.5, 4 burst len */ +#define CONFIG_SYS_DDR_MODE 0x00000022 +#endif +#endif + +/* + * SDRAM on the Local Bus + */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ + + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 + /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 + /* Size of used area in RAM*/ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 + +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ + +#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} } +/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ + +/* TSEC */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 +#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE +#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 +#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0xFIXME +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + +/* + * TSEC configuration + */ + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_PHY_BCM5421S 1 +#define TSEC1_PHY_ADDR 0x19 +#define TSEC2_PHY_ADDR 0x1a +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#ifndef CONFIG_SYS_RAMBOOT +/* Address and size of Redundant Environment Sector */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +/* System IO Config */ +#define CONFIG_SYS_SICRH 0 +#define CONFIG_SYS_SICRL SICRL_LDP_A + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_HOSTNAME "SBC8349" +#define CONFIG_ROOTPATH "/tftpboot/rootfs" +#define CONFIG_BOOTFILE "uImage" + + /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=sbc8349\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ + "update=protect off ff800000 ff83ffff; " \ + "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ + "upd=run load update\0" \ + "fdtaddr=780000\0" \ + "fdtfile=sbc8349.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ + "$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sbc8548.h b/roms/u-boot/include/configs/sbc8548.h new file mode 100644 index 000000000..6e26d456a --- /dev/null +++ b/roms/u-boot/include/configs/sbc8548.h @@ -0,0 +1,540 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2007,2009 Wind River Systems + * Copyright 2007 Embedded Specialties, Inc. + * Copyright 2004, 2007 Freescale Semiconductor. + */ + +/* + * sbc8548 board configuration file + * Please refer to board/sbc8548/README for more info. + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_PCI1 +#endif + +#ifdef CONFIG_66 +#define CONFIG_SYS_CLK_DIV 1 +#endif + +#ifdef CONFIG_33 +#define CONFIG_SYS_CLK_DIV 2 +#endif + +#ifdef CONFIG_PCIE +#define CONFIG_PCIE1 +#endif + +/* + * High Level Configuration Options + */ + +/* + * If you want to boot from the SODIMM flash, instead of the soldered + * on flash, set this, and change JP12, SW2:8 accordingly. + */ +#undef CONFIG_SYS_ALT_BOOT + +#undef CONFIG_RIO + +#ifdef CONFIG_PCI +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#endif + +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ + +/* + * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] + */ +#ifndef CONFIG_SYS_CLK_DIV +#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ +#endif +#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ + +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* DDR Setup */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +/* + * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD + * to collide, meaning you couldn't reliably read either. So + * physically remove the LBC PC100 SDRAM module from the board + * before enabling the two SPD options below, or check that you + * have the hardware fix on your board via "i2c probe" and looking + * for a device at 0x53. + */ +#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#undef CONFIG_DDR_SPD + +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 + +/* + * The hardware fix for the I2C address collision puts the DDR + * SPD at 0x53, but if we are running on an older board w/o the + * fix, it will still be at 0x51. We check 0x53 1st. + */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ +#define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */ + +/* + * Make sure required options are set + */ +#ifndef CONFIG_SPD_EEPROM + #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ + #define CONFIG_SYS_DDR_CONTROL 0xc300c000 +#endif + +/* + * FLASH on the Local Bus + * Two banks, one 8MB the other 64MB, using the CFI driver. + * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have + * CS0 the 8MB boot flash, and CS6 the 64MB flash. + * + * Default: + * ec00_0000 efff_ffff 64MB SODIMM + * ff80_0000 ffff_ffff 8MB soldered flash + * + * Alternate: + * ef80_0000 efff_ffff 8MB soldered flash + * fc00_0000 ffff_ffff 64MB SODIMM + * + * BR0_8M: + * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 + * Port Size = 8 bits = BRx[19:20] = 01 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * BR0_64M: + * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0 + * Port Size = 32 bits = BRx[19:20] = 11 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M + * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M + */ +#define CONFIG_SYS_BR0_8M 0xff800801 +#define CONFIG_SYS_BR0_64M 0xfc001801 + +/* + * BR6_8M: + * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0 + * Port Size = 8 bits = BRx[19:20] = 01 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + + * BR6_64M: + * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 + * Port Size = 32 bits = BRx[19:20] = 11 + * + * 0 4 8 12 16 20 24 28 + * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M + * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M + */ +#define CONFIG_SYS_BR6_8M 0xef800801 +#define CONFIG_SYS_BR6_64M 0xec001801 + +/* + * OR0_8M: + * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 + * XAM = OR0[17:18] = 11 + * CSNT = OR0[20] = 1 + * ACS = half cycle delay = OR0[21:22] = 11 + * SCY = 6 = OR0[24:27] = 0110 + * TRLX = use relaxed timing = OR0[29] = 1 + * EAD = use external address latch delay = OR0[31] = 1 + * + * OR0_64M: + * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0 + * + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M + * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M + */ +#define CONFIG_SYS_OR0_8M 0xff806e65 +#define CONFIG_SYS_OR0_64M 0xfc006e65 + +/* + * OR6_8M: + * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0 + * XAM = OR6[17:18] = 11 + * CSNT = OR6[20] = 1 + * ACS = half cycle delay = OR6[21:22] = 11 + * SCY = 6 = OR6[24:27] = 0110 + * TRLX = use relaxed timing = OR6[29] = 1 + * EAD = use external address latch delay = OR6[31] = 1 + * + * OR6_64M: + * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M + * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M + */ +#define CONFIG_SYS_OR6_8M 0xff806e65 +#define CONFIG_SYS_OR6_64M 0xfc006e65 + +#ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */ +#define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ +#define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ + +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M + +#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M +#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M +#else /* JP12 in alternate position */ +#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */ +#define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */ + +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M + +#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M +#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M +#endif + +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_ALT_FLASH} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO + +/* CS5 = Local bus peripherals controlled by the EPLD */ + +#define CONFIG_SYS_BR5_PRELIM 0xf8000801 +#define CONFIG_SYS_OR5_PRELIM 0xff006e65 +#define CONFIG_SYS_EPLD_BASE 0xf8000000 +#define CONFIG_SYS_LED_DISP_BASE 0xf8000000 +#define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 +#define CONFIG_SYS_BD_REV 0xf8300000 +#define CONFIG_SYS_EEPROM_BASE 0xf8b00000 + +/* + * SDRAM on the Local Bus (CS3 and CS4) + * Note that most boards have a hardware errata where both the + * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible + * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. + * A hardware workaround is also available, see README.sbc8548 file. + */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ + +/* + * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. + * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR3, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + */ + +#define CONFIG_SYS_BR3_PRELIM 0xf0001861 + +/* + * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * + * For OR3, need: + * 64MB mask for AM, OR3[0:7] = 1111 1100 + * XAM, OR3[17:18] = 11 + * 10 columns OR3[19-21] = 011 + * 12 rows OR3[23-25] = 011 + * EAD set for extra time OR[31] = 0 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 + */ + +#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 + +/* + * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. + * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. + * + * For BR4, need: + * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 + * + */ + +#define CONFIG_SYS_BR4_PRELIM 0xf4001861 + +/* + * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * + * For OR4, need: + * 64MB mask for AM, OR3[0:7] = 1111 1100 + * XAM, OR3[17:18] = 11 + * 10 columns OR3[19-21] = 011 + * 12 rows OR3[23-25] = 011 + * EAD set for extra time OR[31] = 0 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 + */ + +#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 + +#define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ + +/* + * Common settings for all Local Bus SDRAM commands. + */ +#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ + | LSDMR_BSMA1516 \ + | LSDMR_PRETOACT3 \ + | LSDMR_ACTTORW3 \ + | LSDMR_BUFCMD \ + | LSDMR_BL8 \ + | LSDMR_WRC2 \ + | LSDMR_CL3 \ + ) + +#define CONFIG_SYS_LBC_LSDMR_PCHALL \ + (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) +#define CONFIG_SYS_LBC_LSDMR_ARFRSH \ + (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) +#define CONFIG_SYS_LBC_LSDMR_MRW \ + (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) +#define CONFIG_SYS_LBC_LSDMR_RFEN \ + (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN) + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ + +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and + * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM + * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg + * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right + * thing for MONITOR_LEN in both cases. + */ +#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ +#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ + +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ + +#ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ +#endif + +#ifdef CONFIG_RIO +/* + * RapidIO MMU + */ +#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 +#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ +#endif + +#if defined(CONFIG_PCI) + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 0x19 +#define TSEC2_PHY_ADDR 0x1a + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: eTSEC[0-3] */ +#define CONFIG_ETHPRIME "eTSEC0" +#endif /* CONFIG_TSEC_ENET */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_IPADDR 192.168.0.55 + +#define CONFIG_HOSTNAME "sbc8548" +#define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx" +#define CONFIG_BOOTFILE "/uImage" +#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ + +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ + +#define CONFIG_EXTRA_ENV_SETTINGS \ +"netdev=eth0\0" \ +"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ +"tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ +"consoledev=ttyS0\0" \ +"ramdiskaddr=2000000\0" \ +"ramdiskfile=uRamdisk\0" \ +"fdtaddr=1e00000\0" \ +"fdtfile=sbc8548.dtb\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sbc8641d.h b/roms/u-boot/include/configs/sbc8641d.h new file mode 100644 index 000000000..3d5aee0dd --- /dev/null +++ b/roms/u-boot/include/configs/sbc8641d.h @@ -0,0 +1,509 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2007 Wind River Systems + * Copyright 2007 Embedded Specialties, Inc. + * Joe Hamman + * + * Copyright 2006 Freescale Semiconductor. + * + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + */ + +/* + * SBC8641D board configuration file + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_SERVERIP, etc in this file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ + +#ifdef RUN_DIAG +#define CONFIG_SYS_DIAG_ADDR 0xff800000 +#endif + +#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 + +/* + * virtual address to be used for temporary mappings. There + * should be 128k free at this VA. + */ +#define CONFIG_SYS_SCRATCH_VA 0xe8000000 + +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + +#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ + +#define CONFIG_BAT_RW 1 /* Use common BAT rw code */ + +#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CACHE_LINE_INTERLEAVING 0x20000000 +#define PAGE_INTERLEAVING 0x21000000 +#define BANK_INTERLEAVING 0x22000000 +#define SUPER_BANK_INTERLEAVING 0x23000000 + +#define CONFIG_ALTIVEC 1 + +/* + * L2CR setup -- make sure this is right for your board! + */ +#define CONFIG_SYS_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2CR_L2E) + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) +#endif + +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ + +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 +#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ +#define CONFIG_VERY_BIG_RAM + +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ + +#else + /* + * Manually set up DDR1 & DDR2 parameters + */ + + #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ + + #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F + #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 + #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 + #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 + #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 + #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 + #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 + #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 + #define CONFIG_SYS_DDR_TIMING_3 0x00000000 + #define CONFIG_SYS_DDR_TIMING_0 0x00220802 + #define CONFIG_SYS_DDR_TIMING_1 0x38377322 + #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 + #define CONFIG_SYS_DDR_CFG_1A 0x43008008 + #define CONFIG_SYS_DDR_CFG_2 0x24401000 + #define CONFIG_SYS_DDR_MODE_1 0x23c00542 + #define CONFIG_SYS_DDR_MODE_2 0x00000000 + #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 + #define CONFIG_SYS_DDR_INTERVAL 0x05080100 + #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 + #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 + #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 + + #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F + #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 + #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 + #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 + #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 + #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 + #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 + #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 + #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 + #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 + #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 + #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 + #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 + #define CONFIG_SYS_DDR2_CFG_2 0x24401000 + #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 + #define CONFIG_SYS_DDR2_MODE_2 0x00000000 + #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 + #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 + #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 + #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 + #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 + +#endif + +/* #define CONFIG_ID_EEPROM 1 +#define ID_EEPROM_ADDR 0x57 */ + +/* + * The SBC8641D contains 16MB flash space at ff000000. + */ +#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ + +/* Flash */ +#define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ +#define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ + +/* 64KB EEPROM */ +#define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ +#define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ + +/* EPLD - User switches, board id, LEDs */ +#define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ +#define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ + +/* Local bus SDRAM 128MB */ +#define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ +#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ +#define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ +#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ + +/* Disk on Chip (DOC) 128MB */ +#define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ +#define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ + +/* LCD */ +#define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ +#define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ + +/* Control logic & misc peripherals */ +#define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ +#define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ + +#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CONFIG_SYS_FLASH_EMPTY_INFO + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#ifndef CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ +#else +#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } + +/* + * RapidIO MMU + */ +#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 +#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS +#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS +#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ + +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 +#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS +#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS +#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SATA_ULI5288 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) +#endif + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "eTSEC4" + +#define TSEC1_PHY_ADDR 0x1F +#define TSEC2_PHY_ADDR 0x00 +#define TSEC3_PHY_ADDR 0x01 +#define TSEC4_PHY_ADDR 0x02 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS TSEC_GIGABIT +#define TSEC4_FLAGS TSEC_GIGABIT + +#define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ + +#define CONFIG_ETHPRIME "eTSEC1" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR + */ +#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) +#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U + +/* + * BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 512M PCI-Express 1 Memory + * 0xa000_0000 512M PCI-Express 2 Memory + * Changed it for operating from 0xd0000000 + */ +#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U + +/* + * BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M RapidIO Memory + */ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U + +/* + * BAT3 4M Cache-inhibited, guarded + * 0xf800_0000 4M CCSR + */ +#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U + +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) +#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ + | BATL_PP_RW | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ + | BATU_BL_1M | BATU_VS | BATU_VP) +#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ + | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU +#endif + +/* + * BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 + * Note that this is at 0xe0000000 + */ +#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U + +/* + * BAT5 128K Cacheable, non-guarded + * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) + */ +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L +#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U + +/* + * BAT6 32M Cache-inhibited, guarded + * 0xfe00_0000 32M FLASH + */ +#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U + +/* Map the last 1M of flash where we're running from reset */ +#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY + +#define CONFIG_SYS_DBAT7L 0x00000000 +#define CONFIG_SYS_DBAT7U 0x00000000 +#define CONFIG_SYS_IBAT7L 0x00000000 +#define CONFIG_SYS_IBAT7U 0x00000000 + +/* + * Environment + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 32768 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_HAS_ETH0 1 +#define CONFIG_HAS_ETH1 1 +#define CONFIG_HAS_ETH2 1 +#define CONFIG_HAS_ETH3 1 + +#define CONFIG_IPADDR 192.168.0.50 + +#define CONFIG_HOSTNAME "sbc8641d" +#define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_NETMASK 255.255.255.0 + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=uRamdisk\0" \ + "dtbaddr=400000\0" \ + "dtbfile=sbc8641d.dtb\0" \ + "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ + "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ + "maxcpus=1" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr $ramdiskaddr $dtbaddr" + +#define CONFIG_FLASHBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "bootm ffd00000 ffb00000 ffa00000" + +#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/seaboard.h b/roms/u-boot/include/configs/seaboard.h new file mode 100644 index 000000000..5b5aa1b2f --- /dev/null +++ b/roms/u-boot/include/configs/seaboard.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* LP0 suspend / resume */ +#define CONFIG_TEGRA_LP0 +#define CONFIG_TEGRA_PMU +#define CONFIG_TPS6586X_POWER +#define CONFIG_TEGRA_CLOCK_SCALING + +#include "tegra20-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTD +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD + +/* Environment in eMMC, at the end of 2nd "boot sector" */ + +/* NAND support */ +#define CONFIG_TEGRA_NAND + +/* Max number of NAND devices */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sei510.h b/roms/u-boot/include/configs/sei510.h new file mode 100644 index 000000000..d37b4c640 --- /dev/null +++ b/roms/u-boot/include/configs/sei510.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for the SEI510 + * + * Copyright (C) 2019 Baylibre, SAS + * Author: Jerome Brunet + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define LOGO_UUID "43a3305d-150f-4cc9-bd3b-38fca8693846;" +#define CACHE_UUID "99207ae6-5207-11e9-999e-6f77a3612069;" +#define SYSTEM_UUID "99f9b7ac-5207-11e9-8507-c3c037e393f3;" +#define VENDOR_UUID "9d082802-5207-11e9-954c-cbbce08ba108;" +#define USERDATA_UUID "9b976e42-5207-11e9-8f16-ff47ac594b22;" +#define ROOT_UUID "ddb8c3f6-d94d-4394-b633-3134139cc2e0;" + +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=boot,size=64M,bootable,uuid=${uuid_gpt_boot};" \ + "name=logo,size=2M,uuid=" LOGO_UUID \ + "name=cache,size=256M,uuid=" CACHE_UUID \ + "name=system,size=1536M,uuid=" SYSTEM_UUID \ + "name=vendor,size=256M,uuid=" VENDOR_UUID \ + "name=userdata,size=5341M,uuid=" USERDATA_UUID \ + "name=rootfs,size=-,uuid=" ROOT_UUID + + +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sei610.h b/roms/u-boot/include/configs/sei610.h new file mode 100644 index 000000000..6d093161c --- /dev/null +++ b/roms/u-boot/include/configs/sei610.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for the SEI510 + * + * Copyright (C) 2019 Baylibre, SAS + * Author: Jerome Brunet + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define LOGO_UUID "43a3305d-150f-4cc9-bd3b-38fca8693846;" +#define CACHE_UUID "99207ae6-5207-11e9-999e-6f77a3612069;" +#define SYSTEM_UUID "99f9b7ac-5207-11e9-8507-c3c037e393f3;" +#define VENDOR_UUID "9d082802-5207-11e9-954c-cbbce08ba108;" +#define USERDATA_UUID "9b976e42-5207-11e9-8f16-ff47ac594b22;" +#define ROOT_UUID "ddb8c3f6-d94d-4394-b633-3134139cc2e0;" + +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=boot,size=64M,bootable,uuid=${uuid_gpt_boot};" \ + "name=logo,size=2M,uuid=" LOGO_UUID \ + "name=cache,size=256M,uuid=" CACHE_UUID \ + "name=system,size=1536M,uuid=" SYSTEM_UUID \ + "name=vendor,size=256M,uuid=" VENDOR_UUID \ + "name=userdata,size=12795M,uuid=" USERDATA_UUID \ + "name=rootfs,size=-,uuid=" ROOT_UUID + +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sfr_nb4_ser.h b/roms/u-boot/include/configs/sfr_nb4_ser.h new file mode 100644 index 000000000..529fc9495 --- /dev/null +++ b/roms/u-boot/include/configs/sfr_nb4_ser.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + diff --git a/roms/u-boot/include/configs/sheep_rk3368.h b/roms/u-boot/include/configs/sheep_rk3368.h new file mode 100644 index 000000000..08cc4bf35 --- /dev/null +++ b/roms/u-boot/include/configs/sheep_rk3368.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIGS_PX5_EVB_H +#define __CONFIGS_PX5_EVB_H + +#include + +#define KERNEL_LOAD_ADDR 0x280000 +#define DTB_LOAD_ADDR 0x5600000 +#define INITRD_LOAD_ADDR 0x5bf0000 + +#endif diff --git a/roms/u-boot/include/configs/sheevaplug.h b/roms/u-boot/include/configs/sheevaplug.h new file mode 100644 index 000000000..41ba79965 --- /dev/null +++ b/roms/u-boot/include/configs/sheevaplug.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009-2014 + * Gerald Kerma + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + */ + +#ifndef _CONFIG_SHEEVAPLUG_H +#define _CONFIG_SHEEVAPLUG_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ + +#include "mv-plug-common.h" + +/* + * Environment variables configurations + */ +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +/* + * Environment is right behind U-Boot in flash. Make sure U-Boot + * doesn't grow into the environment area. + */ +#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ + "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ + "bootm 0x6400000;" + +#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ + "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS_DEFAULT \ + "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \ + "x_bootcmd_usb=usb start\0" \ + "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 +#endif /* CONFIG_CMD_NET */ + +/* + * SATA driver configuration + */ +#ifdef CONFIG_IDE +#define __io +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /* CONFIG_IDE */ + +#endif /* _CONFIG_SHEEVAPLUG_H */ diff --git a/roms/u-boot/include/configs/siemens-am33x-common.h b/roms/u-boot/include/configs/siemens-am33x-common.h new file mode 100644 index 000000000..e18af7493 --- /dev/null +++ b/roms/u-boot/include/configs/siemens-am33x-common.h @@ -0,0 +1,449 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * siemens am33x common board options + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef __CONFIG_SIEMENS_AM33X_COMMON_H +#define __CONFIG_SIEMENS_AM33X_COMMON_H + +#include + +#define CONFIG_DMA_COHERENT +#define CONFIG_DMA_COHERENT_SIZE (1 << 20) + +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) +#ifdef CONFIG_SIEMENS_MACH_TYPE +#define CONFIG_MACH_TYPE CONFIG_SIEMENS_MACH_TYPE +#endif + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* commands to include */ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_ROOTPATH "/opt/eldk" +#endif + +#define CONFIG_SYS_AUTOLOAD "yes" + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 32 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * memtest works on 8 MB in DRAM after skipping 32MB from + * start addr of ram disk + */ + +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ + + /* Physical Memory Map */ +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + /* Platform/Board specific defs */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x44e09000 +#define CONFIG_SYS_NS16550_COM4 0x481a6000 + + +/* I2C Configuration */ +#define CONFIG_I2C +#define CONFIG_SYS_I2C + +/* Defines for SPL */ +#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ + CONFIG_SPL_TEXT_BASE) + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW + +#define CONFIG_SYS_NAND_ECCSTEPS 4 +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#ifndef CONFIG_SPL_BUILD +/* + * USB configuration + */ +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +/* USB DRACO ID as default */ +#define CONFIG_USBD_HS + +/* USB Device Firmware Update support */ +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20) +#define DFU_MANIFEST_POLL_TIMEOUT 25000 + +#endif /* CONFIG_SPL_BUILD */ + +/* + * Default to using SPI for environment, etc. We have multiple copies + * of SPL as the ROM will check these locations. + * 0x0 - 0x20000 : First copy of SPL + * 0x20000 - 0x40000 : Second copy of SPL + * 0x40000 - 0x60000 : Third copy of SPL + * 0x60000 - 0x80000 : Fourth copy of SPL + * 0x80000 - 0xDF000 : U-Boot + * 0xDF000 - 0xE0000 : U-Boot Environment + * 0xE0000 - 0x442000 : Linux Kernel + * 0x442000 - 0x800000 : Userland + */ + +#define CONFIG_NET_RETRY_COUNT 10 + +/* NAND support */ +#ifdef CONFIG_MTD_RAW_NAND +/* UBI Support */ + +/* Commen environment */ +#define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \ + "setenv bootargs ${bootargs};" \ + "mtdparts default;" \ + "draco_led 1;" \ + "dfu 0 nand 0;" \ + "draco_led 0;\0" \ + +#define COMMON_ENV_NAND_BOOT \ + "nand_boot=echo Booting from nand; " \ + "if test ${upgrade_available} -eq 1; then " \ + "if test ${bootcount} -gt ${bootlimit}; " \ + "then " \ + "setenv upgrade_available 0;" \ + "setenv ${partitionset_active} true;" \ + "if test -n ${A}; then " \ + "setenv partitionset_active B; " \ + "env delete A; " \ + "fi;" \ + "if test -n ${B}; then " \ + "setenv partitionset_active A; " \ + "env delete B; " \ + "fi;" \ + "saveenv; " \ + "fi;" \ + "fi;" \ + "echo set ${partitionset_active}...;" \ + "run nand_args; " + +#define COMMON_ENV_NAND_CMDS "flash_self=run nand_boot\0" \ + "flash_self_test=setenv testargs test; " \ + "run nand_boot\0" \ + "dfu_start=echo Preparing for dfu mode ...; " \ + "run dfu_args; \0" + +#define COMMON_ENV_SETTINGS \ + "verify=no \0" \ + "project_dir=targetdir\0" \ + "upgrade_available=0\0" \ + "altbootcmd=run bootcmd\0" \ + "partitionset_active=A\0" \ + "loadaddr=0x82000000\0" \ + "kloadaddr=0x81000000\0" \ + "script_addr=0x81900000\0" \ + "console=console=ttyMTD,mtdoops console=ttyO0,115200n8 panic=5\0" \ + "nfsopts=nolock rw\0" \ + "ip_method=none\0" \ + "bootenv=uEnv.txt\0" \ + "bootargs_defaults=setenv bootargs " \ + "console=${console} " \ + "${testargs} " \ + "${optargs}\0" \ + "siemens_help=echo; "\ + "echo Type 'run flash_self' to use kernel and root " \ + "filesystem on memory; echo Type 'run flash_self_test' to " \ + "use kernel and root filesystem on memory, boot in test " \ + "mode; echo Not ready yet: 'run flash_nfs' to use kernel " \ + "from memory and root filesystem over NFS; echo Type " \ + "'run net_nfs' to get Kernel over TFTP and mount root " \ + "filesystem over NFS; " \ + "echo Set partitionset_active variable to 'A' " \ + "or 'B' to select kernel and rootfs partition; " \ + "echo" \ + "\0" + +/* + * Variant 1 partition layout + * chip-size = 256MiB + *| name | size | address area | + *------------------------------------------------------- + *| spl | 128.000 KiB | 0x 0..0x 1ffff | + *| spl.backup1 | 128.000 KiB | 0x 20000..0x 3ffff | + *| spl.backup2 | 128.000 KiB | 0x 40000..0x 5ffff | + *| spl.backup3 | 128.000 KiB | 0x 60000..0x 7ffff | + *| u-boot | 1.875 MiB | 0x 80000..0x 25ffff | + *| uboot.env | 128.000 KiB | 0x 260000..0x 27ffff | + *| kernel_a | 5.000 MiB | 0x 280000..0x 77ffff | + *| kernel_b | 5.000 MiB | 0x 780000..0x c7ffff | + *| mtdoops | 8.000 MiB | 0x c80000..0x 147ffff | + *| rootfs | 235.500 MiB | 0x 1480000..0x fffffff | + *------------------------------------------------------- + + "mtdparts=omap2-nand.0:" \ + "128k(spl)," \ + "128k(spl.backup1)," \ + "128k(spl.backup2)," \ + "128k(spl.backup3)," \ + "1920k(u-boot)," \ + "128k(uboot.env)," \ + "5120k(kernel_a)," \ + "5120k(kernel_b)," \ + "8192k(mtdoops)," \ + "-(rootfs)" + */ + +#define DFU_ALT_INFO_NAND_V1 \ + "spl part 0 1;" \ + "spl.backup1 part 0 2;" \ + "spl.backup2 part 0 3;" \ + "spl.backup3 part 0 4;" \ + "u-boot part 0 5;" \ + "u-boot.env part 0 6;" \ + "kernel_a part 0 7;" \ + "kernel_b part 0 8;" \ + "rootfs partubi 0 10" + +#define CONFIG_ENV_SETTINGS_NAND_V1 \ + "nand_active_ubi_vol=rootfs_a\0" \ + "nand_active_ubi_vol_A=rootfs_a\0" \ + "nand_active_ubi_vol_B=rootfs_b\0" \ + "nand_root_fs_type=ubifs rootwait=1\0" \ + "nand_src_addr=0x280000\0" \ + "nand_src_addr_A=0x280000\0" \ + "nand_src_addr_B=0x780000\0" \ + "nand_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv ${partitionset_active} true;" \ + "if test -n ${A}; then " \ + "setenv nand_active_ubi_vol ${nand_active_ubi_vol_A};" \ + "setenv nand_src_addr ${nand_src_addr_A};" \ + "fi;" \ + "if test -n ${B}; then " \ + "setenv nand_active_ubi_vol ${nand_active_ubi_vol_B};" \ + "setenv nand_src_addr ${nand_src_addr_B};" \ + "fi;" \ + "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ + "ubi.mtd=9,${ubi_off};" \ + "setenv bootargs ${bootargs} " \ + "root=${nand_root} noinitrd ${mtdparts} " \ + "rootfstype=${nand_root_fs_type} ip=${ip_method} " \ + "console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \ + "=mtdoops\0" \ + COMMON_ENV_DFU_ARGS \ + "dfu_alt_info=" DFU_ALT_INFO_NAND_V1 "\0" \ + COMMON_ENV_NAND_BOOT \ + "nand read.i ${kloadaddr} ${nand_src_addr} " \ + "${nand_img_size}; bootm ${kloadaddr}\0" \ + COMMON_ENV_NAND_CMDS + +#define CONFIG_ENV_SETTINGS_V1 \ + COMMON_ENV_SETTINGS \ + "net_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv bootfile ${project_dir}/kernel/uImage;" \ + "setenv rootpath /home/projects/${project_dir}/rootfs;" \ + "setenv bootargs ${bootargs} " \ + "root=/dev/nfs ${mtdparts} " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} " \ + "ip=${ipaddr}:${serverip}:" \ + "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ + "net_nfs=echo Booting from network ...; " \ + "run net_args; " \ + "tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \ + "bootm ${kloadaddr}\0" + +/* + * Variant 2 partition layout (default) + * chip-size = 256MiB or 512 MiB + *| name | size | address area | + *------------------------------------------------------- + *| spl | 128.000 KiB | 0x 0..0x 1ffff | + *| spl.backup1 | 128.000 KiB | 0x 20000..0x 3ffff | + *| spl.backup2 | 128.000 KiB | 0x 40000..0x 5ffff | + *| spl.backup3 | 128.000 KiB | 0x 60000..0x 7ffff | + *| u-boot | 1.875 MiB | 0x 80000..0x 25ffff | + *| uboot.env0 | 512.000 KiB | 0x 260000..0x 2Dffff | + *| uboot.env1 | 512.000 KiB | 0x 2E0000..0x 35ffff | + *| mtdoops | 512.000 KiB | 0x 360000..0x 3dffff | + *| (256) rootfs | 252.125 MiB | 0x 3E0000..0x fffffff | + *| (512) rootfs | 508.125 MiB | 0x 3E0000..0x1fffffff | + *------------------------------------------------------- + */ + +#define DFU_ALT_INFO_NAND_V2 \ + "spl part 0 1;" \ + "spl.backup1 part 0 2;" \ + "spl.backup2 part 0 3;" \ + "spl.backup3 part 0 4;" \ + "u-boot part 0 5;" \ + "u-boot.env0 part 0 6;" \ + "u-boot.env1 part 0 7;" \ + "rootfs partubi 0 9" \ + +#define CONFIG_ENV_SETTINGS_NAND_V2 \ + "nand_active_ubi_vol=rootfs_a\0" \ + "rootfs_name=rootfs\0" \ + "kernel_name=uImage\0"\ + "nand_root_fs_type=ubifs rootwait=1\0" \ + "nand_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv ${partitionset_active} true;" \ + "if test -n ${A}; then " \ + "setenv nand_active_ubi_vol ${rootfs_name}_a;" \ + "fi;" \ + "if test -n ${B}; then " \ + "setenv nand_active_ubi_vol ${rootfs_name}_b;" \ + "fi;" \ + "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ + "ubi.mtd=rootfs,2048;" \ + "setenv bootargs ${bootargs} " \ + "root=${nand_root} noinitrd ${mtdparts} " \ + "rootfstype=${nand_root_fs_type} ip=${ip_method} " \ + "console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \ + "=mtdoops\0" \ + COMMON_ENV_DFU_ARGS \ + "dfu_alt_info=" DFU_ALT_INFO_NAND_V2 "\0" \ + COMMON_ENV_NAND_BOOT \ + "ubi part rootfs ${ubi_off};" \ + "ubifsmount ubi0:${nand_active_ubi_vol};" \ + "ubifsload ${kloadaddr} boot/${kernel_name};" \ + "ubifsload ${loadaddr} boot/${dtb_name}.dtb;" \ + "bootm ${kloadaddr} - ${loadaddr}\0" \ + "nand_boot_backup=ubifsload ${loadaddr} boot/am335x-draco.dtb;" \ + "bootm ${kloadaddr} - ${loadaddr}\0" \ + COMMON_ENV_NAND_CMDS + +#define CONFIG_ENV_SETTINGS_V2 \ + COMMON_ENV_SETTINGS \ + "net_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv bootfile ${project_dir}/kernel/uImage;" \ + "setenv bootdtb ${project_dir}/kernel/dtb;" \ + "setenv rootpath /home/projects/${project_dir}/rootfs;" \ + "setenv bootargs ${bootargs} " \ + "root=/dev/nfs ${mtdparts} " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} " \ + "ip=${ipaddr}:${serverip}:" \ + "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ + "net_nfs=echo Booting from network ...; " \ + "run net_args; " \ + "tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \ + "tftpboot ${loadaddr} ${serverip}:${bootdtb}; " \ + "bootm ${kloadaddr} - ${loadaddr}\0" + +/* + * Variant 3 partition layout + * chip-size = 512MiB + *| name | size | address area | + *------------------------------------------------------- + *| spl | 128.000 KiB | 0x 0..0x 1ffff | + *| spl.backup1 | 128.000 KiB | 0x 20000..0x 3ffff | + *| spl.backup2 | 128.000 KiB | 0x 40000..0x 5ffff | + *| spl.backup3 | 128.000 KiB | 0x 60000..0x 7ffff | + *| u-boot | 1.875 MiB | 0x 80000..0x 25ffff | + *| uboot.env0 | 512.000 KiB | 0x 260000..0x 2Dffff | + *| uboot.env1 | 512.000 KiB | 0x 2E0000..0x 35ffff | + *| rootfs | 300.000 MiB | 0x 360000..0x12f5ffff | + *| mtdoops | 512.000 KiB | 0x12f60000..0x12fdffff | + *|configuration | 104.125 MiB | 0x12fe0000..0x1fffffff | + *------------------------------------------------------- + + "mtdparts=omap2-nand.0:" \ + "128k(spl)," \ + "128k(spl.backup1)," \ + "128k(spl.backup2)," \ + "128k(spl.backup3)," \ + "1920k(u-boot)," \ + "512k(u-boot.env0)," \ + "512k(u-boot.env1)," \ + "300m(rootfs)," \ + "512k(mtdoops)," \ + "-(configuration)" + + */ + +#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ + /* to access nand at */ + /* CS0 */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND + devices */ +#if !defined(CONFIG_SPI_BOOT) +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#endif +#endif + +/* Reboot after 60 sec if bootcmd fails */ +#define CONFIG_RESET_TO_RETRY +#define CONFIG_BOOT_RETRY_TIME 60 + +#endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */ diff --git a/roms/u-boot/include/configs/siemens-ccp-common.h b/roms/u-boot/include/configs/siemens-ccp-common.h new file mode 100644 index 000000000..01051c8ad --- /dev/null +++ b/roms/u-boot/include/configs/siemens-ccp-common.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Be very careful updating CONFIG_IDENT_STRING + * This string will control the update flow whether an U-Boot should be + * updated or not. If the version of installed U-Boot (in flash) is smaller + * than the version to be installed (from update file), an update will + * be performed. + * + * General rules: + * 1. First 4 characters ' ##v' or IDENT_MAGIC represent kind of a magic number + * to identify the following strings after easily. Don't change them! + * + * 2. First 2 digits after 'v' or CCP_MAJOR are updated with U-Boot version + * change, e.g. from 2015.04 to 2018.03 + * + * 3. Second 2 digits after '.' or CCP_MINOR are updated if we want to upgrade + * U-Boot within an U-Boot version. + */ +#define CCP_IDENT_MAGIC " ##v" +#define GENERATE_CCP_VERSION(MAJOR, MINOR) CCP_IDENT_MAGIC MAJOR "." MINOR diff --git a/roms/u-boot/include/configs/siemens-env-common.h b/roms/u-boot/include/configs/siemens-env-common.h new file mode 100644 index 000000000..36fa5d936 --- /dev/null +++ b/roms/u-boot/include/configs/siemens-env-common.h @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* Common env settings */ + +/** set_bootargs() + * input: + * console: string, tty, etc. + * baudrate: string, tty baudrate + * testargs: string + * optargs: string + * output: + * bootargs: string, default boot string + */ +#define ENV_BOOTARGS_DEFAULT "set_bootargs=" \ + "setenv bootargs " \ + "console=${console} " \ + "${testargs} " \ + "${optargs}\0" + +/** set_bootargs_net() + * input: + * kernel_name: + * dtb_name: + * project_dir: + * output: + */ +#define ENV_NET_FCT_NETARGS "set_bootargs_net=" \ + "run set_bootargs;" \ + "setenv bootfile ${project_dir}/boot/${kernel_name};" \ + "setenv bootdtb ${project_dir}/boot/${dtb_name_nfs}.dtb;" \ + "setenv rootpath /home/projects/${project_dir}/;" \ + "setenv bootargs ${bootargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} " \ + "ip=${ipaddr}:${serverip}:" \ + "${gatewayip}:${netmask}:${hostname}:eth0:off\0" + +/** net_nfs() + * input: + * output: + */ +#define ENV_NET_FCT_BOOT "net_nfs=" \ + "echo Booting from network ...; " \ + "run set_bootargs_net; " \ + "tftpboot ${dtb_loadaddr} ${serverip}:${bootdtb};" \ + "if test $? -eq 1;" \ + "then " \ + "echo Loading default.dtb!;" \ + "tftpboot ${dtb_loadaddr} ${serverip}:${project_dir}/boot/${dtb_name_default}.dtb;" \ + "fi;" \ + "tftpboot ${kernel_loadaddr} ${serverip}:${bootfile};" \ + "printenv bootargs;" \ + "booti ${kernel_loadaddr} - ${dtb_loadaddr}\0" + +/** check_update() + * input: + * upgrade_available: [0|1], if set to 1 check bootcount variables + * bootcount: int, bootcount + * bootlimit: int, limit cootcount + * toggle_partition(): - toggles active partition set + * output: + * upgrade_available: [0|1], set to 0 if bootcount > bootlimit + */ +#define ENV_FCT_CHECK_UPGRADE "check_upgrade="\ + "if test ${upgrade_available} -eq 1; " \ + "then " \ + "echo upgrade_available is set; " \ + "if test ${bootcount} -gt ${bootlimit}; " \ + "then " \ + "setenv upgrade_available 0;" \ + "echo toggle partition;" \ + "run toggle_partition;" \ + "fi;" \ + "fi;\0" + +/** toggle_partition() + * input: + * partitionset_active: [A|B], selected partition set + * output: + * partitionset_active: [A|B], toggle + */ +#define ENV_FCT_TOGGLE_PARTITION "toggle_partition="\ + "setenv ${partitionset_active} true;" \ + "if test -n ${A}; " \ + "then " \ + "setenv partitionset_active B; " \ + "env delete A; " \ + "fi;" \ + "if test -n ${B}; "\ + "then " \ + "setenv partitionset_active A; " \ + "env delete B; " \ + "fi;" \ + "saveenv\0" + +/** set_partition() + * input: + * partitionset_active: [A|B], selected partition set + * rootfs_name: string, mmc device file in kernel, e.g. /dev/mmcblk0 + * output: + * mmc_active_vol: string, mmc partition device file in kernel, e.g. /dev/mmcblk0p2 + * mmc_part_nr: int, partition number of mmc, e.g. /dev/mmcblk0p2 --> 2 + */ +#define ENV_EMMC_FCT_SET_ACTIVE_PARTITION "set_partition=" \ + "setenv ${partitionset_active} true;" \ + "if test -n ${A}; " \ + "then " \ + "setenv mmc_part_nr 1;" \ + "fi;" \ + "if test -n ${B}; " \ + "then " \ + "setenv mmc_part_nr 2;" \ + "fi;" \ + "setenv mmc_active_vol ${rootfs_name}p${mmc_part_nr} \0" + +/** set_bootargs_mmc() + * input: + * bootargs: string, default bootargs + * mmc_active_vol string, mmc partition device file in kernel, e.g. /dev/mmcblk0p2 + * ip_method: string, [none|?] + * output: + * bootargs: string + */ +#define ENV_EMMC_FCT_SET_EMMC_BOOTARGS "set_bootargs_mmc=" \ + "setenv bootargs ${bootargs} " \ + "root=${mmc_active_vol} rw " \ + "rootdelay=1 rootwait " \ + "rootfstype=ext4 " \ + "ip=${ip_method} \0" + +/** mmc_load_bootfiles() + * input: + * mmc_part_nr: + * dtb_loadaddr: + * dtb_name: + * kernel_loadaddr: + * kernel_name: + */ +#define ENV_EMMC_FCT_LOADFROM_EMMC "mmc_load_bootfiles=" \ + "echo Loading from eMMC ...;" \ + "ext4load mmc 0:${mmc_part_nr} ${dtb_loadaddr} boot/${dtb_name}.dtb;" \ + "if test $? -eq 1;" \ + "then " \ + "echo Loading default.dtb!;" \ + "ext4load mmc 0:${mmc_part_nr} ${dtb_loadaddr} boot/${dtb_name_default}.dtb;" \ + "fi;" \ + "ext4load mmc 0:${mmc_part_nr} ${kernel_loadaddr} boot/${kernel_name};" \ + "printenv bootargs;\0" + +/** mmc_boot() + * input: + * mmc_part_nr: + * dtb_loadaddr: + * dtb_name: + * kernel_loadaddr: + * kernel_name: + */ +#define ENV_EMMC_FCT_EMMC_BOOT "mmc_boot=" \ + "run set_bootargs;" \ + "run check_upgrade; " \ + "run set_partition;" \ + "run set_bootargs_mmc;" \ + "run mmc_load_bootfiles;" \ + "echo Booting from eMMC ...; " \ + "booti ${kernel_loadaddr} - ${dtb_loadaddr} \0" + +#define ENV_EMMC_ALIASES "" \ + "flash_self=run mmc_boot\0" \ + "flash_self_test=setenv testargs test; " \ + "run mmc_boot\0" + +#define ENV_COMMON "" \ + "project_dir=targetdir/rootfs\0" \ + "serverip=192.168.251.2\0" \ + "ipaddr=192.168.251.1\0" \ + "dtb_name_nfs=default\0" \ + "dtb_name_default=default\0" \ + "kernel_name=Image\0" \ + "partitionset_active=A\0" \ + "dtb_loadaddr=0x83000000\0" \ + "kernel_loadaddr=0x80280000\0" \ + "ip_method=none\0" \ + "rootfs_name=/dev/mmcblk0\0" \ + "upgrade_available=0\0" \ + "bootlimit=3\0" \ + "altbootcmd=run bootcmd\0" \ + "optargs=\0" \ + +/**********************************************************************/ + +#define ENV_EMMC ENV_EMMC_FCT_EMMC_BOOT \ + ENV_EMMC_FCT_LOADFROM_EMMC \ + ENV_EMMC_FCT_SET_EMMC_BOOTARGS \ + ENV_EMMC_FCT_SET_ACTIVE_PARTITION \ + ENV_FCT_CHECK_UPGRADE \ + ENV_EMMC_ALIASES \ + ENV_FCT_TOGGLE_PARTITION + +#define ENV_NET ENV_NET_FCT_BOOT \ + ENV_NET_FCT_NETARGS \ + ENV_BOOTARGS_DEFAULT diff --git a/roms/u-boot/include/configs/sifive-unleashed.h b/roms/u-boot/include/configs/sifive-unleashed.h new file mode 100644 index 000000000..0d69d1c54 --- /dev/null +++ b/roms/u-boot/include/configs/sifive-unleashed.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#ifdef CONFIG_SPL + +#define CONFIG_SPL_MAX_SIZE 0x00100000 +#define CONFIG_SPL_BSS_START_ADDR 0x85000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 + +#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \ + GENERATED_GBL_DATA_SIZE) + +#endif + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +#define CONFIG_SYS_MALLOC_LEN SZ_8M + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 + +#define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMER_FREQ 1000000 + +#define RISCV_SMODE_TIMER_FREQ 1000000 + +/* Environment options */ + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(SF, sf, 0) \ + func(DHCP, dhcp, na) + +#include +#include + +#define TYPE_GUID_LOADER1 "5B193300-FC78-40CD-8002-E86C45580B47" +#define TYPE_GUID_LOADER2 "2E54B353-1271-4842-806F-E436D6AF6985" +#define TYPE_GUID_SYSTEM "0FC63DAF-8483-4772-8E79-3D69D8477DE4" + +#define PARTS_DEFAULT \ + "name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \ + "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \ + "name=system,size=-,bootable,type=${type_guid_gpt_system};" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "scriptaddr=0x88100000\0" \ + "script_offset_f=0x1fff000\0" \ + "script_size_f=0x1000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ + "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \ + "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ + "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ + "partitions=" PARTS_DEFAULT "\0" \ + BOOTENV \ + BOOTENV_SF + +#define CONFIG_PREBOOT \ + "setenv fdt_addr ${fdtcontroladdr};" \ + "fdt addr ${fdtcontroladdr};" +#endif + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sifive-unmatched.h b/roms/u-boot/include/configs/sifive-unmatched.h new file mode 100644 index 000000000..4fad69bb1 --- /dev/null +++ b/roms/u-boot/include/configs/sifive-unmatched.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2020-2021 SiFive, Inc + * + * Authors: + * Pragnesh Patel + */ + +#ifndef __SIFIVE_UNMATCHED_H +#define __SIFIVE_UNMATCHED_H + +#include + +#ifdef CONFIG_SPL + +#define CONFIG_SPL_MAX_SIZE 0x00100000 +#define CONFIG_SPL_BSS_START_ADDR 0x85000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 + +#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \ + GENERATED_GBL_DATA_SIZE) + +#endif + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +#define CONFIG_SYS_MALLOC_LEN SZ_8M + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 + +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */ + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* Environment options */ + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(NVME, nvme, 0) \ + func(USB, usb, 0) \ + func(MMC, mmc, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#define TYPE_GUID_LOADER1 "5B193300-FC78-40CD-8002-E86C45580B47" +#define TYPE_GUID_LOADER2 "2E54B353-1271-4842-806F-E436D6AF6985" +#define TYPE_GUID_SYSTEM "0FC63DAF-8483-4772-8E79-3D69D8477DE4" + +#define PARTS_DEFAULT \ + "name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \ + "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \ + "name=system,size=-,bootable,type=${type_guid_gpt_system};" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ + "kernel_comp_addr_r=0x90000000\0" \ + "kernel_comp_size=0x4000000\0" \ + "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \ + "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ + "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ + "partitions=" PARTS_DEFAULT "\0" \ + BOOTENV + +#define CONFIG_PREBOOT \ + "setenv fdt_addr ${fdtcontroladdr};" \ + "fdt addr ${fdtcontroladdr};" +#endif /* CONFIG_SPL_BUILD */ + +#endif /* __SIFIVE_UNMATCHED_H */ diff --git a/roms/u-boot/include/configs/silinux-ek874.h b/roms/u-boot/include/configs/silinux-ek874.h new file mode 100644 index 000000000..25c0cd233 --- /dev/null +++ b/roms/u-boot/include/configs/silinux-ek874.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/silinux-ek874.h + * This file is Silicon Linux EK874 board configuration. + * + * Copyright (C) 2021 Renesas Electronics Corporation + */ + +#ifndef __SILINUX_EK874_H +#define __SILINUX_EK874_H + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_BITBANGMII_MULTI + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +#endif /* __SILINUX_EK874_H */ diff --git a/roms/u-boot/include/configs/silk.h b/roms/u-boot/include/configs/silk.h new file mode 100644 index 000000000..eee60fdfa --- /dev/null +++ b/roms/u-boot/include/configs/silk.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * include/configs/silk.h + * This file is silk board configuration. + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + */ + +#ifndef __SILK_H +#define __SILK_H + +#include "rcar-gen2-common.h" + +#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 +#define STACK_AREA_SIZE 0x00100000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) + +/* FLASH */ +#define CONFIG_SPI_FLASH_QUAD + +/* SH Ether */ +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" + +/* SPL support */ +#define CONFIG_SPL_STACK 0xe6340000 +#define CONFIG_SPL_MAX_SIZE 0x4000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIF2 +#define CONFIG_SH_SCIF_CLK_FREQ 65000000 +#endif + +#endif /* __SILK_H */ diff --git a/roms/u-boot/include/configs/sipeed-maix.h b/roms/u-boot/include/configs/sipeed-maix.h new file mode 100644 index 000000000..0fbe8a590 --- /dev/null +++ b/roms/u-boot/include/configs/sipeed-maix.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-20 Sean Anderson + */ + +#ifndef CONFIGS_SIPEED_MAIX_H +#define CONFIGS_SIPEED_MAIX_H + +#include + +#define CONFIG_SYS_LOAD_ADDR 0x80000000 +/* Start just below the second bank so we don't clobber it during reloc */ +#define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF +#define CONFIG_SYS_MALLOC_LEN SZ_128K +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_SIZE SZ_8M + +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80060000\0" \ + "fdt_addr_r=0x80400000\0" \ + "scriptaddr=0x80020000\0" \ + "kernel_addr_r=0x80060000\0" \ + "fdtfile=kendryte/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "k210_bootcmd=load mmc 0:1 $loadaddr /uImage && " \ + "load mmc 0:1 $fdt_addr_r /k210.dtb && " \ + "bootm $loadaddr - $fdt_addr_r\0" +#endif + +#endif /* CONFIGS_SIPEED_MAIX_H */ diff --git a/roms/u-boot/include/configs/slimbootloader.h b/roms/u-boot/include/configs/slimbootloader.h new file mode 100644 index 000000000..b8169072c --- /dev/null +++ b/roms/u-boot/include/configs/slimbootloader.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Intel Corporation + */ + +#ifndef __SLIMBOOTLOADER_CONFIG_H__ +#define __SLIMBOOTLOADER_CONFIG_H__ + +#include + +#define CONFIG_STD_DEVICES_SETTINGS \ + "stdin=serial,i8042-kbd,usbkbd\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +/* + * Override CONFIG_EXTRA_ENV_SETTINGS in x86-common.h + */ +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_STD_DEVICES_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=0x4000000\0" \ + "ramdiskfile=initrd\0" \ + "bootdev=usb\0" \ + "bootdevnum=0\0" \ + "bootdevpart=0\0" \ + "bootfsload=fatload\0" \ + "bootusb=setenv bootdev usb; boot\0" \ + "bootscsi=setenv bootdev scsi; boot\0" \ + "bootmmc=setenv bootdev mmc; boot\0" \ + "bootargs=console=ttyS0,115200 console=tty0\0" + +/* + * Override CONFIG_BOOTCOMMAND in x86-common.h + */ +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND \ + "if test ${bootdev} = \"usb\"; then ${bootdev} start; fi; " \ + "if test ${bootdev} = \"scsi\"; then ${bootdev} scan; fi; " \ + "${bootdev} info; " \ + "${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} " \ + "${loadaddr} ${bootfile}; " \ + "${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} " \ + "${ramdiskaddr} ${ramdiskfile}; " \ + "zboot ${loadaddr} 0 ${ramdiskaddr} ${filesize}" + +#endif /* __SLIMBOOTLOADER_CONFIG_H__ */ diff --git a/roms/u-boot/include/configs/smartweb.h b/roms/u-boot/include/configs/smartweb.h new file mode 100644 index 000000000..6e715dc0c --- /dev/null +++ b/roms/u-boot/include/configs/smartweb.h @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * (C) Copyright 2010 + * Achim Ehrlich + * taskit GmbH + * + * (C) Copyright 2012 + * Markus Hubig + * IMKO GmbH + * + * (C) Copyright 2014 + * Heiko Schocher + * DENX Software Engineering GmbH + * + * Configuation settings for the smartweb. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include +#include + +/* + * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot + * program. Since the linker has to swallow that define, we must use a pure + * hex number here! + */ + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ + +/* misc settings */ +#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */ +#define CONFIG_INITRD_TAG /* pass initrd param to kernel */ +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* U-Boot is loaded by a bootloader */ + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 32 + +/* setting board specific options */ +#define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB +#define CONFIG_SYS_AUTOLOAD "yes" +#define CONFIG_RESET_TO_RETRY + +/* The LED PINs */ +#define CONFIG_RED_LED AT91_PIN_PA9 +#define CONFIG_GREEN_LED AT91_PIN_PA6 + +/* + * SDRAM: 1 bank, 64 MB, base address 0x20000000 + * Already initialized before u-boot gets started. + */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE (64 * SZ_1M) + +/* + * Perform a SDRAM Memtest from the start of SDRAM + * till the beginning of the U-Boot position in RAM. + */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN \ + ROUND(3 * CONFIG_ENV_SIZE + (4 * SZ_1M), 0x1000) + +/* NAND flash settings */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ + +/* serial console */ +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS + +/* + * Ethernet configuration + * + */ +#define CONFIG_MACB +#define CONFIG_RMII /* use reduced MII inteface */ +#define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */ +#define CONFIG_AT91_WANTS_COMMON_PHY + +/* BOOTP and DHCP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_NFSBOOTCOMMAND \ + "setenv autoload yes; setenv autoboot yes; " \ + "setenv bootargs ${basicargs} ${mtdparts} " \ + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \ + "dhcp" + +#if !defined(CONFIG_SPL_BUILD) +/* USB configuration */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +/* USB DFU support */ + +#define CONFIG_USB_GADGET_AT91 + +/* DFU class support */ +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M +#define DFU_MANIFEST_POLL_TIMEOUT 25000 +#endif + +/* General Boot Parameter */ +#define CONFIG_BOOTCOMMAND "run flashboot" +#define CONFIG_SYS_CBSIZE 512 + +/* + * RAM Memory address where to put the + * Linux Kernel befor starting. + */ +#define CONFIG_SYS_LOAD_ADDR 0x22000000 + +/* + * The NAND Flash partitions: + */ +#define CONFIG_ENV_RANGE (SZ_512K) + +/* + * Predefined environment variables. + * Usefull to define some easy to use boot commands. + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + \ + "basicargs=console=ttyS0,115200\0" \ + \ + "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x301000 +#define CONFIG_SPL_STACK_R +#define CONFIG_SPL_STACK_R_ADDR CONFIG_SYS_TEXT_BASE +#else +/* + * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, + * leaving the correct space for initial global data structure above that + * address while providing maximum stack area below. + */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) +#endif + +/* Defines for SPL */ +#define CONFIG_SPL_MAX_SIZE (SZ_4K) + +#define CONFIG_SPL_BSS_START_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SPL_BSS_MAX_SIZE (SZ_16K) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN + +#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) +#define CONFIG_SYS_USE_NANDFLASH 1 +#define CONFIG_SPL_NAND_RAW_ONLY +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +#define CONFIG_SYS_NAND_SIZE (SZ_256M) +#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K +#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } + +#define CONFIG_SPL_ATMEL_SIZE +#define CONFIG_SYS_MASTER_CLOCK (198656000/2) +#define AT91_PLL_LOCK_TIMEOUT 1000000 +#define CONFIG_SYS_AT91_PLLA 0x2060bf09 +#define CONFIG_SYS_MCKR 0x100 +#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) +#define CONFIG_SYS_AT91_PLLB 0x10483f0e + +#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/smdk5250.h b/roms/u-boot/include/configs/smdk5250.h new file mode 100644 index 000000000..3af13673f --- /dev/null +++ b/roms/u-boot/include/configs/smdk5250.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Configuration settings for the SAMSUNG SMDK5250 board. + */ + +#ifndef __CONFIG_SMDK_H +#define __CONFIG_SMDK_H + +#include +#include +#include + +#undef CONFIG_EXYNOS_FB +#undef CONFIG_EXYNOS_DP +#undef CONFIG_KEYBOARD + +#define CONFIG_BOARD_COMMON + +#endif /* __CONFIG_SMDK_H */ diff --git a/roms/u-boot/include/configs/smdk5420.h b/roms/u-boot/include/configs/smdk5420.h new file mode 100644 index 000000000..d06dfe43a --- /dev/null +++ b/roms/u-boot/include/configs/smdk5420.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG SMDK5420 board. + */ + +#ifndef __CONFIG_SMDK5420_H +#define __CONFIG_SMDK5420_H + +#include +#include +#include + +#undef CONFIG_EXYNOS_FB +#undef CONFIG_EXYNOS_DP + +#undef CONFIG_KEYBOARD + +#define CONFIG_BOARD_COMMON + +#define CONFIG_SMDK5420 /* which is in a SMDK5420 */ + +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) + +/* USB */ +#define CONFIG_USB_XHCI_EXYNOS + +/* DRAM Memory Banks */ +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + +#endif /* __CONFIG_SMDK5420_H */ diff --git a/roms/u-boot/include/configs/smdkc100.h b/roms/u-boot/include/configs/smdkc100.h new file mode 100644 index 000000000..77773cdea --- /dev/null +++ b/roms/u-boot/include/configs/smdkc100.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang + * HeungJun Kim + * Inki Dae + * + * Configuation settings for the SAMSUNG SMDKC100 board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ +#define CONFIG_S5P 1 /* which is in a S5P Family */ +#define CONFIG_S5PC100 1 /* which is in a S5PC100 */ + +#include /* get chip and board defs */ + +/* input clock of PLL: SMDKC100 has 12MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 12000000 + +/* DRAM Base */ +#define CONFIG_SYS_SDRAM_BASE 0x30000000 + +/* Text Base */ + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG + +/* + * Size of malloc() pool + * 1MB = 0x100000, 0x100000 = 1024 * 1024 + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) + +/* + * select serial console configuration + */ + +/* PWM */ +#define CONFIG_PWM 1 + +#define CONFIG_BOOTCOMMAND "run ubifsboot" + +#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext2" \ + " console=ttySAC0,115200n8" \ + " mem=128M" + +#define CONFIG_COMMON_BOOT "console=ttySAC0,115200n8" \ + " mem=128M " \ + " " CONFIG_MTDPARTS_DEFAULT + +#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \ + " onenand write 0x32008000 0x0 0x40000\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_UPDATEB \ + "updatek=" \ + "onenand erase 0x60000 0x300000;" \ + "onenand write 0x31008000 0x60000 0x300000\0" \ + "updateu=" \ + "onenand erase block 147-4095;" \ + "onenand write 0x32000000 0x1260000 0x8C0000\0" \ + "bootk=" \ + "onenand read 0x30007FC0 0x60000 0x300000;" \ + "bootm 0x30007FC0\0" \ + "flashboot=" \ + "set bootargs root=/dev/mtdblock${bootblock} " \ + "rootfstype=${rootfstype} " \ + "ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT ";" \ + "run bootk\0" \ + "ubifsboot=" \ + "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ + " ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; " \ + "run bootk\0" \ + "boottrace=setenv opts initcall_debug; run bootcmd\0" \ + "android=" \ + "set bootargs root=ubi0!ramdisk ubi.mtd=${ubiblock} " \ + "rootfstype=ubifs init=/init.sh " CONFIG_COMMON_BOOT "; " \ + "run bootk\0" \ + "nfsboot=" \ + "set bootargs root=/dev/nfs ubi.mtd=${ubiblock} " \ + "nfsroot=${nfsroot},nolock " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:nowplus:usb0:off " CONFIG_COMMON_BOOT "; " \ + "run bootk\0" \ + "ramboot=" \ + "set bootargs " CONFIG_RAMDISK_BOOT \ + " initrd=0x33000000,8M ramdisk=8192\0" \ + "rootfstype=cramfs\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "meminfo=mem=128M\0" \ + "nfsroot=/nfsroot/arm\0" \ + "bootblock=5\0" \ + "ubiblock=4\0" \ + "ubi=enabled" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +/* memtest works on */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + +/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE (128 << 20) /* 0x8000000, 128 MB Bank #1 */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */ + +#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000) +#define CONFIG_ENABLE_MMU +#endif + +#ifdef CONFIG_ENABLE_MMU +#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000 +#else +#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE +#endif + +/*----------------------------------------------------------------------- + * Boot configuration + */ + +#define CONFIG_USE_ONENAND_BOARD_INIT +#define CONFIG_SAMSUNG_ONENAND 1 +#define CONFIG_SYS_ONENAND_BASE 0xE7100000 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) + +/* + * Ethernet Contoller driver + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/ +#endif /* CONFIG_CMD_NET */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/smdkv310.h b/roms/u-boot/include/configs/smdkv310.h new file mode 100644 index 000000000..fc2f6ecf6 --- /dev/null +++ b/roms/u-boot/include/configs/smdkv310.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 Samsung Electronics + * + * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "exynos4-common.h" + +#undef CONFIG_BOARD_COMMON +#undef CONFIG_USB_GADGET_DWC2_OTG_PHY +#undef CONFIG_REVISION_TAG + +/* High Level Configuration Options */ +#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ + +/* Mach Type */ +#define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310 + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +/* Handling Sleep Mode*/ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +/* MMC SPL */ +#define CONFIG_SKIP_LOWLEVEL_INIT +#define COPY_BL2_FNPTR_ADDR 0x00002488 + +#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" + +/* memtest works on */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + +/* SMDKV310 has 4 bank of DRAM */ +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE + +/* FLASH and environment organization */ + +#define CONFIG_CLK_1000_400_200 + +/* MIU (Memory Interleaving Unit) */ +#define CONFIG_MIU_2BIT_INTERLEAVED + +#define RESERVE_BLOCK_SIZE (512) +#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ + +#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) + +#define CONFIG_SYS_INIT_SP_ADDR 0x02040000 + +/* U-Boot copy size from boot Media to DRAM.*/ +#define COPY_BL2_SIZE 0x80000 +#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) +#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) + +/* Ethernet Controllor Driver */ +#ifdef CONFIG_CMD_NET +#define CONFIG_ENV_SROM_BANK 1 +#endif /*CONFIG_CMD_NET*/ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/smegw01.h b/roms/u-boot/include/configs/smegw01.h new file mode 100644 index 000000000..50f00136a --- /dev/null +++ b/roms/u-boot/include/configs/smegw01.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 NXP Semiconductors + * Copyright (C) 2021 Fabio Estevam + * + * Configuration settings for the smegw01 board. + */ + +#ifndef __SMEGW01_CONFIG_H +#define __SMEGW01_CONFIG_H + +#include "mx7_common.h" +#include + +#define PHYS_SDRAM_SIZE SZ_512M + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) + +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdtfile=imx7d-smegw01.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "bootm_size=0x10000000\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if run loadimage; then " \ + "run mmcboot; " \ + "fi; " \ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#endif diff --git a/roms/u-boot/include/configs/snapper9260.h b/roms/u-boot/include/configs/snapper9260.h new file mode 100644 index 000000000..f5f99ee0d --- /dev/null +++ b/roms/u-boot/include/configs/snapper9260.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Bluewater Systems Snapper 9260 and 9G20 modules + * + * (C) Copyright 2011 Bluewater Systems + * Author: Andre Renaud + * Author: Ryan Mallon + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* SoC type is defined in boards.cfg */ +#include +#include + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 + +/* CPU */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ +#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) + +/* Mem test settings */ + +/* NAND Flash */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R +#define CONFIG_AT91_WANTS_COMMON_PHY +#define CONFIG_TFTP_PORT +#define CONFIG_TFTP_TSIZE + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +/* GPIOs and IO expander */ +#define CONFIG_ATMEL_LEGACY +#define CONFIG_AT91_GPIO_PULLUP 1 +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} } + +/* UARTs/Serial console */ +#ifndef CONFIG_DM_SERIAL +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#endif + +/* I2C - Bit-bashed */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SOFT_SPEED 100000 +#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F +#define CONFIG_SOFT_I2C_READ_REPEATED_START +#define I2C_INIT do { \ + at91_set_gpio_output(AT91_PIN_PA23, 1); \ + at91_set_gpio_output(AT91_PIN_PA24, 1); \ + at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ + at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ + } while (0) +#define I2C_SOFT_DECLARATIONS +#define I2C_ACTIVE +#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1); +#define I2C_READ at91_get_gpio_value(AT91_PIN_PA23); +#define I2C_SDA(bit) do { \ + if (bit) { \ + at91_set_gpio_input(AT91_PIN_PA23, 1); \ + } else { \ + at91_set_gpio_output(AT91_PIN_PA23, 1); \ + at91_set_gpio_value(AT91_PIN_PA23, bit); \ + } \ + } while (0) +#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) +#define I2C_DELAY udelay(2) + +/* Boot options */ +#define CONFIG_SYS_LOAD_ADDR 0x23000000 + +#define CONFIG_BOOTP_BOOTFILESIZE + +/* Environment settings */ + +/* Console settings */ + +/* U-Boot memory settings */ +#define CONFIG_SYS_MALLOC_LEN (1 << 20) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/snapper9g45.h b/roms/u-boot/include/configs/snapper9g45.h new file mode 100644 index 000000000..bbd3b1187 --- /dev/null +++ b/roms/u-boot/include/configs/snapper9g45.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Bluewater Systems Snapper 9G45 module + * + * (C) Copyright 2011 Bluewater Systems + * Author: Andre Renaud + * Author: Ryan Mallon + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* SoC type is defined in boards.cfg */ +#include +#include + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 + +/* CPU */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ +#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) + +/* Mem test settings */ + +/* NAND Flash */ +#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R +#define CONFIG_AT91_WANTS_COMMON_PHY +#define CONFIG_TFTP_PORT +#define CONFIG_TFTP_TSIZE + +/* MMC */ +#define CONFIG_GENERIC_ATMEL_MCI + +/* LCD */ +#define CONFIG_ATMEL_LCD +#define CONFIG_GURNARD_SPLASH + +/* GPIOs and IO expander */ +#define CONFIG_ATMEL_LEGACY +#define CONFIG_AT91_GPIO_PULLUP 1 + +/* UARTs/Serial console */ + +/* Boot options */ +#define CONFIG_SYS_LOAD_ADDR 0x23000000 + +#define CONFIG_BOOTP_BOOTFILESIZE + +/* Environment settings */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ethaddr=00:00:00:00:00:00\0" \ + "serial=0\0" \ + "stdout=serial_atmel\0" \ + "stderr=serial_atmel\0" \ + "stdin=serial_atmel\0" \ + "bootlimit=3\0" \ + "loadaddr=0x71000000\0" \ + "board_rev=2\0" \ + "bootfile=/tftpboot/uImage\0" \ + "bootargs_def=console=ttyS0,115200 panic=5 quiet lpj=997376\0" \ + "nfsroot=/export/root\0" \ + "boot_working=setenv bootargs $bootargs_def; nboot $loadaddr 0 0x20c0000 && bootm\0" \ + "boot_safe=setenv bootargs $bootargs_def; nboot $loadaddr 0 0xc0000 && bootm\0" \ + "boot_tftp=setenv bootargs $bootargs_def ip=any nfsroot=$nfsroot; setenv autoload y && bootp && bootm\0" \ + "boot_usb=setenv bootargs $bootargs_def; usb start && usb storage && fatload usb 0:1 $loadaddr dds-xm200.bin && bootm\0" \ + "boot_mmc=setenv bootargs $bootargs_def; mmc rescan && fatload mmc 0:1 $loadaddr dds-xm200.bin && bootm\0" \ + "bootcmd=run boot_mmc ; run boot_usb ; run boot_working ; run boot_safe\0" \ + "altbootcmd=run boot_mmc ; run boot_usb ; run boot_safe ; run boot_working\0" + +/* Console settings */ + +/* U-Boot memory settings */ +#define CONFIG_SYS_MALLOC_LEN (1 << 20) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sniper.h b/roms/u-boot/include/configs/sniper.h new file mode 100644 index 000000000..4747e74b6 --- /dev/null +++ b/roms/u-boot/include/configs/sniper.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * LG Optimus Black codename sniper config + * + * Copyright (C) 2015 Paul Kocialkowski + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +/* + * CPU + */ + +#define CONFIG_ARM_ARCH_CP15_ERRATA + +/* + * Board + */ + +/* + * Clocks + */ + +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 + +#define V_NS16550_CLK 48000000 +#define V_OSCK 26000000 +#define V_SCLK (V_OSCK >> 1) + +/* + * DRAM + */ + +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * Memory + */ + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) + +/* + * I2C + */ + +#define CONFIG_SYS_I2C +#define CONFIG_I2C_MULTI_BUS + +/* + * Input + */ + +/* + * SPL + */ + +#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ + CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE (512 * 1024) +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SYS_CBSIZE 512 + +/* + * Serial + */ + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#endif + +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 + +#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ + 115200 } + +/* + * Environment + */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x82000000\0" \ + "loadaddr=0x82000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "fdtaddr=0x88000000\0" \ + "ramdisk_addr_r=0x88080000\0" \ + "pxefile_addr_r=0x80100000\0" \ + "scriptaddr=0x80000000\0" \ + "bootm_size=0x10000000\0" \ + "boot_mmc_dev=0\0" \ + "kernel_mmc_part=3\0" \ + "recovery_mmc_part=4\0" \ + "fdtfile=omap3-sniper.dtb\0" \ + "bootfile=/boot/extlinux/extlinux.conf\0" \ + "bootargs=console=ttyO2,115200 vram=5M,0x9FA00000 omapfb.vram=0:5M\0" + +/* + * ATAGs + */ + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SERIAL_TAG + +/* + * Boot + */ + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_BOOTCOMMAND \ + "setenv boot_mmc_part ${kernel_mmc_part}; " \ + "if test reboot-${reboot-mode} = reboot-r; then " \ + "echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; " \ + "if test reboot-${reboot-mode} = reboot-b; then " \ + "echo fastboot; fastboot 0; fi; " \ + "part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; " \ + "part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; " \ + "mmc dev ${boot_mmc_dev}; " \ + "mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && " \ + "bootm ${kernel_addr_r};" + +#endif diff --git a/roms/u-boot/include/configs/snow.h b/roms/u-boot/include/configs/snow.h new file mode 100644 index 000000000..c082b2d82 --- /dev/null +++ b/roms/u-boot/include/configs/snow.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5 Snow board. + */ + +#ifndef __CONFIG_SNOW_H +#define __CONFIG_SNOW_H + +#define EXYNOS_FDTFILE_SETTING \ + "fdtfile=exynos5250-snow.dtb\0" + +#include +#include +#include + +#define CONFIG_BOARD_COMMON + +#endif /* __CONFIG_SNOW_H */ diff --git a/roms/u-boot/include/configs/socfpga_agilex_socdk.h b/roms/u-boot/include/configs/socfpga_agilex_socdk.h new file mode 100644 index 000000000..4eede7c84 --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_agilex_socdk.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2019 Intel Corporation + * + */ + +#ifndef __CONFIG_SOCFGPA_AGILEX_H__ +#define __CONFIG_SOCFGPA_AGILEX_H__ + +#include + +#endif /* __CONFIG_SOCFGPA_AGILEX_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_arria10_socdk.h b/roms/u-boot/include/configs/socfpga_arria10_socdk.h new file mode 100644 index 000000000..645e66e6b --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_arria10_socdk.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2015-2019 Altera Corporation + */ + +#ifndef __CONFIG_SOCFGPA_ARRIA10_H__ +#define __CONFIG_SOCFGPA_ARRIA10_H__ + +#include + +/* Booting Linux */ +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * U-Boot general configurations + */ + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 + +/* + * Serial / UART configurations + */ +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +/* + * L4 OSC1 Timer 0 + */ +/* reload value when timer count to zero */ +#define TIMER_LOAD_VAL 0xFFFFFFFF + +/* + * Flash configurations + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* SPL memory allocation configuration, this is for FAT implementation */ +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000 + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_arria5_secu1.h b/roms/u-boot/include/configs/socfpga_arria5_secu1.h new file mode 100644 index 000000000..c25d6bd82 --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_arria5_secu1.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017-2020 Hitachi Power Grids + * + */ +#ifndef __CONFIG_SOCFPGA_SECU1_H__ +#define __CONFIG_SOCFPGA_SECU1_H__ + +#include +#include + +/* Call misc_init_r */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_HUSH_INIT_VAR +/* Eternal oscillator */ +#define CONFIG_SYS_TIMER_RATE 40000000 + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512MiB on SECU1 */ + +/* + * We use bootcounter in i2c nvram of the RTC (0x68) + * The offset fopr the bootcounter is 0x9e, which are + * the last two bytes of the 128 bytes large NVRAM in the + * RTC which begin at address 0x20 + */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* Booting Linux */ +#define CONFIG_BOOTFILE "zImage" + +#define CONFIG_BOOTCOMMAND \ + "setenv bootcmd '" \ + "bridge enable; " \ + "if test ${bootnum} = \"b\"; " \ + "then run _fpga_loadsafe; " \ + "else if test ${bootcount} -eq 4; then echo \"Switching copy...\"; setexpr x $bootnum % 2 && setexpr bootnum $x + 1; saveenv; fi; " \ + "run _fpga_loaduser; " \ + "fi;" \ + "echo \"Booting bank $bootnum\" && run userload && run userboot;" \ + "' && " \ + "setenv altbootcmd 'setenv bootnum b && saveenv && boot;' && " \ + "saveenv && saveenv && boot;" + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SYS_BOOTM_LEN (64 << 20) + +/* Environment settings */ + +/* + * Autoboot + * + * After 45s of inactivity in the prompt, the board will reset. + * Set 'bootretry' in the environment to -1 to disable this behavior + */ +#define CONFIG_BOOT_RETRY_TIME 45 +#define CONFIG_RESET_TO_RETRY + +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_KM_KERNEL_ADDR + +/* + * FPGA Remote Update related environment + * + * Note that since those commands access the FPGA, the HPS-to-FPGA + * bridges MUST have been previously enabled (for example + * with 'bridge enable'). + */ +#define FPGA_RMTU_ENV \ + "rmtu_page=0xFF29000C\0" \ + "rmtu_reconfig=0xFF290018\0" \ + "fpga_safebase=0x0\0" \ + "fpga_userbase=0x2000000\0" \ + "_fpga_loaduser=echo Loading FPGA USER image..." \ + " && mw ${rmtu_page} ${fpga_userbase} && mw ${rmtu_reconfig} 1\0" \ + "_fpga_loadsafe=echo Loading FPGA SAFE image..." \ + " && mw ${rmtu_page} ${fpga_safebase} && mw ${rmtu_reconfig} 1\0" \ + +#define CONFIG_KM_NEW_ENV \ + "newenv=" \ + "nand erase 0x100000 0x40000\0" + +#define CONFIG_KM_DEF_ENV_BOOTTARGETS \ + "release=" \ + "run newenv; reset\0" \ + "develop=" \ + "tftp 0x200000 scripts/develop-secu.txt && env import -t 0x200000 ${filesize} && saveenv && reset\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + FPGA_RMTU_ENV \ + CONFIG_KM_DEF_ENV_BOOTTARGETS \ + CONFIG_KM_NEW_ENV \ + "socfpga_legacy_reset_compat=1\0" \ + "altbootcmd=run bootcmd;\0" \ + "bootlimit=6\0" \ + "bootnum=1\0" \ + "bootretry=" __stringify(CONFIG_BOOT_RETRY_TIME) "\0" \ + "fdt_addr=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ + "load=tftpboot ${loadaddr} u-boot-with-nand-spl.sfp\0" \ + "loadaddr=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "update=nand erase 0x0 0x00100000 && nand write ${loadaddr} 0x0 ${filesize}\0" \ + "userload=ubi part nand.ubi &&" \ + "ubi check rootfs$bootnum &&" \ + "ubi read $fdt_addr dtb$bootnum &&" \ + "ubi read $loadaddr kernel$bootnum\0" \ + "userboot=setenv bootargs " CONFIG_BOOTARGS \ + " ubi.mtd=1 ubi.block=0,rootfs$bootnum root=/dev/ubiblock0_$ubivolid" \ + " ro rootfstype=squashfs init=sbin/preinit;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "verify=y\0" + +/* The rest of the configuration is shared */ +#include + +#ifdef CONFIG_SPL_NAND_SUPPORT +#undef CONFIG_SYS_NAND_U_BOOT_OFFS +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#endif + +#undef CONFIG_WATCHDOG_TIMEOUT_MSECS +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 + +#endif /* __CONFIG_SOCFPGA_SECU1_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_arria5_socdk.h b/roms/u-boot/include/configs/socfpga_arria5_socdk.h new file mode 100644 index 000000000..af6137aeb --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_arria5_socdk.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Marek Vasut + */ +#ifndef __CONFIG_SOCFPGA_ARRIA5_H__ +#define __CONFIG_SOCFPGA_ARRIA5_H__ + +#include + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ + +/* Booting Linux */ +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_common.h b/roms/u-boot/include/configs/socfpga_common.h new file mode 100644 index 000000000..62b327cd6 --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_common.h @@ -0,0 +1,254 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Altera Corporation + */ +#ifndef __CONFIG_SOCFPGA_COMMON_H__ +#define __CONFIG_SOCFPGA_COMMON_H__ + +#include + +/* + * High level configuration + */ +#define CONFIG_CLOCKS + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * Memory configurations + */ +#define PHYS_SDRAM_1 0x0 +#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE +#define CONFIG_SPL_PAD_TO 0x10000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CONFIG_SPL_PAD_TO 0x40000 +/* SPL memory allocation configuration, this is for FAT implementation */ +#ifndef CONFIG_SYS_SPL_MALLOC_SIZE +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 +#endif +#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ + CONFIG_SYS_SPL_MALLOC_SIZE) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE) +#endif + +/* + * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal + * SRAM as bootcounter storage. Make sure to not put the stack directly + * at this address to not overwrite the bootcounter by checking, if the + * bootcounter address is located in the internal SRAM. + */ +#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ + (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE))) +#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR +#else +#define CONFIG_SPL_STACK \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) +#endif + +/* + * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc + * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage + * in U-Boot pre-reloc is higher than in SPL. + */ +#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR +#else +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK +#endif + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ + +/* + * Cache + */ +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS + +/* + * Ethernet on SoC (EMAC) + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_DW_ALTDESCRIPTOR +#endif + +/* + * FPGA Driver + */ +#ifdef CONFIG_CMD_FPGA +#define CONFIG_FPGA_COUNT 1 +#endif + +/* + * L4 OSC1 Timer 0 + */ +#ifndef CONFIG_TIMER +#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) +#ifndef CONFIG_SYS_TIMER_RATE +#define CONFIG_SYS_TIMER_RATE 25000000 +#endif +#endif + +/* + * L4 Watchdog + */ +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS +#define CONFIG_DW_WDT_CLOCK_KHZ 25000 + +/* + * MMC Driver + */ +#ifdef CONFIG_CMD_MMC +/* FIXME */ +/* using smaller max blk cnt to avoid flooding the limited stack we have */ +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ +#endif + +/* + * NAND Support + */ +#ifdef CONFIG_NAND_DENALI +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS +#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS +#endif + +/* + * QSPI support + */ +/* QSPI reference clock */ +#ifndef __ASSEMBLY__ +unsigned int cm_get_qspi_controller_clk_hz(void); +#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() +#endif + +/* + * USB + */ + +/* + * USB Gadget (DFU, UMS) + */ +#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* USB IDs */ +#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 +#endif + +/* + * U-Boot environment + */ + +/* Environment for SDMMC boot */ + +/* Environment for QSPI boot */ + +/* + * SPL + * + * SRAM Memory layout for gen 5: + * + * 0xFFFF_0000 ...... Start of SRAM + * 0xFFFF_xxxx ...... Top of stack (grows down) + * 0xFFFF_yyyy ...... Global Data + * 0xFFFF_zzzz ...... Malloc area + * 0xFFFF_FFFF ...... End of SRAM + * + * SRAM Memory layout for Arria 10: + * 0xFFE0_0000 ...... Start of SRAM (bottom) + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) + * 0xFFEy_yyyy ...... Global Data + * 0xFFEz_zzzz ...... Malloc area (grows up to top) + * 0xFFE3_FFFF ...... End of SRAM (top) + */ +#ifndef CONFIG_SPL_TEXT_BASE +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE +#endif + +/* SPL SDMMC boot support */ +#ifdef CONFIG_SPL_MMC_SUPPORT +#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif +#else +#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 +#endif +#endif + +/* SPL QSPI boot support */ + +/* SPL NAND boot support */ +#ifdef CONFIG_SPL_NAND_SUPPORT +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000 +#endif +#endif + +/* Extra Environment */ +#ifndef CONFIG_SPL_BUILD + +#ifdef CONFIG_CMD_DHCP +#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +#define BOOT_TARGET_DEVICES_DHCP(func) +#endif + +#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) +#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) +#else +#define BOOT_TARGET_DEVICES_PXE(func) +#endif + +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_PXE(func) \ + BOOT_TARGET_DEVICES_DHCP(func) + +#include + +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "bootm_size=0xa000000\0" \ + "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ + "fdt_addr_r=0x02000000\0" \ + "scriptaddr=0x02100000\0" \ + "pxefile_addr_r=0x02200000\0" \ + "ramdisk_addr_r=0x02300000\0" \ + "socfpga_legacy_reset_compat=1\0" \ + BOOTENV + +#endif +#endif + +#endif /* __CONFIG_SOCFPGA_COMMON_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_cyclone5_socdk.h b/roms/u-boot/include/configs/socfpga_cyclone5_socdk.h new file mode 100644 index 000000000..028db2a09 --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_cyclone5_socdk.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Marek Vasut + */ +#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ +#define __CONFIG_SOCFPGA_CYCLONE5_H__ + +#include + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ + +/* Booting Linux */ +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_dbm_soc1.h b/roms/u-boot/include/configs/socfpga_dbm_soc1.h new file mode 100644 index 000000000..bffedcb75 --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_dbm_soc1.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Marek Vasut + */ +#ifndef __CONFIG_DEVBOARDS_DBM_SOC1_H__ +#define __CONFIG_DEVBOARDS_DBM_SOC1_H__ + +#include + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ + +/* Booting Linux */ +#define CONFIG_BOOTFILE "fitImage" +#define CONFIG_BOOTCOMMAND "run mmc_mmc" +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Environment is in MMC */ + +/* Extra Environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "consdev=ttyS0\0" \ + "baudrate=115200\0" \ + "bootscript=boot.scr\0" \ + "bootdev=/dev/mmcblk0p2\0" \ + "rootdev=/dev/mmcblk0p3\0" \ + "netdev=eth0\0" \ + "hostname=dbm_soc1\0" \ + "kernel_addr_r=0x10000000\0" \ + "dfu_alt_info=mmc raw 0 3867148288\0" \ + "update_filename=u-boot-with-spl.sfp\0" \ + "update_sd_offset=0x800\0" \ + "update_sd=" /* Update the SD firmware partition */ \ + "if mmc rescan ; then " \ + "if tftp ${update_filename} ; then " \ + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ + "setexpr fw_sz ${fw_sz} + 1 ; " \ + "mmc write ${loadaddr} ${update_sd_offset} ${fw_sz} ; " \ + "fi ; " \ + "fi\0" \ + "fpga_filename=output_file.rbf\0" \ + "load_fpga=" /* Load FPGA bitstream */ \ + "if tftp ${fpga_filename} ; then " \ + "fpga load 0 $loadaddr $filesize ; " \ + "bridge enable ; " \ + "fi\0" \ + "addcons=" \ + "setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off\0" \ + "addmisc=" \ + "setenv bootargs ${bootargs} ${miscargs}\0" \ + "addargs=run addcons addmisc\0" \ + "mmcload=" \ + "mmc rescan ; " \ + "load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \ + "netload=" \ + "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ + "miscargs=nohlt panic=1\0" \ + "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ + "nfsargs=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ + "mmc_mmc=" \ + "run mmcload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "mmc_nfs=" \ + "run mmcload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_mmc=" \ + "run netload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_nfs=" \ + "run netload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "try_bootscript=" \ + "mmc rescan;" \ + "if test -e mmc 0:2 ${bootscript} ; then " \ + "if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \ + "then ; " \ + "echo Running bootscript... ; " \ + "source ${kernel_addr_r} ; " \ + "fi ; " \ + "fi\0" \ + "socfpga_legacy_reset_compat=1\0" + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_DEVBOARDS_DBM_SOC1_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_de0_nano_soc.h b/roms/u-boot/include/configs/socfpga_de0_nano_soc.h new file mode 100644 index 000000000..21108e344 --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_de0_nano_soc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Marek Vasut + */ +#ifndef __CONFIG_TERASIC_DE0_H__ +#define __CONFIG_TERASIC_DE0_H__ + +#include + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ + +/* Booting Linux */ +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_TERASIC_DE0_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_de10_nano.h b/roms/u-boot/include/configs/socfpga_de10_nano.h new file mode 100644 index 000000000..d85f98fbd --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_de10_nano.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017, Intel Corporation + */ +#ifndef __CONFIG_TERASIC_DE10_H__ +#define __CONFIG_TERASIC_DE10_H__ + +#include + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ + +/* Booting Linux */ +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_TERASIC_DE10_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_de1_soc.h b/roms/u-boot/include/configs/socfpga_de1_soc.h new file mode 100644 index 000000000..9919d292d --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_de1_soc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Marek Vasut + */ +#ifndef __CONFIG_TERASIC_DE1_SOC_H__ +#define __CONFIG_TERASIC_DE1_SOC_H__ + +#include + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ + +/* Booting Linux */ +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_TERASIC_DE1_SOC_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_is1.h b/roms/u-boot/include/configs/socfpga_is1.h new file mode 100644 index 000000000..c4da5947f --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_is1.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Marek Vasut + * Copyright (C) 2016 Pavel Machek + */ +#ifndef __CONFIG_SOCFPGA_IS1_H__ +#define __CONFIG_SOCFPGA_IS1_H__ + +#include + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x10000000 + +/* Booting Linux */ +#define CONFIG_BOOTFILE "zImage" +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_ARP_TIMEOUT 500UL +#endif + +/* The rest of the configuration is shared */ +#include + +/* + * Bootcounter + */ +#define CONFIG_SYS_BOOTCOUNT_BE + +#endif /* __CONFIG_SOCFPGA_IS1_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_mcvevk.h b/roms/u-boot/include/configs/socfpga_mcvevk.h new file mode 100644 index 000000000..50c596170 --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_mcvevk.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Marek Vasut + */ +#ifndef __CONFIG_ARIES_MCVEVK_H__ +#define __CONFIG_ARIES_MCVEVK_H__ + +#include + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on MCV */ + +/* Booting Linux */ +#define CONFIG_BOOTFILE "fitImage" +#define CONFIG_BOOTCOMMAND "run mmc_mmc" +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Environment is in MMC */ + +/* Extra Environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "consdev=ttyS0\0" \ + "baudrate=115200\0" \ + "bootscript=boot.scr\0" \ + "setuuid=part uuid mmc 0:3 uuid\0" \ + "netdev=eth0\0" \ + "hostname=mcvevk\0" \ + "kernel_addr_r=0x10000000\0" \ + "socfpga_legacy_reset_compat=1\0" \ + "bootm_size=0xa000000\0" \ + "dfu_alt_info=mmc raw 0 3867148288\0" \ + "update_filename=u-boot-with-spl.sfp\0" \ + "update_sd_offset=0x800\0" \ + "update_sd=" /* Update the SD firmware partition */ \ + "if mmc rescan ; then " \ + "if tftp ${update_filename} ; then " \ + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ + "setexpr fw_sz ${fw_sz} + 1 ; " \ + "mmc write ${loadaddr} ${update_sd_offset} ${fw_sz} ; " \ + "fi ; " \ + "fi\0" \ + "update_qspi_offset=0x0\0" \ + "update_qspi=" /* Update the QSPI firmware */ \ + "if sf probe ; then " \ + "if tftp ${update_filename} ; then " \ + "sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \ + "fi ; " \ + "fi\0" \ + "fpga_filename=output_file.rbf\0" \ + "load_fpga=" /* Load FPGA bitstream */ \ + "if tftp ${fpga_filename} ; then " \ + "fpga load 0 $loadaddr $filesize ; " \ + "bridge enable ; " \ + "fi\0" \ + "addcons=" \ + "setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off\0" \ + "addmisc=" \ + "setenv bootargs ${bootargs} ${miscargs}\0" \ + "addargs=run addcons addmisc\0" \ + "mmcload=" \ + "mmc rescan ; " \ + "load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \ + "netload=" \ + "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ + "miscargs=nohlt panic=1\0" \ + "mmcargs=setenv bootargs root=PARTUUID=${uuid} rw rootwait\0" \ + "nfsargs=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ + "mmc_mmc=" \ + "run mmcload setuuid mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "mmc_nfs=" \ + "run mmcload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_mmc=" \ + "run netload setuuid mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_nfs=" \ + "run netload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "try_bootscript=" \ + "mmc rescan;" \ + "if test -e mmc 0:2 ${bootscript} ; then " \ + "if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \ + "then ; " \ + "echo Running bootscript... ; " \ + "source ${kernel_addr_r} ; " \ + "fi ; " \ + "fi\0" + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_ARIES_MCVEVK_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_soc64_common.h b/roms/u-boot/include/configs/socfpga_soc64_common.h new file mode 100644 index 000000000..38fd775b5 --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_soc64_common.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2017-2019 Intel Corporation + * + */ + +#ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__ +#define __CONFIG_SOCFPGA_SOC64_COMMON_H__ + +#include +#include +#include + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_LOADADDR 0x2000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_REMAKE_ELF +/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ +#define CPU_RELEASE_ADDR 0xFFD12210 +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* + * U-Boot console configurations + */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Extend size of kernel image for uncompression */ +#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) + +/* + * U-Boot run time memory configurations + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \ + + CONFIG_SYS_INIT_RAM_SIZE \ + - SOC64_HANDOFF_SIZE) +#else +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE \ + + 0x100000) +#endif +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) +#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) + +/* + * U-Boot environment configurations + */ + +/* + * QSPI support + */ + #ifdef CONFIG_CADENCE_QSPI +/* Enable it if you want to use dual-stacked mode */ +/*#define CONFIG_QSPI_RBF_ADDR 0x720000*/ + +/* Flash device info */ + +/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nor0=ff705000.spi.0" +#endif /* CONFIG_SPL_BUILD */ + +#ifndef __ASSEMBLY__ +unsigned int cm_get_qspi_controller_clk_hz(void); +#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() +#endif + +#endif /* CONFIG_CADENCE_QSPI */ + +/* + * Environment variable + */ + +#ifdef CONFIG_FIT +#define CONFIG_BOOTFILE "kernel.itb" +#else +#define CONFIG_BOOTFILE "Image" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootfile=" CONFIG_BOOTFILE "\0" \ + "fdt_addr=8000000\0" \ + "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "booti ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootfile};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootm ${loadaddr}\0" \ + "mmcfitload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootfile}\0" \ + "linux_qspi_enable=if sf probe; then " \ + "echo Enabling QSPI at Linux DTB...;" \ + "fdt addr ${fdt_addr}; fdt resize;" \ + "fdt set /soc/spi@ff8d2000 status okay;" \ + "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \ + " ${qspi_clock}; fi; \0" \ + "scriptaddr=0x02100000\0" \ + "scriptfile=u-boot.scr\0" \ + "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ + "then source ${scriptaddr}; fi\0" \ + "socfpga_legacy_reset_compat=1\0" + +/* + * Generic Interrupt Controller Definitions + */ +#define CONFIG_GICV2 + +/* + * External memory configurations + */ +#define PHYS_SDRAM_1 0x0 +#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) +#define CONFIG_SYS_SDRAM_BASE 0 + +/* + * Serial / UART configurations + */ +#define CONFIG_SYS_NS16550_CLK 100000000 +#define CONFIG_SYS_NS16550_MEM32 + +/* + * Timer & watchdog configurations + */ +#define COUNTER_FREQUENCY 400000000 + +/* + * SDMMC configurations + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 +#endif +/* + * Flash configurations + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_DW_ALTDESCRIPTOR +#endif /* CONFIG_CMD_NET */ + +/* + * L4 Watchdog + */ +#ifndef CONFIG_SPL_BUILD +#undef CONFIG_HW_WATCHDOG +#undef CONFIG_DESIGNWARE_WATCHDOG +#endif +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS +#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +#ifndef __ASSEMBLY__ +unsigned int cm_get_l4_sys_free_clk_hz(void); +#define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) +#endif +#else +#define CONFIG_DW_WDT_CLOCK_KHZ 100000 +#endif + +/* + * SPL memory layout + * + * On chip RAM + * 0xFFE0_0000 ...... Start of OCRAM + * SPL code, rwdata + * empty space + * 0xFFEx_xxxx ...... Top of stack (grows down) + * 0xFFEy_yyyy ...... Global Data + * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN) + * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB) + * 0xFFE3_FFFF ...... End of OCRAM + * + * SDRAM + * 0x0000_0000 ...... Start of SDRAM_1 + * unused / empty space for image loading + * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE) + * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE) + * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) + * + */ +#define CONFIG_SPL_TARGET "spl/u-boot-spl-dtb.hex" +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \ + - CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \ + - CONFIG_SYS_SPL_MALLOC_SIZE) + +/* SPL SDMMC boot support */ +#ifdef CONFIG_SPL_LOAD_FIT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" +#else +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif + +#endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_sockit.h b/roms/u-boot/include/configs/socfpga_sockit.h new file mode 100644 index 000000000..972999949 --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_sockit.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Marek Vasut + */ +#ifndef __CONFIG_TERASIC_SOCKIT_H__ +#define __CONFIG_TERASIC_SOCKIT_H__ + +#include + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ + +/* Booting Linux */ +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_TERASIC_SOCKIT_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_socrates.h b/roms/u-boot/include/configs/socfpga_socrates.h new file mode 100644 index 000000000..7faea150a --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_socrates.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Marek Vasut + */ +#ifndef __CONFIG_SOCFPGA_SOCRATES_H__ +#define __CONFIG_SOCFPGA_SOCRATES_H__ + +#include + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */ + +/* Booting Linux */ +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_SOCFPGA_SOCRATES_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_sr1500.h b/roms/u-boot/include/configs/socfpga_sr1500.h new file mode 100644 index 000000000..ccaa050ae --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_sr1500.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Stefan Roese + */ +#ifndef __CONFIG_SOCFPGA_SR1500_H__ +#define __CONFIG_SOCFPGA_SR1500_H__ + +#include + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ + +/* Booting Linux */ +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Ethernet on SoC (EMAC) */ +#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII +/* The PHY is autodetected, so no MII PHY address is needed here */ +#define PHY_ANEG_TIMEOUT 8000 + +/* Enable SPI NOR flash reset, needed for SPI booting */ +#define CONFIG_SPI_N25Q256A_RESET + +/* + * Bootcounter + */ +#define CONFIG_SYS_BOOTCOUNT_BE + +/* Environment setting for SPI flash */ + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_SOCFPGA_SR1500_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_stratix10_socdk.h b/roms/u-boot/include/configs/socfpga_stratix10_socdk.h new file mode 100644 index 000000000..09b46ba01 --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_stratix10_socdk.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2017-2019 Intel Corporation + * + */ + +#ifndef __CONFIG_SOCFGPA_STRATIX10_H__ +#define __CONFIG_SOCFGPA_STRATIX10_H__ + +#include + +#endif /* __CONFIG_SOCFGPA_STRATIX10_H__ */ diff --git a/roms/u-boot/include/configs/socfpga_vining_fpga.h b/roms/u-boot/include/configs/socfpga_vining_fpga.h new file mode 100644 index 000000000..06976d804 --- /dev/null +++ b/roms/u-boot/include/configs/socfpga_vining_fpga.h @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015-2019 Marek Vasut + */ +#ifndef __CONFIG_SOFTING_VINING_FPGA_H__ +#define __CONFIG_SOFTING_VINING_FPGA_H__ + +#include + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */ + +/* Booting Linux */ +#define CONFIG_BOOTFILE "fitImage" +#define CONFIG_BOOTCOMMAND "run selboot" +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MiB */ +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Ethernet on SoC (EMAC) */ + +/* Extra Environment */ +#define CONFIG_HOSTNAME "socfpga_vining_fpga" + +/* + * Active LOW GPIO buttons: + * A: GPIO 77 ... the button between USB B and ethernet + * B: GPIO 78 ... the button between USB A ports + * + * The logic: + * if button B is pressed, boot recovery system after 10 seconds + * if force_boottype is set, boot system depending on the value in the + * $force_boottype variable after 1 second + * if button B is not pressed and force_boottype is not set, boot normal + * Linux system after 5 seconds + */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "consdev=ttyS0\0" \ + "baudrate=115200\0" \ + "bootscript=boot.scr\0" \ + "ubimtdnr=5\0" \ + "ubimtd=rootfs\0" \ + "ubipart=ubi0:vining-fpga-rootfs\0" \ + "ubisfcs=1\0" /* Default is flash at CS#1 */ \ + "netdev=eth0\0" \ + "hostname=vining_fpga\0" \ + "kernel_addr_r=0x10000000\0" \ + "fdt_addr_r=0x20000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "dfu_alt_info=qspi0 sf 0:0;qspi1 sf 0:1\0" \ + "mtdparts_0_16m=ff705000.spi.0:" /* 16MiB+128MiB SF config */ \ + "1m(u-boot)," \ + "64k(env1)," \ + "64k(env2)," \ + "256k(softing1)," \ + "256k(softing2)," \ + "-(rcvrfs)\0" /* Recovery */ \ + "mtdparts_0_256m=ff705000.spi.0:" /* 256MiB(+256MiB) config */ \ + "1m(u-boot)," \ + "64k(env1)," \ + "64k(env2)," \ + "256k(softing1)," \ + "256k(softing2)," \ + "14720k(rcvrfs)," /* Recovery */ \ + "64m(rootfs)," /* Root */ \ + "-(userfs)\0" /* User */ \ + "mtdparts_1_128m=ff705000.spi.1:" /* 16MiB+128MiB SF config */ \ + "64m(rootfs)," \ + "-(userfs)\0" \ + "mtdparts_1_256m=ff705000.spi.1:" /* 256MiB+256MiB SF config */ \ + "-(userfs2)\0" \ + "update_filename=u-boot-with-spl-dtb.sfp\0" \ + "update_qspi_offset=0x0\0" \ + "update_qspi=" /* Update the QSPI firmware */ \ + "if sf probe ; then " \ + "if tftp ${update_filename} ; then " \ + "sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \ + "fi ; " \ + "fi\0" \ + "sf_identify=" \ + "setenv sf_size_0 ; setenv sf_size_1 ; " \ + "sf probe 0:0 && setenv sf_size_0 ${sf_size} ; " \ + "sf probe 0:1 && setenv sf_size_1 ${sf_size} ; " \ + "if test -z \"${sf_size_1}\" ; then " \ + /* 1x256MiB SF */ \ + "setenv mtdparts_0 ${mtdparts_0_256m} ; " \ + "setenv mtdparts_1 ; " \ + "elif test \"${sf_size_0}\" = \"1000000\" ; then " \ + /* 16MiB+128MiB SF */ \ + "setenv mtdparts_0 ${mtdparts_0_16m} ; " \ + "setenv mtdparts_1 ${mtdparts_1_128m} ; " \ + "else " \ + /* 256MiB+256MiB SF */ \ + "setenv mtdparts_0 ${mtdparts_0_256m} ; " \ + "setenv mtdparts_1 ${mtdparts_1_256m} ; " \ + "fi\0" \ + "fpga_filename=output_file.rbf\0" \ + "load_fpga=" /* Load FPGA bitstream */ \ + "if tftp ${fpga_filename} ; then " \ + "fpga load 0 $loadaddr $filesize ; " \ + "bridge enable ; " \ + "fi\0" \ + "addcons=" \ + "setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off\0" \ + "addmisc=" \ + "setenv bootargs ${bootargs} ${miscargs}\0" \ + "addmtd=" \ + "if test -z \"${sf_size_1}\" ; then " \ + "setenv mtdparts \"${mtdparts_0}\" ; " \ + "else " \ + "setenv mtdparts \"${mtdparts_0};${mtdparts_1}\" ; " \ + "fi ; " \ + "setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \ + "addargs=run addcons addmtd addmisc\0" \ + "ubiload=" \ + "ubi part ${ubimtd} ; ubifsmount ${ubipart} ; " \ + "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \ + "netload=" \ + "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ + "miscargs=nohlt panic=1\0" \ + "ubiargs=" \ + "setenv bootargs ubi.mtd=${ubimtdnr} " \ + "root=${ubipart} rootfstype=ubifs\0" \ + "nfsargs=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ + "ubi_sfsel=" \ + "if test \"${boottype}\" = \"rcvr\" ; then " \ + "setenv ubisfcs 0 ; " \ + "setenv ubimtd rcvrfs ; " \ + "setenv ubimtdnr 5 ; " \ + "setenv mtdparts mtdparts=${mtdparts_0} ; " \ + "setenv mtdids nor0=ff705000.spi.0 ; " \ + "setenv ubipart ubi0:vining-fpga-rootfs ; " \ + "else " \ + "if test \"${sf_size_0}\" = \"1000000\" ; then "\ + /* 16MiB+128MiB SF */ \ + "setenv ubisfcs 1 ; " \ + "setenv ubimtd rootfs ; " \ + "setenv ubimtdnr 6 ; " \ + "setenv mtdparts mtdparts=${mtdparts_1} ; " \ + "setenv mtdids nor0=ff705000.spi.1 ; " \ + "setenv ubipart ubi0:vining-fpga-rootfs ; " \ + "else " \ + /* 256MiB(+256MiB) SF */ \ + "setenv ubisfcs 0 ; " \ + "setenv ubimtd rootfs ; " \ + "setenv ubimtdnr 6 ; " \ + "setenv mtdparts mtdparts=${mtdparts_0} ; " \ + "setenv mtdids nor0=ff705000.spi.0 ; " \ + "setenv ubipart ubi0:vining-fpga-rootfs ; " \ + "fi ; " \ + "fi ; " \ + "sf probe 0:${ubisfcs}\0" \ + "boot_kernel=" \ + "if test -z \"${sf_size_1}\" ; then " /* 1x256MiB SF */ \ + "imxtract ${kernel_addr_r} fdt@1 ${fdt_addr_r} && " \ + "fdt addr ${fdt_addr_r} && " \ + "fdt resize && " \ + "fdt set /soc/spi@ff705000/n25q00@1 status disabled && " \ + "bootm ${kernel_addr_r}:kernel@1 - ${fdt_addr_r} ; " \ + "else " \ + "bootm ${kernel_addr_r} ; " \ + "fi\0" \ + "ubi_ubi=" \ + "run ubi_sfsel ubiload ubiargs addargs boot_kernel\0" \ + "ubi_nfs=" \ + "run ubiload nfsargs addip addargs boot_kernel\0" \ + "net_ubi=" \ + "run netload ubiargs addargs boot_kernel\0" \ + "net_nfs=" \ + "run netload nfsargs addip addargs boot_kernel\0" \ + "selboot=" /* Select from where to boot. */ \ + "run sf_identify ; " \ + "if test \"${bootmode}\" = \"qspi\" ; then " \ + "led all off ; " \ + "if test \"${boottype}\" = \"rcvr\" ; then " \ + "echo \"Booting recovery system\" ; " \ + "led 3 on ; " /* Bottom RED */ \ + "fi ; " \ + "led 1 on ; " /* Top RED */ \ + "run ubi_ubi ; " \ + "else echo \"Unsupported boot mode: \"${bootmode} ; " \ + "fi\0" \ + "socfpga_legacy_reset_compat=1\0" + +/* Support changing the prompt string */ +#define CONFIG_CMDLINE_PS_SUPPORT + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_SOFTING_VINING_FPGA_H__ */ diff --git a/roms/u-boot/include/configs/socrates.h b/roms/u-boot/include/configs/socrates.h new file mode 100644 index 000000000..da6054696 --- /dev/null +++ b/roms/u-boot/include/configs/socrates.h @@ -0,0 +1,284 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * Wolfgang Denk + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003 Motorola,Inc. + * Xianghua Xiao + */ + +/* + * Socrates + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_SOCRATES 1 + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +/* + * sysclk for MPC85xx + * + * Two valid values are: + * 33000000 + * 66000000 + * + * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz + * is likely the desired value here, so that is now the default. + * The board, however, can run at 66MHz. In any event, this value + * must match the settings of some switches. Details can be found + * in the README.mpc85xxads. + */ + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 66666666 +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ + +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ + +#define CONFIG_SYS_CCSRBAR 0xE0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* DDR Setup */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD + +#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 + +/* I2C addresses of SPD EEPROMs */ +#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ + +#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ + +/* Hardcoded values, to use instead of SPD */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 +#define CONFIG_SYS_DDR_TIMING_0 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1 0x3935D322 +#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 +#define CONFIG_SYS_DDR_MODE 0x00480432 +#define CONFIG_SYS_DDR_INTERVAL 0x030C0100 +#define CONFIG_SYS_DDR_CONFIG_2 0x04400000 +#define CONFIG_SYS_DDR_CONFIG 0xC3008000 +#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 +#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ + +/* + * Flash on the LocalBus + */ +#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_SYS_FLASH0 0xFE000000 +#define CONFIG_SYS_FLASH1 0xFC000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } + +#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ + +#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ +#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */ +#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */ +#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ + +/* FPGA and NAND */ +#define CONFIG_SYS_FPGA_BASE 0xc0000000 +#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ +#define CONFIG_SYS_HMI_BASE 0xc0010000 +#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ +#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ + +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* LIME GDC */ +#define CONFIG_SYS_LIME_BASE 0xc8000000 +#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ +#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ +#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */ + +#define CONFIG_SYS_SPD_BUS_NUM 0 + +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 + +/* + * General PCI + * Memory space is mapped 1-1. + */ + +/* PCI is clocked by the external source at 33 MHz */ +#define CONFIG_PCI_CLK_FREQ 33000000 +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 +#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE +#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "TSEC1" +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 0 +#define TSEC3_PHY_ADDR 1 + +#define TSEC1_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS TSEC_GIGABIT + +/* Options are: TSEC[0,1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 + +/* + * Environment + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_TIMESTAMP /* Print image info with ts */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ +#endif + +#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consdev=ttyS0\0" \ + "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ + "bootfile=/home/tftp/syscon3/uImage\0" \ + "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ + "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ + "uboot_addr=FFF60000\0" \ + "kernel_addr=FE000000\0" \ + "fdt_addr=FE1E0000\0" \ + "ramdisk_addr=FE200000\0" \ + "fdt_addr_r=B00000\0" \ + "kernel_addr_r=200000\0" \ + "ramdisk_addr_r=400000\0" \ + "rootpath=/opt/eldk/ppc_85xxDP\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath\0" \ + "addcons=setenv bootargs $bootargs " \ + "console=$consdev,$baudrate\0" \ + "addip=setenv bootargs $bootargs " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ + ":$hostname:$netdev:off panic=1\0" \ + "boot_nor=run ramargs addcons;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "tftp ${fdt_addr_r} ${fdt_file}; " \ + "run nfsargs addip addcons;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "update_uboot=tftp 100000 ${uboot_file};" \ + "protect off fff60000 ffffffff;" \ + "era fff60000 ffffffff;" \ + "cp.b 100000 fff60000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "update_kernel=tftp 100000 ${bootfile};" \ + "era fe000000 fe1dffff;" \ + "cp.b 100000 fe000000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "update_fdt=tftp 100000 ${fdt_file};" \ + "era fe1e0000 fe1fffff;" \ + "cp.b 100000 fe1e0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "update_initrd=tftp 100000 ${initrd_file};" \ + "era fe200000 fe9fffff;" \ + "cp.b 100000 fe200000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "clean_data=era fea00000 fff5ffff\0" \ + "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ + "load_usb=usb start;" \ + "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ + "boot_usb=run load_usb usbargs addcons;" \ + "bootm ${kernel_addr_r} - ${fdt_addr};" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "" +#define CONFIG_BOOTCOMMAND "run boot_nor" + +/* pass open firmware flat tree */ + +/* USB support */ +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_PCI_OHCI 1 +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/som-db5800-som-6867.h b/roms/u-boot/include/configs/som-db5800-som-6867.h new file mode 100644 index 000000000..201f2c2ec --- /dev/null +++ b/roms/u-boot/include/configs/som-db5800-som-6867.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Google, Inc + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/somlabs_visionsom_6ull.h b/roms/u-boot/include/configs/somlabs_visionsom_6ull.h new file mode 100644 index 000000000..945d0ecc7 --- /dev/null +++ b/roms/u-boot/include/configs/somlabs_visionsom_6ull.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017-2019 A. Karas, SomLabs + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the SoMlabs VisionSOM 6ULL board. + */ +#ifndef __SOMLABS_VISIONSOM_6ULL_H +#define __SOMLABS_VISIONSOM_6ULL_H + +#include +#include +#include "mx6_common.h" +#include + +/* SPL options */ +#include "imx6_spl.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#ifdef CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#endif /* CONFIG_FSL_USDHC */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "console=ttymxc0\0" \ + "initrd_addr=0x86800000\0" \ + "fdt_addr=0x83000000\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "splashimage=0x80000000\0" \ + "splashfile=/boot/splash.bmp\0" \ + "mmcdev=1\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk1p1 rootwait rw\0" \ + "setrootmmc=setenv rootspec root=${mmcroot}\0" \ + "setbootscriptmmc=setenv loadbootscript " \ + "load mmc ${mmcdev}:${mmcpart} " \ + "${loadaddr} /boot/${script};\0" \ + "setloadmmc=setenv loadimage load mmc ${mmcdev}:${mmcpart} " \ + "${loadaddr} /boot/${image}; " \ + "setenv loadfdt load mmc ${mmcdev}:${mmcpart} " \ + "${fdt_addr} /boot/${fdt_file};\0" \ + "setbootargs=setenv bootargs console=${console},${baudrate} " \ + "${rootspec}\0" \ + "execbootscript=echo Running bootscript...; source\0" \ + "setfdtfile=setenv fdt_file somlabs-visionsom-6ull.dtb\0" \ + "checkbootdev=run setbootscriptmmc; " \ + "run setrootmmc; " \ + "run setloadmmc; " \ + +#define CONFIG_BOOTCOMMAND \ + "run setfdtfile; " \ + "run checkbootdev; " \ + "run loadfdt;" \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run setbootargs; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "fi; " \ + "fi" + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* environment organization */ + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth0" +#endif + +#endif diff --git a/roms/u-boot/include/configs/spear-common.h b/roms/u-boot/include/configs/spear-common.h new file mode 100644 index 000000000..4ba51d532 --- /dev/null +++ b/roms/u-boot/include/configs/spear-common.h @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, + */ + +#ifndef _SPEAR_COMMON_H +#define _SPEAR_COMMON_H +/* + * Common configurations used for both spear3xx as well as spear6xx + */ + +/* U-Boot Load Address */ + +/* Ethernet driver configuration */ +#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ + +/* USBD driver configuration */ +#if defined(CONFIG_SPEAR_USBTTY) +#define CONFIG_DW_UDC +#define CONFIG_USB_DEVICE +#define CONFIG_USBD_HS +#define CONFIG_USB_TTY + +#define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC" +#define CONFIG_USBD_MANUFACTURER "ST Microelectronics" + +#endif + +#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0" + +/* I2C driver configuration */ +#define CONFIG_SYS_I2C +#if defined(CONFIG_SPEAR600) +#define CONFIG_SYS_I2C_BASE 0xD0200000 +#elif defined(CONFIG_SPEAR300) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#elif defined(CONFIG_SPEAR310) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#endif +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x02 + +#define CONFIG_I2C_CHIPADDRESS 0x50 + +/* Timer, HZ specific defines */ + +/* Flash configuration */ +#if defined(CONFIG_FLASH_PNOR) +#define CONFIG_SPEAR_EMI +#else +#define CONFIG_ST_SMI +#endif + +#if defined(CONFIG_ST_SMI) + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_BASE 0xF8000000 +#define CONFIG_SYS_CS1_FLASH_BASE 0xF9000000 +#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 +#define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_CS1_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) + +#endif + +/* + * Serial Configuration (PL011) + * CONFIG_PL01x_PORTS is defined in specific files + */ +#define CONFIG_PL011_CLOCK (48 * 1000 * 1000) +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ + 57600, 115200 } + +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* NAND FLASH Configuration */ +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_NAND_FSMC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* + * Default Environment Varible definitions + */ + +/* + * U-Boot Environment placing definitions. + */ +#if defined(CONFIG_ENV_IS_IN_FLASH) +#ifdef CONFIG_ST_SMI +/* + * Environment is in serial NOR flash + */ +#define CONFIG_SYS_MONITOR_LEN 0x00040000 +#define CONFIG_FSMTDBLK "/dev/mtdblock3 " + +#define CONFIG_BOOTCOMMAND "bootm 0xf8050000" + +#elif defined(CONFIG_SPEAR_EMI) +/* + * Environment is in parallel NOR flash + */ +#define CONFIG_SYS_MONITOR_LEN 0x00060000 +#define CONFIG_FSMTDBLK "/dev/mtdblock3 " + +#define CONFIG_BOOTCOMMAND "cp.b 0x50080000 0x1600000 " \ + "0x4C0000; bootm 0x1600000" +#endif +#elif defined(CONFIG_ENV_IS_IN_NAND) +/* + * Environment is in NAND + */ + +#define CONFIG_ENV_RANGE 0x10000 +#define CONFIG_FSMTDBLK "/dev/mtdblock7 " + +#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \ + "0x80000 0x4C0000; " \ + "bootm 0x1600000" +#endif + +#define CONFIG_NFSBOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):$(netdev):off " \ + "console=ttyAMA0,115200 $(othbootargs);" \ + "bootm; " + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=ttyAMA0,115200 $(othbootargs);" \ + CONFIG_BOOTCOMMAND + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +/* Miscellaneous configurable options */ +#define CONFIG_BOOT_PARAMS_ADDR 0x00000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#define CONFIG_SYS_MALLOC_LEN (1024*1024) +#define CONFIG_SYS_LOAD_ADDR 0x00800000 + +#define CONFIG_SYS_FLASH_EMPTY_INFO + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_MAXSIZE 0x40000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#endif diff --git a/roms/u-boot/include/configs/spear3xx_evb.h b/roms/u-boot/include/configs/spear3xx_evb.h new file mode 100644 index 000000000..2f642b1a4 --- /dev/null +++ b/roms/u-boot/include/configs/spear3xx_evb.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#if defined(CONFIG_SPEAR300) +#define CONFIG_SPEAR3XX +#elif defined(CONFIG_SPEAR310) +#define CONFIG_SPEAR3XX +#elif defined(CONFIG_SPEAR320) +#define CONFIG_SPEAR3XX +#endif + +#if defined(CONFIG_USBTTY) +#define CONFIG_SPEAR_USBTTY +#endif + +#include + +/* Ethernet driver configuration */ +#define CONFIG_DW_ALTDESCRIPTOR + +#if defined(CONFIG_SPEAR310) +#define CONFIG_MACB +#define CONFIG_MACB0_PHY 0x01 +#define CONFIG_MACB1_PHY 0x03 +#define CONFIG_MACB2_PHY 0x05 +#define CONFIG_MACB3_PHY 0x07 + +#elif defined(CONFIG_SPEAR320) +#define CONFIG_MACB +#define CONFIG_MACB0_PHY 0x01 + +#endif + +/* Serial Configuration (PL011) */ +#define CONFIG_SYS_SERIAL0 0xD0000000 + +#if defined(CONFIG_SPEAR300) +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} + +#elif defined(CONFIG_SPEAR310) + +#if (CONFIG_CONS_INDEX) +#undef CONFIG_PL011_CLOCK +#define CONFIG_PL011_CLOCK (83 * 1000 * 1000) +#endif + +#define CONFIG_SYS_SERIAL1 0xB2000000 +#define CONFIG_SYS_SERIAL2 0xB2080000 +#define CONFIG_SYS_SERIAL3 0xB2100000 +#define CONFIG_SYS_SERIAL4 0xB2180000 +#define CONFIG_SYS_SERIAL5 0xB2200000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1, \ + (void *)CONFIG_SYS_SERIAL2, \ + (void *)CONFIG_SYS_SERIAL3, \ + (void *)CONFIG_SYS_SERIAL4, \ + (void *)CONFIG_SYS_SERIAL5 } +#elif defined(CONFIG_SPEAR320) + +#if (CONFIG_CONS_INDEX) +#undef CONFIG_PL011_CLOCK +#define CONFIG_PL011_CLOCK (83 * 1000 * 1000) +#endif + +#define CONFIG_SYS_SERIAL1 0xA3000000 +#define CONFIG_SYS_SERIAL2 0xA4000000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1, \ + (void *)CONFIG_SYS_SERIAL2 } +#endif + +#if defined(CONFIG_SPEAR_EMI) +#if defined(CONFIG_SPEAR310) +#define CONFIG_SYS_FLASH_BASE 0x50000000 +#define CONFIG_SYS_CS1_FLASH_BASE 0x60000000 +#define CONFIG_SYS_CS2_FLASH_BASE 0x70000000 +#define CONFIG_SYS_CS3_FLASH_BASE 0x80000000 +#define CONFIG_SYS_CS4_FLASH_BASE 0x90000000 +#define CONFIG_SYS_CS5_FLASH_BASE 0xA0000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_CS1_FLASH_BASE, \ + CONFIG_SYS_CS2_FLASH_BASE, \ + CONFIG_SYS_CS3_FLASH_BASE, \ + CONFIG_SYS_CS4_FLASH_BASE, \ + CONFIG_SYS_CS5_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 6 + +#elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_FLASH_BASE 0x44000000 +#define CONFIG_SYS_CS1_FLASH_BASE 0x45000000 +#define CONFIG_SYS_CS2_FLASH_BASE 0x46000000 +#define CONFIG_SYS_CS3_FLASH_BASE 0x47000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_CS1_FLASH_BASE, \ + CONFIG_SYS_CS2_FLASH_BASE, \ + CONFIG_SYS_CS3_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 4 + +#endif + +#define CONFIG_SYS_MAX_FLASH_SECT (127 + 8) +#define CONFIG_SYS_FLASH_QUIET_TEST + +#endif + +/* NAND flash configuration */ +#define CONFIG_SYS_FSMC_NAND_SP +#define CONFIG_SYS_FSMC_NAND_8BIT + +#if defined(CONFIG_SPEAR300) +#define CONFIG_SYS_NAND_BASE 0x80000000 + +#elif defined(CONFIG_SPEAR310) +#define CONFIG_SYS_NAND_BASE 0x40000000 + +#elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_NAND_BASE 0x50000000 + +#endif + +/* Environment Settings */ +#if defined(CONFIG_SPEAR300) +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY + +#elif defined(CONFIG_SPEAR310) || defined(CONFIG_SPEAR320) +#define CONFIG_EXTRA_ENV_UNLOCK "unlock=yes\0" +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY \ + CONFIG_EXTRA_ENV_UNLOCK +#endif + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/spear6xx_evb.h b/roms/u-boot/include/configs/spear6xx_evb.h new file mode 100644 index 000000000..4fedc9efc --- /dev/null +++ b/roms/u-boot/include/configs/spear6xx_evb.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#if defined(CONFIG_USBTTY) +#define CONFIG_SPEAR_USBTTY +#endif + +#include + +/* Serial Configuration (PL011) */ +#define CONFIG_SYS_SERIAL0 0xD0000000 +#define CONFIG_SYS_SERIAL1 0xD0080000 +#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1 } + +/* NAND flash configuration */ +#define CONFIG_SYS_FSMC_NAND_SP +#define CONFIG_SYS_FSMC_NAND_8BIT +#define CONFIG_SYS_NAND_BASE 0xD2000000 + +/* Ethernet PHY configuration */ + +/* Environment Settings */ +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/spring.h b/roms/u-boot/include/configs/spring.h new file mode 100644 index 000000000..0b052453a --- /dev/null +++ b/roms/u-boot/include/configs/spring.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Google, Inc + */ + +#ifndef __CONFIG_SPRING_H +#define __CONFIG_SPRING_H + +#include +#include +#include + +#define CONFIG_BOARD_COMMON + +#endif /* __CONFIG_SPRING_H */ diff --git a/roms/u-boot/include/configs/stemmy.h b/roms/u-boot/include/configs/stemmy.h new file mode 100644 index 000000000..922eec43e --- /dev/null +++ b/roms/u-boot/include/configs/stemmy.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2019 Stephan Gerhold + */ +#ifndef __CONFIGS_STEMMY_H +#define __CONFIGS_STEMMY_H + +#include + +#define CONFIG_SKIP_LOWLEVEL_INIT /* Loaded by another bootloader */ +#define CONFIG_SYS_MALLOC_LEN SZ_2M + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_SIZE SZ_1G +#define CONFIG_SYS_INIT_RAM_SIZE 0x00100000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET + +/* FIXME: This should be loaded from device tree... */ +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0xa0412000 + +#define CONFIG_SYS_LOAD_ADDR 0x00100000 + +#endif diff --git a/roms/u-boot/include/configs/stih410-b2260.h b/roms/u-boot/include/configs/stih410-b2260.h new file mode 100644 index 000000000..33b34ee0c --- /dev/null +++ b/roms/u-boot/include/configs/stih410-b2260.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, for STMicroelectronics. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* ram memory-related information */ +#define PHYS_SDRAM_1 0x40000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define PHYS_SDRAM_1_SIZE 0x3E000000 +#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 /* default load addr */ + +#define CONFIG_SYS_HZ_CLOCK 1000000000 /* 1 GHz */ + +/* Environment */ + +/* + * For booting Linux, use the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ SZ_256M + +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_SYS_BOOTM_LEN SZ_16M + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x40000000\0" \ + "fdtfile=stih410-b2260.dtb\0" \ + "fdt_addr_r=0x47000000\0" \ + "scriptaddr=0x50000000\0" \ + "pxefile_addr_r=0x50100000\0" \ + "ramdisk_addr_r=0x48000000\0" \ + BOOTENV + +/* Extra Commands */ + +#define CONFIG_SETUP_MEMORY_TAGS + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN 0x1800000 +#define CONFIG_SYS_GBL_DATA_SIZE 1024 /* Global data structures */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SYS_MALLOC_LEN - \ + CONFIG_SYS_GBL_DATA_SIZE) + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* USB Configs */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX + +/* NET Configs */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/stm32f429-discovery.h b/roms/u-boot/include/configs/stm32f429-discovery.h new file mode 100644 index 000000000..9d029fbcc --- /dev/null +++ b/roms/u-boot/include/configs/stm32f429-discovery.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 + * Kamil Lulko, + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_FLASH_BASE 0x08000000 + +#define CONFIG_SYS_INIT_SP_ADDR 0x10010000 + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_SYS_LOAD_ADDR 0x90400000 +#define CONFIG_LOADADDR 0x90400000 + +#define CONFIG_SYS_MAX_FLASH_SECT 12 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +#define CONFIG_RED_LED 110 +#define CONFIG_GREEN_LED 109 + +#define CONFIG_STM32_FLASH + +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_CBSIZE 1024 + +#define CONFIG_SYS_MALLOC_LEN (2 << 20) + +#define CONFIG_BOOTCOMMAND \ + "run bootcmd_romfs" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ + "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ + "bootm 0x08044000 - 0x08042000\0" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/stm32f429-evaluation.h b/roms/u-boot/include/configs/stm32f429-evaluation.h new file mode 100644 index 000000000..fefdb2dd1 --- /dev/null +++ b/roms/u-boot/include/configs/stm32f429-evaluation.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) STMicroelectronics SA 2017 + * Author(s): Patrice CHOTARD, for STMicroelectronics. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* For booting Linux, use the first 16MB of memory */ +#define CONFIG_SYS_BOOTMAPSZ SZ_16M + +#define CONFIG_SYS_FLASH_BASE 0x08000000 + +#define CONFIG_SYS_INIT_SP_ADDR 0x10010000 + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_SYS_LOAD_ADDR 0x00400000 +#define CONFIG_LOADADDR 0x00400000 + +#define CONFIG_SYS_MAX_FLASH_SECT 12 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +#define CONFIG_STM32_FLASH + +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_CBSIZE 1024 + +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x00008000\0" \ + "fdtfile=stm32429i-eval.dtb\0" \ + "fdt_addr_r=0x00408000\0" \ + "scriptaddr=0x00418000\0" \ + "pxefile_addr_r=0x00428000\0" \ + "ramdisk_addr_r=0x00438000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/stm32f469-discovery.h b/roms/u-boot/include/configs/stm32f469-discovery.h new file mode 100644 index 000000000..ba9f05a61 --- /dev/null +++ b/roms/u-boot/include/configs/stm32f469-discovery.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) STMicroelectronics SA 2017 + * Author(s): Patrice CHOTARD, for STMicroelectronics. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* For booting Linux, use the first 12MB of memory */ +#define CONFIG_SYS_BOOTMAPSZ SZ_8M + SZ_4M + +#define CONFIG_SYS_FLASH_BASE 0x08000000 + +#define CONFIG_SYS_INIT_SP_ADDR 0x10010000 + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_SYS_LOAD_ADDR 0x00400000 +#define CONFIG_LOADADDR 0x00400000 + +#define CONFIG_SYS_MAX_FLASH_SECT 12 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +#define CONFIG_STM32_FLASH + +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_CBSIZE 1024 + +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x00008000\0" \ + "fdtfile=stm32f469-disco.dtb\0" \ + "fdt_addr_r=0x00408000\0" \ + "scriptaddr=0x00418000\0" \ + "pxefile_addr_r=0x00428000\0" \ + "ramdisk_addr_r=0x00438000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/stm32f746-disco.h b/roms/u-boot/include/configs/stm32f746-disco.h new file mode 100644 index 000000000..08d050adf --- /dev/null +++ b/roms/u-boot/include/configs/stm32f746-disco.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, for STMicroelectronics. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* For booting Linux, use the first 6MB of memory */ +#define CONFIG_SYS_BOOTMAPSZ SZ_4M + SZ_2M + +#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x20050000 + +#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SYS_LOAD_ADDR 0x08008000 +#else +#define CONFIG_SYS_LOAD_ADDR 0xC0400000 +#define CONFIG_LOADADDR 0xC0400000 +#endif + +/* + * Configuration of the external SDRAM memory + */ + +#define CONFIG_SYS_MAX_FLASH_SECT 8 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#define CONFIG_STM32_FLASH + +#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8) +#define CONFIG_DW_ALTDESCRIPTOR + +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_CBSIZE 1024 + +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0xC0008000\0" \ + "fdtfile=stm32f746-disco.dtb\0" \ + "fdt_addr_r=0xC0408000\0" \ + "scriptaddr=0xC0418000\0" \ + "pxefile_addr_r=0xC0428000\0" \ + "ramdisk_addr_r=0xC0438000\0" \ + BOOTENV + +#define CONFIG_DISPLAY_BOARDINFO + +/* For SPL */ +#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_SPL_LEN 0x00008000 +#define CONFIG_SYS_UBOOT_START 0x080083FD +#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ + CONFIG_SYS_SPL_LEN) + +/* DT blob (fdt) address */ +#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ + 0x1C0000) +#endif +/* For SPL ends */ + +/* For splashcreen */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/stm32h743-disco.h b/roms/u-boot/include/configs/stm32h743-disco.h new file mode 100644 index 000000000..6e10dbdfe --- /dev/null +++ b/roms/u-boot/include/configs/stm32h743-disco.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, for STMicroelectronics. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +/* For booting Linux, use the first 16MB of memory */ +#define CONFIG_SYS_BOOTMAPSZ SZ_16M + +#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x24040000 + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_SYS_LOAD_ADDR 0xD0400000 +#define CONFIG_LOADADDR 0xD0400000 + +#define CONFIG_SYS_HZ_CLOCK 1000000 + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0xD0008000\0" \ + "fdtfile=stm32h743i-disco.dtb\0" \ + "fdt_addr_r=0xD0408000\0" \ + "scriptaddr=0xD0418000\0" \ + "pxefile_addr_r=0xD0428000\0" \ + "ramdisk_addr_r=0xD0438000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/stm32h743-eval.h b/roms/u-boot/include/configs/stm32h743-eval.h new file mode 100644 index 000000000..268d39c7a --- /dev/null +++ b/roms/u-boot/include/configs/stm32h743-eval.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, for STMicroelectronics. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +/* For booting Linux, use the first 16MB of memory */ +#define CONFIG_SYS_BOOTMAPSZ SZ_16M + +#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x24040000 + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_SYS_LOAD_ADDR 0xD0400000 +#define CONFIG_LOADADDR 0xD0400000 + +#define CONFIG_SYS_HZ_CLOCK 1000000 + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0xD0008000\0" \ + "fdtfile=stm32h743i-eval.dtb\0" \ + "fdt_addr_r=0xD0408000\0" \ + "scriptaddr=0xD0418000\0" \ + "pxefile_addr_r=0xD0428000\0" \ + "ramdisk_addr_r=0xD0438000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/stm32h750-art-pi.h b/roms/u-boot/include/configs/stm32h750-art-pi.h new file mode 100644 index 000000000..3fd546116 --- /dev/null +++ b/roms/u-boot/include/configs/stm32h750-art-pi.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021, STMicroelectronics - All Rights Reserved + * Author(s): Dillon Min + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +/* For booting Linux, use the first 16MB of memory */ +#define CONFIG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M) + +#define CONFIG_SYS_FLASH_BASE 0x90000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x24040000 + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_SYS_LOAD_ADDR 0xC1800000 +#define CONFIG_LOADADDR 0xC1800000 + +#define CONFIG_SYS_HZ_CLOCK 1000000 + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0xC0008000\0" \ + "fdtfile=stm32h750i-art-pi.dtb\0" \ + "fdt_addr_r=0xC0408000\0" \ + "scriptaddr=0xC0418000\0" \ + "pxefile_addr_r=0xC0428000\0" \ + "ramdisk_addr_r=0xC0438000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/stm32mp1.h b/roms/u-boot/include/configs/stm32mp1.h new file mode 100644 index 000000000..440efa1a5 --- /dev/null +++ b/roms/u-boot/include/configs/stm32mp1.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * Configuration settings for the STM32MP15x CPU + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include +#include + +#ifndef CONFIG_TFABOOT +/* PSCI support */ +#define CONFIG_ARMV7_SECURE_BASE STM32_SYSRAM_BASE +#define CONFIG_ARMV7_SECURE_MAX_SIZE STM32_SYSRAM_SIZE +#endif + +/* + * Configuration of the external SRAM memory used by U-Boot + */ +#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE + +/* + * Console I/O buffer size + */ +#define CONFIG_SYS_CBSIZE SZ_1K + +/* + * default load address used for command tftp, bootm , loadb, ... + */ +#define CONFIG_LOADADDR 0xc2000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* ATAGs */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * For booting Linux, use the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ SZ_256M + +/* Extend size of kernel image for uncompression */ +#define CONFIG_SYS_BOOTM_LEN SZ_32M + +/* SPL support */ +#ifdef CONFIG_SPL +/* SPL use DDR */ +#define CONFIG_SYS_SPL_MALLOC_START 0xC0300000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x01D00000 + +/* Restrict SPL to fit within SYSRAM */ +#define STM32_SYSRAM_END (STM32_SYSRAM_BASE + STM32_SYSRAM_SIZE) +#define CONFIG_SPL_MAX_FOOTPRINT (STM32_SYSRAM_END - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_STACK (STM32_SYSRAM_BASE + \ + STM32_SYSRAM_SIZE) +#endif /* #ifdef CONFIG_SPL */ +/*MMC SD*/ +#define CONFIG_SYS_MMC_MAX_DEVICE 3 + +/* NAND support */ +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Ethernet need */ +#ifdef CONFIG_DWC_ETH_QOS +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_BOOTP_SERVERIP +#define CONFIG_SYS_AUTOLOAD "no" +#endif + +/*****************************************************************************/ +#ifdef CONFIG_DISTRO_DEFAULTS +/*****************************************************************************/ + +#if !defined(CONFIG_SPL_BUILD) + +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_MMC0(func) func(MMC, mmc, 0) +#define BOOT_TARGET_MMC1(func) func(MMC, mmc, 1) +#define BOOT_TARGET_MMC2(func) func(MMC, mmc, 2) +#else +#define BOOT_TARGET_MMC0(func) +#define BOOT_TARGET_MMC1(func) +#define BOOT_TARGET_MMC2(func) +#endif + +#ifdef CONFIG_NET +#define BOOT_TARGET_PXE(func) func(PXE, pxe, na) +#else +#define BOOT_TARGET_PXE(func) +#endif + +#ifdef CONFIG_CMD_UBIFS +#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0) +#else +#define BOOT_TARGET_UBIFS(func) +#endif + +#ifdef CONFIG_USB +#define BOOT_TARGET_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_USB(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_MMC1(func) \ + BOOT_TARGET_UBIFS(func) \ + BOOT_TARGET_MMC0(func) \ + BOOT_TARGET_MMC2(func) \ + BOOT_TARGET_USB(func) \ + BOOT_TARGET_PXE(func) + +/* + * bootcmd for stm32mp1: + * for serial/usb: execute the stm32prog command + * for mmc boot (eMMC, SD card), boot only on the same device + * for nand or spi-nand boot, boot with on ubifs partition on UBI partition + * for nor boot, use SD card = mmc0 + */ +#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \ + "echo \"Boot over ${boot_device}${boot_instance}!\";" \ + "if test ${boot_device} = serial || test ${boot_device} = usb;" \ + "then stm32prog ${boot_device} ${boot_instance}; " \ + "else " \ + "run env_check;" \ + "if test ${boot_device} = mmc;" \ + "then env set boot_targets \"mmc${boot_instance}\"; fi;" \ + "if test ${boot_device} = nand ||" \ + " test ${boot_device} = spi-nand ;" \ + "then env set boot_targets ubifs0; fi;" \ + "if test ${boot_device} = nor;" \ + "then env set boot_targets mmc0; fi;" \ + "run distro_bootcmd;" \ + "fi;\0" + +#ifdef CONFIG_FASTBOOT_CMD_OEM_FORMAT +/* eMMC default partitions for fastboot command: oem format */ +#define PARTS_DEFAULT \ + "partitions=" \ + "name=ssbl,size=2M;" \ + "name=bootfs,size=64MB,bootable;" \ + "name=vendorfs,size=16M;" \ + "name=rootfs,size=746M;" \ + "name=userfs,size=-\0" +#else +#define PARTS_DEFAULT +#endif + +#include + +/* + * memory layout for 32M uncompressed/compressed kernel, + * 1M fdt, 1M script, 1M pxe and 1M for splashimage + * and the ramdisk at the end. + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0xc2000000\0" \ + "fdt_addr_r=0xc4000000\0" \ + "scriptaddr=0xc4100000\0" \ + "pxefile_addr_r=0xc4200000\0" \ + "splashimage=0xc4300000\0" \ + "ramdisk_addr_r=0xc4400000\0" \ + "altbootcmd=run bootcmd\0" \ + "env_check=if env info -p -d -q; then env save; fi\0" \ + STM32MP_BOOTCMD \ + PARTS_DEFAULT \ + BOOTENV \ + "boot_net_usb_start=true\0" + +#endif /* ifndef CONFIG_SPL_BUILD */ +#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/stmark2.h b/roms/u-boot/include/configs/stmark2.h new file mode 100644 index 000000000..da162cbb1 --- /dev/null +++ b/roms/u-boot/include/configs/stmark2.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Sysam stmark2 board configuration + * + * (C) Copyright 2017 Angelo Dureghello + */ + +#ifndef __STMARK2_CONFIG_H +#define __STMARK2_CONFIG_H + +#define CONFIG_HOSTNAME "stmark2" + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT 0 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#define LDS_BOARD_TEXT \ + board/sysam/stmark2/sbf_dram_init.o (.text*) + +#define CONFIG_TIMESTAMP + +#define CONFIG_BOOTCOMMAND \ + "sf probe 0:1 50000000; " \ + "sf read ${loadaddr} 0x100000 ${kern_size}; " \ + "bootm ${loadaddr}" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kern_size=0x700000\0" \ + "loadaddr=0x40001000\0" \ + "-(rootfs)\0" \ + "update_uboot=loady ${loadaddr}; " \ + "sf probe 0:1 50000000; " \ + "sf erase 0 0x80000; " \ + "sf write ${loadaddr} 0 ${filesize}\0" \ + "update_kernel=loady ${loadaddr}; " \ + "setenv kern_size ${filesize}; saveenv; " \ + "sf probe 0:1 50000000; " \ + "sf erase 0x100000 0x700000; " \ + "sf write ${loadaddr} 0x100000 ${filesize}\0" \ + "update_rootfs=loady ${loadaddr}; " \ + "sf probe 0:1 50000000; " \ + "sf erase 0x00800000 0x100000; " \ + "sf write ${loadaddr} 0x00800000 ${filesize}\0" \ + "" + +/* Realtime clock */ +#undef CONFIG_MCFRTC +#define CONFIG_RTC_MCFRRTC +#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 + +/* spi not partitions */ +#define CONFIG_JFFS2_DEV "nor0" + +/* Timer */ +#define CONFIG_MCFTMR + +/* DSPI and Serial Flash */ +#define CONFIG_CF_DSPI +#define CONFIG_SERIAL_FLASH + +#define CONFIG_SYS_SBFHDR_SIZE 0x7 + +/* Input, PCI, Flexbus, and VCO */ +#define CONFIG_EXTRA_CLOCK + +#define CONFIG_PRAM 2048 /* 2048 KB */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) +#define CONFIG_SYS_MBAR 0xFC000000 + +/* + * Definitions for initial stack pointer and data area (in internal SRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +/* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) - 32) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ + +#define CONFIG_SYS_DRAM_TEST + +#if defined(CONFIG_CF_SBF) +#define CONFIG_SERIAL_BOOT +#endif + +#if defined(CONFIG_SERIAL_BOOT) +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) +#else +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif + +#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) +/* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +/* Reserve 256 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ + +#if defined(CONFIG_CF_SBF) +#define CONFIG_ENV_IS_IN_SPI_FLASH 1 +#endif + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + +#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 12) + +#ifdef CONFIG_MCFFEC +#define CONFIG_MII_INIT 1 +#define CONFIG_SYS_DISCOVER_PHY +#define CONFIG_SYS_RX_ETH_BUFFER 8 +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +#ifndef CONFIG_SYS_DISCOVER_PHY +#define FECDUPLEX FULL +#define FECSPEED _100BASET +#else +#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#endif +#endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif +#endif /* __STMARK2_CONFIG_H */ diff --git a/roms/u-boot/include/configs/stout.h b/roms/u-boot/include/configs/stout.h new file mode 100644 index 000000000..a1e7e86f3 --- /dev/null +++ b/roms/u-boot/include/configs/stout.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * include/configs/stout.h + * This file is Stout board configuration. + * + * Copyright (C) 2015 Renesas Electronics Europe GmbH + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + */ + +#ifndef __STOUT_H +#define __STOUT_H + +#include "rcar-gen2-common.h" + +#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 +#define STACK_AREA_SIZE 0x00100000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) + +/* SCIF */ +#define CONFIG_SCIF_A + +/* SPI */ +#define CONFIG_SPI_FLASH_QUAD + +/* SH Ether */ +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" + +/* SPL support */ +#define CONFIG_SPL_STACK 0xe6340000 +#define CONFIG_SPL_MAX_SIZE 0x4000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIFA0 +#define CONFIG_SH_SCIF_CLK_FREQ 52000000 +#endif + +#endif /* __STOUT_H */ diff --git a/roms/u-boot/include/configs/stv0991.h b/roms/u-boot/include/configs/stv0991.h new file mode 100644 index 000000000..0058dcd4b --- /dev/null +++ b/roms/u-boot/include/configs/stv0991.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, for STMicroelectronics. + */ + +#ifndef __CONFIG_STV0991_H +#define __CONFIG_STV0991_H +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH + +/* ram memory-related information */ +#define PHYS_SDRAM_1 0x00000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define PHYS_SDRAM_1_SIZE 0x00198000 + +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024) + +/* user interface */ +#define CONFIG_SYS_CBSIZE 1024 + +/* MISC */ +#define CONFIG_SYS_LOAD_ADDR 0x00000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +/* U-Boot Load Address */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* GMAC related configs */ + +#define CONFIG_DW_ALTDESCRIPTOR + +/* Command support defines */ +#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ + +/* Misc configuration */ + +#define CONFIG_BOOTCOMMAND "go 0x40040000" + +/* ++ * QSPI support ++ */ +#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ +#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 + +#endif + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sun4i.h b/roms/u-boot/include/configs/sun4i.h new file mode 100644 index 000000000..603376058 --- /dev/null +++ b/roms/u-boot/include/configs/sun4i.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom + * + * Configuration settings for the Allwinner A10 (sun4i) CPU + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A10 specific configuration + */ + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#define CONFIG_MACH_TYPE (4104 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sun50i.h b/roms/u-boot/include/configs/sun50i.h new file mode 100644 index 000000000..bc2e3a3d0 --- /dev/null +++ b/roms/u-boot/include/configs/sun50i.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the Allwinner A64 (sun50i) CPU + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A64 specific configuration + */ + +#ifndef CONFIG_SUN50I_GEN_H6 +#define GICD_BASE 0x1c81000 +#define GICC_BASE 0x1c82000 +#else +#define GICD_BASE 0x3021000 +#define GICC_BASE 0x3022000 +#endif + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sun5i.h b/roms/u-boot/include/configs/sun5i.h new file mode 100644 index 000000000..ee42af80d --- /dev/null +++ b/roms/u-boot/include/configs/sun5i.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom + * + * Configuration settings for the Allwinner A13 (sun5i) CPU + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#define CONFIG_MACH_TYPE (4138 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sun6i.h b/roms/u-boot/include/configs/sun6i.h new file mode 100644 index 000000000..1e490daac --- /dev/null +++ b/roms/u-boot/include/configs/sun6i.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * (C) Copyright 2013 Maxime Ripard + * + * Configuration settings for the Allwinner A31 (sun6i) CPU + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A31 specific configuration + */ + +#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE +#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */ + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sun7i.h b/roms/u-boot/include/configs/sun7i.h new file mode 100644 index 000000000..d2fd58667 --- /dev/null +++ b/roms/u-boot/include/configs/sun7i.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * + * Configuration settings for the Allwinner A20 (sun7i) CPU + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A20 specific configuration + */ + +#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE +#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */ + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#define CONFIG_MACH_TYPE (4283 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sun8i.h b/roms/u-boot/include/configs/sun8i.h new file mode 100644 index 000000000..9b4675e4c --- /dev/null +++ b/roms/u-boot/include/configs/sun8i.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 Chen-Yu Tsai + * + * Configuration settings for the Allwinner A23 (sun8i) CPU + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A23 specific configuration + */ + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sun9i.h b/roms/u-boot/include/configs/sun9i.h new file mode 100644 index 000000000..6ee08cf0d --- /dev/null +++ b/roms/u-boot/include/configs/sun9i.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Hans de Goede + * + * Configuration settings for the Allwinner A80 (sun9i) CPU + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A80 specific configuration + */ + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/sunxi-common.h b/roms/u-boot/include/configs/sunxi-common.h new file mode 100644 index 000000000..9e37e9968 --- /dev/null +++ b/roms/u-boot/include/configs/sunxi-common.h @@ -0,0 +1,471 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012-2012 Henrik Nordstrom + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Configuration settings for the Allwinner sunxi series of boards. + */ + +#ifndef _SUNXI_COMMON_CONFIG_H +#define _SUNXI_COMMON_CONFIG_H + +#include +#include + +#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT +/* + * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the + * expense of restricting some features, so the regular machine id values can + * be used. + */ +# define CONFIG_MACH_TYPE_COMPAT_REV 0 +#else +/* + * A compatibility guard to prevent loading outdated buggy sunxi-3.4 kernels. + * Only sunxi-3.4 kernels with appropriate fixes applied are able to pass + * beyond the machine id check. + */ +# define CONFIG_MACH_TYPE_COMPAT_REV 1 +#endif + +#ifdef CONFIG_ARM64 +#define CONFIG_SYS_BOOTM_LEN (32 << 20) +#endif + +/* Serial & console */ +#define CONFIG_SYS_NS16550_SERIAL +/* ns16550 reg in the low bits of cpu reg */ +#define CONFIG_SYS_NS16550_CLK 24000000 +#ifndef CONFIG_DM_SERIAL +# define CONFIG_SYS_NS16550_REG_SIZE -4 +# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE +# define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE +# define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE +# define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE +# define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE +#endif + +/* CPU */ +#define COUNTER_FREQUENCY 24000000 + +/* + * The DRAM Base differs between some models. We cannot use macros for the + * CONFIG_FOO defines which contain the DRAM base address since they end + * up unexpanded in include/autoconf.mk . + * + * So we have to have this #ifdef #else #endif block for these. + */ +#ifdef CONFIG_MACH_SUN9I +#define SDRAM_OFFSET(x) 0x2##x +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */ +/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here + * since it needs to fit in with the other values. By also #defining it + * we get warnings if the Kconfig value mismatches. */ +#define CONFIG_SPL_STACK_R_ADDR 0x2fe00000 +#define CONFIG_SPL_BSS_START_ADDR 0x2ff80000 +#else +#define SDRAM_OFFSET(x) 0x4##x +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */ +/* V3s do not have enough memory to place code at 0x4a000000 */ +/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here + * since it needs to fit in with the other values. By also #defining it + * we get warnings if the Kconfig value mismatches. */ +#define CONFIG_SPL_STACK_R_ADDR 0x4fe00000 +#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 +#endif + +#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ + +/* + * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is + * slightly bigger. Note that it is possible to map the first 32 KiB of the + * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the + * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and + * the 1 actually activates the mapping of the first 32 KiB to 0x00000000. + * A64 and H5 also has SRAM A1 at 0x00010000, but no magic remap register + * is known yet. + * H6 has SRAM A1 at 0x00020000. + */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS +/* FIXME: this may be larger on some SoCs */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ + +#ifdef CONFIG_AHCI +#define CONFIG_SYS_64BIT_LBA +#endif + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_SERIAL_TAG + +#ifdef CONFIG_NAND_SUNXI +#define CONFIG_SYS_NAND_MAX_ECCPOS 1664 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_MAX_NAND_DEVICE 8 +#endif + +/* mmc config */ +#ifdef CONFIG_MMC +#define CONFIG_MMC_SUNXI_SLOT 0 +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) + +#ifdef CONFIG_ARM64 +/* + * This is actually (CONFIG_ENV_OFFSET - + * (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)), but the value will be used + * directly in a makefile, without the preprocessor expansion. + */ +#define CONFIG_BOARD_SIZE_LIMIT 0x7e000 +#endif + +#define CONFIG_SYS_MMC_MAX_DEVICE 4 +#endif + +#ifndef CONFIG_MACH_SUN8I_V3S +/* 64MB of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20)) +#else +/* 2MB of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20)) +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ + +/* standalone support */ +#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR + +/* FLASH and environment organization */ + +#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */ + +#define CONFIG_SPL_BOARD_LOAD_IMAGE + +/* + * We cannot use expressions here, because expressions won't be evaluated in + * autoconf.mk. + */ +#if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000 +#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ +#ifdef CONFIG_ARM64 +/* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */ +#define LOW_LEVEL_SRAM_STACK 0x00054000 +#else +#define LOW_LEVEL_SRAM_STACK 0x00018000 +#endif /* !CONFIG_ARM64 */ +#elif CONFIG_SUNXI_SRAM_ADDRESS == 0x20000 +#ifdef CONFIG_MACH_SUN50I_H616 +#define CONFIG_SPL_MAX_SIZE 0xbfa0 /* 48 KiB */ +#define LOW_LEVEL_SRAM_STACK 0x58000 +#else +#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ +/* end of SRAM A2 on H6 for now */ +#define LOW_LEVEL_SRAM_STACK 0x00118000 +#endif +#else +#define CONFIG_SPL_MAX_SIZE 0x5fa0 /* 24KB on sun4i/sun7i */ +#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ +#endif + +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#ifndef CONFIG_MACH_SUN50I_H616 +#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ +#endif + + +/* I2C */ +#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \ + defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \ + defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE +#define CONFIG_SYS_I2C_MVTWSI +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x7f +#endif +#endif + +#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) +#define CONFIG_SYS_I2C_SOFT +#define CONFIG_SYS_I2C_SOFT_SPEED 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00 +/* We use pin names in Kconfig and sunxi_name_to_gpio() */ +#define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda +#define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl +#ifndef __ASSEMBLY__ +extern int soft_i2c_gpio_sda; +extern int soft_i2c_gpio_scl; +#endif +#define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */ +#define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */ +#else +#define CONFIG_SYS_SPD_BUS_NUM 0 /* The axp209 i2c bus is bus 0 */ +#define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */ +#endif + +/* Ethernet support */ + +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#endif + +#ifndef CONFIG_SPL_BUILD + +#ifdef CONFIG_ARM64 +/* + * Boards seem to come with at least 512MB of DRAM. + * The kernel should go at 512K, which is the default text offset (that will + * be adjusted at runtime if needed). + * There is no compression for arm64 kernels (yet), so leave some space + * for really big kernels, say 256MB for now. + * Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd. + */ +#define BOOTM_SIZE __stringify(0xa000000) +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0080000)) +#define KERNEL_COMP_ADDR_R __stringify(SDRAM_OFFSET(4000000)) +#define KERNEL_COMP_SIZE __stringify(0xb000000) +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000)) +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(FD00000)) +#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(FE00000)) +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FF00000)) + +#else +/* + * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. + * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, + * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end. + */ +#ifndef CONFIG_MACH_SUN8I_V3S +#define BOOTM_SIZE __stringify(0xa000000) +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) +#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(3300000)) +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3400000)) +#else +/* + * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc. + * 16M uncompressed kernel, 8M compressed kernel, 1M fdt, + * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end. + */ +#define BOOTM_SIZE __stringify(0x2e00000) +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000)) +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(1800000)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1900000)) +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1A00000)) +#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(1B00000)) +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1C00000)) +#endif +#endif + +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=" BOOTM_SIZE "\0" \ + "kernel_addr_r=" KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" FDT_ADDR_R "\0" \ + "scriptaddr=" SCRIPT_ADDR_R "\0" \ + "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ + "fdtoverlay_addr_r=" FDTOVERLAY_ADDR_R "\0" \ + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" + +#ifdef CONFIG_ARM64 + +#define MEM_LAYOUT_ENV_EXTRA_SETTINGS \ + "kernel_comp_addr_r=" KERNEL_COMP_ADDR_R "\0" \ + "kernel_comp_size=" KERNEL_COMP_SIZE "\0" + +#else + +#define MEM_LAYOUT_ENV_EXTRA_SETTINGS "" + +#endif + +#define DFU_ALT_INFO_RAM \ + "dfu_alt_info_ram=" \ + "kernel ram " KERNEL_ADDR_R " 0x1000000;" \ + "fdt ram " FDT_ADDR_R " 0x100000;" \ + "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0" + +#ifdef CONFIG_MMC +#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 +#define BOOTENV_DEV_MMC_AUTO(devtypeu, devtypel, instance) \ + BOOTENV_DEV_MMC(MMC, mmc, 0) \ + BOOTENV_DEV_MMC(MMC, mmc, 1) \ + "bootcmd_mmc_auto=" \ + "if test ${mmc_bootdev} -eq 1; then " \ + "run bootcmd_mmc1; " \ + "run bootcmd_mmc0; " \ + "elif test ${mmc_bootdev} -eq 0; then " \ + "run bootcmd_mmc0; " \ + "run bootcmd_mmc1; " \ + "fi\0" + +#define BOOTENV_DEV_NAME_MMC_AUTO(devtypeu, devtypel, instance) \ + "mmc_auto " + +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC_AUTO, mmc_auto, na) +#else +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#endif +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#ifdef CONFIG_AHCI +#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) +#else +#define BOOT_TARGET_DEVICES_SCSI(func) +#endif + +#ifdef CONFIG_USB_STORAGE +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + +#ifdef CONFIG_CMD_PXE +#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) +#else +#define BOOT_TARGET_DEVICES_PXE(func) +#endif + +#ifdef CONFIG_CMD_DHCP +#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +#define BOOT_TARGET_DEVICES_DHCP(func) +#endif + +/* FEL boot support, auto-execute boot.scr if a script address was provided */ +#define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \ + "bootcmd_fel=" \ + "if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \ + "echo '(FEL boot)'; " \ + "source ${fel_scriptaddr}; " \ + "fi\0" +#define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \ + "fel " + +#define BOOT_TARGET_DEVICES(func) \ + func(FEL, fel, na) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_SCSI(func) \ + BOOT_TARGET_DEVICES_USB(func) \ + BOOT_TARGET_DEVICES_PXE(func) \ + BOOT_TARGET_DEVICES_DHCP(func) + +#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT +#define BOOTCMD_SUNXI_COMPAT \ + "bootcmd_sunxi_compat=" \ + "setenv root /dev/mmcblk0p3 rootwait; " \ + "if ext2load mmc 0 0x44000000 uEnv.txt; then " \ + "echo Loaded environment from uEnv.txt; " \ + "env import -t 0x44000000 ${filesize}; " \ + "fi; " \ + "setenv bootargs console=${console} root=${root} ${extraargs}; " \ + "ext2load mmc 0 0x43000000 script.bin && " \ + "ext2load mmc 0 0x48000000 uImage && " \ + "bootm 0x48000000\0" +#else +#define BOOTCMD_SUNXI_COMPAT +#endif + +#include + +#ifdef CONFIG_USB_KEYBOARD +#define CONSOLE_STDIN_SETTINGS \ + "stdin=serial,usbkbd\0" +#else +#define CONSOLE_STDIN_SETTINGS \ + "stdin=serial\0" +#endif + +#ifdef CONFIG_DM_VIDEO +#define CONSOLE_STDOUT_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" +#else +#define CONSOLE_STDOUT_SETTINGS \ + "stdout=serial\0" \ + "stderr=serial\0" +#endif + +#ifdef CONFIG_MTDIDS_DEFAULT +#define SUNXI_MTDIDS_DEFAULT \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" +#else +#define SUNXI_MTDIDS_DEFAULT +#endif + +#ifdef CONFIG_MTDPARTS_DEFAULT +#define SUNXI_MTDPARTS_DEFAULT \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" +#else +#define SUNXI_MTDPARTS_DEFAULT +#endif + +#define PARTS_DEFAULT \ + "name=loader1,start=8k,size=32k,uuid=${uuid_gpt_loader1};" \ + "name=loader2,size=984k,uuid=${uuid_gpt_loader2};" \ + "name=esp,size=128M,bootable,uuid=${uuid_gpt_esp};" \ + "name=system,size=-,uuid=${uuid_gpt_system};" + +#define UUID_GPT_ESP "c12a7328-f81f-11d2-ba4b-00a0c93ec93b" + +#ifdef CONFIG_ARM64 +#define UUID_GPT_SYSTEM "b921b045-1df0-41c3-af44-4c6f280d3fae" +#else +#define UUID_GPT_SYSTEM "69dad710-2ce4-4e3c-b16c-21a1d49abed3" +#endif + +#define CONSOLE_ENV_SETTINGS \ + CONSOLE_STDIN_SETTINGS \ + CONSOLE_STDOUT_SETTINGS + +#ifdef CONFIG_ARM64 +#define FDTFILE "allwinner/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#else +#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONSOLE_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + MEM_LAYOUT_ENV_EXTRA_SETTINGS \ + DFU_ALT_INFO_RAM \ + "fdtfile=" FDTFILE "\0" \ + "console=ttyS0,115200\0" \ + SUNXI_MTDIDS_DEFAULT \ + SUNXI_MTDPARTS_DEFAULT \ + "uuid_gpt_esp=" UUID_GPT_ESP "\0" \ + "uuid_gpt_system=" UUID_GPT_SYSTEM "\0" \ + "partitions=" PARTS_DEFAULT "\0" \ + BOOTCMD_SUNXI_COMPAT \ + BOOTENV + +#else /* ifndef CONFIG_SPL_BUILD */ +#define CONFIG_EXTRA_ENV_SETTINGS +#endif + +#endif /* _SUNXI_COMMON_CONFIG_H */ diff --git a/roms/u-boot/include/configs/syzygy_hub.h b/roms/u-boot/include/configs/syzygy_hub.h new file mode 100644 index 000000000..7af7b08eb --- /dev/null +++ b/roms/u-boot/include/configs/syzygy_hub.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 Xilinx + * (C) Copyright 2017 Opal Kelly Inc. + * + * Configuration settings for the SYZYGY Hub development board + * See zynq-common.h for Zynq common configs + */ + +#ifndef __CONFIG_SYZYGY_HUB_H +#define __CONFIG_SYZYGY_HUB_H + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fit_image=fit.itb\0" \ + "bitstream_image=download.bit\0" \ + "loadbit_addr=0x1000000\0" \ + "load_addr=0x2000000\0" \ + "fit_size=0x800000\0" \ + "flash_off=0x100000\0" \ + "nor_flash_off=0xE2100000\0" \ + "fdt_high=0x20000000\0" \ + "initrd_high=0x20000000\0" \ + "loadbootenv_addr=0x2000000\0" \ + "fdt_addr_r=0x1f00000\0" \ + "pxefile_addr_r=0x2000000\0" \ + "kernel_addr_r=0x2000000\0" \ + "scriptaddr=0x3000000\0" \ + "ramdisk_addr_r=0x3100000\0" \ + "bootenv=uEnv.txt\0" \ + "bootenv_dev=mmc\0" \ + "loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from ${bootenv_dev} ...; " \ + "env import -t ${loadbootenv_addr} $filesize\0" \ + "bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \ + "setbootenv=if env run bootenv_existence_test; then " \ + "if env run loadbootenv; then " \ + "env run importbootenv; " \ + "fi; " \ + "fi; \0" \ + "sd_loadbootenv=set bootenv_dev mmc && " \ + "run setbootenv \0" \ + "usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv\0" \ + "preboot=if test $modeboot = sdboot; then " \ + "run sd_loadbootenv; " \ + "echo Checking if uenvcmd is set ...; " \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi; " \ + "fi; \0" \ + "sdboot=echo Copying FPGA Bitstream from SD to RAM... && " \ + "load mmc 0 ${loadbit_addr} ${bitstream_image} && " \ + "echo Programming FPGA... && " \ + "fpga loadb 0 ${loadbit_addr} ${filesize} && " \ + "echo Copying FIT from SD to RAM... && " \ + "load mmc 0 ${load_addr} ${fit_image} && " \ + "bootm ${load_addr}\0" \ + "jtagboot=echo TFTPing FIT to RAM... && " \ + "tftpboot ${load_addr} ${fit_image} && " \ + "bootm ${load_addr}\0" \ + BOOTENV + +#include + +#endif /* __CONFIG_SYZYGY_HUB_H */ diff --git a/roms/u-boot/include/configs/t4qds.h b/roms/u-boot/include/configs/t4qds.h new file mode 100644 index 000000000..a5cbb112f --- /dev/null +++ b/roms/u-boot/include/configs/t4qds.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + */ + +/* + * Corenet DS style board configuration file + */ +#ifndef __T4QDS_H +#define __T4QDS_H + +/* High Level Configuration Options */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (512 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_DDR_SPD + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 + +/* + * RapidIO + */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ + +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#endif /* CONFIG_PCI */ + +/* SATA */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/tam3517-common.h b/roms/u-boot/include/configs/tam3517-common.h new file mode 100644 index 000000000..afc9adbe1 --- /dev/null +++ b/roms/u-boot/include/configs/tam3517-common.h @@ -0,0 +1,308 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright (C) 2009 TechNexion Ltd. + */ + +#ifndef __TAM3517_H +#define __TAM3517_H + +/* + * High Level Configuration Options + */ + +#include /* get chip and board defs */ +#include + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ + 2 * 1024 * 1024) +/* + * DDR related + */ +#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +/* + * select serial console configuration + */ +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 + +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +/* EHCI */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 + +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access */ + /* nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_MAXARGS 32 /* max number of command */ + /* args */ +/* memtest works on */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * AM3517 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +/* + * Physical Memory Map + */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Redundant Environment */ +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * ethernet support, EMAC + * + */ +#define CONFIG_NET_RETRY_COUNT 10 + +/* Defines for SPL */ +#define CONFIG_SPL_CONSOLE +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ + +#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ + CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +/* FAT */ +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" + +/* RAW SD card / eMMC */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ + +/* NAND boot config */ +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ + 48, 49, 50, 51, 52, 53, 54, 55,\ + 56, 57, 58, 59, 60, 61, 62, 63} +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 + +/* Setup MTD for NAND on the SOM */ + +#define CONFIG_TAM3517_SETTINGS \ + "netdev=eth0\0" \ + "nandargs=setenv bootargs root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip_sta=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ + "addip=if test -n ${ipdyn};then run addip_dyn;" \ + "else run addip_sta;fi\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttyO0,${baudrate}\0" \ + "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ + "loadaddr=82000000\0" \ + "kernel_addr_r=82000000\0" \ + "hostname=" CONFIG_HOSTNAME "\0" \ + "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ + "flash_self=run ramargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr}\0" \ + "nandboot=run nandargs addip addtty addmtd addmisc;" \ + "nand read ${kernel_addr_r} kernel\0" \ + "bootm ${kernel_addr_r}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr_r}\0" \ + "net_self=if run net_self_load;then " \ + "run ramargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ + "else echo Images not loades;fi\0" \ + "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "loadmlo=tftp ${loadaddr} ${mlo}\0" \ + "mlo=" CONFIG_HOSTNAME "/MLO\0" \ + "uboot_addr=0x80000\0" \ + "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ + "nand write ${loadaddr} ${uboot_addr} 80000\0" \ + "updatemlo=nandecc hw;nand erase 0 20000;" \ + "nand write ${loadaddr} 0 20000\0" \ + "upd=if run load;then echo Updating u-boot;if run update;" \ + "then echo U-Boot updated;" \ + "else echo Error updating u-boot !;" \ + "echo Board without bootloader !!;" \ + "fi;" \ + "else echo U-Boot not downloaded..exiting;fi\0" \ + +/* + * this is common code for all TAM3517 boards. + * MAC address is stored from manufacturer in + * I2C EEPROM + */ +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +/* + * The I2C EEPROM on the TAM3517 contains + * mac address and production data + */ +struct tam3517_module_info { + char customer[48]; + char product[48]; + + /* + * bit 0~47 : sequence number + * bit 48~55 : week of year, from 0. + * bit 56~63 : year + */ + unsigned long long sequence_number; + + /* + * bit 0~7 : revision fixed + * bit 8~15 : revision major + * bit 16~31 : TNxxx + */ + unsigned int revision; + unsigned char eth_addr[4][8]; + unsigned char _rev[100]; +}; + +#define TAM3517_READ_EEPROM(info, ret) \ +do { \ + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ + if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ + (void *)info, sizeof(*info))) \ + ret = 1; \ + else \ + ret = 0; \ +} while (0) + +#define TAM3517_READ_MAC_FROM_EEPROM(info) \ +do { \ + char buf[80], ethname[20]; \ + int i; \ + memset(buf, 0, sizeof(buf)); \ + for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ + sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ + (info)->eth_addr[i][5], \ + (info)->eth_addr[i][4], \ + (info)->eth_addr[i][3], \ + (info)->eth_addr[i][2], \ + (info)->eth_addr[i][1], \ + (info)->eth_addr[i][0]); \ + \ + if (i) \ + sprintf(ethname, "eth%daddr", i); \ + else \ + strcpy(ethname, "ethaddr"); \ + printf("Setting %s from EEPROM with %s\n", ethname, buf);\ + env_set(ethname, buf); \ + } \ +} while (0) + +/* The following macros are taken from Technexion's documentation */ +#define TAM3517_sequence_number(info) \ + ((info)->sequence_number % 0x1000000000000LL) +#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) +#define TAM3517_year(info) ((info)->sequence_number >> 56) +#define TAM3517_revision_fixed(info) ((info)->revision % 0x100) +#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) +#define TAM3517_revision_tn(info) ((info)->revision >> 16) + +#define TAM3517_PRINT_SOM_INFO(info) \ +do { \ + printf("Vendor:%s\n", (info)->customer); \ + printf("SOM: %s\n", (info)->product); \ + printf("SeqNr: %02llu%02llu%012llu\n", \ + TAM3517_year(info), \ + TAM3517_week_of_year(info), \ + TAM3517_sequence_number(info)); \ + printf("Rev: TN%u %u.%u\n", \ + TAM3517_revision_tn(info), \ + TAM3517_revision_major(info), \ + TAM3517_revision_fixed(info)); \ +} while (0) + +#endif + +#endif /* __TAM3517_H */ diff --git a/roms/u-boot/include/configs/taurus.h b/roms/u-boot/include/configs/taurus.h new file mode 100644 index 000000000..39eae8e2b --- /dev/null +++ b/roms/u-boot/include/configs/taurus.h @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Common board functions for Siemens TAURUS (AT91SAM9G20) based boards + * (C) Copyright 2013 Siemens AG + * + * Based on: + * U-Boot file: include/configs/at91sam9260ek.h + * + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include +#include + +/* + * Warning: changing CONFIG_SYS_TEXT_BASE requires + * adapting the initial boot program. + * Since the linker has to swallow that define, we must use a pure + * hex number here! + */ + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ + +/* Misc CPU related */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ + +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS + +/* + * SDRAM: 1 bank, min 32, max 128 MB + * Initialized before u-boot gets started. + */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) + +/* + * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, + * leaving the correct space for initial global data structure above + * that address while providing maximum stack area below. + */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 +#endif + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_AT91_WANTS_COMMON_PHY + +/* USB */ +#if defined(CONFIG_BOARD_TAURUS) +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +/* USB DFU support */ + +#define CONFIG_USB_GADGET_AT91 + +/* DFU class support */ +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) +#define DFU_MANIFEST_POLL_TIMEOUT 25000 +#endif + +/* SPI EEPROM */ +#define TAURUS_SPI_MASK (1 << 4) + +#if defined(CONFIG_SPL_BUILD) +/* SPL related */ +#endif + +/* load address */ +#define CONFIG_SYS_LOAD_ADDR 0x22000000 + +/* bootstrap in spi flash , u-boot + env + linux in nandflash */ + +#ifndef CONFIG_SPL_BUILD +#if defined(CONFIG_BOARD_AXM) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ + "${gatewayip}:${netmask}:${hostname}:${netdev}::off\0" \ + "addtest=setenv bootargs ${bootargs} loglevel=4 test\0" \ + "boot_file=setenv bootfile /${project_dir}/kernel/uImage\0" \ + "boot_retries=0\0" \ + "ethact=macb0\0" \ + "flash_nfs=run nand_kernel;run nfsargs;run addip;" \ + "upgrade_available;bootm ${kernel_ram};reset\0" \ + "flash_self=run nand_kernel;run setbootargs;upgrade_available;" \ + "bootm ${kernel_ram};reset\0" \ + "flash_self_test=run nand_kernel;run setbootargs addtest;" \ + "upgrade_available;bootm ${kernel_ram};reset\0" \ + "hostname=systemone\0" \ + "kernel_Off=0x00200000\0" \ + "kernel_Off_fallback=0x03800000\0" \ + "kernel_ram=0x21500000\0" \ + "kernel_size=0x00400000\0" \ + "kernel_size_fallback=0x00400000\0" \ + "loads_echo=1\0" \ + "nand_kernel=nand read.e ${kernel_ram} ${kernel_Off} " \ + "${kernel_size}\0" \ + "net_nfs=run boot_file;tftp ${kernel_ram} ${bootfile};" \ + "run nfsargs;run addip;upgrade_available;" \ + "bootm ${kernel_ram};reset\0" \ + "netdev=eth0\0" \ + "nfsargs=run root_path;setenv bootargs ${bootargs} root=/dev/nfs " \ + "rw nfsroot=${serverip}:${rootpath} " \ + "at91sam9_wdt.wdt_timeout=16\0" \ + "partitionset_active=A\0" \ + "preboot=echo;echo Type 'run flash_self' to use kernel and root " \ + "filesystem on memory;echo Type 'run flash_nfs' to use " \ + "kernel from memory and root filesystem over NFS;echo Type " \ + "'run net_nfs' to get Kernel over TFTP and mount root " \ + "filesystem over NFS;echo\0" \ + "project_dir=systemone\0" \ + "root_path=setenv rootpath /home/projects/${project_dir}/rootfs\0" \ + "rootfs=/dev/mtdblock5\0" \ + "rootfs_fallback=/dev/mtdblock7\0" \ + "setbootargs=setenv bootargs ${bootargs} console=ttyMTD,mtdoops " \ + "root=${rootfs} rootfstype=jffs2 panic=7 " \ + "at91sam9_wdt.wdt_timeout=16\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "upgrade_available=0\0" +#endif +#endif /* #ifndef CONFIG_SPL_BUILD */ +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN \ + ROUND(3 * CONFIG_ENV_SIZE + SZ_4M, 0x1000) + +/* Defines for SPL */ +#define CONFIG_SPL_MAX_SIZE (31 * SZ_512) +#define CONFIG_SPL_STACK (ATMEL_BASE_SRAM1 + SZ_16K) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN + +#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_BSS_MAX_SIZE (3 * SZ_512) + +#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) +#define CONFIG_SYS_USE_NANDFLASH 1 +#define CONFIG_SPL_NAND_RAW_ONLY +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +#define CONFIG_SYS_NAND_SIZE (256 * SZ_1M) +#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K +#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } + +#define CONFIG_SPL_ATMEL_SIZE +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define AT91_PLL_LOCK_TIMEOUT 1000000 +#define CONFIG_SYS_AT91_PLLA 0x202A3F01 +#define CONFIG_SYS_MCKR 0x1300 +#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) +#define CONFIG_SYS_AT91_PLLB 0x10193F05 + +#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO + +#endif diff --git a/roms/u-boot/include/configs/tb100.h b/roms/u-boot/include/configs/tb100.h new file mode 100644 index 000000000..f42b0df1c --- /dev/null +++ b/roms/u-boot/include/configs/tb100.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011-2014 Pierrick Hascoet, Abilis Systems + */ + +#ifndef _CONFIG_TB100_H_ +#define _CONFIG_TB100_H_ + +#include + +/* + * Memory configuration + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE SZ_128M + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN SZ_128K +#define CONFIG_SYS_BOOTM_LEN SZ_32M +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +/* + * UART configuration + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK 166666666 + +/* + * Even though the board houses Realtek RTL8211E PHY + * corresponding PHY driver (drivers/net/phy/realtek.c) behaves unexpectedly. + * In particular "parse_status" reports link is down. + * + * Until Realtek PHY driver is fixed fall back to generic PHY driver + * which implements all required functionality and behaves much more stable. + * + * + */ + +/* + * Ethernet configuration + */ +#define ETH0_BASE_ADDRESS 0xFE100000 +#define ETH1_BASE_ADDRESS 0xFE110000 + +/* + * Environment configuration + */ +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ + +#endif /* _CONFIG_TB100_H_ */ diff --git a/roms/u-boot/include/configs/tbs2910.h b/roms/u-boot/include/configs/tbs2910.h new file mode 100644 index 000000000..a2e59ce61 --- /dev/null +++ b/roms/u-boot/include/configs/tbs2910.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Soeren Moch + * + * Configuration settings for the TBS2910 MatrixARM board. + */ + +#ifndef __TBS2910_CONFIG_H +#define __TBS2910_CONFIG_H + +#include "mx6_common.h" + +/* General configuration */ + +#define CONFIG_MACH_TYPE 3980 + +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) + +#define CONFIG_SYS_BOOTMAPSZ 0x10000000 + +/* Serial console */ +#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ + +/* Framebuffer */ +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +/* PCI */ +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) +#endif + +/* SATA */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_SYS_64BIT_LBA +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#ifdef CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USBD_HS +#endif /* CONFIG_CMD_USB_MASS_STORAGE */ +#endif /* CONFIG_CMD_USB */ + +#define CONFIG_BOARD_SIZE_LIMIT 392192 /* (CONFIG_ENV_OFFSET - 1024) */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \ + "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \ + "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \ + "bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \ + "bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \ + "${bootargs_mmc3}\0" \ + "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \ + "rdinit=/sbin/init enable_wait_mode=off\0" \ + "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \ + "mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \ + "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \ + "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \ + "run bootargs_upd; " \ + "bootm 0x10800000 0x10d00000\0" \ + "console=ttymxc0\0" \ + "fan=gpio set 92\0" \ + "fdt_addr_r=0x18000000\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "kernel_addr_r=0x12000000\0" \ + "pxefile_addr_r=0x10100000\0" \ + "ramdisk_addr_r=0x18080000\0" \ + "scriptaddr=0x10000000\0" \ + "set_con_serial=setenv stdout serial; " \ + "setenv stderr serial\0" \ + "set_con_hdmi=setenv stdout serial,vidconsole; " \ + "setenv stderr serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" + +/* Enable distro boot */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(SATA, sata, 0) \ + func(USB, usb, 0) + +#include + +#endif /* __TBS2910_CONFIG_H * */ diff --git a/roms/u-boot/include/configs/tec-ng.h b/roms/u-boot/include/configs/tec-ng.h new file mode 100644 index 000000000..2bc531c46 --- /dev/null +++ b/roms/u-boot/include/configs/tec-ng.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 + * Avionic Design GmbH + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra30-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTD +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +/* Environment in eMMC, at the end of 2nd "boot sector" */ + +/* SPI */ +#define CONFIG_TEGRA_SLINK_CTRLS 6 +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* Tag support */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/tec.h b/roms/u-boot/include/configs/tec.h new file mode 100644 index 000000000..aa9665eab --- /dev/null +++ b/roms/u-boot/include/configs/tec.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + * (C) Copyright 2011-2012 + * Avionic Design GmbH + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra20-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +/* NAND support */ +#define CONFIG_TEGRA_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Environment in NAND, aligned to start of last sector */ + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/tegra-common-post.h b/roms/u-boot/include/configs/tegra-common-post.h new file mode 100644 index 000000000..fae0e761f --- /dev/null +++ b/roms/u-boot/include/configs/tegra-common-post.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation + */ + +#ifndef __TEGRA_COMMON_POST_H +#define __TEGRA_COMMON_POST_H + +/* + * Size of malloc() pool + */ +#ifdef CONFIG_DFU_OVER_USB +#define CONFIG_SYS_MALLOC_LEN (SZ_4M + \ + CONFIG_SYS_DFU_DATA_BUF_SIZE + \ + CONFIG_SYS_DFU_MAX_FILE_SIZE) +#else +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ +#endif + +#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ + +#ifndef CONFIG_SPL_BUILD +#ifndef BOOT_TARGET_DEVICES +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) +#endif +#include +#else +#define BOOTENV +#endif + +#ifdef CONFIG_TEGRA_KEYBOARD +#define STDIN_KBD_KBC ",tegra-kbc" +#else +#define STDIN_KBD_KBC "" +#endif + +#ifdef CONFIG_USB_KEYBOARD +#define STDIN_KBD_USB ",usbkbd" +#else +#define STDIN_KBD_USB "" +#endif + +#ifdef CONFIG_LCD +#define STDOUT_LCD ",lcd" +#else +#define STDOUT_LCD "" +#endif + +#ifdef CONFIG_DM_VIDEO +#define STDOUT_VIDEO ",vidconsole" +#else +#define STDOUT_VIDEO "" +#endif + +#ifdef CONFIG_CROS_EC_KEYB +#define STDOUT_CROS_EC ",cros-ec-keyb" +#else +#define STDOUT_CROS_EC "" +#endif + +#define TEGRA_DEVICE_SETTINGS \ + "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB STDOUT_CROS_EC "\0" \ + "stdout=serial" STDOUT_LCD STDOUT_VIDEO "\0" \ + "stderr=serial" STDOUT_LCD STDOUT_VIDEO "\0" \ + "" + +#ifndef BOARD_EXTRA_ENV_SETTINGS +#define BOARD_EXTRA_ENV_SETTINGS +#endif + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#ifndef CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS +#define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS +#endif + +#ifdef CONFIG_ARM64 +#define FDT_HIGH "ffffffffffffffff" +#define INITRD_HIGH "ffffffffffffffff" +#else +#define FDT_HIGH "ffffffff" +#define INITRD_HIGH "ffffffff" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + TEGRA_DEVICE_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + "fdt_high=" FDT_HIGH "\0" \ + "initrd_high=" INITRD_HIGH "\0" \ + BOOTENV \ + BOARD_EXTRA_ENV_SETTINGS \ + CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS + +#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) +#define CONFIG_TEGRA_SPI +#endif + +/* overrides for SPL build here */ +#ifdef CONFIG_SPL_BUILD + +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY + +/* remove I2C support */ +#ifdef CONFIG_SYS_I2C_TEGRA +#undef CONFIG_SYS_I2C_TEGRA +#endif + +/* remove USB */ +#ifdef CONFIG_USB_EHCI_TEGRA +#undef CONFIG_USB_EHCI_TEGRA +#endif + +#endif /* CONFIG_SPL_BUILD */ + +#endif /* __TEGRA_COMMON_POST_H */ diff --git a/roms/u-boot/include/configs/tegra-common-usb-gadget.h b/roms/u-boot/include/configs/tegra-common-usb-gadget.h new file mode 100644 index 000000000..e6b61c4e8 --- /dev/null +++ b/roms/u-boot/include/configs/tegra-common-usb-gadget.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2014 + * NVIDIA Corporation + */ + +#ifndef _TEGRA_COMMON_USB_GADGET_H_ +#define _TEGRA_COMMON_USB_GADGET_H_ + +#ifndef CONFIG_SPL_BUILD +/* USB gadget mode support*/ +#ifndef CONFIG_TEGRA20 +#define CONFIG_CI_UDC_HAS_HOSTPC +#endif +/* DFU protocol */ +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M +#define CONFIG_SYS_DFU_MAX_FILE_SIZE SZ_32M +#endif + +#endif /* _TEGRA_COMMON_USB_GADGET_H_ */ diff --git a/roms/u-boot/include/configs/tegra-common.h b/roms/u-boot/include/configs/tegra-common.h new file mode 100644 index 000000000..432eceaf3 --- /dev/null +++ b/roms/u-boot/include/configs/tegra-common.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation + */ + +#ifndef _TEGRA_COMMON_H_ +#define _TEGRA_COMMON_H_ +#include +#include + +/* + * High Level Configuration Options + */ +#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ + +#include /* get chip and board defs */ + +/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ +#ifndef CONFIG_ARM64 +#define CONFIG_SYS_TIMER_RATE 1000000 +#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE +#endif + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ + +/* Environment */ + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * Common HW configuration. + * If this varies between SoCs later, move to tegraNN-common.h + * Note: This is number of devices, not max device ID. + */ +#define CONFIG_SYS_MMC_MAX_DEVICE 4 + +/* + * Increasing the size of the IO buffer as default nfsargs size is more + * than 256 and so it is not possible to edit it + */ +#define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#ifdef CONFIG_ARM64 +#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#else +#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define PHYS_SDRAM_1 NV_PA_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ + +#ifndef CONFIG_ARM64 +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#endif + +#ifndef CONFIG_ARM64 +/* Defines for SPL */ +#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SPL_TEXT_BASE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 +#endif + +#endif /* _TEGRA_COMMON_H_ */ diff --git a/roms/u-boot/include/configs/tegra114-common.h b/roms/u-boot/include/configs/tegra114-common.h new file mode 100644 index 000000000..9d751b674 --- /dev/null +++ b/roms/u-boot/include/configs/tegra114-common.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA114_COMMON_H_ +#define _TEGRA114_COMMON_H_ +#include "tegra-common.h" + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_STACKBASE 0x83800000 /* 56MB */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 32M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for + * the compressed kernel to be up to 32M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define CONFIG_LOADADDR 0x81000000 +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x83000000\0" \ + "ramdisk_addr_r=0x83100000\0" + +/* Defines for SPL */ +#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 +#define CONFIG_SPL_STACK 0x800ffffc + +/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 + +#endif /* _TEGRA114_COMMON_H_ */ diff --git a/roms/u-boot/include/configs/tegra124-common.h b/roms/u-boot/include/configs/tegra124-common.h new file mode 100644 index 000000000..0eb8f9280 --- /dev/null +++ b/roms/u-boot/include/configs/tegra124-common.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 + * NVIDIA Corporation + */ + +#ifndef _TEGRA124_COMMON_H_ +#define _TEGRA124_COMMON_H_ + +#include "tegra-common.h" + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_STACKBASE 0x83800000 /* 56MB */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 32M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for + * the compressed kernel to be up to 32M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define CONFIG_LOADADDR 0x81000000 +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x83000000\0" \ + "ramdisk_addr_r=0x83100000\0" + +/* Defines for SPL */ +#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 +#define CONFIG_SPL_STACK 0x800ffffc + +/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 + +/* GPU needs setup */ +#define CONFIG_TEGRA_GPU + +#endif /* _TEGRA124_COMMON_H_ */ diff --git a/roms/u-boot/include/configs/tegra186-common.h b/roms/u-boot/include/configs/tegra186-common.h new file mode 100644 index 000000000..d5f21e090 --- /dev/null +++ b/roms/u-boot/include/configs/tegra186-common.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2013-2016, NVIDIA CORPORATION. + */ + +#ifndef _TEGRA186_COMMON_H_ +#define _TEGRA186_COMMON_H_ + +#include "tegra-common.h" + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ + +/* Generic Interrupt Controller */ +#define CONFIG_GICV2 + +#undef FDTFILE +#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \ + "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \ + "setenv efi_fdtfile ${vendor}/${soc}-${board}${boardver}.dtb; " \ + "fi; " + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define CONFIG_LOADADDR 0x80080000 +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdt_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x82100000\0" + +#endif diff --git a/roms/u-boot/include/configs/tegra20-common.h b/roms/u-boot/include/configs/tegra20-common.h new file mode 100644 index 000000000..fdd899695 --- /dev/null +++ b/roms/u-boot/include/configs/tegra20-common.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation + */ + +#ifndef _TEGRA20_COMMON_H_ +#define _TEGRA20_COMMON_H_ +#include "tegra-common.h" + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_STACKBASE 0x03800000 /* 56MB */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 32M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for + * the compressed kernel to be up to 32M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define CONFIG_LOADADDR 0x01000000 +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x10000000\0" \ + "pxefile_addr_r=0x10100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x03000000\0" \ + "ramdisk_addr_r=0x03100000\0" + +/* Defines for SPL */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00090000 +#define CONFIG_SPL_STACK 0x000ffffc + +/* Align LCD to 1MB boundary */ +#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE + +#ifdef CONFIG_TEGRA_LP0 +#define TEGRA_LP0_ADDR 0x1C406000 +#define TEGRA_LP0_SIZE 0x2000 +#define TEGRA_LP0_VEC \ + "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ + "@" __stringify(TEGRA_LP0_ADDR) " " +#else +#define TEGRA_LP0_VEC +#endif + +/* + * This parameter affects a TXFILLTUNING field that controls how much data is + * sent to the latency fifo before it is sent to the wire. Without this + * parameter, the default (2) causes occasional Data Buffer Errors in OUT + * packets depending on the buffer address and size. + */ +#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 +#define CONFIG_EHCI_IS_TDI + +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#endif /* _TEGRA20_COMMON_H_ */ diff --git a/roms/u-boot/include/configs/tegra210-common.h b/roms/u-boot/include/configs/tegra210-common.h new file mode 100644 index 000000000..2226effe1 --- /dev/null +++ b/roms/u-boot/include/configs/tegra210-common.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation + */ + +#ifndef _TEGRA210_COMMON_H_ +#define _TEGRA210_COMMON_H_ + +#include "tegra-common.h" + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ + +/* Generic Interrupt Controller */ +#define CONFIG_GICV2 + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define CONFIG_LOADADDR 0x80080000 +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x83000000\0" \ + "ramdisk_addr_r=0x83200000\0" + +/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 + +/* GPU needs setup */ +#define CONFIG_TEGRA_GPU + +#endif /* _TEGRA210_COMMON_H_ */ diff --git a/roms/u-boot/include/configs/tegra30-common.h b/roms/u-boot/include/configs/tegra30-common.h new file mode 100644 index 000000000..6c5dc24b2 --- /dev/null +++ b/roms/u-boot/include/configs/tegra30-common.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation + */ + +#ifndef _TEGRA30_COMMON_H_ +#define _TEGRA30_COMMON_H_ +#include "tegra-common.h" + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_STACKBASE 0x83800000 /* 56MB */ + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 32M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for + * the compressed kernel to be up to 32M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define CONFIG_LOADADDR 0x81000000 +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x83000000\0" \ + "ramdisk_addr_r=0x83100000\0" + +/* Defines for SPL */ +#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 +#define CONFIG_SPL_STACK 0x800ffffc + +/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 + +#endif /* _TEGRA30_COMMON_H_ */ diff --git a/roms/u-boot/include/configs/theadorable-x86-common.h b/roms/u-boot/include/configs/theadorable-x86-common.h new file mode 100644 index 000000000..193c6c3bb --- /dev/null +++ b/roms/u-boot/include/configs/theadorable-x86-common.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Stefan Roese + */ + +/* + * Common options, macros and default environment for all + * theadorable x86 based boards + */ + +#ifndef __THEADORABLE_X86_COMMON_H +#define __THEADORABLE_X86_COMMON_H + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +/* Environment settings */ + +#undef CONFIG_BOOTCOMMAND +#undef CONFIG_EXTRA_ENV_SETTINGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "tftpdir=" DEF_ENV_TFTPDIR "\0" \ + "eth_init=" DEF_ENV_ETH_INIT "\0" \ + "ubuntu_part=" __stringify(DEF_ENV_UBUNTU_PART) "\0" \ + "yocto_part=" __stringify(DEF_ENV_YOCTO_PART) "\0" \ + "ubuntu_tty=" __stringify(DEF_ENV_UBUNTU_TTY) "\0" \ + "yocto_tty=" __stringify(DEF_ENV_YOCTO_TTY) "\0" \ + "start_eth=if test -n \"${eth_init}\";" \ + "then run eth_init;else sleep 0;fi\0" \ + "kernel-ver=4.8.0-54-generic\0" \ + "boot=zboot 03000000 0 04000000 ${filesize}\0" \ + "mtdparts=mtdparts=intel-spi:4k(descriptor),7084k(me)," \ + "8k(env1),8k(env2),64k(mrc),640k(u-boot)," \ + "64k(vga),-(fsp)\0" \ + "addtty_ubuntu=setenv bootargs ${bootargs} " \ + "console=ttyS${ubuntu_tty},${baudrate}\0" \ + "addtty_yocto=setenv bootargs ${bootargs} " \ + "console=ttyS${yocto_tty},${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addmisc=setenv bootargs ${bootargs} " \ + "intel-spi.writeable=1 vmalloc=300M " \ + "pci=realloc=on,hpmemsize=0,hpiosize=0\0" \ + "bootcmd=if env exists recovery_status;" \ + "then run swupdate;" \ + "else run yocto_boot;run swupdate;" \ + "fi\0" \ + "setroot=part uuid scsi 0:${partnr} uuid;" \ + "setenv root PARTUUID=${uuid}\0" \ + "setroot_ubuntu=setenv partnr ${ubuntu_part};run setroot\0" \ + "setroot_yocto=setenv partnr ${yocto_part};run setroot\0" \ + "ubuntu_args=setenv bootargs " \ + "root=${root} ro\0" \ + "ubuntu_args_quiet=setenv bootargs " \ + "root=${root} ro quiet\0" \ + "ubuntu_load=load scsi 0:${ubuntu_part} 03000000 " \ + "/boot/vmlinuz-${kernel-ver};" \ + "load scsi 0:${ubuntu_part} 04000000 " \ + "/boot/initrd.img-${kernel-ver}\0" \ + "ubuntu_boot=run setroot_ubuntu ubuntu_args_quiet " \ + "addmtd addmisc ubuntu_load boot\0" \ + "ubuntu_boot_console=run setroot_ubuntu ubuntu_args " \ + "addtty_ubuntu addmtd addmisc ubuntu_load boot\0" \ + "net_args=setenv bootargs root=${root} ro\0" \ + "net_boot=run start_eth setroot_ubuntu net_args " \ + "addtty_ubuntu addmtd addmisc;" \ + "tftp 03000000 ${tftpdir}/bzImage;" \ + "load scsi 0:${ubuntu_part} 04000000 " \ + "/boot/initrd.img-${kernel-ver};" \ + "run boot\0" \ + "yocto_args=setenv bootargs root=${root} " \ + "panic=1\0" \ + "yocto_args_fast=setenv bootargs root=${root} " \ + "quiet panic=1\0" \ + "yocto_boot=run setroot_yocto yocto_args addmtd addmisc " \ + "addtty_yocto;" \ + "if run yocto_load;then zboot 03000000;fi\0" \ + "yocto_boot_fast=run setroot_yocto yocto_args_fast addmtd " \ + "addmisc addtty_yocto yocto_load;zboot 03000000\0" \ + "yocto_boot_tftp=run setroot_yocto yocto_args addmtd " \ + "addmisc addtty_yocto " \ + "start_eth yocto_load_tftp;zboot 03000000\0" \ + "yocto_kernel=bzImage\0" \ + "yocto_load=load scsi 0:${yocto_part} 03000000 " \ + "/boot/${yocto_kernel}\0" \ + "yocto_load_tftp=tftp 03000000 dfi/bzImage\0" \ + "swupdate=if env exists swupdate_factory;" \ + "then run swupdate_usb;run swupdate_run;" \ + "else setenv swupdate_part 2;run swupdate_mmc;" \ + "run swupdate_run;setenv swupdate_part 1;" \ + "run swupdate_mmc;run swupdate_usb;" \ + "run swupdate_run;" \ + "fi\0" \ + "swupdate-initrd=/boot/swupdate-image-theadorable.ext4.gz\0" \ + "swupdate-kernel=/boot/bzImage\0" \ + "swupdate_args=setenv bootargs root=/dev/ram rw panic=1\0" \ + "swupdate_dev=0\0" \ + "swupdate_factory=0\0" \ + "swupdate_interface=usb\0" \ + "swupdate_kernel=vmlinuz-4.4.0-28-generic\0" \ + "swupdate_load=load ${swupdate_interface} ${swupdate_dev}:" \ + "${swupdate_part} 03000000 ${swupdate-kernel}" \ + " && load ${swupdate_interface} ${swupdate_dev}:" \ + "${swupdate_part} 04000000 ${swupdate-initrd}\0" \ + "swupdate_mmc=setenv swupdate_interface mmc;" \ + "setenv swupdate_dev ${swupdate_mmcdev};" \ + "setenv swupdate_part 1;" \ + "mmc dev ${swupdate_dev};mmc rescan\0" \ + "swupdate_mmcdev=0\0" \ + "swupdate_part=1\0" \ + "swupdate_run=run swupdate_args addtty_yocto addmtd addmisc;" \ + "if run swupdate_load;then run boot;" \ + "else echo SWUpdate cannot be started from " \ + "${swupdate_interface};" \ + "fi\0" \ + "swupdate_usb=setenv swupdate_interface usb;" \ + "setenv swupdate_dev 0;setenv swupdate_part 1;" \ + "usb start\0" \ + "logo_tftp=tftp ${loadaddr} ${tftpdir}/logo.bmp;" \ + "bmp display ${loadaddr}\0" \ + "preboot=scsi scan;load scsi 0:${ubuntu_part} ${loadaddr} " \ + "/boot/logo/logo.bmp;bmp display ${loadaddr}\0" \ + "rootpath=/tftpboot/theadorable-x86-conga/work/" \ + "rootfs-yocto-swupdate-2017-03-29\0" \ + "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ + "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ + "set_bootargs_nfs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},tcp,nfsvers=3\0" \ + "net_nfs=run start_eth set_bootargs_nfs addtty_yocto addip " \ + "addmtd addmisc;tftp 03000000 ${tftpdir}/bzImage;" \ + "zboot 03000000\0" \ + "load_uboot=tftp ${loadaddr} ${tftpdir}/u-boot.rom\0" \ + "update_uboot=sf probe;" \ + "sf update ${loadaddr} 0 800000;saveenv\0" \ + "upd_uboot=run start_eth load_uboot update_uboot\0" + +#endif /* __THEADORABLE_X86_COMMON_H */ diff --git a/roms/u-boot/include/configs/theadorable-x86-conga-qa3-e3845.h b/roms/u-boot/include/configs/theadorable-x86-conga-qa3-e3845.h new file mode 100644 index 000000000..1c4362db5 --- /dev/null +++ b/roms/u-boot/include/configs/theadorable-x86-conga-qa3-e3845.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Stefan Roese + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* Set the board specific parameters */ +#define DEF_ENV_TFTPDIR "theadorable-x86-conga" +#define DEF_ENV_ETH_INIT "" +#define DEF_ENV_UBUNTU_PART 2 +#define DEF_ENV_UBUNTU_TTY 0 /* Use ttyS0 */ +#define DEF_ENV_YOCTO_PART 3 +#define DEF_ENV_YOCTO_TTY 0 /* Use ttyS0 */ + +/* + * Include the theadorable-x86 common options, macros and default + * environment + */ +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/theadorable-x86-dfi-bt700.h b/roms/u-boot/include/configs/theadorable-x86-dfi-bt700.h new file mode 100644 index 000000000..bb3186e21 --- /dev/null +++ b/roms/u-boot/include/configs/theadorable-x86-dfi-bt700.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Stefan Roese + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* Use BayTrail internal HS UART which is memory-mapped */ +#undef CONFIG_SYS_NS16550_PORT_MAPPED + +/* Set the board specific parameters */ +#define DEF_ENV_TFTPDIR "theadorable-x86-dfi" +#define DEF_ENV_ETH_INIT "usb reset" +#define DEF_ENV_UBUNTU_PART 1 +#define DEF_ENV_UBUNTU_TTY 4 /* Use ttyS4 */ +#define DEF_ENV_YOCTO_PART 2 +#define DEF_ENV_YOCTO_TTY 1 /* Use ttyS1 */ + +/* + * Include the theadorable-x86 common options, macros and default + * environment + */ +#include + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/theadorable.h b/roms/u-boot/include/configs/theadorable.h new file mode 100644 index 000000000..587b134a1 --- /dev/null +++ b/roms/u-boot/include/configs/theadorable.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015-2016 Stefan Roese + */ + +#ifndef _CONFIG_THEADORABLE_H +#define _CONFIG_THEADORABLE_H + +/* + * High Level Configuration Options (easy to change) + */ + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* + * The debugging version enables USB support via defconfig. + * This version should also enable all other non-production + * interfaces / features. + */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 + +/* Environment in SPI NOR flash */ + +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* Keep device tree and initrd in lower memory so the kernel can access them */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +/* SATA support */ +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_LBA48 + +/* Enable LCD and reserve 512KB from top of memory*/ +#define CONFIG_SYS_MEM_TOP_HIDE 0x80000 + +/* FPGA programming support */ +#define CONFIG_FPGA_STRATIX_V + +/* + * Bootcounter + */ +/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */ +#define BOOTCOUNT_ADDR 0x1000 + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * Memory layout while starting into the bin_hdr via the + * BootROM: + * + * 0x4000.4000 - 0x4003.4000 headers space (192KiB) + * 0x4000.4030 bin_hdr start address + * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) + * 0x4007.fffc BootROM stack top + * + * The address space between 0x4007.fffc and 0x400f.fff is not locked in + * L2 cache thus cannot be used. + */ + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +/* SPL related SPI defines */ +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS + +/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ +#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ + +#endif /* _CONFIG_THEADORABLE_H */ diff --git a/roms/u-boot/include/configs/thuban.h b/roms/u-boot/include/configs/thuban.h new file mode 100644 index 000000000..15a8469fe --- /dev/null +++ b/roms/u-boot/include/configs/thuban.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef __CONFIG_THUBAN_H +#define __CONFIG_THUBAN_H + +#include "siemens-am33x-common.h" + +#define DDR_PLL_FREQ 303 + +#define BOARD_DFU_BUTTON_GPIO 27 /* Use as default */ +#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ + +#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + "button_dfu0=27\0" \ + "led0=103,1,0\0" \ + "led1=64,0,1\0" + + /* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define EEPROM_ADDR_DDR3 0x90 +#define EEPROM_ADDR_CHIP 0x120 + +#define CONFIG_FACTORYSET + +/* Define own nand partitions */ +#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) + +#ifndef CONFIG_SPL_BUILD + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=thuban\0" \ + "ubi_off=2048\0"\ + "nand_img_size=0x400000\0" \ + "optargs=\0" \ + "preboot=draco_led 0\0" \ + CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + CONFIG_ENV_SETTINGS_V2 \ + CONFIG_ENV_SETTINGS_NAND_V2 + +#ifndef CONFIG_RESTORE_FLASH +/* set to negative value for no autoboot */ + +#define CONFIG_BOOTCOMMAND \ +"if dfubutton; then " \ + "run dfu_start; " \ + "reset; " \ +"fi;" \ +"run nand_boot;" \ +"run nand_boot_backup;" \ +"reset;" + +#else + +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif +#endif /* CONFIG_SPL_BUILD */ +#endif /* ! __CONFIG_THUBAN_H */ diff --git a/roms/u-boot/include/configs/thunderx_88xx.h b/roms/u-boot/include/configs/thunderx_88xx.h new file mode 100644 index 000000000..4d3c58d1e --- /dev/null +++ b/roms/u-boot/include/configs/thunderx_88xx.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/** + * (C) Copyright 2014, Cavium Inc. +**/ + +#ifndef __THUNDERX_88XX_H__ +#define __THUNDERX_88XX_H__ + +#define CONFIG_REMAKE_ELF + +#define CONFIG_THUNDERX + +#define CONFIG_SYS_64BIT + +#define MEM_BASE 0x00500000 + +#define CONFIG_SYS_LOWMEM_BASE MEM_BASE + +/* Link Definitions */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +/* SMP Spin Table Definitions */ +#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) + +/* PL011 Serial Configuration */ + +#define CONFIG_PL011_CLOCK 24000000 + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE (0x801000000000) +#define GICR_BASE (0x801000002000) +#define CONFIG_SYS_SERIAL0 0x87e024000000 +#define CONFIG_SYS_SERIAL1 0x87e025000000 + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (MEM_BASE) + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Initial environment variables */ +#define UBOOT_IMG_HEAD_SIZE 0x40 +/* C80000 - 0x40 */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=08007ffc0\0" \ + "fdt_addr=0x94C00000\0" \ + "fdt_high=0x9fffffff\0" + +/* Do not preserve environment */ + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 64 /* max command args */ +#define CONFIG_NO_RELOCATION 1 +#define PLL_REF_CLK 50000000 /* 50 MHz */ +#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) + +#endif /* __THUNDERX_88XX_H__ */ diff --git a/roms/u-boot/include/configs/ti814x_evm.h b/roms/u-boot/include/configs/ti814x_evm.h new file mode 100644 index 000000000..67bcc0c21 --- /dev/null +++ b/roms/u-boot/include/configs/ti814x_evm.h @@ -0,0 +1,148 @@ +/* + * ti814x_evm.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CONFIG_TI814X_EVM_H +#define __CONFIG_TI814X_EVM_H + +#include + +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +#define CONFIG_MACH_TYPE MACH_TYPE_TI8148EVM + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG /* for ramdisk support */ + +/* commands to include */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "fdtaddr=0x80F80000\0" \ + "rdaddr=0x81000000\0" \ + "bootfile=/boot/uImage\0" \ + "fdtfile=\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ + "ramrootfstype=ext2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ + "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ + "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "ramboot=echo Booting from ramdisk ...; " \ + "run ramargs; " \ + "bootm ${loadaddr}\0" \ + "fdtfile=ti814x-evm.dtb\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loaduimage; then " \ + "run mmcboot;" \ + "fi;" \ + "fi;" \ + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 + +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */ + +/** + * Physical Memory Map + */ +#define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */ + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +/** + * Platform/Board specific defs + */ +#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ + +/* CPU */ + +/* Defines for SPL */ +#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ + CONFIG_SPL_TEXT_BASE) + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80800000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* Ethernet */ +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_PHY_ET1011C_TX_CLK_FIX + +#endif /* ! __CONFIG_TI814X_EVM_H */ diff --git a/roms/u-boot/include/configs/ti816x_evm.h b/roms/u-boot/include/configs/ti816x_evm.h new file mode 100644 index 000000000..44fdc4c30 --- /dev/null +++ b/roms/u-boot/include/configs/ti816x_evm.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * ti816x_evm.h + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + */ + +#ifndef __CONFIG_TI816X_EVM_H +#define __CONFIG_TI816X_EVM_H + +#include +#include + +#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc rescan;" \ + "fatload mmc 0 ${loadaddr} uImage;" \ + "bootm ${loadaddr}" \ + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/** + * Platform/Board specific defs + */ +#define CONFIG_SYS_CLK_FREQ 27000000 +#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ + +/* allow overwriting serial config and ethaddr */ + + +/* + * GPMC NAND block. We support 1 device and the physical address to + * access CS0 at is 0x8000000. + */ +#define CONFIG_SYS_NAND_BASE 0x8000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* NAND: SPL related configs */ + +/* NAND: device related configs */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +/* NAND: driver related configs */ +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ + CONFIG_SPL_TEXT_BASE) + +#define CONFIG_NET_RETRY_COUNT 10 + +/* Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * Disable MMC DM for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_MMC +#undef CONFIG_TIMER +#endif +#endif diff --git a/roms/u-boot/include/configs/ti_am335x_common.h b/roms/u-boot/include/configs/ti_am335x_common.h new file mode 100644 index 000000000..c57b20a06 --- /dev/null +++ b/roms/u-boot/include/configs/ti_am335x_common.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * ti_am335x_common.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * For more details, please see the technical documents listed at + * http://www.ti.com/product/am3359#technicaldocuments + */ + +#ifndef __CONFIG_TI_AM335X_COMMON_H__ +#define __CONFIG_TI_AM335X_COMMON_H__ + +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ + +#include + +/* NS16550 Configuration */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_NS16550_SERIAL +#ifndef CONFIG_DM_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#endif +#endif +#define CONFIG_SYS_NS16550_CLK 48000000 + +#ifndef CONFIG_SPL_BUILD +/* Network defines. */ +#define CONFIG_NET_RETRY_COUNT 10 +#endif + +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x402F0400 and 0x4030B800 as a download area and + * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also + * supports X-MODEM loading via UART, and we leverage this and then use + * Y-MODEM to load u-boot.img, when booted over UART. + */ +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (128 << 20)) + +/* Enable the watchdog inside of SPL */ + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * When building U-Boot such that there is no previous loader + * we need to call board_early_init_f. This is taken care of in + * s_init when we have SPL used. + */ + +/* Now bring in the rest of the common code. */ +#include + +#endif /* __CONFIG_TI_AM335X_COMMON_H__ */ diff --git a/roms/u-boot/include/configs/ti_armv7_common.h b/roms/u-boot/include/configs/ti_armv7_common.h new file mode 100644 index 000000000..f13e9e526 --- /dev/null +++ b/roms/u-boot/include/configs/ti_armv7_common.h @@ -0,0 +1,212 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * ti_armv7_common.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * The various ARMv7 SoCs from TI all share a number of IP blocks when + * implementing a given feature. Rather than define these in every + * board or even SoC common file, we define a common file to be re-used + * in all cases. While technically true that some of these details are + * configurable at the board design, they are common throughout SoC + * reference platforms as well as custom designs and become de facto + * standards. + */ + +#ifndef __CONFIG_TI_ARMV7_COMMON_H__ +#define __CONFIG_TI_ARMV7_COMMON_H__ + +/* Support both device trees and ATAGs. */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Our DDR memory always starts at 0x80000000 and U-Boot shall have + * relocated itself to higher in memory by the time this value is used. + * However, set this to a 32MB offset to allow for easier Linux kernel + * booting as the default is often used as the kernel load address. + */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +/* + * We setup defaults based on constraints from the Linux kernel, which should + * also be safe elsewhere. We have the default load at 32MB into DDR (for + * the kernel), FDT above 128MB (the maximum location for the end of the + * kernel), and the ramdisk 512KB above that (allowing for hopefully never + * seen large trees). We say all of this must be within the first 256MB + * as that will normally be within the kernel lowmem and thus visible via + * bootm_size and we only run on platforms with 256MB or more of memory. + * + * As a temporary storage for DTBO blobs (which should be applied into DTB + * blob), we use the location 15.5 MB above the ramdisk. If someone wants to + * use ramdisk bigger than 15.5 MB, then DTBO can be loaded and applied to DTB + * blob before loading the ramdisk, as DTBO location is only used as a temporary + * storage, and can be re-used after 'fdt apply' command is done. + */ +#define DEFAULT_LINUX_BOOT_ENV \ + "loadaddr=0x82000000\0" \ + "kernel_addr_r=0x82000000\0" \ + "fdtaddr=0x88000000\0" \ + "dtboaddr=0x89000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "rdaddr=0x88080000\0" \ + "ramdisk_addr_r=0x88080000\0" \ + "scriptaddr=0x80000000\0" \ + "pxefile_addr_r=0x80100000\0" \ + "bootm_size=0x10000000\0" \ + "boot_fdt=try\0" + +#define DEFAULT_FIT_TI_ARGS \ + "boot_fit=0\0" \ + "addr_fit=0x90000000\0" \ + "name_fit=fitImage\0" \ + "update_to_fit=setenv loadaddr ${addr_fit}; setenv bootfile ${name_fit}\0" \ + "get_overlaystring=" \ + "for overlay in $name_overlays;" \ + "do;" \ + "setenv overlaystring ${overlaystring}'#'${overlay};" \ + "done;\0" \ + "run_fit=bootm ${addr_fit}#${fdtfile}${overlaystring}\0" \ + +/* + * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined, + * we say (for simplicity) that we have 1 bank, always, even when + * we have more. We always start at 0x80000000, and we place the + * initial stack pointer in our SRAM. Otherwise, we can define + * CONFIG_NR_DRAM_BANKS before including this file. + */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +#ifndef CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) +#endif + +/* Timer information. */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +/* If DM_I2C, enable non-DM I2C support */ +#if !CONFIG_IS_ENABLED(DM_I2C) +#define CONFIG_I2C +#define CONFIG_SYS_I2C +#endif + +/* + * The following are general good-enough settings for U-Boot. We set a + * large malloc pool as we generally have a lot of DDR, and we opt for + * function over binary size in the main portion of U-Boot as this is + * generally easily constrained later if needed. We enable the config + * options that give us information in the environment about what board + * we are on so we do not need to rely on the command prompt. We set a + * console baudrate of 115200 and use the default baud rate table. + */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +/* As stated above, the following choices are optional. */ + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 64 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * When we have SPI, NOR or NAND flash we expect to be making use of + * mtdparts, both for ease of use in U-Boot and for passing information + * on to the Linux kernel. + */ + +/* + * Our platforms make use of SPL to initalize the hardware (primarily + * memory) enough for full U-Boot to be loaded. We make use of the general + * SPL framework found under common/spl/. Given our generally common memory + * map, we set a number of related defaults and sizes here. + */ +#if !defined(CONFIG_NOR_BOOT) && \ + !(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX)) + +/* + * We also support Falcon Mode so that the Linux kernel can be booted + * directly from SPL. This is not currently available on HS devices. + */ + +/* + * Place the image at the start of the ROM defined image space (per + * CONFIG_SPL_TEXT_BASE and we limit our size to the ROM-defined + * downloaded image area minus 1KiB for scratch space. We initalize DRAM as + * soon as we can so that we can place stack, malloc and BSS there. We load + * U-Boot itself into memory at 0x80800000 for legacy reasons (to not conflict + * with older SPLs). We have our BSS be placed 2MiB after this, to allow for + * the default Linux kernel address of 0x80008000 to work with most sized + * kernels, in the Falcon Mode case. We have the SPL malloc pool at the end + * of the BSS area. We suggest that the stack be placed at 32MiB after the + * start of DRAM to allow room for all of the above (handled in Kconfig). + */ +#ifndef CONFIG_SPL_BSS_START_ADDR +#define CONFIG_SPL_BSS_START_ADDR 0x80a00000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +#endif +#ifndef CONFIG_SYS_SPL_MALLOC_START +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_8M +#endif +#ifndef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ + CONFIG_SPL_TEXT_BASE) +#endif + + +/* FAT sd card locations. */ +#ifndef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif + +#ifdef CONFIG_SPL_OS_BOOT +/* FAT */ +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" + +/* RAW SD card / eMMC */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1700 /* address 0x2E0000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x1500 /* address 0x2A0000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x200 /* 256KiB */ +#endif + +/* General parts of the framework, required. */ + +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#endif +#endif /* !CONFIG_NOR_BOOT */ + +/* Generic Environment Variables */ + +#ifdef CONFIG_CMD_NET +#define NETARGS \ + "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ + "::off\0" \ + "nfsopts=nolock\0" \ + "rootpath=/export/rootfs\0" \ + "netloadimage=tftp ${loadaddr} ${bootfile}\0" \ + "netloadfdt=tftp ${fdtaddr} ${fdtfile}\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "run netloadimage; " \ + "run netloadfdt; " \ + "run netargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" +#else +#define NETARGS "" +#endif + +#endif /* __CONFIG_TI_ARMV7_COMMON_H__ */ diff --git a/roms/u-boot/include/configs/ti_armv7_keystone2.h b/roms/u-boot/include/configs/ti_armv7_keystone2.h new file mode 100644 index 000000000..cfc2be7b9 --- /dev/null +++ b/roms/u-boot/include/configs/ti_armv7_keystone2.h @@ -0,0 +1,283 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Common configuration header file for all Keystone II EVM platforms + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + */ + +#ifndef __CONFIG_KS2_EVM_H +#define __CONFIG_KS2_EVM_H + +#define CONFIG_SOC_KEYSTONE + +/* U-Boot Build Configuration */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ + +/* SoC Configuration */ +#define CONFIG_SPL_TARGET "u-boot-spi.gph" + +/* Memory Configuration */ +#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 +#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_ISW_ENTRY_ADDR - \ + GENERATED_GBL_DATA_SIZE) + +#ifdef CONFIG_SYS_MALLOC_F_LEN +#define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN +#else +#define SPL_MALLOC_F_SIZE 0 +#endif + +/* SPL SPI Loader Configuration */ +#define CONFIG_SPL_PAD_TO 65536 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) +#define CONFIG_SPL_BSS_START_ADDR (CONFIG_ISW_ENTRY_ADDR + \ + CONFIG_SPL_MAX_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024) +#define KEYSTONE_SPL_STACK_SIZE (8 * 1024) +#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ + CONFIG_SYS_SPL_MALLOC_SIZE + \ + SPL_MALLOC_F_SIZE + \ + KEYSTONE_SPL_STACK_SIZE - 4) + +/* SRAM scratch space entries */ +#define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8 + +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR) +#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200) +#define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) + +/* UART Configuration */ +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE +#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE + +#ifndef CONFIG_SOC_K2G +#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6) +#else +#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2 +#endif + +/* SPI Configuration */ +#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) + +/* Network Configuration */ +#define CONFIG_NET_RETRY_COUNT 32 +#define CONFIG_SYS_SGMII_REFCLK_MHZ 312 +#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 +#define CONFIG_SYS_SGMII_RATESCALE 2 + +/* Keyston Navigator Configuration */ +#define CONFIG_TI_KSNAV +#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS +#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE +#define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE +#define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE +#define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE +#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE +#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE +#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE +#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE +#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE +#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE +#define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE +#define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM +#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM + +/* NETCP pktdma */ +#define CONFIG_KSNAV_PKTDMA_NETCP +#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE +#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE +#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM +#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE +#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM +#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE +#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE +#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM +#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE +#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE +#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE + +/* Keystone net */ +#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR +#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE +#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE +#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE +#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES + +#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + +/* I2C Configuration */ +#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ +#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */ +#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ + +/* EEPROM definitions */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CONFIG_ENV_EEPROM_IS_ON_I2C + +/* NAND Configuration */ +#define CONFIG_KEYSTONE_RBL_NAND +#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET +#define CONFIG_SYS_NAND_MASK_CLE 0x4000 +#define CONFIG_SYS_NAND_MASK_ALE 0x2000 +#define CONFIG_SYS_NAND_CS 2 +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST + +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE + +#define DFU_ALT_INFO_MMC \ + "dfu_alt_info_mmc=" \ + "MLO fat 0 1;" \ + "u-boot.img fat 0 1;" \ + "uEnv.txt fat 0 1\0" + +/* DFU settings */ +#define DFUARGS \ + "dfu_bufsiz=0x10000\0" \ + DFU_ALT_INFO_MMC \ + +/* U-Boot general configuration */ +#define CONFIG_TIMESTAMP + +/* EDMA3 */ +#define CONFIG_TI_EDMA3 + +#define KERNEL_MTD_PARTS \ + "mtdparts=" \ + SPI_MTD_PARTS + +#define DEFAULT_FW_INITRAMFS_BOOT_ENV \ + "name_fw_rd=k2-fw-initrd.cpio.gz\0" \ + "set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0" \ + "init_fw_rd_net=dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; " \ + "run set_rd_spec\0" \ + "init_fw_rd_nfs=nfs ${rdaddr} ${nfs_root}/boot/${name_fw_rd}; " \ + "run set_rd_spec\0" \ + "init_fw_rd_ramfs=setenv rd_spec -\0" \ + "init_fw_rd_ubi=ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; " \ + "run set_rd_spec\0" \ + +#define DEFAULT_PMMC_BOOT_ENV \ + "set_name_pmmc=setenv name_pmmc ti-sci-firmware-${soc_variant}.bin\0" \ + "dev_pmmc=0\0" \ + "get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc}\0" \ + "get_pmmc_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_pmmc}\0" \ + "get_pmmc_ramfs=run get_pmmc_net\0" \ + "get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} " \ + "${bootdir}/${name_pmmc}\0" \ + "get_pmmc_ubi=ubifsload ${loadaddr} ${bootdir}/${name_pmmc}\0" \ + "run_pmmc=rproc init; rproc list; " \ + "rproc load ${dev_pmmc} ${loadaddr} 0x${filesize}; " \ + "rproc start ${dev_pmmc}\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + DFUARGS \ + "bootdir=/boot\0" \ + "tftp_root=/\0" \ + "nfs_root=/export\0" \ + "mem_lpae=1\0" \ + "uinitrd_fixup=1\0" \ + "addr_ubi=0x82000000\0" \ + "addr_secdb_key=0xc000000\0" \ + "name_kern=zImage\0" \ + "addr_mon=0x87000000\0" \ + "addr_non_sec_mon=0x0c097fc0\0" \ + "addr_load_sec_bm=0x0c09c000\0" \ + "run_mon=mon_install ${addr_mon}\0" \ + "run_mon_hs=mon_install ${addr_non_sec_mon} " \ + "${addr_load_sec_bm}\0" \ + "run_kern=bootz ${loadaddr} ${rd_spec} ${fdtaddr}\0" \ + "init_net=run args_all args_net\0" \ + "init_nfs=setenv autoload no; dhcp; run args_all args_net\0" \ + "init_ubi=run args_all args_ubi; " \ + "ubi part ubifs; ubifsmount ubi:rootfs;\0" \ + "get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \ + "get_fdt_nfs=nfs ${fdtaddr} ${nfs_root}/boot/${name_fdt}\0" \ + "get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt}\0" \ + "get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \ + "get_kern_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_kern}\0" \ + "get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0" \ + "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ + "get_mon_nfs=nfs ${addr_mon} ${nfs_root}/boot/${name_mon}\0" \ + "get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0" \ + "get_fit_net=dhcp ${addr_fit} ${tftp_root}/${name_fit}\0" \ + "get_fit_nfs=nfs ${addr_fit} ${nfs_root}/boot/${name_fit}\0" \ + "get_fit_ubi=ubifsload ${addr_fit} ${bootdir}/${name_fit}\0" \ + "get_fit_mmc=load mmc ${bootpart} ${addr_fit} ${bootdir}/${name_fit}\0" \ + "get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \ + "get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \ + "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \ + "sf write ${loadaddr} 0 ${filesize}\0" \ + "burn_uboot_nand=nand erase 0 0x100000; " \ + "nand write ${loadaddr} 0 ${filesize}\0" \ + "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1 " \ + KERNEL_MTD_PARTS \ + "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ + "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ + "${nfs_options} ip=dhcp\0" \ + "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \ + "get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \ + "get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \ + "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ + "get_fit_ramfs=dhcp ${addr_fit} ${tftp_root}/${name_fit}\0" \ + "get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0" \ + "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \ + "get_ubi_nfs=nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi}\0" \ + "burn_ubi=nand erase.part ubifs; " \ + "nand write ${addr_ubi} ubifs ${filesize}\0" \ + "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \ + "args_ramfs=setenv bootargs ${bootargs} " \ + "rdinit=/sbin/init rw root=/dev/ram0 " \ + "initrd=0x808080000,80M\0" \ + "no_post=1\0" \ + "mtdparts=mtdparts=davinci_nand.0:" \ + "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0" + +#ifndef CONFIG_BOOTCOMMAND +#ifndef CONFIG_TI_SECURE_DEVICE +#define CONFIG_BOOTCOMMAND \ + "run init_${boot}; " \ + "run get_mon_${boot} run_mon; " \ + "run get_kern_${boot}; " \ + "run init_fw_rd_${boot}; " \ + "run get_fdt_${boot}; " \ + "run run_kern" +#else +#define CONFIG_BOOTCOMMAND \ + "run run_mon_hs; " \ + "run init_${boot}; " \ + "run get_fit_${boot}; " \ + "bootm ${addr_fit}#${name_fdt}" +#endif +#endif + +/* Now for the remaining common defines */ +#include + +/* we may include files below only after all above definitions */ +#include +#include +#ifndef CONFIG_SOC_K2G +#define CONFIG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6) +#else +#define CONFIG_SYS_HZ_CLOCK get_external_clk(sys_clk) +#endif + +#endif /* __CONFIG_KS2_EVM_H */ diff --git a/roms/u-boot/include/configs/ti_armv7_omap.h b/roms/u-boot/include/configs/ti_armv7_omap.h new file mode 100644 index 000000000..727c64831 --- /dev/null +++ b/roms/u-boot/include/configs/ti_armv7_omap.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * ti_armv7_omap.h + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * The various ARMv7 SoCs from TI all share a number of IP blocks when + * implementing a given feature. This is meant to isolate the features + * that are based on OMAP architecture. + */ +#ifndef __CONFIG_TI_ARMV7_OMAP_H__ +#define __CONFIG_TI_ARMV7_OMAP_H__ + +/* + * GPMC NAND block. We support 1 device and the physical address to + * access CS0 at is 0x8000000. + */ +#ifdef CONFIG_MTD_RAW_NAND +#ifndef CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_NAND_BASE 0x8000000 +#endif +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#endif + +/* Now for the remaining common defines */ +#include + +#endif /* __CONFIG_TI_ARMV7_OMAP_H__ */ diff --git a/roms/u-boot/include/configs/ti_omap3_common.h b/roms/u-boot/include/configs/ti_omap3_common.h new file mode 100644 index 000000000..3d7cb175f --- /dev/null +++ b/roms/u-boot/include/configs/ti_omap3_common.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * ti_omap3_common.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * For more details, please see the technical documents listed at + * http://www.ti.com/product/omap3530 + * http://www.ti.com/product/omap3630 + * http://www.ti.com/product/dm3730 + */ + +#ifndef __CONFIG_TI_OMAP3_COMMON_H__ +#define __CONFIG_TI_OMAP3_COMMON_H__ + +/* + * High Level Configuration Options + */ + +#include +#include + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +/* NS16550 Configuration */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#if !defined(CONFIG_DM_SERIAL) +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#endif /* !CONFIG_DM_SERIAL */ +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ + 115200} + +/* Select serial console configuration */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#endif + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) + +/* SPL */ +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (64 << 20)) + +#ifdef CONFIG_MTD_RAW_NAND +#define CONFIG_SYS_NAND_BASE 0x30000000 +#endif + +/* Now bring in the rest of the common code. */ +#include + +#endif /* __CONFIG_TI_OMAP3_COMMON_H__ */ diff --git a/roms/u-boot/include/configs/ti_omap4_common.h b/roms/u-boot/include/configs/ti_omap4_common.h new file mode 100644 index 000000000..1e316227a --- /dev/null +++ b/roms/u-boot/include/configs/ti_omap4_common.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments Incorporated. + * Aneesh V + * Steve Sakoman + * + * TI OMAP4 common configuration settings + */ + +#ifndef __CONFIG_TI_OMAP4_COMMON_H +#define __CONFIG_TI_OMAP4_COMMON_H + +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 1 +#define CONFIG_SYS_PL310_BASE 0x48242000 +#endif + +/* Get CPU defs */ +#include +#include + +/* Use General purpose timer 1 */ +#define CONFIG_SYS_TIMERBASE GPT2_BASE + +/* + * For the DDR timing information we can either dynamically determine + * the timings to use or use pre-determined timings (based on using the + * dynamic method. Default to the static timing infomation. + */ +#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +#endif + +#include + +/* + * Hardware drivers + */ +#define CONFIG_SYS_NS16550_CLK 48000000 +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_COM3 UART3_BASE +#endif + +/* TWL6030 */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_TWL6030_POWER 1 +#endif + +/* USB */ + +/* USB device configuration */ +#define CONFIG_USB_DEVICE 1 +#define CONFIG_USB_TTY 1 + +/* + * Environment setup + */ +#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv mmcdev " #instance"; "\ + "setenv bootpart " #instance":2 ; "\ + "run mmcboot\0" + +#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(LEGACY_MMC, legacy_mmc, 0) \ + func(MMC, mmc, 1) \ + func(LEGACY_MMC, legacy_mmc, 1) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + DEFAULT_FIT_TI_ARGS \ + "console=ttyO2,115200n8\0" \ + "fdtfile=undefined\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "usbtty=cdc_acm\0" \ + "vram=16M\0" \ + "loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \ + "uimageboot=echo Booting from mmc${mmcdev} ...; " \ + "run args_mmc; " \ + "bootm ${loadaddr}\0" \ + "findfdt="\ + "if test $board_name = sdp4430; then " \ + "setenv fdtfile omap4-sdp.dtb; fi; " \ + "if test $board_name = panda; then " \ + "setenv fdtfile omap4-panda.dtb; fi;" \ + "if test $board_name = panda-a4; then " \ + "setenv fdtfile omap4-panda-a4.dtb; fi;" \ + "if test $board_name = panda-es; then " \ + "setenv fdtfile omap4-panda-es.dtb; fi;" \ + "if test $board_name = duovero; then " \ + "setenv fdtfile omap4-duovero-parlor.dtb; fi;" \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree to use; fi; \0" \ + BOOTENV + +/* + * Defines for SPL + * It is known that this will break HS devices. Since the current size of + * SPL is overlapped with public stack and breaking non HS devices to boot. + * So moving TEXT_BASE down to non-HS limit. + */ +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (128 << 20)) + +#ifdef CONFIG_SPL_BUILD +/* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */ +#undef CONFIG_SYS_I2C +#endif + +#endif /* __CONFIG_TI_OMAP4_COMMON_H */ diff --git a/roms/u-boot/include/configs/ti_omap5_common.h b/roms/u-boot/include/configs/ti_omap5_common.h new file mode 100644 index 000000000..de0a6af2f --- /dev/null +++ b/roms/u-boot/include/configs/ti_omap5_common.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated. + * Sricharan R + * + * Derived from OMAP4 done by: + * Aneesh V + * + * TI OMAP5 AND DRA7XX common configuration settings + * + * For more details, please see the technical documents listed at + * http://www.ti.com/product/omap5432 + */ + +#ifndef __CONFIG_TI_OMAP5_COMMON_H +#define __CONFIG_TI_OMAP5_COMMON_H + +/* Use General purpose timer 1 */ +#define CONFIG_SYS_TIMERBASE GPT2_BASE + +/* + * For the DDR timing information we can either dynamically determine + * the timings to use or use pre-determined timings (based on using the + * dynamic method. Default to the static timing infomation. + */ +#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +#endif + +#define CONFIG_PALMAS_POWER + +#include +#include + +#include + +/* + * Hardware drivers + */ +#define CONFIG_SYS_NS16550_CLK 48000000 +#if !defined(CONFIG_DM_SERIAL) +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#endif + +/* + * Environment setup + */ + +#ifndef DFUARGS +#define DFUARGS +#endif + +#include +#include +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + DEFAULT_FIT_TI_ARGS \ + DEFAULT_COMMON_BOOT_TI_ARGS \ + DEFAULT_FDT_TI_ARGS \ + DFUARGS \ + NETARGS \ + NANDARGS \ + +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x40300000 and 0x4031E000 as a download area for OMAP5. + * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000. + * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and + * print some information. + */ +#ifdef CONFIG_TI_SECURE_DEVICE +/* + * For memory booting on HS parts, the first 4KB of the internal RAM is + * reserved for secure world use and the flash loader image is + * preceded by a secure certificate. The SPL will therefore run in internal + * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)). + */ +#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000 +/* If no specific start address is specified then the secure EMIF + * region will be placed at the end of the DDR space. In order to prevent + * the main u-boot relocation from clobbering that memory and causing a + * firewall violation, we tell u-boot that memory is protected RAM (PRAM) + */ +#if (CONFIG_TI_SECURE_EMIF_REGION_START == 0) +#define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10 +#endif +#else +/* + * For all booting on GP parts, the flash loader image is + * downloaded into internal RAM at address 0x40300000. + */ +#endif + +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (128 << 20)) +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_TIMER +#endif + +#endif /* __CONFIG_TI_OMAP5_COMMON_H */ diff --git a/roms/u-boot/include/configs/tinker_rk3288.h b/roms/u-boot/include/configs/tinker_rk3288.h new file mode 100644 index 000000000..269ec529a --- /dev/null +++ b/roms/u-boot/include/configs/tinker_rk3288.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#undef BOOT_TARGET_DEVICES + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dchp, na) + +#endif diff --git a/roms/u-boot/include/configs/topic_miami.h b/roms/u-boot/include/configs/topic_miami.h new file mode 100644 index 000000000..c12cd7cca --- /dev/null +++ b/roms/u-boot/include/configs/topic_miami.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 Topic Embedded Products + * + * Configuration for Zynq Evaluation and Development Board - Miami + * See zynq-common.h for Zynq common configs + */ + +#ifndef __CONFIG_TOPIC_MIAMI_H +#define __CONFIG_TOPIC_MIAMI_H + + +/* Speed up boot time by ignoring the environment which we never used */ + +#include "zynq-common.h" + +/* Fixup settings */ + +/* SPL settings */ +#undef CONFIG_SPL_ETH_SUPPORT +#undef CONFIG_SPL_MAX_FOOTPRINT +#define CONFIG_SPL_MAX_FOOTPRINT CONFIG_SYS_SPI_U_BOOT_OFFS +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +/* No falcon support */ +#undef CONFIG_SPL_OS_BOOT + +/* FPGA commands that we don't use */ + +/* Extras */ + +/* Faster flash, ours may run at 108 MHz */ +#undef CONFIG_SPI_FLASH_WINBOND + +/* Setup proper boot sequences for Miami boards */ + +#if defined(CONFIG_USB) +# define EXTRA_ENV_USB \ + "usbreset=i2c dev 1 && i2c mw 41 1 ff && i2c mw 41 3 fe && "\ + "i2c mw 41 1 fe && i2c mw 41 1 ff\0" \ + "usbboot=run usbreset && if usb start; then " \ + "echo Booting from USB... && " \ + "if load usb 0 0x1900000 ${bootscript}; then "\ + "source 0x1900000; fi; " \ + "load usb 0 ${kernel_addr} ${kernel_image} && " \ + "load usb 0 ${devicetree_addr} ${devicetree_image} && " \ + "load usb 0 ${ramdisk_load_address} ${ramdisk_image} && " \ + "bootm ${kernel_addr} ${ramdisk_load_address} "\ + "${devicetree_addr}; " \ + "fi\0" + /* Note that addresses here should match the addresses in the env */ +# define DFU_ALT_INFO \ + "dfu_alt_info=" \ + "uImage ram 0x2080000 0x500000;" \ + "devicetree.dtb ram 0x2000000 0x20000;" \ + "uramdisk.image.gz ram 0x4000000 0x10000000\0" \ + "dfu_ram=run usbreset && dfu 0 ram 0\0" \ + "thor_ram=run usbreset && thordown 0 ram 0\0" +#else +# define EXTRA_ENV_USB +#endif + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_image=uImage\0" \ + "kernel_addr=0x2080000\0" \ + "ramdisk_image=uramdisk.image.gz\0" \ + "ramdisk_load_address=0x4000000\0" \ + "devicetree_image=devicetree.dtb\0" \ + "devicetree_addr=0x2000000\0" \ + "bitstream_image=fpga.bin\0" \ + "bootscript=autorun.scr\0" \ + "loadbit_addr=0x100000\0" \ + "loadbootenv_addr=0x2000000\0" \ + "kernel_size=0x440000\0" \ + "devicetree_size=0x10000\0" \ + "boot_size=0xF00000\0" \ + "fdt_high=0x20000000\0" \ + "initrd_high=0x20000000\0" \ + "mmc_loadbit=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \ + "mmcinfo && " \ + "load mmc 0 ${loadbit_addr} ${bitstream_image} && " \ + "fpga load 0 ${loadbit_addr} ${filesize}\0" \ + "qspiboot=echo Booting from QSPI flash... && " \ + "sf probe && " \ + "sf read ${devicetree_addr} 0xA0000 ${devicetree_size} && " \ + "sf read ${kernel_addr} 0xC0000 ${kernel_size} && " \ + "bootm ${kernel_addr} - ${devicetree_addr}\0" \ + "sdboot=if mmcinfo; then " \ + "setenv bootargs console=ttyPS0,115200 " \ + "root=/dev/mmcblk0p2 rw rootfstype=ext4 " \ + "rootwait quiet ; " \ + "load mmc 0 ${kernel_addr} ${kernel_image}&& " \ + "load mmc 0 ${devicetree_addr} ${devicetree_image}&& " \ + "bootm ${kernel_addr} - ${devicetree_addr}; " \ + "fi\0" \ + EXTRA_ENV_USB \ + DFU_ALT_INFO + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "if mmcinfo; then " \ + "if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; " \ + "fi; fi; run $modeboot" +#undef CONFIG_DISPLAY_BOARDINFO + +#endif /* __CONFIG_TOPIC_MIAMI_H */ diff --git a/roms/u-boot/include/configs/total_compute.h b/roms/u-boot/include/configs/total_compute.h new file mode 100644 index 000000000..cc93f1930 --- /dev/null +++ b/roms/u-boot/include/configs/total_compute.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for Total Compute platform. Parts were derived from other ARM + * configurations. + * (C) Copyright 2020 Arm Limited + * Usama Arif + */ + +#ifndef __TOTAL_COMPUTE_H +#define __TOTAL_COMPUTE_H + +#define CONFIG_REMAKE_ELF + +/* Link Definitions */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) + +#define UART0_BASE 0x7ff80000 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) + +/* PL011 Serial Configuration */ +#define CONFIG_PL011_CLOCK 7372800 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR 0x90000000 + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 0x80000000 +/* Top 48MB reserved for secure world use */ +#define DRAM_SEC_SIZE 0x03000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_ARM_PL180_MMCI_BASE 0x001c050000 +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 +#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 12000000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x20000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_addr_r=0x80080000\0" \ + "initrd_addr_r=0x88000000\0" \ + "fdt_addr_r=0x83000000\0" +/* + * If vbmeta partition is present, boot Android with verification using AVB. + * Else if system partition is present (no vbmeta partition), boot Android + * without verification (for development purposes). + * Else boot FIT image. + */ +#define CONFIG_BOOTCOMMAND \ + "if part number mmc 0 vbmeta is_avb; then" \ + " echo MMC with vbmeta partition detected.;" \ + " echo starting Android Verified boot.;" \ + " avb init 0; " \ + " if avb verify; then " \ + " set bootargs $bootargs $avb_bootargs; " \ + " part start mmc 0 boot boot_start; " \ + " part size mmc 0 boot boot_size; " \ + " mmc read ${load_addr} ${boot_start} ${boot_size}; " \ + " bootm ${load_addr} ${load_addr} ${fdt_addr_r}; " \ + " else; " \ + " echo AVB verification failed.; " \ + " exit; " \ + " fi; " \ + "elif part number mmc 0 system is_non_avb_android; then " \ + " booti ${kernel_addr_r} ${initrd_addr_r} ${fdt_addr_r};" \ + "else;" \ + " echo Booting FIT image.;" \ + " bootm ${load_addr} ${load_addr} ${fdt_addr_r}; " \ + "fi;" + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_SYS_FLASH_BASE 0x0C000000 +/* 256 x 256KiB sectors */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ +#define FLASH_MAX_SECTOR_SIZE 0x00040000 + +#endif /* __TOTAL_COMPUTE_H */ diff --git a/roms/u-boot/include/configs/tplink_wdr4300.h b/roms/u-boot/include/configs/tplink_wdr4300.h new file mode 100644 index 000000000..f25f6dccb --- /dev/null +++ b/roms/u-boot/include/configs/tplink_wdr4300.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Marek Vasut + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 280 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN 0x40000 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + +#define CONFIG_SYS_SDRAM_BASE 0xa0000000 +#define CONFIG_SYS_LOAD_ADDR 0xa1000000 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_CLK 40000000 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {9600, 19200, 38400, 57600, 115200} + +#define CONFIG_BOOTCOMMAND \ + "dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr" + +/* + * Command + */ +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ + +/* USB, USB storage, USB ethernet */ +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_IS_TDI + +/* + * Diagnostics + */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/tqma6.h b/roms/u-boot/include/configs/tqma6.h new file mode 100644 index 000000000..b58c475c2 --- /dev/null +++ b/roms/u-boot/include/configs/tqma6.h @@ -0,0 +1,328 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013, 2014, 2017 Markus Niebel + * + * Configuration settings for the TQ Systems TQMa6 module. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +/* SPL */ +/* #if defined(CONFIG_SPL_BUILD) */ +/* common IMX6 SPL configuration */ +#include "imx6_spl.h" + +/* #endif */ + +/* place code in last 4 MiB of RAM */ + +#include "mx6_common.h" + +#if defined(CONFIG_TQMA6S) +#define PHYS_SDRAM_SIZE (512u * SZ_1M) +#elif defined(CONFIG_TQMA6DL) +#define PHYS_SDRAM_SIZE (SZ_1G) +#elif defined(CONFIG_TQMA6Q) +#define PHYS_SDRAM_SIZE (SZ_1G) +#endif + +/* SPI Flash */ + +#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K + +/* I2C Configs */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 100000 + +/* I2C EEPROM (M24C64) */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS 5 /* 32 Bytes */ +#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS 20 + +#if !defined(CONFIG_DM_PMIC) +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define TQMA6_PFUZE100_I2C_BUS 2 +#endif + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +/* USB Configs */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE ENET_BASE_ADDR + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) + +#if defined(CONFIG_TQMA6X_MMC_BOOT) + +#define TQMA6_UBOOT_OFFSET SZ_1K +#define TQMA6_UBOOT_SECTOR_START 0x2 +#define TQMA6_UBOOT_SECTOR_COUNT 0x7fe + +#define TQMA6_FDT_OFFSET (2 * SZ_1M) +#define TQMA6_FDT_SECTOR_START 0x1000 +#define TQMA6_FDT_SECTOR_COUNT 0x800 + +#define TQMA6_KERNEL_SECTOR_START 0x2000 +#define TQMA6_KERNEL_SECTOR_COUNT 0x2000 + +#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ + "uboot_start="__stringify(TQMA6_UBOOT_SECTOR_START)"\0" \ + "uboot_size="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0" \ + "fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0" \ + "fdt_size="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0" \ + "kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0" \ + "kernel_size="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "loadimage=mmc dev ${mmcdev}; " \ + "mmc read ${loadaddr} ${kernel_start} ${kernel_size};\0" \ + "loadfdt=mmc dev ${mmcdev}; " \ + "mmc read ${fdt_addr} ${fdt_start} ${fdt_size};\0" \ + "update_uboot=if tftp ${uboot}; then " \ + "if itest ${filesize} > 0; then " \ + "mmc dev ${mmcdev}; mmc rescan; " \ + "setexpr blkc ${filesize} + 0x1ff; " \ + "setexpr blkc ${blkc} / 0x200; " \ + "if itest ${blkc} <= ${uboot_size}; then " \ + "mmc write ${loadaddr} ${uboot_start} " \ + "${blkc}; " \ + "fi; " \ + "fi; fi; " \ + "setenv filesize; setenv blkc \0" \ + "update_kernel=run kernel_name; " \ + "if tftp ${kernel}; then " \ + "if itest ${filesize} > 0; then " \ + "mmc dev ${mmcdev}; mmc rescan; " \ + "setexpr blkc ${filesize} + 0x1ff; " \ + "setexpr blkc ${blkc} / 0x200; " \ + "if itest ${blkc} <= ${kernel_size}; then " \ + "mmc write ${loadaddr} " \ + "${kernel_start} ${blkc}; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "setenv filesize; setenv blkc \0" \ + "update_fdt=if tftp ${fdt_file}; then " \ + "if itest ${filesize} > 0; then " \ + "mmc dev ${mmcdev}; mmc rescan; " \ + "setexpr blkc ${filesize} + 0x1ff; " \ + "setexpr blkc ${blkc} / 0x200; " \ + "if itest ${blkc} <= ${fdt_size}; then " \ + "mmc write ${loadaddr} ${fdt_start} ${blkc}; " \ + "fi; " \ + "fi; fi; " \ + "setenv filesize; setenv blkc \0" \ + +#define CONFIG_BOOTCOMMAND \ + "run mmcboot; run netboot; run panicboot" + +#elif defined(CONFIG_TQMA6X_SPI_BOOT) + +#define TQMA6_UBOOT_OFFSET 0x400 +#define TQMA6_UBOOT_SECTOR_START 0x0 +/* max u-boot size: 512k */ +#define TQMA6_UBOOT_SECTOR_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE +#define TQMA6_UBOOT_SECTOR_COUNT 0x8 +#define TQMA6_UBOOT_SIZE (TQMA6_UBOOT_SECTOR_SIZE * \ + TQMA6_UBOOT_SECTOR_COUNT) + +#define TQMA6_FDT_OFFSET (CONFIG_ENV_OFFSET_REDUND + \ + CONFIG_ENV_SECT_SIZE) +#define TQMA6_FDT_SECT_SIZE (TQMA6_SPI_FLASH_SECTOR_SIZE) + +#define TQMA6_FDT_SECTOR_START 0x0a /* 8 Sector u-boot, 2 Sector env */ +#define TQMA6_FDT_SECTOR_COUNT 0x01 + +#define TQMA6_KERNEL_SECTOR_START 0x10 +#define TQMA6_KERNEL_SECTOR_COUNT 0x60 + +#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ + "mmcblkdev=0\0" \ + "uboot_offset="__stringify(TQMA6_UBOOT_OFFSET)"\0" \ + "uboot_sectors="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0" \ + "fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0" \ + "fdt_sectors="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0" \ + "kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0" \ + "kernel_sectors="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0" \ + "update_uboot=if tftp ${uboot}; then " \ + "if itest ${filesize} > 0; then " \ + "setexpr blkc ${filesize} + " \ + __stringify(TQMA6_UBOOT_OFFSET) "; " \ + "setexpr size ${uboot_sectors} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "if itest ${blkc} <= ${size}; then " \ + "sf probe; " \ + "sf erase 0 ${size}; " \ + "sf write ${loadaddr} ${uboot_offset} " \ + "${filesize}; " \ + "fi; " \ + "fi; fi; " \ + "setenv filesize 0; setenv blkc; setenv size \0" \ + "update_kernel=run kernel_name; if tftp ${kernel}; then " \ + "if itest ${filesize} > 0; then " \ + "setexpr size ${kernel_sectors} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "setexpr offset ${kernel_start} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "if itest ${filesize} <= ${size}; then " \ + "sf probe; " \ + "sf erase ${offset} ${size}; " \ + "sf write ${loadaddr} ${offset} " \ + "${filesize}; " \ + "fi; " \ + "fi; fi; " \ + "setenv filesize 0; setenv size ; setenv offset\0" \ + "update_fdt=if tftp ${fdt_file}; then " \ + "if itest ${filesize} > 0; then " \ + "setexpr size ${fdt_sectors} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "setexpr offset ${fdt_start} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "if itest ${filesize} <= ${size}; then " \ + "sf probe; " \ + "sf erase ${offset} ${size}; " \ + "sf write ${loadaddr} ${offset} " \ + "${filesize}; " \ + "fi; " \ + "fi; fi; " \ + "setenv filesize 0; setenv size ; setenv offset\0" \ + "loadimage=sf probe; " \ + "setexpr size ${kernel_sectors} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "setexpr offset ${kernel_start} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "sf read ${loadaddr} ${offset} ${size}; " \ + "setenv size ; setenv offset\0" \ + "loadfdt=sf probe; " \ + "setexpr size ${fdt_sectors} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "setexpr offset ${fdt_start} * " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ + "sf read ${fdt_addr} ${offset} ${size}; " \ + "setenv size ; setenv offset\0" \ + +#define CONFIG_BOOTCOMMAND \ + "sf probe; run mmcboot; run netboot; run panicboot" \ + +#else + +#error "need to define boot source" + +#endif + +/* 128 MiB offset as in ARM related docu for linux suggested */ +#define TQMA6_FDT_ADDRESS 0x18000000 + +/* set to a resonable value, changeable by user */ +#define TQMA6_CMA_SIZE 160M + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "board=tqma6\0" \ + "uimage=uImage\0" \ + "zimage=zImage\0" \ + "boot_type=bootz\0" \ + "kernel_name=if test \"${boot_type}\" != bootz; then " \ + "setenv kernel ${uimage}; " \ + "else setenv kernel ${zimage}; fi\0" \ + "uboot=u-boot.imx\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr="__stringify(TQMA6_FDT_ADDRESS)"\0" \ + "console=" CONSOLE_DEV "\0" \ + "cma_size="__stringify(TQMA6_CMA_SIZE)"\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "rootfsmode=ro\0" \ + "addcma=setenv bootargs ${bootargs} cma=${cma_size}\0" \ + "addtty=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ + "addfb=setenv bootargs ${bootargs} " \ + "imx-fbdev.legacyfb_depth=32 consoleblank=0\0" \ + "mmcpart=2\0" \ + "mmcblkdev=0\0" \ + "mmcargs=run addmmc addtty addfb addcma\0" \ + "addmmc=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk${mmcblkdev}p${mmcpart} ${rootfsmode} " \ + "rootwait\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "setenv bootargs; " \ + "run mmcargs; " \ + "run loadimage; " \ + "if run loadfdt; then " \ + "echo boot device tree kernel ...; " \ + "${boot_type} ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "${boot_type}; " \ + "fi;\0" \ + "setenv bootargs \0" \ + "netdev=eth0\0" \ + "rootpath=/srv/nfs/tqma6\0" \ + "ipmode=static\0" \ + "netargs=run addnfs addip addtty addfb addcma\0" \ + "addnfs=setenv bootargs ${bootargs} " \ + "root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},v3,tcp;\0" \ + "addip_static=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ + "${hostname}:${netdev}:off\0" \ + "addip_dynamic=setenv bootargs ${bootargs} ip=dhcp\0" \ + "addip=if test \"${ipmode}\" != static; then " \ + "run addip_dynamic; else run addip_static; fi\0" \ + "set_getcmd=if test \"${ipmode}\" != static; then " \ + "setenv getcmd dhcp; setenv autoload yes; " \ + "else setenv getcmd tftp; setenv autoload no; fi\0" \ + "netboot=echo Booting from net ...; " \ + "run kernel_name; " \ + "run set_getcmd; " \ + "setenv bootargs; " \ + "run netargs; " \ + "if ${getcmd} ${kernel}; then " \ + "if ${getcmd} ${fdt_addr} ${fdt_file}; then " \ + "${boot_type} ${loadaddr} - ${fdt_addr}; " \ + "fi; " \ + "fi; " \ + "echo ... failed\0" \ + "panicboot=echo No boot device !!! reset\0" \ + TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* + * All the defines above are for the TQMa6 SoM + * + * Now include the baseboard specific configuration + */ +#ifdef CONFIG_MBA6 +#include "tqma6_mba6.h" +#elif CONFIG_WRU4 +#include "tqma6_wru4.h" +#else +#error "No baseboard for the TQMa6 defined!" +#endif + +/* Support at least the sensor on TQMa6 SOM */ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/tqma6_mba6.h b/roms/u-boot/include/configs/tqma6_mba6.h new file mode 100644 index 000000000..bee6d2f33 --- /dev/null +++ b/roms/u-boot/include/configs/tqma6_mba6.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 - 2017 Markus Niebel + * + * Configuration settings for the TQ Systems TQMa6 module on + * MBa6 starter kit + */ + +#ifndef __CONFIG_TQMA6_MBA6_H +#define __CONFIG_TQMA6_MBA6_H + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC_PHYADDR 0x03 + +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONSOLE_DEV "ttymxc1" + +#endif /* __CONFIG_TQMA6_MBA6_H */ diff --git a/roms/u-boot/include/configs/tqma6_wru4.h b/roms/u-boot/include/configs/tqma6_wru4.h new file mode 100644 index 000000000..4c4a1a0ee --- /dev/null +++ b/roms/u-boot/include/configs/tqma6_wru4.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Stefan Roese + */ + +#ifndef __CONFIG_TQMA6_WRU4_H +#define __CONFIG_TQMA6_WRU4_H + +/* Ethernet */ +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0x01 + +/* UART */ +#define CONFIG_MXC_UART_BASE UART4_BASE +#define CONSOLE_DEV "ttymxc3" + +/* Watchdog */ + +/* Config on-board RTC */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_RTC_BUS_NUM 2 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +/* Turn off RTC square-wave output to save battery */ +#define CONFIG_RTC_DS1337_NOOSC + +/* LED */ + +/* Bootcounter */ +#define CONFIG_SYS_BOOTCOUNT_BE + +/* I2C */ +#define CONFIG_SYS_I2C + +#endif /* __CONFIG_TQMA6_WRU4_H */ diff --git a/roms/u-boot/include/configs/trats.h b/roms/u-boot/include/configs/trats.h new file mode 100644 index 000000000..a44792d85 --- /dev/null +++ b/roms/u-boot/include/configs/trats.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 Samsung Electronics + * Heungjun Kim + * + * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board. + */ + +#ifndef __CONFIG_TRATS_H +#define __CONFIG_TRATS_H + +#include + +#define CONFIG_TRATS + +#define CONFIG_TIZEN /* TIZEN lib */ + +#define CONFIG_SYS_L2CACHE_OFF +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x10502000 +#endif + +/* TRATS has 4 banks of DRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ + +/* memtest works on */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) + +#define CONFIG_MACH_TYPE MACH_TYPE_TRATS + +#define CONFIG_BOOTCOMMAND "run autoboot" + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ + - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +#define CONFIG_BOOTBLOCK "10" +#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" + +/* Tizen - partitions definitions */ +#define PARTS_CSA "csa-mmc" +#define PARTS_BOOT "boot" +#define PARTS_QBOOT "qboot" +#define PARTS_CSC "csc" +#define PARTS_ROOT "platform" +#define PARTS_DATA "data" +#define PARTS_UMS "ums" + +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ + "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ + "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ + "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ + "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ + "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ + "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ + +#define CONFIG_DFU_ALT \ + "u-boot raw 0x80 0x400;" \ + "/uImage ext4 0 2;" \ + "/modem.bin ext4 0 2;" \ + "/exynos4210-trats.dtb ext4 0 2;" \ + ""PARTS_CSA" part 0 1;" \ + ""PARTS_BOOT" part 0 2;" \ + ""PARTS_QBOOT" part 0 3;" \ + ""PARTS_CSC" part 0 4;" \ + ""PARTS_ROOT" part 0 5;" \ + ""PARTS_DATA" part 0 6;" \ + ""PARTS_UMS" part 0 7;" \ + "params.bin raw 0x38 0x8;" \ + "/Image.itb ext4 0 2\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootk=" \ + "run loaduimage;" \ + "if run loaddtb; then " \ + "bootm 0x40007FC0 - ${fdtaddr};" \ + "fi;" \ + "bootm 0x40007FC0;\0" \ + "updatebackup=" \ + "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ + "mmc dev 0 0\0" \ + "updatebootb=" \ + "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ + "lpj=lpj=3981312\0" \ + "nfsboot=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${nfsroot},nolock,tcp " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ + "; run bootk\0" \ + "ramfsboot=" \ + "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \ + "${console} ${meminfo} " \ + "initrd=0x43000000,8M ramdisk=8192\0" \ + "mmcboot=" \ + "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ + "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ + "run bootk\0" \ + "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \ + "boottrace=setenv opts initcall_debug; run bootcmd\0" \ + "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ + "verify=n\0" \ + "rootfstype=ext4\0" \ + "console=console=ttySAC2,115200n8\0" \ + "meminfo=crashkernel=32M@0x50000000\0" \ + "nfsroot=/nfsroot/arm\0" \ + "bootblock=" CONFIG_BOOTBLOCK "\0" \ + "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ + "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ + "${fdtfile}\0" \ + "mmcdev=0\0" \ + "mmcbootpart=2\0" \ + "mmcrootpart=5\0" \ + "opts=always_resume=1\0" \ + "partitions=" PARTS_DEFAULT \ + "dfu_alt_info=" CONFIG_DFU_ALT \ + "spladdr=0x40000100\0" \ + "splsize=0x200\0" \ + "splfile=falcon.bin\0" \ + "spl_export=" \ + "setexpr spl_imgsize ${splsize} + 8 ;" \ + "setenv spl_imgsize 0x${spl_imgsize};" \ + "setexpr spl_imgaddr ${spladdr} - 8 ;" \ + "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ + "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ + "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ + "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ + "spl export atags 0x40007FC0;" \ + "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ + "mw.l ${spl_addr_tmp} ${splsize};" \ + "ext4write mmc ${mmcdev}:${mmcbootpart}" \ + " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ + "setenv spl_imgsize;" \ + "setenv spl_imgaddr;" \ + "setenv spl_addr_tmp;\0" \ + CONFIG_EXTRA_ENV_ITB \ + "fdtaddr=40800000\0" \ + +/* Falcon mode definitions */ +#define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100 + +/* GPT */ + +/* Security subsystem - enable hw_rand() */ +#define CONFIG_EXYNOS_ACE_SHA + +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +/* Download menu - Samsung common */ +#define CONFIG_LCD_MENU + +/* Download menu - definitions for check keys */ +#ifndef __ASSEMBLY__ + +#define KEY_PWR_PMIC_NAME "MAX8997_PMIC" +#define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1 +#define KEY_PWR_STATUS_MASK (1 << 0) +#define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1 +#define KEY_PWR_INTERRUPT_MASK (1 << 0) + +#define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 +#define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 +#endif /* __ASSEMBLY__ */ + +/* LCD console */ +#define LCD_BPP LCD_COLOR16 + +/* LCD */ +#define CONFIG_FB_ADDR 0x52504000 +#define CONFIG_EXYNOS_MIPI_DSIM +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/trats2.h b/roms/u-boot/include/configs/trats2.h new file mode 100644 index 000000000..4b1eff08f --- /dev/null +++ b/roms/u-boot/include/configs/trats2.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Samsung Electronics + * Sanghee Kim + * Piotr Wilczek + * + * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board. + */ + +#ifndef __CONFIG_TRATS2_H +#define __CONFIG_TRATS2_H + +#include + +#define CONFIG_TIZEN /* TIZEN lib */ + +#define CONFIG_SYS_L2CACHE_OFF +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x10502000 +#endif + +/* TRATS2 has 4 banks of DRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ +/* memtest works on */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + +#define CONFIG_BOOTCOMMAND "run autoboot" + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ + - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +/* Tizen - partitions definitions */ +#define PARTS_CSA "csa-mmc" +#define PARTS_BOOT "boot" +#define PARTS_QBOOT "qboot" +#define PARTS_CSC "csc" +#define PARTS_ROOT "platform" +#define PARTS_DATA "data" +#define PARTS_UMS "ums" + +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ + "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ + "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ + "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ + "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ + "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ + "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ + +#define CONFIG_DFU_ALT \ + "u-boot raw 0x80 0x800;" \ + "/uImage ext4 0 2;" \ + "/modem.bin ext4 0 2;" \ + "/exynos4412-trats2.dtb ext4 0 2;" \ + ""PARTS_CSA" part 0 1;" \ + ""PARTS_BOOT" part 0 2;" \ + ""PARTS_QBOOT" part 0 3;" \ + ""PARTS_CSC" part 0 4;" \ + ""PARTS_ROOT" part 0 5;" \ + ""PARTS_DATA" part 0 6;" \ + ""PARTS_UMS" part 0 7;" \ + "params.bin raw 0x38 0x8;" \ + "/Image.itb ext4 0 2\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootk=" \ + "run loaduimage;" \ + "if run loaddtb; then " \ + "bootm 0x40007FC0 - ${fdtaddr};" \ + "fi;" \ + "bootm 0x40007FC0;\0" \ + "updatebackup=" \ + "mmc dev 0 2; mmc write 0x51000000 0 0x800;" \ + " mmc dev 0 0\0" \ + "updatebootb=" \ + "mmc read 0x51000000 0x80 0x800; run updatebackup\0" \ + "mmcboot=" \ + "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ + "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ + "run bootk\0" \ + "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ + "boottrace=setenv opts initcall_debug; run bootcmd\0" \ + "verify=n\0" \ + "rootfstype=ext4\0" \ + "console=console=ttySAC2,115200n8\0" \ + "kernelname=uImage\0" \ + "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \ + "${kernelname}\0" \ + "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ + "${fdtfile}\0" \ + "mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \ + "mmcbootpart=2\0" \ + "mmcrootpart=5\0" \ + "opts=always_resume=1\0" \ + "partitions=" PARTS_DEFAULT \ + "dfu_alt_info=" CONFIG_DFU_ALT \ + "uartpath=ap\0" \ + "usbpath=ap\0" \ + "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \ + "consoleoff=set console console=ram; save; reset\0" \ + "spladdr=0x40000100\0" \ + "splsize=0x200\0" \ + "splfile=falcon.bin\0" \ + "spl_export=" \ + "setexpr spl_imgsize ${splsize} + 8 ;" \ + "setenv spl_imgsize 0x${spl_imgsize};" \ + "setexpr spl_imgaddr ${spladdr} - 8 ;" \ + "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ + "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ + "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ + "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ + "spl export atags 0x40007FC0;" \ + "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ + "mw.l ${spl_addr_tmp} ${splsize};" \ + "ext4write mmc ${mmcdev}:${mmcbootpart}" \ + " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ + "setenv spl_imgsize;" \ + "setenv spl_imgaddr;" \ + "setenv spl_addr_tmp;\0" \ + CONFIG_EXTRA_ENV_ITB \ + "fdtaddr=40800000\0" \ + +/* GPT */ + +/* Security subsystem - enable hw_rand() */ +#define CONFIG_EXYNOS_ACE_SHA + +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +/* Download menu - Samsung common */ +#define CONFIG_LCD_MENU + +/* Download menu - definitions for check keys */ +#ifndef __ASSEMBLY__ + +#define KEY_PWR_PMIC_NAME "MAX77686_PMIC" +#define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1 +#define KEY_PWR_STATUS_MASK (1 << 0) +#define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1 +#define KEY_PWR_INTERRUPT_MASK (1 << 1) + +#define KEY_VOL_UP_GPIO EXYNOS4X12_GPIO_X22 +#define KEY_VOL_DOWN_GPIO EXYNOS4X12_GPIO_X33 +#endif /* __ASSEMBLY__ */ + +/* LCD console */ +#define LCD_BPP LCD_COLOR16 + +/* LCD */ +#define CONFIG_FB_ADDR 0x52504000 +#define CONFIG_EXYNOS_MIPI_DSIM +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/trimslice.h b/roms/u-boot/include/configs/trimslice.h new file mode 100644 index 000000000..b914e444b --- /dev/null +++ b/roms/u-boot/include/configs/trimslice.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include "tegra20-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "Compulab Trimslice" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_TEGRA_UARTA_GPU +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE + +/* SPI */ + +/* Environment in SPI */ +/* 1MiB flash, environment located as high as possible */ + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/tuge1.h b/roms/u-boot/include/configs/tuge1.h new file mode 100644 index 000000000..d43ccbe8d --- /dev/null +++ b/roms/u-boot/include/configs/tuge1.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2013 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_HOSTNAME "tuge1" + +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/turris_mox.h b/roms/u-boot/include/configs/turris_mox.h new file mode 100644 index 000000000..9c021a1ef --- /dev/null +++ b/roms/u-boot/include/configs/turris_mox.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Marek Behun + * + * Based on mvebu_armada-37xx.h by Stefan Roese + */ + +#ifndef _CONFIG_TURRIS_MOX_H +#define _CONFIG_TURRIS_MOX_H + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) + +#define CONFIG_LAST_STAGE_INIT + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* additions for new ARM relocation support */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +/* auto boot */ + +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200, 230400, 460800, 921600 } + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ + +/* + * Other required minimal configurations + */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ + +/* End of 16M scrubbed by training in bootrom */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) + +/* + * I2C + */ +#define CONFIG_I2C_MV +#define CONFIG_SYS_I2C_SLAVE 0x0 + +/* Environment in SPI NOR flash */ + +/* + * Ethernet Driver configuration + */ +#define CONFIG_ARP_TIMEOUT 200 +#define CONFIG_NET_RETRY_COUNT 50 + +#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3) + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#define TURRIS_MOX_BOOTCMD_RESCUE \ + "setenv bootargs \"console=ttyMV0,115200 " \ + "earlycon=ar3700_uart,0xd0012000\" && " \ + "sf probe && " \ + "sf read 0x5000000 0x190000 && " \ + "lzmadec 0x5000000 0x5800000 && " \ + "bootm 0x5800000" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "scriptaddr=0x4d00000\0" \ + "pxefile_addr_r=0x4e00000\0" \ + "fdt_addr_r=0x4f00000\0" \ + "kernel_addr_r=0x5000000\0" \ + "ramdisk_addr_r=0x8000000\0" \ + "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "bootcmd_rescue=" TURRIS_MOX_BOOTCMD_RESCUE "\0" \ + BOOTENV + +#endif /* _CONFIG_TURRIS_MOX_H */ diff --git a/roms/u-boot/include/configs/turris_omnia.h b/roms/u-boot/include/configs/turris_omnia.h new file mode 100644 index 000000000..7da18f97d --- /dev/null +++ b/roms/u-boot/include/configs/turris_omnia.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Marek Behun + * Copyright (C) 2016 Tomas Hlavacek + */ + +#ifndef _CONFIG_TURRIS_OMNIA_H +#define _CONFIG_TURRIS_OMNIA_H + +/* + * High Level Configuration Options (easy to change) + */ + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +/* Environment in SPI NOR flash */ + +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* Keep device tree and initrd in lower memory so the kernel can access them */ +#define RELOCATION_LIMITS_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +/* Defines for SPL */ +#define CONFIG_SPL_SIZE (140 << 10) +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT + +#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI +/* SPL related SPI defines */ +# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS +#endif + +#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC +/* SPL related MMC defines */ +# define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) +# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS +# ifdef CONFIG_SPL_BUILD +# define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ +# endif +#endif + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Include the common distro boot environment */ +#ifndef CONFIG_SPL_BUILD + +#ifdef CONFIG_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#ifdef CONFIG_USB_STORAGE +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + +#ifdef CONFIG_SCSI +#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) +#else +#define BOOT_TARGET_DEVICES_SCSI(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_SCSI(func) \ + BOOT_TARGET_DEVICES_USB(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#define KERNEL_ADDR_R __stringify(0x1000000) +#define FDT_ADDR_R __stringify(0x2000000) +#define RAMDISK_ADDR_R __stringify(0x2200000) +#define SCRIPT_ADDR_R __stringify(0x1800000) +#define PXEFILE_ADDR_R __stringify(0x1900000) + +#define LOAD_ADDRESS_ENV_SETTINGS \ + "kernel_addr_r=" KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" FDT_ADDR_R "\0" \ + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ + "scriptaddr=" SCRIPT_ADDR_R "\0" \ + "pxefile_addr_r=" PXEFILE_ADDR_R "\0" + +#include + +/* + * The factory reset bootcommand on Omnia first sets all the front LEDs to green + * and then tries to load the rescue image from SPI flash memory and boot it + */ +#define TURRIS_OMNIA_BOOTCMD_RESCUE \ + "i2c dev 2; " \ + "i2c mw 0x2a.1 0x3 0x1c 1; " \ + "i2c mw 0x2a.1 0x4 0x1c 1; " \ + "mw.l 0x01000000 0x00ff000c; " \ + "i2c write 0x01000000 0x2a.1 0x5 4 -s; " \ + "setenv bootargs \"earlyprintk console=ttyS0,115200" \ + " omniarescue=$omnia_reset rescue_mode=$omnia_reset\"; " \ + "sf probe; " \ + "sf read 0x1000000 0x100000 0x700000; " \ + "lzmadec 0x1000000 0x1700000; " \ + "if gpio input gpio@71_4; then " \ + "bootm 0x1700000#sfp; " \ + "else " \ + "bootm 0x1700000; " \ + "fi; " \ + "bootz 0x1000000" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + RELOCATION_LIMITS_ENV_SETTINGS \ + LOAD_ADDRESS_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "console=ttyS0,115200\0" \ + "ethact=ethernet@34000\0" \ + "bootcmd_rescue=" TURRIS_OMNIA_BOOTCMD_RESCUE "\0" \ + BOOTENV + +#endif /* CONFIG_SPL_BUILD */ + +#endif /* _CONFIG_TURRIS_OMNIA_H */ diff --git a/roms/u-boot/include/configs/tuxx1.h b/roms/u-boot/include/configs/tuxx1.h new file mode 100644 index 000000000..f5a9f1284 --- /dev/null +++ b/roms/u-boot/include/configs/tuxx1.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2013 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_HOSTNAME "tuxx1" + +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h" + +#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ + 0x0000c000 | \ + MxMR_WLFx_2X) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/udoo.h b/roms/u-boot/include/configs/udoo.h new file mode 100644 index 000000000..298369373 --- /dev/null +++ b/roms/u-boot/include/configs/udoo.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for Udoo board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + +#include "imx6_spl.h" + +/* Provide the MACH_TYPE value that the vendor kernel requires. */ +#define CONFIG_MACH_TYPE 4800 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART2_BASE + +/* SATA Configs */ +#define CONFIG_LBA48 + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc1,115200\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdtfile=undefined\0" \ + "fdt_addr=0x18000000\0" \ + "fdt_addr_r=0x18000000\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcrootfstype=ext4\0" \ + "findfdt="\ + "if test ${board_rev} = MX6Q; then " \ + "setenv fdtfile imx6q-udoo.dtb; fi; " \ + "if test ${board_rev} = MX6DL; then " \ + "setenv fdtfile imx6dl-udoo.dtb; fi; " \ + "if test ${fdtfile} = undefined; then " \ + "echo WARNING: Could not determine dtb to use; fi\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(SATA, sata, 0) \ + func(DHCP, dhcp, na) + +#include +#include + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ + +#endif /* __CONFIG_H * */ diff --git a/roms/u-boot/include/configs/udoo_neo.h b/roms/u-boot/include/configs/udoo_neo.h new file mode 100644 index 000000000..b6f75c926 --- /dev/null +++ b/roms/u-boot/include/configs/udoo_neo.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * Copyright Jasbir Matharu + * Copyright 2015 UDOO Team + * + * Configuration settings for the UDOO NEO board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + +#include "imx6_spl.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* Command definition */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* Linux only */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdtfile=undefined\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_addr_r=0x83000000\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcrootfstype=ext4\0" \ + "findfdt="\ + "if test $board_name = BASIC; then " \ + "setenv fdtfile imx6sx-udoo-neo-basic.dtb; fi; " \ + "if test $board_name = BASICKS; then " \ + "setenv fdtfile imx6sx-udoo-neo-basic.dtb; fi; " \ + "if test $board_name = FULL; then " \ + "setenv fdtfile imx6sx-udoo-neo-full.dtb; fi; " \ + "if test $board_name = EXTENDED; then " \ + "setenv fdtfile imx6sx-udoo-neo-extended.dtb; fi; " \ + "if test $fdtfile = UNDEFINED; then " \ + "echo WARNING: Could not determine dtb to use; fi\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x84000000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) + +#include + +/* Miscellaneous configurable options */ + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* I2C configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#define PFUZE3000_I2C_BUS 0 + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/ulcb.h b/roms/u-boot/include/configs/ulcb.h new file mode 100644 index 000000000..1ce844f49 --- /dev/null +++ b/roms/u-boot/include/configs/ulcb.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/ulcb.h + * This file is ULCB board configuration. + * + * Copyright (C) 2017 Renesas Electronics Corporation + */ + +#ifndef __ULCB_H +#define __ULCB_H + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_BITBANGMII_MULTI + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +/* Environment in eMMC, at the end of 2nd "boot sector" */ + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +#endif /* __ULCB_H */ diff --git a/roms/u-boot/include/configs/uniphier.h b/roms/u-boot/include/configs/uniphier.h new file mode 100644 index 000000000..bad4e4137 --- /dev/null +++ b/roms/u-boot/include/configs/uniphier.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012-2015 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + */ + +/* U-Boot - Common settings for UniPhier Family */ + +#ifndef __CONFIG_UNIPHIER_H__ +#define __CONFIG_UNIPHIER_H__ + +#ifndef CONFIG_SPL_BUILD +#include + +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) +#else +#define BOOT_TARGET_DEVICE_MMC(func) +#endif + +#ifdef CONFIG_CMD_UBIFS +#define BOOT_TARGET_DEVICE_UBIFS(func) func(UBIFS, ubifs, 0) +#else +#define BOOT_TARGET_DEVICE_UBIFS(func) +#endif + +#ifdef CONFIG_CMD_USB +#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICE_USB(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICE_MMC(func) \ + BOOT_TARGET_DEVICE_UBIFS(func) \ + BOOT_TARGET_DEVICE_USB(func) +#else +#define BOOTENV +#endif + +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#define CONFIG_TIMESTAMP + +#define CONFIG_SYS_MONITOR_BASE 0 +#define CONFIG_SYS_MONITOR_LEN 0x00200000 /* 2MB */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#if !defined(CONFIG_ARM64) +/* Time clock 1MHz */ +#define CONFIG_SYS_TIMER_RATE 1000000 +#endif + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_REGS_BASE 0x68100000 +#define CONFIG_SYS_NAND_DATA_BASE 0x68000000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + +/* + * Network Configuration + */ +#define CONFIG_SERVERIP 192.168.11.1 +#define CONFIG_IPADDR 192.168.11.10 +#define CONFIG_GATEWAYIP 192.168.11.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_SYS_LOAD_ADDR 0x85000000 +#define CONFIG_SYS_BOOTM_LEN (32 << 20) + +#if defined(CONFIG_ARM64) +/* ARM Trusted Firmware */ +#define BOOT_IMAGES \ + "second_image=unph_bl.bin\0" \ + "third_image=fip.bin\0" +#else +#define BOOT_IMAGES \ + "second_image=u-boot-spl.bin\0" \ + "third_image=u-boot.bin\0" +#endif + +#define CONFIG_ROOTPATH "/nfs/root/path" +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs $bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ + "run __nfsboot" + +#ifdef CONFIG_FIT +#define CONFIG_BOOTFILE "fitImage" +#define KERNEL_ADDR_R_OFFSET "0x05100000" +#define LINUXBOOT_ENV_SETTINGS \ + "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ + "bootm $kernel_addr_r\0" \ + "__nfsboot=run tftpboot\0" +#else +#ifdef CONFIG_ARM64 +#define CONFIG_BOOTFILE "Image" +#define LINUXBOOT_CMD "booti" +#define KERNEL_ADDR_R_OFFSET "0x02080000" +#else +#define CONFIG_BOOTFILE "zImage" +#define LINUXBOOT_CMD "bootz" +#define KERNEL_ADDR_R_OFFSET "0x00208000" +#endif +#define LINUXBOOT_ENV_SETTINGS \ + "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \ + LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ + "tftpboot=tftpboot $kernel_addr_r $bootfile && " \ + "tftpboot $fdt_addr_r $fdtfile &&" \ + "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ + "setenv ramdisk_addr_r $ramdisk_addr_r:$filesize &&" \ + "run boot_common\0" \ + "__nfsboot=tftpboot $kernel_addr_load $bootfile && " \ + "tftpboot $fdt_addr_r $fdtfile &&" \ + "setenv ramdisk_addr_r - &&" \ + "run boot_common\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr_r_offset=0x05100000\0" \ + "kernel_addr_r_offset=" KERNEL_ADDR_R_OFFSET "\0" \ + "ramdisk_addr_r_offset=0x06000000\0" \ + "ramdisk_file=rootfs.cpio.gz\0" \ + "netdev=eth0\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "loadaddr_offset=0x05000000\0" \ + "script=boot.scr\0" \ + "scriptaddr=0x85000000\0" \ + "nor_base=0x42000000\0" \ + "emmcboot=mmcsetn && run bootcmd_mmc${mmc_first_dev}\0" \ + "nandboot=run bootcmd_ubifs0\0" \ + "norboot=run tftpboot\0" \ + "sdboot=sdsetn && run bootcmd_mmc${sd_first_dev}\0" \ + "usbboot=run bootcmd_usb0\0" \ + "emmcscript=setenv devtype mmc && " \ + "mmcsetn && " \ + "setenv devnum ${mmc_first_dev} && " \ + "run loadscript_fat\0" \ + "nandscript=echo Running ${script} from ubi ... && " \ + "ubi part UBI && " \ + "ubifsmount ubi0:boot && " \ + "ubifsload ${loadaddr} ${script} && " \ + "source $loadaddr\0" \ + "sdscript=setenv devtype mmc && " \ + "sdsetn && " \ + "setenv devnum ${sd_first_dev} && " \ + "run loadscript_fat\0" \ + "norscript=echo Running ${script} from tftp ... && " \ + "tftpboot ${script} &&" \ + "source $loadaddr\0" \ + "usbscript=usb start && " \ + "setenv devtype usb && " \ + "setenv devnum 0 && " \ + "run loadscript_fat\0" \ + "loadscript_fat=echo Running ${script} from ${devtype}${devnum} ... && " \ + "load ${devtype} ${devnum}:1 ${loadaddr} ${script} && " \ + "source $loadaddr\0" \ + "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ + "tftpboot $tmp_addr $second_image && " \ + "setexpr tmp_addr $nor_base + 0x70000 && " \ + "tftpboot $tmp_addr $third_image\0" \ + "emmcupdate=mmcsetn &&" \ + "mmc dev $mmc_first_dev &&" \ + "mmc partconf $mmc_first_dev 0 1 1 &&" \ + "tftpboot $second_image && " \ + "mmc write $loadaddr 0 100 && " \ + "tftpboot $third_image && " \ + "mmc write $loadaddr 100 f00\0" \ + "nandupdate=nand erase 0 0x00100000 &&" \ + "tftpboot $second_image && " \ + "nand write $loadaddr 0 0x00020000 && " \ + "tftpboot $third_image && " \ + "nand write $loadaddr 0x00020000 0x001e0000\0" \ + "sdupdate=sdsetn &&" \ + "mmc dev $sd_first_dev &&" \ + "tftpboot $second_image && " \ + "mmc write $loadaddr 0 100 && " \ + "tftpboot $third_image && " \ + "mmc write $loadaddr 100 f00\0" \ + "usbupdate=usb start &&" \ + "tftpboot $second_image && " \ + "usb write $loadaddr 0 100 && " \ + "tftpboot $third_image && " \ + "usb write $loadaddr 100 f00\0" \ + BOOT_IMAGES \ + LINUXBOOT_ENV_SETTINGS \ + BOOTENV + +#define CONFIG_SYS_BOOTMAPSZ 0x20000000 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) + +/* only for SPL */ +#define CONFIG_SPL_STACK (0x00100000) + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 + +/* subtract sizeof(struct image_header) */ +#define CONFIG_SYS_UBOOT_BASE (0x130000 - 0x40) + +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_MAX_FOOTPRINT 0x10000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 + +#define CONFIG_SPL_PAD_TO 0x20000 + +#endif /* __CONFIG_UNIPHIER_H__ */ diff --git a/roms/u-boot/include/configs/usb_a9263.h b/roms/u-boot/include/configs/usb_a9263.h new file mode 100644 index 000000000..73bf2d19d --- /dev/null +++ b/roms/u-boot/include/configs/usb_a9263.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2013 + * Stelian Pop + * Lead Tech Design + * Thomas Petazzoni, Free Electrons, + * Mateusz Kulikowski + * + * Settings for Calao USB-A9263 board + * + * U-Boot image has to be less than 200704 bytes, otherwise at91bootstrap + * installed on board will not be able to load it properly. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 + +#define CONFIG_MACH_TYPE MACH_TYPE_USB_A9263 + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* + * Hardware drivers + */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) +#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) +#endif + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_AT91_WANTS_COMMON_PHY + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CONFIG_BOOTCOMMAND "nboot 21000000 0" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) + +#endif diff --git a/roms/u-boot/include/configs/usbarmory.h b/roms/u-boot/include/configs/usbarmory.h new file mode 100644 index 000000000..27053c067 --- /dev/null +++ b/roms/u-boot/include/configs/usbarmory.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * USB armory MkI board configuration settings + * http://inversepath.com/usbarmory + * + * Copyright (C) 2015, Inverse Path + * Andrej Rosano + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_FSL_CLK + +#include + +/* U-Boot environment */ + +/* U-Boot general configurations */ +#define CONFIG_SYS_CBSIZE 512 + +/* UART */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* SD/MMC */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + +/* USB */ +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ + +/* Fuse */ +#define CONFIG_FSL_IIM + +/* U-Boot memory offsets */ +#define CONFIG_LOADADDR 0x72000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Linux boot */ +#define CONFIG_HOSTNAME "usbarmory" +#define CONFIG_BOOTCOMMAND \ + "run distro_bootcmd; " \ + "setenv bootargs console=${console} ${bootargs_default}; " \ + "ext2load mmc 0:1 ${kernel_addr_r} /boot/zImage; " \ + "ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; " \ + "bootz ${kernel_addr_r} - ${fdt_addr_r}" + +#define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0) + +#include + +#define MEM_LAYOUT_ENV_SETTINGS \ + "kernel_addr_r=0x70800000\0" \ + "fdt_addr_r=0x71000000\0" \ + "scriptaddr=0x70800000\0" \ + "pxefile_addr_r=0x70800000\0" \ + "ramdisk_addr_r=0x73000000\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + "bootargs_default=root=/dev/mmcblk0p1 rootwait rw\0" \ + "fdtfile=imx53-usbarmory.dtb\0" \ + "console=ttymxc0,115200\0" \ + BOOTENV + +#ifndef CONFIG_CMDLINE +#define USBARMORY_FIT_PATH "/boot/usbarmory.itb" +#define USBARMORY_FIT_ADDR "0x70800000" +#endif + +/* Physical Memory Map */ +#define PHYS_SDRAM CSD0_BASE_ADDR +#define PHYS_SDRAM_SIZE (gd->ram_size) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/vcoreiii.h b/roms/u-boot/include/configs/vcoreiii.h new file mode 100644 index 000000000..82a8fa735 --- /dev/null +++ b/roms/u-boot/include/configs/vcoreiii.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef __VCOREIII_H +#define __VCOREIII_H + +#include + +/* Onboard devices */ + +#define CONFIG_SYS_MALLOC_LEN 0x1F0000 +#define CONFIG_SYS_LOAD_ADDR 0x00100000 +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +#if defined(CONFIG_SOC_LUTON) || defined(CONFIG_SOC_SERVAL) +#define CPU_CLOCK_RATE 416666666 /* Clock for the MIPS core */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 208333333 +#else +#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */ +#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) +#endif +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ) +#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) +#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT) +#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M) +#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16) +#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M) +#else +#error Unknown DDR size - please add! +#endif + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT) +#define VCOREIII_DEFAULT_MTD_ENV \ + "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ + "mtdids="CONFIG_MTDIDS_DEFAULT"\0" +#else +#define VCOREIII_DEFAULT_MTD_ENV /* Go away */ +#endif + +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + VCOREIII_DEFAULT_MTD_ENV \ + "loadaddr=0x81000000\0" \ + "spi_image_off=0x00100000\0" \ + "console=ttyS0,115200\0" \ + "setup=setenv bootargs console=${console} ${mtdparts}" \ + "${bootargs_extra}\0" \ + "spiboot=run setup; sf probe; sf read ${loadaddr}" \ + "${spi_image_off} 0x600000; bootm ${loadaddr}\0" \ + "ubootfile=u-boot.bin\0" \ + "update=sf probe;mtdparts;dhcp ${loadaddr} ${ubootfile};" \ + "sf erase UBoot 0x100000;" \ + "sf write ${loadaddr} UBoot ${filesize}\0" \ + "bootcmd=run spiboot\0" \ + "" +#endif /* __VCOREIII_H */ diff --git a/roms/u-boot/include/configs/ve8313.h b/roms/u-boot/include/configs/ve8313.h new file mode 100644 index 000000000..91249f2eb --- /dev/null +++ b/roms/u-boot/include/configs/ve8313.h @@ -0,0 +1,260 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. + * + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + */ +/* + * ve8313 board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 + +#define CONFIG_PCI_INDIRECT_BRIDGE 1 + +/* + * On-board devices + * + */ + +/* + * Device configurations + */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ + +/* + * Manually set up DDR parameters, as this board does not + * have the SPD connected to I2C. + */ +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_AP \ + | CSCONFIG_ODT_RD_NEVER \ + | CSCONFIG_ODT_WR_ALL \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) + /* 0x80840102 */ + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (3 << TIMING_CFG0_RRT_SHIFT) \ + | (2 << TIMING_CFG0_WWT_SHIFT) \ + | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x0e720802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (6 << TIMING_CFG1_REFREC_SHIFT) \ + | (2 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x26256222 */ +#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (5 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x029028c7 */ +#define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x03202000 */ +#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_32) + /* 0x43080000 */ +#define CONFIG_SYS_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0232 << SDRAM_MODE_SD_SHIFT)) + /* 0x44400232 */ +#define CONFIG_SYS_DDR_MODE_2 0x8000C000 + +#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + /*0x02000000*/ +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ + | DDRCDR_PZ_NOMZ \ + | DDRCDR_NZ_NOMZ \ + | DDRCDR_M_ODR) + /* 0x73000002 */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 +#define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ + +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) + +/* + * NAND settings + */ +#define CONFIG_SYS_NAND_BASE 0x61000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 + + + +/* Still needed for spl_minimal.c */ +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM + + + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +#if defined(CONFIG_PCI) +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#endif + +/* + * TSEC + */ + +#define CONFIG_TSEC1 +#ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 +#define CONFIG_TSEC1_NAME "TSEC1" +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x01 +#define TSEC1_FLAGS 0 +#define TSEC1_PHYIDX 0 +#endif + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC1" + +/* + * Environment + */ +/* Address and size of Redundant Environment Sector */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) + +/* System IO Config */ +#define CONFIG_SYS_SICRH (0x01000000 | \ + SICRH_ETSEC2_B | \ + SICRH_ETSEC2_C | \ + SICRH_ETSEC2_D | \ + SICRH_ETSEC2_E | \ + SICRH_ETSEC2_F | \ + SICRH_ETSEC2_G | \ + SICRH_TSOBI1 | \ + SICRH_TSOBI2) + /* 0x010fff03 */ +#define CONFIG_SYS_SICRL (SICRL_LBC | \ + SICRL_SPI_A | \ + SICRL_SPI_B | \ + SICRL_SPI_C | \ + SICRL_SPI_D | \ + SICRL_ETSEC2_A) + /* 0x33fc0003) */ + +#define CONFIG_NETDEV eth0 + +#define CONFIG_HOSTNAME "ve8313" +#define CONFIG_UBOOTPATH ve8313/u-boot.bin + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" __stringify(CONFIG_NETDEV) "\0" \ + "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \ + "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "u-boot_addr_r=100000\0" \ + "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ + "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ + " +${filesize};" \ + "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ + "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \ + " ${filesize};" \ + "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \ + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/venice2.h b/roms/u-boot/include/configs/venice2.h new file mode 100644 index 000000000..fe861a6f7 --- /dev/null +++ b/roms/u-boot/include/configs/venice2.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013-2014 + * NVIDIA Corporation + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra124-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +/* Environment in eMMC, at the end of 2nd "boot sector" */ + +/* SPI */ +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/ventana.h b/roms/u-boot/include/configs/ventana.h new file mode 100644 index 000000000..21f90f38f --- /dev/null +++ b/roms/u-boot/include/configs/ventana.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include "tegra20-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Ventana" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTD +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA + +/* Environment in eMMC, at the end of 2nd "boot sector" */ + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/verdin-imx8mm.h b/roms/u-boot/include/configs/verdin-imx8mm.h new file mode 100644 index 000000000..7be5e5ddf --- /dev/null +++ b/roms/u-boot/include/configs/verdin-imx8mm.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Toradex + */ + +#ifndef __VERDIN_IMX8MM_H +#define __VERDIN_IMX8MM_H + +#include +#include + +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x920000 +#define CONFIG_SPL_BSS_START_ADDR 0x910000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x930000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE +#endif + +#define MEM_LAYOUT_ENV_SETTINGS \ + "fdt_addr_r=0x44000000\0" \ + "kernel_addr_r=0x42000000\0" \ + "ramdisk_addr_r=0x46400000\0" \ + "scriptaddr=0x46000000\0" + +#define CONFIG_LOADADDR 0x40480000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Enable Distro Boot */ +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) +#include +#undef CONFIG_ISO_PARTITION +#else +#define BOOTENV +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + MEM_LAYOUT_ENV_SETTINGS \ + "bootcmd_mfg=fastboot 0\0" \ + "console=ttymxc0\0" \ + "fdt_addr=0x43000000\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_image=Image\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \ + "\0" \ + "nfsboot=run netargs; dhcp ${loadaddr} ${kernel_image}; " \ + "tftp ${fdt_addr} verdin/${fdtfile}; " \ + "booti ${loadaddr} - ${fdt_addr}\0" \ + "setup=setenv setupargs console=${console},${baudrate} " \ + "console=tty1 consoleblank=0 earlycon\0" \ + "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \ + "if test \"$confirm\" = \"y\"; then " \ + "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ + "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x2 " \ + "${blkcnt}; fi\0" + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#if defined(CONFIG_ENV_IS_IN_MMC) +/* Environment in eMMC, before config block at the end of 1st "boot sector" */ +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +/* SDRAM configuration */ +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ + +/* UART */ +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE SZ_2K +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* USDHC */ +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* ENET */ +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 7 +#define FEC_QUIRK_ENET_MAC +#define IMX_FEC_BASE 0x30BE0000 + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#endif /*_VERDIN_IMX8MM_H */ + diff --git a/roms/u-boot/include/configs/vexpress_aemv8a.h b/roms/u-boot/include/configs/vexpress_aemv8a.h new file mode 100644 index 000000000..7318fb6c5 --- /dev/null +++ b/roms/u-boot/include/configs/vexpress_aemv8a.h @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for Versatile Express. Parts were derived from other ARM + * configurations. + */ + +#ifndef __VEXPRESS_AEMV8A_H +#define __VEXPRESS_AEMV8A_H + +#define CONFIG_REMAKE_ELF + +/* Link Definitions */ +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP +/* ATF loads u-boot here for BASE_FVP model */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) +#elif CONFIG_TARGET_VEXPRESS64_JUNO +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#endif + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* CS register bases for the original memory map. */ +#define V2M_PA_CS0 0x00000000 +#define V2M_PA_CS1 0x14000000 +#define V2M_PA_CS2 0x18000000 +#define V2M_PA_CS3 0x1c000000 +#define V2M_PA_CS4 0x0c000000 +#define V2M_PA_CS5 0x10000000 + +#define V2M_PERIPH_OFFSET(x) (x << 16) +#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) +#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) +#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) + +#define V2M_BASE 0x80000000 + +/* Common peripherals relative to CS7. */ +#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) +#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) +#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) +#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) + +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define V2M_UART0 0x7ff80000 +#define V2M_UART1 0x7ff70000 +#else /* Not Juno */ +#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) +#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) +#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) +#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) +#endif + +#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) + +#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) +#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) + +#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) +#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) + +#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) + +#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) + +/* System register offsets. */ +#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) +#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) +#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 24000000 /* 24MHz */ + +/* Generic Interrupt Controller Definitions */ +#ifdef CONFIG_GICV3 +#define GICD_BASE (0x2f000000) +#define GICR_BASE (0x2f100000) +#else + +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP +#define GICD_BASE (0x2f000000) +#define GICC_BASE (0x2c000000) +#elif CONFIG_TARGET_VEXPRESS64_JUNO +#define GICD_BASE (0x2C010000) +#define GICC_BASE (0x2C02f000) +#endif +#endif /* !CONFIG_GICV3 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) + +#ifndef CONFIG_TARGET_VEXPRESS64_JUNO +/* The Vexpress64 simulators use SMSC91C111 */ +#define CONFIG_SMC91111 1 +#define CONFIG_SMC91111_BASE (0x01A000000) +#endif + +/* PL011 Serial Configuration */ +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define CONFIG_PL011_CLOCK 7372800 +#else +#define CONFIG_PL011_CLOCK 24000000 +#endif + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ +/* Top 16MB reserved for secure world use */ +#define DRAM_SEC_SIZE 0x01000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define PHYS_SDRAM_2 (0x880000000) +#define PHYS_SDRAM_2_SIZE 0x180000000 +#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP && CONFIG_NR_DRAM_BANKS == 2 +#define PHYS_SDRAM_2 (0x880000000) +#define PHYS_SDRAM_2_SIZE 0x80000000 +#endif + +/* Enable memtest */ + +/* Initial environment variables */ +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +/* + * Defines where the kernel and FDT exist in NOR flash and where it will + * be copied into DRAM + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_name=norkern\0" \ + "kernel_alt_name=Image\0" \ + "kernel_addr_r=0x80080000\0" \ + "ramdisk_name=ramdisk.img\0" \ + "ramdisk_addr_r=0x88000000\0" \ + "fdtfile=board.dtb\0" \ + "fdt_alt_name=juno\0" \ + "fdt_addr_r=0x80000000\0" \ + +#ifndef CONFIG_BOOTCOMMAND +/* Copy the kernel and FDT to DRAM memory and boot */ +#define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr_r} ;"\ + "if test $? -eq 1; then "\ + " echo Loading ${kernel_alt_name} instead of "\ + "${kernel_name}; "\ + " afs load ${kernel_alt_name} ${kernel_addr_r};"\ + "fi ; "\ + "afs load ${fdtfile} ${fdt_addr_r} ;"\ + "if test $? -eq 1; then "\ + " echo Loading ${fdt_alt_name} instead of "\ + "${fdtfile}; "\ + " afs load ${fdt_alt_name} ${fdt_addr_r}; "\ + "fi ; "\ + "fdt addr ${fdt_addr_r}; fdt resize; " \ + "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\ + "then "\ + " setenv ramdisk_param ${ramdisk_addr_r}; "\ + " else setenv ramdisk_param -; "\ + "fi ; " \ + "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}" +#endif + + +#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_name=Image\0" \ + "kernel_addr=0x80080000\0" \ + "initrd_name=ramdisk.img\0" \ + "initrd_addr=0x88000000\0" \ + "fdtfile=devtree.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "boot_name=boot.img\0" \ + "boot_addr=0x8007f800\0" + +#ifndef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "if smhload ${boot_name} ${boot_addr}; then " \ + " set bootargs; " \ + " abootimg addr ${boot_addr}; " \ + " abootimg get dtb --index=0 fdt_addr; " \ + " bootm ${boot_addr} ${boot_addr} " \ + " ${fdt_addr}; " \ + "else; " \ + " set fdt_high 0xffffffffffffffff; " \ + " set initrd_high 0xffffffffffffffff; " \ + " smhload ${kernel_name} ${kernel_addr}; " \ + " smhload ${fdtfile} ${fdt_addr}; " \ + " smhload ${initrd_name} ${initrd_addr} "\ + " initrd_end; " \ + " fdt addr ${fdt_addr}; fdt resize; " \ + " fdt chosen ${initrd_addr} ${initrd_end}; " \ + " booti $kernel_addr - $fdt_addr; " \ + "fi" +#endif +#endif + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define CONFIG_SYS_FLASH_BASE 0x08000000 +/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ +#define CONFIG_SYS_MAX_FLASH_SECT 259 +/* Store environment at top of flash in the same location as blank.img */ +/* in the Juno firmware. */ +#else +#define CONFIG_SYS_FLASH_BASE 0x0C000000 +/* 256 x 256KiB sectors */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 +/* Store environment at top of flash */ +#endif + +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#endif + +#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ +#define FLASH_MAX_SECTOR_SIZE 0x00040000 + +#endif /* __VEXPRESS_AEMV8A_H */ diff --git a/roms/u-boot/include/configs/vexpress_common.h b/roms/u-boot/include/configs/vexpress_common.h new file mode 100644 index 000000000..b131480e5 --- /dev/null +++ b/roms/u-boot/include/configs/vexpress_common.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 ARM Limited + * (C) Copyright 2010 Linaro + * Matt Waddel, + * + * Configuration for Versatile Express. Parts were derived from other ARM + * configurations. + */ + +#ifndef __VEXPRESS_COMMON_H +#define __VEXPRESS_COMMON_H + +/* + * Definitions copied from linux kernel: + * arch/arm/mach-vexpress/include/mach/motherboard.h + */ +#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP +/* CS register bases for the original memory map. */ +#define V2M_PA_CS0 0x40000000 +#define V2M_PA_CS1 0x44000000 +#define V2M_PA_CS2 0x48000000 +#define V2M_PA_CS3 0x4c000000 +#define V2M_PA_CS7 0x10000000 + +#define V2M_PERIPH_OFFSET(x) (x << 12) +#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0)) +#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1)) +#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2)) + +#define V2M_BASE 0x60000000 +#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP) +/* CS register bases for the extended memory map. */ +#define V2M_PA_CS0 0x08000000 +#define V2M_PA_CS1 0x0c000000 +#define V2M_PA_CS2 0x14000000 +#define V2M_PA_CS3 0x18000000 +#define V2M_PA_CS7 0x1c000000 + +#define V2M_PERIPH_OFFSET(x) (x << 16) +#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1)) +#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2)) +#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3)) + +#define V2M_BASE 0x80000000 +#endif + +/* + * Physical addresses, offset from V2M_PA_CS0-3 + */ +#define V2M_NOR0 (V2M_PA_CS0) +#define V2M_NOR1 (V2M_PA_CS1) +#define V2M_SRAM (V2M_PA_CS2) +#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000) +#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000) + +/* Common peripherals relative to CS7. */ +#define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4)) +#define V2M_MMCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5)) +#define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6)) +#define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7)) + +#define V2M_UART0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9)) +#define V2M_UART1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10)) +#define V2M_UART2 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11)) +#define V2M_UART3 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12)) + +#define V2M_WDT (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15)) + +#define V2M_TIMER01 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17)) +#define V2M_TIMER23 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18)) + +#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22)) +#define V2M_RTC (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23)) + +#define V2M_CF (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26)) + +#define V2M_CLCD (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31)) +#define V2M_SIZE_CS7 V2M_PERIPH_OFFSET(32) + +/* System register offsets. */ +#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) +#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) +#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) + +/* + * Configuration + */ +#define SYS_CFG_START (1 << 31) +#define SYS_CFG_WRITE (1 << 30) +#define SYS_CFG_OSC (1 << 20) +#define SYS_CFG_VOLT (2 << 20) +#define SYS_CFG_AMP (3 << 20) +#define SYS_CFG_TEMP (4 << 20) +#define SYS_CFG_RESET (5 << 20) +#define SYS_CFG_SCC (6 << 20) +#define SYS_CFG_MUXFPGA (7 << 20) +#define SYS_CFG_SHUTDOWN (8 << 20) +#define SYS_CFG_REBOOT (9 << 20) +#define SYS_CFG_DVIMODE (11 << 20) +#define SYS_CFG_POWER (12 << 20) +#define SYS_CFG_SITE_MB (0 << 16) +#define SYS_CFG_SITE_DB1 (1 << 16) +#define SYS_CFG_SITE_DB2 (2 << 16) +#define SYS_CFG_STACK(n) ((n) << 12) + +#define SYS_CFG_ERR (1 << 1) +#define SYS_CFG_COMPLETE (1 << 0) + +/* Board info register */ +#define SYS_ID V2M_SYSREGS +#define CONFIG_REVISION_TAG 1 + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_SYS_L2CACHE_OFF 1 +#define CONFIG_INITRD_TAG 1 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) /* >= 512 KiB */ + +#define SCTL_BASE V2M_SYSCTL +#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0) + +#define CONFIG_SYS_TIMER_RATE 1000000 +#define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) +#define CONFIG_SYS_TIMER_COUNTS_DOWN + +/* PL011 Serial Configuration */ +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} + +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_SERIAL0 V2M_UART0 +#define CONFIG_SYS_SERIAL1 V2M_UART1 + +#define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 +#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000 + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000) +#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000) + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ +#define PHYS_SDRAM_2 (((unsigned int)V2M_BASE) + \ + ((unsigned int)0x20000000)) +#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ +#define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */ + +/* additions for new relocation code */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET + +/* Basic environment settings */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) +#include + +#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP +#define CONFIG_PLATFORM_ENV_SETTINGS \ + "loadaddr=0x80008000\0" \ + "ramdisk_addr_r=0x61000000\0" \ + "kernel_addr=0x44100000\0" \ + "ramdisk_addr=0x44800000\0" \ + "maxramdisk=0x1800000\0" \ + "pxefile_addr_r=0x88000000\0" \ + "scriptaddr=0x88000000\0" \ + "kernel_addr_r=0x80008000\0" +#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP) +#define CONFIG_PLATFORM_ENV_SETTINGS \ + "loadaddr=0xa0008000\0" \ + "ramdisk_addr_r=0x81000000\0" \ + "kernel_addr=0x0c100000\0" \ + "ramdisk_addr=0x0c800000\0" \ + "maxramdisk=0x1800000\0" \ + "pxefile_addr_r=0xa8000000\0" \ + "scriptaddr=0xa8000000\0" \ + "kernel_addr_r=0xa0008000\0" +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_PLATFORM_ENV_SETTINGS \ + BOOTENV \ + "console=ttyAMA0,38400n8\0" \ + "dram=1024M\0" \ + "root=/dev/sda1 rw\0" \ + "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \ + "24M@0x2000000(initrd)\0" \ + "flashargs=setenv bootargs root=${root} console=${console} " \ + "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \ + "devtmpfs.mount=0 vmalloc=256M\0" \ + "bootflash=run flashargs; " \ + "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \ + "bootm ${kernel_addr} ${ramdisk_addr_r}\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" + +/* FLASH and environment organization */ +#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ +#define CONFIG_SYS_FLASH_SIZE 0x04000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_BASE0 V2M_NOR0 +#define CONFIG_SYS_FLASH_BASE1 V2M_NOR1 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0 + +/* Timeout values in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ + +/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */ +#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */ +#define FLASH_MAX_SECTOR_SIZE 0x00040000 /* 256 KB sectors */ + +/* Room required on the stack for the environment data */ + +/* + * Amount of flash used for environment: + * We don't know which end has the small erase blocks so we use the penultimate + * sector location for the environment + */ + +/* Store environment at top of flash */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \ + CONFIG_SYS_FLASH_BASE1 } + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ + +#endif /* VEXPRESS_COMMON_H */ diff --git a/roms/u-boot/include/configs/veyron.h b/roms/u-boot/include/configs/veyron.h new file mode 100644 index 000000000..2ab6d6c6a --- /dev/null +++ b/roms/u-boot/include/configs/veyron.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#define CONFIG_KEYBOARD + +#endif diff --git a/roms/u-boot/include/configs/vf610twr.h b/roms/u-boot/include/configs/vf610twr.h new file mode 100644 index 000000000..fd4c749d9 --- /dev/null +++ b/roms/u-boot/include/configs/vf610twr.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale Vybrid vf610twr board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_MACH_TYPE 4146 + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* Enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) + +/* NAND support */ +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR + +/* Dynamic MTD partition support */ +#endif + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_FEC_MXC_PHYADDR 0 + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_SPD_BUS_NUM 0 + + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +/* We boot from the gfxRAM area of the OCRAM. */ +#define CONFIG_BOARD_SIZE_LIMIT 520192 + +/* + * We do have 128MB of memory on the Vybrid Tower board. Leave the last + * 16MB alone to avoid conflicts with Cortex-M4 firmwares running from + * DDR3. Hence, limit the memory range for image processing to 112MB + * using bootm_size. All of the following must be within this range. + * We have the default load at 32MB into DDR (for the kernel), FDT at + * 64MB and the ramdisk 512KB above that (allowing for hopefully never + * seen large trees). This allows a reasonable split between ramdisk + * and kernel size, where the ram disk can be a bit larger. + */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x07000000\0" \ + "loadaddr=0x82000000\0" \ + "kernel_addr_r=0x82000000\0" \ + "fdt_addr=0x84000000\0" \ + "fdt_addr_r=0x84000000\0" \ + "rdaddr=0x84080000\0" \ + "ramdisk_addr_r=0x84080000\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttyLP1\0" \ + "fdt_file=vf610-twr.dtb\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "update_sd_firmware_filename=u-boot.imx\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ + +/* Physical memory map */ +#define PHYS_SDRAM (0x80000000) +#define PHYS_SDRAM_SIZE (128 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_RANGE (512 * 1024) +#endif + +#endif diff --git a/roms/u-boot/include/configs/vinco.h b/roms/u-boot/include/configs/vinco.h new file mode 100644 index 000000000..496c228b5 --- /dev/null +++ b/roms/u-boot/include/configs/vinco.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the VInCo platform. + * + * Based on the settings for the SAMA5-EK board + * Copyright (C) 2014 Atmel + * Bo Shen + * Copyright (C) 2015 Free Electrons + * Gregory CLEMENT gregory.clement@free-electrons.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +/* The value in the common file is too far away for the VInCo platform */ + +/* serial console */ +#define CONFIG_USART_BASE 0xfc00c000 +#define CONFIG_USART_ID 30 + +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x4000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* SerialFlash */ + +#ifdef CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI0 +#define CONFIG_SPI_FLASH_STMICRO +#endif + +/* MMC */ + +#ifdef CONFIG_CMD_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define ATMEL_BASE_MMCI 0xfc000000 +#define CONFIG_SYS_MMC_CLK_OD 500000 + +/* For generating MMC partitions */ + +#endif + +/* USB device */ + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY + +#ifdef CONFIG_SPI_BOOT +/* bootstrap + u-boot + env + linux in serial flash */ +/* Use our own mapping for the VInCo platform */ + +/* Update the bootcommand according to our mapping for the VInCo platform */ +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "mmc dev 0 0;" \ + "mmc read ${loadaddr} ${k_offset} ${k_blksize};" \ + "mmc read ${oftaddr} ${dtb_offset} ${dtb_blksize};" \ + "bootz ${loadaddr} - ${oftaddr}" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_start=0x20000\0" \ + "kernel_size=0x800000\0" \ + "mmcblksize=0x200\0" \ + "oftaddr=0x21000000\0" \ + "loadaddr=0x22000000\0" \ + "update_uboot=tftp ${loadaddr} u-boot.bin;sf probe 0;" \ + "sf erase 0x20000 0x4B000; sf write ${loadaddr} 0x20000 0x4B000\0" \ + "create_partition=setexpr dtb_start ${kernel_start} + 0x400000;" \ + "setexpr rootfs_start ${kernel_start} + ${kernel_size};" \ + "setenv partitions 'name=kernel,size=${kernel_size}," \ + "start=${kernel_start};name=rootfs,size=-';" \ + "gpt write mmc 0 ${partitions} \0"\ + "f2blk_size=setexpr fileblksize ${filesize} / ${mmcblksize};" \ + "setexpr fileblksize ${fileblksize} + 1\0" \ + "store_kernel=tftp ${loadaddr} zImage; run f2blk_size;" \ + "setexpr k_blksize ${fileblksize};" \ + "setexpr k_offset ${kernel_start} / ${mmcblksize};" \ + "mmc write ${fileaddr} ${k_offset} ${fileblksize}\0" \ + "store_dtb=tftp ${loadaddr} at91-vinco.dtb; run f2blk_size;" \ + "setexpr dtb_blksize ${fileblksize};" \ + "setexpr dtb_offset ${dtb_start} / ${mmcblksize};" \ + "mmc write ${fileaddr} ${dtb_offset} ${fileblksize}\0" \ + "store_rootfs=tftp ${loadaddr} vinco-gateway-image-vinco.ext4;" \ + "setexpr rootfs_offset ${rootfs_start} / ${mmcblksize};" \ + "mmc write ${fileaddr} ${rootfs_offset} ${fileblksize}\0" \ + "bootdelay=0\0" + +#endif + +#endif diff --git a/roms/u-boot/include/configs/vining_2000.h b/roms/u-boot/include/configs/vining_2000.h new file mode 100644 index 000000000..f97431f13 --- /dev/null +++ b/roms/u-boot/include/configs/vining_2000.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 samtec automotive software & electronics gmbh + * + * Configuration settings for the Samtec VIN|ING 2000 board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + +#ifdef CONFIG_SPL +#include "imx6_spl.h" +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) +#include + +/* Miscellaneous configurable options */ + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +/* Network */ +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0 + +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) +#endif + +#define CONFIG_IMX6_PWM_PER_CLK 66000000 + +#ifdef CONFIG_ENV_IS_IN_MMC +/* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */ +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_MXC_UART_BASE UART1_BASE +#endif + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/vme8349.h b/roms/u-boot/include/configs/vme8349.h new file mode 100644 index 000000000..20fcce187 --- /dev/null +++ b/roms/u-boot/include/configs/vme8349.h @@ -0,0 +1,315 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * esd vme8349 U-Boot configuration file + * Copyright (c) 2008, 2009 esd gmbh Hannover Germany + * + * (C) Copyright 2006-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * reinhard.arlt@esd-electronics.de + * Based on the MPC8349EMDS config. + */ + +/* + * vme8349 board configuration file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ + +/* Don't enable PCI2 on vme834x - it doesn't exist physically. */ +#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ + +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ + +/* + * DDR Setup + */ +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +#define CONFIG_SPD_EEPROM +#define SPD_EEPROM_ADDRESS 0x54 +#define CONFIG_SYS_READ_SPD vme8349_read_spd +#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ + +/* + * 32-bit data path mode. + * + * Please note that using this mode for devices with the real density of 64-bit + * effectively reduces the amount of available memory due to the effect of + * wrapping around while translating address to row/columns, for example in the + * 256MB module the upper 128MB get aliased with contents of the lower + * 128MB); normally this define should be used for devices with real 32-bit + * data path. + */ +#undef CONFIG_DDR_32BIT + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ + | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) +#define CONFIG_DDR_2T_TIMING +#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN) + /* 0x80080001 */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ + + +#define CONFIG_SYS_WINDOW1_BASE 0xf0000000 + + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ + +#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } +/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ + +#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ + +/* TSEC */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 +#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE +#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 +#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0xFIXME +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + +/* + * TSEC configuration + */ + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_GMII /* MII PHY management */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_PHY_M88E1111 +#define TSEC1_PHY_ADDR 0x08 +#define TSEC2_PHY_ADDR 0x10 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#ifndef CONFIG_SYS_RAMBOOT +/* Address and size of Redundant Environment Sector */ +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#define CONFIG_SYS_RTC_BUS_NUM 0x01 +#define CONFIG_SYS_I2C_RTC_ADDR 0x32 + +/* Pass Ethernet MAC to VxWorks */ +#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +/* System IO Config */ +#define CONFIG_SYS_SICRH 0 +#define CONFIG_SYS_SICRL SICRL_LDP_A + +#define CONFIG_SYS_GPIO1_PRELIM +#define CONFIG_SYS_GPIO1_DIR 0x00100000 +#define CONFIG_SYS_GPIO1_DAT 0x00100000 + +#define CONFIG_SYS_GPIO2_PRELIM +#define CONFIG_SYS_GPIO2_DIR 0x78900000 +#define CONFIG_SYS_GPIO2_DAT 0x70100000 + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_HOSTNAME "VME8349" +#define CONFIG_ROOTPATH "/tftpboot/rootfs" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=vme8349\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ + "update=protect off fff00000 fff3ffff; " \ + "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ + "upd=run load update\0" \ + "fdtaddr=780000\0" \ + "fdtfile=vme8349.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ + "$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#ifndef __ASSEMBLY__ +int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len); +#endif + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/vocore2.h b/roms/u-boot/include/configs/vocore2.h new file mode 100644 index 000000000..dfdb8fcc0 --- /dev/null +++ b/roms/u-boot/include/configs/vocore2.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Mauro Condarelli + */ + +#ifndef __VOCORE2_CONFIG_H__ +#define __VOCORE2_CONFIG_H__ + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +/* SPL */ +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SPL_BSS_START_ADDR 0x80010000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_PAD_TO 0 + +/* Dummy value */ +#define CONFIG_SYS_UBOOT_BASE 0 + +/* Serial SPL */ +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_CLK 40000000 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM3 0xb0000e00 +#define CONFIG_CONS_INDEX 3 + +/* RAM */ + +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_CBSIZE 512 + +/* U-Boot */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +/* Environment settings */ + +#endif //__VOCORE2_CONFIG_H__ diff --git a/roms/u-boot/include/configs/vyasa-rk3288.h b/roms/u-boot/include/configs/vyasa-rk3288.h new file mode 100644 index 000000000..3dc10b29c --- /dev/null +++ b/roms/u-boot/include/configs/vyasa-rk3288.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Amarula Solutions + * + * Configuration settings for Amarula Vyasa RK3288. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#undef BOOT_TARGET_DEVICES + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + +#ifndef CONFIG_TPL_BUILD + +#define CONFIG_SPL_OS_BOOT + +/* Falcon Mode */ +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SYS_SPL_ARGS_ADDR 0x0ffe5000 + +/* Falcon Mode - MMC support: args@16MB kernel@17MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8000 /* 16MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x8800 /* 17MB */ +#endif + +#endif diff --git a/roms/u-boot/include/configs/wandboard.h b/roms/u-boot/include/configs/wandboard.h new file mode 100644 index 000000000..bd64893fc --- /dev/null +++ b/roms/u-boot/include/configs/wandboard.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for the Wandboard. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + +#include "imx6_spl.h" + +#define CONFIG_MACH_TYPE MACH_TYPE_WANDBOARD_IMX6 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* SATA Configs */ + +#ifdef CONFIG_CMD_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#endif + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +/* USB Configs */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* Framebuffer */ +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0\0" \ + "splashpos=m,m\0" \ + "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=undefined\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_addr_r=0x18000000\0" \ + "fdt_addr=0x18000000\0" \ + "ip_dyn=yes\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "finduuid=part uuid mmc 0:1 uuid\0" \ + "update_sd_firmware_filename=u-boot.imx\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + "findfdt="\ + "if test $board_name = D1 && test $board_rev = MX6QP ; then " \ + "setenv fdtfile imx6qp-wandboard-revd1.dtb; fi; " \ + "if test $board_name = D1 && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-wandboard-revd1.dtb; fi; " \ + "if test $board_name = D1 && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-wandboard-revd1.dtb; fi; " \ + "if test $board_name = C1 && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-wandboard.dtb; fi; " \ + "if test $board_name = C1 && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-wandboard.dtb; fi; " \ + "if test $board_name = B1 && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-wandboard-revb1.dtb; fi; " \ + "if test $board_name = B1 && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-wandboard-revb1.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine dtb to use; fi; \0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "ramdiskaddr=0x13000000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(SATA, sata, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include +#include + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ + +#endif /* __CONFIG_H * */ diff --git a/roms/u-boot/include/configs/warp.h b/roms/u-boot/include/configs/warp.h new file mode 100644 index 000000000..0f97804eb --- /dev/null +++ b/roms/u-boot/include/configs/warp.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 O.S. Systems Software LTDA. + * Copyright (C) 2014 Kynetics LLC. + * Copyright (C) 2014 Revolution Robotics, Inc. + * + * Author: Otavio Salvador + * + * Configuration settings for the WaRP Board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ + +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE + +/* Watchdog */ + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* VDD voltage 1.65 - 1.95 */ +#define CONFIG_SYS_SD_VOLTAGE 0x00000080 + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG2 port enabled */ +#endif + +#define CONFIG_USBD_HS + +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx6sl-warp.dtb\0" \ + "fdt_addr=0x88000000\0" \ + "initrd_addr=0x83800000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "finduuid=part uuid mmc 0:2 uuid\0" \ + "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=PARTUUID=${uuid} rootwait rw\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run finduuid; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/warp7.h b/roms/u-boot/include/configs/warp7.h new file mode 100644 index 000000000..8eb106027 --- /dev/null +++ b/roms/u-boot/include/configs/warp7.h @@ -0,0 +1,160 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 NXP Semiconductors + * + * Configuration settings for the i.MX7S Warp board. + */ + +#ifndef __WARP7_CONFIG_H +#define __WARP7_CONFIG_H + +#include "mx7_common.h" +#include + +#define PHYS_SDRAM_SIZE SZ_512M + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) + +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR +#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* Switch on SERIAL_TAG */ +#define CONFIG_SERIAL_TAG + +#define CONFIG_DFU_ENV_SETTINGS \ + "dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \ + +/* When booting with FIT specify the node entry containing boot.scr */ +#if defined(CONFIG_FIT) +#define BOOT_SCR_STRING "source ${bootscriptaddr}:${bootscr_fitimage_name}\0" +#else +#define BOOT_SCR_STRING "source ${bootscriptaddr}\0" +#endif + +#ifndef CONFIG_OPTEE_LOAD_ADDR +#define CONFIG_OPTEE_LOAD_ADDR 0 +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_DFU_ENV_SETTINGS \ + "script=boot.scr\0" \ + "bootscr_fitimage_name=bootscr\0" \ + "script_signed=boot.scr.imx-signed\0" \ + "bootscriptaddr=0x83200000\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "ethact=usb_ether\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx7s-warp.dtb\0" \ + "fdt_addr=" __stringify(CONFIG_SYS_FDT_ADDR)"\0" \ + "fdtovaddr=0x83100000\0" \ + "optee_addr=" __stringify(CONFIG_OPTEE_LOAD_ADDR)"\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "rootpart=" __stringify(CONFIG_WARP7_ROOT_PART) "\0" \ + "finduuid=part uuid mmc 0:${rootpart} uuid\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=PARTUUID=${uuid} rootwait rw\0" \ + "ivt_offset=" __stringify(BOOTROM_IVT_HDR_OFFSET)"\0"\ + "warp7_auth_or_fail=hab_auth_img_or_fail ${hab_ivt_addr} ${filesize} 0;\0" \ + "do_bootscript_hab=" \ + "if test ${hab_enabled} -eq 1; then " \ + "setexpr hab_ivt_addr ${bootscriptaddr} - ${ivt_offset}; " \ + "setenv script ${script_signed}; " \ + "load mmc ${mmcdev}:${mmcpart} ${hab_ivt_addr} ${script}; " \ + "run warp7_auth_or_fail; " \ + "run bootscript; "\ + "fi;\0" \ + "loadbootscript=" \ + "load mmc ${mmcdev}:${mmcpart} ${bootscriptaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + BOOT_SCR_STRING \ + "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run finduuid; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "run do_bootscript_hab;" \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi" + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* + * Environment starts at CONFIG_ENV_OFFSET= 0xC0000 = 768k = 768*1024 = 786432 + * + * Detect overlap between U-Boot image and environment area in build-time + * + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset + * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408 + * + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so + * write the direct value here + */ +#define CONFIG_BOARD_SIZE_LIMIT 785408 + +/* I2C configs */ +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* environment organization */ + +#define CONFIG_SYS_FSL_USDHC_NUM 1 + + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +#define CONFIG_USBD_HS + +/* USB Device Firmware Update support */ +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +#define CONFIG_USBNET_DEV_ADDR "de:ad:be:af:00:01" + +/* Environment variable name to represent HAB enable state */ +#define HAB_ENABLED_ENVNAME "hab_enabled" + +#endif diff --git a/roms/u-boot/include/configs/work_92105.h b/roms/u-boot/include/configs/work_92105.h new file mode 100644 index 000000000..7874b77f3 --- /dev/null +++ b/roms/u-boot/include/configs/work_92105.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * WORK Microwave work_92105 board configuration file + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD + */ + +#ifndef __CONFIG_WORK_92105_H__ +#define __CONFIG_WORK_92105_H__ + +/* SoC and board defines */ +#include +#include + +/* + * Define work_92105 machine type by hand -- done only for compatibility + * with original board code + */ +#define CONFIG_MACH_TYPE 736 + +#if !defined(CONFIG_SPL_BUILD) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * Memory configurations + */ +#define CONFIG_SYS_MALLOC_LEN SZ_1M +#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CONFIG_SYS_SDRAM_SIZE SZ_128M + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ + - GENERATED_GBL_DATA_SIZE) + +/* + * Serial Driver + */ +#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ + +/* + * Ethernet Driver + */ + +#define CONFIG_LPC32XX_ETH +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */ + +/* + * I2C driver + */ + +#define CONFIG_SYS_I2C_LPC32XX +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SPEED 350000 + +/* + * I2C EEPROM + */ + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* + * I2C RTC + */ + +#define CONFIG_RTC_DS1374 + +/* + * U-Boot General Configurations + */ +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * NAND chip timings for FIXME: which one? + */ + +#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 +#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 +#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 +#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 +#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 +#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 +#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 + +/* + * NAND + */ + +/* driver configuration */ +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_MAX_NAND_CHIPS 1 +#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE +#define CONFIG_NAND_LPC32XX_MLC + +/* + * GPIO + */ + +#define CONFIG_LPC32XX_GPIO + +/* + * Environment + */ + +/* + * Boot Linux + */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR 0x80008000 + +/* + * SPL + */ + +/* SPL will be executed at offset 0 */ +/* SPL will use SRAM as stack */ +#define CONFIG_SPL_STACK 0x0000FFF8 +/* Use the framework and generic lib */ +/* SPL will use serial */ +/* SPL will load U-Boot from NAND offset 0x40000 */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000 +#define CONFIG_SPL_PAD_TO 0x20000 +/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ +#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */ +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE + +/* + * Include SoC specific configuration + */ +#include + +#endif /* __CONFIG_WORK_92105_H__*/ diff --git a/roms/u-boot/include/configs/x530.h b/roms/u-boot/include/configs/x530.h new file mode 100644 index 000000000..4446510df --- /dev/null +++ b/roms/u-boot/include/configs/x530.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Allied Telesis Labs + */ + +#ifndef _CONFIG_X530_H +#define _CONFIG_X530_H + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_DISPLAY_BOARDINFO_LATE + +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#if !defined(CONFIG_DM_SERIAL) +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE +#endif + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +/* NAND */ +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define BBT_CUSTOM_SCAN +#define BBT_CUSTOM_SCAN_PAGE 0 +#define BBT_CUSTOM_SCAN_POSITION 2048 + +/* SPI NOR flash default params, used by sf commands */ + +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)" +#define MTDPARTS_MTDOOPS "errlog" + +/* Partition support */ + +/* Additional FS support/configuration */ + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +/* Environment in SPI NOR flash */ + +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* NAND */ +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_MALLOC_LEN (4 << 20) + +#include + +/* + * Other required minimal configurations + */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ + +/* Keep device tree and initrd in low memory so the kernel can access them */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +#define CONFIG_SYS_LOAD_ADDR 0x1000000 +#define CONFIG_UBI_PART user +#define CONFIG_UBIFS_VOLUME user + +/* SPL */ + +/* Defines for SPL */ +#define CONFIG_SPL_SIZE (140 << 10) +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +/* SPL related SPI defines */ +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS + +#endif /* _CONFIG_X530_H */ diff --git a/roms/u-boot/include/configs/x600.h b/roms/u-boot/include/configs/x600.h new file mode 100644 index 000000000..0dd572279 --- /dev/null +++ b/roms/u-boot/include/configs/x600.h @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2009, STMicroelectronics - All Rights Reserved + * Author(s): Vipin Kumar, for STMicroelectronics. + * + * Copyright (C) 2012, 2015 Stefan Roese + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SPEAR600 /* SPEAr600 SoC */ +#define CONFIG_X600 /* on X600 board */ + +#include + +/* Timer, HZ specific defines */ +#define CONFIG_SYS_HZ_CLOCK 8300000 + +#define CONFIG_SYS_FLASH_BASE 0xf8000000 +/* Reserve 8KiB for SPL */ +#define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO +#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ + CONFIG_SYS_SPL_LEN) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN 0x60000 + +/* Serial Configuration (PL011) */ +#define CONFIG_SYS_SERIAL0 0xD0000000 +#define CONFIG_SYS_SERIAL1 0xD0080000 +#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1 } +#define CONFIG_PL011_CLOCK (48 * 1000 * 1000) +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ + 57600, 115200 } +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* NOR FLASH config options */ +#define CONFIG_ST_SMI +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 +#define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) + +/* NAND FLASH config options */ +#define CONFIG_NAND_FSMC +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE +#define CONFIG_MTD_ECC_SOFT +#define CONFIG_SYS_FSMC_NAND_8BIT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_ECC_BCH + +/* UBI/UBI config options */ + +/* Ethernet config options */ +#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ + +#define CONFIG_SPEAR_GPIO + +/* I2C config options */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_BASE 0xD0200000 +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x02 +#define CONFIG_I2C_CHIPADDRESS 0x50 + +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* FPGA config options */ +#define CONFIG_FPGA_COUNT 1 + +/* USB EHCI options */ +#define CONFIG_USB_EHCI_SPEAR +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* + * U-Boot Environment placing definitions. + */ + +/* Miscellaneous configurable options */ +#define CONFIG_BOOT_PARAMS_ADDR 0x00000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#define CONFIG_SYS_MALLOC_LEN (8 << 20) +#define CONFIG_SYS_LOAD_ADDR 0x00800000 + +#define CONFIG_HOSTNAME "x600" +#define CONFIG_UBI_PART ubi0 +#define CONFIG_UBIFS_VOLUME rootfs + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "u-boot_addr=1000000\0" \ + "u-boot=" CONFIG_HOSTNAME "/u-boot.spr\0" \ + "load=tftp ${u-boot_addr} ${u-boot}\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};" \ + "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ + "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " ${filesize};" \ + "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize}\0" \ + "upd=run load update\0" \ + "ubifs=" CONFIG_HOSTNAME "/ubifs.img\0" \ + "part=" __stringify(CONFIG_UBI_PART) "\0" \ + "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ + "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ + "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ + " ${filesize}\0" \ + "upd_ubifs=run load_ubifs update_ubifs\0" \ + "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ + "ubi create ${vol} 4000000\0" \ + "netdev=eth0\0" \ + "rootpath=/opt/eldk-4.2/arm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "boot_part=0\0" \ + "altbootcmd=if test $boot_part -eq 0;then " \ + "echo Switching to partition 1!;" \ + "setenv boot_part 1;" \ + "else; " \ + "echo Switching to partition 0!;" \ + "setenv boot_part 0;" \ + "fi;" \ + "saveenv;boot\0" \ + "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ + "root=ubi0:rootfs rootfstype=ubifs\0" \ + "kernel=" CONFIG_HOSTNAME "/uImage\0" \ + "kernel_fs=/boot/uImage \0" \ + "kernel_addr=1000000\0" \ + "dtb=" CONFIG_HOSTNAME "/" \ + CONFIG_HOSTNAME ".dtb\0" \ + "dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0" \ + "dtb_addr=1800000\0" \ + "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ + "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ + "${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "net_nfs=run load_dtb load_kernel; " \ + "run nfsargs addip addcon addmtd addmisc;" \ + "bootm ${kernel_addr} - ${dtb_addr}\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ + " addcon addmisc addmtd;" \ + "bootm ${kernel_addr} - ${dtb_addr}\0" \ + "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \ + "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ + "ubifsload ${dtb_addr} ${dtb_fs};\0" \ + "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ + "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ + "bootcmd=run nand_ubifs\0" \ + "\0" + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_MAXSIZE 0x40000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SRAM_BASE 0xd2800000 +/* Preserve the last 2 lwords for the boot-counter */ +#define CONFIG_SRAM_SIZE ((8 << 10) - 0x8) +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* + * SPL related defines + */ +#define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00) +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" + +/* + * Please select/define only one of the following + * Each definition corresponds to a supported DDR chip. + * DDR configuration is based on the following selection + */ +#define CONFIG_DDR_MT47H64M16 1 +#define CONFIG_DDR_MT47H32M16 0 +#define CONFIG_DDR_MT47H128M8 0 + +/* + * Synchronous/Asynchronous operation of DDR + * + * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation + * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation + * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation + */ +#define CONFIG_DDR_2HCLK 1 +#define CONFIG_DDR_HCLK 0 +#define CONFIG_DDR_PLL2 0 + +/* + * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported + * or not. Modify/Add to only these macros to define new boot types + */ +#define USB_BOOT_SUPPORTED 0 +#define PCIE_BOOT_SUPPORTED 0 +#define SNOR_BOOT_SUPPORTED 1 +#define NAND_BOOT_SUPPORTED 1 +#define PNOR_BOOT_SUPPORTED 0 +#define TFTP_BOOT_SUPPORTED 0 +#define UART_BOOT_SUPPORTED 0 +#define SPI_BOOT_SUPPORTED 0 +#define I2C_BOOT_SUPPORTED 0 +#define MMC_BOOT_SUPPORTED 0 + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/x86-chromebook.h b/roms/u-boot/include/configs/x86-chromebook.h new file mode 100644 index 000000000..0efc7156a --- /dev/null +++ b/roms/u-boot/include/configs/x86-chromebook.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Google, Inc + */ + +#ifndef _X86_CHROMEBOOK_H +#define _X86_CHROMEBOOK_H + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_X86_MRC_ADDR 0xfffa0000 +#define CONFIG_X86_REFCODE_ADDR 0xffea0000 +#define CONFIG_X86_REFCODE_RUN_ADDR 0 + +#define CONFIG_PCI_MEM_BUS 0xe0000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_PREF_BUS 0xd0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x1000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xefff + +#define CONFIG_BIOSEMU +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ + "stdout=vidconsole,serial\0" \ + "stderr=vidconsole,serial\0" + +#endif diff --git a/roms/u-boot/include/configs/x86-common.h b/roms/u-boot/include/configs/x86-common.h new file mode 100644 index 000000000..f186dd6b8 --- /dev/null +++ b/roms/u-boot/include/configs/x86-common.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + */ + +#include + +#ifndef __CONFIG_X86_COMMON_H +#define __CONFIG_X86_COMMON_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PHYSMEM + +#define CONFIG_SYS_BOOTM_LEN (16 << 20) + +/* SATA AHCI storage */ +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_LBA48 +#define CONFIG_SYS_64BIT_LBA + +#endif + +/* Generic TPM interfaced through LPC bus */ +#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 + +/*----------------------------------------------------------------------- + * Real Time Clock Configuration + */ +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 +#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS + +/*----------------------------------------------------------------------- + * Serial Configuration + */ +#define CONFIG_SYS_NS16550_PORT_MAPPED + +#ifndef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND \ + "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000" +#endif + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_CBSIZE 512 + +#define CONFIG_SYS_LOAD_ADDR 0x20000000 + +/*----------------------------------------------------------------------- + * CPU Features + */ + +#define CONFIG_SYS_STACK_SIZE (32 * 1024) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MALLOC_LEN 0x200000 + +/*----------------------------------------------------------------------- + * Environment configuration + */ + +/*----------------------------------------------------------------------- + * PCI configuration + */ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE + +/*----------------------------------------------------------------------- + * USB configuration + */ + +#define CONFIG_TFTP_TSIZE +#define CONFIG_BOOTP_BOOTFILESIZE + +/* Default environment */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_HOSTNAME "x86" +#define CONFIG_BOOTFILE "bzImage" +#define CONFIG_LOADADDR 0x1000000 +#define CONFIG_RAMDISK_ADDR 0x4000000 +#if defined(CONFIG_GENERATE_ACPI_TABLE) || defined(CONFIG_EFI_STUB) +#define CONFIG_OTHBOOTARGS "othbootargs=\0" +#else +#define CONFIG_OTHBOOTARGS "othbootargs=acpi=off\0" +#endif + +#if defined(CONFIG_DISTRO_DEFAULTS) +#define DISTRO_BOOTENV BOOTENV +#else +#define DISTRO_BOOTENV +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DISTRO_BOOTENV \ + CONFIG_STD_DEVICES_SETTINGS \ + "pciconfighost=1\0" \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + CONFIG_OTHBOOTARGS \ + "scriptaddr=0x7000000\0" \ + "kernel_addr_r=0x1000000\0" \ + "ramdisk_addr_r=0x4000000\0" \ + "ramdiskfile=initramfs.gz\0" + + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftpboot $kernel_addr_r $bootfile;" \ + "tftpboot $ramdisk_addr_r $ramdiskfile;" \ + "zboot $kernel_addr_r 0 $ramdisk_addr_r $filesize" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftpboot $kernel_addr_r $bootfile;" \ + "zboot $kernel_addr_r" + + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/xea.h b/roms/u-boot/include/configs/xea.h new file mode 100644 index 000000000..1207f7501 --- /dev/null +++ b/roms/u-boot/include/configs/xea.h @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * Copyright (C) 2018 DENX Software Engineering + * Måns Rullgård, DENX Software Engineering, mans@mansr.com + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ +#ifndef __CONFIGS_XEA_H__ +#define __CONFIGS_XEA_H__ + +#include + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* SPL */ +#define CONFIG_SPL_STACK 0x20000 + +#define CONFIG_SYS_SPL_ARGS_ADDR 0x44000000 + +#define CONFIG_SYS_SPI_KERNEL_OFFS SZ_1M +#define CONFIG_SYS_SPI_ARGS_OFFS SZ_512K +#define CONFIG_SYS_SPI_ARGS_SIZE SZ_32K + +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (SZ_512K / 0x200) +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (SZ_32K / 0x200) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (SZ_1M / 0x200) + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SPI_FLASH_MTD +#endif + +/* Memory configuration */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Environment */ + +/* Booting Linux */ +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTCOMMAND "run ${bootpri} ; run ${bootsec}" +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Extra Environment */ +#define CONFIG_HOSTNAME "xea" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootmode=update\0" \ + "bootpri=mmc_mmc\0" \ + "bootsec=sf_swu\0" \ + "consdev=ttyAMA0\0" \ + "baudrate=115200\0" \ + "dtbaddr=0x44000000\0" \ + "dtbfile=imx28-xea.dtb\0" \ + "rootdev=/dev/mmcblk0p2\0" \ + "netdev=eth0\0" \ + "rdaddr=0x43000000\0" \ + "swufile=swupdate.img\0" \ + "sf_kernel_offset=0x100000\0" \ + "sf_kernel_size=0x400000\0" \ + "sf_swu_offset=0x500000\0" \ + "sf_swu_size=0x800000\0" \ + "rootpath=/opt/eldk-5.5/armv5te/rootfs-qte-sdk\0" \ + "do_update_mmc=" \ + "if mmc rescan ; then " \ + "mmc dev 0 ${update_mmc_part} ; " \ + "if dhcp ${hostname}/${update_filename} ; then " \ + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ + "setexpr fw_sz ${fw_sz} + 1 ; " \ + "mmc write ${loadaddr} ${update_offset} ${fw_sz} ; " \ + "fi ; " \ + "fi\0" \ + "do_update_sf=" \ + "if sf probe ; then " \ + "if dhcp ${hostname}/${update_filename} ; then " \ + "sf erase ${update_offset} +${filesize} ; " \ + "sf write ${loadaddr} ${update_offset} ${filesize} ; " \ + "fi ; " \ + "fi\0" \ + "update_spl_filename=u-boot.sb\0" \ + "update_spl=" \ + "setenv update_filename ${update_spl_filename} ; " \ + "setenv update_offset 0 ; " \ + "run do_update_sf\0" \ + "update_uboot_filename=u-boot.img\0" \ + "update_uboot=" \ + "setenv update_filename ${update_uboot_filename} ; " \ + "setenv update_offset 0x10000 ; " \ + "run do_update_sf ; " \ + "setenv update_mmc_part 1 ; " \ + "setenv update_offset 0 ; " \ + "run do_update_mmc\0" \ + "update_kernel_filename=uImage\0" \ + "update_kernel=" \ + "setenv update_mmc_part 1 ; " \ + "setenv update_filename ${update_kernel_filename} ; " \ + "setenv update_offset 0x800 ; " \ + "run do_update_mmc ; " \ + "setenv update_filename ${dtbfile} ; " \ + "setenv update_offset 0x400 ; " \ + "run do_update_mmc\0" \ + "update_sfkernel=" \ + "setenv update_filename fitImage ; " \ + "setenv update_offset ${sf_kernel_offset} ; " \ + "run do_update_sf\0" \ + "update_swu=" \ + "setenv update_filename ${swufile} ; " \ + "setenv update_offset ${sf_swu_offset} ; " \ + "run do_update_sf\0" \ + "addcons=" \ + "setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off\0" \ + "addmisc=" \ + "setenv bootargs ${bootargs} ${miscargs}\0" \ + "addargs=run addcons addmisc\0" \ + "mmcload=" \ + "mmc rescan ; " \ + "mmc dev 0 1 ; " \ + "mmc read ${loadaddr} 0x800 0x2000 ; " \ + "mmc read ${dtbaddr} 0x400 0x80\0" \ + "netload=" \ + "dhcp ${loadaddr} ${hostname}/${bootfile} ; " \ + "tftp ${dtbaddr} ${hostname}/${dtbfile}\0" \ + "sfload=" \ + "sf probe ; " \ + "sf read ${loadaddr} ${sf_kernel_offset} ${sf_kernel_size}\0" \ + "usbload=" \ + "usb start ; " \ + "load usb 0:1 ${loadaddr} ${bootfile}\0" \ + "miscargs=panic=1\0" \ + "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ + "nfsargs=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ + "mmc_mmc=" \ + "if run mmcload mmcargs addargs ; then " \ + "bootm ${loadaddr} - ${dtbaddr} ; " \ + "fi\0" \ + "mmc_nfs=" \ + "if run mmcload nfsargs addip addargs ; then " \ + "bootm ${loadaddr} - ${dtbaddr} ; " \ + "fi\0" \ + "sf_mmc=" \ + "if run sfload mmcargs addargs ; then " \ + "bootm ${loadaddr} - ${dtbaddr} ; " \ + "fi\0" \ + "sf_swu=" \ + "if run sfload ; then " \ + "sf read ${rdaddr} ${sf_swu_offset} ${sf_swu_size} ; " \ + "setenv bootargs root=/dev/ram0 rw ; " \ + "run addargs ; " \ + "bootm ${loadaddr} ${rdaddr} ; " \ + "fi\0" \ + "net_mmc=" \ + "if run netload mmcargs addargs ; then " \ + "bootm ${loadaddr} - ${dtbaddr} ; " \ + "fi\0" \ + "net_nfs=" \ + "if run netload nfsargs addip addargs ; then " \ + "bootm ${loadaddr} - ${dtbaddr} ; " \ + "fi\0" \ + "prebootcmd=" \ + "if test \"${envsaved}\" != y ; then ; " \ + "setenv envsaved y ; " \ + "saveenv ; " \ + "fi ; " \ + "if test \"${bootmode}\" = normal ; then " \ + "setenv bootdelay 0 ; " \ + "setenv bootpri mmc_mmc ; " \ + "elif test \"${bootmode}\" = devel ; then " \ + "setenv bootdelay 3 ; " \ + "setenv bootpri net_mmc ; " \ + "else " \ + "if test \"${bootmode}\" != update ; then " \ + "echo Warning: unknown bootmode \"${bootmode}\" ; " \ + "fi ; " \ + "setenv bootdelay 1 ; " \ + "setenv bootpri sf_swu ; " \ + "fi\0" + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_XEA_H__ */ diff --git a/roms/u-boot/include/configs/xenguest_arm64.h b/roms/u-boot/include/configs/xenguest_arm64.h new file mode 100644 index 000000000..d76ce13d1 --- /dev/null +++ b/roms/u-boot/include/configs/xenguest_arm64.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * (C) Copyright 2020 EPAM Systemc Inc. + */ +#ifndef __XENGUEST_ARM64_H +#define __XENGUEST_ARM64_H + +#ifndef __ASSEMBLY__ +#include +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS + +#undef CONFIG_NR_DRAM_BANKS +#undef CONFIG_SYS_SDRAM_BASE + +#define CONFIG_NR_DRAM_BANKS 1 + +/* + * This can be any arbitrary address as we are using PIE, but + * please note, that CONFIG_SYS_TEXT_BASE must match the below. + */ +#define CONFIG_SYS_LOAD_ADDR 0x40000000 +#define CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE CONFIG_SYS_LOAD_ADDR + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_OF_SYSTEM_SETUP + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadimage=ext4load pvblock 0 0x90000000 /boot/Image;\0" \ + "pvblockboot=run loadimage;" \ + "booti 0x90000000 - 0x88000000;\0" + +#endif /* __XENGUEST_ARM64_H */ diff --git a/roms/u-boot/include/configs/xilinx_versal.h b/roms/u-boot/include/configs/xilinx_versal.h new file mode 100644 index 000000000..380f93a2f --- /dev/null +++ b/roms/u-boot/include/configs/xilinx_versal.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for Xilinx Versal + * (C) Copyright 2016 - 2018 Xilinx, Inc. + * Michal Simek + * + * Based on Configuration for Xilinx ZynqMP + */ + +#ifndef __XILINX_VERSAL_H +#define __XILINX_VERSAL_H + +#define CONFIG_REMAKE_ELF + +/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0xF9000000 +#define GICR_BASE 0xF9080000 + +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE + +/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ +#if CONFIG_COUNTER_FREQUENCY +# define COUNTER_FREQUENCY CONFIG_COUNTER_FREQUENCY +#endif + +/* Serial setup */ +#define CONFIG_CPU_ARMV8 + +#define CONFIG_SYS_BAUDRATE_TABLE \ + { 4800, 9600, 19200, 38400, 57600, 115200 } + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MAY_FAIL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR 0x8000000 + +/* Monitor Command Prompt */ +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_MAXARGS 64 + +#if defined(CONFIG_CMD_DFU) +#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000 +#define DFU_DEFAULT_POLL_TIMEOUT 300 +#define CONFIG_THOR_RESET_OFF +#endif + +/* Ethernet driver */ +#if defined(CONFIG_ZYNQ_GEM) +# define CONFIG_NET_MULTI +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define PHY_ANEG_TIMEOUT 20000 +#endif + +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +#define CONFIG_CLOCKS + +#define ENV_MEM_LAYOUT_SETTINGS \ + "fdt_addr_r=0x40000000\0" \ + "fdt_size_r=0x400000\0" \ + "pxefile_addr_r=0x10000000\0" \ + "kernel_addr_r=0x18000000\0" \ + "kernel_size_r=0x10000000\0" \ + "scriptaddr=0x20000000\0" \ + "ramdisk_addr_r=0x02100000\0" \ + "script_size_f=0x80000\0" + +#if defined(CONFIG_MMC_SDHCI_ZYNQ) +# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) +#else +# define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) +# define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) +#else +# define BOOT_TARGET_DEVICES_PXE(func) +#endif + +#if defined(CONFIG_CMD_DHCP) +# define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +# define BOOT_TARGET_DEVICES_DHCP(func) +#endif + +#if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL) +# define BOOT_TARGET_DEVICES_XSPI(func) func(XSPI, xspi, 0) +#else +# define BOOT_TARGET_DEVICES_XSPI(func) +#endif + +#define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \ + "bootcmd_xspi0=sf probe 0 0 0 && " \ + "sf read $scriptaddr $script_offset_f $script_size_f && " \ + "echo XSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \ + "xspi0 " + +#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) + +#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ + "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ + "jtag " + +#define BOOT_TARGET_DEVICES_USB_DFU(func) \ + func(USB_DFU, usb_dfu, 0) func(USB_DFU, usb_dfu, 1) + +#define BOOTENV_DEV_USB_DFU(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=setenv dfu_alt_info boot.scr ram " \ + "$scriptaddr $script_size_f && " \ + "dfu " #instance " ram " #instance " 60 && " \ + "echo DFU" #instance ": Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo DFU" #instance ": SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_USB_DFU(devtypeu, devtypel, instance) \ + "" + +#define BOOT_TARGET_DEVICES_USB_THOR(func) \ + func(USB_THOR, usb_thor, 0) func(USB_THOR, usb_thor, 1) + +#define BOOTENV_DEV_USB_THOR(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=setenv dfu_alt_info boot.scr ram " \ + "$scriptaddr $script_size_f && " \ + "thordown " #instance " ram " #instance " && " \ + "echo THOR" #instance ": Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo THOR" #instance ": SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_USB_THOR(devtypeu, devtypel, instance) \ + "" + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_JTAG(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_XSPI(func) \ + BOOT_TARGET_DEVICES_USB_DFU(func) \ + BOOT_TARGET_DEVICES_USB_THOR(func) \ + BOOT_TARGET_DEVICES_PXE(func) \ + BOOT_TARGET_DEVICES_DHCP(func) + +#include + +/* Initial environment variables */ +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV +#endif + +#endif /* __XILINX_VERSAL_H */ diff --git a/roms/u-boot/include/configs/xilinx_versal_mini.h b/roms/u-boot/include/configs/xilinx_versal_mini.h new file mode 100644 index 000000000..00c971881 --- /dev/null +++ b/roms/u-boot/include/configs/xilinx_versal_mini.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for Xilinx Versal MINI configuration + * + * (C) Copyright 2018-2019 Xilinx, Inc. + * Michal Simek + * Siva Durga Prasad Paladugu + */ + +#ifndef __CONFIG_VERSAL_MINI_H +#define __CONFIG_VERSAL_MINI_H + +#define CONFIG_EXTRA_ENV_SETTINGS + +#include + +/* Undef unneeded configs */ +#undef CONFIG_EXTRA_ENV_SETTINGS + +/* BOOTP options */ +#undef CONFIG_BOOTP_BOOTFILESIZE +#undef CONFIG_BOOTP_MAY_FAIL + +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 + +#endif /* __CONFIG_VERSAL_MINI_H */ diff --git a/roms/u-boot/include/configs/xilinx_versal_mini_qspi.h b/roms/u-boot/include/configs/xilinx_versal_mini_qspi.h new file mode 100644 index 000000000..8572b8b3d --- /dev/null +++ b/roms/u-boot/include/configs/xilinx_versal_mini_qspi.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for Xilinx Versal QSPI Flash utility + * + * (C) Copyright 2018-2019 Xilinx, Inc. + * Michal Simek + * Siva Durga Prasad Paladugu + */ + +#ifndef __CONFIG_VERSAL_MINI_QSPI_H +#define __CONFIG_VERSAL_MINI_QSPI_H + +#include + +#undef CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000) + +#endif /* __CONFIG_VERSAL_MINI_QSPI_H */ diff --git a/roms/u-boot/include/configs/xilinx_zynqmp.h b/roms/u-boot/include/configs/xilinx_zynqmp.h new file mode 100644 index 000000000..986af2be7 --- /dev/null +++ b/roms/u-boot/include/configs/xilinx_zynqmp.h @@ -0,0 +1,271 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for Xilinx ZynqMP + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek + * + * Based on Configuration for Versatile Express + */ + +#ifndef __XILINX_ZYNQMP_H +#define __XILINX_ZYNQMP_H + +#define CONFIG_REMAKE_ELF + +/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ + +/* Generic Interrupt Controller Definitions */ +#define CONFIG_GICV2 +#define GICD_BASE 0xF9010000 +#define GICC_BASE 0xF9020000 + +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE + +/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ +#if !defined(COUNTER_FREQUENCY) +# define COUNTER_FREQUENCY 100000000 +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x4000000) + +/* Serial setup */ +#define CONFIG_CPU_ARMV8 + +#define CONFIG_SYS_BAUDRATE_TABLE \ + { 4800, 9600, 19200, 38400, 57600, 115200 } + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MAY_FAIL + +#ifdef CONFIG_NAND_ARASAN +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_ONFI_DETECTION +#endif + +#if defined(CONFIG_SPL_BUILD) +#define CONFIG_ZYNQMP_PSU_INIT_ENABLED +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR 0x8000000 + +#if defined(CONFIG_ZYNQMP_USB) +#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000 +#define DFU_DEFAULT_POLL_TIMEOUT 300 +#define CONFIG_THOR_RESET_OFF + +#ifndef CONFIG_SPL_BUILD +# define PARTS_DEFAULT \ + "partitions=uuid_disk=${uuid_gpt_disk};" \ + "name=""boot"",size=16M,uuid=${uuid_gpt_boot};" \ + "name=""Linux"",size=-M,uuid=${uuid_gpt_Linux}\0" +#endif +#endif + +#if !defined(PARTS_DEFAULT) +# define PARTS_DEFAULT +#endif + +/* Monitor Command Prompt */ +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_MAXARGS 64 + +/* Ethernet driver */ +#if defined(CONFIG_ZYNQ_GEM) +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define PHY_ANEG_TIMEOUT 20000 +#endif + +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +#define CONFIG_CLOCKS + +#define ENV_MEM_LAYOUT_SETTINGS \ + "fdt_addr_r=0x40000000\0" \ + "fdt_size_r=0x400000\0" \ + "pxefile_addr_r=0x10000000\0" \ + "kernel_addr_r=0x18000000\0" \ + "kernel_size_r=0x10000000\0" \ + "scriptaddr=0x20000000\0" \ + "ramdisk_addr_r=0x02100000\0" \ + "script_size_f=0x80000\0" \ + +#if defined(CONFIG_MMC_SDHCI_ZYNQ) +# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) +#else +# define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#if defined(CONFIG_SATA_CEVA) +# define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) +#else +# define BOOT_TARGET_DEVICES_SCSI(func) +#endif + +#if defined(CONFIG_ZYNQMP_USB) +# define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1) +#else +# define BOOT_TARGET_DEVICES_USB(func) +#endif + +#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) +# define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) +#else +# define BOOT_TARGET_DEVICES_PXE(func) +#endif + +#if defined(CONFIG_CMD_DHCP) +# define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +# define BOOT_TARGET_DEVICES_DHCP(func) +#endif + +#if defined(CONFIG_ZYNQMP_GQSPI) +# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, 0) +#else +# define BOOT_TARGET_DEVICES_QSPI(func) +#endif + +#if defined(CONFIG_NAND_ARASAN) +# define BOOT_TARGET_DEVICES_NAND(func) func(NAND, nand, 0) +#else +# define BOOT_TARGET_DEVICES_NAND(func) +#endif + +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=sf probe " #instance " 0 0 && " \ + "sf read $scriptaddr $script_offset_f $script_size_f && " \ + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "= nand info && " \ + "nand read $scriptaddr $script_offset_f $script_size_f && " \ + "echo NAND: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo NAND: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) + +#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ + "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ + "jtag " + +#define BOOT_TARGET_DEVICES_USB_DFU(func) \ + func(USB_DFU, usb_dfu, 0) func(USB_DFU, usb_dfu, 1) + +#define BOOTENV_DEV_USB_DFU(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=setenv dfu_alt_info boot.scr ram " \ + "$scriptaddr $script_size_f && " \ + "dfu " #instance " ram " #instance " 60 && " \ + "echo DFU" #instance ": Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo DFU" #instance ": SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_USB_DFU(devtypeu, devtypel, instance) \ + "" + +#define BOOT_TARGET_DEVICES_USB_THOR(func) \ + func(USB_THOR, usb_thor, 0) func(USB_THOR, usb_thor, 1) + +#define BOOTENV_DEV_USB_THOR(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=setenv dfu_alt_info boot.scr ram " \ + "$scriptaddr $script_size_f && " \ + "thordown " #instance " ram " #instance " && " \ + "echo THOR" #instance ": Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo THOR" #instance ": SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_USB_THOR(devtypeu, devtypel, instance) \ + "" + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_JTAG(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_QSPI(func) \ + BOOT_TARGET_DEVICES_NAND(func) \ + BOOT_TARGET_DEVICES_USB_DFU(func) \ + BOOT_TARGET_DEVICES_USB_THOR(func) \ + BOOT_TARGET_DEVICES_USB(func) \ + BOOT_TARGET_DEVICES_SCSI(func) \ + BOOT_TARGET_DEVICES_PXE(func) \ + BOOT_TARGET_DEVICES_DHCP(func) + +#include + +/* Initial environment variables */ +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV +#endif + +/* SPL can't handle all huge variables - define just DFU */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU) +#undef CONFIG_EXTRA_ENV_SETTINGS +# define CONFIG_EXTRA_ENV_SETTINGS \ + "dfu_alt_info_ram=uboot.bin ram 0x8000000 0x1000000;" \ + "atf-uboot.ub ram 0x10000000 0x1000000;" \ + "Image ram 0x80000 0x3f80000;" \ + "system.dtb ram 0x4000000 0x100000\0" \ + "dfu_bufsiz=0x1000\0" +#endif + +#define CONFIG_SPL_STACK 0xfffffffc +#define CONFIG_SPL_MAX_SIZE 0x40000 + +/* Just random location in OCM */ +#define CONFIG_SPL_BSS_START_ADDR 0x0 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) +# define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000 +# define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000 +# define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000 +#endif + +/* u-boot is like dtb */ +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "u-boot.bin" +#define CONFIG_SYS_SPL_ARGS_ADDR 0x8000000 + +/* ATF is my kernel image */ +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "atf-uboot.ub" + +/* MMC support */ +#ifdef CONFIG_MMC_SDHCI_ZYNQ +# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */ +# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* unused */ +# define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* unused */ +# if defined(CONFIG_SPL_LOAD_FIT) +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" +# else +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +# endif +#endif + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU) +# define CONFIG_SPL_ENV_SUPPORT +# define CONFIG_SPL_HASH_SUPPORT +# define CONFIG_ENV_MAX_ENTRIES 10 +#endif + +#define CONFIG_SYS_SPL_MALLOC_START 0x20000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE +# error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used" +#endif + +#endif /* __XILINX_ZYNQMP_H */ diff --git a/roms/u-boot/include/configs/xilinx_zynqmp_mini.h b/roms/u-boot/include/configs/xilinx_zynqmp_mini.h new file mode 100644 index 000000000..ef9c768e4 --- /dev/null +++ b/roms/u-boot/include/configs/xilinx_zynqmp_mini.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for Xilinx ZynqMP Flash utility + * + * (C) Copyright 2018 Xilinx, Inc. + * Michal Simek + * Siva Durga Prasad Paladugu + */ + +#ifndef __CONFIG_ZYNQMP_MINI_H +#define __CONFIG_ZYNQMP_MINI_H + +#define CONFIG_EXTRA_ENV_SETTINGS + +#include + +/* Undef unneeded configs */ +#undef CONFIG_BOOTCOMMAND +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_INIT_SP_ADDR + +/* BOOTP options */ +#undef CONFIG_BOOTP_BOOTFILESIZE +#undef CONFIG_BOOTP_MAY_FAIL +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 + +#endif /* __CONFIG_ZYNQMP_MINI_H */ diff --git a/roms/u-boot/include/configs/xilinx_zynqmp_mini_emmc.h b/roms/u-boot/include/configs/xilinx_zynqmp_mini_emmc.h new file mode 100644 index 000000000..a7ae30d4d --- /dev/null +++ b/roms/u-boot/include/configs/xilinx_zynqmp_mini_emmc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for Xilinx ZynqMP eMMC Flash utility + * + * (C) Copyright 2018 Xilinx, Inc. + * Michal Simek + * Siva Durga Prasad Paladugu + */ + +#ifndef __CONFIG_ZYNQMP_MINI_EMMC_H +#define __CONFIG_ZYNQMP_MINI_EMMC_H + +#include + +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MALLOC_LEN 0x800000 + +#endif /* __CONFIG_ZYNQMP_MINI_EMMC_H */ diff --git a/roms/u-boot/include/configs/xilinx_zynqmp_mini_nand.h b/roms/u-boot/include/configs/xilinx_zynqmp_mini_nand.h new file mode 100644 index 000000000..692f6e5d1 --- /dev/null +++ b/roms/u-boot/include/configs/xilinx_zynqmp_mini_nand.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for Xilinx ZynqMP Nand Flash utility + * + * (C) Copyright 2018 Xilinx, Inc. + * Michal Simek + * Siva Durga Prasad Paladugu + */ + +#ifndef __CONFIG_ZYNQMP_MINI_NAND_H +#define __CONFIG_ZYNQMP_MINI_NAND_H + +#include + +#define CONFIG_SYS_SDRAM_SIZE 0x1000000 +#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000) +#define CONFIG_SYS_MALLOC_LEN 0x800000 + +#endif /* __CONFIG_ZYNQMP_MINI_NAND_H */ diff --git a/roms/u-boot/include/configs/xilinx_zynqmp_mini_qspi.h b/roms/u-boot/include/configs/xilinx_zynqmp_mini_qspi.h new file mode 100644 index 000000000..205ddb4ae --- /dev/null +++ b/roms/u-boot/include/configs/xilinx_zynqmp_mini_qspi.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for Xilinx ZynqMP QSPI Flash utility + * + * (C) Copyright 2018 Xilinx, Inc. + * Michal Simek + * Siva Durga Prasad Paladugu + */ + +#ifndef __CONFIG_ZYNQMP_MINI_QSPI_H +#define __CONFIG_ZYNQMP_MINI_QSPI_H + +#include + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000) +#define CONFIG_SYS_MALLOC_LEN 0x1a00 + +#endif /* __CONFIG_ZYNQMP_MINI_QSPI_H */ diff --git a/roms/u-boot/include/configs/xilinx_zynqmp_r5.h b/roms/u-boot/include/configs/xilinx_zynqmp_r5.h new file mode 100644 index 000000000..c0cd72e56 --- /dev/null +++ b/roms/u-boot/include/configs/xilinx_zynqmp_r5.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2018 Xilinx, Inc. (Michal Simek) + */ + +#ifndef __CONFIG_ZYNQMP_R5_H +#define __CONFIG_ZYNQMP_R5_H + +#define CONFIG_EXTRA_ENV_SETTINGS + +/* CPU clock */ +#define CONFIG_CPU_FREQ_HZ 500000000 + +/* Serial drivers */ +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/* Boot configuration */ +#define CONFIG_SYS_LOAD_ADDR 0 /* default? */ + +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ + +#define CONFIG_SYS_MALLOC_LEN 0x1400000 + +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* Extend size of kernel image for uncompression */ +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */ diff --git a/roms/u-boot/include/configs/xpedite517x.h b/roms/u-boot/include/configs/xpedite517x.h new file mode 100644 index 000000000..d3bb92964 --- /dev/null +++ b/roms/u-boot/include/configs/xpedite517x.h @@ -0,0 +1,646 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2009 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + */ + +/* + * xpedite517x board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_SYS_BOARD_NAME "XPedite5170" +#define CONFIG_SYS_FORM_3U_VPX 1 +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ +#define CONFIG_BAT_RW 1 /* Use common BAT rw code */ +#define CONFIG_ALTIVEC 1 + +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCIE1 1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 1 /* PCIE controller 2 */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ + +/* + * DDR config + */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ +#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ +#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ + +/* + * virtual address to be used for temporary mappings. There + * should be 128k free at this VA. + */ +#define CONFIG_SYS_SCRATCH_VA 0xe0000000 + +#ifndef __ASSEMBLY__ +#include +extern unsigned long get_board_sys_clk(unsigned long dummy); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */ + +/* + * L2CR setup + */ +#define CONFIG_SYS_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2CR_L2E) + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR + +/* + * Diagnostics + */ +#define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\ + CONFIG_SYS_POST_I2C) +/* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */ +#define I2C_ADDR_IGNORE_LIST {0x50} + +/* + * Memory map + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable + * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable + * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable + * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable + * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable + * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable + * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable + * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable + * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable + */ + +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) + +/* + * NAND flash configuration + */ +#define CONFIG_SYS_NAND_BASE 0xef800000 +#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2} +#define CONFIG_SYS_MAX_NAND_DEVICE 2 +#define CONFIG_NAND_ACTL +#define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */ +#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */ +#define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */ +#define CONFIG_SYS_NAND_ACTL_DELAY 25 +#define CONFIG_JFFS2_NAND + +/* + * NOR flash configuration + */ +#define CONFIG_SYS_FLASH_BASE 0xf8000000 +#define CONFIG_SYS_FLASH_BASE2 0xf0000000 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \ + {0xf7f00000, 0xc0000} } +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ + +/* + * Chip select configuration + */ +/* NOR Flash 0 on CS0 */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ + BR_PS_16 |\ + BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\ + OR_GPCM_CSNT |\ + OR_GPCM_XACS |\ + OR_GPCM_ACS_DIV2 |\ + OR_GPCM_SCY_8 |\ + OR_GPCM_TRLX |\ + OR_GPCM_EHTR |\ + OR_GPCM_EAD) + +/* NOR Flash 1 on CS1 */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\ + BR_PS_16 |\ + BR_V) +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM + +/* NAND flash on CS2 */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\ + BR_PS_8 |\ + BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\ + OR_GPCM_BCTLD |\ + OR_GPCM_CSNT |\ + OR_GPCM_ACS_DIV4 |\ + OR_GPCM_SCY_4 |\ + OR_GPCM_TRLX |\ + OR_GPCM_EHTR) + +/* Optional NAND flash on CS3 */ +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\ + BR_PS_8 |\ + BR_V) +#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM + +/* + * Use L1 as initial stack + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 100000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 + +/* PEX8518 slave I2C interface */ +#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 + +/* I2C DS1631 temperature sensor */ +#define CONFIG_SYS_I2C_LM90_ADDR 0x4c + +/* I2C EEPROM - AT24C128B */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 + +/* GPIO */ +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 +#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c +#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e +#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f +#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 +#define CONFIG_SYS_I2C_PCA9553_ADDR 0x62 + +/* + * PU = pulled high, PD = pulled low + * I = input, O = output, IO = input/output + */ +/* PCA9557 @ 0x18*/ +#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ +#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ +#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ +#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ +#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ +#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ + +/* PCA9557 @ 0x1c*/ +#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ +#define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */ +#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ +#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ +#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ +#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ +#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ +#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ + +/* PCA9557 @ 0x1e*/ +#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */ +#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */ + +/* PCA9557 @ 0x1f */ +#define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */ +#define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */ +#define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */ +#define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* PCIE1 - PEX8518 */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ + +/* PCIE2 - VPX P1 */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ + +/* + * Networking options + */ +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define CONFIG_HAS_ETH0 + +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_PHY_ADDR 2 +#define TSEC2_PHYIDX 0 +#define CONFIG_HAS_ETH1 + +/* + * BAT mappings + */ +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) +#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\ + BATU_BL_1M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU +#endif + +/* + * BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR + */ +#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U + +/* + * BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 1G PCI-Express 1 Memory + */ +#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\ + BATU_BL_1G |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U + +/* + * BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M PCI-Express 2 Memory + */ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\ + BATU_BL_512M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U + +/* + * BAT3 1M Cache-inhibited, guarded + * 0xe000_0000 1M CCSR + */ +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\ + BATU_BL_1M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U + +/* + * BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 + */ +#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\ + BATU_BL_32M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U + +/* + * BAT5 128K Cacheable, non-guarded + * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory) + */ +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\ + BATL_PP_RW |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\ + BATU_BL_128K |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L +#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U + +/* + * BAT6 256M Cache-inhibited, guarded + * 0xf000_0000 256M FLASH + */ +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\ + BATU_BL_256M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\ + BATL_PP_RW |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U + +/* Map the last 1M of flash where we're running from reset */ +#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\ + BATU_BL_1M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ + BATL_PP_RW |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY + +/* + * BAT7 64M Cache-inhibited, guarded + * 0xe800_0000 64K NAND FLASH + * 0xe804_0000 128K DUART Registers + */ +#define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\ + BATU_BL_512K |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ +#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ + +/* + * Environment Configuration + */ + +/* + * Flash memory map: + * fffc0000 - ffffffff Pri FDT (256KB) + * fff80000 - fffbffff Pri U-Boot Environment (256 KB) + * fff00000 - fff7ffff Pri U-Boot (512 KB) + * fef00000 - ffefffff Pri OS image (16MB) + * f8000000 - feefffff Pri OS Use/Filesystem (111MB) + * + * f7fc0000 - f7ffffff Sec FDT (256KB) + * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB) + * f7f00000 - f7f7ffff Sec U-Boot (512 KB) + * f6f00000 - f7efffff Sec OS image (16MB) + * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) + */ +#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000) +#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000) +#define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000) +#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000) +#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) +#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) + +#define CONFIG_PROG_UBOOT1 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_UBOOT2 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_BOOT_OS_NET \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "if test -n $fdtaddr; then " \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "bootm $osaddr - $fdtaddr; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi; " \ + "else; " \ + "bootm $osaddr; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS1 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS2 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT1 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT2 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=yes\0" \ + "download_cmd=tftp\0" \ + "console_args=console=ttyS0,115200\0" \ + "root_args=root=/dev/nfs rw\0" \ + "misc_args=ip=on\0" \ + "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ + "bootfile=/home/user/file\0" \ + "osfile=/home/user/board.uImage\0" \ + "fdtfile=/home/user/board.dtb\0" \ + "ubootfile=/home/user/u-boot.bin\0" \ + "fdtaddr=0x1e00000\0" \ + "osaddr=0x1000000\0" \ + "loadaddr=0x1000000\0" \ + "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ + "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ + "prog_os1="CONFIG_PROG_OS1"\0" \ + "prog_os2="CONFIG_PROG_OS2"\0" \ + "prog_fdt1="CONFIG_PROG_FDT1"\0" \ + "prog_fdt2="CONFIG_PROG_FDT2"\0" \ + "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ + "bootcmd_flash1=run set_bootargs; " \ + "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ + "bootcmd_flash2=run set_bootargs; " \ + "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ + "bootcmd=run bootcmd_flash1\0" +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/xpedite520x.h b/roms/u-boot/include/configs/xpedite520x.h new file mode 100644 index 000000000..c9bd36902 --- /dev/null +++ b/roms/u-boot/include/configs/xpedite520x.h @@ -0,0 +1,445 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2004-2008 Freescale Semiconductor, Inc. + */ + +/* + * xpedite520x board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_SYS_BOARD_NAME "XPedite5200" +#define CONFIG_SYS_FORM_PMC_XMC 1 + +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCI1 1 /* PCI controller 1 */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ + +/* + * DDR config + */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS 0x54 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +#define CONFIG_SYS_CLK_FREQ 66666666 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CONFIG_SYS_CCSRBAR 0xef000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* + * Diagnostics + */ +#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ + CONFIG_SYS_POST_I2C) +#define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \ + CONFIG_SYS_I2C_EEPROM_ADDR, \ + CONFIG_SYS_I2C_PCA953X_ADDR0, \ + CONFIG_SYS_I2C_PCA953X_ADDR1, \ + CONFIG_SYS_I2C_RTC_ADDR} + +/* + * Memory map + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable + * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable + * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable + * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable + * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable + * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable + * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable + */ + +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) + +/* + * NAND flash configuration + */ +#define CONFIG_SYS_NAND_BASE 0xef800000 +#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_NAND_ACTL +#define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */ +#define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */ +#define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */ +#define CONFIG_SYS_NAND_ACTL_DELAY 25 + +/* + * NOR flash configuration + */ +#define CONFIG_SYS_FLASH_BASE 0xfc000000 +#define CONFIG_SYS_FLASH_BASE2 0xf8000000 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ + {0xfbf40000, 0xc0000} } +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +/* + * Chip select configuration + */ +/* NOR Flash 0 on CS0 */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | \ + BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_8) + +/* NOR Flash 1 on CS1 */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ + BR_PS_16 | \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM + +/* NAND flash on CS2 */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ + BR_PS_8 | \ + BR_V) + +/* NAND flash on CS2 */ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ + OR_GPCM_BCTLD | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_4 | \ + OR_GPCM_TRLX | \ + OR_GPCM_EHTR) + +/* NAND flash on CS3 */ +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ + BR_PS_8 | \ + BR_V) +#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM + +/* + * Use L1 as initial stack + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 + +/* I2C EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 + +/* GPIO */ +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 +#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19 +#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 + +/* PCA957 @ 0x18 */ +#define CONFIG_SYS_PCA953X_BRD_CFG0 0x01 +#define CONFIG_SYS_PCA953X_BRD_CFG1 0x02 +#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04 +#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08 +#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10 +#define CONFIG_SYS_PCA953X_NVM_WP 0x20 +#define CONFIG_SYS_PCA953X_MONARCH 0x40 +#define CONFIG_SYS_PCA953X_EREADY 0x80 + +/* PCA957 @ 0x19 */ +#define CONFIG_SYS_PCA953X_P14_IO0 0x01 +#define CONFIG_SYS_PCA953X_P14_IO1 0x02 +#define CONFIG_SYS_PCA953X_P14_IO2 0x04 +#define CONFIG_SYS_PCA953X_P14_IO3 0x08 +#define CONFIG_SYS_PCA953X_P14_IO4 0x10 +#define CONFIG_SYS_PCA953X_P14_IO5 0x20 +#define CONFIG_SYS_PCA953X_P14_IO6 0x40 +#define CONFIG_SYS_PCA953X_P14_IO7 0x80 + +/* 12-bit ADC used to measure CPU diode */ +#define CONFIG_SYS_I2C_MAX1237_ADDR 0x34 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */ +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */ + +/* + * Networking options + */ +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define CONFIG_HAS_ETH0 + +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC2_PHY_ADDR 2 +#define TSEC2_PHYIDX 0 +#define CONFIG_HAS_ETH1 + +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" +#define TSEC3_FLAGS TSEC_GIGABIT +#define TSEC3_PHY_ADDR 3 +#define TSEC3_PHYIDX 0 +#define CONFIG_HAS_ETH2 + +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "eTSEC4" +#define TSEC4_FLAGS TSEC_GIGABIT +#define TSEC4_PHY_ADDR 4 +#define TSEC4_PHYIDX 0 +#define CONFIG_HAS_ETH3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ +#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ + +/* + * Environment Configuration + */ + +/* + * Flash memory map: + * fff80000 - ffffffff Pri U-Boot (512 KB) + * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) + * fff00000 - fff3ffff Pri FDT (256KB) + * fef00000 - ffefffff Pri OS image (16MB) + * fc000000 - feefffff Pri OS Use/Filesystem (47MB) + * + * fbf80000 - fbffffff Sec U-Boot (512 KB) + * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB) + * fbf00000 - fbf3ffff Sec FDT (256KB) + * faf00000 - fbefffff Sec OS image (16MB) + * f8000000 - faefffff Sec OS Use/Filesystem (47MB) + */ +#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) +#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000) +#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) +#define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000) +#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) +#define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000) + +#define CONFIG_PROG_UBOOT1 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_UBOOT2 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_BOOT_OS_NET \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "if test -n $fdtaddr; then " \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "bootm $osaddr - $fdtaddr; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi; " \ + "else; " \ + "bootm $osaddr; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS1 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS2 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT1 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT2 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=yes\0" \ + "download_cmd=tftp\0" \ + "console_args=console=ttyS0,115200\0" \ + "root_args=root=/dev/nfs rw\0" \ + "misc_args=ip=on\0" \ + "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ + "bootfile=/home/user/file\0" \ + "osfile=/home/user/board.uImage\0" \ + "fdtfile=/home/user/board.dtb\0" \ + "ubootfile=/home/user/u-boot.bin\0" \ + "fdtaddr=0x1e00000\0" \ + "osaddr=0x1000000\0" \ + "loadaddr=0x1000000\0" \ + "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ + "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ + "prog_os1="CONFIG_PROG_OS1"\0" \ + "prog_os2="CONFIG_PROG_OS2"\0" \ + "prog_fdt1="CONFIG_PROG_FDT1"\0" \ + "prog_fdt2="CONFIG_PROG_FDT2"\0" \ + "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ + "bootcmd_flash1=run set_bootargs; " \ + "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ + "bootcmd_flash2=run set_bootargs; " \ + "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ + "bootcmd=run bootcmd_flash1\0" +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/xpedite537x.h b/roms/u-boot/include/configs/xpedite537x.h new file mode 100644 index 000000000..7262c8690 --- /dev/null +++ b/roms/u-boot/include/configs/xpedite537x.h @@ -0,0 +1,496 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + */ + +/* + * xpedite537x board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_SYS_BOARD_NAME "XPedite5370" +#define CONFIG_SYS_FORM_3U_VPX 1 + +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCIE1 1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 1 /* PCIE controller 2 */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ + +/* + * Multicore config + */ +#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ +#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ + +/* + * DDR config + */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ +#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ +#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +#ifndef __ASSEMBLY__ +#include +extern unsigned long get_board_sys_clk(unsigned long dummy); +extern unsigned long get_board_ddr_clk(unsigned long dummy); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CONFIG_SYS_CCSRBAR 0xef000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* + * Diagnostics + */ +#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ + CONFIG_SYS_POST_I2C) +/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */ +#define I2C_ADDR_IGNORE_LIST {0x50} + +/* + * Memory map + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable + * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable + * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable + * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable + * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable + * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable + * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable + * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable + * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable + * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable + */ + +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) + +/* + * NAND flash configuration + */ +#define CONFIG_SYS_NAND_BASE 0xef800000 +#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ + CONFIG_SYS_NAND_BASE2} +#define CONFIG_SYS_MAX_NAND_DEVICE 2 +#define CONFIG_NAND_FSL_ELBC + +/* + * NOR flash configuration + */ +#define CONFIG_SYS_FLASH_BASE 0xf8000000 +#define CONFIG_SYS_FLASH_BASE2 0xf0000000 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ + {0xf7f40000, 0xc0000} } +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +/* + * Chip select configuration + */ +/* NOR Flash 0 on CS0 */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | \ + BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ + OR_GPCM_CSNT | \ + OR_GPCM_XACS | \ + OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_8 | \ + OR_GPCM_TRLX | \ + OR_GPCM_EHTR | \ + OR_GPCM_EAD) + +/* NOR Flash 1 on CS1 */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ + BR_PS_16 | \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM + +/* NAND flash on CS2 */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ + (2< +extern unsigned long get_board_sys_clk(unsigned long dummy); +extern unsigned long get_board_ddr_clk(unsigned long dummy); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CONFIG_SYS_CCSRBAR 0xef000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* + * Diagnostics + */ +#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ + CONFIG_SYS_POST_I2C) +#define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \ + CONFIG_SYS_I2C_LM75_ADDR, \ + CONFIG_SYS_I2C_LM90_ADDR, \ + CONFIG_SYS_I2C_PCA953X_ADDR0, \ + CONFIG_SYS_I2C_PCA953X_ADDR2, \ + CONFIG_SYS_I2C_PCA953X_ADDR3, \ + CONFIG_SYS_I2C_RTC_ADDR} + +/* + * Memory map + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable + * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable + * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable + * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable + * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable + * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable + * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable + * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable + */ + +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) + +/* + * NAND flash configuration + */ +#define CONFIG_SYS_NAND_BASE 0xef800000 +#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ + CONFIG_SYS_NAND_BASE2} +#define CONFIG_SYS_MAX_NAND_DEVICE 2 +#define CONFIG_NAND_FSL_ELBC + +/* + * NOR flash configuration + */ +#define CONFIG_SYS_FLASH_BASE 0xf8000000 +#define CONFIG_SYS_FLASH_BASE2 0xf0000000 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ + {0xf7f40000, 0xc0000} } +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +/* + * Chip select configuration + */ +/* NOR Flash 0 on CS0 */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | \ + BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ + OR_GPCM_CSNT | \ + OR_GPCM_XACS | \ + OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_8 | \ + OR_GPCM_TRLX | \ + OR_GPCM_EHTR | \ + OR_GPCM_EAD) + +/* NOR Flash 1 on CS1 */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ + BR_PS_16 | \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM + +/* NAND flash on CS2 */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ + (2< + * + * Configuration settings for the CCV xPress board + */ +#ifndef __XPRESS_CONFIG_H +#define __XPRESS_CONFIG_H + +#include "mx6_common.h" +#include + +/* SPL options */ +#include "imx6_spl.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 << 20) + +#define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* I2C configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE (128 << 20) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment is in stored in the eMMC boot partition */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC2 */ + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_ENET_DEV 0 +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_UBOOT_SECTOR_START 0x2 +#define CONFIG_UBOOT_SECTOR_COUNT 0x3fe + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc6\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=undefined\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "uboot=ccv/u-boot.imx\0" \ + "uboot_start="__stringify(CONFIG_UBOOT_SECTOR_START)"\0" \ + "uboot_size="__stringify(CONFIG_UBOOT_SECTOR_COUNT)"\0" \ + "update_uboot=if tftp ${uboot}; then " \ + "if itest ${filesize} > 0; then " \ + "mmc dev 0 1;" \ + "setexpr blkc ${filesize} / 0x200;" \ + "setexpr blkc ${blkc} + 1;" \ + "if itest ${blkc} <= ${uboot_size}; then " \ + "mmc write ${loadaddr} ${uboot_start} " \ + "${blkc};" \ + "fi;" \ + "fi; fi;" \ + "setenv filesize; setenv blkc\0" \ + "update_bootpart=mmc bootbus 0 2 1 2;mmc partconf 0 1 1 0\0" + +#endif /* __XPRESS_CONFIG_H */ diff --git a/roms/u-boot/include/configs/xtfpga.h b/roms/u-boot/include/configs/xtfpga.h new file mode 100644 index 000000000..516a6089f --- /dev/null +++ b/roms/u-boot/include/configs/xtfpga.h @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2007-2013 Tensilica, Inc. + * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include +#include + +/* + * The 'xtfpga' board describes a set of very similar boards with only minimal + * differences. + */ + +/*=====================*/ +/* Board and Processor */ +/*=====================*/ + +#define CONFIG_XTFPGA + +/* FPGA CPU freq after init */ +#define CONFIG_SYS_CLK_FREQ (gd->cpu_clk) + +/*===================*/ +/* RAM Layout */ +/*===================*/ + +#if XCHAL_HAVE_PTP_MMU +#define CONFIG_SYS_MEMORY_BASE \ + (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) +#define CONFIG_SYS_IO_BASE 0xf0000000 +#else +#define CONFIG_SYS_MEMORY_BASE 0x60000000 +#define CONFIG_SYS_IO_BASE 0x90000000 +#define CONFIG_MAX_MEM_MAPPED 0x10000000 +#endif + +/* Onboard RAM sizes: + * + * LX60 0x04000000 64 MB + * LX110 0x03000000 48 MB + * LX200 0x06000000 96 MB + * ML605 0x18000000 384 MB + * KC705 0x38000000 896 MB + * + * noMMU configurations can only see first 256MB of onboard memory. + */ + +#if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000 +#define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE +#else +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#endif + +#define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000) + +/* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ +#ifdef CONFIG_XTFPGA_LX60 +# define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */ +#else +# define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ +#endif + +#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */ + +/* Linux boot param area in RAM (used only when booting linux) */ +#define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) + +/* Memory test is destructive so default must not overlap vectors or U-Boot*/ + +/* Load address for stand-alone applications. + * MEMADDR cannot be used here, because the definition needs to be + * a plain number as it's used as -Ttext argument for ld in standalone + * example makefile. + * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually. + */ +#if XCHAL_HAVE_PTP_MMU +#if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR +#define CONFIG_STANDALONE_LOAD_ADDR 0x00800000 +#else +#define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000 +#endif +#else +#define CONFIG_STANDALONE_LOAD_ADDR 0x60800000 +#endif + +#if defined(CONFIG_MAX_MEM_MAPPED) && \ + CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE +#define CONFIG_SYS_MEMORY_SIZE CONFIG_MAX_MEM_MAPPED +#else +#define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE +#endif + +#define XTENSA_SYS_TEXT_ADDR \ + (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN) + +/* Used by tftpboot; env var 'loadaddr' */ +#define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000) + +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ + +#define CONFIG_BOARD_POSTCLK_INIT + +#define CONFIG_BOOTFILE "uImage" + /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 + /* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/*==============================*/ +/* U-Boot autoboot configuration */ +/*==============================*/ + + +/*=========================================*/ +/* FPGA Registers (board info and control) */ +/*=========================================*/ + +/* + * These assume FPGA bitstreams from Tensilica release RB and up. Earlier + * releases may not provide any/all of these registers or at these offsets. + * Some of the FPGA registers are broken down into bitfields described by + * SHIFT left amount and field WIDTH (bits), and also by a bitMASK. + */ + +/* Date of FPGA bitstream build in binary coded decimal (BCD) */ +#define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000) +#define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */ +#define FPGAREG_MTH_WIDTH 8 +#define FPGAREG_MTH_MASK 0xFF000000 +#define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */ +#define FPGAREG_DAY_WIDTH 8 +#define FPGAREG_DAY_MASK 0x00FF0000 +#define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/ +#define FPGAREG_YEAR_WIDTH 16 +#define FPGAREG_YEAR_MASK 0x0000FFFF + +/* FPGA core clock frequency in Hz (also input to UART) */ +#define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ + +/* + * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): + * Bits 0..5 set the lower 6 bits of the default ethernet MAC. + * Bit 6 is reserved for future use by Tensilica. + * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to + * the base of flash * (when on/1) or to the base of RAM (when off/0). + */ +#define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) +#define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ +#define FPGAREG_MAC_WIDTH 6 +#define FPGAREG_MAC_MASK 0x3f +#define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */ +#define FPGAREG_BOOT_WIDTH 1 +#define FPGAREG_BOOT_MASK 0x80 +#define FPGAREG_BOOT_RAM 0 +#define FPGAREG_BOOT_FLASH (1< + * + * Configuation settings for the zmx25 board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_TIMER_RATE 32768 +#define CONFIG_SYS_TIMER_COUNTER \ + (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) + +#define CONFIG_MACH_TYPE MACH_TYPE_ZMX25 +/* + * Environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "gs_fast_boot=setenv bootdelay 5\0" \ + "gs_slow_boot=setenv bootdelay 10\0" \ + "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \ + "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \ + "bootm 0x81000000; bootelf 0x81000000\0" + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Hardware drivers + */ + +/* + * Serial + */ +#define CONFIG_MXC_UART_BASE UART2_BASE + +/* + * Ethernet + */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0x00 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI_MXC +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL +#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN) +#define CONFIG_EHCI_IS_TDI +#endif /* CONFIG_CMD_USB */ + +/* SDRAM */ +#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */ +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */ + +/* + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE 0xA0000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +/* + * CFI FLASH driver setup + */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000) + +#endif /* __CONFIG_H */ diff --git a/roms/u-boot/include/configs/zynq-common.h b/roms/u-boot/include/configs/zynq-common.h new file mode 100644 index 000000000..39035f8be --- /dev/null +++ b/roms/u-boot/include/configs/zynq-common.h @@ -0,0 +1,272 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 Michal Simek + * (C) Copyright 2013 - 2018 Xilinx, Inc. + * + * Common configuration options for all Zynq boards. + */ + +#ifndef __CONFIG_ZYNQ_COMMON_H +#define __CONFIG_ZYNQ_COMMON_H + +/* CPU clock */ +#ifndef CONFIG_CPU_FREQ_HZ +# define CONFIG_CPU_FREQ_HZ 800000000 +#endif + +#define CONFIG_REMAKE_ELF + +/* Cache options */ +#define CONFIG_SYS_L2CACHE_OFF +#ifndef CONFIG_SYS_L2CACHE_OFF +# define CONFIG_SYS_L2_PL310 +# define CONFIG_SYS_PL310_BASE 0xf8f02000 +#endif + +#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600 +#define CONFIG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) + +/* Serial drivers */ +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/* Ethernet driver */ +#if defined(CONFIG_ZYNQ_GEM) +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_BOOTP_MAY_FAIL +#endif + +/* NOR */ +#ifdef CONFIG_MTD_NOR_FLASH +# define CONFIG_SYS_MAX_FLASH_BANKS 1 +# define CONFIG_SYS_MAX_FLASH_SECT 512 +# define CONFIG_SYS_FLASH_ERASE_TOUT 1000 +# define CONFIG_SYS_FLASH_WRITE_TOUT 5000 +# define CONFIG_FLASH_SHOW_PROGRESS 10 +# undef CONFIG_SYS_FLASH_EMPTY_INFO +# define CONFIG_SYS_FLASH_QUIET_TEST +#endif + +#ifdef CONFIG_NAND_ZYNQ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif + +#ifdef CONFIG_USB_EHCI_ZYNQ +# define CONFIG_EHCI_IS_TDI + +# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000 +# define DFU_DEFAULT_POLL_TIMEOUT 300 +# define CONFIG_THOR_RESET_OFF +#endif + +/* enable preboot to be loaded before CONFIG_BOOTDELAY */ + +/* Boot configuration */ +#define CONFIG_SYS_LOAD_ADDR 0 /* default? */ + +#ifdef CONFIG_SPL_BUILD +#define BOOTENV +#else + +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#ifdef CONFIG_CMD_USB +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + +#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) +#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) +#else +#define BOOT_TARGET_DEVICES_PXE(func) +#endif + +#if defined(CONFIG_CMD_DHCP) +#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +#define BOOT_TARGET_DEVICES_DHCP(func) +#endif + +#if defined(CONFIG_ZYNQ_QSPI) +# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) +#else +# define BOOT_TARGET_DEVICES_QSPI(func) +#endif + +#if defined(CONFIG_NAND_ZYNQ) +# define BOOT_TARGET_DEVICES_NAND(func) func(NAND, nand, na) +#else +# define BOOT_TARGET_DEVICES_NAND(func) +#endif + +#if defined(CONFIG_MTD_NOR_FLASH) +# define BOOT_TARGET_DEVICES_NOR(func) func(NOR, nor, na) +#else +# define BOOT_TARGET_DEVICES_NOR(func) +#endif + +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_qspi=sf probe 0 0 0 && " \ + "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + "qspi " + +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_nand=nand info && " \ + "nand read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ + "echo NAND: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo NAND: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + "nand " + +#define BOOTENV_DEV_NOR(devtypeu, devtypel, instance) \ + "script_offset_nor=0xE2FC0000\0" \ + "bootcmd_nor=cp.b ${script_offset_nor} ${scriptaddr} ${script_size_f} && " \ + "echo NOR: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo NOR: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_NOR(devtypeu, devtypel, instance) \ + "nor " + +#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) + +#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ + "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ + "jtag " + +#define BOOT_TARGET_DEVICES_USB_DFU(func) \ + func(USB_DFU, usb_dfu, 0) func(USB_DFU, usb_dfu, 1) + +#define BOOTENV_DEV_USB_DFU(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=setenv dfu_alt_info boot.scr ram " \ + "$scriptaddr $script_size_f && " \ + "dfu " #instance " ram " #instance " 60 && " \ + "echo DFU" #instance ": Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo DFU" #instance ": SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_USB_DFU(devtypeu, devtypel, instance) \ + "" + +#define BOOT_TARGET_DEVICES_USB_THOR(func) \ + func(USB_THOR, usb_thor, 0) func(USB_THOR, usb_thor, 1) + +#define BOOTENV_DEV_USB_THOR(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=setenv dfu_alt_info boot.scr ram " \ + "$scriptaddr $script_size_f && " \ + "thordown " #instance " ram " #instance " && " \ + "echo THOR" #instance ": Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo THOR" #instance ": SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_USB_THOR(devtypeu, devtypel, instance) \ + "" + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_JTAG(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_QSPI(func) \ + BOOT_TARGET_DEVICES_NAND(func) \ + BOOT_TARGET_DEVICES_NOR(func) \ + BOOT_TARGET_DEVICES_USB_DFU(func) \ + BOOT_TARGET_DEVICES_USB_THOR(func) \ + BOOT_TARGET_DEVICES_USB(func) \ + BOOT_TARGET_DEVICES_PXE(func) \ + BOOT_TARGET_DEVICES_DHCP(func) + +#include +#endif /* CONFIG_SPL_BUILD */ + +/* Default environment */ +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "scriptaddr=0x20000\0" \ + "script_size_f=0x40000\0" \ + "fdt_addr_r=0x1f00000\0" \ + "pxefile_addr_r=0x2000000\0" \ + "kernel_addr_r=0x2000000\0" \ + "scriptaddr=0x3000000\0" \ + "ramdisk_addr_r=0x3100000\0" \ + BOOTENV +#endif + +/* Miscellaneous configurable options */ + +#define CONFIG_CLOCKS +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + + +/* Extend size of kernel image for uncompression */ +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +/* Boot FreeBSD/vxWorks from an ELF image */ +#define CONFIG_SYS_MMC_MAX_DEVICE 1 + +/* MMC support */ +#ifdef CONFIG_MMC_SDHCI_ZYNQ +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif + +/* Address in RAM where the parameters must be copied by SPL. */ +#define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000 + +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "system.dtb" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" + +/* Not using MMC raw mode - just for compilation purpose */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 + +/* qspi mode is working fine */ +#ifdef CONFIG_ZYNQ_QSPI +#define CONFIG_SYS_SPI_ARGS_OFFS 0x200000 +#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 +#define CONFIG_SYS_SPI_KERNEL_OFFS (CONFIG_SYS_SPI_ARGS_OFFS + \ + CONFIG_SYS_SPI_ARGS_SIZE) +#endif + +/* SP location before relocation, must use scratch RAM */ + +/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */ +#define CONFIG_SPL_MAX_SIZE 0x30000 + +/* On the top of OCM space */ +#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SPL_STACK_R_ADDR +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000000 + +/* + * SPL stack position - and stack goes down + * 0xfffffe00 is used for putting wfi loop. + * Set it up as limit for now. + */ +#define CONFIG_SPL_STACK 0xfffffe00 + +/* BSS setup */ +#define CONFIG_SPL_BSS_START_ADDR 0x100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 + +#endif /* __CONFIG_ZYNQ_COMMON_H */ diff --git a/roms/u-boot/include/configs/zynq_cse.h b/roms/u-boot/include/configs/zynq_cse.h new file mode 100644 index 000000000..0491cf513 --- /dev/null +++ b/roms/u-boot/include/configs/zynq_cse.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 - 2017 Xilinx. + * + * Configuration settings for the Xilinx Zynq CSE board. + * See zynq-common.h for Zynq common configs + */ + +#ifndef __CONFIG_ZYNQ_CSE_H +#define __CONFIG_ZYNQ_CSE_H + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#include + +/* Undef unneeded configs */ +#undef CONFIG_EXTRA_ENV_SETTINGS + +#undef CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_CBSIZE 1024 + +#undef CONFIG_SYS_INIT_RAM_ADDR +#undef CONFIG_SYS_INIT_RAM_SIZE +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#undef CONFIG_SPL_BSS_START_ADDR +#undef CONFIG_SPL_BSS_MAX_SIZE +#define CONFIG_SPL_BSS_START_ADDR 0x20000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x8000 + +#endif /* __CONFIG_ZYNQ_CSE_H */ diff --git a/roms/u-boot/include/console.h b/roms/u-boot/include/console.h new file mode 100644 index 000000000..7e628c0cf --- /dev/null +++ b/roms/u-boot/include/console.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef __CONSOLE_H +#define __CONSOLE_H + +#include +#include +#include + +extern char console_buffer[]; + +/* common/console.c */ +int console_init_f(void); /* Before relocation; uses the serial stuff */ +int console_init_r(void); /* After relocation; uses the console stuff */ +int console_start(int file, struct stdio_dev *sdev); /* Start a console device */ +void console_stop(int file, struct stdio_dev *sdev); /* Stop a console device */ +int console_assign(int file, const char *devname); /* Assign the console */ +int ctrlc(void); +int had_ctrlc(void); /* have we had a Control-C since last clear? */ +void clear_ctrlc(void); /* clear the Control-C condition */ +int disable_ctrlc(int); /* 1 to disable, 0 to enable Control-C detect */ +int confirm_yesno(void); /* 1 if input is "y", "Y", "yes" or "YES" */ + +/** + * console_search_dev() - search for stdio device with given flags and name + * @flags: device flags as per input/output/system + * @name: device name + * + * Iterates over registered STDIO devices and match them with given @flags + * and @name. + * + * @return pointer to the &struct stdio_dev if found, or NULL otherwise + */ +struct stdio_dev *console_search_dev(int flags, const char *name); + +#ifdef CONFIG_CONSOLE_RECORD +/** + * console_record_init() - set up the console recording buffers + * + * This should be called as soon as malloc() is available so that the maximum + * amount of console output can be recorded. + * + * @return 0 if OK, -ENOMEM if out of memory + */ +int console_record_init(void); + +/** + * console_record_reset() - reset the console recording buffers + * + * Removes any data in the buffers + */ +void console_record_reset(void); + +/** + * console_record_reset_enable() - reset and enable the console buffers + * + * This should be called to enable the console buffer. + * + * @return 0 (always) + */ +int console_record_reset_enable(void); + +/** + * console_record_readline() - Read a line from the console output + * + * This reads the next available line from the console output previously + * recorded. + * + * @str: Place to put string + * @maxlen: Maximum length of @str including nul terminator + * @return length of string returned + */ +int console_record_readline(char *str, int maxlen); + +/** + * console_record_avail() - Get the number of available bytes in console output + * + * @return available bytes (0 if empty) + */ +int console_record_avail(void); +#else +static inline int console_record_init(void) +{ + /* Always succeed, since it is not enabled */ + + return 0; +} + +static inline void console_record_reset(void) +{ + /* Nothing to do here */ +} + +static inline int console_record_reset_enable(void) +{ + /* Cannot enable it as it is not supported */ + return -ENOSYS; +} + +static inline int console_record_readline(char *str, int maxlen) +{ + /* Nothing to read */ + return 0; +} + +static inline int console_record_avail(void) +{ + /* There is never anything available */ + return 0; +} + +#endif /* !CONFIG_CONSOLE_RECORD */ + +/** + * console_announce_r() - print a U-Boot console on non-serial consoles + * + * When U-Boot starts up with a display it generally does not announce itself + * on the display. The banner is instead emitted on the UART before relocation. + * This function prints a banner on devices which (we assume) did not receive + * it before relocation. + * + * @return 0 (meaning no errors) + */ +int console_announce_r(void); + +/** + * console_puts_select_stderr() - Output a string to selected console devices + * + * This writes to stderr only. It is useful for outputting errors + * + * @serial_only: true to output only to serial, false to output to everything + * else + * @s: String to output + */ +void console_puts_select_stderr(bool serial_only, const char *s); + +/* + * CONSOLE multiplexing. + */ +#ifdef CONFIG_CONSOLE_MUX +#include +#endif + +#endif diff --git a/roms/u-boot/include/cortina.h b/roms/u-boot/include/cortina.h new file mode 100644 index 000000000..ba7fafe9c --- /dev/null +++ b/roms/u-boot/include/cortina.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Cortina PHY drivers + * + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef _CORTINA_H_ +#define _CORTINA_H_ + +#define VILLA_GLOBAL_CHIP_ID_LSB 0x000 +#define VILLA_GLOBAL_CHIP_ID_MSB 0x001 +#define VILLA_GLOBAL_BIST_CONTROL 0x002 +#define VILLA_GLOBAL_BIST_STATUS 0x003 +#define VILLA_GLOBAL_LINE_SOFT_RESET 0x007 +#define VILLA_GLOBAL_HOST_SOFT_RESET 0x008 +#define VILLA_GLOBAL_DWNLD_CHECKSUM_CTRL 0x00A +#define VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS 0x00B +#define VILLA_GLOBAL_MSEQCLKCTRL 0x00E +#define VILLA_MSEQ_OPTIONS 0x1D0 +#define VILLA_MSEQ_PC 0x1D3 +#define VILLA_MSEQ_BANKSELECT 0x1DF +#define VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT 0x2DB +#define VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT 0x36E +#define VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER 0x403 +#define VILLA_LINE_SDS_COMMON_SRX0_RX_CPA 0x404 +#define VILLA_LINE_SDS_COMMON_SRX0_RX_CPB 0x405 +#define VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL 0x369 +#define VILLA_MSEQ_ENABLE_MSB 0x194 +#define VILLA_MSEQ_SPARE21_LSB 0x226 +#define VILLA_MSEQ_RESET_COUNT_LSB 0x1E0 +#define VILLA_MSEQ_SPARE12_MSB 0x215 +#define VILLA_MSEQ_SPARE2_LSB 0x200 +#define VILLA_MSEQ_SPARE7_LSB 0x20A +#define VILLA_MSEQ_SPARE9_LSB 0x20E +#define VILLA_MSEQ_SPARE3_LSB 0x202 +#define VILLA_MSEQ_SPARE3_MSB 0x203 +#define VILLA_MSEQ_SPARE8_LSB 0x20C +#define VILLA_MSEQ_SPARE8_MSB 0x20D +#define VILLA_MSEQ_COEF8_FFE0_LSB 0x1E2 +#define VILLA_MSEQ_COEF8_FFE1_LSB 0x1E4 +#define VILLA_MSEQ_COEF8_FFE2_LSB 0x1E6 +#define VILLA_MSEQ_COEF8_FFE3_LSB 0x1E8 +#define VILLA_MSEQ_COEF8_FFE4_LSB 0x1EA +#define VILLA_MSEQ_COEF8_FFE5_LSB 0x1EC +#define VILLA_MSEQ_COEF8_DFE0_LSB 0x1F0 +#define VILLA_MSEQ_COEF8_DFE0N_LSB 0x1EE +#define VILLA_MSEQ_COEF8_DFE1_LSB 0x1F2 +#define VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK 0x2E2 +#define VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB 0x360 +#define VILLA_MSEQ_POWER_DOWN_LSB 0x198 +#define VILLA_MSEQ_POWER_DOWN_MSB 0x199 +#define VILLA_MSEQ_CAL_RX_SLICER 0x1B8 +#define VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB 0x365 +#define VILLA_MSEQ_COEF_INIT_SEL 0x1AE +#define VILLA_DSP_SDS_DSP_PRECODEDINITFFE21 0x26A +#define VILLA_MSEQ_SERDES_PARAM_LSB 0x195 +#define VILLA_MSEQ_SPARE25_LSB 0x22E +#define VILLA_MSEQ_SPARE23_LSB 0x22A +#define VILLA_MSEQ_CAL_RX_DFE_EQ 0x1BA +#define VILLA_GLOBAL_VILLA2_COMPATIBLE 0x030 +#define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x812 +#define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x813 +#define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x427 +#define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x428 + +/* Cortina CS4223 */ +#define CS4223_EEPROM_STATUS 0x5001 +#define CS4223_EEPROM_FIRMWARE_LOADDONE 0x1 + +#define mseq_edc_bist_done (0x1<<0) +#define mseq_edc_bist_fail (0x1<<8) + +struct cortina_reg_config { + unsigned short reg_addr; + unsigned short reg_value; +}; +#endif diff --git a/roms/u-boot/include/cp1250.h b/roms/u-boot/include/cp1250.h new file mode 100644 index 000000000..adacf8a95 --- /dev/null +++ b/roms/u-boot/include/cp1250.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* + * Constant CP1250 contains the Unicode code points for characters 0x80 - 0xff + * of the code page 1250. + */ +#define CP1250 { \ + 0x20ac, 0x0000, 0x201a, 0x0000, \ + 0x201e, 0x2026, 0x2020, 0x2021, \ + 0x0000, 0x2030, 0x0160, 0x2039, \ + 0x015a, 0x0164, 0x017d, 0x0179, \ + 0x0000, 0x2018, 0x2019, 0x201c, \ + 0x201d, 0x2022, 0x2013, 0x2014, \ + 0x0000, 0x2122, 0x0161, 0x203a, \ + 0x015b, 0x0165, 0x017e, 0x017a, \ + 0x00a0, 0x02c7, 0x02d8, 0x0141, \ + 0x00a4, 0x0104, 0x00a6, 0x00a7, \ + 0x00a8, 0x00a9, 0x015e, 0x00ab, \ + 0x00ac, 0x00ad, 0x00ae, 0x017b, \ + 0x00b0, 0x00b1, 0x02db, 0x0142, \ + 0x00b4, 0x00b5, 0x00b6, 0x00b7, \ + 0x00b8, 0x0105, 0x015f, 0x00bb, \ + 0x013d, 0x02dd, 0x013e, 0x017c, \ + 0x0154, 0x00c1, 0x00c2, 0x0102, \ + 0x00c4, 0x0139, 0x0106, 0x00c7, \ + 0x010c, 0x00c9, 0x0118, 0x00cb, \ + 0x011a, 0x00cd, 0x00ce, 0x010e, \ + 0x0110, 0x0143, 0x0147, 0x00d3, \ + 0x00d4, 0x0150, 0x00d6, 0x00d7, \ + 0x0158, 0x016e, 0x00da, 0x0170, \ + 0x00dc, 0x00dd, 0x0162, 0x00df, \ + 0x0155, 0x00e1, 0x00e2, 0x0103, \ + 0x00e4, 0x013a, 0x0107, 0x00e7, \ + 0x010d, 0x00e9, 0x0119, 0x00eb, \ + 0x011b, 0x00ed, 0x00ee, 0x010f, \ + 0x0111, 0x0144, 0x0148, 0x00f3, \ + 0x00f4, 0x0151, 0x00f6, 0x00f7, \ + 0x0159, 0x016f, 0x00fa, 0x0171, \ + 0x00fc, 0x00fd, 0x0163, 0x02d9, \ +} diff --git a/roms/u-boot/include/cp437.h b/roms/u-boot/include/cp437.h new file mode 100644 index 000000000..0b2b97132 --- /dev/null +++ b/roms/u-boot/include/cp437.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* + * Constant CP437 contains the Unicode code points for characters 0x80 - 0xff + * of the code page 437. + */ +#define CP437 { \ + 0x00c7, 0x00fc, 0x00e9, 0x00e2, \ + 0x00e4, 0x00e0, 0x00e5, 0x00e7, \ + 0x00ea, 0x00eb, 0x00e8, 0x00ef, \ + 0x00ee, 0x00ec, 0x00c4, 0x00c5, \ + 0x00c9, 0x00e6, 0x00c6, 0x00f4, \ + 0x00f6, 0x00f2, 0x00fb, 0x00f9, \ + 0x00ff, 0x00d6, 0x00dc, 0x00a2, \ + 0x00a3, 0x00a5, 0x20a7, 0x0192, \ + 0x00e1, 0x00ed, 0x00f3, 0x00fa, \ + 0x00f1, 0x00d1, 0x00aa, 0x00ba, \ + 0x00bf, 0x2310, 0x00ac, 0x00bd, \ + 0x00bc, 0x00a1, 0x00ab, 0x00bb, \ + 0x2591, 0x2592, 0x2593, 0x2502, \ + 0x2524, 0x2561, 0x2562, 0x2556, \ + 0x2555, 0x2563, 0x2551, 0x2557, \ + 0x255d, 0x255c, 0x255b, 0x2510, \ + 0x2514, 0x2534, 0x252c, 0x251c, \ + 0x2500, 0x253c, 0x255e, 0x255f, \ + 0x255a, 0x2554, 0x2569, 0x2566, \ + 0x2560, 0x2550, 0x256c, 0x2567, \ + 0x2568, 0x2564, 0x2565, 0x2559, \ + 0x2558, 0x2552, 0x2553, 0x256b, \ + 0x256a, 0x2518, 0x250c, 0x2588, \ + 0x2584, 0x258c, 0x2590, 0x2580, \ + 0x03b1, 0x00df, 0x0393, 0x03c0, \ + 0x03a3, 0x03c3, 0x00b5, 0x03c4, \ + 0x03a6, 0x0398, 0x03a9, 0x03b4, \ + 0x221e, 0x03c6, 0x03b5, 0x2229, \ + 0x2261, 0x00b1, 0x2265, 0x2264, \ + 0x2320, 0x2321, 0x00f7, 0x2248, \ + 0x00b0, 0x2219, 0x00b7, 0x221a, \ + 0x207f, 0x00b2, 0x25a0, 0x00a0, \ +} diff --git a/roms/u-boot/include/cpsw.h b/roms/u-boot/include/cpsw.h new file mode 100644 index 000000000..786f8b385 --- /dev/null +++ b/roms/u-boot/include/cpsw.h @@ -0,0 +1,85 @@ +/* + * CPSW Ethernet Switch Driver + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CPSW_H_ +#define _CPSW_H_ + +#include + +/* reg offset */ +#define CPSW_HOST_PORT_OFFSET 0x108 +#define CPSW_SLAVE0_OFFSET 0x208 +#define CPSW_SLAVE1_OFFSET 0x308 +#define CPSW_SLAVE_SIZE 0x100 +#define CPSW_CPDMA_OFFSET 0x800 +#define CPSW_HW_STATS 0x900 +#define CPSW_STATERAM_OFFSET 0xa00 +#define CPSW_CPTS_OFFSET 0xc00 +#define CPSW_ALE_OFFSET 0xd00 +#define CPSW_SLIVER0_OFFSET 0xd80 +#define CPSW_SLIVER1_OFFSET 0xdc0 +#define CPSW_BD_OFFSET 0x2000 +#define CPSW_MDIO_DIV 0xff + +#define AM335X_GMII_SEL_OFFSET 0x630 + +struct cpsw_slave_data { + u32 slave_reg_ofs; + u32 sliver_reg_ofs; + int phy_addr; + int phy_if; + ofnode phy_of_handle; + int max_speed; +}; + +enum { + CPSW_CTRL_VERSION_1 = 0, + CPSW_CTRL_VERSION_2 /* am33xx like devices */ +}; + +struct cpsw_platform_data { + u32 mdio_base; + u32 cpsw_base; + u32 mac_id; + u32 gmii_sel; + int mdio_div; + int channels; /* number of cpdma channels (symmetric) */ + u32 cpdma_reg_ofs; /* cpdma register offset */ + int slaves; /* number of slave cpgmac ports */ + u32 ale_reg_ofs; /* address lookup engine reg offset */ + int ale_entries; /* ale table size */ + u32 host_port_reg_ofs; /* cpdma host port registers */ + u32 hw_stats_reg_ofs; /* cpsw hw stats counters */ + u32 bd_ram_ofs; /* Buffer Descriptor RAM offset */ + u32 mac_control; + struct cpsw_slave_data *slave_data; + void (*control)(int enabled); + u32 host_port_num; + u32 active_slave; + bool rmii_clock_external; + u8 version; + const char *phy_sel_compat; + u32 syscon_addr; + const char *macid_sel_compat; +}; + +int cpsw_register(struct cpsw_platform_data *data); +int ti_cm_get_macid_addr(struct udevice *dev, int slave, + struct cpsw_platform_data *data); +void ti_cm_get_macid(struct udevice *dev, struct cpsw_platform_data *data, + u8 *mac_addr); +int cpsw_get_slave_phy_addr(struct udevice *dev, int slave); + +#endif /* _CPSW_H_ */ diff --git a/roms/u-boot/include/cpu.h b/roms/u-boot/include/cpu.h new file mode 100644 index 000000000..be02a1671 --- /dev/null +++ b/roms/u-boot/include/cpu.h @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass + */ + +#ifndef __CPU_H +#define __CPU_H + +struct udevice; + +/** + * struct cpu_plat - platform data for a CPU + * @cpu_id: Platform-specific way of identifying the CPU. + * @ucode_version: Microcode version, if CPU_FEAT_UCODE is set + * @device_id: Driver-defined device identifier + * @family: DMTF CPU Family identifier + * @id: DMTF CPU Processor identifier + * @timebase_freq: the current frequency at which the cpu timer timebase + * registers are updated (in Hz) + * + * This can be accessed with dev_get_parent_plat() for any UCLASS_CPU + * device. + */ +struct cpu_plat { + int cpu_id; + int ucode_version; + ulong device_id; + u16 family; + u32 id[2]; + u32 timebase_freq; +}; + +/* CPU features - mostly just a placeholder for now */ +enum { + CPU_FEAT_L1_CACHE = 0, /* Supports level 1 cache */ + CPU_FEAT_MMU = 1, /* Supports virtual memory */ + CPU_FEAT_UCODE = 2, /* Requires/uses microcode */ + CPU_FEAT_DEVICE_ID = 3, /* Provides a device ID */ + + CPU_FEAT_COUNT, +}; + +/** + * struct cpu_info - Information about a CPU + * + * @cpu_freq: Current CPU frequency in Hz + * @features: Flags for supported CPU features + * @address_width: Width of the CPU address space in bits (e.g. 32) + */ +struct cpu_info { + ulong cpu_freq; + ulong features; + uint address_width; +}; + +struct cpu_ops { + /** + * get_desc() - Get a description string for a CPU + * + * @dev: Device to check (UCLASS_CPU) + * @buf: Buffer to place string + * @size: Size of string space + * @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error + */ + int (*get_desc)(const struct udevice *dev, char *buf, int size); + + /** + * get_info() - Get information about a CPU + * + * @dev: Device to check (UCLASS_CPU) + * @info: Returns CPU info + * @return 0 if OK, -ve on error + */ + int (*get_info)(const struct udevice *dev, struct cpu_info *info); + + /** + * get_count() - Get number of CPUs + * + * @dev: Device to check (UCLASS_CPU) + * @return CPU count if OK, -ve on error + */ + int (*get_count)(const struct udevice *dev); + + /** + * get_vendor() - Get vendor name of a CPU + * + * @dev: Device to check (UCLASS_CPU) + * @buf: Buffer to place string + * @size: Size of string space + * @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error + */ + int (*get_vendor)(const struct udevice *dev, char *buf, int size); + + /** + * is_current() - Check if the CPU that U-Boot is currently running from + * + * @dev: Device to check (UCLASS_CPU) + * @return 1 if the CPU that U-Boot is currently running from, 0 + * if not. + */ + int (*is_current)(struct udevice *dev); +}; + +#define cpu_get_ops(dev) ((struct cpu_ops *)(dev)->driver->ops) + +/** + * cpu_get_desc() - Get a description string for a CPU + * @dev: Device to check (UCLASS_CPU) + * @buf: Buffer to place string + * @size: Size of string space + * + * Return: 0 if OK, -ENOSPC if buffer is too small, other -ve on error + */ +int cpu_get_desc(const struct udevice *dev, char *buf, int size); + +/** + * cpu_get_info() - Get information about a CPU + * @dev: Device to check (UCLASS_CPU) + * @info: Returns CPU info + * + * Return: 0 if OK, -ve on error + */ +int cpu_get_info(const struct udevice *dev, struct cpu_info *info); + +/** + * cpu_get_count() - Get number of CPUs + * @dev: Device to check (UCLASS_CPU) + * + * Return: CPU count if OK, -ve on error + */ +int cpu_get_count(const struct udevice *dev); + +/** + * cpu_get_vendor() - Get vendor name of a CPU + * @dev: Device to check (UCLASS_CPU) + * @buf: Buffer to place string + * @size: Size of string space + * + * Return: 0 if OK, -ENOSPC if buffer is too small, other -ve on error + */ +int cpu_get_vendor(const struct udevice *dev, char *buf, int size); + +/** + * cpu_probe_all() - Probe all available CPUs + * + * Return: 0 if OK, -ve on error + */ +int cpu_probe_all(void); + +/** + * cpu_is_current() - Check if the CPU that U-Boot is currently running from + * + * Return: 1 if yes, - 0 if not + */ +int cpu_is_current(struct udevice *cpu); + +/** + * cpu_get_current_dev() - Get CPU udevice for current CPU + * + * Return: udevice if OK, - NULL on error + */ +struct udevice *cpu_get_current_dev(void); + +#endif diff --git a/roms/u-boot/include/cpu_func.h b/roms/u-boot/include/cpu_func.h new file mode 100644 index 000000000..c3a66f040 --- /dev/null +++ b/roms/u-boot/include/cpu_func.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Copyright 2019 Google LLC + */ + +#ifndef __CPU_LEGACY_H +#define __CPU_LEGACY_H + +#include + +/* + * Multicore arch functions + * + * These should be moved to use the CPU uclass. + */ +int cpu_status(u32 nr); +int cpu_reset(u32 nr); +int cpu_disable(u32 nr); +int cpu_release(u32 nr, int argc, char *const argv[]); + +static inline int cpumask_next(int cpu, unsigned int mask) +{ + for (cpu++; !((1 << cpu) & mask); cpu++) + ; + + return cpu; +} + +#define for_each_cpu(iter, cpu, num_cpus, mask) \ + for (iter = 0, cpu = cpumask_next(-1, mask); \ + iter < num_cpus; \ + iter++, cpu = cpumask_next(cpu, mask)) \ + +int cpu_numcores(void); +int cpu_num_dspcores(void); +u32 cpu_mask(void); +u32 cpu_dsp_mask(void); +int is_core_valid(unsigned int core); + +/** + * checkcpu() - perform an early check of the CPU + * + * This is used on PowerPC, SH and X86 machines as a CPU init mechanism. It is + * called during the pre-relocation init sequence in board_init_f(). + * + * @return 0 if oK, -ve on error + */ +int checkcpu(void); + +void smp_set_core_boot_addr(unsigned long addr, int corenr); +void smp_kick_all_cpus(void); + +int icache_status(void); +void icache_enable(void); +void icache_disable(void); +int dcache_status(void); +void dcache_enable(void); +void dcache_disable(void); +void mmu_disable(void); + +/* arch/$(ARCH)/lib/cache.c */ +void enable_caches(void); +void flush_cache(unsigned long addr, unsigned long size); +void flush_dcache_all(void); +void flush_dcache_range(unsigned long start, unsigned long stop); +void invalidate_dcache_range(unsigned long start, unsigned long stop); +void invalidate_dcache_all(void); +void invalidate_icache_all(void); + +enum { + /* Disable caches (else flush caches but leave them active) */ + CBL_DISABLE_CACHES = 1 << 0, + CBL_SHOW_BOOTSTAGE_REPORT = 1 << 1, + + CBL_ALL = 3, +}; + +/** + * Clean up ready for linux + * + * @param flags Flags to control what is done + */ +int cleanup_before_linux_select(int flags); + +void reset_cpu(void); + +#endif diff --git a/roms/u-boot/include/cramfs/cramfs_fs.h b/roms/u-boot/include/cramfs/cramfs_fs.h new file mode 100644 index 000000000..e0c14f04a --- /dev/null +++ b/roms/u-boot/include/cramfs/cramfs_fs.h @@ -0,0 +1,100 @@ +#ifndef __CRAMFS_H +#define __CRAMFS_H + +#define CRAMFS_MAGIC 0x28cd3d45 /* some random number */ +#define CRAMFS_SIGNATURE "Compressed ROMFS" + +/* + * Width of various bitfields in struct cramfs_inode. + * Primarily used to generate warnings in mkcramfs. + */ +#define CRAMFS_MODE_WIDTH 16 +#define CRAMFS_UID_WIDTH 16 +#define CRAMFS_SIZE_WIDTH 24 +#define CRAMFS_GID_WIDTH 8 +#define CRAMFS_NAMELEN_WIDTH 6 +#define CRAMFS_OFFSET_WIDTH 26 + +/* + * Since inode.namelen is a unsigned 6-bit number, the maximum cramfs + * path length is 63 << 2 = 252. + */ +#define CRAMFS_MAXPATHLEN (((1 << CRAMFS_NAMELEN_WIDTH) - 1) << 2) + +/* + * Reasonably terse representation of the inode data. + */ +struct cramfs_inode { + u32 mode:CRAMFS_MODE_WIDTH, uid:CRAMFS_UID_WIDTH; + + /* SIZE for device files is i_rdev */ + u32 size:CRAMFS_SIZE_WIDTH, gid:CRAMFS_GID_WIDTH; + + /* NAMELEN is the length of the file name, divided by 4 and + rounded up. (cramfs doesn't support hard links.) */ + /* OFFSET: For symlinks and non-empty regular files, this + contains the offset (divided by 4) of the file data in + compressed form (starting with an array of block pointers; + see README). For non-empty directories it is the offset + (divided by 4) of the inode of the first file in that + directory. For anything else, offset is zero. */ + u32 namelen:CRAMFS_NAMELEN_WIDTH, offset:CRAMFS_OFFSET_WIDTH; +}; + +struct cramfs_info { + u32 crc; + u32 edition; + u32 blocks; + u32 files; +}; + +/* + * Superblock information at the beginning of the FS. + */ +struct cramfs_super { + u32 magic; /* 0x28cd3d45 - random number */ + u32 size; /* length in bytes */ + u32 flags; /* feature flags */ + u32 future; /* reserved for future use */ + u8 signature[16]; /* "Compressed ROMFS" */ + struct cramfs_info fsid; /* unique filesystem info */ + u8 name[16]; /* user-defined name */ + struct cramfs_inode root; /* root inode data */ +}; + +/* + * Feature flags + * + * 0x00000000 - 0x000000ff: features that work for all past kernels + * 0x00000100 - 0xffffffff: features that don't work for past kernels + */ +#define CRAMFS_FLAG_FSID_VERSION_2 0x00000001 /* fsid version #2 */ +#define CRAMFS_FLAG_SORTED_DIRS 0x00000002 /* sorted dirs */ +#define CRAMFS_FLAG_HOLES 0x00000100 /* support for holes */ +#define CRAMFS_FLAG_WRONG_SIGNATURE 0x00000200 /* reserved */ +#define CRAMFS_FLAG_SHIFTED_ROOT_OFFSET 0x00000400 /* shifted root fs */ + +/* + * Valid values in super.flags. Currently we refuse to mount + * if (flags & ~CRAMFS_SUPPORTED_FLAGS). Maybe that should be + * changed to test super.future instead. + */ +#define CRAMFS_SUPPORTED_FLAGS ( 0x000000ff \ + | CRAMFS_FLAG_HOLES \ + | CRAMFS_FLAG_WRONG_SIGNATURE \ + | CRAMFS_FLAG_SHIFTED_ROOT_OFFSET ) + +#define CRAMFS_16(x) (x) +#define CRAMFS_24(x) (x) +#define CRAMFS_32(x) (x) +#define CRAMFS_GET_NAMELEN(x) ((x)->namelen) +#define CRAMFS_GET_OFFSET(x) ((x)->offset) +#define CRAMFS_SET_OFFSET(x,y) ((x)->offset = (y)) +#define CRAMFS_SET_NAMELEN(x,y) ((x)->namelen = (y)) + +/* Uncompression interfaces to the underlying zlib */ +int cramfs_uncompress_block(void *dst, void *src, int srclen); +int cramfs_uncompress_init(void); +int cramfs_uncompress_exit(void); + +#endif /* __CRAMFS_H */ diff --git a/roms/u-boot/include/cros_ec.h b/roms/u-boot/include/cros_ec.h new file mode 100644 index 000000000..9396b4d24 --- /dev/null +++ b/roms/u-boot/include/cros_ec.h @@ -0,0 +1,655 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Chromium OS cros_ec driver + * + * Copyright (c) 2012 The Chromium OS Authors. + */ + +#ifndef _CROS_EC_H +#define _CROS_EC_H + +#include +#include +#include +#include +#include + +/* Our configuration information */ +struct cros_ec_dev { + struct udevice *dev; /* Transport device */ + struct gpio_desc ec_int; /* GPIO used as EC interrupt line */ + int protocol_version; /* Protocol version to use */ + int optimise_flash_write; /* Don't write erased flash blocks */ + + /* + * These two buffers will always be dword-aligned and include enough + * space for up to 7 word-alignment bytes also, so we can ensure that + * the body of the message is always dword-aligned (64-bit). + * + * We use this alignment to keep ARM and x86 happy. Probably word + * alignment would be OK, there might be a small performance advantage + * to using dword. + */ + uint8_t din[ALIGN(MSG_BYTES + sizeof(int64_t), sizeof(int64_t))] + __aligned(sizeof(int64_t)); + uint8_t dout[ALIGN(MSG_BYTES + sizeof(int64_t), sizeof(int64_t))] + __aligned(sizeof(int64_t)); +}; + +/* + * Hard-code the number of columns we happen to know we have right now. It + * would be more correct to call cros_ec_info() at startup and determine the + * actual number of keyboard cols from there. + */ +#define CROS_EC_KEYSCAN_COLS 13 + +/* Information returned by a key scan */ +struct mbkp_keyscan { + uint8_t data[CROS_EC_KEYSCAN_COLS]; +}; + +/* Holds information about the Chrome EC */ +struct fdt_cros_ec { + struct fmap_entry flash; /* Address and size of EC flash */ + /* + * Byte value of erased flash, or -1 if not known. It is normally + * 0xff but some flash devices use 0 (e.g. STM32Lxxx) + */ + int flash_erase_value; + struct fmap_entry region[EC_FLASH_REGION_COUNT]; +}; + +/** + * Read the ID of the CROS-EC device + * + * The ID is a string identifying the CROS-EC device. + * + * @param dev CROS-EC device + * @param id Place to put the ID + * @param maxlen Maximum length of the ID field + * @return 0 if ok, -1 on error + */ +int cros_ec_read_id(struct udevice *dev, char *id, int maxlen); + +/** + * Read a keyboard scan from the CROS-EC device + * + * Send a message requesting a keyboard scan and return the result + * + * @param dev CROS-EC device + * @param scan Place to put the scan results + * @return 0 if ok, -1 on error + */ +int cros_ec_scan_keyboard(struct udevice *dev, struct mbkp_keyscan *scan); + +/** + * Get the next pending MKBP event from the ChromeOS EC device. + * + * Send a message requesting the next event and return the result. + * + * @param event Place to put the event. + * @return 0 if ok, <0 on error. + */ +int cros_ec_get_next_event(struct udevice *dev, + struct ec_response_get_next_event *event); + +/** + * Read which image is currently running on the CROS-EC device. + * + * @param dev CROS-EC device + * @param image Destination for image identifier + * @return 0 if ok, <0 on error + */ +int cros_ec_read_current_image(struct udevice *dev, + enum ec_current_image *image); + +/** + * Read the hash of the CROS-EC device firmware. + * + * @param dev CROS-EC device + * @param hash_offset Offset in flash to read from + * @param hash Destination for hash information + * @return 0 if ok, <0 on error + */ +int cros_ec_read_hash(struct udevice *dev, uint hash_offset, + struct ec_response_vboot_hash *hash); + +/** + * Send a reboot command to the CROS-EC device. + * + * Note that some reboot commands (such as EC_REBOOT_COLD) also reboot the AP. + * + * @param dev CROS-EC device + * @param cmd Reboot command + * @param flags Flags for reboot command (EC_REBOOT_FLAG_*) + * @return 0 if ok, <0 on error + */ +int cros_ec_reboot(struct udevice *dev, enum ec_reboot_cmd cmd, uint8_t flags); + +/** + * Check if the CROS-EC device has an interrupt pending. + * + * Read the status of the external interrupt connected to the CROS-EC device. + * If no external interrupt is configured, this always returns 1. + * + * @param dev CROS-EC device + * @return 0 if no interrupt is pending + */ +int cros_ec_interrupt_pending(struct udevice *dev); + +enum { + CROS_EC_OK, + CROS_EC_ERR = 1, + CROS_EC_ERR_FDT_DECODE, + CROS_EC_ERR_CHECK_VERSION, + CROS_EC_ERR_READ_ID, + CROS_EC_ERR_DEV_INIT, +}; + +/** + * Initialise the Chromium OS EC driver + * + * @param blob Device tree blob containing setup information + * @param cros_ecp Returns pointer to the cros_ec device, or NULL if none + * @return 0 if we got an cros_ec device and all is well (or no cros_ec is + * expected), -ve if we should have an cros_ec device but failed to find + * one, or init failed (-CROS_EC_ERR_...). + */ +int cros_ec_init(const void *blob, struct udevice**cros_ecp); + +/** + * Read information about the keyboard matrix + * + * @param dev CROS-EC device + * @param info Place to put the info structure + */ +int cros_ec_info(struct udevice *dev, struct ec_response_mkbp_info *info); + +/** + * Read the host event flags + * + * @param dev CROS-EC device + * @param events_ptr Destination for event flags. Not changed on error. + * @return 0 if ok, <0 on error + */ +int cros_ec_get_host_events(struct udevice *dev, uint32_t *events_ptr); + +/** + * Clear the specified host event flags + * + * @param dev CROS-EC device + * @param events Event flags to clear + * @return 0 if ok, <0 on error + */ +int cros_ec_clear_host_events(struct udevice *dev, uint32_t events); + +/** + * Get/set flash protection + * + * @param dev CROS-EC device + * @param set_mask Mask of flags to set; if 0, just retrieves existing + * protection state without changing it. + * @param set_flags New flag values; only bits in set_mask are applied; + * ignored if set_mask=0. + * @param prot Destination for updated protection state from EC. + * @return 0 if ok, <0 on error + */ +int cros_ec_flash_protect(struct udevice *dev, uint32_t set_mask, + uint32_t set_flags, + struct ec_response_flash_protect *resp); + +/** + * Notify EC of current boot mode + * + * @param dev CROS-EC device + * @param vboot_mode Verified boot mode + * @return 0 if ok, <0 on error + */ +int cros_ec_entering_mode(struct udevice *dev, int mode); + +/** + * Run internal tests on the cros_ec interface. + * + * @param dev CROS-EC device + * @return 0 if ok, <0 if the test failed + */ +int cros_ec_test(struct udevice *dev); + +/** + * Update the EC RW copy. + * + * @param dev CROS-EC device + * @param image the content to write + * @param imafge_size content length + * @return 0 if ok, <0 if the test failed + */ +int cros_ec_flash_update_rw(struct udevice *dev, const uint8_t *image, + int image_size); + +/** + * Return a pointer to the board's CROS-EC device + * + * @return pointer to CROS-EC device, or NULL if none is available + */ +struct udevice *board_get_cros_ec_dev(void); + +struct dm_cros_ec_ops { + /** + * check_version() - Check the protocol version being used (optional) + * + * If provided, this function should check that the EC can be supported + * by the driver. If not provided, HELLO messages will be sent to try + * to determine the protocol version. + * + * @dev: Device to check + * @return 0 if the protocol is valid, -ve if not supported + */ + int (*check_version)(struct udevice *dev); + + /** + * command() - Old-style command interface + * + * This sends a command and receives a response (deprecated, use + * packet()) + * + * @dev: Device to use + * @cmd: Command to send (only supports 0-0xff) + * @cmd_version: Version of command to send (often 0) + * @dout: Output data (may be NULL If dout_len=0) + * @dout_len: Length of output data excluding 4-byte header + * @dinp: On input, set to point to input data, often struct + * cros_ec_dev->din - typically this is left alone but may be + * updated by the driver + * @din_len: Maximum length of response + * @return number of bytes in response, or -ve on error + */ + int (*command)(struct udevice *dev, uint8_t cmd, int cmd_version, + const uint8_t *dout, int dout_len, + uint8_t **dinp, int din_len); + + /** + * packet() - New-style command interface + * + * This interface is preferred over command(), since it is typically + * easier to implement. + * + * @dev: Device to use + * @out_bytes: Number of bytes to send (from struct cros_ec_dev->dout) + * @in_bytes: Maximum number of bytes to expect in response + * @return number of bytes in response, or -ve on error + */ + int (*packet)(struct udevice *dev, int out_bytes, int in_bytes); + + /** + * get_switches() - Get value of EC switches + * + * This is currently supported on the LPC EC. + * + * @dev: Device to use + * @return current switches value, or -ENOSYS if not supported + */ + int (*get_switches)(struct udevice *dev); +}; + +#define dm_cros_ec_get_ops(dev) \ + ((struct dm_cros_ec_ops *)(dev)->driver->ops) + +int cros_ec_register(struct udevice *dev); + +/** + * Dump a block of data for a command. + * + * @param name Name for data (e.g. 'in', 'out') + * @param cmd Command number associated with data, or -1 for none + * @param data Data block to dump + * @param len Length of data block to dump + */ +void cros_ec_dump_data(const char *name, int cmd, const uint8_t *data, int len); + +/** + * Calculate a simple 8-bit checksum of a data block + * + * @param data Data block to checksum + * @param size Size of data block in bytes + * @return checksum value (0 to 255) + */ +int cros_ec_calc_checksum(const uint8_t *data, int size); + +int cros_ec_flash_erase(struct udevice *dev, uint32_t offset, uint32_t size); + +/** + * Read data from the flash + * + * Read an arbitrary amount of data from the EC flash, by repeatedly reading + * small blocks. + * + * The offset starts at 0. You can obtain the region information from + * cros_ec_flash_offset() to find out where to read for a particular region. + * + * @param dev CROS-EC device + * @param data Pointer to data buffer to read into + * @param offset Offset within flash to read from + * @param size Number of bytes to read + * @return 0 if ok, -1 on error + */ +int cros_ec_flash_read(struct udevice *dev, uint8_t *data, uint32_t offset, + uint32_t size); + +/** + * Read back flash parameters + * + * This function reads back parameters of the flash as reported by the EC + * + * @param dev Pointer to device + * @param info Pointer to output flash info struct + */ +int cros_ec_read_flashinfo(struct udevice *dev, + struct ec_response_flash_info *info); + +/** + * Write data to the flash + * + * Write an arbitrary amount of data to the EC flash, by repeatedly writing + * small blocks. + * + * The offset starts at 0. You can obtain the region information from + * cros_ec_flash_offset() to find out where to write for a particular region. + * + * Attempting to write to the region where the EC is currently running from + * will result in an error. + * + * @param dev CROS-EC device + * @param data Pointer to data buffer to write + * @param offset Offset within flash to write to. + * @param size Number of bytes to write + * @return 0 if ok, -1 on error + */ +int cros_ec_flash_write(struct udevice *dev, const uint8_t *data, + uint32_t offset, uint32_t size); + +/** + * Obtain position and size of a flash region + * + * @param dev CROS-EC device + * @param region Flash region to query + * @param offset Returns offset of flash region in EC flash + * @param size Returns size of flash region + * @return 0 if ok, -1 on error + */ +int cros_ec_flash_offset(struct udevice *dev, enum ec_flash_region region, + uint32_t *offset, uint32_t *size); + +/** + * cros_ec_get_sku_id() - Read the SKU ID + * + * @dev: CROS-EC device + * return SKU ID, or -ve on error + */ +int cros_ec_get_sku_id(struct udevice *dev); + +/** + * Read/write non-volatile data from/to a CROS-EC device. + * + * @param dev CROS-EC device + * @param block Buffer of VbNvContext to be read/write + * @return 0 if ok, -1 on error + */ +int cros_ec_read_nvdata(struct udevice *dev, uint8_t *block, int size); +int cros_ec_write_nvdata(struct udevice *dev, const uint8_t *block, int size); + +/** + * Read the version information for the EC images + * + * @param dev CROS-EC device + * @param versionp This is set to point to the version information + * @return 0 if ok, -1 on error + */ +int cros_ec_read_version(struct udevice *dev, + struct ec_response_get_version **versionp); + +/** + * Read the build information for the EC + * + * @param dev CROS-EC device + * @param versionp This is set to point to the build string + * @return 0 if ok, -1 on error + */ +int cros_ec_read_build_info(struct udevice *dev, char **strp); + +/** + * Switch on/off a LDO / FET. + * + * @param dev CROS-EC device + * @param index index of the LDO/FET to switch + * @param state new state of the LDO/FET : EC_LDO_STATE_ON|OFF + * @return 0 if ok, -1 on error + */ +int cros_ec_set_ldo(struct udevice *dev, uint8_t index, uint8_t state); + +/** + * Read back a LDO / FET current state. + * + * @param dev CROS-EC device + * @param index index of the LDO/FET to switch + * @param state current state of the LDO/FET : EC_LDO_STATE_ON|OFF + * @return 0 if ok, -1 on error + */ +int cros_ec_get_ldo(struct udevice *dev, uint8_t index, uint8_t *state); + +/** + * Get access to the error reported when cros_ec_board_init() was called + * + * This permits delayed reporting of the EC error if it failed during + * early init. + * + * @return error (0 if there was no error, -ve if there was an error) + */ +int cros_ec_get_error(void); + +/** + * Returns information from the FDT about the Chrome EC flash + * + * @param dev Device to read from + * @param config Structure to use to return information + */ +int cros_ec_decode_ec_flash(struct udevice *dev, struct fdt_cros_ec *config); + +/** + * Check the current keyboard state, in case recovery mode is requested. + * This function is for sandbox only. + * + * @param ec CROS-EC device + */ +void cros_ec_check_keyboard(struct udevice *dev); + +struct i2c_msg; +/* + * Tunnel an I2C transfer to the EC + * + * @param dev CROS-EC device + * @param port The remote port on EC to use + * @param msg List of messages to transfer + * @param nmsgs Number of messages to transfer + */ +int cros_ec_i2c_tunnel(struct udevice *dev, int port, struct i2c_msg *msg, + int nmsgs); + +/** + * cros_ec_get_events_b() - Get event mask B + * + * @return value of event mask, default value of 0 if it could not be read + */ +uint64_t cros_ec_get_events_b(struct udevice *dev); + +/** + * cros_ec_clear_events_b() - Clear even mask B + * + * Any pending events in the B range are cleared + * + * @return 0 if OK, -ve on error + */ +int cros_ec_clear_events_b(struct udevice *dev, uint64_t mask); + +/** + * cros_ec_efs_verify() - tell the EC to verify one of its images + * + * @param dev CROS-EC device + * @param region Flash region to query + * @return 0 if OK, -ve on error + */ +int cros_ec_efs_verify(struct udevice *dev, enum ec_flash_region region); + +/** + * cros_ec_battery_cutoff() - Request that the battery be cut off + * + * This tells the battery to stop supplying power. This is used before shipping + * a device to ensure that the battery remains charged while the device is + * shipped or sitting on the shelf waiting to be purchased. + * + * @param dev CROS-EC device + * @param flags Flags to use (EC_BATTERY_CUTOFF_FLAG_...) + * @return 0 if OK, -ve on error + */ +int cros_ec_battery_cutoff(struct udevice *dev, uint8_t flags); + +/** + * cros_ec_set_pwm_duty() - Set duty cycle of a generic pwm + * + * Note that duty value needs to be passed to the EC as a 16 bit number + * for increased precision. + * + * @param dev CROS-EC device + * @param index Index of the pwm + * @param duty Desired duty cycle, in 0..EC_PWM_MAX_DUTY range. + * @return 0 if OK, -ve on error + */ +int cros_ec_set_pwm_duty(struct udevice *dev, uint8_t index, uint16_t duty); + +/** + * cros_ec_read_limit_power() - Check if power is limited by batter/charger + * + * Sometimes the battery is low and / or the device is connected to a charger + * that cannot supply much power. + * + * @param dev CROS-EC device + * @param limit_powerp Returns whether power is limited (0 or 1) + * @return 0 if OK, -ENOSYS if the EC does not support this comment, -EINVAL + * if the EC returned an invalid response + */ +int cros_ec_read_limit_power(struct udevice *dev, int *limit_powerp); + +/** + * cros_ec_config_powerbtn() - Configure the behaviour of the power button + * + * @param dev CROS-EC device + * @param flags Flags to use (EC_POWER_BUTTON_...) + * @return 0 if OK, -ve on error + */ +int cros_ec_config_powerbtn(struct udevice *dev, uint32_t flags); + +/** + * cros_ec_get_lid_shutdown_mask() - Set the lid shutdown mask + * + * Determines whether a lid close event is reported + * + * @param dev CROS-EC device + * @return shufdown mas if OK, -ve on error + */ +int cros_ec_get_lid_shutdown_mask(struct udevice *dev); + +/** + * cros_ec_set_lid_shutdown_mask() - Set the lid shutdown mask + * + * Set whether a lid close event is reported + * + * @param dev CROS-EC device + * @param enable true to enable reporting, false to disable + * @return shufdown mas if OK, -ve on error + */ +int cros_ec_set_lid_shutdown_mask(struct udevice *dev, int enable); + +/** + * cros_ec_hello() - Send a hello message + * + * Sends a message with a fixed input value and checks that the expected output + * value is received + * + * @dev: CROS-EC device + * @handshakep: If non-NULL, returns received handshake value on error + * @return 0 if OK, -ve on error + */ +int cros_ec_hello(struct udevice *dev, uint *handshakep); + +/** + * cros_ec_get_features() - Get the set of features provided by the EC + * + * See enum ec_feature_code for the list of available features + * + * @dev: CROS-EC device + * @featuresp: Returns a bitmask of supported features + * @return 0 if OK, -ve on error + */ +int cros_ec_get_features(struct udevice *dev, u64 *featuresp); + +/** + * cros_ec_check_feature() - Check if a feature is supported + * + * @dev: CROS-EC device + * @feature: Feature number to check (enum ec_feature_code) + * @return true if supported, false if not, -ve on error + */ +int cros_ec_check_feature(struct udevice *dev, uint feature); + +/** + * cros_ec_get_switches() - Get switches value + * + * @dev: CROS-EC device + * @return switches value, or -ENOSYS if not supported, or other -ve value on + * other error + */ +int cros_ec_get_switches(struct udevice *dev); + +/** + * cros_ec_vstore_supported() - Check if vstore is supported + * + * @dev: CROS-EC device + * @return false if not supported, true if supported, -ve on error + */ +int cros_ec_vstore_supported(struct udevice *dev); + +/** + * cros_ec_vstore_info() - Get vstore information + * + * @dev: CROS-EC device + * @lockedp: mask of locked slots + * @return number of vstore slots supported by the EC,, -ve on error + */ +int cros_ec_vstore_info(struct udevice *dev, u32 *lockedp); + +/** + * cros_ec_vstore_read() - Read data from EC vstore slot + * + * @dev: CROS-EC device + * @slot: vstore slot to read from + * @data: buffer to store read data, must be EC_VSTORE_SLOT_SIZE bytes + * @return 0 if OK, -ve on error + */ +int cros_ec_vstore_read(struct udevice *dev, int slot, uint8_t *data); + +/** + * cros_ec_vstore_write() - Save data into EC vstore slot + * + * The maximum size of data is EC_VSTORE_SLOT_SIZE. It is the caller's + * responsibility to check the number of implemented slots by querying the + * vstore info. + * + * @dev: CROS-EC device + * @slot: vstore slot to write into + * @data: data to write + * @size: size of data in bytes + * @return 0 if OK, -ve on error + */ +int cros_ec_vstore_write(struct udevice *dev, int slot, const uint8_t *data, + size_t size); + +#endif diff --git a/roms/u-boot/include/cros_ec_message.h b/roms/u-boot/include/cros_ec_message.h new file mode 100644 index 000000000..977951b30 --- /dev/null +++ b/roms/u-boot/include/cros_ec_message.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Chromium OS Matrix Keyboard Message Protocol definitions + * + * Copyright (c) 2012 The Chromium OS Authors. + */ + +#ifndef _CROS_MESSAGE_H +#define _CROS_MESSAGE_H + +/* + * Command interface between EC and AP, for LPC, I2C and SPI interfaces. + * + * This is copied from the Chromium OS Open Source Embedded Controller code. + */ +enum { + /* The header byte, which follows the preamble */ + MSG_HEADER = 0xec, + + MSG_HEADER_BYTES = 3, + MSG_TRAILER_BYTES = 2, + MSG_PROTO_BYTES = MSG_HEADER_BYTES + MSG_TRAILER_BYTES, + + /* Max length of messages */ + MSG_BYTES = EC_PROTO2_MAX_PARAM_SIZE + MSG_PROTO_BYTES, +}; + +#endif diff --git a/roms/u-boot/include/crypto/internal/rsa.h b/roms/u-boot/include/crypto/internal/rsa.h new file mode 100644 index 000000000..e870133f4 --- /dev/null +++ b/roms/u-boot/include/crypto/internal/rsa.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * RSA internal helpers + * + * Copyright (c) 2015, Intel Corporation + * Authors: Tadeusz Struk + */ +#ifndef _RSA_HELPER_ +#define _RSA_HELPER_ +#include + +/** + * rsa_key - RSA key structure + * @n : RSA modulus raw byte stream + * @e : RSA public exponent raw byte stream + * @d : RSA private exponent raw byte stream + * @p : RSA prime factor p of n raw byte stream + * @q : RSA prime factor q of n raw byte stream + * @dp : RSA exponent d mod (p - 1) raw byte stream + * @dq : RSA exponent d mod (q - 1) raw byte stream + * @qinv : RSA CRT coefficient q^(-1) mod p raw byte stream + * @n_sz : length in bytes of RSA modulus n + * @e_sz : length in bytes of RSA public exponent + * @d_sz : length in bytes of RSA private exponent + * @p_sz : length in bytes of p field + * @q_sz : length in bytes of q field + * @dp_sz : length in bytes of dp field + * @dq_sz : length in bytes of dq field + * @qinv_sz : length in bytes of qinv field + */ +struct rsa_key { + const u8 *n; + const u8 *e; + const u8 *d; + const u8 *p; + const u8 *q; + const u8 *dp; + const u8 *dq; + const u8 *qinv; + size_t n_sz; + size_t e_sz; + size_t d_sz; + size_t p_sz; + size_t q_sz; + size_t dp_sz; + size_t dq_sz; + size_t qinv_sz; +}; + +int rsa_parse_pub_key(struct rsa_key *rsa_key, const void *key, + unsigned int key_len); + +int rsa_parse_priv_key(struct rsa_key *rsa_key, const void *key, + unsigned int key_len); + +extern struct crypto_template rsa_pkcs1pad_tmpl; +#endif diff --git a/roms/u-boot/include/crypto/pkcs7.h b/roms/u-boot/include/crypto/pkcs7.h new file mode 100644 index 000000000..ca35df29f --- /dev/null +++ b/roms/u-boot/include/crypto/pkcs7.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* PKCS#7 crypto data parser + * + * Copyright (C) 2012 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + */ + +#ifndef _CRYPTO_PKCS7_H +#define _CRYPTO_PKCS7_H + +#ifndef __UBOOT__ +#include +#include +#endif + +struct key; +struct pkcs7_message; + +/* + * pkcs7_parser.c + */ +extern struct pkcs7_message *pkcs7_parse_message(const void *data, + size_t datalen); +extern void pkcs7_free_message(struct pkcs7_message *pkcs7); + +extern int pkcs7_get_content_data(const struct pkcs7_message *pkcs7, + const void **_data, size_t *_datalen, + size_t *_headerlen); + +#ifdef __UBOOT__ +struct pkcs7_signed_info; +struct x509_certificate; + +int pkcs7_verify_one(struct pkcs7_message *pkcs7, + struct pkcs7_signed_info *sinfo, + struct x509_certificate **signer); +#else +/* + * pkcs7_trust.c + */ +extern int pkcs7_validate_trust(struct pkcs7_message *pkcs7, + struct key *trust_keyring); + +/* + * pkcs7_verify.c + */ +extern int pkcs7_verify(struct pkcs7_message *pkcs7, + enum key_being_used_for usage); + +extern int pkcs7_supply_detached_data(struct pkcs7_message *pkcs7, + const void *data, size_t datalen); +#endif + +#endif /* _CRYPTO_PKCS7_H */ diff --git a/roms/u-boot/include/crypto/pkcs7_parser.h b/roms/u-boot/include/crypto/pkcs7_parser.h new file mode 100644 index 000000000..906033a90 --- /dev/null +++ b/roms/u-boot/include/crypto/pkcs7_parser.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* PKCS#7 crypto data parser internal definitions + * + * Copyright (C) 2012 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + */ + +#ifndef _PKCS7_PARSER_H +#define _PKCS7_PARSER_H + +#include +#include +#include + +#define kenter(FMT, ...) \ + pr_devel("==> %s("FMT")\n", __func__, ##__VA_ARGS__) +#define kleave(FMT, ...) \ + pr_devel("<== %s()"FMT"\n", __func__, ##__VA_ARGS__) + +struct pkcs7_signed_info { + struct pkcs7_signed_info *next; + struct x509_certificate *signer; /* Signing certificate (in msg->certs) */ + unsigned index; + bool unsupported_crypto; /* T if not usable due to missing crypto */ + bool blacklisted; + + /* Message digest - the digest of the Content Data (or NULL) */ + const void *msgdigest; + unsigned msgdigest_len; + + /* Authenticated Attribute data (or NULL) */ + unsigned authattrs_len; + const void *authattrs; + unsigned long aa_set; +#define sinfo_has_content_type 0 +#define sinfo_has_signing_time 1 +#define sinfo_has_message_digest 2 +#define sinfo_has_smime_caps 3 +#define sinfo_has_ms_opus_info 4 +#define sinfo_has_ms_statement_type 5 + time64_t signing_time; + + /* Message signature. + * + * This contains the generated digest of _either_ the Content Data or + * the Authenticated Attributes [RFC2315 9.3]. If the latter, one of + * the attributes contains the digest of the the Content Data within + * it. + * + * THis also contains the issuing cert serial number and issuer's name + * [PKCS#7 or CMS ver 1] or issuing cert's SKID [CMS ver 3]. + */ + struct public_key_signature *sig; +}; + +struct pkcs7_message { + struct x509_certificate *certs; /* Certificate list */ + struct x509_certificate *crl; /* Revocation list */ + struct pkcs7_signed_info *signed_infos; + u8 version; /* Version of cert (1 -> PKCS#7 or CMS; 3 -> CMS) */ + bool have_authattrs; /* T if have authattrs */ + + /* Content Data (or NULL) */ + enum OID data_type; /* Type of Data */ + size_t data_len; /* Length of Data */ + size_t data_hdrlen; /* Length of Data ASN.1 header */ + const void *data; /* Content Data (or 0) */ +}; +#endif /* _PKCS7_PARSER_H */ diff --git a/roms/u-boot/include/crypto/public_key.h b/roms/u-boot/include/crypto/public_key.h new file mode 100644 index 000000000..3ba90fcc3 --- /dev/null +++ b/roms/u-boot/include/crypto/public_key.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Asymmetric public-key algorithm definitions + * + * See Documentation/crypto/asymmetric-keys.txt + * + * Copyright (C) 2012 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + */ + +#ifndef _LINUX_PUBLIC_KEY_H +#define _LINUX_PUBLIC_KEY_H + +#ifdef __UBOOT__ +#include +#else +#include +#endif +#include + +/* + * Cryptographic data for the public-key subtype of the asymmetric key type. + * + * Note that this may include private part of the key as well as the public + * part. + */ +struct public_key { + void *key; + u32 keylen; + enum OID algo; + void *params; + u32 paramlen; + bool key_is_private; + const char *id_type; + const char *pkey_algo; +}; + +extern void public_key_free(struct public_key *key); + +/* + * Public key cryptography signature data + */ +struct public_key_signature { + struct asymmetric_key_id *auth_ids[2]; + u8 *s; /* Signature */ + u32 s_size; /* Number of bytes in signature */ + u8 *digest; + u8 digest_size; /* Number of bytes in digest */ + const char *pkey_algo; + const char *hash_algo; + const char *encoding; +}; + +extern void public_key_signature_free(struct public_key_signature *sig); + +#ifndef __UBOOT__ +extern struct asymmetric_key_subtype public_key_subtype; + +struct key; +struct key_type; +union key_payload; + +extern int restrict_link_by_signature(struct key *dest_keyring, + const struct key_type *type, + const union key_payload *payload, + struct key *trust_keyring); + +extern int restrict_link_by_key_or_keyring(struct key *dest_keyring, + const struct key_type *type, + const union key_payload *payload, + struct key *trusted); + +extern int restrict_link_by_key_or_keyring_chain(struct key *trust_keyring, + const struct key_type *type, + const union key_payload *payload, + struct key *trusted); + +extern int query_asymmetric_key(const struct kernel_pkey_params *, + struct kernel_pkey_query *); + +extern int encrypt_blob(struct kernel_pkey_params *, const void *, void *); +extern int decrypt_blob(struct kernel_pkey_params *, const void *, void *); +extern int create_signature(struct kernel_pkey_params *, const void *, void *); +extern int verify_signature(const struct key *, + const struct public_key_signature *); +#endif /* __UBOOT__ */ + +int public_key_verify_signature(const struct public_key *pkey, + const struct public_key_signature *sig); + +#endif /* _LINUX_PUBLIC_KEY_H */ diff --git a/roms/u-boot/include/crypto/x509_parser.h b/roms/u-boot/include/crypto/x509_parser.h new file mode 100644 index 000000000..4cbdc1d66 --- /dev/null +++ b/roms/u-boot/include/crypto/x509_parser.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* X.509 certificate parser internal definitions + * + * Copyright (C) 2012 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + */ + +#ifndef _X509_PARSER_H +#define _X509_PARSER_H + +#include +#include +#include + +struct x509_certificate { + struct x509_certificate *next; + struct x509_certificate *signer; /* Certificate that signed this one */ + struct public_key *pub; /* Public key details */ + struct public_key_signature *sig; /* Signature parameters */ + char *issuer; /* Name of certificate issuer */ + char *subject; /* Name of certificate subject */ + struct asymmetric_key_id *id; /* Issuer + Serial number */ + struct asymmetric_key_id *skid; /* Subject + subjectKeyId (optional) */ + time64_t valid_from; + time64_t valid_to; + const void *tbs; /* Signed data */ + unsigned tbs_size; /* Size of signed data */ + unsigned raw_sig_size; /* Size of sigature */ + const void *raw_sig; /* Signature data */ + const void *raw_serial; /* Raw serial number in ASN.1 */ + unsigned raw_serial_size; + unsigned raw_issuer_size; + const void *raw_issuer; /* Raw issuer name in ASN.1 */ + const void *raw_subject; /* Raw subject name in ASN.1 */ + unsigned raw_subject_size; + unsigned raw_skid_size; + const void *raw_skid; /* Raw subjectKeyId in ASN.1 */ + unsigned index; + bool seen; /* Infinite recursion prevention */ + bool verified; + bool self_signed; /* T if self-signed (check unsupported_sig too) */ + bool unsupported_key; /* T if key uses unsupported crypto */ + bool unsupported_sig; /* T if signature uses unsupported crypto */ + bool blacklisted; +}; + +/* + * x509_cert_parser.c + */ +extern void x509_free_certificate(struct x509_certificate *cert); +extern struct x509_certificate *x509_cert_parse(const void *data, size_t datalen); +extern int x509_decode_time(time64_t *_t, size_t hdrlen, + unsigned char tag, + const unsigned char *value, size_t vlen); + +/* + * x509_public_key.c + */ +extern int x509_get_sig_params(struct x509_certificate *cert); +extern int x509_check_for_self_signed(struct x509_certificate *cert); +#endif /* _X509_PARSER_H */ diff --git a/roms/u-boot/include/ctype.h b/roms/u-boot/include/ctype.h new file mode 120000 index 000000000..9e43f9c6c --- /dev/null +++ b/roms/u-boot/include/ctype.h @@ -0,0 +1 @@ +linux/ctype.h \ No newline at end of file diff --git a/roms/u-boot/include/ddr_spd.h b/roms/u-boot/include/ddr_spd.h new file mode 100644 index 000000000..fe163da43 --- /dev/null +++ b/roms/u-boot/include/ddr_spd.h @@ -0,0 +1,564 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + */ + +#ifndef _DDR_SPD_H_ +#define _DDR_SPD_H_ + +/* + * Format from "JEDEC Standard No. 21-C, + * Appendix D: Rev 1.0: SPD's for DDR SDRAM + */ +typedef struct ddr1_spd_eeprom_s { + unsigned char info_size; /* 0 # bytes written into serial memory */ + unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ + unsigned char mem_type; /* 2 Fundamental memory type */ + unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ + unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ + unsigned char nrows; /* 5 Number of DIMM Banks */ + unsigned char dataw_lsb; /* 6 Data Width of this assembly */ + unsigned char dataw_msb; /* 7 ... Data Width continuation */ + unsigned char voltage; /* 8 Voltage intf std of this assembly */ + unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ + unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ + unsigned char config; /* 11 DIMM Configuration type */ + unsigned char refresh; /* 12 Refresh Rate/Type */ + unsigned char primw; /* 13 Primary SDRAM Width */ + unsigned char ecw; /* 14 Error Checking SDRAM width */ + unsigned char min_delay; /* 15 for Back to Back Random Address */ + unsigned char burstl; /* 16 Burst Lengths Supported */ + unsigned char nbanks; /* 17 # of Banks on SDRAM Device */ + unsigned char cas_lat; /* 18 CAS# Latencies Supported */ + unsigned char cs_lat; /* 19 CS# Latency */ + unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */ + unsigned char mod_attr; /* 21 SDRAM Module Attributes */ + unsigned char dev_attr; /* 22 SDRAM Device Attributes */ + unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */ + unsigned char clk_access2; /* 24 SDRAM Access from + Clk @ CL=X-0.5 (tAC) */ + unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */ + unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */ + unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ + unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ + unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ + unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ + unsigned char bank_dens; /* 31 Density of each bank on module */ + unsigned char ca_setup; /* 32 Addr + Cmd Setup Time Before Clk */ + unsigned char ca_hold; /* 33 Addr + Cmd Hold Time After Clk */ + unsigned char data_setup; /* 34 Data Input Setup Time Before Strobe */ + unsigned char data_hold; /* 35 Data Input Hold Time After Strobe */ + unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */ + unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ + unsigned char trfc; /* 42 Min Auto to Active period tRFC */ + unsigned char tckmax; /* 43 Max device cycle time tCKmax */ + unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ + unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ + unsigned char res_46; /* 46 Reserved */ + unsigned char dimm_height; /* 47 DDR SDRAM DIMM Height */ + unsigned char res_48_61[14]; /* 48-61 Reserved */ + unsigned char spd_rev; /* 62 SPD Data Revision Code */ + unsigned char cksum; /* 63 Checksum for bytes 0-62 */ + unsigned char mid[8]; /* 64-71 Mfr's JEDEC ID code per JEP-106 */ + unsigned char mloc; /* 72 Manufacturing Location */ + unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ + unsigned char rev[2]; /* 91 Revision Code */ + unsigned char mdate[2]; /* 93 Manufacturing Date */ + unsigned char sernum[4]; /* 95 Assembly Serial Number */ + unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ + +} ddr1_spd_eeprom_t; + +/* + * Format from "JEDEC Appendix X: Serial Presence Detects for DDR2 SDRAM", + * SPD Revision 1.2 + */ +typedef struct ddr2_spd_eeprom_s { + unsigned char info_size; /* 0 # bytes written into serial memory */ + unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ + unsigned char mem_type; /* 2 Fundamental memory type */ + unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ + unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ + unsigned char mod_ranks; /* 5 Number of DIMM Ranks */ + unsigned char dataw; /* 6 Module Data Width */ + unsigned char res_7; /* 7 Reserved */ + unsigned char voltage; /* 8 Voltage intf std of this assembly */ + unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ + unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ + unsigned char config; /* 11 DIMM Configuration type */ + unsigned char refresh; /* 12 Refresh Rate/Type */ + unsigned char primw; /* 13 Primary SDRAM Width */ + unsigned char ecw; /* 14 Error Checking SDRAM width */ + unsigned char res_15; /* 15 Reserved */ + unsigned char burstl; /* 16 Burst Lengths Supported */ + unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */ + unsigned char cas_lat; /* 18 CAS# Latencies Supported */ + unsigned char mech_char; /* 19 DIMM Mechanical Characteristics */ + unsigned char dimm_type; /* 20 DIMM type information */ + unsigned char mod_attr; /* 21 SDRAM Module Attributes */ + unsigned char dev_attr; /* 22 SDRAM Device Attributes */ + unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-1 */ + unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */ + unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-2 */ + unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */ + unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ + unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ + unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ + unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ + unsigned char rank_dens; /* 31 Density of each rank on module */ + unsigned char ca_setup; /* 32 Addr+Cmd Setup Time Before Clk (tIS) */ + unsigned char ca_hold; /* 33 Addr+Cmd Hold Time After Clk (tIH) */ + unsigned char data_setup; /* 34 Data Input Setup Time + Before Strobe (tDS) */ + unsigned char data_hold; /* 35 Data Input Hold Time + After Strobe (tDH) */ + unsigned char twr; /* 36 Write Recovery time tWR */ + unsigned char twtr; /* 37 Int write to read delay tWTR */ + unsigned char trtp; /* 38 Int read to precharge delay tRTP */ + unsigned char mem_probe; /* 39 Mem analysis probe characteristics */ + unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */ + unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ + unsigned char trfc; /* 42 Min Auto to Active period tRFC */ + unsigned char tckmax; /* 43 Max device cycle time tCKmax */ + unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ + unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ + unsigned char pll_relock; /* 46 PLL Relock time */ + unsigned char t_casemax; /* 47 Tcasemax */ + unsigned char psi_ta_dram; /* 48 Thermal Resistance of DRAM Package from + Top (Case) to Ambient (Psi T-A DRAM) */ + unsigned char dt0_mode; /* 49 DRAM Case Temperature Rise from Ambient + due to Activate-Precharge/Mode Bits + (DT0/Mode Bits) */ + unsigned char dt2n_dt2q; /* 50 DRAM Case Temperature Rise from Ambient + due to Precharge/Quiet Standby + (DT2N/DT2Q) */ + unsigned char dt2p; /* 51 DRAM Case Temperature Rise from Ambient + due to Precharge Power-Down (DT2P) */ + unsigned char dt3n; /* 52 DRAM Case Temperature Rise from Ambient + due to Active Standby (DT3N) */ + unsigned char dt3pfast; /* 53 DRAM Case Temperature Rise from Ambient + due to Active Power-Down with + Fast PDN Exit (DT3Pfast) */ + unsigned char dt3pslow; /* 54 DRAM Case Temperature Rise from Ambient + due to Active Power-Down with Slow + PDN Exit (DT3Pslow) */ + unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient + due to Page Open Burst Read/DT4R4W + Mode Bit (DT4R/DT4R4W Mode Bit) */ + unsigned char dt5b; /* 56 DRAM Case Temperature Rise from Ambient + due to Burst Refresh (DT5B) */ + unsigned char dt7; /* 57 DRAM Case Temperature Rise from Ambient + due to Bank Interleave Reads with + Auto-Precharge (DT7) */ + unsigned char psi_ta_pll; /* 58 Thermal Resistance of PLL Package form + Top (Case) to Ambient (Psi T-A PLL) */ + unsigned char psi_ta_reg; /* 59 Thermal Reisitance of Register Package + from Top (Case) to Ambient + (Psi T-A Register) */ + unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient + due to PLL Active (DT PLL Active) */ + unsigned char dtregact; /* 61 Register Case Temperature Rise from + Ambient due to Register Active/Mode Bit + (DT Register Active/Mode Bit) */ + unsigned char spd_rev; /* 62 SPD Data Revision Code */ + unsigned char cksum; /* 63 Checksum for bytes 0-62 */ + unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-106 */ + unsigned char mloc; /* 72 Manufacturing Location */ + unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ + unsigned char rev[2]; /* 91 Revision Code */ + unsigned char mdate[2]; /* 93 Manufacturing Date */ + unsigned char sernum[4]; /* 95 Assembly Serial Number */ + unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ + +} ddr2_spd_eeprom_t; + +typedef struct ddr3_spd_eeprom_s { + /* General Section: Bytes 0-59 */ + unsigned char info_size_crc; /* 0 # bytes written into serial memory, + CRC coverage */ + unsigned char spd_rev; /* 1 Total # bytes of SPD mem device */ + unsigned char mem_type; /* 2 Key Byte / Fundamental mem type */ + unsigned char module_type; /* 3 Key Byte / Module Type */ + unsigned char density_banks; /* 4 SDRAM Density and Banks */ + unsigned char addressing; /* 5 SDRAM Addressing */ + unsigned char module_vdd; /* 6 Module nominal voltage, VDD */ + unsigned char organization; /* 7 Module Organization */ + unsigned char bus_width; /* 8 Module Memory Bus Width */ + unsigned char ftb_div; /* 9 Fine Timebase (FTB) + Dividend / Divisor */ + unsigned char mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */ + unsigned char mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */ + unsigned char tck_min; /* 12 SDRAM Minimum Cycle Time */ + unsigned char res_13; /* 13 Reserved */ + unsigned char caslat_lsb; /* 14 CAS Latencies Supported, + Least Significant Byte */ + unsigned char caslat_msb; /* 15 CAS Latencies Supported, + Most Significant Byte */ + unsigned char taa_min; /* 16 Min CAS Latency Time */ + unsigned char twr_min; /* 17 Min Write REcovery Time */ + unsigned char trcd_min; /* 18 Min RAS# to CAS# Delay Time */ + unsigned char trrd_min; /* 19 Min Row Active to + Row Active Delay Time */ + unsigned char trp_min; /* 20 Min Row Precharge Delay Time */ + unsigned char tras_trc_ext; /* 21 Upper Nibbles for tRAS and tRC */ + unsigned char tras_min_lsb; /* 22 Min Active to Precharge + Delay Time */ + unsigned char trc_min_lsb; /* 23 Min Active to Active/Refresh + Delay Time, LSB */ + unsigned char trfc_min_lsb; /* 24 Min Refresh Recovery Delay Time */ + unsigned char trfc_min_msb; /* 25 Min Refresh Recovery Delay Time */ + unsigned char twtr_min; /* 26 Min Internal Write to + Read Command Delay Time */ + unsigned char trtp_min; /* 27 Min Internal Read to Precharge + Command Delay Time */ + unsigned char tfaw_msb; /* 28 Upper Nibble for tFAW */ + unsigned char tfaw_min; /* 29 Min Four Activate Window + Delay Time*/ + unsigned char opt_features; /* 30 SDRAM Optional Features */ + unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */ + unsigned char therm_sensor; /* 32 Module Thermal Sensor */ + unsigned char device_type; /* 33 SDRAM device type */ + int8_t fine_tck_min; /* 34 Fine offset for tCKmin */ + int8_t fine_taa_min; /* 35 Fine offset for tAAmin */ + int8_t fine_trcd_min; /* 36 Fine offset for tRCDmin */ + int8_t fine_trp_min; /* 37 Fine offset for tRPmin */ + int8_t fine_trc_min; /* 38 Fine offset for tRCmin */ + unsigned char res_39_59[21]; /* 39-59 Reserved, General Section */ + + /* Module-Specific Section: Bytes 60-116 */ + union { + struct { + /* 60 (Unbuffered) Module Nominal Height */ + unsigned char mod_height; + /* 61 (Unbuffered) Module Maximum Thickness */ + unsigned char mod_thickness; + /* 62 (Unbuffered) Reference Raw Card Used */ + unsigned char ref_raw_card; + /* 63 (Unbuffered) Address Mapping from + Edge Connector to DRAM */ + unsigned char addr_mapping; + /* 64-116 (Unbuffered) Reserved */ + unsigned char res_64_116[53]; + } unbuffered; + struct { + /* 60 (Registered) Module Nominal Height */ + unsigned char mod_height; + /* 61 (Registered) Module Maximum Thickness */ + unsigned char mod_thickness; + /* 62 (Registered) Reference Raw Card Used */ + unsigned char ref_raw_card; + /* 63 DIMM Module Attributes */ + unsigned char modu_attr; + /* 64 RDIMM Thermal Heat Spreader Solution */ + unsigned char thermal; + /* 65 Register Manufacturer ID Code, Least Significant Byte */ + unsigned char reg_id_lo; + /* 66 Register Manufacturer ID Code, Most Significant Byte */ + unsigned char reg_id_hi; + /* 67 Register Revision Number */ + unsigned char reg_rev; + /* 68 Register Type */ + unsigned char reg_type; + /* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */ + unsigned char rcw[8]; + } registered; + unsigned char uc[57]; /* 60-116 Module-Specific Section */ + } mod_section; + + /* Unique Module ID: Bytes 117-125 */ + unsigned char mmid_lsb; /* 117 Module MfgID Code LSB - JEP-106 */ + unsigned char mmid_msb; /* 118 Module MfgID Code MSB - JEP-106 */ + unsigned char mloc; /* 119 Mfg Location */ + unsigned char mdate[2]; /* 120-121 Mfg Date */ + unsigned char sernum[4]; /* 122-125 Module Serial Number */ + + /* CRC: Bytes 126-127 */ + unsigned char crc[2]; /* 126-127 SPD CRC */ + + /* Other Manufacturer Fields and User Space: Bytes 128-255 */ + unsigned char mpart[18]; /* 128-145 Mfg's Module Part Number */ + unsigned char mrev[2]; /* 146-147 Module Revision Code */ + + unsigned char dmid_lsb; /* 148 DRAM MfgID Code LSB - JEP-106 */ + unsigned char dmid_msb; /* 149 DRAM MfgID Code MSB - JEP-106 */ + + unsigned char msd[26]; /* 150-175 Mfg's Specific Data */ + unsigned char cust[80]; /* 176-255 Open for Customer Use */ + +} ddr3_spd_eeprom_t; + +/* From JEEC Standard No. 21-C release 23A */ +struct ddr4_spd_eeprom_s { + /* General Section: Bytes 0-127 */ + uint8_t info_size_crc; /* 0 # bytes */ + uint8_t spd_rev; /* 1 Total # bytes of SPD */ + uint8_t mem_type; /* 2 Key Byte / mem type */ + uint8_t module_type; /* 3 Key Byte / Module Type */ + uint8_t density_banks; /* 4 Density and Banks */ + uint8_t addressing; /* 5 Addressing */ + uint8_t package_type; /* 6 Package type */ + uint8_t opt_feature; /* 7 Optional features */ + uint8_t thermal_ref; /* 8 Thermal and refresh */ + uint8_t oth_opt_features; /* 9 Other optional features */ + uint8_t res_10; /* 10 Reserved */ + uint8_t module_vdd; /* 11 Module nominal voltage */ + uint8_t organization; /* 12 Module Organization */ + uint8_t bus_width; /* 13 Module Memory Bus Width */ + uint8_t therm_sensor; /* 14 Module Thermal Sensor */ + uint8_t ext_type; /* 15 Extended module type */ + uint8_t res_16; + uint8_t timebases; /* 17 MTb and FTB */ + uint8_t tck_min; /* 18 tCKAVGmin */ + uint8_t tck_max; /* 19 TCKAVGmax */ + uint8_t caslat_b1; /* 20 CAS latencies, 1st byte */ + uint8_t caslat_b2; /* 21 CAS latencies, 2nd byte */ + uint8_t caslat_b3; /* 22 CAS latencies, 3rd byte */ + uint8_t caslat_b4; /* 23 CAS latencies, 4th byte */ + uint8_t taa_min; /* 24 Min CAS Latency Time */ + uint8_t trcd_min; /* 25 Min RAS# to CAS# Delay Time */ + uint8_t trp_min; /* 26 Min Row Precharge Delay Time */ + uint8_t tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */ + uint8_t tras_min_lsb; /* 28 tRASmin, lsb */ + uint8_t trc_min_lsb; /* 29 tRCmin, lsb */ + uint8_t trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */ + uint8_t trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */ + uint8_t trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */ + uint8_t trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */ + uint8_t trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */ + uint8_t trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */ + uint8_t tfaw_msb; /* 36 Upper Nibble for tFAW */ + uint8_t tfaw_min; /* 37 tFAW, lsb */ + uint8_t trrds_min; /* 38 tRRD_Smin, MTB */ + uint8_t trrdl_min; /* 39 tRRD_Lmin, MTB */ + uint8_t tccdl_min; /* 40 tCCS_Lmin, MTB */ + uint8_t res_41[60-41]; /* 41 Rserved */ + uint8_t mapping[78-60]; /* 60~77 Connector to SDRAM bit map */ + uint8_t res_78[117-78]; /* 78~116, Reserved */ + int8_t fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */ + int8_t fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */ + int8_t fine_trrds_min; /* 119 Fine offset for tRRD_Smin */ + int8_t fine_trc_min; /* 120 Fine offset for tRCmin */ + int8_t fine_trp_min; /* 121 Fine offset for tRPmin */ + int8_t fine_trcd_min; /* 122 Fine offset for tRCDmin */ + int8_t fine_taa_min; /* 123 Fine offset for tAAmin */ + int8_t fine_tck_max; /* 124 Fine offset for tCKAVGmax */ + int8_t fine_tck_min; /* 125 Fine offset for tCKAVGmin */ + /* CRC: Bytes 126-127 */ + uint8_t crc[2]; /* 126-127 SPD CRC */ + + /* Module-Specific Section: Bytes 128-255 */ + union { + struct { + /* 128 (Unbuffered) Module Nominal Height */ + uint8_t mod_height; + /* 129 (Unbuffered) Module Maximum Thickness */ + uint8_t mod_thickness; + /* 130 (Unbuffered) Reference Raw Card Used */ + uint8_t ref_raw_card; + /* 131 (Unbuffered) Address Mapping from + Edge Connector to DRAM */ + uint8_t addr_mapping; + /* 132~253 (Unbuffered) Reserved */ + uint8_t res_132[254-132]; + /* 254~255 CRC */ + uint8_t crc[2]; + } unbuffered; + struct { + /* 128 (Registered) Module Nominal Height */ + uint8_t mod_height; + /* 129 (Registered) Module Maximum Thickness */ + uint8_t mod_thickness; + /* 130 (Registered) Reference Raw Card Used */ + uint8_t ref_raw_card; + /* 131 DIMM Module Attributes */ + uint8_t modu_attr; + /* 132 RDIMM Thermal Heat Spreader Solution */ + uint8_t thermal; + /* 133 Register Manufacturer ID Code, LSB */ + uint8_t reg_id_lo; + /* 134 Register Manufacturer ID Code, MSB */ + uint8_t reg_id_hi; + /* 135 Register Revision Number */ + uint8_t reg_rev; + /* 136 Address mapping from register to DRAM */ + u8 reg_map; + u8 ca_stren; + u8 clk_stren; + /* 139~253 Reserved */ + u8 res_137[254 - 139]; + /* 254~255 CRC */ + uint8_t crc[2]; + } registered; + struct { + /* 128 (Loadreduced) Module Nominal Height */ + uint8_t mod_height; + /* 129 (Loadreduced) Module Maximum Thickness */ + uint8_t mod_thickness; + /* 130 (Loadreduced) Reference Raw Card Used */ + uint8_t ref_raw_card; + /* 131 DIMM Module Attributes */ + uint8_t modu_attr; + /* 132 RDIMM Thermal Heat Spreader Solution */ + uint8_t thermal; + /* 133 Register Manufacturer ID Code, LSB */ + uint8_t reg_id_lo; + /* 134 Register Manufacturer ID Code, MSB */ + uint8_t reg_id_hi; + /* 135 Register Revision Number */ + uint8_t reg_rev; + /* 136 Address mapping from register to DRAM */ + uint8_t reg_map; + /* 137 Register Output Drive Strength for CMD/Add*/ + uint8_t reg_drv; + /* 138 Register Output Drive Strength for CK */ + uint8_t reg_drv_ck; + /* 139 Data Buffer Revision Number */ + uint8_t data_buf_rev; + /* 140 DRAM VrefDQ for Package Rank 0 */ + uint8_t vrefqe_r0; + /* 141 DRAM VrefDQ for Package Rank 1 */ + uint8_t vrefqe_r1; + /* 142 DRAM VrefDQ for Package Rank 2 */ + uint8_t vrefqe_r2; + /* 143 DRAM VrefDQ for Package Rank 3 */ + uint8_t vrefqe_r3; + /* 144 Data Buffer VrefDQ for DRAM Interface */ + uint8_t data_intf; + /* + * 145 Data Buffer MDQ Drive Strength and RTT + * for data rate <= 1866 + */ + uint8_t data_drv_1866; + /* + * 146 Data Buffer MDQ Drive Strength and RTT + * for 1866 < data rate <= 2400 + */ + uint8_t data_drv_2400; + /* + * 147 Data Buffer MDQ Drive Strength and RTT + * for 2400 < data rate <= 3200 + */ + uint8_t data_drv_3200; + /* 148 DRAM Drive Strength */ + uint8_t dram_drv; + /* + * 149 DRAM ODT (RTT_WR, RTT_NOM) + * for data rate <= 1866 + */ + uint8_t dram_odt_1866; + /* + * 150 DRAM ODT (RTT_WR, RTT_NOM) + * for 1866 < data rate <= 2400 + */ + uint8_t dram_odt_2400; + /* + * 151 DRAM ODT (RTT_WR, RTT_NOM) + * for 2400 < data rate <= 3200 + */ + uint8_t dram_odt_3200; + /* + * 152 DRAM ODT (RTT_PARK) + * for data rate <= 1866 + */ + uint8_t dram_odt_park_1866; + /* + * 153 DRAM ODT (RTT_PARK) + * for 1866 < data rate <= 2400 + */ + uint8_t dram_odt_park_2400; + /* + * 154 DRAM ODT (RTT_PARK) + * for 2400 < data rate <= 3200 + */ + uint8_t dram_odt_park_3200; + uint8_t res_155[254-155]; /* Reserved */ + /* 254~255 CRC */ + uint8_t crc[2]; + } loadreduced; + uint8_t uc[128]; /* 128-255 Module-Specific Section */ + } mod_section; + + uint8_t res_256[320-256]; /* 256~319 Reserved */ + + /* Module supplier's data: Byte 320~383 */ + uint8_t mmid_lsb; /* 320 Module MfgID Code LSB */ + uint8_t mmid_msb; /* 321 Module MfgID Code MSB */ + uint8_t mloc; /* 322 Mfg Location */ + uint8_t mdate[2]; /* 323~324 Mfg Date */ + uint8_t sernum[4]; /* 325~328 Module Serial Number */ + uint8_t mpart[20]; /* 329~348 Mfg's Module Part Number */ + uint8_t mrev; /* 349 Module Revision Code */ + uint8_t dmid_lsb; /* 350 DRAM MfgID Code LSB */ + uint8_t dmid_msb; /* 351 DRAM MfgID Code MSB */ + uint8_t stepping; /* 352 DRAM stepping */ + uint8_t msd[29]; /* 353~381 Mfg's Specific Data */ + uint8_t res_382[2]; /* 382~383 Reserved */ + + uint8_t user[512-384]; /* 384~511 End User Programmable */ +}; + +extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd); +extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd); +extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd); +extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd); +extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); +unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd); + +/* + * Byte 2 Fundamental Memory Types. + */ +#define SPD_MEMTYPE_FPM (0x01) +#define SPD_MEMTYPE_EDO (0x02) +#define SPD_MEMTYPE_PIPE_NIBBLE (0x03) +#define SPD_MEMTYPE_SDRAM (0x04) +#define SPD_MEMTYPE_ROM (0x05) +#define SPD_MEMTYPE_SGRAM (0x06) +#define SPD_MEMTYPE_DDR (0x07) +#define SPD_MEMTYPE_DDR2 (0x08) +#define SPD_MEMTYPE_DDR2_FBDIMM (0x09) +#define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A) +#define SPD_MEMTYPE_DDR3 (0x0B) +#define SPD_MEMTYPE_DDR4 (0x0C) + +/* DIMM Type for DDR2 SPD (according to v1.3) */ +#define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00) +#define DDR2_SPD_DIMMTYPE_RDIMM (0x01) +#define DDR2_SPD_DIMMTYPE_UDIMM (0x02) +#define DDR2_SPD_DIMMTYPE_SO_DIMM (0x04) +#define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM (0x06) +#define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM (0x07) +#define DDR2_SPD_DIMMTYPE_MICRO_DIMM (0x08) +#define DDR2_SPD_DIMMTYPE_MINI_RDIMM (0x10) +#define DDR2_SPD_DIMMTYPE_MINI_UDIMM (0x20) + +/* Byte 3 Key Byte / Module Type for DDR3 SPD */ +#define DDR3_SPD_MODULETYPE_MASK (0x0f) +#define DDR3_SPD_MODULETYPE_RDIMM (0x01) +#define DDR3_SPD_MODULETYPE_UDIMM (0x02) +#define DDR3_SPD_MODULETYPE_SO_DIMM (0x03) +#define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04) +#define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05) +#define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06) +#define DDR3_SPD_MODULETYPE_MINI_CDIMM (0x07) +#define DDR3_SPD_MODULETYPE_72B_SO_UDIMM (0x08) +#define DDR3_SPD_MODULETYPE_72B_SO_RDIMM (0x09) +#define DDR3_SPD_MODULETYPE_72B_SO_CDIMM (0x0A) +#define DDR3_SPD_MODULETYPE_LRDIMM (0x0B) +#define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C) +#define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D) + +/* DIMM Type for DDR4 SPD */ +#define DDR4_SPD_MODULETYPE_MASK (0x0f) +#define DDR4_SPD_MODULETYPE_EXT (0x00) +#define DDR4_SPD_MODULETYPE_RDIMM (0x01) +#define DDR4_SPD_MODULETYPE_UDIMM (0x02) +#define DDR4_SPD_MODULETYPE_SO_DIMM (0x03) +#define DDR4_SPD_MODULETYPE_LRDIMM (0x04) +#define DDR4_SPD_MODULETYPE_MINI_RDIMM (0x05) +#define DDR4_SPD_MODULETYPE_MINI_UDIMM (0x06) +#define DDR4_SPD_MODULETYPE_72B_SO_UDIMM (0x08) +#define DDR4_SPD_MODULETYPE_72B_SO_RDIMM (0x09) +#define DDR4_SPD_MODULETYPE_16B_SO_DIMM (0x0C) +#define DDR4_SPD_MODULETYPE_32B_SO_DIMM (0x0D) + +#endif /* _DDR_SPD_H_ */ diff --git a/roms/u-boot/include/debug_uart.h b/roms/u-boot/include/debug_uart.h new file mode 100644 index 000000000..714b369e6 --- /dev/null +++ b/roms/u-boot/include/debug_uart.h @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Early debug UART support + * + * (C) Copyright 2014 Google, Inc + * Writte by Simon Glass + */ + +#ifndef _DEBUG_UART_H +#define _DEBUG_UART_H + +/* + * The debug UART is intended for use very early in U-Boot to debug problems + * when an ICE or other debug mechanism is not available. + * + * To use it you should: + * - Make sure your UART supports this interface + * - Enable CONFIG_DEBUG_UART + * - Enable the CONFIG for your UART to tell it to provide this interface + * (e.g. CONFIG_DEBUG_UART_NS16550) + * - Define the required settings as needed (see below) + * - Call debug_uart_init() before use + * - Call printch() to output a character + * + * Depending on your platform it may be possible to use this UART before a + * stack is available. + * + * If your UART does not support this interface you can probably add support + * quite easily. Remember that you cannot use driver model and it is preferred + * to use no stack. + * + * You must not use this UART once driver model is working and the serial + * drivers are up and running (done in serial_init()). Otherwise the drivers + * may conflict and you will get strange output. + * + * + * To enable the debug UART in your serial driver: + * + * - #include + * - Define _debug_uart_init(), trying to avoid using the stack + * - Define _debug_uart_putc() as static inline (avoiding stack usage) + * - Immediately afterwards, add DEBUG_UART_FUNCS to define the rest of the + * functionality (printch(), etc.) + * + * If your board needs additional init for the UART to work, enable + * CONFIG_DEBUG_UART_BOARD_INIT and write a function called + * board_debug_uart_init() to perform that init. When debug_uart_init() is + * called, the init will happen automatically. + */ + +/** + * debug_uart_init() - Set up the debug UART ready for use + * + * This sets up the UART with the correct baud rate, etc. + * + * Available CONFIG is: + * + * - CONFIG_DEBUG_UART_BASE: Base address of UART + * - CONFIG_BAUDRATE: Requested baud rate + * - CONFIG_DEBUG_UART_CLOCK: Input clock for UART + */ +void debug_uart_init(void); + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void); +#else +static inline void board_debug_uart_init(void) +{ +} +#endif + +/** + * printch() - Output a character to the debug UART + * + * @ch: Character to output + */ +void printch(int ch); + +/** + * printascii() - Output an ASCII string to the debug UART + * + * @str: String to output + */ +void printascii(const char *str); + +/** + * printhex2() - Output a 2-digit hex value + * + * @value: Value to output + */ +void printhex2(unsigned int value); + +/** + * printhex4() - Output a 4-digit hex value + * + * @value: Value to output + */ +void printhex4(unsigned int value); + +/** + * printhex8() - Output a 8-digit hex value + * + * @value: Value to output + */ +void printhex8(unsigned int value); + +/** + * printdec() - Output a decimalism value + * + * @value: Value to output + */ +void printdec(unsigned int value); + +#ifdef CONFIG_DEBUG_UART_ANNOUNCE +#define _DEBUG_UART_ANNOUNCE printascii("\n\n"); +#else +#define _DEBUG_UART_ANNOUNCE +#endif + +#define serial_dout(reg, value) \ + serial_out_shift((char *)com_port + \ + ((char *)reg - (char *)com_port) * \ + (1 << CONFIG_DEBUG_UART_SHIFT), \ + CONFIG_DEBUG_UART_SHIFT, value) +#define serial_din(reg) \ + serial_in_shift((char *)com_port + \ + ((char *)reg - (char *)com_port) * \ + (1 << CONFIG_DEBUG_UART_SHIFT), \ + CONFIG_DEBUG_UART_SHIFT) + +/* + * Now define some functions - this should be inserted into the serial driver + */ +#define DEBUG_UART_FUNCS \ +\ + static inline void _printch(int ch) \ + { \ + if (ch == '\n') \ + _debug_uart_putc('\r'); \ + _debug_uart_putc(ch); \ + } \ +\ + void printch(int ch) \ + { \ + _printch(ch); \ + } \ +\ + void printascii(const char *str) \ + { \ + while (*str) \ + _printch(*str++); \ + } \ +\ + static inline void printhex1(unsigned int digit) \ + { \ + digit &= 0xf; \ + _debug_uart_putc(digit > 9 ? digit - 10 + 'a' : digit + '0'); \ + } \ +\ + static inline void printhex(unsigned int value, int digits) \ + { \ + while (digits-- > 0) \ + printhex1(value >> (4 * digits)); \ + } \ +\ + void printhex2(unsigned int value) \ + { \ + printhex(value, 2); \ + } \ +\ + void printhex4(unsigned int value) \ + { \ + printhex(value, 4); \ + } \ +\ + void printhex8(unsigned int value) \ + { \ + printhex(value, 8); \ + } \ +\ + void printdec(unsigned int value) \ + { \ + if (value > 10) { \ + printdec(value / 10); \ + value %= 10; \ + } else if (value == 10) { \ + _debug_uart_putc('1'); \ + value = 0; \ + } \ + _debug_uart_putc('0' + value); \ + } \ +\ + void debug_uart_init(void) \ + { \ + board_debug_uart_init(); \ + _debug_uart_init(); \ + _DEBUG_UART_ANNOUNCE \ + } \ + +#endif diff --git a/roms/u-boot/include/dfu.h b/roms/u-boot/include/dfu.h new file mode 100644 index 000000000..d18b70172 --- /dev/null +++ b/roms/u-boot/include/dfu.h @@ -0,0 +1,554 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * dfu.h - DFU flashable area description + * + * Copyright (C) 2012 Samsung Electronics + * authors: Andrzej Pietrasiewicz + * Lukasz Majewski + */ + +#ifndef __DFU_ENTITY_H_ +#define __DFU_ENTITY_H_ + +#include +#include +#include +#include +#include + +enum dfu_device_type { + DFU_DEV_MMC = 1, + DFU_DEV_ONENAND, + DFU_DEV_NAND, + DFU_DEV_RAM, + DFU_DEV_SF, + DFU_DEV_MTD, + DFU_DEV_VIRT, +}; + +enum dfu_layout { + DFU_RAW_ADDR = 1, + DFU_FS_FAT, + DFU_FS_EXT2, + DFU_FS_EXT3, + DFU_FS_EXT4, + DFU_RAM_ADDR, + DFU_SKIP, + DFU_SCRIPT, +}; + +enum dfu_op { + DFU_OP_READ = 1, + DFU_OP_WRITE, + DFU_OP_SIZE, +}; + +struct mmc_internal_data { + int dev_num; + + /* RAW programming */ + unsigned int lba_start; + unsigned int lba_size; + unsigned int lba_blk_size; + + /* eMMC HW partition access */ + int hw_partition; + + /* FAT/EXT */ + unsigned int dev; + unsigned int part; +}; + +struct mtd_internal_data { + struct mtd_info *info; + + /* RAW programming */ + u64 start; + u64 size; + /* for ubi partition */ + unsigned int ubi; +}; + +struct nand_internal_data { + /* RAW programming */ + u64 start; + u64 size; + + unsigned int dev; + unsigned int part; + /* for nand/ubi use */ + unsigned int ubi; +}; + +struct ram_internal_data { + unsigned long start; + unsigned int size; +}; + +struct sf_internal_data { + struct spi_flash *dev; + + /* RAW programming */ + u64 start; + u64 size; + /* for sf/ubi use */ + unsigned int ubi; +}; + +struct virt_internal_data { + int dev_num; +}; + +#define DFU_NAME_SIZE 32 +#ifndef CONFIG_SYS_DFU_DATA_BUF_SIZE +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024*1024*8) /* 8 MiB */ +#endif +#ifndef CONFIG_SYS_DFU_MAX_FILE_SIZE +#define CONFIG_SYS_DFU_MAX_FILE_SIZE CONFIG_SYS_DFU_DATA_BUF_SIZE +#endif +#ifndef DFU_DEFAULT_POLL_TIMEOUT +#define DFU_DEFAULT_POLL_TIMEOUT 0 +#endif +#ifndef DFU_MANIFEST_POLL_TIMEOUT +#define DFU_MANIFEST_POLL_TIMEOUT DFU_DEFAULT_POLL_TIMEOUT +#endif + +struct dfu_entity { + char name[DFU_NAME_SIZE]; + int alt; + void *dev_private; + enum dfu_device_type dev_type; + enum dfu_layout layout; + unsigned long max_buf_size; + + union { + struct mmc_internal_data mmc; + struct mtd_internal_data mtd; + struct nand_internal_data nand; + struct ram_internal_data ram; + struct sf_internal_data sf; + struct virt_internal_data virt; + } data; + + int (*get_medium_size)(struct dfu_entity *dfu, u64 *size); + + int (*read_medium)(struct dfu_entity *dfu, + u64 offset, void *buf, long *len); + + int (*write_medium)(struct dfu_entity *dfu, + u64 offset, void *buf, long *len); + + int (*flush_medium)(struct dfu_entity *dfu); + unsigned int (*poll_timeout)(struct dfu_entity *dfu); + + void (*free_entity)(struct dfu_entity *dfu); + + struct list_head list; + + /* on the fly state */ + u32 crc; + u64 offset; + int i_blk_seq_num; + u8 *i_buf; + u8 *i_buf_start; + u8 *i_buf_end; + u64 r_left; + long b_left; + + u32 bad_skip; /* for nand use */ + + unsigned int inited:1; +}; + +struct list_head; +extern struct list_head dfu_list; + +#ifdef CONFIG_SET_DFU_ALT_INFO +/** + * set_dfu_alt_info() - set dfu_alt_info environment variable + * + * If CONFIG_SET_DFU_ALT_INFO=y, this board specific function is called to set + * environment variable dfu_alt_info. + * + * @interface: dfu interface, e.g. "mmc" or "nand" + * @devstr: device number as string + */ +void set_dfu_alt_info(char *interface, char *devstr); +#endif + +/** + * dfu_alt_init() - initialize buffer for dfu entities + * + * @num: number of entities + * @dfu: on return allocated buffer + * Return: 0 on success + */ +int dfu_alt_init(int num, struct dfu_entity **dfu); + +/** + * dfu_alt_add() - add alternate to dfu entity buffer + * + * @dfu: dfu entity + * @interface: dfu interface, e.g. "mmc" or "nand" + * @devstr: device number as string + * @s: string description of alternate + * Return: 0 on success + */ +int dfu_alt_add(struct dfu_entity *dfu, char *interface, char *devstr, char *s); + +/** + * dfu_config_entities() - initialize dfu entitities from envirionment + * + * Initialize the list of dfu entities from environment variable dfu_alt_info. + * The list must be freed by calling dfu_free_entities(). This function bypasses + * set_dfu_alt_info(). So typically you should use dfu_init_env_entities() + * instead. + * + * See function :c:func:`dfu_free_entities` + * See function :c:func:`dfu_init_env_entities` + * + * @s: string with alternates + * @interface: interface, e.g. "mmc" or "nand" + * @devstr: device number as string + * Return: 0 on success, a negative error code otherwise + */ +int dfu_config_entities(char *s, char *interface, char *devstr); + +/** + * dfu_free_entities() - free the list of dfu entities + * + * Free the internal list of dfu entities. + * + * See function :c:func:`dfu_init_env_entities` + */ +void dfu_free_entities(void); + +/** + * dfu_show_entities() - print DFU alt settings list + */ +void dfu_show_entities(void); + +/** + * dfu_get_alt_number() - get number of alternates + * + * Return: number of alternates in the dfu entities list + */ +int dfu_get_alt_number(void); + +/** + * dfu_get_dev_type() - get string representation for dfu device type + * + * @type: device type + * Return: string representation for device type + */ +const char *dfu_get_dev_type(enum dfu_device_type type); + +/** + * dfu_get_layout() - get string describing layout + * + * Internally layouts are represented by enum dfu_device_type values. This + * function translates an enum value to a human readable string, e.g. DFU_FS_FAT + * is translated to "FAT". + * + * @layout: layout + * Result: string representation for the layout + */ +const char *dfu_get_layout(enum dfu_layout layout); + +/** + * dfu_get_entity() - get dfu entity for an alternate id + * + * @alt: alternate id + * Return: dfu entity + */ +struct dfu_entity *dfu_get_entity(int alt); + +char *dfu_extract_token(char** e, int *n); + +/** + * dfu_get_alt() - get alternate id for filename + * + * Environment variable dfu_alt_info defines the write destinations (alternates) + * for different filenames. This function get the index of the alternate for + * a filename. If an absolute filename is provided (starting with '/'), the + * directory path is ignored. + * + * @name: filename + * Return: id of the alternate or negative error number (-ENODEV) + */ +int dfu_get_alt(char *name); + +/** + * dfu_init_env_entities() - initialize dfu entitities from envirionment + * + * Initialize the list of dfu entities from environment variable dfu_alt_info. + * The list must be freed by calling dfu_free_entities(). + * @interface and @devstr are used to select the relevant set of alternates + * from environment variable dfu_alt_info. + * + * If environment variable dfu_alt_info specifies the interface and the device, + * use NULL for @interface and @devstr. + * + * See function :c:func:`dfu_free_entities` + * + * @interface: interface, e.g. "mmc" or "nand" + * @devstr: device number as string + * Return: 0 on success, a negative error code otherwise + */ +int dfu_init_env_entities(char *interface, char *devstr); + +unsigned char *dfu_get_buf(struct dfu_entity *dfu); +unsigned char *dfu_free_buf(void); +unsigned long dfu_get_buf_size(void); +bool dfu_usb_get_reset(void); + +#ifdef CONFIG_DFU_TIMEOUT +unsigned long dfu_get_timeout(void); +void dfu_set_timeout(unsigned long); +#endif + +/** + * dfu_read() - read from dfu entity + * + * The block sequence number @blk_seq_num is a 16 bit counter that must be + * incremented with each call for the same dfu entity @de. + * + * @de: dfu entity + * @buf: buffer + * @size: size of buffer + * @blk_seq_num: block sequence number + * Return: 0 for success, -1 for error + */ +int dfu_read(struct dfu_entity *de, void *buf, int size, int blk_seq_num); + +/** + * dfu_write() - write to dfu entity + * + * Write the contents of a buffer @buf to the dfu entity @de. After writing + * the last block call dfu_flush(). If a file is already loaded completely + * into memory it is preferable to use dfu_write_from_mem_addr() which takes + * care of blockwise transfer and flushing. + * + * The block sequence number @blk_seq_num is a 16 bit counter that must be + * incremented with each call for the same dfu entity @de. + * + * See function :c:func:`dfu_flush` + * See function :c:func:`dfu_write_from_mem_addr` + * + * @de: dfu entity + * @buf: buffer + * @size: size of buffer + * @blk_seq_num: block sequence number + * Return: 0 for success, -1 for error + */ +int dfu_write(struct dfu_entity *de, void *buf, int size, int blk_seq_num); + +/** + * dfu_flush() - flush to dfu entity + * + * This function has to be called after writing the last block to the dfu + * entity @de. + * + * The block sequence number @blk_seq_num is a 16 bit counter that must be + * incremented with each call for the same dfu entity @de. + * + * See function :c:func:`dfu_write` + * + * @de: dfu entity + * @buf: ignored + * @size: ignored + * @blk_seq_num: block sequence number of last write - ignored + * Return: 0 for success, -1 for error + */ +int dfu_flush(struct dfu_entity *de, void *buf, int size, int blk_seq_num); + +/** + * dfu_initiated_callback() - weak callback called on DFU transaction start + * + * It is a callback function called by DFU stack when a DFU transaction is + * initiated. This function allows to manage some board specific behavior on + * DFU targets. + * + * @dfu: pointer to the dfu_entity, which should be initialized + */ +void dfu_initiated_callback(struct dfu_entity *dfu); + +/** + * dfu_flush_callback() - weak callback called at the end of the DFU write + * + * It is a callback function called by DFU stack after DFU manifestation. + * This function allows to manage some board specific behavior on DFU targets + * + * @dfu: pointer to the dfu_entity, which should be flushed + */ +void dfu_flush_callback(struct dfu_entity *dfu); + +int dfu_transaction_initiate(struct dfu_entity *dfu, bool read); +void dfu_transaction_cleanup(struct dfu_entity *dfu); + +/* + * dfu_defer_flush - pointer to store dfu_entity for deferred flashing. + * It should be NULL when not used. + */ +extern struct dfu_entity *dfu_defer_flush; + +/** + * dfu_get_defer_flush() - get current value of dfu_defer_flush pointer + * + * Return: value of the dfu_defer_flush pointer + */ +static inline struct dfu_entity *dfu_get_defer_flush(void) +{ + return dfu_defer_flush; +} + +/** + * dfu_set_defer_flush() - set the dfu_defer_flush pointer + * + * @dfu: pointer to the dfu_entity, which should be written + */ +static inline void dfu_set_defer_flush(struct dfu_entity *dfu) +{ + dfu_defer_flush = dfu; +} + +/** + * dfu_write_from_mem_addr() - write data from memory to DFU managed medium + * + * This function adds support for writing data starting from fixed memory + * address (like $loadaddr) to dfu managed medium (e.g. NAND, MMC, file system) + * + * @dfu: dfu entity to which we want to store data + * @buf: fixed memory address from where data starts + * @size: number of bytes to write + * + * Return: 0 on success, other value on failure + */ +int dfu_write_from_mem_addr(struct dfu_entity *dfu, void *buf, int size); + +/* Device specific */ +#if CONFIG_IS_ENABLED(DFU_MMC) +extern int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr, char *s); +#else +static inline int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr, + char *s) +{ + puts("MMC support not available!\n"); + return -1; +} +#endif + +#if CONFIG_IS_ENABLED(DFU_NAND) +extern int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr, char *s); +#else +static inline int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr, + char *s) +{ + puts("NAND support not available!\n"); + return -1; +} +#endif + +#if CONFIG_IS_ENABLED(DFU_RAM) +extern int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr, char *s); +#else +static inline int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr, + char *s) +{ + puts("RAM support not available!\n"); + return -1; +} +#endif + +#if CONFIG_IS_ENABLED(DFU_SF) +extern int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr, char *s); +#else +static inline int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr, + char *s) +{ + puts("SF support not available!\n"); + return -1; +} +#endif + +#if CONFIG_IS_ENABLED(DFU_MTD) +int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char *s); +#else +static inline int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, + char *s) +{ + puts("MTD support not available!\n"); + return -1; +} +#endif + +#ifdef CONFIG_DFU_VIRT +int dfu_fill_entity_virt(struct dfu_entity *dfu, char *devstr, char *s); +int dfu_write_medium_virt(struct dfu_entity *dfu, u64 offset, + void *buf, long *len); +int dfu_get_medium_size_virt(struct dfu_entity *dfu, u64 *size); +int dfu_read_medium_virt(struct dfu_entity *dfu, u64 offset, + void *buf, long *len); +#else +static inline int dfu_fill_entity_virt(struct dfu_entity *dfu, char *devstr, + char *s) +{ + puts("VIRT support not available!\n"); + return -1; +} +#endif + +extern bool dfu_reinit_needed; + +#if CONFIG_IS_ENABLED(DFU_WRITE_ALT) +/** + * dfu_write_by_name() - write data to DFU medium + * @dfu_entity_name: Name of DFU entity to write + * @addr: Address of data buffer to write + * @len: Number of bytes + * @interface: Destination DFU medium (e.g. "mmc") + * @devstring: Instance number of destination DFU medium (e.g. "1") + * + * This function is storing data received on DFU supported medium which + * is specified by @dfu_entity_name. + * + * Return: 0 - on success, error code - otherwise + */ +int dfu_write_by_name(char *dfu_entity_name, void *addr, + unsigned int len, char *interface, char *devstring); + +/** + * dfu_write_by_alt() - write data to DFU medium + * @dfu_alt_num: DFU alt setting number + * @addr: Address of data buffer to write + * @len: Number of bytes + * @interface: Destination DFU medium (e.g. "mmc") + * @devstring: Instance number of destination DFU medium (e.g. "1") + * + * This function is storing data received on DFU supported medium which + * is specified by @dfu_alt_name. + * + * Return: 0 - on success, error code - otherwise + */ +int dfu_write_by_alt(int dfu_alt_num, void *addr, unsigned int len, + char *interface, char *devstring); +#else +static inline int dfu_write_by_name(char *dfu_entity_name, void *addr, + unsigned int len, char *interface, + char *devstring) +{ + puts("write support for DFU not available!\n"); + return -ENOSYS; +} + +static inline int dfu_write_by_alt(int dfu_alt_num, void *addr, + unsigned int len, char *interface, + char *devstring) +{ + puts("write support for DFU not available!\n"); + return -ENOSYS; +} +#endif + +int dfu_add(struct usb_configuration *c); +#endif /* __DFU_ENTITY_H_ */ diff --git a/roms/u-boot/include/dialog_pmic.h b/roms/u-boot/include/dialog_pmic.h new file mode 100644 index 000000000..fbfc5360d --- /dev/null +++ b/roms/u-boot/include/dialog_pmic.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * da9053 register declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + */ + +#ifndef __DIALOG_PMIC_H__ +#define __DIALOG_PMIC_H__ + +enum { + DA9053_PAGECON0_REG = 0, + DA9053_STATUSA_REG, + DA9053_STATUSB_REG, + DA9053_STATUSC_REG, + DA9053_STATUSD_REG, + DA9053_EVENTA_REG, + DA9053_EVENTB_REG, + DA9053_EVENTC_REG, + DA9053_EVENTD_REG, + DA9053_FAULTLOG_REG, + DA9053_IRQMASKA_REG, + DA9053_IRQMASKB_REG, + DA9053_IRQMASKC_REG, + DA9053_IRQMASKD_REG, + DA9053_CONTROLA_REG, + DA9053_CONTROLB_REG, + DA9053_CONTROLC_REG, + DA9053_CONTROLD_REG, + DA9053_PDDIS_REG, + DA9053_INTERFACE_REG, + DA9053_RESET_REG, + DA9053_GPIO0001_REG, + DA9053_GPIO0203_REG, + DA9053_GPIO0405_REG, + DA9053_GPIO0607_REG, + DA9053_GPIO0809_REG, + DA9053_GPIO1011_REG, + DA9053_GPIO1213_REG, + DA9053_GPIO1415_REG, + DA9053_ID01_REG, + DA9053_ID23_REG, + DA9053_ID45_REG, + DA9053_ID67_REG, + DA9053_ID89_REG, + DA9053_ID1011_REG, + DA9053_ID1213_REG, + DA9053_ID1415_REG, + DA9053_ID1617_REG, + DA9053_ID1819_REG, + DA9053_ID2021_REG, + DA9053_SEQSTATUS_REG, + DA9053_SEQA_REG, + DA9053_SEQB_REG, + DA9053_SEQTIMER_REG, + DA9053_BUCKA_REG, + DA9053_BUCKB_REG, + DA9053_BUCKCORE_REG, + DA9053_BUCKPRO_REG, + DA9053_BUCKMEM_REG, + DA9053_BUCKPERI_REG, + DA9053_LDO1_REG, + DA9053_LDO2_REG, + DA9053_LDO3_REG, + DA9053_LDO4_REG, + DA9053_LDO5_REG, + DA9053_LDO6_REG, + DA9053_LDO7_REG, + DA9053_LDO8_REG, + DA9053_LDO9_REG, + DA9053_LDO10_REG, + DA9053_SUPPLY_REG, + DA9053_PULLDOWN_REG, + DA9053_CHGBUCK_REG, + DA9053_WAITCONT_REG, + DA9053_ISET_REG, + DA9053_BATCHG_REG, + DA9053_CHGCONT_REG, + DA9053_INPUTCONT_REG, + DA9053_CHGTIME_REG, + DA9053_BBATCONT_REG, + DA9053_BOOST_REG, + DA9053_LEDCONT_REG, + DA9053_LEDMIN123_REG, + DA9053_LED1CONF_REG, + DA9053_LED2CONF_REG, + DA9053_LED3CONF_REG, + DA9053_LED1CONT_REG, + DA9053_LED2CONT_REG, + DA9053_LED3CONT_REG, + DA9053_LED4CONT_REG, + DA9053_LED5CONT_REG, + DA9053_ADCMAN_REG, + DA9053_ADCCONT_REG, + DA9053_ADCRESL_REG, + DA9053_ADCRESH_REG, + DA9053_VDDRES_REG, + DA9053_VDDMON_REG, + DA9053_ICHGAV_REG, + DA9053_ICHGTHD_REG, + DA9053_ICHGEND_REG, + DA9053_TBATRES_REG, + DA9053_TBATHIGHP_REG, + DA9053_TBATHIGHIN_REG, + DA9053_TBATLOW_REG, + DA9053_TOFFSET_REG, + DA9053_ADCIN4RES_REG, + DA9053_AUTO4HIGH_REG, + DA9053_AUTO4LOW_REG, + DA9053_ADCIN5RES_REG, + DA9053_AUTO5HIGH_REG, + DA9053_AUTO5LOW_REG, + DA9053_ADCIN6RES_REG, + DA9053_AUTO6HIGH_REG, + DA9053_AUTO6LOW_REG, + DA9053_TJUNCRES_REG, + DA9053_TSICONTA_REG, + DA9053_TSICONTB_REG, + DA9053_TSIXMSB_REG, + DA9053_TSIYMSB_REG, + DA9053_TSILSB_REG, + DA9053_TSIZMSB_REG, + DA9053_COUNTS_REG, + DA9053_COUNTMI_REG, + DA9053_COUNTH_REG, + DA9053_COUNTD_REG, + DA9053_COUNTMO_REG, + DA9053_COUNTY_REG, + DA9053_ALARMMI_REG, + DA9053_ALARMH_REG, + DA9053_ALARMD_REG, + DA9053_ALARMMO_REG, + DA9053_ALARMY_REG, + DA9053_SECONDA_REG, + DA9053_SECONDB_REG, + DA9053_SECONDC_REG, + DA9053_SECONDD_REG, + DA9053_PAGECON128_REG, + DA9053_CHIPID_REG, + DA9053_CONFIGID_REG, + DA9053_OTPCONT_REG, + DA9053_OSCTRIM_REG, + DA9053_GPID0_REG, + DA9053_GPID1_REG, + DA9053_GPID2_REG, + DA9053_GPID3_REG, + DA9053_GPID4_REG, + DA9053_GPID5_REG, + DA9053_GPID6_REG, + DA9053_GPID7_REG, + DA9053_GPID8_REG, + DA9053_GPID9_REG, + DIALOG_NUM_OF_REGS, +}; + +#define DA_BUCKCORE_VBCORE_1_250V 0x1E + +/* BUCKCORE REGISTER */ +#define DA9052_BUCKCORE_BCORECONF (1 << 7) +#define DA9052_BUCKCORE_BCOREEN (1 << 6) +#define DA9052_BUCKCORE_VBCORE 63 + +/* SUPPLY REGISTER */ +#define DA9052_SUPPLY_VLOCK (1 << 7) +#define DA9052_SUPPLY_VMEMSWEN (1 << 6) +#define DA9052_SUPPLY_VPERISWEN (1 << 5) +#define DA9052_SUPPLY_VLDO3GO (1 << 4) +#define DA9052_SUPPLY_VLDO2GO (1 << 3) +#define DA9052_SUPPLY_VBMEMGO (1 << 2) +#define DA9052_SUPPLY_VBPROGO (1 << 1) +#define DA9052_SUPPLY_VBCOREGO (1 << 0) + +#endif /* __DIALOG_PMIC_H__ */ diff --git a/roms/u-boot/include/display.h b/roms/u-boot/include/display.h new file mode 100644 index 000000000..66294616e --- /dev/null +++ b/roms/u-boot/include/display.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Google Inc. + */ + +#ifndef _DISPLAY_H +#define _DISPLAY_H + +struct udevice; +struct display_timing; + +/** + * Display uclass platform data for each device + * + * @source_id: ID for the source of the display data, typically a video + * controller + * @src_dev: Source device providing the video + * @in_use: Display is being used + */ +struct display_plat { + int source_id; + struct udevice *src_dev; + bool in_use; +}; + +/** + * display_read_timing() - Read timing information + * + * @dev: Device to read from + * @return 0 if OK, -ve on error + */ +int display_read_timing(struct udevice *dev, struct display_timing *timing); + +/** + * display_port_enable() - Enable a display port device + * + * @dev: Device to enable + * @panel_bpp: Number of bits per pixel for panel + * @timing: Display timings + * @return 0 if OK, -ve on error + */ +int display_enable(struct udevice *dev, int panel_bpp, + const struct display_timing *timing); + +/** + * display_in_use() - Check if a display is in use by any device + * + * @return true if the device is in use (display_enable() has been called + * successfully), else false + */ +bool display_in_use(struct udevice *dev); + +struct dm_display_ops { + /** + * read_timing() - Read information directly + * + * @dev: Device to read from + * @timing: Display timings + * @return 0 if OK, -ve on error + */ + int (*read_timing)(struct udevice *dev, struct display_timing *timing); + + /** + * read_edid() - Read information from EDID + * + * @dev: Device to read from + * @buf: Buffer to read into (should be EDID_SIZE bytes) + * @buf_size: Buffer size (should be EDID_SIZE) + * @return number of bytes read, <=0 for error + */ + int (*read_edid)(struct udevice *dev, u8 *buf, int buf_size); + + /** + * enable() - Enable the display port device + * + * @dev: Device to enable + * @panel_bpp: Number of bits per pixel for panel + * @timing: Display timings + * @return 0 if OK, -ve on error + */ + int (*enable)(struct udevice *dev, int panel_bpp, + const struct display_timing *timing); + + /** + * mode_valid() - Check if mode is supported + * + * @dev: Device to enable + * @timing: Display timings + * @return true if supported, false if not + */ + bool (*mode_valid)(struct udevice *dev, + const struct display_timing *timing); +}; + +#define display_get_ops(dev) ((struct dm_display_ops *)(dev)->driver->ops) + +#endif diff --git a/roms/u-boot/include/display_options.h b/roms/u-boot/include/display_options.h new file mode 100644 index 000000000..049688e39 --- /dev/null +++ b/roms/u-boot/include/display_options.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Google, Inc + * + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef __DISPLAY_OPTIONS_H +#define __DISPLAY_OPTIONS_H + +/** + * print_size() - Print a size with a suffix + * + * Print sizes as "xxx KiB", "xxx.y KiB", "xxx MiB", "xxx.y MiB", + * xxx GiB, xxx.y GiB, etc as needed; allow for optional trailing string + * (like "\n") + * + * @size: Size to print + * @suffix String to print after the size + */ +void print_size(uint64_t size, const char *suffix); + +/** + * print_freq() - Print a frequency with a suffix + * + * Print frequencies as "x.xx GHz", "xxx kHz", etc as needed; allow for + * optional trailing string (like "\n") + * + * @freq: Frequency to print in Hz + * @suffix String to print after the frequency + */ +void print_freq(uint64_t freq, const char *suffix); + +/** + * print_buffer() - Print data buffer in hex and ascii form + * + * Data reads are buffered so that each memory address is only read once. + * This is useful when displaying the contents of volatile registers. + * + * @addr: Starting address to display at start of line + * @data: pointer to data buffer + * @width: data value width. May be 1, 2, or 4. + * @count: number of values to display + * @linelen: Number of values to print per line; specify 0 for default length + */ +int print_buffer(ulong addr, const void *data, uint width, uint count, + uint linelen); + +/** + * display_options() - display the version string / build tag + * + * This displays the U-Boot version string. If a build tag is available this + * is displayed also. + */ +int display_options(void); + +/* Suggested length of the buffer to pass to display_options_get_banner() */ +#define DISPLAY_OPTIONS_BANNER_LENGTH 200 + +/** + * display_options_get_banner() - Get the U-Boot banner as a string + * + * This returns the U-Boot banner string + * + * @newlines: true to include two newlines at the start + * @buf: place to put string + * @size: Size of buf (string is truncated to fit) + * @return buf + */ +char *display_options_get_banner(bool newlines, char *buf, int size); + +/* This function is used for testing only */ +char *display_options_get_banner_priv(bool newlines, const char *build_tag, + char *buf, int size); + +#endif diff --git a/roms/u-boot/include/div64.h b/roms/u-boot/include/div64.h new file mode 100644 index 000000000..8b92d2b18 --- /dev/null +++ b/roms/u-boot/include/div64.h @@ -0,0 +1,244 @@ +#ifndef _ASM_GENERIC_DIV64_H +#define _ASM_GENERIC_DIV64_H +/* + * Copyright (C) 2003 Bernardo Innocenti + * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h + * + * Optimization for constant divisors on 32-bit machines: + * Copyright (C) 2006-2015 Nicolas Pitre + * + * The semantics of do_div() are: + * + * u32 do_div(u64 *n, u32 base) + * { + * u32 remainder = *n % base; + * *n = *n / base; + * return remainder; + * } + * + * NOTE: macro parameter n is evaluated multiple times, + * beware of side effects! + */ + +#include +#include + +#if BITS_PER_LONG == 64 + +# define do_div(n,base) ({ \ + u32 __base = (base); \ + u32 __rem; \ + __rem = ((u64)(n)) % __base; \ + (n) = ((u64)(n)) / __base; \ + __rem; \ + }) + +#elif BITS_PER_LONG == 32 + +#include + +/* + * If the divisor happens to be constant, we determine the appropriate + * inverse at compile time to turn the division into a few inline + * multiplications which ought to be much faster. And yet only if compiling + * with a sufficiently recent gcc version to perform proper 64-bit constant + * propagation. + * + * (It is unfortunate that gcc doesn't perform all this internally.) + */ + +#ifndef __div64_const32_is_OK +#define __div64_const32_is_OK (__GNUC__ >= 4) +#endif + +#define __div64_const32(n, ___b) \ +({ \ + /* \ + * Multiplication by reciprocal of b: n / b = n * (p / b) / p \ + * \ + * We rely on the fact that most of this code gets optimized \ + * away at compile time due to constant propagation and only \ + * a few multiplication instructions should remain. \ + * Hence this monstrous macro (static inline doesn't always \ + * do the trick here). \ + */ \ + u64 ___res, ___x, ___t, ___m, ___n = (n); \ + u32 ___p, ___bias; \ + \ + /* determine MSB of b */ \ + ___p = 1 << ilog2(___b); \ + \ + /* compute m = ((p << 64) + b - 1) / b */ \ + ___m = (~0ULL / ___b) * ___p; \ + ___m += (((~0ULL % ___b + 1) * ___p) + ___b - 1) / ___b; \ + \ + /* one less than the dividend with highest result */ \ + ___x = ~0ULL / ___b * ___b - 1; \ + \ + /* test our ___m with res = m * x / (p << 64) */ \ + ___res = ((___m & 0xffffffff) * (___x & 0xffffffff)) >> 32; \ + ___t = ___res += (___m & 0xffffffff) * (___x >> 32); \ + ___res += (___x & 0xffffffff) * (___m >> 32); \ + ___t = (___res < ___t) ? (1ULL << 32) : 0; \ + ___res = (___res >> 32) + ___t; \ + ___res += (___m >> 32) * (___x >> 32); \ + ___res /= ___p; \ + \ + /* Now sanitize and optimize what we've got. */ \ + if (~0ULL % (___b / (___b & -___b)) == 0) { \ + /* special case, can be simplified to ... */ \ + ___n /= (___b & -___b); \ + ___m = ~0ULL / (___b / (___b & -___b)); \ + ___p = 1; \ + ___bias = 1; \ + } else if (___res != ___x / ___b) { \ + /* \ + * We can't get away without a bias to compensate \ + * for bit truncation errors. To avoid it we'd need an \ + * additional bit to represent m which would overflow \ + * a 64-bit variable. \ + * \ + * Instead we do m = p / b and n / b = (n * m + m) / p. \ + */ \ + ___bias = 1; \ + /* Compute m = (p << 64) / b */ \ + ___m = (~0ULL / ___b) * ___p; \ + ___m += ((~0ULL % ___b + 1) * ___p) / ___b; \ + } else { \ + /* \ + * Reduce m / p, and try to clear bit 31 of m when \ + * possible, otherwise that'll need extra overflow \ + * handling later. \ + */ \ + u32 ___bits = -(___m & -___m); \ + ___bits |= ___m >> 32; \ + ___bits = (~___bits) << 1; \ + /* \ + * If ___bits == 0 then setting bit 31 is unavoidable. \ + * Simply apply the maximum possible reduction in that \ + * case. Otherwise the MSB of ___bits indicates the \ + * best reduction we should apply. \ + */ \ + if (!___bits) { \ + ___p /= (___m & -___m); \ + ___m /= (___m & -___m); \ + } else { \ + ___p >>= ilog2(___bits); \ + ___m >>= ilog2(___bits); \ + } \ + /* No bias needed. */ \ + ___bias = 0; \ + } \ + \ + /* \ + * Now we have a combination of 2 conditions: \ + * \ + * 1) whether or not we need to apply a bias, and \ + * \ + * 2) whether or not there might be an overflow in the cross \ + * product determined by (___m & ((1 << 63) | (1 << 31))). \ + * \ + * Select the best way to do (m_bias + m * n) / (1 << 64). \ + * From now on there will be actual runtime code generated. \ + */ \ + ___res = __arch_xprod_64(___m, ___n, ___bias); \ + \ + ___res /= ___p; \ +}) + +#ifndef __arch_xprod_64 +/* + * Default C implementation for __arch_xprod_64() + * + * Prototype: u64 __arch_xprod_64(const u64 m, u64 n, bool bias) + * Semantic: retval = ((bias ? m : 0) + m * n) >> 64 + * + * The product is a 128-bit value, scaled down to 64 bits. + * Assuming constant propagation to optimize away unused conditional code. + * Architectures may provide their own optimized assembly implementation. + */ +static inline u64 __arch_xprod_64(const u64 m, u64 n, bool bias) +{ + u32 m_lo = m; + u32 m_hi = m >> 32; + u32 n_lo = n; + u32 n_hi = n >> 32; + u64 res, tmp; + + if (!bias) { + res = ((u64)m_lo * n_lo) >> 32; + } else if (!(m & ((1ULL << 63) | (1ULL << 31)))) { + /* there can't be any overflow here */ + res = (m + (u64)m_lo * n_lo) >> 32; + } else { + res = m + (u64)m_lo * n_lo; + tmp = (res < m) ? (1ULL << 32) : 0; + res = (res >> 32) + tmp; + } + + if (!(m & ((1ULL << 63) | (1ULL << 31)))) { + /* there can't be any overflow here */ + res += (u64)m_lo * n_hi; + res += (u64)m_hi * n_lo; + res >>= 32; + } else { + tmp = res += (u64)m_lo * n_hi; + res += (u64)m_hi * n_lo; + tmp = (res < tmp) ? (1ULL << 32) : 0; + res = (res >> 32) + tmp; + } + + res += (u64)m_hi * n_hi; + + return res; +} +#endif + +#ifndef __div64_32 +extern u32 __div64_32(u64 *dividend, u32 divisor); +#endif + +/* The unnecessary pointer compare is there + * to check for type safety (n must be 64bit) + */ +# define do_div(n,base) ({ \ + u32 __base = (base); \ + u32 __rem; \ + (void)(((typeof((n)) *)0) == ((u64 *)0)); \ + if (__builtin_constant_p(__base) && \ + is_power_of_2(__base)) { \ + __rem = (n) & (__base - 1); \ + (n) >>= ilog2(__base); \ + } else if (__div64_const32_is_OK && \ + __builtin_constant_p(__base) && \ + __base != 0) { \ + u32 __res_lo, __n_lo = (n); \ + (n) = __div64_const32(n, __base); \ + /* the remainder can be computed with 32-bit regs */ \ + __res_lo = (n); \ + __rem = __n_lo - __res_lo * __base; \ + } else if (likely(((n) >> 32) == 0)) { \ + __rem = (u32)(n) % __base; \ + (n) = (u32)(n) / __base; \ + } else \ + __rem = __div64_32(&(n), __base); \ + __rem; \ + }) + +#else /* BITS_PER_LONG == ?? */ + +# error do_div() does not yet support the C64 + +#endif /* BITS_PER_LONG */ + +/* Wrapper for do_div(). Doesn't modify dividend and returns + * the result, not remainder. + */ +static inline u64 lldiv(u64 dividend, u32 divisor) +{ + u64 __res = dividend; + do_div(__res, divisor); + return(__res); +} + +#endif /* _ASM_GENERIC_DIV64_H */ diff --git a/roms/u-boot/include/dm-demo.h b/roms/u-boot/include/dm-demo.h new file mode 100644 index 000000000..7b6d0d80f --- /dev/null +++ b/roms/u-boot/include/dm-demo.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2013 Google, Inc + */ + +#ifndef __DM_DEMO_H +#define __DM_DEMO_H + +/** + * struct dm_demo_pdata - configuration data for demo instance + * + * @colour: Color of the demo + * @sides: Numbers of sides + * @default_char: Default ASCII character to output (65 = 'A') + */ +struct dm_demo_pdata { + const char *colour; + int sides; + int default_char; +}; + +struct demo_ops { + int (*hello)(struct udevice *dev, int ch); + int (*status)(struct udevice *dev, int *status); + int (*set_light)(struct udevice *dev, int light); + int (*get_light)(struct udevice *dev); +}; + +int demo_hello(struct udevice *dev, int ch); +int demo_status(struct udevice *dev, int *status); +int demo_set_light(struct udevice *dev, int light); +int demo_get_light(struct udevice *dev); +int demo_list(void); + +int demo_parse_dt(struct udevice *dev); + +#endif diff --git a/roms/u-boot/include/dm.h b/roms/u-boot/include/dm.h new file mode 100644 index 000000000..a1b84169e --- /dev/null +++ b/roms/u-boot/include/dm.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2013 Google, Inc + */ + +#ifdef _DM_H_ +#warning "Suspect dm.h is included from a header file - please fix" +#endif + +#ifndef _DM_H_ +#define _DM_H_ + +#include +#include +#include +#include +#include +#include + +#endif diff --git a/roms/u-boot/include/dm/acpi.h b/roms/u-boot/include/dm/acpi.h new file mode 100644 index 000000000..7f1f2ef2c --- /dev/null +++ b/roms/u-boot/include/dm/acpi.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Core ACPI (Advanced Configuration and Power Interface) support + * + * Copyright 2019 Google LLC + * Written by Simon Glass + */ + +#ifndef __DM_ACPI_H__ +#define __DM_ACPI_H__ + +/* Allow operations to be optional for ACPI */ +#if CONFIG_IS_ENABLED(ACPIGEN) +#define ACPI_OPS_PTR(_ptr) .acpi_ops = _ptr, +#else +#define ACPI_OPS_PTR(_ptr) +#endif + +/* Length of an ACPI name string, excluding null terminator */ +#define ACPI_NAME_LEN 4 + +/* Length of an ACPI name string including nul terminator */ +#define ACPI_NAME_MAX (ACPI_NAME_LEN + 1) + +/* Number of nested objects supported */ +#define ACPIGEN_LENSTACK_SIZE 10 + +#if !defined(__ACPI__) + +struct nhlt; +struct udevice; + +/** enum acpi_dump_option - selects what ACPI information to dump */ +enum acpi_dump_option { + ACPI_DUMP_LIST, /* Just the list of items */ + ACPI_DUMP_CONTENTS, /* Include the binary contents also */ +}; + +/** + * struct acpi_ctx - Context used for writing ACPI tables + * + * This contains a few useful pieces of information used when writing + * + * @base: Base address of ACPI tables + * @current: Current address for writing + * @rsdp: Pointer to the Root System Description Pointer, typically used when + * adding a new table. The RSDP holds pointers to the RSDT and XSDT. + * @rsdt: Pointer to the Root System Description Table + * @xsdt: Pointer to the Extended System Description Table + * @nhlt: Intel Non-High-Definition-Audio Link Table (NHLT) pointer, used to + * build up information that audio codecs need to provide in the NHLT ACPI + * table + * @len_stack: Stack of 'length' words to fix up later + * @ltop: Points to current top of stack (0 = empty) + */ +struct acpi_ctx { + void *base; + void *current; + struct acpi_rsdp *rsdp; + struct acpi_rsdt *rsdt; + struct acpi_xsdt *xsdt; + struct nhlt *nhlt; + char *len_stack[ACPIGEN_LENSTACK_SIZE]; + int ltop; +}; + +/** + * struct acpi_ops - ACPI operations supported by driver model + */ +struct acpi_ops { + /** + * get_name() - Obtain the ACPI name of a device + * + * @dev: Device to check + * @out_name: Place to put the name, must hold at least ACPI_NAME_MAX + * bytes + * @return 0 if OK, -ENOENT if no name is available, other -ve value on + * other error + */ + int (*get_name)(const struct udevice *dev, char *out_name); + + /** + * write_tables() - Write out any tables required by this device + * + * @dev: Device to write + * @ctx: ACPI context to use + * @return 0 if OK, -ve on error + */ + int (*write_tables)(const struct udevice *dev, struct acpi_ctx *ctx); + + /** + * fill_ssdt() - Generate SSDT code for a device + * + * This is called to create the SSDT code. The method should write out + * whatever ACPI code is needed by this device. It will end up in the + * SSDT table. + * + * Note that this is called 'fill' because the entire contents of the + * SSDT is build by calling this method on all devices. + * + * @dev: Device to write + * @ctx: ACPI context to use + * @return 0 if OK, -ve on error + */ + int (*fill_ssdt)(const struct udevice *dev, struct acpi_ctx *ctx); + + /** + * inject_dsdt() - Generate DSDT code for a device + * + * This is called to create the DSDT code. The method should write out + * whatever ACPI code is needed by this device. It will end up in the + * DSDT table. + * + * Note that this is called 'inject' because the output of calling this + * method on all devices is injected into the DSDT, the bulk of which + * is written in .asl files for the board. + * + * @dev: Device to write + * @ctx: ACPI context to use + * @return 0 if OK, -ve on error + */ + int (*inject_dsdt)(const struct udevice *dev, struct acpi_ctx *ctx); + + /** + * setup_nhlt() - Set up audio information for this device + * + * The method can add information to ctx->nhlt if it likes + * + * @return 0 if OK, -ENODATA if nothing to add, -ve on error + */ + int (*setup_nhlt)(const struct udevice *dev, struct acpi_ctx *ctx); +}; + +#define device_get_acpi_ops(dev) ((dev)->driver->acpi_ops) + +/** + * acpi_get_name() - Obtain the ACPI name of a device + * + * @dev: Device to check + * @out_name: Place to put the name, must hold at least ACPI_NAME_MAX + * bytes + * @return 0 if OK, -ENOENT if no name is available, other -ve value on + * other error + */ +int acpi_get_name(const struct udevice *dev, char *out_name); + +/** + * acpi_copy_name() - Copy an ACPI name to an output buffer + * + * This convenience function can be used to return a literal string as a name + * in functions that implement the get_name() method. + * + * For example: + * + * static int mydev_get_name(const struct udevice *dev, char *out_name) + * { + * return acpi_copy_name(out_name, "WIBB"); + * } + * + * @out_name: Place to put the name + * @name: Name to copy + * @return 0 (always) + */ +int acpi_copy_name(char *out_name, const char *name); + +/** + * acpi_write_dev_tables() - Write ACPI tables required by devices + * + * This scans through all devices and tells them to write any tables they want + * to write. + * + * @return 0 if OK, -ve if any device returned an error + */ +int acpi_write_dev_tables(struct acpi_ctx *ctx); + +/** + * acpi_fill_ssdt() - Generate ACPI tables for SSDT + * + * This is called to create the SSDT code for all devices. + * + * @ctx: ACPI context to use + * @return 0 if OK, -ve on error + */ +int acpi_fill_ssdt(struct acpi_ctx *ctx); + +/** + * acpi_inject_dsdt() - Generate ACPI tables for DSDT + * + * This is called to create the DSDT code for all devices. + * + * @ctx: ACPI context to use + * @return 0 if OK, -ve on error + */ +int acpi_inject_dsdt(struct acpi_ctx *ctx); + +/** + * acpi_setup_nhlt() - Set up audio information + * + * This is called to set up the nhlt information for all devices. + * + * @ctx: ACPI context to use + * @nhlt: Pointer to nhlt information to add to + * @return 0 if OK, -ve on error + */ +int acpi_setup_nhlt(struct acpi_ctx *ctx, struct nhlt *nhlt); + +/** + * acpi_dump_items() - Dump out the collected ACPI items + * + * This lists the ACPI DSDT and SSDT items generated by the various U-Boot + * drivers. + * + * @option: Sets what should be dumpyed + */ +void acpi_dump_items(enum acpi_dump_option option); + +/** + * acpi_get_path() - Get the full ACPI path for a device + * + * This checks for any override in the device tree and calls acpi_device_path() + * if not + * + * @dev: Device to check + * @out_path: Buffer to place the path in (should be ACPI_PATH_MAX long) + * @maxlen: Size of buffer (typically ACPI_PATH_MAX) + * @return 0 if OK, -ve on error + */ +int acpi_get_path(const struct udevice *dev, char *out_path, int maxlen); + +/** + * acpi_reset_items() - Reset the list of ACPI items to empty + * + * This list keeps track of DSDT and SSDT items that are generated + * programmatically. The 'acpi items' command shows the list. Use this function + * to empty the list, before writing new items. + */ +void acpi_reset_items(void); + +#endif /* __ACPI__ */ + +#endif diff --git a/roms/u-boot/include/dm/device-internal.h b/roms/u-boot/include/dm/device-internal.h new file mode 100644 index 000000000..e6b71cbfd --- /dev/null +++ b/roms/u-boot/include/dm/device-internal.h @@ -0,0 +1,429 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * Marek Vasut + */ + +#ifndef _DM_DEVICE_INTERNAL_H +#define _DM_DEVICE_INTERNAL_H + +#include +#include + +struct device_node; +struct udevice; + +/* + * These two macros DM_DEVICE_INST and DM_DEVICE_REF are only allowed in code + * generated by dtoc, because the ordering is important and if other instances + * creep in then they may mess up the ordering expected by dtoc. + * + * It is OK to use them with 'extern' though, since that does not actually + * add a new record to the linker_list. + */ + +/** + * DM_DEVICE_INST() - Declare a bound device ready for run-time use + * + * This adds an actual struct udevice to a list which is found by driver model + * on start-up. + * + * For example: + * + * extern U_BOOT_DRIVER(sandbox_fixed_clock); + * extern DM_UCLASS_INST(clk); + * + * DM_DEVICE_INST(clk_fixed) = { + * .driver = DM_DRIVER_REF(sandbox_fixed_clock), + * .name = "sandbox_fixed_clock", + * .plat_ = &_sandbox_fixed_clock_plat_clk_fixed, + * .uclass = DM_UCLASS_REF(clk), + * ... + * .seq_ = 0, + * }; + * + * @_name: Name of the udevice. This must be a valid C identifier, used by the + * linker_list. + */ +#define DM_DEVICE_INST(_name) \ + ll_entry_declare(struct udevice, _name, udevice) + +/** + * DM_DEVICE_REF() - Get a reference to a device + * + * This is useful in data structures and code for referencing a udevice at + * build time. Before this is used, an extern DM_DEVICE_INST() must have been + * declared. + * + * For example: + * + * extern DM_DEVICE_INST(clk_fixed); + * + * struct udevice *devs[] = { + * DM_DEVICE_REF(clk_fixed), + * }; + * + * @_name: Name of the udevice. This must be a valid C identifier, used by the + * linker_list + * @returns struct udevice * for the device + */ +#define DM_DEVICE_REF(_name) \ + ll_entry_ref(struct udevice, _name, udevice) + +/** + * DM_DEVICE_GET() - Get a pointer to a given device + * + * This is similar to DM_DEVICE_REF() except that it does not need the extern + * declaration before it. However it cannot be used in a data structures, only + * in code within a function. + * + * For example: + * + * void some_function() { + * struct udevice *dev = DM_DEVICE_GET(clk_fixed); + * ... + * } + */ +#define DM_DEVICE_GET(__name) \ + ll_entry_get(struct udevice, __name, udevice) + +/** + * device_bind() - Create a device and bind it to a driver + * + * Called to set up a new device attached to a driver. The device will either + * have plat, or a device tree node which can be used to create the + * plat. + * + * Once bound a device exists but is not yet active until device_probe() is + * called. + * + * @parent: Pointer to device's parent, under which this driver will exist + * @drv: Device's driver + * @name: Name of device (e.g. device tree node name) + * @plat: Pointer to data for this device - the structure is device- + * specific but may include the device's I/O address, etc.. This is NULL for + * devices which use device tree. + * @ofnode: Devicetree node for this device. This is ofnode_null() for + * devices which don't use devicetree or don't have a node. + * @devp: if non-NULL, returns a pointer to the bound device + * @return 0 if OK, -ve on error + */ +int device_bind(struct udevice *parent, const struct driver *drv, + const char *name, void *plat, ofnode node, + struct udevice **devp); + +/** + * device_bind_with_driver_data() - Create a device and bind it to a driver + * + * Called to set up a new device attached to a driver, in the case where the + * driver was matched to the device by means of a match table that provides + * driver_data. + * + * Once bound a device exists but is not yet active until device_probe() is + * called. + * + * @parent: Pointer to device's parent, under which this driver will exist + * @drv: Device's driver + * @name: Name of device (e.g. device tree node name) + * @driver_data: The driver_data field from the driver's match table. + * @node: Device tree node for this device. This is invalid for devices which + * don't use device tree. + * @devp: if non-NULL, returns a pointer to the bound device + * @return 0 if OK, -ve on error + */ +int device_bind_with_driver_data(struct udevice *parent, + const struct driver *drv, const char *name, + ulong driver_data, ofnode node, + struct udevice **devp); +/** + * device_bind_by_name: Create a device and bind it to a driver + * + * This is a helper function used to bind devices which do not use device + * tree. + * + * @parent: Pointer to device's parent + * @pre_reloc_only: If true, bind the driver only if its DM_FLAG_PRE_RELOC flag + * is set. If false bind the driver always. + * @info: Name and plat for this device + * @devp: if non-NULL, returns a pointer to the bound device + * @return 0 if OK, -ve on error + */ +int device_bind_by_name(struct udevice *parent, bool pre_reloc_only, + const struct driver_info *info, struct udevice **devp); + +/** + * device_reparent: reparent the device to a new parent + * + * @dev: pointer to device to be reparented + * @new_parent: pointer to new parent device + * @return 0 if OK, -ve on error + */ +int device_reparent(struct udevice *dev, struct udevice *new_parent); + +/** + * device_of_to_plat() - Read platform data for a device + * + * Read platform data for a device (typically from the device tree) so that + * the information needed to probe the device is present. + * + * This may cause some others devices to be probed if this one depends on them, + * e.g. a GPIO line will cause a GPIO device to be probed. + * + * All private data associated with the device is allocated. + * + * @dev: Pointer to device to process + * @return 0 if OK, -ve on error + */ +int device_of_to_plat(struct udevice *dev); + +/** + * device_probe() - Probe a device, activating it + * + * Activate a device so that it is ready for use. All its parents are probed + * first. + * + * @dev: Pointer to device to probe + * @return 0 if OK, -ve on error + */ +int device_probe(struct udevice *dev); + +/** + * device_remove() - Remove a device, de-activating it + * + * De-activate a device so that it is no longer ready for use. All its + * children are deactivated first. + * + * @dev: Pointer to device to remove + * @flags: Flags for selective device removal (DM_REMOVE_...) + * @return 0 if OK, -EKEYREJECTED if not removed due to flags, -EPROBE_DEFER if + * this is a vital device and flags is DM_REMOVE_NON_VITAL, other -ve on + * error (such an error here is normally a very bad thing) + */ +#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE) +int device_remove(struct udevice *dev, uint flags); +#else +static inline int device_remove(struct udevice *dev, uint flags) { return 0; } +#endif + +/** + * device_unbind() - Unbind a device, destroying it + * + * Unbind a device and remove all memory used by it + * + * @dev: Pointer to device to unbind + * @return 0 if OK, -ve on error + */ +#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE) +int device_unbind(struct udevice *dev); +#else +static inline int device_unbind(struct udevice *dev) { return 0; } +#endif + +#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE) +void device_free(struct udevice *dev); +#else +static inline void device_free(struct udevice *dev) {} +#endif + +/** + * device_chld_unbind() - Unbind all device's children from the device if bound + * to drv + * + * On error, the function continues to unbind all children, and reports the + * first error. + * + * @dev: The device that is to be stripped of its children + * @drv: The targeted driver + * @return 0 on success, -ve on error + */ +#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE) +int device_chld_unbind(struct udevice *dev, struct driver *drv); +#else +static inline int device_chld_unbind(struct udevice *dev, struct driver *drv) +{ + return 0; +} +#endif + +/** + * device_chld_remove() - Stop all device's children + * + * This continues through all children recursively stopping part-way through if + * an error occurs. Return values of -EKEYREJECTED are ignored and processing + * continues, since they just indicate that the child did not elect to be + * removed based on the value of @flags. Return values of -EPROBE_DEFER cause + * processing of other children to continue, but the function will return + * -EPROBE_DEFER. + * + * @dev: The device whose children are to be removed + * @drv: The targeted driver + * @flags: Flag, if this functions is called in the pre-OS stage + * @return 0 on success, -EPROBE_DEFER if any child failed to remove, other + * -ve on error + */ +#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE) +int device_chld_remove(struct udevice *dev, struct driver *drv, + uint flags); +#else +static inline int device_chld_remove(struct udevice *dev, struct driver *drv, + uint flags) +{ + return 0; +} +#endif + +/** + * dev_set_priv() - Set the private data for a device + * + * This is normally handled by driver model, which automatically allocates + * private data when an 'auto' size if provided by the driver. + * + * Use this function to override normal operation for special situations, such + * as needing to allocate a variable amount of data. + * + * If OF_PLATDATA_RT is enabled, this function cannot be used out of core driver + * model code, since the pointer must be within the gd->dm_priv_base region. + * + * @dev Device to check + * @priv New private-data pointer + */ +void dev_set_priv(struct udevice *dev, void *priv); + +/** + * dev_set_parent_priv() - Set the parent-private data for a device + * + * This is normally handled by driver model, which automatically allocates + * parent-private data when an 'auto' size if provided by the driver. + * + * Use this function to override normal operation for special situations, such + * as needing to allocate a variable amount of data. + * + * If OF_PLATDATA_RT is enabled, this function cannot be used out of core driver + * model code, since the pointer must be within the gd->dm_priv_base region. + * + * @dev: Device to update + * @parent_priv: New parent-private data + */ +void dev_set_parent_priv(struct udevice *dev, void *parent_priv); + +/** + * dev_set_uclass_priv() - Set the uclass private data for a device + * + * This is normally handled by driver model, which automatically allocates + * uclass-private data when an 'auto' size if provided by the driver. + * + * Use this function to override normal operation for special situations, such + * as needing to allocate a variable amount of data. + * + * If OF_PLATDATA_RT is enabled, this function cannot be used out of core driver + * model code, since the pointer must be within the gd->dm_priv_base region. + * + * @dev: Device to update + * @uclass_priv: New uclass private data + */ +void dev_set_uclass_priv(struct udevice *dev, void *uclass_priv); + +/** + * dev_set_plat() - Set the platform data for a device + * + * This is normally handled by driver model, which automatically allocates + * platform data when an 'auto' size if provided by the driver. + * + * Use this function to override normal operation for special situations, such + * as needing to allocate a variable amount of data. + * + * If OF_PLATDATA_RT is enabled, this function cannot be used out of core driver + * model code, since the pointer must be within the gd->dm_priv_base region. + * + * @dev Device to check + * @plat New platform-data pointer + */ +void dev_set_plat(struct udevice *dev, void *priv); + +/** + * dev_set_parent_plat() - Set the parent platform data for a device + * + * This is normally handled by driver model, which automatically allocates + * parent platform data when an 'auto' size if provided by the driver. + * + * Use this function to override normal operation for special situations, such + * as needing to allocate a variable amount of data. + * + * If OF_PLATDATA_RT is enabled, this function cannot be used out of core driver + * model code, since the pointer must be within the gd->dm_priv_base region. + * + * @dev: Device to update + * @parent_plat: New parent platform data + */ +void dev_set_parent_plat(struct udevice *dev, void *parent_plat); + +/** + * dev_set_uclass_plat() - Set the uclass platform data for a device + * + * This is normally handled by driver model, which automatically allocates + * uclass platform data when an 'auto' size if provided by the driver. + * + * Use this function to override normal operation for special situations, such + * as needing to allocate a variable amount of data. + * + * If OF_PLATDATA_RT is enabled, this function cannot be used out of core driver + * model code, since the pointer must be within the gd->dm_priv_base region. + * + * @dev: Device to update + * @uclass_plat: New uclass platform data + */ +void dev_set_uclass_plat(struct udevice *dev, void *uclass_plat); + +/** + * simple_bus_translate() - translate a bus address to a system address + * + * This handles the 'ranges' property in a simple bus. It translates the + * device address @addr to a system address using this property. + * + * @dev: Simple bus device (parent of target device) + * @addr: Address to translate + * @return new address + */ +fdt_addr_t simple_bus_translate(struct udevice *dev, fdt_addr_t addr); + +/* Cast away any volatile pointer */ +#define DM_ROOT_NON_CONST (((gd_t *)gd)->dm_root) +#define DM_UCLASS_ROOT_NON_CONST (((gd_t *)gd)->uclass_root) +#define DM_UCLASS_ROOT_S_NON_CONST (((gd_t *)gd)->uclass_root_s) + +/* device resource management */ +#ifdef CONFIG_DEVRES + +/** + * devres_release_probe - Release managed resources allocated after probing + * @dev: Device to release resources for + * + * Release all resources allocated for @dev when it was probed or later. + * This function is called on driver removal. + */ +void devres_release_probe(struct udevice *dev); + +/** + * devres_release_all - Release all managed resources + * @dev: Device to release resources for + * + * Release all resources associated with @dev. This function is + * called on driver unbinding. + */ +void devres_release_all(struct udevice *dev); + +#else /* ! CONFIG_DEVRES */ + +static inline void devres_release_probe(struct udevice *dev) +{ +} + +static inline void devres_release_all(struct udevice *dev) +{ +} + +#endif /* ! CONFIG_DEVRES */ +#endif diff --git a/roms/u-boot/include/dm/device.h b/roms/u-boot/include/dm/device.h new file mode 100644 index 000000000..0a9718a5b --- /dev/null +++ b/roms/u-boot/include/dm/device.h @@ -0,0 +1,997 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * Marek Vasut + */ + +#ifndef _DM_DEVICE_H +#define _DM_DEVICE_H + +#include +#include +#include +#include +#include +#include +#include + +struct driver_info; + +/* Driver is active (probed). Cleared when it is removed */ +#define DM_FLAG_ACTIVATED (1 << 0) + +/* DM is responsible for allocating and freeing plat */ +#define DM_FLAG_ALLOC_PDATA (1 << 1) + +/* DM should init this device prior to relocation */ +#define DM_FLAG_PRE_RELOC (1 << 2) + +/* DM is responsible for allocating and freeing parent_plat */ +#define DM_FLAG_ALLOC_PARENT_PDATA (1 << 3) + +/* DM is responsible for allocating and freeing uclass_plat */ +#define DM_FLAG_ALLOC_UCLASS_PDATA (1 << 4) + +/* Allocate driver private data on a DMA boundary */ +#define DM_FLAG_ALLOC_PRIV_DMA (1 << 5) + +/* Device is bound */ +#define DM_FLAG_BOUND (1 << 6) + +/* Device name is allocated and should be freed on unbind() */ +#define DM_FLAG_NAME_ALLOCED (1 << 7) + +/* Device has platform data provided by of-platdata */ +#define DM_FLAG_OF_PLATDATA (1 << 8) + +/* + * Call driver remove function to stop currently active DMA transfers or + * give DMA buffers back to the HW / controller. This may be needed for + * some drivers to do some final stage cleanup before the OS is called + * (U-Boot exit) + */ +#define DM_FLAG_ACTIVE_DMA (1 << 9) + +/* + * Call driver remove function to do some final configuration, before + * U-Boot exits and the OS is started + */ +#define DM_FLAG_OS_PREPARE (1 << 10) + +/* DM does not enable/disable the power domains corresponding to this device */ +#define DM_FLAG_DEFAULT_PD_CTRL_OFF (1 << 11) + +/* Driver plat has been read. Cleared when the device is removed */ +#define DM_FLAG_PLATDATA_VALID (1 << 12) + +/* + * Device is removed without switching off its power domain. This might + * be required, i. e. for serial console (debug) output when booting OS. + */ +#define DM_FLAG_LEAVE_PD_ON (1 << 13) + +/* + * Device is vital to the operation of other devices. It is possible to remove + * removed this device after all regular devices are removed. This is useful + * e.g. for clock, which need to be active during the device-removal phase. + */ +#define DM_FLAG_VITAL (1 << 14) + +/* + * One or multiple of these flags are passed to device_remove() so that + * a selective device removal as specified by the remove-stage and the + * driver flags can be done. + * + * DO NOT use these flags in your driver's @flags value... + * use the above DM_FLAG_... values instead + */ +enum { + /* Normal remove, remove all devices */ + DM_REMOVE_NORMAL = 1 << 0, + + /* Remove devices with active DMA */ + DM_REMOVE_ACTIVE_DMA = DM_FLAG_ACTIVE_DMA, + + /* Remove devices which need some final OS preparation steps */ + DM_REMOVE_OS_PREPARE = DM_FLAG_OS_PREPARE, + + /* Remove only devices that are not marked vital */ + DM_REMOVE_NON_VITAL = DM_FLAG_VITAL, + + /* Remove devices with any active flag */ + DM_REMOVE_ACTIVE_ALL = DM_REMOVE_ACTIVE_DMA | DM_REMOVE_OS_PREPARE, + + /* Don't power down any attached power domains */ + DM_REMOVE_NO_PD = 1 << 1, +}; + +/** + * struct udevice - An instance of a driver + * + * This holds information about a device, which is a driver bound to a + * particular port or peripheral (essentially a driver instance). + * + * A device will come into existence through a 'bind' call, either due to + * a U_BOOT_DRVINFO() macro (in which case plat is non-NULL) or a node + * in the device tree (in which case of_offset is >= 0). In the latter case + * we translate the device tree information into plat in a function + * implemented by the driver of_to_plat method (called just before the + * probe method if the device has a device tree node. + * + * All three of plat, priv and uclass_priv can be allocated by the + * driver, or you can use the auto members of struct driver and + * struct uclass_driver to have driver model do this automatically. + * + * @driver: The driver used by this device + * @name: Name of device, typically the FDT node name + * @plat_: Configuration data for this device (do not access outside driver + * model) + * @parent_plat_: The parent bus's configuration data for this device (do not + * access outside driver model) + * @uclass_plat_: The uclass's configuration data for this device (do not access + * outside driver model) + * @driver_data: Driver data word for the entry that matched this device with + * its driver + * @parent: Parent of this device, or NULL for the top level device + * @priv_: Private data for this device (do not access outside driver model) + * @uclass: Pointer to uclass for this device + * @uclass_priv_: The uclass's private data for this device (do not access + * outside driver model) + * @parent_priv_: The parent's private data for this device (do not access + * outside driver model) + * @uclass_node: Used by uclass to link its devices + * @child_head: List of children of this device + * @sibling_node: Next device in list of all devices + * @flags_: Flags for this device DM_FLAG_... (do not access outside driver + * model) + * @seq_: Allocated sequence number for this device (-1 = none). This is set up + * when the device is bound and is unique within the device's uclass. If the + * device has an alias in the devicetree then that is used to set the sequence + * number. Otherwise, the next available number is used. Sequence numbers are + * used by certain commands that need device to be numbered (e.g. 'mmc dev'). + * (do not access outside driver model) + * @node_: Reference to device tree node for this device (do not access outside + * driver model) + * @devres_head: List of memory allocations associated with this device. + * When CONFIG_DEVRES is enabled, devm_kmalloc() and friends will + * add to this list. Memory so-allocated will be freed + * automatically when the device is removed / unbound + * @dma_offset: Offset between the physical address space (CPU's) and the + * device's bus address space + */ +struct udevice { + const struct driver *driver; + const char *name; + void *plat_; + void *parent_plat_; + void *uclass_plat_; + ulong driver_data; + struct udevice *parent; + void *priv_; + struct uclass *uclass; + void *uclass_priv_; + void *parent_priv_; + struct list_head uclass_node; + struct list_head child_head; + struct list_head sibling_node; +#if !CONFIG_IS_ENABLED(OF_PLATDATA_RT) + u32 flags_; +#endif + int seq_; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + ofnode node_; +#endif +#ifdef CONFIG_DEVRES + struct list_head devres_head; +#endif +#if CONFIG_IS_ENABLED(DM_DMA) + ulong dma_offset; +#endif +}; + +/** + * udevice_rt - runtime information set up by U-Boot + * + * This is only used with OF_PLATDATA_RT + * + * There is one of these for every udevice in the linker list, indexed by + * the udevice_info idx value. + * + * @flags_: Flags for this device DM_FLAG_... (do not access outside driver + * model) + */ +struct udevice_rt { + u32 flags_; +}; + +/* Maximum sequence number supported */ +#define DM_MAX_SEQ 999 + +/* Returns the operations for a device */ +#define device_get_ops(dev) (dev->driver->ops) + +#if CONFIG_IS_ENABLED(OF_PLATDATA_RT) +u32 dev_get_flags(const struct udevice *dev); +void dev_or_flags(const struct udevice *dev, u32 or); +void dev_bic_flags(const struct udevice *dev, u32 bic); +#else +static inline u32 dev_get_flags(const struct udevice *dev) +{ + return dev->flags_; +} + +static inline void dev_or_flags(struct udevice *dev, u32 or) +{ + dev->flags_ |= or; +} + +static inline void dev_bic_flags(struct udevice *dev, u32 bic) +{ + dev->flags_ &= ~bic; +} +#endif /* OF_PLATDATA_RT */ + +/** + * dev_ofnode() - get the DT node reference associated with a udevice + * + * @dev: device to check + * @return reference of the the device's DT node + */ +static inline ofnode dev_ofnode(const struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + return dev->node_; +#else + return ofnode_null(); +#endif +} + +/* Returns non-zero if the device is active (probed and not removed) */ +#define device_active(dev) (dev_get_flags(dev) & DM_FLAG_ACTIVATED) + +#if CONFIG_IS_ENABLED(DM_DMA) +#define dev_set_dma_offset(_dev, _offset) _dev->dma_offset = _offset +#define dev_get_dma_offset(_dev) _dev->dma_offset +#else +#define dev_set_dma_offset(_dev, _offset) +#define dev_get_dma_offset(_dev) 0 +#endif + +static inline int dev_of_offset(const struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + return ofnode_to_offset(dev_ofnode(dev)); +#else + return -1; +#endif +} + +static inline bool dev_has_ofnode(const struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + return ofnode_valid(dev_ofnode(dev)); +#else + return false; +#endif +} + +static inline void dev_set_ofnode(struct udevice *dev, ofnode node) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + dev->node_ = node; +#endif +} + +static inline int dev_seq(const struct udevice *dev) +{ + return dev->seq_; +} + +/** + * struct udevice_id - Lists the compatible strings supported by a driver + * @compatible: Compatible string + * @data: Data for this compatible string + */ +struct udevice_id { + const char *compatible; + ulong data; +}; + +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#define of_match_ptr(_ptr) (_ptr) +#else +#define of_match_ptr(_ptr) NULL +#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ + +/** + * struct driver - A driver for a feature or peripheral + * + * This holds methods for setting up a new device, and also removing it. + * The device needs information to set itself up - this is provided either + * by plat or a device tree node (which we find by looking up + * matching compatible strings with of_match). + * + * Drivers all belong to a uclass, representing a class of devices of the + * same type. Common elements of the drivers can be implemented in the uclass, + * or the uclass can provide a consistent interface to the drivers within + * it. + * + * @name: Device name + * @id: Identifies the uclass we belong to + * @of_match: List of compatible strings to match, and any identifying data + * for each. + * @bind: Called to bind a device to its driver + * @probe: Called to probe a device, i.e. activate it + * @remove: Called to remove a device, i.e. de-activate it + * @unbind: Called to unbind a device from its driver + * @of_to_plat: Called before probe to decode device tree data + * @child_post_bind: Called after a new child has been bound + * @child_pre_probe: Called before a child device is probed. The device has + * memory allocated but it has not yet been probed. + * @child_post_remove: Called after a child device is removed. The device + * has memory allocated but its device_remove() method has been called. + * @priv_auto: If non-zero this is the size of the private data + * to be allocated in the device's ->priv pointer. If zero, then the driver + * is responsible for allocating any data required. + * @plat_auto: If non-zero this is the size of the + * platform data to be allocated in the device's ->plat pointer. + * This is typically only useful for device-tree-aware drivers (those with + * an of_match), since drivers which use plat will have the data + * provided in the U_BOOT_DRVINFO() instantiation. + * @per_child_auto: Each device can hold private data owned by + * its parent. If required this will be automatically allocated if this + * value is non-zero. + * @per_child_plat_auto: A bus likes to store information about + * its children. If non-zero this is the size of this data, to be allocated + * in the child's parent_plat pointer. + * @ops: Driver-specific operations. This is typically a list of function + * pointers defined by the driver, to implement driver functions required by + * the uclass. + * @flags: driver flags - see DM_FLAGS_... + * @acpi_ops: Advanced Configuration and Power Interface (ACPI) operations, + * allowing the device to add things to the ACPI tables passed to Linux + */ +struct driver { + char *name; + enum uclass_id id; + const struct udevice_id *of_match; + int (*bind)(struct udevice *dev); + int (*probe)(struct udevice *dev); + int (*remove)(struct udevice *dev); + int (*unbind)(struct udevice *dev); + int (*of_to_plat)(struct udevice *dev); + int (*child_post_bind)(struct udevice *dev); + int (*child_pre_probe)(struct udevice *dev); + int (*child_post_remove)(struct udevice *dev); + int priv_auto; + int plat_auto; + int per_child_auto; + int per_child_plat_auto; + const void *ops; /* driver-specific operations */ + uint32_t flags; +#if CONFIG_IS_ENABLED(ACPIGEN) + struct acpi_ops *acpi_ops; +#endif +}; + +/* Declare a new U-Boot driver */ +#define U_BOOT_DRIVER(__name) \ + ll_entry_declare(struct driver, __name, driver) + +/* Get a pointer to a given driver */ +#define DM_DRIVER_GET(__name) \ + ll_entry_get(struct driver, __name, driver) + +/** + * DM_DRIVER_REF() - Get a reference to a driver + * + * This is useful in data structures and code for referencing a driver at + * build time. Before this is used, an extern U_BOOT_DRIVER() must have been + * declared. + * + * For example: + * + * extern U_BOOT_DRIVER(sandbox_fixed_clock); + * + * struct driver *drvs[] = { + * DM_DRIVER_REF(sandbox_fixed_clock), + * }; + * + * @_name: Name of the driver. This must be a valid C identifier, used by the + * linker_list + * @returns struct driver * for the driver + */ +#define DM_DRIVER_REF(_name) \ + ll_entry_ref(struct driver, _name, driver) + +/** + * Declare a macro to state a alias for a driver name. This macro will + * produce no code but its information will be parsed by tools like + * dtoc + */ +#define DM_DRIVER_ALIAS(__name, __alias) + +/** + * Declare a macro to indicate which phase of U-Boot this driver is fore. + * + * + * This macro produces no code but its information will be parsed by dtoc. The + * macro can be only be used once in a driver. Put it within the U_BOOT_DRIVER() + * declaration, e.g.: + * + * U_BOOT_DRIVER(cpu) = { + * .name = ... + * ... + * DM_PHASE(tpl) + * }; + */ +#define DM_PHASE(_phase) + +/** + * Declare a macro to declare a header needed for a driver. Often the correct + * header can be found automatically, but only for struct declarations. For + * enums and #defines used in the driver declaration and declared in a different + * header from the structs, this macro must be used. + * + * This macro produces no code but its information will be parsed by dtoc. The + * macro can be used multiple times with different headers, for the same driver. + * Put it within the U_BOOT_DRIVER() declaration, e.g.: + * + * U_BOOT_DRIVER(cpu) = { + * .name = ... + * ... + * DM_HEADER() + * }; + */ +#define DM_HEADER(_hdr) + +/** + * dev_get_plat() - Get the platform data for a device + * + * This checks that dev is not NULL, but no other checks for now + * + * @dev Device to check + * @return platform data, or NULL if none + */ +void *dev_get_plat(const struct udevice *dev); + +/** + * dev_get_parent_plat() - Get the parent platform data for a device + * + * This checks that dev is not NULL, but no other checks for now + * + * @dev Device to check + * @return parent's platform data, or NULL if none + */ +void *dev_get_parent_plat(const struct udevice *dev); + +/** + * dev_get_uclass_plat() - Get the uclass platform data for a device + * + * This checks that dev is not NULL, but no other checks for now + * + * @dev Device to check + * @return uclass's platform data, or NULL if none + */ +void *dev_get_uclass_plat(const struct udevice *dev); + +/** + * dev_get_priv() - Get the private data for a device + * + * This checks that dev is not NULL, but no other checks for now + * + * @dev Device to check + * @return private data, or NULL if none + */ +void *dev_get_priv(const struct udevice *dev); + +/** + * dev_get_parent_priv() - Get the parent private data for a device + * + * The parent private data is data stored in the device but owned by the + * parent. For example, a USB device may have parent data which contains + * information about how to talk to the device over USB. + * + * This checks that dev is not NULL, but no other checks for now + * + * @dev Device to check + * @return parent data, or NULL if none + */ +void *dev_get_parent_priv(const struct udevice *dev); + +/** + * dev_get_uclass_priv() - Get the private uclass data for a device + * + * This checks that dev is not NULL, but no other checks for now + * + * @dev Device to check + * @return private uclass data for this device, or NULL if none + */ +void *dev_get_uclass_priv(const struct udevice *dev); + +/** + * struct dev_get_parent() - Get the parent of a device + * + * @child: Child to check + * @return parent of child, or NULL if this is the root device + */ +struct udevice *dev_get_parent(const struct udevice *child); + +/** + * dev_get_driver_data() - get the driver data used to bind a device + * + * When a device is bound using a device tree node, it matches a + * particular compatible string in struct udevice_id. This function + * returns the associated data value for that compatible string. This is + * the 'data' field in struct udevice_id. + * + * As an example, consider this structure: + * static const struct udevice_id tegra_i2c_ids[] = { + * { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 }, + * { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD }, + * { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC }, + * { } + * }; + * + * When driver model finds a driver for this it will store the 'data' value + * corresponding to the compatible string it matches. This function returns + * that value. This allows the driver to handle several variants of a device. + * + * For USB devices, this is the driver_info field in struct usb_device_id. + * + * @dev: Device to check + * @return driver data (0 if none is provided) + */ +ulong dev_get_driver_data(const struct udevice *dev); + +/** + * dev_get_driver_ops() - get the device's driver's operations + * + * This checks that dev is not NULL, and returns the pointer to device's + * driver's operations. + * + * @dev: Device to check + * @return void pointer to driver's operations or NULL for NULL-dev or NULL-ops + */ +const void *dev_get_driver_ops(const struct udevice *dev); + +/** + * device_get_uclass_id() - return the uclass ID of a device + * + * @dev: Device to check + * @return uclass ID for the device + */ +enum uclass_id device_get_uclass_id(const struct udevice *dev); + +/** + * dev_get_uclass_name() - return the uclass name of a device + * + * This checks that dev is not NULL. + * + * @dev: Device to check + * @return pointer to the uclass name for the device + */ +const char *dev_get_uclass_name(const struct udevice *dev); + +/** + * device_get_child() - Get the child of a device by index + * + * Returns the numbered child, 0 being the first. This does not use + * sequence numbers, only the natural order. + * + * @dev: Parent device to check + * @index: Child index + * @devp: Returns pointer to device + * @return 0 if OK, -ENODEV if no such device, other error if the device fails + * to probe + */ +int device_get_child(const struct udevice *parent, int index, + struct udevice **devp); + +/** + * device_get_child_count() - Get the available child count of a device + * + * Returns the number of children to a device. + * + * @parent: Parent device to check + */ +int device_get_child_count(const struct udevice *parent); + +/** + * device_find_child_by_seq() - Find a child device based on a sequence + * + * This searches for a device with the given seq. + * + * @parent: Parent device + * @seq: Sequence number to find (0=first) + * @devp: Returns pointer to device (there is only one per for each seq). + * Set to NULL if none is found + * @return 0 if OK, -ENODEV if not found + */ +int device_find_child_by_seq(const struct udevice *parent, int seq, + struct udevice **devp); + +/** + * device_get_child_by_seq() - Get a child device based on a sequence + * + * If an active device has this sequence it will be returned. If there is no + * such device then this will check for a device that is requesting this + * sequence. + * + * The device is probed to activate it ready for use. + * + * @parent: Parent device + * @seq: Sequence number to find (0=first) + * @devp: Returns pointer to device (there is only one per for each seq) + * Set to NULL if none is found + * @return 0 if OK, -ve on error + */ +int device_get_child_by_seq(const struct udevice *parent, int seq, + struct udevice **devp); + +/** + * device_find_child_by_of_offset() - Find a child device based on FDT offset + * + * Locates a child device by its device tree offset. + * + * @parent: Parent device + * @of_offset: Device tree offset to find + * @devp: Returns pointer to device if found, otherwise this is set to NULL + * @return 0 if OK, -ve on error + */ +int device_find_child_by_of_offset(const struct udevice *parent, int of_offset, + struct udevice **devp); + +/** + * device_get_child_by_of_offset() - Get a child device based on FDT offset + * + * Locates a child device by its device tree offset. + * + * The device is probed to activate it ready for use. + * + * @parent: Parent device + * @of_offset: Device tree offset to find + * @devp: Returns pointer to device if found, otherwise this is set to NULL + * @return 0 if OK, -ve on error + */ +int device_get_child_by_of_offset(const struct udevice *parent, int of_offset, + struct udevice **devp); + +/** + * device_find_global_by_ofnode() - Get a device based on ofnode + * + * Locates a device by its device tree ofnode, searching globally throughout + * the all driver model devices. + * + * The device is NOT probed + * + * @node: Device tree ofnode to find + * @devp: Returns pointer to device if found, otherwise this is set to NULL + * @return 0 if OK, -ve on error + */ + +int device_find_global_by_ofnode(ofnode node, struct udevice **devp); + +/** + * device_get_global_by_ofnode() - Get a device based on ofnode + * + * Locates a device by its device tree ofnode, searching globally throughout + * the all driver model devices. + * + * The device is probed to activate it ready for use. + * + * @node: Device tree ofnode to find + * @devp: Returns pointer to device if found, otherwise this is set to NULL + * @return 0 if OK, -ve on error + */ +int device_get_global_by_ofnode(ofnode node, struct udevice **devp); + +/** + * device_get_by_ofplat_idx() - Get a device based on of-platdata index + * + * Locates a device by either its struct driver_info index, or its + * struct udevice index. The latter is used with OF_PLATDATA_INST, since we have + * a list of build-time instantiated struct udevice records, The former is used + * with !OF_PLATDATA_INST since in that case we have a list of + * struct driver_info records. + * + * The index number is written into the idx field of struct phandle_1_arg, etc. + * It is the position of this driver_info/udevice in its linker list. + * + * The device is probed to activate it ready for use. + * + * @idx: Index number of the driver_info/udevice structure (0=first) + * @devp: Returns pointer to device if found, otherwise this is set to NULL + * @return 0 if OK, -ve on error + */ +int device_get_by_ofplat_idx(uint idx, struct udevice **devp); + +/** + * device_find_first_child() - Find the first child of a device + * + * @parent: Parent device to search + * @devp: Returns first child device, or NULL if none + * @return 0 + */ +int device_find_first_child(const struct udevice *parent, + struct udevice **devp); + +/** + * device_find_next_child() - Find the next child of a device + * + * @devp: Pointer to previous child device on entry. Returns pointer to next + * child device, or NULL if none + * @return 0 + */ +int device_find_next_child(struct udevice **devp); + +/** + * device_find_first_inactive_child() - Find the first inactive child + * + * This is used to locate an existing child of a device which is of a given + * uclass. + * + * The device is NOT probed + * + * @parent: Parent device to search + * @uclass_id: Uclass to look for + * @devp: Returns device found, if any + * @return 0 if found, else -ENODEV + */ +int device_find_first_inactive_child(const struct udevice *parent, + enum uclass_id uclass_id, + struct udevice **devp); + +/** + * device_find_first_child_by_uclass() - Find the first child of a device in uc + * + * @parent: Parent device to search + * @uclass_id: Uclass to look for + * @devp: Returns first child device in that uclass, if any + * @return 0 if found, else -ENODEV + */ +int device_find_first_child_by_uclass(const struct udevice *parent, + enum uclass_id uclass_id, + struct udevice **devp); + +/** + * device_find_child_by_name() - Find a child by device name + * + * @parent: Parent device to search + * @name: Name to look for + * @devp: Returns device found, if any + * @return 0 if found, else -ENODEV + */ +int device_find_child_by_name(const struct udevice *parent, const char *name, + struct udevice **devp); + +/** + * device_first_child_ofdata_err() - Find the first child and reads its plat + * + * The of_to_plat() method is called on the child before it is returned, + * but the child is not probed. + * + * @parent: Parent to check + * @devp: Returns child that was found, if any + * @return 0 on success, -ENODEV if no children, other -ve on error + */ +int device_first_child_ofdata_err(struct udevice *parent, + struct udevice **devp); + +/* + * device_next_child_ofdata_err() - Find the next child and read its plat + * + * The of_to_plat() method is called on the child before it is returned, + * but the child is not probed. + * + * @devp: On entry, points to the previous child; on exit returns the child that + * was found, if any + * @return 0 on success, -ENODEV if no children, other -ve on error + */ +int device_next_child_ofdata_err(struct udevice **devp); + +/** + * device_first_child_err() - Get the first child of a device + * + * The device returned is probed if necessary, and ready for use + * + * @parent: Parent device to search + * @devp: Returns device found, if any + * @return 0 if found, -ENODEV if not, -ve error if device failed to probe + */ +int device_first_child_err(struct udevice *parent, struct udevice **devp); + +/** + * device_next_child_err() - Get the next child of a parent device + * + * The device returned is probed if necessary, and ready for use + * + * @devp: On entry, pointer to device to lookup. On exit, returns pointer + * to the next sibling if no error occurred + * @return 0 if found, -ENODEV if not, -ve error if device failed to probe + */ +int device_next_child_err(struct udevice **devp); + +/** + * device_has_children() - check if a device has any children + * + * @dev: Device to check + * @return true if the device has one or more children + */ +bool device_has_children(const struct udevice *dev); + +/** + * device_has_active_children() - check if a device has any active children + * + * @dev: Device to check + * @return true if the device has one or more children and at least one of + * them is active (probed). + */ +bool device_has_active_children(const struct udevice *dev); + +/** + * device_is_last_sibling() - check if a device is the last sibling + * + * This function can be useful for display purposes, when special action needs + * to be taken when displaying the last sibling. This can happen when a tree + * view of devices is being displayed. + * + * @dev: Device to check + * @return true if there are no more siblings after this one - i.e. is it + * last in the list. + */ +bool device_is_last_sibling(const struct udevice *dev); + +/** + * device_set_name() - set the name of a device + * + * This must be called in the device's bind() method and no later. Normally + * this is unnecessary but for probed devices which don't get a useful name + * this function can be helpful. + * + * The name is allocated and will be freed automatically when the device is + * unbound. + * + * @dev: Device to update + * @name: New name (this string is allocated new memory and attached to + * the device) + * @return 0 if OK, -ENOMEM if there is not enough memory to allocate the + * string + */ +int device_set_name(struct udevice *dev, const char *name); + +/** + * device_set_name_alloced() - note that a device name is allocated + * + * This sets the DM_FLAG_NAME_ALLOCED flag for the device, so that when it is + * unbound the name will be freed. This avoids memory leaks. + * + * @dev: Device to update + */ +void device_set_name_alloced(struct udevice *dev); + +/** + * device_is_compatible() - check if the device is compatible with the compat + * + * This allows to check whether the device is comaptible with the compat. + * + * @dev: udevice pointer for which compatible needs to be verified. + * @compat: Compatible string which needs to verified in the given + * device + * @return true if OK, false if the compatible is not found + */ +bool device_is_compatible(const struct udevice *dev, const char *compat); + +/** + * of_machine_is_compatible() - check if the machine is compatible with + * the compat + * + * This allows to check whether the machine is comaptible with the compat. + * + * @compat: Compatible string which needs to verified + * @return true if OK, false if the compatible is not found + */ +bool of_machine_is_compatible(const char *compat); + +/** + * dev_disable_by_path() - Disable a device given its device tree path + * + * @path: The device tree path identifying the device to be disabled + * @return 0 on success, -ve on error + */ +int dev_disable_by_path(const char *path); + +/** + * dev_enable_by_path() - Enable a device given its device tree path + * + * @path: The device tree path identifying the device to be enabled + * @return 0 on success, -ve on error + */ +int dev_enable_by_path(const char *path); + +/** + * device_is_on_pci_bus - Test if a device is on a PCI bus + * + * @dev: device to test + * @return: true if it is on a PCI bus, false otherwise + */ +static inline bool device_is_on_pci_bus(const struct udevice *dev) +{ + return dev->parent && device_get_uclass_id(dev->parent) == UCLASS_PCI; +} + +/** + * device_foreach_child_safe() - iterate through child devices safely + * + * This allows the @pos child to be removed in the loop if required. + * + * @pos: struct udevice * for the current device + * @next: struct udevice * for the next device + * @parent: parent device to scan + */ +#define device_foreach_child_safe(pos, next, parent) \ + list_for_each_entry_safe(pos, next, &parent->child_head, sibling_node) + +/** + * device_foreach_child() - iterate through child devices + * + * @pos: struct udevice * for the current device + * @parent: parent device to scan + */ +#define device_foreach_child(pos, parent) \ + list_for_each_entry(pos, &parent->child_head, sibling_node) + +/** + * device_foreach_child_of_to_plat() - iterate through children + * + * This stops when it gets an error, with @pos set to the device that failed to + * read ofdata. + + * This creates a for() loop which works through the available children of + * a device in order from start to end. Device ofdata is read by calling + * device_of_to_plat() on each one. The devices are not probed. + * + * @pos: struct udevice * for the current device + * @parent: parent device to scan + */ +#define device_foreach_child_of_to_plat(pos, parent) \ + for (int _ret = device_first_child_ofdata_err(parent, &dev); !_ret; \ + _ret = device_next_child_ofdata_err(&dev)) + +/** + * device_foreach_child_probe() - iterate through children, probing them + * + * This creates a for() loop which works through the available children of + * a device in order from start to end. Devices are probed if necessary, + * and ready for use. + * + * This stops when it gets an error, with @pos set to the device that failed to + * probe + * + * @pos: struct udevice * for the current device + * @parent: parent device to scan + */ +#define device_foreach_child_probe(pos, parent) \ + for (int _ret = device_first_child_err(parent, &dev); !_ret; \ + _ret = device_next_child_err(&dev)) + +/** + * dm_scan_fdt_dev() - Bind child device in the device tree + * + * This handles device which have sub-nodes in the device tree. It scans all + * sub-nodes and binds drivers for each node where a driver can be found. + * + * If this is called prior to relocation, only pre-relocation devices will be + * bound (those marked with u-boot,dm-pre-reloc in the device tree, or where + * the driver has the DM_FLAG_PRE_RELOC flag set). Otherwise, all devices will + * be bound. + * + * @dev: Device to scan + * @return 0 if OK, -ve on error + */ +int dm_scan_fdt_dev(struct udevice *dev); + +#endif diff --git a/roms/u-boot/include/dm/device_compat.h b/roms/u-boot/include/dm/device_compat.h new file mode 100644 index 000000000..82d7a7d49 --- /dev/null +++ b/roms/u-boot/include/dm/device_compat.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Sean Anderson + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * Marek Vasut + */ + +#ifndef _DM_DEVICE_COMPAT_H +#define _DM_DEVICE_COMPAT_H + +#include +#include +#include + +/* + * Define a new identifier which can be tested on by C code. A similar + * definition is made for DEBUG in . + */ +#ifdef VERBOSE_DEBUG +#define _VERBOSE_DEBUG 1 +#else +#define _VERBOSE_DEBUG 0 +#endif + +/** + * dev_printk_emit() - Emit a formatted log message + * @cat: Category of the message + * @level: Log level of the message + * @fmt: Format string + * @...: Arguments for @fmt + * + * This macro logs a message through the appropriate channel. It is a macro so + * the if statements can be optimized out (as @level should be a constant known + * at compile-time). + * + * If DEBUG or VERBOSE_DEBUG is defined, then some messages are always printed + * (through printf()). This is to match the historical behavior of the dev_xxx + * functions. + * + * If LOG is enabled, use log() to emit the message, otherwise print it based on + * the console loglevel. + */ +#define dev_printk_emit(cat, level, fmt, ...) \ +({ \ + if ((_DEBUG && level == LOGL_DEBUG) || \ + (_VERBOSE_DEBUG && level == LOGL_DEBUG_CONTENT)) \ + printf(fmt, ##__VA_ARGS__); \ + else if (CONFIG_IS_ENABLED(LOG)) \ + log(cat, level, fmt, ##__VA_ARGS__); \ + else if (level < CONFIG_VAL(LOGLEVEL)) \ + printf(fmt, ##__VA_ARGS__); \ +}) + +/** + * __dev_printk() - Log a message for a device + * @level: Log level of the message + * @dev: A &struct udevice or &struct device + * @fmt: Format string + * @...: Arguments for @fmt + * + * This macro formats and prints dev_xxx log messages. It is done as a macro + * because working with variadic argument is much easier this way, we can + * interrogate the type of device we are passed (and whether it *is* a &struct + * udevice or &struct device), and dev_printk_emit() can optimize out unused if + * branches. + * + * Because this is a macro, we must enforce type checks ourselves. Ideally, we + * would only accept udevices, but there is a significant amount of code (mostly + * USB) which calls dev_xxx with &struct device. When assigning ``__dev``, we + * must first cast ``dev`` to ``void *`` so we don't get warned when ``dev`` is + * a &struct device. Even though the latter branch is not taken, it will still + * get compiled and type-checked. + * + * The format strings in case of a ``NULL`` ``dev`` MUST be kept the same. + * Otherwise, @fmt will be duplicated in the data section (with slightly + * different prefixes). This is why ``(NULL udevice *)`` is printed as two + * string arguments, and not by string pasting. + */ +#define __dev_printk(level, dev, fmt, ...) \ +({ \ + if (__same_type(dev, struct device *)) { \ + dev_printk_emit(LOG_CATEGORY, level, fmt, ##__VA_ARGS__); \ + } else { \ + BUILD_BUG_ON(!__same_type(dev, struct udevice *)); \ + struct udevice *__dev = (void *)dev; \ + if (__dev) \ + dev_printk_emit(__dev->driver->id, level, \ + "%s %s: " fmt, \ + __dev->driver->name, __dev->name, \ + ##__VA_ARGS__); \ + else \ + dev_printk_emit(LOG_CATEGORY, level, \ + "%s %s: " fmt, \ + "(NULL", "udevice *)", \ + ##__VA_ARGS__); \ + } \ +}) + +#define dev_emerg(dev, fmt, ...) \ + __dev_printk(LOGL_EMERG, dev, fmt, ##__VA_ARGS__) +#define dev_alert(dev, fmt, ...) \ + __dev_printk(LOGL_ALERT, dev, fmt, ##__VA_ARGS__) +#define dev_crit(dev, fmt, ...) \ + __dev_printk(LOGL_CRIT, dev, fmt, ##__VA_ARGS__) +#define dev_err(dev, fmt, ...) \ + __dev_printk(LOGL_ERR, dev, fmt, ##__VA_ARGS__) +#define dev_warn(dev, fmt, ...) \ + __dev_printk(LOGL_WARNING, dev, fmt, ##__VA_ARGS__) +#define dev_notice(dev, fmt, ...) \ + __dev_printk(LOGL_NOTICE, dev, fmt, ##__VA_ARGS__) +#define dev_info(dev, fmt, ...) \ + __dev_printk(LOGL_INFO, dev, fmt, ##__VA_ARGS__) +#define dev_dbg(dev, fmt, ...) \ + __dev_printk(LOGL_DEBUG, dev, fmt, ##__VA_ARGS__) +#define dev_vdbg(dev, fmt, ...) \ + __dev_printk(LOGL_DEBUG_CONTENT, dev, fmt, ##__VA_ARGS__) + +#endif diff --git a/roms/u-boot/include/dm/devres.h b/roms/u-boot/include/dm/devres.h new file mode 100644 index 000000000..17bb1ee8d --- /dev/null +++ b/roms/u-boot/include/dm/devres.h @@ -0,0 +1,293 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * Based on the original work in Linux by + * Copyright (c) 2006 SUSE Linux Products GmbH + * Copyright (c) 2006 Tejun Heo + * Copyright 2019 Google LLC + */ + +#ifndef _DM_DEVRES_H +#define _DM_DEVRES_H + +#include + +struct udevice; + +/* device resource management */ +typedef void (*dr_release_t)(struct udevice *dev, void *res); +typedef int (*dr_match_t)(struct udevice *dev, void *res, void *match_data); + +/** + * struct devres_stats - Information about devres allocations for a device + * + * @allocs: Number of allocations + * @total_size: Total size of allocations in bytes + */ +struct devres_stats { + int allocs; + int total_size; +}; + +#ifdef CONFIG_DEVRES + +#ifdef CONFIG_DEBUG_DEVRES +void *__devres_alloc(dr_release_t release, size_t size, gfp_t gfp, + const char *name); +#define _devres_alloc(release, size, gfp) \ + __devres_alloc(release, size, gfp, #release) +#else +void *_devres_alloc(dr_release_t release, size_t size, gfp_t gfp); +#endif + +/** + * devres_alloc() - Allocate device resource data + * @release: Release function devres will be associated with + * @size: Allocation size + * @gfp: Allocation flags + * + * Allocate devres of @size bytes. The allocated area is associated + * with @release. The returned pointer can be passed to + * other devres_*() functions. + * + * RETURNS: + * Pointer to allocated devres on success, NULL on failure. + */ +#define devres_alloc(release, size, gfp) \ + _devres_alloc(release, size, (gfp) | __GFP_ZERO) + +/** + * devres_free() - Free device resource data + * @res: Pointer to devres data to free + * + * Free devres created with devres_alloc(). + */ +void devres_free(void *res); + +/** + * devres_add() - Register device resource + * @dev: Device to add resource to + * @res: Resource to register + * + * Register devres @res to @dev. @res should have been allocated + * using devres_alloc(). On driver detach, the associated release + * function will be invoked and devres will be freed automatically. + */ +void devres_add(struct udevice *dev, void *res); + +/** + * devres_find() - Find device resource + * @dev: Device to lookup resource from + * @release: Look for resources associated with this release function + * @match: Match function (optional) + * @match_data: Data for the match function + * + * Find the latest devres of @dev which is associated with @release + * and for which @match returns 1. If @match is NULL, it's considered + * to match all. + * + * @return pointer to found devres, NULL if not found. + */ +void *devres_find(struct udevice *dev, dr_release_t release, + dr_match_t match, void *match_data); + +/** + * devres_get() - Find devres, if non-existent, add one atomically + * @dev: Device to lookup or add devres for + * @new_res: Pointer to new initialized devres to add if not found + * @match: Match function (optional) + * @match_data: Data for the match function + * + * Find the latest devres of @dev which has the same release function + * as @new_res and for which @match return 1. If found, @new_res is + * freed; otherwise, @new_res is added atomically. + * + * @return ointer to found or added devres. + */ +void *devres_get(struct udevice *dev, void *new_res, + dr_match_t match, void *match_data); + +/** + * devres_remove() - Find a device resource and remove it + * @dev: Device to find resource from + * @release: Look for resources associated with this release function + * @match: Match function (optional) + * @match_data: Data for the match function + * + * Find the latest devres of @dev associated with @release and for + * which @match returns 1. If @match is NULL, it's considered to + * match all. If found, the resource is removed atomically and + * returned. + * + * @return ointer to removed devres on success, NULL if not found. + */ +void *devres_remove(struct udevice *dev, dr_release_t release, + dr_match_t match, void *match_data); + +/** + * devres_destroy() - Find a device resource and destroy it + * @dev: Device to find resource from + * @release: Look for resources associated with this release function + * @match: Match function (optional) + * @match_data: Data for the match function + * + * Find the latest devres of @dev associated with @release and for + * which @match returns 1. If @match is NULL, it's considered to + * match all. If found, the resource is removed atomically and freed. + * + * Note that the release function for the resource will not be called, + * only the devres-allocated data will be freed. The caller becomes + * responsible for freeing any other data. + * + * @return 0 if devres is found and freed, -ENOENT if not found. + */ +int devres_destroy(struct udevice *dev, dr_release_t release, + dr_match_t match, void *match_data); + +/** + * devres_release() - Find a device resource and destroy it, calling release + * @dev: Device to find resource from + * @release: Look for resources associated with this release function + * @match: Match function (optional) + * @match_data: Data for the match function + * + * Find the latest devres of @dev associated with @release and for + * which @match returns 1. If @match is NULL, it's considered to + * match all. If found, the resource is removed atomically, the + * release function called and the resource freed. + * + * @return 0 if devres is found and freed, -ENOENT if not found. + */ +int devres_release(struct udevice *dev, dr_release_t release, + dr_match_t match, void *match_data); + +/* managed devm_k.alloc/kfree for device drivers */ +/** + * devm_kmalloc() - Resource-managed kmalloc + * @dev: Device to allocate memory for + * @size: Allocation size + * @gfp: Allocation gfp flags + * + * Managed kmalloc. Memory allocated with this function is + * automatically freed on driver detach. Like all other devres + * resources, guaranteed alignment is unsigned long long. + * + * @return pointer to allocated memory on success, NULL on failure. + */ +void *devm_kmalloc(struct udevice *dev, size_t size, gfp_t gfp); +static inline void *devm_kzalloc(struct udevice *dev, size_t size, gfp_t gfp) +{ + return devm_kmalloc(dev, size, gfp | __GFP_ZERO); +} + +static inline void *devm_kmalloc_array(struct udevice *dev, + size_t n, size_t size, gfp_t flags) +{ + if (size != 0 && n > SIZE_MAX / size) + return NULL; + return devm_kmalloc(dev, n * size, flags); +} + +static inline void *devm_kcalloc(struct udevice *dev, + size_t n, size_t size, gfp_t flags) +{ + return devm_kmalloc_array(dev, n, size, flags | __GFP_ZERO); +} + +/** + * devm_kfree() - Resource-managed kfree + * @dev: Device this memory belongs to + * @ptr: Memory to free + * + * Free memory allocated with devm_kmalloc(). + */ +void devm_kfree(struct udevice *dev, void *ptr); + +/* Get basic stats on allocations */ +void devres_get_stats(const struct udevice *dev, struct devres_stats *stats); + +#else /* ! CONFIG_DEVRES */ + +static inline void *devres_alloc(dr_release_t release, size_t size, gfp_t gfp) +{ + return kzalloc(size, gfp); +} + +static inline void devres_free(void *res) +{ + kfree(res); +} + +static inline void devres_add(struct udevice *dev, void *res) +{ +} + +static inline void *devres_find(struct udevice *dev, dr_release_t release, + dr_match_t match, void *match_data) +{ + return NULL; +} + +static inline void *devres_get(struct udevice *dev, void *new_res, + dr_match_t match, void *match_data) +{ + return NULL; +} + +static inline void *devres_remove(struct udevice *dev, dr_release_t release, + dr_match_t match, void *match_data) +{ + return NULL; +} + +static inline int devres_destroy(struct udevice *dev, dr_release_t release, + dr_match_t match, void *match_data) +{ + return 0; +} + +static inline int devres_release(struct udevice *dev, dr_release_t release, + dr_match_t match, void *match_data) +{ + return 0; +} + +static inline void *devm_kmalloc(struct udevice *dev, size_t size, gfp_t gfp) +{ + return kmalloc(size, gfp); +} + +static inline void *devm_kzalloc(struct udevice *dev, size_t size, gfp_t gfp) +{ + return kzalloc(size, gfp); +} + +static inline void *devm_kmalloc_array(struct udevice *dev, + size_t n, size_t size, gfp_t flags) +{ + /* TODO: add kmalloc_array() to linux/compat.h */ + if (size != 0 && n > SIZE_MAX / size) + return NULL; + return kmalloc(n * size, flags); +} + +static inline void *devm_kcalloc(struct udevice *dev, + size_t n, size_t size, gfp_t flags) +{ + /* TODO: add kcalloc() to linux/compat.h */ + return kmalloc(n * size, flags | __GFP_ZERO); +} + +static inline void devm_kfree(struct udevice *dev, void *ptr) +{ + kfree(ptr); +} + +static inline void devres_get_stats(const struct udevice *dev, + struct devres_stats *stats) +{ +} + +#endif /* DEVRES */ +#endif /* _DM_DEVRES_H */ diff --git a/roms/u-boot/include/dm/fdtaddr.h b/roms/u-boot/include/dm/fdtaddr.h new file mode 100644 index 000000000..a4fda581a --- /dev/null +++ b/roms/u-boot/include/dm/fdtaddr.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2017 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * Marek Vasut + */ + +#ifndef _DM_FDTADDR_H +#define _DM_FDTADDR_H + +#include + +struct udevice; + +/** + * devfdt_get_addr() - Get the reg property of a device + * + * @dev: Pointer to a device + * + * @return addr + */ +fdt_addr_t devfdt_get_addr(const struct udevice *dev); + +/** + * devfdt_get_addr_ptr() - Return pointer to the address of the reg property + * of a device + * + * @dev: Pointer to a device + * + * @return Pointer to addr, or NULL if there is no such property + */ +void *devfdt_get_addr_ptr(const struct udevice *dev); + +/** + * devfdt_remap_addr() - Return pointer to the memory-mapped I/O address + * of the reg property of a device + * + * @dev: Pointer to a device + * + * @return Pointer to addr, or NULL if there is no such property + */ +void *devfdt_remap_addr(const struct udevice *dev); + +/** + * devfdt_remap_addr_index() - Return indexed pointer to the memory-mapped + * I/O address of the reg property of a device + * @index: the 'reg' property can hold a list of pairs + * and @index is used to select which one is required + * + * @dev: Pointer to a device + * + * @return Pointer to addr, or NULL if there is no such property + */ +void *devfdt_remap_addr_index(const struct udevice *dev, int index); + +/** + * devfdt_remap_addr_name() - Get the reg property of a device, indexed by + * name, as a memory-mapped I/O pointer + * @name: the 'reg' property can hold a list of pairs, with the + * 'reg-names' property providing named-based identification. @index + * indicates the value to search for in 'reg-names'. + * + * @dev: Pointer to a device + * + * @return Pointer to addr, or NULL if there is no such property + */ +void *devfdt_remap_addr_name(const struct udevice *dev, const char *name); + +/** + * devfdt_map_physmem() - Read device address from reg property of the + * device node and map the address into CPU address + * space. + * + * @dev: Pointer to device + * @size: size of the memory to map + * + * @return mapped address, or NULL if the device does not have reg + * property. + */ +void *devfdt_map_physmem(const struct udevice *dev, unsigned long size); + +/** + * devfdt_get_addr_index() - Get the indexed reg property of a device + * + * @dev: Pointer to a device + * @index: the 'reg' property can hold a list of pairs + * and @index is used to select which one is required + * + * @return addr + */ +fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index); + +/** + * devfdt_get_addr_size_index() - Get the indexed reg property of a device + * + * Returns the address and size specified in the 'reg' property of a device. + * + * @dev: Pointer to a device + * @index: the 'reg' property can hold a list of pairs + * and @index is used to select which one is required + * @size: Pointer to size varible - this function returns the size + * specified in the 'reg' property here + * + * @return addr + */ +fdt_addr_t devfdt_get_addr_size_index(const struct udevice *dev, int index, + fdt_size_t *size); + +/** + * devfdt_get_addr_name() - Get the reg property of a device, indexed by name + * + * @dev: Pointer to a device + * @name: the 'reg' property can hold a list of pairs, with the + * 'reg-names' property providing named-based identification. @index + * indicates the value to search for in 'reg-names'. + * + * @return addr + */ +fdt_addr_t devfdt_get_addr_name(const struct udevice *dev, const char *name); + +/** + * devfdt_get_addr_size_name() - Get the reg property and its size for a device, + * indexed by name + * + * Returns the address and size specified in the 'reg' property of a device. + * + * @dev: Pointer to a device + * @name: the 'reg' property can hold a list of pairs, with the + * 'reg-names' property providing named-based identification. @index + * indicates the value to search for in 'reg-names'. + * @size: Pointer to size variable - this function returns the size + * specified in the 'reg' property here + * + * @return addr + */ +fdt_addr_t devfdt_get_addr_size_name(const struct udevice *dev, + const char *name, fdt_size_t *size); + +/** + * devfdt_get_addr_pci() - Read an address and handle PCI address translation + * + * @dev: Device to read from + * @return address or FDT_ADDR_T_NONE if not found + */ +fdt_addr_t devfdt_get_addr_pci(const struct udevice *dev); + +#endif diff --git a/roms/u-boot/include/dm/lists.h b/roms/u-boot/include/dm/lists.h new file mode 100644 index 000000000..1a8655254 --- /dev/null +++ b/roms/u-boot/include/dm/lists.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + */ + +#ifndef _DM_LISTS_H_ +#define _DM_LISTS_H_ + +#include +#include + +/** + * lists_driver_lookup_name() - Return u_boot_driver corresponding to name + * + * This function returns a pointer to a driver given its name. This is used + * for binding a driver given its name and plat. + * + * @name: Name of driver to look up + * @return pointer to driver, or NULL if not found + */ +struct driver *lists_driver_lookup_name(const char *name); + +/** + * lists_uclass_lookup() - Return uclass_driver based on ID of the class + * id: ID of the class + * + * This function returns the pointer to uclass_driver, which is the class's + * base structure based on the ID of the class. Returns NULL on error. + */ +struct uclass_driver *lists_uclass_lookup(enum uclass_id id); + +/** + * lists_bind_drivers() - search for and bind all drivers to parent + * + * This searches the U_BOOT_DRVINFO() structures and creates new devices for + * each one. The devices will have @parent as their parent. + * + * @parent: parent device (root) + * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC flag. + * If false bind all drivers. + */ +int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only); + +/** + * lists_bind_fdt() - bind a device tree node + * + * This creates a new device bound to the given device tree node, with + * @parent as its parent. + * + * @parent: parent device (root) + * @node: device tree node to bind + * @devp: if non-NULL, returns a pointer to the bound device + * @pre_reloc_only: If true, bind only nodes with special devicetree properties, + * or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers. + * @return 0 if device was bound, -EINVAL if the device tree is invalid, + * other -ve value on error + */ +int lists_bind_fdt(struct udevice *parent, ofnode node, struct udevice **devp, + bool pre_reloc_only); + +/** + * device_bind_driver() - bind a device to a driver + * + * This binds a new device to a driver. + * + * @parent: Parent device + * @drv_name: Name of driver to attach to this parent + * @dev_name: Name of the new device thus created + * @devp: If non-NULL, returns the newly bound device + */ +int device_bind_driver(struct udevice *parent, const char *drv_name, + const char *dev_name, struct udevice **devp); + +/** + * device_bind_driver_to_node() - bind a device to a driver for a node + * + * This binds a new device to a driver for a given device tree node. This + * should only be needed if the node lacks a compatible strings. + * + * @parent: Parent device + * @drv_name: Name of driver to attach to this parent + * @dev_name: Name of the new device thus created + * @node: Device tree node + * @devp: If non-NULL, returns the newly bound device + */ +int device_bind_driver_to_node(struct udevice *parent, const char *drv_name, + const char *dev_name, ofnode node, + struct udevice **devp); + +#endif diff --git a/roms/u-boot/include/dm/of.h b/roms/u-boot/include/dm/of.h new file mode 100644 index 000000000..5cb6f44a6 --- /dev/null +++ b/roms/u-boot/include/dm/of.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2017 Google, Inc + * Written by Simon Glass + */ + +#ifndef _DM_OF_H +#define _DM_OF_H + +#include +#include + +/* integer value within a device tree property which references another node */ +typedef u32 phandle; + +/** + * struct property: Device tree property + * + * @name: Property name + * @length: Length of property in bytes + * @value: Pointer to property value + * @next: Pointer to next property, or NULL if none + */ +struct property { + char *name; + int length; + void *value; + struct property *next; +}; + +/** + * struct device_node: Device tree node + * + * @name: Node name + * @type: Node type (value of device_type property) or "" if none + * @phandle: Phandle value of this none, or 0 if none + * @full_name: Full path to node, e.g. "/bus@1/spi@1100" + * @properties: Pointer to head of list of properties, or NULL if none + * @parent: Pointer to parent node, or NULL if this is the root node + * @child: Pointer to head of child node list, or NULL if no children + * @sibling: Pointer to the next sibling node, or NULL if this is the last + */ +struct device_node { + const char *name; + const char *type; + phandle phandle; + const char *full_name; + + struct property *properties; + struct device_node *parent; + struct device_node *child; + struct device_node *sibling; +}; + +#define OF_MAX_PHANDLE_ARGS 16 + +/** + * struct of_phandle_args - structure to hold phandle and arguments + * + * This is used when decoding a phandle in a device tree property. Typically + * these look like this: + * + * wibble { + * phandle = <5>; + * }; + * + * ... + * some-prop = <&wibble 1 2 3> + * + * Here &node is the phandle of the node 'wibble', i.e. 5. There are three + * arguments: 1, 2, 3. + * + * So when decoding the phandle in some-prop, np will point to wibble, + * args_count will be 3 and the three arguments will be in args. + * + * @np: Node that the phandle refers to + * @args_count: Number of arguments + * @args: Argument values + */ +struct of_phandle_args { + struct device_node *np; + int args_count; + uint32_t args[OF_MAX_PHANDLE_ARGS]; +}; + +DECLARE_GLOBAL_DATA_PTR; + +/** + * of_live_active() - check if livetree is active + * + * @returns true if livetree is active, false it not + */ +static inline bool of_live_active(void) +{ + return gd_of_root() != NULL; +} + +#define OF_BAD_ADDR ((u64)-1) + +static inline const char *of_node_full_name(const struct device_node *np) +{ + return np ? np->full_name : ""; +} + +/* Default #address and #size cells */ +#if !defined(OF_ROOT_NODE_ADDR_CELLS_DEFAULT) +#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 2 +#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1 +#endif + +/* Default string compare functions */ +#if !defined(of_compat_cmp) +#define of_compat_cmp(s1, s2, l) strcasecmp((s1), (s2)) +#define of_prop_cmp(s1, s2) strcmp((s1), (s2)) +#define of_node_cmp(s1, s2) strcasecmp((s1), (s2)) +#endif + +/* Helper to read a big number; size is in cells (not bytes) */ +static inline u64 of_read_number(const __be32 *cell, int size) +{ + u64 r = 0; + while (size--) + r = (r << 32) | be32_to_cpu(*(cell++)); + return r; +} + +/* Like of_read_number, but we want an unsigned long result */ +static inline unsigned long of_read_ulong(const __be32 *cell, int size) +{ + /* toss away upper bits if unsigned long is smaller than u64 */ + return of_read_number(cell, size); +} + +#endif diff --git a/roms/u-boot/include/dm/of_access.h b/roms/u-boot/include/dm/of_access.h new file mode 100644 index 000000000..cc382b167 --- /dev/null +++ b/roms/u-boot/include/dm/of_access.h @@ -0,0 +1,507 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Originally from Linux v4.9 + * Copyright (C) 1996-2005 Paul Mackerras. + * + * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp. + * Updates for SPARC64 by David S. Miller + * Derived from PowerPC and Sparc prom.h files by Stephen Rothwell, IBM Corp. + * + * Copyright (c) 2017 Google, Inc + * Written by Simon Glass + * + * Modified for U-Boot + * Copyright (c) 2017 Google, Inc + */ + +#ifndef _DM_OF_ACCESS_H +#define _DM_OF_ACCESS_H + +#include + +/** + * of_find_all_nodes - Get next node in global list + * @prev: Previous node or NULL to start iteration + * of_node_put() will be called on it + * + * Returns a node pointer with refcount incremented, use + * of_node_put() on it when done. + */ +struct device_node *of_find_all_nodes(struct device_node *prev); + +#define for_each_of_allnodes_from(from, dn) \ + for (dn = of_find_all_nodes(from); dn; dn = of_find_all_nodes(dn)) +#define for_each_of_allnodes(dn) for_each_of_allnodes_from(NULL, dn) + +/* Dummy functions to mirror Linux. These are not used in U-Boot */ +#define of_node_get(x) (x) +static inline void of_node_put(const struct device_node *np) { } + +/** + * of_n_addr_cells() - Get the number of address cells for a node + * + * This walks back up the tree to find the closest #address-cells property + * which controls the given node. + * + * @np: Node pointer to check + * @return number of address cells this node uses + */ +int of_n_addr_cells(const struct device_node *np); + +/** + * of_n_size_cells() - Get the number of size cells for a node + * + * This walks back up the tree to find the closest #size-cells property + * which controls the given node. + * + * @np: Node pointer to check + * @return number of size cells this node uses + */ +int of_n_size_cells(const struct device_node *np); + +/** + * of_simple_addr_cells() - Get the address cells property in a node + * + * This function matches fdt_address_cells(). + * + * @np: Node pointer to check + * @return value of #address-cells property in this node, or 2 if none + */ +int of_simple_addr_cells(const struct device_node *np); + +/** + * of_simple_size_cells() - Get the size cells property in a node + * + * This function matches fdt_size_cells(). + * + * @np: Node pointer to check + * @return value of #size-cells property in this node, or 2 if none + */ +int of_simple_size_cells(const struct device_node *np); + +/** + * of_find_property() - find a property in a node + * + * @np: Pointer to device node holding property + * @name: Name of property + * @lenp: If non-NULL, returns length of property + * @return pointer to property, or NULL if not found + */ +struct property *of_find_property(const struct device_node *np, + const char *name, int *lenp); + +/** + * of_get_property() - get a property value + * + * Find a property with a given name for a given node and return the value. + * + * @np: Pointer to device node holding property + * @name: Name of property + * @lenp: If non-NULL, returns length of property + * @return pointer to property value, or NULL if not found + */ +const void *of_get_property(const struct device_node *np, const char *name, + int *lenp); + +/** + * of_get_first_property()- get to the pointer of the first property + * + * Get pointer to the first property of the node, it is used to iterate + * and read all the property with of_get_next_property_by_prop(). + * + * @np: Pointer to device node + * @return pointer to property or NULL if not found + */ +const struct property *of_get_first_property(const struct device_node *np); + +/** + * of_get_next_property() - get to the pointer of the next property + * + * Get pointer to the next property of the node, it is used to iterate + * and read all the property with of_get_property_by_prop(). + * + * @np: Pointer to device node + * @property: pointer of the current property + * @return pointer to next property or NULL if not found + */ +const struct property *of_get_next_property(const struct device_node *np, + const struct property *property); + +/** + * of_get_property_by_prop() - get a property value of a node property + * + * Get value for the property identified by node and property pointer. + * + * @node: node to read + * @property: pointer of the property to read + * @propname: place to property name on success + * @lenp: place to put length on success + * @return pointer to property value or NULL if error + */ +const void *of_get_property_by_prop(const struct device_node *np, + const struct property *property, + const char **name, + int *lenp); + +/** + * of_device_is_compatible() - Check if the node matches given constraints + * @device: pointer to node + * @compat: required compatible string, NULL or "" for any match + * @type: required device_type value, NULL or "" for any match + * @name: required node name, NULL or "" for any match + * + * Checks if the given @compat, @type and @name strings match the + * properties of the given @device. A constraints can be skipped by + * passing NULL or an empty string as the constraint. + * + * @return 0 for no match, and a positive integer on match. The return + * value is a relative score with larger values indicating better + * matches. The score is weighted for the most specific compatible value + * to get the highest score. Matching type is next, followed by matching + * name. Practically speaking, this results in the following priority + * order for matches: + * + * 1. specific compatible && type && name + * 2. specific compatible && type + * 3. specific compatible && name + * 4. specific compatible + * 5. general compatible && type && name + * 6. general compatible && type + * 7. general compatible && name + * 8. general compatible + * 9. type && name + * 10. type + * 11. name + */ +int of_device_is_compatible(const struct device_node *np, const char *compat, + const char *type, const char *name); + +/** + * of_device_is_available() - check if a device is available for use + * + * @device: Node to check for availability + * + * @return true if the status property is absent or set to "okay", false + * otherwise + */ +bool of_device_is_available(const struct device_node *np); + +/** + * of_get_parent() - Get a node's parent, if any + * + * @node: Node to check + * @eturns a node pointer, or NULL if none + */ +struct device_node *of_get_parent(const struct device_node *np); + +/** + * of_find_node_opts_by_path() - Find a node matching a full OF path + * + * @path: Either the full path to match, or if the path does not start with + * '/', the name of a property of the /aliases node (an alias). In the + * case of an alias, the node matching the alias' value will be returned. + * @opts: Address of a pointer into which to store the start of an options + * string appended to the end of the path with a ':' separator. Can be NULL + * + * Valid paths: + * /foo/bar Full path + * foo Valid alias + * foo/bar Valid alias + relative path + * + * @return a node pointer or NULL if not found + */ +struct device_node *of_find_node_opts_by_path(const char *path, + const char **opts); + +static inline struct device_node *of_find_node_by_path(const char *path) +{ + return of_find_node_opts_by_path(path, NULL); +} + +/** + * of_find_compatible_node() - find a node based on its compatible string + * + * Find a node based on type and one of the tokens in its "compatible" property + * @from: Node to start searching from or NULL. the node you pass will not be + * searched, only the next one will; typically, you pass what the previous + * call returned. + * @type: The type string to match "device_type" or NULL to ignore + * @compatible: The string to match to one of the tokens in the device + * "compatible" list. + * @return node pointer or NULL if not found + */ +struct device_node *of_find_compatible_node(struct device_node *from, + const char *type, const char *compatible); + +/** + * of_find_node_by_prop_value() - find a node with a given property value + * + * Find a node based on a property value. + * @from: Node to start searching from or NULL. the node you pass will not be + * searched, only the next one will; typically, you pass what the previous + * call returned. + * @propname: property name to check + * @propval: property value to search for + * @proplen: length of the value in propval + * @return node pointer or NULL if not found + */ +struct device_node *of_find_node_by_prop_value(struct device_node *from, + const char *propname, + const void *propval, + int proplen); +/** + * of_find_node_by_phandle() - Find a node given a phandle + * + * @handle: phandle of the node to find + * + * @return node pointer, or NULL if not found + */ +struct device_node *of_find_node_by_phandle(phandle handle); + +/** + * of_read_u32() - Find and read a 32-bit integer from a property + * + * Search for a property in a device node and read a 32-bit value from + * it. + * + * @np: device node from which the property value is to be read. + * @propname: name of the property to be searched. + * @outp: pointer to return value, modified only if return value is 0. + * + * @return 0 on success, -EINVAL if the property does not exist, + * -ENODATA if property does not have a value, and -EOVERFLOW if the + * property data isn't large enough. + */ +int of_read_u32(const struct device_node *np, const char *propname, u32 *outp); + +/** + * of_read_u32_index() - Find and read a 32-bit value from a multi-value + * property + * + * Search for a property in a device node and read a 32-bit value from + * it. + * + * @np: device node from which the property value is to be read. + * @propname: name of the property to be searched. + * @index: index of the u32 in the list of values + * @outp: pointer to return value, modified only if return value is 0. + * + * @return 0 on success, -EINVAL if the property does not exist, + * -ENODATA if property does not have a value, and -EOVERFLOW if the + * property data isn't large enough. + */ +int of_read_u32_index(const struct device_node *np, const char *propname, + int index, u32 *outp); + +/** + * of_read_u64() - Find and read a 64-bit integer from a property + * + * Search for a property in a device node and read a 64-bit value from + * it. + * + * @np: device node from which the property value is to be read. + * @propname: name of the property to be searched. + * @outp: pointer to return value, modified only if return value is 0. + * + * @return 0 on success, -EINVAL if the property does not exist, + * -ENODATA if property does not have a value, and -EOVERFLOW if the + * property data isn't large enough. + */ +int of_read_u64(const struct device_node *np, const char *propname, u64 *outp); + +/** + * of_read_u32_array() - Find and read an array of 32 bit integers + * + * Search for a property in a device node and read 32-bit value(s) from + * it. + * + * @np: device node from which the property value is to be read. + * @propname: name of the property to be searched. + * @out_values: pointer to return value, modified only if return value is 0. + * @sz: number of array elements to read + * @return 0 on success, -EINVAL if the property does not exist, -ENODATA + * if property does not have a value, and -EOVERFLOW is longer than sz. + */ +int of_read_u32_array(const struct device_node *np, const char *propname, + u32 *out_values, size_t sz); + +/** + * of_property_match_string() - Find string in a list and return index + * + * This function searches a string list property and returns the index + * of a specific string value. + * + * @np: pointer to node containing string list property + * @propname: string list property name + * @string: pointer to string to search for in string list + * @return 0 on success, -EINVAL if the property does not exist, -ENODATA + * if property does not have a value, and -EOVERFLOW is longer than sz. + */ +int of_property_match_string(const struct device_node *np, const char *propname, + const char *string); + +int of_property_read_string_helper(const struct device_node *np, + const char *propname, const char **out_strs, + size_t sz, int index); + +/** + * of_property_read_string_index() - Find and read a string from a multiple + * strings property. + * @np: device node from which the property value is to be read. + * @propname: name of the property to be searched. + * @index: index of the string in the list of strings + * @out_string: pointer to null terminated return string, modified only if + * return value is 0. + * + * Search for a property in a device tree node and retrieve a null + * terminated string value (pointer to data, not a copy) in the list of strings + * contained in that property. + * Returns 0 on success, -EINVAL if the property does not exist, -ENODATA if + * property does not have a value, and -EILSEQ if the string is not + * null-terminated within the length of the property data. + * + * The out_string pointer is modified only if a valid string can be decoded. + */ +static inline int of_property_read_string_index(const struct device_node *np, + const char *propname, + int index, const char **output) +{ + int rc = of_property_read_string_helper(np, propname, output, 1, index); + return rc < 0 ? rc : 0; +} + +/** + * of_property_count_strings() - Find and return the number of strings from a + * multiple strings property. + * @np: device node from which the property value is to be read. + * @propname: name of the property to be searched. + * + * Search for a property in a device tree node and retrieve the number of null + * terminated string contain in it. Returns the number of strings on + * success, -EINVAL if the property does not exist, -ENODATA if property + * does not have a value, and -EILSEQ if the string is not null-terminated + * within the length of the property data. + */ +static inline int of_property_count_strings(const struct device_node *np, + const char *propname) +{ + return of_property_read_string_helper(np, propname, NULL, 0, 0); +} + +/** + * of_parse_phandle - Resolve a phandle property to a device_node pointer + * @np: Pointer to device node holding phandle property + * @phandle_name: Name of property holding a phandle value + * @index: For properties holding a table of phandles, this is the index into + * the table + * + * Returns the device_node pointer with refcount incremented. Use + * of_node_put() on it when done. + */ +struct device_node *of_parse_phandle(const struct device_node *np, + const char *phandle_name, int index); + +/** + * of_parse_phandle_with_args() - Find a node pointed by phandle in a list + * + * @np: pointer to a device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cells_count: Cell count to use if @cells_name is NULL + * @index: index of a phandle to parse out + * @out_args: optional pointer to output arguments structure (will be filled) + * @return 0 on success (with @out_args filled out if not NULL), -ENOENT if + * @list_name does not exist, -EINVAL if a phandle was not found, + * @cells_name could not be found, the arguments were truncated or there + * were too many arguments. + * + * This function is useful to parse lists of phandles and their arguments. + * Returns 0 on success and fills out_args, on error returns appropriate + * errno value. + * + * Caller is responsible to call of_node_put() on the returned out_args->np + * pointer. + * + * Example: + * + * phandle1: node1 { + * #list-cells = <2>; + * } + * + * phandle2: node2 { + * #list-cells = <1>; + * } + * + * node3 { + * list = <&phandle1 1 2 &phandle2 3>; + * } + * + * To get a device_node of the `node2' node you may call this: + * of_parse_phandle_with_args(node3, "list", "#list-cells", 1, &args); + */ +int of_parse_phandle_with_args(const struct device_node *np, + const char *list_name, const char *cells_name, + int cells_count, int index, + struct of_phandle_args *out_args); + +/** + * of_count_phandle_with_args() - Count the number of phandle in a list + * + * @np: pointer to a device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cells_count: Cell count to use if @cells_name is NULL + * @return number of phandle found, -ENOENT if + * @list_name does not exist, -EINVAL if a phandle was not found, + * @cells_name could not be found, the arguments were truncated or there + * were too many arguments. + * + * Returns number of phandle found on success, on error returns appropriate + * errno value. + * + */ +int of_count_phandle_with_args(const struct device_node *np, + const char *list_name, const char *cells_name, + int cells_count); + +/** + * of_alias_scan() - Scan all properties of the 'aliases' node + * + * The function scans all the properties of the 'aliases' node and populates + * the lookup table with the properties. It returns the number of alias + * properties found, or an error code in case of failure. + * + * @return 9 if OK, -ENOMEM if not enough memory + */ +int of_alias_scan(void); + +/** + * of_alias_get_id - Get alias id for the given device_node + * + * Travels the lookup table to get the alias id for the given device_node and + * alias stem. + * + * @np: Pointer to the given device_node + * @stem: Alias stem of the given device_node + * @return alias ID, if found, else -ENODEV + */ +int of_alias_get_id(const struct device_node *np, const char *stem); + +/** + * of_alias_get_highest_id - Get highest alias id for the given stem + * @stem: Alias stem to be examined + * + * The function travels the lookup table to get the highest alias id for the + * given alias stem. + * @return alias ID, if found, else -1 + */ +int of_alias_get_highest_id(const char *stem); + +/** + * of_get_stdout() - Get node to use for stdout + * + * @return node referred to by stdout-path alias, or NULL if none + */ +struct device_node *of_get_stdout(void); + +#endif diff --git a/roms/u-boot/include/dm/of_addr.h b/roms/u-boot/include/dm/of_addr.h new file mode 100644 index 000000000..ee21d5cf4 --- /dev/null +++ b/roms/u-boot/include/dm/of_addr.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Taken from Linux v4.9 drivers/of/address.c + * + * Modified for U-Boot + * Copyright (c) 2017 Google, Inc + */ + +#ifndef _DM_OF_ADDR_H +#define _DM_OF_ADDR_H + +/** + * of_translate_address() - translate a device-tree address to a CPU address + * + * Translate an address from the device-tree into a CPU physical address, + * this walks up the tree and applies the various bus mappings on the way. + * + * Note: We consider that crossing any level with #size-cells == 0 to mean + * that translation is impossible (that is we are not dealing with a value + * that can be mapped to a cpu physical address). This is not really specified + * that way, but this is traditionally the way IBM at least do things + * + * @np: node to check + * @in_addr: pointer to input address + * @return translated address or OF_BAD_ADDR on error + */ +u64 of_translate_address(const struct device_node *no, const __be32 *in_addr); + +/** + * of_translate_dma_address() - translate a device-tree DMA address to a CPU + * address + * + * Translate a DMA address from the device-tree into a CPU physical address, + * this walks up the tree and applies the various bus mappings on the way. + * + * Note: We consider that crossing any level with #size-cells == 0 to mean + * that translation is impossible (that is we are not dealing with a value + * that can be mapped to a cpu physical address). This is not really specified + * that way, but this is traditionally the way IBM at least do things + * + * @np: node to check + * @in_addr: pointer to input DMA address + * @return translated DMA address or OF_BAD_ADDR on error + */ +u64 of_translate_dma_address(const struct device_node *no, const __be32 *in_addr); + + +/** + * of_get_dma_range() - get dma-ranges for a specific DT node + * + * Get DMA ranges for a specifc node, this is useful to perform bus->cpu and + * cpu->bus address translations + * + * @param blob Pointer to device tree blob + * @param node_offset Node DT offset + * @param cpu Pointer to variable storing the range's cpu address + * @param bus Pointer to variable storing the range's bus address + * @param size Pointer to variable storing the range's size + * @return translated DMA address or OF_BAD_ADDR on error + */ +int of_get_dma_range(const struct device_node *dev, phys_addr_t *cpu, + dma_addr_t *bus, u64 *size); + +/** + * of_get_address() - obtain an address from a node + * + * Extract an address from a node, returns the region size and the address + * space flags too. The PCI version uses a BAR number instead of an absolute + * index. + * + * @np: Node to check + * @index: Index of address to read (0 = first) + * @size: place to put size on success + * @flags: place to put flags on success + * @return pointer to address which can be read + */ +const __be32 *of_get_address(const struct device_node *no, int index, + u64 *size, unsigned int *flags); + +struct resource; + +/** + * of_address_to_resource() - translate device tree address to resource + * + * Note that if your address is a PIO address, the conversion will fail if + * the physical address can't be internally converted to an IO token with + * pci_address_to_pio(), that is because it's either called to early or it + * can't be matched to any host bridge IO space + * + * @np: node to check + * @index: index of address to read (0 = first) + * @r: place to put resource information + * @return 0 if OK, -ve on error + */ +int of_address_to_resource(const struct device_node *no, int index, + struct resource *r); + +#endif diff --git a/roms/u-boot/include/dm/of_extra.h b/roms/u-boot/include/dm/of_extra.h new file mode 100644 index 000000000..f0d205491 --- /dev/null +++ b/roms/u-boot/include/dm/of_extra.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2017 Google, Inc + * Written by Simon Glass + */ + +#ifndef _DM_OF_EXTRA_H +#define _DM_OF_EXTRA_H + +#include + +enum fmap_compress_t { + FMAP_COMPRESS_NONE, + FMAP_COMPRESS_LZMA, + FMAP_COMPRESS_LZ4, + + FMAP_COMPRESS_COUNT, + FMAP_COMPRESS_UNKNOWN, +}; + +enum fmap_hash_t { + FMAP_HASH_NONE, + FMAP_HASH_SHA1, + FMAP_HASH_SHA256, +}; + +/* A flash map entry, containing an offset and length */ +struct fmap_entry { + uint32_t offset; + uint32_t length; + uint32_t used; /* Number of bytes used in region */ + enum fmap_compress_t compress_algo; /* Compression type */ + uint32_t unc_length; /* Uncompressed length */ + enum fmap_hash_t hash_algo; /* Hash algorithm */ + const uint8_t *hash; /* Hash value */ + int hash_size; /* Hash size */ + /* Node pointer if CBFS, else NULL */ + const struct cbfs_cachenode *cbfs_node; + /* Hash node pointer if CBFS, else NULL */ + const struct cbfs_cachenode *cbfs_hash_node; +}; + +/** + * Read a flash entry from the fdt + * + * @param node Reference to node to read + * @param entry Place to put offset and size of this node + * @return 0 if ok, -ve on error + */ +int ofnode_read_fmap_entry(ofnode node, struct fmap_entry *entry); + +/** + * ofnode_decode_region() - Decode a memory region from a node + * + * Look up a property in a node which contains a memory region address and + * size. Then return a pointer to this address. + * + * The property must hold one address with a length. This is only tested on + * 32-bit machines. + * + * @param node ofnode to examine + * @param prop_name name of property to find + * @param basep Returns base address of region + * @param size Returns size of region + * @return 0 if ok, -1 on error (property not found) + */ +int ofnode_decode_region(ofnode node, const char *prop_name, fdt_addr_t *basep, + fdt_size_t *sizep); + +/** + * ofnode_decode_memory_region()- Decode a named region within a memory bank + * + * This function handles selection of a memory region. The region is + * specified as an offset/size within a particular type of memory. + * + * The properties used are: + * + * -memory for the name of the memory bank + * -offset for the offset in that bank + * + * The property value must have an offset and a size. The function checks + * that the region is entirely within the memory bank.5 + * + * @param node ofnode containing the properties (-1 for /config) + * @param mem_type Type of memory to use, which is a name, such as + * "u-boot" or "kernel". + * @param suffix String to append to the memory/offset + * property names + * @param basep Returns base of region + * @param sizep Returns size of region + * @return 0 if OK, -ive on error + */ +int ofnode_decode_memory_region(ofnode config_node, const char *mem_type, + const char *suffix, fdt_addr_t *basep, + fdt_size_t *sizep); + +/** + * ofnode_phy_is_fixed_link() - Detect fixed-link pseudo-PHY device + * + * This function detects whether the ethernet controller connects to a + * fixed-link pseudo-PHY device. + * + * This function supports the following two DT bindings: + * - the new DT binding, where 'fixed-link' is a sub-node of the + * Ethernet device + * - the old DT binding, where 'fixed-link' is a property with 5 + * cells encoding various information about the fixed PHY + * + * If both new and old bindings exist, the new one is preferred. + * + * @param eth_node ofnode containing the fixed-link subnode/property + * @param phy_node if fixed-link PHY detected, containing the PHY ofnode + * @return true if a fixed-link pseudo-PHY device exists, false otherwise + */ +bool ofnode_phy_is_fixed_link(ofnode eth_node, ofnode *phy_node); + +#endif diff --git a/roms/u-boot/include/dm/ofnode.h b/roms/u-boot/include/dm/ofnode.h new file mode 100644 index 000000000..8a69fd87d --- /dev/null +++ b/roms/u-boot/include/dm/ofnode.h @@ -0,0 +1,1083 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2017 Google, Inc + * Written by Simon Glass + */ + +#ifndef _DM_OFNODE_H +#define _DM_OFNODE_H + +/* TODO(sjg@chromium.org): Drop fdtdec.h include */ +#include +#include +#include +#include + +/* Enable checks to protect against invalid calls */ +#undef OF_CHECKS + +struct resource; + +/** + * ofnode - reference to a device tree node + * + * This union can hold either a straightforward pointer to a struct device_node + * in the live device tree, or an offset within the flat device tree. In the + * latter case, the pointer value is just the integer offset within the flat DT. + * + * Thus we can reference nodes in both the live tree (once available) and the + * flat tree (until then). Functions are available to translate between an + * ofnode and either an offset or a struct device_node *. + * + * The reference can also hold a null offset, in which case the pointer value + * here is NULL. This corresponds to a struct device_node * value of + * NULL, or an offset of -1. + * + * There is no ambiguity as to whether ofnode holds an offset or a node + * pointer: when the live tree is active it holds a node pointer, otherwise it + * holds an offset. The value itself does not need to be unique and in theory + * the same value could point to a valid device node or a valid offset. We + * could arrange for a unique value to be used (e.g. by making the pointer + * point to an offset within the flat device tree in the case of an offset) but + * this increases code size slightly due to the subtraction. Since it offers no + * real benefit, the approach described here seems best. + * + * For now these points use constant types, since we don't allow writing + * the DT. + * + * @np: Pointer to device node, used for live tree + * @of_offset: Pointer into flat device tree, used for flat tree. Note that this + * is not a really a pointer to a node: it is an offset value. See above. + */ +typedef union ofnode_union { + const struct device_node *np; + long of_offset; +} ofnode; + +struct ofnode_phandle_args { + ofnode node; + int args_count; + uint32_t args[OF_MAX_PHANDLE_ARGS]; +}; + +/** + * ofprop - reference to a property of a device tree node + * + * This struct hold the reference on one property of one node, + * using struct ofnode and an offset within the flat device tree or either + * a pointer to a struct property in the live device tree. + * + * Thus we can reference arguments in both the live tree and the flat tree. + * + * The property reference can also hold a null reference. This corresponds to + * a struct property NULL pointer or an offset of -1. + * + * @node: Pointer to device node + * @offset: Pointer into flat device tree, used for flat tree. + * @prop: Pointer to property, used for live treee. + */ + +struct ofprop { + ofnode node; + union { + int offset; + const struct property *prop; + }; +}; + +/** + * ofnode_to_np() - convert an ofnode to a live DT node pointer + * + * This cannot be called if the reference contains an offset. + * + * @node: Reference containing struct device_node * (possibly invalid) + * @return pointer to device node (can be NULL) + */ +static inline const struct device_node *ofnode_to_np(ofnode node) +{ +#ifdef OF_CHECKS + if (!of_live_active()) + return NULL; +#endif + return node.np; +} + +/** + * ofnode_to_offset() - convert an ofnode to a flat DT offset + * + * This cannot be called if the reference contains a node pointer. + * + * @node: Reference containing offset (possibly invalid) + * @return DT offset (can be -1) + */ +static inline int ofnode_to_offset(ofnode node) +{ +#ifdef OF_CHECKS + if (of_live_active()) + return -1; +#endif + return node.of_offset; +} + +/** + * ofnode_valid() - check if an ofnode is valid + * + * @return true if the reference contains a valid ofnode, false if it is NULL + */ +static inline bool ofnode_valid(ofnode node) +{ + if (of_live_active()) + return node.np != NULL; + else + return node.of_offset >= 0; +} + +/** + * offset_to_ofnode() - convert a DT offset to an ofnode + * + * @of_offset: DT offset (either valid, or -1) + * @return reference to the associated DT offset + */ +static inline ofnode offset_to_ofnode(int of_offset) +{ + ofnode node; + + if (of_live_active()) + node.np = NULL; + else + node.of_offset = of_offset >= 0 ? of_offset : -1; + + return node; +} + +/** + * np_to_ofnode() - convert a node pointer to an ofnode + * + * @np: Live node pointer (can be NULL) + * @return reference to the associated node pointer + */ +static inline ofnode np_to_ofnode(const struct device_node *np) +{ + ofnode node; + + node.np = np; + + return node; +} + +/** + * ofnode_is_np() - check if a reference is a node pointer + * + * This function associated that if there is a valid live tree then all + * references will use it. This is because using the flat DT when the live tree + * is valid is not permitted. + * + * @node: reference to check (possibly invalid) + * @return true if the reference is a live node pointer, false if it is a DT + * offset + */ +static inline bool ofnode_is_np(ofnode node) +{ +#ifdef OF_CHECKS + /* + * Check our assumption that flat tree offsets are not used when a + * live tree is in use. + */ + assert(!ofnode_valid(node) || + (of_live_active() ? ofnode_to_np(node) + : ofnode_to_np(node))); +#endif + return of_live_active() && ofnode_valid(node); +} + +/** + * ofnode_equal() - check if two references are equal + * + * @return true if equal, else false + */ +static inline bool ofnode_equal(ofnode ref1, ofnode ref2) +{ + /* We only need to compare the contents */ + return ref1.of_offset == ref2.of_offset; +} + +/** + * ofnode_null() - Obtain a null ofnode + * + * This returns an ofnode which points to no node. It works both with the flat + * tree and livetree. + */ +static inline ofnode ofnode_null(void) +{ + ofnode node; + + if (of_live_active()) + node.np = NULL; + else + node.of_offset = -1; + + return node; +} + +static inline ofnode ofnode_root(void) +{ + ofnode node; + + if (of_live_active()) + node.np = gd_of_root(); + else + node.of_offset = 0; + + return node; +} + +/** + * ofnode_read_u32() - Read a 32-bit integer from a property + * + * @ref: valid node reference to read property from + * @propname: name of the property to read from + * @outp: place to put value (if found) + * @return 0 if OK, -ve on error + */ +int ofnode_read_u32(ofnode node, const char *propname, u32 *outp); + +/** + * ofnode_read_u32_index() - Read a 32-bit integer from a multi-value property + * + * @ref: valid node reference to read property from + * @propname: name of the property to read from + * @index: index of the integer to return + * @outp: place to put value (if found) + * @return 0 if OK, -ve on error + */ +int ofnode_read_u32_index(ofnode node, const char *propname, int index, + u32 *outp); + +/** + * ofnode_read_s32() - Read a 32-bit integer from a property + * + * @ref: valid node reference to read property from + * @propname: name of the property to read from + * @outp: place to put value (if found) + * @return 0 if OK, -ve on error + */ +static inline int ofnode_read_s32(ofnode node, const char *propname, + s32 *out_value) +{ + return ofnode_read_u32(node, propname, (u32 *)out_value); +} + +/** + * ofnode_read_u32_default() - Read a 32-bit integer from a property + * + * @ref: valid node reference to read property from + * @propname: name of the property to read from + * @def: default value to return if the property has no value + * @return property value, or @def if not found + */ +u32 ofnode_read_u32_default(ofnode ref, const char *propname, u32 def); + +/** + * ofnode_read_u32_index_default() - Read a 32-bit integer from a multi-value + * property + * + * @ref: valid node reference to read property from + * @propname: name of the property to read from + * @index: index of the integer to return + * @def: default value to return if the property has no value + * @return property value, or @def if not found + */ +u32 ofnode_read_u32_index_default(ofnode ref, const char *propname, int index, + u32 def); + +/** + * ofnode_read_s32_default() - Read a 32-bit integer from a property + * + * @ref: valid node reference to read property from + * @propname: name of the property to read from + * @def: default value to return if the property has no value + * @return property value, or @def if not found + */ +int ofnode_read_s32_default(ofnode node, const char *propname, s32 def); + +/** + * ofnode_read_u64() - Read a 64-bit integer from a property + * + * @node: valid node reference to read property from + * @propname: name of the property to read from + * @outp: place to put value (if found) + * @return 0 if OK, -ve on error + */ +int ofnode_read_u64(ofnode node, const char *propname, u64 *outp); + +/** + * ofnode_read_u64_default() - Read a 64-bit integer from a property + * + * @ref: valid node reference to read property from + * @propname: name of the property to read from + * @def: default value to return if the property has no value + * @return property value, or @def if not found + */ +u64 ofnode_read_u64_default(ofnode node, const char *propname, u64 def); + +/** + * ofnode_read_prop() - Read a property from a node + * + * @node: valid node reference to read property from + * @propname: name of the property to read + * @sizep: if non-NULL, returns the size of the property, or an error code + if not found + * @return property value, or NULL if there is no such property + */ +const void *ofnode_read_prop(ofnode node, const char *propname, int *sizep); + +/** + * ofnode_read_string() - Read a string from a property + * + * @node: valid node reference to read property from + * @propname: name of the property to read + * @return string from property value, or NULL if there is no such property + */ +const char *ofnode_read_string(ofnode node, const char *propname); + +/** + * ofnode_read_u32_array() - Find and read an array of 32 bit integers + * + * @node: valid node reference to read property from + * @propname: name of the property to read + * @out_values: pointer to return value, modified only if return value is 0 + * @sz: number of array elements to read + * @return 0 if OK, -ve on error + * + * Search for a property in a device node and read 32-bit value(s) from + * it. Returns 0 on success, -EINVAL if the property does not exist, + * -ENODATA if property does not have a value, and -EOVERFLOW if the + * property data isn't large enough. + * + * The out_values is modified only if a valid u32 value can be decoded. + */ +int ofnode_read_u32_array(ofnode node, const char *propname, + u32 *out_values, size_t sz); + +/** + * ofnode_read_bool() - read a boolean value from a property + * + * @node: valid node reference to read property from + * @propname: name of property to read + * @return true if property is present (meaning true), false if not present + */ +bool ofnode_read_bool(ofnode node, const char *propname); + +/** + * ofnode_find_subnode() - find a named subnode of a parent node + * + * @node: valid reference to parent node + * @subnode_name: name of subnode to find + * @return reference to subnode (which can be invalid if there is no such + * subnode) + */ +ofnode ofnode_find_subnode(ofnode node, const char *subnode_name); + +#if CONFIG_IS_ENABLED(DM_INLINE_OFNODE) +#include + +static inline bool ofnode_is_enabled(ofnode node) +{ + if (ofnode_is_np(node)) { + return of_device_is_available(ofnode_to_np(node)); + } else { + return fdtdec_get_is_enabled(gd->fdt_blob, + ofnode_to_offset(node)); + } +} + +static inline ofnode ofnode_first_subnode(ofnode node) +{ + assert(ofnode_valid(node)); + if (ofnode_is_np(node)) + return np_to_ofnode(node.np->child); + + return offset_to_ofnode( + fdt_first_subnode(gd->fdt_blob, ofnode_to_offset(node))); +} + +static inline ofnode ofnode_next_subnode(ofnode node) +{ + assert(ofnode_valid(node)); + if (ofnode_is_np(node)) + return np_to_ofnode(node.np->sibling); + + return offset_to_ofnode( + fdt_next_subnode(gd->fdt_blob, ofnode_to_offset(node))); +} +#else +/** + * ofnode_is_enabled() - Checks whether a node is enabled. + * This looks for a 'status' property. If this exists, then returns true if + * the status is 'okay' and false otherwise. If there is no status property, + * it returns true on the assumption that anything mentioned should be enabled + * by default. + * + * @node: node to examine + * @return false (not enabled) or true (enabled) + */ +bool ofnode_is_enabled(ofnode node); + +/** + * ofnode_first_subnode() - find the first subnode of a parent node + * + * @node: valid reference to a valid parent node + * @return reference to the first subnode (which can be invalid if the parent + * node has no subnodes) + */ +ofnode ofnode_first_subnode(ofnode node); + +/** + * ofnode_next_subnode() - find the next sibling of a subnode + * + * @node: valid reference to previous node (sibling) + * @return reference to the next subnode (which can be invalid if the node + * has no more siblings) + */ +ofnode ofnode_next_subnode(ofnode node); +#endif /* DM_INLINE_OFNODE */ + +/** + * ofnode_get_parent() - get the ofnode's parent (enclosing ofnode) + * + * @node: valid node to look up + * @return ofnode reference of the parent node + */ +ofnode ofnode_get_parent(ofnode node); + +/** + * ofnode_get_name() - get the name of a node + * + * @node: valid node to look up + * @return name of node + */ +const char *ofnode_get_name(ofnode node); + +/** + * ofnode_get_by_phandle() - get ofnode from phandle + * + * @phandle: phandle to look up + * @return ofnode reference to the phandle + */ +ofnode ofnode_get_by_phandle(uint phandle); + +/** + * ofnode_read_size() - read the size of a property + * + * @node: node to check + * @propname: property to check + * @return size of property if present, or -EINVAL if not + */ +int ofnode_read_size(ofnode node, const char *propname); + +/** + * ofnode_get_addr_size_index() - get an address/size from a node + * based on index + * + * This reads the register address/size from a node based on index + * + * @node: node to read from + * @index: Index of address to read (0 for first) + * @size: Pointer to size of the address + * @return address, or FDT_ADDR_T_NONE if not present or invalid + */ +phys_addr_t ofnode_get_addr_size_index(ofnode node, int index, + fdt_size_t *size); + +/** + * ofnode_get_addr_index() - get an address from a node + * + * This reads the register address from a node + * + * @node: node to read from + * @index: Index of address to read (0 for first) + * @return address, or FDT_ADDR_T_NONE if not present or invalid + */ +phys_addr_t ofnode_get_addr_index(ofnode node, int index); + +/** + * ofnode_get_addr() - get an address from a node + * + * This reads the register address from a node + * + * @node: node to read from + * @return address, or FDT_ADDR_T_NONE if not present or invalid + */ +phys_addr_t ofnode_get_addr(ofnode node); + +/** + * ofnode_get_size() - get size from a node + * + * This reads the register size from a node + * + * @node: node to read from + * @return size of the address, or FDT_SIZE_T_NONE if not present or invalid + */ +fdt_size_t ofnode_get_size(ofnode node); + +/** + * ofnode_stringlist_search() - find a string in a string list and return index + * + * Note that it is possible for this function to succeed on property values + * that are not NUL-terminated. That's because the function will stop after + * finding the first occurrence of @string. This can for example happen with + * small-valued cell properties, such as #address-cells, when searching for + * the empty string. + * + * @node: node to check + * @propname: name of the property containing the string list + * @string: string to look up in the string list + * + * @return: + * the index of the string in the list of strings + * -ENODATA if the property is not found + * -EINVAL on some other error + */ +int ofnode_stringlist_search(ofnode node, const char *propname, + const char *string); + +/** + * ofnode_read_string_index() - obtain an indexed string from a string list + * + * Note that this will successfully extract strings from properties with + * non-NUL-terminated values. For example on small-valued cell properties + * this function will return the empty string. + * + * If non-NULL, the length of the string (on success) or a negative error-code + * (on failure) will be stored in the integer pointer to by lenp. + * + * @node: node to check + * @propname: name of the property containing the string list + * @index: index of the string to return + * @lenp: return location for the string length or an error code on failure + * + * @return: + * length of string, if found or -ve error value if not found + */ +int ofnode_read_string_index(ofnode node, const char *propname, int index, + const char **outp); + +/** + * ofnode_read_string_count() - find the number of strings in a string list + * + * @node: node to check + * @propname: name of the property containing the string list + * @return: + * number of strings in the list, or -ve error value if not found + */ +int ofnode_read_string_count(ofnode node, const char *property); + +/** + * ofnode_parse_phandle_with_args() - Find a node pointed by phandle in a list + * + * This function is useful to parse lists of phandles and their arguments. + * Returns 0 on success and fills out_args, on error returns appropriate + * errno value. + * + * Caller is responsible to call of_node_put() on the returned out_args->np + * pointer. + * + * Example: + * + * phandle1: node1 { + * #list-cells = <2>; + * } + * + * phandle2: node2 { + * #list-cells = <1>; + * } + * + * node3 { + * list = <&phandle1 1 2 &phandle2 3>; + * } + * + * To get a device_node of the `node2' node you may call this: + * ofnode_parse_phandle_with_args(node3, "list", "#list-cells", 0, 1, &args); + * + * @node: device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cells_count: Cell count to use if @cells_name is NULL + * @index: index of a phandle to parse out + * @out_args: optional pointer to output arguments structure (will be filled) + * @return 0 on success (with @out_args filled out if not NULL), -ENOENT if + * @list_name does not exist, -EINVAL if a phandle was not found, + * @cells_name could not be found, the arguments were truncated or there + * were too many arguments. + */ +int ofnode_parse_phandle_with_args(ofnode node, const char *list_name, + const char *cells_name, int cell_count, + int index, + struct ofnode_phandle_args *out_args); + +/** + * ofnode_count_phandle_with_args() - Count number of phandle in a list + * + * This function is useful to count phandles into a list. + * Returns number of phandle on success, on error returns appropriate + * errno value. + * + * @node: device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cells_count: Cell count to use if @cells_name is NULL + * @return number of phandle on success, -ENOENT if @list_name does not + * exist, -EINVAL if a phandle was not found, @cells_name could not + * be found. + */ +int ofnode_count_phandle_with_args(ofnode node, const char *list_name, + const char *cells_name, int cell_count); + +/** + * ofnode_path() - find a node by full path + * + * @path: Full path to node, e.g. "/bus/spi@1" + * @return reference to the node found. Use ofnode_valid() to check if it exists + */ +ofnode ofnode_path(const char *path); + +/** + * ofnode_read_chosen_prop() - get the value of a chosen property + * + * This looks for a property within the /chosen node and returns its value + * + * @propname: Property name to look for + * @sizep: Returns size of property, or FDT_ERR_... error code if function + * returns NULL + * @return property value if found, else NULL + */ +const void *ofnode_read_chosen_prop(const char *propname, int *sizep); + +/** + * ofnode_read_chosen_string() - get the string value of a chosen property + * + * This looks for a property within the /chosen node and returns its value, + * checking that it is a valid nul-terminated string + * + * @propname: Property name to look for + * @return string value if found, else NULL + */ +const char *ofnode_read_chosen_string(const char *propname); + +/** + * ofnode_get_chosen_node() - get a referenced node from the chosen node + * + * This looks up a named property in the chosen node and uses that as a path to + * look up a code. + * + * @return the referenced node if present, else ofnode_null() + */ +ofnode ofnode_get_chosen_node(const char *propname); + +/** + * ofnode_read_aliases_prop() - get the value of a aliases property + * + * This looks for a property within the /aliases node and returns its value + * + * @propname: Property name to look for + * @sizep: Returns size of property, or FDT_ERR_... error code if function + * returns NULL + * @return property value if found, else NULL + */ +const void *ofnode_read_aliases_prop(const char *propname, int *sizep); + +/** + * ofnode_get_aliases_node() - get a referenced node from the aliases node + * + * This looks up a named property in the aliases node and uses that as a path to + * look up a code. + * + * @return the referenced node if present, else ofnode_null() + */ +ofnode ofnode_get_aliases_node(const char *propname); + +struct display_timing; +/** + * ofnode_decode_display_timing() - decode display timings + * + * Decode display timings from the supplied 'display-timings' node. + * See doc/device-tree-bindings/video/display-timing.txt for binding + * information. + * + * @node 'display-timing' node containing the timing subnodes + * @index Index number to read (0=first timing subnode) + * @config Place to put timings + * @return 0 if OK, -FDT_ERR_NOTFOUND if not found + */ +int ofnode_decode_display_timing(ofnode node, int index, + struct display_timing *config); + +/** + * ofnode_get_property() - get a pointer to the value of a node property + * + * @node: node to read + * @propname: property to read + * @lenp: place to put length on success + * @return pointer to property, or NULL if not found + */ +const void *ofnode_get_property(ofnode node, const char *propname, int *lenp); + +/** + * ofnode_get_first_property()- get the reference of the first property + * + * Get reference to the first property of the node, it is used to iterate + * and read all the property with ofnode_get_property_by_prop(). + * + * @node: node to read + * @prop: place to put argument reference + * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found + */ +int ofnode_get_first_property(ofnode node, struct ofprop *prop); + +/** + * ofnode_get_next_property() - get the reference of the next property + * + * Get reference to the next property of the node, it is used to iterate + * and read all the property with ofnode_get_property_by_prop(). + * + * @prop: reference of current argument and place to put reference of next one + * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found + */ +int ofnode_get_next_property(struct ofprop *prop); + +/** + * ofnode_get_property_by_prop() - get a pointer to the value of a property + * + * Get value for the property identified by the provided reference. + * + * @prop: reference on property + * @propname: If non-NULL, place to property name on success, + * @lenp: If non-NULL, place to put length on success + * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found + */ +const void *ofnode_get_property_by_prop(const struct ofprop *prop, + const char **propname, int *lenp); + +/** + * ofnode_is_available() - check if a node is marked available + * + * @node: node to check + * @return true if node's 'status' property is "okay" (or is missing) + */ +bool ofnode_is_available(ofnode node); + +/** + * ofnode_get_addr_size() - get address and size from a property + * + * This does no address translation. It simply reads an property that contains + * an address and a size value, one after the other. + * + * @node: node to read from + * @propname: property to read + * @sizep: place to put size value (on success) + * @return address value, or FDT_ADDR_T_NONE on error + */ +phys_addr_t ofnode_get_addr_size(ofnode node, const char *propname, + phys_size_t *sizep); + +/** + * ofnode_read_u8_array_ptr() - find an 8-bit array + * + * Look up a property in a node and return a pointer to its contents as a + * byte array of given length. The property must have at least enough data + * for the array (count bytes). It may have more, but this will be ignored. + * The data is not copied. + * + * @node node to examine + * @propname name of property to find + * @sz number of array elements + * @return pointer to byte array if found, or NULL if the property is not + * found or there is not enough data + */ +const uint8_t *ofnode_read_u8_array_ptr(ofnode node, const char *propname, + size_t sz); + +/** + * ofnode_read_pci_addr() - look up a PCI address + * + * Look at an address property in a node and return the PCI address which + * corresponds to the given type in the form of fdt_pci_addr. + * The property must hold one fdt_pci_addr with a lengh. + * + * @node node to examine + * @type pci address type (FDT_PCI_SPACE_xxx) + * @propname name of property to find + * @addr returns pci address in the form of fdt_pci_addr + * @return 0 if ok, -ENOENT if the property did not exist, -EINVAL if the + * format of the property was invalid, -ENXIO if the requested + * address type was not found + */ +int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type, + const char *propname, struct fdt_pci_addr *addr); + +/** + * ofnode_read_pci_vendev() - look up PCI vendor and device id + * + * Look at the compatible property of a device node that represents a PCI + * device and extract pci vendor id and device id from it. + * + * @param node node to examine + * @param vendor vendor id of the pci device + * @param device device id of the pci device + * @return 0 if ok, negative on error + */ +int ofnode_read_pci_vendev(ofnode node, u16 *vendor, u16 *device); + +/** + * ofnode_read_addr_cells() - Get the number of address cells for a node + * + * This walks back up the tree to find the closest #address-cells property + * which controls the given node. + * + * @node: Node to check + * @return number of address cells this node uses + */ +int ofnode_read_addr_cells(ofnode node); + +/** + * ofnode_read_size_cells() - Get the number of size cells for a node + * + * This walks back up the tree to find the closest #size-cells property + * which controls the given node. + * + * @node: Node to check + * @return number of size cells this node uses + */ +int ofnode_read_size_cells(ofnode node); + +/** + * ofnode_read_simple_addr_cells() - Get the address cells property in a node + * + * This function matches fdt_address_cells(). + * + * @np: Node pointer to check + * @return value of #address-cells property in this node, or 2 if none + */ +int ofnode_read_simple_addr_cells(ofnode node); + +/** + * ofnode_read_simple_size_cells() - Get the size cells property in a node + * + * This function matches fdt_size_cells(). + * + * @np: Node pointer to check + * @return value of #size-cells property in this node, or 2 if none + */ +int ofnode_read_simple_size_cells(ofnode node); + +/** + * ofnode_pre_reloc() - check if a node should be bound before relocation + * + * Device tree nodes can be marked as needing-to-be-bound in the loader stages + * via special device tree properties. + * + * Before relocation this function can be used to check if nodes are required + * in either SPL or TPL stages. + * + * After relocation and jumping into the real U-Boot binary it is possible to + * determine if a node was bound in one of SPL/TPL stages. + * + * There are 4 settings currently in use + * - u-boot,dm-pre-proper: U-Boot proper pre-relocation only + * - u-boot,dm-pre-reloc: legacy and indicates any of TPL or SPL + * Existing platforms only use it to indicate nodes needed in + * SPL. Should probably be replaced by u-boot,dm-spl for + * new platforms. + * - u-boot,dm-spl: SPL and U-Boot pre-relocation + * - u-boot,dm-tpl: TPL and U-Boot pre-relocation + * + * @node: node to check + * @return true if node is needed in SPL/TL, false otherwise + */ +bool ofnode_pre_reloc(ofnode node); + +/** + * ofnode_read_resource() - Read a resource from a node + * + * Read resource information from a node at the given index + * + * @node: Node to read from + * @index: Index of resource to read (0 = first) + * @res: Returns resource that was read, on success + * @return 0 if OK, -ve on error + */ +int ofnode_read_resource(ofnode node, uint index, struct resource *res); + +/** + * ofnode_read_resource_byname() - Read a resource from a node by name + * + * Read resource information from a node matching the given name. This uses a + * 'reg-names' string list property with the names matching the associated + * 'reg' property list. + * + * @node: Node to read from + * @name: Name of resource to read + * @res: Returns resource that was read, on success + * @return 0 if OK, -ve on error + */ +int ofnode_read_resource_byname(ofnode node, const char *name, + struct resource *res); + +/** + * ofnode_by_compatible() - Find the next compatible node + * + * Find the next node after @from that is compatible with @compat + * + * @from: ofnode to start from (use ofnode_null() to start at the beginning) + * @compat: Compatible string to match + * @return ofnode found, or ofnode_null() if none + */ +ofnode ofnode_by_compatible(ofnode from, const char *compat); + +/** + * ofnode_by_prop_value() - Find the next node with given property value + * + * Find the next node after @from that has a @propname with a value + * @propval and a length @proplen. + * + * @from: ofnode to start from (use ofnode_null() to start at the + * beginning) @propname: property name to check @propval: property value to + * search for @proplen: length of the value in propval @return ofnode + * found, or ofnode_null() if none + */ +ofnode ofnode_by_prop_value(ofnode from, const char *propname, + const void *propval, int proplen); + +/** + * ofnode_for_each_subnode() - iterate over all subnodes of a parent + * + * @node: child node (ofnode, lvalue) + * @parent: parent node (ofnode) + * + * This is a wrapper around a for loop and is used like so: + * + * ofnode node; + * + * ofnode_for_each_subnode(node, parent) { + * Use node + * ... + * } + * + * Note that this is implemented as a macro and @node is used as + * iterator in the loop. The parent variable can be a constant or even a + * literal. + */ +#define ofnode_for_each_subnode(node, parent) \ + for (node = ofnode_first_subnode(parent); \ + ofnode_valid(node); \ + node = ofnode_next_subnode(node)) + +/** + * ofnode_get_child_count() - get the child count of a ofnode + * + * @node: valid node to get its child count + * @return the number of subnodes + */ +int ofnode_get_child_count(ofnode parent); + +/** + * ofnode_translate_address() - Translate a device-tree address + * + * Translate an address from the device-tree into a CPU physical address. This + * function walks up the tree and applies the various bus mappings along the + * way. + * + * @ofnode: Device tree node giving the context in which to translate the + * address + * @in_addr: pointer to the address to translate + * @return the translated address; OF_BAD_ADDR on error + */ +u64 ofnode_translate_address(ofnode node, const fdt32_t *in_addr); + +/** + * ofnode_translate_dma_address() - Translate a device-tree DMA address + * + * Translate a DMA address from the device-tree into a CPU physical address. + * This function walks up the tree and applies the various bus mappings along + * the way. + * + * @ofnode: Device tree node giving the context in which to translate the + * DMA address + * @in_addr: pointer to the DMA address to translate + * @return the translated DMA address; OF_BAD_ADDR on error + */ +u64 ofnode_translate_dma_address(ofnode node, const fdt32_t *in_addr); + +/** + * ofnode_get_dma_range() - get dma-ranges for a specific DT node + * + * Get DMA ranges for a specifc node, this is useful to perform bus->cpu and + * cpu->bus address translations + * + * @param blob Pointer to device tree blob + * @param node_offset Node DT offset + * @param cpu Pointer to variable storing the range's cpu address + * @param bus Pointer to variable storing the range's bus address + * @param size Pointer to variable storing the range's size + * @return translated DMA address or OF_BAD_ADDR on error + */ +int ofnode_get_dma_range(ofnode node, phys_addr_t *cpu, dma_addr_t *bus, + u64 *size); + +/** + * ofnode_device_is_compatible() - check if the node is compatible with compat + * + * This allows to check whether the node is comaptible with the compat. + * + * @node: Device tree node for which compatible needs to be verified. + * @compat: Compatible string which needs to verified in the given node. + * @return true if OK, false if the compatible is not found + */ +int ofnode_device_is_compatible(ofnode node, const char *compat); + +/** + * ofnode_write_prop() - Set a property of a ofnode + * + * Note that the value passed to the function is *not* allocated by the + * function itself, but must be allocated by the caller if necessary. + * + * @node: The node for whose property should be set + * @propname: The name of the property to set + * @len: The length of the new value of the property + * @value: The new value of the property (must be valid prior to calling + * the function) + * @return 0 if successful, -ve on error + */ +int ofnode_write_prop(ofnode node, const char *propname, int len, + const void *value); + +/** + * ofnode_write_string() - Set a string property of a ofnode + * + * Note that the value passed to the function is *not* allocated by the + * function itself, but must be allocated by the caller if necessary. + * + * @node: The node for whose string property should be set + * @propname: The name of the string property to set + * @value: The new value of the string property (must be valid prior to + * calling the function) + * @return 0 if successful, -ve on error + */ +int ofnode_write_string(ofnode node, const char *propname, const char *value); + +/** + * ofnode_set_enabled() - Enable or disable a device tree node given by its + * ofnode + * + * This function effectively sets the node's "status" property to either "okay" + * or "disable", hence making it available for driver model initialization or + * not. + * + * @node: The node to enable + * @value: Flag that tells the function to either disable or enable the + * node + * @return 0 if successful, -ve on error + */ +int ofnode_set_enabled(ofnode node, bool value); + +#endif diff --git a/roms/u-boot/include/dm/pci.h b/roms/u-boot/include/dm/pci.h new file mode 100644 index 000000000..bddacbf59 --- /dev/null +++ b/roms/u-boot/include/dm/pci.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Google, Inc + */ + +#ifndef __DM_PCI_H +#define __DM_PCI_H + +struct udevice; + +/** + * pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device + * + * Get devfn from fdt_pci_addr of the specified device + * + * This returns an int to avoid a dependency on pci.h + * + * @dev: PCI device + * @return devfn in bits 15...8 if found (pci_dev_t format), or -ENODEV if not + * found + */ +int pci_get_devfn(struct udevice *dev); + +/** + * pci_ofplat_get_devfn() - Get the PCI dev/fn from of-platdata + * + * This function is used to obtain a PCI device/function from of-platdata + * register data. In this case the first cell of the 'reg' property contains + * the required information. + * + * This returns an int to avoid a dependency on pci.h + * + * @reg: reg value from dt-plat.c array (first member). This is not a + * pointer type, since the caller may use fdt32_t or fdt64_t depending on + * the address sizes. + * @return device/function for that device (pci_dev_t format) + */ +static inline int pci_ofplat_get_devfn(u32 reg) +{ + return reg & 0xff00; +} + +#endif diff --git a/roms/u-boot/include/dm/pinctrl.h b/roms/u-boot/include/dm/pinctrl.h new file mode 100644 index 000000000..1bdc8d3cb --- /dev/null +++ b/roms/u-boot/include/dm/pinctrl.h @@ -0,0 +1,626 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Masahiro Yamada + */ + +#ifndef __PINCTRL_H +#define __PINCTRL_H + +#define PINNAME_SIZE 10 +#define PINMUX_SIZE 40 + +/** + * struct pinconf_param - pin config parameters + * @property: Property name in DT nodes + * @param: ID for this config parameter + * @default_value: default value for this config parameter used in case + * no value is specified in DT nodes + */ +struct pinconf_param { + const char * const property; + unsigned int param; + u32 default_value; +}; + +/** + * struct pinctrl_ops - pin control operations, to be implemented by + * pin controller drivers. + * + * set_state() is the only mandatory operation. You can implement your pinctrl + * driver with its own @set_state. In this case, the other callbacks are not + * required. Otherwise, generic pinctrl framework is also available; use + * pinctrl_generic_set_state for @set_state, and implement other operations + * depending on your necessity. + */ +struct pinctrl_ops { + /** + * @get_pins_count: Get the number of selectable pins + * + * @dev: Pinctrl device to use + * + * This function is necessary to parse the "pins" property in DTS. + * + * @Return: + * number of selectable named pins available in this driver + */ + int (*get_pins_count)(struct udevice *dev); + + /** + * @get_pin_name: Get the name of a pin + * + * @dev: Pinctrl device of the pin + * + * @selector: The pin selector + * + * This function is called by the core to figure out which pin it will + * do operations to. This function is necessary to parse the "pins" + * property in DTS. + * + * @Return: const pointer to the name of the pin + */ + const char *(*get_pin_name)(struct udevice *dev, unsigned selector); + + /** + * @get_groups_count: Get the number of selectable groups + * + * @dev: Pinctrl device to use + * + * This function is necessary to parse the "groups" property in DTS. + * + * @Return: + * number of selectable named groups available in the driver + */ + int (*get_groups_count)(struct udevice *dev); + + /** + * @get_group_name: Get the name of a group + * + * @dev: Pinctrl device of the group + * + * @selector: The group selector + * + * This function is called by the core to figure out which group it + * will do operations to. This function is necessary to parse the + * "groups" property in DTS. + * + * @Return: Pointer to the name of the group + */ + const char *(*get_group_name)(struct udevice *dev, unsigned selector); + + /** + * @get_functions_count: Get the number of selectable functions + * + * @dev: Pinctrl device to use + * + * This function is necessary for pin-muxing. + * + * @Return: + * number of selectable named functions available in this driver + */ + int (*get_functions_count)(struct udevice *dev); + + /** + * @get_function_name: Get the name of a function + * + * @dev: Pinmux device of the function + * + * @selector: The function selector + * + * This function is called by the core to figure out which mux setting + * it will map a certain device to. This function is necessary for + * pin-muxing. + * + * @Return: + * Pointer to the function name of the muxing selector + */ + const char *(*get_function_name)(struct udevice *dev, + unsigned selector); + + /** + * @pinmux_set: Mux a pin to a function + * + * @dev: Pinctrl device to use + * + * @pin_selector: The pin selector + * + * @func_selector: The func selector + * + * On simple controllers one of @pin_selector or @func_selector may be + * ignored. This function is necessary for pin-muxing against a single + * pin. + * + * @Return: 0 if OK, or negative error code on failure + */ + int (*pinmux_set)(struct udevice *dev, unsigned pin_selector, + unsigned func_selector); + + /** + * @pinmux_group_set: Mux a group of pins to a function + * + * @dev: Pinctrl device to use + * + * @group_selector: The group selector + * + * @func_selector: The func selector + * + * On simple controllers one of @group_selector or @func_selector may be + * ignored. This function is necessary for pin-muxing against a group of + * pins. + * + * @Return: 0 if OK, or negative error code on failure + */ + int (*pinmux_group_set)(struct udevice *dev, unsigned group_selector, + unsigned func_selector); + + /** + * @pinmux_property_set: Enable a pinmux group + * + * @dev: Pinctrl device to use + * + * @pinmux_group: A u32 representing the pin identifier and mux + * settings. The exact format of a pinmux group is left + * up to the driver. + * + * Mux a single pin to a single function based on a driver-specific + * pinmux group. This function is necessary for parsing the "pinmux" + * property in DTS, and for pin-muxing against a pinmux group. + * + * @Return: + * Pin selector for the muxed pin if OK, or negative error code on + * failure + */ + int (*pinmux_property_set)(struct udevice *dev, u32 pinmux_group); + + /** + * @pinconf_num_params: + * Number of driver-specific parameters to be parsed from device + * trees. This member is necessary for pin configuration. + */ + unsigned int pinconf_num_params; + + /** + * @pinconf_params: + * List of driver-specific parameters to be parsed from the device + * tree. This member is necessary for pin configuration. + */ + const struct pinconf_param *pinconf_params; + + /** + * @pinconf_set: Configure an individual pin with a parameter + * + * @dev: Pinctrl device to use + * + * @pin_selector: The pin selector + * + * @param: An &enum pin_config_param from @pinconf_params + * + * @argument: The argument to this param from the device tree, or + * @pinconf_params.default_value + * + * This function is necessary for pin configuration against a single + * pin. + * + * @Return: 0 if OK, or negative error code on failure + */ + int (*pinconf_set)(struct udevice *dev, unsigned pin_selector, + unsigned param, unsigned argument); + + /** + * @pinconf_group_set: Configure all pins in a group with a parameter + * + * @dev: Pinctrl device to use + * + * @pin_selector: The group selector + * + * @param: A &enum pin_config_param from + * @pinconf_params + * + * @argument: The argument to this param from the device tree, or + * @pinconf_params.default_value + * + * This function is necessary for pin configuration against a group of + * pins. + * + * @Return: 0 if OK, or negative error code on failure + */ + int (*pinconf_group_set)(struct udevice *dev, unsigned group_selector, + unsigned param, unsigned argument); + + /** + * @set_state: Configure a pinctrl device + * + * @dev: Pinctrl device to use + * + * @config: Pseudo device pointing a config node + * + * This function is required to be implemented by all pinctrl drivers. + * Drivers may set this member to pinctrl_generic_set_state(), which + * will call other functions in &struct pinctrl_ops to parse + * @config. + * + * @Return: 0 if OK, or negative error code on failure + */ + int (*set_state)(struct udevice *dev, struct udevice *config); + + /** + * @set_state_simple: Configure a pinctrl device + * + * @dev: Pinctrl device to use + * + * @config: Pseudo-device pointing a config node + * + * This function is usually a simpler version of set_state(). Only the + * first pinctrl device on the system is supported by this function. + * + * @Return: 0 if OK, or negative error code on failure + */ + int (*set_state_simple)(struct udevice *dev, struct udevice *periph); + + /** + * @request: Request a particular pinctrl function + * + * @dev: Device to adjust (%UCLASS_PINCTRL) + * + * @func: Function number (driver-specific) + * + * This activates the selected function. + * + * @Return: 0 if OK, or negative error code on failure + */ + int (*request)(struct udevice *dev, int func, int flags); + + /** + * @get_periph_id: Get the peripheral ID for a device + * + * @dev: Pinctrl device to use for decoding + * + * @periph: Device to check + * + * This generally looks at the peripheral's device tree node to work + * out the peripheral ID. The return value is normally interpreted as + * &enum periph_id. so long as this is defined by the platform (which it + * should be). + * + * @Return: + * Peripheral ID of @periph, or %-ENOENT on error + */ + int (*get_periph_id)(struct udevice *dev, struct udevice *periph); + + /** + * @get_gpio_mux: Get the mux value for a particular GPIO + * + * @dev: Pinctrl device to use + * + * @banknum: GPIO bank number + * + * @index: GPIO index within the bank + * + * This allows the raw mux value for a GPIO to be obtained. It is + * useful for displaying the function being used by that GPIO, such + * as with the 'gpio' command. This function is internal to the GPIO + * subsystem and should not be used by generic code. Typically it is + * used by a GPIO driver with knowledge of the SoC pinctrl setup. + * + * @Return: + * Mux value (SoC-specific, e.g. 0 for input, 1 for output) + */ + int (*get_gpio_mux)(struct udevice *dev, int banknum, int index); + + /** + * @get_pin_muxing: Show pin muxing + * + * @dev: Pinctrl device to use + * + * @selector: Pin selector + * + * @buf: Buffer to fill with pin muxing description + * + * @size: Size of @buf + * + * This allows to display the muxing of a given pin. It's useful for + * debug purposes to know if a pin is configured as GPIO or as an + * alternate function and which one. Typically it is used by a PINCTRL + * driver with knowledge of the SoC pinctrl setup. + * + * @Return: 0 if OK, or negative error code on failure + */ + int (*get_pin_muxing)(struct udevice *dev, unsigned int selector, + char *buf, int size); + + /** + * @gpio_request_enable: Request and enable GPIO on a certain pin. + * + * @dev: Pinctrl device to use + * + * @selector: Pin selector + * + * Implement this only if you can mux every pin individually as GPIO. + * The affected GPIO range is passed along with an offset(pin number) + * into that specific GPIO range - function selectors and pin groups are + * orthogonal to this, the core will however make sure the pins do not + * collide. + * + * @Return: + * 0 if OK, or negative error code on failure + */ + int (*gpio_request_enable)(struct udevice *dev, unsigned int selector); + + /** + * @gpio_disable_free: Free up GPIO muxing on a certain pin. + * + * @dev: Pinctrl device to use + * + * @selector: Pin selector + * + * This function is the reverse of @gpio_request_enable. + * + * @Return: 0 if OK, or negative error code on failure + */ + int (*gpio_disable_free)(struct udevice *dev, unsigned int selector); +}; + +#define pinctrl_get_ops(dev) ((struct pinctrl_ops *)(dev)->driver->ops) + +/** + * enum pin_config_param - Generic pin configuration parameters + * + * @PIN_CONFIG_BIAS_BUS_HOLD: The pin will be set to weakly latch so that it + * weakly drives the last value on a tristate bus, also known as a "bus + * holder", "bus keeper" or "repeater". This allows another device on the + * bus to change the value by driving the bus high or low and switching to + * tristate. The argument is ignored. + * @PIN_CONFIG_BIAS_DISABLE: Disable any pin bias on the pin, a + * transition from say pull-up to pull-down implies that you disable + * pull-up in the process, this setting disables all biasing. + * @PIN_CONFIG_BIAS_HIGH_IMPEDANCE: The pin will be set to a high impedance + * mode, also know as "third-state" (tristate) or "high-Z" or "floating". + * On output pins this effectively disconnects the pin, which is useful + * if for example some other pin is going to drive the signal connected + * to it for a while. Pins used for input are usually always high + * impedance. + * @PIN_CONFIG_BIAS_PULL_DOWN: The pin will be pulled down (usually with high + * impedance to GROUND). If the argument is != 0 pull-down is enabled, + * if it is 0, pull-down is total, i.e. the pin is connected to GROUND. + * @PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: The pin will be pulled up or down based + * on embedded knowledge of the controller hardware, like current mux + * function. The pull direction and possibly strength too will normally + * be decided completely inside the hardware block and not be readable + * from the kernel side. + * If the argument is != 0 pull up/down is enabled, if it is 0, the + * configuration is ignored. The proper way to disable it is to use + * @PIN_CONFIG_BIAS_DISABLE. + * @PIN_CONFIG_BIAS_PULL_UP: The pin will be pulled up (usually with high + * impedance to VDD). If the argument is != 0 pull-up is enabled, + * if it is 0, pull-up is total, i.e. the pin is connected to VDD. + * @PIN_CONFIG_DRIVE_OPEN_DRAIN: The pin will be driven with open drain (open + * collector) which means it is usually wired with other output ports + * which are then pulled up with an external resistor. Setting this + * config will enable open drain mode, the argument is ignored. + * @PIN_CONFIG_DRIVE_OPEN_SOURCE: The pin will be driven with open source + * (open emitter). Setting this config will enable open source mode, the + * argument is ignored. + * @PIN_CONFIG_DRIVE_PUSH_PULL: The pin will be driven actively high and + * low, this is the most typical case and is typically achieved with two + * active transistors on the output. Setting this config will enable + * push-pull mode, the argument is ignored. + * @PIN_CONFIG_DRIVE_STRENGTH: The pin will sink or source at most the current + * passed as argument. The argument is in mA. + * @PIN_CONFIG_DRIVE_STRENGTH_UA: The pin will sink or source at most the + * current passed as argument. The argument is in uA. + * @PIN_CONFIG_INPUT_DEBOUNCE: This will configure the pin to debounce mode, + * which means it will wait for signals to settle when reading inputs. The + * argument gives the debounce time in usecs. Setting the + * argument to zero turns debouncing off. + * @PIN_CONFIG_INPUT_ENABLE: Enable the pin's input. Note that this does not + * affect the pin's ability to drive output. 1 enables input, 0 disables + * input. + * @PIN_CONFIG_INPUT_SCHMITT: This will configure an input pin to run in + * schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis, + * the threshold value is given on a custom format as argument when + * setting pins to this mode. + * @PIN_CONFIG_INPUT_SCHMITT_ENABLE: Control schmitt-trigger mode on the pin. + * If the argument != 0, schmitt-trigger mode is enabled. If it's 0, + * schmitt-trigger mode is disabled. + * @PIN_CONFIG_LOW_POWER_MODE: This will configure the pin for low power + * operation, if several modes of operation are supported these can be + * passed in the argument on a custom form, else just use argument 1 + * to indicate low power mode, argument 0 turns low power mode off. + * @PIN_CONFIG_OUTPUT_ENABLE: This will enable the pin's output mode + * without driving a value there. For most platforms this reduces to + * enable the output buffers and then let the pin controller current + * configuration (eg. the currently selected mux function) drive values on + * the line. Use argument 1 to enable output mode, argument 0 to disable + * it. + * @PIN_CONFIG_OUTPUT: This will configure the pin as an output and drive a + * value on the line. Use argument 1 to indicate high level, argument 0 to + * indicate low level. (Please see Documentation/driver-api/pinctl.rst, + * section "GPIO mode pitfalls" for a discussion around this parameter.) + * @PIN_CONFIG_POWER_SOURCE: If the pin can select between different power + * supplies, the argument to this parameter (on a custom format) tells + * the driver which alternative power source to use. + * @PIN_CONFIG_SLEEP_HARDWARE_STATE: Indicate this is sleep related state. + * @PIN_CONFIG_SLEW_RATE: If the pin can select slew rate, the argument to + * this parameter (on a custom format) tells the driver which alternative + * slew rate to use. + * @PIN_CONFIG_SKEW_DELAY: If the pin has programmable skew rate (on inputs) + * or latch delay (on outputs) this parameter (in a custom format) + * specifies the clock skew or latch delay. It typically controls how + * many double inverters are put in front of the line. + * @PIN_CONFIG_END: This is the last enumerator for pin configurations, if + * you need to pass in custom configurations to the pin controller, use + * PIN_CONFIG_END+1 as the base offset. + * @PIN_CONFIG_MAX: This is the maximum configuration value that can be + * presented using the packed format. + */ +enum pin_config_param { + PIN_CONFIG_BIAS_BUS_HOLD, + PIN_CONFIG_BIAS_DISABLE, + PIN_CONFIG_BIAS_HIGH_IMPEDANCE, + PIN_CONFIG_BIAS_PULL_DOWN, + PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, + PIN_CONFIG_BIAS_PULL_UP, + PIN_CONFIG_DRIVE_OPEN_DRAIN, + PIN_CONFIG_DRIVE_OPEN_SOURCE, + PIN_CONFIG_DRIVE_PUSH_PULL, + PIN_CONFIG_DRIVE_STRENGTH, + PIN_CONFIG_DRIVE_STRENGTH_UA, + PIN_CONFIG_INPUT_DEBOUNCE, + PIN_CONFIG_INPUT_ENABLE, + PIN_CONFIG_INPUT_SCHMITT, + PIN_CONFIG_INPUT_SCHMITT_ENABLE, + PIN_CONFIG_LOW_POWER_MODE, + PIN_CONFIG_OUTPUT_ENABLE, + PIN_CONFIG_OUTPUT, + PIN_CONFIG_POWER_SOURCE, + PIN_CONFIG_SLEEP_HARDWARE_STATE, + PIN_CONFIG_SLEW_RATE, + PIN_CONFIG_SKEW_DELAY, + PIN_CONFIG_END = 0x7F, + PIN_CONFIG_MAX = 0xFF, +}; + +#if CONFIG_IS_ENABLED(PINCTRL_GENERIC) +/** + * pinctrl_generic_set_state() - Generic set_state operation + * @pctldev: Pinctrl device to use + * @config: Config device (pseudo device), pointing a config node in DTS + * + * Parse the DT node of @config and its children and handle generic properties + * such as "pins", "groups", "functions", and pin configuration parameters. + * + * Return: 0 on success, or negative error code on failure + */ +int pinctrl_generic_set_state(struct udevice *pctldev, struct udevice *config); +#else +static inline int pinctrl_generic_set_state(struct udevice *pctldev, + struct udevice *config) +{ + return -EINVAL; +} +#endif + +#if CONFIG_IS_ENABLED(PINCTRL) +/** + * pinctrl_select_state() - Set a device to a given state + * @dev: Peripheral device + * @statename: State name, like "default" + * + * Return: 0 on success, or negative error code on failure + */ +int pinctrl_select_state(struct udevice *dev, const char *statename); +#else +static inline int pinctrl_select_state(struct udevice *dev, + const char *statename) +{ + return -EINVAL; +} +#endif + +/** + * pinctrl_request() - Request a particular pinctrl function + * @dev: Pinctrl device to use + * @func: Function number (driver-specific) + * @flags: Flags (driver-specific) + * + * Return: 0 if OK, or negative error code on failure + */ +int pinctrl_request(struct udevice *dev, int func, int flags); + +/** + * pinctrl_request_noflags() - Request a particular pinctrl function + * @dev: Pinctrl device to use + * @func: Function number (driver-specific) + * + * This is similar to pinctrl_request() but uses 0 for @flags. + * + * Return: 0 if OK, or negative error code on failure + */ +int pinctrl_request_noflags(struct udevice *dev, int func); + +/** + * pinctrl_get_periph_id() - Get the peripheral ID for a device + * @dev: Pinctrl device to use for decoding + * @periph: Device to check + * + * This generally looks at the peripheral's device tree node to work out the + * peripheral ID. The return value is normally interpreted as enum periph_id. + * so long as this is defined by the platform (which it should be). + * + * Return: Peripheral ID of @periph, or -ENOENT on error + */ +int pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph); + +/** + * pinctrl_get_gpio_mux() - get the mux value for a particular GPIO + * @dev: Pinctrl device to use + * @banknum: GPIO bank number + * @index: GPIO index within the bank + * + * This allows the raw mux value for a GPIO to be obtained. It is + * useful for displaying the function being used by that GPIO, such + * as with the 'gpio' command. This function is internal to the GPIO + * subsystem and should not be used by generic code. Typically it is + * used by a GPIO driver with knowledge of the SoC pinctrl setup. + * + * Return: Mux value (SoC-specific, e.g. 0 for input, 1 for output) +*/ +int pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index); + +/** + * pinctrl_get_pin_muxing() - Returns the muxing description + * @dev: Pinctrl device to use + * @selector: Pin index within pin-controller + * @buf: Pin's muxing description + * @size: Pin's muxing description length + * + * This allows to display the muxing description of the given pin for + * debug purpose + * + * Return: 0 if OK, or negative error code on failure + */ +int pinctrl_get_pin_muxing(struct udevice *dev, int selector, char *buf, + int size); + +/** + * pinctrl_get_pins_count() - Display pin-controller pins number + * @dev: Pinctrl device to use + * + * This allows to know the number of pins owned by a given pin-controller + * + * Return: Number of pins if OK, or negative error code on failure + */ +int pinctrl_get_pins_count(struct udevice *dev); + +/** + * pinctrl_get_pin_name() - Returns the pin's name + * @dev: Pinctrl device to use + * @selector: Pin index within pin-controller + * @buf: Buffer to fill with the name of the pin + * @size: Size of @buf + * + * This allows to display the pin's name for debug purpose + * + * Return: 0 if OK, or negative error code on failure + */ +int pinctrl_get_pin_name(struct udevice *dev, int selector, char *buf, + int size); + +/** + * pinctrl_gpio_request() - Request a single pin to be used as GPIO + * @dev: GPIO peripheral device + * @offset: GPIO pin offset from the GPIO controller + * + * Return: 0 on success, or negative error code on failure + */ +int pinctrl_gpio_request(struct udevice *dev, unsigned offset); + +/** + * pinctrl_gpio_free() - Free a single pin used as GPIO + * @dev: GPIO peripheral device + * @offset: GPIO pin offset from the GPIO controller + * + * Return: 0 on success, or negative error code on failure + */ +int pinctrl_gpio_free(struct udevice *dev, unsigned offset); + +#endif /* __PINCTRL_H */ diff --git a/roms/u-boot/include/dm/platdata.h b/roms/u-boot/include/dm/platdata.h new file mode 100644 index 000000000..4efb1dfe1 --- /dev/null +++ b/roms/u-boot/include/dm/platdata.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + * Marek Vasut + */ + +#ifndef _DM_PLATDATA_H +#define _DM_PLATDATA_H + +#include + +/** + * struct driver_info - Information required to instantiate a device + * + * NOTE: Avoid using this except in extreme circumstances, where device tree + * is not feasible (e.g. serial driver in SPL where <8KB of SRAM is + * available). U-Boot's driver model uses device tree for configuration. + * + * @name: Driver name + * @plat: Driver-specific platform data + * @plat_size: Size of platform data structure + * @parent_idx: Index of the parent driver_info structure + */ +struct driver_info { + const char *name; + const void *plat; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + unsigned short plat_size; + short parent_idx; +#endif +}; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +#define driver_info_parent_id(driver_info) driver_info->parent_idx +#else +#define driver_info_parent_id(driver_info) (-1) +#endif + +/** + * driver_rt - runtime information set up by U-Boot + * + * There is one of these for every driver_info in the linker list, indexed by + * the driver_info idx value. + * + * @dev: Device created from this idx + */ +struct driver_rt { + struct udevice *dev; +}; + +/** + * NOTE: Avoid using these except in extreme circumstances, where device tree + * is not feasible (e.g. serial driver in SPL where <8KB of SRAM is + * available). U-Boot's driver model uses device tree for configuration. + * + * When of-platdata is in use, U_BOOT_DRVINFO() cannot be used outside of the + * dt-plat.c file created by dtoc + */ +#if CONFIG_IS_ENABLED(OF_PLATDATA) && !defined(DT_PLAT_C) +#define U_BOOT_DRVINFO(__name) _Static_assert(false, \ + "Cannot use U_BOOT_DRVINFO with of-platdata. Please use devicetree instead") +#else +#define U_BOOT_DRVINFO(__name) \ + ll_entry_declare(struct driver_info, __name, driver_info) +#endif + +/* Declare a list of devices. The argument is a driver_info[] array */ +#define U_BOOT_DRVINFOS(__name) \ + ll_entry_declare_list(struct driver_info, __name, driver_info) + +#endif diff --git a/roms/u-boot/include/dm/platform_data/fsl_espi.h b/roms/u-boot/include/dm/platform_data/fsl_espi.h new file mode 100644 index 000000000..de2307f7f --- /dev/null +++ b/roms/u-boot/include/dm/platform_data/fsl_espi.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __fsl_espi_h +#define __fsl_espi_h + +struct fsl_espi_plat { + uint flags; + uint speed_hz; + uint num_chipselect; + fdt_addr_t regs_addr; +}; + +#endif /* __fsl_espi_h */ diff --git a/roms/u-boot/include/dm/platform_data/lpc32xx_hsuart.h b/roms/u-boot/include/dm/platform_data/lpc32xx_hsuart.h new file mode 100644 index 000000000..6f41e0e73 --- /dev/null +++ b/roms/u-boot/include/dm/platform_data/lpc32xx_hsuart.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Vladimir Zapolskiy + */ + +#ifndef _LPC32XX_HSUART_PLAT_H +#define _LPC32XX_HSUART_PLAT_H + +/** + * struct lpc32xx_hsuart_plat - NXP LPC32xx HSUART platform data + * + * @base: Base register address + */ +struct lpc32xx_hsuart_plat { + unsigned long base; +}; + +#endif diff --git a/roms/u-boot/include/dm/platform_data/net_ethoc.h b/roms/u-boot/include/dm/platform_data/net_ethoc.h new file mode 100644 index 000000000..855e9999a --- /dev/null +++ b/roms/u-boot/include/dm/platform_data/net_ethoc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Cadence Design Systems Inc. + */ + +#ifndef _ETHOC_H +#define _ETHOC_H + +#include + +#ifdef CONFIG_DM_ETH + +struct ethoc_eth_pdata { + struct eth_pdata eth_pdata; + phys_addr_t packet_base; +}; + +#endif + +#endif /* _ETHOC_H */ diff --git a/roms/u-boot/include/dm/platform_data/pfe_dm_eth.h b/roms/u-boot/include/dm/platform_data/pfe_dm_eth.h new file mode 100644 index 000000000..100a981a3 --- /dev/null +++ b/roms/u-boot/include/dm/platform_data/pfe_dm_eth.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#ifndef __PFE_DM_ETH_H__ +#define __PFE_DM_ETH_H__ +#include + +struct pfe_ddr_address { + void *ddr_pfe_baseaddr; + unsigned long ddr_pfe_phys_baseaddr; +}; + +struct pfe_eth_pdata { + struct eth_pdata pfe_eth_pdata_mac; + struct pfe_ddr_address pfe_ddr_addr; +}; +#endif /* __PFE_DM_ETH_H__ */ diff --git a/roms/u-boot/include/dm/platform_data/pxa_mmc_gen.h b/roms/u-boot/include/dm/platform_data/pxa_mmc_gen.h new file mode 100644 index 000000000..d15c1551f --- /dev/null +++ b/roms/u-boot/include/dm/platform_data/pxa_mmc_gen.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Marcel Ziswiler + */ + +#ifndef __PXA_MMC_GEN_H +#define __PXA_MMC_GEN_H + +#include + +/* + * struct pxa_mmc_plat - information about a PXA MMC controller + * + * @base: MMC controller base register address + */ +struct pxa_mmc_plat { + struct mmc_config cfg; + struct mmc mmc; + struct pxa_mmc_regs *base; +}; + +#endif /* __PXA_MMC_GEN_H */ diff --git a/roms/u-boot/include/dm/platform_data/serial_bcm283x_mu.h b/roms/u-boot/include/dm/platform_data/serial_bcm283x_mu.h new file mode 100644 index 000000000..6c77272e8 --- /dev/null +++ b/roms/u-boot/include/dm/platform_data/serial_bcm283x_mu.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Stephen Warren + * + * Derived from pl01x code: + * Copyright (c) 2014 Google, Inc + */ + +#ifndef __serial_bcm283x_mu_h +#define __serial_bcm283x_mu_h + +/* + *Information about a serial port + * + * @base: Register base address + */ +struct bcm283x_mu_serial_plat { + unsigned long base; + unsigned int clock; + bool skip_init; +}; + +#endif diff --git a/roms/u-boot/include/dm/platform_data/serial_coldfire.h b/roms/u-boot/include/dm/platform_data/serial_coldfire.h new file mode 100644 index 000000000..5e265e908 --- /dev/null +++ b/roms/u-boot/include/dm/platform_data/serial_coldfire.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Angelo Dureghello + */ + +#ifndef __serial_coldfire_h +#define __serial_coldfire_h + +/* + * struct coldfire_serial_plat - information about a coldfire port + * + * @base: Uart port base register address + * @port: Uart port index, for cpu with pinmux for uart / gpio + * baudrtatre: Uart port baudrate + */ +struct coldfire_serial_plat { + unsigned long base; + int port; + int baudrate; +}; + +#endif /* __serial_coldfire_h */ diff --git a/roms/u-boot/include/dm/platform_data/serial_mxc.h b/roms/u-boot/include/dm/platform_data/serial_mxc.h new file mode 100644 index 000000000..cc59eeb1d --- /dev/null +++ b/roms/u-boot/include/dm/platform_data/serial_mxc.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2014 Google, Inc + */ + +#ifndef __serial_mxc_h +#define __serial_mxc_h + +/* Information about a serial port */ +struct mxc_serial_plat { + struct mxc_uart *reg; /* address of registers in physical memory */ + bool use_dte; +}; + +#endif diff --git a/roms/u-boot/include/dm/platform_data/serial_pl01x.h b/roms/u-boot/include/dm/platform_data/serial_pl01x.h new file mode 100644 index 000000000..e3d4e308a --- /dev/null +++ b/roms/u-boot/include/dm/platform_data/serial_pl01x.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2014 Google, Inc + */ + +#ifndef __serial_pl01x_h +#define __serial_pl01x_h + +enum pl01x_type { + TYPE_PL010, + TYPE_PL011, +}; + +/* + *Information about a serial port + * + * @base: Register base address + * @type: Port type + * @clock: Input clock rate, used for calculating the baud rate divisor + * @skip_init: Don't attempt to change port configuration (also means @clock + * is ignored) + */ +struct pl01x_serial_plat { + unsigned long base; + enum pl01x_type type; + unsigned int clock; + bool skip_init; +}; + +#endif diff --git a/roms/u-boot/include/dm/platform_data/serial_pxa.h b/roms/u-boot/include/dm/platform_data/serial_pxa.h new file mode 100644 index 000000000..0d7dc4c46 --- /dev/null +++ b/roms/u-boot/include/dm/platform_data/serial_pxa.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2016 Marcel Ziswiler + */ + +#ifndef __SERIAL_PXA_H +#define __SERIAL_PXA_H + +/* + * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can + * easily handle enabling of clock. + */ +#ifdef CONFIG_CPU_MONAHANS +#define UART_CLK_BASE CKENA_21_BTUART +#define UART_CLK_REG CKENA +#define BTUART_INDEX 0 +#define FFUART_INDEX 1 +#define STUART_INDEX 2 +#elif CONFIG_CPU_PXA25X +#define UART_CLK_BASE BIT(4) /* HWUART */ +#define UART_CLK_REG CKEN +#define HWUART_INDEX 0 +#define STUART_INDEX 1 +#define FFUART_INDEX 2 +#define BTUART_INDEX 3 +#else /* PXA27x */ +#define UART_CLK_BASE CKEN5_STUART +#define UART_CLK_REG CKEN +#define STUART_INDEX 0 +#define FFUART_INDEX 1 +#define BTUART_INDEX 2 +#endif + +/* + * Only PXA250 has HWUART, to avoid poluting the code with more macros, + * artificially introduce this. + */ +#ifndef CONFIG_CPU_PXA25X +#define HWUART_INDEX 0xff +#endif + +/* + * struct pxa_serial_plat - information about a PXA port + * + * @base: Uart port base register address + * @port: Uart port index, for cpu with pinmux for uart / gpio + * baudrtatre: Uart port baudrate + */ +struct pxa_serial_plat { + struct pxa_uart_regs *base; + int port; + int baudrate; +}; + +#endif /* __SERIAL_PXA_H */ diff --git a/roms/u-boot/include/dm/platform_data/serial_sh.h b/roms/u-boot/include/dm/platform_data/serial_sh.h new file mode 100644 index 000000000..69cd012fc --- /dev/null +++ b/roms/u-boot/include/dm/platform_data/serial_sh.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2014 Nobuhiro Iwamatsu + * Copyright (c) 2014 Renesas Electronics Corporation + */ + +#ifndef __serial_sh_h +#define __serial_sh_h + +enum sh_clk_mode { + INT_CLK, + EXT_CLK, +}; + +enum sh_serial_type { + PORT_SCI, + PORT_SCIF, + PORT_SCIFA, + PORT_SCIFB, +}; + +/* + * Information about SCIF port + * + * @base: Register base address + * @clk: Input clock rate, used for calculating the baud rate divisor + * @clk_mode: Clock mode, set internal (INT) or external (EXT) + * @type: Type of SCIF + */ +struct sh_serial_plat { + unsigned long base; + unsigned int clk; + enum sh_clk_mode clk_mode; + enum sh_serial_type type; +}; +#endif /* __serial_sh_h */ diff --git a/roms/u-boot/include/dm/platform_data/spi_coldfire.h b/roms/u-boot/include/dm/platform_data/spi_coldfire.h new file mode 100644 index 000000000..da514bad0 --- /dev/null +++ b/roms/u-boot/include/dm/platform_data/spi_coldfire.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2018 Angelo Dureghello + */ + +#ifndef __spi_coldfire_h +#define __spi_coldfire_h + +#define MAX_CTAR_REGS 8 +#define MAX_CTAR_FIELDS 8 + +/* + * struct coldfire_spi_plat - information about a coldfire spi module + * + * @regs_addr: base address for module registers + * @speed_hz: default SCK frequency + * @mode: default SPI mode + * @num_cs: number of DSPI chipselect signals + */ +struct coldfire_spi_plat { + fdt_addr_t regs_addr; + uint speed_hz; + uint mode; + uint num_cs; + uint ctar[MAX_CTAR_REGS][MAX_CTAR_FIELDS]; +}; + +#endif /* __spi_coldfire_h */ + diff --git a/roms/u-boot/include/dm/platform_data/spi_davinci.h b/roms/u-boot/include/dm/platform_data/spi_davinci.h new file mode 100644 index 000000000..42a467e40 --- /dev/null +++ b/roms/u-boot/include/dm/platform_data/spi_davinci.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2018 Jagan Teki + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __spi_davinci_h +#define __spi_davinci_h + +struct davinci_spi_plat { + struct davinci_spi_regs *regs; + u8 num_cs; /* total no. of CS available */ +}; + +#endif /* __spi_davinci_h */ diff --git a/roms/u-boot/include/dm/platform_data/spi_pl022.h b/roms/u-boot/include/dm/platform_data/spi_pl022.h new file mode 100644 index 000000000..7f74b3cbc --- /dev/null +++ b/roms/u-boot/include/dm/platform_data/spi_pl022.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 + * Quentin Schulz, Bootlin, quentin.schulz@bootlin.com + * + * Structure for use with U_BOOT_DRVINFO for pl022 SPI devices or to use + * in of_to_plat. + */ + +#ifndef __spi_pl022_h +#define __spi_pl022_h + +#include + +struct pl022_spi_pdata { + fdt_addr_t addr; + fdt_size_t size; + unsigned int freq; +}; + +#endif /* __spi_pl022_h */ diff --git a/roms/u-boot/include/dm/read.h b/roms/u-boot/include/dm/read.h new file mode 100644 index 000000000..5bf340561 --- /dev/null +++ b/roms/u-boot/include/dm/read.h @@ -0,0 +1,1078 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Function to read values from the device tree node attached to a udevice. + * + * Copyright (c) 2017 Google, Inc + * Written by Simon Glass + */ + +#ifndef _DM_READ_H +#define _DM_READ_H + +#include + +#include +#include +#include +#include + +struct resource; + +#if CONFIG_IS_ENABLED(OF_LIVE) +static inline const struct device_node *dev_np(const struct udevice *dev) +{ + return ofnode_to_np(dev_ofnode(dev)); +} +#else +static inline const struct device_node *dev_np(const struct udevice *dev) +{ + return NULL; +} +#endif + +#if !defined(CONFIG_DM_DEV_READ_INLINE) || CONFIG_IS_ENABLED(OF_PLATDATA) +/** + * dev_read_u32() - read a 32-bit integer from a device's DT property + * + * @dev: device to read DT property from + * @propname: name of the property to read from + * @outp: place to put value (if found) + * @return 0 if OK, -ve on error + */ +int dev_read_u32(const struct udevice *dev, const char *propname, u32 *outp); + +/** + * dev_read_u32_default() - read a 32-bit integer from a device's DT property + * + * @dev: device to read DT property from + * @propname: name of the property to read from + * @def: default value to return if the property has no value + * @return property value, or @def if not found + */ +int dev_read_u32_default(const struct udevice *dev, const char *propname, + int def); + +/** + * dev_read_u32_index() - read an indexed 32-bit integer from a device's DT + * property + * + * @dev: device to read DT property from + * @propname: name of the property to read from + * @index: index of the integer to return + * @outp: place to put value (if found) + * @return 0 if OK, -ve on error + */ +int dev_read_u32_index(struct udevice *dev, const char *propname, int index, + u32 *outp); + +/** + * dev_read_u32_index_default() - read an indexed 32-bit integer from a device's + * DT property + * + * @dev: device to read DT property from + * @propname: name of the property to read from + * @index: index of the integer to return + * @def: default value to return if the property has no value + * @return property value, or @def if not found + */ +u32 dev_read_u32_index_default(struct udevice *dev, const char *propname, + int index, u32 def); + +/** + * dev_read_s32() - read a signed 32-bit integer from a device's DT property + * + * @dev: device to read DT property from + * @propname: name of the property to read from + * @outp: place to put value (if found) + * @return 0 if OK, -ve on error + */ +int dev_read_s32(const struct udevice *dev, const char *propname, s32 *outp); + +/** + * dev_read_s32_default() - read a signed 32-bit int from a device's DT property + * + * @dev: device to read DT property from + * @propname: name of the property to read from + * @def: default value to return if the property has no value + * @return property value, or @def if not found + */ +int dev_read_s32_default(const struct udevice *dev, const char *propname, + int def); + +/** + * dev_read_u32u() - read a 32-bit integer from a device's DT property + * + * This version uses a standard uint type. + * + * @dev: device to read DT property from + * @propname: name of the property to read from + * @outp: place to put value (if found) + * @return 0 if OK, -ve on error + */ +int dev_read_u32u(const struct udevice *dev, const char *propname, uint *outp); + +/** + * dev_read_u64() - read a 64-bit integer from a device's DT property + * + * @dev: device to read DT property from + * @propname: name of the property to read from + * @outp: place to put value (if found) + * @return 0 if OK, -ve on error + */ +int dev_read_u64(const struct udevice *dev, const char *propname, u64 *outp); + +/** + * dev_read_u64_default() - read a 64-bit integer from a device's DT property + * + * @dev: device to read DT property from + * @propname: name of the property to read from + * @def: default value to return if the property has no value + * @return property value, or @def if not found + */ +u64 dev_read_u64_default(const struct udevice *dev, const char *propname, + u64 def); + +/** + * dev_read_string() - Read a string from a device's DT property + * + * @dev: device to read DT property from + * @propname: name of the property to read + * @return string from property value, or NULL if there is no such property + */ +const char *dev_read_string(const struct udevice *dev, const char *propname); + +/** + * dev_read_bool() - read a boolean value from a device's DT property + * + * @dev: device to read DT property from + * @propname: name of property to read + * @return true if property is present (meaning true), false if not present + */ +bool dev_read_bool(const struct udevice *dev, const char *propname); + +/** + * dev_read_subnode() - find a named subnode of a device + * + * @dev: device whose DT node contains the subnode + * @subnode_name: name of subnode to find + * @return reference to subnode (which can be invalid if there is no such + * subnode) + */ +ofnode dev_read_subnode(const struct udevice *dev, const char *subbnode_name); + +/** + * dev_read_size() - read the size of a property + * + * @dev: device to check + * @propname: property to check + * @return size of property if present, or -EINVAL if not + */ +int dev_read_size(const struct udevice *dev, const char *propname); + +/** + * dev_read_addr_index() - Get the indexed reg property of a device + * + * @dev: Device to read from + * @index: the 'reg' property can hold a list of pairs + * and @index is used to select which one is required + * + * @return address or FDT_ADDR_T_NONE if not found + */ +fdt_addr_t dev_read_addr_index(const struct udevice *dev, int index); + +/** + * dev_read_addr_size_index() - Get the indexed reg property of a device + * + * @dev: Device to read from + * @index: the 'reg' property can hold a list of pairs + * and @index is used to select which one is required + * @size: place to put size value (on success) + * + * @return address or FDT_ADDR_T_NONE if not found + */ +fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index, + fdt_size_t *size); + +/** + * dev_remap_addr_index() - Get the indexed reg property of a device + * as a memory-mapped I/O pointer + * + * @dev: Device to read from + * @index: the 'reg' property can hold a list of pairs + * and @index is used to select which one is required + * + * @return pointer or NULL if not found + */ +void *dev_remap_addr_index(const struct udevice *dev, int index); + +/** + * dev_read_addr_name() - Get the reg property of a device, indexed by name + * + * @dev: Device to read from + * @name: the 'reg' property can hold a list of pairs, with the + * 'reg-names' property providing named-based identification. @index + * indicates the value to search for in 'reg-names'. + * + * @return address or FDT_ADDR_T_NONE if not found + */ +fdt_addr_t dev_read_addr_name(const struct udevice *dev, const char *name); + +/** + * dev_read_addr_size_name() - Get the reg property of a device, indexed by name + * + * @dev: Device to read from + * @name: the 'reg' property can hold a list of pairs, with the + * 'reg-names' property providing named-based identification. @index + * indicates the value to search for in 'reg-names'. + * @size: place to put size value (on success) + * + * @return address or FDT_ADDR_T_NONE if not found + */ +fdt_addr_t dev_read_addr_size_name(const struct udevice *dev, const char *name, + fdt_size_t *size); + +/** + * dev_remap_addr_name() - Get the reg property of a device, indexed by name, + * as a memory-mapped I/O pointer + * + * @dev: Device to read from + * @name: the 'reg' property can hold a list of pairs, with the + * 'reg-names' property providing named-based identification. @index + * indicates the value to search for in 'reg-names'. + * + * @return pointer or NULL if not found + */ +void *dev_remap_addr_name(const struct udevice *dev, const char *name); + +/** + * dev_read_addr() - Get the reg property of a device + * + * @dev: Device to read from + * + * @return address or FDT_ADDR_T_NONE if not found + */ +fdt_addr_t dev_read_addr(const struct udevice *dev); + +/** + * dev_read_addr_ptr() - Get the reg property of a device + * as a pointer + * + * @dev: Device to read from + * + * @return pointer or NULL if not found + */ +void *dev_read_addr_ptr(const struct udevice *dev); + +/** + * dev_read_addr_pci() - Read an address and handle PCI address translation + * + * At present U-Boot does not have address translation logic for PCI in the + * livetree implementation (of_addr.c). This special function supports this for + * the flat tree implementation. + * + * This function should be removed (and code should use dev_read() instead) + * once: + * + * 1. PCI address translation is added; and either + * 2. everything uses livetree where PCI translation is used (which is feasible + * in SPL and U-Boot proper) or PCI address translation is added to + * fdtdec_get_addr() and friends. + * + * @dev: Device to read from + * @return address or FDT_ADDR_T_NONE if not found + */ +fdt_addr_t dev_read_addr_pci(const struct udevice *dev); + +/** + * dev_remap_addr() - Get the reg property of a device as a + * memory-mapped I/O pointer + * + * @dev: Device to read from + * + * @return pointer or NULL if not found + */ +void *dev_remap_addr(const struct udevice *dev); + +/** + * dev_read_addr_size() - get address and size from a device property + * + * This does no address translation. It simply reads an property that contains + * an address and a size value, one after the other. + * + * @dev: Device to read from + * @propname: property to read + * @sizep: place to put size value (on success) + * @return address value, or FDT_ADDR_T_NONE on error + */ +fdt_addr_t dev_read_addr_size(const struct udevice *dev, const char *propname, + fdt_size_t *sizep); + +/** + * dev_read_name() - get the name of a device's node + * + * @dev: Device to read from + * @return name of node + */ +const char *dev_read_name(const struct udevice *dev); + +/** + * dev_read_stringlist_search() - find string in a string list and return index + * + * Note that it is possible for this function to succeed on property values + * that are not NUL-terminated. That's because the function will stop after + * finding the first occurrence of @string. This can for example happen with + * small-valued cell properties, such as #address-cells, when searching for + * the empty string. + * + * @dev: device to check + * @propname: name of the property containing the string list + * @string: string to look up in the string list + * + * @return: + * the index of the string in the list of strings + * -ENODATA if the property is not found + * -EINVAL on some other error + */ +int dev_read_stringlist_search(const struct udevice *dev, const char *property, + const char *string); + +/** + * dev_read_string_index() - obtain an indexed string from a string list + * + * @dev: device to examine + * @propname: name of the property containing the string list + * @index: index of the string to return + * @out: return location for the string + * + * @return: + * length of string, if found or -ve error value if not found + */ +int dev_read_string_index(const struct udevice *dev, const char *propname, + int index, const char **outp); + +/** + * dev_read_string_count() - find the number of strings in a string list + * + * @dev: device to examine + * @propname: name of the property containing the string list + * @return: + * number of strings in the list, or -ve error value if not found + */ +int dev_read_string_count(const struct udevice *dev, const char *propname); +/** + * dev_read_phandle_with_args() - Find a node pointed by phandle in a list + * + * This function is useful to parse lists of phandles and their arguments. + * Returns 0 on success and fills out_args, on error returns appropriate + * errno value. + * + * Caller is responsible to call of_node_put() on the returned out_args->np + * pointer. + * + * Example: + * + * phandle1: node1 { + * #list-cells = <2>; + * } + * + * phandle2: node2 { + * #list-cells = <1>; + * } + * + * node3 { + * list = <&phandle1 1 2 &phandle2 3>; + * } + * + * To get a device_node of the `node2' node you may call this: + * dev_read_phandle_with_args(dev, "list", "#list-cells", 0, 1, &args); + * + * @dev: device whose node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cells_count: Cell count to use if @cells_name is NULL + * @index: index of a phandle to parse out + * @out_args: optional pointer to output arguments structure (will be filled) + * @return 0 on success (with @out_args filled out if not NULL), -ENOENT if + * @list_name does not exist, -EINVAL if a phandle was not found, + * @cells_name could not be found, the arguments were truncated or there + * were too many arguments. + */ +int dev_read_phandle_with_args(const struct udevice *dev, const char *list_name, + const char *cells_name, int cell_count, + int index, struct ofnode_phandle_args *out_args); + +/** + * dev_count_phandle_with_args() - Return phandle number in a list + * + * This function is usefull to get phandle number contained in a property list. + * For example, this allows to allocate the right amount of memory to keep + * clock's reference contained into the "clocks" property. + * + * + * @dev: device whose node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cells_count: Cell count to use if @cells_name is NULL + * @Returns number of phandle found on success, on error returns appropriate + * errno value. + */ + +int dev_count_phandle_with_args(const struct udevice *dev, + const char *list_name, const char *cells_name, + int cell_count); + +/** + * dev_read_addr_cells() - Get the number of address cells for a device's node + * + * This walks back up the tree to find the closest #address-cells property + * which controls the given node. + * + * @dev: device to check + * @return number of address cells this node uses + */ +int dev_read_addr_cells(const struct udevice *dev); + +/** + * dev_read_size_cells() - Get the number of size cells for a device's node + * + * This walks back up the tree to find the closest #size-cells property + * which controls the given node. + * + * @dev: device to check + * @return number of size cells this node uses + */ +int dev_read_size_cells(const struct udevice *dev); + +/** + * dev_read_addr_cells() - Get the address cells property in a node + * + * This function matches fdt_address_cells(). + * + * @dev: device to check + * @return number of address cells this node uses + */ +int dev_read_simple_addr_cells(const struct udevice *dev); + +/** + * dev_read_size_cells() - Get the size cells property in a node + * + * This function matches fdt_size_cells(). + * + * @dev: device to check + * @return number of size cells this node uses + */ +int dev_read_simple_size_cells(const struct udevice *dev); + +/** + * dev_read_phandle() - Get the phandle from a device + * + * @dev: device to check + * @return phandle (1 or greater), or 0 if no phandle or other error + */ +int dev_read_phandle(const struct udevice *dev); + +/** + * dev_read_prop()- - read a property from a device's node + * + * @dev: device to check + * @propname: property to read + * @lenp: place to put length on success + * @return pointer to property, or NULL if not found + */ +const void *dev_read_prop(const struct udevice *dev, const char *propname, + int *lenp); + +/** + * dev_read_first_prop()- get the reference of the first property + * + * Get reference to the first property of the node, it is used to iterate + * and read all the property with dev_read_prop_by_prop(). + * + * @dev: device to check + * @prop: place to put argument reference + * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found + */ +int dev_read_first_prop(const struct udevice *dev, struct ofprop *prop); + +/** + * ofnode_get_next_property() - get the reference of the next property + * + * Get reference to the next property of the node, it is used to iterate + * and read all the property with dev_read_prop_by_prop(). + * + * @prop: reference of current argument and place to put reference of next one + * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found + */ +int dev_read_next_prop(struct ofprop *prop); + +/** + * dev_read_prop_by_prop() - get a pointer to the value of a property + * + * Get value for the property identified by the provided reference. + * + * @prop: reference on property + * @propname: If non-NULL, place to property name on success, + * @lenp: If non-NULL, place to put length on success + * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found + */ +const void *dev_read_prop_by_prop(struct ofprop *prop, + const char **propname, int *lenp); + +/** + * dev_read_alias_seq() - Get the alias sequence number of a node + * + * This works out whether a node is pointed to by an alias, and if so, the + * sequence number of that alias. Aliases are of the form where + * is the sequence number. For example spi2 would be sequence number 2. + * + * @dev: device to look up + * @devnump: set to the sequence number if one is found + * @return 0 if a sequence was found, -ve if not + */ +int dev_read_alias_seq(const struct udevice *dev, int *devnump); + +/** + * dev_read_u32_array() - Find and read an array of 32 bit integers + * + * Search for a property in a device node and read 32-bit value(s) from + * it. + * + * The out_values is modified only if a valid u32 value can be decoded. + * + * @dev: device to look up + * @propname: name of the property to read + * @out_values: pointer to return value, modified only if return value is 0 + * @sz: number of array elements to read + * @return 0 on success, -EINVAL if the property does not exist, -ENODATA if + * property does not have a value, and -EOVERFLOW if the property data isn't + * large enough. + */ +int dev_read_u32_array(const struct udevice *dev, const char *propname, + u32 *out_values, size_t sz); + +/** + * dev_read_first_subnode() - find the first subnode of a device's node + * + * @dev: device to look up + * @return reference to the first subnode (which can be invalid if the device's + * node has no subnodes) + */ +ofnode dev_read_first_subnode(const struct udevice *dev); + +/** + * ofnode_next_subnode() - find the next sibling of a subnode + * + * @node: valid reference to previous node (sibling) + * @return reference to the next subnode (which can be invalid if the node + * has no more siblings) + */ +ofnode dev_read_next_subnode(ofnode node); + +/** + * dev_read_u8_array_ptr() - find an 8-bit array + * + * Look up a device's node property and return a pointer to its contents as a + * byte array of given length. The property must have at least enough data + * for the array (count bytes). It may have more, but this will be ignored. + * The data is not copied. + * + * @dev: device to look up + * @propname: name of property to find + * @sz: number of array elements + * @return pointer to byte array if found, or NULL if the property is not + * found or there is not enough data + */ +const uint8_t *dev_read_u8_array_ptr(const struct udevice *dev, + const char *propname, size_t sz); + +/** + * dev_read_enabled() - check whether a node is enabled + * + * This looks for a 'status' property. If this exists, then returns 1 if + * the status is 'ok' and 0 otherwise. If there is no status property, + * it returns 1 on the assumption that anything mentioned should be enabled + * by default. + * + * @dev: device to examine + * @return integer value 0 (not enabled) or 1 (enabled) + */ +int dev_read_enabled(const struct udevice *dev); + +/** + * dev_read_resource() - obtain an indexed resource from a device. + * + * @dev: device to examine + * @index index of the resource to retrieve (0 = first) + * @res returns the resource + * @return 0 if ok, negative on error + */ +int dev_read_resource(const struct udevice *dev, uint index, + struct resource *res); + +/** + * dev_read_resource_byname() - obtain a named resource from a device. + * + * @dev: device to examine + * @name: name of the resource to retrieve + * @res: returns the resource + * @return 0 if ok, negative on error + */ +int dev_read_resource_byname(const struct udevice *dev, const char *name, + struct resource *res); + +/** + * dev_translate_address() - Translate a device-tree address + * + * Translate an address from the device-tree into a CPU physical address. This + * function walks up the tree and applies the various bus mappings along the + * way. + * + * @dev: device giving the context in which to translate the address + * @in_addr: pointer to the address to translate + * @return the translated address; OF_BAD_ADDR on error + */ +u64 dev_translate_address(const struct udevice *dev, const fdt32_t *in_addr); + +/** + * dev_translate_dma_address() - Translate a device-tree DMA address + * + * Translate a DMA address from the device-tree into a CPU physical address. + * This function walks up the tree and applies the various bus mappings along + * the way. + * + * @dev: device giving the context in which to translate the DMA address + * @in_addr: pointer to the DMA address to translate + * @return the translated DMA address; OF_BAD_ADDR on error + */ +u64 dev_translate_dma_address(const struct udevice *dev, + const fdt32_t *in_addr); + +/** + * dev_get_dma_range() - Get a device's DMA constraints + * + * Provide the address bases and size of the linear mapping between the CPU and + * a device's BUS address space. + * + * @dev: device giving the context in which to translate the DMA address + * @cpu: base address for CPU's view of memory + * @bus: base address for BUS's view of memory + * @size: size of the address space + * @return 0 if ok, negative on error + */ +int dev_get_dma_range(const struct udevice *dev, phys_addr_t *cpu, + dma_addr_t *bus, u64 *size); + +/** + * dev_read_alias_highest_id - Get highest alias id for the given stem + * @stem: Alias stem to be examined + * + * The function travels the lookup table to get the highest alias id for the + * given alias stem. + * @return alias ID, if found, else -1 + */ +int dev_read_alias_highest_id(const char *stem); + +/** + * dev_get_child_count() - get the child count of a device + * + * @dev: device to use for interation (struct udevice *) + * @return the count of child subnode + */ +int dev_get_child_count(const struct udevice *dev); + +/** + * dev_read_pci_bus_range - Read PCI bus-range resource + * + * Look at the bus range property of a device node and return the pci bus + * range for this node. + * + * @dev: device to examine + * @res returns the resource + * @return 0 if ok, negative on error + */ +int dev_read_pci_bus_range(const struct udevice *dev, struct resource *res); + +/** + * dev_decode_display_timing() - decode display timings + * + * Decode display timings from the supplied 'display-timings' node. + * See doc/device-tree-bindings/video/display-timing.txt for binding + * information. + * + * @dev: device to read DT display timings from. The node linked to the device + * contains a child node called 'display-timings' which in turn contains + * one or more display timing nodes. + * @index: index number to read (0=first timing subnode) + * @config: place to put timings + * @return 0 if OK, -FDT_ERR_NOTFOUND if not found + */ +int dev_decode_display_timing(const struct udevice *dev, int index, + struct display_timing *config); + +#else /* CONFIG_DM_DEV_READ_INLINE is enabled */ +#include + +static inline int dev_read_u32(const struct udevice *dev, + const char *propname, u32 *outp) +{ + return ofnode_read_u32(dev_ofnode(dev), propname, outp); +} + +static inline int dev_read_u32_default(const struct udevice *dev, + const char *propname, int def) +{ + return ofnode_read_u32_default(dev_ofnode(dev), propname, def); +} + +static inline int dev_read_u32_index(struct udevice *dev, + const char *propname, int index, u32 *outp) +{ + return ofnode_read_u32_index(dev_ofnode(dev), propname, index, outp); +} + +static inline u32 dev_read_u32_index_default(struct udevice *dev, + const char *propname, int index, + u32 def) +{ + return ofnode_read_u32_index_default(dev_ofnode(dev), propname, index, + def); +} + +static inline int dev_read_s32(const struct udevice *dev, + const char *propname, s32 *outp) +{ + return ofnode_read_s32(dev_ofnode(dev), propname, outp); +} + +static inline int dev_read_s32_default(const struct udevice *dev, + const char *propname, int def) +{ + return ofnode_read_s32_default(dev_ofnode(dev), propname, def); +} + +static inline int dev_read_u32u(const struct udevice *dev, + const char *propname, uint *outp) +{ + u32 val; + int ret; + + ret = ofnode_read_u32(dev_ofnode(dev), propname, &val); + if (ret) + return ret; + *outp = val; + + return 0; +} + +static inline int dev_read_u64(const struct udevice *dev, + const char *propname, u64 *outp) +{ + return ofnode_read_u64(dev_ofnode(dev), propname, outp); +} + +static inline u64 dev_read_u64_default(const struct udevice *dev, + const char *propname, u64 def) +{ + return ofnode_read_u64_default(dev_ofnode(dev), propname, def); +} + +static inline const char *dev_read_string(const struct udevice *dev, + const char *propname) +{ + return ofnode_read_string(dev_ofnode(dev), propname); +} + +static inline bool dev_read_bool(const struct udevice *dev, + const char *propname) +{ + return ofnode_read_bool(dev_ofnode(dev), propname); +} + +static inline ofnode dev_read_subnode(const struct udevice *dev, + const char *subbnode_name) +{ + return ofnode_find_subnode(dev_ofnode(dev), subbnode_name); +} + +static inline int dev_read_size(const struct udevice *dev, const char *propname) +{ + return ofnode_read_size(dev_ofnode(dev), propname); +} + +static inline fdt_addr_t dev_read_addr_index(const struct udevice *dev, + int index) +{ + return devfdt_get_addr_index(dev, index); +} + +static inline fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, + int index, + fdt_size_t *size) +{ + return devfdt_get_addr_size_index(dev, index, size); +} + +static inline fdt_addr_t dev_read_addr_name(const struct udevice *dev, + const char *name) +{ + return devfdt_get_addr_name(dev, name); +} + +static inline fdt_addr_t dev_read_addr_size_name(const struct udevice *dev, + const char *name, + fdt_size_t *size) +{ + return devfdt_get_addr_size_name(dev, name, size); +} + +static inline fdt_addr_t dev_read_addr(const struct udevice *dev) +{ + return devfdt_get_addr(dev); +} + +static inline void *dev_read_addr_ptr(const struct udevice *dev) +{ + return devfdt_get_addr_ptr(dev); +} + +static inline fdt_addr_t dev_read_addr_pci(const struct udevice *dev) +{ + return devfdt_get_addr_pci(dev); +} + +static inline void *dev_remap_addr(const struct udevice *dev) +{ + return devfdt_remap_addr(dev); +} + +static inline void *dev_remap_addr_index(const struct udevice *dev, int index) +{ + return devfdt_remap_addr_index(dev, index); +} + +static inline void *dev_remap_addr_name(const struct udevice *dev, + const char *name) +{ + return devfdt_remap_addr_name(dev, name); +} + +static inline fdt_addr_t dev_read_addr_size(const struct udevice *dev, + const char *propname, + fdt_size_t *sizep) +{ + return ofnode_get_addr_size(dev_ofnode(dev), propname, sizep); +} + +static inline const char *dev_read_name(const struct udevice *dev) +{ + return ofnode_get_name(dev_ofnode(dev)); +} + +static inline int dev_read_stringlist_search(const struct udevice *dev, + const char *propname, + const char *string) +{ + return ofnode_stringlist_search(dev_ofnode(dev), propname, string); +} + +static inline int dev_read_string_index(const struct udevice *dev, + const char *propname, int index, + const char **outp) +{ + return ofnode_read_string_index(dev_ofnode(dev), propname, index, outp); +} + +static inline int dev_read_string_count(const struct udevice *dev, + const char *propname) +{ + return ofnode_read_string_count(dev_ofnode(dev), propname); +} + +static inline int dev_read_phandle_with_args(const struct udevice *dev, + const char *list_name, const char *cells_name, int cell_count, + int index, struct ofnode_phandle_args *out_args) +{ + return ofnode_parse_phandle_with_args(dev_ofnode(dev), list_name, + cells_name, cell_count, index, + out_args); +} + +static inline int dev_count_phandle_with_args(const struct udevice *dev, + const char *list_name, const char *cells_name, int cell_count) +{ + return ofnode_count_phandle_with_args(dev_ofnode(dev), list_name, + cells_name, cell_count); +} + +static inline int dev_read_addr_cells(const struct udevice *dev) +{ + int parent = fdt_parent_offset(gd->fdt_blob, dev_of_offset(dev)); + + return fdt_address_cells(gd->fdt_blob, parent); +} + +static inline int dev_read_size_cells(const struct udevice *dev) +{ + int parent = fdt_parent_offset(gd->fdt_blob, dev_of_offset(dev)); + + return fdt_size_cells(gd->fdt_blob, parent); +} + +static inline int dev_read_simple_addr_cells(const struct udevice *dev) +{ + return fdt_address_cells(gd->fdt_blob, dev_of_offset(dev)); +} + +static inline int dev_read_simple_size_cells(const struct udevice *dev) +{ + return fdt_size_cells(gd->fdt_blob, dev_of_offset(dev)); +} + +static inline int dev_read_phandle(const struct udevice *dev) +{ + return fdt_get_phandle(gd->fdt_blob, dev_of_offset(dev)); +} + +static inline const void *dev_read_prop(const struct udevice *dev, + const char *propname, int *lenp) +{ + return ofnode_get_property(dev_ofnode(dev), propname, lenp); +} + +static inline int dev_read_first_prop(const struct udevice *dev, struct ofprop *prop) +{ + return ofnode_get_first_property(dev_ofnode(dev), prop); +} + +static inline int dev_read_next_prop(struct ofprop *prop) +{ + return ofnode_get_next_property(prop); +} + +static inline const void *dev_read_prop_by_prop(struct ofprop *prop, + const char **propname, + int *lenp) +{ + return ofnode_get_property_by_prop(prop, propname, lenp); +} + +static inline int dev_read_alias_seq(const struct udevice *dev, int *devnump) +{ +#if CONFIG_IS_ENABLED(OF_CONTROL) + return fdtdec_get_alias_seq(gd->fdt_blob, dev->uclass->uc_drv->name, + dev_of_offset(dev), devnump); +#else + return -ENOTSUPP; +#endif +} + +static inline int dev_read_u32_array(const struct udevice *dev, + const char *propname, u32 *out_values, + size_t sz) +{ + return ofnode_read_u32_array(dev_ofnode(dev), propname, out_values, sz); +} + +static inline ofnode dev_read_first_subnode(const struct udevice *dev) +{ + return ofnode_first_subnode(dev_ofnode(dev)); +} + +static inline ofnode dev_read_next_subnode(ofnode node) +{ + return ofnode_next_subnode(node); +} + +static inline const uint8_t *dev_read_u8_array_ptr(const struct udevice *dev, + const char *propname, + size_t sz) +{ + return ofnode_read_u8_array_ptr(dev_ofnode(dev), propname, sz); +} + +static inline int dev_read_enabled(const struct udevice *dev) +{ + return fdtdec_get_is_enabled(gd->fdt_blob, dev_of_offset(dev)); +} + +static inline int dev_read_resource(const struct udevice *dev, uint index, + struct resource *res) +{ + return ofnode_read_resource(dev_ofnode(dev), index, res); +} + +static inline int dev_read_resource_byname(const struct udevice *dev, + const char *name, + struct resource *res) +{ + return ofnode_read_resource_byname(dev_ofnode(dev), name, res); +} + +static inline u64 dev_translate_address(const struct udevice *dev, + const fdt32_t *in_addr) +{ + return ofnode_translate_address(dev_ofnode(dev), in_addr); +} + +static inline u64 dev_translate_dma_address(const struct udevice *dev, + const fdt32_t *in_addr) +{ + return ofnode_translate_dma_address(dev_ofnode(dev), in_addr); +} + +static inline int dev_get_dma_range(const struct udevice *dev, phys_addr_t *cpu, + dma_addr_t *bus, u64 *size) +{ + return ofnode_get_dma_range(dev_ofnode(dev), cpu, bus, size); +} + +static inline int dev_read_alias_highest_id(const char *stem) +{ + if (!CONFIG_IS_ENABLED(OF_LIBFDT) || !gd->fdt_blob) + return -1; + return fdtdec_get_alias_highest_id(gd->fdt_blob, stem); +} + +static inline int dev_get_child_count(const struct udevice *dev) +{ + return ofnode_get_child_count(dev_ofnode(dev)); +} + +static inline int dev_decode_display_timing(const struct udevice *dev, + int index, + struct display_timing *config) +{ + return ofnode_decode_display_timing(dev_ofnode(dev), index, config); +} + +#endif /* CONFIG_DM_DEV_READ_INLINE */ + +/** + * dev_for_each_subnode() - Helper function to iterate through subnodes + * + * This creates a for() loop which works through the subnodes in a device's + * device-tree node. + * + * @subnode: ofnode holding the current subnode + * @dev: device to use for interation (struct udevice *) + */ +#define dev_for_each_subnode(subnode, dev) \ + for (subnode = dev_read_first_subnode(dev); \ + ofnode_valid(subnode); \ + subnode = ofnode_next_subnode(subnode)) + +/** + * dev_for_each_property() - Helper function to iterate through property + * + * This creates a for() loop which works through the property in a device's + * device-tree node. + * + * @prop: struct ofprop holding the current property + * @dev: device to use for interation (struct udevice *) + */ +#define dev_for_each_property(prop, dev) \ + for (int ret_prop = dev_read_first_prop(dev, &prop); \ + !ret_prop; \ + ret_prop = dev_read_next_prop(&prop)) + +#endif diff --git a/roms/u-boot/include/dm/root.h b/roms/u-boot/include/dm/root.h new file mode 100644 index 000000000..42510b106 --- /dev/null +++ b/roms/u-boot/include/dm/root.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + */ + +#ifndef _DM_ROOT_H_ +#define _DM_ROOT_H_ + +struct udevice; + +/* Head of the uclass list if CONFIG_OF_PLATDATA_INST is enabled */ +extern struct list_head uclass_head; + +/** + * dm_root() - Return pointer to the top of the driver tree + * + * This function returns pointer to the root node of the driver tree, + * + * @return pointer to root device, or NULL if not inited yet + */ +struct udevice *dm_root(void); + +struct global_data; +/** + * dm_fixup_for_gd_move() - Handle global_data moving to a new place + * + * The uclass list is part of global_data. Due to the way lists work, moving + * the list will cause it to become invalid. This function fixes that up so + * that the uclass list will work correctly. + */ +void dm_fixup_for_gd_move(struct global_data *new_gd); + +/** + * dm_scan_plat() - Scan all platform data and bind drivers + * + * This scans all available plat and creates drivers for each + * + * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC + * flag. If false bind all drivers. + * @return 0 if OK, -ve on error + */ +int dm_scan_plat(bool pre_reloc_only); + +/** + * dm_scan_fdt() - Scan the device tree and bind drivers + * + * This scans the device tree and creates a driver for each node. Only + * the top-level subnodes are examined. + * + * @pre_reloc_only: If true, bind only nodes with special devicetree properties, + * or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers. + * @return 0 if OK, -ve on error + */ +int dm_scan_fdt(bool pre_reloc_only); + +/** + * dm_extended_scan() - Scan the device tree and bind drivers + * + * This calls dm_scna_dft() which scans the device tree and creates a driver + * for each node. the top-level subnodes are examined and also all sub-nodes + * of "clocks" node. + * + * @pre_reloc_only: If true, bind only nodes with special devicetree properties, + * or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers. + * @return 0 if OK, -ve on error + */ +int dm_extended_scan(bool pre_reloc_only); + +/** + * dm_scan_other() - Scan for other devices + * + * Some devices may not be visible to Driver Model. This weak function can + * be provided by boards which wish to create their own devices + * programmaticaly. They should do this by calling device_bind() on each + * device. + * + * @pre_reloc_only: If true, bind only nodes with special devicetree properties, + * or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers. + * @return 0 if OK, -ve on error + */ +int dm_scan_other(bool pre_reloc_only); + +/** + * dm_init_and_scan() - Initialise Driver Model structures and scan for devices + * + * This function initialises the roots of the driver tree and uclass trees, + * then scans and binds available devices from platform data and the FDT. + * This calls dm_init() to set up Driver Model structures. + * + * @pre_reloc_only: If true, bind only nodes with special devicetree properties, + * or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers. + * @return 0 if OK, -ve on error + */ +int dm_init_and_scan(bool pre_reloc_only); + +/** + * dm_init() - Initialise Driver Model structures + * + * This function will initialize roots of driver tree and class tree. + * This needs to be called before anything uses the DM + * + * @of_live: Enable live device tree + * @return 0 if OK, -ve on error + */ +int dm_init(bool of_live); + +/** + * dm_uninit - Uninitialise Driver Model structures + * + * All devices will be removed and unbound + * @return 0 if OK, -ve on error + */ +int dm_uninit(void); + +#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE) +/** + * dm_remove_devices_flags - Call remove function of all drivers with + * specific removal flags set to selectively + * remove drivers + * + * All devices with the matching flags set will be removed + * + * @flags: Flags for selective device removal + * @return 0 if OK, -ve on error + */ +int dm_remove_devices_flags(uint flags); +#else +static inline int dm_remove_devices_flags(uint flags) { return 0; } +#endif + +#endif diff --git a/roms/u-boot/include/dm/simple_bus.h b/roms/u-boot/include/dm/simple_bus.h new file mode 100644 index 000000000..b7104013c --- /dev/null +++ b/roms/u-boot/include/dm/simple_bus.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Google LLC + */ + +#ifndef __DM_SIMPLE_BUS_H +#define __DM_SIMPLE_BUS_H + +struct simple_bus_plat { + fdt_addr_t base; + fdt_size_t size; + fdt_addr_t target; +}; + +#endif diff --git a/roms/u-boot/include/dm/test.h b/roms/u-boot/include/dm/test.h new file mode 100644 index 000000000..a9562b2bf --- /dev/null +++ b/roms/u-boot/include/dm/test.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2013 Google, Inc. + */ + +#ifndef __DM_TEST_H +#define __DM_TEST_H + +struct udevice; + +/** + * struct dm_test_cdata - configuration data for test instance + * + * @ping_add: Amonut to add each time we get a ping + * @base: Base address of this device + */ +struct dm_test_pdata { + int ping_add; + uint32_t base; +}; + +/** + * struct test_ops - Operations supported by the test device + * + * @ping: Ping operation + * @dev: Device to operate on + * @pingval: Value to ping the device with + * @pingret: Returns resulting value from driver + * @return 0 if OK, -ve on error + */ +struct test_ops { + int (*ping)(struct udevice *dev, int pingval, int *pingret); +}; + +/* Operations that our test driver supports */ +enum { + DM_TEST_OP_BIND = 0, + DM_TEST_OP_UNBIND, + DM_TEST_OP_PROBE, + DM_TEST_OP_REMOVE, + + /* For uclass */ + DM_TEST_OP_POST_BIND, + DM_TEST_OP_PRE_UNBIND, + DM_TEST_OP_PRE_PROBE, + DM_TEST_OP_POST_PROBE, + DM_TEST_OP_PRE_REMOVE, + DM_TEST_OP_INIT, + DM_TEST_OP_DESTROY, + + DM_TEST_OP_COUNT, +}; + +/* Test driver types */ +enum { + DM_TEST_TYPE_FIRST = 0, + DM_TEST_TYPE_SECOND, + + DM_TEST_TYPE_COUNT, +}; + +/* The number added to the ping total on each probe */ +#define DM_TEST_START_TOTAL 5 + +/** + * struct dm_test_priv - private data for the test devices + */ +struct dm_test_priv { + int ping_total; + int op_count[DM_TEST_OP_COUNT]; + int uclass_flag; + int uclass_total; + int uclass_postp; +}; + +/* struct dm_test_uc_priv - private data for the testdrv uclass */ +struct dm_test_uc_priv { + int dummy; +}; + +/** + * struct dm_test_perdev_class_priv - private per-device data for test uclass + */ +struct dm_test_uclass_perdev_priv { + int base_add; +}; + +/** + * struct dm_test_uclass_priv - private data for test uclass + */ +struct dm_test_uclass_priv { + int total_add; +}; + +/** + * struct dm_test_parent_data - parent's information on each child + * + * @sum: Test value used to check parent data works correctly + * @flag: Used to track calling of parent operations + * @uclass_flag: Used to track calling of parent operations by uclass + */ +struct dm_test_parent_data { + int sum; + int flag; +}; + +/* Test values for test device's uclass platform data */ +enum { + TEST_UC_PDATA_INTVAL1 = 2, + TEST_UC_PDATA_INTVAL2 = 334, + TEST_UC_PDATA_INTVAL3 = 789452, +}; + +/** + * struct dm_test_uclass_platda - uclass's information on each device + * + * @intval1: set to TEST_UC_PDATA_INTVAL1 in .post_bind method of test uclass + * @intval2: set to TEST_UC_PDATA_INTVAL2 in .post_bind method of test uclass + * @intval3: set to TEST_UC_PDATA_INTVAL3 in .post_bind method of test uclass + */ +struct dm_test_perdev_uc_pdata { + int intval1; + int intval2; + int intval3; +}; + +/* + * Operation counts for the test driver, used to check that each method is + * called correctly + */ +extern int dm_testdrv_op_count[DM_TEST_OP_COUNT]; + +extern struct unit_test_state global_dm_test_state; + +/* Declare a new driver model test */ +#define DM_TEST(_name, _flags) \ + UNIT_TEST(_name, UT_TESTF_DM | UT_TESTF_CONSOLE_REC | (_flags), dm_test) + +/* + * struct sandbox_sdl_plat - Platform data for the SDL video driver + * + * This platform data is needed in tests, so declare it here + * + * @xres: Width of display in pixels + * @yres: Height of display in pixels + * @bpix: Log2 of bits per pixel (enum video_log2_bpp) + * @rot: Console rotation (0=normal orientation, 1=90 degrees clockwise, + * 2=upside down, 3=90 degree counterclockwise) + * @vidconsole_drv_name: Name of video console driver (set by tests) + * @font_size: Console font size to select (set by tests) + */ +struct sandbox_sdl_plat { + int xres; + int yres; + int bpix; + int rot; + const char *vidconsole_drv_name; + int font_size; +}; + +/** + * struct dm_test_parent_plat - Used to track state in bus tests + * + * @count: + * @bind_flag: Indicates that the child post-bind method was called + * @uclass_bind_flag: Also indicates that the child post-bind method was called + */ +struct dm_test_parent_plat { + int count; + int bind_flag; + int uclass_bind_flag; +}; + +enum { + TEST_FLAG_CHILD_PROBED = 10, + TEST_FLAG_CHILD_REMOVED = -7, +}; + +/* Declare ping methods for the drivers */ +int test_ping(struct udevice *dev, int pingval, int *pingret); +int testfdt_ping(struct udevice *dev, int pingval, int *pingret); + +/** + * dm_check_operations() - Check that we can perform ping operations + * + * This checks that the ping operations work as expected for a device + * + * @dms: Overall test state + * @dev: Device to test + * @base: Base address, used to check ping return value + * @priv: Pointer to private test information + * @return 0 if OK, -ve on error + */ +int dm_check_operations(struct unit_test_state *uts, struct udevice *dev, + uint32_t base, struct dm_test_priv *priv); + +/** + * dm_check_devices() - check the devices respond to operations correctly + * + * @dms: Overall test state + * @num_devices: Number of test devices to check + * @return 0 if OK, -ve on error + */ +int dm_check_devices(struct unit_test_state *uts, int num_devices); + +/** + * dm_leak_check_start() - Prepare to check for a memory leak + * + * Call this before allocating memory to record the amount of memory being + * used. + * + * @dms: Overall test state + */ +void dm_leak_check_start(struct unit_test_state *uts); + +/** + * dm_leak_check_end() - Check that no memory has leaked + * + * Call this after dm_leak_check_start() and after you have hopefuilly freed + * all the memory that was allocated. This function will print an error if + * it sees a different amount of total memory allocated than before. + * + * @dms: Overall test state + */int dm_leak_check_end(struct unit_test_state *uts); + +#endif diff --git a/roms/u-boot/include/dm/uclass-id.h b/roms/u-boot/include/dm/uclass-id.h new file mode 100644 index 000000000..d800f679d --- /dev/null +++ b/roms/u-boot/include/dm/uclass-id.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + */ + +#ifndef _DM_UCLASS_ID_H +#define _DM_UCLASS_ID_H + +/* TODO(sjg@chromium.org): this could be compile-time generated */ +enum uclass_id { + /* These are used internally by driver model */ + UCLASS_ROOT = 0, + UCLASS_DEMO, + UCLASS_TEST, + UCLASS_TEST_FDT, + UCLASS_TEST_FDT_MANUAL, + UCLASS_TEST_BUS, + UCLASS_TEST_PROBE, + UCLASS_TEST_DUMMY, + UCLASS_TEST_DEVRES, + UCLASS_TEST_ACPI, + UCLASS_SPI_EMUL, /* sandbox SPI device emulator */ + UCLASS_I2C_EMUL, /* sandbox I2C device emulator */ + UCLASS_I2C_EMUL_PARENT, /* parent for I2C device emulators */ + UCLASS_PCI_EMUL, /* sandbox PCI device emulator */ + UCLASS_PCI_EMUL_PARENT, /* parent for PCI device emulators */ + UCLASS_USB_EMUL, /* sandbox USB bus device emulator */ + UCLASS_AXI_EMUL, /* sandbox AXI bus device emulator */ + + /* U-Boot uclasses start here - in alphabetical order */ + UCLASS_ACPI_PMC, /* (x86) Power-management controller (PMC) */ + UCLASS_ADC, /* Analog-to-digital converter */ + UCLASS_AHCI, /* SATA disk controller */ + UCLASS_AUDIO_CODEC, /* Audio codec with control and data path */ + UCLASS_AXI, /* AXI bus */ + UCLASS_BLK, /* Block device */ + UCLASS_BOOTCOUNT, /* Bootcount backing store */ + UCLASS_BUTTON, /* Button */ + UCLASS_CACHE, /* Cache controller */ + UCLASS_CLK, /* Clock source, e.g. used by peripherals */ + UCLASS_CPU, /* CPU, typically part of an SoC */ + UCLASS_CROS_EC, /* Chrome OS EC */ + UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */ + UCLASS_DSI_HOST, /* Display Serial Interface host */ + UCLASS_DMA, /* Direct Memory Access */ + UCLASS_DSA, /* Distributed (Ethernet) Switch Architecture */ + UCLASS_EFI, /* EFI managed devices */ + UCLASS_ETH, /* Ethernet device */ + UCLASS_ETH_PHY, /* Ethernet PHY device */ + UCLASS_FIRMWARE, /* Firmware */ + UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */ + UCLASS_GPIO, /* Bank of general-purpose I/O pins */ + UCLASS_HWSPINLOCK, /* Hardware semaphores */ + UCLASS_I2C, /* I2C bus */ + UCLASS_I2C_EEPROM, /* I2C EEPROM device */ + UCLASS_I2C_GENERIC, /* Generic I2C device */ + UCLASS_I2C_MUX, /* I2C multiplexer */ + UCLASS_I2S, /* I2S bus */ + UCLASS_IDE, /* IDE device */ + UCLASS_IRQ, /* Interrupt controller */ + UCLASS_KEYBOARD, /* Keyboard input device */ + UCLASS_LED, /* Light-emitting diode (LED) */ + UCLASS_LPC, /* x86 'low pin count' interface */ + UCLASS_MAILBOX, /* Mailbox controller */ + UCLASS_MASS_STORAGE, /* Mass storage device */ + UCLASS_MDIO, /* MDIO bus */ + UCLASS_MDIO_MUX, /* MDIO MUX/switch */ + UCLASS_MISC, /* Miscellaneous device */ + UCLASS_MMC, /* SD / MMC card or chip */ + UCLASS_MOD_EXP, /* RSA Mod Exp device */ + UCLASS_MTD, /* Memory Technology Device (MTD) device */ + UCLASS_MUX, /* Multiplexer device */ + UCLASS_NOP, /* No-op devices */ + UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */ + UCLASS_NVME, /* NVM Express device */ + UCLASS_P2SB, /* (x86) Primary-to-Sideband Bus */ + UCLASS_PANEL, /* Display panel, such as an LCD */ + UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */ + UCLASS_PCH, /* x86 platform controller hub */ + UCLASS_PCI, /* PCI bus */ + UCLASS_PCI_EP, /* PCI endpoint device */ + UCLASS_PCI_GENERIC, /* Generic PCI bus device */ + UCLASS_PHY, /* Physical Layer (PHY) device */ + UCLASS_PINCONFIG, /* Pin configuration node device */ + UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */ + UCLASS_PMIC, /* PMIC I/O device */ + UCLASS_POWER_DOMAIN, /* (SoC) Power domains */ + UCLASS_PWM, /* Pulse-width modulator */ + UCLASS_PWRSEQ, /* Power sequence device */ + UCLASS_QFW, /* QEMU firmware config device */ + UCLASS_RAM, /* RAM controller */ + UCLASS_REGULATOR, /* Regulator device */ + UCLASS_REMOTEPROC, /* Remote Processor device */ + UCLASS_RESET, /* Reset controller device */ + UCLASS_RNG, /* Random Number Generator */ + UCLASS_RTC, /* Real time clock device */ + UCLASS_SCMI_AGENT, /* Interface with an SCMI server */ + UCLASS_SCSI, /* SCSI device */ + UCLASS_SERIAL, /* Serial UART */ + UCLASS_SIMPLE_BUS, /* Bus with child devices */ + UCLASS_SMEM, /* Shared memory interface */ + UCLASS_SOC, /* SOC Device */ + UCLASS_SOUND, /* Playing simple sounds */ + UCLASS_SPI, /* SPI bus */ + UCLASS_SPI_FLASH, /* SPI flash */ + UCLASS_SPI_GENERIC, /* Generic SPI flash target */ + UCLASS_SPMI, /* System Power Management Interface bus */ + UCLASS_SYSCON, /* System configuration device */ + UCLASS_SYSINFO, /* Device information from hardware */ + UCLASS_SYSRESET, /* System reset device */ + UCLASS_TEE, /* Trusted Execution Environment device */ + UCLASS_THERMAL, /* Thermal sensor */ + UCLASS_TIMER, /* Timer device */ + UCLASS_TPM, /* Trusted Platform Module TIS interface */ + UCLASS_UFS, /* Universal Flash Storage */ + UCLASS_USB, /* USB bus */ + UCLASS_USB_DEV_GENERIC, /* USB generic device */ + UCLASS_USB_HUB, /* USB hub */ + UCLASS_USB_GADGET_GENERIC, /* USB generic device */ + UCLASS_VIDEO, /* Video or LCD device */ + UCLASS_VIDEO_BRIDGE, /* Video bridge, e.g. DisplayPort to LVDS */ + UCLASS_VIDEO_CONSOLE, /* Text console driver for video device */ + UCLASS_VIDEO_OSD, /* On-screen display */ + UCLASS_VIRTIO, /* VirtIO transport device */ + UCLASS_W1, /* Dallas 1-Wire bus */ + UCLASS_W1_EEPROM, /* one-wire EEPROMs */ + UCLASS_WDT, /* Watchdog Timer driver */ + UCLASS_PVBLOCK, /* Xen virtual block device */ + + UCLASS_COUNT, + UCLASS_INVALID = -1, +}; + +#endif diff --git a/roms/u-boot/include/dm/uclass-internal.h b/roms/u-boot/include/dm/uclass-internal.h new file mode 100644 index 000000000..57c664c6d --- /dev/null +++ b/roms/u-boot/include/dm/uclass-internal.h @@ -0,0 +1,315 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + */ + +#ifndef _DM_UCLASS_INTERNAL_H +#define _DM_UCLASS_INTERNAL_H + +#include + +/* + * These next two macros DM_UCLASS_INST() and DM_UCLASS_REF() are only allowed + * in code generated by dtoc, because the ordering is important and if other + * instances creep in then they may mess up the ordering expected by dtoc. + * + * It is OK to use them with 'extern' though, since that does not actually + * add a new record to the linker_list. + */ + +/** + * DM_UCLASS_INST() - Declare a uclass ready for run-time use + * + * This adds an actual struct uclass to a list which is found by driver model + * on start-up. + * + * For example: + * + * DM_UCLASS_INST(clk) = { + * .uc_drv = DM_UCLASS_DRIVER_REF(clk), + * ... + * }; + * + * @_name: Name of the uclass. This must be a valid C identifier, used by the + * linker_list. + */ +#define DM_UCLASS_INST(_name) \ + ll_entry_declare(struct uclass, _name, uclass) + +/** + * DM_UCLASS_REF() - Get a reference to a uclass + * + * This is useful for referencing a uclass at build time. Before this is used, + * an extern DM_UCLASS_INST() must have been declared. + * + * For example: + * + * extern DM_UCLASS_INST(clk); + * + * struct uclass *ucs[] = { + * DM_UCLASS_REF(clk), + * } + * + * @_name: Name of the uclass. This must be a valid C identifier, used by the + * linker_list + * @returns struct uclass * for the device + */ +#define DM_UCLASS_REF(_name) \ + ll_entry_ref(struct uclass, _name, uclass) + +/** + * uclass_set_priv() - Set the private data for a uclass + * + * This is normally handled by driver model, which automatically allocates + * private data when an 'auto' size if provided by the uclass driver. + * + * Use this function to override normal operation for special situations, such + * as needing to allocate a variable amount of data. + * + * If OF_PLATDATA_RT is enabled, this function cannot be used out of core driver + * model code, since the pointer must be within the gd->dm_priv_base region. + * + * @uc Uclass to update + * @priv New private-data pointer + */ +void uclass_set_priv(struct uclass *uc, void *priv); + +/** + * uclass_find_next_free_seq() - Get the next free sequence number + * + * This returns the next free sequence number. This is useful only if + * OF_CONTROL is not used. The next free sequence number is simply the + * maximum sequence number used by all devices in the uclass + 1. The value + * returned is always greater than the largest alias, if DM_SEQ_ALIAS is enabled + * and the uclass has the DM_UC_FLAG_SEQ_ALIAS flag. + * + * This allows assigning the sequence number in the binding order. + * + * @uc: uclass to check + * @return The next free sequence number + */ +int uclass_find_next_free_seq(struct uclass *uc); + +/** + * uclass_get_device_tail() - handle the end of a get_device call + * + * This handles returning an error or probing a device as needed. + * + * @dev: Device that needs to be probed + * @ret: Error to return. If non-zero then the device is not probed + * @devp: Returns the value of 'dev' if there is no error + * @return ret, if non-zero, else the result of the device_probe() call + */ +int uclass_get_device_tail(struct udevice *dev, int ret, struct udevice **devp); + +/** + * dev_get_uclass_index() - Get uclass and index of device + * @dev: - in - Device that we want the uclass/index of + * @ucp: - out - A pointer to the uclass the device belongs to + * + * The device is not prepared for use - this is an internal function. + * + * @return the index of the device in the uclass list or -ENODEV if not found. + */ +int dev_get_uclass_index(struct udevice *dev, struct uclass **ucp); + +/** + * uclass_find_device() - Return n-th child of uclass + * @id: Id number of the uclass + * @index: Position of the child in uclass's list + * #devp: Returns pointer to device, or NULL on error + * + * The device is not prepared for use - this is an internal function. + * The function uclass_get_device_tail() can be used to probe the device. + * + * @return the uclass pointer of a child at the given index or + * return NULL on error. + */ +int uclass_find_device(enum uclass_id id, int index, struct udevice **devp); + +/** + * uclass_find_first_device() - Return the first device in a uclass + * @id: Id number of the uclass + * #devp: Returns pointer to device, or NULL on error + * + * The device is not prepared for use - this is an internal function. + * The function uclass_get_device_tail() can be used to probe the device. + * + * @return 0 if OK (found or not found), -ve on error + */ +int uclass_find_first_device(enum uclass_id id, struct udevice **devp); + +/** + * uclass_find_next_device() - Return the next device in a uclass + * @devp: On entry, pointer to device to lookup. On exit, returns pointer + * to the next device in the same uclass, or NULL if none + * + * The device is not prepared for use - this is an internal function. + * The function uclass_get_device_tail() can be used to probe the device. + * + * @return 0 if OK (found or not found), -ve on error + */ +int uclass_find_next_device(struct udevice **devp); + +/** + * uclass_find_device_by_name() - Find uclass device based on ID and name + * + * This searches for a device with the exactly given name. + * + * The device is NOT probed, it is merely returned. + * + * @id: ID to look up + * @name: name of a device to find + * @devp: Returns pointer to device (the first one with the name) + * @return 0 if OK, -ve on error + */ +int uclass_find_device_by_name(enum uclass_id id, const char *name, + struct udevice **devp); + +/** + * uclass_find_device_by_seq() - Find uclass device based on ID and sequence + * + * This searches for a device with the given seq. + * + * The device is NOT probed, it is merely returned. + * + * @id: ID to look up + * @seq: Sequence number to find (0=first) + * @devp: Returns pointer to device (there is only one per for each seq) + * @return 0 if OK, -ENODEV if not found + */ +int uclass_find_device_by_seq(enum uclass_id id, int seq, + struct udevice **devp); + +/** + * uclass_find_device_by_of_offset() - Find a uclass device by device tree node + * + * This searches the devices in the uclass for one attached to the given + * device tree node. + * + * The device is NOT probed, it is merely returned. + * + * @id: ID to look up + * @node: Device tree offset to search for (if -ve then -ENODEV is returned) + * @devp: Returns pointer to device (there is only one for each node) + * @return 0 if OK, -ve on error + */ +int uclass_find_device_by_of_offset(enum uclass_id id, int node, + struct udevice **devp); + +/** + * uclass_find_device_by_of_node() - Find a uclass device by device tree node + * + * This searches the devices in the uclass for one attached to the given + * device tree node. + * + * The device is NOT probed, it is merely returned. + * + * @id: ID to look up + * @node: Device tree offset to search for (if NULL then -ENODEV is returned) + * @devp: Returns pointer to device (there is only one for each node) + * @return 0 if OK, -ve on error + */ +int uclass_find_device_by_ofnode(enum uclass_id id, ofnode node, + struct udevice **devp); + +/** + * uclass_find_device_by_phandle() - Find a uclass device by phandle + * + * This searches the devices in the uclass for one with the given phandle. + * + * The device is NOT probed, it is merely returned. + * + * @id: ID to look up + * @parent: Parent device containing the phandle pointer + * @name: Name of property in the parent device node + * @devp: Returns pointer to device (there is only one for each node) + * @return 0 if OK, -ENOENT if there is no @name present in the node, other + * -ve on error + */ +int uclass_find_device_by_phandle(enum uclass_id id, struct udevice *parent, + const char *name, struct udevice **devp); + +/** + * uclass_bind_device() - Associate device with a uclass + * + * Connect the device into uclass's list of devices. + * + * @dev: Pointer to the device + * #return 0 on success, -ve on error + */ +int uclass_bind_device(struct udevice *dev); + +/** + * uclass_unbind_device() - Deassociate device with a uclass + * + * Disconnect the device from uclass's list of devices. + * + * @dev: Pointer to the device + * #return 0 on success, -ve on error + */ +#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE) +int uclass_unbind_device(struct udevice *dev); +#else +static inline int uclass_unbind_device(struct udevice *dev) { return 0; } +#endif + +/** + * uclass_pre_probe_device() - Deal with a device that is about to be probed + * + * Perform any pre-processing that is needed by the uclass before it can be + * probed. This includes the uclass' pre-probe() method and the parent + * uclass' child_pre_probe() method. + * + * @dev: Pointer to the device + * #return 0 on success, -ve on error + */ +int uclass_pre_probe_device(struct udevice *dev); + +/** + * uclass_post_probe_device() - Deal with a device that has just been probed + * + * Perform any post-processing of a probed device that is needed by the + * uclass. + * + * @dev: Pointer to the device + * #return 0 on success, -ve on error + */ +int uclass_post_probe_device(struct udevice *dev); + +/** + * uclass_pre_remove_device() - Handle a device which is about to be removed + * + * Perform any pre-processing of a device that is about to be removed. + * + * @dev: Pointer to the device + * #return 0 on success, -ve on error + */ +#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE) +int uclass_pre_remove_device(struct udevice *dev); +#else +static inline int uclass_pre_remove_device(struct udevice *dev) { return 0; } +#endif + +/** + * uclass_find() - Find uclass by its id + * + * @id: Id to serach for + * @return pointer to uclass, or NULL if not found + */ +struct uclass *uclass_find(enum uclass_id key); + +/** + * uclass_destroy() - Destroy a uclass + * + * Destroy a uclass and all its devices + * + * @uc: uclass to destroy + * @return 0 on success, -ve on error + */ +int uclass_destroy(struct uclass *uc); + +#endif diff --git a/roms/u-boot/include/dm/uclass.h b/roms/u-boot/include/dm/uclass.h new file mode 100644 index 000000000..6752d8ee0 --- /dev/null +++ b/roms/u-boot/include/dm/uclass.h @@ -0,0 +1,482 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2013 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann + */ + +#ifndef _DM_UCLASS_H +#define _DM_UCLASS_H + +#include +#include +#include +#include + +/** + * struct uclass - a U-Boot drive class, collecting together similar drivers + * + * A uclass provides an interface to a particular function, which is + * implemented by one or more drivers. Every driver belongs to a uclass even + * if it is the only driver in that uclass. An example uclass is GPIO, which + * provides the ability to change read inputs, set and clear outputs, etc. + * There may be drivers for on-chip SoC GPIO banks, I2C GPIO expanders and + * PMIC IO lines, all made available in a unified way through the uclass. + * + * @priv_: Private data for this uclass (do not access outside driver model) + * @uc_drv: The driver for the uclass itself, not to be confused with a + * 'struct driver' + * @dev_head: List of devices in this uclass (devices are attached to their + * uclass when their bind method is called) + * @sibling_node: Next uclass in the linked list of uclasses + */ +struct uclass { + void *priv_; + struct uclass_driver *uc_drv; + struct list_head dev_head; + struct list_head sibling_node; +}; + +struct driver; +struct udevice; + +/* Members of this uclass sequence themselves with aliases */ +#define DM_UC_FLAG_SEQ_ALIAS (1 << 0) + +/* Members of this uclass without aliases don't get a sequence number */ +#define DM_UC_FLAG_NO_AUTO_SEQ (1 << 1) + +/* Same as DM_FLAG_ALLOC_PRIV_DMA */ +#define DM_UC_FLAG_ALLOC_PRIV_DMA (1 << 5) + +/** + * struct uclass_driver - Driver for the uclass + * + * A uclass_driver provides a consistent interface to a set of related + * drivers. + * + * @name: Name of uclass driver + * @id: ID number of this uclass + * @post_bind: Called after a new device is bound to this uclass + * @pre_unbind: Called before a device is unbound from this uclass + * @pre_probe: Called before a new device is probed + * @post_probe: Called after a new device is probed + * @pre_remove: Called before a device is removed + * @child_post_bind: Called after a child is bound to a device in this uclass + * @child_pre_probe: Called before a child in this uclass is probed + * @child_post_probe: Called after a child in this uclass is probed + * @init: Called to set up the uclass + * @destroy: Called to destroy the uclass + * @priv_auto: If non-zero this is the size of the private data + * to be allocated in the uclass's ->priv pointer. If zero, then the uclass + * driver is responsible for allocating any data required. + * @per_device_auto: Each device can hold private data owned + * by the uclass. If required this will be automatically allocated if this + * value is non-zero. + * @per_device_plat_auto: Each device can hold platform data + * owned by the uclass as 'dev->uclass_plat'. If the value is non-zero, + * then this will be automatically allocated. + * @per_child_auto: Each child device (of a parent in this + * uclass) can hold parent data for the device/uclass. This value is only + * used as a fallback if this member is 0 in the driver. + * @per_child_plat_auto: A bus likes to store information about + * its children. If non-zero this is the size of this data, to be allocated + * in the child device's parent_plat pointer. This value is only used as + * a fallback if this member is 0 in the driver. + * @ops: Uclass operations, providing the consistent interface to devices + * within the uclass. + * @flags: Flags for this uclass (DM_UC_...) + */ +struct uclass_driver { + const char *name; + enum uclass_id id; + int (*post_bind)(struct udevice *dev); + int (*pre_unbind)(struct udevice *dev); + int (*pre_probe)(struct udevice *dev); + int (*post_probe)(struct udevice *dev); + int (*pre_remove)(struct udevice *dev); + int (*child_post_bind)(struct udevice *dev); + int (*child_pre_probe)(struct udevice *dev); + int (*child_post_probe)(struct udevice *dev); + int (*init)(struct uclass *class); + int (*destroy)(struct uclass *class); + int priv_auto; + int per_device_auto; + int per_device_plat_auto; + int per_child_auto; + int per_child_plat_auto; + const void *ops; + uint32_t flags; +}; + +/* Declare a new uclass_driver */ +#define UCLASS_DRIVER(__name) \ + ll_entry_declare(struct uclass_driver, __name, uclass_driver) + +/* + * These two macros DM_UCLASS_DRIVER_REF and DM_UCLASS_DRIVER_REF are only + * allowed in code generated by dtoc, because the ordering is important and if + * other instances creep in then they may mess up the ordering expected by dtoc. + * + * It is OK to use them with 'extern' though, since that does not actually + * add a new record to the linker_list. + */ + +/** + * DM_UCLASS_DRIVER_REF() - Get a reference to a uclass driver + * + * This is useful in data structures and code for referencing a uclass_driver at + * build time. Before this is used, an extern UCLASS_DRIVER() must have been + * declared. + * + * For example: + * + * extern UCLASS_DRIVER(clk); + * + * struct uclass_driver *drvs[] = { + * DM_UCLASS_DRIVER_REF(clk), + * }; + * + * @_name: Name of the uclass_driver. This must be a valid C identifier, used by + * the linker_list. + * @returns struct uclass_driver * for the uclass driver + */ +#define DM_UCLASS_DRIVER_REF(_name) \ + ll_entry_ref(struct uclass_driver, _name, uclass_driver) + +/** + * uclass_get_priv() - Get the private data for a uclass + * + * @uc Uclass to check + * @return private data, or NULL if none + */ +void *uclass_get_priv(const struct uclass *uc); + +/** + * uclass_get() - Get a uclass based on an ID, creating it if needed + * + * Every uclass is identified by an ID, a number from 0 to n-1 where n is + * the number of uclasses. This function allows looking up a uclass by its + * ID. + * + * @key: ID to look up + * @ucp: Returns pointer to uclass (there is only one per ID) + * @return 0 if OK, -ve on error + */ +int uclass_get(enum uclass_id key, struct uclass **ucp); + +/** + * uclass_get_name() - Get the name of a uclass driver + * + * @id: ID to look up + * @returns the name of the uclass driver for that ID, or NULL if none + */ +const char *uclass_get_name(enum uclass_id id); + +/** + * uclass_get_by_name() - Look up a uclass by its driver name + * + * @name: Name to look up + * @returns the associated uclass ID, or UCLASS_INVALID if not found + */ +enum uclass_id uclass_get_by_name(const char *name); + +/** + * uclass_get_device() - Get a uclass device based on an ID and index + * + * The device is probed to activate it ready for use. + * + * @id: ID to look up + * @index: Device number within that uclass (0=first) + * @devp: Returns pointer to device (there is only one per for each ID) + * @return 0 if OK, -ve on error + */ +int uclass_get_device(enum uclass_id id, int index, struct udevice **devp); + +/** + * uclass_get_device_by_name() - Get a uclass device by its name + * + * This searches the devices in the uclass for one with the exactly given name. + * + * The device is probed to activate it ready for use. + * + * @id: ID to look up + * @name: name of a device to get + * @devp: Returns pointer to device (the first one with the name) + * @return 0 if OK, -ve on error + */ +int uclass_get_device_by_name(enum uclass_id id, const char *name, + struct udevice **devp); + +/** + * uclass_get_device_by_seq() - Get a uclass device based on an ID and sequence + * + * If an active device has this sequence it will be returned. If there is no + * such device then this will check for a device that is requesting this + * sequence. + * + * The device is probed to activate it ready for use. + * + * @id: ID to look up + * @seq: Sequence number to find (0=first) + * @devp: Returns pointer to device (there is only one for each seq) + * @return 0 if OK, -ve on error + */ +int uclass_get_device_by_seq(enum uclass_id id, int seq, struct udevice **devp); + +/** + * uclass_get_device_by_of_offset() - Get a uclass device by device tree node + * + * This searches the devices in the uclass for one attached to the given + * device tree node. + * + * The device is probed to activate it ready for use. + * + * @id: ID to look up + * @node: Device tree offset to search for (if -ve then -ENODEV is returned) + * @devp: Returns pointer to device (there is only one for each node) + * @return 0 if OK, -ve on error + */ +int uclass_get_device_by_of_offset(enum uclass_id id, int node, + struct udevice **devp); + +/** + * uclass_get_device_by_ofnode() - Get a uclass device by device tree node + * + * This searches the devices in the uclass for one attached to the given + * device tree node. + * + * The device is probed to activate it ready for use. + * + * @id: ID to look up + * @np: Device tree node to search for (if NULL then -ENODEV is returned) + * @devp: Returns pointer to device (there is only one for each node) + * @return 0 if OK, -ve on error + */ +int uclass_get_device_by_ofnode(enum uclass_id id, ofnode node, + struct udevice **devp); + +/** + * uclass_get_device_by_phandle_id() - Get a uclass device by phandle id + * + * This searches the devices in the uclass for one with the given phandle id. + * + * The device is probed to activate it ready for use. + * + * @id: uclass ID to look up + * @phandle_id: the phandle id to look up + * @devp: Returns pointer to device (there is only one for each node). NULL if + * there is no such device. + * @return 0 if OK, -ENODEV if there is no device match the phandle, other + * -ve on error + */ +int uclass_get_device_by_phandle_id(enum uclass_id id, uint phandle_id, + struct udevice **devp); + +/** + * uclass_get_device_by_phandle() - Get a uclass device by phandle + * + * This searches the devices in the uclass for one with the given phandle. + * + * The device is probed to activate it ready for use. + * + * @id: uclass ID to look up + * @parent: Parent device containing the phandle pointer + * @name: Name of property in the parent device node + * @devp: Returns pointer to device (there is only one for each node) + * @return 0 if OK, -ENOENT if there is no @name present in the node, other + * -ve on error + */ +int uclass_get_device_by_phandle(enum uclass_id id, struct udevice *parent, + const char *name, struct udevice **devp); + +/** + * uclass_get_device_by_driver() - Get a uclass device for a driver + * + * This searches the devices in the uclass for one that uses the given + * driver. Use DM_DRIVER_GET(name) for the @drv argument, where 'name' is + * the driver name - as used in U_BOOT_DRIVER(name). + * + * The device is probed to activate it ready for use. + * + * @id: ID to look up + * @drv: Driver to look for + * @devp: Returns pointer to the first device with that driver + * @return 0 if OK, -ve on error + */ +int uclass_get_device_by_driver(enum uclass_id id, const struct driver *drv, + struct udevice **devp); + +/** + * uclass_first_device() - Get the first device in a uclass + * + * The device returned is probed if necessary, and ready for use + * + * This function is useful to start iterating through a list of devices which + * are functioning correctly and can be probed. + * + * @id: Uclass ID to look up + * @devp: Returns pointer to the first device in that uclass if no error + * occurred, or NULL if there is no first device, or an error occurred with + * that device. + * @return 0 if OK (found or not found), other -ve on error + */ +int uclass_first_device(enum uclass_id id, struct udevice **devp); + +/** + * uclass_first_device_err() - Get the first device in a uclass + * + * The device returned is probed if necessary, and ready for use + * + * @id: Uclass ID to look up + * @devp: Returns pointer to the first device in that uclass, or NULL if none + * @return 0 if found, -ENODEV if not found, other -ve on error + */ +int uclass_first_device_err(enum uclass_id id, struct udevice **devp); + +/** + * uclass_next_device() - Get the next device in a uclass + * + * The device returned is probed if necessary, and ready for use + * + * This function is useful to iterate through a list of devices which + * are functioning correctly and can be probed. + * + * @devp: On entry, pointer to device to lookup. On exit, returns pointer + * to the next device in the uclass if no error occurred, or NULL if there is + * no next device, or an error occurred with that next device. + * @return 0 if OK (found or not found), other -ve on error + */ +int uclass_next_device(struct udevice **devp); + +/** + * uclass_next_device_err() - Get the next device in a uclass + * + * The device returned is probed if necessary, and ready for use + * + * @devp: On entry, pointer to device to lookup. On exit, returns pointer + * to the next device in the uclass if no error occurred, or -ENODEV if + * there is no next device. + * @return 0 if found, -ENODEV if not found, other -ve on error + */ +int uclass_next_device_err(struct udevice **devp); + +/** + * uclass_first_device_check() - Get the first device in a uclass + * + * The device returned is probed if necessary, and ready for use + * + * This function is useful to start iterating through a list of devices which + * are functioning correctly and can be probed. + * + * @id: Uclass ID to look up + * @devp: Returns pointer to the first device in that uclass, or NULL if there + * is no first device + * @return 0 if OK (found or not found), other -ve on error. If an error occurs + * it is still possible to move to the next device. + */ +int uclass_first_device_check(enum uclass_id id, struct udevice **devp); + +/** + * uclass_next_device_check() - Get the next device in a uclass + * + * The device returned is probed if necessary, and ready for use + * + * This function is useful to start iterating through a list of devices which + * are functioning correctly and can be probed. + * + * @devp: On entry, pointer to device to lookup. On exit, returns pointer + * to the next device in the uclass if any + * @return 0 if OK (found or not found), other -ve on error. If an error occurs + * it is still possible to move to the next device. + */ +int uclass_next_device_check(struct udevice **devp); + +/** + * uclass_first_device_drvdata() - Find the first device with given driver data + * + * This searches through the devices for a particular uclass looking for one + * that has the given driver data. + * + * @id: Uclass ID to check + * @driver_data: Driver data to search for + * @devp: Returns pointer to the first matching device in that uclass, if found + * @return 0 if found, -ENODEV if not found, other -ve on error + */ +int uclass_first_device_drvdata(enum uclass_id id, ulong driver_data, + struct udevice **devp); + +/** + * uclass_probe_all() - Probe all devices based on an uclass ID + * + * This function probes all devices associated with a uclass by + * looking for its ID. + * + * @id: uclass ID to look up + * @return 0 if OK, other -ve on error + */ +int uclass_probe_all(enum uclass_id id); + +/** + * uclass_id_foreach_dev() - Helper function to iteration through devices + * + * This creates a for() loop which works through the available devices in + * a uclass ID in order from start to end. + * + * If for some reason the uclass cannot be found, this does nothing. + * + * @id: enum uclass_id ID to use + * @pos: struct udevice * to hold the current device. Set to NULL when there + * are no more devices. + * @uc: temporary uclass variable (struct uclass *) + */ +#define uclass_id_foreach_dev(id, pos, uc) \ + if (!uclass_get(id, &uc)) \ + list_for_each_entry(pos, &uc->dev_head, uclass_node) + +/** + * uclass_foreach_dev() - Helper function to iteration through devices + * + * This creates a for() loop which works through the available devices in + * a uclass in order from start to end. + * + * @pos: struct udevice * to hold the current device. Set to NULL when there + * are no more devices. + * @uc: uclass to scan + */ +#define uclass_foreach_dev(pos, uc) \ + list_for_each_entry(pos, &uc->dev_head, uclass_node) + +/** + * uclass_foreach_dev_safe() - Helper function to safely iteration through devs + * + * This creates a for() loop which works through the available devices in + * a uclass in order from start to end. Inside the loop, it is safe to remove + * @pos if required. + * + * @pos: struct udevice * to hold the current device. Set to NULL when there + * are no more devices. + * @next: struct udevice * to hold the next next + * @uc: uclass to scan + */ +#define uclass_foreach_dev_safe(pos, next, uc) \ + list_for_each_entry_safe(pos, next, &uc->dev_head, uclass_node) + +/** + * uclass_foreach_dev_probe() - Helper function to iteration through devices + * of given uclass + * + * This creates a for() loop which works through the available devices in + * a uclass in order from start to end. Devices are probed if necessary, + * and ready for use. + * + * @id: Uclass ID + * @dev: struct udevice * to hold the current device. Set to NULL when there + * are no more devices. + */ +#define uclass_foreach_dev_probe(id, dev) \ + for (int _ret = uclass_first_device_err(id, &dev); !_ret && dev; \ + _ret = uclass_next_device_err(&dev)) + +#endif diff --git a/roms/u-boot/include/dm/util.h b/roms/u-boot/include/dm/util.h new file mode 100644 index 000000000..138893c93 --- /dev/null +++ b/roms/u-boot/include/dm/util.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2013 Google, Inc + */ + +#ifndef __DM_UTIL_H +#define __DM_UTIL_H + +#if CONFIG_IS_ENABLED(DM_WARN) +void dm_warn(const char *fmt, ...); +#else +static inline void dm_warn(const char *fmt, ...) +{ +} +#endif + +struct list_head; + +/** + * list_count_items() - Count number of items in a list + * + * @param head: Head of list + * @return number of items, or 0 if empty + */ +int list_count_items(struct list_head *head); + +/* Dump out a tree of all devices */ +void dm_dump_all(void); + +/* Dump out a list of uclasses and their devices */ +void dm_dump_uclass(void); + +#ifdef CONFIG_DEBUG_DEVRES +/* Dump out a list of device resources */ +void dm_dump_devres(void); +#else +static inline void dm_dump_devres(void) +{ +} +#endif + +/* Dump out a list of drivers */ +void dm_dump_drivers(void); + +/* Dump out a list with each driver's compatibility strings */ +void dm_dump_driver_compat(void); + +/* Dump out a list of drivers with static platform data */ +void dm_dump_static_driver_info(void); + +#endif + +#if CONFIG_IS_ENABLED(OF_PLATDATA_INST) && CONFIG_IS_ENABLED(READ_ONLY) +void *dm_priv_to_rw(void *priv); +#else +static inline void *dm_priv_to_rw(void *priv) +{ + return priv; +} +#endif diff --git a/roms/u-boot/include/dm9000.h b/roms/u-boot/include/dm9000.h new file mode 100644 index 000000000..f780e513f --- /dev/null +++ b/roms/u-boot/include/dm9000.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * NOTE: DAVICOM DM9000 ethernet driver interface + * + * Authors: Remy Bohmer + */ +#ifndef __DM9000_H__ +#define __DM9000_H__ + +/****************** function prototypes **********************/ +#if !defined(CONFIG_DM9000_NO_SROM) +void dm9000_write_srom_word(int offset, u16 val); +void dm9000_read_srom_word(int offset, u8 *to); +#endif + +#endif /* __DM9000_H__ */ diff --git a/roms/u-boot/include/dma-uclass.h b/roms/u-boot/include/dma-uclass.h new file mode 100644 index 000000000..340437acc --- /dev/null +++ b/roms/u-boot/include/dma-uclass.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * Copyright (C) 2015 - 2018 Texas Instruments Incorporated + * Written by Mugunthan V N + * + */ + +#ifndef _DMA_UCLASS_H +#define _DMA_UCLASS_H + +/* See dma.h for background documentation. */ + +#include + +struct ofnode_phandle_args; + +/* + * struct dma_ops - Driver model DMA operations + * + * The uclass interface is implemented by all DMA devices which use + * driver model. + */ +struct dma_ops { +#ifdef CONFIG_DMA_CHANNELS + /** + * of_xlate - Translate a client's device-tree (OF) DMA specifier. + * + * The DMA core calls this function as the first step in implementing + * a client's dma_get_by_*() call. + * + * If this function pointer is set to NULL, the DMA core will use a + * default implementation, which assumes #dma-cells = <1>, and that + * the DT cell contains a simple integer DMA Channel. + * + * At present, the DMA API solely supports device-tree. If this + * changes, other xxx_xlate() functions may be added to support those + * other mechanisms. + * + * @dma: The dma struct to hold the translation result. + * @args: The dma specifier values from device tree. + * @return 0 if OK, or a negative error code. + */ + int (*of_xlate)(struct dma *dma, + struct ofnode_phandle_args *args); + /** + * request - Request a translated DMA. + * + * The DMA core calls this function as the second step in + * implementing a client's dma_get_by_*() call, following a successful + * xxx_xlate() call, or as the only step in implementing a client's + * dma_request() call. + * + * @dma: The DMA struct to request; this has been filled in by + * a previoux xxx_xlate() function call, or by the caller of + * dma_request(). + * @return 0 if OK, or a negative error code. + */ + int (*request)(struct dma *dma); + /** + * rfree - Free a previously requested dma. + * + * This is the implementation of the client dma_free() API. + * + * @dma: The DMA to free. + * @return 0 if OK, or a negative error code. + */ + int (*rfree)(struct dma *dma); + /** + * enable() - Enable a DMA Channel. + * + * @dma: The DMA Channel to manipulate. + * @return zero on success, or -ve error code. + */ + int (*enable)(struct dma *dma); + /** + * disable() - Disable a DMA Channel. + * + * @dma: The DMA Channel to manipulate. + * @return zero on success, or -ve error code. + */ + int (*disable)(struct dma *dma); + /** + * prepare_rcv_buf() - Prepare/Add receive DMA buffer. + * + * @dma: The DMA Channel to manipulate. + * @dst: The receive buffer pointer. + * @size: The receive buffer size + * @return zero on success, or -ve error code. + */ + int (*prepare_rcv_buf)(struct dma *dma, void *dst, size_t size); + /** + * receive() - Receive a DMA transfer. + * + * @dma: The DMA Channel to manipulate. + * @dst: The destination pointer. + * @metadata: DMA driver's specific data + * @return zero on success, or -ve error code. + */ + int (*receive)(struct dma *dma, void **dst, void *metadata); + /** + * send() - Send a DMA transfer. + * + * @dma: The DMA Channel to manipulate. + * @src: The source pointer. + * @len: Length of the data to be sent (number of bytes). + * @metadata: DMA driver's specific data + * @return zero on success, or -ve error code. + */ + int (*send)(struct dma *dma, void *src, size_t len, void *metadata); + /** + * get_cfg() - Get DMA channel configuration for client's use + * + * @dma: The DMA Channel to manipulate + * @cfg_id: DMA provider specific ID to identify what + * configuration data client needs + * @data: Pointer to store pointer to DMA driver specific + * configuration data for the given cfg_id (output param) + * @return zero on success, or -ve error code. + */ + int (*get_cfg)(struct dma *dma, u32 cfg_id, void **data); +#endif /* CONFIG_DMA_CHANNELS */ + /** + * transfer() - Issue a DMA transfer. The implementation must + * wait until the transfer is done. + * + * @dev: The DMA device + * @direction: direction of data transfer (should be one from + * enum dma_direction) + * @dst: The destination pointer. + * @src: The source pointer. + * @len: Length of the data to be copied (number of bytes). + * @return zero on success, or -ve error code. + */ + int (*transfer)(struct udevice *dev, int direction, void *dst, + void *src, size_t len); +}; + +#endif /* _DMA_UCLASS_H */ diff --git a/roms/u-boot/include/dma.h b/roms/u-boot/include/dma.h new file mode 100644 index 000000000..a64580a61 --- /dev/null +++ b/roms/u-boot/include/dma.h @@ -0,0 +1,345 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * Copyright (C) 2015 - 2018 Texas Instruments Incorporated + * Written by Mugunthan V N + * + */ + +#ifndef _DMA_H_ +#define _DMA_H_ + +#include +#include +#include + +struct udevice; + +/* + * enum dma_direction - dma transfer direction indicator + * @DMA_MEM_TO_MEM: Memcpy mode + * @DMA_MEM_TO_DEV: From Memory to Device + * @DMA_DEV_TO_MEM: From Device to Memory + * @DMA_DEV_TO_DEV: From Device to Device + */ +enum dma_direction { + DMA_MEM_TO_MEM, + DMA_MEM_TO_DEV, + DMA_DEV_TO_MEM, + DMA_DEV_TO_DEV, +}; + +#define DMA_SUPPORTS_MEM_TO_MEM BIT(0) +#define DMA_SUPPORTS_MEM_TO_DEV BIT(1) +#define DMA_SUPPORTS_DEV_TO_MEM BIT(2) +#define DMA_SUPPORTS_DEV_TO_DEV BIT(3) + +/* + * struct dma_dev_priv - information about a device used by the uclass + * + * @supported: mode of transfers that DMA can support, should be + * one/multiple of DMA_SUPPORTS_* + */ +struct dma_dev_priv { + u32 supported; +}; + +#ifdef CONFIG_DMA_CHANNELS +/** + * A DMA is a feature of computer systems that allows certain hardware + * subsystems to access main system memory, independent of the CPU. + * DMA channels are typically generated externally to the HW module + * consuming them, by an entity this API calls a DMA provider. This API + * provides a standard means for drivers to enable and disable DMAs, and to + * copy, send and receive data using DMA. + * + * A driver that implements UCLASS_DMA is a DMA provider. A provider will + * often implement multiple separate DMAs, since the hardware it manages + * often has this capability. dma_uclass.h describes the interface which + * DMA providers must implement. + * + * DMA consumers/clients are the HW modules driven by the DMA channels. This + * header file describes the API used by drivers for those HW modules. + * + * DMA consumer DMA_MEM_TO_DEV (transmit) usage example (based on networking). + * Note. dma_send() is sync operation always - it'll start transfer and will + * poll for it to complete: + * - get/request dma channel + * struct dma dma_tx; + * ret = dma_get_by_name(common->dev, "tx0", &dma_tx); + * if (ret) ... + * + * - enable dma channel + * ret = dma_enable(&dma_tx); + * if (ret) ... + * + * - dma transmit DMA_MEM_TO_DEV. + * struct ti_drv_packet_data packet_data; + * + * packet_data.opt1 = val1; + * packet_data.opt2 = val2; + * ret = dma_send(&dma_tx, packet, length, &packet_data); + * if (ret) .. + * + * DMA consumer DMA_DEV_TO_MEM (receive) usage example (based on networking). + * Note. dma_receive() is sync operation always - it'll start transfer + * (if required) and will poll for it to complete (or for any previously + * configured dev2mem transfer to complete): + * - get/request dma channel + * struct dma dma_rx; + * ret = dma_get_by_name(common->dev, "rx0", &dma_rx); + * if (ret) ... + * + * - enable dma channel + * ret = dma_enable(&dma_rx); + * if (ret) ... + * + * - dma receive DMA_DEV_TO_MEM. + * struct ti_drv_packet_data packet_data; + * + * len = dma_receive(&dma_rx, (void **)packet, &packet_data); + * if (ret < 0) ... + * + * DMA consumer DMA_DEV_TO_MEM (receive) zero-copy usage example (based on + * networking). Networking subsystem allows to configure and use few receive + * buffers (dev2mem), as Networking RX DMA channels usually implemented + * as streaming interface + * - get/request dma channel + * struct dma dma_rx; + * ret = dma_get_by_name(common->dev, "rx0", &dma_rx); + * if (ret) ... + * + * for (i = 0; i < RX_DESC_NUM; i++) { + * ret = dma_prepare_rcv_buf(&dma_rx, + * net_rx_packets[i], + * RX_BUF_SIZE); + * if (ret) ... + * } + * + * - enable dma channel + * ret = dma_enable(&dma_rx); + * if (ret) ... + * + * - dma receive DMA_DEV_TO_MEM. + * struct ti_drv_packet_data packet_data; + * + * len = dma_receive(&dma_rx, (void **)packet, &packet_data); + * if (ret < 0) .. + * + * -- process packet -- + * + * - return buffer back to DAM channel + * ret = dma_prepare_rcv_buf(&dma_rx, + * net_rx_packets[rx_next], + * RX_BUF_SIZE); + */ + +struct udevice; + +/** + * struct dma - A handle to (allowing control of) a single DMA. + * + * Clients provide storage for DMA handles. The content of the structure is + * managed solely by the DMA API and DMA drivers. A DMA struct is + * initialized by "get"ing the DMA struct. The DMA struct is passed to all + * other DMA APIs to identify which DMA channel to operate upon. + * + * @dev: The device which implements the DMA channel. + * @id: The DMA channel ID within the provider. + * + * Currently, the DMA API assumes that a single integer ID is enough to + * identify and configure any DMA channel for any DMA provider. If this + * assumption becomes invalid in the future, the struct could be expanded to + * either (a) add more fields to allow DMA providers to store additional + * information, or (b) replace the id field with an opaque pointer, which the + * provider would dynamically allocated during its .of_xlate op, and process + * during is .request op. This may require the addition of an extra op to clean + * up the allocation. + */ +struct dma { + struct udevice *dev; + /* + * Written by of_xlate. We assume a single id is enough for now. In the + * future, we might add more fields here. + */ + unsigned long id; +}; + +# if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DMA) +/** + * dma_get_by_index - Get/request a DMA by integer index. + * + * This looks up and requests a DMA. The index is relative to the client + * device; each device is assumed to have n DMAs associated with it somehow, + * and this function finds and requests one of them. The mapping of client + * device DMA indices to provider DMAs may be via device-tree properties, + * board-provided mapping tables, or some other mechanism. + * + * @dev: The client device. + * @index: The index of the DMA to request, within the client's list of + * DMA channels. + * @dma: A pointer to a DMA struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int dma_get_by_index(struct udevice *dev, int index, struct dma *dma); + +/** + * dma_get_by_name - Get/request a DMA by name. + * + * This looks up and requests a DMA. The name is relative to the client + * device; each device is assumed to have n DMAs associated with it somehow, + * and this function finds and requests one of them. The mapping of client + * device DMA names to provider DMAs may be via device-tree properties, + * board-provided mapping tables, or some other mechanism. + * + * @dev: The client device. + * @name: The name of the DMA to request, within the client's list of + * DMA channels. + * @dma: A pointer to a DMA struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int dma_get_by_name(struct udevice *dev, const char *name, struct dma *dma); +# else +static inline int dma_get_by_index(struct udevice *dev, int index, + struct dma *dma) +{ + return -ENOSYS; +} + +static inline int dma_get_by_name(struct udevice *dev, const char *name, + struct dma *dma) +{ + return -ENOSYS; +} +# endif + +/** + * dma_request - Request a DMA by provider-specific ID. + * + * This requests a DMA using a provider-specific ID. Generally, this function + * should not be used, since dma_get_by_index/name() provide an interface that + * better separates clients from intimate knowledge of DMA providers. + * However, this function may be useful in core SoC-specific code. + * + * @dev: The DMA provider device. + * @dma: A pointer to a DMA struct to initialize. The caller must + * have already initialized any field in this struct which the + * DMA provider uses to identify the DMA channel. + * @return 0 if OK, or a negative error code. + */ +int dma_request(struct udevice *dev, struct dma *dma); + +/** + * dma_free - Free a previously requested DMA. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @return 0 if OK, or a negative error code. + */ +int dma_free(struct dma *dma); + +/** + * dma_enable() - Enable (turn on) a DMA channel. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @return zero on success, or -ve error code. + */ +int dma_enable(struct dma *dma); + +/** + * dma_disable() - Disable (turn off) a DMA channel. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @return zero on success, or -ve error code. + */ +int dma_disable(struct dma *dma); + +/** + * dma_prepare_rcv_buf() - Prepare/add receive DMA buffer. + * + * It allows to implement zero-copy async DMA_DEV_TO_MEM (receive) transactions + * if supported by DMA providers. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @dst: The receive buffer pointer. + * @size: The receive buffer size + * @return zero on success, or -ve error code. + */ +int dma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size); + +/** + * dma_receive() - Receive a DMA transfer. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @dst: The destination pointer. + * @metadata: DMA driver's channel specific data + * @return length of received data on success, or zero - no data, + * or -ve error code. + */ +int dma_receive(struct dma *dma, void **dst, void *metadata); + +/** + * dma_send() - Send a DMA transfer. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @src: The source pointer. + * @len: Length of the data to be sent (number of bytes). + * @metadata: DMA driver's channel specific data + * @return zero on success, or -ve error code. + */ +int dma_send(struct dma *dma, void *src, size_t len, void *metadata); + +/** + * dma_get_cfg() - Get DMA channel configuration for client's use + * + * @dma: The DMA Channel to manipulate + * @cfg_id: DMA provider specific ID to identify what + * configuration data client needs + * @cfg_data: Pointer to store pointer to DMA driver specific + * configuration data for the given cfg_id (output param) + * @return zero on success, or -ve error code. + */ +int dma_get_cfg(struct dma *dma, u32 cfg_id, void **cfg_data); +#endif /* CONFIG_DMA_CHANNELS */ + +#if CONFIG_IS_ENABLED(DMA) +/* + * dma_get_device - get a DMA device which supports transfer + * type of transfer_type + * + * @transfer_type - transfer type should be one/multiple of + * DMA_SUPPORTS_* + * @devp - udevice pointer to return the found device + * @return - will return on success and devp will hold the + * pointer to the device + */ +int dma_get_device(u32 transfer_type, struct udevice **devp); + +/* + * dma_memcpy - try to use DMA to do a mem copy which will be + * much faster than CPU mem copy + * + * @dst - destination pointer + * @src - souce pointer + * @len - data length to be copied + * @return - on successful transfer returns no of bytes + transferred and on failure return error code. + */ +int dma_memcpy(void *dst, void *src, size_t len); +#else +static inline int dma_get_device(u32 transfer_type, struct udevice **devp) +{ + return -ENOSYS; +} + +static inline int dma_memcpy(void *dst, void *src, size_t len) +{ + return -ENOSYS; +} +#endif /* CONFIG_DMA */ +#endif /* _DMA_H_ */ diff --git a/roms/u-boot/include/dp83848.h b/roms/u-boot/include/dp83848.h new file mode 100644 index 000000000..f1bc3d86f --- /dev/null +++ b/roms/u-boot/include/dp83848.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * DP83848 ethernet Physical layer + * + * Copyright (C) 2007 Sergey Kubushyn + * + */ + + +/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */ + +#define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */ +#define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */ +#define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */ +#define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */ +#define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */ +#define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */ +#define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */ +#define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */ +#define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */ +#define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */ + +/*--Bit definitions: DP83848_CTL_REG */ +#define DP83848_RESET (1 << 15) /* 1= S/W Reset */ +#define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */ +#define DP83848_SPEED_SELECT (1 << 13) +#define DP83848_AUTONEG (1 << 12) +#define DP83848_POWER_DOWN (1 << 11) +#define DP83848_ISOLATE (1 << 10) +#define DP83848_RESTART_AUTONEG (1 << 9) +#define DP83848_DUPLEX_MODE (1 << 8) +#define DP83848_COLLISION_TEST (1 << 7) + +/*--Bit definitions: DP83848_STAT_REG */ +#define DP83848_100BASE_T4 (1 << 15) +#define DP83848_100BASE_TX_FD (1 << 14) +#define DP83848_100BASE_TX_HD (1 << 13) +#define DP83848_10BASE_T_FD (1 << 12) +#define DP83848_10BASE_T_HD (1 << 11) +#define DP83848_MF_PREAMB_SUPPR (1 << 6) +#define DP83848_AUTONEG_COMP (1 << 5) +#define DP83848_RMT_FAULT (1 << 4) +#define DP83848_AUTONEG_ABILITY (1 << 3) +#define DP83848_LINK_STATUS (1 << 2) +#define DP83848_JABBER_DETECT (1 << 1) +#define DP83848_EXTEND_CAPAB (1 << 0) + +/*--definitions: DP83848_PHYID1 */ +#define DP83848_PHYID1_OUI 0x2000 +#define DP83848_PHYID2_OUI 0x5c90 + +/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */ +#define DP83848_NP (1 << 15) +#define DP83848_ACK (1 << 14) +#define DP83848_RF (1 << 13) +#define DP83848_PAUSE (1 << 10) +#define DP83848_T4 (1 << 9) +#define DP83848_TX_FDX (1 << 8) +#define DP83848_TX_HDX (1 << 7) +#define DP83848_10_FDX (1 << 6) +#define DP83848_10_HDX (1 << 5) +#define DP83848_AN_IEEE_802_3 0x0001 + +/*--Bit definitions: DP83848_ANER */ +#define DP83848_PDF (1 << 4) +#define DP83848_LP_NP_ABLE (1 << 3) +#define DP83848_NP_ABLE (1 << 2) +#define DP83848_PAGE_RX (1 << 1) +#define DP83848_LP_AN_ABLE (1 << 0) + +/*--Bit definitions: DP83848_PHY_STAT */ +#define DP83848_RX_ERR_LATCH (1 << 13) +#define DP83848_POLARITY_STAT (1 << 12) +#define DP83848_FALSE_CAR_SENSE (1 << 11) +#define DP83848_SIG_DETECT (1 << 10) +#define DP83848_DESCRAM_LOCK (1 << 9) +#define DP83848_PAGE_RCV (1 << 8) +#define DP83848_PHY_RMT_FAULT (1 << 6) +#define DP83848_JABBER (1 << 5) +#define DP83848_AUTONEG_COMPLETE (1 << 4) +#define DP83848_LOOPBACK_STAT (1 << 3) +#define DP83848_DUPLEX (1 << 2) +#define DP83848_SPEED (1 << 1) +#define DP83848_LINK (1 << 0) diff --git a/roms/u-boot/include/ds1722.h b/roms/u-boot/include/ds1722.h new file mode 100644 index 000000000..e115696ce --- /dev/null +++ b/roms/u-boot/include/ds1722.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _DS1722_H_ +#define _DS1722_H_ + +#define DS1722_RESOLUTION_8BIT 0x0 +#define DS1722_RESOLUTION_9BIT 0x1 +#define DS1722_RESOLUTION_10BIT 0x2 +#define DS1722_RESOLUTION_11BIT 0x3 +#define DS1722_RESOLUTION_12BIT 0x4 + +int ds1722_probe(int dev); + +#endif /* _DS1722_H_ */ diff --git a/roms/u-boot/include/dsi_host.h b/roms/u-boot/include/dsi_host.h new file mode 100644 index 000000000..9dfc7b368 --- /dev/null +++ b/roms/u-boot/include/dsi_host.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 STMicroelectronics - All Rights Reserved + * Author(s): Yannick Fertre for STMicroelectronics. + * + */ + +#ifndef _DSI_HOST_H +#define _DSI_HOST_H + +#include + +struct dsi_host_ops { + /** + * init() - initialized the dsi_host + * + * @dev: dsi host device + * @device: DSI peripheral device + * @timing: Display timings + * @max_data_lanes: maximum number of data lines + * @phy_ops: set of function pointers for performing physical operations + * @return 0 if OK, -ve on error + */ + int (*init)(struct udevice *dev, + struct mipi_dsi_device *device, + struct display_timing *timings, + unsigned int max_data_lanes, + const struct mipi_dsi_phy_ops *phy_ops); + + /** + * enable() - Enable the dsi_host + * + * @dev: dsi host device + * @return 0 if OK, -ve on error + */ + int (*enable)(struct udevice *dev); + + /** + * disable() - Disable the dsi_host + * + * @dev: dsi host device + * @return 0 if OK, -ve on error + */ + int (*disable)(struct udevice *dev); +}; + +#define dsi_host_get_ops(dev) ((struct dsi_host_ops *)(dev)->driver->ops) + +/** + * dsi_host_init + * + * @dev: dsi host device + * @device: DSI peripheral device + * @timing: Display timings + * @max_data_lanes: maximum number of data lines + * @phy_ops: set of function pointers for performing physical operations + * @return 0 if OK, -ve on error + */ +int dsi_host_init(struct udevice *dev, + struct mipi_dsi_device *device, + struct display_timing *timings, + unsigned int max_data_lanes, + const struct mipi_dsi_phy_ops *phy_ops); + +/** + * dsi_host_enable + * + * @dev: dsi host device + * @return 0 if OK, -ve on error + */ +int dsi_host_enable(struct udevice *dev); + +#endif diff --git a/roms/u-boot/include/dt-bindings/arm/ux500_pm_domains.h b/roms/u-boot/include/dt-bindings/arm/ux500_pm_domains.h new file mode 100644 index 000000000..9bd764f0c --- /dev/null +++ b/roms/u-boot/include/dt-bindings/arm/ux500_pm_domains.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2014 Linaro Ltd. + * + * Author: Ulf Hansson + */ +#ifndef _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H +#define _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H + +#define DOMAIN_VAPE 0 + +/* Number of PM domains. */ +#define NR_DOMAINS (DOMAIN_VAPE + 1) + +#endif diff --git a/roms/u-boot/include/dt-bindings/bus/ti-sysc.h b/roms/u-boot/include/dt-bindings/bus/ti-sysc.h new file mode 100644 index 000000000..eae427454 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/bus/ti-sysc.h @@ -0,0 +1,28 @@ +/* TI sysc interconnect target module defines */ + +/* Generic sysc found on omap2 and later, also known as type1 */ +#define SYSC_OMAP2_CLOCKACTIVITY (3 << 8) +#define SYSC_OMAP2_EMUFREE (1 << 5) +#define SYSC_OMAP2_ENAWAKEUP (1 << 2) +#define SYSC_OMAP2_SOFTRESET (1 << 1) +#define SYSC_OMAP2_AUTOIDLE (1 << 0) + +/* Generic sysc found on omap4 and later, also known as type2 */ +#define SYSC_OMAP4_DMADISABLE (1 << 16) +#define SYSC_OMAP4_FREEEMU (1 << 1) /* Also known as EMUFREE */ +#define SYSC_OMAP4_SOFTRESET (1 << 0) + +/* SmartReflex sysc found on 36xx and later */ +#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26) + +#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4) + +/* PRUSS sysc found on AM33xx/AM43xx/AM57xx */ +#define SYSC_PRUSS_SUB_MWAIT (1 << 5) +#define SYSC_PRUSS_STANDBY_INIT (1 << 4) + +/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */ +#define SYSC_IDLE_FORCE 0 +#define SYSC_IDLE_NO 1 +#define SYSC_IDLE_SMART 2 +#define SYSC_IDLE_SMART_WKUP 3 diff --git a/roms/u-boot/include/dt-bindings/clk/at91.h b/roms/u-boot/include/dt-bindings/clk/at91.h new file mode 100644 index 000000000..e30756b28 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clk/at91.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * This header provides constants for AT91 pmc status. + * The constants defined in this header are being used in dts and PMC code. + * + * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries + * + * Author: Claudiu Beznea + * + * Based on include/dt-bindings/clock/at91.h on Linux. + */ + +#ifndef _DT_BINDINGS_CLK_AT91_H +#define _DT_BINDINGS_CLK_AT91_H + +#define PMC_TYPE_CORE 1 +#define PMC_TYPE_SYSTEM 2 +#define PMC_TYPE_PERIPHERAL 3 +#define PMC_TYPE_GCK 4 +#define PMC_TYPE_SLOW 5 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clk/mpc83xx-clk.h b/roms/u-boot/include/dt-bindings/clk/mpc83xx-clk.h new file mode 100644 index 000000000..db4ea15cf --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clk/mpc83xx-clk.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#ifndef DT_BINDINGS_MPC83XX_CLK_H +#define DT_BINDINGS_MPC83XX_CLK_H +#define MPC83XX_CLK_CORE 0 +#define MPC83XX_CLK_CSB 1 +#define MPC83XX_CLK_QE 2 +#define MPC83XX_CLK_BRG 3 +#define MPC83XX_CLK_LBIU 4 +#define MPC83XX_CLK_LCLK 5 +#define MPC83XX_CLK_MEM 6 +#define MPC83XX_CLK_MEM_SEC 7 +#define MPC83XX_CLK_ENC 8 +#define MPC83XX_CLK_I2C1 9 +#define MPC83XX_CLK_I2C2 10 +#define MPC83XX_CLK_TDM 11 +#define MPC83XX_CLK_SDHC 12 +#define MPC83XX_CLK_TSEC1 13 +#define MPC83XX_CLK_TSEC2 14 +#define MPC83XX_CLK_USBDR 15 +#define MPC83XX_CLK_USBMPH 16 +#define MPC83XX_CLK_PCIEXP1 17 +#define MPC83XX_CLK_PCIEXP2 18 +#define MPC83XX_CLK_SATA 19 +#define MPC83XX_CLK_DMAC 20 +#define MPC83XX_CLK_PCI 21 +/* Count */ +#define MPC83XX_CLK_COUNT 22 +#endif /* DT_BINDINGS_MPC83XX_CLK_H */ diff --git a/roms/u-boot/include/dt-bindings/clk/ti-dra7-atl.h b/roms/u-boot/include/dt-bindings/clk/ti-dra7-atl.h new file mode 100644 index 000000000..42dd4164f --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clk/ti-dra7-atl.h @@ -0,0 +1,40 @@ +/* + * This header provides constants for DRA7 ATL (Audio Tracking Logic) + * + * The constants defined in this header are used in dts files + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Peter Ujfalusi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H +#define _DT_BINDINGS_CLK_DRA7_ATL_H + +#define DRA7_ATL_WS_MCASP1_FSR 0 +#define DRA7_ATL_WS_MCASP1_FSX 1 +#define DRA7_ATL_WS_MCASP2_FSR 2 +#define DRA7_ATL_WS_MCASP2_FSX 3 +#define DRA7_ATL_WS_MCASP3_FSX 4 +#define DRA7_ATL_WS_MCASP4_FSX 5 +#define DRA7_ATL_WS_MCASP5_FSX 6 +#define DRA7_ATL_WS_MCASP6_FSX 7 +#define DRA7_ATL_WS_MCASP7_FSX 8 +#define DRA7_ATL_WS_MCASP8_FSX 9 +#define DRA7_ATL_WS_MCASP8_AHCLKX 10 +#define DRA7_ATL_WS_XREF_CLK3 11 +#define DRA7_ATL_WS_XREF_CLK0 12 +#define DRA7_ATL_WS_XREF_CLK1 13 +#define DRA7_ATL_WS_XREF_CLK2 14 +#define DRA7_ATL_WS_OSC1_X1 15 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clk/versaclock.h b/roms/u-boot/include/dt-bindings/clk/versaclock.h new file mode 100644 index 000000000..c6a6a0946 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clk/versaclock.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* This file defines field values used by the versaclock 6 family + * for defining output type + */ + +#define VC5_LVPECL 0 +#define VC5_CMOS 1 +#define VC5_HCSL33 2 +#define VC5_LVDS 3 +#define VC5_CMOS2 4 +#define VC5_CMOSD 5 +#define VC5_HCSL25 6 diff --git a/roms/u-boot/include/dt-bindings/clock/actions,s700-cmu.h b/roms/u-boot/include/dt-bindings/clock/actions,s700-cmu.h new file mode 100644 index 000000000..3e1942996 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/actions,s700-cmu.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Device Tree binding constants for Actions Semi S700 Clock Management Unit + * + * Copyright (c) 2014 Actions Semi Inc. + * Author: David Liu + * + * Author: Pathiban Nallathambi + * Author: Saravanan Sekar + */ + +#ifndef __DT_BINDINGS_CLOCK_S700_H +#define __DT_BINDINGS_CLOCK_S700_H + +#define CLK_NONE 0 + +/* pll clocks */ +#define CLK_CORE_PLL 1 +#define CLK_DEV_PLL 2 +#define CLK_DDR_PLL 3 +#define CLK_NAND_PLL 4 +#define CLK_DISPLAY_PLL 5 +#define CLK_TVOUT_PLL 6 +#define CLK_CVBS_PLL 7 +#define CLK_AUDIO_PLL 8 +#define CLK_ETHERNET_PLL 9 + +/* system clock */ +#define CLK_CPU 10 +#define CLK_DEV 11 +#define CLK_AHB 12 +#define CLK_APB 13 +#define CLK_DMAC 14 +#define CLK_NOC0_CLK_MUX 15 +#define CLK_NOC1_CLK_MUX 16 +#define CLK_HP_CLK_MUX 17 +#define CLK_HP_CLK_DIV 18 +#define CLK_NOC1_CLK_DIV 19 +#define CLK_NOC0 20 +#define CLK_NOC1 21 +#define CLK_SENOR_SRC 22 + +/* peripheral device clock */ +#define CLK_GPIO 23 +#define CLK_TIMER 24 +#define CLK_DSI 25 +#define CLK_CSI 26 +#define CLK_SI 27 +#define CLK_DE 28 +#define CLK_HDE 29 +#define CLK_VDE 30 +#define CLK_VCE 31 +#define CLK_NAND 32 +#define CLK_SD0 33 +#define CLK_SD1 34 +#define CLK_SD2 35 + +#define CLK_UART0 36 +#define CLK_UART1 37 +#define CLK_UART2 38 +#define CLK_UART3 39 +#define CLK_UART4 40 +#define CLK_UART5 41 +#define CLK_UART6 42 + +#define CLK_PWM0 43 +#define CLK_PWM1 44 +#define CLK_PWM2 45 +#define CLK_PWM3 46 +#define CLK_PWM4 47 +#define CLK_PWM5 48 +#define CLK_GPU3D 49 + +#define CLK_I2C0 50 +#define CLK_I2C1 51 +#define CLK_I2C2 52 +#define CLK_I2C3 53 + +#define CLK_SPI0 54 +#define CLK_SPI1 55 +#define CLK_SPI2 56 +#define CLK_SPI3 57 + +#define CLK_USB3_480MPLL0 58 +#define CLK_USB3_480MPHY0 59 +#define CLK_USB3_5GPHY 60 +#define CLK_USB3_CCE 61 +#define CLK_USB3_MAC 62 + +#define CLK_LCD 63 +#define CLK_HDMI_AUDIO 64 +#define CLK_I2SRX 65 +#define CLK_I2STX 66 + +#define CLK_SENSOR0 67 +#define CLK_SENSOR1 68 + +#define CLK_HDMI_DEV 69 + +#define CLK_ETHERNET 70 +#define CLK_RMII_REF 71 + +#define CLK_USB2H0_PLLEN 72 +#define CLK_USB2H0_PHY 73 +#define CLK_USB2H0_CCE 74 +#define CLK_USB2H1_PLLEN 75 +#define CLK_USB2H1_PHY 76 +#define CLK_USB2H1_CCE 77 + +#define CLK_TVOUT 78 + +#define CLK_THERMAL_SENSOR 79 + +#define CLK_IRC_SWITCH 80 +#define CLK_PCM1 81 +#define CLK_NR_CLKS (CLK_PCM1 + 1) + +#endif /* __DT_BINDINGS_CLOCK_S700_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/actions,s900-cmu.h b/roms/u-boot/include/dt-bindings/clock/actions,s900-cmu.h new file mode 100644 index 000000000..7c1251565 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/actions,s900-cmu.h @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Device Tree binding constants for Actions Semi S900 Clock Management Unit +// +// Copyright (c) 2014 Actions Semi Inc. +// Copyright (c) 2018 Linaro Ltd. + +#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H +#define __DT_BINDINGS_CLOCK_S900_CMU_H + +#define CLK_NONE 0 + +/* fixed rate clocks */ +#define CLK_LOSC 1 +#define CLK_HOSC 2 + +/* pll clocks */ +#define CLK_CORE_PLL 3 +#define CLK_DEV_PLL 4 +#define CLK_DDR_PLL 5 +#define CLK_NAND_PLL 6 +#define CLK_DISPLAY_PLL 7 +#define CLK_DSI_PLL 8 +#define CLK_ASSIST_PLL 9 +#define CLK_AUDIO_PLL 10 + +/* system clock */ +#define CLK_CPU 15 +#define CLK_DEV 16 +#define CLK_NOC 17 +#define CLK_NOC_MUX 18 +#define CLK_NOC_DIV 19 +#define CLK_AHB 20 +#define CLK_APB 21 +#define CLK_DMAC 22 + +/* peripheral device clock */ +#define CLK_GPIO 23 + +#define CLK_BISP 24 +#define CLK_CSI0 25 +#define CLK_CSI1 26 + +#define CLK_DE0 27 +#define CLK_DE1 28 +#define CLK_DE2 29 +#define CLK_DE3 30 +#define CLK_DSI 32 + +#define CLK_GPU 33 +#define CLK_GPU_CORE 34 +#define CLK_GPU_MEM 35 +#define CLK_GPU_SYS 36 + +#define CLK_HDE 37 +#define CLK_I2C0 38 +#define CLK_I2C1 39 +#define CLK_I2C2 40 +#define CLK_I2C3 41 +#define CLK_I2C4 42 +#define CLK_I2C5 43 +#define CLK_I2SRX 44 +#define CLK_I2STX 45 +#define CLK_IMX 46 +#define CLK_LCD 47 +#define CLK_NAND0 48 +#define CLK_NAND1 49 +#define CLK_PWM0 50 +#define CLK_PWM1 51 +#define CLK_PWM2 52 +#define CLK_PWM3 53 +#define CLK_PWM4 54 +#define CLK_PWM5 55 +#define CLK_SD0 56 +#define CLK_SD1 57 +#define CLK_SD2 58 +#define CLK_SD3 59 +#define CLK_SENSOR 60 +#define CLK_SPEED_SENSOR 61 +#define CLK_SPI0 62 +#define CLK_SPI1 63 +#define CLK_SPI2 64 +#define CLK_SPI3 65 +#define CLK_THERMAL_SENSOR 66 +#define CLK_UART0 67 +#define CLK_UART1 68 +#define CLK_UART2 69 +#define CLK_UART3 70 +#define CLK_UART4 71 +#define CLK_UART5 72 +#define CLK_UART6 73 +#define CLK_VCE 74 +#define CLK_VDE 75 + +#define CLK_USB3_480MPLL0 76 +#define CLK_USB3_480MPHY0 77 +#define CLK_USB3_5GPHY 78 +#define CLK_USB3_CCE 79 +#define CLK_USB3_MAC 80 + +#define CLK_TIMER 83 + +#define CLK_HDMI_AUDIO 84 + +#define CLK_24M 85 + +#define CLK_EDP 86 + +#define CLK_24M_EDP 87 +#define CLK_EDP_PLL 88 +#define CLK_EDP_LINK 89 + +#define CLK_USB2H0_PLLEN 90 +#define CLK_USB2H0_PHY 91 +#define CLK_USB2H0_CCE 92 +#define CLK_USB2H1_PLLEN 93 +#define CLK_USB2H1_PHY 94 +#define CLK_USB2H1_CCE 95 + +#define CLK_DDR0 96 +#define CLK_DDR1 97 +#define CLK_DMM 98 + +#define CLK_ETH_MAC 99 +#define CLK_RMII_REF 100 + +#define CLK_NR_CLKS (CLK_RMII_REF + 1) + +#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/agilex-clock.h b/roms/u-boot/include/dt-bindings/clock/agilex-clock.h new file mode 100644 index 000000000..f751aad4d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/agilex-clock.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019, Intel Corporation + */ + +#ifndef __AGILEX_CLOCK_H +#define __AGILEX_CLOCK_H + +/* fixed rate clocks */ +#define AGILEX_OSC1 0 +#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 +#define AGILEX_CB_INTOSC_LS_CLK 2 +#define AGILEX_L4_SYS_FREE_CLK 3 +#define AGILEX_F2S_FREE_CLK 4 + +/* PLL clocks */ +#define AGILEX_MAIN_PLL_CLK 5 +#define AGILEX_MAIN_PLL_C0_CLK 6 +#define AGILEX_MAIN_PLL_C1_CLK 7 +#define AGILEX_MAIN_PLL_C2_CLK 8 +#define AGILEX_MAIN_PLL_C3_CLK 9 +#define AGILEX_PERIPH_PLL_CLK 10 +#define AGILEX_PERIPH_PLL_C0_CLK 11 +#define AGILEX_PERIPH_PLL_C1_CLK 12 +#define AGILEX_PERIPH_PLL_C2_CLK 13 +#define AGILEX_PERIPH_PLL_C3_CLK 14 +#define AGILEX_MPU_FREE_CLK 15 +#define AGILEX_MPU_CCU_CLK 16 +#define AGILEX_BOOT_CLK 17 + +/* fixed factor clocks */ +#define AGILEX_L3_MAIN_FREE_CLK 18 +#define AGILEX_NOC_FREE_CLK 19 +#define AGILEX_S2F_USR0_CLK 20 +#define AGILEX_NOC_CLK 21 +#define AGILEX_EMAC_A_FREE_CLK 22 +#define AGILEX_EMAC_B_FREE_CLK 23 +#define AGILEX_EMAC_PTP_FREE_CLK 24 +#define AGILEX_GPIO_DB_FREE_CLK 25 +#define AGILEX_SDMMC_FREE_CLK 26 +#define AGILEX_S2F_USER0_FREE_CLK 27 +#define AGILEX_S2F_USER1_FREE_CLK 28 +#define AGILEX_PSI_REF_FREE_CLK 29 + +/* Gate clocks */ +#define AGILEX_MPU_CLK 30 +#define AGILEX_MPU_PERIPH_CLK 31 +#define AGILEX_L4_MAIN_CLK 32 +#define AGILEX_L4_MP_CLK 33 +#define AGILEX_L4_SP_CLK 34 +#define AGILEX_CS_AT_CLK 35 +#define AGILEX_CS_TRACE_CLK 36 +#define AGILEX_CS_PDBG_CLK 37 +#define AGILEX_CS_TIMER_CLK 38 +#define AGILEX_S2F_USER0_CLK 39 +#define AGILEX_EMAC0_CLK 40 +#define AGILEX_EMAC1_CLK 41 +#define AGILEX_EMAC2_CLK 42 +#define AGILEX_EMAC_PTP_CLK 43 +#define AGILEX_GPIO_DB_CLK 44 +#define AGILEX_NAND_CLK 45 +#define AGILEX_PSI_REF_CLK 46 +#define AGILEX_S2F_USER1_CLK 47 +#define AGILEX_SDMMC_CLK 48 +#define AGILEX_SPI_M_CLK 49 +#define AGILEX_USB_CLK 50 +#define AGILEX_NAND_X_CLK 51 +#define AGILEX_NAND_ECC_CLK 52 +#define AGILEX_NUM_CLKS 53 + +#endif /* __AGILEX_CLOCK_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/am3.h b/roms/u-boot/include/dt-bindings/clock/am3.h new file mode 100644 index 000000000..86a8806e2 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/am3.h @@ -0,0 +1,227 @@ +/* + * Copyright 2017 Texas Instruments, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_CLK_AM3_H +#define __DT_BINDINGS_CLK_AM3_H + +#define AM3_CLKCTRL_OFFSET 0x0 +#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) + +/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ + +/* l4_per clocks */ +#define AM3_L4_PER_CLKCTRL_OFFSET 0x14 +#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) +#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) +#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) +#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) +#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) +#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) +#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) +#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) +#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) +#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38) +#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c) +#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40) +#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44) +#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48) +#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c) +#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50) +#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60) +#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68) +#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c) +#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70) +#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74) +#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78) +#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c) +#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80) +#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84) +#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88) +#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90) +#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94) +#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0) +#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac) +#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0) +#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4) +#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc) +#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0) +#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4) +#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc) +#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4) +#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8) +#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc) +#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0) +#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8) +#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec) +#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0) +#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4) +#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8) +#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc) +#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100) +#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c) +#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110) +#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120) +#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130) +#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c) + +/* l4_wkup clocks */ +#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4 +#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) +#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4) +#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8) +#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc) +#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14) +#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0) +#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4) +#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8) +#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc) +#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0) +#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4) +#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8) +#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4) + +/* mpu clocks */ +#define AM3_MPU_CLKCTRL_OFFSET 0x4 +#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) +#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4) + +/* l4_rtc clocks */ +#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) + +/* gfx_l3 clocks */ +#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4 +#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) +#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4) + +/* l4_cefuse clocks */ +#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20 +#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) +#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) + +/* XXX: Compatibility part end */ + +/* l4ls clocks */ +#define AM3_L4LS_CLKCTRL_OFFSET 0x38 +#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) +#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38) +#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c) +#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40) +#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44) +#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48) +#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c) +#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50) +#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60) +#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c) +#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70) +#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74) +#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78) +#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c) +#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80) +#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84) +#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88) +#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90) +#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac) +#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0) +#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4) +#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0) +#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4) +#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc) +#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4) +#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8) +#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec) +#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0) +#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4) +#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c) +#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110) +#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130) + +/* l3s clocks */ +#define AM3_L3S_CLKCTRL_OFFSET 0x1c +#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET) +#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c) +#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30) +#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34) +#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68) +#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8) + +/* l3 clocks */ +#define AM3_L3_CLKCTRL_OFFSET 0x24 +#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET) +#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24) +#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28) +#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c) +#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94) +#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0) +#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc) +#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc) +#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0) +#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc) +#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100) + +/* l4hs clocks */ +#define AM3_L4HS_CLKCTRL_OFFSET 0x120 +#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET) +#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120) + +/* pruss_ocp clocks */ +#define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8 +#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET) +#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8) + +/* cpsw_125mhz clocks */ +#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14) + +/* lcdc clocks */ +#define AM3_LCDC_CLKCTRL_OFFSET 0x18 +#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET) +#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18) + +/* clk_24mhz clocks */ +#define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c +#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET) +#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c) + +/* l4_wkup clocks */ +#define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4) +#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8) +#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc) +#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4) +#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8) +#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc) +#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0) +#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4) +#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8) +#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4) + +/* l3_aon clocks */ +#define AM3_L3_AON_CLKCTRL_OFFSET 0x14 +#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET) +#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14) + +/* l4_wkup_aon clocks */ +#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0 +#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET) +#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0) + +/* mpu clocks */ +#define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4) + +/* l4_rtc clocks */ +#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) + +/* gfx_l3 clocks */ +#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4) + +/* l4_cefuse clocks */ +#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20) + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/aspeed-clock.h b/roms/u-boot/include/dt-bindings/clock/aspeed-clock.h new file mode 100644 index 000000000..a1aa8c07c --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/aspeed-clock.h @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 + +#define ASPEED_CLK_GATE_ECLK 0 +#define ASPEED_CLK_GATE_GCLK 1 +#define ASPEED_CLK_GATE_MCLK 2 +#define ASPEED_CLK_GATE_VCLK 3 +#define ASPEED_CLK_GATE_BCLK 4 +#define ASPEED_CLK_GATE_DCLK 5 +#define ASPEED_CLK_GATE_REFCLK 6 +#define ASPEED_CLK_GATE_USBPORT2CLK 7 +#define ASPEED_CLK_GATE_LCLK 8 +#define ASPEED_CLK_GATE_USBUHCICLK 9 +#define ASPEED_CLK_GATE_D1CLK 10 +#define ASPEED_CLK_GATE_YCLK 11 +#define ASPEED_CLK_GATE_USBPORT1CLK 12 +#define ASPEED_CLK_GATE_UART1CLK 13 +#define ASPEED_CLK_GATE_UART2CLK 14 +#define ASPEED_CLK_GATE_UART5CLK 15 +#define ASPEED_CLK_GATE_ESPICLK 16 +#define ASPEED_CLK_GATE_MAC1CLK 17 +#define ASPEED_CLK_GATE_MAC2CLK 18 +#define ASPEED_CLK_GATE_RSACLK 19 +#define ASPEED_CLK_GATE_UART3CLK 20 +#define ASPEED_CLK_GATE_UART4CLK 21 +#define ASPEED_CLK_GATE_SDCLK 22 +#define ASPEED_CLK_GATE_LHCCLK 23 +#define ASPEED_CLK_HPLL 24 +#define ASPEED_CLK_AHB 25 +#define ASPEED_CLK_APB 26 +#define ASPEED_CLK_UART 27 +#define ASPEED_CLK_SDIO 28 +#define ASPEED_CLK_ECLK 29 +#define ASPEED_CLK_ECLK_MUX 30 +#define ASPEED_CLK_LHCLK 31 +#define ASPEED_CLK_MAC 32 +#define ASPEED_CLK_BCLK 33 +#define ASPEED_CLK_MPLL 34 +#define ASPEED_CLK_24M 35 +#define ASPEED_CLK_MAC1RCLK 36 +#define ASPEED_CLK_MAC2RCLK 37 +#define ASPEED_CLK_DPLL 38 +#define ASPEED_CLK_D2PLL 39 diff --git a/roms/u-boot/include/dt-bindings/clock/ast2600-clock.h b/roms/u-boot/include/dt-bindings/clock/ast2600-clock.h new file mode 100644 index 000000000..36294a514 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/ast2600-clock.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#define ASPEED_CLK_GATE_ECLK 0 +#define ASPEED_CLK_GATE_GCLK 1 +#define ASPEED_CLK_GATE_MCLK 2 +#define ASPEED_CLK_GATE_VCLK 3 +#define ASPEED_CLK_GATE_BCLK 4 +#define ASPEED_CLK_GATE_DCLK 5 +#define ASPEED_CLK_GATE_LCLK 6 +#define ASPEED_CLK_GATE_YCLK 7 +#define ASPEED_CLK_GATE_LHCCLK 8 +#define ASPEED_CLK_GATE_REFCLK 9 +#define ASPEED_CLK_GATE_ESPICLK 10 +#define ASPEED_CLK_GATE_UART1CLK 11 +#define ASPEED_CLK_GATE_UART2CLK 12 +#define ASPEED_CLK_GATE_UART3CLK 13 +#define ASPEED_CLK_GATE_UART4CLK 14 +#define ASPEED_CLK_GATE_UART5CLK 15 +#define ASPEED_CLK_GATE_UART6CLK 16 +#define ASPEED_CLK_GATE_UART7CLK 17 +#define ASPEED_CLK_GATE_UART8CLK 18 +#define ASPEED_CLK_GATE_UART9CLK 19 +#define ASPEED_CLK_GATE_UART10CLK 20 +#define ASPEED_CLK_GATE_UART11CLK 21 +#define ASPEED_CLK_GATE_UART12CLK 22 +#define ASPEED_CLK_GATE_UART13CLK 23 +#define ASPEED_CLK_GATE_MAC1CLK 24 +#define ASPEED_CLK_GATE_MAC2CLK 25 +#define ASPEED_CLK_GATE_MAC3CLK 26 +#define ASPEED_CLK_GATE_MAC4CLK 27 +#define ASPEED_CLK_GATE_RSACLK 28 +#define ASPEED_CLK_GATE_SDCLK 29 +#define ASPEED_CLK_GATE_SDEXTCLK 30 +#define ASPEED_CLK_GATE_EMMCCLK 31 +#define ASPEED_CLK_GATE_EMMCEXTCLK 32 +#define ASPEED_CLK_GATE_USBUHCICLK 33 +#define ASPEED_CLK_GATE_USBPORT1CLK 34 +#define ASPEED_CLK_GATE_USBPORT2CLK 35 +#define ASPEED_CLK_GATE_FSICLK 36 + +#define ASPEED_CLK_APLL 37 +#define ASPEED_CLK_EPLL 38 +#define ASPEED_CLK_DPLL 39 +#define ASPEED_CLK_HPLL 40 +#define ASPEED_CLK_AHB 41 +#define ASPEED_CLK_APB1 42 +#define ASPEED_CLK_APB2 43 +#define ASPEED_CLK_UART 44 +#define ASPEED_CLK_SDIO 45 +#define ASPEED_CLK_ECLK 46 +#define ASPEED_CLK_ECLK_MUX 47 +#define ASPEED_CLK_LHCLK 48 +#define ASPEED_CLK_MAC 49 +#define ASPEED_CLK_BCLK 50 +#define ASPEED_CLK_MPLL 51 +#define ASPEED_CLK_24M 52 +#define ASPEED_CLK_EMMC 53 +#define ASPEED_CLK_UARTX 54 +#define ASPEED_CLK_HUARTX 55 diff --git a/roms/u-boot/include/dt-bindings/clock/at91.h b/roms/u-boot/include/dt-bindings/clock/at91.h new file mode 100644 index 000000000..ab3ee241d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/at91.h @@ -0,0 +1,23 @@ +/* + * This header provides constants for AT91 pmc status. + * + * The constants defined in this header are being used in dts. + * + * Licensed under GPLv2 or later. + */ + +#ifndef _DT_BINDINGS_CLK_AT91_H +#define _DT_BINDINGS_CLK_AT91_H + +#define AT91_PMC_MOSCS 0 /* MOSCS Flag */ +#define AT91_PMC_LOCKA 1 /* PLLA Lock */ +#define AT91_PMC_LOCKB 2 /* PLLB Lock */ +#define AT91_PMC_MCKRDY 3 /* Master Clock */ +#define AT91_PMC_LOCKU 6 /* UPLL Lock */ +#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */ +#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */ +#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */ +#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */ +#define AT91_PMC_GCKRDY 24 /* Generated Clocks */ + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/axg-aoclkc.h b/roms/u-boot/include/dt-bindings/clock/axg-aoclkc.h new file mode 100644 index 000000000..8ec4a269c --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/axg-aoclkc.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Qiufang Dai + */ + +#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK +#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK + +#define CLKID_AO_REMOTE 0 +#define CLKID_AO_I2C_MASTER 1 +#define CLKID_AO_I2C_SLAVE 2 +#define CLKID_AO_UART1 3 +#define CLKID_AO_UART2 4 +#define CLKID_AO_IR_BLASTER 5 +#define CLKID_AO_SAR_ADC 6 +#define CLKID_AO_CLK81 7 +#define CLKID_AO_SAR_ADC_SEL 8 +#define CLKID_AO_SAR_ADC_DIV 9 +#define CLKID_AO_SAR_ADC_CLK 10 +#define CLKID_AO_CTS_OSCIN 11 +#define CLKID_AO_32K_PRE 12 +#define CLKID_AO_32K_DIV 13 +#define CLKID_AO_32K_SEL 14 +#define CLKID_AO_32K 15 +#define CLKID_AO_CTS_RTC_OSCIN 16 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/axg-audio-clkc.h b/roms/u-boot/include/dt-bindings/clock/axg-audio-clkc.h new file mode 100644 index 000000000..f561f5c5e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/axg-audio-clkc.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2018 Baylibre SAS. + * Author: Jerome Brunet + */ + +#ifndef __AXG_AUDIO_CLKC_BINDINGS_H +#define __AXG_AUDIO_CLKC_BINDINGS_H + +#define AUD_CLKID_DDR_ARB 29 +#define AUD_CLKID_PDM 30 +#define AUD_CLKID_TDMIN_A 31 +#define AUD_CLKID_TDMIN_B 32 +#define AUD_CLKID_TDMIN_C 33 +#define AUD_CLKID_TDMIN_LB 34 +#define AUD_CLKID_TDMOUT_A 35 +#define AUD_CLKID_TDMOUT_B 36 +#define AUD_CLKID_TDMOUT_C 37 +#define AUD_CLKID_FRDDR_A 38 +#define AUD_CLKID_FRDDR_B 39 +#define AUD_CLKID_FRDDR_C 40 +#define AUD_CLKID_TODDR_A 41 +#define AUD_CLKID_TODDR_B 42 +#define AUD_CLKID_TODDR_C 43 +#define AUD_CLKID_LOOPBACK 44 +#define AUD_CLKID_SPDIFIN 45 +#define AUD_CLKID_SPDIFOUT 46 +#define AUD_CLKID_RESAMPLE 47 +#define AUD_CLKID_POWER_DETECT 48 +#define AUD_CLKID_MST_A_MCLK 49 +#define AUD_CLKID_MST_B_MCLK 50 +#define AUD_CLKID_MST_C_MCLK 51 +#define AUD_CLKID_MST_D_MCLK 52 +#define AUD_CLKID_MST_E_MCLK 53 +#define AUD_CLKID_MST_F_MCLK 54 +#define AUD_CLKID_SPDIFOUT_CLK 55 +#define AUD_CLKID_SPDIFIN_CLK 56 +#define AUD_CLKID_PDM_DCLK 57 +#define AUD_CLKID_PDM_SYSCLK 58 +#define AUD_CLKID_MST_A_SCLK 79 +#define AUD_CLKID_MST_B_SCLK 80 +#define AUD_CLKID_MST_C_SCLK 81 +#define AUD_CLKID_MST_D_SCLK 82 +#define AUD_CLKID_MST_E_SCLK 83 +#define AUD_CLKID_MST_F_SCLK 84 +#define AUD_CLKID_MST_A_LRCLK 86 +#define AUD_CLKID_MST_B_LRCLK 87 +#define AUD_CLKID_MST_C_LRCLK 88 +#define AUD_CLKID_MST_D_LRCLK 89 +#define AUD_CLKID_MST_E_LRCLK 90 +#define AUD_CLKID_MST_F_LRCLK 91 +#define AUD_CLKID_TDMIN_A_SCLK_SEL 116 +#define AUD_CLKID_TDMIN_B_SCLK_SEL 117 +#define AUD_CLKID_TDMIN_C_SCLK_SEL 118 +#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119 +#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120 +#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121 +#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122 +#define AUD_CLKID_TDMIN_A_SCLK 123 +#define AUD_CLKID_TDMIN_B_SCLK 124 +#define AUD_CLKID_TDMIN_C_SCLK 125 +#define AUD_CLKID_TDMIN_LB_SCLK 126 +#define AUD_CLKID_TDMOUT_A_SCLK 127 +#define AUD_CLKID_TDMOUT_B_SCLK 128 +#define AUD_CLKID_TDMOUT_C_SCLK 129 +#define AUD_CLKID_TDMIN_A_LRCLK 130 +#define AUD_CLKID_TDMIN_B_LRCLK 131 +#define AUD_CLKID_TDMIN_C_LRCLK 132 +#define AUD_CLKID_TDMIN_LB_LRCLK 133 +#define AUD_CLKID_TDMOUT_A_LRCLK 134 +#define AUD_CLKID_TDMOUT_B_LRCLK 135 +#define AUD_CLKID_TDMOUT_C_LRCLK 136 +#define AUD_CLKID_SPDIFOUT_B 151 +#define AUD_CLKID_SPDIFOUT_B_CLK 152 +#define AUD_CLKID_TDM_MCLK_PAD0 155 +#define AUD_CLKID_TDM_MCLK_PAD1 156 +#define AUD_CLKID_TDM_LRCLK_PAD0 157 +#define AUD_CLKID_TDM_LRCLK_PAD1 158 +#define AUD_CLKID_TDM_LRCLK_PAD2 159 +#define AUD_CLKID_TDM_SCLK_PAD0 160 +#define AUD_CLKID_TDM_SCLK_PAD1 161 +#define AUD_CLKID_TDM_SCLK_PAD2 162 +#define AUD_CLKID_TOP 163 +#define AUD_CLKID_TORAM 164 +#define AUD_CLKID_EQDRC 165 +#define AUD_CLKID_RESAMPLE_B 166 +#define AUD_CLKID_TOVAD 167 +#define AUD_CLKID_LOCKER 168 +#define AUD_CLKID_SPDIFIN_LB 169 +#define AUD_CLKID_FRDDR_D 170 +#define AUD_CLKID_TODDR_D 171 +#define AUD_CLKID_LOOPBACK_B 172 + +#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/axg-clkc.h b/roms/u-boot/include/dt-bindings/clock/axg-clkc.h new file mode 100644 index 000000000..fd1f938c3 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/axg-clkc.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Meson-AXG clock tree IDs + * + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AXG_CLKC_H +#define __AXG_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2 2 +#define CLKID_FCLK_DIV3 3 +#define CLKID_FCLK_DIV4 4 +#define CLKID_FCLK_DIV5 5 +#define CLKID_FCLK_DIV7 6 +#define CLKID_GP0_PLL 7 +#define CLKID_CLK81 10 +#define CLKID_MPLL0 11 +#define CLKID_MPLL1 12 +#define CLKID_MPLL2 13 +#define CLKID_MPLL3 14 +#define CLKID_DDR 15 +#define CLKID_AUDIO_LOCKER 16 +#define CLKID_MIPI_DSI_HOST 17 +#define CLKID_ISA 18 +#define CLKID_PL301 19 +#define CLKID_PERIPHS 20 +#define CLKID_SPICC0 21 +#define CLKID_I2C 22 +#define CLKID_RNG0 23 +#define CLKID_UART0 24 +#define CLKID_MIPI_DSI_PHY 25 +#define CLKID_SPICC1 26 +#define CLKID_PCIE_A 27 +#define CLKID_PCIE_B 28 +#define CLKID_HIU_IFACE 29 +#define CLKID_ASSIST_MISC 30 +#define CLKID_SD_EMMC_B 31 +#define CLKID_SD_EMMC_C 32 +#define CLKID_DMA 33 +#define CLKID_SPI 34 +#define CLKID_AUDIO 35 +#define CLKID_ETH 36 +#define CLKID_UART1 37 +#define CLKID_G2D 38 +#define CLKID_USB0 39 +#define CLKID_USB1 40 +#define CLKID_RESET 41 +#define CLKID_USB 42 +#define CLKID_AHB_ARB0 43 +#define CLKID_EFUSE 44 +#define CLKID_BOOT_ROM 45 +#define CLKID_AHB_DATA_BUS 46 +#define CLKID_AHB_CTRL_BUS 47 +#define CLKID_USB1_DDR_BRIDGE 48 +#define CLKID_USB0_DDR_BRIDGE 49 +#define CLKID_MMC_PCLK 50 +#define CLKID_VPU_INTR 51 +#define CLKID_SEC_AHB_AHB3_BRIDGE 52 +#define CLKID_GIC 53 +#define CLKID_AO_MEDIA_CPU 54 +#define CLKID_AO_AHB_SRAM 55 +#define CLKID_AO_AHB_BUS 56 +#define CLKID_AO_IFACE 57 +#define CLKID_AO_I2C 58 +#define CLKID_SD_EMMC_B_CLK0 59 +#define CLKID_SD_EMMC_C_CLK0 60 +#define CLKID_HIFI_PLL 69 +#define CLKID_PCIE_CML_EN0 79 +#define CLKID_PCIE_CML_EN1 80 +#define CLKID_MIPI_ENABLE 81 +#define CLKID_GEN_CLK 84 + +#endif /* __AXG_CLKC_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/bcm2835-aux.h b/roms/u-boot/include/dt-bindings/clock/bcm2835-aux.h new file mode 100644 index 000000000..bb79de383 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/bcm2835-aux.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2015 Broadcom Corporation + */ + +#define BCM2835_AUX_CLOCK_UART 0 +#define BCM2835_AUX_CLOCK_SPI1 1 +#define BCM2835_AUX_CLOCK_SPI2 2 +#define BCM2835_AUX_CLOCK_COUNT 3 diff --git a/roms/u-boot/include/dt-bindings/clock/bcm2835.h b/roms/u-boot/include/dt-bindings/clock/bcm2835.h new file mode 100644 index 000000000..2cec01f96 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/bcm2835.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2015 Broadcom Corporation + */ + +#define BCM2835_PLLA 0 +#define BCM2835_PLLB 1 +#define BCM2835_PLLC 2 +#define BCM2835_PLLD 3 +#define BCM2835_PLLH 4 + +#define BCM2835_PLLA_CORE 5 +#define BCM2835_PLLA_PER 6 +#define BCM2835_PLLB_ARM 7 +#define BCM2835_PLLC_CORE0 8 +#define BCM2835_PLLC_CORE1 9 +#define BCM2835_PLLC_CORE2 10 +#define BCM2835_PLLC_PER 11 +#define BCM2835_PLLD_CORE 12 +#define BCM2835_PLLD_PER 13 +#define BCM2835_PLLH_RCAL 14 +#define BCM2835_PLLH_AUX 15 +#define BCM2835_PLLH_PIX 16 + +#define BCM2835_CLOCK_TIMER 17 +#define BCM2835_CLOCK_OTP 18 +#define BCM2835_CLOCK_UART 19 +#define BCM2835_CLOCK_VPU 20 +#define BCM2835_CLOCK_V3D 21 +#define BCM2835_CLOCK_ISP 22 +#define BCM2835_CLOCK_H264 23 +#define BCM2835_CLOCK_VEC 24 +#define BCM2835_CLOCK_HSM 25 +#define BCM2835_CLOCK_SDRAM 26 +#define BCM2835_CLOCK_TSENS 27 +#define BCM2835_CLOCK_EMMC 28 +#define BCM2835_CLOCK_PERI_IMAGE 29 +#define BCM2835_CLOCK_PWM 30 +#define BCM2835_CLOCK_PCM 31 + +#define BCM2835_PLLA_DSI0 32 +#define BCM2835_PLLA_CCP2 33 +#define BCM2835_PLLD_DSI0 34 +#define BCM2835_PLLD_DSI1 35 + +#define BCM2835_CLOCK_AVEO 36 +#define BCM2835_CLOCK_DFT 37 +#define BCM2835_CLOCK_GP0 38 +#define BCM2835_CLOCK_GP1 39 +#define BCM2835_CLOCK_GP2 40 +#define BCM2835_CLOCK_SLIM 41 +#define BCM2835_CLOCK_SMI 42 +#define BCM2835_CLOCK_TEC 43 +#define BCM2835_CLOCK_DPI 44 +#define BCM2835_CLOCK_CAM0 45 +#define BCM2835_CLOCK_CAM1 46 +#define BCM2835_CLOCK_DSI0E 47 +#define BCM2835_CLOCK_DSI1E 48 +#define BCM2835_CLOCK_DSI0P 49 +#define BCM2835_CLOCK_DSI1P 50 diff --git a/roms/u-boot/include/dt-bindings/clock/bcm3380-clock.h b/roms/u-boot/include/dt-bindings/clock/bcm3380-clock.h new file mode 100644 index 000000000..998d08f5b --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/bcm3380-clock.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from Broadcom GPL Source Code: + * Copyright (C) Broadcom Corporation + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM3380_H +#define __DT_BINDINGS_CLOCK_BCM3380_H + +#define BCM3380_CLK0_DDR 0 +#define BCM3380_CLK0_FPM 1 +#define BCM3380_CLK0_CRYPTO 2 +#define BCM3380_CLK0_EPHY 3 +#define BCM3380_CLK0_PCIE 16 +#define BCM3380_CLK0_SPI 17 +#define BCM3380_CLK0_ENET0 18 +#define BCM3380_CLK0_ENET1 19 +#define BCM3380_CLK0_PCM 27 + +#endif /* __DT_BINDINGS_CLOCK_BCM3380_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/bcm6318-clock.h b/roms/u-boot/include/dt-bindings/clock/bcm6318-clock.h new file mode 100644 index 000000000..3f10448ce --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/bcm6318-clock.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6318_H +#define __DT_BINDINGS_CLOCK_BCM6318_H + +#define BCM6318_CLK_ADSL_ASB 0 +#define BCM6318_CLK_USB_ASB 1 +#define BCM6318_CLK_MIPS_ASB 2 +#define BCM6318_CLK_PCIE_ASB 3 +#define BCM6318_CLK_PHYMIPS_ASB 4 +#define BCM6318_CLK_ROBOSW_ASB 5 +#define BCM6318_CLK_SAR_ASB 6 +#define BCM6318_CLK_SDR_ASB 7 +#define BCM6318_CLK_SWREG_ASB 8 +#define BCM6318_CLK_PERIPH_ASB 9 +#define BCM6318_CLK_CPUBUS160 10 +#define BCM6318_CLK_ADSL 11 +#define BCM6318_CLK_SAR125 12 +#define BCM6318_CLK_MIPS 13 +#define BCM6318_CLK_PCIE 14 +#define BCM6318_CLK_ROBOSW250 16 +#define BCM6318_CLK_ROBOSW025 17 +#define BCM6318_CLK_SDR 19 +#define BCM6318_CLK_USB 20 +#define BCM6318_CLK_HSSPI 25 +#define BCM6318_CLK_PCIE25 27 +#define BCM6318_CLK_PHYMIPS 28 +#define BCM6318_CLK_AFE 29 +#define BCM6318_CLK_QPROC 30 + +#define BCM6318_UCLK_ADSL 0 +#define BCM6318_UCLK_ARB 1 +#define BCM6318_UCLK_MIPS 2 +#define BCM6318_UCLK_PCIE 3 +#define BCM6318_UCLK_PERIPH 4 +#define BCM6318_UCLK_PHYMIPS 5 +#define BCM6318_UCLK_ROBOSW 6 +#define BCM6318_UCLK_SAR 7 +#define BCM6318_UCLK_SDR 8 +#define BCM6318_UCLK_USB 9 + +#endif /* __DT_BINDINGS_CLOCK_BCM6318_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/bcm63268-clock.h b/roms/u-boot/include/dt-bindings/clock/bcm63268-clock.h new file mode 100644 index 000000000..2725dcd06 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/bcm63268-clock.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM63268_H +#define __DT_BINDINGS_CLOCK_BCM63268_H + +#define BCM63268_CLK_GLESS 0 +#define BCM63268_CLK_VDSL_QPROC 1 +#define BCM63268_CLK_VDSL_AFE 2 +#define BCM63268_CLK_VDSL 3 +#define BCM63268_CLK_MIPS 4 +#define BCM63268_CLK_WLAN_OCP 5 +#define BCM63268_CLK_DECT 6 +#define BCM63268_CLK_FAP0 7 +#define BCM63268_CLK_FAP1 8 +#define BCM63268_CLK_SAR 9 +#define BCM63268_CLK_ROBOSW 10 +#define BCM63268_CLK_PCM 11 +#define BCM63268_CLK_USBD 12 +#define BCM63268_CLK_USBH 13 +#define BCM63268_CLK_IPSEC 14 +#define BCM63268_CLK_SPI 15 +#define BCM63268_CLK_HSSPI 16 +#define BCM63268_CLK_PCIE 17 +#define BCM63268_CLK_PHYMIPS 18 +#define BCM63268_CLK_GMAC 19 +#define BCM63268_CLK_NAND 20 +#define BCM63268_CLK_TBUS 27 +#define BCM63268_CLK_ROBOSW250 31 + +#define BCM63268_TCLK_EPHY1 0 +#define BCM63268_TCLK_EPHY2 1 +#define BCM63268_TCLK_EPHY3 2 +#define BCM63268_TCLK_GPHY 3 +#define BCM63268_TCLK_DSL 4 +#define BCM63268_TCLK_WO_EPHY 5 +#define BCM63268_TCLK_WO_DSL 6 +#define BCM63268_TCLK_FAP1 11 +#define BCM63268_TCLK_FAP2 15 +#define BCM63268_TCLK_UTO_50 16 +#define BCM63268_TCLK_UTO_EXT 17 +#define BCM63268_TCLK_USB_REF 18 +#define BCM63268_TCLK_SW_RST 29 +#define BCM63268_TCLK_HW_RST 30 +#define BCM63268_TCLK_POR_RST 31 + +#endif /* __DT_BINDINGS_CLOCK_BCM63268_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/bcm6328-clock.h b/roms/u-boot/include/dt-bindings/clock/bcm6328-clock.h new file mode 100644 index 000000000..6f1e018a7 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/bcm6328-clock.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6328_H +#define __DT_BINDINGS_CLOCK_BCM6328_H + +#define BCM6328_CLK_PHYMIPS 0 +#define BCM6328_CLK_ADSL_QPROC 1 +#define BCM6328_CLK_ADSL_AFE 2 +#define BCM6328_CLK_ADSL 3 +#define BCM6328_CLK_MIPS 4 +#define BCM6328_CLK_SAR 5 +#define BCM6328_CLK_PCM 6 +#define BCM6328_CLK_USBD 7 +#define BCM6328_CLK_USBH 8 +#define BCM6328_CLK_HSSPI 9 +#define BCM6328_CLK_PCIE 10 +#define BCM6328_CLK_ROBOSW 11 + +#endif /* __DT_BINDINGS_CLOCK_BCM6328_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/bcm6338-clock.h b/roms/u-boot/include/dt-bindings/clock/bcm6338-clock.h new file mode 100644 index 000000000..489aa1f95 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/bcm6338-clock.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6338_H +#define __DT_BINDINGS_CLOCK_BCM6338_H + +#define BCM6338_CLK_ADSL 0 +#define BCM6338_CLK_MPI 1 +#define BCM6338_CLK_SDRAM 2 +#define BCM6338_CLK_ENET 4 +#define BCM6338_CLK_SAR 5 +#define BCM6338_CLK_SPI 9 + +#endif /* __DT_BINDINGS_CLOCK_BCM6338_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/bcm6348-clock.h b/roms/u-boot/include/dt-bindings/clock/bcm6348-clock.h new file mode 100644 index 000000000..c67a7fea2 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/bcm6348-clock.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6348_H +#define __DT_BINDINGS_CLOCK_BCM6348_H + +#define BCM6348_CLK_ADSL 0 +#define BCM6348_CLK_MPI 1 +#define BCM6348_CLK_SDRAM 2 +#define BCM6348_CLK_M2M 3 +#define BCM6348_CLK_ENET 4 +#define BCM6348_CLK_SAR 5 +#define BCM6348_CLK_USBS 6 +#define BCM6348_CLK_USBH 8 +#define BCM6348_CLK_SPI 9 + +#endif /* __DT_BINDINGS_CLOCK_BCM6348_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/bcm6358-clock.h b/roms/u-boot/include/dt-bindings/clock/bcm6358-clock.h new file mode 100644 index 000000000..a7529bcc0 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/bcm6358-clock.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6358_H +#define __DT_BINDINGS_CLOCK_BCM6358_H + +#define BCM6358_CLK_ENET 4 +#define BCM6358_CLK_ADSL 5 +#define BCM6358_CLK_PCM 8 +#define BCM6358_CLK_SPI 9 +#define BCM6358_CLK_USBS 10 +#define BCM6358_CLK_SAR 11 +#define BCM6358_CLK_EMUSB 17 +#define BCM6358_CLK_ENET0 18 +#define BCM6358_CLK_ENET1 19 +#define BCM6358_CLK_USBSU 20 +#define BCM6358_CLK_EPHY 21 + +#endif /* __DT_BINDINGS_CLOCK_BCM6358_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/bcm6362-clock.h b/roms/u-boot/include/dt-bindings/clock/bcm6362-clock.h new file mode 100644 index 000000000..d3770c504 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/bcm6362-clock.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6362_H +#define __DT_BINDINGS_CLOCK_BCM6362_H + +#define BCM6362_CLK_GLESS 0 +#define BCM6362_CLK_ADSL_QPROC 1 +#define BCM6362_CLK_ADSL_AFE 2 +#define BCM6362_CLK_ADSL 3 +#define BCM6362_CLK_MIPS 4 +#define BCM6362_CLK_WLAN_OCP 5 +#define BCM6362_CLK_SWPKT_USB 7 +#define BCM6362_CLK_SWPKT_SAR 8 +#define BCM6362_CLK_SAR 9 +#define BCM6362_CLK_ROBOSW 10 +#define BCM6362_CLK_PCM 11 +#define BCM6362_CLK_USBD 12 +#define BCM6362_CLK_USBH 13 +#define BCM6362_CLK_IPSEC 14 +#define BCM6362_CLK_SPI 15 +#define BCM6362_CLK_HSSPI 16 +#define BCM6362_CLK_PCIE 17 +#define BCM6362_CLK_FAP 18 +#define BCM6362_CLK_PHYMIPS 19 +#define BCM6362_CLK_NAND 20 + +#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/bcm6368-clock.h b/roms/u-boot/include/dt-bindings/clock/bcm6368-clock.h new file mode 100644 index 000000000..0c8578263 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/bcm6368-clock.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6368_H +#define __DT_BINDINGS_CLOCK_BCM6368_H + +#define BCM6368_CLK_VDSL_QPROC 2 +#define BCM6368_CLK_VDSL_AFE 3 +#define BCM6368_CLK_VDSL_BONDING 4 +#define BCM6368_CLK_VDSL 5 +#define BCM6368_CLK_PHYMIPS 6 +#define BCM6368_CLK_SWPKT_USB 7 +#define BCM6368_CLK_SWPKT_SAR 8 +#define BCM6368_CLK_SPI 9 +#define BCM6368_CLK_USBD 10 +#define BCM6368_CLK_SAR 11 +#define BCM6368_CLK_ROBOSW 12 +#define BCM6368_CLK_UTOPIA 13 +#define BCM6368_CLK_PCM 14 +#define BCM6368_CLK_USBH 15 +#define BCM6368_CLK_GLESS 16 +#define BCM6368_CLK_NAND 17 +#define BCM6368_CLK_IPSEC 18 +#define BCM6368_CLK_USBH_IDDQ 19 + +#endif /* __DT_BINDINGS_CLOCK_BCM6368_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/boston-clock.h b/roms/u-boot/include/dt-bindings/clock/boston-clock.h new file mode 100644 index 000000000..0b3906247 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/boston-clock.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Imagination Technologies + */ + +#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ +#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ + +#define BOSTON_CLK_SYS 0 +#define BOSTON_CLK_CPU 1 + +#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/exynos7420-clk.h b/roms/u-boot/include/dt-bindings/clock/exynos7420-clk.h new file mode 100644 index 000000000..10c558611 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/exynos7420-clk.h @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Author: Naveen Krishna Ch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H +#define _DT_BINDINGS_CLOCK_EXYNOS7_H + +/* TOPC */ +#define DOUT_ACLK_PERIS 1 +#define DOUT_SCLK_BUS0_PLL 2 +#define DOUT_SCLK_BUS1_PLL 3 +#define DOUT_SCLK_CC_PLL 4 +#define DOUT_SCLK_MFC_PLL 5 +#define DOUT_ACLK_CCORE_133 6 +#define DOUT_ACLK_MSCL_532 7 +#define ACLK_MSCL_532 8 +#define DOUT_SCLK_AUD_PLL 9 +#define FOUT_AUD_PLL 10 +#define SCLK_AUD_PLL 11 +#define SCLK_MFC_PLL_B 12 +#define SCLK_MFC_PLL_A 13 +#define SCLK_BUS1_PLL_B 14 +#define SCLK_BUS1_PLL_A 15 +#define SCLK_BUS0_PLL_B 16 +#define SCLK_BUS0_PLL_A 17 +#define SCLK_CC_PLL_B 18 +#define SCLK_CC_PLL_A 19 +#define ACLK_CCORE_133 20 +#define ACLK_PERIS_66 21 +#define TOPC_NR_CLK 22 + +/* TOP0 */ +#define DOUT_ACLK_PERIC1 1 +#define DOUT_ACLK_PERIC0 2 +#define CLK_SCLK_UART0 3 +#define CLK_SCLK_UART1 4 +#define CLK_SCLK_UART2 5 +#define CLK_SCLK_UART3 6 +#define CLK_SCLK_SPI0 7 +#define CLK_SCLK_SPI1 8 +#define CLK_SCLK_SPI2 9 +#define CLK_SCLK_SPI3 10 +#define CLK_SCLK_SPI4 11 +#define CLK_SCLK_SPDIF 12 +#define CLK_SCLK_PCM1 13 +#define CLK_SCLK_I2S1 14 +#define CLK_ACLK_PERIC0_66 15 +#define CLK_ACLK_PERIC1_66 16 +#define TOP0_NR_CLK 17 + +/* TOP1 */ +#define DOUT_ACLK_FSYS1_200 1 +#define DOUT_ACLK_FSYS0_200 2 +#define DOUT_SCLK_MMC2 3 +#define DOUT_SCLK_MMC1 4 +#define DOUT_SCLK_MMC0 5 +#define CLK_SCLK_MMC2 6 +#define CLK_SCLK_MMC1 7 +#define CLK_SCLK_MMC0 8 +#define CLK_ACLK_FSYS0_200 9 +#define CLK_ACLK_FSYS1_200 10 +#define CLK_SCLK_PHY_FSYS1 11 +#define CLK_SCLK_PHY_FSYS1_26M 12 +#define MOUT_SCLK_UFSUNIPRO20 13 +#define DOUT_SCLK_UFSUNIPRO20 14 +#define CLK_SCLK_UFSUNIPRO20 15 +#define DOUT_SCLK_PHY_FSYS1 16 +#define DOUT_SCLK_PHY_FSYS1_26M 17 +#define TOP1_NR_CLK 18 + +/* CCORE */ +#define PCLK_RTC 1 +#define CCORE_NR_CLK 2 + +/* PERIC0 */ +#define PCLK_UART0 1 +#define SCLK_UART0 2 +#define PCLK_HSI2C0 3 +#define PCLK_HSI2C1 4 +#define PCLK_HSI2C4 5 +#define PCLK_HSI2C5 6 +#define PCLK_HSI2C9 7 +#define PCLK_HSI2C10 8 +#define PCLK_HSI2C11 9 +#define PCLK_PWM 10 +#define SCLK_PWM 11 +#define PCLK_ADCIF 12 +#define PERIC0_NR_CLK 13 + +/* PERIC1 */ +#define PCLK_UART1 1 +#define PCLK_UART2 2 +#define PCLK_UART3 3 +#define SCLK_UART1 4 +#define SCLK_UART2 5 +#define SCLK_UART3 6 +#define PCLK_HSI2C2 7 +#define PCLK_HSI2C3 8 +#define PCLK_HSI2C6 9 +#define PCLK_HSI2C7 10 +#define PCLK_HSI2C8 11 +#define PCLK_SPI0 12 +#define PCLK_SPI1 13 +#define PCLK_SPI2 14 +#define PCLK_SPI3 15 +#define PCLK_SPI4 16 +#define SCLK_SPI0 17 +#define SCLK_SPI1 18 +#define SCLK_SPI2 19 +#define SCLK_SPI3 20 +#define SCLK_SPI4 21 +#define PCLK_I2S1 22 +#define PCLK_PCM1 23 +#define PCLK_SPDIF 24 +#define SCLK_I2S1 25 +#define SCLK_PCM1 26 +#define SCLK_SPDIF 27 +#define PERIC1_NR_CLK 28 + +/* PERIS */ +#define PCLK_CHIPID 1 +#define SCLK_CHIPID 2 +#define PCLK_WDT 3 +#define PCLK_TMU 4 +#define SCLK_TMU 5 +#define PERIS_NR_CLK 6 + +/* FSYS0 */ +#define ACLK_MMC2 1 +#define ACLK_AXIUS_USBDRD30X_FSYS0X 2 +#define ACLK_USBDRD300 3 +#define SCLK_USBDRD300_SUSPENDCLK 4 +#define SCLK_USBDRD300_REFCLK 5 +#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6 +#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7 +#define OSCCLK_PHY_CLKOUT_USB30_PHY 8 +#define ACLK_PDMA0 9 +#define ACLK_PDMA1 10 +#define FSYS0_NR_CLK 11 + +/* FSYS1 */ +#define ACLK_MMC1 1 +#define ACLK_MMC0 2 +#define PHYCLK_UFS20_TX0_SYMBOL 3 +#define PHYCLK_UFS20_RX0_SYMBOL 4 +#define PHYCLK_UFS20_RX1_SYMBOL 5 +#define ACLK_UFS20_LINK 6 +#define SCLK_UFSUNIPRO20_USER 7 +#define PHYCLK_UFS20_RX1_SYMBOL_USER 8 +#define PHYCLK_UFS20_RX0_SYMBOL_USER 9 +#define PHYCLK_UFS20_TX0_SYMBOL_USER 10 +#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11 +#define SCLK_COMBO_PHY_EMBEDDED_26M 12 +#define DOUT_PCLK_FSYS1 13 +#define PCLK_GPIO_FSYS1 14 +#define MOUT_FSYS1_PHYCLK_SEL1 15 +#define FSYS1_NR_CLK 16 + +/* MSCL */ +#define USERMUX_ACLK_MSCL_532 1 +#define DOUT_PCLK_MSCL 2 +#define ACLK_MSCL_0 3 +#define ACLK_MSCL_1 4 +#define ACLK_JPEG 5 +#define ACLK_G2D 6 +#define ACLK_LH_ASYNC_SI_MSCL_0 7 +#define ACLK_LH_ASYNC_SI_MSCL_1 8 +#define ACLK_AXI2ACEL_BRIDGE 9 +#define ACLK_XIU_MSCLX_0 10 +#define ACLK_XIU_MSCLX_1 11 +#define ACLK_QE_MSCL_0 12 +#define ACLK_QE_MSCL_1 13 +#define ACLK_QE_JPEG 14 +#define ACLK_QE_G2D 15 +#define ACLK_PPMU_MSCL_0 16 +#define ACLK_PPMU_MSCL_1 17 +#define ACLK_MSCLNP_133 18 +#define ACLK_AHB2APB_MSCL0P 19 +#define ACLK_AHB2APB_MSCL1P 20 + +#define PCLK_MSCL_0 21 +#define PCLK_MSCL_1 22 +#define PCLK_JPEG 23 +#define PCLK_G2D 24 +#define PCLK_QE_MSCL_0 25 +#define PCLK_QE_MSCL_1 26 +#define PCLK_QE_JPEG 27 +#define PCLK_QE_G2D 28 +#define PCLK_PPMU_MSCL_0 29 +#define PCLK_PPMU_MSCL_1 30 +#define PCLK_AXI2ACEL_BRIDGE 31 +#define PCLK_PMU_MSCL 32 +#define MSCL_NR_CLK 33 + +/* AUD */ +#define SCLK_I2S 1 +#define SCLK_PCM 2 +#define PCLK_I2S 3 +#define PCLK_PCM 4 +#define ACLK_ADMA 5 +#define AUD_NR_CLK 6 +#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/g12a-aoclkc.h b/roms/u-boot/include/dt-bindings/clock/g12a-aoclkc.h new file mode 100644 index 000000000..e916e49ff --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/g12a-aoclkc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Qiufang Dai + */ + +#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK +#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK + +#define CLKID_AO_AHB 0 +#define CLKID_AO_IR_IN 1 +#define CLKID_AO_I2C_M0 2 +#define CLKID_AO_I2C_S0 3 +#define CLKID_AO_UART 4 +#define CLKID_AO_PROD_I2C 5 +#define CLKID_AO_UART2 6 +#define CLKID_AO_IR_OUT 7 +#define CLKID_AO_SAR_ADC 8 +#define CLKID_AO_MAILBOX 9 +#define CLKID_AO_M3 10 +#define CLKID_AO_AHB_SRAM 11 +#define CLKID_AO_RTI 12 +#define CLKID_AO_M4_FCLK 13 +#define CLKID_AO_M4_HCLK 14 +#define CLKID_AO_CLK81 15 +#define CLKID_AO_SAR_ADC_SEL 16 +#define CLKID_AO_SAR_ADC_CLK 18 +#define CLKID_AO_CTS_OSCIN 19 +#define CLKID_AO_32K 23 +#define CLKID_AO_CEC 27 +#define CLKID_AO_CTS_RTC_OSCIN 28 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/g12a-clkc.h b/roms/u-boot/include/dt-bindings/clock/g12a-clkc.h new file mode 100644 index 000000000..40d49940d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/g12a-clkc.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +/* + * Meson-G12A clock tree IDs + * + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +#ifndef __G12A_CLKC_H +#define __G12A_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2 2 +#define CLKID_FCLK_DIV3 3 +#define CLKID_FCLK_DIV4 4 +#define CLKID_FCLK_DIV5 5 +#define CLKID_FCLK_DIV7 6 +#define CLKID_GP0_PLL 7 +#define CLKID_CLK81 10 +#define CLKID_MPLL0 11 +#define CLKID_MPLL1 12 +#define CLKID_MPLL2 13 +#define CLKID_MPLL3 14 +#define CLKID_DDR 15 +#define CLKID_DOS 16 +#define CLKID_AUDIO_LOCKER 17 +#define CLKID_MIPI_DSI_HOST 18 +#define CLKID_ETH_PHY 19 +#define CLKID_ISA 20 +#define CLKID_PL301 21 +#define CLKID_PERIPHS 22 +#define CLKID_SPICC0 23 +#define CLKID_I2C 24 +#define CLKID_SANA 25 +#define CLKID_SD 26 +#define CLKID_RNG0 27 +#define CLKID_UART0 28 +#define CLKID_SPICC1 29 +#define CLKID_HIU_IFACE 30 +#define CLKID_MIPI_DSI_PHY 31 +#define CLKID_ASSIST_MISC 32 +#define CLKID_SD_EMMC_A 33 +#define CLKID_SD_EMMC_B 34 +#define CLKID_SD_EMMC_C 35 +#define CLKID_AUDIO_CODEC 36 +#define CLKID_AUDIO 37 +#define CLKID_ETH 38 +#define CLKID_DEMUX 39 +#define CLKID_AUDIO_IFIFO 40 +#define CLKID_ADC 41 +#define CLKID_UART1 42 +#define CLKID_G2D 43 +#define CLKID_RESET 44 +#define CLKID_PCIE_COMB 45 +#define CLKID_PARSER 46 +#define CLKID_USB 47 +#define CLKID_PCIE_PHY 48 +#define CLKID_AHB_ARB0 49 +#define CLKID_AHB_DATA_BUS 50 +#define CLKID_AHB_CTRL_BUS 51 +#define CLKID_HTX_HDCP22 52 +#define CLKID_HTX_PCLK 53 +#define CLKID_BT656 54 +#define CLKID_USB1_DDR_BRIDGE 55 +#define CLKID_MMC_PCLK 56 +#define CLKID_UART2 57 +#define CLKID_VPU_INTR 58 +#define CLKID_GIC 59 +#define CLKID_SD_EMMC_A_CLK0 60 +#define CLKID_SD_EMMC_B_CLK0 61 +#define CLKID_SD_EMMC_C_CLK0 62 +#define CLKID_HIFI_PLL 74 +#define CLKID_VCLK2_VENCI0 80 +#define CLKID_VCLK2_VENCI1 81 +#define CLKID_VCLK2_VENCP0 82 +#define CLKID_VCLK2_VENCP1 83 +#define CLKID_VCLK2_VENCT0 84 +#define CLKID_VCLK2_VENCT1 85 +#define CLKID_VCLK2_OTHER 86 +#define CLKID_VCLK2_ENCI 87 +#define CLKID_VCLK2_ENCP 88 +#define CLKID_DAC_CLK 89 +#define CLKID_AOCLK 90 +#define CLKID_IEC958 91 +#define CLKID_ENC480P 92 +#define CLKID_RNG1 93 +#define CLKID_VCLK2_ENCT 94 +#define CLKID_VCLK2_ENCL 95 +#define CLKID_VCLK2_VENCLMMC 96 +#define CLKID_VCLK2_VENCL 97 +#define CLKID_VCLK2_OTHER1 98 +#define CLKID_FCLK_DIV2P5 99 +#define CLKID_DMA 105 +#define CLKID_EFUSE 106 +#define CLKID_ROM_BOOT 107 +#define CLKID_RESET_SEC 108 +#define CLKID_SEC_AHB_APB3 109 +#define CLKID_VPU_0_SEL 110 +#define CLKID_VPU_0 112 +#define CLKID_VPU_1_SEL 113 +#define CLKID_VPU_1 115 +#define CLKID_VPU 116 +#define CLKID_VAPB_0_SEL 117 +#define CLKID_VAPB_0 119 +#define CLKID_VAPB_1_SEL 120 +#define CLKID_VAPB_1 122 +#define CLKID_VAPB_SEL 123 +#define CLKID_VAPB 124 +#define CLKID_HDMI_PLL 128 +#define CLKID_VID_PLL 129 +#define CLKID_VCLK 138 +#define CLKID_VCLK2 139 +#define CLKID_VCLK_DIV1 148 +#define CLKID_VCLK_DIV2 149 +#define CLKID_VCLK_DIV4 150 +#define CLKID_VCLK_DIV6 151 +#define CLKID_VCLK_DIV12 152 +#define CLKID_VCLK2_DIV1 153 +#define CLKID_VCLK2_DIV2 154 +#define CLKID_VCLK2_DIV4 155 +#define CLKID_VCLK2_DIV6 156 +#define CLKID_VCLK2_DIV12 157 +#define CLKID_CTS_ENCI 162 +#define CLKID_CTS_ENCP 163 +#define CLKID_CTS_VDAC 164 +#define CLKID_HDMI_TX 165 +#define CLKID_HDMI 168 +#define CLKID_MALI_0_SEL 169 +#define CLKID_MALI_0 171 +#define CLKID_MALI_1_SEL 172 +#define CLKID_MALI_1 174 +#define CLKID_MALI 175 +#define CLKID_MPLL_50M 177 +#define CLKID_CPU_CLK 187 +#define CLKID_PCIE_PLL 201 +#define CLKID_VDEC_1 204 +#define CLKID_VDEC_HEVC 207 +#define CLKID_VDEC_HEVCF 210 +#define CLKID_TS 212 +#define CLKID_CPUB_CLK 224 +#define CLKID_GP1_PLL 243 +#define CLKID_DSU_CLK 252 +#define CLKID_CPU1_CLK 253 +#define CLKID_CPU2_CLK 254 +#define CLKID_CPU3_CLK 255 +#define CLKID_SPICC0_SCLK 258 +#define CLKID_SPICC1_SCLK 261 +#define CLKID_NNA_AXI_CLK 264 +#define CLKID_NNA_CORE_CLK 267 + +#endif /* __G12A_CLKC_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/gxbb-aoclkc.h b/roms/u-boot/include/dt-bindings/clock/gxbb-aoclkc.h new file mode 100644 index 000000000..ec3b26319 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/gxbb-aoclkc.h @@ -0,0 +1,74 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + * The full GNU General Public License is included in this distribution + * in the file called COPYING. + * + * BSD LICENSE + * + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK +#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK + +#define CLKID_AO_REMOTE 0 +#define CLKID_AO_I2C_MASTER 1 +#define CLKID_AO_I2C_SLAVE 2 +#define CLKID_AO_UART1 3 +#define CLKID_AO_UART2 4 +#define CLKID_AO_IR_BLASTER 5 +#define CLKID_AO_CEC_32K 6 +#define CLKID_AO_CTS_OSCIN 7 +#define CLKID_AO_32K_PRE 8 +#define CLKID_AO_32K_DIV 9 +#define CLKID_AO_32K_SEL 10 +#define CLKID_AO_32K 11 +#define CLKID_AO_CTS_RTC_OSCIN 12 +#define CLKID_AO_CLK81 13 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/gxbb-clkc.h b/roms/u-boot/include/dt-bindings/clock/gxbb-clkc.h new file mode 100644 index 000000000..4073eb7a9 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/gxbb-clkc.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * GXBB clock tree IDs + */ + +#ifndef __GXBB_CLKC_H +#define __GXBB_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_HDMI_PLL 2 +#define CLKID_FIXED_PLL 3 +#define CLKID_FCLK_DIV2 4 +#define CLKID_FCLK_DIV3 5 +#define CLKID_FCLK_DIV4 6 +#define CLKID_FCLK_DIV5 7 +#define CLKID_FCLK_DIV7 8 +#define CLKID_GP0_PLL 9 +#define CLKID_CLK81 12 +#define CLKID_MPLL0 13 +#define CLKID_MPLL1 14 +#define CLKID_MPLL2 15 +#define CLKID_DDR 16 +#define CLKID_DOS 17 +#define CLKID_ISA 18 +#define CLKID_PL301 19 +#define CLKID_PERIPHS 20 +#define CLKID_SPICC 21 +#define CLKID_I2C 22 +#define CLKID_SAR_ADC 23 +#define CLKID_SMART_CARD 24 +#define CLKID_RNG0 25 +#define CLKID_UART0 26 +#define CLKID_SDHC 27 +#define CLKID_STREAM 28 +#define CLKID_ASYNC_FIFO 29 +#define CLKID_SDIO 30 +#define CLKID_ABUF 31 +#define CLKID_HIU_IFACE 32 +#define CLKID_ASSIST_MISC 33 +#define CLKID_SPI 34 +#define CLKID_ETH 36 +#define CLKID_I2S_SPDIF 35 +#define CLKID_DEMUX 37 +#define CLKID_AIU_GLUE 38 +#define CLKID_IEC958 39 +#define CLKID_I2S_OUT 40 +#define CLKID_AMCLK 41 +#define CLKID_AIFIFO2 42 +#define CLKID_MIXER 43 +#define CLKID_MIXER_IFACE 44 +#define CLKID_ADC 45 +#define CLKID_BLKMV 46 +#define CLKID_AIU 47 +#define CLKID_UART1 48 +#define CLKID_G2D 49 +#define CLKID_USB0 50 +#define CLKID_USB1 51 +#define CLKID_RESET 52 +#define CLKID_NAND 53 +#define CLKID_DOS_PARSER 54 +#define CLKID_USB 55 +#define CLKID_VDIN1 56 +#define CLKID_AHB_ARB0 57 +#define CLKID_EFUSE 58 +#define CLKID_BOOT_ROM 59 +#define CLKID_AHB_DATA_BUS 60 +#define CLKID_AHB_CTRL_BUS 61 +#define CLKID_HDMI_INTR_SYNC 62 +#define CLKID_HDMI_PCLK 63 +#define CLKID_USB1_DDR_BRIDGE 64 +#define CLKID_USB0_DDR_BRIDGE 65 +#define CLKID_MMC_PCLK 66 +#define CLKID_DVIN 67 +#define CLKID_UART2 68 +#define CLKID_SANA 69 +#define CLKID_VPU_INTR 70 +#define CLKID_SEC_AHB_AHB3_BRIDGE 71 +#define CLKID_CLK81_A53 72 +#define CLKID_VCLK2_VENCI0 73 +#define CLKID_VCLK2_VENCI1 74 +#define CLKID_VCLK2_VENCP0 75 +#define CLKID_VCLK2_VENCP1 76 +#define CLKID_GCLK_VENCI_INT0 77 +#define CLKID_GCLK_VENCI_INT 78 +#define CLKID_DAC_CLK 79 +#define CLKID_AOCLK_GATE 80 +#define CLKID_IEC958_GATE 81 +#define CLKID_ENC480P 82 +#define CLKID_RNG1 83 +#define CLKID_GCLK_VENCI_INT1 84 +#define CLKID_VCLK2_VENCLMCC 85 +#define CLKID_VCLK2_VENCL 86 +#define CLKID_VCLK_OTHER 87 +#define CLKID_EDP 88 +#define CLKID_AO_MEDIA_CPU 89 +#define CLKID_AO_AHB_SRAM 90 +#define CLKID_AO_AHB_BUS 91 +#define CLKID_AO_IFACE 92 +#define CLKID_AO_I2C 93 +#define CLKID_SD_EMMC_A 94 +#define CLKID_SD_EMMC_B 95 +#define CLKID_SD_EMMC_C 96 +#define CLKID_SAR_ADC_CLK 97 +#define CLKID_SAR_ADC_SEL 98 +#define CLKID_MALI_0_SEL 100 +#define CLKID_MALI_0 102 +#define CLKID_MALI_1_SEL 103 +#define CLKID_MALI_1 105 +#define CLKID_MALI 106 +#define CLKID_CTS_AMCLK 107 +#define CLKID_CTS_MCLK_I958 110 +#define CLKID_CTS_I958 113 +#define CLKID_32K_CLK 114 +#define CLKID_SD_EMMC_A_CLK0 119 +#define CLKID_SD_EMMC_B_CLK0 122 +#define CLKID_SD_EMMC_C_CLK0 125 +#define CLKID_VPU_0_SEL 126 +#define CLKID_VPU_0 128 +#define CLKID_VPU_1_SEL 129 +#define CLKID_VPU_1 131 +#define CLKID_VPU 132 +#define CLKID_VAPB_0_SEL 133 +#define CLKID_VAPB_0 135 +#define CLKID_VAPB_1_SEL 136 +#define CLKID_VAPB_1 138 +#define CLKID_VAPB_SEL 139 +#define CLKID_VAPB 140 +#define CLKID_VDEC_1 153 +#define CLKID_VDEC_HEVC 156 +#define CLKID_GEN_CLK 159 +#define CLKID_VID_PLL 166 +#define CLKID_VCLK 175 +#define CLKID_VCLK2 176 +#define CLKID_VCLK_DIV1 185 +#define CLKID_VCLK_DIV2 186 +#define CLKID_VCLK_DIV4 187 +#define CLKID_VCLK_DIV6 188 +#define CLKID_VCLK_DIV12 189 +#define CLKID_VCLK2_DIV1 190 +#define CLKID_VCLK2_DIV2 191 +#define CLKID_VCLK2_DIV4 192 +#define CLKID_VCLK2_DIV6 193 +#define CLKID_VCLK2_DIV12 194 +#define CLKID_CTS_ENCI 199 +#define CLKID_CTS_ENCP 200 +#define CLKID_CTS_VDAC 201 +#define CLKID_HDMI_TX 202 +#define CLKID_HDMI 205 +#define CLKID_ACODEC 206 + +#endif /* __GXBB_CLKC_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/hi3660-clock.h b/roms/u-boot/include/dt-bindings/clock/hi3660-clock.h new file mode 100644 index 000000000..e1374e180 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/hi3660-clock.h @@ -0,0 +1,214 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2016-2017 Linaro Ltd. + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + */ + +#ifndef __DTS_HI3660_CLOCK_H +#define __DTS_HI3660_CLOCK_H + +/* fixed rate clocks */ +#define HI3660_CLKIN_SYS 0 +#define HI3660_CLKIN_REF 1 +#define HI3660_CLK_FLL_SRC 2 +#define HI3660_CLK_PPLL0 3 +#define HI3660_CLK_PPLL1 4 +#define HI3660_CLK_PPLL2 5 +#define HI3660_CLK_PPLL3 6 +#define HI3660_CLK_SCPLL 7 +#define HI3660_PCLK 8 +#define HI3660_CLK_UART0_DBG 9 +#define HI3660_CLK_UART6 10 +#define HI3660_OSC32K 11 +#define HI3660_OSC19M 12 +#define HI3660_CLK_480M 13 +#define HI3660_CLK_INV 14 + +/* clk in crgctrl */ +#define HI3660_FACTOR_UART3 15 +#define HI3660_CLK_FACTOR_MMC 16 +#define HI3660_CLK_GATE_I2C0 17 +#define HI3660_CLK_GATE_I2C1 18 +#define HI3660_CLK_GATE_I2C2 19 +#define HI3660_CLK_GATE_I2C6 20 +#define HI3660_CLK_DIV_SYSBUS 21 +#define HI3660_CLK_DIV_320M 22 +#define HI3660_CLK_DIV_A53 23 +#define HI3660_CLK_GATE_SPI0 24 +#define HI3660_CLK_GATE_SPI2 25 +#define HI3660_PCIEPHY_REF 26 +#define HI3660_CLK_ABB_USB 27 +#define HI3660_HCLK_GATE_SDIO0 28 +#define HI3660_HCLK_GATE_SD 29 +#define HI3660_CLK_GATE_AOMM 30 +#define HI3660_PCLK_GPIO0 31 +#define HI3660_PCLK_GPIO1 32 +#define HI3660_PCLK_GPIO2 33 +#define HI3660_PCLK_GPIO3 34 +#define HI3660_PCLK_GPIO4 35 +#define HI3660_PCLK_GPIO5 36 +#define HI3660_PCLK_GPIO6 37 +#define HI3660_PCLK_GPIO7 38 +#define HI3660_PCLK_GPIO8 39 +#define HI3660_PCLK_GPIO9 40 +#define HI3660_PCLK_GPIO10 41 +#define HI3660_PCLK_GPIO11 42 +#define HI3660_PCLK_GPIO12 43 +#define HI3660_PCLK_GPIO13 44 +#define HI3660_PCLK_GPIO14 45 +#define HI3660_PCLK_GPIO15 46 +#define HI3660_PCLK_GPIO16 47 +#define HI3660_PCLK_GPIO17 48 +#define HI3660_PCLK_GPIO18 49 +#define HI3660_PCLK_GPIO19 50 +#define HI3660_PCLK_GPIO20 51 +#define HI3660_PCLK_GPIO21 52 +#define HI3660_CLK_GATE_SPI3 53 +#define HI3660_CLK_GATE_I2C7 54 +#define HI3660_CLK_GATE_I2C3 55 +#define HI3660_CLK_GATE_SPI1 56 +#define HI3660_CLK_GATE_UART1 57 +#define HI3660_CLK_GATE_UART2 58 +#define HI3660_CLK_GATE_UART4 59 +#define HI3660_CLK_GATE_UART5 60 +#define HI3660_CLK_GATE_I2C4 61 +#define HI3660_CLK_GATE_DMAC 62 +#define HI3660_PCLK_GATE_DSS 63 +#define HI3660_ACLK_GATE_DSS 64 +#define HI3660_CLK_GATE_LDI1 65 +#define HI3660_CLK_GATE_LDI0 66 +#define HI3660_CLK_GATE_VIVOBUS 67 +#define HI3660_CLK_GATE_EDC0 68 +#define HI3660_CLK_GATE_TXDPHY0_CFG 69 +#define HI3660_CLK_GATE_TXDPHY0_REF 70 +#define HI3660_CLK_GATE_TXDPHY1_CFG 71 +#define HI3660_CLK_GATE_TXDPHY1_REF 72 +#define HI3660_ACLK_GATE_USB3OTG 73 +#define HI3660_CLK_GATE_SPI4 74 +#define HI3660_CLK_GATE_SD 75 +#define HI3660_CLK_GATE_SDIO0 76 +#define HI3660_CLK_GATE_UFS_SUBSYS 77 +#define HI3660_PCLK_GATE_DSI0 78 +#define HI3660_PCLK_GATE_DSI1 79 +#define HI3660_ACLK_GATE_PCIE 80 +#define HI3660_PCLK_GATE_PCIE_SYS 81 +#define HI3660_CLK_GATE_PCIEAUX 82 +#define HI3660_PCLK_GATE_PCIE_PHY 83 +#define HI3660_CLK_ANDGT_LDI0 84 +#define HI3660_CLK_ANDGT_LDI1 85 +#define HI3660_CLK_ANDGT_EDC0 86 +#define HI3660_CLK_GATE_UFSPHY_GT 87 +#define HI3660_CLK_ANDGT_MMC 88 +#define HI3660_CLK_ANDGT_SD 89 +#define HI3660_CLK_A53HPM_ANDGT 90 +#define HI3660_CLK_ANDGT_SDIO 91 +#define HI3660_CLK_ANDGT_UART0 92 +#define HI3660_CLK_ANDGT_UART1 93 +#define HI3660_CLK_ANDGT_UARTH 94 +#define HI3660_CLK_ANDGT_SPI 95 +#define HI3660_CLK_VIVOBUS_ANDGT 96 +#define HI3660_CLK_AOMM_ANDGT 97 +#define HI3660_CLK_320M_PLL_GT 98 +#define HI3660_AUTODIV_EMMC0BUS 99 +#define HI3660_AUTODIV_SYSBUS 100 +#define HI3660_CLK_GATE_UFSPHY_CFG 101 +#define HI3660_CLK_GATE_UFSIO_REF 102 +#define HI3660_CLK_MUX_SYSBUS 103 +#define HI3660_CLK_MUX_UART0 104 +#define HI3660_CLK_MUX_UART1 105 +#define HI3660_CLK_MUX_UARTH 106 +#define HI3660_CLK_MUX_SPI 107 +#define HI3660_CLK_MUX_I2C 108 +#define HI3660_CLK_MUX_MMC_PLL 109 +#define HI3660_CLK_MUX_LDI1 110 +#define HI3660_CLK_MUX_LDI0 111 +#define HI3660_CLK_MUX_SD_PLL 112 +#define HI3660_CLK_MUX_SD_SYS 113 +#define HI3660_CLK_MUX_EDC0 114 +#define HI3660_CLK_MUX_SDIO_SYS 115 +#define HI3660_CLK_MUX_SDIO_PLL 116 +#define HI3660_CLK_MUX_VIVOBUS 117 +#define HI3660_CLK_MUX_A53HPM 118 +#define HI3660_CLK_MUX_320M 119 +#define HI3660_CLK_MUX_IOPERI 120 +#define HI3660_CLK_DIV_UART0 121 +#define HI3660_CLK_DIV_UART1 122 +#define HI3660_CLK_DIV_UARTH 123 +#define HI3660_CLK_DIV_MMC 124 +#define HI3660_CLK_DIV_SD 125 +#define HI3660_CLK_DIV_EDC0 126 +#define HI3660_CLK_DIV_LDI0 127 +#define HI3660_CLK_DIV_SDIO 128 +#define HI3660_CLK_DIV_LDI1 129 +#define HI3660_CLK_DIV_SPI 130 +#define HI3660_CLK_DIV_VIVOBUS 131 +#define HI3660_CLK_DIV_I2C 132 +#define HI3660_CLK_DIV_UFSPHY 133 +#define HI3660_CLK_DIV_CFGBUS 134 +#define HI3660_CLK_DIV_MMC0BUS 135 +#define HI3660_CLK_DIV_MMC1BUS 136 +#define HI3660_CLK_DIV_UFSPERI 137 +#define HI3660_CLK_DIV_AOMM 138 +#define HI3660_CLK_DIV_IOPERI 139 +#define HI3660_VENC_VOLT_HOLD 140 +#define HI3660_PERI_VOLT_HOLD 141 +#define HI3660_CLK_GATE_VENC 142 +#define HI3660_CLK_GATE_VDEC 143 +#define HI3660_CLK_ANDGT_VENC 144 +#define HI3660_CLK_ANDGT_VDEC 145 +#define HI3660_CLK_MUX_VENC 146 +#define HI3660_CLK_MUX_VDEC 147 +#define HI3660_CLK_DIV_VENC 148 +#define HI3660_CLK_DIV_VDEC 149 +#define HI3660_CLK_FAC_ISP_SNCLK 150 +#define HI3660_CLK_GATE_ISP_SNCLK0 151 +#define HI3660_CLK_GATE_ISP_SNCLK1 152 +#define HI3660_CLK_GATE_ISP_SNCLK2 153 +#define HI3660_CLK_ANGT_ISP_SNCLK 154 +#define HI3660_CLK_MUX_ISP_SNCLK 155 +#define HI3660_CLK_DIV_ISP_SNCLK 156 + +/* clk in pmuctrl */ +#define HI3660_GATE_ABB_192 0 + +/* clk in pctrl */ +#define HI3660_GATE_UFS_TCXO_EN 0 +#define HI3660_GATE_USB_TCXO_EN 1 + +/* clk in sctrl */ +#define HI3660_PCLK_AO_GPIO0 0 +#define HI3660_PCLK_AO_GPIO1 1 +#define HI3660_PCLK_AO_GPIO2 2 +#define HI3660_PCLK_AO_GPIO3 3 +#define HI3660_PCLK_AO_GPIO4 4 +#define HI3660_PCLK_AO_GPIO5 5 +#define HI3660_PCLK_AO_GPIO6 6 +#define HI3660_PCLK_GATE_MMBUF 7 +#define HI3660_CLK_GATE_DSS_AXI_MM 8 +#define HI3660_PCLK_MMBUF_ANDGT 9 +#define HI3660_CLK_MMBUF_PLL_ANDGT 10 +#define HI3660_CLK_FLL_MMBUF_ANDGT 11 +#define HI3660_CLK_SYS_MMBUF_ANDGT 12 +#define HI3660_CLK_GATE_PCIEPHY_GT 13 +#define HI3660_ACLK_MUX_MMBUF 14 +#define HI3660_CLK_SW_MMBUF 15 +#define HI3660_CLK_DIV_AOBUS 16 +#define HI3660_PCLK_DIV_MMBUF 17 +#define HI3660_ACLK_DIV_MMBUF 18 +#define HI3660_CLK_DIV_PCIEPHY 19 + +/* clk in iomcu */ +#define HI3660_CLK_I2C0_IOMCU 0 +#define HI3660_CLK_I2C1_IOMCU 1 +#define HI3660_CLK_I2C2_IOMCU 2 +#define HI3660_CLK_I2C6_IOMCU 3 +#define HI3660_CLK_IOMCU_PERI0 4 + +/* clk in stub clock */ +#define HI3660_CLK_STUB_CLUSTER0 0 +#define HI3660_CLK_STUB_CLUSTER1 1 +#define HI3660_CLK_STUB_GPU 2 +#define HI3660_CLK_STUB_DDR 3 +#define HI3660_CLK_STUB_NUM 4 + +#endif /* __DTS_HI3660_CLOCK_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/hi6220-clock.h b/roms/u-boot/include/dt-bindings/clock/hi6220-clock.h new file mode 100644 index 000000000..70ee3833a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/hi6220-clock.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015 Hisilicon Limited. + * + * Author: Bintian Wang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_HI6220_H +#define __DT_BINDINGS_CLOCK_HI6220_H + +/* clk in Hi6220 AO (always on) controller */ +#define HI6220_NONE_CLOCK 0 + +/* fixed rate clocks */ +#define HI6220_REF32K 1 +#define HI6220_CLK_TCXO 2 +#define HI6220_MMC1_PAD 3 +#define HI6220_MMC2_PAD 4 +#define HI6220_MMC0_PAD 5 +#define HI6220_PLL_BBP 6 +#define HI6220_PLL_GPU 7 +#define HI6220_PLL1_DDR 8 +#define HI6220_PLL_SYS 9 +#define HI6220_PLL_SYS_MEDIA 10 +#define HI6220_DDR_SRC 11 +#define HI6220_PLL_MEDIA 12 +#define HI6220_PLL_DDR 13 + +/* fixed factor clocks */ +#define HI6220_300M 14 +#define HI6220_150M 15 +#define HI6220_PICOPHY_SRC 16 +#define HI6220_MMC0_SRC_SEL 17 +#define HI6220_MMC1_SRC_SEL 18 +#define HI6220_MMC2_SRC_SEL 19 +#define HI6220_VPU_CODEC 20 +#define HI6220_MMC0_SMP 21 +#define HI6220_MMC1_SMP 22 +#define HI6220_MMC2_SMP 23 + +/* gate clocks */ +#define HI6220_WDT0_PCLK 24 +#define HI6220_WDT1_PCLK 25 +#define HI6220_WDT2_PCLK 26 +#define HI6220_TIMER0_PCLK 27 +#define HI6220_TIMER1_PCLK 28 +#define HI6220_TIMER2_PCLK 29 +#define HI6220_TIMER3_PCLK 30 +#define HI6220_TIMER4_PCLK 31 +#define HI6220_TIMER5_PCLK 32 +#define HI6220_TIMER6_PCLK 33 +#define HI6220_TIMER7_PCLK 34 +#define HI6220_TIMER8_PCLK 35 +#define HI6220_UART0_PCLK 36 + +#define HI6220_AO_NR_CLKS 37 + +/* clk in Hi6220 systrl */ +/* gate clock */ +#define HI6220_MMC0_CLK 1 +#define HI6220_MMC0_CIUCLK 2 +#define HI6220_MMC1_CLK 3 +#define HI6220_MMC1_CIUCLK 4 +#define HI6220_MMC2_CLK 5 +#define HI6220_MMC2_CIUCLK 6 +#define HI6220_USBOTG_HCLK 7 +#define HI6220_CLK_PICOPHY 8 +#define HI6220_HIFI 9 +#define HI6220_DACODEC_PCLK 10 +#define HI6220_EDMAC_ACLK 11 +#define HI6220_CS_ATB 12 +#define HI6220_I2C0_CLK 13 +#define HI6220_I2C1_CLK 14 +#define HI6220_I2C2_CLK 15 +#define HI6220_I2C3_CLK 16 +#define HI6220_UART1_PCLK 17 +#define HI6220_UART2_PCLK 18 +#define HI6220_UART3_PCLK 19 +#define HI6220_UART4_PCLK 20 +#define HI6220_SPI_CLK 21 +#define HI6220_TSENSOR_CLK 22 +#define HI6220_MMU_CLK 23 +#define HI6220_HIFI_SEL 24 +#define HI6220_MMC0_SYSPLL 25 +#define HI6220_MMC1_SYSPLL 26 +#define HI6220_MMC2_SYSPLL 27 +#define HI6220_MMC0_SEL 28 +#define HI6220_MMC1_SEL 29 +#define HI6220_BBPPLL_SEL 30 +#define HI6220_MEDIA_PLL_SRC 31 +#define HI6220_MMC2_SEL 32 +#define HI6220_CS_ATB_SYSPLL 33 + +/* mux clocks */ +#define HI6220_MMC0_SRC 34 +#define HI6220_MMC0_SMP_IN 35 +#define HI6220_MMC1_SRC 36 +#define HI6220_MMC1_SMP_IN 37 +#define HI6220_MMC2_SRC 38 +#define HI6220_MMC2_SMP_IN 39 +#define HI6220_HIFI_SRC 40 +#define HI6220_UART1_SRC 41 +#define HI6220_UART2_SRC 42 +#define HI6220_UART3_SRC 43 +#define HI6220_UART4_SRC 44 +#define HI6220_MMC0_MUX0 45 +#define HI6220_MMC1_MUX0 46 +#define HI6220_MMC2_MUX0 47 +#define HI6220_MMC0_MUX1 48 +#define HI6220_MMC1_MUX1 49 +#define HI6220_MMC2_MUX1 50 + +/* divider clocks */ +#define HI6220_CLK_BUS 51 +#define HI6220_MMC0_DIV 52 +#define HI6220_MMC1_DIV 53 +#define HI6220_MMC2_DIV 54 +#define HI6220_HIFI_DIV 55 +#define HI6220_BBPPLL0_DIV 56 +#define HI6220_CS_DAPB 57 +#define HI6220_CS_ATB_DIV 58 + +#define HI6220_SYS_NR_CLKS 59 + +/* clk in Hi6220 media controller */ +/* gate clocks */ +#define HI6220_DSI_PCLK 1 +#define HI6220_G3D_PCLK 2 +#define HI6220_ACLK_CODEC_VPU 3 +#define HI6220_ISP_SCLK 4 +#define HI6220_ADE_CORE 5 +#define HI6220_MED_MMU 6 +#define HI6220_CFG_CSI4PHY 7 +#define HI6220_CFG_CSI2PHY 8 +#define HI6220_ISP_SCLK_GATE 9 +#define HI6220_ISP_SCLK_GATE1 10 +#define HI6220_ADE_CORE_GATE 11 +#define HI6220_CODEC_VPU_GATE 12 +#define HI6220_MED_SYSPLL 13 + +/* mux clocks */ +#define HI6220_1440_1200 14 +#define HI6220_1000_1200 15 +#define HI6220_1000_1440 16 + +/* divider clocks */ +#define HI6220_CODEC_JPEG 17 +#define HI6220_ISP_SCLK_SRC 18 +#define HI6220_ISP_SCLK1 19 +#define HI6220_ADE_CORE_SRC 20 +#define HI6220_ADE_PIX_SRC 21 +#define HI6220_G3D_CLK 22 +#define HI6220_CODEC_VPU_SRC 23 + +#define HI6220_MEDIA_NR_CLKS 24 + +/* clk in Hi6220 power controller */ +/* gate clocks */ +#define HI6220_PLL_GPU_GATE 1 +#define HI6220_PLL1_DDR_GATE 2 +#define HI6220_PLL_DDR_GATE 3 +#define HI6220_PLL_MEDIA_GATE 4 +#define HI6220_PLL0_BBP_GATE 5 + +/* divider clocks */ +#define HI6220_DDRC_SRC 6 +#define HI6220_DDRC_AXI1 7 + +#define HI6220_POWER_NR_CLKS 8 +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/histb-clock.h b/roms/u-boot/include/dt-bindings/clock/histb-clock.h new file mode 100644 index 000000000..136de2473 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/histb-clock.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __DTS_HISTB_CLOCK_H +#define __DTS_HISTB_CLOCK_H + +/* clocks provided by core CRG */ +#define HISTB_OSC_CLK 0 +#define HISTB_APB_CLK 1 +#define HISTB_AHB_CLK 2 +#define HISTB_UART1_CLK 3 +#define HISTB_UART2_CLK 4 +#define HISTB_UART3_CLK 5 +#define HISTB_I2C0_CLK 6 +#define HISTB_I2C1_CLK 7 +#define HISTB_I2C2_CLK 8 +#define HISTB_I2C3_CLK 9 +#define HISTB_I2C4_CLK 10 +#define HISTB_I2C5_CLK 11 +#define HISTB_SPI0_CLK 12 +#define HISTB_SPI1_CLK 13 +#define HISTB_SPI2_CLK 14 +#define HISTB_SCI_CLK 15 +#define HISTB_FMC_CLK 16 +#define HISTB_MMC_BIU_CLK 17 +#define HISTB_MMC_CIU_CLK 18 +#define HISTB_MMC_DRV_CLK 19 +#define HISTB_MMC_SAMPLE_CLK 20 +#define HISTB_SDIO0_BIU_CLK 21 +#define HISTB_SDIO0_CIU_CLK 22 +#define HISTB_SDIO0_DRV_CLK 23 +#define HISTB_SDIO0_SAMPLE_CLK 24 +#define HISTB_PCIE_AUX_CLK 25 +#define HISTB_PCIE_PIPE_CLK 26 +#define HISTB_PCIE_SYS_CLK 27 +#define HISTB_PCIE_BUS_CLK 28 +#define HISTB_ETH0_MAC_CLK 29 +#define HISTB_ETH0_MACIF_CLK 30 +#define HISTB_ETH1_MAC_CLK 31 +#define HISTB_ETH1_MACIF_CLK 32 +#define HISTB_COMBPHY1_CLK 33 +#define HISTB_USB2_BUS_CLK 34 +#define HISTB_USB2_PHY_CLK 35 +#define HISTB_USB2_UTMI_CLK 36 +#define HISTB_USB2_12M_CLK 37 +#define HISTB_USB2_48M_CLK 38 +#define HISTB_USB2_OTG_UTMI_CLK 39 +#define HISTB_USB2_PHY1_REF_CLK 40 +#define HISTB_USB2_PHY2_REF_CLK 41 +#define HISTB_COMBPHY0_CLK 42 +#define HISTB_USB3_BUS_CLK 43 +#define HISTB_USB3_UTMI_CLK 44 +#define HISTB_USB3_PIPE_CLK 45 +#define HISTB_USB3_SUSPEND_CLK 46 +#define HISTB_USB3_BUS_CLK1 47 +#define HISTB_USB3_UTMI_CLK1 48 +#define HISTB_USB3_PIPE_CLK1 49 +#define HISTB_USB3_SUSPEND_CLK1 50 + +/* clocks provided by mcu CRG */ +#define HISTB_MCE_CLK 1 +#define HISTB_IR_CLK 2 +#define HISTB_TIMER01_CLK 3 +#define HISTB_LEDC_CLK 4 +#define HISTB_UART0_CLK 5 +#define HISTB_LSADC_CLK 6 + +#endif /* __DTS_HISTB_CLOCK_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/imx5-clock.h b/roms/u-boot/include/dt-bindings/clock/imx5-clock.h new file mode 100644 index 000000000..d382fc71a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/imx5-clock.h @@ -0,0 +1,219 @@ +/* + * Copyright 2013 Lucas Stach, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX5_H +#define __DT_BINDINGS_CLOCK_IMX5_H + +#define IMX5_CLK_DUMMY 0 +#define IMX5_CLK_CKIL 1 +#define IMX5_CLK_OSC 2 +#define IMX5_CLK_CKIH1 3 +#define IMX5_CLK_CKIH2 4 +#define IMX5_CLK_AHB 5 +#define IMX5_CLK_IPG 6 +#define IMX5_CLK_AXI_A 7 +#define IMX5_CLK_AXI_B 8 +#define IMX5_CLK_UART_PRED 9 +#define IMX5_CLK_UART_ROOT 10 +#define IMX5_CLK_ESDHC_A_PRED 11 +#define IMX5_CLK_ESDHC_B_PRED 12 +#define IMX5_CLK_ESDHC_C_SEL 13 +#define IMX5_CLK_ESDHC_D_SEL 14 +#define IMX5_CLK_EMI_SEL 15 +#define IMX5_CLK_EMI_SLOW_PODF 16 +#define IMX5_CLK_NFC_PODF 17 +#define IMX5_CLK_ECSPI_PRED 18 +#define IMX5_CLK_ECSPI_PODF 19 +#define IMX5_CLK_USBOH3_PRED 20 +#define IMX5_CLK_USBOH3_PODF 21 +#define IMX5_CLK_USB_PHY_PRED 22 +#define IMX5_CLK_USB_PHY_PODF 23 +#define IMX5_CLK_CPU_PODF 24 +#define IMX5_CLK_DI_PRED 25 +#define IMX5_CLK_TVE_SEL 27 +#define IMX5_CLK_UART1_IPG_GATE 28 +#define IMX5_CLK_UART1_PER_GATE 29 +#define IMX5_CLK_UART2_IPG_GATE 30 +#define IMX5_CLK_UART2_PER_GATE 31 +#define IMX5_CLK_UART3_IPG_GATE 32 +#define IMX5_CLK_UART3_PER_GATE 33 +#define IMX5_CLK_I2C1_GATE 34 +#define IMX5_CLK_I2C2_GATE 35 +#define IMX5_CLK_GPT_IPG_GATE 36 +#define IMX5_CLK_PWM1_IPG_GATE 37 +#define IMX5_CLK_PWM1_HF_GATE 38 +#define IMX5_CLK_PWM2_IPG_GATE 39 +#define IMX5_CLK_PWM2_HF_GATE 40 +#define IMX5_CLK_GPT_HF_GATE 41 +#define IMX5_CLK_FEC_GATE 42 +#define IMX5_CLK_USBOH3_PER_GATE 43 +#define IMX5_CLK_ESDHC1_IPG_GATE 44 +#define IMX5_CLK_ESDHC2_IPG_GATE 45 +#define IMX5_CLK_ESDHC3_IPG_GATE 46 +#define IMX5_CLK_ESDHC4_IPG_GATE 47 +#define IMX5_CLK_SSI1_IPG_GATE 48 +#define IMX5_CLK_SSI2_IPG_GATE 49 +#define IMX5_CLK_SSI3_IPG_GATE 50 +#define IMX5_CLK_ECSPI1_IPG_GATE 51 +#define IMX5_CLK_ECSPI1_PER_GATE 52 +#define IMX5_CLK_ECSPI2_IPG_GATE 53 +#define IMX5_CLK_ECSPI2_PER_GATE 54 +#define IMX5_CLK_CSPI_IPG_GATE 55 +#define IMX5_CLK_SDMA_GATE 56 +#define IMX5_CLK_EMI_SLOW_GATE 57 +#define IMX5_CLK_IPU_SEL 58 +#define IMX5_CLK_IPU_GATE 59 +#define IMX5_CLK_NFC_GATE 60 +#define IMX5_CLK_IPU_DI1_GATE 61 +#define IMX5_CLK_VPU_SEL 62 +#define IMX5_CLK_VPU_GATE 63 +#define IMX5_CLK_VPU_REFERENCE_GATE 64 +#define IMX5_CLK_UART4_IPG_GATE 65 +#define IMX5_CLK_UART4_PER_GATE 66 +#define IMX5_CLK_UART5_IPG_GATE 67 +#define IMX5_CLK_UART5_PER_GATE 68 +#define IMX5_CLK_TVE_GATE 69 +#define IMX5_CLK_TVE_PRED 70 +#define IMX5_CLK_ESDHC1_PER_GATE 71 +#define IMX5_CLK_ESDHC2_PER_GATE 72 +#define IMX5_CLK_ESDHC3_PER_GATE 73 +#define IMX5_CLK_ESDHC4_PER_GATE 74 +#define IMX5_CLK_USB_PHY_GATE 75 +#define IMX5_CLK_HSI2C_GATE 76 +#define IMX5_CLK_MIPI_HSC1_GATE 77 +#define IMX5_CLK_MIPI_HSC2_GATE 78 +#define IMX5_CLK_MIPI_ESC_GATE 79 +#define IMX5_CLK_MIPI_HSP_GATE 80 +#define IMX5_CLK_LDB_DI1_DIV_3_5 81 +#define IMX5_CLK_LDB_DI1_DIV 82 +#define IMX5_CLK_LDB_DI0_DIV_3_5 83 +#define IMX5_CLK_LDB_DI0_DIV 84 +#define IMX5_CLK_LDB_DI1_GATE 85 +#define IMX5_CLK_CAN2_SERIAL_GATE 86 +#define IMX5_CLK_CAN2_IPG_GATE 87 +#define IMX5_CLK_I2C3_GATE 88 +#define IMX5_CLK_LP_APM 89 +#define IMX5_CLK_PERIPH_APM 90 +#define IMX5_CLK_MAIN_BUS 91 +#define IMX5_CLK_AHB_MAX 92 +#define IMX5_CLK_AIPS_TZ1 93 +#define IMX5_CLK_AIPS_TZ2 94 +#define IMX5_CLK_TMAX1 95 +#define IMX5_CLK_TMAX2 96 +#define IMX5_CLK_TMAX3 97 +#define IMX5_CLK_SPBA 98 +#define IMX5_CLK_UART_SEL 99 +#define IMX5_CLK_ESDHC_A_SEL 100 +#define IMX5_CLK_ESDHC_B_SEL 101 +#define IMX5_CLK_ESDHC_A_PODF 102 +#define IMX5_CLK_ESDHC_B_PODF 103 +#define IMX5_CLK_ECSPI_SEL 104 +#define IMX5_CLK_USBOH3_SEL 105 +#define IMX5_CLK_USB_PHY_SEL 106 +#define IMX5_CLK_IIM_GATE 107 +#define IMX5_CLK_USBOH3_GATE 108 +#define IMX5_CLK_EMI_FAST_GATE 109 +#define IMX5_CLK_IPU_DI0_GATE 110 +#define IMX5_CLK_GPC_DVFS 111 +#define IMX5_CLK_PLL1_SW 112 +#define IMX5_CLK_PLL2_SW 113 +#define IMX5_CLK_PLL3_SW 114 +#define IMX5_CLK_IPU_DI0_SEL 115 +#define IMX5_CLK_IPU_DI1_SEL 116 +#define IMX5_CLK_TVE_EXT_SEL 117 +#define IMX5_CLK_MX51_MIPI 118 +#define IMX5_CLK_PLL4_SW 119 +#define IMX5_CLK_LDB_DI1_SEL 120 +#define IMX5_CLK_DI_PLL4_PODF 121 +#define IMX5_CLK_LDB_DI0_SEL 122 +#define IMX5_CLK_LDB_DI0_GATE 123 +#define IMX5_CLK_USB_PHY1_GATE 124 +#define IMX5_CLK_USB_PHY2_GATE 125 +#define IMX5_CLK_PER_LP_APM 126 +#define IMX5_CLK_PER_PRED1 127 +#define IMX5_CLK_PER_PRED2 128 +#define IMX5_CLK_PER_PODF 129 +#define IMX5_CLK_PER_ROOT 130 +#define IMX5_CLK_SSI_APM 131 +#define IMX5_CLK_SSI1_ROOT_SEL 132 +#define IMX5_CLK_SSI2_ROOT_SEL 133 +#define IMX5_CLK_SSI3_ROOT_SEL 134 +#define IMX5_CLK_SSI_EXT1_SEL 135 +#define IMX5_CLK_SSI_EXT2_SEL 136 +#define IMX5_CLK_SSI_EXT1_COM_SEL 137 +#define IMX5_CLK_SSI_EXT2_COM_SEL 138 +#define IMX5_CLK_SSI1_ROOT_PRED 139 +#define IMX5_CLK_SSI1_ROOT_PODF 140 +#define IMX5_CLK_SSI2_ROOT_PRED 141 +#define IMX5_CLK_SSI2_ROOT_PODF 142 +#define IMX5_CLK_SSI_EXT1_PRED 143 +#define IMX5_CLK_SSI_EXT1_PODF 144 +#define IMX5_CLK_SSI_EXT2_PRED 145 +#define IMX5_CLK_SSI_EXT2_PODF 146 +#define IMX5_CLK_SSI1_ROOT_GATE 147 +#define IMX5_CLK_SSI2_ROOT_GATE 148 +#define IMX5_CLK_SSI3_ROOT_GATE 149 +#define IMX5_CLK_SSI_EXT1_GATE 150 +#define IMX5_CLK_SSI_EXT2_GATE 151 +#define IMX5_CLK_EPIT1_IPG_GATE 152 +#define IMX5_CLK_EPIT1_HF_GATE 153 +#define IMX5_CLK_EPIT2_IPG_GATE 154 +#define IMX5_CLK_EPIT2_HF_GATE 155 +#define IMX5_CLK_CAN_SEL 156 +#define IMX5_CLK_CAN1_SERIAL_GATE 157 +#define IMX5_CLK_CAN1_IPG_GATE 158 +#define IMX5_CLK_OWIRE_GATE 159 +#define IMX5_CLK_GPU3D_SEL 160 +#define IMX5_CLK_GPU2D_SEL 161 +#define IMX5_CLK_GPU3D_GATE 162 +#define IMX5_CLK_GPU2D_GATE 163 +#define IMX5_CLK_GARB_GATE 164 +#define IMX5_CLK_CKO1_SEL 165 +#define IMX5_CLK_CKO1_PODF 166 +#define IMX5_CLK_CKO1 167 +#define IMX5_CLK_CKO2_SEL 168 +#define IMX5_CLK_CKO2_PODF 169 +#define IMX5_CLK_CKO2 170 +#define IMX5_CLK_SRTC_GATE 171 +#define IMX5_CLK_PATA_GATE 172 +#define IMX5_CLK_SATA_GATE 173 +#define IMX5_CLK_SPDIF_XTAL_SEL 174 +#define IMX5_CLK_SPDIF0_SEL 175 +#define IMX5_CLK_SPDIF1_SEL 176 +#define IMX5_CLK_SPDIF0_PRED 177 +#define IMX5_CLK_SPDIF0_PODF 178 +#define IMX5_CLK_SPDIF1_PRED 179 +#define IMX5_CLK_SPDIF1_PODF 180 +#define IMX5_CLK_SPDIF0_COM_SEL 181 +#define IMX5_CLK_SPDIF1_COM_SEL 182 +#define IMX5_CLK_SPDIF0_GATE 183 +#define IMX5_CLK_SPDIF1_GATE 184 +#define IMX5_CLK_SPDIF_IPG_GATE 185 +#define IMX5_CLK_OCRAM 186 +#define IMX5_CLK_SAHARA_IPG_GATE 187 +#define IMX5_CLK_SATA_REF 188 +#define IMX5_CLK_STEP_SEL 189 +#define IMX5_CLK_CPU_PODF_SEL 190 +#define IMX5_CLK_ARM 191 +#define IMX5_CLK_FIRI_PRED 192 +#define IMX5_CLK_FIRI_SEL 193 +#define IMX5_CLK_FIRI_PODF 194 +#define IMX5_CLK_FIRI_SERIAL_GATE 195 +#define IMX5_CLK_FIRI_IPG_GATE 196 +#define IMX5_CLK_CSI0_MCLK1_PRED 197 +#define IMX5_CLK_CSI0_MCLK1_SEL 198 +#define IMX5_CLK_CSI0_MCLK1_PODF 199 +#define IMX5_CLK_CSI0_MCLK1_GATE 200 +#define IMX5_CLK_IEEE1588_PRED 201 +#define IMX5_CLK_IEEE1588_SEL 202 +#define IMX5_CLK_IEEE1588_PODF 203 +#define IMX5_CLK_IEEE1588_GATE 204 +#define IMX5_CLK_END 205 + +#endif /* __DT_BINDINGS_CLOCK_IMX5_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/imx6qdl-clock.h b/roms/u-boot/include/dt-bindings/clock/imx6qdl-clock.h new file mode 100644 index 000000000..29050337d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/imx6qdl-clock.h @@ -0,0 +1,274 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H +#define __DT_BINDINGS_CLOCK_IMX6QDL_H + +#define IMX6QDL_CLK_DUMMY 0 +#define IMX6QDL_CLK_CKIL 1 +#define IMX6QDL_CLK_CKIH 2 +#define IMX6QDL_CLK_OSC 3 +#define IMX6QDL_CLK_PLL2_PFD0_352M 4 +#define IMX6QDL_CLK_PLL2_PFD1_594M 5 +#define IMX6QDL_CLK_PLL2_PFD2_396M 6 +#define IMX6QDL_CLK_PLL3_PFD0_720M 7 +#define IMX6QDL_CLK_PLL3_PFD1_540M 8 +#define IMX6QDL_CLK_PLL3_PFD2_508M 9 +#define IMX6QDL_CLK_PLL3_PFD3_454M 10 +#define IMX6QDL_CLK_PLL2_198M 11 +#define IMX6QDL_CLK_PLL3_120M 12 +#define IMX6QDL_CLK_PLL3_80M 13 +#define IMX6QDL_CLK_PLL3_60M 14 +#define IMX6QDL_CLK_TWD 15 +#define IMX6QDL_CLK_STEP 16 +#define IMX6QDL_CLK_PLL1_SW 17 +#define IMX6QDL_CLK_PERIPH_PRE 18 +#define IMX6QDL_CLK_PERIPH2_PRE 19 +#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20 +#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21 +#define IMX6QDL_CLK_AXI_SEL 22 +#define IMX6QDL_CLK_ESAI_SEL 23 +#define IMX6QDL_CLK_ASRC_SEL 24 +#define IMX6QDL_CLK_SPDIF_SEL 25 +#define IMX6QDL_CLK_GPU2D_AXI 26 +#define IMX6QDL_CLK_GPU3D_AXI 27 +#define IMX6QDL_CLK_GPU2D_CORE_SEL 28 +#define IMX6QDL_CLK_GPU3D_CORE_SEL 29 +#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30 +#define IMX6QDL_CLK_IPU1_SEL 31 +#define IMX6QDL_CLK_IPU2_SEL 32 +#define IMX6QDL_CLK_LDB_DI0_SEL 33 +#define IMX6QDL_CLK_LDB_DI1_SEL 34 +#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35 +#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36 +#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37 +#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38 +#define IMX6QDL_CLK_IPU1_DI0_SEL 39 +#define IMX6QDL_CLK_IPU1_DI1_SEL 40 +#define IMX6QDL_CLK_IPU2_DI0_SEL 41 +#define IMX6QDL_CLK_IPU2_DI1_SEL 42 +#define IMX6QDL_CLK_HSI_TX_SEL 43 +#define IMX6QDL_CLK_PCIE_AXI_SEL 44 +#define IMX6QDL_CLK_SSI1_SEL 45 +#define IMX6QDL_CLK_SSI2_SEL 46 +#define IMX6QDL_CLK_SSI3_SEL 47 +#define IMX6QDL_CLK_USDHC1_SEL 48 +#define IMX6QDL_CLK_USDHC2_SEL 49 +#define IMX6QDL_CLK_USDHC3_SEL 50 +#define IMX6QDL_CLK_USDHC4_SEL 51 +#define IMX6QDL_CLK_ENFC_SEL 52 +#define IMX6QDL_CLK_EIM_SEL 53 +#define IMX6QDL_CLK_EIM_SLOW_SEL 54 +#define IMX6QDL_CLK_VDO_AXI_SEL 55 +#define IMX6QDL_CLK_VPU_AXI_SEL 56 +#define IMX6QDL_CLK_CKO1_SEL 57 +#define IMX6QDL_CLK_PERIPH 58 +#define IMX6QDL_CLK_PERIPH2 59 +#define IMX6QDL_CLK_PERIPH_CLK2 60 +#define IMX6QDL_CLK_PERIPH2_CLK2 61 +#define IMX6QDL_CLK_IPG 62 +#define IMX6QDL_CLK_IPG_PER 63 +#define IMX6QDL_CLK_ESAI_PRED 64 +#define IMX6QDL_CLK_ESAI_PODF 65 +#define IMX6QDL_CLK_ASRC_PRED 66 +#define IMX6QDL_CLK_ASRC_PODF 67 +#define IMX6QDL_CLK_SPDIF_PRED 68 +#define IMX6QDL_CLK_SPDIF_PODF 69 +#define IMX6QDL_CLK_CAN_ROOT 70 +#define IMX6QDL_CLK_ECSPI_ROOT 71 +#define IMX6QDL_CLK_GPU2D_CORE_PODF 72 +#define IMX6QDL_CLK_GPU3D_CORE_PODF 73 +#define IMX6QDL_CLK_GPU3D_SHADER 74 +#define IMX6QDL_CLK_IPU1_PODF 75 +#define IMX6QDL_CLK_IPU2_PODF 76 +#define IMX6QDL_CLK_LDB_DI0_PODF 77 +#define IMX6QDL_CLK_LDB_DI1_PODF 78 +#define IMX6QDL_CLK_IPU1_DI0_PRE 79 +#define IMX6QDL_CLK_IPU1_DI1_PRE 80 +#define IMX6QDL_CLK_IPU2_DI0_PRE 81 +#define IMX6QDL_CLK_IPU2_DI1_PRE 82 +#define IMX6QDL_CLK_HSI_TX_PODF 83 +#define IMX6QDL_CLK_SSI1_PRED 84 +#define IMX6QDL_CLK_SSI1_PODF 85 +#define IMX6QDL_CLK_SSI2_PRED 86 +#define IMX6QDL_CLK_SSI2_PODF 87 +#define IMX6QDL_CLK_SSI3_PRED 88 +#define IMX6QDL_CLK_SSI3_PODF 89 +#define IMX6QDL_CLK_UART_SERIAL_PODF 90 +#define IMX6QDL_CLK_USDHC1_PODF 91 +#define IMX6QDL_CLK_USDHC2_PODF 92 +#define IMX6QDL_CLK_USDHC3_PODF 93 +#define IMX6QDL_CLK_USDHC4_PODF 94 +#define IMX6QDL_CLK_ENFC_PRED 95 +#define IMX6QDL_CLK_ENFC_PODF 96 +#define IMX6QDL_CLK_EIM_PODF 97 +#define IMX6QDL_CLK_EIM_SLOW_PODF 98 +#define IMX6QDL_CLK_VPU_AXI_PODF 99 +#define IMX6QDL_CLK_CKO1_PODF 100 +#define IMX6QDL_CLK_AXI 101 +#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102 +#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103 +#define IMX6QDL_CLK_ARM 104 +#define IMX6QDL_CLK_AHB 105 +#define IMX6QDL_CLK_APBH_DMA 106 +#define IMX6QDL_CLK_ASRC 107 +#define IMX6QDL_CLK_CAN1_IPG 108 +#define IMX6QDL_CLK_CAN1_SERIAL 109 +#define IMX6QDL_CLK_CAN2_IPG 110 +#define IMX6QDL_CLK_CAN2_SERIAL 111 +#define IMX6QDL_CLK_ECSPI1 112 +#define IMX6QDL_CLK_ECSPI2 113 +#define IMX6QDL_CLK_ECSPI3 114 +#define IMX6QDL_CLK_ECSPI4 115 +#define IMX6Q_CLK_ECSPI5 116 +#define IMX6DL_CLK_I2C4 116 +#define IMX6QDL_CLK_ENET 117 +#define IMX6QDL_CLK_ESAI_EXTAL 118 +#define IMX6QDL_CLK_GPT_IPG 119 +#define IMX6QDL_CLK_GPT_IPG_PER 120 +#define IMX6QDL_CLK_GPU2D_CORE 121 +#define IMX6QDL_CLK_GPU3D_CORE 122 +#define IMX6QDL_CLK_HDMI_IAHB 123 +#define IMX6QDL_CLK_HDMI_ISFR 124 +#define IMX6QDL_CLK_I2C1 125 +#define IMX6QDL_CLK_I2C2 126 +#define IMX6QDL_CLK_I2C3 127 +#define IMX6QDL_CLK_IIM 128 +#define IMX6QDL_CLK_ENFC 129 +#define IMX6QDL_CLK_IPU1 130 +#define IMX6QDL_CLK_IPU1_DI0 131 +#define IMX6QDL_CLK_IPU1_DI1 132 +#define IMX6QDL_CLK_IPU2 133 +#define IMX6QDL_CLK_IPU2_DI0 134 +#define IMX6QDL_CLK_LDB_DI0 135 +#define IMX6QDL_CLK_LDB_DI1 136 +#define IMX6QDL_CLK_IPU2_DI1 137 +#define IMX6QDL_CLK_HSI_TX 138 +#define IMX6QDL_CLK_MLB 139 +#define IMX6QDL_CLK_MMDC_CH0_AXI 140 +#define IMX6QDL_CLK_MMDC_CH1_AXI 141 +#define IMX6QDL_CLK_OCRAM 142 +#define IMX6QDL_CLK_OPENVG_AXI 143 +#define IMX6QDL_CLK_PCIE_AXI 144 +#define IMX6QDL_CLK_PWM1 145 +#define IMX6QDL_CLK_PWM2 146 +#define IMX6QDL_CLK_PWM3 147 +#define IMX6QDL_CLK_PWM4 148 +#define IMX6QDL_CLK_PER1_BCH 149 +#define IMX6QDL_CLK_GPMI_BCH_APB 150 +#define IMX6QDL_CLK_GPMI_BCH 151 +#define IMX6QDL_CLK_GPMI_IO 152 +#define IMX6QDL_CLK_GPMI_APB 153 +#define IMX6QDL_CLK_SATA 154 +#define IMX6QDL_CLK_SDMA 155 +#define IMX6QDL_CLK_SPBA 156 +#define IMX6QDL_CLK_SSI1 157 +#define IMX6QDL_CLK_SSI2 158 +#define IMX6QDL_CLK_SSI3 159 +#define IMX6QDL_CLK_UART_IPG 160 +#define IMX6QDL_CLK_UART_SERIAL 161 +#define IMX6QDL_CLK_USBOH3 162 +#define IMX6QDL_CLK_USDHC1 163 +#define IMX6QDL_CLK_USDHC2 164 +#define IMX6QDL_CLK_USDHC3 165 +#define IMX6QDL_CLK_USDHC4 166 +#define IMX6QDL_CLK_VDO_AXI 167 +#define IMX6QDL_CLK_VPU_AXI 168 +#define IMX6QDL_CLK_CKO1 169 +#define IMX6QDL_CLK_PLL1_SYS 170 +#define IMX6QDL_CLK_PLL2_BUS 171 +#define IMX6QDL_CLK_PLL3_USB_OTG 172 +#define IMX6QDL_CLK_PLL4_AUDIO 173 +#define IMX6QDL_CLK_PLL5_VIDEO 174 +#define IMX6QDL_CLK_PLL8_MLB 175 +#define IMX6QDL_CLK_PLL7_USB_HOST 176 +#define IMX6QDL_CLK_PLL6_ENET 177 +#define IMX6QDL_CLK_SSI1_IPG 178 +#define IMX6QDL_CLK_SSI2_IPG 179 +#define IMX6QDL_CLK_SSI3_IPG 180 +#define IMX6QDL_CLK_ROM 181 +#define IMX6QDL_CLK_USBPHY1 182 +#define IMX6QDL_CLK_USBPHY2 183 +#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184 +#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185 +#define IMX6QDL_CLK_SATA_REF 186 +#define IMX6QDL_CLK_SATA_REF_100M 187 +#define IMX6QDL_CLK_PCIE_REF 188 +#define IMX6QDL_CLK_PCIE_REF_125M 189 +#define IMX6QDL_CLK_ENET_REF 190 +#define IMX6QDL_CLK_USBPHY1_GATE 191 +#define IMX6QDL_CLK_USBPHY2_GATE 192 +#define IMX6QDL_CLK_PLL4_POST_DIV 193 +#define IMX6QDL_CLK_PLL5_POST_DIV 194 +#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195 +#define IMX6QDL_CLK_EIM_SLOW 196 +#define IMX6QDL_CLK_SPDIF 197 +#define IMX6QDL_CLK_CKO2_SEL 198 +#define IMX6QDL_CLK_CKO2_PODF 199 +#define IMX6QDL_CLK_CKO2 200 +#define IMX6QDL_CLK_CKO 201 +#define IMX6QDL_CLK_VDOA 202 +#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203 +#define IMX6QDL_CLK_LVDS1_SEL 204 +#define IMX6QDL_CLK_LVDS2_SEL 205 +#define IMX6QDL_CLK_LVDS1_GATE 206 +#define IMX6QDL_CLK_LVDS2_GATE 207 +#define IMX6QDL_CLK_ESAI_IPG 208 +#define IMX6QDL_CLK_ESAI_MEM 209 +#define IMX6QDL_CLK_ASRC_IPG 210 +#define IMX6QDL_CLK_ASRC_MEM 211 +#define IMX6QDL_CLK_LVDS1_IN 212 +#define IMX6QDL_CLK_LVDS2_IN 213 +#define IMX6QDL_CLK_ANACLK1 214 +#define IMX6QDL_CLK_ANACLK2 215 +#define IMX6QDL_PLL1_BYPASS_SRC 216 +#define IMX6QDL_PLL2_BYPASS_SRC 217 +#define IMX6QDL_PLL3_BYPASS_SRC 218 +#define IMX6QDL_PLL4_BYPASS_SRC 219 +#define IMX6QDL_PLL5_BYPASS_SRC 220 +#define IMX6QDL_PLL6_BYPASS_SRC 221 +#define IMX6QDL_PLL7_BYPASS_SRC 222 +#define IMX6QDL_CLK_PLL1 223 +#define IMX6QDL_CLK_PLL2 224 +#define IMX6QDL_CLK_PLL3 225 +#define IMX6QDL_CLK_PLL4 226 +#define IMX6QDL_CLK_PLL5 227 +#define IMX6QDL_CLK_PLL6 228 +#define IMX6QDL_CLK_PLL7 229 +#define IMX6QDL_PLL1_BYPASS 230 +#define IMX6QDL_PLL2_BYPASS 231 +#define IMX6QDL_PLL3_BYPASS 232 +#define IMX6QDL_PLL4_BYPASS 233 +#define IMX6QDL_PLL5_BYPASS 234 +#define IMX6QDL_PLL6_BYPASS 235 +#define IMX6QDL_PLL7_BYPASS 236 +#define IMX6QDL_CLK_GPT_3M 237 +#define IMX6QDL_CLK_VIDEO_27M 238 +#define IMX6QDL_CLK_MIPI_CORE_CFG 239 +#define IMX6QDL_CLK_MIPI_IPG 240 +#define IMX6QDL_CLK_CAAM_MEM 241 +#define IMX6QDL_CLK_CAAM_ACLK 242 +#define IMX6QDL_CLK_CAAM_IPG 243 +#define IMX6QDL_CLK_SPDIF_GCLK 244 +#define IMX6QDL_CLK_UART_SEL 245 +#define IMX6QDL_CLK_IPG_PER_SEL 246 +#define IMX6QDL_CLK_ECSPI_SEL 247 +#define IMX6QDL_CLK_CAN_SEL 248 +#define IMX6QDL_CLK_MMDC_CH1_AXI_CG 249 +#define IMX6QDL_CLK_PRE0 250 +#define IMX6QDL_CLK_PRE1 251 +#define IMX6QDL_CLK_PRE2 252 +#define IMX6QDL_CLK_PRE3 253 +#define IMX6QDL_CLK_PRG0_AXI 254 +#define IMX6QDL_CLK_PRG1_AXI 255 +#define IMX6QDL_CLK_PRG0_APB 256 +#define IMX6QDL_CLK_PRG1_APB 257 +#define IMX6QDL_CLK_PRE_AXI 258 +#define IMX6QDL_CLK_END 259 + +#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/imx6sl-clock.h b/roms/u-boot/include/dt-bindings/clock/imx6sl-clock.h new file mode 100644 index 000000000..e14573e29 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/imx6sl-clock.h @@ -0,0 +1,180 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H +#define __DT_BINDINGS_CLOCK_IMX6SL_H + +#define IMX6SL_CLK_DUMMY 0 +#define IMX6SL_CLK_CKIL 1 +#define IMX6SL_CLK_OSC 2 +#define IMX6SL_CLK_PLL1_SYS 3 +#define IMX6SL_CLK_PLL2_BUS 4 +#define IMX6SL_CLK_PLL3_USB_OTG 5 +#define IMX6SL_CLK_PLL4_AUDIO 6 +#define IMX6SL_CLK_PLL5_VIDEO 7 +#define IMX6SL_CLK_PLL6_ENET 8 +#define IMX6SL_CLK_PLL7_USB_HOST 9 +#define IMX6SL_CLK_USBPHY1 10 +#define IMX6SL_CLK_USBPHY2 11 +#define IMX6SL_CLK_USBPHY1_GATE 12 +#define IMX6SL_CLK_USBPHY2_GATE 13 +#define IMX6SL_CLK_PLL4_POST_DIV 14 +#define IMX6SL_CLK_PLL5_POST_DIV 15 +#define IMX6SL_CLK_PLL5_VIDEO_DIV 16 +#define IMX6SL_CLK_ENET_REF 17 +#define IMX6SL_CLK_PLL2_PFD0 18 +#define IMX6SL_CLK_PLL2_PFD1 19 +#define IMX6SL_CLK_PLL2_PFD2 20 +#define IMX6SL_CLK_PLL3_PFD0 21 +#define IMX6SL_CLK_PLL3_PFD1 22 +#define IMX6SL_CLK_PLL3_PFD2 23 +#define IMX6SL_CLK_PLL3_PFD3 24 +#define IMX6SL_CLK_PLL2_198M 25 +#define IMX6SL_CLK_PLL3_120M 26 +#define IMX6SL_CLK_PLL3_80M 27 +#define IMX6SL_CLK_PLL3_60M 28 +#define IMX6SL_CLK_STEP 29 +#define IMX6SL_CLK_PLL1_SW 30 +#define IMX6SL_CLK_OCRAM_ALT_SEL 31 +#define IMX6SL_CLK_OCRAM_SEL 32 +#define IMX6SL_CLK_PRE_PERIPH2_SEL 33 +#define IMX6SL_CLK_PRE_PERIPH_SEL 34 +#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35 +#define IMX6SL_CLK_PERIPH_CLK2_SEL 36 +#define IMX6SL_CLK_CSI_SEL 37 +#define IMX6SL_CLK_LCDIF_AXI_SEL 38 +#define IMX6SL_CLK_USDHC1_SEL 39 +#define IMX6SL_CLK_USDHC2_SEL 40 +#define IMX6SL_CLK_USDHC3_SEL 41 +#define IMX6SL_CLK_USDHC4_SEL 42 +#define IMX6SL_CLK_SSI1_SEL 43 +#define IMX6SL_CLK_SSI2_SEL 44 +#define IMX6SL_CLK_SSI3_SEL 45 +#define IMX6SL_CLK_PERCLK_SEL 46 +#define IMX6SL_CLK_PXP_AXI_SEL 47 +#define IMX6SL_CLK_EPDC_AXI_SEL 48 +#define IMX6SL_CLK_GPU2D_OVG_SEL 49 +#define IMX6SL_CLK_GPU2D_SEL 50 +#define IMX6SL_CLK_LCDIF_PIX_SEL 51 +#define IMX6SL_CLK_EPDC_PIX_SEL 52 +#define IMX6SL_CLK_SPDIF0_SEL 53 +#define IMX6SL_CLK_SPDIF1_SEL 54 +#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55 +#define IMX6SL_CLK_ECSPI_SEL 56 +#define IMX6SL_CLK_UART_SEL 57 +#define IMX6SL_CLK_PERIPH 58 +#define IMX6SL_CLK_PERIPH2 59 +#define IMX6SL_CLK_OCRAM_PODF 60 +#define IMX6SL_CLK_PERIPH_CLK2_PODF 61 +#define IMX6SL_CLK_PERIPH2_CLK2_PODF 62 +#define IMX6SL_CLK_IPG 63 +#define IMX6SL_CLK_CSI_PODF 64 +#define IMX6SL_CLK_LCDIF_AXI_PODF 65 +#define IMX6SL_CLK_USDHC1_PODF 66 +#define IMX6SL_CLK_USDHC2_PODF 67 +#define IMX6SL_CLK_USDHC3_PODF 68 +#define IMX6SL_CLK_USDHC4_PODF 69 +#define IMX6SL_CLK_SSI1_PRED 70 +#define IMX6SL_CLK_SSI1_PODF 71 +#define IMX6SL_CLK_SSI2_PRED 72 +#define IMX6SL_CLK_SSI2_PODF 73 +#define IMX6SL_CLK_SSI3_PRED 74 +#define IMX6SL_CLK_SSI3_PODF 75 +#define IMX6SL_CLK_PERCLK 76 +#define IMX6SL_CLK_PXP_AXI_PODF 77 +#define IMX6SL_CLK_EPDC_AXI_PODF 78 +#define IMX6SL_CLK_GPU2D_OVG_PODF 79 +#define IMX6SL_CLK_GPU2D_PODF 80 +#define IMX6SL_CLK_LCDIF_PIX_PRED 81 +#define IMX6SL_CLK_EPDC_PIX_PRED 82 +#define IMX6SL_CLK_LCDIF_PIX_PODF 83 +#define IMX6SL_CLK_EPDC_PIX_PODF 84 +#define IMX6SL_CLK_SPDIF0_PRED 85 +#define IMX6SL_CLK_SPDIF0_PODF 86 +#define IMX6SL_CLK_SPDIF1_PRED 87 +#define IMX6SL_CLK_SPDIF1_PODF 88 +#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89 +#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90 +#define IMX6SL_CLK_ECSPI_ROOT 91 +#define IMX6SL_CLK_UART_ROOT 92 +#define IMX6SL_CLK_AHB 93 +#define IMX6SL_CLK_MMDC_ROOT 94 +#define IMX6SL_CLK_ARM 95 +#define IMX6SL_CLK_ECSPI1 96 +#define IMX6SL_CLK_ECSPI2 97 +#define IMX6SL_CLK_ECSPI3 98 +#define IMX6SL_CLK_ECSPI4 99 +#define IMX6SL_CLK_EPIT1 100 +#define IMX6SL_CLK_EPIT2 101 +#define IMX6SL_CLK_EXTERN_AUDIO 102 +#define IMX6SL_CLK_GPT 103 +#define IMX6SL_CLK_GPT_SERIAL 104 +#define IMX6SL_CLK_GPU2D_OVG 105 +#define IMX6SL_CLK_I2C1 106 +#define IMX6SL_CLK_I2C2 107 +#define IMX6SL_CLK_I2C3 108 +#define IMX6SL_CLK_OCOTP 109 +#define IMX6SL_CLK_CSI 110 +#define IMX6SL_CLK_PXP_AXI 111 +#define IMX6SL_CLK_EPDC_AXI 112 +#define IMX6SL_CLK_LCDIF_AXI 113 +#define IMX6SL_CLK_LCDIF_PIX 114 +#define IMX6SL_CLK_EPDC_PIX 115 +#define IMX6SL_CLK_OCRAM 116 +#define IMX6SL_CLK_PWM1 117 +#define IMX6SL_CLK_PWM2 118 +#define IMX6SL_CLK_PWM3 119 +#define IMX6SL_CLK_PWM4 120 +#define IMX6SL_CLK_SDMA 121 +#define IMX6SL_CLK_SPDIF 122 +#define IMX6SL_CLK_SSI1 123 +#define IMX6SL_CLK_SSI2 124 +#define IMX6SL_CLK_SSI3 125 +#define IMX6SL_CLK_UART 126 +#define IMX6SL_CLK_UART_SERIAL 127 +#define IMX6SL_CLK_USBOH3 128 +#define IMX6SL_CLK_USDHC1 129 +#define IMX6SL_CLK_USDHC2 130 +#define IMX6SL_CLK_USDHC3 131 +#define IMX6SL_CLK_USDHC4 132 +#define IMX6SL_CLK_PLL4_AUDIO_DIV 133 +#define IMX6SL_CLK_SPBA 134 +#define IMX6SL_CLK_ENET 135 +#define IMX6SL_CLK_LVDS1_SEL 136 +#define IMX6SL_CLK_LVDS1_OUT 137 +#define IMX6SL_CLK_LVDS1_IN 138 +#define IMX6SL_CLK_ANACLK1 139 +#define IMX6SL_PLL1_BYPASS_SRC 140 +#define IMX6SL_PLL2_BYPASS_SRC 141 +#define IMX6SL_PLL3_BYPASS_SRC 142 +#define IMX6SL_PLL4_BYPASS_SRC 143 +#define IMX6SL_PLL5_BYPASS_SRC 144 +#define IMX6SL_PLL6_BYPASS_SRC 145 +#define IMX6SL_PLL7_BYPASS_SRC 146 +#define IMX6SL_CLK_PLL1 147 +#define IMX6SL_CLK_PLL2 148 +#define IMX6SL_CLK_PLL3 149 +#define IMX6SL_CLK_PLL4 150 +#define IMX6SL_CLK_PLL5 151 +#define IMX6SL_CLK_PLL6 152 +#define IMX6SL_CLK_PLL7 153 +#define IMX6SL_PLL1_BYPASS 154 +#define IMX6SL_PLL2_BYPASS 155 +#define IMX6SL_PLL3_BYPASS 156 +#define IMX6SL_PLL4_BYPASS 157 +#define IMX6SL_PLL5_BYPASS 158 +#define IMX6SL_PLL6_BYPASS 159 +#define IMX6SL_PLL7_BYPASS 160 +#define IMX6SL_CLK_SSI1_IPG 161 +#define IMX6SL_CLK_SSI2_IPG 162 +#define IMX6SL_CLK_SSI3_IPG 163 +#define IMX6SL_CLK_SPDIF_GCLK 164 +#define IMX6SL_CLK_END 165 + +#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/imx6sll-clock.h b/roms/u-boot/include/dt-bindings/clock/imx6sll-clock.h new file mode 100644 index 000000000..39c25671d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/imx6sll-clock.h @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H +#define __DT_BINDINGS_CLOCK_IMX6SLL_H + +#define IMX6SLL_CLK_DUMMY 0 +#define IMX6SLL_CLK_CKIL 1 +#define IMX6SLL_CLK_OSC 2 +#define IMX6SLL_PLL1_BYPASS_SRC 3 +#define IMX6SLL_PLL2_BYPASS_SRC 4 +#define IMX6SLL_PLL3_BYPASS_SRC 5 +#define IMX6SLL_PLL4_BYPASS_SRC 6 +#define IMX6SLL_PLL5_BYPASS_SRC 7 +#define IMX6SLL_PLL6_BYPASS_SRC 8 +#define IMX6SLL_PLL7_BYPASS_SRC 9 +#define IMX6SLL_CLK_PLL1 10 +#define IMX6SLL_CLK_PLL2 11 +#define IMX6SLL_CLK_PLL3 12 +#define IMX6SLL_CLK_PLL4 13 +#define IMX6SLL_CLK_PLL5 14 +#define IMX6SLL_CLK_PLL6 15 +#define IMX6SLL_CLK_PLL7 16 +#define IMX6SLL_PLL1_BYPASS 17 +#define IMX6SLL_PLL2_BYPASS 18 +#define IMX6SLL_PLL3_BYPASS 19 +#define IMX6SLL_PLL4_BYPASS 20 +#define IMX6SLL_PLL5_BYPASS 21 +#define IMX6SLL_PLL6_BYPASS 22 +#define IMX6SLL_PLL7_BYPASS 23 +#define IMX6SLL_CLK_PLL1_SYS 24 +#define IMX6SLL_CLK_PLL2_BUS 25 +#define IMX6SLL_CLK_PLL3_USB_OTG 26 +#define IMX6SLL_CLK_PLL4_AUDIO 27 +#define IMX6SLL_CLK_PLL5_VIDEO 28 +#define IMX6SLL_CLK_PLL6_ENET 29 +#define IMX6SLL_CLK_PLL7_USB_HOST 30 +#define IMX6SLL_CLK_USBPHY1 31 +#define IMX6SLL_CLK_USBPHY2 32 +#define IMX6SLL_CLK_USBPHY1_GATE 33 +#define IMX6SLL_CLK_USBPHY2_GATE 34 +#define IMX6SLL_CLK_PLL2_PFD0 35 +#define IMX6SLL_CLK_PLL2_PFD1 36 +#define IMX6SLL_CLK_PLL2_PFD2 37 +#define IMX6SLL_CLK_PLL2_PFD3 38 +#define IMX6SLL_CLK_PLL3_PFD0 39 +#define IMX6SLL_CLK_PLL3_PFD1 40 +#define IMX6SLL_CLK_PLL3_PFD2 41 +#define IMX6SLL_CLK_PLL3_PFD3 42 +#define IMX6SLL_CLK_PLL4_POST_DIV 43 +#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44 +#define IMX6SLL_CLK_PLL5_POST_DIV 45 +#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46 +#define IMX6SLL_CLK_PLL2_198M 47 +#define IMX6SLL_CLK_PLL3_120M 48 +#define IMX6SLL_CLK_PLL3_80M 49 +#define IMX6SLL_CLK_PLL3_60M 50 +#define IMX6SLL_CLK_STEP 51 +#define IMX6SLL_CLK_PLL1_SW 52 +#define IMX6SLL_CLK_AXI_ALT_SEL 53 +#define IMX6SLL_CLK_AXI_SEL 54 +#define IMX6SLL_CLK_PERIPH_PRE 55 +#define IMX6SLL_CLK_PERIPH2_PRE 56 +#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57 +#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58 +#define IMX6SLL_CLK_PERCLK_SEL 59 +#define IMX6SLL_CLK_USDHC1_SEL 60 +#define IMX6SLL_CLK_USDHC2_SEL 61 +#define IMX6SLL_CLK_USDHC3_SEL 62 +#define IMX6SLL_CLK_SSI1_SEL 63 +#define IMX6SLL_CLK_SSI2_SEL 64 +#define IMX6SLL_CLK_SSI3_SEL 65 +#define IMX6SLL_CLK_PXP_SEL 66 +#define IMX6SLL_CLK_LCDIF_PRE_SEL 67 +#define IMX6SLL_CLK_LCDIF_SEL 68 +#define IMX6SLL_CLK_EPDC_PRE_SEL 69 +#define IMX6SLL_CLK_SPDIF_SEL 70 +#define IMX6SLL_CLK_ECSPI_SEL 71 +#define IMX6SLL_CLK_UART_SEL 72 +#define IMX6SLL_CLK_ARM 73 +#define IMX6SLL_CLK_PERIPH 74 +#define IMX6SLL_CLK_PERIPH2 75 +#define IMX6SLL_CLK_PERIPH2_CLK2 76 +#define IMX6SLL_CLK_PERIPH_CLK2 77 +#define IMX6SLL_CLK_MMDC_PODF 78 +#define IMX6SLL_CLK_AXI_PODF 79 +#define IMX6SLL_CLK_AHB 80 +#define IMX6SLL_CLK_IPG 81 +#define IMX6SLL_CLK_PERCLK 82 +#define IMX6SLL_CLK_USDHC1_PODF 83 +#define IMX6SLL_CLK_USDHC2_PODF 84 +#define IMX6SLL_CLK_USDHC3_PODF 85 +#define IMX6SLL_CLK_SSI1_PRED 86 +#define IMX6SLL_CLK_SSI2_PRED 87 +#define IMX6SLL_CLK_SSI3_PRED 88 +#define IMX6SLL_CLK_SSI1_PODF 89 +#define IMX6SLL_CLK_SSI2_PODF 90 +#define IMX6SLL_CLK_SSI3_PODF 91 +#define IMX6SLL_CLK_PXP_PODF 92 +#define IMX6SLL_CLK_LCDIF_PRED 93 +#define IMX6SLL_CLK_LCDIF_PODF 94 +#define IMX6SLL_CLK_EPDC_SEL 95 +#define IMX6SLL_CLK_EPDC_PODF 96 +#define IMX6SLL_CLK_SPDIF_PRED 97 +#define IMX6SLL_CLK_SPDIF_PODF 98 +#define IMX6SLL_CLK_ECSPI_PODF 99 +#define IMX6SLL_CLK_UART_PODF 100 + +/* CCGR 0 */ +#define IMX6SLL_CLK_AIPSTZ1 101 +#define IMX6SLL_CLK_AIPSTZ2 102 +#define IMX6SLL_CLK_DCP 103 +#define IMX6SLL_CLK_UART2_IPG 104 +#define IMX6SLL_CLK_UART2_SERIAL 105 + +/* CCGR 1 */ +#define IMX6SLL_CLK_ECSPI1 106 +#define IMX6SLL_CLK_ECSPI2 107 +#define IMX6SLL_CLK_ECSPI3 108 +#define IMX6SLL_CLK_ECSPI4 109 +#define IMX6SLL_CLK_UART3_IPG 110 +#define IMX6SLL_CLK_UART3_SERIAL 111 +#define IMX6SLL_CLK_UART4_IPG 112 +#define IMX6SLL_CLK_UART4_SERIAL 113 +#define IMX6SLL_CLK_EPIT1 114 +#define IMX6SLL_CLK_EPIT2 115 +#define IMX6SLL_CLK_GPT_BUS 116 +#define IMX6SLL_CLK_GPT_SERIAL 117 + +/* CCGR2 */ +#define IMX6SLL_CLK_CSI 118 +#define IMX6SLL_CLK_I2C1 119 +#define IMX6SLL_CLK_I2C2 120 +#define IMX6SLL_CLK_I2C3 121 +#define IMX6SLL_CLK_OCOTP 122 +#define IMX6SLL_CLK_LCDIF_APB 123 +#define IMX6SLL_CLK_PXP 124 + +/* CCGR3 */ +#define IMX6SLL_CLK_UART5_IPG 125 +#define IMX6SLL_CLK_UART5_SERIAL 126 +#define IMX6SLL_CLK_EPDC_AXI 127 +#define IMX6SLL_CLK_EPDC_PIX 128 +#define IMX6SLL_CLK_LCDIF_PIX 129 +#define IMX6SLL_CLK_WDOG1 130 +#define IMX6SLL_CLK_MMDC_P0_FAST 131 +#define IMX6SLL_CLK_MMDC_P0_IPG 132 +#define IMX6SLL_CLK_OCRAM 133 + +/* CCGR4 */ +#define IMX6SLL_CLK_PWM1 134 +#define IMX6SLL_CLK_PWM2 135 +#define IMX6SLL_CLK_PWM3 136 +#define IMX6SLL_CLK_PWM4 137 + +/* CCGR 5 */ +#define IMX6SLL_CLK_ROM 138 +#define IMX6SLL_CLK_SDMA 139 +#define IMX6SLL_CLK_KPP 140 +#define IMX6SLL_CLK_WDOG2 141 +#define IMX6SLL_CLK_SPBA 142 +#define IMX6SLL_CLK_SPDIF 143 +#define IMX6SLL_CLK_SPDIF_GCLK 144 +#define IMX6SLL_CLK_SSI1 145 +#define IMX6SLL_CLK_SSI1_IPG 146 +#define IMX6SLL_CLK_SSI2 147 +#define IMX6SLL_CLK_SSI2_IPG 148 +#define IMX6SLL_CLK_SSI3 149 +#define IMX6SLL_CLK_SSI3_IPG 150 +#define IMX6SLL_CLK_UART1_IPG 151 +#define IMX6SLL_CLK_UART1_SERIAL 152 + +/* CCGR 6 */ +#define IMX6SLL_CLK_USBOH3 153 +#define IMX6SLL_CLK_USDHC1 154 +#define IMX6SLL_CLK_USDHC2 155 +#define IMX6SLL_CLK_USDHC3 156 + +#define IMX6SLL_CLK_IPP_DI0 157 +#define IMX6SLL_CLK_IPP_DI1 158 +#define IMX6SLL_CLK_LDB_DI0_SEL 159 +#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160 +#define IMX6SLL_CLK_LDB_DI0_DIV_7 161 +#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162 +#define IMX6SLL_CLK_LDB_DI0 163 +#define IMX6SLL_CLK_LDB_DI1_SEL 164 +#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165 +#define IMX6SLL_CLK_LDB_DI1_DIV_7 166 +#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167 +#define IMX6SLL_CLK_LDB_DI1 168 +#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169 +#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170 +#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171 +#define IMX6SLL_CLK_EXTERN_AUDIO 172 + +#define IMX6SLL_CLK_END 173 + +#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/imx6sx-clock.h b/roms/u-boot/include/dt-bindings/clock/imx6sx-clock.h new file mode 100644 index 000000000..1c64997d6 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/imx6sx-clock.h @@ -0,0 +1,281 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H +#define __DT_BINDINGS_CLOCK_IMX6SX_H + +#define IMX6SX_CLK_DUMMY 0 +#define IMX6SX_CLK_CKIL 1 +#define IMX6SX_CLK_CKIH 2 +#define IMX6SX_CLK_OSC 3 +#define IMX6SX_CLK_PLL1_SYS 4 +#define IMX6SX_CLK_PLL2_BUS 5 +#define IMX6SX_CLK_PLL3_USB_OTG 6 +#define IMX6SX_CLK_PLL4_AUDIO 7 +#define IMX6SX_CLK_PLL5_VIDEO 8 +#define IMX6SX_CLK_PLL6_ENET 9 +#define IMX6SX_CLK_PLL7_USB_HOST 10 +#define IMX6SX_CLK_USBPHY1 11 +#define IMX6SX_CLK_USBPHY2 12 +#define IMX6SX_CLK_USBPHY1_GATE 13 +#define IMX6SX_CLK_USBPHY2_GATE 14 +#define IMX6SX_CLK_PCIE_REF 15 +#define IMX6SX_CLK_PCIE_REF_125M 16 +#define IMX6SX_CLK_ENET_REF 17 +#define IMX6SX_CLK_PLL2_PFD0 18 +#define IMX6SX_CLK_PLL2_PFD1 19 +#define IMX6SX_CLK_PLL2_PFD2 20 +#define IMX6SX_CLK_PLL2_PFD3 21 +#define IMX6SX_CLK_PLL3_PFD0 22 +#define IMX6SX_CLK_PLL3_PFD1 23 +#define IMX6SX_CLK_PLL3_PFD2 24 +#define IMX6SX_CLK_PLL3_PFD3 25 +#define IMX6SX_CLK_PLL2_198M 26 +#define IMX6SX_CLK_PLL3_120M 27 +#define IMX6SX_CLK_PLL3_80M 28 +#define IMX6SX_CLK_PLL3_60M 29 +#define IMX6SX_CLK_TWD 30 +#define IMX6SX_CLK_PLL4_POST_DIV 31 +#define IMX6SX_CLK_PLL4_AUDIO_DIV 32 +#define IMX6SX_CLK_PLL5_POST_DIV 33 +#define IMX6SX_CLK_PLL5_VIDEO_DIV 34 +#define IMX6SX_CLK_STEP 35 +#define IMX6SX_CLK_PLL1_SW 36 +#define IMX6SX_CLK_OCRAM_SEL 37 +#define IMX6SX_CLK_PERIPH_PRE 38 +#define IMX6SX_CLK_PERIPH2_PRE 39 +#define IMX6SX_CLK_PERIPH_CLK2_SEL 40 +#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41 +#define IMX6SX_CLK_PCIE_AXI_SEL 42 +#define IMX6SX_CLK_GPU_AXI_SEL 43 +#define IMX6SX_CLK_GPU_CORE_SEL 44 +#define IMX6SX_CLK_EIM_SLOW_SEL 45 +#define IMX6SX_CLK_USDHC1_SEL 46 +#define IMX6SX_CLK_USDHC2_SEL 47 +#define IMX6SX_CLK_USDHC3_SEL 48 +#define IMX6SX_CLK_USDHC4_SEL 49 +#define IMX6SX_CLK_SSI1_SEL 50 +#define IMX6SX_CLK_SSI2_SEL 51 +#define IMX6SX_CLK_SSI3_SEL 52 +#define IMX6SX_CLK_QSPI1_SEL 53 +#define IMX6SX_CLK_PERCLK_SEL 54 +#define IMX6SX_CLK_VID_SEL 55 +#define IMX6SX_CLK_ESAI_SEL 56 +#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57 +#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58 +#define IMX6SX_CLK_CAN_SEL 59 +#define IMX6SX_CLK_UART_SEL 60 +#define IMX6SX_CLK_QSPI2_SEL 61 +#define IMX6SX_CLK_LDB_DI1_SEL 62 +#define IMX6SX_CLK_LDB_DI0_SEL 63 +#define IMX6SX_CLK_SPDIF_SEL 64 +#define IMX6SX_CLK_AUDIO_SEL 65 +#define IMX6SX_CLK_ENET_PRE_SEL 66 +#define IMX6SX_CLK_ENET_SEL 67 +#define IMX6SX_CLK_M4_PRE_SEL 68 +#define IMX6SX_CLK_M4_SEL 69 +#define IMX6SX_CLK_ECSPI_SEL 70 +#define IMX6SX_CLK_LCDIF1_PRE_SEL 71 +#define IMX6SX_CLK_LCDIF2_PRE_SEL 72 +#define IMX6SX_CLK_LCDIF1_SEL 73 +#define IMX6SX_CLK_LCDIF2_SEL 74 +#define IMX6SX_CLK_DISPLAY_SEL 75 +#define IMX6SX_CLK_CSI_SEL 76 +#define IMX6SX_CLK_CKO1_SEL 77 +#define IMX6SX_CLK_CKO2_SEL 78 +#define IMX6SX_CLK_CKO 79 +#define IMX6SX_CLK_PERIPH_CLK2 80 +#define IMX6SX_CLK_PERIPH2_CLK2 81 +#define IMX6SX_CLK_IPG 82 +#define IMX6SX_CLK_GPU_CORE_PODF 83 +#define IMX6SX_CLK_GPU_AXI_PODF 84 +#define IMX6SX_CLK_LCDIF1_PODF 85 +#define IMX6SX_CLK_QSPI1_PODF 86 +#define IMX6SX_CLK_EIM_SLOW_PODF 87 +#define IMX6SX_CLK_LCDIF2_PODF 88 +#define IMX6SX_CLK_PERCLK 89 +#define IMX6SX_CLK_VID_PODF 90 +#define IMX6SX_CLK_CAN_PODF 91 +#define IMX6SX_CLK_USDHC1_PODF 92 +#define IMX6SX_CLK_USDHC2_PODF 93 +#define IMX6SX_CLK_USDHC3_PODF 94 +#define IMX6SX_CLK_USDHC4_PODF 95 +#define IMX6SX_CLK_UART_PODF 96 +#define IMX6SX_CLK_ESAI_PRED 97 +#define IMX6SX_CLK_ESAI_PODF 98 +#define IMX6SX_CLK_SSI3_PRED 99 +#define IMX6SX_CLK_SSI3_PODF 100 +#define IMX6SX_CLK_SSI1_PRED 101 +#define IMX6SX_CLK_SSI1_PODF 102 +#define IMX6SX_CLK_QSPI2_PRED 103 +#define IMX6SX_CLK_QSPI2_PODF 104 +#define IMX6SX_CLK_SSI2_PRED 105 +#define IMX6SX_CLK_SSI2_PODF 106 +#define IMX6SX_CLK_SPDIF_PRED 107 +#define IMX6SX_CLK_SPDIF_PODF 108 +#define IMX6SX_CLK_AUDIO_PRED 109 +#define IMX6SX_CLK_AUDIO_PODF 110 +#define IMX6SX_CLK_ENET_PODF 111 +#define IMX6SX_CLK_M4_PODF 112 +#define IMX6SX_CLK_ECSPI_PODF 113 +#define IMX6SX_CLK_LCDIF1_PRED 114 +#define IMX6SX_CLK_LCDIF2_PRED 115 +#define IMX6SX_CLK_DISPLAY_PODF 116 +#define IMX6SX_CLK_CSI_PODF 117 +#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118 +#define IMX6SX_CLK_LDB_DI0_DIV_7 119 +#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120 +#define IMX6SX_CLK_LDB_DI1_DIV_7 121 +#define IMX6SX_CLK_CKO1_PODF 122 +#define IMX6SX_CLK_CKO2_PODF 123 +#define IMX6SX_CLK_PERIPH 124 +#define IMX6SX_CLK_PERIPH2 125 +#define IMX6SX_CLK_OCRAM 126 +#define IMX6SX_CLK_AHB 127 +#define IMX6SX_CLK_MMDC_PODF 128 +#define IMX6SX_CLK_ARM 129 +#define IMX6SX_CLK_AIPS_TZ1 130 +#define IMX6SX_CLK_AIPS_TZ2 131 +#define IMX6SX_CLK_APBH_DMA 132 +#define IMX6SX_CLK_ASRC_GATE 133 +#define IMX6SX_CLK_CAAM_MEM 134 +#define IMX6SX_CLK_CAAM_ACLK 135 +#define IMX6SX_CLK_CAAM_IPG 136 +#define IMX6SX_CLK_CAN1_IPG 137 +#define IMX6SX_CLK_CAN1_SERIAL 138 +#define IMX6SX_CLK_CAN2_IPG 139 +#define IMX6SX_CLK_CAN2_SERIAL 140 +#define IMX6SX_CLK_CPU_DEBUG 141 +#define IMX6SX_CLK_DCIC1 142 +#define IMX6SX_CLK_DCIC2 143 +#define IMX6SX_CLK_AIPS_TZ3 144 +#define IMX6SX_CLK_ECSPI1 145 +#define IMX6SX_CLK_ECSPI2 146 +#define IMX6SX_CLK_ECSPI3 147 +#define IMX6SX_CLK_ECSPI4 148 +#define IMX6SX_CLK_ECSPI5 149 +#define IMX6SX_CLK_EPIT1 150 +#define IMX6SX_CLK_EPIT2 151 +#define IMX6SX_CLK_ESAI_EXTAL 152 +#define IMX6SX_CLK_WAKEUP 153 +#define IMX6SX_CLK_GPT_BUS 154 +#define IMX6SX_CLK_GPT_SERIAL 155 +#define IMX6SX_CLK_GPU 156 +#define IMX6SX_CLK_OCRAM_S 157 +#define IMX6SX_CLK_CANFD 158 +#define IMX6SX_CLK_CSI 159 +#define IMX6SX_CLK_I2C1 160 +#define IMX6SX_CLK_I2C2 161 +#define IMX6SX_CLK_I2C3 162 +#define IMX6SX_CLK_OCOTP 163 +#define IMX6SX_CLK_IOMUXC 164 +#define IMX6SX_CLK_IPMUX1 165 +#define IMX6SX_CLK_IPMUX2 166 +#define IMX6SX_CLK_IPMUX3 167 +#define IMX6SX_CLK_TZASC1 168 +#define IMX6SX_CLK_LCDIF_APB 169 +#define IMX6SX_CLK_PXP_AXI 170 +#define IMX6SX_CLK_M4 171 +#define IMX6SX_CLK_ENET 172 +#define IMX6SX_CLK_DISPLAY_AXI 173 +#define IMX6SX_CLK_LCDIF2_PIX 174 +#define IMX6SX_CLK_LCDIF1_PIX 175 +#define IMX6SX_CLK_LDB_DI0 176 +#define IMX6SX_CLK_QSPI1 177 +#define IMX6SX_CLK_MLB 178 +#define IMX6SX_CLK_MMDC_P0_FAST 179 +#define IMX6SX_CLK_MMDC_P0_IPG 180 +#define IMX6SX_CLK_AXI 181 +#define IMX6SX_CLK_PCIE_AXI 182 +#define IMX6SX_CLK_QSPI2 183 +#define IMX6SX_CLK_PER1_BCH 184 +#define IMX6SX_CLK_PER2_MAIN 185 +#define IMX6SX_CLK_PWM1 186 +#define IMX6SX_CLK_PWM2 187 +#define IMX6SX_CLK_PWM3 188 +#define IMX6SX_CLK_PWM4 189 +#define IMX6SX_CLK_GPMI_BCH_APB 190 +#define IMX6SX_CLK_GPMI_BCH 191 +#define IMX6SX_CLK_GPMI_IO 192 +#define IMX6SX_CLK_GPMI_APB 193 +#define IMX6SX_CLK_ROM 194 +#define IMX6SX_CLK_SDMA 195 +#define IMX6SX_CLK_SPBA 196 +#define IMX6SX_CLK_SPDIF 197 +#define IMX6SX_CLK_SSI1_IPG 198 +#define IMX6SX_CLK_SSI2_IPG 199 +#define IMX6SX_CLK_SSI3_IPG 200 +#define IMX6SX_CLK_SSI1 201 +#define IMX6SX_CLK_SSI2 202 +#define IMX6SX_CLK_SSI3 203 +#define IMX6SX_CLK_UART_IPG 204 +#define IMX6SX_CLK_UART_SERIAL 205 +#define IMX6SX_CLK_SAI1 206 +#define IMX6SX_CLK_SAI2 207 +#define IMX6SX_CLK_USBOH3 208 +#define IMX6SX_CLK_USDHC1 209 +#define IMX6SX_CLK_USDHC2 210 +#define IMX6SX_CLK_USDHC3 211 +#define IMX6SX_CLK_USDHC4 212 +#define IMX6SX_CLK_EIM_SLOW 213 +#define IMX6SX_CLK_PWM8 214 +#define IMX6SX_CLK_VADC 215 +#define IMX6SX_CLK_GIS 216 +#define IMX6SX_CLK_I2C4 217 +#define IMX6SX_CLK_PWM5 218 +#define IMX6SX_CLK_PWM6 219 +#define IMX6SX_CLK_PWM7 220 +#define IMX6SX_CLK_CKO1 221 +#define IMX6SX_CLK_CKO2 222 +#define IMX6SX_CLK_IPP_DI0 223 +#define IMX6SX_CLK_IPP_DI1 224 +#define IMX6SX_CLK_ENET_AHB 225 +#define IMX6SX_CLK_OCRAM_PODF 226 +#define IMX6SX_CLK_GPT_3M 227 +#define IMX6SX_CLK_ENET_PTP 228 +#define IMX6SX_CLK_ENET_PTP_REF 229 +#define IMX6SX_CLK_ENET2_REF 230 +#define IMX6SX_CLK_ENET2_REF_125M 231 +#define IMX6SX_CLK_AUDIO 232 +#define IMX6SX_CLK_LVDS1_SEL 233 +#define IMX6SX_CLK_LVDS1_OUT 234 +#define IMX6SX_CLK_ASRC_IPG 235 +#define IMX6SX_CLK_ASRC_MEM 236 +#define IMX6SX_CLK_SAI1_IPG 237 +#define IMX6SX_CLK_SAI2_IPG 238 +#define IMX6SX_CLK_ESAI_IPG 239 +#define IMX6SX_CLK_ESAI_MEM 240 +#define IMX6SX_CLK_LVDS1_IN 241 +#define IMX6SX_CLK_ANACLK1 242 +#define IMX6SX_PLL1_BYPASS_SRC 243 +#define IMX6SX_PLL2_BYPASS_SRC 244 +#define IMX6SX_PLL3_BYPASS_SRC 245 +#define IMX6SX_PLL4_BYPASS_SRC 246 +#define IMX6SX_PLL5_BYPASS_SRC 247 +#define IMX6SX_PLL6_BYPASS_SRC 248 +#define IMX6SX_PLL7_BYPASS_SRC 249 +#define IMX6SX_CLK_PLL1 250 +#define IMX6SX_CLK_PLL2 251 +#define IMX6SX_CLK_PLL3 252 +#define IMX6SX_CLK_PLL4 253 +#define IMX6SX_CLK_PLL5 254 +#define IMX6SX_CLK_PLL6 255 +#define IMX6SX_CLK_PLL7 256 +#define IMX6SX_PLL1_BYPASS 257 +#define IMX6SX_PLL2_BYPASS 258 +#define IMX6SX_PLL3_BYPASS 259 +#define IMX6SX_PLL4_BYPASS 260 +#define IMX6SX_PLL5_BYPASS 261 +#define IMX6SX_PLL6_BYPASS 262 +#define IMX6SX_PLL7_BYPASS 263 +#define IMX6SX_CLK_SPDIF_GCLK 264 +#define IMX6SX_CLK_LVDS2_SEL 265 +#define IMX6SX_CLK_LVDS2_OUT 266 +#define IMX6SX_CLK_LVDS2_IN 267 +#define IMX6SX_CLK_ANACLK2 268 +#define IMX6SX_CLK_MMDC_P1_IPG 269 +#define IMX6SX_CLK_CLK_END 270 + +#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/imx6ul-clock.h b/roms/u-boot/include/dt-bindings/clock/imx6ul-clock.h new file mode 100644 index 000000000..79094338e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/imx6ul-clock.h @@ -0,0 +1,262 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H +#define __DT_BINDINGS_CLOCK_IMX6UL_H + +#define IMX6UL_CLK_DUMMY 0 +#define IMX6UL_CLK_CKIL 1 +#define IMX6UL_CLK_CKIH 2 +#define IMX6UL_CLK_OSC 3 +#define IMX6UL_PLL1_BYPASS_SRC 4 +#define IMX6UL_PLL2_BYPASS_SRC 5 +#define IMX6UL_PLL3_BYPASS_SRC 6 +#define IMX6UL_PLL4_BYPASS_SRC 7 +#define IMX6UL_PLL5_BYPASS_SRC 8 +#define IMX6UL_PLL6_BYPASS_SRC 9 +#define IMX6UL_PLL7_BYPASS_SRC 10 +#define IMX6UL_CLK_PLL1 11 +#define IMX6UL_CLK_PLL2 12 +#define IMX6UL_CLK_PLL3 13 +#define IMX6UL_CLK_PLL4 14 +#define IMX6UL_CLK_PLL5 15 +#define IMX6UL_CLK_PLL6 16 +#define IMX6UL_CLK_PLL7 17 +#define IMX6UL_PLL1_BYPASS 18 +#define IMX6UL_PLL2_BYPASS 19 +#define IMX6UL_PLL3_BYPASS 20 +#define IMX6UL_PLL4_BYPASS 21 +#define IMX6UL_PLL5_BYPASS 22 +#define IMX6UL_PLL6_BYPASS 23 +#define IMX6UL_PLL7_BYPASS 24 +#define IMX6UL_CLK_PLL1_SYS 25 +#define IMX6UL_CLK_PLL2_BUS 26 +#define IMX6UL_CLK_PLL3_USB_OTG 27 +#define IMX6UL_CLK_PLL4_AUDIO 28 +#define IMX6UL_CLK_PLL5_VIDEO 29 +#define IMX6UL_CLK_PLL6_ENET 30 +#define IMX6UL_CLK_PLL7_USB_HOST 31 +#define IMX6UL_CLK_USBPHY1 32 +#define IMX6UL_CLK_USBPHY2 33 +#define IMX6UL_CLK_USBPHY1_GATE 34 +#define IMX6UL_CLK_USBPHY2_GATE 35 +#define IMX6UL_CLK_PLL2_PFD0 36 +#define IMX6UL_CLK_PLL2_PFD1 37 +#define IMX6UL_CLK_PLL2_PFD2 38 +#define IMX6UL_CLK_PLL2_PFD3 39 +#define IMX6UL_CLK_PLL3_PFD0 40 +#define IMX6UL_CLK_PLL3_PFD1 41 +#define IMX6UL_CLK_PLL3_PFD2 42 +#define IMX6UL_CLK_PLL3_PFD3 43 +#define IMX6UL_CLK_ENET_REF 44 +#define IMX6UL_CLK_ENET2_REF 45 +#define IMX6UL_CLK_ENET2_REF_125M 46 +#define IMX6UL_CLK_ENET_PTP_REF 47 +#define IMX6UL_CLK_ENET_PTP 48 +#define IMX6UL_CLK_PLL4_POST_DIV 49 +#define IMX6UL_CLK_PLL4_AUDIO_DIV 50 +#define IMX6UL_CLK_PLL5_POST_DIV 51 +#define IMX6UL_CLK_PLL5_VIDEO_DIV 52 +#define IMX6UL_CLK_PLL2_198M 53 +#define IMX6UL_CLK_PLL3_80M 54 +#define IMX6UL_CLK_PLL3_60M 55 +#define IMX6UL_CLK_STEP 56 +#define IMX6UL_CLK_PLL1_SW 57 +#define IMX6UL_CLK_AXI_ALT_SEL 58 +#define IMX6UL_CLK_AXI_SEL 59 +#define IMX6UL_CLK_PERIPH_PRE 60 +#define IMX6UL_CLK_PERIPH2_PRE 61 +#define IMX6UL_CLK_PERIPH_CLK2_SEL 62 +#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63 +#define IMX6UL_CLK_USDHC1_SEL 64 +#define IMX6UL_CLK_USDHC2_SEL 65 +#define IMX6UL_CLK_BCH_SEL 66 +#define IMX6UL_CLK_GPMI_SEL 67 +#define IMX6UL_CLK_EIM_SLOW_SEL 68 +#define IMX6UL_CLK_SPDIF_SEL 69 +#define IMX6UL_CLK_SAI1_SEL 70 +#define IMX6UL_CLK_SAI2_SEL 71 +#define IMX6UL_CLK_SAI3_SEL 72 +#define IMX6UL_CLK_LCDIF_PRE_SEL 73 +#define IMX6UL_CLK_SIM_PRE_SEL 74 +#define IMX6UL_CLK_LDB_DI0_SEL 75 +#define IMX6UL_CLK_LDB_DI1_SEL 76 +#define IMX6UL_CLK_ENFC_SEL 77 +#define IMX6UL_CLK_CAN_SEL 78 +#define IMX6UL_CLK_ECSPI_SEL 79 +#define IMX6UL_CLK_UART_SEL 80 +#define IMX6UL_CLK_QSPI1_SEL 81 +#define IMX6UL_CLK_PERCLK_SEL 82 +#define IMX6UL_CLK_LCDIF_SEL 83 +#define IMX6UL_CLK_SIM_SEL 84 +#define IMX6UL_CLK_PERIPH 85 +#define IMX6UL_CLK_PERIPH2 86 +#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87 +#define IMX6UL_CLK_LDB_DI0_DIV_7 88 +#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89 +#define IMX6UL_CLK_LDB_DI1_DIV_7 90 +#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91 +#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92 +#define IMX6UL_CLK_ARM 93 +#define IMX6UL_CLK_PERIPH_CLK2 94 +#define IMX6UL_CLK_PERIPH2_CLK2 95 +#define IMX6UL_CLK_AHB 96 +#define IMX6UL_CLK_MMDC_PODF 97 +#define IMX6UL_CLK_AXI_PODF 98 +#define IMX6UL_CLK_PERCLK 99 +#define IMX6UL_CLK_IPG 100 +#define IMX6UL_CLK_USDHC1_PODF 101 +#define IMX6UL_CLK_USDHC2_PODF 102 +#define IMX6UL_CLK_BCH_PODF 103 +#define IMX6UL_CLK_GPMI_PODF 104 +#define IMX6UL_CLK_EIM_SLOW_PODF 105 +#define IMX6UL_CLK_SPDIF_PRED 106 +#define IMX6UL_CLK_SPDIF_PODF 107 +#define IMX6UL_CLK_SAI1_PRED 108 +#define IMX6UL_CLK_SAI1_PODF 109 +#define IMX6UL_CLK_SAI2_PRED 110 +#define IMX6UL_CLK_SAI2_PODF 111 +#define IMX6UL_CLK_SAI3_PRED 112 +#define IMX6UL_CLK_SAI3_PODF 113 +#define IMX6UL_CLK_LCDIF_PRED 114 +#define IMX6UL_CLK_LCDIF_PODF 115 +#define IMX6UL_CLK_SIM_PODF 116 +#define IMX6UL_CLK_QSPI1_PDOF 117 +#define IMX6UL_CLK_ENFC_PRED 118 +#define IMX6UL_CLK_ENFC_PODF 119 +#define IMX6UL_CLK_CAN_PODF 120 +#define IMX6UL_CLK_ECSPI_PODF 121 +#define IMX6UL_CLK_UART_PODF 122 +#define IMX6UL_CLK_ADC1 123 +#define IMX6UL_CLK_ADC2 124 +#define IMX6UL_CLK_AIPSTZ1 125 +#define IMX6UL_CLK_AIPSTZ2 126 +#define IMX6UL_CLK_AIPSTZ3 127 +#define IMX6UL_CLK_APBHDMA 128 +#define IMX6UL_CLK_ASRC_IPG 129 +#define IMX6UL_CLK_ASRC_MEM 130 +#define IMX6UL_CLK_GPMI_BCH_APB 131 +#define IMX6UL_CLK_GPMI_BCH 132 +#define IMX6UL_CLK_GPMI_IO 133 +#define IMX6UL_CLK_GPMI_APB 134 +#define IMX6UL_CLK_CAAM_MEM 135 +#define IMX6UL_CLK_CAAM_ACLK 136 +#define IMX6UL_CLK_CAAM_IPG 137 +#define IMX6UL_CLK_CSI 138 +#define IMX6UL_CLK_ECSPI1 139 +#define IMX6UL_CLK_ECSPI2 140 +#define IMX6UL_CLK_ECSPI3 141 +#define IMX6UL_CLK_ECSPI4 142 +#define IMX6UL_CLK_EIM 143 +#define IMX6UL_CLK_ENET 144 +#define IMX6UL_CLK_ENET_AHB 145 +#define IMX6UL_CLK_EPIT1 146 +#define IMX6UL_CLK_EPIT2 147 +#define IMX6UL_CLK_CAN1_IPG 148 +#define IMX6UL_CLK_CAN1_SERIAL 149 +#define IMX6UL_CLK_CAN2_IPG 150 +#define IMX6UL_CLK_CAN2_SERIAL 151 +#define IMX6UL_CLK_GPT1_BUS 152 +#define IMX6UL_CLK_GPT1_SERIAL 153 +#define IMX6UL_CLK_GPT2_BUS 154 +#define IMX6UL_CLK_GPT2_SERIAL 155 +#define IMX6UL_CLK_I2C1 156 +#define IMX6UL_CLK_I2C2 157 +#define IMX6UL_CLK_I2C3 158 +#define IMX6UL_CLK_I2C4 159 +#define IMX6UL_CLK_IOMUXC 160 +#define IMX6UL_CLK_LCDIF_APB 161 +#define IMX6UL_CLK_LCDIF_PIX 162 +#define IMX6UL_CLK_MMDC_P0_FAST 163 +#define IMX6UL_CLK_MMDC_P0_IPG 164 +#define IMX6UL_CLK_OCOTP 165 +#define IMX6UL_CLK_OCRAM 166 +#define IMX6UL_CLK_PWM1 167 +#define IMX6UL_CLK_PWM2 168 +#define IMX6UL_CLK_PWM3 169 +#define IMX6UL_CLK_PWM4 170 +#define IMX6UL_CLK_PWM5 171 +#define IMX6UL_CLK_PWM6 172 +#define IMX6UL_CLK_PWM7 173 +#define IMX6UL_CLK_PWM8 174 +#define IMX6UL_CLK_PXP 175 +#define IMX6UL_CLK_QSPI 176 +#define IMX6UL_CLK_ROM 177 +#define IMX6UL_CLK_SAI1 178 +#define IMX6UL_CLK_SAI1_IPG 179 +#define IMX6UL_CLK_SAI2 180 +#define IMX6UL_CLK_SAI2_IPG 181 +#define IMX6UL_CLK_SAI3 182 +#define IMX6UL_CLK_SAI3_IPG 183 +#define IMX6UL_CLK_SDMA 184 +#define IMX6UL_CLK_SIM 185 +#define IMX6UL_CLK_SIM_S 186 +#define IMX6UL_CLK_SPBA 187 +#define IMX6UL_CLK_SPDIF 188 +#define IMX6UL_CLK_UART1_IPG 189 +#define IMX6UL_CLK_UART1_SERIAL 190 +#define IMX6UL_CLK_UART2_IPG 191 +#define IMX6UL_CLK_UART2_SERIAL 192 +#define IMX6UL_CLK_UART3_IPG 193 +#define IMX6UL_CLK_UART3_SERIAL 194 +#define IMX6UL_CLK_UART4_IPG 195 +#define IMX6UL_CLK_UART4_SERIAL 196 +#define IMX6UL_CLK_UART5_IPG 197 +#define IMX6UL_CLK_UART5_SERIAL 198 +#define IMX6UL_CLK_UART6_IPG 199 +#define IMX6UL_CLK_UART6_SERIAL 200 +#define IMX6UL_CLK_UART7_IPG 201 +#define IMX6UL_CLK_UART7_SERIAL 202 +#define IMX6UL_CLK_UART8_IPG 203 +#define IMX6UL_CLK_UART8_SERIAL 204 +#define IMX6UL_CLK_USBOH3 205 +#define IMX6UL_CLK_USDHC1 206 +#define IMX6UL_CLK_USDHC2 207 +#define IMX6UL_CLK_WDOG1 208 +#define IMX6UL_CLK_WDOG2 209 +#define IMX6UL_CLK_WDOG3 210 +#define IMX6UL_CLK_LDB_DI0 211 +#define IMX6UL_CLK_AXI 212 +#define IMX6UL_CLK_SPDIF_GCLK 213 +#define IMX6UL_CLK_GPT_3M 214 +#define IMX6UL_CLK_SIM2 215 +#define IMX6UL_CLK_SIM1 216 +#define IMX6UL_CLK_IPP_DI0 217 +#define IMX6UL_CLK_IPP_DI1 218 +#define IMX6UL_CA7_SECONDARY_SEL 219 +#define IMX6UL_CLK_PER_BCH 220 +#define IMX6UL_CLK_CSI_SEL 221 +#define IMX6UL_CLK_CSI_PODF 222 +#define IMX6UL_CLK_PLL3_120M 223 +#define IMX6UL_CLK_KPP 224 +#define IMX6ULL_CLK_ESAI_PRED 225 +#define IMX6ULL_CLK_ESAI_PODF 226 +#define IMX6ULL_CLK_ESAI_EXTAL 227 +#define IMX6ULL_CLK_ESAI_MEM 228 +#define IMX6ULL_CLK_ESAI_IPG 229 +#define IMX6ULL_CLK_DCP_CLK 230 +#define IMX6ULL_CLK_EPDC_PRE_SEL 231 +#define IMX6ULL_CLK_EPDC_SEL 232 +#define IMX6ULL_CLK_EPDC_PODF 233 +#define IMX6ULL_CLK_EPDC_ACLK 234 +#define IMX6ULL_CLK_EPDC_PIX 235 +#define IMX6ULL_CLK_ESAI_SEL 236 +#define IMX6UL_CLK_CKO1_SEL 237 +#define IMX6UL_CLK_CKO1_PODF 238 +#define IMX6UL_CLK_CKO1 239 +#define IMX6UL_CLK_CKO2_SEL 240 +#define IMX6UL_CLK_CKO2_PODF 241 +#define IMX6UL_CLK_CKO2 242 +#define IMX6UL_CLK_CKO 243 +#define IMX6UL_CLK_GPIO1 244 +#define IMX6UL_CLK_GPIO2 245 +#define IMX6UL_CLK_GPIO3 246 +#define IMX6UL_CLK_GPIO4 247 +#define IMX6UL_CLK_GPIO5 248 +#define IMX6UL_CLK_MMDC_P1_IPG 249 + +#define IMX6UL_CLK_END 250 + +#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/imx7d-clock.h b/roms/u-boot/include/dt-bindings/clock/imx7d-clock.h new file mode 100644 index 000000000..b2325d3e2 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/imx7d-clock.h @@ -0,0 +1,459 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX7D_H +#define __DT_BINDINGS_CLOCK_IMX7D_H + +#define IMX7D_OSC_24M_CLK 0 +#define IMX7D_PLL_ARM_MAIN 1 +#define IMX7D_PLL_ARM_MAIN_CLK 2 +#define IMX7D_PLL_ARM_MAIN_SRC 3 +#define IMX7D_PLL_ARM_MAIN_BYPASS 4 +#define IMX7D_PLL_SYS_MAIN 5 +#define IMX7D_PLL_SYS_MAIN_CLK 6 +#define IMX7D_PLL_SYS_MAIN_SRC 7 +#define IMX7D_PLL_SYS_MAIN_BYPASS 8 +#define IMX7D_PLL_SYS_MAIN_480M 9 +#define IMX7D_PLL_SYS_MAIN_240M 10 +#define IMX7D_PLL_SYS_MAIN_120M 11 +#define IMX7D_PLL_SYS_MAIN_480M_CLK 12 +#define IMX7D_PLL_SYS_MAIN_240M_CLK 13 +#define IMX7D_PLL_SYS_MAIN_120M_CLK 14 +#define IMX7D_PLL_SYS_PFD0_392M_CLK 15 +#define IMX7D_PLL_SYS_PFD0_196M 16 +#define IMX7D_PLL_SYS_PFD0_196M_CLK 17 +#define IMX7D_PLL_SYS_PFD1_332M_CLK 18 +#define IMX7D_PLL_SYS_PFD1_166M 19 +#define IMX7D_PLL_SYS_PFD1_166M_CLK 20 +#define IMX7D_PLL_SYS_PFD2_270M_CLK 21 +#define IMX7D_PLL_SYS_PFD2_135M 22 +#define IMX7D_PLL_SYS_PFD2_135M_CLK 23 +#define IMX7D_PLL_SYS_PFD3_CLK 24 +#define IMX7D_PLL_SYS_PFD4_CLK 25 +#define IMX7D_PLL_SYS_PFD5_CLK 26 +#define IMX7D_PLL_SYS_PFD6_CLK 27 +#define IMX7D_PLL_SYS_PFD7_CLK 28 +#define IMX7D_PLL_ENET_MAIN 29 +#define IMX7D_PLL_ENET_MAIN_CLK 30 +#define IMX7D_PLL_ENET_MAIN_SRC 31 +#define IMX7D_PLL_ENET_MAIN_BYPASS 32 +#define IMX7D_PLL_ENET_MAIN_500M 33 +#define IMX7D_PLL_ENET_MAIN_250M 34 +#define IMX7D_PLL_ENET_MAIN_125M 35 +#define IMX7D_PLL_ENET_MAIN_100M 36 +#define IMX7D_PLL_ENET_MAIN_50M 37 +#define IMX7D_PLL_ENET_MAIN_40M 38 +#define IMX7D_PLL_ENET_MAIN_25M 39 +#define IMX7D_PLL_ENET_MAIN_500M_CLK 40 +#define IMX7D_PLL_ENET_MAIN_250M_CLK 41 +#define IMX7D_PLL_ENET_MAIN_125M_CLK 42 +#define IMX7D_PLL_ENET_MAIN_100M_CLK 43 +#define IMX7D_PLL_ENET_MAIN_50M_CLK 44 +#define IMX7D_PLL_ENET_MAIN_40M_CLK 45 +#define IMX7D_PLL_ENET_MAIN_25M_CLK 46 +#define IMX7D_PLL_DRAM_MAIN 47 +#define IMX7D_PLL_DRAM_MAIN_CLK 48 +#define IMX7D_PLL_DRAM_MAIN_SRC 49 +#define IMX7D_PLL_DRAM_MAIN_BYPASS 50 +#define IMX7D_PLL_DRAM_MAIN_533M 51 +#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52 +#define IMX7D_PLL_AUDIO_MAIN 53 +#define IMX7D_PLL_AUDIO_MAIN_CLK 54 +#define IMX7D_PLL_AUDIO_MAIN_SRC 55 +#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56 +#define IMX7D_PLL_VIDEO_MAIN_CLK 57 +#define IMX7D_PLL_VIDEO_MAIN 58 +#define IMX7D_PLL_VIDEO_MAIN_SRC 59 +#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60 +#define IMX7D_USB_MAIN_480M_CLK 61 +#define IMX7D_ARM_A7_ROOT_CLK 62 +#define IMX7D_ARM_A7_ROOT_SRC 63 +#define IMX7D_ARM_A7_ROOT_CG 64 +#define IMX7D_ARM_A7_ROOT_DIV 65 +#define IMX7D_ARM_M4_ROOT_CLK 66 +#define IMX7D_ARM_M4_ROOT_SRC 67 +#define IMX7D_ARM_M4_ROOT_CG 68 +#define IMX7D_ARM_M4_ROOT_DIV 69 +#define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */ +#define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */ +#define IMX7D_ARM_M0_ROOT_CG 72 /* unused */ +#define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */ +#define IMX7D_MAIN_AXI_ROOT_CLK 74 +#define IMX7D_MAIN_AXI_ROOT_SRC 75 +#define IMX7D_MAIN_AXI_ROOT_CG 76 +#define IMX7D_MAIN_AXI_ROOT_DIV 77 +#define IMX7D_DISP_AXI_ROOT_CLK 78 +#define IMX7D_DISP_AXI_ROOT_SRC 79 +#define IMX7D_DISP_AXI_ROOT_CG 80 +#define IMX7D_DISP_AXI_ROOT_DIV 81 +#define IMX7D_ENET_AXI_ROOT_CLK 82 +#define IMX7D_ENET_AXI_ROOT_SRC 83 +#define IMX7D_ENET_AXI_ROOT_CG 84 +#define IMX7D_ENET_AXI_ROOT_DIV 85 +#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 +#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 +#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 +#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 +#define IMX7D_AHB_CHANNEL_ROOT_CLK 90 +#define IMX7D_AHB_CHANNEL_ROOT_SRC 91 +#define IMX7D_AHB_CHANNEL_ROOT_CG 92 +#define IMX7D_AHB_CHANNEL_ROOT_DIV 93 +#define IMX7D_DRAM_PHYM_ROOT_CLK 94 +#define IMX7D_DRAM_PHYM_ROOT_SRC 95 +#define IMX7D_DRAM_PHYM_ROOT_CG 96 +#define IMX7D_DRAM_PHYM_ROOT_DIV 97 +#define IMX7D_DRAM_ROOT_CLK 98 +#define IMX7D_DRAM_ROOT_SRC 99 +#define IMX7D_DRAM_ROOT_CG 100 +#define IMX7D_DRAM_ROOT_DIV 101 +#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 +#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 +#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 +#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 +#define IMX7D_DRAM_ALT_ROOT_CLK 106 +#define IMX7D_DRAM_ALT_ROOT_SRC 107 +#define IMX7D_DRAM_ALT_ROOT_CG 108 +#define IMX7D_DRAM_ALT_ROOT_DIV 109 +#define IMX7D_USB_HSIC_ROOT_CLK 110 +#define IMX7D_USB_HSIC_ROOT_SRC 111 +#define IMX7D_USB_HSIC_ROOT_CG 112 +#define IMX7D_USB_HSIC_ROOT_DIV 113 +#define IMX7D_PCIE_CTRL_ROOT_CLK 114 +#define IMX7D_PCIE_CTRL_ROOT_SRC 115 +#define IMX7D_PCIE_CTRL_ROOT_CG 116 +#define IMX7D_PCIE_CTRL_ROOT_DIV 117 +#define IMX7D_PCIE_PHY_ROOT_CLK 118 +#define IMX7D_PCIE_PHY_ROOT_SRC 119 +#define IMX7D_PCIE_PHY_ROOT_CG 120 +#define IMX7D_PCIE_PHY_ROOT_DIV 121 +#define IMX7D_EPDC_PIXEL_ROOT_CLK 122 +#define IMX7D_EPDC_PIXEL_ROOT_SRC 123 +#define IMX7D_EPDC_PIXEL_ROOT_CG 124 +#define IMX7D_EPDC_PIXEL_ROOT_DIV 125 +#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 +#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 +#define IMX7D_LCDIF_PIXEL_ROOT_CG 128 +#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 +#define IMX7D_MIPI_DSI_ROOT_CLK 130 +#define IMX7D_MIPI_DSI_ROOT_SRC 131 +#define IMX7D_MIPI_DSI_ROOT_CG 132 +#define IMX7D_MIPI_DSI_ROOT_DIV 133 +#define IMX7D_MIPI_CSI_ROOT_CLK 134 +#define IMX7D_MIPI_CSI_ROOT_SRC 135 +#define IMX7D_MIPI_CSI_ROOT_CG 136 +#define IMX7D_MIPI_CSI_ROOT_DIV 137 +#define IMX7D_MIPI_DPHY_ROOT_CLK 138 +#define IMX7D_MIPI_DPHY_ROOT_SRC 139 +#define IMX7D_MIPI_DPHY_ROOT_CG 140 +#define IMX7D_MIPI_DPHY_ROOT_DIV 141 +#define IMX7D_SAI1_ROOT_CLK 142 +#define IMX7D_SAI1_ROOT_SRC 143 +#define IMX7D_SAI1_ROOT_CG 144 +#define IMX7D_SAI1_ROOT_DIV 145 +#define IMX7D_SAI2_ROOT_CLK 146 +#define IMX7D_SAI2_ROOT_SRC 147 +#define IMX7D_SAI2_ROOT_CG 148 +#define IMX7D_SAI2_ROOT_DIV 149 +#define IMX7D_SAI3_ROOT_CLK 150 +#define IMX7D_SAI3_ROOT_SRC 151 +#define IMX7D_SAI3_ROOT_CG 152 +#define IMX7D_SAI3_ROOT_DIV 153 +#define IMX7D_SPDIF_ROOT_CLK 154 +#define IMX7D_SPDIF_ROOT_SRC 155 +#define IMX7D_SPDIF_ROOT_CG 156 +#define IMX7D_SPDIF_ROOT_DIV 157 +#define IMX7D_ENET1_REF_ROOT_CLK 158 +#define IMX7D_ENET1_REF_ROOT_SRC 159 +#define IMX7D_ENET1_REF_ROOT_CG 160 +#define IMX7D_ENET1_REF_ROOT_DIV 161 +#define IMX7D_ENET1_TIME_ROOT_CLK 162 +#define IMX7D_ENET1_TIME_ROOT_SRC 163 +#define IMX7D_ENET1_TIME_ROOT_CG 164 +#define IMX7D_ENET1_TIME_ROOT_DIV 165 +#define IMX7D_ENET2_REF_ROOT_CLK 166 +#define IMX7D_ENET2_REF_ROOT_SRC 167 +#define IMX7D_ENET2_REF_ROOT_CG 168 +#define IMX7D_ENET2_REF_ROOT_DIV 169 +#define IMX7D_ENET2_TIME_ROOT_CLK 170 +#define IMX7D_ENET2_TIME_ROOT_SRC 171 +#define IMX7D_ENET2_TIME_ROOT_CG 172 +#define IMX7D_ENET2_TIME_ROOT_DIV 173 +#define IMX7D_ENET_PHY_REF_ROOT_CLK 174 +#define IMX7D_ENET_PHY_REF_ROOT_SRC 175 +#define IMX7D_ENET_PHY_REF_ROOT_CG 176 +#define IMX7D_ENET_PHY_REF_ROOT_DIV 177 +#define IMX7D_EIM_ROOT_CLK 178 +#define IMX7D_EIM_ROOT_SRC 179 +#define IMX7D_EIM_ROOT_CG 180 +#define IMX7D_EIM_ROOT_DIV 181 +#define IMX7D_NAND_ROOT_CLK 182 +#define IMX7D_NAND_ROOT_SRC 183 +#define IMX7D_NAND_ROOT_CG 184 +#define IMX7D_NAND_ROOT_DIV 185 +#define IMX7D_QSPI_ROOT_CLK 186 +#define IMX7D_QSPI_ROOT_SRC 187 +#define IMX7D_QSPI_ROOT_CG 188 +#define IMX7D_QSPI_ROOT_DIV 189 +#define IMX7D_USDHC1_ROOT_CLK 190 +#define IMX7D_USDHC1_ROOT_SRC 191 +#define IMX7D_USDHC1_ROOT_CG 192 +#define IMX7D_USDHC1_ROOT_DIV 193 +#define IMX7D_USDHC2_ROOT_CLK 194 +#define IMX7D_USDHC2_ROOT_SRC 195 +#define IMX7D_USDHC2_ROOT_CG 196 +#define IMX7D_USDHC2_ROOT_DIV 197 +#define IMX7D_USDHC3_ROOT_CLK 198 +#define IMX7D_USDHC3_ROOT_SRC 199 +#define IMX7D_USDHC3_ROOT_CG 200 +#define IMX7D_USDHC3_ROOT_DIV 201 +#define IMX7D_CAN1_ROOT_CLK 202 +#define IMX7D_CAN1_ROOT_SRC 203 +#define IMX7D_CAN1_ROOT_CG 204 +#define IMX7D_CAN1_ROOT_DIV 205 +#define IMX7D_CAN2_ROOT_CLK 206 +#define IMX7D_CAN2_ROOT_SRC 207 +#define IMX7D_CAN2_ROOT_CG 208 +#define IMX7D_CAN2_ROOT_DIV 209 +#define IMX7D_I2C1_ROOT_CLK 210 +#define IMX7D_I2C1_ROOT_SRC 211 +#define IMX7D_I2C1_ROOT_CG 212 +#define IMX7D_I2C1_ROOT_DIV 213 +#define IMX7D_I2C2_ROOT_CLK 214 +#define IMX7D_I2C2_ROOT_SRC 215 +#define IMX7D_I2C2_ROOT_CG 216 +#define IMX7D_I2C2_ROOT_DIV 217 +#define IMX7D_I2C3_ROOT_CLK 218 +#define IMX7D_I2C3_ROOT_SRC 219 +#define IMX7D_I2C3_ROOT_CG 220 +#define IMX7D_I2C3_ROOT_DIV 221 +#define IMX7D_I2C4_ROOT_CLK 222 +#define IMX7D_I2C4_ROOT_SRC 223 +#define IMX7D_I2C4_ROOT_CG 224 +#define IMX7D_I2C4_ROOT_DIV 225 +#define IMX7D_UART1_ROOT_CLK 226 +#define IMX7D_UART1_ROOT_SRC 227 +#define IMX7D_UART1_ROOT_CG 228 +#define IMX7D_UART1_ROOT_DIV 229 +#define IMX7D_UART2_ROOT_CLK 230 +#define IMX7D_UART2_ROOT_SRC 231 +#define IMX7D_UART2_ROOT_CG 232 +#define IMX7D_UART2_ROOT_DIV 233 +#define IMX7D_UART3_ROOT_CLK 234 +#define IMX7D_UART3_ROOT_SRC 235 +#define IMX7D_UART3_ROOT_CG 236 +#define IMX7D_UART3_ROOT_DIV 237 +#define IMX7D_UART4_ROOT_CLK 238 +#define IMX7D_UART4_ROOT_SRC 239 +#define IMX7D_UART4_ROOT_CG 240 +#define IMX7D_UART4_ROOT_DIV 241 +#define IMX7D_UART5_ROOT_CLK 242 +#define IMX7D_UART5_ROOT_SRC 243 +#define IMX7D_UART5_ROOT_CG 244 +#define IMX7D_UART5_ROOT_DIV 245 +#define IMX7D_UART6_ROOT_CLK 246 +#define IMX7D_UART6_ROOT_SRC 247 +#define IMX7D_UART6_ROOT_CG 248 +#define IMX7D_UART6_ROOT_DIV 249 +#define IMX7D_UART7_ROOT_CLK 250 +#define IMX7D_UART7_ROOT_SRC 251 +#define IMX7D_UART7_ROOT_CG 252 +#define IMX7D_UART7_ROOT_DIV 253 +#define IMX7D_ECSPI1_ROOT_CLK 254 +#define IMX7D_ECSPI1_ROOT_SRC 255 +#define IMX7D_ECSPI1_ROOT_CG 256 +#define IMX7D_ECSPI1_ROOT_DIV 257 +#define IMX7D_ECSPI2_ROOT_CLK 258 +#define IMX7D_ECSPI2_ROOT_SRC 259 +#define IMX7D_ECSPI2_ROOT_CG 260 +#define IMX7D_ECSPI2_ROOT_DIV 261 +#define IMX7D_ECSPI3_ROOT_CLK 262 +#define IMX7D_ECSPI3_ROOT_SRC 263 +#define IMX7D_ECSPI3_ROOT_CG 264 +#define IMX7D_ECSPI3_ROOT_DIV 265 +#define IMX7D_ECSPI4_ROOT_CLK 266 +#define IMX7D_ECSPI4_ROOT_SRC 267 +#define IMX7D_ECSPI4_ROOT_CG 268 +#define IMX7D_ECSPI4_ROOT_DIV 269 +#define IMX7D_PWM1_ROOT_CLK 270 +#define IMX7D_PWM1_ROOT_SRC 271 +#define IMX7D_PWM1_ROOT_CG 272 +#define IMX7D_PWM1_ROOT_DIV 273 +#define IMX7D_PWM2_ROOT_CLK 274 +#define IMX7D_PWM2_ROOT_SRC 275 +#define IMX7D_PWM2_ROOT_CG 276 +#define IMX7D_PWM2_ROOT_DIV 277 +#define IMX7D_PWM3_ROOT_CLK 278 +#define IMX7D_PWM3_ROOT_SRC 279 +#define IMX7D_PWM3_ROOT_CG 280 +#define IMX7D_PWM3_ROOT_DIV 281 +#define IMX7D_PWM4_ROOT_CLK 282 +#define IMX7D_PWM4_ROOT_SRC 283 +#define IMX7D_PWM4_ROOT_CG 284 +#define IMX7D_PWM4_ROOT_DIV 285 +#define IMX7D_FLEXTIMER1_ROOT_CLK 286 +#define IMX7D_FLEXTIMER1_ROOT_SRC 287 +#define IMX7D_FLEXTIMER1_ROOT_CG 288 +#define IMX7D_FLEXTIMER1_ROOT_DIV 289 +#define IMX7D_FLEXTIMER2_ROOT_CLK 290 +#define IMX7D_FLEXTIMER2_ROOT_SRC 291 +#define IMX7D_FLEXTIMER2_ROOT_CG 292 +#define IMX7D_FLEXTIMER2_ROOT_DIV 293 +#define IMX7D_SIM1_ROOT_CLK 294 +#define IMX7D_SIM1_ROOT_SRC 295 +#define IMX7D_SIM1_ROOT_CG 296 +#define IMX7D_SIM1_ROOT_DIV 297 +#define IMX7D_SIM2_ROOT_CLK 298 +#define IMX7D_SIM2_ROOT_SRC 299 +#define IMX7D_SIM2_ROOT_CG 300 +#define IMX7D_SIM2_ROOT_DIV 301 +#define IMX7D_GPT1_ROOT_CLK 302 +#define IMX7D_GPT1_ROOT_SRC 303 +#define IMX7D_GPT1_ROOT_CG 304 +#define IMX7D_GPT1_ROOT_DIV 305 +#define IMX7D_GPT2_ROOT_CLK 306 +#define IMX7D_GPT2_ROOT_SRC 307 +#define IMX7D_GPT2_ROOT_CG 308 +#define IMX7D_GPT2_ROOT_DIV 309 +#define IMX7D_GPT3_ROOT_CLK 310 +#define IMX7D_GPT3_ROOT_SRC 311 +#define IMX7D_GPT3_ROOT_CG 312 +#define IMX7D_GPT3_ROOT_DIV 313 +#define IMX7D_GPT4_ROOT_CLK 314 +#define IMX7D_GPT4_ROOT_SRC 315 +#define IMX7D_GPT4_ROOT_CG 316 +#define IMX7D_GPT4_ROOT_DIV 317 +#define IMX7D_TRACE_ROOT_CLK 318 +#define IMX7D_TRACE_ROOT_SRC 319 +#define IMX7D_TRACE_ROOT_CG 320 +#define IMX7D_TRACE_ROOT_DIV 321 +#define IMX7D_WDOG1_ROOT_CLK 322 +#define IMX7D_WDOG_ROOT_SRC 323 +#define IMX7D_WDOG_ROOT_CG 324 +#define IMX7D_WDOG_ROOT_DIV 325 +#define IMX7D_CSI_MCLK_ROOT_CLK 326 +#define IMX7D_CSI_MCLK_ROOT_SRC 327 +#define IMX7D_CSI_MCLK_ROOT_CG 328 +#define IMX7D_CSI_MCLK_ROOT_DIV 329 +#define IMX7D_AUDIO_MCLK_ROOT_CLK 330 +#define IMX7D_AUDIO_MCLK_ROOT_SRC 331 +#define IMX7D_AUDIO_MCLK_ROOT_CG 332 +#define IMX7D_AUDIO_MCLK_ROOT_DIV 333 +#define IMX7D_WRCLK_ROOT_CLK 334 +#define IMX7D_WRCLK_ROOT_SRC 335 +#define IMX7D_WRCLK_ROOT_CG 336 +#define IMX7D_WRCLK_ROOT_DIV 337 +#define IMX7D_CLKO1_ROOT_SRC 338 +#define IMX7D_CLKO1_ROOT_CG 339 +#define IMX7D_CLKO1_ROOT_DIV 340 +#define IMX7D_CLKO2_ROOT_SRC 341 +#define IMX7D_CLKO2_ROOT_CG 342 +#define IMX7D_CLKO2_ROOT_DIV 343 +#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 +#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 +#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 +#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 +#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 +#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 +#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 +#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 +#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 +#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 +#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 +#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 +#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 +#define IMX7D_SAI1_ROOT_PRE_DIV 357 +#define IMX7D_SAI2_ROOT_PRE_DIV 358 +#define IMX7D_SAI3_ROOT_PRE_DIV 359 +#define IMX7D_SPDIF_ROOT_PRE_DIV 360 +#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 +#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 +#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 +#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 +#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 +#define IMX7D_EIM_ROOT_PRE_DIV 366 +#define IMX7D_NAND_ROOT_PRE_DIV 367 +#define IMX7D_QSPI_ROOT_PRE_DIV 368 +#define IMX7D_USDHC1_ROOT_PRE_DIV 369 +#define IMX7D_USDHC2_ROOT_PRE_DIV 370 +#define IMX7D_USDHC3_ROOT_PRE_DIV 371 +#define IMX7D_CAN1_ROOT_PRE_DIV 372 +#define IMX7D_CAN2_ROOT_PRE_DIV 373 +#define IMX7D_I2C1_ROOT_PRE_DIV 374 +#define IMX7D_I2C2_ROOT_PRE_DIV 375 +#define IMX7D_I2C3_ROOT_PRE_DIV 376 +#define IMX7D_I2C4_ROOT_PRE_DIV 377 +#define IMX7D_UART1_ROOT_PRE_DIV 378 +#define IMX7D_UART2_ROOT_PRE_DIV 379 +#define IMX7D_UART3_ROOT_PRE_DIV 380 +#define IMX7D_UART4_ROOT_PRE_DIV 381 +#define IMX7D_UART5_ROOT_PRE_DIV 382 +#define IMX7D_UART6_ROOT_PRE_DIV 383 +#define IMX7D_UART7_ROOT_PRE_DIV 384 +#define IMX7D_ECSPI1_ROOT_PRE_DIV 385 +#define IMX7D_ECSPI2_ROOT_PRE_DIV 386 +#define IMX7D_ECSPI3_ROOT_PRE_DIV 387 +#define IMX7D_ECSPI4_ROOT_PRE_DIV 388 +#define IMX7D_PWM1_ROOT_PRE_DIV 389 +#define IMX7D_PWM2_ROOT_PRE_DIV 390 +#define IMX7D_PWM3_ROOT_PRE_DIV 391 +#define IMX7D_PWM4_ROOT_PRE_DIV 392 +#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 +#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 +#define IMX7D_SIM1_ROOT_PRE_DIV 395 +#define IMX7D_SIM2_ROOT_PRE_DIV 396 +#define IMX7D_GPT1_ROOT_PRE_DIV 397 +#define IMX7D_GPT2_ROOT_PRE_DIV 398 +#define IMX7D_GPT3_ROOT_PRE_DIV 399 +#define IMX7D_GPT4_ROOT_PRE_DIV 400 +#define IMX7D_TRACE_ROOT_PRE_DIV 401 +#define IMX7D_WDOG_ROOT_PRE_DIV 402 +#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 +#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 +#define IMX7D_WRCLK_ROOT_PRE_DIV 405 +#define IMX7D_CLKO1_ROOT_PRE_DIV 406 +#define IMX7D_CLKO2_ROOT_PRE_DIV 407 +#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 +#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 +#define IMX7D_LVDS1_IN_CLK 410 +#define IMX7D_LVDS1_OUT_SEL 411 +#define IMX7D_LVDS1_OUT_CLK 412 +#define IMX7D_CLK_DUMMY 413 +#define IMX7D_GPT_3M_CLK 414 +#define IMX7D_OCRAM_CLK 415 +#define IMX7D_OCRAM_S_CLK 416 +#define IMX7D_WDOG2_ROOT_CLK 417 +#define IMX7D_WDOG3_ROOT_CLK 418 +#define IMX7D_WDOG4_ROOT_CLK 419 +#define IMX7D_SDMA_CORE_CLK 420 +#define IMX7D_USB1_MAIN_480M_CLK 421 +#define IMX7D_USB_CTRL_CLK 422 +#define IMX7D_USB_PHY1_CLK 423 +#define IMX7D_USB_PHY2_CLK 424 +#define IMX7D_IPG_ROOT_CLK 425 +#define IMX7D_SAI1_IPG_CLK 426 +#define IMX7D_SAI2_IPG_CLK 427 +#define IMX7D_SAI3_IPG_CLK 428 +#define IMX7D_PLL_AUDIO_TEST_DIV 429 +#define IMX7D_PLL_AUDIO_POST_DIV 430 +#define IMX7D_PLL_VIDEO_TEST_DIV 431 +#define IMX7D_PLL_VIDEO_POST_DIV 432 +#define IMX7D_MU_ROOT_CLK 433 +#define IMX7D_SEMA4_HS_ROOT_CLK 434 +#define IMX7D_PLL_DRAM_TEST_DIV 435 +#define IMX7D_ADC_ROOT_CLK 436 +#define IMX7D_CLK_ARM 437 +#define IMX7D_CKIL 438 +#define IMX7D_OCOTP_CLK 439 +#define IMX7D_NAND_RAWNAND_CLK 440 +#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 +#define IMX7D_SNVS_CLK 442 +#define IMX7D_CAAM_CLK 443 +#define IMX7D_KPP_ROOT_CLK 444 +#define IMX7D_CLK_END 445 +#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/imx7ulp-clock.h b/roms/u-boot/include/dt-bindings/clock/imx7ulp-clock.h new file mode 100644 index 000000000..0a955df4a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/imx7ulp-clock.h @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H +#define __DT_BINDINGS_CLOCK_IMX7ULP_H + +#define IMX7ULP_CLK_DUMMY 0 +#define IMX7ULP_CLK_CKIL 1 +#define IMX7ULP_CLK_OSC 2 +#define IMX7ULP_CLK_FIRC 3 + +/* SCG1 */ +#define IMX7ULP_CLK_SPLL_PRE_SEL 4 +#define IMX7ULP_CLK_SPLL_PRE_DIV 5 +#define IMX7ULP_CLK_SPLL 6 +#define IMX7ULP_CLK_SPLL_POST_DIV1 7 +#define IMX7ULP_CLK_SPLL_POST_DIV2 8 +#define IMX7ULP_CLK_SPLL_PFD0 9 +#define IMX7ULP_CLK_SPLL_PFD1 10 +#define IMX7ULP_CLK_SPLL_PFD2 11 +#define IMX7ULP_CLK_SPLL_PFD3 12 +#define IMX7ULP_CLK_SPLL_PFD_SEL 13 +#define IMX7ULP_CLK_SPLL_SEL 14 +#define IMX7ULP_CLK_APLL_PRE_SEL 15 +#define IMX7ULP_CLK_APLL_PRE_DIV 16 +#define IMX7ULP_CLK_APLL 17 +#define IMX7ULP_CLK_APLL_POST_DIV1 18 +#define IMX7ULP_CLK_APLL_POST_DIV2 19 +#define IMX7ULP_CLK_APLL_PFD0 20 +#define IMX7ULP_CLK_APLL_PFD1 21 +#define IMX7ULP_CLK_APLL_PFD2 22 +#define IMX7ULP_CLK_APLL_PFD3 23 +#define IMX7ULP_CLK_APLL_PFD_SEL 24 +#define IMX7ULP_CLK_APLL_SEL 25 +#define IMX7ULP_CLK_UPLL 26 +#define IMX7ULP_CLK_SYS_SEL 27 +#define IMX7ULP_CLK_CORE_DIV 28 +#define IMX7ULP_CLK_BUS_DIV 29 +#define IMX7ULP_CLK_PLAT_DIV 30 +#define IMX7ULP_CLK_DDR_SEL 31 +#define IMX7ULP_CLK_DDR_DIV 32 +#define IMX7ULP_CLK_NIC_SEL 33 +#define IMX7ULP_CLK_NIC0_DIV 34 +#define IMX7ULP_CLK_GPU_DIV 35 +#define IMX7ULP_CLK_NIC1_DIV 36 +#define IMX7ULP_CLK_NIC1_BUS_DIV 37 +#define IMX7ULP_CLK_NIC1_EXT_DIV 38 + +/* PCG2 */ +#define IMX7ULP_CLK_DMA1 39 +#define IMX7ULP_CLK_RGPIO2P1 40 +#define IMX7ULP_CLK_FLEXBUS 41 +#define IMX7ULP_CLK_SEMA42_1 42 +#define IMX7ULP_CLK_DMA_MUX1 43 +#define IMX7ULP_CLK_SNVS 44 +#define IMX7ULP_CLK_CAAM 45 +#define IMX7ULP_CLK_LPTPM4 46 +#define IMX7ULP_CLK_LPTPM5 47 +#define IMX7ULP_CLK_LPIT1 48 +#define IMX7ULP_CLK_LPSPI2 49 +#define IMX7ULP_CLK_LPSPI3 50 +#define IMX7ULP_CLK_LPI2C4 51 +#define IMX7ULP_CLK_LPI2C5 52 +#define IMX7ULP_CLK_LPUART4 53 +#define IMX7ULP_CLK_LPUART5 54 +#define IMX7ULP_CLK_FLEXIO1 55 +#define IMX7ULP_CLK_USB0 56 +#define IMX7ULP_CLK_USB1 57 +#define IMX7ULP_CLK_USB_PHY 58 +#define IMX7ULP_CLK_USB_PL301 59 +#define IMX7ULP_CLK_USDHC0 60 +#define IMX7ULP_CLK_USDHC1 61 +#define IMX7ULP_CLK_WDG1 62 +#define IMX7ULP_CLK_WDG2 63 + +/* PCG3 */ +#define IMX7ULP_CLK_LPTPM6 64 +#define IMX7ULP_CLK_LPTPM7 65 +#define IMX7ULP_CLK_LPI2C6 66 +#define IMX7ULP_CLK_LPI2C7 67 +#define IMX7ULP_CLK_LPUART6 68 +#define IMX7ULP_CLK_LPUART7 69 +#define IMX7ULP_CLK_VIU 70 +#define IMX7ULP_CLK_DSI 71 +#define IMX7ULP_CLK_LCDIF 72 +#define IMX7ULP_CLK_MMDC 73 +#define IMX7ULP_CLK_PCTLC 74 +#define IMX7ULP_CLK_PCTLD 75 +#define IMX7ULP_CLK_PCTLE 76 +#define IMX7ULP_CLK_PCTLF 77 +#define IMX7ULP_CLK_GPU3D 78 +#define IMX7ULP_CLK_GPU2D 79 + +#define IMX7ULP_CLK_MIPI_PLL 80 +#define IMX7ULP_CLK_SIRC 81 + +#define IMX7ULP_CLK_SCG1_CLKOUT 82 + +#define IMX7ULP_CLK_END 83 + +/*cm4 clocks*/ +#define IMX7ULP_CM4_CLK_DUMMY 0 +#define IMX7ULP_CM4_CLK_CKIL 1 +#define IMX7ULP_CM4_CLK_OSC 2 +#define IMX7ULP_CM4_CLK_FIRC 3 +#define IMX7ULP_CM4_CLK_SIRC 4 + +/* SCG0 */ +#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL 5 +#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV 6 +#define IMX7ULP_CM4_CLK_SPLL 7 +#define IMX7ULP_CM4_CLK_SPLL_VCO 8 +#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1 9 +#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2 10 +#define IMX7ULP_CM4_CLK_SPLL_PFD0 11 +#define IMX7ULP_CM4_CLK_SPLL_PFD1 12 +#define IMX7ULP_CM4_CLK_SPLL_PFD2 13 +#define IMX7ULP_CM4_CLK_SPLL_PFD3 14 +#define IMX7ULP_CM4_CLK_SPLL_PFD_SEL 15 +#define IMX7ULP_CM4_CLK_SPLL_PFD 16 +#define IMX7ULP_CM4_CLK_SPLL_SEL 17 +#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL 18 +#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV 19 +#define IMX7ULP_CM4_CLK_APLL 20 +#define IMX7ULP_CM4_CLK_APLL_VCO 21 +#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1 22 +#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2 23 +#define IMX7ULP_CM4_CLK_APLL_PFD0 24 +#define IMX7ULP_CM4_CLK_APLL_PFD1 25 +#define IMX7ULP_CM4_CLK_APLL_PFD2 26 +#define IMX7ULP_CM4_CLK_APLL_PFD3 27 +#define IMX7ULP_CM4_CLK_APLL_PFD_SEL 28 +#define IMX7ULP_CM4_CLK_APLL_PFD 29 +#define IMX7ULP_CM4_CLK_APLL_SEL 30 +#define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV 31 +#define IMX7ULP_CM4_CLK_SYS_SEL 32 +#define IMX7ULP_CM4_CLK_CORE_DIV 33 +#define IMX7ULP_CM4_CLK_BUS_DIV 34 +#define IMX7ULP_CM4_CLK_PLAT_DIV 35 +#define IMX7ULP_CM4_CLK_SLOW_DIV 36 + +#define IMX7ULP_CM4_CLK_SAI0_SEL 37 +#define IMX7ULP_CM4_CLK_SAI0_DIV 38 +#define IMX7ULP_CM4_CLK_SAI0_ROOT 39 +#define IMX7ULP_CM4_CLK_SAI0_IPG 40 +#define IMX7ULP_CM4_CLK_SAI1_SEL 41 +#define IMX7ULP_CM4_CLK_SAI1_DIV 42 +#define IMX7ULP_CM4_CLK_SAI1_ROOT 43 +#define IMX7ULP_CM4_CLK_SAI1_IPG 44 + +#define IMX7ULP_CLK_SCG0_CLKOUT 45 + +#define IMX7ULP_CM4_CLK_END 46 + +#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/imx8mm-clock.h b/roms/u-boot/include/dt-bindings/clock/imx8mm-clock.h new file mode 100644 index 000000000..e63a5530a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/imx8mm-clock.h @@ -0,0 +1,279 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017-2018 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H +#define __DT_BINDINGS_CLOCK_IMX8MM_H + +#define IMX8MM_CLK_DUMMY 0 +#define IMX8MM_CLK_32K 1 +#define IMX8MM_CLK_24M 2 +#define IMX8MM_OSC_HDMI_CLK 3 +#define IMX8MM_CLK_EXT1 4 +#define IMX8MM_CLK_EXT2 5 +#define IMX8MM_CLK_EXT3 6 +#define IMX8MM_CLK_EXT4 7 +#define IMX8MM_AUDIO_PLL1_REF_SEL 8 +#define IMX8MM_AUDIO_PLL2_REF_SEL 9 +#define IMX8MM_VIDEO_PLL1_REF_SEL 10 +#define IMX8MM_DRAM_PLL_REF_SEL 11 +#define IMX8MM_GPU_PLL_REF_SEL 12 +#define IMX8MM_VPU_PLL_REF_SEL 13 +#define IMX8MM_ARM_PLL_REF_SEL 14 +#define IMX8MM_SYS_PLL1_REF_SEL 15 +#define IMX8MM_SYS_PLL2_REF_SEL 16 +#define IMX8MM_SYS_PLL3_REF_SEL 17 +#define IMX8MM_AUDIO_PLL1 18 +#define IMX8MM_AUDIO_PLL2 19 +#define IMX8MM_VIDEO_PLL1 20 +#define IMX8MM_DRAM_PLL 21 +#define IMX8MM_GPU_PLL 22 +#define IMX8MM_VPU_PLL 23 +#define IMX8MM_ARM_PLL 24 +#define IMX8MM_SYS_PLL1 25 +#define IMX8MM_SYS_PLL2 26 +#define IMX8MM_SYS_PLL3 27 +#define IMX8MM_AUDIO_PLL1_BYPASS 28 +#define IMX8MM_AUDIO_PLL2_BYPASS 29 +#define IMX8MM_VIDEO_PLL1_BYPASS 30 +#define IMX8MM_DRAM_PLL_BYPASS 31 +#define IMX8MM_GPU_PLL_BYPASS 32 +#define IMX8MM_VPU_PLL_BYPASS 33 +#define IMX8MM_ARM_PLL_BYPASS 34 +#define IMX8MM_SYS_PLL1_BYPASS 35 +#define IMX8MM_SYS_PLL2_BYPASS 36 +#define IMX8MM_SYS_PLL3_BYPASS 37 +#define IMX8MM_AUDIO_PLL1_OUT 38 +#define IMX8MM_AUDIO_PLL2_OUT 39 +#define IMX8MM_VIDEO_PLL1_OUT 40 +#define IMX8MM_DRAM_PLL_OUT 41 +#define IMX8MM_GPU_PLL_OUT 42 +#define IMX8MM_VPU_PLL_OUT 43 +#define IMX8MM_ARM_PLL_OUT 44 +#define IMX8MM_SYS_PLL1_OUT 45 +#define IMX8MM_SYS_PLL2_OUT 46 +#define IMX8MM_SYS_PLL3_OUT 47 +#define IMX8MM_SYS_PLL1_40M 48 +#define IMX8MM_SYS_PLL1_80M 49 +#define IMX8MM_SYS_PLL1_100M 50 +#define IMX8MM_SYS_PLL1_133M 51 +#define IMX8MM_SYS_PLL1_160M 52 +#define IMX8MM_SYS_PLL1_200M 53 +#define IMX8MM_SYS_PLL1_266M 54 +#define IMX8MM_SYS_PLL1_400M 55 +#define IMX8MM_SYS_PLL1_800M 56 +#define IMX8MM_SYS_PLL2_50M 57 +#define IMX8MM_SYS_PLL2_100M 58 +#define IMX8MM_SYS_PLL2_125M 59 +#define IMX8MM_SYS_PLL2_166M 60 +#define IMX8MM_SYS_PLL2_200M 61 +#define IMX8MM_SYS_PLL2_250M 62 +#define IMX8MM_SYS_PLL2_333M 63 +#define IMX8MM_SYS_PLL2_500M 64 +#define IMX8MM_SYS_PLL2_1000M 65 + +/* core */ +#define IMX8MM_CLK_A53_SRC 66 +#define IMX8MM_CLK_M4_SRC 67 +#define IMX8MM_CLK_VPU_SRC 68 +#define IMX8MM_CLK_GPU3D_SRC 69 +#define IMX8MM_CLK_GPU2D_SRC 70 +#define IMX8MM_CLK_A53_CG 71 +#define IMX8MM_CLK_M4_CG 72 +#define IMX8MM_CLK_VPU_CG 73 +#define IMX8MM_CLK_GPU3D_CG 74 +#define IMX8MM_CLK_GPU2D_CG 75 +#define IMX8MM_CLK_A53_DIV 76 +#define IMX8MM_CLK_M4_DIV 77 +#define IMX8MM_CLK_VPU_DIV 78 +#define IMX8MM_CLK_GPU3D_DIV 79 +#define IMX8MM_CLK_GPU2D_DIV 80 + +/* bus */ +#define IMX8MM_CLK_MAIN_AXI 81 +#define IMX8MM_CLK_ENET_AXI 82 +#define IMX8MM_CLK_NAND_USDHC_BUS 83 +#define IMX8MM_CLK_VPU_BUS 84 +#define IMX8MM_CLK_DISP_AXI 85 +#define IMX8MM_CLK_DISP_APB 86 +#define IMX8MM_CLK_DISP_RTRM 87 +#define IMX8MM_CLK_USB_BUS 88 +#define IMX8MM_CLK_GPU_AXI 89 +#define IMX8MM_CLK_GPU_AHB 90 +#define IMX8MM_CLK_NOC 91 +#define IMX8MM_CLK_NOC_APB 92 + +#define IMX8MM_CLK_AHB 93 +#define IMX8MM_CLK_AUDIO_AHB 94 +#define IMX8MM_CLK_IPG_ROOT 95 +#define IMX8MM_CLK_IPG_AUDIO_ROOT 96 + +#define IMX8MM_CLK_DRAM_ALT 97 +#define IMX8MM_CLK_DRAM_APB 98 +#define IMX8MM_CLK_VPU_G1 99 +#define IMX8MM_CLK_VPU_G2 100 +#define IMX8MM_CLK_DISP_DTRC 101 +#define IMX8MM_CLK_DISP_DC8000 102 +#define IMX8MM_CLK_PCIE1_CTRL 103 +#define IMX8MM_CLK_PCIE1_PHY 104 +#define IMX8MM_CLK_PCIE1_AUX 105 +#define IMX8MM_CLK_DC_PIXEL 106 +#define IMX8MM_CLK_LCDIF_PIXEL 107 +#define IMX8MM_CLK_SAI1 108 +#define IMX8MM_CLK_SAI2 109 +#define IMX8MM_CLK_SAI3 110 +#define IMX8MM_CLK_SAI4 111 +#define IMX8MM_CLK_SAI5 112 +#define IMX8MM_CLK_SAI6 113 +#define IMX8MM_CLK_SPDIF1 114 +#define IMX8MM_CLK_SPDIF2 115 +#define IMX8MM_CLK_ENET_REF 116 +#define IMX8MM_CLK_ENET_TIMER 117 +#define IMX8MM_CLK_ENET_PHY_REF 118 +#define IMX8MM_CLK_NAND 119 +#define IMX8MM_CLK_QSPI 120 +#define IMX8MM_CLK_USDHC1 121 +#define IMX8MM_CLK_USDHC2 122 +#define IMX8MM_CLK_I2C1 123 +#define IMX8MM_CLK_I2C2 124 +#define IMX8MM_CLK_I2C3 125 +#define IMX8MM_CLK_I2C4 126 +#define IMX8MM_CLK_UART1 127 +#define IMX8MM_CLK_UART2 128 +#define IMX8MM_CLK_UART3 129 +#define IMX8MM_CLK_UART4 130 +#define IMX8MM_CLK_USB_CORE_REF 131 +#define IMX8MM_CLK_USB_PHY_REF 132 +#define IMX8MM_CLK_ECSPI1 133 +#define IMX8MM_CLK_ECSPI2 134 +#define IMX8MM_CLK_PWM1 135 +#define IMX8MM_CLK_PWM2 136 +#define IMX8MM_CLK_PWM3 137 +#define IMX8MM_CLK_PWM4 138 +#define IMX8MM_CLK_GPT1 139 +#define IMX8MM_CLK_WDOG 140 +#define IMX8MM_CLK_WRCLK 141 +#define IMX8MM_CLK_DSI_CORE 142 +#define IMX8MM_CLK_DSI_PHY_REF 143 +#define IMX8MM_CLK_DSI_DBI 144 +#define IMX8MM_CLK_USDHC3 145 +#define IMX8MM_CLK_CSI1_CORE 146 +#define IMX8MM_CLK_CSI1_PHY_REF 147 +#define IMX8MM_CLK_CSI1_ESC 148 +#define IMX8MM_CLK_CSI2_CORE 149 +#define IMX8MM_CLK_CSI2_PHY_REF 150 +#define IMX8MM_CLK_CSI2_ESC 151 +#define IMX8MM_CLK_PCIE2_CTRL 152 +#define IMX8MM_CLK_PCIE2_PHY 153 +#define IMX8MM_CLK_PCIE2_AUX 154 +#define IMX8MM_CLK_ECSPI3 155 +#define IMX8MM_CLK_PDM 156 +#define IMX8MM_CLK_VPU_H1 157 +#define IMX8MM_CLK_CLKO1 158 + +#define IMX8MM_CLK_ECSPI1_ROOT 159 +#define IMX8MM_CLK_ECSPI2_ROOT 160 +#define IMX8MM_CLK_ECSPI3_ROOT 161 +#define IMX8MM_CLK_ENET1_ROOT 162 +#define IMX8MM_CLK_GPT1_ROOT 163 +#define IMX8MM_CLK_I2C1_ROOT 164 +#define IMX8MM_CLK_I2C2_ROOT 165 +#define IMX8MM_CLK_I2C3_ROOT 166 +#define IMX8MM_CLK_I2C4_ROOT 167 +#define IMX8MM_CLK_OCOTP_ROOT 168 +#define IMX8MM_CLK_PCIE1_ROOT 169 +#define IMX8MM_CLK_PWM1_ROOT 170 +#define IMX8MM_CLK_PWM2_ROOT 171 +#define IMX8MM_CLK_PWM3_ROOT 172 +#define IMX8MM_CLK_PWM4_ROOT 173 +#define IMX8MM_CLK_QSPI_ROOT 174 +#define IMX8MM_CLK_NAND_ROOT 175 +#define IMX8MM_CLK_SAI1_ROOT 176 +#define IMX8MM_CLK_SAI1_IPG 177 +#define IMX8MM_CLK_SAI2_ROOT 178 +#define IMX8MM_CLK_SAI2_IPG 179 +#define IMX8MM_CLK_SAI3_ROOT 180 +#define IMX8MM_CLK_SAI3_IPG 181 +#define IMX8MM_CLK_SAI4_ROOT 182 +#define IMX8MM_CLK_SAI4_IPG 183 +#define IMX8MM_CLK_SAI5_ROOT 184 +#define IMX8MM_CLK_SAI5_IPG 185 +#define IMX8MM_CLK_SAI6_ROOT 186 +#define IMX8MM_CLK_SAI6_IPG 187 +#define IMX8MM_CLK_UART1_ROOT 188 +#define IMX8MM_CLK_UART2_ROOT 189 +#define IMX8MM_CLK_UART3_ROOT 190 +#define IMX8MM_CLK_UART4_ROOT 191 +#define IMX8MM_CLK_USB1_CTRL_ROOT 192 +#define IMX8MM_CLK_GPU3D_ROOT 193 +#define IMX8MM_CLK_USDHC1_ROOT 194 +#define IMX8MM_CLK_USDHC2_ROOT 195 +#define IMX8MM_CLK_WDOG1_ROOT 196 +#define IMX8MM_CLK_WDOG2_ROOT 197 +#define IMX8MM_CLK_WDOG3_ROOT 198 +#define IMX8MM_CLK_VPU_G1_ROOT 199 +#define IMX8MM_CLK_GPU_BUS_ROOT 200 +#define IMX8MM_CLK_VPU_H1_ROOT 201 +#define IMX8MM_CLK_VPU_G2_ROOT 202 +#define IMX8MM_CLK_PDM_ROOT 203 +#define IMX8MM_CLK_DISP_ROOT 204 +#define IMX8MM_CLK_DISP_AXI_ROOT 205 +#define IMX8MM_CLK_DISP_APB_ROOT 206 +#define IMX8MM_CLK_DISP_RTRM_ROOT 207 +#define IMX8MM_CLK_USDHC3_ROOT 208 +#define IMX8MM_CLK_TMU_ROOT 209 +#define IMX8MM_CLK_VPU_DEC_ROOT 210 +#define IMX8MM_CLK_SDMA1_ROOT 211 +#define IMX8MM_CLK_SDMA2_ROOT 212 +#define IMX8MM_CLK_SDMA3_ROOT 213 +#define IMX8MM_CLK_GPT_3M 214 +#define IMX8MM_CLK_ARM 215 +#define IMX8MM_CLK_PDM_IPG 216 +#define IMX8MM_CLK_GPU2D_ROOT 217 +#define IMX8MM_CLK_MU_ROOT 218 +#define IMX8MM_CLK_CSI1_ROOT 219 + +#define IMX8MM_CLK_DRAM_CORE 220 +#define IMX8MM_CLK_DRAM_ALT_ROOT 221 + +#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222 + +#define IMX8MM_CLK_GPIO1_ROOT 223 +#define IMX8MM_CLK_GPIO2_ROOT 224 +#define IMX8MM_CLK_GPIO3_ROOT 225 +#define IMX8MM_CLK_GPIO4_ROOT 226 +#define IMX8MM_CLK_GPIO5_ROOT 227 + +#define IMX8MM_CLK_SNVS_ROOT 228 +#define IMX8MM_CLK_GIC 229 + +#define IMX8MM_SYS_PLL1_40M_CG 230 +#define IMX8MM_SYS_PLL1_80M_CG 231 +#define IMX8MM_SYS_PLL1_100M_CG 232 +#define IMX8MM_SYS_PLL1_133M_CG 233 +#define IMX8MM_SYS_PLL1_160M_CG 234 +#define IMX8MM_SYS_PLL1_200M_CG 235 +#define IMX8MM_SYS_PLL1_266M_CG 236 +#define IMX8MM_SYS_PLL1_400M_CG 237 +#define IMX8MM_SYS_PLL2_50M_CG 238 +#define IMX8MM_SYS_PLL2_100M_CG 239 +#define IMX8MM_SYS_PLL2_125M_CG 240 +#define IMX8MM_SYS_PLL2_166M_CG 241 +#define IMX8MM_SYS_PLL2_200M_CG 242 +#define IMX8MM_SYS_PLL2_250M_CG 243 +#define IMX8MM_SYS_PLL2_333M_CG 244 +#define IMX8MM_SYS_PLL2_500M_CG 245 + +#define IMX8MM_CLK_M4_CORE 246 +#define IMX8MM_CLK_VPU_CORE 247 +#define IMX8MM_CLK_GPU3D_CORE 248 +#define IMX8MM_CLK_GPU2D_CORE 249 + +#define IMX8MM_CLK_CLKO2 250 + +#define IMX8MM_CLK_A53_CORE 251 + +#define IMX8MM_CLK_END 252 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/imx8mn-clock.h b/roms/u-boot/include/dt-bindings/clock/imx8mn-clock.h new file mode 100644 index 000000000..621ea0e87 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/imx8mn-clock.h @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2018-2019 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H +#define __DT_BINDINGS_CLOCK_IMX8MN_H + +#define IMX8MN_CLK_DUMMY 0 +#define IMX8MN_CLK_32K 1 +#define IMX8MN_CLK_24M 2 +#define IMX8MN_OSC_HDMI_CLK 3 +#define IMX8MN_CLK_EXT1 4 +#define IMX8MN_CLK_EXT2 5 +#define IMX8MN_CLK_EXT3 6 +#define IMX8MN_CLK_EXT4 7 +#define IMX8MN_AUDIO_PLL1_REF_SEL 8 +#define IMX8MN_AUDIO_PLL2_REF_SEL 9 +#define IMX8MN_VIDEO_PLL1_REF_SEL 10 +#define IMX8MN_DRAM_PLL_REF_SEL 11 +#define IMX8MN_GPU_PLL_REF_SEL 12 +#define IMX8MN_VPU_PLL_REF_SEL 13 +#define IMX8MN_ARM_PLL_REF_SEL 14 +#define IMX8MN_SYS_PLL1_REF_SEL 15 +#define IMX8MN_SYS_PLL2_REF_SEL 16 +#define IMX8MN_SYS_PLL3_REF_SEL 17 +#define IMX8MN_AUDIO_PLL1 18 +#define IMX8MN_AUDIO_PLL2 19 +#define IMX8MN_VIDEO_PLL1 20 +#define IMX8MN_DRAM_PLL 21 +#define IMX8MN_GPU_PLL 22 +#define IMX8MN_VPU_PLL 23 +#define IMX8MN_ARM_PLL 24 +#define IMX8MN_SYS_PLL1 25 +#define IMX8MN_SYS_PLL2 26 +#define IMX8MN_SYS_PLL3 27 +#define IMX8MN_AUDIO_PLL1_BYPASS 28 +#define IMX8MN_AUDIO_PLL2_BYPASS 29 +#define IMX8MN_VIDEO_PLL1_BYPASS 30 +#define IMX8MN_DRAM_PLL_BYPASS 31 +#define IMX8MN_GPU_PLL_BYPASS 32 +#define IMX8MN_VPU_PLL_BYPASS 33 +#define IMX8MN_ARM_PLL_BYPASS 34 +#define IMX8MN_SYS_PLL1_BYPASS 35 +#define IMX8MN_SYS_PLL2_BYPASS 36 +#define IMX8MN_SYS_PLL3_BYPASS 37 +#define IMX8MN_AUDIO_PLL1_OUT 38 +#define IMX8MN_AUDIO_PLL2_OUT 39 +#define IMX8MN_VIDEO_PLL1_OUT 40 +#define IMX8MN_DRAM_PLL_OUT 41 +#define IMX8MN_GPU_PLL_OUT 42 +#define IMX8MN_VPU_PLL_OUT 43 +#define IMX8MN_ARM_PLL_OUT 44 +#define IMX8MN_SYS_PLL1_OUT 45 +#define IMX8MN_SYS_PLL2_OUT 46 +#define IMX8MN_SYS_PLL3_OUT 47 +#define IMX8MN_SYS_PLL1_40M 48 +#define IMX8MN_SYS_PLL1_80M 49 +#define IMX8MN_SYS_PLL1_100M 50 +#define IMX8MN_SYS_PLL1_133M 51 +#define IMX8MN_SYS_PLL1_160M 52 +#define IMX8MN_SYS_PLL1_200M 53 +#define IMX8MN_SYS_PLL1_266M 54 +#define IMX8MN_SYS_PLL1_400M 55 +#define IMX8MN_SYS_PLL1_800M 56 +#define IMX8MN_SYS_PLL2_50M 57 +#define IMX8MN_SYS_PLL2_100M 58 +#define IMX8MN_SYS_PLL2_125M 59 +#define IMX8MN_SYS_PLL2_166M 60 +#define IMX8MN_SYS_PLL2_200M 61 +#define IMX8MN_SYS_PLL2_250M 62 +#define IMX8MN_SYS_PLL2_333M 63 +#define IMX8MN_SYS_PLL2_500M 64 +#define IMX8MN_SYS_PLL2_1000M 65 + +/* CORE CLOCK ROOT */ +#define IMX8MN_CLK_A53_SRC 66 +#define IMX8MN_CLK_GPU_CORE_SRC 67 +#define IMX8MN_CLK_GPU_SHADER_SRC 68 +#define IMX8MN_CLK_A53_CG 69 +#define IMX8MN_CLK_GPU_CORE_CG 70 +#define IMX8MN_CLK_GPU_SHADER_CG 71 +#define IMX8MN_CLK_A53_DIV 72 +#define IMX8MN_CLK_GPU_CORE_DIV 73 +#define IMX8MN_CLK_GPU_SHADER_DIV 74 + +/* BUS CLOCK ROOT */ +#define IMX8MN_CLK_MAIN_AXI 75 +#define IMX8MN_CLK_ENET_AXI 76 +#define IMX8MN_CLK_NAND_USDHC_BUS 77 +#define IMX8MN_CLK_DISP_AXI 78 +#define IMX8MN_CLK_DISP_APB 79 +#define IMX8MN_CLK_USB_BUS 80 +#define IMX8MN_CLK_GPU_AXI 81 +#define IMX8MN_CLK_GPU_AHB 82 +#define IMX8MN_CLK_NOC 83 +#define IMX8MN_CLK_AHB 84 +#define IMX8MN_CLK_AUDIO_AHB 85 + +/* IPG CLOCK ROOT */ +#define IMX8MN_CLK_IPG_ROOT 86 +#define IMX8MN_CLK_IPG_AUDIO_ROOT 87 + +/* IP */ +#define IMX8MN_CLK_DRAM_CORE 88 +#define IMX8MN_CLK_DRAM_ALT 89 +#define IMX8MN_CLK_DRAM_APB 90 +#define IMX8MN_CLK_DRAM_ALT_ROOT 91 +#define IMX8MN_CLK_DISP_PIXEL 92 +#define IMX8MN_CLK_SAI2 93 +#define IMX8MN_CLK_SAI3 94 +#define IMX8MN_CLK_SAI5 95 +#define IMX8MN_CLK_SAI6 96 +#define IMX8MN_CLK_SPDIF1 97 +#define IMX8MN_CLK_ENET_REF 98 +#define IMX8MN_CLK_ENET_TIMER 99 +#define IMX8MN_CLK_ENET_PHY_REF 100 +#define IMX8MN_CLK_NAND 101 +#define IMX8MN_CLK_QSPI 102 +#define IMX8MN_CLK_USDHC1 103 +#define IMX8MN_CLK_USDHC2 104 +#define IMX8MN_CLK_I2C1 105 +#define IMX8MN_CLK_I2C2 106 +#define IMX8MN_CLK_I2C3 107 +#define IMX8MN_CLK_I2C4 108 +#define IMX8MN_CLK_UART1 109 +#define IMX8MN_CLK_UART2 110 +#define IMX8MN_CLK_UART3 111 +#define IMX8MN_CLK_UART4 112 +#define IMX8MN_CLK_USB_CORE_REF 113 +#define IMX8MN_CLK_USB_PHY_REF 114 +#define IMX8MN_CLK_ECSPI1 115 +#define IMX8MN_CLK_ECSPI2 116 +#define IMX8MN_CLK_PWM1 117 +#define IMX8MN_CLK_PWM2 118 +#define IMX8MN_CLK_PWM3 119 +#define IMX8MN_CLK_PWM4 120 +#define IMX8MN_CLK_WDOG 121 +#define IMX8MN_CLK_WRCLK 122 +#define IMX8MN_CLK_CLKO1 123 +#define IMX8MN_CLK_CLKO2 124 +#define IMX8MN_CLK_DSI_CORE 125 +#define IMX8MN_CLK_DSI_PHY_REF 126 +#define IMX8MN_CLK_DSI_DBI 127 +#define IMX8MN_CLK_USDHC3 128 +#define IMX8MN_CLK_CAMERA_PIXEL 129 +#define IMX8MN_CLK_CSI1_PHY_REF 130 +#define IMX8MN_CLK_CSI2_PHY_REF 131 +#define IMX8MN_CLK_CSI2_ESC 132 +#define IMX8MN_CLK_ECSPI3 133 +#define IMX8MN_CLK_PDM 134 +#define IMX8MN_CLK_SAI7 135 + +#define IMX8MN_CLK_ECSPI1_ROOT 136 +#define IMX8MN_CLK_ECSPI2_ROOT 137 +#define IMX8MN_CLK_ECSPI3_ROOT 138 +#define IMX8MN_CLK_ENET1_ROOT 139 +#define IMX8MN_CLK_GPIO1_ROOT 140 +#define IMX8MN_CLK_GPIO2_ROOT 141 +#define IMX8MN_CLK_GPIO3_ROOT 142 +#define IMX8MN_CLK_GPIO4_ROOT 143 +#define IMX8MN_CLK_GPIO5_ROOT 144 +#define IMX8MN_CLK_I2C1_ROOT 145 +#define IMX8MN_CLK_I2C2_ROOT 146 +#define IMX8MN_CLK_I2C3_ROOT 147 +#define IMX8MN_CLK_I2C4_ROOT 148 +#define IMX8MN_CLK_MU_ROOT 149 +#define IMX8MN_CLK_OCOTP_ROOT 150 +#define IMX8MN_CLK_PWM1_ROOT 151 +#define IMX8MN_CLK_PWM2_ROOT 152 +#define IMX8MN_CLK_PWM3_ROOT 153 +#define IMX8MN_CLK_PWM4_ROOT 154 +#define IMX8MN_CLK_QSPI_ROOT 155 +#define IMX8MN_CLK_NAND_ROOT 156 +#define IMX8MN_CLK_SAI2_ROOT 157 +#define IMX8MN_CLK_SAI2_IPG 158 +#define IMX8MN_CLK_SAI3_ROOT 159 +#define IMX8MN_CLK_SAI3_IPG 160 +#define IMX8MN_CLK_SAI5_ROOT 161 +#define IMX8MN_CLK_SAI5_IPG 162 +#define IMX8MN_CLK_SAI6_ROOT 163 +#define IMX8MN_CLK_SAI6_IPG 164 +#define IMX8MN_CLK_SAI7_ROOT 165 +#define IMX8MN_CLK_SAI7_IPG 166 +#define IMX8MN_CLK_SDMA1_ROOT 167 +#define IMX8MN_CLK_SDMA2_ROOT 168 +#define IMX8MN_CLK_UART1_ROOT 169 +#define IMX8MN_CLK_UART2_ROOT 170 +#define IMX8MN_CLK_UART3_ROOT 171 +#define IMX8MN_CLK_UART4_ROOT 172 +#define IMX8MN_CLK_USB1_CTRL_ROOT 173 +#define IMX8MN_CLK_USDHC1_ROOT 174 +#define IMX8MN_CLK_USDHC2_ROOT 175 +#define IMX8MN_CLK_WDOG1_ROOT 176 +#define IMX8MN_CLK_WDOG2_ROOT 177 +#define IMX8MN_CLK_WDOG3_ROOT 178 +#define IMX8MN_CLK_GPU_BUS_ROOT 179 +#define IMX8MN_CLK_ASRC_ROOT 180 +#define IMX8MN_CLK_GPU3D_ROOT 181 +#define IMX8MN_CLK_PDM_ROOT 182 +#define IMX8MN_CLK_PDM_IPG 183 +#define IMX8MN_CLK_DISP_AXI_ROOT 184 +#define IMX8MN_CLK_DISP_APB_ROOT 185 +#define IMX8MN_CLK_DISP_PIXEL_ROOT 186 +#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187 +#define IMX8MN_CLK_USDHC3_ROOT 188 +#define IMX8MN_CLK_SDMA3_ROOT 189 +#define IMX8MN_CLK_TMU_ROOT 190 +#define IMX8MN_CLK_ARM 191 +#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192 +#define IMX8MN_CLK_GPU_CORE_ROOT 193 +#define IMX8MN_CLK_GIC 194 + +#define IMX8MN_SYS_PLL1_40M_CG 195 +#define IMX8MN_SYS_PLL1_80M_CG 196 +#define IMX8MN_SYS_PLL1_100M_CG 197 +#define IMX8MN_SYS_PLL1_133M_CG 198 +#define IMX8MN_SYS_PLL1_160M_CG 199 +#define IMX8MN_SYS_PLL1_200M_CG 200 +#define IMX8MN_SYS_PLL1_266M_CG 201 +#define IMX8MN_SYS_PLL1_400M_CG 202 +#define IMX8MN_SYS_PLL2_50M_CG 203 +#define IMX8MN_SYS_PLL2_100M_CG 204 +#define IMX8MN_SYS_PLL2_125M_CG 205 +#define IMX8MN_SYS_PLL2_166M_CG 206 +#define IMX8MN_SYS_PLL2_200M_CG 207 +#define IMX8MN_SYS_PLL2_250M_CG 208 +#define IMX8MN_SYS_PLL2_333M_CG 209 +#define IMX8MN_SYS_PLL2_500M_CG 210 + +#define IMX8MN_CLK_SNVS_ROOT 211 +#define IMX8MN_CLK_GPU_CORE 212 +#define IMX8MN_CLK_GPU_SHADER 213 + +#define IMX8MN_CLK_A53_CORE 214 + +#define IMX8MN_CLK_END 215 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/imx8mp-clock.h b/roms/u-boot/include/dt-bindings/clock/imx8mp-clock.h new file mode 100644 index 000000000..e8d68fbb6 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/imx8mp-clock.h @@ -0,0 +1,389 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MP_H +#define __DT_BINDINGS_CLOCK_IMX8MP_H + +#define IMX8MP_CLK_DUMMY 0 +#define IMX8MP_CLK_32K 1 +#define IMX8MP_CLK_24M 2 +#define IMX8MP_OSC_HDMI_CLK 3 +#define IMX8MP_CLK_EXT1 4 +#define IMX8MP_CLK_EXT2 5 +#define IMX8MP_CLK_EXT3 6 +#define IMX8MP_CLK_EXT4 7 +#define IMX8MP_AUDIO_PLL1_REF_SEL 8 +#define IMX8MP_AUDIO_PLL2_REF_SEL 9 +#define IMX8MP_VIDEO_PLL1_REF_SEL 10 +#define IMX8MP_DRAM_PLL_REF_SEL 11 +#define IMX8MP_GPU_PLL_REF_SEL 12 +#define IMX8MP_VPU_PLL_REF_SEL 13 +#define IMX8MP_ARM_PLL_REF_SEL 14 +#define IMX8MP_SYS_PLL1_REF_SEL 15 +#define IMX8MP_SYS_PLL2_REF_SEL 16 +#define IMX8MP_SYS_PLL3_REF_SEL 17 +#define IMX8MP_AUDIO_PLL1 18 +#define IMX8MP_AUDIO_PLL2 19 +#define IMX8MP_VIDEO_PLL1 20 +#define IMX8MP_DRAM_PLL 21 +#define IMX8MP_GPU_PLL 22 +#define IMX8MP_VPU_PLL 23 +#define IMX8MP_ARM_PLL 24 +#define IMX8MP_SYS_PLL1 25 +#define IMX8MP_SYS_PLL2 26 +#define IMX8MP_SYS_PLL3 27 +#define IMX8MP_AUDIO_PLL1_BYPASS 28 +#define IMX8MP_AUDIO_PLL2_BYPASS 29 +#define IMX8MP_VIDEO_PLL1_BYPASS 30 +#define IMX8MP_DRAM_PLL_BYPASS 31 +#define IMX8MP_GPU_PLL_BYPASS 32 +#define IMX8MP_VPU_PLL_BYPASS 33 +#define IMX8MP_ARM_PLL_BYPASS 34 +#define IMX8MP_SYS_PLL1_BYPASS 35 +#define IMX8MP_SYS_PLL2_BYPASS 36 +#define IMX8MP_SYS_PLL3_BYPASS 37 +#define IMX8MP_AUDIO_PLL1_OUT 38 +#define IMX8MP_AUDIO_PLL2_OUT 39 +#define IMX8MP_VIDEO_PLL1_OUT 40 +#define IMX8MP_DRAM_PLL_OUT 41 +#define IMX8MP_GPU_PLL_OUT 42 +#define IMX8MP_VPU_PLL_OUT 43 +#define IMX8MP_ARM_PLL_OUT 44 +#define IMX8MP_SYS_PLL1_OUT 45 +#define IMX8MP_SYS_PLL2_OUT 46 +#define IMX8MP_SYS_PLL3_OUT 47 +#define IMX8MP_SYS_PLL1_40M 48 +#define IMX8MP_SYS_PLL1_80M 49 +#define IMX8MP_SYS_PLL1_100M 50 +#define IMX8MP_SYS_PLL1_133M 51 +#define IMX8MP_SYS_PLL1_160M 52 +#define IMX8MP_SYS_PLL1_200M 53 +#define IMX8MP_SYS_PLL1_266M 54 +#define IMX8MP_SYS_PLL1_400M 55 +#define IMX8MP_SYS_PLL1_800M 56 +#define IMX8MP_SYS_PLL2_50M 57 +#define IMX8MP_SYS_PLL2_100M 58 +#define IMX8MP_SYS_PLL2_125M 59 +#define IMX8MP_SYS_PLL2_166M 60 +#define IMX8MP_SYS_PLL2_200M 61 +#define IMX8MP_SYS_PLL2_250M 62 +#define IMX8MP_SYS_PLL2_333M 63 +#define IMX8MP_SYS_PLL2_500M 64 +#define IMX8MP_SYS_PLL2_1000M 65 +#define IMX8MP_CLK_A53_SRC 66 +#define IMX8MP_CLK_M7_SRC 67 +#define IMX8MP_CLK_ML_SRC 68 +#define IMX8MP_CLK_GPU3D_CORE_SRC 69 +#define IMX8MP_CLK_GPU3D_SHADER_SRC 70 +#define IMX8MP_CLK_GPU2D_SRC 71 +#define IMX8MP_CLK_AUDIO_AXI_SRC 72 +#define IMX8MP_CLK_HSIO_AXI_SRC 73 +#define IMX8MP_CLK_MEDIA_ISP_SRC 74 +#define IMX8MP_CLK_A53_CG 75 +#define IMX8MP_CLK_M4_CG 76 +#define IMX8MP_CLK_ML_CG 77 +#define IMX8MP_CLK_GPU3D_CORE_CG 78 +#define IMX8MP_CLK_GPU3D_SHADER_CG 79 +#define IMX8MP_CLK_GPU2D_CG 80 +#define IMX8MP_CLK_AUDIO_AXI_CG 81 +#define IMX8MP_CLK_HSIO_AXI_CG 82 +#define IMX8MP_CLK_MEDIA_ISP_CG 83 +#define IMX8MP_CLK_A53_DIV 84 +#define IMX8MP_CLK_M7_DIV 85 +#define IMX8MP_CLK_ML_DIV 86 +#define IMX8MP_CLK_GPU3D_CORE_DIV 87 +#define IMX8MP_CLK_GPU3D_SHADER_DIV 88 +#define IMX8MP_CLK_GPU2D_DIV 89 +#define IMX8MP_CLK_AUDIO_AXI_DIV 90 +#define IMX8MP_CLK_HSIO_AXI_DIV 91 +#define IMX8MP_CLK_MEDIA_ISP_DIV 92 +#define IMX8MP_CLK_MAIN_AXI 93 +#define IMX8MP_CLK_ENET_AXI 94 +#define IMX8MP_CLK_NAND_USDHC_BUS 95 +#define IMX8MP_CLK_VPU_BUS 96 +#define IMX8MP_CLK_MEDIA_AXI 97 +#define IMX8MP_CLK_MEDIA_APB 98 +#define IMX8MP_CLK_HDMI_APB 99 +#define IMX8MP_CLK_HDMI_AXI 100 +#define IMX8MP_CLK_GPU_AXI 101 +#define IMX8MP_CLK_GPU_AHB 102 +#define IMX8MP_CLK_NOC 103 +#define IMX8MP_CLK_NOC_IO 104 +#define IMX8MP_CLK_ML_AXI 105 +#define IMX8MP_CLK_ML_AHB 106 +#define IMX8MP_CLK_AHB 107 +#define IMX8MP_CLK_AUDIO_AHB 108 +#define IMX8MP_CLK_MIPI_DSI_ESC_RX 109 +#define IMX8MP_CLK_IPG_ROOT 110 +#define IMX8MP_CLK_IPG_AUDIO_ROOT 111 +#define IMX8MP_CLK_DRAM_ALT 112 +#define IMX8MP_CLK_DRAM_APB 113 +#define IMX8MP_CLK_VPU_G1 114 +#define IMX8MP_CLK_VPU_G2 115 +#define IMX8MP_CLK_CAN1 116 +#define IMX8MP_CLK_CAN2 117 +#define IMX8MP_CLK_MEMREPAIR 118 +#define IMX8MP_CLK_PCIE_PHY 119 +#define IMX8MP_CLK_PCIE_AUX 120 +#define IMX8MP_CLK_I2C5 121 +#define IMX8MP_CLK_I2C6 122 +#define IMX8MP_CLK_SAI1 123 +#define IMX8MP_CLK_SAI2 124 +#define IMX8MP_CLK_SAI3 125 +#define IMX8MP_CLK_SAI4 126 +#define IMX8MP_CLK_SAI5 127 +#define IMX8MP_CLK_SAI6 128 +#define IMX8MP_CLK_ENET_QOS 129 +#define IMX8MP_CLK_ENET_QOS_TIMER 130 +#define IMX8MP_CLK_ENET_REF 131 +#define IMX8MP_CLK_ENET_TIMER 132 +#define IMX8MP_CLK_ENET_PHY_REF 133 +#define IMX8MP_CLK_NAND 134 +#define IMX8MP_CLK_QSPI 135 +#define IMX8MP_CLK_USDHC1 136 +#define IMX8MP_CLK_USDHC2 137 +#define IMX8MP_CLK_I2C1 138 +#define IMX8MP_CLK_I2C2 139 +#define IMX8MP_CLK_I2C3 140 +#define IMX8MP_CLK_I2C4 141 +#define IMX8MP_CLK_UART1 142 +#define IMX8MP_CLK_UART2 143 +#define IMX8MP_CLK_UART3 144 +#define IMX8MP_CLK_UART4 145 +#define IMX8MP_CLK_USB_CORE_REF 146 +#define IMX8MP_CLK_USB_PHY_REF 147 +#define IMX8MP_CLK_GIC 148 +#define IMX8MP_CLK_ECSPI1 149 +#define IMX8MP_CLK_ECSPI2 150 +#define IMX8MP_CLK_PWM1 151 +#define IMX8MP_CLK_PWM2 152 +#define IMX8MP_CLK_PWM3 153 +#define IMX8MP_CLK_PWM4 154 +#define IMX8MP_CLK_GPT1 155 +#define IMX8MP_CLK_GPT2 156 +#define IMX8MP_CLK_GPT3 157 +#define IMX8MP_CLK_GPT4 158 +#define IMX8MP_CLK_GPT5 159 +#define IMX8MP_CLK_GPT6 160 +#define IMX8MP_CLK_TRACE 161 +#define IMX8MP_CLK_WDOG 162 +#define IMX8MP_CLK_WRCLK 163 +#define IMX8MP_CLK_IPP_DO_CLKO1 164 +#define IMX8MP_CLK_IPP_DO_CLKO2 165 +#define IMX8MP_CLK_HDMI_FDCC_TST 166 +#define IMX8MP_CLK_HDMI_24M 167 +#define IMX8MP_CLK_HDMI_REF_266M 168 +#define IMX8MP_CLK_USDHC3 169 +#define IMX8MP_CLK_MEDIA_CAM1_PIX 170 +#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171 +#define IMX8MP_CLK_MEDIA_DISP1_PIX 172 +#define IMX8MP_CLK_MEDIA_CAM2_PIX 173 +#define IMX8MP_CLK_MEDIA_LDB 174 +#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175 +#define IMX8MP_CLK_PCIE2_CTRL 176 +#define IMX8MP_CLK_PCIE2_PHY 177 +#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178 +#define IMX8MP_CLK_ECSPI3 179 +#define IMX8MP_CLK_PDM 180 +#define IMX8MP_CLK_VPU_VC8000E 181 +#define IMX8MP_CLK_SAI7 182 +#define IMX8MP_CLK_GPC_ROOT 183 +#define IMX8MP_CLK_ANAMIX_ROOT 184 +#define IMX8MP_CLK_CPU_ROOT 185 +#define IMX8MP_CLK_CSU_ROOT 186 +#define IMX8MP_CLK_DEBUG_ROOT 187 +#define IMX8MP_CLK_DRAM1_ROOT 188 +#define IMX8MP_CLK_ECSPI1_ROOT 189 +#define IMX8MP_CLK_ECSPI2_ROOT 190 +#define IMX8MP_CLK_ECSPI3_ROOT 191 +#define IMX8MP_CLK_ENET1_ROOT 192 +#define IMX8MP_CLK_GPIO1_ROOT 193 +#define IMX8MP_CLK_GPIO2_ROOT 194 +#define IMX8MP_CLK_GPIO3_ROOT 195 +#define IMX8MP_CLK_GPIO4_ROOT 196 +#define IMX8MP_CLK_GPIO5_ROOT 197 +#define IMX8MP_CLK_GPT1_ROOT 198 +#define IMX8MP_CLK_GPT2_ROOT 199 +#define IMX8MP_CLK_GPT3_ROOT 200 +#define IMX8MP_CLK_GPT4_ROOT 201 +#define IMX8MP_CLK_GPT5_ROOT 202 +#define IMX8MP_CLK_GPT6_ROOT 203 +#define IMX8MP_CLK_HS_ROOT 204 +#define IMX8MP_CLK_I2C1_ROOT 205 +#define IMX8MP_CLK_I2C2_ROOT 206 +#define IMX8MP_CLK_I2C3_ROOT 207 +#define IMX8MP_CLK_I2C4_ROOT 208 +#define IMX8MP_CLK_IOMUX_ROOT 209 +#define IMX8MP_CLK_IPMUX1_ROOT 210 +#define IMX8MP_CLK_IPMUX2_ROOT 211 +#define IMX8MP_CLK_IPMUX3_ROOT 212 +#define IMX8MP_CLK_MU_ROOT 213 +#define IMX8MP_CLK_OCOTP_ROOT 214 +#define IMX8MP_CLK_OCRAM_ROOT 215 +#define IMX8MP_CLK_OCRAM_S_ROOT 216 +#define IMX8MP_CLK_PCIE_ROOT 217 +#define IMX8MP_CLK_PERFMON1_ROOT 218 +#define IMX8MP_CLK_PERFMON2_ROOT 219 +#define IMX8MP_CLK_PWM1_ROOT 220 +#define IMX8MP_CLK_PWM2_ROOT 221 +#define IMX8MP_CLK_PWM3_ROOT 222 +#define IMX8MP_CLK_PWM4_ROOT 223 +#define IMX8MP_CLK_QOS_ROOT 224 +#define IMX8MP_CLK_QOS_ENET_ROOT 225 +#define IMX8MP_CLK_QSPI_ROOT 226 +#define IMX8MP_CLK_NAND_ROOT 227 +#define IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 228 +#define IMX8MP_CLK_RDC_ROOT 229 +#define IMX8MP_CLK_ROM_ROOT 230 +#define IMX8MP_CLK_I2C5_ROOT 231 +#define IMX8MP_CLK_I2C6_ROOT 232 +#define IMX8MP_CLK_CAN1_ROOT 233 +#define IMX8MP_CLK_CAN2_ROOT 234 +#define IMX8MP_CLK_SCTR_ROOT 235 +#define IMX8MP_CLK_SDMA1_ROOT 236 +#define IMX8MP_CLK_ENET_QOS_ROOT 237 +#define IMX8MP_CLK_SEC_DEBUG_ROOT 238 +#define IMX8MP_CLK_SEMA1_ROOT 239 +#define IMX8MP_CLK_SEMA2_ROOT 240 +#define IMX8MP_CLK_IRQ_STEER_ROOT 241 +#define IMX8MP_CLK_SIM_ENET_ROOT 242 +#define IMX8MP_CLK_SIM_M_ROOT 243 +#define IMX8MP_CLK_SIM_MAIN_ROOT 244 +#define IMX8MP_CLK_SIM_S_ROOT 245 +#define IMX8MP_CLK_SIM_WAKEUP_ROOT 246 +#define IMX8MP_CLK_GPU2D_ROOT 247 +#define IMX8MP_CLK_GPU3D_ROOT 248 +#define IMX8MP_CLK_SNVS_ROOT 249 +#define IMX8MP_CLK_TRACE_ROOT 250 +#define IMX8MP_CLK_UART1_ROOT 251 +#define IMX8MP_CLK_UART2_ROOT 252 +#define IMX8MP_CLK_UART3_ROOT 253 +#define IMX8MP_CLK_UART4_ROOT 254 +#define IMX8MP_CLK_USB_ROOT 255 +#define IMX8MP_CLK_USB_PHY_ROOT 256 +#define IMX8MP_CLK_USDHC1_ROOT 257 +#define IMX8MP_CLK_USDHC2_ROOT 258 +#define IMX8MP_CLK_WDOG1_ROOT 259 +#define IMX8MP_CLK_WDOG2_ROOT 260 +#define IMX8MP_CLK_WDOG3_ROOT 261 +#define IMX8MP_CLK_VPU_G1_ROOT 262 +#define IMX8MP_CLK_GPU_ROOT 263 +#define IMX8MP_CLK_NOC_WRAPPER_ROOT 264 +#define IMX8MP_CLK_VPU_VC8KE_ROOT 265 +#define IMX8MP_CLK_VPU_G2_ROOT 266 +#define IMX8MP_CLK_NPU_ROOT 267 +#define IMX8MP_CLK_HSIO_ROOT 268 +#define IMX8MP_CLK_MEDIA_APB_ROOT 269 +#define IMX8MP_CLK_MEDIA_AXI_ROOT 270 +#define IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT 271 +#define IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT 272 +#define IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT 273 +#define IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT 274 +#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT 275 +#define IMX8MP_CLK_MEDIA_ISP_ROOT 276 +#define IMX8MP_CLK_USDHC3_ROOT 277 +#define IMX8MP_CLK_HDMI_ROOT 278 +#define IMX8MP_CLK_XTAL_ROOT 279 +#define IMX8MP_CLK_PLL_ROOT 280 +#define IMX8MP_CLK_TSENSOR_ROOT 281 +#define IMX8MP_CLK_VPU_ROOT 282 +#define IMX8MP_CLK_MRPR_ROOT 283 +#define IMX8MP_CLK_AUDIO_ROOT 284 +#define IMX8MP_CLK_DRAM_ALT_ROOT 285 +#define IMX8MP_CLK_DRAM_CORE 286 +#define IMX8MP_CLK_ARM 287 +#define IMX8MP_CLK_A53_CORE 288 + +#define IMX8MP_SYS_PLL1_40M_CG 289 +#define IMX8MP_SYS_PLL1_80M_CG 290 +#define IMX8MP_SYS_PLL1_100M_CG 291 +#define IMX8MP_SYS_PLL1_133M_CG 292 +#define IMX8MP_SYS_PLL1_160M_CG 293 +#define IMX8MP_SYS_PLL1_200M_CG 294 +#define IMX8MP_SYS_PLL1_266M_CG 295 +#define IMX8MP_SYS_PLL1_400M_CG 296 +#define IMX8MP_SYS_PLL2_50M_CG 297 +#define IMX8MP_SYS_PLL2_100M_CG 298 +#define IMX8MP_SYS_PLL2_125M_CG 299 +#define IMX8MP_SYS_PLL2_166M_CG 300 +#define IMX8MP_SYS_PLL2_200M_CG 301 +#define IMX8MP_SYS_PLL2_250M_CG 302 +#define IMX8MP_SYS_PLL2_333M_CG 303 +#define IMX8MP_SYS_PLL2_500M_CG 304 + +#define IMX8MP_CLK_M7_CORE 305 +#define IMX8MP_CLK_ML_CORE 306 +#define IMX8MP_CLK_GPU3D_CORE 307 +#define IMX8MP_CLK_GPU3D_SHADER_CORE 308 +#define IMX8MP_CLK_GPU2D_CORE 309 +#define IMX8MP_CLK_AUDIO_AXI 310 +#define IMX8MP_CLK_HSIO_AXI 311 +#define IMX8MP_CLK_MEDIA_ISP 312 + +#define IMX8MP_CLK_END 313 + +#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 +#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 +#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2 +#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3 +#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4 +#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5 +#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6 +#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7 +#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8 +#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9 +#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10 +#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11 +#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12 +#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13 +#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14 +#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15 +#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16 +#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17 +#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18 +#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19 +#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20 +#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21 +#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22 +#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23 +#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24 +#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25 +#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26 +#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27 +#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28 +#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29 +#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30 +#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31 +#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32 +#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33 +#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34 +#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35 +#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 +#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 +#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 +#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39 +#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 +#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 +#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 +#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43 +#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44 +#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45 +#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46 +#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47 +#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48 +#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49 +#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50 +#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51 +#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52 +#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53 +#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54 +#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55 +#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56 +#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57 +#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58 + +#define IMX8MP_CLK_AUDIOMIX_END 59 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/imx8mq-clock.h b/roms/u-boot/include/dt-bindings/clock/imx8mq-clock.h new file mode 100644 index 000000000..9b8045d75 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/imx8mq-clock.h @@ -0,0 +1,436 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H +#define __DT_BINDINGS_CLOCK_IMX8MQ_H + +#define IMX8MQ_CLK_DUMMY 0 +#define IMX8MQ_CLK_32K 1 +#define IMX8MQ_CLK_25M 2 +#define IMX8MQ_CLK_27M 3 +#define IMX8MQ_CLK_EXT1 4 +#define IMX8MQ_CLK_EXT2 5 +#define IMX8MQ_CLK_EXT3 6 +#define IMX8MQ_CLK_EXT4 7 + +/* ANAMIX PLL clocks */ +/* FRAC PLLs */ +/* ARM PLL */ +#define IMX8MQ_ARM_PLL_REF_SEL 8 +#define IMX8MQ_ARM_PLL_REF_DIV 9 +#define IMX8MQ_ARM_PLL 10 +#define IMX8MQ_ARM_PLL_BYPASS 11 +#define IMX8MQ_ARM_PLL_OUT 12 + +/* GPU PLL */ +#define IMX8MQ_GPU_PLL_REF_SEL 13 +#define IMX8MQ_GPU_PLL_REF_DIV 14 +#define IMX8MQ_GPU_PLL 15 +#define IMX8MQ_GPU_PLL_BYPASS 16 +#define IMX8MQ_GPU_PLL_OUT 17 + +/* VPU PLL */ +#define IMX8MQ_VPU_PLL_REF_SEL 18 +#define IMX8MQ_VPU_PLL_REF_DIV 19 +#define IMX8MQ_VPU_PLL 20 +#define IMX8MQ_VPU_PLL_BYPASS 21 +#define IMX8MQ_VPU_PLL_OUT 22 + +/* AUDIO PLL1 */ +#define IMX8MQ_AUDIO_PLL1_REF_SEL 23 +#define IMX8MQ_AUDIO_PLL1_REF_DIV 24 +#define IMX8MQ_AUDIO_PLL1 25 +#define IMX8MQ_AUDIO_PLL1_BYPASS 26 +#define IMX8MQ_AUDIO_PLL1_OUT 27 + +/* AUDIO PLL2 */ +#define IMX8MQ_AUDIO_PLL2_REF_SEL 28 +#define IMX8MQ_AUDIO_PLL2_REF_DIV 29 +#define IMX8MQ_AUDIO_PLL2 30 +#define IMX8MQ_AUDIO_PLL2_BYPASS 31 +#define IMX8MQ_AUDIO_PLL2_OUT 32 + +/* VIDEO PLL1 */ +#define IMX8MQ_VIDEO_PLL1_REF_SEL 33 +#define IMX8MQ_VIDEO_PLL1_REF_DIV 34 +#define IMX8MQ_VIDEO_PLL1 35 +#define IMX8MQ_VIDEO_PLL1_BYPASS 36 +#define IMX8MQ_VIDEO_PLL1_OUT 37 + +/* SYS1 PLL */ +#define IMX8MQ_SYS1_PLL1_REF_SEL 38 +#define IMX8MQ_SYS1_PLL1_REF_DIV 39 +#define IMX8MQ_SYS1_PLL1 40 +#define IMX8MQ_SYS1_PLL1_OUT 41 +#define IMX8MQ_SYS1_PLL1_OUT_DIV 42 +#define IMX8MQ_SYS1_PLL2 43 +#define IMX8MQ_SYS1_PLL2_DIV 44 +#define IMX8MQ_SYS1_PLL2_OUT 45 + +/* SYS2 PLL */ +#define IMX8MQ_SYS2_PLL1_REF_SEL 46 +#define IMX8MQ_SYS2_PLL1_REF_DIV 47 +#define IMX8MQ_SYS2_PLL1 48 +#define IMX8MQ_SYS2_PLL1_OUT 49 +#define IMX8MQ_SYS2_PLL1_OUT_DIV 50 +#define IMX8MQ_SYS2_PLL2 51 +#define IMX8MQ_SYS2_PLL2_DIV 52 +#define IMX8MQ_SYS2_PLL2_OUT 53 + +/* SYS3 PLL */ +#define IMX8MQ_SYS3_PLL1_REF_SEL 54 +#define IMX8MQ_SYS3_PLL1_REF_DIV 55 +#define IMX8MQ_SYS3_PLL1 56 +#define IMX8MQ_SYS3_PLL1_OUT 57 +#define IMX8MQ_SYS3_PLL1_OUT_DIV 58 +#define IMX8MQ_SYS3_PLL2 59 +#define IMX8MQ_SYS3_PLL2_DIV 60 +#define IMX8MQ_SYS3_PLL2_OUT 61 + +/* DRAM PLL */ +#define IMX8MQ_DRAM_PLL1_REF_SEL 62 +#define IMX8MQ_DRAM_PLL1_REF_DIV 63 +#define IMX8MQ_DRAM_PLL1 64 +#define IMX8MQ_DRAM_PLL1_OUT 65 +#define IMX8MQ_DRAM_PLL1_OUT_DIV 66 +#define IMX8MQ_DRAM_PLL2 67 +#define IMX8MQ_DRAM_PLL2_DIV 68 +#define IMX8MQ_DRAM_PLL2_OUT 69 + +/* SYS PLL DIV */ +#define IMX8MQ_SYS1_PLL_40M 70 +#define IMX8MQ_SYS1_PLL_80M 71 +#define IMX8MQ_SYS1_PLL_100M 72 +#define IMX8MQ_SYS1_PLL_133M 73 +#define IMX8MQ_SYS1_PLL_160M 74 +#define IMX8MQ_SYS1_PLL_200M 75 +#define IMX8MQ_SYS1_PLL_266M 76 +#define IMX8MQ_SYS1_PLL_400M 77 +#define IMX8MQ_SYS1_PLL_800M 78 + +#define IMX8MQ_SYS2_PLL_50M 79 +#define IMX8MQ_SYS2_PLL_100M 80 +#define IMX8MQ_SYS2_PLL_125M 81 +#define IMX8MQ_SYS2_PLL_166M 82 +#define IMX8MQ_SYS2_PLL_200M 83 +#define IMX8MQ_SYS2_PLL_250M 84 +#define IMX8MQ_SYS2_PLL_333M 85 +#define IMX8MQ_SYS2_PLL_500M 86 +#define IMX8MQ_SYS2_PLL_1000M 87 + +/* CCM ROOT clocks */ +/* A53 */ +#define IMX8MQ_CLK_A53_SRC 88 +#define IMX8MQ_CLK_A53_CG 89 +#define IMX8MQ_CLK_A53_DIV 90 +/* M4 */ +#define IMX8MQ_CLK_M4_SRC 91 +#define IMX8MQ_CLK_M4_CG 92 +#define IMX8MQ_CLK_M4_DIV 93 +/* VPU */ +#define IMX8MQ_CLK_VPU_SRC 94 +#define IMX8MQ_CLK_VPU_CG 95 +#define IMX8MQ_CLK_VPU_DIV 96 +/* GPU CORE */ +#define IMX8MQ_CLK_GPU_CORE_SRC 97 +#define IMX8MQ_CLK_GPU_CORE_CG 98 +#define IMX8MQ_CLK_GPU_CORE_DIV 99 +/* GPU SHADER */ +#define IMX8MQ_CLK_GPU_SHADER_SRC 100 +#define IMX8MQ_CLK_GPU_SHADER_CG 101 +#define IMX8MQ_CLK_GPU_SHADER_DIV 102 + +/* BUS TYPE */ +/* MAIN AXI */ +#define IMX8MQ_CLK_MAIN_AXI 103 +/* ENET AXI */ +#define IMX8MQ_CLK_ENET_AXI 104 +/* NAND_USDHC_BUS */ +#define IMX8MQ_CLK_NAND_USDHC_BUS 105 +/* VPU BUS */ +#define IMX8MQ_CLK_VPU_BUS 106 +/* DISP_AXI */ +#define IMX8MQ_CLK_DISP_AXI 107 +/* DISP APB */ +#define IMX8MQ_CLK_DISP_APB 108 +/* DISP RTRM */ +#define IMX8MQ_CLK_DISP_RTRM 109 +/* USB_BUS */ +#define IMX8MQ_CLK_USB_BUS 110 +/* GPU_AXI */ +#define IMX8MQ_CLK_GPU_AXI 111 +/* GPU_AHB */ +#define IMX8MQ_CLK_GPU_AHB 112 +/* NOC */ +#define IMX8MQ_CLK_NOC 113 +/* NOC_APB */ +#define IMX8MQ_CLK_NOC_APB 115 + +/* AHB */ +#define IMX8MQ_CLK_AHB 116 +/* AUDIO AHB */ +#define IMX8MQ_CLK_AUDIO_AHB 117 + +/* DRAM_ALT */ +#define IMX8MQ_CLK_DRAM_ALT 118 +/* DRAM APB */ +#define IMX8MQ_CLK_DRAM_APB 119 +/* VPU_G1 */ +#define IMX8MQ_CLK_VPU_G1 120 +/* VPU_G2 */ +#define IMX8MQ_CLK_VPU_G2 121 +/* DISP_DTRC */ +#define IMX8MQ_CLK_DISP_DTRC 122 +/* DISP_DC8000 */ +#define IMX8MQ_CLK_DISP_DC8000 123 +/* PCIE_CTRL */ +#define IMX8MQ_CLK_PCIE1_CTRL 124 +/* PCIE_PHY */ +#define IMX8MQ_CLK_PCIE1_PHY 125 +/* PCIE_AUX */ +#define IMX8MQ_CLK_PCIE1_AUX 126 +/* DC_PIXEL */ +#define IMX8MQ_CLK_DC_PIXEL 127 +/* LCDIF_PIXEL */ +#define IMX8MQ_CLK_LCDIF_PIXEL 128 +/* SAI1~6 */ +#define IMX8MQ_CLK_SAI1 129 + +#define IMX8MQ_CLK_SAI2 130 + +#define IMX8MQ_CLK_SAI3 131 + +#define IMX8MQ_CLK_SAI4 132 + +#define IMX8MQ_CLK_SAI5 133 + +#define IMX8MQ_CLK_SAI6 134 +/* SPDIF1 */ +#define IMX8MQ_CLK_SPDIF1 135 +/* SPDIF2 */ +#define IMX8MQ_CLK_SPDIF2 136 +/* ENET_REF */ +#define IMX8MQ_CLK_ENET_REF 137 +/* ENET_TIMER */ +#define IMX8MQ_CLK_ENET_TIMER 138 +/* ENET_PHY */ +#define IMX8MQ_CLK_ENET_PHY_REF 139 +/* NAND */ +#define IMX8MQ_CLK_NAND 140 +/* QSPI */ +#define IMX8MQ_CLK_QSPI 141 +/* USDHC1 */ +#define IMX8MQ_CLK_USDHC1 142 +/* USDHC2 */ +#define IMX8MQ_CLK_USDHC2 143 +/* I2C1 */ +#define IMX8MQ_CLK_I2C1 144 +/* I2C2 */ +#define IMX8MQ_CLK_I2C2 145 +/* I2C3 */ +#define IMX8MQ_CLK_I2C3 146 +/* I2C4 */ +#define IMX8MQ_CLK_I2C4 147 +/* UART1 */ +#define IMX8MQ_CLK_UART1 148 +/* UART2 */ +#define IMX8MQ_CLK_UART2 149 +/* UART3 */ +#define IMX8MQ_CLK_UART3 150 +/* UART4 */ +#define IMX8MQ_CLK_UART4 151 +/* USB_CORE_REF */ +#define IMX8MQ_CLK_USB_CORE_REF 152 +/* USB_PHY_REF */ +#define IMX8MQ_CLK_USB_PHY_REF 153 +/* ECSPI1 */ +#define IMX8MQ_CLK_ECSPI1 154 +/* ECSPI2 */ +#define IMX8MQ_CLK_ECSPI2 155 +/* PWM1 */ +#define IMX8MQ_CLK_PWM1 156 +/* PWM2 */ +#define IMX8MQ_CLK_PWM2 157 +/* PWM3 */ +#define IMX8MQ_CLK_PWM3 158 +/* PWM4 */ +#define IMX8MQ_CLK_PWM4 159 +/* GPT1 */ +#define IMX8MQ_CLK_GPT1 160 +/* WDOG */ +#define IMX8MQ_CLK_WDOG 161 +/* WRCLK */ +#define IMX8MQ_CLK_WRCLK 162 +/* DSI_CORE */ +#define IMX8MQ_CLK_DSI_CORE 163 +/* DSI_PHY */ +#define IMX8MQ_CLK_DSI_PHY_REF 164 +/* DSI_DBI */ +#define IMX8MQ_CLK_DSI_DBI 165 +/*DSI_ESC */ +#define IMX8MQ_CLK_DSI_ESC 166 +/* CSI1_CORE */ +#define IMX8MQ_CLK_CSI1_CORE 167 +/* CSI1_PHY */ +#define IMX8MQ_CLK_CSI1_PHY_REF 168 +/* CSI_ESC */ +#define IMX8MQ_CLK_CSI1_ESC 169 +/* CSI2_CORE */ +#define IMX8MQ_CLK_CSI2_CORE 170 +/* CSI2_PHY */ +#define IMX8MQ_CLK_CSI2_PHY_REF 171 +/* CSI2_ESC */ +#define IMX8MQ_CLK_CSI2_ESC 172 +/* PCIE2_CTRL */ +#define IMX8MQ_CLK_PCIE2_CTRL 173 +/* PCIE2_PHY */ +#define IMX8MQ_CLK_PCIE2_PHY 174 +/* PCIE2_AUX */ +#define IMX8MQ_CLK_PCIE2_AUX 175 +/* ECSPI3 */ +#define IMX8MQ_CLK_ECSPI3 176 + +/* CCGR clocks */ +#define IMX8MQ_CLK_A53_ROOT 177 +#define IMX8MQ_CLK_DRAM_ROOT 178 +#define IMX8MQ_CLK_ECSPI1_ROOT 179 +#define IMX8MQ_CLK_ECSPI2_ROOT 180 +#define IMX8MQ_CLK_ECSPI3_ROOT 181 +#define IMX8MQ_CLK_ENET1_ROOT 182 +#define IMX8MQ_CLK_GPT1_ROOT 183 +#define IMX8MQ_CLK_I2C1_ROOT 184 +#define IMX8MQ_CLK_I2C2_ROOT 185 +#define IMX8MQ_CLK_I2C3_ROOT 186 +#define IMX8MQ_CLK_I2C4_ROOT 187 +#define IMX8MQ_CLK_M4_ROOT 188 +#define IMX8MQ_CLK_PCIE1_ROOT 189 +#define IMX8MQ_CLK_PCIE2_ROOT 190 +#define IMX8MQ_CLK_PWM1_ROOT 191 +#define IMX8MQ_CLK_PWM2_ROOT 192 +#define IMX8MQ_CLK_PWM3_ROOT 193 +#define IMX8MQ_CLK_PWM4_ROOT 194 +#define IMX8MQ_CLK_QSPI_ROOT 195 +#define IMX8MQ_CLK_SAI1_ROOT 196 +#define IMX8MQ_CLK_SAI2_ROOT 197 +#define IMX8MQ_CLK_SAI3_ROOT 198 +#define IMX8MQ_CLK_SAI4_ROOT 199 +#define IMX8MQ_CLK_SAI5_ROOT 200 +#define IMX8MQ_CLK_SAI6_ROOT 201 +#define IMX8MQ_CLK_UART1_ROOT 202 +#define IMX8MQ_CLK_UART2_ROOT 203 +#define IMX8MQ_CLK_UART3_ROOT 204 +#define IMX8MQ_CLK_UART4_ROOT 205 +#define IMX8MQ_CLK_USB1_CTRL_ROOT 206 +#define IMX8MQ_CLK_USB2_CTRL_ROOT 207 +#define IMX8MQ_CLK_USB1_PHY_ROOT 208 +#define IMX8MQ_CLK_USB2_PHY_ROOT 209 +#define IMX8MQ_CLK_USDHC1_ROOT 210 +#define IMX8MQ_CLK_USDHC2_ROOT 211 +#define IMX8MQ_CLK_WDOG1_ROOT 212 +#define IMX8MQ_CLK_WDOG2_ROOT 213 +#define IMX8MQ_CLK_WDOG3_ROOT 214 +#define IMX8MQ_CLK_GPU_ROOT 215 +#define IMX8MQ_CLK_HEVC_ROOT 216 +#define IMX8MQ_CLK_AVC_ROOT 217 +#define IMX8MQ_CLK_VP9_ROOT 218 +#define IMX8MQ_CLK_HEVC_INTER_ROOT 219 +#define IMX8MQ_CLK_DISP_ROOT 220 +#define IMX8MQ_CLK_HDMI_ROOT 221 +#define IMX8MQ_CLK_HDMI_PHY_ROOT 222 +#define IMX8MQ_CLK_VPU_DEC_ROOT 223 +#define IMX8MQ_CLK_CSI1_ROOT 224 +#define IMX8MQ_CLK_CSI2_ROOT 225 +#define IMX8MQ_CLK_RAWNAND_ROOT 226 +#define IMX8MQ_CLK_SDMA1_ROOT 227 +#define IMX8MQ_CLK_SDMA2_ROOT 228 +#define IMX8MQ_CLK_VPU_G1_ROOT 229 +#define IMX8MQ_CLK_VPU_G2_ROOT 230 + +/* SCCG PLL GATE */ +#define IMX8MQ_SYS1_PLL_OUT 231 +#define IMX8MQ_SYS2_PLL_OUT 232 +#define IMX8MQ_SYS3_PLL_OUT 233 +#define IMX8MQ_DRAM_PLL_OUT 234 + +#define IMX8MQ_GPT_3M_CLK 235 + +#define IMX8MQ_CLK_IPG_ROOT 236 +#define IMX8MQ_CLK_IPG_AUDIO_ROOT 237 +#define IMX8MQ_CLK_SAI1_IPG 238 +#define IMX8MQ_CLK_SAI2_IPG 239 +#define IMX8MQ_CLK_SAI3_IPG 240 +#define IMX8MQ_CLK_SAI4_IPG 241 +#define IMX8MQ_CLK_SAI5_IPG 242 +#define IMX8MQ_CLK_SAI6_IPG 243 + +/* DSI AHB/IPG clocks */ +/* rxesc clock */ +#define IMX8MQ_CLK_DSI_AHB 244 +/* txesc clock */ +#define IMX8MQ_CLK_DSI_IPG_DIV 245 + +#define IMX8MQ_CLK_TMU_ROOT 246 + +/* Display root clocks */ +#define IMX8MQ_CLK_DISP_AXI_ROOT 247 +#define IMX8MQ_CLK_DISP_APB_ROOT 248 +#define IMX8MQ_CLK_DISP_RTRM_ROOT 249 + +#define IMX8MQ_CLK_OCOTP_ROOT 250 + +#define IMX8MQ_CLK_DRAM_ALT_ROOT 251 +#define IMX8MQ_CLK_DRAM_CORE 252 + +#define IMX8MQ_CLK_MU_ROOT 253 +#define IMX8MQ_VIDEO2_PLL_OUT 254 + +#define IMX8MQ_CLK_CLKO2 255 + +#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 256 + +#define IMX8MQ_CLK_CLKO1 257 +#define IMX8MQ_CLK_ARM 258 + +#define IMX8MQ_CLK_GPIO1_ROOT 259 +#define IMX8MQ_CLK_GPIO2_ROOT 260 +#define IMX8MQ_CLK_GPIO3_ROOT 261 +#define IMX8MQ_CLK_GPIO4_ROOT 262 +#define IMX8MQ_CLK_GPIO5_ROOT 263 + +#define IMX8MQ_CLK_SNVS_ROOT 264 +#define IMX8MQ_CLK_GIC 265 + +#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266 + +#define IMX8MQ_SYS1_PLL_40M_CG 267 +#define IMX8MQ_SYS1_PLL_80M_CG 268 +#define IMX8MQ_SYS1_PLL_100M_CG 269 +#define IMX8MQ_SYS1_PLL_133M_CG 270 +#define IMX8MQ_SYS1_PLL_160M_CG 271 +#define IMX8MQ_SYS1_PLL_200M_CG 272 +#define IMX8MQ_SYS1_PLL_266M_CG 273 +#define IMX8MQ_SYS1_PLL_400M_CG 274 +#define IMX8MQ_SYS1_PLL_800M_CG 275 +#define IMX8MQ_SYS2_PLL_50M_CG 276 +#define IMX8MQ_SYS2_PLL_100M_CG 277 +#define IMX8MQ_SYS2_PLL_125M_CG 278 +#define IMX8MQ_SYS2_PLL_166M_CG 279 +#define IMX8MQ_SYS2_PLL_200M_CG 280 +#define IMX8MQ_SYS2_PLL_250M_CG 281 +#define IMX8MQ_SYS2_PLL_333M_CG 282 +#define IMX8MQ_SYS2_PLL_500M_CG 283 +#define IMX8MQ_SYS2_PLL_1000M_CG 284 + +#define IMX8MQ_CLK_GPU_CORE 285 +#define IMX8MQ_CLK_GPU_SHADER 286 +#define IMX8MQ_CLK_M4_CORE 287 +#define IMX8MQ_CLK_VPU_CORE 288 + +#define IMX8MQ_CLK_A53_CORE 289 + +#define IMX8MQ_CLK_END 290 + +#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/imx8qm-clock.h b/roms/u-boot/include/dt-bindings/clock/imx8qm-clock.h new file mode 100644 index 000000000..58de976e6 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/imx8qm-clock.h @@ -0,0 +1,846 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8QM_H +#define __DT_BINDINGS_CLOCK_IMX8QM_H + +#define IMX8QM_CLK_DUMMY 0 + +#define IMX8QM_A53_DIV 1 +#define IMX8QM_A53_CLK 2 +#define IMX8QM_A72_DIV 3 +#define IMX8QM_A72_CLK 4 + +/* SC Clocks. */ +#define IMX8QM_SC_I2C_DIV 5 +#define IMX8QM_SC_I2C_CLK 6 +#define IMX8QM_SC_PID0_DIV 7 +#define IMX8QM_SC_PID0_CLK 8 +#define IMX8QM_SC_PIT_DIV 9 +#define IMX8QM_SC_PIT_CLK 10 +#define IMX8QM_SC_TPM_DIV 11 +#define IMX8QM_SC_TPM_CLK 12 +#define IMX8QM_SC_UART_DIV 13 +#define IMX8QM_SC_UART_CLK 14 + +/* LSIO */ +#define IMX8QM_PWM0_DIV 15 +#define IMX8QM_PWM0_CLK 16 +#define IMX8QM_PWM1_DIV 17 +#define IMX8QM_PWM1_CLK 18 +#define IMX8QM_PWM2_DIV 19 +#define IMX8QM_PWM2_CLK 20 +#define IMX8QM_PWM3_DIV 21 +#define IMX8QM_PWM3_CLK 22 +#define IMX8QM_PWM4_DIV 23 +#define IMX8QM_PWM4_CLK 24 +#define IMX8QM_PWM5_DIV 26 +#define IMX8QM_PWM5_CLK 27 +#define IMX8QM_PWM6_DIV 28 +#define IMX8QM_PWM6_CLK 29 +#define IMX8QM_PWM7_DIV 30 +#define IMX8QM_PWM7_CLK 31 +#define IMX8QM_FSPI0_DIV 32 +#define IMX8QM_FSPI0_CLK 33 +#define IMX8QM_FSPI1_DIV 34 +#define IMX8QM_FSPI1_CLK 35 +#define IMX8QM_GPT0_DIV 36 +#define IMX8QM_GPT0_CLK 37 +#define IMX8QM_GPT1_DIV 38 +#define IMX8QM_GPT1_CLK 39 +#define IMX8QM_GPT2_DIV 40 +#define IMX8QM_GPT2_CLK 41 +#define IMX8QM_GPT3_DIV 42 +#define IMX8QM_GPT3_CLK 43 +#define IMX8QM_GPT4_DIV 44 +#define IMX8QM_GPT4_CLK 45 + +/* Connectivity */ +#define IMX8QM_APBHDMA_CLK 46 +#define IMX8QM_GPMI_APB_CLK 47 +#define IMX8QM_GPMI_APB_BCH_CLK 48 +#define IMX8QM_GPMI_BCH_IO_DIV 49 +#define IMX8QM_GPMI_BCH_IO_CLK 50 +#define IMX8QM_GPMI_BCH_DIV 51 +#define IMX8QM_GPMI_BCH_CLK 52 +#define IMX8QM_SDHC0_IPG_CLK 53 +#define IMX8QM_SDHC0_DIV 54 +#define IMX8QM_SDHC0_CLK 55 +#define IMX8QM_SDHC1_IPG_CLK 56 +#define IMX8QM_SDHC1_DIV 57 +#define IMX8QM_SDHC1_CLK 58 +#define IMX8QM_SDHC2_IPG_CLK 59 +#define IMX8QM_SDHC2_DIV 60 +#define IMX8QM_SDHC2_CLK 61 +#define IMX8QM_USB2_OH_AHB_CLK 62 +#define IMX8QM_USB2_OH_IPG_S_CLK 63 +#define IMX8QM_USB2_OH_IPG_S_PL301_CLK 64 +#define IMX8QM_USB2_PHY_IPG_CLK 65 +#define IMX8QM_USB3_IPG_CLK 66 +#define IMX8QM_USB3_CORE_PCLK 67 +#define IMX8QM_USB3_PHY_CLK 68 +#define IMX8QM_USB3_ACLK_DIV 69 +#define IMX8QM_USB3_ACLK 70 +#define IMX8QM_USB3_BUS_DIV 71 +#define IMX8QM_USB3_BUS_CLK 72 +#define IMX8QM_USB3_LPM_DIV 73 +#define IMX8QM_USB3_LPM_CLK 74 +#define IMX8QM_ENET0_AHB_CLK 75 +#define IMX8QM_ENET0_IPG_S_CLK 76 +#define IMX8QM_ENET0_IPG_CLK 77 +#define IMX8QM_ENET0_RGMII_DIV 78 +#define IMX8QM_ENET0_RGMII_TX_CLK 79 +#define IMX8QM_ENET0_ROOT_DIV 80 +#define IMX8QM_ENET0_TX_CLK 81 +#define IMX8QM_ENET0_ROOT_CLK 82 +#define IMX8QM_ENET0_PTP_CLK 83 +#define IMX8QM_ENET0_BYPASS_DIV 84 +#define IMX8QM_ENET1_AHB_CLK 85 +#define IMX8QM_ENET1_IPG_S_CLK 86 +#define IMX8QM_ENET1_IPG_CLK 87 +#define IMX8QM_ENET1_RGMII_DIV 88 +#define IMX8QM_ENET1_RGMII_TX_CLK 89 +#define IMX8QM_ENET1_ROOT_DIV 90 +#define IMX8QM_ENET1_TX_CLK 91 +#define IMX8QM_ENET1_ROOT_CLK 92 +#define IMX8QM_ENET1_PTP_CLK 93 +#define IMX8QM_ENET1_BYPASS_DIV 94 +#define IMX8QM_MLB_CLK 95 +#define IMX8QM_MLB_HCLK 96 +#define IMX8QM_MLB_IPG_CLK 97 +#define IMX8QM_EDMA_CLK 98 +#define IMX8QM_EDMA_IPG_CLK 99 + +/* DMA */ +#define IMX8QM_SPI0_IPG_CLK 100 +#define IMX8QM_SPI0_DIV 101 +#define IMX8QM_SPI0_CLK 102 +#define IMX8QM_SPI1_IPG_CLK 103 +#define IMX8QM_SPI1_DIV 104 +#define IMX8QM_SPI1_CLK 105 +#define IMX8QM_SPI2_IPG_CLK 106 +#define IMX8QM_SPI2_DIV 107 +#define IMX8QM_SPI2_CLK 108 +#define IMX8QM_SPI3_IPG_CLK 109 +#define IMX8QM_SPI3_DIV 110 +#define IMX8QM_SPI3_CLK 111 +#define IMX8QM_UART0_IPG_CLK 112 +#define IMX8QM_UART0_DIV 113 +#define IMX8QM_UART0_CLK 114 +#define IMX8QM_UART1_IPG_CLK 115 +#define IMX8QM_UART1_DIV 116 +#define IMX8QM_UART1_CLK 117 +#define IMX8QM_UART2_IPG_CLK 118 +#define IMX8QM_UART2_DIV 119 +#define IMX8QM_UART2_CLK 120 +#define IMX8QM_UART3_IPG_CLK 121 +#define IMX8QM_UART3_DIV 122 +#define IMX8QM_UART3_CLK 123 +#define IMX8QM_UART4_IPG_CLK 124 +#define IMX8QM_UART4_DIV 125 +#define IMX8QM_EMVSIM0_IPG_CLK 126 +#define IMX8QM_UART4_CLK 127 +#define IMX8QM_EMVSIM0_DIV 128 +#define IMX8QM_EMVSIM0_CLK 129 +#define IMX8QM_EMVSIM1_IPG_CLK 130 +#define IMX8QM_EMVSIM1_DIV 131 +#define IMX8QM_EMVSIM1_CLK 132 +#define IMX8QM_CAN0_IPG_CHI_CLK 133 +#define IMX8QM_CAN0_IPG_CLK 134 +#define IMX8QM_CAN0_DIV 135 +#define IMX8QM_CAN0_CLK 136 +#define IMX8QM_CAN1_IPG_CHI_CLK 137 +#define IMX8QM_CAN1_IPG_CLK 138 +#define IMX8QM_CAN1_DIV 139 +#define IMX8QM_CAN1_CLK 140 +#define IMX8QM_CAN2_IPG_CHI_CLK 141 +#define IMX8QM_CAN2_IPG_CLK 142 +#define IMX8QM_CAN2_DIV 143 +#define IMX8QM_CAN2_CLK 144 +#define IMX8QM_I2C0_IPG_CLK 145 +#define IMX8QM_I2C0_DIV 146 +#define IMX8QM_I2C0_CLK 147 +#define IMX8QM_I2C1_IPG_CLK 148 +#define IMX8QM_I2C1_DIV 149 +#define IMX8QM_I2C1_CLK 150 +#define IMX8QM_I2C2_IPG_CLK 151 +#define IMX8QM_I2C2_DIV 152 +#define IMX8QM_I2C2_CLK 153 +#define IMX8QM_I2C3_IPG_CLK 154 +#define IMX8QM_I2C3_DIV 155 +#define IMX8QM_I2C3_CLK 156 +#define IMX8QM_I2C4_IPG_CLK 157 +#define IMX8QM_I2C4_DIV 158 +#define IMX8QM_I2C4_CLK 159 +#define IMX8QM_FTM0_IPG_CLK 160 +#define IMX8QM_FTM0_DIV 161 +#define IMX8QM_FTM0_CLK 162 +#define IMX8QM_FTM1_IPG_CLK 163 +#define IMX8QM_FTM1_DIV 164 +#define IMX8QM_FTM1_CLK 165 +#define IMX8QM_ADC0_IPG_CLK 166 +#define IMX8QM_ADC0_DIV 167 +#define IMX8QM_ADC0_CLK 168 +#define IMX8QM_ADC1_IPG_CLK 169 +#define IMX8QM_ADC1_DIV 170 +#define IMX8QM_ADC1_CLK 171 + +/* Audio */ +#define IMX8QM_AUD_PLL0_DIV 172 +#define IMX8QM_AUD_PLL0 173 +#define IMX8QM_AUD_PLL1_DIV 174 +#define IMX8QM_AUD_PLL1 175 +#define IMX8QM_AUD_AMIX_IPG 182 +#define IMX8QM_AUD_ESAI_0_IPG 183 +#define IMX8QM_AUD_ESAI_1_IPG 184 +#define IMX8QM_AUD_ESAI_0_EXTAL_IPG 185 +#define IMX8QM_AUD_ESAI_1_EXTAL_IPG 186 +#define IMX8QM_AUD_SAI_0_IPG 187 +#define IMX8QM_AUD_SAI_0_IPG_S 188 +#define IMX8QM_AUD_SAI_0_MCLK 189 +#define IMX8QM_AUD_SAI_1_IPG 190 +#define IMX8QM_AUD_SAI_1_IPG_S 191 +#define IMX8QM_AUD_SAI_1_MCLK 192 +#define IMX8QM_AUD_SAI_2_IPG 193 +#define IMX8QM_AUD_SAI_2_IPG_S 194 +#define IMX8QM_AUD_SAI_2_MCLK 195 +#define IMX8QM_AUD_SAI_3_IPG 196 +#define IMX8QM_AUD_SAI_3_IPG_S 197 +#define IMX8QM_AUD_SAI_3_MCLK 198 +#define IMX8QM_AUD_SAI_6_IPG 199 +#define IMX8QM_AUD_SAI_6_IPG_S 200 +#define IMX8QM_AUD_SAI_6_MCLK 201 +#define IMX8QM_AUD_SAI_7_IPG 202 +#define IMX8QM_AUD_SAI_7_IPG_S 203 +#define IMX8QM_AUD_SAI_7_MCLK 204 +#define IMX8QM_AUD_SAI_HDMIRX0_IPG 205 +#define IMX8QM_AUD_SAI_HDMIRX0_IPG_S 206 +#define IMX8QM_AUD_SAI_HDMIRX0_MCLK 207 +#define IMX8QM_AUD_SAI_HDMITX0_IPG 208 +#define IMX8QM_AUD_SAI_HDMITX0_IPG_S 209 +#define IMX8QM_AUD_SAI_HDMITX0_MCLK 210 +#define IMX8QM_AUD_MQS_IPG 211 +#define IMX8QM_AUD_MQS_HMCLK 212 +#define IMX8QM_AUD_GPT5_IPG_S 213 +#define IMX8QM_AUD_GPT5_CLKIN 214 +#define IMX8QM_AUD_GPT5_24M_CLK 215 +#define IMX8QM_AUD_GPT6_IPG_S 216 +#define IMX8QM_AUD_GPT6_CLKIN 217 +#define IMX8QM_AUD_GPT6_24M_CLK 218 +#define IMX8QM_AUD_GPT7_IPG_S 219 +#define IMX8QM_AUD_GPT7_CLKIN 220 +#define IMX8QM_AUD_GPT7_24M_CLK 221 +#define IMX8QM_AUD_GPT8_IPG_S 222 +#define IMX8QM_AUD_GPT8_CLKIN 223 +#define IMX8QM_AUD_GPT8_24M_CLK 224 +#define IMX8QM_AUD_GPT9_IPG_S 225 +#define IMX8QM_AUD_GPT9_CLKIN 226 +#define IMX8QM_AUD_GPT9_24M_CLK 227 +#define IMX8QM_AUD_GPT10_IPG_S 228 +#define IMX8QM_AUD_GPT10_CLKIN 229 +#define IMX8QM_AUD_GPT10_24M_CLK 230 +#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV 232 +#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK 233 +#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV 234 +#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK 235 +#define IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV 236 +#define IMX8QM_AUD_ACM_AUD_REC_CLK0_CLK 237 +#define IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV 238 +#define IMX8QM_AUD_ACM_AUD_REC_CLK1_CLK 239 +#define IMX8QM_AUD_MCLKOUT0 240 +#define IMX8QM_AUD_MCLKOUT1 241 +#define IMX8QM_AUD_SPDIF_0_TX_CLK 242 +#define IMX8QM_AUD_SPDIF_0_GCLKW 243 +#define IMX8QM_AUD_SPDIF_0_IPG_S 244 +#define IMX8QM_AUD_SPDIF_1_TX_CLK 245 +#define IMX8QM_AUD_SPDIF_1_GCLKW 246 +#define IMX8QM_AUD_SPDIF_1_IPG_S 247 +#define IMX8QM_AUD_ASRC_0_IPG 248 +#define IMX8QM_AUD_ASRC_0_MEM 249 +#define IMX8QM_AUD_ASRC_1_IPG 250 +#define IMX8QM_AUD_ASRC_1_MEM 251 + +/* VPU */ +#define IMX8QM_VPU_CORE_DIV 252 +#define IMX8QM_VPU_CORE_CLK 253 +#define IMX8QM_VPU_UART_DIV 254 +#define IMX8QM_VPU_UART_CLK 255 +#define IMX8QM_VPU_DDR_DIV 256 +#define IMX8QM_VPU_DDR_CLK 257 +#define IMX8QM_VPU_SYS_DIV 258 +#define IMX8QM_VPU_SYS_CLK 259 +#define IMX8QM_VPU_XUVI_DIV 260 +#define IMX8QM_VPU_XUVI_CLK 261 + +/* GPU Clocks. */ +#define IMX8QM_GPU0_CORE_DIV 262 +#define IMX8QM_GPU0_CORE_CLK 263 +#define IMX8QM_GPU0_SHADER_DIV 264 +#define IMX8QM_GPU0_SHADER_CLK 265 +#define IMX8QM_GPU1_CORE_DIV 266 +#define IMX8QM_GPU1_CORE_CLK 267 +#define IMX8QM_GPU1_SHADER_DIV 268 +#define IMX8QM_GPU1_SHADER_CLK 269 + +/* MIPI CSI */ +#define IMX8QM_CSI0_IPG_CLK_S 270 +#define IMX8QM_CSI0_LIS_IPG_CLK 271 +#define IMX8QM_CSI0_APB_CLK 272 +#define IMX8QM_CSI0_I2C0_DIV 273 +#define IMX8QM_CSI0_I2C0_CLK 274 +#define IMX8QM_CSI0_PWM0_DIV 275 +#define IMX8QM_CSI0_PWM0_CLK 276 +#define IMX8QM_CSI0_CORE_DIV 277 +#define IMX8QM_CSI0_CORE_CLK 278 +#define IMX8QM_CSI0_ESC_DIV 279 +#define IMX8QM_CSI0_ESC_CLK 280 +#define IMX8QM_CSI1_IPG_CLK_S 281 +#define IMX8QM_CSI1_LIS_IPG_CLK 282 +#define IMX8QM_CSI1_APB_CLK 283 +#define IMX8QM_CSI1_I2C0_DIV 284 +#define IMX8QM_CSI1_I2C0_CLK 285 +#define IMX8QM_CSI1_PWM0_DIV 286 +#define IMX8QM_CSI1_PWM0_CLK 287 +#define IMX8QM_CSI1_CORE_DIV 288 +#define IMX8QM_CSI1_CORE_CLK 289 +#define IMX8QM_CSI1_ESC_DIV 290 +#define IMX8QM_CSI1_ESC_CLK 291 + +/* Display */ +#define IMX8QM_DC0_PLL0_DIV 292 +#define IMX8QM_DC0_PLL0_CLK 293 +#define IMX8QM_DC0_PLL1_DIV 294 +#define IMX8QM_DC0_PLL1_CLK 295 +#define IMX8QM_DC0_DISP0_DIV 296 +#define IMX8QM_DC0_DISP0_CLK 297 +#define IMX8QM_DC0_DISP1_DIV 298 +#define IMX8QM_DC0_DISP1_CLK 299 +#define IMX8QM_DC0_BYPASS_0_DIV 300 +#define IMX8QM_DC0_BYPASS_1_DIV 301 +#define IMX8QM_DC0_IRIS_AXI_CLK 302 +#define IMX8AM_DC0_IRIS_MVPL_CLK 303 +#define IMX8QM_DC0_DISP0_MSI_CLK 304 +#define IMX8QM_DC0_LIS_IPG_CLK 305 +#define IMX8QM_DC0_PXL_CMB_APB_CLK 306 +#define IMX8QM_DC0_PRG0_RTRAM_CLK 307 +#define IMX8QM_DC0_PRG1_RTRAM_CLK 308 +#define IMX8QM_DC0_PRG2_RTRAM_CLK 309 +#define IMX8QM_DC0_PRG3_RTRAM_CLK 310 +#define IMX8QM_DC0_PRG4_RTRAM_CLK 311 +#define IMX8QM_DC0_PRG5_RTRAM_CLK 312 +#define IMX8QM_DC0_PRG6_RTRAM_CLK 313 +#define IMX8QM_DC0_PRG7_RTRAM_CLK 314 +#define IMX8QM_DC0_PRG8_RTRAM_CLK 315 +#define IMX8QM_DC0_PRG0_APB_CLK 316 +#define IMX8QM_DC0_PRG1_APB_CLK 317 +#define IMX8QM_DC0_PRG2_APB_CLK 318 +#define IMX8QM_DC0_PRG3_APB_CLK 319 +#define IMX8QM_DC0_PRG4_APB_CLK 320 +#define IMX8QM_DC0_PRG5_APB_CLK 321 +#define IMX8QM_DC0_PRG6_APB_CLK 322 +#define IMX8QM_DC0_PRG7_APB_CLK 323 +#define IMX8QM_DC0_PRG8_APB_CLK 324 +#define IMX8QM_DC0_DPR0_APB_CLK 325 +#define IMX8QM_DC0_DPR1_APB_CLK 326 +#define IMX8QM_DC0_RTRAM0_CLK 327 +#define IMX8QM_DC0_RTRAM1_CLK 328 +#define IMX8QM_DC1_PLL0_DIV 329 +#define IMX8QM_DC1_PLL0_CLK 330 +#define IMX8QM_DC1_PLL1_DIV 331 +#define IMX8QM_DC1_PLL1_CLK 332 +#define IMX8QM_DC1_DISP0_DIV 333 +#define IMX8QM_DC1_DISP0_CLK 334 +#define IMX8QM_DC1_BYPASS_0_DIV 335 +#define IMX8QM_DC1_BYPASS_1_DIV 336 +#define IMX8QM_DC1_DISP1_DIV 337 +#define IMX8QM_DC1_DISP1_CLK 338 +#define IMX8QM_DC1_IRIS_AXI_CLK 339 +#define IMX8AM_DC1_IRIS_MVPL_CLK 340 +#define IMX8QM_DC1_DISP0_MSI_CLK 341 +#define IMX8QM_DC1_LIS_IPG_CLK 342 +#define IMX8QM_DC1_PXL_CMB_APB_CLK 343 +#define IMX8QM_DC1_PRG0_RTRAM_CLK 344 +#define IMX8QM_DC1_PRG1_RTRAM_CLK 345 +#define IMX8QM_DC1_PRG2_RTRAM_CLK 346 +#define IMX8QM_DC1_PRG3_RTRAM_CLK 347 +#define IMX8QM_DC1_PRG4_RTRAM_CLK 348 +#define IMX8QM_DC1_PRG5_RTRAM_CLK 349 +#define IMX8QM_DC1_PRG6_RTRAM_CLK 350 +#define IMX8QM_DC1_PRG7_RTRAM_CLK 351 +#define IMX8QM_DC1_PRG8_RTRAM_CLK 352 +#define IMX8QM_DC1_PRG0_APB_CLK 353 +#define IMX8QM_DC1_PRG1_APB_CLK 354 +#define IMX8QM_DC1_PRG2_APB_CLK 355 +#define IMX8QM_DC1_PRG3_APB_CLK 356 +#define IMX8QM_DC1_PRG4_APB_CLK 357 +#define IMX8QM_DC1_PRG5_APB_CLK 358 +#define IMX8QM_DC1_PRG6_APB_CLK 359 +#define IMX8QM_DC1_PRG7_APB_CLK 360 +#define IMX8QM_DC1_PRG8_APB_CLK 361 +#define IMX8QM_DC1_DPR0_APB_CLK 362 +#define IMX8QM_DC1_DPR1_APB_CLK 363 +#define IMX8QM_DC1_RTRAM0_CLK 364 +#define IMX8QM_DC1_RTRAM1_CLK 365 + +/* DRC */ +#define IMX8QM_DRC0_PLL0_DIV 366 +#define IMX8QM_DRC0_PLL0_CLK 367 +#define IMX8QM_DRC0_DIV 368 +#define IMX8QM_DRC0_CLK 369 +#define IMX8QM_DRC1_PLL0_DIV 370 +#define IMX8QM_DRC1_PLL0_CLK 371 +#define IMX8QM_DRC1_DIV 372 +#define IMX8QM_DRC1_CLK 373 + +/* HDMI */ +#define IMX8QM_HDMI_AV_PLL_DIV 374 +#define IMX8QM_HDMI_AV_PLL_CLK 375 +#define IMX8QM_HDMI_I2S_BYPASS_CLK 376 +#define IMX8QM_HDMI_I2C0_DIV 377 +#define IMX8QM_HDMI_I2C0_CLK 378 +#define IMX8QM_HDMI_PXL_DIV 379 +#define IMX8QM_HDMI_PXL_CLK 380 +#define IMX8QM_HDMI_PXL_LINK_DIV 381 +#define IMX8QM_HDMI_PXL_LINK_CLK 382 +#define IMX8QM_HDMI_PXL_MUX_DIV 383 +#define IMX8QM_HDMI_PXL_MUX_CLK 384 +#define IMX8QM_HDMI_I2S_DIV 385 +#define IMX8QM_HDMI_I2S_CLK 386 +#define IMX8QM_HDMI_HDP_CORE_DIV 387 +#define IMX8QM_HDMI_HDP_CORE_CLK 388 +#define IMX8QM_HDMI_I2C_IPG_S_CLK 389 +#define IMX8QM_HDMI_I2C_IPG_CLK 390 +#define IMX8QM_HDMI_PWM_IPG_S_CLK 391 +#define IMX8QM_HDMI_PWM_IPG_CLK 392 +#define IMX8QM_HDMI_PWM_32K_CLK 393 +#define IMX8QM_HDMI_GPIO_IPG_CLK 394 +#define IMX8QM_HDMI_PXL_LINK_SLV_ODD_CLK 395 +#define IMX8QM_HDMI_PXL_LINK_SLV_EVEN_CLK 396 +#define IMX8QM_HDMI_LIS_IPG_CLK 397 +#define IMX8QM_HDMI_MSI_HCLK 398 +#define IMX8QM_HDMI_PXL_EVEN_CLK 399 +#define IMX8QM_HDMI_HDP_CLK 400 +#define IMX8QM_HDMI_PXL_DBL_CLK 401 +#define IMX8QM_HDMI_APB_CLK 402 +#define IMX8QM_HDMI_PXL_LPCG_CLK 403 +#define IMX8QM_HDMI_HDP_PHY_CLK 404 +#define IMX8QM_HDMI_IPG_DIV 405 +#define IMX8QM_HDMI_VIF_CLK 406 +#define IMX8QM_HDMI_DIG_PLL_DIV 407 +#define IMX8QM_HDMI_DIG_PLL_CLK 408 +#define IMX8QM_HDMI_APB_MUX_CSR_CLK 409 +#define IMX8QM_HDMI_APB_MUX_CTRL_CLK 410 + +/* RX-HDMI */ +#define IMX8QM_HDMI_RX_I2S_BYPASS_CLK 411 +#define IMX8QM_HDMI_RX_BYPASS_CLK 412 +#define IMX8QM_HDMI_RX_SPDIF_BYPASS_CLK 413 +#define IMX8QM_HDMI_RX_I2C0_DIV 414 +#define IMX8QM_HDMI_RX_I2C0_CLK 415 +#define IMX8QM_HDMI_RX_SPDIF_DIV 416 +#define IMX8QM_HDMI_RX_SPDIF_CLK 417 +#define IMX8QM_HDMI_RX_HD_REF_DIV 418 +#define IMX8QM_HDMI_RX_HD_REF_CLK 419 +#define IMX8QM_HDMI_RX_HD_CORE_DIV 420 +#define IMX8QM_HDMI_RX_HD_CORE_CLK 421 +#define IMX8QM_HDMI_RX_PXL_DIV 422 +#define IMX8QM_HDMI_RX_PXL_CLK 423 +#define IMX8QM_HDMI_RX_I2S_DIV 424 +#define IMX8QM_HDMI_RX_I2S_CLK 425 +#define IMX8QM_HDMI_RX_PWM_DIV 426 +#define IMX8QM_HDMI_RX_PWM_CLK 427 + +/* LVDS */ +#define IMX8QM_LVDS0_BYPASS_CLK 428 +#define IMX8QM_LVDS0_PIXEL_DIV 429 +#define IMX8QM_LVDS0_PIXEL_CLK 430 +#define IMX8QM_LVDS0_PHY_DIV 431 +#define IMX8QM_LVDS0_PHY_CLK 432 +#define IMX8QM_LVDS0_I2C0_IPG_CLK 433 +#define IMX8QM_LVDS0_I2C0_DIV 434 +#define IMX8QM_LVDS0_I2C0_CLK 435 +#define IMX8QM_LVDS0_I2C1_IPG_CLK 436 +#define IMX8QM_LVDS0_I2C1_DIV 437 +#define IMX8QM_LVDS0_I2C1_CLK 438 +#define IMX8QM_LVDS0_PWM0_IPG_CLK 439 +#define IMX8QM_LVDS0_PWM0_DIV 440 +#define IMX8QM_LVDS0_PWM0_CLK 441 +#define IMX8QM_LVDS0_GPIO_IPG_CLK 444 +#define IMX8QM_LVDS1_BYPASS_DIV 445 +#define IMX8QM_LVDS1_BYPASS_CLK 446 +#define IMX8QM_LVDS1_PIXEL_DIV 447 +#define IMX8QM_LVDS1_PIXEL_CLK 448 +#define IMX8QM_LVDS1_PHY_DIV 449 +#define IMX8QM_LVDS1_PHY_CLK 450 +#define IMX8QM_LVDS1_I2C0_IPG_CLK 451 +#define IMX8QM_LVDS1_I2C0_DIV 452 +#define IMX8QM_LVDS1_I2C0_CLK 453 +#define IMX8QM_LVDS1_I2C1_IPG_CLK 454 +#define IMX8QM_LVDS1_I2C1_DIV 455 +#define IMX8QM_LVDS1_I2C1_CLK 456 +#define IMX8QM_LVDS1_PWM0_IPG_CLK 457 +#define IMX8QM_LVDS1_PWM0_DIV 458 +#define IMX8QM_LVDS1_PWM0_CLK 459 +#define IMX8QM_LVDS1_GPIO_IPG_CLK 462 + +/* MIPI */ +#define IMX8QM_MIPI0_BYPASS_CLK 465 +#define IMX8QM_MIPI0_I2C0_DIV 466 +#define IMX8QM_MIPI0_I2C0_CLK 467 +#define IMX8QM_MIPI0_I2C1_DIV 468 +#define IMX8QM_MIPI0_I2C1_CLK 469 +#define IMX8QM_MIPI0_PWM0_DIV 470 +#define IMX8QM_MIPI0_PWM0_CLK 471 +#define IMX8QM_MIPI0_DSI_TX_ESC_DIV 472 +#define IMX8QM_MIPI0_DSI_TX_ESC_CLK 473 +#define IMX8QM_MIPI0_DSI_RX_ESC_DIV 474 +#define IMX8QM_MIPI0_DSI_RX_ESC_CLK 475 +#define IMX8QM_MIPI0_PXL_DIV 476 +#define IMX8QM_MIPI0_PXL_CLK 477 +#define IMX8QM_MIPI1_BYPASS_CLK 479 +#define IMX8QM_MIPI1_I2C0_DIV 480 +#define IMX8QM_MIPI1_I2C0_CLK 481 +#define IMX8QM_MIPI1_I2C1_DIV 482 +#define IMX8QM_MIPI1_I2C1_CLK 483 +#define IMX8QM_MIPI1_PWM0_DIV 484 +#define IMX8QM_MIPI1_PWM0_CLK 485 +#define IMX8QM_MIPI1_DSI_TX_ESC_DIV 486 +#define IMX8QM_MIPI1_DSI_TX_ESC_CLK 487 +#define IMX8QM_MIPI1_DSI_RX_ESC_DIV 488 +#define IMX8QM_MIPI1_DSI_RX_ESC_CLK 489 +#define IMX8QM_MIPI1_PXL_DIV 490 +#define IMX8QM_MIPI1_PXL_CLK 491 + +/* Imaging */ +#define IMX8QM_IMG_JPEG_ENC_IPG_CLK 492 +#define IMX8QM_IMG_JPEG_ENC_CLK 493 +#define IMX8QM_IMG_JPEG_DEC_IPG_CLK 494 +#define IMX8QM_IMG_JPEG_DEC_CLK 495 +#define IMX8QM_IMG_PXL_LINK_DC0_CLK 496 +#define IMX8QM_IMG_PXL_LINK_DC1_CLK 497 +#define IMX8QM_IMG_PXL_LINK_CSI0_CLK 498 +#define IMX8QM_IMG_PXL_LINK_CSI1_CLK 499 +#define IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK 500 +#define IMX8QM_IMG_PDMA_0_CLK 501 +#define IMX8QM_IMG_PDMA_1_CLK 502 +#define IMX8QM_IMG_PDMA_2_CLK 503 +#define IMX8QM_IMG_PDMA_3_CLK 504 +#define IMX8QM_IMG_PDMA_4_CLK 505 +#define IMX8QM_IMG_PDMA_5_CLK 506 +#define IMX8QM_IMG_PDMA_6_CLK 507 +#define IMX8QM_IMG_PDMA_7_CLK 508 + +/* HSIO */ +#define IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK 509 +#define IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK 510 +#define IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK 511 +#define IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK 512 +#define IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK 513 +#define IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK 514 +#define IMX8QM_HSIO_PCIE_X1_PER_CLK 515 +#define IMX8QM_HSIO_PCIE_X2_PER_CLK 516 +#define IMX8QM_HSIO_SATA_PER_CLK 517 +#define IMX8QM_HSIO_PHY_X1_PER_CLK 518 +#define IMX8QM_HSIO_PHY_X2_PER_CLK 519 +#define IMX8QM_HSIO_MISC_PER_CLK 520 +#define IMX8QM_HSIO_PHY_X1_APB_CLK 521 +#define IMX8QM_HSIO_PHY_X2_APB_0_CLK 522 +#define IMX8QM_HSIO_PHY_X2_APB_1_CLK 523 +#define IMX8QM_HSIO_SATA_CLK 524 +#define IMX8QM_HSIO_GPIO_CLK 525 +#define IMX8QM_HSIO_PHY_X1_PCLK 526 +#define IMX8QM_HSIO_PHY_X2_PCLK_0 527 +#define IMX8QM_HSIO_PHY_X2_PCLK_1 528 +#define IMX8QM_HSIO_SATA_EPCS_RX_CLK 529 +#define IMX8QM_HSIO_SATA_EPCS_TX_CLK 530 + +/* M4 */ +#define IMX8QM_M4_0_CORE_DIV 531 +#define IMX8QM_M4_0_CORE_CLK 532 +#define IMX8QM_M4_0_I2C_DIV 533 +#define IMX8QM_M4_0_I2C_CLK 534 +#define IMX8QM_M4_0_PIT_DIV 535 +#define IMX8QM_M4_0_PIT_CLK 536 +#define IMX8QM_M4_0_TPM_DIV 537 +#define IMX8QM_M4_0_TPM_CLK 538 +#define IMX8QM_M4_0_UART_DIV 539 +#define IMX8QM_M4_0_UART_CLK 540 +#define IMX8QM_M4_0_WDOG_DIV 541 +#define IMX8QM_M4_0_WDOG_CLK 542 +#define IMX8QM_M4_1_CORE_DIV 543 +#define IMX8QM_M4_1_CORE_CLK 544 +#define IMX8QM_M4_1_I2C_DIV 545 +#define IMX8QM_M4_1_I2C_CLK 546 +#define IMX8QM_M4_1_PIT_DIV 547 +#define IMX8QM_M4_1_PIT_CLK 548 +#define IMX8QM_M4_1_TPM_DIV 549 +#define IMX8QM_M4_1_TPM_CLK 550 +#define IMX8QM_M4_1_UART_DIV 551 +#define IMX8QM_M4_1_UART_CLK 552 +#define IMX8QM_M4_1_WDOG_DIV 553 +#define IMX8QM_M4_1_WDOG_CLK 554 + +/* IPG clocks */ +#define IMX8QM_24MHZ 555 +#define IMX8QM_GPT_3M 556 +#define IMX8QM_IPG_DMA_CLK_ROOT 557 +#define IMX8QM_IPG_AUD_CLK_ROOT 558 +#define IMX8QM_IPG_CONN_CLK_ROOT 559 +#define IMX8QM_AHB_CONN_CLK_ROOT 560 +#define IMX8QM_AXI_CONN_CLK_ROOT 561 +#define IMX8QM_IPG_MIPI_CSI_CLK_ROOT 562 +#define IMX8QM_DC_AXI_EXT_CLK 563 +#define IMX8QM_DC_AXI_INT_CLK 564 +#define IMX8QM_DC_CFG_CLK 565 +#define IMX8QM_HDMI_IPG_CLK 566 +#define IMX8QM_LVDS_IPG_CLK 567 +#define IMX8QM_IMG_AXI_CLK 568 +#define IMX8QM_IMG_IPG_CLK 569 +#define IMX8QM_IMG_PXL_CLK 570 +#define IMX8QM_CSI0_I2C0_IPG_CLK 571 +#define IMX8QM_CSI0_PWM0_IPG_CLK 572 +#define IMX8QM_CSI1_I2C0_IPG_CLK 573 +#define IMX8QM_CSI1_PWM0_IPG_CLK 574 +#define IMX8QM_DC0_DPR0_B_CLK 575 +#define IMX8QM_DC0_DPR1_B_CLK 576 +#define IMX8QM_DC1_DPR0_B_CLK 577 +#define IMX8QM_DC1_DPR1_B_CLK 578 +#define IMX8QM_32KHZ 579 +#define IMX8QM_HSIO_AXI_CLK 580 +#define IMX8QM_HSIO_PER_CLK 581 +#define IMX8QM_HDMI_RX_GPIO_IPG_S_CLK 582 +#define IMX8QM_HDMI_RX_PWM_IPG_S_CLK 583 +#define IMX8QM_HDMI_RX_PWM_IPG_CLK 584 +#define IMX8QM_HDMI_RX_I2C_DIV_CLK 585 +#define IMX8QM_HDMI_RX_I2C_IPG_S_CLK 586 +#define IMX8QM_HDMI_RX_I2C_IPG_CLK 587 +#define IMX8QM_HDMI_RX_SINK_PCLK 588 +#define IMX8QM_HDMI_RX_SINK_SCLK 589 +#define IMX8QM_HDMI_RX_PXL_ENC_CLK 590 +#define IMX8QM_HDMI_RX_IPG_CLK 591 + +/* ACM */ +#define IMX8QM_HDMI_RX_MCLK 592 +#define IMX8QM_EXT_AUD_MCLK0 593 +#define IMX8QM_EXT_AUD_MCLK1 594 +#define IMX8QM_ESAI0_RX_CLK 595 +#define IMX8QM_ESAI0_RX_HF_CLK 596 +#define IMX8QM_ESAI0_TX_CLK 597 +#define IMX8QM_ESAI0_TX_HF_CLK 598 +#define IMX8QM_ESAI1_RX_CLK 599 +#define IMX8QM_ESAI1_RX_HF_CLK 600 +#define IMX8QM_ESAI1_TX_CLK 601 +#define IMX8QM_ESAI1_TX_HF_CLK 602 +#define IMX8QM_SPDIF0_RX 603 +#define IMX8QM_SPDIF1_RX 604 +#define IMX8QM_SAI0_RX_BCLK 605 +#define IMX8QM_SAI0_TX_BCLK 606 +#define IMX8QM_SAI1_RX_BCLK 607 +#define IMX8QM_SAI1_TX_BCLK 608 +#define IMX8QM_SAI2_RX_BCLK 609 +#define IMX8QM_SAI3_RX_BCLK 610 +#define IMX8QM_HDMI_RX_SAI0_RX_BCLK 611 +#define IMX8QM_SAI6_RX_BCLK 612 +#define IMX8QM_HDMI_TX_SAI0_TX_BCLK 613 + +#define IMX8QM_ACM_AUD_CLK0_SEL 614 +#define IMX8QM_ACM_AUD_CLK0_CLK 615 +#define IMX8QM_ACM_AUD_CLK1_SEL 616 +#define IMX8QM_ACM_AUD_CLK1_CLK 617 +#define IMX8QM_ACM_MCLKOUT0_SEL 618 +#define IMX8QM_ACM_MCLKOUT0_CLK 619 +#define IMX8QM_ACM_MCLKOUT1_SEL 620 +#define IMX8QM_ACM_MCLKOUT1_CLK 621 +#define IMX8QM_ACM_ASRC0_MUX_CLK_SEL 622 +#define IMX8QM_ACM_ASRC0_MUX_CLK_CLK 623 +#define IMX8QM_ACM_ASRC1_MUX_CLK_SEL 624 +#define IMX8QM_ACM_ASRC1_MUX_CLK_CLK 625 +#define IMX8QM_ACM_ESAI0_MCLK_SEL 626 +#define IMX8QM_ACM_ESAI0_MCLK_CLK 627 +#define IMX8QM_ACM_ESAI1_MCLK_SEL 628 +#define IMX8QM_ACM_ESAI1_MCLK_CLK 629 +#define IMX8QM_ACM_GPT0_MUX_CLK_SEL 630 +#define IMX8QM_ACM_GPT0_MUX_CLK_CLK 631 +#define IMX8QM_ACM_GPT1_MUX_CLK_SEL 632 +#define IMX8QM_ACM_GPT1_MUX_CLK_CLK 633 +#define IMX8QM_ACM_GPT2_MUX_CLK_SEL 634 +#define IMX8QM_ACM_GPT2_MUX_CLK_CLK 635 +#define IMX8QM_ACM_GPT3_MUX_CLK_SEL 636 +#define IMX8QM_ACM_GPT3_MUX_CLK_CLK 637 +#define IMX8QM_ACM_GPT4_MUX_CLK_SEL 638 +#define IMX8QM_ACM_GPT4_MUX_CLK_CLK 639 +#define IMX8QM_ACM_GPT5_MUX_CLK_SEL 640 +#define IMX8QM_ACM_GPT5_MUX_CLK_CLK 641 +#define IMX8QM_ACM_SAI0_MCLK_SEL 642 +#define IMX8QM_ACM_SAI0_MCLK_CLK 643 +#define IMX8QM_ACM_SAI1_MCLK_SEL 644 +#define IMX8QM_ACM_SAI1_MCLK_CLK 645 +#define IMX8QM_ACM_SAI2_MCLK_SEL 646 +#define IMX8QM_ACM_SAI2_MCLK_CLK 647 +#define IMX8QM_ACM_SAI3_MCLK_SEL 648 +#define IMX8QM_ACM_SAI3_MCLK_CLK 649 +#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_SEL 650 +#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_CLK 651 +#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL 652 +#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_CLK 653 +#define IMX8QM_ACM_SAI6_MCLK_SEL 654 +#define IMX8QM_ACM_SAI6_MCLK_CLK 655 +#define IMX8QM_ACM_SAI7_MCLK_SEL 656 +#define IMX8QM_ACM_SAI7_MCLK_CLK 657 +#define IMX8QM_ACM_SPDIF0_TX_CLK_SEL 658 +#define IMX8QM_ACM_SPDIF0_TX_CLK_CLK 659 +#define IMX8QM_ACM_SPDIF1_TX_CLK_SEL 660 +#define IMX8QM_ACM_SPDIF1_TX_CLK_CLK 661 +#define IMX8QM_ACM_MQS_TX_CLK_SEL 662 +#define IMX8QM_ACM_MQS_TX_CLK_CLK 663 + +#define IMX8QM_ENET0_REF_25MHZ_125MHZ_SEL 664 +#define IMX8QM_ENET0_REF_25MHZ_125MHZ_CLK 665 +#define IMX8QM_ENET1_REF_25MHZ_125MHZ_SEL 666 +#define IMX8QM_ENET1_REF_25MHZ_125MHZ_CLK 667 +#define IMX8QM_ENET0_REF_50MHZ_CLK 668 +#define IMX8QM_ENET1_REF_50MHZ_CLK 669 +#define IMX8QM_ENET_25MHZ_CLK 670 +#define IMX8QM_ENET_125MHZ_CLK 671 +#define IMX8QM_ENET0_REF_DIV 672 +#define IMX8QM_ENET0_REF_CLK 673 +#define IMX8QM_ENET1_REF_DIV 674 +#define IMX8QM_ENET1_REF_CLK 675 +#define IMX8QM_ENET0_RMII_TX_CLK 676 +#define IMX8QM_ENET1_RMII_TX_CLK 677 +#define IMX8QM_ENET0_RMII_TX_SEL 678 +#define IMX8QM_ENET1_RMII_TX_SEL 679 +#define IMX8QM_ENET0_RMII_RX_CLK 680 +#define IMX8QM_ENET1_RMII_RX_CLK 681 + +#define IMX8QM_KPP_CLK 683 +#define IMX8QM_GPT0_HF_CLK 684 +#define IMX8QM_GPT0_IPG_S_CLK 685 +#define IMX8QM_GPT0_IPG_SLV_CLK 686 +#define IMX8QM_GPT0_IPG_MSTR_CLK 687 +#define IMX8QM_GPT1_HF_CLK 688 +#define IMX8QM_GPT1_IPG_S_CLK 689 +#define IMX8QM_GPT1_IPG_SLV_CLK 690 +#define IMX8QM_GPT1_IPG_MSTR_CLK 691 +#define IMX8QM_GPT2_HF_CLK 692 +#define IMX8QM_GPT2_IPG_S_CLK 693 +#define IMX8QM_GPT2_IPG_SLV_CLK 694 +#define IMX8QM_GPT2_IPG_MSTR_CLK 695 +#define IMX8QM_GPT3_HF_CLK 696 +#define IMX8QM_GPT3_IPG_S_CLK 697 +#define IMX8QM_GPT3_IPG_SLV_CLK 698 +#define IMX8QM_GPT3_IPG_MSTR_CLK 699 +#define IMX8QM_GPT4_HF_CLK 700 +#define IMX8QM_GPT4_IPG_S_CLK 701 +#define IMX8QM_GPT4_IPG_SLV_CLK 702 +#define IMX8QM_GPT4_IPG_MSTR_CLK 703 +#define IMX8QM_PWM0_HF_CLK 704 +#define IMX8QM_PWM0_IPG_S_CLK 705 +#define IMX8QM_PWM0_IPG_SLV_CLK 706 +#define IMX8QM_PWM0_IPG_MSTR_CLK 707 +#define IMX8QM_PWM1_HF_CLK 708 +#define IMX8QM_PWM1_IPG_S_CLK 709 +#define IMX8QM_PWM1_IPG_SLV_CLK 710 +#define IMX8QM_PWM1_IPG_MSTR_CLK 711 +#define IMX8QM_PWM2_HF_CLK 712 +#define IMX8QM_PWM2_IPG_S_CLK 713 +#define IMX8QM_PWM2_IPG_SLV_CLK 714 +#define IMX8QM_PWM2_IPG_MSTR_CLK 715 +#define IMX8QM_PWM3_HF_CLK 716 +#define IMX8QM_PWM3_IPG_S_CLK 717 +#define IMX8QM_PWM3_IPG_SLV_CLK 718 +#define IMX8QM_PWM3_IPG_MSTR_CLK 719 +#define IMX8QM_PWM4_HF_CLK 720 +#define IMX8QM_PWM4_IPG_S_CLK 721 +#define IMX8QM_PWM4_IPG_SLV_CLK 722 +#define IMX8QM_PWM4_IPG_MSTR_CLK 723 +#define IMX8QM_PWM5_HF_CLK 724 +#define IMX8QM_PWM5_IPG_S_CLK 725 +#define IMX8QM_PWM5_IPG_SLV_CLK 726 +#define IMX8QM_PWM5_IPG_MSTR_CLK 727 +#define IMX8QM_PWM6_HF_CLK 728 +#define IMX8QM_PWM6_IPG_S_CLK 729 +#define IMX8QM_PWM6_IPG_SLV_CLK 730 +#define IMX8QM_PWM6_IPG_MSTR_CLK 731 +#define IMX8QM_PWM7_HF_CLK 732 +#define IMX8QM_PWM7_IPG_S_CLK 733 +#define IMX8QM_PWM7_IPG_SLV_CLK 734 +#define IMX8QM_PWM7_IPG_MSTR_CLK 735 +#define IMX8QM_FSPI0_HCLK 736 +#define IMX8QM_FSPI0_IPG_CLK 737 +#define IMX8QM_FSPI0_IPG_S_CLK 738 +#define IMX8QM_FSPI1_HCLK 736 +#define IMX8QM_FSPI1_IPG_CLK 737 +#define IMX8QM_FSPI1_IPG_S_CLK 738 +#define IMX8QM_GPIO0_IPG_S_CLK 739 +#define IMX8QM_GPIO1_IPG_S_CLK 740 +#define IMX8QM_GPIO2_IPG_S_CLK 741 +#define IMX8QM_GPIO3_IPG_S_CLK 742 +#define IMX8QM_GPIO4_IPG_S_CLK 743 +#define IMX8QM_GPIO5_IPG_S_CLK 744 +#define IMX8QM_GPIO6_IPG_S_CLK 745 +#define IMX8QM_GPIO7_IPG_S_CLK 746 +#define IMX8QM_ROMCP_CLK 747 +#define IMX8QM_ROMCP_REG_CLK 748 +#define IMX8QM_96KROM_CLK 749 +#define IMX8QM_OCRAM_MEM_CLK 750 +#define IMX8QM_OCRAM_CTRL_CLK 751 +#define IMX8QM_LSIO_BUS_CLK 752 +#define IMX8QM_LSIO_MEM_CLK 753 +#define IMX8QM_LVDS0_LIS_IPG_CLK 754 +#define IMX8QM_LVDS1_LIS_IPG_CLK 755 +#define IMX8QM_MIPI0_LIS_IPG_CLK 756 +#define IMX8QM_MIPI0_I2C0_IPG_S_CLK 757 +#define IMX8QM_MIPI0_I2C0_IPG_CLK 758 +#define IMX8QM_MIPI0_I2C1_IPG_S_CLK 759 +#define IMX8QM_MIPI0_I2C1_IPG_CLK 760 +#define IMX8QM_MIPI0_CLK_ROOT 761 +#define IMX8QM_MIPI1_LIS_IPG_CLK 762 +#define IMX8QM_MIPI1_I2C0_IPG_S_CLK 763 +#define IMX8QM_MIPI1_I2C0_IPG_CLK 764 +#define IMX8QM_MIPI1_I2C1_IPG_S_CLK 765 +#define IMX8QM_MIPI1_I2C1_IPG_CLK 766 +#define IMX8QM_MIPI1_CLK_ROOT 767 +#define IMX8QM_DC0_DISP0_SEL 768 +#define IMX8QM_DC0_DISP1_SEL 769 +#define IMX8QM_DC1_DISP0_SEL 770 +#define IMX8QM_DC1_DISP1_SEL 771 + +/* CM40 */ +#define IMX8QM_CM40_IPG_CLK 772 +#define IMX8QM_CM40_I2C_DIV 773 +#define IMX8QM_CM40_I2C_CLK 774 +#define IMX8QM_CM40_I2C_IPG_CLK 775 + +/* CM41 */ +#define IMX8QM_CM41_IPG_CLK 776 +#define IMX8QM_CM41_I2C_DIV 777 +#define IMX8QM_CM41_I2C_CLK 778 +#define IMX8QM_CM41_I2C_IPG_CLK 779 + +#define IMX8QM_HDMI_PXL_SEL 780 +#define IMX8QM_HDMI_PXL_LINK_SEL 781 +#define IMX8QM_HDMI_PXL_MUX_SEL 782 +#define IMX8QM_HDMI_AV_PLL_BYPASS_CLK 783 + +#define IMX8QM_HDMI_RX_PXL_SEL 784 +#define IMX8QM_HDMI_RX_HD_REF_SEL 785 +#define IMX8QM_HDMI_RX_HD_CORE_SEL 786 +#define IMX8QM_HDMI_RX_DIG_PLL_CLK 787 + +#define IMX8QM_LSIO_MU5A_IPG_S_CLK 788 +#define IMX8QM_LSIO_MU5A_IPG_CLK 789 +#define IMX8QM_LSIO_MU6A_IPG_S_CLK 790 +#define IMX8QM_LSIO_MU6A_IPG_CLK 791 + +/* DSP */ +#define IMX8QM_AUD_DSP_ADB_ACLK 792 +#define IMX8QM_AUD_DSP_IPG 793 +#define IMX8QM_AUD_DSP_CORE_CLK 794 +#define IMX8QM_AUD_OCRAM_IPG 795 + +#define IMX8QM_CLK_END 796 + +#endif /* __DT_BINDINGS_CLOCK_IMX8QM_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/imx8qxp-clock.h b/roms/u-boot/include/dt-bindings/clock/imx8qxp-clock.h new file mode 100644 index 000000000..d0334ea39 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/imx8qxp-clock.h @@ -0,0 +1,583 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H +#define __DT_BINDINGS_CLOCK_IMX8QXP_H + +#define IMX8QXP_CLK_DUMMY 0 + +#define IMX8QXP_UART0_IPG_CLK 1 +#define IMX8QXP_UART0_DIV 2 +#define IMX8QXP_UART0_CLK 3 + +#define IMX8QXP_IPG_DMA_CLK_ROOT 4 + +/* GPU Clocks. */ +#define IMX8QXP_GPU0_CORE_DIV 5 +#define IMX8QXP_GPU0_CORE_CLK 6 +#define IMX8QXP_GPU0_SHADER_DIV 7 +#define IMX8QXP_GPU0_SHADER_CLK 8 + +#define IMX8QXP_24MHZ 9 +#define IMX8QXP_GPT_3M 10 +#define IMX8QXP_32KHZ 11 + +/* LSIO SS */ +#define IMX8QXP_LSIO_MEM_CLK 12 +#define IMX8QXP_LSIO_BUS_CLK 13 +#define IMX8QXP_LSIO_PWM0_DIV 14 +#define IMX8QXP_LSIO_PWM0_IPG_S_CLK 15 +#define IMX8QXP_LSIO_PWM0_IPG_SLV_CLK 16 +#define IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK 17 +#define IMX8QXP_LSIO_PWM0_HF_CLK 18 +#define IMX8QXP_LSIO_PWM0_CLK 19 +#define IMX8QXP_LSIO_PWM1_DIV 20 +#define IMX8QXP_LSIO_PWM1_IPG_S_CLK 21 +#define IMX8QXP_LSIO_PWM1_IPG_SLV_CLK 22 +#define IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK 23 +#define IMX8QXP_LSIO_PWM1_HF_CLK 24 +#define IMX8QXP_LSIO_PWM1_CLK 25 +#define IMX8QXP_LSIO_PWM2_DIV 26 +#define IMX8QXP_LSIO_PWM2_IPG_S_CLK 27 +#define IMX8QXP_LSIO_PWM2_IPG_SLV_CLK 28 +#define IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK 29 +#define IMX8QXP_LSIO_PWM2_HF_CLK 30 +#define IMX8QXP_LSIO_PWM2_CLK 31 +#define IMX8QXP_LSIO_PWM3_DIV 32 +#define IMX8QXP_LSIO_PWM3_IPG_S_CLK 33 +#define IMX8QXP_LSIO_PWM3_IPG_SLV_CLK 34 +#define IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK 35 +#define IMX8QXP_LSIO_PWM3_HF_CLK 36 +#define IMX8QXP_LSIO_PWM3_CLK 37 +#define IMX8QXP_LSIO_PWM4_DIV 38 +#define IMX8QXP_LSIO_PWM4_IPG_S_CLK 39 +#define IMX8QXP_LSIO_PWM4_IPG_SLV_CLK 40 +#define IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK 42 +#define IMX8QXP_LSIO_PWM4_HF_CLK 43 +#define IMX8QXP_LSIO_PWM4_CLK 44 +#define IMX8QXP_LSIO_PWM5_DIV 45 +#define IMX8QXP_LSIO_PWM5_IPG_S_CLK 46 +#define IMX8QXP_LSIO_PWM5_IPG_SLV_CLK 47 +#define IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK 48 +#define IMX8QXP_LSIO_PWM5_HF_CLK 49 +#define IMX8QXP_LSIO_PWM5_CLK 50 +#define IMX8QXP_LSIO_PWM6_DIV 51 +#define IMX8QXP_LSIO_PWM6_IPG_S_CLK 52 +#define IMX8QXP_LSIO_PWM6_IPG_SLV_CLK 53 +#define IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK 54 +#define IMX8QXP_LSIO_PWM6_HF_CLK 55 +#define IMX8QXP_LSIO_PWM6_CLK 56 +#define IMX8QXP_LSIO_PWM7_DIV 57 +#define IMX8QXP_LSIO_PWM7_IPG_S_CLK 58 +#define IMX8QXP_LSIO_PWM7_IPG_SLV_CLK 59 +#define IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK 60 +#define IMX8QXP_LSIO_PWM7_HF_CLK 61 +#define IMX8QXP_LSIO_PWM7_CLK 62 +#define IMX8QXP_LSIO_GPT0_DIV 63 +#define IMX8QXP_LSIO_GPT0_IPG_S_CLK 64 +#define IMX8QXP_LSIO_GPT0_IPG_SLV_CLK 65 +#define IMX8QXP_LSIO_GPT0_IPG_MSTR_CLK 66 +#define IMX8QXP_LSIO_GPT0_HF_CLK 67 +#define IMX8QXP_LSIO_GPT0_CLK 68 +#define IMX8QXP_LSIO_GPT1_DIV 69 +#define IMX8QXP_LSIO_GPT1_IPG_S_CLK 70 +#define IMX8QXP_LSIO_GPT1_IPG_SLV_CLK 71 +#define IMX8QXP_LSIO_GPT1_IPG_MSTR_CLK 72 +#define IMX8QXP_LSIO_GPT1_HF_CLK 73 +#define IMX8QXP_LSIO_GPT1_CLK 74 +#define IMX8QXP_LSIO_GPT2_DIV 75 +#define IMX8QXP_LSIO_GPT2_IPG_S_CLK 76 +#define IMX8QXP_LSIO_GPT2_IPG_SLV_CLK 77 +#define IMX8QXP_LSIO_GPT2_IPG_MSTR_CLK 78 +#define IMX8QXP_LSIO_GPT2_HF_CLK 79 +#define IMX8QXP_LSIO_GPT2_CLK 80 +#define IMX8QXP_LSIO_GPT3_DIV 81 +#define IMX8QXP_LSIO_GPT3_IPG_S_CLK 82 +#define IMX8QXP_LSIO_GPT3_IPG_SLV_CLK 83 +#define IMX8QXP_LSIO_GPT3_IPG_MSTR_CLK 84 +#define IMX8QXP_LSIO_GPT3_HF_CLK 85 +#define IMX8QXP_LSIO_GPT3_CLK 86 +#define IMX8QXP_LSIO_GPT4_DIV 87 +#define IMX8QXP_LSIO_GPT4_IPG_S_CLK 88 +#define IMX8QXP_LSIO_GPT4_IPG_SLV_CLK 89 +#define IMX8QXP_LSIO_GPT4_IPG_MSTR_CLK 90 +#define IMX8QXP_LSIO_GPT4_HF_CLK 91 +#define IMX8QXP_LSIO_GPT4_CLK 92 +#define IMX8QXP_LSIO_FSPI0_DIV 93 +#define IMX8QXP_LSIO_FSPI0_HCLK 94 +#define IMX8QXP_LSIO_FSPI0_IPG_S_CLK 95 +#define IMX8QXP_LSIO_FSPI0_IPG_CLK 96 +#define IMX8QXP_LSIO_FSPI0_CLK 97 +#define IMX8QXP_LSIO_FSPI1_DIV 98 +#define IMX8QXP_LSIO_FSPI1_HCLK 99 +#define IMX8QXP_LSIO_FSPI1_IPG_S_CLK 100 +#define IMX8QXP_LSIO_FSPI1_IPG_CLK 101 +#define IMX8QXP_LSIO_FSPI1_CLK 102 +#define IMX8QXP_LSIO_GPIO0_IPG_S_CLK 103 +#define IMX8QXP_LSIO_GPIO1_IPG_S_CLK 104 +#define IMX8QXP_LSIO_GPIO2_IPG_S_CLK 105 +#define IMX8QXP_LSIO_GPIO3_IPG_S_CLK 106 +#define IMX8QXP_LSIO_GPIO4_IPG_S_CLK 107 +#define IMX8QXP_LSIO_GPIO5_IPG_S_CLK 108 +#define IMX8QXP_LSIO_GPIO6_IPG_S_CLK 109 +#define IMX8QXP_LSIO_GPIO7_IPG_S_CLK 110 +#define IMX8QXP_LSIO_ROMCP_REG_CLK 111 +#define IMX8QXP_LSIO_ROMCP_CLK 112 +#define IMX8QXP_LSIO_96KROM_CLK 113 +#define IMX8QXP_LSIO_OCRAM_MEM_CLK 114 +#define IMX8QXP_LSIO_OCRAM_CTRL_CLK 115 + +/* ADMA SS */ +#define IMX8QXP_UART1_IPG_CLK 116 +#define IMX8QXP_UART2_IPG_CLK 117 +#define IMX8QXP_UART3_IPG_CLK 118 +#define IMX8QXP_UART1_DIV 119 +#define IMX8QXP_UART2_DIV 120 +#define IMX8QXP_UART3_DIV 121 +#define IMX8QXP_UART1_CLK 122 +#define IMX8QXP_UART2_CLK 123 +#define IMX8QXP_UART3_CLK 124 +#define IMX8QXP_SPI0_IPG_CLK 125 +#define IMX8QXP_SPI1_IPG_CLK 126 +#define IMX8QXP_SPI2_IPG_CLK 127 +#define IMX8QXP_SPI3_IPG_CLK 128 +#define IMX8QXP_SPI0_DIV 129 +#define IMX8QXP_SPI1_DIV 130 +#define IMX8QXP_SPI2_DIV 131 +#define IMX8QXP_SPI3_DIV 132 +#define IMX8QXP_SPI0_CLK 133 +#define IMX8QXP_SPI1_CLK 134 +#define IMX8QXP_SPI2_CLK 135 +#define IMX8QXP_SPI3_CLK 136 +#define IMX8QXP_CAN0_IPG_CHI_CLK 137 +#define IMX8QXP_CAN1_IPG_CHI_CLK 138 +#define IMX8QXP_CAN2_IPG_CHI_CLK 139 +#define IMX8QXP_CAN0_IPG_CLK 140 +#define IMX8QXP_CAN1_IPG_CLK 141 +#define IMX8QXP_CAN2_IPG_CLK 142 +#define IMX8QXP_CAN0_DIV 143 +#define IMX8QXP_CAN1_DIV 144 +#define IMX8QXP_CAN2_DIV 145 +#define IMX8QXP_CAN0_CLK 146 +#define IMX8QXP_CAN1_CLK 147 +#define IMX8QXP_CAN2_CLK 148 +#define IMX8QXP_I2C0_IPG_CLK 149 +#define IMX8QXP_I2C1_IPG_CLK 150 +#define IMX8QXP_I2C2_IPG_CLK 151 +#define IMX8QXP_I2C3_IPG_CLK 152 +#define IMX8QXP_I2C0_DIV 153 +#define IMX8QXP_I2C1_DIV 154 +#define IMX8QXP_I2C2_DIV 155 +#define IMX8QXP_I2C3_DIV 156 +#define IMX8QXP_I2C0_CLK 157 +#define IMX8QXP_I2C1_CLK 158 +#define IMX8QXP_I2C2_CLK 159 +#define IMX8QXP_I2C3_CLK 160 +#define IMX8QXP_FTM0_IPG_CLK 161 +#define IMX8QXP_FTM1_IPG_CLK 162 +#define IMX8QXP_FTM0_DIV 163 +#define IMX8QXP_FTM1_DIV 164 +#define IMX8QXP_FTM0_CLK 165 +#define IMX8QXP_FTM1_CLK 166 +#define IMX8QXP_ADC0_IPG_CLK 167 +#define IMX8QXP_ADC0_DIV 168 +#define IMX8QXP_ADC0_CLK 169 +#define IMX8QXP_PWM_IPG_CLK 170 +#define IMX8QXP_PWM_DIV 171 +#define IMX8QXP_PWM_CLK 172 +#define IMX8QXP_LCD_IPG_CLK 173 +#define IMX8QXP_LCD_DIV 174 +#define IMX8QXP_LCD_CLK 175 + +/* Connectivity SS */ +#define IMX8QXP_AXI_CONN_CLK_ROOT 176 +#define IMX8QXP_AHB_CONN_CLK_ROOT 177 +#define IMX8QXP_IPG_CONN_CLK_ROOT 178 +#define IMX8QXP_SDHC0_IPG_CLK 179 +#define IMX8QXP_SDHC1_IPG_CLK 180 +#define IMX8QXP_SDHC2_IPG_CLK 181 +#define IMX8QXP_SDHC0_DIV 182 +#define IMX8QXP_SDHC1_DIV 183 +#define IMX8QXP_SDHC2_DIV 184 +#define IMX8QXP_SDHC0_CLK 185 +#define IMX8QXP_SDHC1_CLK 186 +#define IMX8QXP_SDHC2_CLK 187 +#define IMX8QXP_ENET0_ROOT_DIV 188 +#define IMX8QXP_ENET0_REF_DIV 189 +#define IMX8QXP_ENET1_REF_DIV 190 +#define IMX8QXP_ENET0_BYPASS_DIV 191 +#define IMX8QXP_ENET0_RGMII_DIV 192 +#define IMX8QXP_ENET1_ROOT_DIV 193 +#define IMX8QXP_ENET1_BYPASS_DIV 194 +#define IMX8QXP_ENET1_RGMII_DIV 195 +#define IMX8QXP_ENET0_AHB_CLK 196 +#define IMX8QXP_ENET0_IPG_S_CLK 197 +#define IMX8QXP_ENET0_IPG_CLK 198 +#define IMX8QXP_ENET1_AHB_CLK 199 +#define IMX8QXP_ENET1_IPG_S_CLK 200 +#define IMX8QXP_ENET1_IPG_CLK 201 +#define IMX8QXP_ENET0_ROOT_CLK 202 +#define IMX8QXP_ENET1_ROOT_CLK 203 +#define IMX8QXP_ENET0_TX_CLK 204 +#define IMX8QXP_ENET1_TX_CLK 205 +#define IMX8QXP_ENET0_PTP_CLK 206 +#define IMX8QXP_ENET1_PTP_CLK 207 +#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_SEL 208 +#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_SEL 209 +#define IMX8QXP_ENET0_RMII_TX_SEL 210 +#define IMX8QXP_ENET1_RMII_TX_SEL 211 +#define IMX8QXP_ENET0_RGMII_TX_CLK 212 +#define IMX8QXP_ENET1_RGMII_TX_CLK 213 +#define IMX8QXP_ENET0_RMII_RX_CLK 214 +#define IMX8QXP_ENET1_RMII_RX_CLK 215 +#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_CLK 216 +#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_CLK 217 +#define IMX8QXP_ENET0_REF_50MHZ_CLK 218 +#define IMX8QXP_ENET1_REF_50MHZ_CLK 219 +#define IMX8QXP_GPMI_BCH_IO_DIV 220 +#define IMX8QXP_GPMI_BCH_DIV 221 +#define IMX8QXP_GPMI_APB_CLK 222 +#define IMX8QXP_GPMI_APB_BCH_CLK 223 +#define IMX8QXP_GPMI_BCH_IO_CLK 224 +#define IMX8QXP_GPMI_BCH_CLK 225 +#define IMX8QXP_APBHDMA_CLK 226 +#define IMX8QXP_USB3_ACLK_DIV 227 +#define IMX8QXP_USB3_BUS_DIV 228 +#define IMX8QXP_USB3_LPM_DIV 229 +#define IMX8QXP_USB3_IPG_CLK 230 +#define IMX8QXP_USB3_CORE_PCLK 231 +#define IMX8QXP_USB3_PHY_CLK 232 +#define IMX8QXP_USB3_ACLK 233 +#define IMX8QXP_USB3_BUS_CLK 234 +#define IMX8QXP_USB3_LPM_CLK 235 +#define IMX8QXP_USB2_OH_AHB_CLK 236 +#define IMX8QXP_USB2_OH_IPG_S_CLK 237 +#define IMX8QXP_USB2_OH_IPG_S_PL301_CLK 238 +#define IMX8QXP_USB2_PHY_IPG_CLK 239 +#define IMX8QXP_EDMA_CLK 240 +#define IMX8QXP_EDMA_IPG_CLK 241 +#define IMX8QXP_MLB_HCLK 242 +#define IMX8QXP_MLB_CLK 243 +#define IMX8QXP_MLB_IPG_CLK 244 + +/* Display controller SS */ +/* DC part1 */ +#define IMX8QXP_DC_AXI_EXT_CLK 245 +#define IMX8QXP_DC_AXI_INT_CLK 246 +#define IMX8QXP_DC_CFG_CLK 247 +#define IMX8QXP_DC0_DISP0_CLK 248 +#define IMX8QXP_DC0_DISP1_CLK 249 +#define IMX8QXP_DC0_PRG0_RTRAM_CLK 250 +#define IMX8QXP_DC0_PRG0_APB_CLK 251 +#define IMX8QXP_DC0_PRG1_RTRAM_CLK 252 +#define IMX8QXP_DC0_PRG1_APB_CLK 253 +#define IMX8QXP_DC0_PRG2_RTRAM_CLK 254 +#define IMX8QXP_DC0_PRG2_APB_CLK 255 +#define IMX8QXP_DC0_PRG3_RTRAM_CLK 256 +#define IMX8QXP_DC0_PRG3_APB_CLK 257 +#define IMX8QXP_DC0_PRG4_RTRAM_CLK 258 +#define IMX8QXP_DC0_PRG4_APB_CLK 259 +#define IMX8QXP_DC0_PRG5_RTRAM_CLK 260 +#define IMX8QXP_DC0_PRG5_APB_CLK 261 +#define IMX8QXP_DC0_PRG6_RTRAM_CLK 262 +#define IMX8QXP_DC0_PRG6_APB_CLK 263 +#define IMX8QXP_DC0_PRG7_RTRAM_CLK 264 +#define IMX8QXP_DC0_PRG7_APB_CLK 265 +#define IMX8QXP_DC0_PRG8_RTRAM_CLK 266 +#define IMX8QXP_DC0_PRG8_APB_CLK 267 +#define IMX8QXP_DC0_DPR0_APB_CLK 268 +#define IMX8QXP_DC0_DPR0_B_CLK 269 +#define IMX8QXP_DC0_RTRAM0_CLK 270 +#define IMX8QXP_DC0_RTRAM1_CLK 271 + +/* MIPI-LVDS part1 */ +#define IMX8QXP_MIPI_IPG_CLK 272 +#define IMX8QXP_MIPI0_I2C0_DIV 273 +#define IMX8QXP_MIPI0_I2C1_DIV 274 +#define IMX8QXP_MIPI0_I2C0_CLK 275 +#define IMX8QXP_MIPI0_I2C1_CLK 276 +#define IMX8QXP_MIPI0_I2C0_IPG_S_CLK 277 +#define IMX8QXP_MIPI0_I2C0_IPG_CLK 278 +#define IMX8QXP_MIPI0_I2C1_IPG_S_CLK 279 +#define IMX8QXP_MIPI0_I2C1_IPG_CLK 280 +#define IMX8QXP_MIPI0_PWM_IPG_S_CLK 281 +#define IMX8QXP_MIPI0_PWM_IPG_CLK 282 +#define IMX8QXP_MIPI0_PWM_32K_CLK 283 +#define IMX8QXP_MIPI0_GPIO_IPG_CLK 284 + +#define IMX8QXP_IMG_JPEG_ENC_IPG_CLK 285 +#define IMX8QXP_IMG_JPEG_ENC_CLK 286 +#define IMX8QXP_IMG_JPEG_DEC_IPG_CLK 287 +#define IMX8QXP_IMG_JPEG_DEC_CLK 288 +#define IMX8QXP_IMG_PXL_LINK_DC0_CLK 289 +#define IMX8QXP_IMG_PXL_LINK_DC1_CLK 290 +#define IMX8QXP_IMG_PXL_LINK_CSI0_CLK 291 +#define IMX8QXP_IMG_PXL_LINK_CSI1_CLK 292 +#define IMX8QXP_IMG_PXL_LINK_HDMI_IN_CLK 293 +#define IMX8QXP_IMG_PDMA_0_CLK 294 +#define IMX8QXP_IMG_PDMA_1_CLK 295 +#define IMX8QXP_IMG_PDMA_2_CLK 296 +#define IMX8QXP_IMG_PDMA_3_CLK 297 +#define IMX8QXP_IMG_PDMA_4_CLK 298 +#define IMX8QXP_IMG_PDMA_5_CLK 299 +#define IMX8QXP_IMG_PDMA_6_CLK 300 +#define IMX8QXP_IMG_PDMA_7_CLK 301 +#define IMX8QXP_IMG_AXI_CLK 302 +#define IMX8QXP_IMG_IPG_CLK 303 +#define IMX8QXP_IMG_PXL_CLK 304 + +#define IMX8QXP_CSI0_I2C0_DIV 305 +#define IMX8QXP_CSI0_PWM0_DIV 306 +#define IMX8QXP_CSI0_CORE_DIV 307 +#define IMX8QXP_CSI0_ESC_DIV 308 +#define IMX8QXP_CSI0_IPG_CLK_S 309 +#define IMX8QXP_CSI0_IPG_CLK 310 +#define IMX8QXP_CSI0_APB_CLK 311 +#define IMX8QXP_CSI0_I2C0_IPG_CLK 312 +#define IMX8QXP_CSI0_I2C0_CLK 313 +#define IMX8QXP_CSI0_PWM0_IPG_CLK 314 +#define IMX8QXP_CSI0_PWM0_CLK 315 +#define IMX8QXP_CSI0_CORE_CLK 316 +#define IMX8QXP_CSI0_ESC_CLK 317 + +#define IMX8QXP_HSIO_AXI_CLK 318 +#define IMX8QXP_HSIO_PER_CLK 319 +#define IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK 320 +#define IMX8QXP_HSIO_PCIE_SLV_AXI_CLK 321 +#define IMX8QXP_HSIO_PCIE_DBI_AXI_CLK 322 +#define IMX8QXP_HSIO_PCIE_X1_PER_CLK 323 +#define IMX8QXP_HSIO_PHY_X1_PER_CLK 324 +#define IMX8QXP_HSIO_MISC_PER_CLK 325 +#define IMX8QXP_HSIO_PHY_X1_APB_CLK 326 +#define IMX8QXP_HSIO_GPIO_CLK 327 +#define IMX8QXP_HSIO_PHY_X1_PCLK 328 + +#define IMX8QXP_A35_DIV 329 + +/* ACM */ +#define IMX8QXP_EXT_AUD_MCLK0 330 +#define IMX8QXP_EXT_AUD_MCLK1 331 +#define IMX8QXP_ESAI0_RX_CLK 332 +#define IMX8QXP_ESAI0_RX_HF_CLK 333 +#define IMX8QXP_ESAI0_TX_CLK 334 +#define IMX8QXP_ESAI0_TX_HF_CLK 335 +#define IMX8QXP_SPDIF0_RX 336 +#define IMX8QXP_SAI0_RX_BCLK 337 +#define IMX8QXP_SAI0_TX_BCLK 338 +#define IMX8QXP_SAI1_RX_BCLK 339 +#define IMX8QXP_SAI1_TX_BCLK 340 +#define IMX8QXP_SAI2_RX_BCLK 341 +#define IMX8QXP_SAI3_RX_BCLK 342 +#define IMX8QXP_SAI4_RX_BCLK 343 + +#define IMX8QXP_ACM_AUD_CLK0_SEL 344 +#define IMX8QXP_ACM_AUD_CLK0_CLK 345 +#define IMX8QXP_ACM_AUD_CLK1_SEL 346 +#define IMX8QXP_ACM_AUD_CLK1_CLK 347 +#define IMX8QXP_ACM_MCLKOUT0_SEL 348 +#define IMX8QXP_ACM_MCLKOUT0_CLK 349 +#define IMX8QXP_ACM_MCLKOUT1_SEL 350 +#define IMX8QXP_ACM_MCLKOUT1_CLK 351 +#define IMX8QXP_ACM_ESAI0_MCLK_SEL 352 +#define IMX8QXP_ACM_ESAI0_MCLK_CLK 353 +#define IMX8QXP_ACM_GPT0_MUX_CLK_SEL 354 +#define IMX8QXP_ACM_GPT0_MUX_CLK_CLK 355 +#define IMX8QXP_ACM_GPT1_MUX_CLK_SEL 356 +#define IMX8QXP_ACM_GPT1_MUX_CLK_CLK 357 +#define IMX8QXP_ACM_GPT2_MUX_CLK_SEL 358 +#define IMX8QXP_ACM_GPT2_MUX_CLK_CLK 359 +#define IMX8QXP_ACM_GPT3_MUX_CLK_SEL 360 +#define IMX8QXP_ACM_GPT3_MUX_CLK_CLK 361 +#define IMX8QXP_ACM_GPT4_MUX_CLK_SEL 362 +#define IMX8QXP_ACM_GPT4_MUX_CLK_CLK 363 +#define IMX8QXP_ACM_GPT5_MUX_CLK_SEL 364 +#define IMX8QXP_ACM_GPT5_MUX_CLK_CLK 365 +#define IMX8QXP_ACM_SAI0_MCLK_SEL 366 +#define IMX8QXP_ACM_SAI0_MCLK_CLK 367 +#define IMX8QXP_ACM_SAI1_MCLK_SEL 368 +#define IMX8QXP_ACM_SAI1_MCLK_CLK 369 +#define IMX8QXP_ACM_SAI2_MCLK_SEL 370 +#define IMX8QXP_ACM_SAI2_MCLK_CLK 371 +#define IMX8QXP_ACM_SAI3_MCLK_SEL 372 +#define IMX8QXP_ACM_SAI3_MCLK_CLK 373 +#define IMX8QXP_ACM_SAI4_MCLK_SEL 374 +#define IMX8QXP_ACM_SAI4_MCLK_CLK 375 +#define IMX8QXP_ACM_SAI5_MCLK_SEL 376 +#define IMX8QXP_ACM_SAI5_MCLK_CLK 377 +#define IMX8QXP_ACM_SPDIF0_TX_CLK_SEL 378 +#define IMX8QXP_ACM_SPDIF0_TX_CLK_CLK 379 +#define IMX8QXP_ACM_MQS_TX_CLK_SEL 380 +#define IMX8QXP_ACM_MQS_TX_CLK_CLK 381 +#define IMX8QXP_ACM_ASRC0_MUX_CLK_SEL 382 +#define IMX8QXP_ACM_ASRC1_MUX_CLK_SEL 383 +#define IMX8QXP_ACM_ASRC0_MUX_CLK_CLK 384 +#define IMX8QXP_ACM_ASRC1_MUX_CLK_CLK 385 + +#define IMX8QXP_IPG_AUD_CLK_ROOT 386 + +/* Audio */ +#define IMX8QXP_AUD_PLL0_DIV 387 +#define IMX8QXP_AUD_PLL0 388 +#define IMX8QXP_AUD_PLL1_DIV 389 +#define IMX8QXP_AUD_PLL1 390 +#define IMX8QXP_AUD_AMIX_IPG 391 +#define IMX8QXP_AUD_ESAI_0_IPG 392 +#define IMX8QXP_AUD_ESAI_0_EXTAL_IPG 393 +#define IMX8QXP_AUD_SAI_0_IPG 394 +#define IMX8QXP_AUD_SAI_0_MCLK 395 +#define IMX8QXP_AUD_SAI_1_IPG 396 +#define IMX8QXP_AUD_SAI_1_MCLK 397 +#define IMX8QXP_AUD_SAI_2_IPG 398 +#define IMX8QXP_AUD_SAI_2_MCLK 399 +#define IMX8QXP_AUD_SAI_3_IPG 400 +#define IMX8QXP_AUD_SAI_3_MCLK 401 +#define IMX8QXP_AUD_SAI_4_IPG 402 +#define IMX8QXP_AUD_SAI_4_MCLK 403 +#define IMX8QXP_AUD_SAI_5_IPG 404 +#define IMX8QXP_AUD_SAI_5_MCLK 405 +#define IMX8QXP_AUD_MQS_IPG 406 +#define IMX8QXP_AUD_MQS_HMCLK 407 +#define IMX8QXP_AUD_GPT5_IPG 408 +#define IMX8QXP_AUD_GPT5_CLKIN 409 +#define IMX8QXP_AUD_GPT6_IPG 410 +#define IMX8QXP_AUD_GPT6_CLKIN 411 +#define IMX8QXP_AUD_GPT7_IPG 412 +#define IMX8QXP_AUD_GPT7_CLKIN 413 +#define IMX8QXP_AUD_GPT8_IPG 414 +#define IMX8QXP_AUD_GPT8_CLKIN 415 +#define IMX8QXP_AUD_GPT9_IPG 416 +#define IMX8QXP_AUD_GPT9_CLKIN 417 +#define IMX8QXP_AUD_GPT10_IPG 418 +#define IMX8QXP_AUD_GPT10_CLKIN 419 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV 420 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK 421 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV 422 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK 423 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV 424 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_CLK 425 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV 426 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_CLK 427 +#define IMX8QXP_AUD_MCLKOUT0 428 +#define IMX8QXP_AUD_MCLKOUT1 429 +#define IMX8QXP_AUD_SPDIF_0_TX_CLK 430 +#define IMX8QXP_AUD_SPDIF_0_GCLKW 431 +#define IMX8QXP_AUD_SPDIF_0_IPG 432 +#define IMX8QXP_AUD_ASRC_0_IPG 433 +#define IMX8QXP_AUD_ASRC_1_IPG 434 +#define IMX8QXP_AUD_DSP_ADB_ACLK 435 +#define IMX8QXP_AUD_DSP_IPG 436 +#define IMX8QXP_AUD_DSP_CORE_CLK 437 +#define IMX8QXP_AUD_OCRAM_IPG 438 + +/* DC part2 */ +#define IMX8QXP_DC0_DISP0_DIV 439 +#define IMX8QXP_DC0_DISP1_DIV 440 +#define IMX8QXP_DC0_BYPASS_0_DIV 441 +#define IMX8QXP_DC0_BYPASS_1_DIV 442 +#define IMX8QXP_DC0_PLL0_DIV 443 +#define IMX8QXP_DC0_PLL1_DIV 444 +#define IMX8QXP_DC0_PLL0_CLK 445 +#define IMX8QXP_DC0_PLL1_CLK 446 + +/* MIPI-LVDS part2 */ +#define IMX8QXP_MIPI0_BYPASS_CLK 447 +#define IMX8QXP_MIPI0_PIXEL_DIV 448 +#define IMX8QXP_MIPI0_PIXEL_CLK 449 +#define IMX8QXP_MIPI0_LVDS_PIXEL_DIV 450 +#define IMX8QXP_MIPI0_LVDS_PIXEL_CLK 451 +#define IMX8QXP_MIPI0_LVDS_BYPASS_CLK 452 +#define IMX8QXP_MIPI0_LVDS_PHY_DIV 453 +#define IMX8QXP_MIPI0_LVDS_PHY_CLK 454 +#define IMX8QXP_MIPI0_DSI_TX_ESC_DIV 455 +#define IMX8QXP_MIPI0_DSI_RX_ESC_DIV 456 +#define IMX8QXP_MIPI0_DSI_TX_ESC_CLK 457 +#define IMX8QXP_MIPI0_DSI_RX_ESC_CLK 458 +#define IMX8QXP_MIPI0_LIS_IPG_CLK 459 +#define IMX8QXP_MIPI1_I2C0_DIV 460 +#define IMX8QXP_MIPI1_I2C1_DIV 461 +#define IMX8QXP_MIPI1_I2C0_CLK 462 +#define IMX8QXP_MIPI1_I2C1_CLK 463 +#define IMX8QXP_MIPI1_I2C0_IPG_S_CLK 464 +#define IMX8QXP_MIPI1_I2C0_IPG_CLK 465 +#define IMX8QXP_MIPI1_I2C1_IPG_S_CLK 466 +#define IMX8QXP_MIPI1_I2C1_IPG_CLK 467 +#define IMX8QXP_MIPI1_PWM_IPG_S_CLK 468 +#define IMX8QXP_MIPI1_PWM_IPG_CLK 469 +#define IMX8QXP_MIPI1_PWM_32K_CLK 470 +#define IMX8QXP_MIPI1_GPIO_IPG_CLK 471 +#define IMX8QXP_MIPI1_BYPASS_CLK 472 +#define IMX8QXP_MIPI1_PIXEL_DIV 473 +#define IMX8QXP_MIPI1_PIXEL_CLK 474 +#define IMX8QXP_MIPI1_LVDS_PIXEL_DIV 475 +#define IMX8QXP_MIPI1_LVDS_PIXEL_CLK 476 +#define IMX8QXP_MIPI1_LVDS_BYPASS_CLK 477 +#define IMX8QXP_MIPI1_LVDS_PHY_DIV 478 +#define IMX8QXP_MIPI1_LVDS_PHY_CLK 479 +#define IMX8QXP_MIPI1_DSI_TX_ESC_DIV 480 +#define IMX8QXP_MIPI1_DSI_RX_ESC_DIV 481 +#define IMX8QXP_MIPI1_DSI_TX_ESC_CLK 482 +#define IMX8QXP_MIPI1_DSI_RX_ESC_CLK 483 + +#define IMX8QXP_MIPI1_LIS_IPG_CLK 484 + +/* CM40 */ +#define IMX8QXP_CM40_IPG_CLK 485 +#define IMX8QXP_CM40_I2C_DIV 486 +#define IMX8QXP_CM40_I2C_CLK 487 +#define IMX8QXP_CM40_I2C_IPG_CLK 488 + +/* VPU clocks. */ +#define IMX8QXP_VPU_ENC_CLK 489 +#define IMX8QXP_VPU_DEC_CLK 490 + +/* MIPI-LVDS part3 */ +#define IMX8QXP_MIPI0_DSI_PLL_CLK 491 +#define IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK 492 +#define IMX8QXP_MIPI0_LVDS_PIXEL_SEL 493 +#define IMX8QXP_MIPI0_LVDS_PHY_SEL 494 +#define IMX8QXP_MIPI0_DSI_TX_ESC_SEL 495 +#define IMX8QXP_MIPI0_DSI_RX_ESC_SEL 496 +#define IMX8QXP_MIPI0_DSI_PHY_SEL 498 +#define IMX8QXP_MIPI0_DSI_PHY_DIV 499 +#define IMX8QXP_MIPI0_DSI_PHY_CLK 500 +#define IMX8QXP_MIPI1_DSI_PLL_CLK 501 +#define IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK 502 +#define IMX8QXP_MIPI1_LVDS_PIXEL_SEL 503 +#define IMX8QXP_MIPI1_LVDS_PHY_SEL 504 +#define IMX8QXP_MIPI1_DSI_TX_ESC_SEL 505 +#define IMX8QXP_MIPI1_DSI_RX_ESC_SEL 506 +#define IMX8QXP_MIPI1_DSI_PHY_SEL 507 +#define IMX8QXP_MIPI1_DSI_PHY_DIV 508 +#define IMX8QXP_MIPI1_DSI_PHY_CLK 509 + +/* DC part3 */ +#define IMX8QXP_DC0_DPR1_APB_CLK 510 +#define IMX8QXP_DC0_DPR1_B_CLK 511 + +#define IMX8QXP_CONN_PLL0_CLK 512 +#define IMX8QXP_CONN_PLL1_CLK 513 +#define IMX8QXP_SDHC0_SEL 514 +#define IMX8QXP_SDHC1_SEL 515 +#define IMX8QXP_SDHC2_SEL 516 + +/* PARALLER CSI */ +#define IMX8QXP_PARALLEL_CSI_CLK_DPLL 517 +#define IMX8QXP_PARALLEL_CSI_CLK_SEL 518 +#define IMX8QXP_PARALLEL_CSI_PER_CLK_DIV 519 +#define IMX8QXP_PARALLEL_CSI_PIXEL_CLK 520 +#define IMX8QXP_PARALLEL_CSI_IPG_CLK 521 +#define IMX8QXP_PARALLEL_CSI_MCLK_DIV 522 +#define IMX8QXP_PARALLEL_CSI_MISC0_CLK 523 + +#define IMX8QXP_MIPI0_PWM_DIV 524 +#define IMX8QXP_MIPI1_PWM_DIV 525 +#define IMX8QXP_MIPI0_PWM_CLK 526 +#define IMX8QXP_MIPI1_PWM_CLK 527 + +#define IMX8QXP_LSIO_MU5A_IPG_S_CLK 528 +#define IMX8QXP_LSIO_MU5A_IPG_CLK 529 + +#define IMX8QXP_CLK_END 530 +#endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/imxrt1020-clock.h b/roms/u-boot/include/dt-bindings/clock/imxrt1020-clock.h new file mode 100644 index 000000000..836244358 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/imxrt1020-clock.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright(C) 2020 + * Author(s): Giulio Benetti + */ + +#ifndef __DT_BINDINGS_CLOCK_IMXRT1020_H +#define __DT_BINDINGS_CLOCK_IMXRT1020_H + +#define IMXRT1020_CLK_DUMMY 0 +#define IMXRT1020_CLK_CKIL 1 +#define IMXRT1020_CLK_CKIH 2 +#define IMXRT1020_CLK_OSC 3 +#define IMXRT1020_CLK_PLL2_PFD0_352M 4 +#define IMXRT1020_CLK_PLL2_PFD1_594M 5 +#define IMXRT1020_CLK_PLL2_PFD2_396M 6 +#define IMXRT1020_CLK_PLL2_PFD3_297M 7 +#define IMXRT1020_CLK_PLL3_PFD0_720M 8 +#define IMXRT1020_CLK_PLL3_PFD1_664_62M 9 +#define IMXRT1020_CLK_PLL3_PFD2_508_24M 10 +#define IMXRT1020_CLK_PLL3_PFD3_454_74M 11 +#define IMXRT1020_CLK_PLL2_198M 12 +#define IMXRT1020_CLK_PLL3_120M 13 +#define IMXRT1020_CLK_PLL3_80M 14 +#define IMXRT1020_CLK_PLL3_60M 15 +#define IMXRT1020_CLK_PLL2_BYPASS 16 +#define IMXRT1020_CLK_PLL3_BYPASS 17 +#define IMXRT1020_CLK_PLL6_BYPASS 18 +#define IMXRT1020_CLK_PRE_PERIPH_SEL 19 +#define IMXRT1020_CLK_PERIPH_SEL 20 +#define IMXRT1020_CLK_SEMC_ALT_SEL 21 +#define IMXRT1020_CLK_SEMC_SEL 22 +#define IMXRT1020_CLK_USDHC1_SEL 23 +#define IMXRT1020_CLK_USDHC2_SEL 24 +#define IMXRT1020_CLK_LPUART_SEL 25 +#define IMXRT1020_CLK_ARM_PODF 26 +#define IMXRT1020_CLK_LPUART_PODF 27 +#define IMXRT1020_CLK_USDHC1_PODF 28 +#define IMXRT1020_CLK_USDHC2_PODF 29 +#define IMXRT1020_CLK_SEMC_PODF 30 +#define IMXRT1020_CLK_AHB_PODF 31 +#define IMXRT1020_CLK_USDHC1 32 +#define IMXRT1020_CLK_USDHC2 33 +#define IMXRT1020_CLK_LPUART1 34 +#define IMXRT1020_CLK_SEMC 35 +#define IMXRT1020_CLK_PLL2_SYS 36 +#define IMXRT1020_CLK_PLL3_USB_OTG 37 +#define IMXRT1020_CLK_PLL4_AUDIO 38 +#define IMXRT1020_CLK_PLL6_ENET 39 +#define IMXRT1020_CLK_END 40 + +#endif /* __DT_BINDINGS_CLOCK_IMXRT1020_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/imxrt1050-clock.h b/roms/u-boot/include/dt-bindings/clock/imxrt1050-clock.h new file mode 100644 index 000000000..f74dbbcf9 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/imxrt1050-clock.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright(C) 2019 + * Author(s): Giulio Benetti + */ + +#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H +#define __DT_BINDINGS_CLOCK_IMXRT1050_H + +#define IMXRT1050_CLK_DUMMY 0 +#define IMXRT1050_CLK_CKIL 1 +#define IMXRT1050_CLK_CKIH 2 +#define IMXRT1050_CLK_OSC 3 +#define IMXRT1050_CLK_PLL2_PFD0_352M 4 +#define IMXRT1050_CLK_PLL2_PFD1_594M 5 +#define IMXRT1050_CLK_PLL2_PFD2_396M 6 +#define IMXRT1050_CLK_PLL3_PFD0_720M 7 +#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8 +#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9 +#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10 +#define IMXRT1050_CLK_PLL2_198M 11 +#define IMXRT1050_CLK_PLL3_120M 12 +#define IMXRT1050_CLK_PLL3_80M 13 +#define IMXRT1050_CLK_PLL3_60M 14 +#define IMXRT1050_CLK_PLL1_BYPASS 15 +#define IMXRT1050_CLK_PLL2_BYPASS 16 +#define IMXRT1050_CLK_PLL3_BYPASS 17 +#define IMXRT1050_CLK_PLL5_BYPASS 19 +#define IMXRT1050_CLK_PLL1_REF_SEL 20 +#define IMXRT1050_CLK_PLL2_REF_SEL 21 +#define IMXRT1050_CLK_PLL3_REF_SEL 22 +#define IMXRT1050_CLK_PLL5_REF_SEL 23 +#define IMXRT1050_CLK_PRE_PERIPH_SEL 24 +#define IMXRT1050_CLK_PERIPH_SEL 25 +#define IMXRT1050_CLK_SEMC_ALT_SEL 26 +#define IMXRT1050_CLK_SEMC_SEL 27 +#define IMXRT1050_CLK_USDHC1_SEL 28 +#define IMXRT1050_CLK_USDHC2_SEL 29 +#define IMXRT1050_CLK_LPUART_SEL 30 +#define IMXRT1050_CLK_LCDIF_SEL 31 +#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 32 +#define IMXRT1050_CLK_VIDEO_DIV 33 +#define IMXRT1050_CLK_ARM_PODF 34 +#define IMXRT1050_CLK_LPUART_PODF 35 +#define IMXRT1050_CLK_USDHC1_PODF 36 +#define IMXRT1050_CLK_USDHC2_PODF 37 +#define IMXRT1050_CLK_SEMC_PODF 38 +#define IMXRT1050_CLK_AHB_PODF 39 +#define IMXRT1050_CLK_LCDIF_PRED 40 +#define IMXRT1050_CLK_LCDIF_PODF 41 +#define IMXRT1050_CLK_USDHC1 42 +#define IMXRT1050_CLK_USDHC2 43 +#define IMXRT1050_CLK_LPUART1 44 +#define IMXRT1050_CLK_SEMC 45 +#define IMXRT1050_CLK_LCDIF_APB 46 +#define IMXRT1050_CLK_PLL1_ARM 47 +#define IMXRT1050_CLK_PLL2_SYS 48 +#define IMXRT1050_CLK_PLL3_USB_OTG 49 +#define IMXRT1050_CLK_PLL4_AUDIO 50 +#define IMXRT1050_CLK_PLL5_VIDEO 51 +#define IMXRT1050_CLK_PLL6_ENET 52 +#define IMXRT1050_CLK_PLL7_USB_HOST 53 +#define IMXRT1050_CLK_LCDIF_PIX 54 +#define IMXRT1050_CLK_USBOH3 55 +#define IMXRT1050_CLK_END 56 + +#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/intel-clock.h b/roms/u-boot/include/dt-bindings/clock/intel-clock.h new file mode 100644 index 000000000..e1edd3c71 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/intel-clock.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This header provides constants for Intel clocks. + * + * The constants defined in this header are used in the device tree + * + * Copyright 2019 Google LLC + */ + +#ifndef _DT_BINDINGS_CLK_INTEL_H +#define _DT_BINDINGS_CLK_INTEL_H + +#define CLK_I2C 1 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/jz4780-cgu.h b/roms/u-boot/include/dt-bindings/clock/jz4780-cgu.h new file mode 100644 index 000000000..73214c52c --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/jz4780-cgu.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the jz4780 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ + +#define JZ4780_CLK_EXCLK 0 +#define JZ4780_CLK_RTCLK 1 +#define JZ4780_CLK_APLL 2 +#define JZ4780_CLK_MPLL 3 +#define JZ4780_CLK_EPLL 4 +#define JZ4780_CLK_VPLL 5 +#define JZ4780_CLK_OTGPHY 6 +#define JZ4780_CLK_SCLKA 7 +#define JZ4780_CLK_CPUMUX 8 +#define JZ4780_CLK_CPU 9 +#define JZ4780_CLK_L2CACHE 10 +#define JZ4780_CLK_AHB0 11 +#define JZ4780_CLK_AHB2PMUX 12 +#define JZ4780_CLK_AHB2 13 +#define JZ4780_CLK_PCLK 14 +#define JZ4780_CLK_DDR 15 +#define JZ4780_CLK_VPU 16 +#define JZ4780_CLK_I2SPLL 17 +#define JZ4780_CLK_I2S 18 +#define JZ4780_CLK_LCD0PIXCLK 19 +#define JZ4780_CLK_LCD1PIXCLK 20 +#define JZ4780_CLK_MSCMUX 21 +#define JZ4780_CLK_MSC0 22 +#define JZ4780_CLK_MSC1 23 +#define JZ4780_CLK_MSC2 24 +#define JZ4780_CLK_UHC 25 +#define JZ4780_CLK_SSIPLL 26 +#define JZ4780_CLK_SSI 27 +#define JZ4780_CLK_CIMMCLK 28 +#define JZ4780_CLK_PCMPLL 29 +#define JZ4780_CLK_PCM 30 +#define JZ4780_CLK_GPU 31 +#define JZ4780_CLK_HDMI 32 +#define JZ4780_CLK_BCH 33 +#define JZ4780_CLK_NEMC 34 +#define JZ4780_CLK_OTG0 35 +#define JZ4780_CLK_SSI0 36 +#define JZ4780_CLK_SMB0 37 +#define JZ4780_CLK_SMB1 38 +#define JZ4780_CLK_SCC 39 +#define JZ4780_CLK_AIC 40 +#define JZ4780_CLK_TSSI0 41 +#define JZ4780_CLK_OWI 42 +#define JZ4780_CLK_KBC 43 +#define JZ4780_CLK_SADC 44 +#define JZ4780_CLK_UART0 45 +#define JZ4780_CLK_UART1 46 +#define JZ4780_CLK_UART2 47 +#define JZ4780_CLK_UART3 48 +#define JZ4780_CLK_SSI1 49 +#define JZ4780_CLK_SSI2 50 +#define JZ4780_CLK_PDMA 51 +#define JZ4780_CLK_GPS 52 +#define JZ4780_CLK_MAC 53 +#define JZ4780_CLK_SMB2 54 +#define JZ4780_CLK_CIM 55 +#define JZ4780_CLK_LCD 56 +#define JZ4780_CLK_TVE 57 +#define JZ4780_CLK_IPU 58 +#define JZ4780_CLK_DDR0 59 +#define JZ4780_CLK_DDR1 60 +#define JZ4780_CLK_SMB3 61 +#define JZ4780_CLK_TSSI1 62 +#define JZ4780_CLK_COMPRESS 63 +#define JZ4780_CLK_AIC1 64 +#define JZ4780_CLK_GPVLC 65 +#define JZ4780_CLK_OTG1 66 +#define JZ4780_CLK_UART4 67 +#define JZ4780_CLK_AHBMON 68 +#define JZ4780_CLK_SMB4 69 +#define JZ4780_CLK_DES 70 +#define JZ4780_CLK_X2D 71 +#define JZ4780_CLK_CORE1 72 + +#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/k210-sysctl.h b/roms/u-boot/include/dt-bindings/clock/k210-sysctl.h new file mode 100644 index 000000000..fe852bbd9 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/k210-sysctl.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-20 Sean Anderson + */ + +#ifndef CLOCK_K210_SYSCTL_H +#define CLOCK_K210_SYSCTL_H + +/* + * Arbitrary identifiers for clocks. + */ +#define K210_CLK_NONE 0 +#define K210_CLK_IN0_H 1 +#define K210_CLK_PLL0_H 2 +#define K210_CLK_PLL0 3 +#define K210_CLK_PLL1 4 +#define K210_CLK_PLL2 5 +#define K210_CLK_PLL2_H 6 +#define K210_CLK_CPU 7 +#define K210_CLK_SRAM0 8 +#define K210_CLK_SRAM1 9 +#define K210_CLK_APB0 10 +#define K210_CLK_APB1 11 +#define K210_CLK_APB2 12 +#define K210_CLK_ROM 13 +#define K210_CLK_DMA 14 +#define K210_CLK_AI 15 +#define K210_CLK_DVP 16 +#define K210_CLK_FFT 17 +#define K210_CLK_GPIO 18 +#define K210_CLK_SPI0 19 +#define K210_CLK_SPI1 20 +#define K210_CLK_SPI2 21 +#define K210_CLK_SPI3 22 +#define K210_CLK_I2S0 23 +#define K210_CLK_I2S1 24 +#define K210_CLK_I2S2 25 +#define K210_CLK_I2S0_M 26 +#define K210_CLK_I2S1_M 27 +#define K210_CLK_I2S2_M 28 +#define K210_CLK_I2C0 29 +#define K210_CLK_I2C1 30 +#define K210_CLK_I2C2 31 +#define K210_CLK_UART1 32 +#define K210_CLK_UART2 33 +#define K210_CLK_UART3 34 +#define K210_CLK_AES 35 +#define K210_CLK_FPIOA 36 +#define K210_CLK_TIMER0 37 +#define K210_CLK_TIMER1 38 +#define K210_CLK_TIMER2 39 +#define K210_CLK_WDT0 40 +#define K210_CLK_WDT1 41 +#define K210_CLK_SHA 42 +#define K210_CLK_OTP 43 +#define K210_CLK_RTC 44 +#define K210_CLK_ACLK 45 +#define K210_CLK_CLINT 46 + +#endif /* CLOCK_K210_SYSCTL_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/maxim,max77802.h b/roms/u-boot/include/dt-bindings/clock/maxim,max77802.h new file mode 100644 index 000000000..997312edc --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/maxim,max77802.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants clocks for the Maxim 77802 PMIC. + */ + +#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H +#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H + +/* Fixed rate clocks. */ + +#define MAX77802_CLK_32K_AP 0 +#define MAX77802_CLK_32K_CP 1 + +/* Total number of clocks. */ +#define MAX77802_CLKS_NUM (MAX77802_CLK_32K_CP + 1) + +#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/microchip,clock.h b/roms/u-boot/include/dt-bindings/clock/microchip,clock.h new file mode 100644 index 000000000..ea6f161f9 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/microchip,clock.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (c) 2015 Purna Chandra Mandal + * + */ + +#ifndef __CLK_MICROCHIP_PIC32 +#define __CLK_MICROCHIP_PIC32 + +/* clock output indices */ +#define BASECLK 0 +#define PLLCLK 1 +#define MPLL 2 +#define SYSCLK 3 +#define PB1CLK 4 +#define PB2CLK 5 +#define PB3CLK 6 +#define PB4CLK 7 +#define PB5CLK 8 +#define PB6CLK 9 +#define PB7CLK 10 +#define REF1CLK 11 +#define REF2CLK 12 +#define REF3CLK 13 +#define REF4CLK 14 +#define REF5CLK 15 + +#endif /* __CLK_MICROCHIP_PIC32 */ diff --git a/roms/u-boot/include/dt-bindings/clock/microchip-mpfs-clock.h b/roms/u-boot/include/dt-bindings/clock/microchip-mpfs-clock.h new file mode 100644 index 000000000..55fe64693 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/microchip-mpfs-clock.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari + */ + +#ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ +#define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ + +#define CLK_CPU 0 +#define CLK_AXI 1 +#define CLK_AHB 2 + +#define CLK_ENVM 3 +#define CLK_MAC0 4 +#define CLK_MAC1 5 +#define CLK_MMC 6 +#define CLK_TIMER 7 +#define CLK_MMUART0 8 +#define CLK_MMUART1 9 +#define CLK_MMUART2 10 +#define CLK_MMUART3 11 +#define CLK_MMUART4 12 +#define CLK_SPI0 13 +#define CLK_SPI1 14 +#define CLK_I2C0 15 +#define CLK_I2C1 16 +#define CLK_CAN0 17 +#define CLK_CAN1 18 +#define CLK_USB 19 +#define CLK_RESERVED 20 +#define CLK_RTC 21 +#define CLK_QSPI 22 +#define CLK_GPIO0 23 +#define CLK_GPIO1 24 +#define CLK_GPIO2 25 +#define CLK_DDRC 26 +#define CLK_FIC0 27 +#define CLK_FIC1 28 +#define CLK_FIC2 29 +#define CLK_FIC3 30 +#define CLK_ATHENA 31 +#define CLK_CFM 32 + +#endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/mt7620-clk.h b/roms/u-boot/include/dt-bindings/clock/mt7620-clk.h new file mode 100644 index 000000000..3bb91ebdf --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/mt7620-clk.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao + */ + +#ifndef _DT_BINDINGS_MT7620_CLK_H_ +#define _DT_BINDINGS_MT7620_CLK_H_ + +/* Base clocks */ +#define CLK_SYS 34 +#define CLK_CPU 33 +#define CLK_XTAL 32 + +/* Peripheral clocks */ +#define CLK_SDHC 30 +#define CLK_MIPS_CNT 28 +#define CLK_PCIE 26 +#define CLK_UPHY_12M 25 +#define CLK_EPHY 24 +#define CLK_ESW 23 +#define CLK_UPHY_48M 22 +#define CLK_FE 21 +#define CLK_UARTL 19 +#define CLK_SPI 18 +#define CLK_I2S 17 +#define CLK_I2C 16 +#define CLK_NAND 15 +#define CLK_GDMA 14 +#define CLK_PIO 13 +#define CLK_UARTF 12 +#define CLK_PCM 11 +#define CLK_MC 10 +#define CLK_INTC 9 +#define CLK_TIMER 8 +#define CLK_GE2 7 +#define CLK_GE1 6 + +#endif /* _DT_BINDINGS_MT7620_CLK_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/mt7622-clk.h b/roms/u-boot/include/dt-bindings/clock/mt7622-clk.h new file mode 100644 index 000000000..22b8d08b6 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/mt7622-clk.h @@ -0,0 +1,271 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019 MediaTek Inc. + */ +#ifndef _DT_BINDINGS_CLK_MT7622_H +#define _DT_BINDINGS_CLK_MT7622_H + +/* TOPCKGEN */ + +/* FIXED_CLKS */ +#define CLK_TOP_TO_U2_PHY 0 +#define CLK_TOP_TO_U2_PHY_1P 1 +#define CLK_TOP_PCIE0_PIPE_EN 2 +#define CLK_TOP_PCIE1_PIPE_EN 3 +#define CLK_TOP_SSUSB_TX250M 4 +#define CLK_TOP_SSUSB_EQ_RX250M 5 +#define CLK_TOP_SSUSB_CDR_REF 6 +#define CLK_TOP_SSUSB_CDR_FB 7 +#define CLK_TOP_SATA_ASIC 8 +#define CLK_TOP_SATA_RBC 9 +/* FIXED_DIVS */ +#define CLK_TOP_TO_USB3_SYS 10 +#define CLK_TOP_P1_1MHZ 11 +#define CLK_TOP_4MHZ 12 +#define CLK_TOP_P0_1MHZ 13 +#define CLK_TOP_TXCLK_SRC_PRE 14 +#define CLK_TOP_RTC 15 +#define CLK_TOP_MEMPLL 16 +#define CLK_TOP_DMPLL 17 +#define CLK_TOP_SYSPLL_D2 18 +#define CLK_TOP_SYSPLL1_D2 19 +#define CLK_TOP_SYSPLL1_D4 20 +#define CLK_TOP_SYSPLL1_D8 21 +#define CLK_TOP_SYSPLL2_D4 22 +#define CLK_TOP_SYSPLL2_D8 23 +#define CLK_TOP_SYSPLL_D5 24 +#define CLK_TOP_SYSPLL3_D2 25 +#define CLK_TOP_SYSPLL3_D4 26 +#define CLK_TOP_SYSPLL4_D2 27 +#define CLK_TOP_SYSPLL4_D4 28 +#define CLK_TOP_SYSPLL4_D16 29 +#define CLK_TOP_UNIVPLL 30 +#define CLK_TOP_UNIVPLL_D2 31 +#define CLK_TOP_UNIVPLL1_D2 32 +#define CLK_TOP_UNIVPLL1_D4 33 +#define CLK_TOP_UNIVPLL1_D8 34 +#define CLK_TOP_UNIVPLL1_D16 35 +#define CLK_TOP_UNIVPLL2_D2 36 +#define CLK_TOP_UNIVPLL2_D4 37 +#define CLK_TOP_UNIVPLL2_D8 38 +#define CLK_TOP_UNIVPLL2_D16 39 +#define CLK_TOP_UNIVPLL_D5 40 +#define CLK_TOP_UNIVPLL3_D2 41 +#define CLK_TOP_UNIVPLL3_D4 42 +#define CLK_TOP_UNIVPLL3_D16 43 +#define CLK_TOP_UNIVPLL_D7 44 +#define CLK_TOP_UNIVPLL_D80_D4 45 +#define CLK_TOP_UNIV48M 46 +#define CLK_TOP_SGMIIPLL 47 +#define CLK_TOP_SGMIIPLL_D2 48 +#define CLK_TOP_AUD1PLL 49 +#define CLK_TOP_AUD2PLL 50 +#define CLK_TOP_AUD_I2S2_MCK 51 +#define CLK_TOP_TO_USB3_REF 52 +#define CLK_TOP_PCIE1_MAC_EN 53 +#define CLK_TOP_PCIE0_MAC_EN 54 +#define CLK_TOP_ETH_500M 55 +/* TOP_MUXES */ +#define CLK_TOP_AXI_SEL 56 +#define CLK_TOP_MEM_SEL 57 +#define CLK_TOP_DDRPHYCFG_SEL 58 +#define CLK_TOP_ETH_SEL 59 +#define CLK_TOP_PWM_SEL 60 +#define CLK_TOP_F10M_REF_SEL 61 +#define CLK_TOP_NFI_INFRA_SEL 62 +#define CLK_TOP_FLASH_SEL 63 +#define CLK_TOP_UART_SEL 64 +#define CLK_TOP_SPI0_SEL 65 +#define CLK_TOP_SPI1_SEL 66 +#define CLK_TOP_MSDC50_0_SEL 67 +#define CLK_TOP_MSDC30_0_SEL 68 +#define CLK_TOP_MSDC30_1_SEL 69 +#define CLK_TOP_A1SYS_HP_SEL 70 +#define CLK_TOP_A2SYS_HP_SEL 71 +#define CLK_TOP_INTDIR_SEL 72 +#define CLK_TOP_AUD_INTBUS_SEL 73 +#define CLK_TOP_PMICSPI_SEL 74 +#define CLK_TOP_SCP_SEL 75 +#define CLK_TOP_ATB_SEL 76 +#define CLK_TOP_HIF_SEL 77 +#define CLK_TOP_AUDIO_SEL 78 +#define CLK_TOP_U2_SEL 79 +#define CLK_TOP_AUD1_SEL 80 +#define CLK_TOP_AUD2_SEL 81 +#define CLK_TOP_IRRX_SEL 82 +#define CLK_TOP_IRTX_SEL 83 +#define CLK_TOP_ASM_L_SEL 84 +#define CLK_TOP_ASM_M_SEL 85 +#define CLK_TOP_ASM_H_SEL 86 +#define CLK_TOP_APLL1_SEL 87 +#define CLK_TOP_APLL2_SEL 88 +#define CLK_TOP_I2S0_MCK_SEL 89 +#define CLK_TOP_I2S1_MCK_SEL 90 +#define CLK_TOP_I2S2_MCK_SEL 91 +#define CLK_TOP_I2S3_MCK_SEL 92 +#define CLK_TOP_APLL1_DIV 93 +#define CLK_TOP_APLL2_DIV 94 +#define CLK_TOP_I2S0_MCK_DIV 95 +#define CLK_TOP_I2S1_MCK_DIV 96 +#define CLK_TOP_I2S2_MCK_DIV 97 +#define CLK_TOP_I2S3_MCK_DIV 98 +#define CLK_TOP_A1SYS_HP_DIV 99 +#define CLK_TOP_A2SYS_HP_DIV 100 +#define CLK_TOP_APLL1_DIV_PD 101 +#define CLK_TOP_APLL2_DIV_PD 102 +#define CLK_TOP_I2S0_MCK_DIV_PD 103 +#define CLK_TOP_I2S1_MCK_DIV_PD 104 +#define CLK_TOP_I2S2_MCK_DIV_PD 105 +#define CLK_TOP_I2S3_MCK_DIV_PD 106 + +/* INFRACFG */ + +#define CLK_INFRA_DBGCLK_PD 0 +#define CLK_INFRA_TRNG 1 +#define CLK_INFRA_AUDIO_PD 2 +#define CLK_INFRA_IRRX_PD 3 +#define CLK_INFRA_APXGPT_PD 4 +#define CLK_INFRA_PMIC_PD 5 + +/* PERICFG */ + +#define CLK_PERI_THERM_PD 0 +#define CLK_PERI_PWM1_PD 1 +#define CLK_PERI_PWM2_PD 2 +#define CLK_PERI_PWM3_PD 3 +#define CLK_PERI_PWM4_PD 4 +#define CLK_PERI_PWM5_PD 5 +#define CLK_PERI_PWM6_PD 6 +#define CLK_PERI_PWM7_PD 7 +#define CLK_PERI_PWM_PD 8 +#define CLK_PERI_AP_DMA_PD 9 +#define CLK_PERI_MSDC30_0_PD 10 +#define CLK_PERI_MSDC30_1_PD 11 +#define CLK_PERI_UART0_PD 12 +#define CLK_PERI_UART1_PD 13 +#define CLK_PERI_UART2_PD 14 +#define CLK_PERI_UART3_PD 15 +#define CLK_PERI_BTIF_PD 16 +#define CLK_PERI_I2C0_PD 17 +#define CLK_PERI_I2C1_PD 18 +#define CLK_PERI_I2C2_PD 19 +#define CLK_PERI_SPI1_PD 20 +#define CLK_PERI_AUXADC_PD 21 +#define CLK_PERI_SPI0_PD 22 +#define CLK_PERI_SNFI_PD 23 +#define CLK_PERI_NFI_PD 24 +#define CLK_PERI_NFIECC_PD 25 +#define CLK_PERI_FLASH_PD 26 +#define CLK_PERI_IRTX_PD 27 + +/* APMIXEDSYS */ + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIV2PLL 2 +#define CLK_APMIXED_ETH1PLL 3 +#define CLK_APMIXED_ETH2PLL 4 +#define CLK_APMIXED_AUD1PLL 5 +#define CLK_APMIXED_AUD2PLL 6 +#define CLK_APMIXED_TRGPLL 7 +#define CLK_APMIXED_SGMIPLL 8 + +/* AUDIOSYS */ + +#define CLK_AUDIO_AFE 0 +#define CLK_AUDIO_HDMI 1 +#define CLK_AUDIO_SPDF 2 +#define CLK_AUDIO_APLL 3 +#define CLK_AUDIO_I2SIN1 4 +#define CLK_AUDIO_I2SIN2 5 +#define CLK_AUDIO_I2SIN3 6 +#define CLK_AUDIO_I2SIN4 7 +#define CLK_AUDIO_I2SO1 8 +#define CLK_AUDIO_I2SO2 9 +#define CLK_AUDIO_I2SO3 10 +#define CLK_AUDIO_I2SO4 11 +#define CLK_AUDIO_ASRCI1 12 +#define CLK_AUDIO_ASRCI2 13 +#define CLK_AUDIO_ASRCO1 14 +#define CLK_AUDIO_ASRCO2 15 +#define CLK_AUDIO_INTDIR 16 +#define CLK_AUDIO_A1SYS 17 +#define CLK_AUDIO_A2SYS 18 +#define CLK_AUDIO_UL1 19 +#define CLK_AUDIO_UL2 20 +#define CLK_AUDIO_UL3 21 +#define CLK_AUDIO_UL4 22 +#define CLK_AUDIO_UL5 23 +#define CLK_AUDIO_UL6 24 +#define CLK_AUDIO_DL1 25 +#define CLK_AUDIO_DL2 26 +#define CLK_AUDIO_DL3 27 +#define CLK_AUDIO_DL4 28 +#define CLK_AUDIO_DL5 29 +#define CLK_AUDIO_DL6 30 +#define CLK_AUDIO_DLMCH 31 +#define CLK_AUDIO_ARB1 32 +#define CLK_AUDIO_AWB 33 +#define CLK_AUDIO_AWB3 34 +#define CLK_AUDIO_DAI 35 +#define CLK_AUDIO_MOD 36 +#define CLK_AUDIO_ASRCI3 37 +#define CLK_AUDIO_ASRCI4 38 +#define CLK_AUDIO_ASRCO3 39 +#define CLK_AUDIO_ASRCO4 40 +#define CLK_AUDIO_MEM_ASRC1 41 +#define CLK_AUDIO_MEM_ASRC2 42 +#define CLK_AUDIO_MEM_ASRC3 43 +#define CLK_AUDIO_MEM_ASRC4 44 +#define CLK_AUDIO_MEM_ASRC5 45 +#define CLK_AUDIO_AFE_CONN 46 +#define CLK_AUDIO_NR_CLK 47 + +/* SSUSBSYS */ + +#define CLK_SSUSB_U2_PHY_1P_EN 0 +#define CLK_SSUSB_U2_PHY_EN 1 +#define CLK_SSUSB_REF_EN 2 +#define CLK_SSUSB_SYS_EN 3 +#define CLK_SSUSB_MCU_EN 4 +#define CLK_SSUSB_DMA_EN 5 +#define CLK_SSUSB_NR_CLK 6 + +/* PCIESYS */ + +#define CLK_PCIE_P1_AUX_EN 0 +#define CLK_PCIE_P1_OBFF_EN 1 +#define CLK_PCIE_P1_AHB_EN 2 +#define CLK_PCIE_P1_AXI_EN 3 +#define CLK_PCIE_P1_MAC_EN 4 +#define CLK_PCIE_P1_PIPE_EN 5 +#define CLK_PCIE_P0_AUX_EN 6 +#define CLK_PCIE_P0_OBFF_EN 7 +#define CLK_PCIE_P0_AHB_EN 8 +#define CLK_PCIE_P0_AXI_EN 9 +#define CLK_PCIE_P0_MAC_EN 10 +#define CLK_PCIE_P0_PIPE_EN 11 +#define CLK_SATA_AHB_EN 12 +#define CLK_SATA_AXI_EN 13 +#define CLK_SATA_ASIC_EN 14 +#define CLK_SATA_RBC_EN 15 +#define CLK_SATA_PM_EN 16 +#define CLK_PCIE_NR_CLK 17 + +/* ETHSYS */ + +#define CLK_ETH_HSDMA_EN 0 +#define CLK_ETH_ESW_EN 1 +#define CLK_ETH_GP2_EN 2 +#define CLK_ETH_GP1_EN 3 +#define CLK_ETH_GP0_EN 4 + +/* SGMIISYS */ + +#define CLK_SGMII_TX250M_EN 0 +#define CLK_SGMII_RX250M_EN 1 +#define CLK_SGMII_CDR_REF 2 +#define CLK_SGMII_CDR_FB 3 + +#endif /* _DT_BINDINGS_CLK_MT7622_H */ + diff --git a/roms/u-boot/include/dt-bindings/clock/mt7623-clk.h b/roms/u-boot/include/dt-bindings/clock/mt7623-clk.h new file mode 100644 index 000000000..71ced1593 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/mt7623-clk.h @@ -0,0 +1,413 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_CLK_MT2701_H +#define _DT_BINDINGS_CLK_MT2701_H + +/* TOPCKGEN */ +#define CLK_TOP_FCLKS_OFF 0 + +#define CLK_TOP_DPI 0 +#define CLK_TOP_DMPLL 1 +#define CLK_TOP_VENCPLL 2 +#define CLK_TOP_HDMI_0_PIX340M 3 +#define CLK_TOP_HDMI_0_DEEP340M 4 +#define CLK_TOP_HDMI_0_PLL340M 5 +#define CLK_TOP_HADDS2_FB 6 +#define CLK_TOP_WBG_DIG_416M 7 +#define CLK_TOP_DSI0_LNTC_DSI 8 +#define CLK_TOP_HDMI_SCL_RX 9 +#define CLK_TOP_32K_EXTERNAL 10 +#define CLK_TOP_HDMITX_CLKDIG_CTS 11 +#define CLK_TOP_AUD_EXT1 12 +#define CLK_TOP_AUD_EXT2 13 +#define CLK_TOP_NFI1X_PAD 14 + +#define CLK_TOP_SYSPLL 15 +#define CLK_TOP_SYSPLL_D2 16 +#define CLK_TOP_SYSPLL_D3 17 +#define CLK_TOP_SYSPLL_D5 18 +#define CLK_TOP_SYSPLL_D7 19 +#define CLK_TOP_SYSPLL1_D2 20 +#define CLK_TOP_SYSPLL1_D4 21 +#define CLK_TOP_SYSPLL1_D8 22 +#define CLK_TOP_SYSPLL1_D16 23 +#define CLK_TOP_SYSPLL2_D2 24 +#define CLK_TOP_SYSPLL2_D4 25 +#define CLK_TOP_SYSPLL2_D8 26 +#define CLK_TOP_SYSPLL3_D2 27 +#define CLK_TOP_SYSPLL3_D4 28 +#define CLK_TOP_SYSPLL4_D2 29 +#define CLK_TOP_SYSPLL4_D4 30 +#define CLK_TOP_UNIVPLL 31 +#define CLK_TOP_UNIVPLL_D2 32 +#define CLK_TOP_UNIVPLL_D3 33 +#define CLK_TOP_UNIVPLL_D5 34 +#define CLK_TOP_UNIVPLL_D7 35 +#define CLK_TOP_UNIVPLL_D26 36 +#define CLK_TOP_UNIVPLL_D52 37 +#define CLK_TOP_UNIVPLL_D108 38 +#define CLK_TOP_USB_PHY48M 39 +#define CLK_TOP_UNIVPLL1_D2 40 +#define CLK_TOP_UNIVPLL1_D4 41 +#define CLK_TOP_UNIVPLL1_D8 42 +#define CLK_TOP_UNIVPLL2_D2 43 +#define CLK_TOP_UNIVPLL2_D4 44 +#define CLK_TOP_UNIVPLL2_D8 45 +#define CLK_TOP_UNIVPLL2_D16 46 +#define CLK_TOP_UNIVPLL2_D32 47 +#define CLK_TOP_UNIVPLL3_D2 48 +#define CLK_TOP_UNIVPLL3_D4 49 +#define CLK_TOP_UNIVPLL3_D8 50 +#define CLK_TOP_MSDCPLL 51 +#define CLK_TOP_MSDCPLL_D2 52 +#define CLK_TOP_MSDCPLL_D4 53 +#define CLK_TOP_MSDCPLL_D8 54 +#define CLK_TOP_MMPLL 55 +#define CLK_TOP_MMPLL_D2 56 +#define CLK_TOP_DMPLL_D2 57 +#define CLK_TOP_DMPLL_D4 58 +#define CLK_TOP_DMPLL_X2 59 +#define CLK_TOP_TVDPLL 60 +#define CLK_TOP_TVDPLL_D2 61 +#define CLK_TOP_TVDPLL_D4 62 +#define CLK_TOP_VDECPLL 63 +#define CLK_TOP_TVD2PLL 64 +#define CLK_TOP_TVD2PLL_D2 65 +#define CLK_TOP_MIPIPLL 66 +#define CLK_TOP_MIPIPLL_D2 67 +#define CLK_TOP_MIPIPLL_D4 68 +#define CLK_TOP_HDMIPLL 69 +#define CLK_TOP_HDMIPLL_D2 70 +#define CLK_TOP_HDMIPLL_D3 71 +#define CLK_TOP_ARMPLL_1P3G 72 +#define CLK_TOP_AUDPLL 73 +#define CLK_TOP_AUDPLL_D4 74 +#define CLK_TOP_AUDPLL_D8 75 +#define CLK_TOP_AUDPLL_D16 76 +#define CLK_TOP_AUDPLL_D24 77 +#define CLK_TOP_AUD1PLL_98M 78 +#define CLK_TOP_AUD2PLL_90M 79 +#define CLK_TOP_HADDS2PLL_98M 80 +#define CLK_TOP_HADDS2PLL_294M 81 +#define CLK_TOP_ETHPLL_500M 82 +#define CLK_TOP_CLK26M_D8 83 +#define CLK_TOP_32K_INTERNAL 84 +#define CLK_TOP_AXISEL_D4 85 +#define CLK_TOP_8BDAC 86 + +#define CLK_TOP_AXI_SEL 87 +#define CLK_TOP_MEM_SEL 88 +#define CLK_TOP_DDRPHYCFG_SEL 89 +#define CLK_TOP_MM_SEL 90 +#define CLK_TOP_PWM_SEL 91 +#define CLK_TOP_VDEC_SEL 92 +#define CLK_TOP_MFG_SEL 93 +#define CLK_TOP_CAMTG_SEL 94 +#define CLK_TOP_UART_SEL 95 +#define CLK_TOP_SPI0_SEL 96 +#define CLK_TOP_USB20_SEL 97 +#define CLK_TOP_MSDC30_0_SEL 98 +#define CLK_TOP_MSDC30_1_SEL 99 +#define CLK_TOP_MSDC30_2_SEL 100 +#define CLK_TOP_AUDIO_SEL 101 +#define CLK_TOP_AUDINTBUS_SEL 102 +#define CLK_TOP_PMICSPI_SEL 103 +#define CLK_TOP_SCP_SEL 104 +#define CLK_TOP_DPI0_SEL 105 +#define CLK_TOP_DPI1_SEL 106 +#define CLK_TOP_TVE_SEL 107 +#define CLK_TOP_HDMI_SEL 108 +#define CLK_TOP_APLL_SEL 109 +#define CLK_TOP_RTC_SEL 110 +#define CLK_TOP_NFI2X_SEL 111 +#define CLK_TOP_EMMC_HCLK_SEL 112 +#define CLK_TOP_FLASH_SEL 113 +#define CLK_TOP_DI_SEL 114 +#define CLK_TOP_NR_SEL 115 +#define CLK_TOP_OSD_SEL 116 +#define CLK_TOP_HDMIRX_BIST_SEL 117 +#define CLK_TOP_INTDIR_SEL 118 +#define CLK_TOP_ASM_I_SEL 119 +#define CLK_TOP_ASM_M_SEL 120 +#define CLK_TOP_ASM_H_SEL 121 +#define CLK_TOP_MS_CARD_SEL 122 +#define CLK_TOP_ETHIF_SEL 123 +#define CLK_TOP_HDMIRX26_24_SEL 124 +#define CLK_TOP_MSDC30_3_SEL 125 +#define CLK_TOP_CMSYS_SEL 126 +#define CLK_TOP_SPI1_SEL 127 +#define CLK_TOP_SPI2_SEL 128 +#define CLK_TOP_8BDAC_SEL 129 +#define CLK_TOP_AUD2DVD_SEL 130 +#define CLK_TOP_PADMCLK_SEL 131 +#define CLK_TOP_AUD_MUX1_SEL 132 +#define CLK_TOP_AUD_MUX2_SEL 133 +#define CLK_TOP_AUDPLL_MUX_SEL 134 +#define CLK_TOP_AUD_K1_SRC_SEL 135 +#define CLK_TOP_AUD_K2_SRC_SEL 136 +#define CLK_TOP_AUD_K3_SRC_SEL 137 +#define CLK_TOP_AUD_K4_SRC_SEL 138 +#define CLK_TOP_AUD_K5_SRC_SEL 139 +#define CLK_TOP_AUD_K6_SRC_SEL 140 + +#define CLK_TOP_AUD_EXTCK1_DIV 141 +#define CLK_TOP_AUD_EXTCK2_DIV 142 +#define CLK_TOP_AUD_MUX1_DIV 143 +#define CLK_TOP_AUD_MUX2_DIV 144 +#define CLK_TOP_AUD_K1_SRC_DIV 145 +#define CLK_TOP_AUD_K2_SRC_DIV 146 +#define CLK_TOP_AUD_K3_SRC_DIV 147 +#define CLK_TOP_AUD_K4_SRC_DIV 148 +#define CLK_TOP_AUD_K5_SRC_DIV 149 +#define CLK_TOP_AUD_K6_SRC_DIV 150 +#define CLK_TOP_AUD_48K_TIMING 151 +#define CLK_TOP_AUD_44K_TIMING 152 +#define CLK_TOP_AUD_I2S1_MCLK 153 +#define CLK_TOP_AUD_I2S2_MCLK 154 +#define CLK_TOP_AUD_I2S3_MCLK 155 +#define CLK_TOP_AUD_I2S4_MCLK 156 +#define CLK_TOP_AUD_I2S5_MCLK 157 +#define CLK_TOP_AUD_I2S6_MCLK 158 +#define CLK_TOP_NR 159 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIVPLL 2 +#define CLK_APMIXED_MMPLL 3 +#define CLK_APMIXED_MSDCPLL 4 +#define CLK_APMIXED_TVDPLL 5 +#define CLK_APMIXED_AUD1PLL 6 +#define CLK_APMIXED_TRGPLL 7 +#define CLK_APMIXED_ETHPLL 8 +#define CLK_APMIXED_VDECPLL 9 +#define CLK_APMIXED_HADDS2PLL 10 +#define CLK_APMIXED_AUD2PLL 11 +#define CLK_APMIXED_TVD2PLL 12 +#define CLK_APMIXED_NR 13 + +/* INFRACFG */ +#define CLK_INFRA_DBG 0 +#define CLK_INFRA_SMI 1 +#define CLK_INFRA_QAXI_CM4 2 +#define CLK_INFRA_AUD_SPLIN_B 3 +#define CLK_INFRA_AUDIO 4 +#define CLK_INFRA_EFUSE 5 +#define CLK_INFRA_L2C_SRAM 6 +#define CLK_INFRA_M4U 7 +#define CLK_INFRA_CONNMCU 8 +#define CLK_INFRA_TRNG 9 +#define CLK_INFRA_RAMBUFIF 10 +#define CLK_INFRA_CPUM 11 +#define CLK_INFRA_KP 12 +#define CLK_INFRA_CEC 13 +#define CLK_INFRA_IRRX 14 +#define CLK_INFRA_PMICSPI 15 +#define CLK_INFRA_PMICWRAP 16 +#define CLK_INFRA_DDCCI 17 +#define CLK_INFRA_CPUSEL 18 +#define CLK_INFRA_NR 19 + +/* PERICFG */ +#define CLK_PERI_NFI 0 +#define CLK_PERI_THERM 1 +#define CLK_PERI_PWM1 2 +#define CLK_PERI_PWM2 3 +#define CLK_PERI_PWM3 4 +#define CLK_PERI_PWM4 5 +#define CLK_PERI_PWM5 6 +#define CLK_PERI_PWM6 7 +#define CLK_PERI_PWM7 8 +#define CLK_PERI_PWM 9 +#define CLK_PERI_USB0 10 +#define CLK_PERI_USB1 11 +#define CLK_PERI_AP_DMA 12 +#define CLK_PERI_MSDC30_0 13 +#define CLK_PERI_MSDC30_1 14 +#define CLK_PERI_MSDC30_2 15 +#define CLK_PERI_MSDC30_3 16 +#define CLK_PERI_MSDC50_3 17 +#define CLK_PERI_NLI 18 +#define CLK_PERI_UART0 19 +#define CLK_PERI_UART1 20 +#define CLK_PERI_UART2 21 +#define CLK_PERI_UART3 22 +#define CLK_PERI_BTIF 23 +#define CLK_PERI_I2C0 24 +#define CLK_PERI_I2C1 25 +#define CLK_PERI_I2C2 26 +#define CLK_PERI_I2C3 27 +#define CLK_PERI_AUXADC 28 +#define CLK_PERI_SPI0 39 +#define CLK_PERI_ETH 30 +#define CLK_PERI_USB0_MCU 31 + +#define CLK_PERI_USB1_MCU 32 +#define CLK_PERI_USB_SLV 33 +#define CLK_PERI_GCPU 34 +#define CLK_PERI_NFI_ECC 35 +#define CLK_PERI_NFI_PAD 36 +#define CLK_PERI_FLASH 37 +#define CLK_PERI_HOST89_INT 38 +#define CLK_PERI_HOST89_SPI 39 +#define CLK_PERI_HOST89_DVD 40 +#define CLK_PERI_SPI1 41 +#define CLK_PERI_SPI2 42 +#define CLK_PERI_FCI 43 +#define CLK_PERI_NR 44 + +/* AUDIO */ +#define CLK_AUD_AFE 0 +#define CLK_AUD_LRCK_DETECT 1 +#define CLK_AUD_I2S 2 +#define CLK_AUD_APLL_TUNER 3 +#define CLK_AUD_HDMI 4 +#define CLK_AUD_SPDF 5 +#define CLK_AUD_SPDF2 6 +#define CLK_AUD_APLL 7 +#define CLK_AUD_TML 8 +#define CLK_AUD_AHB_IDLE_EXT 9 +#define CLK_AUD_AHB_IDLE_INT 10 + +#define CLK_AUD_I2SIN1 11 +#define CLK_AUD_I2SIN2 12 +#define CLK_AUD_I2SIN3 13 +#define CLK_AUD_I2SIN4 14 +#define CLK_AUD_I2SIN5 15 +#define CLK_AUD_I2SIN6 16 +#define CLK_AUD_I2SO1 17 +#define CLK_AUD_I2SO2 18 +#define CLK_AUD_I2SO3 19 +#define CLK_AUD_I2SO4 20 +#define CLK_AUD_I2SO5 21 +#define CLK_AUD_I2SO6 22 +#define CLK_AUD_ASRCI1 23 +#define CLK_AUD_ASRCI2 24 +#define CLK_AUD_ASRCO1 25 +#define CLK_AUD_ASRCO2 26 +#define CLK_AUD_ASRC11 27 +#define CLK_AUD_ASRC12 28 +#define CLK_AUD_HDMIRX 29 +#define CLK_AUD_INTDIR 30 +#define CLK_AUD_A1SYS 31 +#define CLK_AUD_A2SYS 32 +#define CLK_AUD_AFE_CONN 33 +#define CLK_AUD_AFE_PCMIF 34 +#define CLK_AUD_AFE_MRGIF 35 + +#define CLK_AUD_MMIF_UL1 36 +#define CLK_AUD_MMIF_UL2 37 +#define CLK_AUD_MMIF_UL3 38 +#define CLK_AUD_MMIF_UL4 39 +#define CLK_AUD_MMIF_UL5 40 +#define CLK_AUD_MMIF_UL6 41 +#define CLK_AUD_MMIF_DL1 42 +#define CLK_AUD_MMIF_DL2 43 +#define CLK_AUD_MMIF_DL3 44 +#define CLK_AUD_MMIF_DL4 45 +#define CLK_AUD_MMIF_DL5 46 +#define CLK_AUD_MMIF_DL6 47 +#define CLK_AUD_MMIF_DLMCH 48 +#define CLK_AUD_MMIF_ARB1 49 +#define CLK_AUD_MMIF_AWB1 50 +#define CLK_AUD_MMIF_AWB2 51 +#define CLK_AUD_MMIF_DAI 52 + +#define CLK_AUD_DMIC1 53 +#define CLK_AUD_DMIC2 54 +#define CLK_AUD_ASRCI3 55 +#define CLK_AUD_ASRCI4 56 +#define CLK_AUD_ASRCI5 57 +#define CLK_AUD_ASRCI6 58 +#define CLK_AUD_ASRCO3 59 +#define CLK_AUD_ASRCO4 60 +#define CLK_AUD_ASRCO5 61 +#define CLK_AUD_ASRCO6 62 +#define CLK_AUD_MEM_ASRC1 63 +#define CLK_AUD_MEM_ASRC2 64 +#define CLK_AUD_MEM_ASRC3 65 +#define CLK_AUD_MEM_ASRC4 66 +#define CLK_AUD_MEM_ASRC5 67 +#define CLK_AUD_DSD_ENC 68 +#define CLK_AUD_ASRC_BRG 60 +#define CLK_AUD_NR 70 + +/* MMSYS */ +#define CLK_MM_SMI_COMMON 0 +#define CLK_MM_SMI_LARB0 1 +#define CLK_MM_CMDQ 2 +#define CLK_MM_MUTEX 3 +#define CLK_MM_DISP_COLOR 4 +#define CLK_MM_DISP_BLS 5 +#define CLK_MM_DISP_WDMA 6 +#define CLK_MM_DISP_RDMA 7 +#define CLK_MM_DISP_OVL 8 +#define CLK_MM_MDP_TDSHP 9 +#define CLK_MM_MDP_WROT 10 +#define CLK_MM_MDP_WDMA 11 +#define CLK_MM_MDP_RSZ1 12 +#define CLK_MM_MDP_RSZ0 13 +#define CLK_MM_MDP_RDMA 14 +#define CLK_MM_MDP_BLS_26M 15 +#define CLK_MM_CAM_MDP 16 +#define CLK_MM_FAKE_ENG 17 +#define CLK_MM_MUTEX_32K 18 +#define CLK_MM_DISP_RDMA1 19 +#define CLK_MM_DISP_UFOE 20 + +#define CLK_MM_DSI_ENGINE 21 +#define CLK_MM_DSI_DIG 22 +#define CLK_MM_DPI_DIGL 23 +#define CLK_MM_DPI_ENGINE 24 +#define CLK_MM_DPI1_DIGL 25 +#define CLK_MM_DPI1_ENGINE 26 +#define CLK_MM_TVE_OUTPUT 27 +#define CLK_MM_TVE_INPUT 28 +#define CLK_MM_HDMI_PIXEL 29 +#define CLK_MM_HDMI_PLL 30 +#define CLK_MM_HDMI_AUDIO 31 +#define CLK_MM_HDMI_SPDIF 32 +#define CLK_MM_TVE_FMM 33 +#define CLK_MM_NR 34 + +/* IMGSYS */ +#define CLK_IMG_SMI_COMM 0 +#define CLK_IMG_RESZ 1 +#define CLK_IMG_JPGDEC_SMI 2 +#define CLK_IMG_JPGDEC 3 +#define CLK_IMG_VENC_LT 4 +#define CLK_IMG_VENC 5 +#define CLK_IMG_NR 6 + +/* VDEC */ +#define CLK_VDEC_CKGEN 0 +#define CLK_VDEC_LARB 1 +#define CLK_VDEC_NR 2 + +/* HIFSYS */ +#define CLK_HIFSYS_USB0PHY 0 +#define CLK_HIFSYS_USB1PHY 1 +#define CLK_HIFSYS_PCIE0 2 +#define CLK_HIFSYS_PCIE1 3 +#define CLK_HIFSYS_PCIE2 4 +#define CLK_HIFSYS_NR 5 + +/* ETHSYS */ +#define CLK_ETHSYS_HSDMA 0 +#define CLK_ETHSYS_ESW 1 +#define CLK_ETHSYS_GP2 2 +#define CLK_ETHSYS_GP1 3 +#define CLK_ETHSYS_PCM 4 +#define CLK_ETHSYS_GDMA 5 +#define CLK_ETHSYS_I2S 6 +#define CLK_ETHSYS_CRYPTO 7 +#define CLK_ETHSYS_NR 8 + +/* G3DSYS */ +#define CLK_G3DSYS_CORE 0 +#define CLK_G3DSYS_NR 1 + +#endif /* _DT_BINDINGS_CLK_MT2701_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/mt7628-clk.h b/roms/u-boot/include/dt-bindings/clock/mt7628-clk.h new file mode 100644 index 000000000..b5866fdc0 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/mt7628-clk.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * Author: Weijie Gao + */ + +#ifndef _DT_BINDINGS_MT7628_CLK_H_ +#define _DT_BINDINGS_MT7628_CLK_H_ + +/* Base clocks */ +#define CLK_SYS 34 +#define CLK_CPU 33 +#define CLK_XTAL 32 + +/* Peripheral clocks */ +#define CLK_PWM 31 +#define CLK_SDXC 30 +#define CLK_CRYPTO 29 +#define CLK_MIPS_CNT 28 +#define CLK_PCIE 26 +#define CLK_UPHY 25 +#define CLK_ETH 23 +#define CLK_UART2 20 +#define CLK_UART1 19 +#define CLK_SPI 18 +#define CLK_I2S 17 +#define CLK_I2C 16 +#define CLK_GDMA 14 +#define CLK_PIO 13 +#define CLK_UART0 12 +#define CLK_PCM 11 +#define CLK_MC 10 +#define CLK_INTC 9 +#define CLK_TIMER 8 + +#endif /* _DT_BINDINGS_MT7628_CLK_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/mt7629-clk.h b/roms/u-boot/include/dt-bindings/clock/mt7629-clk.h new file mode 100644 index 000000000..0bbfbfa74 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/mt7629-clk.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_CLK_MT7629_H +#define _DT_BINDINGS_CLK_MT7629_H + +/* TOPCKGEN */ +#define CLK_TOP_FCLKS_OFF 0 + +#define CLK_TOP_TO_U2_PHY 0 +#define CLK_TOP_TO_U2_PHY_1P 1 +#define CLK_TOP_PCIE0_PIPE_EN 2 +#define CLK_TOP_PCIE1_PIPE_EN 3 +#define CLK_TOP_SSUSB_TX250M 4 +#define CLK_TOP_SSUSB_EQ_RX250M 5 +#define CLK_TOP_SSUSB_CDR_REF 6 +#define CLK_TOP_SSUSB_CDR_FB 7 +#define CLK_TOP_SATA_ASIC 8 +#define CLK_TOP_SATA_RBC 9 + +#define CLK_TOP_TO_USB3_SYS 10 +#define CLK_TOP_P1_1MHZ 11 +#define CLK_TOP_4MHZ 12 +#define CLK_TOP_P0_1MHZ 13 +#define CLK_TOP_ETH_500M 14 +#define CLK_TOP_TXCLK_SRC_PRE 15 +#define CLK_TOP_RTC 16 +#define CLK_TOP_PWM_QTR_26M 17 +#define CLK_TOP_CPUM_TCK_IN 18 +#define CLK_TOP_TO_USB3_DA_TOP 19 +#define CLK_TOP_MEMPLL 20 +#define CLK_TOP_DMPLL 21 +#define CLK_TOP_DMPLL_D4 22 +#define CLK_TOP_DMPLL_D8 23 +#define CLK_TOP_SYSPLL_D2 24 +#define CLK_TOP_SYSPLL1_D2 25 +#define CLK_TOP_SYSPLL1_D4 26 +#define CLK_TOP_SYSPLL1_D8 27 +#define CLK_TOP_SYSPLL1_D16 28 +#define CLK_TOP_SYSPLL2_D2 29 +#define CLK_TOP_SYSPLL2_D4 30 +#define CLK_TOP_SYSPLL2_D8 31 +#define CLK_TOP_SYSPLL_D5 32 +#define CLK_TOP_SYSPLL3_D2 33 +#define CLK_TOP_SYSPLL3_D4 34 +#define CLK_TOP_SYSPLL_D7 35 +#define CLK_TOP_SYSPLL4_D2 36 +#define CLK_TOP_SYSPLL4_D4 37 +#define CLK_TOP_SYSPLL4_D16 38 +#define CLK_TOP_UNIVPLL 39 +#define CLK_TOP_UNIVPLL1_D2 40 +#define CLK_TOP_UNIVPLL1_D4 41 +#define CLK_TOP_UNIVPLL1_D8 42 +#define CLK_TOP_UNIVPLL_D3 43 +#define CLK_TOP_UNIVPLL2_D2 44 +#define CLK_TOP_UNIVPLL2_D4 45 +#define CLK_TOP_UNIVPLL2_D8 46 +#define CLK_TOP_UNIVPLL2_D16 47 +#define CLK_TOP_UNIVPLL_D5 48 +#define CLK_TOP_UNIVPLL3_D2 49 +#define CLK_TOP_UNIVPLL3_D4 50 +#define CLK_TOP_UNIVPLL3_D16 51 +#define CLK_TOP_UNIVPLL_D7 52 +#define CLK_TOP_UNIVPLL_D80_D4 53 +#define CLK_TOP_UNIV48M 54 +#define CLK_TOP_SGMIIPLL_D2 55 +#define CLK_TOP_CLKXTAL_D4 56 +#define CLK_TOP_HD_FAXI 57 +#define CLK_TOP_FAXI 58 +#define CLK_TOP_F_FAUD_INTBUS 59 +#define CLK_TOP_AP2WBHIF_HCLK 60 +#define CLK_TOP_10M_INFRAO 61 +#define CLK_TOP_MSDC30_1 62 +#define CLK_TOP_SPI 63 +#define CLK_TOP_SF 64 +#define CLK_TOP_FLASH 65 +#define CLK_TOP_TO_USB3_REF 66 +#define CLK_TOP_TO_USB3_MCU 67 +#define CLK_TOP_TO_USB3_DMA 68 +#define CLK_TOP_FROM_TOP_AHB 69 +#define CLK_TOP_FROM_TOP_AXI 70 +#define CLK_TOP_PCIE1_MAC_EN 71 +#define CLK_TOP_PCIE0_MAC_EN 72 + +#define CLK_TOP_AXI_SEL 73 +#define CLK_TOP_MEM_SEL 74 +#define CLK_TOP_DDRPHYCFG_SEL 75 +#define CLK_TOP_ETH_SEL 76 +#define CLK_TOP_PWM_SEL 77 +#define CLK_TOP_F10M_REF_SEL 78 +#define CLK_TOP_NFI_INFRA_SEL 79 +#define CLK_TOP_FLASH_SEL 80 +#define CLK_TOP_UART_SEL 81 +#define CLK_TOP_SPI0_SEL 82 +#define CLK_TOP_SPI1_SEL 83 +#define CLK_TOP_MSDC50_0_SEL 84 +#define CLK_TOP_MSDC30_0_SEL 85 +#define CLK_TOP_MSDC30_1_SEL 86 +#define CLK_TOP_AP2WBMCU_SEL 87 +#define CLK_TOP_AP2WBHIF_SEL 88 +#define CLK_TOP_AUDIO_SEL 89 +#define CLK_TOP_AUD_INTBUS_SEL 90 +#define CLK_TOP_PMICSPI_SEL 91 +#define CLK_TOP_SCP_SEL 92 +#define CLK_TOP_ATB_SEL 93 +#define CLK_TOP_HIF_SEL 94 +#define CLK_TOP_SATA_SEL 95 +#define CLK_TOP_U2_SEL 96 +#define CLK_TOP_AUD1_SEL 97 +#define CLK_TOP_AUD2_SEL 98 +#define CLK_TOP_IRRX_SEL 99 +#define CLK_TOP_IRTX_SEL 100 +#define CLK_TOP_SATA_MCU_SEL 101 +#define CLK_TOP_PCIE0_MCU_SEL 102 +#define CLK_TOP_PCIE1_MCU_SEL 103 +#define CLK_TOP_SSUSB_MCU_SEL 104 +#define CLK_TOP_CRYPTO_SEL 105 +#define CLK_TOP_SGMII_REF_1_SEL 106 +#define CLK_TOP_10M_SEL 107 +#define CLK_TOP_NR_CLK 108 + +/* INFRACFG */ +#define CLK_INFRA_MUX1_SEL 0 +#define CLK_INFRA_DBGCLK_PD 1 +#define CLK_INFRA_TRNG_PD 2 +#define CLK_INFRA_DEVAPC_PD 3 +#define CLK_INFRA_APXGPT_PD 4 +#define CLK_INFRA_SEJ_PD 5 +#define CLK_INFRA_NR_CLK 6 + +/* PERICFG */ +#define CLK_PERIBUS_SEL 0 +#define CLK_PERI_PWM1_PD 1 +#define CLK_PERI_PWM2_PD 2 +#define CLK_PERI_PWM3_PD 3 +#define CLK_PERI_PWM4_PD 4 +#define CLK_PERI_PWM5_PD 5 +#define CLK_PERI_PWM6_PD 6 +#define CLK_PERI_PWM7_PD 7 +#define CLK_PERI_PWM_PD 8 +#define CLK_PERI_AP_DMA_PD 9 +#define CLK_PERI_MSDC30_1_PD 10 +#define CLK_PERI_UART0_PD 11 +#define CLK_PERI_UART1_PD 12 +#define CLK_PERI_UART2_PD 13 +#define CLK_PERI_UART3_PD 14 +#define CLK_PERI_BTIF_PD 15 +#define CLK_PERI_I2C0_PD 16 +#define CLK_PERI_SPI0_PD 17 +#define CLK_PERI_SNFI_PD 18 +#define CLK_PERI_NFI_PD 19 +#define CLK_PERI_NFIECC_PD 20 +#define CLK_PERI_FLASH_PD 21 +#define CLK_PERI_NR_CLK 22 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIV2PLL 2 +#define CLK_APMIXED_ETH1PLL 3 +#define CLK_APMIXED_ETH2PLL 4 +#define CLK_APMIXED_SGMIPLL 5 +#define CLK_APMIXED_NR_CLK 6 + +/* SSUSBSYS */ +#define CLK_SSUSB_U2_PHY_1P_EN 0 +#define CLK_SSUSB_U2_PHY_EN 1 +#define CLK_SSUSB_REF_EN 2 +#define CLK_SSUSB_SYS_EN 3 +#define CLK_SSUSB_MCU_EN 4 +#define CLK_SSUSB_DMA_EN 5 +#define CLK_SSUSB_NR_CLK 6 + +/* PCIESYS */ +#define CLK_PCIE_P1_AUX_EN 0 +#define CLK_PCIE_P1_OBFF_EN 1 +#define CLK_PCIE_P1_AHB_EN 2 +#define CLK_PCIE_P1_AXI_EN 3 +#define CLK_PCIE_P1_MAC_EN 4 +#define CLK_PCIE_P1_PIPE_EN 5 +#define CLK_PCIE_P0_AUX_EN 6 +#define CLK_PCIE_P0_OBFF_EN 7 +#define CLK_PCIE_P0_AHB_EN 8 +#define CLK_PCIE_P0_AXI_EN 9 +#define CLK_PCIE_P0_MAC_EN 10 +#define CLK_PCIE_P0_PIPE_EN 11 +#define CLK_PCIE_NR_CLK 12 + +/* ETHSYS */ +#define CLK_ETH_FE_EN 0 +#define CLK_ETH_GP2_EN 1 +#define CLK_ETH_GP1_EN 2 +#define CLK_ETH_GP0_EN 3 +#define CLK_ETH_ESW_EN 4 +#define CLK_ETH_NR_CLK 5 + +/* SGMIISYS */ +#define CLK_SGMII_TX_EN 0 +#define CLK_SGMII_RX_EN 1 +#define CLK_SGMII_CDR_REF 2 +#define CLK_SGMII_CDR_FB 3 +#define CLK_SGMII_NR_CLK 4 + +#endif /* _DT_BINDINGS_CLK_MT7629_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/mt8183-clk.h b/roms/u-boot/include/dt-bindings/clock/mt8183-clk.h new file mode 100644 index 000000000..f7e6367ce --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/mt8183-clk.h @@ -0,0 +1,329 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Weiyi Lu + */ + +#ifndef _DT_BINDINGS_CLK_MT8183_H +#define _DT_BINDINGS_CLK_MT8183_H + +/* APMIXED */ +#define CLK_APMIXED_ARMPLL_LL 0 +#define CLK_APMIXED_ARMPLL_L 1 +#define CLK_APMIXED_CCIPLL 2 +#define CLK_APMIXED_MAINPLL 3 +#define CLK_APMIXED_UNIV2PLL 4 +#define CLK_APMIXED_MSDCPLL 5 +#define CLK_APMIXED_MMPLL 6 +#define CLK_APMIXED_MFGPLL 7 +#define CLK_APMIXED_TVDPLL 8 +#define CLK_APMIXED_APLL1 9 +#define CLK_APMIXED_APLL2 10 +#define CLK_APMIXED_SSUSB_26M 11 +#define CLK_APMIXED_APPLL_26M 12 +#define CLK_APMIXED_MIPIC0_26M 13 +#define CLK_APMIXED_MDPLLGP_26M 14 +#define CLK_APMIXED_MMSYS_26M 15 +#define CLK_APMIXED_UFS_26M 16 +#define CLK_APMIXED_MIPIC1_26M 17 +#define CLK_APMIXED_MEMPLL_26M 18 +#define CLK_APMIXED_CLKSQ_LVPLL_26M 19 +#define CLK_APMIXED_MIPID0_26M 20 +#define CLK_APMIXED_MIPID1_26M 21 +#define CLK_APMIXED_NR_CLK 22 + +/* TOPCKGEN */ +#define CLK_TOP_CLK26M 0 +#define CLK_TOP_ULPOSC 1 +#define CLK_TOP_UNIVP_192M 2 +#define CLK_TOP_CLK13M 3 +#define CLK_TOP_F26M_CK_D2 4 +#define CLK_TOP_SYSPLL_CK 5 +#define CLK_TOP_SYSPLL_D2 6 +#define CLK_TOP_SYSPLL_D3 7 +#define CLK_TOP_SYSPLL_D5 8 +#define CLK_TOP_SYSPLL_D7 9 +#define CLK_TOP_SYSPLL_D2_D2 10 +#define CLK_TOP_SYSPLL_D2_D4 11 +#define CLK_TOP_SYSPLL_D2_D8 12 +#define CLK_TOP_SYSPLL_D2_D16 13 +#define CLK_TOP_SYSPLL_D3_D2 14 +#define CLK_TOP_SYSPLL_D3_D4 15 +#define CLK_TOP_SYSPLL_D3_D8 16 +#define CLK_TOP_SYSPLL_D5_D2 17 +#define CLK_TOP_SYSPLL_D5_D4 18 +#define CLK_TOP_SYSPLL_D7_D2 19 +#define CLK_TOP_SYSPLL_D7_D4 20 +#define CLK_TOP_UNIVPLL_CK 21 +#define CLK_TOP_UNIVPLL_D2 22 +#define CLK_TOP_UNIVPLL_D3 23 +#define CLK_TOP_UNIVPLL_D5 24 +#define CLK_TOP_UNIVPLL_D7 25 +#define CLK_TOP_UNIVPLL_D2_D2 26 +#define CLK_TOP_UNIVPLL_D2_D4 27 +#define CLK_TOP_UNIVPLL_D2_D8 28 +#define CLK_TOP_UNIVPLL_D3_D2 29 +#define CLK_TOP_UNIVPLL_D3_D4 30 +#define CLK_TOP_UNIVPLL_D3_D8 31 +#define CLK_TOP_UNIVPLL_D5_D2 32 +#define CLK_TOP_UNIVPLL_D5_D4 33 +#define CLK_TOP_UNIVPLL_D5_D8 34 +#define CLK_TOP_UNIVP_192M_CK 35 +#define CLK_TOP_UNIVP_192M_D2 36 +#define CLK_TOP_UNIVP_192M_D4 37 +#define CLK_TOP_UNIVP_192M_D8 38 +#define CLK_TOP_UNIVP_192M_D16 39 +#define CLK_TOP_UNIVP_192M_D32 40 +#define CLK_TOP_APLL1_CK 41 +#define CLK_TOP_APLL1_D2 42 +#define CLK_TOP_APLL1_D4 43 +#define CLK_TOP_APLL1_D8 44 +#define CLK_TOP_APLL2_CK 45 +#define CLK_TOP_APLL2_D2 46 +#define CLK_TOP_APLL2_D4 47 +#define CLK_TOP_APLL2_D8 48 +#define CLK_TOP_TVDPLL_CK 49 +#define CLK_TOP_TVDPLL_D2 50 +#define CLK_TOP_TVDPLL_D4 51 +#define CLK_TOP_TVDPLL_D8 52 +#define CLK_TOP_TVDPLL_D16 53 +#define CLK_TOP_MMPLL_CK 54 +#define CLK_TOP_MMPLL_D4 55 +#define CLK_TOP_MMPLL_D4_D2 56 +#define CLK_TOP_MMPLL_D4_D4 57 +#define CLK_TOP_MMPLL_D5 58 +#define CLK_TOP_MMPLL_D5_D2 59 +#define CLK_TOP_MMPLL_D5_D4 60 +#define CLK_TOP_MMPLL_D6 61 +#define CLK_TOP_MMPLL_D7 62 +#define CLK_TOP_MFGPLL_CK 63 +#define CLK_TOP_MSDCPLL_CK 64 +#define CLK_TOP_MSDCPLL_D2 65 +#define CLK_TOP_MSDCPLL_D4 66 +#define CLK_TOP_MSDCPLL_D8 67 +#define CLK_TOP_MSDCPLL_D16 68 +#define CLK_TOP_AD_OSC_CK 69 +#define CLK_TOP_OSC_D2 70 +#define CLK_TOP_OSC_D4 71 +#define CLK_TOP_OSC_D8 72 +#define CLK_TOP_OSC_D16 73 +#define CLK_TOP_UNIVPLL 74 +#define CLK_TOP_UNIVPLL_D3_D16 75 +#define CLK_TOP_APLL12_DIV0 76 +#define CLK_TOP_APLL12_DIV1 77 +#define CLK_TOP_APLL12_DIV2 78 +#define CLK_TOP_APLL12_DIV3 79 +#define CLK_TOP_APLL12_DIV4 80 +#define CLK_TOP_APLL12_DIVB 81 +#define CLK_TOP_ARMPLL_DIV_PLL1 82 +#define CLK_TOP_ARMPLL_DIV_PLL2 83 +#define CLK_TOP_MUX_AXI 84 +#define CLK_TOP_MUX_MM 85 +#define CLK_TOP_MUX_IMG 86 +#define CLK_TOP_MUX_CAM 87 +#define CLK_TOP_MUX_DSP 88 +#define CLK_TOP_MUX_DSP1 89 +#define CLK_TOP_MUX_DSP2 90 +#define CLK_TOP_MUX_IPU_IF 91 +#define CLK_TOP_MUX_MFG 92 +#define CLK_TOP_MUX_F52M_MFG 93 +#define CLK_TOP_MUX_CAMTG 94 +#define CLK_TOP_MUX_CAMTG2 95 +#define CLK_TOP_MUX_CAMTG3 96 +#define CLK_TOP_MUX_CAMTG4 97 +#define CLK_TOP_MUX_UART 98 +#define CLK_TOP_MUX_SPI 99 +#define CLK_TOP_MUX_MSDC50_0_HCLK 100 +#define CLK_TOP_MUX_MSDC50_0 101 +#define CLK_TOP_MUX_MSDC30_1 102 +#define CLK_TOP_MUX_MSDC30_2 103 +#define CLK_TOP_MUX_AUDIO 104 +#define CLK_TOP_MUX_AUD_INTBUS 105 +#define CLK_TOP_MUX_PMICSPI 106 +#define CLK_TOP_MUX_FPWRAP_ULPOSC 107 +#define CLK_TOP_MUX_ATB 108 +#define CLK_TOP_MUX_SSPM 109 +#define CLK_TOP_MUX_DPI0 110 +#define CLK_TOP_MUX_SCAM 111 +#define CLK_TOP_MUX_DISP_PWM 112 +#define CLK_TOP_MUX_USB_TOP 113 +#define CLK_TOP_MUX_SSUSB_TOP_XHCI 114 +#define CLK_TOP_MUX_SPM 115 +#define CLK_TOP_MUX_I2C 116 +#define CLK_TOP_MUX_SCP 117 +#define CLK_TOP_MUX_SENINF 118 +#define CLK_TOP_MUX_DXCC 119 +#define CLK_TOP_MUX_AUD_ENG1 120 +#define CLK_TOP_MUX_AUD_ENG2 121 +#define CLK_TOP_MUX_FAES_UFSFDE 122 +#define CLK_TOP_MUX_FUFS 123 +#define CLK_TOP_MUX_AUD_1 124 +#define CLK_TOP_MUX_AUD_2 125 +#define CLK_TOP_MUX_APLL_I2S0 126 +#define CLK_TOP_MUX_APLL_I2S1 127 +#define CLK_TOP_MUX_APLL_I2S2 128 +#define CLK_TOP_MUX_APLL_I2S3 129 +#define CLK_TOP_MUX_APLL_I2S4 130 +#define CLK_TOP_MUX_APLL_I2S5 131 +#define CLK_TOP_NR_CLK 132 + +/* INFRACFG_AO */ +#define CLK_INFRA_PMIC_TMR 0 +#define CLK_INFRA_PMIC_AP 1 +#define CLK_INFRA_PMIC_MD 2 +#define CLK_INFRA_PMIC_CONN 3 +#define CLK_INFRA_SCPSYS 4 +#define CLK_INFRA_SEJ 5 +#define CLK_INFRA_APXGPT 6 +#define CLK_INFRA_ICUSB 7 +#define CLK_INFRA_GCE 8 +#define CLK_INFRA_THERM 9 +#define CLK_INFRA_I2C0 10 +#define CLK_INFRA_I2C1 11 +#define CLK_INFRA_I2C2 12 +#define CLK_INFRA_I2C3 13 +#define CLK_INFRA_PWM_HCLK 14 +#define CLK_INFRA_PWM1 15 +#define CLK_INFRA_PWM2 16 +#define CLK_INFRA_PWM3 17 +#define CLK_INFRA_PWM4 18 +#define CLK_INFRA_PWM 19 +#define CLK_INFRA_UART0 20 +#define CLK_INFRA_UART1 21 +#define CLK_INFRA_UART2 22 +#define CLK_INFRA_UART3 23 +#define CLK_INFRA_GCE_26M 24 +#define CLK_INFRA_CQ_DMA_FPC 25 +#define CLK_INFRA_BTIF 26 +#define CLK_INFRA_SPI0 27 +#define CLK_INFRA_MSDC0 28 +#define CLK_INFRA_MSDC1 29 +#define CLK_INFRA_MSDC2 30 +#define CLK_INFRA_MSDC0_SCK 31 +#define CLK_INFRA_DVFSRC 32 +#define CLK_INFRA_GCPU 33 +#define CLK_INFRA_TRNG 34 +#define CLK_INFRA_AUXADC 35 +#define CLK_INFRA_CPUM 36 +#define CLK_INFRA_CCIF1_AP 37 +#define CLK_INFRA_CCIF1_MD 38 +#define CLK_INFRA_AUXADC_MD 39 +#define CLK_INFRA_MSDC1_SCK 40 +#define CLK_INFRA_MSDC2_SCK 41 +#define CLK_INFRA_AP_DMA 42 +#define CLK_INFRA_XIU 43 +#define CLK_INFRA_DEVICE_APC 44 +#define CLK_INFRA_CCIF_AP 45 +#define CLK_INFRA_DEBUGSYS 46 +#define CLK_INFRA_AUDIO 47 +#define CLK_INFRA_CCIF_MD 48 +#define CLK_INFRA_DXCC_SEC_CORE 49 +#define CLK_INFRA_DXCC_AO 50 +#define CLK_INFRA_DRAMC_F26M 51 +#define CLK_INFRA_IRTX 52 +#define CLK_INFRA_DISP_PWM 53 +#define CLK_INFRA_CLDMA_BCLK 54 +#define CLK_INFRA_AUDIO_26M_BCLK 55 +#define CLK_INFRA_SPI1 56 +#define CLK_INFRA_I2C4 57 +#define CLK_INFRA_MODEM_TEMP_SHARE 58 +#define CLK_INFRA_SPI2 59 +#define CLK_INFRA_SPI3 60 +#define CLK_INFRA_UNIPRO_SCK 61 +#define CLK_INFRA_UNIPRO_TICK 62 +#define CLK_INFRA_UFS_MP_SAP_BCLK 63 +#define CLK_INFRA_MD32_BCLK 64 +#define CLK_INFRA_SSPM 65 +#define CLK_INFRA_UNIPRO_MBIST 66 +#define CLK_INFRA_SSPM_BUS_HCLK 67 +#define CLK_INFRA_I2C5 68 +#define CLK_INFRA_I2C5_ARBITER 69 +#define CLK_INFRA_I2C5_IMM 70 +#define CLK_INFRA_I2C1_ARBITER 71 +#define CLK_INFRA_I2C1_IMM 72 +#define CLK_INFRA_I2C2_ARBITER 73 +#define CLK_INFRA_I2C2_IMM 74 +#define CLK_INFRA_SPI4 75 +#define CLK_INFRA_SPI5 76 +#define CLK_INFRA_CQ_DMA 77 +#define CLK_INFRA_UFS 78 +#define CLK_INFRA_AES_UFSFDE 79 +#define CLK_INFRA_UFS_TICK 80 +#define CLK_INFRA_MSDC0_SELF 81 +#define CLK_INFRA_MSDC1_SELF 82 +#define CLK_INFRA_MSDC2_SELF 83 +#define CLK_INFRA_SSPM_26M_SELF 84 +#define CLK_INFRA_SSPM_32K_SELF 85 +#define CLK_INFRA_UFS_AXI 86 +#define CLK_INFRA_I2C6 87 +#define CLK_INFRA_AP_MSDC0 88 +#define CLK_INFRA_MD_MSDC0 89 +#define CLK_INFRA_USB 90 +#define CLK_INFRA_DEVMPU_BCLK 91 +#define CLK_INFRA_CCIF2_AP 92 +#define CLK_INFRA_CCIF2_MD 93 +#define CLK_INFRA_CCIF3_AP 94 +#define CLK_INFRA_CCIF3_MD 95 +#define CLK_INFRA_SEJ_F13M 96 +#define CLK_INFRA_AES_BCLK 97 +#define CLK_INFRA_I2C7 98 +#define CLK_INFRA_I2C8 99 +#define CLK_INFRA_FBIST2FPC 100 +#define CLK_INFRA_NR_CLK 101 + +/* MMSYS_CONFIG */ +#define CLK_MM_SMI_COMMON 0 +#define CLK_MM_SMI_LARB0 1 +#define CLK_MM_SMI_LARB1 2 +#define CLK_MM_GALS_COMM0 3 +#define CLK_MM_GALS_COMM1 4 +#define CLK_MM_GALS_CCU2MM 5 +#define CLK_MM_GALS_IPU12MM 6 +#define CLK_MM_GALS_IMG2MM 7 +#define CLK_MM_GALS_CAM2MM 8 +#define CLK_MM_GALS_IPU2MM 9 +#define CLK_MM_MDP_DL_TXCK 10 +#define CLK_MM_IPU_DL_TXCK 11 +#define CLK_MM_MDP_RDMA0 12 +#define CLK_MM_MDP_RDMA1 13 +#define CLK_MM_MDP_RSZ0 14 +#define CLK_MM_MDP_RSZ1 15 +#define CLK_MM_MDP_TDSHP 16 +#define CLK_MM_MDP_WROT0 17 +#define CLK_MM_FAKE_ENG 18 +#define CLK_MM_DISP_OVL0 19 +#define CLK_MM_DISP_OVL0_2L 20 +#define CLK_MM_DISP_OVL1_2L 21 +#define CLK_MM_DISP_RDMA0 22 +#define CLK_MM_DISP_RDMA1 23 +#define CLK_MM_DISP_WDMA0 24 +#define CLK_MM_DISP_COLOR0 25 +#define CLK_MM_DISP_CCORR0 26 +#define CLK_MM_DISP_AAL0 27 +#define CLK_MM_DISP_GAMMA0 28 +#define CLK_MM_DISP_DITHER0 29 +#define CLK_MM_DISP_SPLIT 30 +#define CLK_MM_DSI0_MM 31 +#define CLK_MM_DSI0_IF 32 +#define CLK_MM_DPI_MM 33 +#define CLK_MM_DPI_IF 34 +#define CLK_MM_FAKE_ENG2 35 +#define CLK_MM_MDP_DL_RX 36 +#define CLK_MM_IPU_DL_RX 37 +#define CLK_MM_26M 38 +#define CLK_MM_MMSYS_R2Y 39 +#define CLK_MM_DISP_RSZ 40 +#define CLK_MM_MDP_WDMA0 41 +#define CLK_MM_MDP_AAL 42 +#define CLK_MM_MDP_CCORR 43 +#define CLK_MM_DBI_MM 44 +#define CLK_MM_DBI_IF 45 +#define CLK_MM_NR_CLK 46 + +/* MCUCFG */ +#define CLK_MCU_MP0_SEL 0 +#define CLK_MCU_MP2_SEL 1 +#define CLK_MCU_BUS_SEL 2 +#define CLK_MCU_NR_CLK 3 + +#endif /* _DT_BINDINGS_CLK_MT8183_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/mt8512-clk.h b/roms/u-boot/include/dt-bindings/clock/mt8512-clk.h new file mode 100644 index 000000000..fdc3474c0 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/mt8512-clk.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_CLK_MT8512_H +#define _DT_BINDINGS_CLK_MT8512_H + +/* TOPCKGEN */ + +#define CLK_TOP_CLK_NULL 0 +#define CLK_TOP_CLK32K 1 +#define CLK_TOP_SYSPLL1_D2 2 +#define CLK_TOP_SYSPLL1_D4 3 +#define CLK_TOP_SYSPLL1_D8 4 +#define CLK_TOP_SYSPLL1_D16 5 +#define CLK_TOP_SYSPLL_D3 6 +#define CLK_TOP_SYSPLL2_D2 7 +#define CLK_TOP_SYSPLL2_D4 8 +#define CLK_TOP_SYSPLL2_D8 9 +#define CLK_TOP_SYSPLL_D5 10 +#define CLK_TOP_SYSPLL3_D4 11 +#define CLK_TOP_SYSPLL_D7 12 +#define CLK_TOP_SYSPLL4_D2 13 +#define CLK_TOP_UNIVPLL 14 +#define CLK_TOP_UNIVPLL_D2 15 +#define CLK_TOP_UNIVPLL1_D2 16 +#define CLK_TOP_UNIVPLL1_D4 17 +#define CLK_TOP_UNIVPLL1_D8 18 +#define CLK_TOP_UNIVPLL_D3 19 +#define CLK_TOP_UNIVPLL2_D2 20 +#define CLK_TOP_UNIVPLL2_D4 21 +#define CLK_TOP_UNIVPLL2_D8 22 +#define CLK_TOP_UNIVPLL_D5 23 +#define CLK_TOP_UNIVPLL3_D2 24 +#define CLK_TOP_UNIVPLL3_D4 25 +#define CLK_TOP_TCONPLL_D2 26 +#define CLK_TOP_TCONPLL_D4 27 +#define CLK_TOP_TCONPLL_D8 28 +#define CLK_TOP_TCONPLL_D16 29 +#define CLK_TOP_TCONPLL_D32 30 +#define CLK_TOP_TCONPLL_D64 31 +#define CLK_TOP_USB20_192M 32 +#define CLK_TOP_USB20_192M_D2 33 +#define CLK_TOP_USB20_192M_D4_T 34 +#define CLK_TOP_APLL1 35 +#define CLK_TOP_APLL1_D2 36 +#define CLK_TOP_APLL1_D3 37 +#define CLK_TOP_APLL1_D4 38 +#define CLK_TOP_APLL1_D8 39 +#define CLK_TOP_APLL1_D16 40 +#define CLK_TOP_APLL2 41 +#define CLK_TOP_APLL2_D2 42 +#define CLK_TOP_APLL2_D3 43 +#define CLK_TOP_APLL2_D4 44 +#define CLK_TOP_APLL2_D8 45 +#define CLK_TOP_APLL2_D16 46 +#define CLK_TOP_CLK26M 47 +#define CLK_TOP_SYS_26M_D2 48 +#define CLK_TOP_MSDCPLL 49 +#define CLK_TOP_MSDCPLL_D2 50 +#define CLK_TOP_DSPPLL 51 +#define CLK_TOP_DSPPLL_D2 52 +#define CLK_TOP_DSPPLL_D4 53 +#define CLK_TOP_DSPPLL_D8 54 +#define CLK_TOP_IPPLL 55 +#define CLK_TOP_IPPLL_D2 56 +#define CLK_TOP_NFI2X_CK_D2 57 +#define CLK_TOP_AXI_SEL 58 +#define CLK_TOP_MEM_SEL 59 +#define CLK_TOP_UART_SEL 60 +#define CLK_TOP_SPI_SEL 61 +#define CLK_TOP_SPIS_SEL 62 +#define CLK_TOP_MSDC50_0_HC_SEL 63 +#define CLK_TOP_MSDC2_2_HC_SEL 64 +#define CLK_TOP_MSDC50_0_SEL 65 +#define CLK_TOP_MSDC50_2_SEL 66 +#define CLK_TOP_MSDC30_1_SEL 67 +#define CLK_TOP_AUDIO_SEL 68 +#define CLK_TOP_AUD_INTBUS_SEL 69 +#define CLK_TOP_HAPLL1_SEL 70 +#define CLK_TOP_HAPLL2_SEL 71 +#define CLK_TOP_A2SYS_SEL 72 +#define CLK_TOP_A1SYS_SEL 73 +#define CLK_TOP_ASM_L_SEL 74 +#define CLK_TOP_ASM_M_SEL 75 +#define CLK_TOP_ASM_H_SEL 76 +#define CLK_TOP_AUD_SPDIF_SEL 77 +#define CLK_TOP_AUD_1_SEL 78 +#define CLK_TOP_AUD_2_SEL 79 +#define CLK_TOP_SSUSB_SYS_SEL 80 +#define CLK_TOP_SSUSB_XHCI_SEL 81 +#define CLK_TOP_SPM_SEL 82 +#define CLK_TOP_I2C_SEL 83 +#define CLK_TOP_PWM_SEL 84 +#define CLK_TOP_DSP_SEL 85 +#define CLK_TOP_NFI2X_SEL 86 +#define CLK_TOP_SPINFI_SEL 87 +#define CLK_TOP_ECC_SEL 88 +#define CLK_TOP_GCPU_SEL 89 +#define CLK_TOP_GCPU_CPM_SEL 90 +#define CLK_TOP_MBIST_DIAG_SEL 91 +#define CLK_TOP_IP0_NNA_SEL 92 +#define CLK_TOP_IP1_NNA_SEL 93 +#define CLK_TOP_IP2_WFST_SEL 94 +#define CLK_TOP_SFLASH_SEL 95 +#define CLK_TOP_SRAM_SEL 96 +#define CLK_TOP_MM_SEL 97 +#define CLK_TOP_DPI0_SEL 98 +#define CLK_TOP_DBG_ATCLK_SEL 99 +#define CLK_TOP_OCC_104M_SEL 100 +#define CLK_TOP_OCC_68M_SEL 101 +#define CLK_TOP_OCC_182M_SEL 102 + +/* TOPCKGEN Gates */ +#define CLK_TOP_CONN_32K 0 +#define CLK_TOP_CONN_26M 1 +#define CLK_TOP_DSP_32K 2 +#define CLK_TOP_DSP_26M 3 +#define CLK_TOP_USB20_48M_EN 4 +#define CLK_TOP_UNIVPLL_48M_EN 5 +#define CLK_TOP_SSUSB_TOP_CK_EN 6 +#define CLK_TOP_SSUSB_PHY_CK_EN 7 +#define CLK_TOP_I2SI1_MCK 8 +#define CLK_TOP_TDMIN_MCK 9 +#define CLK_TOP_I2SO1_MCK 10 + +/* INFRASYS */ + +#define CLK_INFRA_DSP_AXI 0 +#define CLK_INFRA_APXGPT 1 +#define CLK_INFRA_ICUSB 2 +#define CLK_INFRA_GCE 3 +#define CLK_INFRA_THERM 4 +#define CLK_INFRA_PWM_HCLK 5 +#define CLK_INFRA_PWM1 6 +#define CLK_INFRA_PWM2 7 +#define CLK_INFRA_PWM3 8 +#define CLK_INFRA_PWM4 9 +#define CLK_INFRA_PWM5 10 +#define CLK_INFRA_PWM 11 +#define CLK_INFRA_UART0 12 +#define CLK_INFRA_UART1 13 +#define CLK_INFRA_UART2 14 +#define CLK_INFRA_DSP_UART 15 +#define CLK_INFRA_GCE_26M 16 +#define CLK_INFRA_CQDMA_FPC 17 +#define CLK_INFRA_BTIF 18 +#define CLK_INFRA_SPI 19 +#define CLK_INFRA_MSDC0 20 +#define CLK_INFRA_MSDC1 21 +#define CLK_INFRA_DVFSRC 22 +#define CLK_INFRA_GCPU 23 +#define CLK_INFRA_TRNG 24 +#define CLK_INFRA_AUXADC 25 +#define CLK_INFRA_AUXADC_MD 26 +#define CLK_INFRA_AP_DMA 27 +#define CLK_INFRA_DEBUGSYS 28 +#define CLK_INFRA_AUDIO 29 +#define CLK_INFRA_FLASHIF 30 +#define CLK_INFRA_PWM_FB6 31 +#define CLK_INFRA_PWM_FB7 32 +#define CLK_INFRA_AUD_ASRC 33 +#define CLK_INFRA_AUD_26M 34 +#define CLK_INFRA_SPIS 35 +#define CLK_INFRA_CQ_DMA 36 +#define CLK_INFRA_AP_MSDC0 37 +#define CLK_INFRA_MD_MSDC0 38 +#define CLK_INFRA_MSDC0_SRC 39 +#define CLK_INFRA_MSDC1_SRC 40 +#define CLK_INFRA_IRRX_26M 41 +#define CLK_INFRA_IRRX_32K 42 +#define CLK_INFRA_I2C0_AXI 43 +#define CLK_INFRA_I2C1_AXI 44 +#define CLK_INFRA_I2C2_AXI 45 +#define CLK_INFRA_NFI 46 +#define CLK_INFRA_NFIECC 47 +#define CLK_INFRA_NFI_HCLK 48 +#define CLK_INFRA_SUSB_133 49 +#define CLK_INFRA_USB_SYS 50 +#define CLK_INFRA_USB_XHCI 51 +#define CLK_INFRA_NR_CLK 52 + +/* APMIXEDSYS */ + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIVPLL2 2 +#define CLK_APMIXED_MSDCPLL 3 +#define CLK_APMIXED_APLL1 4 +#define CLK_APMIXED_APLL2 5 +#define CLK_APMIXED_IPPLL 6 +#define CLK_APMIXED_DSPPLL 7 +#define CLK_APMIXED_TCONPLL 8 +#define CLK_APMIXED_NR_CLK 9 + +#endif /* _DT_BINDINGS_CLK_MT8512_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/mt8516-clk.h b/roms/u-boot/include/dt-bindings/clock/mt8516-clk.h new file mode 100644 index 000000000..745b87f3a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/mt8516-clk.h @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 BayLibre, SAS + * Copyright (c) 2018 MediaTek Inc. + * Author: Fabien Parent + */ + +#ifndef _DT_BINDINGS_CLK_MT8516_H +#define _DT_BINDINGS_CLK_MT8516_H + + +/* APMIXEDSYS */ + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIVPLL 2 +#define CLK_APMIXED_MMPLL 3 +#define CLK_APMIXED_APLL1 4 +#define CLK_APMIXED_APLL2 5 +#define CLK_APMIXED_NR_CLK 6 + +/* TOPCKGEN */ + +#define CLK_TOP_CLK_NULL 0 +#define CLK_TOP_I2S_INFRA_BCK 1 +#define CLK_TOP_MEMPLL 2 +#define CLK_TOP_DMPLL 3 +#define CLK_TOP_MAINPLL_D2 4 +#define CLK_TOP_MAINPLL_D4 5 +#define CLK_TOP_MAINPLL_D8 6 +#define CLK_TOP_MAINPLL_D16 7 +#define CLK_TOP_MAINPLL_D11 8 +#define CLK_TOP_MAINPLL_D22 9 +#define CLK_TOP_MAINPLL_D3 10 +#define CLK_TOP_MAINPLL_D6 11 +#define CLK_TOP_MAINPLL_D12 12 +#define CLK_TOP_MAINPLL_D5 13 +#define CLK_TOP_MAINPLL_D10 14 +#define CLK_TOP_MAINPLL_D20 15 +#define CLK_TOP_MAINPLL_D40 16 +#define CLK_TOP_MAINPLL_D7 17 +#define CLK_TOP_MAINPLL_D14 18 +#define CLK_TOP_UNIVPLL_D2 19 +#define CLK_TOP_UNIVPLL_D4 20 +#define CLK_TOP_UNIVPLL_D8 21 +#define CLK_TOP_UNIVPLL_D16 22 +#define CLK_TOP_UNIVPLL_D3 23 +#define CLK_TOP_UNIVPLL_D6 24 +#define CLK_TOP_UNIVPLL_D12 25 +#define CLK_TOP_UNIVPLL_D24 26 +#define CLK_TOP_UNIVPLL_D5 27 +#define CLK_TOP_UNIVPLL_D20 28 +#define CLK_TOP_MMPLL380M 29 +#define CLK_TOP_MMPLL_D2 30 +#define CLK_TOP_MMPLL_200M 31 +#define CLK_TOP_USB_PHY48M 32 +#define CLK_TOP_APLL1 33 +#define CLK_TOP_APLL1_D2 34 +#define CLK_TOP_APLL1_D4 35 +#define CLK_TOP_APLL1_D8 36 +#define CLK_TOP_APLL2 37 +#define CLK_TOP_APLL2_D2 38 +#define CLK_TOP_APLL2_D4 39 +#define CLK_TOP_APLL2_D8 40 +#define CLK_TOP_CLK26M 41 +#define CLK_TOP_CLK26M_D2 42 +#define CLK_TOP_AHB_INFRA_D2 43 +#define CLK_TOP_NFI1X 44 +#define CLK_TOP_ETH_D2 45 +#define CLK_TOP_UART0_SEL 46 +#define CLK_TOP_GFMUX_EMI1X_SEL 47 +#define CLK_TOP_EMI_DDRPHY_SEL 48 +#define CLK_TOP_AHB_INFRA_SEL 49 +#define CLK_TOP_CSW_MUX_MFG_SEL 50 +#define CLK_TOP_MSDC0_SEL 51 +#define CLK_TOP_PWM_MM_SEL 52 +#define CLK_TOP_UART1_SEL 53 +#define CLK_TOP_MSDC1_SEL 54 +#define CLK_TOP_SPM_52M_SEL 55 +#define CLK_TOP_PMICSPI_SEL 56 +#define CLK_TOP_QAXI_AUD26M_SEL 57 +#define CLK_TOP_AUD_INTBUS_SEL 58 +#define CLK_TOP_NFI2X_PAD_SEL 59 +#define CLK_TOP_NFI1X_PAD_SEL 60 +#define CLK_TOP_MFG_MM_SEL 61 +#define CLK_TOP_DDRPHYCFG_SEL 62 +#define CLK_TOP_USB_78M_SEL 63 +#define CLK_TOP_SPINOR_SEL 64 +#define CLK_TOP_MSDC2_SEL 65 +#define CLK_TOP_ETH_SEL 66 +#define CLK_TOP_AXI_MFG_IN_SEL 67 +#define CLK_TOP_SLOW_MFG_SEL 68 +#define CLK_TOP_AUD1_SEL 69 +#define CLK_TOP_AUD2_SEL 70 +#define CLK_TOP_AUD_ENGEN1_SEL 71 +#define CLK_TOP_AUD_ENGEN2_SEL 72 +#define CLK_TOP_I2C_SEL 73 +#define CLK_TOP_AUD_I2S0_M_SEL 74 +#define CLK_TOP_AUD_I2S1_M_SEL 75 +#define CLK_TOP_AUD_I2S2_M_SEL 76 +#define CLK_TOP_AUD_I2S3_M_SEL 77 +#define CLK_TOP_AUD_I2S4_M_SEL 78 +#define CLK_TOP_AUD_I2S5_M_SEL 79 +#define CLK_TOP_AUD_SPDIF_B_SEL 80 +#define CLK_TOP_PWM_SEL 81 +#define CLK_TOP_SPI_SEL 82 +#define CLK_TOP_AUD_SPDIFIN_SEL 83 +#define CLK_TOP_UART2_SEL 84 +#define CLK_TOP_BSI_SEL 85 +#define CLK_TOP_DBG_ATCLK_SEL 86 +#define CLK_TOP_CSW_NFIECC_SEL 87 +#define CLK_TOP_NFIECC_SEL 88 +#define CLK_TOP_APLL12_CK_DIV0 89 +#define CLK_TOP_APLL12_CK_DIV1 90 +#define CLK_TOP_APLL12_CK_DIV2 91 +#define CLK_TOP_APLL12_CK_DIV3 92 +#define CLK_TOP_APLL12_CK_DIV4 93 +#define CLK_TOP_APLL12_CK_DIV4B 94 +#define CLK_TOP_APLL12_CK_DIV5 95 +#define CLK_TOP_APLL12_CK_DIV5B 96 +#define CLK_TOP_APLL12_CK_DIV6 97 +#define CLK_TOP_NR_CLK 98 + +/* TOPCKGEN Gates */ +#define CLK_TOP_PWM_MM 0 +#define CLK_TOP_MFG_MM 1 +#define CLK_TOP_SPM_52M 2 +#define CLK_TOP_THEM 3 +#define CLK_TOP_APDMA 4 +#define CLK_TOP_I2C0 5 +#define CLK_TOP_I2C1 6 +#define CLK_TOP_AUXADC1 7 +#define CLK_TOP_NFI 8 +#define CLK_TOP_NFIECC 9 +#define CLK_TOP_DEBUGSYS 10 +#define CLK_TOP_PWM 11 +#define CLK_TOP_UART0 12 +#define CLK_TOP_UART1 13 +#define CLK_TOP_BTIF 14 +#define CLK_TOP_USB 15 +#define CLK_TOP_FLASHIF_26M 16 +#define CLK_TOP_AUXADC2 17 +#define CLK_TOP_I2C2 18 +#define CLK_TOP_MSDC0 19 +#define CLK_TOP_MSDC1 20 +#define CLK_TOP_NFI2X 21 +#define CLK_TOP_PMICWRAP_AP 22 +#define CLK_TOP_SEJ 23 +#define CLK_TOP_MEMSLP_DLYER 24 +#define CLK_TOP_SPI 25 +#define CLK_TOP_APXGPT 26 +#define CLK_TOP_AUDIO 27 +#define CLK_TOP_PMICWRAP_MD 28 +#define CLK_TOP_PMICWRAP_CONN 29 +#define CLK_TOP_PMICWRAP_26M 30 +#define CLK_TOP_AUX_ADC 31 +#define CLK_TOP_AUX_TP 32 +#define CLK_TOP_MSDC2 33 +#define CLK_TOP_RBIST 34 +#define CLK_TOP_NFI_BUS 35 +#define CLK_TOP_GCE 36 +#define CLK_TOP_TRNG 37 +#define CLK_TOP_SEJ_13M 38 +#define CLK_TOP_AES 39 +#define CLK_TOP_PWM_B 40 +#define CLK_TOP_PWM1_FB 41 +#define CLK_TOP_PWM2_FB 42 +#define CLK_TOP_PWM3_FB 43 +#define CLK_TOP_PWM4_FB 44 +#define CLK_TOP_PWM5_FB 45 +#define CLK_TOP_USB_1P 46 +#define CLK_TOP_FLASHIF_FREERUN 47 +#define CLK_TOP_66M_ETH 48 +#define CLK_TOP_133M_ETH 49 +#define CLK_TOP_FETH_25M 50 +#define CLK_TOP_FETH_50M 51 +#define CLK_TOP_FLASHIF_AXI 52 +#define CLK_TOP_USBIF 53 +#define CLK_TOP_UART2 54 +#define CLK_TOP_BSI 55 +#define CLK_TOP_MSDC0_INFRA 56 +#define CLK_TOP_MSDC1_INFRA 57 +#define CLK_TOP_MSDC2_INFRA 58 +#define CLK_TOP_USB_78M 59 +#define CLK_TOP_RG_SPINOR 60 +#define CLK_TOP_RG_MSDC2 61 +#define CLK_TOP_RG_ETH 62 +#define CLK_TOP_RG_AXI_MFG 63 +#define CLK_TOP_RG_SLOW_MFG 64 +#define CLK_TOP_RG_AUD1 65 +#define CLK_TOP_RG_AUD2 66 +#define CLK_TOP_RG_AUD_ENGEN1 67 +#define CLK_TOP_RG_AUD_ENGEN2 68 +#define CLK_TOP_RG_I2C 69 +#define CLK_TOP_RG_PWM_INFRA 70 +#define CLK_TOP_RG_AUD_SPDIF_IN 71 +#define CLK_TOP_RG_UART2 72 +#define CLK_TOP_RG_BSI 73 +#define CLK_TOP_RG_DBG_ATCLK 74 +#define CLK_TOP_RG_NFIECC 75 +#define CLK_TOP_RG_APLL1_D2_EN 76 +#define CLK_TOP_RG_APLL1_D4_EN 77 +#define CLK_TOP_RG_APLL1_D8_EN 78 +#define CLK_TOP_RG_APLL2_D2_EN 79 +#define CLK_TOP_RG_APLL2_D4_EN 80 +#define CLK_TOP_RG_APLL2_D8_EN 81 +#define CLK_TOP_APLL12_DIV0 82 +#define CLK_TOP_APLL12_DIV1 83 +#define CLK_TOP_APLL12_DIV2 84 +#define CLK_TOP_APLL12_DIV3 85 +#define CLK_TOP_APLL12_DIV4 86 +#define CLK_TOP_APLL12_DIV4B 87 +#define CLK_TOP_APLL12_DIV5 88 +#define CLK_TOP_APLL12_DIV5B 89 +#define CLK_TOP_APLL12_DIV6 90 + +/* INFRACFG */ + +#define CLK_IFR_MUX1_SEL 0 +#define CLK_IFR_ETH_25M_SEL 1 +#define CLK_IFR_I2C0_SEL 2 +#define CLK_IFR_I2C1_SEL 3 +#define CLK_IFR_I2C2_SEL 4 +#define CLK_IFR_NR_CLK 5 + +/* AUDIOTOP */ + +#define CLK_AUD_AFE 0 +#define CLK_AUD_I2S 1 +#define CLK_AUD_22M 2 +#define CLK_AUD_24M 3 +#define CLK_AUD_INTDIR 4 +#define CLK_AUD_APLL2_TUNER 5 +#define CLK_AUD_APLL_TUNER 6 +#define CLK_AUD_HDMI 7 +#define CLK_AUD_SPDF 8 +#define CLK_AUD_ADC 9 +#define CLK_AUD_DAC 10 +#define CLK_AUD_DAC_PREDIS 11 +#define CLK_AUD_TML 12 +#define CLK_AUD_NR_CLK 13 + +/* MFGCFG */ + +#define CLK_MFG_BAXI 0 +#define CLK_MFG_BMEM 1 +#define CLK_MFG_BG3D 2 +#define CLK_MFG_B26M 3 +#define CLK_MFG_NR_CLK 4 + +#endif /* _DT_BINDINGS_CLK_MT8516_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/mt8518-clk.h b/roms/u-boot/include/dt-bindings/clock/mt8518-clk.h new file mode 100644 index 000000000..43b724796 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/mt8518-clk.h @@ -0,0 +1,249 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_CLK_MT8518_H +#define _DT_BINDINGS_CLK_MT8518_H + +/* APMIXEDSYS */ + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIVPLL 2 +#define CLK_APMIXED_MMPLL 3 +#define CLK_APMIXED_APLL1 4 +#define CLK_APMIXED_APLL2 5 +#define CLK_APMIXED_TVDPLL 6 +#define CLK_APMIXED_NR_CLK 7 + +/* TOPCKGEN */ + +#define CLK_TOP_CLK_NULL 0 +#define CLK_TOP_FQ_TRNG_OUT0 1 +#define CLK_TOP_FQ_TRNG_OUT1 2 +#define CLK_TOP_CLK32K 3 +#define CLK_TOP_DMPLL 4 +#define CLK_TOP_MAINPLL_D4 5 +#define CLK_TOP_MAINPLL_D8 6 +#define CLK_TOP_MAINPLL_D16 7 +#define CLK_TOP_MAINPLL_D11 8 +#define CLK_TOP_MAINPLL_D22 9 +#define CLK_TOP_MAINPLL_D3 10 +#define CLK_TOP_MAINPLL_D6 11 +#define CLK_TOP_MAINPLL_D12 12 +#define CLK_TOP_MAINPLL_D5 13 +#define CLK_TOP_MAINPLL_D10 14 +#define CLK_TOP_MAINPLL_D20 15 +#define CLK_TOP_MAINPLL_D40 16 +#define CLK_TOP_MAINPLL_D7 17 +#define CLK_TOP_MAINPLL_D14 18 +#define CLK_TOP_UNIVPLL_D2 19 +#define CLK_TOP_UNIVPLL_D4 20 +#define CLK_TOP_UNIVPLL_D8 21 +#define CLK_TOP_UNIVPLL_D16 22 +#define CLK_TOP_UNIVPLL_D3 23 +#define CLK_TOP_UNIVPLL_D6 24 +#define CLK_TOP_UNIVPLL_D12 25 +#define CLK_TOP_UNIVPLL_D24 26 +#define CLK_TOP_UNIVPLL_D5 27 +#define CLK_TOP_UNIVPLL_D20 28 +#define CLK_TOP_UNIVPLL_D10 29 +#define CLK_TOP_MMPLL_D2 30 +#define CLK_TOP_USB20_48M 31 +#define CLK_TOP_APLL1 32 +#define CLK_TOP_APLL1_D4 33 +#define CLK_TOP_APLL2 34 +#define CLK_TOP_APLL2_D2 35 +#define CLK_TOP_APLL2_D3 36 +#define CLK_TOP_APLL2_D4 37 +#define CLK_TOP_APLL2_D8 38 +#define CLK_TOP_CLK26M 39 +#define CLK_TOP_CLK26M_D2 40 +#define CLK_TOP_CLK26M_D4 41 +#define CLK_TOP_CLK26M_D8 42 +#define CLK_TOP_CLK26M_D793 43 +#define CLK_TOP_TVDPLL 44 +#define CLK_TOP_TVDPLL_D2 45 +#define CLK_TOP_TVDPLL_D4 46 +#define CLK_TOP_TVDPLL_D8 47 +#define CLK_TOP_TVDPLL_D16 48 +#define CLK_TOP_USB20_CLK480M 49 +#define CLK_TOP_RG_APLL1_D2 50 +#define CLK_TOP_RG_APLL1_D4 51 +#define CLK_TOP_RG_APLL1_D8 52 +#define CLK_TOP_RG_APLL1_D16 53 +#define CLK_TOP_RG_APLL1_D3 54 +#define CLK_TOP_RG_APLL2_D2 55 +#define CLK_TOP_RG_APLL2_D4 56 +#define CLK_TOP_RG_APLL2_D8 57 +#define CLK_TOP_RG_APLL2_D16 58 +#define CLK_TOP_RG_APLL2_D3 59 +#define CLK_TOP_NFI1X_INFRA_BCLK 60 +#define CLK_TOP_AHB_INFRA_D2 61 +#define CLK_TOP_UART0_SEL 62 +#define CLK_TOP_EMI1X_SEL 63 +#define CLK_TOP_EMI_DDRPHY_SEL 64 +#define CLK_TOP_MSDC1_SEL 65 +#define CLK_TOP_PWM_MM_SEL 66 +#define CLK_TOP_UART1_SEL 67 +#define CLK_TOP_SPM_52M_SEL 68 +#define CLK_TOP_PMICSPI_SEL 69 +#define CLK_TOP_NFI2X_SEL 70 +#define CLK_TOP_DDRPHYCFG_SEL 71 +#define CLK_TOP_SMI_SEL 72 +#define CLK_TOP_USB_SEL 73 +#define CLK_TOP_SPINOR_SEL 74 +#define CLK_TOP_ETH_SEL 75 +#define CLK_TOP_AUD1_SEL 76 +#define CLK_TOP_AUD2_SEL 77 +#define CLK_TOP_I2C_SEL 78 +#define CLK_TOP_AUD_I2S0_M_SEL 79 +#define CLK_TOP_AUD_I2S3_M_SEL 80 +#define CLK_TOP_AUD_I2S4_M_SEL 81 +#define CLK_TOP_AUD_I2S6_M_SEL 82 +#define CLK_TOP_PWM_SEL 83 +#define CLK_TOP_AUD_SPDIFIN_SEL 84 +#define CLK_TOP_UART2_SEL 85 +#define CLK_TOP_DBG_ATCLK_SEL 86 +#define CLK_TOP_PNG_SYS_SEL 87 +#define CLK_TOP_SEJ_13M_SEL 88 +#define CLK_TOP_IMGRZ_SYS_SEL 89 +#define CLK_TOP_GRAPH_ECLK_SEL 90 +#define CLK_TOP_FDBI_SEL 91 +#define CLK_TOP_FAUDIO_SEL 92 +#define CLK_TOP_FA2SYS_SEL 93 +#define CLK_TOP_FA1SYS_SEL 94 +#define CLK_TOP_FASM_M_SEL 95 +#define CLK_TOP_FASM_H_SEL 96 +#define CLK_TOP_FASM_L_SEL 97 +#define CLK_TOP_FECC_CK_SEL 98 +#define CLK_TOP_PE2_MAC_SEL 99 +#define CLK_TOP_CMSYS_SEL 100 +#define CLK_TOP_GCPU_SEL 101 +#define CLK_TOP_SPIS_CK_SEL 102 +#define CLK_TOP_APLL1_REF_SEL 103 +#define CLK_TOP_APLL2_REF_SEL 104 +#define CLK_TOP_INT_32K_SEL 105 +#define CLK_TOP_APLL1_SRC_SEL 106 +#define CLK_TOP_APLL2_SRC_SEL 107 +#define CLK_TOP_FAUD_INTBUS_SEL 108 +#define CLK_TOP_AXIBUS_SEL 109 +#define CLK_TOP_HAPLL1_SEL 110 +#define CLK_TOP_HAPLL2_SEL 111 +#define CLK_TOP_SPINFI_SEL 112 +#define CLK_TOP_MSDC0_SEL 113 +#define CLK_TOP_MSDC0_CLK50_SEL 114 +#define CLK_TOP_MSDC2_SEL 115 +#define CLK_TOP_MSDC2_CLK50_SEL 116 +#define CLK_TOP_DISP_DPI_CK_SEL 117 +#define CLK_TOP_SPI1_SEL 118 +#define CLK_TOP_SPI2_SEL 119 +#define CLK_TOP_SPI3_SEL 120 +#define CLK_TOP_APLL12_CK_DIV0 121 +#define CLK_TOP_APLL12_CK_DIV3 122 +#define CLK_TOP_APLL12_CK_DIV4 123 +#define CLK_TOP_APLL12_CK_DIV6 124 + +/* TOPCKGEN Gates */ +#define CLK_TOP_PWM_MM 0 +#define CLK_TOP_SMI 1 +#define CLK_TOP_SPI2 2 +#define CLK_TOP_SPI3 3 +#define CLK_TOP_SPINFI 4 +#define CLK_TOP_26M_DEBUG 5 +#define CLK_TOP_USB_48M_DEBUG 6 +#define CLK_TOP_52M_DEBUG 7 +#define CLK_TOP_32K_DEBUG 8 +#define CLK_TOP_THERM 9 +#define CLK_TOP_APDMA 10 +#define CLK_TOP_I2C0 11 +#define CLK_TOP_I2C1 12 +#define CLK_TOP_AUXADC1 13 +#define CLK_TOP_NFI 14 +#define CLK_TOP_NFIECC 15 +#define CLK_TOP_DEBUGSYS 16 +#define CLK_TOP_PWM 17 +#define CLK_TOP_UART0 18 +#define CLK_TOP_UART1 19 +#define CLK_TOP_USB 20 +#define CLK_TOP_FLASHIF_26M 21 +#define CLK_TOP_AUXADC2 22 +#define CLK_TOP_I2C2 23 +#define CLK_TOP_MSDC0 24 +#define CLK_TOP_MSDC1 25 +#define CLK_TOP_NFI2X 26 +#define CLK_TOP_MEMSLP_DLYER 27 +#define CLK_TOP_SPI 28 +#define CLK_TOP_APXGPT 29 +#define CLK_TOP_PMICWRAP_MD 30 +#define CLK_TOP_PMICWRAP_CONN 31 +#define CLK_TOP_PMIC_SYSCK 32 +#define CLK_TOP_AUX_ADC 33 +#define CLK_TOP_AUX_TP 34 +#define CLK_TOP_RBIST 35 +#define CLK_TOP_NFI_BUS 36 +#define CLK_TOP_GCE 37 +#define CLK_TOP_TRNG 38 +#define CLK_TOP_PWM_B 39 +#define CLK_TOP_PWM1_FB 40 +#define CLK_TOP_PWM2_FB 41 +#define CLK_TOP_PWM3_FB 42 +#define CLK_TOP_PWM4_FB 43 +#define CLK_TOP_PWM5_FB 44 +#define CLK_TOP_FLASHIF_FREERUN 45 +#define CLK_TOP_CQDMA 46 +#define CLK_TOP_66M_ETH 47 +#define CLK_TOP_133M_ETH 48 +#define CLK_TOP_FLASHIF_AXI 49 +#define CLK_TOP_USBIF 50 +#define CLK_TOP_UART2 51 +#define CLK_TOP_GCPU_B 52 +#define CLK_TOP_MSDC0_B 53 +#define CLK_TOP_MSDC1_B 54 +#define CLK_TOP_MSDC2_B 55 +#define CLK_TOP_USB_B 56 +#define CLK_TOP_SPINOR 57 +#define CLK_TOP_MSDC2 58 +#define CLK_TOP_ETH 59 +#define CLK_TOP_AUD1 60 +#define CLK_TOP_AUD2 61 +#define CLK_TOP_I2C 62 +#define CLK_TOP_PWM_INFRA 63 +#define CLK_TOP_AUD_SPDIF_IN 64 +#define CLK_TOP_RG_UART2 65 +#define CLK_TOP_DBG_AT 66 +#define CLK_TOP_APLL12_DIV0 67 +#define CLK_TOP_APLL12_DIV3 68 +#define CLK_TOP_APLL12_DIV4 69 +#define CLK_TOP_APLL12_DIV6 70 +#define CLK_TOP_IMGRZ_SYS 71 +#define CLK_TOP_PNG_SYS 72 +#define CLK_TOP_GRAPH_E 73 +#define CLK_TOP_FDBI 74 +#define CLK_TOP_FAUDIO 75 +#define CLK_TOP_FAUD_INTBUS 76 +#define CLK_TOP_HAPLL1 77 +#define CLK_TOP_HAPLL2 78 +#define CLK_TOP_FA2SYS 79 +#define CLK_TOP_FA1SYS 80 +#define CLK_TOP_FASM_L 81 +#define CLK_TOP_FASM_M 82 +#define CLK_TOP_FASM_H 83 +#define CLK_TOP_FECC 84 +#define CLK_TOP_PE2_MAC 85 +#define CLK_TOP_CMSYS 86 +#define CLK_TOP_GCPU 87 +#define CLK_TOP_SPIS 88 +#define CLK_TOP_I2C3 89 +#define CLK_TOP_SPI_SLV_B 90 +#define CLK_TOP_SPI_SLV_BUS 91 +#define CLK_TOP_PCIE_MAC_BUS 92 +#define CLK_TOP_CMSYS_BUS 93 +#define CLK_TOP_ECC_B 94 +#define CLK_TOP_PCIE_PHY_BUS 95 +#define CLK_TOP_PCIE_AUX 96 +#define CLK_TOP_DISP_DPI 97 +#define CLK_TOP_NR_CLK 98 + +#endif /* _DT_BINDINGS_CLK_MT8518_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/octeon-clock.h b/roms/u-boot/include/dt-bindings/clock/octeon-clock.h new file mode 100644 index 000000000..34e6a3bf4 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/octeon-clock.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Stefan Roese + */ + +#ifndef __DT_BINDINGS_CLOCK_OCTEON_CLOCK_H +#define __DT_BINDINGS_CLOCK_OCTEON_CLOCK_H + +#define OCTEON_CLK_CORE 0 +#define OCTEON_CLK_IO 1 + +#endif /* __DT_BINDINGS_CLOCK_OCTEON_CLOCK_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/omap4.h b/roms/u-boot/include/dt-bindings/clock/omap4.h new file mode 100644 index 000000000..88d73be84 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/omap4.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2017 Texas Instruments, Inc. + */ +#ifndef __DT_BINDINGS_CLK_OMAP4_H +#define __DT_BINDINGS_CLK_OMAP4_H + +#define OMAP4_CLKCTRL_OFFSET 0x20 +#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) + +/* mpuss clocks */ +#define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* tesla clocks */ +#define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* abe clocks */ +#define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +#define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) +#define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) +#define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) +#define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) +#define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) +#define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) +#define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) +#define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) +#define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) +#define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) + +/* l4_ao clocks */ +#define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) + +/* l3_1 clocks */ +#define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l3_2 clocks */ +#define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) + +/* ducati clocks */ +#define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l3_dma clocks */ +#define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l3_emif clocks */ +#define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) + +/* d2d clocks */ +#define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l4_cfg clocks */ +#define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) + +/* l3_instr clocks */ +#define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) + +/* ivahd clocks */ +#define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) + +/* iss clocks */ +#define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) + +/* l3_dss clocks */ +#define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l3_gfx clocks */ +#define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l3_init clocks */ +#define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +#define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) +#define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) +#define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) +#define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0) +#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) + +/* l4_per clocks */ +#define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +#define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) +#define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) +#define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) +#define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) +#define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) +#define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) +#define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) +#define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) +#define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) +#define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) +#define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0) +#define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8) +#define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0) +#define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8) +#define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0) +#define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) +#define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0) +#define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8) +#define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100) +#define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108) +#define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120) +#define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128) +#define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138) +#define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140) +#define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148) +#define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150) +#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158) +#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160) + +/* l4_secure clocks */ +#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0 +#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET) +#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0) +#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8) +#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0) +#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8) +#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0) +#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8) +#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8) + +/* l4_wkup clocks */ +#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +#define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) +#define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) +#define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) + +/* emu_sys clocks */ +#define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/omap5.h b/roms/u-boot/include/dt-bindings/clock/omap5.h new file mode 100644 index 000000000..41775272f --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/omap5.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2017 Texas Instruments, Inc. + */ +#ifndef __DT_BINDINGS_CLK_OMAP5_H +#define __DT_BINDINGS_CLK_OMAP5_H + +#define OMAP5_CLKCTRL_OFFSET 0x20 +#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET) + +/* mpu clocks */ +#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* dsp clocks */ +#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* abe clocks */ +#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) +#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) +#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) +#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) +#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) +#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) +#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) +#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) + +/* l3main1 clocks */ +#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* l3main2 clocks */ +#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* ipu clocks */ +#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* dma clocks */ +#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* emif clocks */ +#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) + +/* l4cfg clocks */ +#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) + +/* l3instr clocks */ +#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) + +/* l4per clocks */ +#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) +#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) +#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) +#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) +#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60) +#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) +#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) +#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) +#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) +#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0) +#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8) +#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0) +#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8) +#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0) +#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) +#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8) +#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100) +#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108) +#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110) +#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118) +#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120) +#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128) +#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140) +#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148) +#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150) +#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158) +#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160) +#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168) +#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) +#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) + +/* l4_secure clocks */ +#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0 +#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET) +#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0) +#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8) +#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0) +#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8) +#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0) +#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8) +#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8) + +/* iva clocks */ +#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) + +/* dss clocks */ +#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* gpu clocks */ +#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* l3init clocks */ +#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) +#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) +#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88) +#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0) +#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8) +#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) + +/* wkupaon clocks */ +#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) +#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) +#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) +#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/px30-cru.h b/roms/u-boot/include/dt-bindings/clock/px30-cru.h new file mode 100644 index 000000000..e5e59690b --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/px30-cru.h @@ -0,0 +1,389 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Elaine + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H +#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_NPLL 4 +#define APLL_BOOST_H 5 +#define APLL_BOOST_L 6 +#define ARMCLK 7 + +/* sclk gates (special clocks) */ +#define USB480M 14 +#define SCLK_PDM 15 +#define SCLK_I2S0_TX 16 +#define SCLK_I2S0_TX_OUT 17 +#define SCLK_I2S0_RX 18 +#define SCLK_I2S0_RX_OUT 19 +#define SCLK_I2S1 20 +#define SCLK_I2S1_OUT 21 +#define SCLK_I2S2 22 +#define SCLK_I2S2_OUT 23 +#define SCLK_UART1 24 +#define SCLK_UART2 25 +#define SCLK_UART3 26 +#define SCLK_UART4 27 +#define SCLK_UART5 28 +#define SCLK_I2C0 29 +#define SCLK_I2C1 30 +#define SCLK_I2C2 31 +#define SCLK_I2C3 32 +#define SCLK_I2C4 33 +#define SCLK_PWM0 34 +#define SCLK_PWM1 35 +#define SCLK_SPI0 36 +#define SCLK_SPI1 37 +#define SCLK_TIMER0 38 +#define SCLK_TIMER1 39 +#define SCLK_TIMER2 40 +#define SCLK_TIMER3 41 +#define SCLK_TIMER4 42 +#define SCLK_TIMER5 43 +#define SCLK_TSADC 44 +#define SCLK_SARADC 45 +#define SCLK_OTP 46 +#define SCLK_OTP_USR 47 +#define SCLK_CRYPTO 48 +#define SCLK_CRYPTO_APK 49 +#define SCLK_DDRC 50 +#define SCLK_ISP 51 +#define SCLK_CIF_OUT 52 +#define SCLK_RGA_CORE 53 +#define SCLK_VOPB_PWM 54 +#define SCLK_NANDC 55 +#define SCLK_SDIO 56 +#define SCLK_EMMC 57 +#define SCLK_SFC 58 +#define SCLK_SDMMC 59 +#define SCLK_OTG_ADP 60 +#define SCLK_GMAC_SRC 61 +#define SCLK_GMAC 62 +#define SCLK_GMAC_RX_TX 63 +#define SCLK_MAC_REF 64 +#define SCLK_MAC_REFOUT 65 +#define SCLK_MAC_OUT 66 +#define SCLK_SDMMC_DRV 67 +#define SCLK_SDMMC_SAMPLE 68 +#define SCLK_SDIO_DRV 69 +#define SCLK_SDIO_SAMPLE 70 +#define SCLK_EMMC_DRV 71 +#define SCLK_EMMC_SAMPLE 72 +#define SCLK_GPU 73 +#define SCLK_PVTM 74 +#define SCLK_CORE_VPU 75 +#define SCLK_GMAC_RMII 76 +#define SCLK_UART2_SRC 77 +#define SCLK_NANDC_DIV 78 +#define SCLK_NANDC_DIV50 79 +#define SCLK_SDIO_DIV 80 +#define SCLK_SDIO_DIV50 81 +#define SCLK_EMMC_DIV 82 +#define SCLK_EMMC_DIV50 83 + +/* dclk gates */ +#define DCLK_VOPB 150 +#define DCLK_VOPL 151 + +/* aclk gates */ +#define ACLK_GPU 170 +#define ACLK_BUS_PRE 171 +#define ACLK_CRYPTO 172 +#define ACLK_VI_PRE 173 +#define ACLK_VO_PRE 174 +#define ACLK_VPU 175 +#define ACLK_PERI_PRE 176 +#define ACLK_GMAC 178 +#define ACLK_CIF 179 +#define ACLK_ISP 180 +#define ACLK_VOPB 181 +#define ACLK_VOPL 182 +#define ACLK_RGA 183 +#define ACLK_GIC 184 +#define ACLK_DCF 186 +#define ACLK_DMAC 187 + +/* hclk gates */ +#define HCLK_BUS_PRE 240 +#define HCLK_CRYPTO 241 +#define HCLK_VI_PRE 242 +#define HCLK_VO_PRE 243 +#define HCLK_VPU 244 +#define HCLK_PERI_PRE 245 +#define HCLK_MMC_NAND 246 +#define HCLK_SDMMC 247 +#define HCLK_USB 248 +#define HCLK_CIF 249 +#define HCLK_ISP 250 +#define HCLK_VOPB 251 +#define HCLK_VOPL 252 +#define HCLK_RGA 253 +#define HCLK_NANDC 254 +#define HCLK_SDIO 255 +#define HCLK_EMMC 256 +#define HCLK_SFC 257 +#define HCLK_OTG 258 +#define HCLK_HOST 259 +#define HCLK_HOST_ARB 260 +#define HCLK_PDM 261 +#define HCLK_I2S0 262 +#define HCLK_I2S1 263 +#define HCLK_I2S2 264 + +/* pclk gates */ +#define PCLK_BUS_PRE 320 +#define PCLK_DDR 321 +#define PCLK_VO_PRE 322 +#define PCLK_GMAC 323 +#define PCLK_MIPI_DSI 324 +#define PCLK_MIPIDSIPHY 325 +#define PCLK_MIPICSIPHY 326 +#define PCLK_USB_GRF 327 +#define PCLK_DCF 328 +#define PCLK_UART1 329 +#define PCLK_UART2 330 +#define PCLK_UART3 331 +#define PCLK_UART4 332 +#define PCLK_UART5 333 +#define PCLK_I2C0 334 +#define PCLK_I2C1 335 +#define PCLK_I2C2 336 +#define PCLK_I2C3 337 +#define PCLK_I2C4 338 +#define PCLK_PWM0 339 +#define PCLK_PWM1 340 +#define PCLK_SPI0 341 +#define PCLK_SPI1 342 +#define PCLK_SARADC 343 +#define PCLK_TSADC 344 +#define PCLK_TIMER 345 +#define PCLK_OTP_NS 346 +#define PCLK_WDT_NS 347 +#define PCLK_GPIO1 348 +#define PCLK_GPIO2 349 +#define PCLK_GPIO3 350 +#define PCLK_ISP 351 +#define PCLK_CIF 352 +#define PCLK_OTP_PHY 353 + +#define CLK_NR_CLKS (PCLK_OTP_PHY + 1) + +/* pmu-clocks indices */ + +#define PLL_GPLL 1 + +#define SCLK_RTC32K_PMU 4 +#define SCLK_WIFI_PMU 5 +#define SCLK_UART0_PMU 6 +#define SCLK_PVTM_PMU 7 +#define PCLK_PMU_PRE 8 +#define SCLK_REF24M_PMU 9 +#define SCLK_USBPHY_REF 10 +#define SCLK_MIPIDSIPHY_REF 11 + +#define XIN24M_DIV 12 + +#define PCLK_GPIO0_PMU 20 +#define PCLK_UART0_PMU 21 + +#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_CORE_NOC 13 +#define SRST_STRC_A 14 +#define SRST_L2C 15 + +#define SRST_DAP 16 +#define SRST_CORE_PVTM 17 +#define SRST_GPU 18 +#define SRST_GPU_NIU 19 +#define SRST_UPCTL2 20 +#define SRST_UPCTL2_A 21 +#define SRST_UPCTL2_P 22 +#define SRST_MSCH 23 +#define SRST_MSCH_P 24 +#define SRST_DDRMON_P 25 +#define SRST_DDRSTDBY_P 26 +#define SRST_DDRSTDBY 27 +#define SRST_DDRGRF_p 28 +#define SRST_AXI_SPLIT_A 29 +#define SRST_AXI_CMD_A 30 +#define SRST_AXI_CMD_P 31 + +#define SRST_DDRPHY 32 +#define SRST_DDRPHYDIV 33 +#define SRST_DDRPHY_P 34 +#define SRST_VPU_A 36 +#define SRST_VPU_NIU_A 37 +#define SRST_VPU_H 38 +#define SRST_VPU_NIU_H 39 +#define SRST_VI_NIU_A 40 +#define SRST_VI_NIU_H 41 +#define SRST_ISP_H 42 +#define SRST_ISP 43 +#define SRST_CIF_A 44 +#define SRST_CIF_H 45 +#define SRST_CIF_PCLKIN 46 +#define SRST_MIPICSIPHY_P 47 + +#define SRST_VO_NIU_A 48 +#define SRST_VO_NIU_H 49 +#define SRST_VO_NIU_P 50 +#define SRST_VOPB_A 51 +#define SRST_VOPB_H 52 +#define SRST_VOPB 53 +#define SRST_PWM_VOPB 54 +#define SRST_VOPL_A 55 +#define SRST_VOPL_H 56 +#define SRST_VOPL 57 +#define SRST_RGA_A 58 +#define SRST_RGA_H 59 +#define SRST_RGA 60 +#define SRST_MIPIDSI_HOST_P 61 +#define SRST_MIPIDSIPHY_P 62 +#define SRST_VPU_CORE 63 + +#define SRST_PERI_NIU_A 64 +#define SRST_USB_NIU_H 65 +#define SRST_USB2OTG_H 66 +#define SRST_USB2OTG 67 +#define SRST_USB2OTG_ADP 68 +#define SRST_USB2HOST_H 69 +#define SRST_USB2HOST_ARB_H 70 +#define SRST_USB2HOST_AUX_H 71 +#define SRST_USB2HOST_EHCI 72 +#define SRST_USB2HOST 73 +#define SRST_USBPHYPOR 74 +#define SRST_USBPHY_OTG_PORT 75 +#define SRST_USBPHY_HOST_PORT 76 +#define SRST_USBPHY_GRF 77 +#define SRST_CPU_BOOST_P 78 +#define SRST_CPU_BOOST 79 + +#define SRST_MMC_NAND_NIU_H 80 +#define SRST_SDIO_H 81 +#define SRST_EMMC_H 82 +#define SRST_SFC_H 83 +#define SRST_SFC 84 +#define SRST_SDCARD_NIU_H 85 +#define SRST_SDMMC_H 86 +#define SRST_NANDC_H 89 +#define SRST_NANDC 90 +#define SRST_GMAC_NIU_A 92 +#define SRST_GMAC_NIU_P 93 +#define SRST_GMAC_A 94 + +#define SRST_PMU_NIU_P 96 +#define SRST_PMU_SGRF_P 97 +#define SRST_PMU_GRF_P 98 +#define SRST_PMU 99 +#define SRST_PMU_MEM_P 100 +#define SRST_PMU_GPIO0_P 101 +#define SRST_PMU_UART0_P 102 +#define SRST_PMU_CRU_P 103 +#define SRST_PMU_PVTM 104 +#define SRST_PMU_UART 105 +#define SRST_PMU_NIU_H 106 +#define SRST_PMU_DDR_FAIL_SAVE 107 +#define SRST_PMU_CORE_PERF_A 108 +#define SRST_PMU_CORE_GRF_P 109 +#define SRST_PMU_GPU_PERF_A 110 +#define SRST_PMU_GPU_GRF_P 111 + +#define SRST_CRYPTO_NIU_A 112 +#define SRST_CRYPTO_NIU_H 113 +#define SRST_CRYPTO_A 114 +#define SRST_CRYPTO_H 115 +#define SRST_CRYPTO 116 +#define SRST_CRYPTO_APK 117 +#define SRST_BUS_NIU_H 120 +#define SRST_USB_NIU_P 121 +#define SRST_BUS_TOP_NIU_P 122 +#define SRST_INTMEM_A 123 +#define SRST_GIC_A 124 +#define SRST_ROM_H 126 +#define SRST_DCF_A 127 + +#define SRST_DCF_P 128 +#define SRST_PDM_H 129 +#define SRST_PDM 130 +#define SRST_I2S0_H 131 +#define SRST_I2S0_TX 132 +#define SRST_I2S1_H 133 +#define SRST_I2S1 134 +#define SRST_I2S2_H 135 +#define SRST_I2S2 136 +#define SRST_UART1_P 137 +#define SRST_UART1 138 +#define SRST_UART2_P 139 +#define SRST_UART2 140 +#define SRST_UART3_P 141 +#define SRST_UART3 142 +#define SRST_UART4_P 143 + +#define SRST_UART4 144 +#define SRST_UART5_P 145 +#define SRST_UART5 146 +#define SRST_I2C0_P 147 +#define SRST_I2C0 148 +#define SRST_I2C1_P 149 +#define SRST_I2C1 150 +#define SRST_I2C2_P 151 +#define SRST_I2C2 152 +#define SRST_I2C3_P 153 +#define SRST_I2C3 154 +#define SRST_PWM0_P 157 +#define SRST_PWM0 158 +#define SRST_PWM1_P 159 + +#define SRST_PWM1 160 +#define SRST_SPI0_P 161 +#define SRST_SPI0 162 +#define SRST_SPI1_P 163 +#define SRST_SPI1 164 +#define SRST_SARADC_P 165 +#define SRST_SARADC 166 +#define SRST_TSADC_P 167 +#define SRST_TSADC 168 +#define SRST_TIMER_P 169 +#define SRST_TIMER0 170 +#define SRST_TIMER1 171 +#define SRST_TIMER2 172 +#define SRST_TIMER3 173 +#define SRST_TIMER4 174 +#define SRST_TIMER5 175 + +#define SRST_OTP_NS_P 176 +#define SRST_OTP_NS_SBPI 177 +#define SRST_OTP_NS_USR 178 +#define SRST_OTP_PHY_P 179 +#define SRST_OTP_PHY 180 +#define SRST_WDT_NS_P 181 +#define SRST_GPIO1_P 182 +#define SRST_GPIO2_P 183 +#define SRST_GPIO3_P 184 +#define SRST_SGRF_P 185 +#define SRST_GRF_P 186 +#define SRST_I2S0_RX 191 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/qcom,ipq4019-gcc.h b/roms/u-boot/include/dt-bindings/clock/qcom,ipq4019-gcc.h new file mode 100644 index 000000000..7130e222e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/qcom,ipq4019-gcc.h @@ -0,0 +1,96 @@ +/* Copyright (c) 2015 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +#ifndef __QCOM_CLK_IPQ4019_H__ +#define __QCOM_CLK_IPQ4019_H__ + +#define GCC_DUMMY_CLK 0 +#define AUDIO_CLK_SRC 1 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 2 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 3 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 4 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 5 +#define BLSP1_UART1_APPS_CLK_SRC 6 +#define BLSP1_UART2_APPS_CLK_SRC 7 +#define GCC_USB3_MOCK_UTMI_CLK_SRC 8 +#define GCC_APPS_CLK_SRC 9 +#define GCC_APPS_AHB_CLK_SRC 10 +#define GP1_CLK_SRC 11 +#define GP2_CLK_SRC 12 +#define GP3_CLK_SRC 13 +#define SDCC1_APPS_CLK_SRC 14 +#define FEPHY_125M_DLY_CLK_SRC 15 +#define WCSS2G_CLK_SRC 16 +#define WCSS5G_CLK_SRC 17 +#define GCC_APSS_AHB_CLK 18 +#define GCC_AUDIO_AHB_CLK 19 +#define GCC_AUDIO_PWM_CLK 20 +#define GCC_BLSP1_AHB_CLK 21 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 +#define GCC_BLSP1_UART1_APPS_CLK 26 +#define GCC_BLSP1_UART2_APPS_CLK 27 +#define GCC_DCD_XO_CLK 28 +#define GCC_GP1_CLK 29 +#define GCC_GP2_CLK 30 +#define GCC_GP3_CLK 31 +#define GCC_BOOT_ROM_AHB_CLK 32 +#define GCC_CRYPTO_AHB_CLK 33 +#define GCC_CRYPTO_AXI_CLK 34 +#define GCC_CRYPTO_CLK 35 +#define GCC_ESS_CLK 36 +#define GCC_IMEM_AXI_CLK 37 +#define GCC_IMEM_CFG_AHB_CLK 38 +#define GCC_PCIE_AHB_CLK 39 +#define GCC_PCIE_AXI_M_CLK 40 +#define GCC_PCIE_AXI_S_CLK 41 +#define GCC_PCNOC_AHB_CLK 42 +#define GCC_PRNG_AHB_CLK 43 +#define GCC_QPIC_AHB_CLK 44 +#define GCC_QPIC_CLK 45 +#define GCC_SDCC1_AHB_CLK 46 +#define GCC_SDCC1_APPS_CLK 47 +#define GCC_SNOC_PCNOC_AHB_CLK 48 +#define GCC_SYS_NOC_125M_CLK 49 +#define GCC_SYS_NOC_AXI_CLK 50 +#define GCC_TCSR_AHB_CLK 51 +#define GCC_TLMM_AHB_CLK 52 +#define GCC_USB2_MASTER_CLK 53 +#define GCC_USB2_SLEEP_CLK 54 +#define GCC_USB2_MOCK_UTMI_CLK 55 +#define GCC_USB3_MASTER_CLK 56 +#define GCC_USB3_SLEEP_CLK 57 +#define GCC_USB3_MOCK_UTMI_CLK 58 +#define GCC_WCSS2G_CLK 59 +#define GCC_WCSS2G_REF_CLK 60 +#define GCC_WCSS2G_RTC_CLK 61 +#define GCC_WCSS5G_CLK 62 +#define GCC_WCSS5G_REF_CLK 63 +#define GCC_WCSS5G_RTC_CLK 64 +#define GCC_APSS_DDRPLL_VCO 65 +#define GCC_SDCC_PLLDIV_CLK 66 +#define GCC_FEPLL_VCO 67 +#define GCC_FEPLL125_CLK 68 +#define GCC_FEPLL125DLY_CLK 69 +#define GCC_FEPLL200_CLK 70 +#define GCC_FEPLL500_CLK 71 +#define GCC_FEPLL_WCSS2G_CLK 72 +#define GCC_FEPLL_WCSS5G_CLK 73 +#define GCC_APSS_CPU_PLLDIV_CLK 74 +#define GCC_PCNOC_AHB_CLK_SRC 75 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/r7s72100-clock.h b/roms/u-boot/include/dt-bindings/clock/r7s72100-clock.h new file mode 100644 index 000000000..a267ac250 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r7s72100-clock.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2014 Renesas Solutions Corp. + * Copyright (C) 2014 Wolfram Sang, Sang Engineering + */ + +#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__ +#define __DT_BINDINGS_CLOCK_R7S72100_H__ + +#define R7S72100_CLK_PLL 0 +#define R7S72100_CLK_I 1 +#define R7S72100_CLK_G 2 + +/* MSTP2 */ +#define R7S72100_CLK_CORESIGHT 0 + +/* MSTP3 */ +#define R7S72100_CLK_IEBUS 7 +#define R7S72100_CLK_IRDA 6 +#define R7S72100_CLK_LIN0 5 +#define R7S72100_CLK_LIN1 4 +#define R7S72100_CLK_MTU2 3 +#define R7S72100_CLK_CAN 2 +#define R7S72100_CLK_ADCPWR 1 +#define R7S72100_CLK_PWM 0 + +/* MSTP4 */ +#define R7S72100_CLK_SCIF0 7 +#define R7S72100_CLK_SCIF1 6 +#define R7S72100_CLK_SCIF2 5 +#define R7S72100_CLK_SCIF3 4 +#define R7S72100_CLK_SCIF4 3 +#define R7S72100_CLK_SCIF5 2 +#define R7S72100_CLK_SCIF6 1 +#define R7S72100_CLK_SCIF7 0 + +/* MSTP5 */ +#define R7S72100_CLK_SCI0 7 +#define R7S72100_CLK_SCI1 6 +#define R7S72100_CLK_SG0 5 +#define R7S72100_CLK_SG1 4 +#define R7S72100_CLK_SG2 3 +#define R7S72100_CLK_SG3 2 +#define R7S72100_CLK_OSTM0 1 +#define R7S72100_CLK_OSTM1 0 + +/* MSTP6 */ +#define R7S72100_CLK_ADC 7 +#define R7S72100_CLK_CEU 6 +#define R7S72100_CLK_DOC0 5 +#define R7S72100_CLK_DOC1 4 +#define R7S72100_CLK_DRC0 3 +#define R7S72100_CLK_DRC1 2 +#define R7S72100_CLK_JCU 1 +#define R7S72100_CLK_RTC 0 + +/* MSTP7 */ +#define R7S72100_CLK_VDEC0 7 +#define R7S72100_CLK_VDEC1 6 +#define R7S72100_CLK_ETHER 4 +#define R7S72100_CLK_NAND 3 +#define R7S72100_CLK_USB0 1 +#define R7S72100_CLK_USB1 0 + +/* MSTP8 */ +#define R7S72100_CLK_IMR0 7 +#define R7S72100_CLK_IMR1 6 +#define R7S72100_CLK_IMRDISP 5 +#define R7S72100_CLK_MMCIF 4 +#define R7S72100_CLK_MLB 3 +#define R7S72100_CLK_ETHAVB 2 +#define R7S72100_CLK_SCUX 1 + +/* MSTP9 */ +#define R7S72100_CLK_I2C0 7 +#define R7S72100_CLK_I2C1 6 +#define R7S72100_CLK_I2C2 5 +#define R7S72100_CLK_I2C3 4 +#define R7S72100_CLK_SPIBSC0 3 +#define R7S72100_CLK_SPIBSC1 2 +#define R7S72100_CLK_VDC50 1 /* and LVDS */ +#define R7S72100_CLK_VDC51 0 + +/* MSTP10 */ +#define R7S72100_CLK_SPI0 7 +#define R7S72100_CLK_SPI1 6 +#define R7S72100_CLK_SPI2 5 +#define R7S72100_CLK_SPI3 4 +#define R7S72100_CLK_SPI4 3 +#define R7S72100_CLK_CDROM 2 +#define R7S72100_CLK_SPDIF 1 +#define R7S72100_CLK_RGPVG2 0 + +/* MSTP11 */ +#define R7S72100_CLK_SSI0 5 +#define R7S72100_CLK_SSI1 4 +#define R7S72100_CLK_SSI2 3 +#define R7S72100_CLK_SSI3 2 +#define R7S72100_CLK_SSI4 1 +#define R7S72100_CLK_SSI5 0 + +/* MSTP12 */ +#define R7S72100_CLK_SDHI00 3 +#define R7S72100_CLK_SDHI01 2 +#define R7S72100_CLK_SDHI10 1 +#define R7S72100_CLK_SDHI11 0 + +/* MSTP13 */ +#define R7S72100_CLK_PIX1 2 +#define R7S72100_CLK_PIX0 1 + +#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/r8a774a1-cpg-mssr.h new file mode 100644 index 000000000..67bf8cdf4 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a774a1-cpg-mssr.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ + +#include + +/* r8a774a1 CPG Core Clocks */ +#define R8A774A1_CLK_Z 0 +#define R8A774A1_CLK_Z2 1 +#define R8A774A1_CLK_ZG 2 +#define R8A774A1_CLK_ZTR 3 +#define R8A774A1_CLK_ZTRD2 4 +#define R8A774A1_CLK_ZT 5 +#define R8A774A1_CLK_ZX 6 +#define R8A774A1_CLK_S0D1 7 +#define R8A774A1_CLK_S0D2 8 +#define R8A774A1_CLK_S0D3 9 +#define R8A774A1_CLK_S0D4 10 +#define R8A774A1_CLK_S0D6 11 +#define R8A774A1_CLK_S0D8 12 +#define R8A774A1_CLK_S0D12 13 +#define R8A774A1_CLK_S1D2 14 +#define R8A774A1_CLK_S1D4 15 +#define R8A774A1_CLK_S2D1 16 +#define R8A774A1_CLK_S2D2 17 +#define R8A774A1_CLK_S2D4 18 +#define R8A774A1_CLK_S3D1 19 +#define R8A774A1_CLK_S3D2 20 +#define R8A774A1_CLK_S3D4 21 +#define R8A774A1_CLK_LB 22 +#define R8A774A1_CLK_CL 23 +#define R8A774A1_CLK_ZB3 24 +#define R8A774A1_CLK_ZB3D2 25 +#define R8A774A1_CLK_ZB3D4 26 +#define R8A774A1_CLK_CR 27 +#define R8A774A1_CLK_CRD2 28 +#define R8A774A1_CLK_SD0H 29 +#define R8A774A1_CLK_SD0 30 +#define R8A774A1_CLK_SD1H 31 +#define R8A774A1_CLK_SD1 32 +#define R8A774A1_CLK_SD2H 33 +#define R8A774A1_CLK_SD2 34 +#define R8A774A1_CLK_SD3H 35 +#define R8A774A1_CLK_SD3 36 +#define R8A774A1_CLK_RPC 37 +#define R8A774A1_CLK_RPCD2 38 +#define R8A774A1_CLK_MSO 39 +#define R8A774A1_CLK_HDMI 40 +#define R8A774A1_CLK_CSI0 41 +#define R8A774A1_CLK_CP 42 +#define R8A774A1_CLK_CPEX 43 +#define R8A774A1_CLK_R 44 +#define R8A774A1_CLK_OSC 45 +#define R8A774A1_CLK_CANFD 46 + +#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a774b1-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/r8a774b1-cpg-mssr.h new file mode 100644 index 000000000..28e0f8f76 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a774b1-cpg-mssr.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ + +#include + +/* r8a774b1 CPG Core Clocks */ +#define R8A774B1_CLK_Z 0 +#define R8A774B1_CLK_ZG 1 +#define R8A774B1_CLK_ZTR 2 +#define R8A774B1_CLK_ZTRD2 3 +#define R8A774B1_CLK_ZT 4 +#define R8A774B1_CLK_ZX 5 +#define R8A774B1_CLK_S0D1 6 +#define R8A774B1_CLK_S0D2 7 +#define R8A774B1_CLK_S0D3 8 +#define R8A774B1_CLK_S0D4 9 +#define R8A774B1_CLK_S0D6 10 +#define R8A774B1_CLK_S0D8 11 +#define R8A774B1_CLK_S0D12 12 +#define R8A774B1_CLK_S1D2 13 +#define R8A774B1_CLK_S1D4 14 +#define R8A774B1_CLK_S2D1 15 +#define R8A774B1_CLK_S2D2 16 +#define R8A774B1_CLK_S2D4 17 +#define R8A774B1_CLK_S3D1 18 +#define R8A774B1_CLK_S3D2 19 +#define R8A774B1_CLK_S3D4 20 +#define R8A774B1_CLK_LB 21 +#define R8A774B1_CLK_CL 22 +#define R8A774B1_CLK_ZB3 23 +#define R8A774B1_CLK_ZB3D2 24 +#define R8A774B1_CLK_CR 25 +#define R8A774B1_CLK_DDR 26 +#define R8A774B1_CLK_SD0H 27 +#define R8A774B1_CLK_SD0 28 +#define R8A774B1_CLK_SD1H 29 +#define R8A774B1_CLK_SD1 30 +#define R8A774B1_CLK_SD2H 31 +#define R8A774B1_CLK_SD2 32 +#define R8A774B1_CLK_SD3H 33 +#define R8A774B1_CLK_SD3 34 +#define R8A774B1_CLK_RPC 35 +#define R8A774B1_CLK_RPCD2 36 +#define R8A774B1_CLK_MSO 37 +#define R8A774B1_CLK_HDMI 38 +#define R8A774B1_CLK_CSI0 39 +#define R8A774B1_CLK_CP 40 +#define R8A774B1_CLK_CPEX 41 +#define R8A774B1_CLK_R 42 +#define R8A774B1_CLK_OSC 43 +#define R8A774B1_CLK_CANFD 44 + +#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a774c0-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/r8a774c0-cpg-mssr.h new file mode 100644 index 000000000..9db5c76e2 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a774c0-cpg-mssr.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ + +#include + +/* r8a774c0 CPG Core Clocks */ +#define R8A774C0_CLK_Z2 0 +#define R8A774C0_CLK_ZG 1 +#define R8A774C0_CLK_ZTR 2 +#define R8A774C0_CLK_ZT 3 +#define R8A774C0_CLK_ZX 4 +#define R8A774C0_CLK_S0D1 5 +#define R8A774C0_CLK_S0D3 6 +#define R8A774C0_CLK_S0D6 7 +#define R8A774C0_CLK_S0D12 8 +#define R8A774C0_CLK_S0D24 9 +#define R8A774C0_CLK_S1D1 10 +#define R8A774C0_CLK_S1D2 11 +#define R8A774C0_CLK_S1D4 12 +#define R8A774C0_CLK_S2D1 13 +#define R8A774C0_CLK_S2D2 14 +#define R8A774C0_CLK_S2D4 15 +#define R8A774C0_CLK_S3D1 16 +#define R8A774C0_CLK_S3D2 17 +#define R8A774C0_CLK_S3D4 18 +#define R8A774C0_CLK_S0D6C 19 +#define R8A774C0_CLK_S3D1C 20 +#define R8A774C0_CLK_S3D2C 21 +#define R8A774C0_CLK_S3D4C 22 +#define R8A774C0_CLK_LB 23 +#define R8A774C0_CLK_CL 24 +#define R8A774C0_CLK_ZB3 25 +#define R8A774C0_CLK_ZB3D2 26 +#define R8A774C0_CLK_CR 27 +#define R8A774C0_CLK_CRD2 28 +#define R8A774C0_CLK_SD0H 29 +#define R8A774C0_CLK_SD0 30 +#define R8A774C0_CLK_SD1H 31 +#define R8A774C0_CLK_SD1 32 +#define R8A774C0_CLK_SD3H 33 +#define R8A774C0_CLK_SD3 34 +#define R8A774C0_CLK_RPC 35 +#define R8A774C0_CLK_RPCD2 36 +#define R8A774C0_CLK_ZA2 37 +#define R8A774C0_CLK_ZA8 38 +#define R8A774C0_CLK_Z2D 39 +#define R8A774C0_CLK_MSO 40 +#define R8A774C0_CLK_R 41 +#define R8A774C0_CLK_OSC 42 +#define R8A774C0_CLK_LV0 43 +#define R8A774C0_CLK_LV1 44 +#define R8A774C0_CLK_CSI0 45 +#define R8A774C0_CLK_CP 46 +#define R8A774C0_CLK_CPEX 47 +#define R8A774C0_CLK_CANFD 48 + +#endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a774e1-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/r8a774e1-cpg-mssr.h new file mode 100644 index 000000000..b2fc1d1c3 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a774e1-cpg-mssr.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ + +#include + +/* R8A774E1 CPG Core Clocks */ +#define R8A774E1_CLK_Z 0 +#define R8A774E1_CLK_Z2 1 +#define R8A774E1_CLK_ZG 2 +#define R8A774E1_CLK_ZTR 3 +#define R8A774E1_CLK_ZTRD2 4 +#define R8A774E1_CLK_ZT 5 +#define R8A774E1_CLK_ZX 6 +#define R8A774E1_CLK_S0D1 7 +#define R8A774E1_CLK_S0D2 8 +#define R8A774E1_CLK_S0D3 9 +#define R8A774E1_CLK_S0D4 10 +#define R8A774E1_CLK_S0D6 11 +#define R8A774E1_CLK_S0D8 12 +#define R8A774E1_CLK_S0D12 13 +#define R8A774E1_CLK_S1D2 14 +#define R8A774E1_CLK_S1D4 15 +#define R8A774E1_CLK_S2D1 16 +#define R8A774E1_CLK_S2D2 17 +#define R8A774E1_CLK_S2D4 18 +#define R8A774E1_CLK_S3D1 19 +#define R8A774E1_CLK_S3D2 20 +#define R8A774E1_CLK_S3D4 21 +#define R8A774E1_CLK_LB 22 +#define R8A774E1_CLK_CL 23 +#define R8A774E1_CLK_ZB3 24 +#define R8A774E1_CLK_ZB3D2 25 +#define R8A774E1_CLK_ZB3D4 26 +#define R8A774E1_CLK_CR 27 +#define R8A774E1_CLK_CRD2 28 +#define R8A774E1_CLK_SD0H 29 +#define R8A774E1_CLK_SD0 30 +#define R8A774E1_CLK_SD1H 31 +#define R8A774E1_CLK_SD1 32 +#define R8A774E1_CLK_SD2H 33 +#define R8A774E1_CLK_SD2 34 +#define R8A774E1_CLK_SD3H 35 +#define R8A774E1_CLK_SD3 36 +#define R8A774E1_CLK_RPC 37 +#define R8A774E1_CLK_RPCD2 38 +#define R8A774E1_CLK_MSO 39 +#define R8A774E1_CLK_HDMI 40 +#define R8A774E1_CLK_CSI0 41 +#define R8A774E1_CLK_CP 42 +#define R8A774E1_CLK_CPEX 43 +#define R8A774E1_CLK_R 44 +#define R8A774E1_CLK_OSC 45 +#define R8A774E1_CLK_CANFD 46 + +#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a7790-clock.h b/roms/u-boot/include/dt-bindings/clock/r8a7790-clock.h new file mode 100644 index 000000000..c92ff1e60 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a7790-clock.h @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2013 Ideas On Board SPRL + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__ +#define __DT_BINDINGS_CLOCK_R8A7790_H__ + +/* CPG */ +#define R8A7790_CLK_MAIN 0 +#define R8A7790_CLK_PLL0 1 +#define R8A7790_CLK_PLL1 2 +#define R8A7790_CLK_PLL3 3 +#define R8A7790_CLK_LB 4 +#define R8A7790_CLK_QSPI 5 +#define R8A7790_CLK_SDH 6 +#define R8A7790_CLK_SD0 7 +#define R8A7790_CLK_SD1 8 +#define R8A7790_CLK_Z 9 +#define R8A7790_CLK_RCAN 10 +#define R8A7790_CLK_ADSP 11 + +/* MSTP0 */ +#define R8A7790_CLK_MSIOF0 0 + +/* MSTP1 */ +#define R8A7790_CLK_VCP1 0 +#define R8A7790_CLK_VCP0 1 +#define R8A7790_CLK_VPC1 2 +#define R8A7790_CLK_VPC0 3 +#define R8A7790_CLK_JPU 6 +#define R8A7790_CLK_SSP1 9 +#define R8A7790_CLK_TMU1 11 +#define R8A7790_CLK_3DG 12 +#define R8A7790_CLK_2DDMAC 15 +#define R8A7790_CLK_FDP1_2 17 +#define R8A7790_CLK_FDP1_1 18 +#define R8A7790_CLK_FDP1_0 19 +#define R8A7790_CLK_TMU3 21 +#define R8A7790_CLK_TMU2 22 +#define R8A7790_CLK_CMT0 24 +#define R8A7790_CLK_TMU0 25 +#define R8A7790_CLK_VSP1_DU1 27 +#define R8A7790_CLK_VSP1_DU0 28 +#define R8A7790_CLK_VSP1_R 30 +#define R8A7790_CLK_VSP1_S 31 + +/* MSTP2 */ +#define R8A7790_CLK_SCIFA2 2 +#define R8A7790_CLK_SCIFA1 3 +#define R8A7790_CLK_SCIFA0 4 +#define R8A7790_CLK_MSIOF2 5 +#define R8A7790_CLK_SCIFB0 6 +#define R8A7790_CLK_SCIFB1 7 +#define R8A7790_CLK_MSIOF1 8 +#define R8A7790_CLK_MSIOF3 15 +#define R8A7790_CLK_SCIFB2 16 +#define R8A7790_CLK_SYS_DMAC1 18 +#define R8A7790_CLK_SYS_DMAC0 19 + +/* MSTP3 */ +#define R8A7790_CLK_IIC2 0 +#define R8A7790_CLK_TPU0 4 +#define R8A7790_CLK_MMCIF1 5 +#define R8A7790_CLK_SCIF2 10 +#define R8A7790_CLK_SDHI3 11 +#define R8A7790_CLK_SDHI2 12 +#define R8A7790_CLK_SDHI1 13 +#define R8A7790_CLK_SDHI0 14 +#define R8A7790_CLK_MMCIF0 15 +#define R8A7790_CLK_IIC0 18 +#define R8A7790_CLK_PCIEC 19 +#define R8A7790_CLK_IIC1 23 +#define R8A7790_CLK_SSUSB 28 +#define R8A7790_CLK_CMT1 29 +#define R8A7790_CLK_USBDMAC0 30 +#define R8A7790_CLK_USBDMAC1 31 + +/* MSTP4 */ +#define R8A7790_CLK_IRQC 7 +#define R8A7790_CLK_INTC_SYS 8 + +/* MSTP5 */ +#define R8A7790_CLK_AUDIO_DMAC1 1 +#define R8A7790_CLK_AUDIO_DMAC0 2 +#define R8A7790_CLK_ADSP_MOD 6 +#define R8A7790_CLK_THERMAL 22 +#define R8A7790_CLK_PWM 23 + +/* MSTP7 */ +#define R8A7790_CLK_EHCI 3 +#define R8A7790_CLK_HSUSB 4 +#define R8A7790_CLK_HSCIF1 16 +#define R8A7790_CLK_HSCIF0 17 +#define R8A7790_CLK_SCIF1 20 +#define R8A7790_CLK_SCIF0 21 +#define R8A7790_CLK_DU2 22 +#define R8A7790_CLK_DU1 23 +#define R8A7790_CLK_DU0 24 +#define R8A7790_CLK_LVDS1 25 +#define R8A7790_CLK_LVDS0 26 + +/* MSTP8 */ +#define R8A7790_CLK_MLB 2 +#define R8A7790_CLK_VIN3 8 +#define R8A7790_CLK_VIN2 9 +#define R8A7790_CLK_VIN1 10 +#define R8A7790_CLK_VIN0 11 +#define R8A7790_CLK_ETHERAVB 12 +#define R8A7790_CLK_ETHER 13 +#define R8A7790_CLK_SATA1 14 +#define R8A7790_CLK_SATA0 15 + +/* MSTP9 */ +#define R8A7790_CLK_GPIO5 7 +#define R8A7790_CLK_GPIO4 8 +#define R8A7790_CLK_GPIO3 9 +#define R8A7790_CLK_GPIO2 10 +#define R8A7790_CLK_GPIO1 11 +#define R8A7790_CLK_GPIO0 12 +#define R8A7790_CLK_RCAN1 15 +#define R8A7790_CLK_RCAN0 16 +#define R8A7790_CLK_QSPI_MOD 17 +#define R8A7790_CLK_IICDVFS 26 +#define R8A7790_CLK_I2C3 28 +#define R8A7790_CLK_I2C2 29 +#define R8A7790_CLK_I2C1 30 +#define R8A7790_CLK_I2C0 31 + +/* MSTP10 */ +#define R8A7790_CLK_SSI_ALL 5 +#define R8A7790_CLK_SSI9 6 +#define R8A7790_CLK_SSI8 7 +#define R8A7790_CLK_SSI7 8 +#define R8A7790_CLK_SSI6 9 +#define R8A7790_CLK_SSI5 10 +#define R8A7790_CLK_SSI4 11 +#define R8A7790_CLK_SSI3 12 +#define R8A7790_CLK_SSI2 13 +#define R8A7790_CLK_SSI1 14 +#define R8A7790_CLK_SSI0 15 +#define R8A7790_CLK_SCU_ALL 17 +#define R8A7790_CLK_SCU_DVC1 18 +#define R8A7790_CLK_SCU_DVC0 19 +#define R8A7790_CLK_SCU_CTU1_MIX1 20 +#define R8A7790_CLK_SCU_CTU0_MIX0 21 +#define R8A7790_CLK_SCU_SRC9 22 +#define R8A7790_CLK_SCU_SRC8 23 +#define R8A7790_CLK_SCU_SRC7 24 +#define R8A7790_CLK_SCU_SRC6 25 +#define R8A7790_CLK_SCU_SRC5 26 +#define R8A7790_CLK_SCU_SRC4 27 +#define R8A7790_CLK_SCU_SRC3 28 +#define R8A7790_CLK_SCU_SRC2 29 +#define R8A7790_CLK_SCU_SRC1 30 +#define R8A7790_CLK_SCU_SRC0 31 + +#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/r8a7790-cpg-mssr.h new file mode 100644 index 000000000..c5955b56b --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a7790-cpg-mssr.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2015 Renesas Electronics Corp. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ + +#include + +/* r8a7790 CPG Core Clocks */ +#define R8A7790_CLK_Z 0 +#define R8A7790_CLK_Z2 1 +#define R8A7790_CLK_ZG 2 +#define R8A7790_CLK_ZTR 3 +#define R8A7790_CLK_ZTRD2 4 +#define R8A7790_CLK_ZT 5 +#define R8A7790_CLK_ZX 6 +#define R8A7790_CLK_ZS 7 +#define R8A7790_CLK_HP 8 +#define R8A7790_CLK_I 9 +#define R8A7790_CLK_B 10 +#define R8A7790_CLK_LB 11 +#define R8A7790_CLK_P 12 +#define R8A7790_CLK_CL 13 +#define R8A7790_CLK_M2 14 +#define R8A7790_CLK_ADSP 15 +#define R8A7790_CLK_IMP 16 +#define R8A7790_CLK_ZB3 17 +#define R8A7790_CLK_ZB3D2 18 +#define R8A7790_CLK_DDR 19 +#define R8A7790_CLK_SDH 20 +#define R8A7790_CLK_SD0 21 +#define R8A7790_CLK_SD1 22 +#define R8A7790_CLK_SD2 23 +#define R8A7790_CLK_SD3 24 +#define R8A7790_CLK_MMC0 25 +#define R8A7790_CLK_MMC1 26 +#define R8A7790_CLK_MP 27 +#define R8A7790_CLK_SSP 28 +#define R8A7790_CLK_SSPRS 29 +#define R8A7790_CLK_QSPI 30 +#define R8A7790_CLK_CP 31 +#define R8A7790_CLK_RCAN 32 +#define R8A7790_CLK_R 33 +#define R8A7790_CLK_OSC 34 + +#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a7791-clock.h b/roms/u-boot/include/dt-bindings/clock/r8a7791-clock.h new file mode 100644 index 000000000..bb4f18b1b --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a7791-clock.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2013 Ideas On Board SPRL + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__ +#define __DT_BINDINGS_CLOCK_R8A7791_H__ + +/* CPG */ +#define R8A7791_CLK_MAIN 0 +#define R8A7791_CLK_PLL0 1 +#define R8A7791_CLK_PLL1 2 +#define R8A7791_CLK_PLL3 3 +#define R8A7791_CLK_LB 4 +#define R8A7791_CLK_QSPI 5 +#define R8A7791_CLK_SDH 6 +#define R8A7791_CLK_SD0 7 +#define R8A7791_CLK_Z 8 +#define R8A7791_CLK_RCAN 9 +#define R8A7791_CLK_ADSP 10 + +/* MSTP0 */ +#define R8A7791_CLK_MSIOF0 0 + +/* MSTP1 */ +#define R8A7791_CLK_VCP0 1 +#define R8A7791_CLK_VPC0 3 +#define R8A7791_CLK_JPU 6 +#define R8A7791_CLK_SSP1 9 +#define R8A7791_CLK_TMU1 11 +#define R8A7791_CLK_3DG 12 +#define R8A7791_CLK_2DDMAC 15 +#define R8A7791_CLK_FDP1_1 18 +#define R8A7791_CLK_FDP1_0 19 +#define R8A7791_CLK_TMU3 21 +#define R8A7791_CLK_TMU2 22 +#define R8A7791_CLK_CMT0 24 +#define R8A7791_CLK_TMU0 25 +#define R8A7791_CLK_VSP1_DU1 27 +#define R8A7791_CLK_VSP1_DU0 28 +#define R8A7791_CLK_VSP1_S 31 + +/* MSTP2 */ +#define R8A7791_CLK_SCIFA2 2 +#define R8A7791_CLK_SCIFA1 3 +#define R8A7791_CLK_SCIFA0 4 +#define R8A7791_CLK_MSIOF2 5 +#define R8A7791_CLK_SCIFB0 6 +#define R8A7791_CLK_SCIFB1 7 +#define R8A7791_CLK_MSIOF1 8 +#define R8A7791_CLK_SCIFB2 16 +#define R8A7791_CLK_SYS_DMAC1 18 +#define R8A7791_CLK_SYS_DMAC0 19 + +/* MSTP3 */ +#define R8A7791_CLK_TPU0 4 +#define R8A7791_CLK_SDHI2 11 +#define R8A7791_CLK_SDHI1 12 +#define R8A7791_CLK_SDHI0 14 +#define R8A7791_CLK_MMCIF0 15 +#define R8A7791_CLK_IIC0 18 +#define R8A7791_CLK_PCIEC 19 +#define R8A7791_CLK_IIC1 23 +#define R8A7791_CLK_SSUSB 28 +#define R8A7791_CLK_CMT1 29 +#define R8A7791_CLK_USBDMAC0 30 +#define R8A7791_CLK_USBDMAC1 31 + +/* MSTP4 */ +#define R8A7791_CLK_IRQC 7 +#define R8A7791_CLK_INTC_SYS 8 + +/* MSTP5 */ +#define R8A7791_CLK_AUDIO_DMAC1 1 +#define R8A7791_CLK_AUDIO_DMAC0 2 +#define R8A7791_CLK_ADSP_MOD 6 +#define R8A7791_CLK_THERMAL 22 +#define R8A7791_CLK_PWM 23 + +/* MSTP7 */ +#define R8A7791_CLK_EHCI 3 +#define R8A7791_CLK_HSUSB 4 +#define R8A7791_CLK_HSCIF2 13 +#define R8A7791_CLK_SCIF5 14 +#define R8A7791_CLK_SCIF4 15 +#define R8A7791_CLK_HSCIF1 16 +#define R8A7791_CLK_HSCIF0 17 +#define R8A7791_CLK_SCIF3 18 +#define R8A7791_CLK_SCIF2 19 +#define R8A7791_CLK_SCIF1 20 +#define R8A7791_CLK_SCIF0 21 +#define R8A7791_CLK_DU1 23 +#define R8A7791_CLK_DU0 24 +#define R8A7791_CLK_LVDS0 26 + +/* MSTP8 */ +#define R8A7791_CLK_IPMMU_SGX 0 +#define R8A7791_CLK_MLB 2 +#define R8A7791_CLK_VIN2 9 +#define R8A7791_CLK_VIN1 10 +#define R8A7791_CLK_VIN0 11 +#define R8A7791_CLK_ETHERAVB 12 +#define R8A7791_CLK_ETHER 13 +#define R8A7791_CLK_SATA1 14 +#define R8A7791_CLK_SATA0 15 + +/* MSTP9 */ +#define R8A7791_CLK_GYROADC 1 +#define R8A7791_CLK_GPIO7 4 +#define R8A7791_CLK_GPIO6 5 +#define R8A7791_CLK_GPIO5 7 +#define R8A7791_CLK_GPIO4 8 +#define R8A7791_CLK_GPIO3 9 +#define R8A7791_CLK_GPIO2 10 +#define R8A7791_CLK_GPIO1 11 +#define R8A7791_CLK_GPIO0 12 +#define R8A7791_CLK_RCAN1 15 +#define R8A7791_CLK_RCAN0 16 +#define R8A7791_CLK_QSPI_MOD 17 +#define R8A7791_CLK_I2C5 25 +#define R8A7791_CLK_IICDVFS 26 +#define R8A7791_CLK_I2C4 27 +#define R8A7791_CLK_I2C3 28 +#define R8A7791_CLK_I2C2 29 +#define R8A7791_CLK_I2C1 30 +#define R8A7791_CLK_I2C0 31 + +/* MSTP10 */ +#define R8A7791_CLK_SSI_ALL 5 +#define R8A7791_CLK_SSI9 6 +#define R8A7791_CLK_SSI8 7 +#define R8A7791_CLK_SSI7 8 +#define R8A7791_CLK_SSI6 9 +#define R8A7791_CLK_SSI5 10 +#define R8A7791_CLK_SSI4 11 +#define R8A7791_CLK_SSI3 12 +#define R8A7791_CLK_SSI2 13 +#define R8A7791_CLK_SSI1 14 +#define R8A7791_CLK_SSI0 15 +#define R8A7791_CLK_SCU_ALL 17 +#define R8A7791_CLK_SCU_DVC1 18 +#define R8A7791_CLK_SCU_DVC0 19 +#define R8A7791_CLK_SCU_CTU1_MIX1 20 +#define R8A7791_CLK_SCU_CTU0_MIX0 21 +#define R8A7791_CLK_SCU_SRC9 22 +#define R8A7791_CLK_SCU_SRC8 23 +#define R8A7791_CLK_SCU_SRC7 24 +#define R8A7791_CLK_SCU_SRC6 25 +#define R8A7791_CLK_SCU_SRC5 26 +#define R8A7791_CLK_SCU_SRC4 27 +#define R8A7791_CLK_SCU_SRC3 28 +#define R8A7791_CLK_SCU_SRC2 29 +#define R8A7791_CLK_SCU_SRC1 30 +#define R8A7791_CLK_SCU_SRC0 31 + +/* MSTP11 */ +#define R8A7791_CLK_SCIFA3 6 +#define R8A7791_CLK_SCIFA4 7 +#define R8A7791_CLK_SCIFA5 8 + +#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a7791-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/r8a7791-cpg-mssr.h new file mode 100644 index 000000000..aadd06c56 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a7791-cpg-mssr.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2015 Renesas Electronics Corp. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ + +#include + +/* r8a7791 CPG Core Clocks */ +#define R8A7791_CLK_Z 0 +#define R8A7791_CLK_ZG 1 +#define R8A7791_CLK_ZTR 2 +#define R8A7791_CLK_ZTRD2 3 +#define R8A7791_CLK_ZT 4 +#define R8A7791_CLK_ZX 5 +#define R8A7791_CLK_ZS 6 +#define R8A7791_CLK_HP 7 +#define R8A7791_CLK_I 8 +#define R8A7791_CLK_B 9 +#define R8A7791_CLK_LB 10 +#define R8A7791_CLK_P 11 +#define R8A7791_CLK_CL 12 +#define R8A7791_CLK_M2 13 +#define R8A7791_CLK_ADSP 14 +#define R8A7791_CLK_ZB3 15 +#define R8A7791_CLK_ZB3D2 16 +#define R8A7791_CLK_DDR 17 +#define R8A7791_CLK_SDH 18 +#define R8A7791_CLK_SD0 19 +#define R8A7791_CLK_SD2 20 +#define R8A7791_CLK_SD3 21 +#define R8A7791_CLK_MMC0 22 +#define R8A7791_CLK_MP 23 +#define R8A7791_CLK_SSP 24 +#define R8A7791_CLK_SSPRS 25 +#define R8A7791_CLK_QSPI 26 +#define R8A7791_CLK_CP 27 +#define R8A7791_CLK_RCAN 28 +#define R8A7791_CLK_R 29 +#define R8A7791_CLK_OSC 30 + +#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a7792-clock.h b/roms/u-boot/include/dt-bindings/clock/r8a7792-clock.h new file mode 100644 index 000000000..2948d9ce3 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a7792-clock.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2016 Cogent Embedded, Inc. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__ +#define __DT_BINDINGS_CLOCK_R8A7792_H__ + +/* CPG */ +#define R8A7792_CLK_MAIN 0 +#define R8A7792_CLK_PLL0 1 +#define R8A7792_CLK_PLL1 2 +#define R8A7792_CLK_PLL3 3 +#define R8A7792_CLK_LB 4 +#define R8A7792_CLK_QSPI 5 + +/* MSTP0 */ +#define R8A7792_CLK_MSIOF0 0 + +/* MSTP1 */ +#define R8A7792_CLK_JPU 6 +#define R8A7792_CLK_TMU1 11 +#define R8A7792_CLK_TMU3 21 +#define R8A7792_CLK_TMU2 22 +#define R8A7792_CLK_CMT0 24 +#define R8A7792_CLK_TMU0 25 +#define R8A7792_CLK_VSP1DU1 27 +#define R8A7792_CLK_VSP1DU0 28 +#define R8A7792_CLK_VSP1_SY 31 + +/* MSTP2 */ +#define R8A7792_CLK_MSIOF1 8 +#define R8A7792_CLK_SYS_DMAC1 18 +#define R8A7792_CLK_SYS_DMAC0 19 + +/* MSTP3 */ +#define R8A7792_CLK_TPU0 4 +#define R8A7792_CLK_SDHI0 14 +#define R8A7792_CLK_CMT1 29 + +/* MSTP4 */ +#define R8A7792_CLK_IRQC 7 +#define R8A7792_CLK_INTC_SYS 8 + +/* MSTP5 */ +#define R8A7792_CLK_AUDIO_DMAC0 2 +#define R8A7792_CLK_THERMAL 22 +#define R8A7792_CLK_PWM 23 + +/* MSTP7 */ +#define R8A7792_CLK_HSCIF1 16 +#define R8A7792_CLK_HSCIF0 17 +#define R8A7792_CLK_SCIF3 18 +#define R8A7792_CLK_SCIF2 19 +#define R8A7792_CLK_SCIF1 20 +#define R8A7792_CLK_SCIF0 21 +#define R8A7792_CLK_DU1 23 +#define R8A7792_CLK_DU0 24 + +/* MSTP8 */ +#define R8A7792_CLK_VIN5 4 +#define R8A7792_CLK_VIN4 5 +#define R8A7792_CLK_VIN3 8 +#define R8A7792_CLK_VIN2 9 +#define R8A7792_CLK_VIN1 10 +#define R8A7792_CLK_VIN0 11 +#define R8A7792_CLK_ETHERAVB 12 + +/* MSTP9 */ +#define R8A7792_CLK_GPIO7 4 +#define R8A7792_CLK_GPIO6 5 +#define R8A7792_CLK_GPIO5 7 +#define R8A7792_CLK_GPIO4 8 +#define R8A7792_CLK_GPIO3 9 +#define R8A7792_CLK_GPIO2 10 +#define R8A7792_CLK_GPIO1 11 +#define R8A7792_CLK_GPIO0 12 +#define R8A7792_CLK_GPIO11 13 +#define R8A7792_CLK_GPIO10 14 +#define R8A7792_CLK_CAN1 15 +#define R8A7792_CLK_CAN0 16 +#define R8A7792_CLK_QSPI_MOD 17 +#define R8A7792_CLK_GPIO9 19 +#define R8A7792_CLK_GPIO8 21 +#define R8A7792_CLK_I2C5 25 +#define R8A7792_CLK_IICDVFS 26 +#define R8A7792_CLK_I2C4 27 +#define R8A7792_CLK_I2C3 28 +#define R8A7792_CLK_I2C2 29 +#define R8A7792_CLK_I2C1 30 +#define R8A7792_CLK_I2C0 31 + +/* MSTP10 */ +#define R8A7792_CLK_SSI_ALL 5 +#define R8A7792_CLK_SSI4 11 +#define R8A7792_CLK_SSI3 12 + +#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a7792-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/r8a7792-cpg-mssr.h new file mode 100644 index 000000000..829c44db0 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a7792-cpg-mssr.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2015 Renesas Electronics Corp. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ + +#include + +/* r8a7792 CPG Core Clocks */ +#define R8A7792_CLK_Z 0 +#define R8A7792_CLK_ZG 1 +#define R8A7792_CLK_ZTR 2 +#define R8A7792_CLK_ZTRD2 3 +#define R8A7792_CLK_ZT 4 +#define R8A7792_CLK_ZX 5 +#define R8A7792_CLK_ZS 6 +#define R8A7792_CLK_HP 7 +#define R8A7792_CLK_I 8 +#define R8A7792_CLK_B 9 +#define R8A7792_CLK_LB 10 +#define R8A7792_CLK_P 11 +#define R8A7792_CLK_CL 12 +#define R8A7792_CLK_M2 13 +#define R8A7792_CLK_IMP 14 +#define R8A7792_CLK_ZB3 15 +#define R8A7792_CLK_ZB3D2 16 +#define R8A7792_CLK_DDR 17 +#define R8A7792_CLK_SD 18 +#define R8A7792_CLK_MP 19 +#define R8A7792_CLK_QSPI 20 +#define R8A7792_CLK_CP 21 +#define R8A7792_CLK_CPEX 22 +#define R8A7792_CLK_RCAN 23 +#define R8A7792_CLK_R 24 +#define R8A7792_CLK_OSC 25 + +#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a7793-clock.h b/roms/u-boot/include/dt-bindings/clock/r8a7793-clock.h new file mode 100644 index 000000000..49c66d8ed --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a7793-clock.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * r8a7793 clock definition + * + * Copyright (C) 2014 Renesas Electronics Corporation + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__ +#define __DT_BINDINGS_CLOCK_R8A7793_H__ + +/* CPG */ +#define R8A7793_CLK_MAIN 0 +#define R8A7793_CLK_PLL0 1 +#define R8A7793_CLK_PLL1 2 +#define R8A7793_CLK_PLL3 3 +#define R8A7793_CLK_LB 4 +#define R8A7793_CLK_QSPI 5 +#define R8A7793_CLK_SDH 6 +#define R8A7793_CLK_SD0 7 +#define R8A7793_CLK_Z 8 +#define R8A7793_CLK_RCAN 9 +#define R8A7793_CLK_ADSP 10 + +/* MSTP0 */ +#define R8A7793_CLK_MSIOF0 0 + +/* MSTP1 */ +#define R8A7793_CLK_VCP0 1 +#define R8A7793_CLK_VPC0 3 +#define R8A7793_CLK_SSP1 9 +#define R8A7793_CLK_TMU1 11 +#define R8A7793_CLK_3DG 12 +#define R8A7793_CLK_2DDMAC 15 +#define R8A7793_CLK_FDP1_1 18 +#define R8A7793_CLK_FDP1_0 19 +#define R8A7793_CLK_TMU3 21 +#define R8A7793_CLK_TMU2 22 +#define R8A7793_CLK_CMT0 24 +#define R8A7793_CLK_TMU0 25 +#define R8A7793_CLK_VSP1_DU1 27 +#define R8A7793_CLK_VSP1_DU0 28 +#define R8A7793_CLK_VSP1_S 31 + +/* MSTP2 */ +#define R8A7793_CLK_SCIFA2 2 +#define R8A7793_CLK_SCIFA1 3 +#define R8A7793_CLK_SCIFA0 4 +#define R8A7793_CLK_MSIOF2 5 +#define R8A7793_CLK_SCIFB0 6 +#define R8A7793_CLK_SCIFB1 7 +#define R8A7793_CLK_MSIOF1 8 +#define R8A7793_CLK_SCIFB2 16 +#define R8A7793_CLK_SYS_DMAC1 18 +#define R8A7793_CLK_SYS_DMAC0 19 + +/* MSTP3 */ +#define R8A7793_CLK_TPU0 4 +#define R8A7793_CLK_SDHI2 11 +#define R8A7793_CLK_SDHI1 12 +#define R8A7793_CLK_SDHI0 14 +#define R8A7793_CLK_MMCIF0 15 +#define R8A7793_CLK_IIC0 18 +#define R8A7793_CLK_PCIEC 19 +#define R8A7793_CLK_IIC1 23 +#define R8A7793_CLK_SSUSB 28 +#define R8A7793_CLK_CMT1 29 +#define R8A7793_CLK_USBDMAC0 30 +#define R8A7793_CLK_USBDMAC1 31 + +/* MSTP4 */ +#define R8A7793_CLK_IRQC 7 +#define R8A7793_CLK_INTC_SYS 8 + +/* MSTP5 */ +#define R8A7793_CLK_AUDIO_DMAC1 1 +#define R8A7793_CLK_AUDIO_DMAC0 2 +#define R8A7793_CLK_ADSP_MOD 6 +#define R8A7793_CLK_THERMAL 22 +#define R8A7793_CLK_PWM 23 + +/* MSTP7 */ +#define R8A7793_CLK_EHCI 3 +#define R8A7793_CLK_HSUSB 4 +#define R8A7793_CLK_HSCIF2 13 +#define R8A7793_CLK_SCIF5 14 +#define R8A7793_CLK_SCIF4 15 +#define R8A7793_CLK_HSCIF1 16 +#define R8A7793_CLK_HSCIF0 17 +#define R8A7793_CLK_SCIF3 18 +#define R8A7793_CLK_SCIF2 19 +#define R8A7793_CLK_SCIF1 20 +#define R8A7793_CLK_SCIF0 21 +#define R8A7793_CLK_DU1 23 +#define R8A7793_CLK_DU0 24 +#define R8A7793_CLK_LVDS0 26 + +/* MSTP8 */ +#define R8A7793_CLK_IPMMU_SGX 0 +#define R8A7793_CLK_VIN2 9 +#define R8A7793_CLK_VIN1 10 +#define R8A7793_CLK_VIN0 11 +#define R8A7793_CLK_ETHER 13 +#define R8A7793_CLK_SATA1 14 +#define R8A7793_CLK_SATA0 15 + +/* MSTP9 */ +#define R8A7793_CLK_GPIO7 4 +#define R8A7793_CLK_GPIO6 5 +#define R8A7793_CLK_GPIO5 7 +#define R8A7793_CLK_GPIO4 8 +#define R8A7793_CLK_GPIO3 9 +#define R8A7793_CLK_GPIO2 10 +#define R8A7793_CLK_GPIO1 11 +#define R8A7793_CLK_GPIO0 12 +#define R8A7793_CLK_RCAN1 15 +#define R8A7793_CLK_RCAN0 16 +#define R8A7793_CLK_QSPI_MOD 17 +#define R8A7793_CLK_I2C5 25 +#define R8A7793_CLK_IICDVFS 26 +#define R8A7793_CLK_I2C4 27 +#define R8A7793_CLK_I2C3 28 +#define R8A7793_CLK_I2C2 29 +#define R8A7793_CLK_I2C1 30 +#define R8A7793_CLK_I2C0 31 + +/* MSTP10 */ +#define R8A7793_CLK_SSI_ALL 5 +#define R8A7793_CLK_SSI9 6 +#define R8A7793_CLK_SSI8 7 +#define R8A7793_CLK_SSI7 8 +#define R8A7793_CLK_SSI6 9 +#define R8A7793_CLK_SSI5 10 +#define R8A7793_CLK_SSI4 11 +#define R8A7793_CLK_SSI3 12 +#define R8A7793_CLK_SSI2 13 +#define R8A7793_CLK_SSI1 14 +#define R8A7793_CLK_SSI0 15 +#define R8A7793_CLK_SCU_ALL 17 +#define R8A7793_CLK_SCU_DVC1 18 +#define R8A7793_CLK_SCU_DVC0 19 +#define R8A7793_CLK_SCU_CTU1_MIX1 20 +#define R8A7793_CLK_SCU_CTU0_MIX0 21 +#define R8A7793_CLK_SCU_SRC9 22 +#define R8A7793_CLK_SCU_SRC8 23 +#define R8A7793_CLK_SCU_SRC7 24 +#define R8A7793_CLK_SCU_SRC6 25 +#define R8A7793_CLK_SCU_SRC5 26 +#define R8A7793_CLK_SCU_SRC4 27 +#define R8A7793_CLK_SCU_SRC3 28 +#define R8A7793_CLK_SCU_SRC2 29 +#define R8A7793_CLK_SCU_SRC1 30 +#define R8A7793_CLK_SCU_SRC0 31 + +/* MSTP11 */ +#define R8A7793_CLK_SCIFA3 6 +#define R8A7793_CLK_SCIFA4 7 +#define R8A7793_CLK_SCIFA5 8 + +#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a7793-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/r8a7793-cpg-mssr.h new file mode 100644 index 000000000..d1ff646c3 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a7793-cpg-mssr.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2015 Renesas Electronics Corp. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ + +#include + +/* r8a7793 CPG Core Clocks */ +#define R8A7793_CLK_Z 0 +#define R8A7793_CLK_ZG 1 +#define R8A7793_CLK_ZTR 2 +#define R8A7793_CLK_ZTRD2 3 +#define R8A7793_CLK_ZT 4 +#define R8A7793_CLK_ZX 5 +#define R8A7793_CLK_ZS 6 +#define R8A7793_CLK_HP 7 +#define R8A7793_CLK_I 8 +#define R8A7793_CLK_B 9 +#define R8A7793_CLK_LB 10 +#define R8A7793_CLK_P 11 +#define R8A7793_CLK_CL 12 +#define R8A7793_CLK_M2 13 +#define R8A7793_CLK_ADSP 14 +#define R8A7793_CLK_ZB3 15 +#define R8A7793_CLK_ZB3D2 16 +#define R8A7793_CLK_DDR 17 +#define R8A7793_CLK_SDH 18 +#define R8A7793_CLK_SD0 19 +#define R8A7793_CLK_SD2 20 +#define R8A7793_CLK_SD3 21 +#define R8A7793_CLK_MMC0 22 +#define R8A7793_CLK_MP 23 +#define R8A7793_CLK_SSP 24 +#define R8A7793_CLK_SSPRS 25 +#define R8A7793_CLK_QSPI 26 +#define R8A7793_CLK_CP 27 +#define R8A7793_CLK_RCAN 28 +#define R8A7793_CLK_R 29 +#define R8A7793_CLK_OSC 30 + +#endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a7794-clock.h b/roms/u-boot/include/dt-bindings/clock/r8a7794-clock.h new file mode 100644 index 000000000..649f00578 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a7794-clock.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2014 Renesas Electronics Corporation + * Copyright 2013 Ideas On Board SPRL + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__ +#define __DT_BINDINGS_CLOCK_R8A7794_H__ + +/* CPG */ +#define R8A7794_CLK_MAIN 0 +#define R8A7794_CLK_PLL0 1 +#define R8A7794_CLK_PLL1 2 +#define R8A7794_CLK_PLL3 3 +#define R8A7794_CLK_LB 4 +#define R8A7794_CLK_QSPI 5 +#define R8A7794_CLK_SDH 6 +#define R8A7794_CLK_SD0 7 +#define R8A7794_CLK_RCAN 8 + +/* MSTP0 */ +#define R8A7794_CLK_MSIOF0 0 + +/* MSTP1 */ +#define R8A7794_CLK_VCP0 1 +#define R8A7794_CLK_VPC0 3 +#define R8A7794_CLK_TMU1 11 +#define R8A7794_CLK_3DG 12 +#define R8A7794_CLK_2DDMAC 15 +#define R8A7794_CLK_FDP1_0 19 +#define R8A7794_CLK_TMU3 21 +#define R8A7794_CLK_TMU2 22 +#define R8A7794_CLK_CMT0 24 +#define R8A7794_CLK_TMU0 25 +#define R8A7794_CLK_VSP1_DU0 28 +#define R8A7794_CLK_VSP1_S 31 + +/* MSTP2 */ +#define R8A7794_CLK_SCIFA2 2 +#define R8A7794_CLK_SCIFA1 3 +#define R8A7794_CLK_SCIFA0 4 +#define R8A7794_CLK_MSIOF2 5 +#define R8A7794_CLK_SCIFB0 6 +#define R8A7794_CLK_SCIFB1 7 +#define R8A7794_CLK_MSIOF1 8 +#define R8A7794_CLK_SCIFB2 16 +#define R8A7794_CLK_SYS_DMAC1 18 +#define R8A7794_CLK_SYS_DMAC0 19 + +/* MSTP3 */ +#define R8A7794_CLK_SDHI2 11 +#define R8A7794_CLK_SDHI1 12 +#define R8A7794_CLK_SDHI0 14 +#define R8A7794_CLK_MMCIF0 15 +#define R8A7794_CLK_IIC0 18 +#define R8A7794_CLK_IIC1 23 +#define R8A7794_CLK_CMT1 29 +#define R8A7794_CLK_USBDMAC0 30 +#define R8A7794_CLK_USBDMAC1 31 + +/* MSTP4 */ +#define R8A7794_CLK_IRQC 7 +#define R8A7794_CLK_INTC_SYS 8 + +/* MSTP5 */ +#define R8A7794_CLK_AUDIO_DMAC0 2 +#define R8A7794_CLK_PWM 23 + +/* MSTP7 */ +#define R8A7794_CLK_EHCI 3 +#define R8A7794_CLK_HSUSB 4 +#define R8A7794_CLK_HSCIF2 13 +#define R8A7794_CLK_SCIF5 14 +#define R8A7794_CLK_SCIF4 15 +#define R8A7794_CLK_HSCIF1 16 +#define R8A7794_CLK_HSCIF0 17 +#define R8A7794_CLK_SCIF3 18 +#define R8A7794_CLK_SCIF2 19 +#define R8A7794_CLK_SCIF1 20 +#define R8A7794_CLK_SCIF0 21 +#define R8A7794_CLK_DU1 23 +#define R8A7794_CLK_DU0 24 + +/* MSTP8 */ +#define R8A7794_CLK_VIN1 10 +#define R8A7794_CLK_VIN0 11 +#define R8A7794_CLK_ETHERAVB 12 +#define R8A7794_CLK_ETHER 13 + +/* MSTP9 */ +#define R8A7794_CLK_GPIO6 5 +#define R8A7794_CLK_GPIO5 7 +#define R8A7794_CLK_GPIO4 8 +#define R8A7794_CLK_GPIO3 9 +#define R8A7794_CLK_GPIO2 10 +#define R8A7794_CLK_GPIO1 11 +#define R8A7794_CLK_GPIO0 12 +#define R8A7794_CLK_RCAN1 15 +#define R8A7794_CLK_RCAN0 16 +#define R8A7794_CLK_QSPI_MOD 17 +#define R8A7794_CLK_I2C5 25 +#define R8A7794_CLK_I2C4 27 +#define R8A7794_CLK_I2C3 28 +#define R8A7794_CLK_I2C2 29 +#define R8A7794_CLK_I2C1 30 +#define R8A7794_CLK_I2C0 31 + +/* MSTP10 */ +#define R8A7794_CLK_SSI_ALL 5 +#define R8A7794_CLK_SSI9 6 +#define R8A7794_CLK_SSI8 7 +#define R8A7794_CLK_SSI7 8 +#define R8A7794_CLK_SSI6 9 +#define R8A7794_CLK_SSI5 10 +#define R8A7794_CLK_SSI4 11 +#define R8A7794_CLK_SSI3 12 +#define R8A7794_CLK_SSI2 13 +#define R8A7794_CLK_SSI1 14 +#define R8A7794_CLK_SSI0 15 +#define R8A7794_CLK_SCU_ALL 17 +#define R8A7794_CLK_SCU_DVC1 18 +#define R8A7794_CLK_SCU_DVC0 19 +#define R8A7794_CLK_SCU_CTU1_MIX1 20 +#define R8A7794_CLK_SCU_CTU0_MIX0 21 +#define R8A7794_CLK_SCU_SRC6 25 +#define R8A7794_CLK_SCU_SRC5 26 +#define R8A7794_CLK_SCU_SRC4 27 +#define R8A7794_CLK_SCU_SRC3 28 +#define R8A7794_CLK_SCU_SRC2 29 +#define R8A7794_CLK_SCU_SRC1 30 + +/* MSTP11 */ +#define R8A7794_CLK_SCIFA3 6 +#define R8A7794_CLK_SCIFA4 7 +#define R8A7794_CLK_SCIFA5 8 + +#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/r8a7794-cpg-mssr.h new file mode 100644 index 000000000..6314e23b5 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a7794-cpg-mssr.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2015 Renesas Electronics Corp. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ + +#include + +/* r8a7794 CPG Core Clocks */ +#define R8A7794_CLK_Z2 0 +#define R8A7794_CLK_ZG 1 +#define R8A7794_CLK_ZTR 2 +#define R8A7794_CLK_ZTRD2 3 +#define R8A7794_CLK_ZT 4 +#define R8A7794_CLK_ZX 5 +#define R8A7794_CLK_ZS 6 +#define R8A7794_CLK_HP 7 +#define R8A7794_CLK_I 8 +#define R8A7794_CLK_B 9 +#define R8A7794_CLK_LB 10 +#define R8A7794_CLK_P 11 +#define R8A7794_CLK_CL 12 +#define R8A7794_CLK_CP 13 +#define R8A7794_CLK_M2 14 +#define R8A7794_CLK_ADSP 15 +#define R8A7794_CLK_ZB3 16 +#define R8A7794_CLK_ZB3D2 17 +#define R8A7794_CLK_DDR 18 +#define R8A7794_CLK_SDH 19 +#define R8A7794_CLK_SD0 20 +#define R8A7794_CLK_SD2 21 +#define R8A7794_CLK_SD3 22 +#define R8A7794_CLK_MMC0 23 +#define R8A7794_CLK_MP 24 +#define R8A7794_CLK_QSPI 25 +#define R8A7794_CLK_CPEX 26 +#define R8A7794_CLK_RCAN 27 +#define R8A7794_CLK_R 28 +#define R8A7794_CLK_OSC 29 + +#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/r8a7795-cpg-mssr.h new file mode 100644 index 000000000..92b3e2a95 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a7795-cpg-mssr.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2015 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ + +#include + +/* r8a7795 CPG Core Clocks */ +#define R8A7795_CLK_Z 0 +#define R8A7795_CLK_Z2 1 +#define R8A7795_CLK_ZR 2 +#define R8A7795_CLK_ZG 3 +#define R8A7795_CLK_ZTR 4 +#define R8A7795_CLK_ZTRD2 5 +#define R8A7795_CLK_ZT 6 +#define R8A7795_CLK_ZX 7 +#define R8A7795_CLK_S0D1 8 +#define R8A7795_CLK_S0D4 9 +#define R8A7795_CLK_S1D1 10 +#define R8A7795_CLK_S1D2 11 +#define R8A7795_CLK_S1D4 12 +#define R8A7795_CLK_S2D1 13 +#define R8A7795_CLK_S2D2 14 +#define R8A7795_CLK_S2D4 15 +#define R8A7795_CLK_S3D1 16 +#define R8A7795_CLK_S3D2 17 +#define R8A7795_CLK_S3D4 18 +#define R8A7795_CLK_LB 19 +#define R8A7795_CLK_CL 20 +#define R8A7795_CLK_ZB3 21 +#define R8A7795_CLK_ZB3D2 22 +#define R8A7795_CLK_CR 23 +#define R8A7795_CLK_CRD2 24 +#define R8A7795_CLK_SD0H 25 +#define R8A7795_CLK_SD0 26 +#define R8A7795_CLK_SD1H 27 +#define R8A7795_CLK_SD1 28 +#define R8A7795_CLK_SD2H 29 +#define R8A7795_CLK_SD2 30 +#define R8A7795_CLK_SD3H 31 +#define R8A7795_CLK_SD3 32 +#define R8A7795_CLK_SSP2 33 +#define R8A7795_CLK_SSP1 34 +#define R8A7795_CLK_SSPRS 35 +#define R8A7795_CLK_RPC 36 +#define R8A7795_CLK_RPCD2 37 +#define R8A7795_CLK_MSO 38 +#define R8A7795_CLK_CANFD 39 +#define R8A7795_CLK_HDMI 40 +#define R8A7795_CLK_CSI0 41 +/* CLK_CSIREF was removed */ +#define R8A7795_CLK_CP 43 +#define R8A7795_CLK_CPEX 44 +#define R8A7795_CLK_R 45 +#define R8A7795_CLK_OSC 46 + +/* r8a7795 ES2.0 CPG Core Clocks */ +#define R8A7795_CLK_S0D2 47 +#define R8A7795_CLK_S0D3 48 +#define R8A7795_CLK_S0D6 49 +#define R8A7795_CLK_S0D8 50 +#define R8A7795_CLK_S0D12 51 + +#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a7796-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/r8a7796-cpg-mssr.h new file mode 100644 index 000000000..c0957cf45 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a7796-cpg-mssr.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2016 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ + +#include + +/* r8a7796 CPG Core Clocks */ +#define R8A7796_CLK_Z 0 +#define R8A7796_CLK_Z2 1 +#define R8A7796_CLK_ZR 2 +#define R8A7796_CLK_ZG 3 +#define R8A7796_CLK_ZTR 4 +#define R8A7796_CLK_ZTRD2 5 +#define R8A7796_CLK_ZT 6 +#define R8A7796_CLK_ZX 7 +#define R8A7796_CLK_S0D1 8 +#define R8A7796_CLK_S0D2 9 +#define R8A7796_CLK_S0D3 10 +#define R8A7796_CLK_S0D4 11 +#define R8A7796_CLK_S0D6 12 +#define R8A7796_CLK_S0D8 13 +#define R8A7796_CLK_S0D12 14 +#define R8A7796_CLK_S1D1 15 +#define R8A7796_CLK_S1D2 16 +#define R8A7796_CLK_S1D4 17 +#define R8A7796_CLK_S2D1 18 +#define R8A7796_CLK_S2D2 19 +#define R8A7796_CLK_S2D4 20 +#define R8A7796_CLK_S3D1 21 +#define R8A7796_CLK_S3D2 22 +#define R8A7796_CLK_S3D4 23 +#define R8A7796_CLK_LB 24 +#define R8A7796_CLK_CL 25 +#define R8A7796_CLK_ZB3 26 +#define R8A7796_CLK_ZB3D2 27 +#define R8A7796_CLK_ZB3D4 28 +#define R8A7796_CLK_CR 29 +#define R8A7796_CLK_CRD2 30 +#define R8A7796_CLK_SD0H 31 +#define R8A7796_CLK_SD0 32 +#define R8A7796_CLK_SD1H 33 +#define R8A7796_CLK_SD1 34 +#define R8A7796_CLK_SD2H 35 +#define R8A7796_CLK_SD2 36 +#define R8A7796_CLK_SD3H 37 +#define R8A7796_CLK_SD3 38 +#define R8A7796_CLK_SSP2 39 +#define R8A7796_CLK_SSP1 40 +#define R8A7796_CLK_SSPRS 41 +#define R8A7796_CLK_RPC 42 +#define R8A7796_CLK_RPCD2 43 +#define R8A7796_CLK_MSO 44 +#define R8A7796_CLK_CANFD 45 +#define R8A7796_CLK_HDMI 46 +#define R8A7796_CLK_CSI0 47 +/* CLK_CSIREF was removed */ +#define R8A7796_CLK_CP 49 +#define R8A7796_CLK_CPEX 50 +#define R8A7796_CLK_R 51 +#define R8A7796_CLK_OSC 52 + +#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a77965-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/r8a77965-cpg-mssr.h new file mode 100644 index 000000000..6d3b5a9a6 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a77965-cpg-mssr.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Jacopo Mondi + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ + +#include + +/* r8a77965 CPG Core Clocks */ +#define R8A77965_CLK_Z 0 +#define R8A77965_CLK_ZR 1 +#define R8A77965_CLK_ZG 2 +#define R8A77965_CLK_ZTR 3 +#define R8A77965_CLK_ZTRD2 4 +#define R8A77965_CLK_ZT 5 +#define R8A77965_CLK_ZX 6 +#define R8A77965_CLK_S0D1 7 +#define R8A77965_CLK_S0D2 8 +#define R8A77965_CLK_S0D3 9 +#define R8A77965_CLK_S0D4 10 +#define R8A77965_CLK_S0D6 11 +#define R8A77965_CLK_S0D8 12 +#define R8A77965_CLK_S0D12 13 +#define R8A77965_CLK_S1D1 14 +#define R8A77965_CLK_S1D2 15 +#define R8A77965_CLK_S1D4 16 +#define R8A77965_CLK_S2D1 17 +#define R8A77965_CLK_S2D2 18 +#define R8A77965_CLK_S2D4 19 +#define R8A77965_CLK_S3D1 20 +#define R8A77965_CLK_S3D2 21 +#define R8A77965_CLK_S3D4 22 +#define R8A77965_CLK_LB 23 +#define R8A77965_CLK_CL 24 +#define R8A77965_CLK_ZB3 25 +#define R8A77965_CLK_ZB3D2 26 +#define R8A77965_CLK_CR 27 +#define R8A77965_CLK_CRD2 28 +#define R8A77965_CLK_SD0H 29 +#define R8A77965_CLK_SD0 30 +#define R8A77965_CLK_SD1H 31 +#define R8A77965_CLK_SD1 32 +#define R8A77965_CLK_SD2H 33 +#define R8A77965_CLK_SD2 34 +#define R8A77965_CLK_SD3H 35 +#define R8A77965_CLK_SD3 36 +#define R8A77965_CLK_SSP2 37 +#define R8A77965_CLK_SSP1 38 +#define R8A77965_CLK_SSPRS 39 +#define R8A77965_CLK_RPC 40 +#define R8A77965_CLK_RPCD2 41 +#define R8A77965_CLK_MSO 42 +#define R8A77965_CLK_CANFD 43 +#define R8A77965_CLK_HDMI 44 +#define R8A77965_CLK_CSI0 45 +#define R8A77965_CLK_CP 46 +#define R8A77965_CLK_CPEX 47 +#define R8A77965_CLK_R 48 +#define R8A77965_CLK_OSC 49 + +#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/r8a77970-cpg-mssr.h new file mode 100644 index 000000000..414639559 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a77970-cpg-mssr.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2017 Cogent Embedded, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ + +#include + +/* r8a77970 CPG Core Clocks */ +#define R8A77970_CLK_Z2 0 +#define R8A77970_CLK_ZR 1 +#define R8A77970_CLK_ZTR 2 +#define R8A77970_CLK_ZTRD2 3 +#define R8A77970_CLK_ZT 4 +#define R8A77970_CLK_ZX 5 +#define R8A77970_CLK_S1D1 6 +#define R8A77970_CLK_S1D2 7 +#define R8A77970_CLK_S1D4 8 +#define R8A77970_CLK_S2D1 9 +#define R8A77970_CLK_S2D2 10 +#define R8A77970_CLK_S2D4 11 +#define R8A77970_CLK_LB 12 +#define R8A77970_CLK_CL 13 +#define R8A77970_CLK_ZB3 14 +#define R8A77970_CLK_ZB3D2 15 +#define R8A77970_CLK_DDR 16 +#define R8A77970_CLK_CR 17 +#define R8A77970_CLK_CRD2 18 +#define R8A77970_CLK_SD0H 19 +#define R8A77970_CLK_SD0 20 +#define R8A77970_CLK_RPC 21 +#define R8A77970_CLK_RPCD2 22 +#define R8A77970_CLK_MSO 23 +#define R8A77970_CLK_CANFD 24 +#define R8A77970_CLK_CSI0 25 +#define R8A77970_CLK_FRAY 26 +#define R8A77970_CLK_CP 27 +#define R8A77970_CLK_CPEX 28 +#define R8A77970_CLK_R 29 +#define R8A77970_CLK_OSC 30 + +#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a77980-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/r8a77980-cpg-mssr.h new file mode 100644 index 000000000..a4c0d76c3 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a77980-cpg-mssr.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ + +#include + +/* r8a77980 CPG Core Clocks */ +#define R8A77980_CLK_Z2 0 +#define R8A77980_CLK_ZR 1 +#define R8A77980_CLK_ZTR 2 +#define R8A77980_CLK_ZTRD2 3 +#define R8A77980_CLK_ZT 4 +#define R8A77980_CLK_ZX 5 +#define R8A77980_CLK_S0D1 6 +#define R8A77980_CLK_S0D2 7 +#define R8A77980_CLK_S0D3 8 +#define R8A77980_CLK_S0D4 9 +#define R8A77980_CLK_S0D6 10 +#define R8A77980_CLK_S0D12 11 +#define R8A77980_CLK_S0D24 12 +#define R8A77980_CLK_S1D1 13 +#define R8A77980_CLK_S1D2 14 +#define R8A77980_CLK_S1D4 15 +#define R8A77980_CLK_S2D1 16 +#define R8A77980_CLK_S2D2 17 +#define R8A77980_CLK_S2D4 18 +#define R8A77980_CLK_S3D1 19 +#define R8A77980_CLK_S3D2 20 +#define R8A77980_CLK_S3D4 21 +#define R8A77980_CLK_LB 22 +#define R8A77980_CLK_CL 23 +#define R8A77980_CLK_ZB3 24 +#define R8A77980_CLK_ZB3D2 25 +#define R8A77980_CLK_ZB3D4 26 +#define R8A77980_CLK_SD0H 27 +#define R8A77980_CLK_SD0 28 +#define R8A77980_CLK_RPC 29 +#define R8A77980_CLK_RPCD2 30 +#define R8A77980_CLK_MSO 31 +#define R8A77980_CLK_CANFD 32 +#define R8A77980_CLK_CSI0 33 +#define R8A77980_CLK_CP 34 +#define R8A77980_CLK_CPEX 35 +#define R8A77980_CLK_R 36 +#define R8A77980_CLK_OSC 37 + +#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/r8a77990-cpg-mssr.h new file mode 100644 index 000000000..a596a482f --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a77990-cpg-mssr.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ + +#include + +/* r8a77990 CPG Core Clocks */ +#define R8A77990_CLK_Z2 0 +#define R8A77990_CLK_ZR 1 +#define R8A77990_CLK_ZG 2 +#define R8A77990_CLK_ZTR 3 +#define R8A77990_CLK_ZT 4 +#define R8A77990_CLK_ZX 5 +#define R8A77990_CLK_S0D1 6 +#define R8A77990_CLK_S0D3 7 +#define R8A77990_CLK_S0D6 8 +#define R8A77990_CLK_S0D12 9 +#define R8A77990_CLK_S0D24 10 +#define R8A77990_CLK_S1D1 11 +#define R8A77990_CLK_S1D2 12 +#define R8A77990_CLK_S1D4 13 +#define R8A77990_CLK_S2D1 14 +#define R8A77990_CLK_S2D2 15 +#define R8A77990_CLK_S2D4 16 +#define R8A77990_CLK_S3D1 17 +#define R8A77990_CLK_S3D2 18 +#define R8A77990_CLK_S3D4 19 +#define R8A77990_CLK_S0D6C 20 +#define R8A77990_CLK_S3D1C 21 +#define R8A77990_CLK_S3D2C 22 +#define R8A77990_CLK_S3D4C 23 +#define R8A77990_CLK_LB 24 +#define R8A77990_CLK_CL 25 +#define R8A77990_CLK_ZB3 26 +#define R8A77990_CLK_ZB3D2 27 +#define R8A77990_CLK_CR 28 +#define R8A77990_CLK_CRD2 29 +#define R8A77990_CLK_SD0H 30 +#define R8A77990_CLK_SD0 31 +#define R8A77990_CLK_SD1H 32 +#define R8A77990_CLK_SD1 33 +#define R8A77990_CLK_SD3H 34 +#define R8A77990_CLK_SD3 35 +#define R8A77990_CLK_RPC 36 +#define R8A77990_CLK_RPCD2 37 +#define R8A77990_CLK_ZA2 38 +#define R8A77990_CLK_ZA8 39 +#define R8A77990_CLK_Z2D 40 +#define R8A77990_CLK_CANFD 41 +#define R8A77990_CLK_MSO 42 +#define R8A77990_CLK_R 43 +#define R8A77990_CLK_OSC 44 +#define R8A77990_CLK_LV0 45 +#define R8A77990_CLK_LV1 46 +#define R8A77990_CLK_CSI0 47 +#define R8A77990_CLK_CP 48 +#define R8A77990_CLK_CPEX 49 + +#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/r8a77995-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/r8a77995-cpg-mssr.h new file mode 100644 index 000000000..fd701c4e8 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/r8a77995-cpg-mssr.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2017 Glider bvba + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ + +#include + +/* r8a77995 CPG Core Clocks */ +#define R8A77995_CLK_Z2 0 +#define R8A77995_CLK_ZG 1 +#define R8A77995_CLK_ZTR 2 +#define R8A77995_CLK_ZT 3 +#define R8A77995_CLK_ZX 4 +#define R8A77995_CLK_S0D1 5 +#define R8A77995_CLK_S1D1 6 +#define R8A77995_CLK_S1D2 7 +#define R8A77995_CLK_S1D4 8 +#define R8A77995_CLK_S2D1 9 +#define R8A77995_CLK_S2D2 10 +#define R8A77995_CLK_S2D4 11 +#define R8A77995_CLK_S3D1 12 +#define R8A77995_CLK_S3D2 13 +#define R8A77995_CLK_S3D4 14 +#define R8A77995_CLK_S1D4C 15 +#define R8A77995_CLK_S3D1C 16 +#define R8A77995_CLK_S3D2C 17 +#define R8A77995_CLK_S3D4C 18 +#define R8A77995_CLK_LB 19 +#define R8A77995_CLK_CL 20 +#define R8A77995_CLK_ZB3 21 +#define R8A77995_CLK_ZB3D2 22 +#define R8A77995_CLK_CR 23 +#define R8A77995_CLK_CRD2 24 +#define R8A77995_CLK_SD0H 25 +#define R8A77995_CLK_SD0 26 +/* CLK_SSP2 was removed */ +/* CLK_SSP1 was removed */ +#define R8A77995_CLK_RPC 29 +#define R8A77995_CLK_RPCD2 30 +#define R8A77995_CLK_ZA2 31 +#define R8A77995_CLK_ZA8 32 +#define R8A77995_CLK_Z2D 33 +#define R8A77995_CLK_CANFD 34 +#define R8A77995_CLK_MSO 35 +#define R8A77995_CLK_R 36 +#define R8A77995_CLK_OSC 37 +#define R8A77995_CLK_LV0 38 +#define R8A77995_CLK_LV1 39 +#define R8A77995_CLK_CP 40 +#define R8A77995_CLK_CPEX 41 + +#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/renesas-cpg-mssr.h b/roms/u-boot/include/dt-bindings/clock/renesas-cpg-mssr.h new file mode 100644 index 000000000..569a3cc33 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/renesas-cpg-mssr.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2015 Renesas Electronics Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ + +#define CPG_CORE 0 /* Core Clock */ +#define CPG_MOD 1 /* Module Clock */ + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */ diff --git a/roms/u-boot/include/dt-bindings/clock/rk3036-cru.h b/roms/u-boot/include/dt-bindings/clock/rk3036-cru.h new file mode 100644 index 000000000..2c0552d1a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/rk3036-cru.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_GPLL 3 +#define ARMCLK 4 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI 65 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_NANDC 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_OTGPHY0 93 +#define SCLK_LCDC 100 +#define SCLK_HDMI 109 +#define SCLK_HEVC 111 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_VIDEO 125 +#define SCLK_MAC 151 +#define SCLK_MACREF 152 +#define SCLK_SFC 160 + +#define DCLK_LCDC 190 + +/* aclk gates */ +#define ACLK_DMAC2 194 +#define ACLK_LCDC 197 +#define ACLK_VIO 203 +#define ACLK_VCODEC 208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_SPI 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_HDMI 360 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_WDT 368 + +/* hclk gates */ +#define HCLK_OTG0 449 +#define HCLK_OTG1 450 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_I2S 462 +#define HCLK_LCDC 465 +#define HCLK_ROM 467 +#define HCLK_VIO_BUS 472 +#define HCLK_VCODEC 476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE0_DBG 4 +#define SRST_CORE1_DBG 5 +#define SRST_CORE0_POR 8 +#define SRST_CORE1_POR 9 +#define SRST_L2C 12 +#define SRST_TOPDBG 13 +#define SRST_STRC_SYS_A 14 +#define SRST_PD_CORE_NIU 15 + +#define SRST_TIMER2 16 +#define SRST_CPUSYS_H 17 +#define SRST_AHB2APB_H 19 +#define SRST_TIMER3 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_PERI_NIU 23 +#define SRST_I2S 24 +#define SRST_DDR_PLL 25 +#define SRST_GPU_DLL 26 +#define SRST_TIMER0 27 +#define SRST_TIMER1 28 +#define SRST_CORE_DLL 29 +#define SRST_EFUSE_P 30 +#define SRST_ACODEC_P 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_SFC 47 + +#define SRST_PWM0 48 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_GRF 55 +#define SRST_PERIPHSYS_A 57 +#define SRST_PERIPHSYS_H 58 +#define SRST_PERIPHSYS_P 59 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA2 64 +#define SRST_MAC 66 +#define SRST_NANDC 68 +#define SRST_USBOTG0 69 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_OTGC1 74 +#define SRST_DDRMSCH 79 + +#define SRST_MMC0 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI0 84 +#define SRST_WDT 86 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 + +#define SRST_HDMI_P 96 +#define SRST_VIO_BUS_H 99 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_USBPOR 105 + +#define SRST_VCODEC_A 112 +#define SRST_VCODEC_H 113 +#define SRST_VIO1_A 114 +#define SRST_HEVC 115 +#define SRST_VCODEC_NIU_A 116 +#define SRST_LCDC1_A 117 +#define SRST_LCDC1_H 118 +#define SRST_LCDC1_D 119 +#define SRST_GPU 120 +#define SRST_GPU_NIU_A 122 + +#define SRST_DBG_P 131 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/rk3066a-cru.h b/roms/u-boot/include/dt-bindings/clock/rk3066a-cru.h new file mode 100644 index 000000000..014eec586 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/rk3066a-cru.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H + +#include + +/* soft-reset indices */ +#define SRST_SRST1 0 +#define SRST_SRST2 1 + +#define SRST_L2MEM 18 +#define SRST_I2S0 23 +#define SRST_I2S1 24 +#define SRST_I2S2 25 +#define SRST_TIMER2 29 + +#define SRST_GPIO4 36 +#define SRST_GPIO6 38 + +#define SRST_TSADC 92 + +#define SRST_HDMI 96 +#define SRST_HDMI_APB 97 +#define SRST_CIF1 111 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/rk3128-cru.h b/roms/u-boot/include/dt-bindings/clock/rk3128-cru.h new file mode 100644 index 000000000..cfb3afbb2 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/rk3128-cru.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_GPLL 3 +#define ARMCLK 4 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI 65 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_NANDC 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_SARADC 91 +#define SCLK_OTGPHY0 93 +#define SCLK_LCDC 100 +#define SCLK_HDMI 109 +#define SCLK_HEVC 111 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_VIDEO 125 +#define SCLK_MAC 151 +#define SCLK_MACREF 152 +#define SCLK_SFC 160 + +#define DCLK_LCDC 190 + +/* aclk gates */ +#define ACLK_DMAC2 194 +#define ACLK_VIO0 197 +#define ACLK_VIO1 203 +#define ACLK_VCODEC 208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_SARADC 318 +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_SPI 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_HDMI 360 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_WDT 368 + +/* hclk gates */ +#define HCLK_OTG0 449 +#define HCLK_OTG1 450 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_I2S 462 +#define HCLK_LCDC 465 +#define HCLK_ROM 467 +#define HCLK_VIO_BUS 472 +#define HCLK_VCODEC 476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE0_DBG 4 +#define SRST_CORE1_DBG 5 +#define SRST_CORE0_POR 8 +#define SRST_CORE1_POR 9 +#define SRST_L2C 12 +#define SRST_TOPDBG 13 +#define SRST_STRC_SYS_A 14 +#define SRST_PD_CORE_NIU 15 + +#define SRST_TIMER2 16 +#define SRST_CPUSYS_H 17 +#define SRST_AHB2APB_H 19 +#define SRST_TIMER3 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_PERI_NIU 23 +#define SRST_I2S 24 +#define SRST_DDR_PLL 25 +#define SRST_GPU_DLL 26 +#define SRST_TIMER0 27 +#define SRST_TIMER1 28 +#define SRST_CORE_DLL 29 +#define SRST_EFUSE_P 30 +#define SRST_ACODEC_P 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_SFC 47 + +#define SRST_PWM0 48 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_GRF 55 +#define SRST_PERIPHSYS_A 57 +#define SRST_PERIPHSYS_H 58 +#define SRST_PERIPHSYS_P 59 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA2 64 +#define SRST_MAC 66 +#define SRST_NANDC 68 +#define SRST_USBOTG0 69 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_OTGC1 74 +#define SRST_DDRMSCH 79 + +#define SRST_MMC0 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI0 84 +#define SRST_WDT 86 +#define SRST_SARADC 87 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 + +#define SRST_HDMI_P 96 +#define SRST_VIO_BUS_H 99 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_USBPOR 105 + +#define SRST_VCODEC_A 112 +#define SRST_VCODEC_H 113 +#define SRST_VIO1_A 114 +#define SRST_HEVC 115 +#define SRST_VCODEC_NIU_A 116 +#define SRST_LCDC1_A 117 +#define SRST_LCDC1_H 118 +#define SRST_LCDC1_D 119 +#define SRST_GPU 120 +#define SRST_GPU_NIU_A 122 + +#define SRST_DBG_P 131 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/rk3188-cru-common.h b/roms/u-boot/include/dt-bindings/clock/rk3188-cru-common.h new file mode 100644 index 000000000..1e7931da0 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/rk3188-cru-common.h @@ -0,0 +1,255 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H + +/* core clocks from */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define CORE_PERI 5 +#define CORE_L2C 6 +#define ARMCLK 7 + +/* sclk gates (special clocks) */ +#define SCLK_UART0 64 +#define SCLK_UART1 65 +#define SCLK_UART2 66 +#define SCLK_UART3 67 +#define SCLK_MAC 68 +#define SCLK_SPI0 69 +#define SCLK_SPI1 70 +#define SCLK_SARADC 71 +#define SCLK_SDMMC 72 +#define SCLK_SDIO 73 +#define SCLK_EMMC 74 +#define SCLK_I2S0 75 +#define SCLK_I2S1 76 +#define SCLK_I2S2 77 +#define SCLK_SPDIF 78 +#define SCLK_CIF0 79 +#define SCLK_CIF1 80 +#define SCLK_OTGPHY0 81 +#define SCLK_OTGPHY1 82 +#define SCLK_HSADC 83 +#define SCLK_TIMER0 84 +#define SCLK_TIMER1 85 +#define SCLK_TIMER2 86 +#define SCLK_TIMER3 87 +#define SCLK_TIMER4 88 +#define SCLK_TIMER5 89 +#define SCLK_TIMER6 90 +#define SCLK_JTAG 91 +#define SCLK_SMC 92 +#define SCLK_TSADC 93 + +#define DCLK_LCDC0 190 +#define DCLK_LCDC1 191 + +/* aclk gates */ +#define ACLK_DMA1 192 +#define ACLK_DMA2 193 +#define ACLK_GPS 194 +#define ACLK_LCDC0 195 +#define ACLK_LCDC1 196 +#define ACLK_GPU 197 +#define ACLK_SMC 198 +#define ACLK_CIF 199 +#define ACLK_IPP 200 +#define ACLK_RGA 201 +#define ACLK_CIF0 202 +#define ACLK_CPU 203 +#define ACLK_PERI 204 + +/* pclk gates */ +#define PCLK_GRF 320 +#define PCLK_PMU 321 +#define PCLK_TIMER0 322 +#define PCLK_TIMER1 323 +#define PCLK_TIMER2 324 +#define PCLK_TIMER3 325 +#define PCLK_PWM01 326 +#define PCLK_PWM23 327 +#define PCLK_SPI0 328 +#define PCLK_SPI1 329 +#define PCLK_SARADC 330 +#define PCLK_WDT 331 +#define PCLK_UART0 332 +#define PCLK_UART1 333 +#define PCLK_UART2 334 +#define PCLK_UART3 335 +#define PCLK_I2C0 336 +#define PCLK_I2C1 337 +#define PCLK_I2C2 338 +#define PCLK_I2C3 339 +#define PCLK_I2C4 340 +#define PCLK_GPIO0 341 +#define PCLK_GPIO1 342 +#define PCLK_GPIO2 343 +#define PCLK_GPIO3 344 +#define PCLK_GPIO4 345 +#define PCLK_GPIO6 346 +#define PCLK_EFUSE 347 +#define PCLK_TZPC 348 +#define PCLK_TSADC 349 +#define PCLK_CPU 350 +#define PCLK_PERI 351 +#define PCLK_DDRUPCTL 352 +#define PCLK_PUBL 353 + +/* hclk gates */ +#define HCLK_SDMMC 448 +#define HCLK_SDIO 449 +#define HCLK_EMMC 450 +#define HCLK_OTG0 451 +#define HCLK_EMAC 452 +#define HCLK_SPDIF 453 +#define HCLK_I2S0 454 +#define HCLK_I2S1 455 +#define HCLK_I2S2 456 +#define HCLK_OTG1 457 +#define HCLK_HSIC 458 +#define HCLK_HSADC 459 +#define HCLK_PIDF 460 +#define HCLK_LCDC0 461 +#define HCLK_LCDC1 462 +#define HCLK_ROM 463 +#define HCLK_CIF0 464 +#define HCLK_IPP 465 +#define HCLK_RGA 466 +#define HCLK_NANDC0 467 +#define HCLK_CPU 468 +#define HCLK_PERI 469 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_MCORE 2 +#define SRST_CORE0 3 +#define SRST_CORE1 4 +#define SRST_MCORE_DBG 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE0_WDT 12 +#define SRST_CORE1_WDT 13 +#define SRST_STRC_SYS 14 +#define SRST_L2C 15 + +#define SRST_CPU_AHB 17 +#define SRST_AHB2APB 19 +#define SRST_DMA1 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_SPDIF 26 +#define SRST_TIMER0 27 +#define SRST_TIMER1 28 +#define SRST_EFUSE 30 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 + +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_UART3 42 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_I2C3 46 +#define SRST_I2C4 47 + +#define SRST_PWM0 48 +#define SRST_PWM1 49 +#define SRST_DAP_PO 50 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_TPIU_ATB 53 +#define SRST_PMU_APB 54 +#define SRST_GRF 55 +#define SRST_PMU 56 +#define SRST_PERI_AXI 57 +#define SRST_PERI_AHB 58 +#define SRST_PERI_APB 59 +#define SRST_PERI_NIU 60 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA2 64 +#define SRST_SMC 65 +#define SRST_MAC 66 +#define SRST_NANC0 68 +#define SRST_USBOTG0 69 +#define SRST_USBPHY0 70 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_USBPHY1 73 +#define SRST_OTGC1 74 +#define SRST_HSADC 76 +#define SRST_PIDFILTER 77 +#define SRST_DDR_MSCH 79 + +#define SRST_TZPC 80 +#define SRST_SDMMC 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI0 84 +#define SRST_SPI1 85 +#define SRST_WDT 86 +#define SRST_SARADC 87 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_APB 89 +#define SRST_DDRCTL 90 +#define SRST_DDRCTL_APB 91 +#define SRST_DDRPUB 93 + +#define SRST_VIO0_AXI 98 +#define SRST_VIO0_AHB 99 +#define SRST_LCDC0_AXI 100 +#define SRST_LCDC0_AHB 101 +#define SRST_LCDC0_DCLK 102 +#define SRST_LCDC1_AXI 103 +#define SRST_LCDC1_AHB 104 +#define SRST_LCDC1_DCLK 105 +#define SRST_IPP_AXI 106 +#define SRST_IPP_AHB 107 +#define SRST_RGA_AXI 108 +#define SRST_RGA_AHB 109 +#define SRST_CIF0 110 + +#define SRST_VCODEC_AXI 112 +#define SRST_VCODEC_AHB 113 +#define SRST_VIO1_AXI 114 +#define SRST_VCODEC_CPU 115 +#define SRST_VCODEC_NIU 116 +#define SRST_GPU 120 +#define SRST_GPU_NIU 122 +#define SRST_TFUN_ATB 125 +#define SRST_TFUN_APB 126 +#define SRST_CTI4_APB 127 + +#define SRST_TPIU_APB 128 +#define SRST_TRACE 129 +#define SRST_CORE_DBG 130 +#define SRST_DBG_APB 131 +#define SRST_CTI0 132 +#define SRST_CTI0_APB 133 +#define SRST_CTI1 134 +#define SRST_CTI1_APB 135 +#define SRST_PTM_CORE0 136 +#define SRST_PTM_CORE1 137 +#define SRST_PTM0 138 +#define SRST_PTM0_ATB 139 +#define SRST_PTM1 140 +#define SRST_PTM1_ATB 141 +#define SRST_CTM 142 +#define SRST_TS 143 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/rk3188-cru.h b/roms/u-boot/include/dt-bindings/clock/rk3188-cru.h new file mode 100644 index 000000000..1da306e17 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/rk3188-cru.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H + +#include + +/* soft-reset indices */ +#define SRST_PTM_CORE2 0 +#define SRST_PTM_CORE3 1 +#define SRST_CORE2 5 +#define SRST_CORE3 6 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 + +#define SRST_TIMER2 16 +#define SRST_TIMER4 23 +#define SRST_I2S0 24 +#define SRST_TIMER5 25 +#define SRST_TIMER3 29 +#define SRST_TIMER6 31 + +#define SRST_PTM3 36 +#define SRST_PTM3_ATB 37 + +#define SRST_GPS 67 +#define SRST_HSICPHY 75 +#define SRST_TIMER 78 + +#define SRST_PTM2 92 +#define SRST_CORE2_WDT 94 +#define SRST_CORE3_WDT 95 + +#define SRST_PTM2_ATB 111 + +#define SRST_HSIC 117 +#define SRST_CTI2 118 +#define SRST_CTI2_APB 119 +#define SRST_GPU_BRIDGE 121 +#define SRST_CTI3 123 +#define SRST_CTI3_APB 124 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/rk3228-cru.h b/roms/u-boot/include/dt-bindings/clock/rk3228-cru.h new file mode 100644 index 000000000..1217d5239 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/rk3228-cru.h @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define ARMCLK 5 + +/* sclk gates (special clocks) */ +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_TSADC 72 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S0 80 +#define SCLK_I2S1 81 +#define SCLK_I2S2 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_VOP 122 +#define SCLK_HDMI_HDCP 123 +#define SCLK_MAC_SRC 124 +#define SCLK_MAC_EXTCLK 125 +#define SCLK_MAC 126 +#define SCLK_MAC_REFOUT 127 +#define SCLK_MAC_REF 128 +#define SCLK_MAC_RX 129 +#define SCLK_MAC_TX 130 +#define SCLK_MAC_PHY 131 +#define SCLK_MAC_OUT 132 + +/* dclk gates */ +#define DCLK_VOP 190 +#define DCLK_HDMI_PHY 191 + +/* aclk gates */ +#define ACLK_DMAC 194 +#define ACLK_PERI 210 +#define ACLK_VOP 211 +#define ACLK_GMAC 212 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_SPI0 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_TSADC 344 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_PERI 363 +#define PCLK_HDMI_CTRL 364 +#define PCLK_HDMI_PHY 365 +#define PCLK_GMAC 367 + +/* hclk gates */ +#define HCLK_I2S0_8CH 442 +#define HCLK_I2S1_8CH 443 +#define HCLK_I2S2_2CH 444 +#define HCLK_SPDIF_8CH 445 +#define HCLK_VOP 452 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_ACLK_CORE 13 +#define SRST_NOC 14 +#define SRST_L2C 15 + +#define SRST_CPUSYS_H 18 +#define SRST_BUSSYS_H 19 +#define SRST_SPDIF 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_OTG_ADP 23 +#define SRST_I2S0 24 +#define SRST_I2S1 25 +#define SRST_I2S2 26 +#define SRST_ACODEC_P 27 +#define SRST_DFIMON 28 +#define SRST_MSCH 29 +#define SRST_EFUSE1024 30 +#define SRST_EFUSE256 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_PERIPH_NOC_A 36 +#define SRST_PERIPH_NOC_BUS_H 37 +#define SRST_PERIPH_NOC_P 38 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_PHYNOC 42 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_I2C3 46 + +#define SRST_PWM 48 +#define SRST_A53_GIC 49 +#define SRST_DAP 51 +#define SRST_DAP_NOC 52 +#define SRST_CRYPTO 53 +#define SRST_SGRF 54 +#define SRST_GRF 55 +#define SRST_GMAC 56 +#define SRST_PERIPH_NOC_H 58 +#define SRST_MACPHY 63 + +#define SRST_DMA 64 +#define SRST_NANDC 68 +#define SRST_USBOTG 69 +#define SRST_OTGC 70 +#define SRST_USBHOST0 71 +#define SRST_HOST_CTRL0 72 +#define SRST_USBHOST1 73 +#define SRST_HOST_CTRL1 74 +#define SRST_USBHOST2 75 +#define SRST_HOST_CTRL2 76 +#define SRST_USBPOR0 77 +#define SRST_USBPOR1 78 +#define SRST_DDRMSCH 79 + +#define SRST_SMART_CARD 80 +#define SRST_SDMMC 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI 84 +#define SRST_TSP_H 85 +#define SRST_TSP 86 +#define SRST_TSADC 87 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 +#define SRST_HOST0_ECHI 92 +#define SRST_HOST1_ECHI 93 +#define SRST_HOST2_ECHI 94 +#define SRST_VOP_NOC_A 95 + +#define SRST_HDMI_P 96 +#define SRST_VIO_ARBI_H 97 +#define SRST_IEP_NOC_A 98 +#define SRST_VIO_NOC_H 99 +#define SRST_VOP_A 100 +#define SRST_VOP_H 101 +#define SRST_VOP_D 102 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_UTMI2 105 +#define SRST_UTMI3 106 +#define SRST_RGA 107 +#define SRST_RGA_NOC_A 108 +#define SRST_RGA_A 109 +#define SRST_RGA_H 110 +#define SRST_HDCP_A 111 + +#define SRST_VPU_A 112 +#define SRST_VPU_H 113 +#define SRST_VPU_NOC_A 116 +#define SRST_VPU_NOC_H 117 +#define SRST_RKVDEC_A 118 +#define SRST_RKVDEC_NOC_A 119 +#define SRST_RKVDEC_H 120 +#define SRST_RKVDEC_NOC_H 121 +#define SRST_RKVDEC_CORE 122 +#define SRST_RKVDEC_CABAC 123 +#define SRST_IEP_A 124 +#define SRST_IEP_H 125 +#define SRST_GPU_A 126 +#define SRST_GPU_NOC_A 127 + +#define SRST_CORE_DBG 128 +#define SRST_DBG_P 129 +#define SRST_TIMER0 130 +#define SRST_TIMER1 131 +#define SRST_TIMER2 132 +#define SRST_TIMER3 133 +#define SRST_TIMER4 134 +#define SRST_TIMER5 135 +#define SRST_VIO_H2P 136 +#define SRST_HDMIPHY 139 +#define SRST_VDAC 140 +#define SRST_TIMER_6CH_P 141 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/rk3288-cru.h b/roms/u-boot/include/dt-bindings/clock/rk3288-cru.h new file mode 100644 index 000000000..e368d7675 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/rk3288-cru.h @@ -0,0 +1,370 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner + */ + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_NPLL 5 +#define ARMCLK 6 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI0 65 +#define SCLK_SPI1 66 +#define SCLK_SPI2 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO0 69 +#define SCLK_SDIO1 70 +#define SCLK_EMMC 71 +#define SCLK_TSADC 72 +#define SCLK_SARADC 73 +#define SCLK_PS2C 74 +#define SCLK_NANDC0 75 +#define SCLK_NANDC1 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_UART3 80 +#define SCLK_UART4 81 +#define SCLK_I2S0 82 +#define SCLK_SPDIF 83 +#define SCLK_SPDIF8CH 84 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 +#define SCLK_TIMER6 91 +#define SCLK_HSADC 92 +#define SCLK_OTGPHY0 93 +#define SCLK_OTGPHY1 94 +#define SCLK_OTGPHY2 95 +#define SCLK_OTG_ADP 96 +#define SCLK_HSICPHY480M 97 +#define SCLK_HSICPHY12M 98 +#define SCLK_MACREF 99 +#define SCLK_LCDC_PWM0 100 +#define SCLK_LCDC_PWM1 101 +#define SCLK_MAC_RX 102 +#define SCLK_MAC_TX 103 +#define SCLK_EDP_24M 104 +#define SCLK_EDP 105 +#define SCLK_RGA 106 +#define SCLK_ISP 107 +#define SCLK_ISP_JPE 108 +#define SCLK_HDMI_HDCP 109 +#define SCLK_HDMI_CEC 110 +#define SCLK_HEVC_CABAC 111 +#define SCLK_HEVC_CORE 112 +#define SCLK_I2S0_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO0_DRV 115 +#define SCLK_SDIO1_DRV 116 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO0_SAMPLE 119 +#define SCLK_SDIO1_SAMPLE 120 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_USBPHY480M_SRC 122 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 + +#define SCLK_MAC_PLL 150 +#define SCLK_MAC 151 +#define SCLK_MACREF_OUT 152 + +#define DCLK_VOP0 190 +#define DCLK_VOP1 191 + +/* aclk gates */ +#define ACLK_GPU 192 +#define ACLK_DMAC1 193 +#define ACLK_DMAC2 194 +#define ACLK_MMU 195 +#define ACLK_GMAC 196 +#define ACLK_VOP0 197 +#define ACLK_VOP1 198 +#define ACLK_CRYPTO 199 +#define ACLK_RGA 200 +#define ACLK_RGA_NIU 201 +#define ACLK_IEP 202 +#define ACLK_VIO0_NIU 203 +#define ACLK_VIP 204 +#define ACLK_ISP 205 +#define ACLK_VIO1_NIU 206 +#define ACLK_HEVC 207 +#define ACLK_VCODEC 208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_GPIO4 324 +#define PCLK_GPIO5 325 +#define PCLK_GPIO6 326 +#define PCLK_GPIO7 327 +#define PCLK_GPIO8 328 +#define PCLK_GRF 329 +#define PCLK_SGRF 330 +#define PCLK_PMU 331 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_I2C4 336 +#define PCLK_I2C5 337 +#define PCLK_SPI0 338 +#define PCLK_SPI1 339 +#define PCLK_SPI2 340 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_UART3 344 +#define PCLK_UART4 345 +#define PCLK_TSADC 346 +#define PCLK_SARADC 347 +#define PCLK_SIM 348 +#define PCLK_GMAC 349 +#define PCLK_PWM 350 +#define PCLK_RKPWM 351 +#define PCLK_PS2C 352 +#define PCLK_TIMER 353 +#define PCLK_TZPC 354 +#define PCLK_EDP_CTRL 355 +#define PCLK_MIPI_DSI0 356 +#define PCLK_MIPI_DSI1 357 +#define PCLK_MIPI_CSI 358 +#define PCLK_LVDS_PHY 359 +#define PCLK_HDMI_CTRL 360 +#define PCLK_VIO2_H2P 361 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL0 364 +#define PCLK_PUBL0 365 +#define PCLK_DDRUPCTL1 366 +#define PCLK_PUBL1 367 +#define PCLK_WDT 368 + +/* hclk gates */ +#define HCLK_GPS 448 +#define HCLK_OTG0 449 +#define HCLK_USBHOST0 450 +#define HCLK_USBHOST1 451 +#define HCLK_HSIC 452 +#define HCLK_NANDC0 453 +#define HCLK_NANDC1 454 +#define HCLK_TSP 455 +#define HCLK_SDMMC 456 +#define HCLK_SDIO0 457 +#define HCLK_SDIO1 458 +#define HCLK_EMMC 459 +#define HCLK_HSADC 460 +#define HCLK_CRYPTO 461 +#define HCLK_I2S0 462 +#define HCLK_SPDIF 463 +#define HCLK_SPDIF8CH 464 +#define HCLK_VOP0 465 +#define HCLK_VOP1 466 +#define HCLK_ROM 467 +#define HCLK_IEP 468 +#define HCLK_ISP 469 +#define HCLK_RGA 470 +#define HCLK_VIO_AHB_ARBI 471 +#define HCLK_VIO_NIU 472 +#define HCLK_VIP 473 +#define HCLK_VIO2_H2P 474 +#define HCLK_HEVC 475 +#define HCLK_VCODEC 476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE2 2 +#define SRST_CORE3 3 +#define SRST_CORE0_PO 4 +#define SRST_CORE1_PO 5 +#define SRST_CORE2_PO 6 +#define SRST_CORE3_PO 7 +#define SRST_PDCORE_STRSYS 8 +#define SRST_PDBUS_STRSYS 9 +#define SRST_L2C 10 +#define SRST_TOPDBG 11 +#define SRST_CORE0_DBG 12 +#define SRST_CORE1_DBG 13 +#define SRST_CORE2_DBG 14 +#define SRST_CORE3_DBG 15 + +#define SRST_PDBUG_AHB_ARBITOR 16 +#define SRST_EFUSE256 17 +#define SRST_DMAC1 18 +#define SRST_INTMEM 19 +#define SRST_ROM 20 +#define SRST_SPDIF8CH 21 +#define SRST_TIMER 22 +#define SRST_I2S0 23 +#define SRST_SPDIF 24 +#define SRST_TIMER0 25 +#define SRST_TIMER1 26 +#define SRST_TIMER2 27 +#define SRST_TIMER3 28 +#define SRST_TIMER4 29 +#define SRST_TIMER5 30 +#define SRST_EFUSE 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_GPIO4 36 +#define SRST_GPIO5 37 +#define SRST_GPIO6 38 +#define SRST_GPIO7 39 +#define SRST_GPIO8 40 +#define SRST_I2C0 42 +#define SRST_I2C1 43 +#define SRST_I2C2 44 +#define SRST_I2C3 45 +#define SRST_I2C4 46 +#define SRST_I2C5 47 + +#define SRST_DWPWM 48 +#define SRST_MMC_PERI 49 +#define SRST_PERIPH_MMU 50 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_TPIU 53 +#define SRST_PMU_APB 54 +#define SRST_GRF 55 +#define SRST_PMU 56 +#define SRST_PERIPH_AXI 57 +#define SRST_PERIPH_AHB 58 +#define SRST_PERIPH_APB 59 +#define SRST_PERIPH_NIU 60 +#define SRST_PDPERI_AHB_ARBI 61 +#define SRST_EMEM 62 +#define SRST_USB_PERI 63 + +#define SRST_DMAC2 64 +#define SRST_MAC 66 +#define SRST_GPS 67 +#define SRST_RKPWM 69 +#define SRST_CCP 71 +#define SRST_USBHOST0 72 +#define SRST_HSIC 73 +#define SRST_HSIC_AUX 74 +#define SRST_HSIC_PHY 75 +#define SRST_HSADC 76 +#define SRST_NANDC0 77 +#define SRST_NANDC1 78 + +#define SRST_TZPC 80 +#define SRST_SPI0 83 +#define SRST_SPI1 84 +#define SRST_SPI2 85 +#define SRST_SARADC 87 +#define SRST_PDALIVE_NIU 88 +#define SRST_PDPMU_INTMEM 89 +#define SRST_PDPMU_NIU 90 +#define SRST_SGRF 91 + +#define SRST_VIO_ARBI 96 +#define SRST_RGA_NIU 97 +#define SRST_VIO0_NIU_AXI 98 +#define SRST_VIO_NIU_AHB 99 +#define SRST_LCDC0_AXI 100 +#define SRST_LCDC0_AHB 101 +#define SRST_LCDC0_DCLK 102 +#define SRST_VIO1_NIU_AXI 103 +#define SRST_VIP 104 +#define SRST_RGA_CORE 105 +#define SRST_IEP_AXI 106 +#define SRST_IEP_AHB 107 +#define SRST_RGA_AXI 108 +#define SRST_RGA_AHB 109 +#define SRST_ISP 110 +#define SRST_EDP 111 + +#define SRST_VCODEC_AXI 112 +#define SRST_VCODEC_AHB 113 +#define SRST_VIO_H2P 114 +#define SRST_MIPIDSI0 115 +#define SRST_MIPIDSI1 116 +#define SRST_MIPICSI 117 +#define SRST_LVDS_PHY 118 +#define SRST_LVDS_CON 119 +#define SRST_GPU 120 +#define SRST_HDMI 121 +#define SRST_CORE_PVTM 124 +#define SRST_GPU_PVTM 125 + +#define SRST_MMC0 128 +#define SRST_SDIO0 129 +#define SRST_SDIO1 130 +#define SRST_EMMC 131 +#define SRST_USBOTG_AHB 132 +#define SRST_USBOTG_PHY 133 +#define SRST_USBOTG_CON 134 +#define SRST_USBHOST0_AHB 135 +#define SRST_USBHOST0_PHY 136 +#define SRST_USBHOST0_CON 137 +#define SRST_USBHOST1_AHB 138 +#define SRST_USBHOST1_PHY 139 +#define SRST_USBHOST1_CON 140 +#define SRST_USB_ADP 141 +#define SRST_ACC_EFUSE 142 + +#define SRST_CORESIGHT 144 +#define SRST_PD_CORE_AHB_NOC 145 +#define SRST_PD_CORE_APB_NOC 146 +#define SRST_PD_CORE_MP_AXI 147 +#define SRST_GIC 148 +#define SRST_LCDC_PWM0 149 +#define SRST_LCDC_PWM1 150 +#define SRST_VIO0_H2P_BRG 151 +#define SRST_VIO1_H2P_BRG 152 +#define SRST_RGA_H2P_BRG 153 +#define SRST_HEVC 154 +#define SRST_TSADC 159 + +#define SRST_DDRPHY0 160 +#define SRST_DDRPHY0_APB 161 +#define SRST_DDRCTRL0 162 +#define SRST_DDRCTRL0_APB 163 +#define SRST_DDRPHY0_CTRL 164 +#define SRST_DDRPHY1 165 +#define SRST_DDRPHY1_APB 166 +#define SRST_DDRCTRL1 167 +#define SRST_DDRCTRL1_APB 168 +#define SRST_DDRPHY1_CTRL 169 +#define SRST_DDRMSCH0 170 +#define SRST_DDRMSCH1 171 +#define SRST_CRYPTO 174 +#define SRST_C2C_HOST 175 + +#define SRST_LCDC1_AXI 176 +#define SRST_LCDC1_AHB 177 +#define SRST_LCDC1_DCLK 178 +#define SRST_UART0 179 +#define SRST_UART1 180 +#define SRST_UART2 181 +#define SRST_UART3 182 +#define SRST_UART4 183 +#define SRST_SIMC 186 +#define SRST_PS2C 187 +#define SRST_TSP 188 +#define SRST_TSP_CLKIN0 189 +#define SRST_TSP_CLKIN1 190 +#define SRST_TSP_27M 191 diff --git a/roms/u-boot/include/dt-bindings/clock/rk3308-cru.h b/roms/u-boot/include/dt-bindings/clock/rk3308-cru.h new file mode 100644 index 000000000..d97840f9e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/rk3308-cru.h @@ -0,0 +1,387 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 Rockchip Electronics Co. Ltd. + * Author: Finley Xiao + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_VPLL0 3 +#define PLL_VPLL1 4 +#define ARMCLK 5 + +/* sclk (special clocks) */ +#define USB480M 14 +#define SCLK_RTC32K 15 +#define SCLK_PVTM_CORE 16 +#define SCLK_UART0 17 +#define SCLK_UART1 18 +#define SCLK_UART2 19 +#define SCLK_UART3 20 +#define SCLK_UART4 21 +#define SCLK_I2C0 22 +#define SCLK_I2C1 23 +#define SCLK_I2C2 24 +#define SCLK_I2C3 25 +#define SCLK_PWM0 26 +#define SCLK_SPI0 27 +#define SCLK_SPI1 28 +#define SCLK_SPI2 29 +#define SCLK_TIMER0 30 +#define SCLK_TIMER1 31 +#define SCLK_TIMER2 32 +#define SCLK_TIMER3 33 +#define SCLK_TIMER4 34 +#define SCLK_TIMER5 35 +#define SCLK_TSADC 36 +#define SCLK_SARADC 37 +#define SCLK_OTP 38 +#define SCLK_OTP_USR 39 +#define SCLK_CPU_BOOST 40 +#define SCLK_CRYPTO 41 +#define SCLK_CRYPTO_APK 42 +#define SCLK_NANDC_DIV 43 +#define SCLK_NANDC_DIV50 44 +#define SCLK_NANDC 45 +#define SCLK_SDMMC_DIV 46 +#define SCLK_SDMMC_DIV50 47 +#define SCLK_SDMMC 48 +#define SCLK_SDMMC_DRV 49 +#define SCLK_SDMMC_SAMPLE 50 +#define SCLK_SDIO_DIV 51 +#define SCLK_SDIO_DIV50 52 +#define SCLK_SDIO 53 +#define SCLK_SDIO_DRV 54 +#define SCLK_SDIO_SAMPLE 55 +#define SCLK_EMMC_DIV 56 +#define SCLK_EMMC_DIV50 57 +#define SCLK_EMMC 58 +#define SCLK_EMMC_DRV 59 +#define SCLK_EMMC_SAMPLE 60 +#define SCLK_SFC 61 +#define SCLK_OTG_ADP 62 +#define SCLK_MAC_SRC 63 +#define SCLK_MAC 64 +#define SCLK_MAC_REF 65 +#define SCLK_MAC_RX_TX 66 +#define SCLK_MAC_RMII 67 +#define SCLK_DDR_MON_TIMER 68 +#define SCLK_DDR_MON 69 +#define SCLK_DDRCLK 70 +#define SCLK_PMU 71 +#define SCLK_USBPHY_REF 72 +#define SCLK_WIFI 73 +#define SCLK_PVTM_PMU 74 +#define SCLK_PDM 75 +#define SCLK_I2S0_8CH_TX 76 +#define SCLK_I2S0_8CH_TX_OUT 77 +#define SCLK_I2S0_8CH_RX 78 +#define SCLK_I2S0_8CH_RX_OUT 79 +#define SCLK_I2S1_8CH_TX 80 +#define SCLK_I2S1_8CH_TX_OUT 81 +#define SCLK_I2S1_8CH_RX 82 +#define SCLK_I2S1_8CH_RX_OUT 83 +#define SCLK_I2S2_8CH_TX 84 +#define SCLK_I2S2_8CH_TX_OUT 85 +#define SCLK_I2S2_8CH_RX 86 +#define SCLK_I2S2_8CH_RX_OUT 87 +#define SCLK_I2S3_8CH_TX 88 +#define SCLK_I2S3_8CH_TX_OUT 89 +#define SCLK_I2S3_8CH_RX 90 +#define SCLK_I2S3_8CH_RX_OUT 91 +#define SCLK_I2S0_2CH 92 +#define SCLK_I2S0_2CH_OUT 93 +#define SCLK_I2S1_2CH 94 +#define SCLK_I2S1_2CH_OUT 95 +#define SCLK_SPDIF_TX_DIV 96 +#define SCLK_SPDIF_TX_DIV50 97 +#define SCLK_SPDIF_TX 98 +#define SCLK_SPDIF_RX_DIV 99 +#define SCLK_SPDIF_RX_DIV50 100 +#define SCLK_SPDIF_RX 101 +#define SCLK_I2S0_8CH_TX_MUX 102 +#define SCLK_I2S0_8CH_RX_MUX 103 +#define SCLK_I2S1_8CH_TX_MUX 104 +#define SCLK_I2S1_8CH_RX_MUX 105 +#define SCLK_I2S2_8CH_TX_MUX 106 +#define SCLK_I2S2_8CH_RX_MUX 107 +#define SCLK_I2S3_8CH_TX_MUX 108 +#define SCLK_I2S3_8CH_RX_MUX 109 +#define SCLK_I2S0_8CH_TX_SRC 110 +#define SCLK_I2S0_8CH_RX_SRC 111 +#define SCLK_I2S1_8CH_TX_SRC 112 +#define SCLK_I2S1_8CH_RX_SRC 113 +#define SCLK_I2S2_8CH_TX_SRC 114 +#define SCLK_I2S2_8CH_RX_SRC 115 +#define SCLK_I2S3_8CH_TX_SRC 116 +#define SCLK_I2S3_8CH_RX_SRC 117 +#define SCLK_I2S0_2CH_SRC 118 +#define SCLK_I2S1_2CH_SRC 119 +#define SCLK_PWM1 120 +#define SCLK_PWM2 121 +#define SCLK_OWIRE 122 + +/* dclk */ +#define DCLK_VOP 125 + +/* aclk */ +#define ACLK_BUS_SRC 130 +#define ACLK_BUS 131 +#define ACLK_PERI_SRC 132 +#define ACLK_PERI 133 +#define ACLK_MAC 134 +#define ACLK_CRYPTO 135 +#define ACLK_VOP 136 +#define ACLK_GIC 137 +#define ACLK_DMAC0 138 +#define ACLK_DMAC1 139 + +/* hclk */ +#define HCLK_BUS 150 +#define HCLK_PERI 151 +#define HCLK_AUDIO 152 +#define HCLK_NANDC 153 +#define HCLK_SDMMC 154 +#define HCLK_SDIO 155 +#define HCLK_EMMC 156 +#define HCLK_SFC 157 +#define HCLK_OTG 158 +#define HCLK_HOST 159 +#define HCLK_HOST_ARB 160 +#define HCLK_PDM 161 +#define HCLK_SPDIFTX 162 +#define HCLK_SPDIFRX 163 +#define HCLK_I2S0_8CH 164 +#define HCLK_I2S1_8CH 165 +#define HCLK_I2S2_8CH 166 +#define HCLK_I2S3_8CH 167 +#define HCLK_I2S0_2CH 168 +#define HCLK_I2S1_2CH 169 +#define HCLK_VAD 170 +#define HCLK_CRYPTO 171 +#define HCLK_VOP 172 + +/* pclk */ +#define PCLK_BUS 190 +#define PCLK_DDR 191 +#define PCLK_PERI 192 +#define PCLK_PMU 193 +#define PCLK_AUDIO 194 +#define PCLK_MAC 195 +#define PCLK_ACODEC 196 +#define PCLK_UART0 197 +#define PCLK_UART1 198 +#define PCLK_UART2 199 +#define PCLK_UART3 200 +#define PCLK_UART4 201 +#define PCLK_I2C0 202 +#define PCLK_I2C1 203 +#define PCLK_I2C2 204 +#define PCLK_I2C3 205 +#define PCLK_PWM0 206 +#define PCLK_SPI0 207 +#define PCLK_SPI1 208 +#define PCLK_SPI2 209 +#define PCLK_SARADC 210 +#define PCLK_TSADC 211 +#define PCLK_TIMER 212 +#define PCLK_OTP_NS 213 +#define PCLK_WDT 214 +#define PCLK_GPIO0 215 +#define PCLK_GPIO1 216 +#define PCLK_GPIO2 217 +#define PCLK_GPIO3 218 +#define PCLK_GPIO4 219 +#define PCLK_SGRF 220 +#define PCLK_GRF 221 +#define PCLK_USBSD_DET 222 +#define PCLK_DDR_UPCTL 223 +#define PCLK_DDR_MON 224 +#define PCLK_DDRPHY 225 +#define PCLK_DDR_STDBY 226 +#define PCLK_USB_GRF 227 +#define PCLK_CRU 228 +#define PCLK_OTP_PHY 229 +#define PCLK_CPU_BOOST 230 +#define PCLK_PWM1 231 +#define PCLK_PWM2 232 +#define PCLK_CAN 233 +#define PCLK_OWIRE 234 + +#define CLK_NR_CLKS (PCLK_OWIRE + 1) + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_CORE_NOC 13 +#define SRST_STRC_A 14 +#define SRST_L2C 15 + +/* cru_softrst_con1 */ +#define SRST_DAP 16 +#define SRST_CORE_PVTM 17 +#define SRST_CORE_PRF 18 +#define SRST_CORE_GRF 19 +#define SRST_DDRUPCTL 20 +#define SRST_DDRUPCTL_P 22 +#define SRST_MSCH 23 +#define SRST_DDRMON_P 25 +#define SRST_DDRSTDBY_P 26 +#define SRST_DDRSTDBY 27 +#define SRST_DDRPHY 28 +#define SRST_DDRPHY_DIV 29 +#define SRST_DDRPHY_P 30 + +/* cru_softrst_con2 */ +#define SRST_BUS_NIU_H 32 +#define SRST_USB_NIU_P 33 +#define SRST_CRYPTO_A 34 +#define SRST_CRYPTO_H 35 +#define SRST_CRYPTO 36 +#define SRST_CRYPTO_APK 37 +#define SRST_VOP_A 38 +#define SRST_VOP_H 39 +#define SRST_VOP_D 40 +#define SRST_INTMEM_A 41 +#define SRST_ROM_H 42 +#define SRST_GIC_A 43 +#define SRST_UART0_P 44 +#define SRST_UART0 45 +#define SRST_UART1_P 46 +#define SRST_UART1 47 + +/* cru_softrst_con3 */ +#define SRST_UART2_P 48 +#define SRST_UART2 49 +#define SRST_UART3_P 50 +#define SRST_UART3 51 +#define SRST_UART4_P 52 +#define SRST_UART4 53 +#define SRST_I2C0_P 54 +#define SRST_I2C0 55 +#define SRST_I2C1_P 56 +#define SRST_I2C1 57 +#define SRST_I2C2_P 58 +#define SRST_I2C2 59 +#define SRST_I2C3_P 60 +#define SRST_I2C3 61 +#define SRST_PWM0_P 62 +#define SRST_PWM0 63 + +/* cru_softrst_con4 */ +#define SRST_SPI0_P 64 +#define SRST_SPI0 65 +#define SRST_SPI1_P 66 +#define SRST_SPI1 67 +#define SRST_SPI2_P 68 +#define SRST_SPI2 69 +#define SRST_SARADC_P 70 +#define SRST_TSADC_P 71 +#define SRST_TSADC 72 +#define SRST_TIMER0_P 73 +#define SRST_TIMER0 74 +#define SRST_TIMER1 75 +#define SRST_TIMER2 76 +#define SRST_TIMER3 77 +#define SRST_TIMER4 78 +#define SRST_TIMER5 79 + +/* cru_softrst_con5 */ +#define SRST_OTP_NS_P 80 +#define SRST_OTP_NS_SBPI 81 +#define SRST_OTP_NS_USR 82 +#define SRST_OTP_PHY_P 83 +#define SRST_OTP_PHY 84 +#define SRST_GPIO0_P 86 +#define SRST_GPIO1_P 87 +#define SRST_GPIO2_P 88 +#define SRST_GPIO3_P 89 +#define SRST_GPIO4_P 90 +#define SRST_GRF_P 91 +#define SRST_USBSD_DET_P 92 +#define SRST_PMU 93 +#define SRST_PMU_PVTM 94 +#define SRST_USB_GRF_P 95 + +/* cru_softrst_con6 */ +#define SRST_CPU_BOOST 96 +#define SRST_CPU_BOOST_P 97 +#define SRST_PWM1_P 98 +#define SRST_PWM1 99 +#define SRST_PWM2_P 100 +#define SRST_PWM2 101 +#define SRST_PERI_NIU_A 104 +#define SRST_PERI_NIU_H 105 +#define SRST_PERI_NIU_p 106 +#define SRST_USB2OTG_H 107 +#define SRST_USB2OTG 108 +#define SRST_USB2OTG_ADP 109 +#define SRST_USB2HOST_H 110 +#define SRST_USB2HOST_ARB_H 111 + +/* cru_softrst_con7 */ +#define SRST_USB2HOST_AUX_H 112 +#define SRST_USB2HOST_EHCI 113 +#define SRST_USB2HOST 114 +#define SRST_USBPHYPOR 115 +#define SRST_UTMI0 116 +#define SRST_UTMI1 117 +#define SRST_SDIO_H 118 +#define SRST_EMMC_H 119 +#define SRST_SFC_H 120 +#define SRST_SFC 121 +#define SRST_SD_H 122 +#define SRST_NANDC_H 123 +#define SRST_NANDC_N 124 +#define SRST_MAC_A 125 +#define SRST_CAN_P 126 +#define SRST_OWIRE_P 127 + +/* cru_softrst_con8 */ +#define SRST_AUDIO_NIU_H 128 +#define SRST_AUDIO_NIU_P 129 +#define SRST_PDM_H 130 +#define SRST_PDM_M 131 +#define SRST_SPDIFTX_H 132 +#define SRST_SPDIFTX_M 133 +#define SRST_SPDIFRX_H 134 +#define SRST_SPDIFRX_M 135 +#define SRST_I2S0_8CH_H 136 +#define SRST_I2S0_8CH_TX_M 137 +#define SRST_I2S0_8CH_RX_M 138 +#define SRST_I2S1_8CH_H 139 +#define SRST_I2S1_8CH_TX_M 140 +#define SRST_I2S1_8CH_RX_M 141 +#define SRST_I2S2_8CH_H 142 +#define SRST_I2S2_8CH_TX_M 143 + +/* cru_softrst_con9 */ +#define SRST_I2S2_8CH_RX_M 144 +#define SRST_I2S3_8CH_H 145 +#define SRST_I2S3_8CH_TX_M 146 +#define SRST_I2S3_8CH_RX_M 147 +#define SRST_I2S0_2CH_H 148 +#define SRST_I2S0_2CH_M 149 +#define SRST_I2S1_2CH_H 150 +#define SRST_I2S1_2CH_M 151 +#define SRST_VAD_H 152 +#define SRST_ACODEC_P 153 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/rk3328-cru.h b/roms/u-boot/include/dt-bindings/clock/rk3328-cru.h new file mode 100644 index 000000000..555b4ff66 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/rk3328-cru.h @@ -0,0 +1,393 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Elaine + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_NPLL 5 +#define ARMCLK 6 + +/* sclk gates (special clocks) */ +#define SCLK_RTC32K 30 +#define SCLK_SDMMC_EXT 31 +#define SCLK_SPI 32 +#define SCLK_SDMMC 33 +#define SCLK_SDIO 34 +#define SCLK_EMMC 35 +#define SCLK_TSADC 36 +#define SCLK_SARADC 37 +#define SCLK_UART0 38 +#define SCLK_UART1 39 +#define SCLK_UART2 40 +#define SCLK_I2S0 41 +#define SCLK_I2S1 42 +#define SCLK_I2S2 43 +#define SCLK_I2S1_OUT 44 +#define SCLK_I2S2_OUT 45 +#define SCLK_SPDIF 46 +#define SCLK_TIMER0 47 +#define SCLK_TIMER1 48 +#define SCLK_TIMER2 49 +#define SCLK_TIMER3 50 +#define SCLK_TIMER4 51 +#define SCLK_TIMER5 52 +#define SCLK_WIFI 53 +#define SCLK_CIF_OUT 54 +#define SCLK_I2C0 55 +#define SCLK_I2C1 56 +#define SCLK_I2C2 57 +#define SCLK_I2C3 58 +#define SCLK_CRYPTO 59 +#define SCLK_PWM 60 +#define SCLK_PDM 61 +#define SCLK_EFUSE 62 +#define SCLK_OTP 63 +#define SCLK_DDRCLK 64 +#define SCLK_VDEC_CABAC 65 +#define SCLK_VDEC_CORE 66 +#define SCLK_VENC_DSP 67 +#define SCLK_VENC_CORE 68 +#define SCLK_RGA 69 +#define SCLK_HDMI_SFC 70 +#define SCLK_HDMI_CEC 71 +#define SCLK_USB3_REF 72 +#define SCLK_USB3_SUSPEND 73 +#define SCLK_SDMMC_DRV 74 +#define SCLK_SDIO_DRV 75 +#define SCLK_EMMC_DRV 76 +#define SCLK_SDMMC_EXT_DRV 77 +#define SCLK_SDMMC_SAMPLE 78 +#define SCLK_SDIO_SAMPLE 79 +#define SCLK_EMMC_SAMPLE 80 +#define SCLK_SDMMC_EXT_SAMPLE 81 +#define SCLK_VOP 82 +#define SCLK_MAC2PHY_RXTX 83 +#define SCLK_MAC2PHY_SRC 84 +#define SCLK_MAC2PHY_REF 85 +#define SCLK_MAC2PHY_OUT 86 +#define SCLK_MAC2IO_RX 87 +#define SCLK_MAC2IO_TX 88 +#define SCLK_MAC2IO_REFOUT 89 +#define SCLK_MAC2IO_REF 90 +#define SCLK_MAC2IO_OUT 91 +#define SCLK_TSP 92 +#define SCLK_HSADC_TSP 93 +#define SCLK_USB3PHY_REF 94 +#define SCLK_REF_USB3OTG 95 +#define SCLK_USB3OTG_REF 96 +#define SCLK_USB3OTG_SUSPEND 97 +#define SCLK_REF_USB3OTG_SRC 98 +#define SCLK_MAC2IO_SRC 99 +#define SCLK_MAC2IO 100 +#define SCLK_MAC2PHY 101 +#define SCLK_MAC2IO_EXT 102 + +/* dclk gates */ +#define DCLK_LCDC 120 +#define DCLK_HDMIPHY 121 +#define HDMIPHY 122 +#define USB480M 123 +#define DCLK_LCDC_SRC 124 + +/* aclk gates */ +#define ACLK_AXISRAM 130 +#define ACLK_VOP_PRE 131 +#define ACLK_USB3OTG 132 +#define ACLK_RGA_PRE 133 +#define ACLK_DMAC 134 +#define ACLK_GPU 135 +#define ACLK_BUS_PRE 136 +#define ACLK_PERI_PRE 137 +#define ACLK_RKVDEC_PRE 138 +#define ACLK_RKVDEC 139 +#define ACLK_RKVENC 140 +#define ACLK_VPU_PRE 141 +#define ACLK_VIO_PRE 142 +#define ACLK_VPU 143 +#define ACLK_VIO 144 +#define ACLK_VOP 145 +#define ACLK_GMAC 146 +#define ACLK_H265 147 +#define ACLK_H264 148 +#define ACLK_MAC2PHY 149 +#define ACLK_MAC2IO 150 +#define ACLK_DCF 151 +#define ACLK_TSP 152 +#define ACLK_PERI 153 +#define ACLK_RGA 154 +#define ACLK_IEP 155 +#define ACLK_CIF 156 +#define ACLK_HDCP 157 + +/* pclk gates */ +#define PCLK_GPIO0 200 +#define PCLK_GPIO1 201 +#define PCLK_GPIO2 202 +#define PCLK_GPIO3 203 +#define PCLK_GRF 204 +#define PCLK_I2C0 205 +#define PCLK_I2C1 206 +#define PCLK_I2C2 207 +#define PCLK_I2C3 208 +#define PCLK_SPI 209 +#define PCLK_UART0 210 +#define PCLK_UART1 211 +#define PCLK_UART2 212 +#define PCLK_TSADC 213 +#define PCLK_PWM 214 +#define PCLK_TIMER 215 +#define PCLK_BUS_PRE 216 +#define PCLK_PERI_PRE 217 +#define PCLK_HDMI_CTRL 218 +#define PCLK_HDMI_PHY 219 +#define PCLK_GMAC 220 +#define PCLK_H265 221 +#define PCLK_MAC2PHY 222 +#define PCLK_MAC2IO 223 +#define PCLK_USB3PHY_OTG 224 +#define PCLK_USB3PHY_PIPE 225 +#define PCLK_USB3_GRF 226 +#define PCLK_USB2_GRF 227 +#define PCLK_HDMIPHY 228 +#define PCLK_DDR 229 +#define PCLK_PERI 230 +#define PCLK_HDMI 231 +#define PCLK_HDCP 232 +#define PCLK_DCF 233 +#define PCLK_SARADC 234 +#define PCLK_ACODECPHY 235 +#define PCLK_WDT 236 + +/* hclk gates */ +#define HCLK_PERI 308 +#define HCLK_TSP 309 +#define HCLK_GMAC 310 +#define HCLK_I2S0_8CH 311 +#define HCLK_I2S1_8CH 312 +#define HCLK_I2S2_2CH 313 +#define HCLK_SPDIF_8CH 314 +#define HCLK_VOP 315 +#define HCLK_NANDC 316 +#define HCLK_SDMMC 317 +#define HCLK_SDIO 318 +#define HCLK_EMMC 319 +#define HCLK_SDMMC_EXT 320 +#define HCLK_RKVDEC_PRE 321 +#define HCLK_RKVDEC 322 +#define HCLK_RKVENC 323 +#define HCLK_VPU_PRE 324 +#define HCLK_VIO_PRE 325 +#define HCLK_VPU 326 +#define HCLK_BUS_PRE 328 +#define HCLK_PERI_PRE 329 +#define HCLK_H264 330 +#define HCLK_CIF 331 +#define HCLK_OTG_PMU 332 +#define HCLK_OTG 333 +#define HCLK_HOST0 334 +#define HCLK_HOST0_ARB 335 +#define HCLK_CRYPTO_MST 336 +#define HCLK_CRYPTO_SLV 337 +#define HCLK_PDM 338 +#define HCLK_IEP 339 +#define HCLK_RGA 340 +#define HCLK_HDCP 341 + +#define CLK_NR_CLKS (HCLK_HDCP + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_CORE_NIU 13 +#define SRST_STRC_A 14 +#define SRST_L2C 15 + +#define SRST_A53_GIC 18 +#define SRST_DAP 19 +#define SRST_PMU_P 21 +#define SRST_EFUSE 22 +#define SRST_BUSSYS_H 23 +#define SRST_BUSSYS_P 24 +#define SRST_SPDIF 25 +#define SRST_INTMEM 26 +#define SRST_ROM 27 +#define SRST_GPIO0 28 +#define SRST_GPIO1 29 +#define SRST_GPIO2 30 +#define SRST_GPIO3 31 + +#define SRST_I2S0 32 +#define SRST_I2S1 33 +#define SRST_I2S2 34 +#define SRST_I2S0_H 35 +#define SRST_I2S1_H 36 +#define SRST_I2S2_H 37 +#define SRST_UART0 38 +#define SRST_UART1 39 +#define SRST_UART2 40 +#define SRST_UART0_P 41 +#define SRST_UART1_P 42 +#define SRST_UART2_P 43 +#define SRST_I2C0 44 +#define SRST_I2C1 45 +#define SRST_I2C2 46 +#define SRST_I2C3 47 + +#define SRST_I2C0_P 48 +#define SRST_I2C1_P 49 +#define SRST_I2C2_P 50 +#define SRST_I2C3_P 51 +#define SRST_EFUSE_SE_P 52 +#define SRST_EFUSE_NS_P 53 +#define SRST_PWM0 54 +#define SRST_PWM0_P 55 +#define SRST_DMA 56 +#define SRST_TSP_A 57 +#define SRST_TSP_H 58 +#define SRST_TSP 59 +#define SRST_TSP_HSADC 60 +#define SRST_DCF_A 61 +#define SRST_DCF_P 62 + +#define SRST_SCR 64 +#define SRST_SPI 65 +#define SRST_TSADC 66 +#define SRST_TSADC_P 67 +#define SRST_CRYPTO 68 +#define SRST_SGRF 69 +#define SRST_GRF 70 +#define SRST_USB_GRF 71 +#define SRST_TIMER_6CH_P 72 +#define SRST_TIMER0 73 +#define SRST_TIMER1 74 +#define SRST_TIMER2 75 +#define SRST_TIMER3 76 +#define SRST_TIMER4 77 +#define SRST_TIMER5 78 +#define SRST_USB3GRF 79 + +#define SRST_PHYNIU 80 +#define SRST_HDMIPHY 81 +#define SRST_VDAC 82 +#define SRST_ACODEC_p 83 +#define SRST_SARADC 85 +#define SRST_SARADC_P 86 +#define SRST_GRF_DDR 87 +#define SRST_DFIMON 88 +#define SRST_MSCH 89 +#define SRST_DDRMSCH 91 +#define SRST_DDRCTRL 92 +#define SRST_DDRCTRL_P 93 +#define SRST_DDRPHY 94 +#define SRST_DDRPHY_P 95 + +#define SRST_GMAC_NIU_A 96 +#define SRST_GMAC_NIU_P 97 +#define SRST_GMAC2PHY_A 98 +#define SRST_GMAC2IO_A 99 +#define SRST_MACPHY 100 +#define SRST_OTP_PHY 101 +#define SRST_GPU_A 102 +#define SRST_GPU_NIU_A 103 +#define SRST_SDMMCEXT 104 +#define SRST_PERIPH_NIU_A 105 +#define SRST_PERIHP_NIU_H 106 +#define SRST_PERIHP_P 107 +#define SRST_PERIPHSYS_H 108 +#define SRST_MMC0 109 +#define SRST_SDIO 110 +#define SRST_EMMC 111 + +#define SRST_USB2OTG_H 112 +#define SRST_USB2OTG 113 +#define SRST_USB2OTG_ADP 114 +#define SRST_USB2HOST_H 115 +#define SRST_USB2HOST_ARB 116 +#define SRST_USB2HOST_AUX 117 +#define SRST_USB2HOST_EHCIPHY 118 +#define SRST_USB2HOST_UTMI 119 +#define SRST_USB3OTG 120 +#define SRST_USBPOR 121 +#define SRST_USB2OTG_UTMI 122 +#define SRST_USB2HOST_PHY_UTMI 123 +#define SRST_USB3OTG_UTMI 124 +#define SRST_USB3PHY_U2 125 +#define SRST_USB3PHY_U3 126 +#define SRST_USB3PHY_PIPE 127 + +#define SRST_VIO_A 128 +#define SRST_VIO_BUS_H 129 +#define SRST_VIO_H2P_H 130 +#define SRST_VIO_ARBI_H 131 +#define SRST_VOP_NIU_A 132 +#define SRST_VOP_A 133 +#define SRST_VOP_H 134 +#define SRST_VOP_D 135 +#define SRST_RGA 136 +#define SRST_RGA_NIU_A 137 +#define SRST_RGA_A 138 +#define SRST_RGA_H 139 +#define SRST_IEP_A 140 +#define SRST_IEP_H 141 +#define SRST_HDMI 142 +#define SRST_HDMI_P 143 + +#define SRST_HDCP_A 144 +#define SRST_HDCP 145 +#define SRST_HDCP_H 146 +#define SRST_CIF_A 147 +#define SRST_CIF_H 148 +#define SRST_CIF_P 149 +#define SRST_OTP_P 150 +#define SRST_OTP_SBPI 151 +#define SRST_OTP_USER 152 +#define SRST_DDRCTRL_A 153 +#define SRST_DDRSTDY_P 154 +#define SRST_DDRSTDY 155 +#define SRST_PDM_H 156 +#define SRST_PDM 157 +#define SRST_USB3PHY_OTG_P 158 +#define SRST_USB3PHY_PIPE_P 159 + +#define SRST_VCODEC_A 160 +#define SRST_VCODEC_NIU_A 161 +#define SRST_VCODEC_H 162 +#define SRST_VCODEC_NIU_H 163 +#define SRST_VDEC_A 164 +#define SRST_VDEC_NIU_A 165 +#define SRST_VDEC_H 166 +#define SRST_VDEC_NIU_H 167 +#define SRST_VDEC_CORE 168 +#define SRST_VDEC_CABAC 169 +#define SRST_DDRPHYDIV 175 + +#define SRST_RKVENC_NIU_A 176 +#define SRST_RKVENC_NIU_H 177 +#define SRST_RKVENC_H265_A 178 +#define SRST_RKVENC_H265_P 179 +#define SRST_RKVENC_H265_CORE 180 +#define SRST_RKVENC_H265_DSP 181 +#define SRST_RKVENC_H264_A 182 +#define SRST_RKVENC_H264_H 183 +#define SRST_RKVENC_INTMEM 184 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/rk3368-cru.h b/roms/u-boot/include/dt-bindings/clock/rk3368-cru.h new file mode 100644 index 000000000..0a06c5f51 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/rk3368-cru.h @@ -0,0 +1,381 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2015 Heiko Stuebner + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H + +/* core clocks */ +#define PLL_APLLB 1 +#define PLL_APLLL 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define ARMCLKB 7 +#define ARMCLKL 8 + +/* sclk gates (special clocks) */ +#define SCLK_GPU_CORE 64 +#define SCLK_SPI0 65 +#define SCLK_SPI1 66 +#define SCLK_SPI2 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO0 69 +#define SCLK_EMMC 71 +#define SCLK_TSADC 72 +#define SCLK_SARADC 73 +#define SCLK_NANDC0 75 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_UART3 80 +#define SCLK_UART4 81 +#define SCLK_I2S_8CH 82 +#define SCLK_SPDIF_8CH 83 +#define SCLK_I2S_2CH 84 +#define SCLK_TIMER00 85 +#define SCLK_TIMER01 86 +#define SCLK_TIMER02 87 +#define SCLK_TIMER03 88 +#define SCLK_TIMER04 89 +#define SCLK_TIMER05 90 +#define SCLK_OTGPHY0 93 +#define SCLK_OTG_ADP 96 +#define SCLK_HSICPHY480M 97 +#define SCLK_HSICPHY12M 98 +#define SCLK_MACREF 99 +#define SCLK_VOP0_PWM 100 +#define SCLK_MAC_RX 102 +#define SCLK_MAC_TX 103 +#define SCLK_EDP_24M 104 +#define SCLK_EDP 105 +#define SCLK_RGA 106 +#define SCLK_ISP 107 +#define SCLK_HDCP 108 +#define SCLK_HDMI_HDCP 109 +#define SCLK_HDMI_CEC 110 +#define SCLK_HEVC_CABAC 111 +#define SCLK_HEVC_CORE 112 +#define SCLK_I2S_8CH_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO0_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO0_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_USBPHY480M 122 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_PMU 125 +#define SCLK_SFC 126 +#define SCLK_MAC 127 +#define SCLK_MACREF_OUT 128 +#define SCLK_TIMER10 133 +#define SCLK_TIMER11 134 +#define SCLK_TIMER12 135 +#define SCLK_TIMER13 136 +#define SCLK_TIMER14 137 +#define SCLK_TIMER15 138 + +#define DCLK_VOP 190 +#define MCLK_CRYPTO 191 + +/* aclk gates */ +#define ACLK_GPU_MEM 192 +#define ACLK_GPU_CFG 193 +#define ACLK_DMAC_BUS 194 +#define ACLK_DMAC_PERI 195 +#define ACLK_PERI_MMU 196 +#define ACLK_GMAC 197 +#define ACLK_VOP 198 +#define ACLK_VOP_IEP 199 +#define ACLK_RGA 200 +#define ACLK_HDCP 201 +#define ACLK_IEP 202 +#define ACLK_VIO0_NOC 203 +#define ACLK_VIP 204 +#define ACLK_ISP 205 +#define ACLK_VIO1_NOC 206 +#define ACLK_VIDEO 208 +#define ACLK_BUS 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_PMUGRF 324 +#define PCLK_MAILBOX 325 +#define PCLK_GRF 329 +#define PCLK_SGRF 330 +#define PCLK_PMU 331 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_I2C4 336 +#define PCLK_I2C5 337 +#define PCLK_SPI0 338 +#define PCLK_SPI1 339 +#define PCLK_SPI2 340 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_UART3 344 +#define PCLK_UART4 345 +#define PCLK_TSADC 346 +#define PCLK_SARADC 347 +#define PCLK_SIM 348 +#define PCLK_GMAC 349 +#define PCLK_PWM0 350 +#define PCLK_PWM1 351 +#define PCLK_TIMER0 353 +#define PCLK_TIMER1 354 +#define PCLK_EDP_CTRL 355 +#define PCLK_MIPI_DSI0 356 +#define PCLK_MIPI_CSI 358 +#define PCLK_HDCP 359 +#define PCLK_HDMI_CTRL 360 +#define PCLK_VIO_H2P 361 +#define PCLK_BUS 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_DDRPHY 365 +#define PCLK_ISP 366 +#define PCLK_VIP 367 +#define PCLK_WDT 368 +#define PCLK_EFUSE256 369 + +/* hclk gates */ +#define HCLK_SFC 448 +#define HCLK_OTG0 449 +#define HCLK_HOST0 450 +#define HCLK_HOST1 451 +#define HCLK_HSIC 452 +#define HCLK_NANDC0 453 +#define HCLK_TSP 455 +#define HCLK_SDMMC 456 +#define HCLK_SDIO0 457 +#define HCLK_EMMC 459 +#define HCLK_HSADC 460 +#define HCLK_CRYPTO 461 +#define HCLK_I2S_2CH 462 +#define HCLK_I2S_8CH 463 +#define HCLK_SPDIF 464 +#define HCLK_VOP 465 +#define HCLK_ROM 467 +#define HCLK_IEP 468 +#define HCLK_ISP 469 +#define HCLK_RGA 470 +#define HCLK_VIO_AHB_ARBI 471 +#define HCLK_VIO_NOC 472 +#define HCLK_VIP 473 +#define HCLK_VIO_H2P 474 +#define HCLK_VIO_HDCPMMU 475 +#define HCLK_VIDEO 476 +#define HCLK_BUS 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE_B0 0 +#define SRST_CORE_B1 1 +#define SRST_CORE_B2 2 +#define SRST_CORE_B3 3 +#define SRST_CORE_B0_PO 4 +#define SRST_CORE_B1_PO 5 +#define SRST_CORE_B2_PO 6 +#define SRST_CORE_B3_PO 7 +#define SRST_L2_B 8 +#define SRST_ADB_B 9 +#define SRST_PD_CORE_B_NIU 10 +#define SRST_PDBUS_STRSYS 11 +#define SRST_SOCDBG_B 14 +#define SRST_CORE_B_DBG 15 + +#define SRST_DMAC1 18 +#define SRST_INTMEM 19 +#define SRST_ROM 20 +#define SRST_SPDIF8CH 21 +#define SRST_I2S8CH 23 +#define SRST_MAILBOX 24 +#define SRST_I2S2CH 25 +#define SRST_EFUSE_256 26 +#define SRST_MCU_SYS 28 +#define SRST_MCU_PO 29 +#define SRST_MCU_NOC 30 +#define SRST_EFUSE 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_GPIO4 36 +#define SRST_PMUGRF 41 +#define SRST_I2C0 42 +#define SRST_I2C1 43 +#define SRST_I2C2 44 +#define SRST_I2C3 45 +#define SRST_I2C4 46 +#define SRST_I2C5 47 + +#define SRST_DWPWM 48 +#define SRST_MMC_PERI 49 +#define SRST_PERIPH_MMU 50 +#define SRST_GRF 55 +#define SRST_PMU 56 +#define SRST_PERIPH_AXI 57 +#define SRST_PERIPH_AHB 58 +#define SRST_PERIPH_APB 59 +#define SRST_PERIPH_NIU 60 +#define SRST_PDPERI_AHB_ARBI 61 +#define SRST_EMEM 62 +#define SRST_USB_PERI 63 + +#define SRST_DMAC2 64 +#define SRST_MAC 66 +#define SRST_GPS 67 +#define SRST_RKPWM 69 +#define SRST_USBHOST0 72 +#define SRST_HSIC 73 +#define SRST_HSIC_AUX 74 +#define SRST_HSIC_PHY 75 +#define SRST_HSADC 76 +#define SRST_NANDC0 77 +#define SRST_SFC 79 + +#define SRST_SPI0 83 +#define SRST_SPI1 84 +#define SRST_SPI2 85 +#define SRST_SARADC 87 +#define SRST_PDALIVE_NIU 88 +#define SRST_PDPMU_INTMEM 89 +#define SRST_PDPMU_NIU 90 +#define SRST_SGRF 91 + +#define SRST_VIO_ARBI 96 +#define SRST_RGA_NIU 97 +#define SRST_VIO0_NIU_AXI 98 +#define SRST_VIO_NIU_AHB 99 +#define SRST_LCDC0_AXI 100 +#define SRST_LCDC0_AHB 101 +#define SRST_LCDC0_DCLK 102 +#define SRST_VIP 104 +#define SRST_RGA_CORE 105 +#define SRST_IEP_AXI 106 +#define SRST_IEP_AHB 107 +#define SRST_RGA_AXI 108 +#define SRST_RGA_AHB 109 +#define SRST_ISP 110 +#define SRST_EDP_24M 111 + +#define SRST_VIDEO_AXI 112 +#define SRST_VIDEO_AHB 113 +#define SRST_MIPIDPHYTX 114 +#define SRST_MIPIDSI0 115 +#define SRST_MIPIDPHYRX 116 +#define SRST_MIPICSI 117 +#define SRST_GPU 120 +#define SRST_HDMI 121 +#define SRST_EDP 122 +#define SRST_PMU_PVTM 123 +#define SRST_CORE_PVTM 124 +#define SRST_GPU_PVTM 125 +#define SRST_GPU_SYS 126 +#define SRST_GPU_MEM_NIU 127 + +#define SRST_MMC0 128 +#define SRST_SDIO0 129 +#define SRST_EMMC 131 +#define SRST_USBOTG_AHB 132 +#define SRST_USBOTG_PHY 133 +#define SRST_USBOTG_CON 134 +#define SRST_USBHOST0_AHB 135 +#define SRST_USBHOST0_PHY 136 +#define SRST_USBHOST0_CON 137 +#define SRST_USBOTG_UTMI 138 +#define SRST_USBHOST1_UTMI 139 +#define SRST_USB_ADP 141 + +#define SRST_CORESIGHT 144 +#define SRST_PD_CORE_AHB_NOC 145 +#define SRST_PD_CORE_APB_NOC 146 +#define SRST_GIC 148 +#define SRST_LCDC_PWM0 149 +#define SRST_RGA_H2P_BRG 153 +#define SRST_VIDEO 154 +#define SRST_GPU_CFG_NIU 157 +#define SRST_TSADC 159 + +#define SRST_DDRPHY0 160 +#define SRST_DDRPHY0_APB 161 +#define SRST_DDRCTRL0 162 +#define SRST_DDRCTRL0_APB 163 +#define SRST_VIDEO_NIU 165 +#define SRST_VIDEO_NIU_AHB 167 +#define SRST_DDRMSCH0 170 +#define SRST_PDBUS_AHB 173 +#define SRST_CRYPTO 174 + +#define SRST_UART0 179 +#define SRST_UART1 180 +#define SRST_UART2 181 +#define SRST_UART3 182 +#define SRST_UART4 183 +#define SRST_SIMC 186 +#define SRST_TSP 188 +#define SRST_TSP_CLKIN0 189 + +#define SRST_CORE_L0 192 +#define SRST_CORE_L1 193 +#define SRST_CORE_L2 194 +#define SRST_CORE_L3 195 +#define SRST_CORE_L0_PO 195 +#define SRST_CORE_L1_PO 197 +#define SRST_CORE_L2_PO 198 +#define SRST_CORE_L3_PO 199 +#define SRST_L2_L 200 +#define SRST_ADB_L 201 +#define SRST_PD_CORE_L_NIU 202 +#define SRST_CCI_SYS 203 +#define SRST_CCI_DDR 204 +#define SRST_CCI 205 +#define SRST_SOCDBG_L 206 +#define SRST_CORE_L_DBG 207 + +#define SRST_CORE_B0_NC 208 +#define SRST_CORE_B0_PO_NC 209 +#define SRST_L2_B_NC 210 +#define SRST_ADB_B_NC 211 +#define SRST_PD_CORE_B_NIU_NC 212 +#define SRST_PDBUS_STRSYS_NC 213 +#define SRST_CORE_L0_NC 214 +#define SRST_CORE_L0_PO_NC 215 +#define SRST_L2_L_NC 216 +#define SRST_ADB_L_NC 217 +#define SRST_PD_CORE_L_NIU_NC 218 +#define SRST_CCI_SYS_NC 219 +#define SRST_CCI_DDR_NC 220 +#define SRST_CCI_NC 221 +#define SRST_TRACE_NC 222 + +#define SRST_TIMER00 224 +#define SRST_TIMER01 225 +#define SRST_TIMER02 226 +#define SRST_TIMER03 227 +#define SRST_TIMER04 228 +#define SRST_TIMER05 229 +#define SRST_TIMER10 230 +#define SRST_TIMER11 231 +#define SRST_TIMER12 232 +#define SRST_TIMER13 233 +#define SRST_TIMER14 234 +#define SRST_TIMER15 235 +#define SRST_TIMER0_APB 236 +#define SRST_TIMER1_APB 237 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/rk3399-cru.h b/roms/u-boot/include/dt-bindings/clock/rk3399-cru.h new file mode 100644 index 000000000..211faf8fa --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/rk3399-cru.h @@ -0,0 +1,749 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H + +/* core clocks */ +#define PLL_APLLL 1 +#define PLL_APLLB 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define PLL_VPLL 7 +#define ARMCLKL 8 +#define ARMCLKB 9 + +/* sclk gates (special clocks) */ +#define SCLK_I2C1 65 +#define SCLK_I2C2 66 +#define SCLK_I2C3 67 +#define SCLK_I2C5 68 +#define SCLK_I2C6 69 +#define SCLK_I2C7 70 +#define SCLK_SPI0 71 +#define SCLK_SPI1 72 +#define SCLK_SPI2 73 +#define SCLK_SPI4 74 +#define SCLK_SPI5 75 +#define SCLK_SDMMC 76 +#define SCLK_SDIO 77 +#define SCLK_EMMC 78 +#define SCLK_TSADC 79 +#define SCLK_SARADC 80 +#define SCLK_UART0 81 +#define SCLK_UART1 82 +#define SCLK_UART2 83 +#define SCLK_UART3 84 +#define SCLK_SPDIF_8CH 85 +#define SCLK_I2S0_8CH 86 +#define SCLK_I2S1_8CH 87 +#define SCLK_I2S2_8CH 88 +#define SCLK_I2S_8CH_OUT 89 +#define SCLK_TIMER00 90 +#define SCLK_TIMER01 91 +#define SCLK_TIMER02 92 +#define SCLK_TIMER03 93 +#define SCLK_TIMER04 94 +#define SCLK_TIMER05 95 +#define SCLK_TIMER06 96 +#define SCLK_TIMER07 97 +#define SCLK_TIMER08 98 +#define SCLK_TIMER09 99 +#define SCLK_TIMER10 100 +#define SCLK_TIMER11 101 +#define SCLK_MACREF 102 +#define SCLK_MAC_RX 103 +#define SCLK_MAC_TX 104 +#define SCLK_MAC 105 +#define SCLK_MACREF_OUT 106 +#define SCLK_VOP0_PWM 107 +#define SCLK_VOP1_PWM 108 +#define SCLK_RGA_CORE 109 +#define SCLK_ISP0 110 +#define SCLK_ISP1 111 +#define SCLK_HDMI_CEC 112 +#define SCLK_HDMI_SFR 113 +#define SCLK_DP_CORE 114 +#define SCLK_PVTM_CORE_L 115 +#define SCLK_PVTM_CORE_B 116 +#define SCLK_PVTM_GPU 117 +#define SCLK_PVTM_DDR 118 +#define SCLK_MIPIDPHY_REF 119 +#define SCLK_MIPIDPHY_CFG 120 +#define SCLK_HSICPHY 121 +#define SCLK_USBPHY480M 122 +#define SCLK_USB2PHY0_REF 123 +#define SCLK_USB2PHY1_REF 124 +#define SCLK_UPHY0_TCPDPHY_REF 125 +#define SCLK_UPHY0_TCPDCORE 126 +#define SCLK_UPHY1_TCPDPHY_REF 127 +#define SCLK_UPHY1_TCPDCORE 128 +#define SCLK_USB3OTG0_REF 129 +#define SCLK_USB3OTG1_REF 130 +#define SCLK_USB3OTG0_SUSPEND 131 +#define SCLK_USB3OTG1_SUSPEND 132 +#define SCLK_CRYPTO0 133 +#define SCLK_CRYPTO1 134 +#define SCLK_CCI_TRACE 135 +#define SCLK_CS 136 +#define SCLK_CIF_OUT 137 +#define SCLK_PCIEPHY_REF 138 +#define SCLK_PCIE_CORE 139 +#define SCLK_M0_PERILP 140 +#define SCLK_M0_PERILP_DEC 141 +#define SCLK_CM0S 142 +#define SCLK_DBG_NOC 143 +#define SCLK_DBG_PD_CORE_B 144 +#define SCLK_DBG_PD_CORE_L 145 +#define SCLK_DFIMON0_TIMER 146 +#define SCLK_DFIMON1_TIMER 147 +#define SCLK_INTMEM0 148 +#define SCLK_INTMEM1 149 +#define SCLK_INTMEM2 150 +#define SCLK_INTMEM3 151 +#define SCLK_INTMEM4 152 +#define SCLK_INTMEM5 153 +#define SCLK_SDMMC_DRV 154 +#define SCLK_SDMMC_SAMPLE 155 +#define SCLK_SDIO_DRV 156 +#define SCLK_SDIO_SAMPLE 157 +#define SCLK_VDU_CORE 158 +#define SCLK_VDU_CA 159 +#define SCLK_PCIE_PM 160 +#define SCLK_SPDIF_REC_DPTX 161 +#define SCLK_DPHY_PLL 162 +#define SCLK_DPHY_TX0_CFG 163 +#define SCLK_DPHY_TX1RX1_CFG 164 +#define SCLK_DPHY_RX0_CFG 165 +#define SCLK_RMII_SRC 166 +#define SCLK_PCIEPHY_REF100M 167 +#define SCLK_USBPHY0_480M_SRC 168 +#define SCLK_USBPHY1_480M_SRC 169 +#define SCLK_DDRCLK 170 +#define SCLK_TESTOUT2 171 + +#define DCLK_VOP0 180 +#define DCLK_VOP1 181 +#define DCLK_VOP0_DIV 182 +#define DCLK_VOP1_DIV 183 +#define DCLK_M0_PERILP 184 + +#define FCLK_CM0S 190 + +/* aclk gates */ +#define ACLK_PERIHP 192 +#define ACLK_PERIHP_NOC 193 +#define ACLK_PERILP0 194 +#define ACLK_PERILP0_NOC 195 +#define ACLK_PERF_PCIE 196 +#define ACLK_PCIE 197 +#define ACLK_INTMEM 198 +#define ACLK_TZMA 199 +#define ACLK_DCF 200 +#define ACLK_CCI 201 +#define ACLK_CCI_NOC0 202 +#define ACLK_CCI_NOC1 203 +#define ACLK_CCI_GRF 204 +#define ACLK_CENTER 205 +#define ACLK_CENTER_MAIN_NOC 206 +#define ACLK_CENTER_PERI_NOC 207 +#define ACLK_GPU 208 +#define ACLK_PERF_GPU 209 +#define ACLK_GPU_GRF 210 +#define ACLK_DMAC0_PERILP 211 +#define ACLK_DMAC1_PERILP 212 +#define ACLK_GMAC 213 +#define ACLK_GMAC_NOC 214 +#define ACLK_PERF_GMAC 215 +#define ACLK_VOP0_NOC 216 +#define ACLK_VOP0 217 +#define ACLK_VOP1_NOC 218 +#define ACLK_VOP1 219 +#define ACLK_RGA 220 +#define ACLK_RGA_NOC 221 +#define ACLK_HDCP 222 +#define ACLK_HDCP_NOC 223 +#define ACLK_HDCP22 224 +#define ACLK_IEP 225 +#define ACLK_IEP_NOC 226 +#define ACLK_VIO 227 +#define ACLK_VIO_NOC 228 +#define ACLK_ISP0 229 +#define ACLK_ISP1 230 +#define ACLK_ISP0_NOC 231 +#define ACLK_ISP1_NOC 232 +#define ACLK_ISP0_WRAPPER 233 +#define ACLK_ISP1_WRAPPER 234 +#define ACLK_VCODEC 235 +#define ACLK_VCODEC_NOC 236 +#define ACLK_VDU 237 +#define ACLK_VDU_NOC 238 +#define ACLK_PERI 239 +#define ACLK_EMMC 240 +#define ACLK_EMMC_CORE 241 +#define ACLK_EMMC_NOC 242 +#define ACLK_EMMC_GRF 243 +#define ACLK_USB3 244 +#define ACLK_USB3_NOC 245 +#define ACLK_USB3OTG0 246 +#define ACLK_USB3OTG1 247 +#define ACLK_USB3_RKSOC_AXI_PERF 248 +#define ACLK_USB3_GRF 249 +#define ACLK_GIC 250 +#define ACLK_GIC_NOC 251 +#define ACLK_GIC_ADB400_CORE_L_2_GIC 252 +#define ACLK_GIC_ADB400_CORE_B_2_GIC 253 +#define ACLK_GIC_ADB400_GIC_2_CORE_L 254 +#define ACLK_GIC_ADB400_GIC_2_CORE_B 255 +#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 +#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 +#define ACLK_ADB400M_PD_CORE_L 258 +#define ACLK_ADB400M_PD_CORE_B 259 +#define ACLK_PERF_CORE_L 260 +#define ACLK_PERF_CORE_B 261 +#define ACLK_GIC_PRE 262 +#define ACLK_VOP0_PRE 263 +#define ACLK_VOP1_PRE 264 + +/* pclk gates */ +#define PCLK_PERIHP 320 +#define PCLK_PERIHP_NOC 321 +#define PCLK_PERILP0 322 +#define PCLK_PERILP1 323 +#define PCLK_PERILP1_NOC 324 +#define PCLK_PERILP_SGRF 325 +#define PCLK_PERIHP_GRF 326 +#define PCLK_PCIE 327 +#define PCLK_SGRF 328 +#define PCLK_INTR_ARB 329 +#define PCLK_CENTER_MAIN_NOC 330 +#define PCLK_CIC 331 +#define PCLK_COREDBG_B 332 +#define PCLK_COREDBG_L 333 +#define PCLK_DBG_CXCS_PD_CORE_B 334 +#define PCLK_DCF 335 +#define PCLK_GPIO2 336 +#define PCLK_GPIO3 337 +#define PCLK_GPIO4 338 +#define PCLK_GRF 339 +#define PCLK_HSICPHY 340 +#define PCLK_I2C1 341 +#define PCLK_I2C2 342 +#define PCLK_I2C3 343 +#define PCLK_I2C5 344 +#define PCLK_I2C6 345 +#define PCLK_I2C7 346 +#define PCLK_SPI0 347 +#define PCLK_SPI1 348 +#define PCLK_SPI2 349 +#define PCLK_SPI4 350 +#define PCLK_SPI5 351 +#define PCLK_UART0 352 +#define PCLK_UART1 353 +#define PCLK_UART2 354 +#define PCLK_UART3 355 +#define PCLK_TSADC 356 +#define PCLK_SARADC 357 +#define PCLK_GMAC 358 +#define PCLK_GMAC_NOC 359 +#define PCLK_TIMER0 360 +#define PCLK_TIMER1 361 +#define PCLK_EDP 362 +#define PCLK_EDP_NOC 363 +#define PCLK_EDP_CTRL 364 +#define PCLK_VIO 365 +#define PCLK_VIO_NOC 366 +#define PCLK_VIO_GRF 367 +#define PCLK_MIPI_DSI0 368 +#define PCLK_MIPI_DSI1 369 +#define PCLK_HDCP 370 +#define PCLK_HDCP_NOC 371 +#define PCLK_HDMI_CTRL 372 +#define PCLK_DP_CTRL 373 +#define PCLK_HDCP22 374 +#define PCLK_GASKET 375 +#define PCLK_DDR 376 +#define PCLK_DDR_MON 377 +#define PCLK_DDR_SGRF 378 +#define PCLK_ISP1_WRAPPER 379 +#define PCLK_WDT 380 +#define PCLK_EFUSE1024NS 381 +#define PCLK_EFUSE1024S 382 +#define PCLK_PMU_INTR_ARB 383 +#define PCLK_MAILBOX0 384 +#define PCLK_USBPHY_MUX_G 385 +#define PCLK_UPHY0_TCPHY_G 386 +#define PCLK_UPHY0_TCPD_G 387 +#define PCLK_UPHY1_TCPHY_G 388 +#define PCLK_UPHY1_TCPD_G 389 +#define PCLK_ALIVE 390 + +/* hclk gates */ +#define HCLK_PERIHP 448 +#define HCLK_PERILP0 449 +#define HCLK_PERILP1 450 +#define HCLK_PERILP0_NOC 451 +#define HCLK_PERILP1_NOC 452 +#define HCLK_M0_PERILP 453 +#define HCLK_M0_PERILP_NOC 454 +#define HCLK_AHB1TOM 455 +#define HCLK_HOST0 456 +#define HCLK_HOST0_ARB 457 +#define HCLK_HOST1 458 +#define HCLK_HOST1_ARB 459 +#define HCLK_HSIC 460 +#define HCLK_SD 461 +#define HCLK_SDMMC 462 +#define HCLK_SDMMC_NOC 463 +#define HCLK_M_CRYPTO0 464 +#define HCLK_M_CRYPTO1 465 +#define HCLK_S_CRYPTO0 466 +#define HCLK_S_CRYPTO1 467 +#define HCLK_I2S0_8CH 468 +#define HCLK_I2S1_8CH 469 +#define HCLK_I2S2_8CH 470 +#define HCLK_SPDIF 471 +#define HCLK_VOP0_NOC 472 +#define HCLK_VOP0 473 +#define HCLK_VOP1_NOC 474 +#define HCLK_VOP1 475 +#define HCLK_ROM 476 +#define HCLK_IEP 477 +#define HCLK_IEP_NOC 478 +#define HCLK_ISP0 479 +#define HCLK_ISP1 480 +#define HCLK_ISP0_NOC 481 +#define HCLK_ISP1_NOC 482 +#define HCLK_ISP0_WRAPPER 483 +#define HCLK_ISP1_WRAPPER 484 +#define HCLK_RGA 485 +#define HCLK_RGA_NOC 486 +#define HCLK_HDCP 487 +#define HCLK_HDCP_NOC 488 +#define HCLK_HDCP22 489 +#define HCLK_VCODEC 490 +#define HCLK_VCODEC_NOC 491 +#define HCLK_VDU 492 +#define HCLK_VDU_NOC 493 +#define HCLK_SDIO 494 +#define HCLK_SDIO_NOC 495 +#define HCLK_SDIOAUDIO_NOC 496 + +#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) + +/* pmu-clocks indices */ + +#define PLL_PPLL 1 + +#define SCLK_32K_SUSPEND_PMU 2 +#define SCLK_SPI3_PMU 3 +#define SCLK_TIMER12_PMU 4 +#define SCLK_TIMER13_PMU 5 +#define SCLK_UART4_PMU 6 +#define SCLK_PVTM_PMU 7 +#define SCLK_WIFI_PMU 8 +#define SCLK_I2C0_PMU 9 +#define SCLK_I2C4_PMU 10 +#define SCLK_I2C8_PMU 11 + +#define PCLK_SRC_PMU 19 +#define PCLK_PMU 20 +#define PCLK_PMUGRF_PMU 21 +#define PCLK_INTMEM1_PMU 22 +#define PCLK_GPIO0_PMU 23 +#define PCLK_GPIO1_PMU 24 +#define PCLK_SGRF_PMU 25 +#define PCLK_NOC_PMU 26 +#define PCLK_I2C0_PMU 27 +#define PCLK_I2C4_PMU 28 +#define PCLK_I2C8_PMU 29 +#define PCLK_RKPWM_PMU 30 +#define PCLK_SPI3_PMU 31 +#define PCLK_TIMER_PMU 32 +#define PCLK_MAILBOX_PMU 33 +#define PCLK_UART4_PMU 34 +#define PCLK_WDT_M0_PMU 35 + +#define FCLK_CM0S_SRC_PMU 44 +#define FCLK_CM0S_PMU 45 +#define SCLK_CM0S_PMU 46 +#define HCLK_CM0S_PMU 47 +#define DCLK_CM0S_PMU 48 +#define PCLK_INTR_ARB_PMU 49 +#define HCLK_NOC_PMU 50 + +#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE_L0 0 +#define SRST_CORE_B0 1 +#define SRST_CORE_PO_L0 2 +#define SRST_CORE_PO_B0 3 +#define SRST_L2_L 4 +#define SRST_L2_B 5 +#define SRST_ADB_L 6 +#define SRST_ADB_B 7 +#define SRST_A_CCI 8 +#define SRST_A_CCIM0_NOC 9 +#define SRST_A_CCIM1_NOC 10 +#define SRST_DBG_NOC 11 + +/* cru_softrst_con1 */ +#define SRST_CORE_L0_T 16 +#define SRST_CORE_L1 17 +#define SRST_CORE_L2 18 +#define SRST_CORE_L3 19 +#define SRST_CORE_PO_L0_T 20 +#define SRST_CORE_PO_L1 21 +#define SRST_CORE_PO_L2 22 +#define SRST_CORE_PO_L3 23 +#define SRST_A_ADB400_GIC2COREL 24 +#define SRST_A_ADB400_COREL2GIC 25 +#define SRST_P_DBG_L 26 +#define SRST_L2_L_T 28 +#define SRST_ADB_L_T 29 +#define SRST_A_RKPERF_L 30 +#define SRST_PVTM_CORE_L 31 + +/* cru_softrst_con2 */ +#define SRST_CORE_B0_T 32 +#define SRST_CORE_B1 33 +#define SRST_CORE_PO_B0_T 36 +#define SRST_CORE_PO_B1 37 +#define SRST_A_ADB400_GIC2COREB 40 +#define SRST_A_ADB400_COREB2GIC 41 +#define SRST_P_DBG_B 42 +#define SRST_L2_B_T 43 +#define SRST_ADB_B_T 45 +#define SRST_A_RKPERF_B 46 +#define SRST_PVTM_CORE_B 47 + +/* cru_softrst_con3 */ +#define SRST_A_CCI_T 50 +#define SRST_A_CCIM0_NOC_T 51 +#define SRST_A_CCIM1_NOC_T 52 +#define SRST_A_ADB400M_PD_CORE_B_T 53 +#define SRST_A_ADB400M_PD_CORE_L_T 54 +#define SRST_DBG_NOC_T 55 +#define SRST_DBG_CXCS 56 +#define SRST_CCI_TRACE 57 +#define SRST_P_CCI_GRF 58 + +/* cru_softrst_con4 */ +#define SRST_A_CENTER_MAIN_NOC 64 +#define SRST_A_CENTER_PERI_NOC 65 +#define SRST_P_CENTER_MAIN 66 +#define SRST_P_DDRMON 67 +#define SRST_P_CIC 68 +#define SRST_P_CENTER_SGRF 69 +#define SRST_DDR0_MSCH 70 +#define SRST_DDRCFG0_MSCH 71 +#define SRST_DDR0 72 +#define SRST_DDRPHY0 73 +#define SRST_DDR1_MSCH 74 +#define SRST_DDRCFG1_MSCH 75 +#define SRST_DDR1 76 +#define SRST_DDRPHY1 77 +#define SRST_DDR_CIC 78 +#define SRST_PVTM_DDR 79 + +/* cru_softrst_con5 */ +#define SRST_A_VCODEC_NOC 80 +#define SRST_A_VCODEC 81 +#define SRST_H_VCODEC_NOC 82 +#define SRST_H_VCODEC 83 +#define SRST_A_VDU_NOC 88 +#define SRST_A_VDU 89 +#define SRST_H_VDU_NOC 90 +#define SRST_H_VDU 91 +#define SRST_VDU_CORE 92 +#define SRST_VDU_CA 93 + +/* cru_softrst_con6 */ +#define SRST_A_IEP_NOC 96 +#define SRST_A_VOP_IEP 97 +#define SRST_A_IEP 98 +#define SRST_H_IEP_NOC 99 +#define SRST_H_IEP 100 +#define SRST_A_RGA_NOC 102 +#define SRST_A_RGA 103 +#define SRST_H_RGA_NOC 104 +#define SRST_H_RGA 105 +#define SRST_RGA_CORE 106 +#define SRST_EMMC_NOC 108 +#define SRST_EMMC 109 +#define SRST_EMMC_GRF 110 + +/* cru_softrst_con7 */ +#define SRST_A_PERIHP_NOC 112 +#define SRST_P_PERIHP_GRF 113 +#define SRST_H_PERIHP_NOC 114 +#define SRST_USBHOST0 115 +#define SRST_HOSTC0_AUX 116 +#define SRST_HOST0_ARB 117 +#define SRST_USBHOST1 118 +#define SRST_HOSTC1_AUX 119 +#define SRST_HOST1_ARB 120 +#define SRST_SDIO0 121 +#define SRST_SDMMC 122 +#define SRST_HSIC 123 +#define SRST_HSIC_AUX 124 +#define SRST_AHB1TOM 125 +#define SRST_P_PERIHP_NOC 126 +#define SRST_HSICPHY 127 + +/* cru_softrst_con8 */ +#define SRST_A_PCIE 128 +#define SRST_P_PCIE 129 +#define SRST_PCIE_CORE 130 +#define SRST_PCIE_MGMT 131 +#define SRST_PCIE_MGMT_STICKY 132 +#define SRST_PCIE_PIPE 133 +#define SRST_PCIE_PM 134 +#define SRST_PCIEPHY 135 +#define SRST_A_GMAC_NOC 136 +#define SRST_A_GMAC 137 +#define SRST_P_GMAC_NOC 138 +#define SRST_P_GMAC_GRF 140 +#define SRST_HSICPHY_POR 142 +#define SRST_HSICPHY_UTMI 143 + +/* cru_softrst_con9 */ +#define SRST_USB2PHY0_POR 144 +#define SRST_USB2PHY0_UTMI_PORT0 145 +#define SRST_USB2PHY0_UTMI_PORT1 146 +#define SRST_USB2PHY0_EHCIPHY 147 +#define SRST_UPHY0_PIPE_L00 148 +#define SRST_UPHY0 149 +#define SRST_UPHY0_TCPDPWRUP 150 +#define SRST_USB2PHY1_POR 152 +#define SRST_USB2PHY1_UTMI_PORT0 153 +#define SRST_USB2PHY1_UTMI_PORT1 154 +#define SRST_USB2PHY1_EHCIPHY 155 +#define SRST_UPHY1_PIPE_L00 156 +#define SRST_UPHY1 157 +#define SRST_UPHY1_TCPDPWRUP 158 + +/* cru_softrst_con10 */ +#define SRST_A_PERILP0_NOC 160 +#define SRST_A_DCF 161 +#define SRST_GIC500 162 +#define SRST_DMAC0_PERILP0 163 +#define SRST_DMAC1_PERILP0 164 +#define SRST_TZMA 165 +#define SRST_INTMEM 166 +#define SRST_ADB400_MST0 167 +#define SRST_ADB400_MST1 168 +#define SRST_ADB400_SLV0 169 +#define SRST_ADB400_SLV1 170 +#define SRST_H_PERILP0 171 +#define SRST_H_PERILP0_NOC 172 +#define SRST_ROM 173 +#define SRST_CRYPTO_S 174 +#define SRST_CRYPTO_M 175 + +/* cru_softrst_con11 */ +#define SRST_P_DCF 176 +#define SRST_CM0S_NOC 177 +#define SRST_CM0S 178 +#define SRST_CM0S_DBG 179 +#define SRST_CM0S_PO 180 +#define SRST_CRYPTO 181 +#define SRST_P_PERILP1_SGRF 182 +#define SRST_P_PERILP1_GRF 183 +#define SRST_CRYPTO1_S 184 +#define SRST_CRYPTO1_M 185 +#define SRST_CRYPTO1 186 +#define SRST_GIC_NOC 188 +#define SRST_SD_NOC 189 +#define SRST_SDIOAUDIO_BRG 190 + +/* cru_softrst_con12 */ +#define SRST_H_PERILP1 192 +#define SRST_H_PERILP1_NOC 193 +#define SRST_H_I2S0_8CH 194 +#define SRST_H_I2S1_8CH 195 +#define SRST_H_I2S2_8CH 196 +#define SRST_H_SPDIF_8CH 197 +#define SRST_P_PERILP1_NOC 198 +#define SRST_P_EFUSE_1024 199 +#define SRST_P_EFUSE_1024S 200 +#define SRST_P_I2C0 201 +#define SRST_P_I2C1 202 +#define SRST_P_I2C2 203 +#define SRST_P_I2C3 204 +#define SRST_P_I2C4 205 +#define SRST_P_I2C5 206 +#define SRST_P_MAILBOX0 207 + +/* cru_softrst_con13 */ +#define SRST_P_UART0 208 +#define SRST_P_UART1 209 +#define SRST_P_UART2 210 +#define SRST_P_UART3 211 +#define SRST_P_SARADC 212 +#define SRST_P_TSADC 213 +#define SRST_P_SPI0 214 +#define SRST_P_SPI1 215 +#define SRST_P_SPI2 216 +#define SRST_P_SPI4 217 +#define SRST_P_SPI5 218 +#define SRST_SPI0 219 +#define SRST_SPI1 220 +#define SRST_SPI2 221 +#define SRST_SPI4 222 +#define SRST_SPI5 223 + +/* cru_softrst_con14 */ +#define SRST_I2S0_8CH 224 +#define SRST_I2S1_8CH 225 +#define SRST_I2S2_8CH 226 +#define SRST_SPDIF_8CH 227 +#define SRST_UART0 228 +#define SRST_UART1 229 +#define SRST_UART2 230 +#define SRST_UART3 231 +#define SRST_TSADC 232 +#define SRST_I2C0 233 +#define SRST_I2C1 234 +#define SRST_I2C2 235 +#define SRST_I2C3 236 +#define SRST_I2C4 237 +#define SRST_I2C5 238 +#define SRST_SDIOAUDIO_NOC 239 + +/* cru_softrst_con15 */ +#define SRST_A_VIO_NOC 240 +#define SRST_A_HDCP_NOC 241 +#define SRST_A_HDCP 242 +#define SRST_H_HDCP_NOC 243 +#define SRST_H_HDCP 244 +#define SRST_P_HDCP_NOC 245 +#define SRST_P_HDCP 246 +#define SRST_P_HDMI_CTRL 247 +#define SRST_P_DP_CTRL 248 +#define SRST_S_DP_CTRL 249 +#define SRST_C_DP_CTRL 250 +#define SRST_P_MIPI_DSI0 251 +#define SRST_P_MIPI_DSI1 252 +#define SRST_DP_CORE 253 +#define SRST_DP_I2S 254 + +/* cru_softrst_con16 */ +#define SRST_GASKET 256 +#define SRST_VIO_GRF 258 +#define SRST_DPTX_SPDIF_REC 259 +#define SRST_HDMI_CTRL 260 +#define SRST_HDCP_CTRL 261 +#define SRST_A_ISP0_NOC 262 +#define SRST_A_ISP1_NOC 263 +#define SRST_H_ISP0_NOC 266 +#define SRST_H_ISP1_NOC 267 +#define SRST_H_ISP0 268 +#define SRST_H_ISP1 269 +#define SRST_ISP0 270 +#define SRST_ISP1 271 + +/* cru_softrst_con17 */ +#define SRST_A_VOP0_NOC 272 +#define SRST_A_VOP1_NOC 273 +#define SRST_A_VOP0 274 +#define SRST_A_VOP1 275 +#define SRST_H_VOP0_NOC 276 +#define SRST_H_VOP1_NOC 277 +#define SRST_H_VOP0 278 +#define SRST_H_VOP1 279 +#define SRST_D_VOP0 280 +#define SRST_D_VOP1 281 +#define SRST_VOP0_PWM 282 +#define SRST_VOP1_PWM 283 +#define SRST_P_EDP_NOC 284 +#define SRST_P_EDP_CTRL 285 + +/* cru_softrst_con18 */ +#define SRST_A_GPU 288 +#define SRST_A_GPU_NOC 289 +#define SRST_A_GPU_GRF 290 +#define SRST_PVTM_GPU 291 +#define SRST_A_USB3_NOC 292 +#define SRST_A_USB3_OTG0 293 +#define SRST_A_USB3_OTG1 294 +#define SRST_A_USB3_GRF 295 +#define SRST_PMU 296 + +/* cru_softrst_con19 */ +#define SRST_P_TIMER0_5 304 +#define SRST_TIMER0 305 +#define SRST_TIMER1 306 +#define SRST_TIMER2 307 +#define SRST_TIMER3 308 +#define SRST_TIMER4 309 +#define SRST_TIMER5 310 +#define SRST_P_TIMER6_11 311 +#define SRST_TIMER6 312 +#define SRST_TIMER7 313 +#define SRST_TIMER8 314 +#define SRST_TIMER9 315 +#define SRST_TIMER10 316 +#define SRST_TIMER11 317 +#define SRST_P_INTR_ARB_PMU 318 +#define SRST_P_ALIVE_SGRF 319 + +/* cru_softrst_con20 */ +#define SRST_P_GPIO2 320 +#define SRST_P_GPIO3 321 +#define SRST_P_GPIO4 322 +#define SRST_P_GRF 323 +#define SRST_P_ALIVE_NOC 324 +#define SRST_P_WDT0 325 +#define SRST_P_WDT1 326 +#define SRST_P_INTR_ARB 327 +#define SRST_P_UPHY0_DPTX 328 +#define SRST_P_UPHY0_APB 330 +#define SRST_P_UPHY0_TCPHY 332 +#define SRST_P_UPHY1_TCPHY 333 +#define SRST_P_UPHY0_TCPDCTRL 334 +#define SRST_P_UPHY1_TCPDCTRL 335 + +/* pmu soft-reset indices */ + +/* pmu_cru_softrst_con0 */ +#define SRST_P_NOC 0 +#define SRST_P_INTMEM 1 +#define SRST_H_CM0S 2 +#define SRST_H_CM0S_NOC 3 +#define SRST_DBG_CM0S 4 +#define SRST_PO_CM0S 5 +#define SRST_P_SPI3 6 +#define SRST_SPI3 7 +#define SRST_P_TIMER_0_1 8 +#define SRST_P_TIMER_0 9 +#define SRST_P_TIMER_1 10 +#define SRST_P_UART4 11 +#define SRST_UART4 12 +#define SRST_P_WDT 13 + +/* pmu_cru_softrst_con1 */ +#define SRST_P_I2C6 16 +#define SRST_P_I2C7 17 +#define SRST_P_I2C8 18 +#define SRST_P_MAILBOX 19 +#define SRST_P_RKPWM 20 +#define SRST_P_PMUGRF 21 +#define SRST_P_SGRF 22 +#define SRST_P_GPIO0 23 +#define SRST_P_GPIO1 24 +#define SRST_P_CRU 25 +#define SRST_P_INTR 26 +#define SRST_PVTM 27 +#define SRST_I2C6 28 +#define SRST_I2C7 29 +#define SRST_I2C8 30 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/rockchip,rk808.h b/roms/u-boot/include/dt-bindings/clock/rockchip,rk808.h new file mode 100644 index 000000000..1a873432f --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/rockchip,rk808.h @@ -0,0 +1,11 @@ +/* + * This header provides constants clk index RK808 pmic clkout + */ +#ifndef _CLK_ROCKCHIP_RK808 +#define _CLK_ROCKCHIP_RK808 + +/* CLOCKOUT index */ +#define RK808_CLKOUT0 0 +#define RK808_CLKOUT1 1 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/rv1108-cru.h b/roms/u-boot/include/dt-bindings/clock/rv1108-cru.h new file mode 100644 index 000000000..10ed9d140 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/rv1108-cru.h @@ -0,0 +1,356 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Shawn Lin + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H + +/* pll id */ +#define PLL_APLL 0 +#define PLL_DPLL 1 +#define PLL_GPLL 2 +#define ARMCLK 3 + +/* sclk gates (special clocks) */ +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_UART0 72 +#define SCLK_UART1 73 +#define SCLK_UART2 74 +#define SCLK_I2S0 75 +#define SCLK_I2S1 76 +#define SCLK_I2S2 77 +#define SCLK_TIMER0 78 +#define SCLK_TIMER1 79 +#define SCLK_SFC 80 +#define SCLK_SDMMC_DRV 81 +#define SCLK_SDIO_DRV 82 +#define SCLK_EMMC_DRV 83 +#define SCLK_SDMMC_SAMPLE 84 +#define SCLK_SDIO_SAMPLE 85 +#define SCLK_EMMC_SAMPLE 86 +#define SCLK_VENC_CORE 87 +#define SCLK_HEVC_CORE 88 +#define SCLK_HEVC_CABAC 89 +#define SCLK_PWM0_PMU 90 +#define SCLK_I2C0_PMU 91 +#define SCLK_WIFI 92 +#define SCLK_CIFOUT 93 +#define SCLK_MIPI_CSI_OUT 94 +#define SCLK_CIF0 95 +#define SCLK_CIF1 96 +#define SCLK_CIF2 97 +#define SCLK_CIF3 98 +#define SCLK_DSP 99 +#define SCLK_DSP_IOP 100 +#define SCLK_DSP_EPP 101 +#define SCLK_DSP_EDP 102 +#define SCLK_DSP_EDAP 103 +#define SCLK_CVBS_HOST 104 +#define SCLK_HDMI_SFR 105 +#define SCLK_HDMI_CEC 106 +#define SCLK_CRYPTO 107 +#define SCLK_SPI 108 +#define SCLK_SARADC 109 +#define SCLK_TSADC 110 +#define SCLK_MAC_PRE 111 +#define SCLK_MAC 112 +#define SCLK_MAC_RX 113 +#define SCLK_MAC_REF 114 +#define SCLK_MAC_REFOUT 115 +#define SCLK_DSP_PFM 116 +#define SCLK_RGA 117 +#define SCLK_I2C1 118 +#define SCLK_I2C2 119 +#define SCLK_I2C3 120 +#define SCLK_PWM 121 +#define SCLK_ISP 122 +#define SCLK_USBPHY 123 +#define SCLK_I2S0_SRC 124 +#define SCLK_I2S1_SRC 125 +#define SCLK_I2S2_SRC 126 +#define SCLK_UART0_SRC 127 +#define SCLK_UART1_SRC 128 +#define SCLK_UART2_SRC 129 +#define SCLK_MAC_TX 130 +#define SCLK_MACREF 131 +#define SCLK_MACREF_OUT 132 + +#define DCLK_VOP_SRC 185 +#define DCLK_HDMIPHY 186 +#define DCLK_VOP 187 + +/* aclk gates */ +#define ACLK_DMAC 192 +#define ACLK_PRE 193 +#define ACLK_CORE 194 +#define ACLK_ENMCORE 195 +#define ACLK_RKVENC 196 +#define ACLK_RKVDEC 197 +#define ACLK_VPU 198 +#define ACLK_CIF0 199 +#define ACLK_VIO0 200 +#define ACLK_VIO1 201 +#define ACLK_VOP 202 +#define ACLK_IEP 203 +#define ACLK_RGA 204 +#define ACLK_ISP 205 +#define ACLK_CIF1 206 +#define ACLK_CIF2 207 +#define ACLK_CIF3 208 +#define ACLK_PERI 209 +#define ACLK_GMAC 210 + +/* pclk gates */ +#define PCLK_GPIO1 256 +#define PCLK_GPIO2 257 +#define PCLK_GPIO3 258 +#define PCLK_GRF 259 +#define PCLK_I2C1 260 +#define PCLK_I2C2 261 +#define PCLK_I2C3 262 +#define PCLK_SPI 263 +#define PCLK_SFC 264 +#define PCLK_UART0 265 +#define PCLK_UART1 266 +#define PCLK_UART2 267 +#define PCLK_TSADC 268 +#define PCLK_PWM 269 +#define PCLK_TIMER 270 +#define PCLK_PERI 271 +#define PCLK_GPIO0_PMU 272 +#define PCLK_I2C0_PMU 273 +#define PCLK_PWM0_PMU 274 +#define PCLK_ISP 275 +#define PCLK_VIO 276 +#define PCLK_MIPI_DSI 277 +#define PCLK_HDMI_CTRL 278 +#define PCLK_SARADC 279 +#define PCLK_DSP_CFG 280 +#define PCLK_BUS 281 +#define PCLK_EFUSE0 282 +#define PCLK_EFUSE1 283 +#define PCLK_WDT 284 +#define PCLK_GMAC 285 + +/* hclk gates */ +#define HCLK_I2S0_8CH 320 +#define HCLK_I2S1_2CH 321 +#define HCLK_I2S2_2CH 322 +#define HCLK_NANDC 323 +#define HCLK_SDMMC 324 +#define HCLK_SDIO 325 +#define HCLK_EMMC 326 +#define HCLK_PERI 327 +#define HCLK_SFC 328 +#define HCLK_RKVENC 329 +#define HCLK_RKVDEC 330 +#define HCLK_CIF0 331 +#define HCLK_VIO 332 +#define HCLK_VOP 333 +#define HCLK_IEP 334 +#define HCLK_RGA 335 +#define HCLK_ISP 336 +#define HCLK_CRYPTO_MST 337 +#define HCLK_CRYPTO_SLV 338 +#define HCLK_HOST0 339 +#define HCLK_OTG 340 +#define HCLK_CIF1 341 +#define HCLK_CIF2 342 +#define HCLK_CIF3 343 +#define HCLK_BUS 344 +#define HCLK_VPU 345 + +#define CLK_NR_CLKS (HCLK_VPU + 1) + +/* reset id */ +#define SRST_CORE_PO_AD 0 +#define SRST_CORE_AD 1 +#define SRST_L2_AD 2 +#define SRST_CPU_NIU_AD 3 +#define SRST_CORE_PO 4 +#define SRST_CORE 5 +#define SRST_L2 6 +#define SRST_CORE_DBG 8 +#define PRST_DBG 9 +#define RST_DAP 10 +#define PRST_DBG_NIU 11 +#define ARST_STRC_SYS_AD 15 + +#define SRST_DDRPHY_CLKDIV 16 +#define SRST_DDRPHY 17 +#define PRST_DDRPHY 18 +#define PRST_HDMIPHY 19 +#define PRST_VDACPHY 20 +#define PRST_VADCPHY 21 +#define PRST_MIPI_CSI_PHY 22 +#define PRST_MIPI_DSI_PHY 23 +#define PRST_ACODEC 24 +#define ARST_BUS_NIU 25 +#define PRST_TOP_NIU 26 +#define ARST_INTMEM 27 +#define HRST_ROM 28 +#define ARST_DMAC 29 +#define SRST_MSCH_NIU 30 +#define PRST_MSCH_NIU 31 + +#define PRST_DDRUPCTL 32 +#define NRST_DDRUPCTL 33 +#define PRST_DDRMON 34 +#define HRST_I2S0_8CH 35 +#define MRST_I2S0_8CH 36 +#define HRST_I2S1_2CH 37 +#define MRST_IS21_2CH 38 +#define HRST_I2S2_2CH 39 +#define MRST_I2S2_2CH 40 +#define HRST_CRYPTO 41 +#define SRST_CRYPTO 42 +#define PRST_SPI 43 +#define SRST_SPI 44 +#define PRST_UART0 45 +#define PRST_UART1 46 +#define PRST_UART2 47 + +#define SRST_UART0 48 +#define SRST_UART1 49 +#define SRST_UART2 50 +#define PRST_I2C1 51 +#define PRST_I2C2 52 +#define PRST_I2C3 53 +#define SRST_I2C1 54 +#define SRST_I2C2 55 +#define SRST_I2C3 56 +#define PRST_PWM1 58 +#define SRST_PWM1 60 +#define PRST_WDT 61 +#define PRST_GPIO1 62 +#define PRST_GPIO2 63 + +#define PRST_GPIO3 64 +#define PRST_GRF 65 +#define PRST_EFUSE 66 +#define PRST_EFUSE512 67 +#define PRST_TIMER0 68 +#define SRST_TIMER0 69 +#define SRST_TIMER1 70 +#define PRST_TSADC 71 +#define SRST_TSADC 72 +#define PRST_SARADC 73 +#define SRST_SARADC 74 +#define HRST_SYSBUS 75 +#define PRST_USBGRF 76 + +#define ARST_PERIPH_NIU 80 +#define HRST_PERIPH_NIU 81 +#define PRST_PERIPH_NIU 82 +#define HRST_PERIPH 83 +#define HRST_SDMMC 84 +#define HRST_SDIO 85 +#define HRST_EMMC 86 +#define HRST_NANDC 87 +#define NRST_NANDC 88 +#define HRST_SFC 89 +#define SRST_SFC 90 +#define ARST_GMAC 91 +#define HRST_OTG 92 +#define SRST_OTG 93 +#define SRST_OTG_ADP 94 +#define HRST_HOST0 95 + +#define HRST_HOST0_AUX 96 +#define HRST_HOST0_ARB 97 +#define SRST_HOST0_EHCIPHY 98 +#define SRST_HOST0_UTMI 99 +#define SRST_USBPOR 100 +#define SRST_UTMI0 101 +#define SRST_UTMI1 102 + +#define ARST_VIO0_NIU 102 +#define ARST_VIO1_NIU 103 +#define HRST_VIO_NIU 104 +#define PRST_VIO_NIU 105 +#define ARST_VOP 106 +#define HRST_VOP 107 +#define DRST_VOP 108 +#define ARST_IEP 109 +#define HRST_IEP 110 +#define ARST_RGA 111 +#define HRST_RGA 112 +#define SRST_RGA 113 +#define PRST_CVBS 114 +#define PRST_HDMI 115 +#define SRST_HDMI 116 +#define PRST_MIPI_DSI 117 + +#define ARST_ISP_NIU 118 +#define HRST_ISP_NIU 119 +#define HRST_ISP 120 +#define SRST_ISP 121 +#define ARST_VIP0 122 +#define HRST_VIP0 123 +#define PRST_VIP0 124 +#define ARST_VIP1 125 +#define HRST_VIP1 126 +#define PRST_VIP1 127 +#define ARST_VIP2 128 +#define HRST_VIP2 129 +#define PRST_VIP2 120 +#define ARST_VIP3 121 +#define HRST_VIP3 122 +#define PRST_VIP4 123 + +#define PRST_CIF1TO4 124 +#define SRST_CVBS_CLK 125 +#define HRST_CVBS 126 + +#define ARST_VPU_NIU 140 +#define HRST_VPU_NIU 141 +#define ARST_VPU 142 +#define HRST_VPU 143 +#define ARST_RKVDEC_NIU 144 +#define HRST_RKVDEC_NIU 145 +#define ARST_RKVDEC 146 +#define HRST_RKVDEC 147 +#define SRST_RKVDEC_CABAC 148 +#define SRST_RKVDEC_CORE 149 +#define ARST_RKVENC_NIU 150 +#define HRST_RKVENC_NIU 151 +#define ARST_RKVENC 152 +#define HRST_RKVENC 153 +#define SRST_RKVENC_CORE 154 + +#define SRST_DSP_CORE 156 +#define SRST_DSP_SYS 157 +#define SRST_DSP_GLOBAL 158 +#define SRST_DSP_OECM 159 +#define PRST_DSP_IOP_NIU 160 +#define ARST_DSP_EPP_NIU 161 +#define ARST_DSP_EDP_NIU 162 +#define PRST_DSP_DBG_NIU 163 +#define PRST_DSP_CFG_NIU 164 +#define PRST_DSP_GRF 165 +#define PRST_DSP_MAILBOX 166 +#define PRST_DSP_INTC 167 +#define PRST_DSP_PFM_MON 169 +#define SRST_DSP_PFM_MON 170 +#define ARST_DSP_EDAP_NIU 171 + +#define SRST_PMU 172 +#define SRST_PMU_I2C0 173 +#define PRST_PMU_I2C0 174 +#define PRST_PMU_GPIO0 175 +#define PRST_PMU_INTMEM 176 +#define PRST_PMU_PWM0 177 +#define SRST_PMU_PWM0 178 +#define PRST_PMU_GRF 179 +#define SRST_PMU_NIU 180 +#define SRST_PMU_PVTM 181 +#define ARST_DSP_EDP_PERF 184 +#define ARST_DSP_EPP_PERF 185 + +#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/sifive-fu540-prci.h b/roms/u-boot/include/dt-bindings/clock/sifive-fu540-prci.h new file mode 100644 index 000000000..6a0b70a37 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sifive-fu540-prci.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018-2019 SiFive, Inc. + * Wesley Terpstra + * Paul Walmsley + */ + +#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H +#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H + +/* Clock indexes for use by Device Tree data and the PRCI driver */ + +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/sifive-fu740-prci.h b/roms/u-boot/include/dt-bindings/clock/sifive-fu740-prci.h new file mode 100644 index 000000000..c1224783c --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sifive-fu740-prci.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2020-2021 SiFive, Inc. + * Wesley Terpstra + * Paul Walmsley + * Zong Li + * Pragnesh Patel + */ + +#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H +#define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H + +/* Clock indexes for use by Device Tree data and the PRCI driver */ + +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_DVFSCOREPLL 3 +#define PRCI_CLK_HFPCLKPLL 4 +#define PRCI_CLK_CLTXPLL 5 +#define PRCI_CLK_TLCLK 6 +#define PRCI_CLK_PCLK 7 +#define PRCI_CLK_PCIEAUX 8 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/snps,hsdk-cgu.h b/roms/u-boot/include/dt-bindings/clock/snps,hsdk-cgu.h new file mode 100644 index 000000000..1ce7661cd --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/snps,hsdk-cgu.h @@ -0,0 +1,43 @@ +/* + * Synopsys HSDK SDP CGU clock driver dts bindings + * + * Copyright (C) 2017 Synopsys + * Author: Eugeniy Paltsev + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __DT_BINDINGS_CLK_HSDK_CGU_H_ +#define __DT_BINDINGS_CLK_HSDK_CGU_H_ + +#define CLK_ARC_PLL 0 +#define CLK_ARC 1 +#define CLK_DDR_PLL 2 +#define CLK_SYS_PLL 3 +#define CLK_SYS_APB 4 +#define CLK_SYS_AXI 5 +#define CLK_SYS_ETH 6 +#define CLK_SYS_USB 7 +#define CLK_SYS_SDIO 8 +#define CLK_SYS_HDMI 9 +#define CLK_SYS_GFX_CORE 10 +#define CLK_SYS_GFX_DMA 11 +#define CLK_SYS_GFX_CFG 12 +#define CLK_SYS_DMAC_CORE 13 +#define CLK_SYS_DMAC_CFG 14 +#define CLK_SYS_SDIO_REF 15 +#define CLK_SYS_SPI_REF 16 +#define CLK_SYS_I2C_REF 17 +#define CLK_SYS_UART_REF 18 +#define CLK_SYS_EBI_REF 19 +#define CLK_TUN_PLL 20 +#define CLK_TUN_TUN 21 +#define CLK_TUN_ROM 22 +#define CLK_TUN_PWM 23 +#define CLK_TUN_TIMER 24 +#define CLK_HDMI_PLL 25 +#define CLK_HDMI 26 + +#endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/ste-ab8500.h b/roms/u-boot/include/dt-bindings/clock/ste-ab8500.h new file mode 100644 index 000000000..fb42dd0ca --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/ste-ab8500.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __STE_CLK_AB8500_H__ +#define __STE_CLK_AB8500_H__ + +#define AB8500_SYSCLK_BUF2 0 +#define AB8500_SYSCLK_BUF3 1 +#define AB8500_SYSCLK_BUF4 2 +#define AB8500_SYSCLK_ULP 3 +#define AB8500_SYSCLK_INT 4 +#define AB8500_SYSCLK_AUDIO 5 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/stih407-clks.h b/roms/u-boot/include/dt-bindings/clock/stih407-clks.h new file mode 100644 index 000000000..082edd9ba --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/stih407-clks.h @@ -0,0 +1,90 @@ +/* + * This header provides constants clk index STMicroelectronics + * STiH407 SoC. + */ +#ifndef _DT_BINDINGS_CLK_STIH407 +#define _DT_BINDINGS_CLK_STIH407 + +/* CLOCKGEN A0 */ +#define CLK_IC_LMI0 0 +#define CLK_IC_LMI1 1 + +/* CLOCKGEN C0 */ +#define CLK_ICN_GPU 0 +#define CLK_FDMA 1 +#define CLK_NAND 2 +#define CLK_HVA 3 +#define CLK_PROC_STFE 4 +#define CLK_PROC_TP 5 +#define CLK_RX_ICN_DMU 6 +#define CLK_RX_ICN_DISP_0 6 +#define CLK_RX_ICN_DISP_1 6 +#define CLK_RX_ICN_HVA 7 +#define CLK_RX_ICN_TS 7 +#define CLK_ICN_CPU 8 +#define CLK_TX_ICN_DMU 9 +#define CLK_TX_ICN_HVA 9 +#define CLK_TX_ICN_TS 9 +#define CLK_ICN_COMPO 9 +#define CLK_MMC_0 10 +#define CLK_MMC_1 11 +#define CLK_JPEGDEC 12 +#define CLK_ICN_REG 13 +#define CLK_TRACE_A9 13 +#define CLK_PTI_STM 13 +#define CLK_EXT2F_A9 13 +#define CLK_IC_BDISP_0 14 +#define CLK_IC_BDISP_1 15 +#define CLK_PP_DMU 16 +#define CLK_VID_DMU 17 +#define CLK_DSS_LPC 18 +#define CLK_ST231_AUD_0 19 +#define CLK_ST231_GP_0 19 +#define CLK_ST231_GP_1 20 +#define CLK_ST231_DMU 21 +#define CLK_ICN_LMI 22 +#define CLK_TX_ICN_DISP_0 23 +#define CLK_TX_ICN_DISP_1 23 +#define CLK_ICN_SBC 24 +#define CLK_STFE_FRC2 25 +#define CLK_ETH_PHY 26 +#define CLK_ETH_REF_PHYCLK 27 +#define CLK_FLASH_PROMIP 28 +#define CLK_MAIN_DISP 29 +#define CLK_AUX_DISP 30 +#define CLK_COMPO_DVP 31 + +/* CLOCKGEN D0 */ +#define CLK_PCM_0 0 +#define CLK_PCM_1 1 +#define CLK_PCM_2 2 +#define CLK_SPDIFF 3 + +/* CLOCKGEN D2 */ +#define CLK_PIX_MAIN_DISP 0 +#define CLK_PIX_PIP 1 +#define CLK_PIX_GDP1 2 +#define CLK_PIX_GDP2 3 +#define CLK_PIX_GDP3 4 +#define CLK_PIX_GDP4 5 +#define CLK_PIX_AUX_DISP 6 +#define CLK_DENC 7 +#define CLK_PIX_HDDAC 8 +#define CLK_HDDAC 9 +#define CLK_SDDAC 10 +#define CLK_PIX_DVO 11 +#define CLK_DVO 12 +#define CLK_PIX_HDMI 13 +#define CLK_TMDS_HDMI 14 +#define CLK_REF_HDMIPHY 15 + +/* CLOCKGEN D3 */ +#define CLK_STFE_FRC1 0 +#define CLK_TSOUT_0 1 +#define CLK_TSOUT_1 2 +#define CLK_MCHI 3 +#define CLK_VSENS_COMPO 4 +#define CLK_FRC1_REMOTE 5 +#define CLK_LPC_0 6 +#define CLK_LPC_1 7 +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/stih410-clks.h b/roms/u-boot/include/dt-bindings/clock/stih410-clks.h new file mode 100644 index 000000000..2097a4bbe --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/stih410-clks.h @@ -0,0 +1,25 @@ +/* + * This header provides constants clk index STMicroelectronics + * STiH410 SoC. + */ +#ifndef _DT_BINDINGS_CLK_STIH410 +#define _DT_BINDINGS_CLK_STIH410 + +#include "stih407-clks.h" + +/* STiH410 introduces new clock outputs compared to STiH407 */ + +/* CLOCKGEN C0 */ +#define CLK_TX_ICN_HADES 32 +#define CLK_RX_ICN_HADES 33 +#define CLK_ICN_REG_16 34 +#define CLK_PP_HADES 35 +#define CLK_CLUST_HADES 36 +#define CLK_HWPE_HADES 37 +#define CLK_FC_HADES 38 + +/* CLOCKGEN D0 */ +#define CLK_PCMR10_MASTER 4 +#define CLK_USB2_PHY 5 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/stm32fx-clock.h b/roms/u-boot/include/dt-bindings/clock/stm32fx-clock.h new file mode 100644 index 000000000..1cc89c548 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/stm32fx-clock.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * stm32fx-clock.h + * + * Copyright (C) 2016 STMicroelectronics + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +/* + * List of clocks wich are not derived from system clock (SYSCLOCK) + * + * The index of these clocks is the secondary index of DT bindings + * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt) + * + * e.g: + ; +*/ + +#ifndef _DT_BINDINGS_CLK_STMFX_H +#define _DT_BINDINGS_CLK_STMFX_H + +#define SYSTICK 0 +#define FCLK 1 +#define CLK_LSI 2 +#define CLK_LSE 3 +#define CLK_HSE_RTC 4 +#define CLK_RTC 5 +#define PLL_VCO_I2S 6 +#define PLL_VCO_SAI 7 +#define CLK_LCD 8 +#define CLK_I2S 9 +#define CLK_SAI1 10 +#define CLK_SAI2 11 +#define CLK_I2SQ_PDIV 12 +#define CLK_SAIQ_PDIV 13 +#define CLK_HSI 14 +#define CLK_SYSCLK 15 +#define CLK_F469_DSI 16 + +#define END_PRIMARY_CLK 17 + +#define CLK_HDMI_CEC 16 +#define CLK_SPDIF 17 +#define CLK_USART1 18 +#define CLK_USART2 19 +#define CLK_USART3 20 +#define CLK_UART4 21 +#define CLK_UART5 22 +#define CLK_USART6 23 +#define CLK_UART7 24 +#define CLK_UART8 25 +#define CLK_I2C1 26 +#define CLK_I2C2 27 +#define CLK_I2C3 28 +#define CLK_I2C4 29 +#define CLK_LPTIMER 30 +#define CLK_PLL_SRC 31 +#define CLK_DFSDM1 32 +#define CLK_ADFSDM1 33 +#define CLK_F769_DSI 34 +#define END_PRIMARY_CLK_F7 35 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/stm32h7-clks.h b/roms/u-boot/include/dt-bindings/clock/stm32h7-clks.h new file mode 100644 index 000000000..4d87e7ebc --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/stm32h7-clks.h @@ -0,0 +1,167 @@ +/* SYS, CORE AND BUS CLOCKS */ +#define SYS_D1CPRE 0 +#define HCLK 1 +#define PCLK1 2 +#define PCLK2 3 +#define PCLK3 4 +#define PCLK4 5 +#define HSI_DIV 6 +#define HSE_1M 7 +#define I2S_CKIN 8 +#define CK_DSI_PHY 9 +#define HSE_CK 10 +#define LSE_CK 11 +#define CSI_KER_DIV122 12 +#define RTC_CK 13 +#define CPU_SYSTICK 14 + +/* OSCILLATOR BANK */ +#define OSC_BANK 18 +#define HSI_CK 18 +#define HSI_KER_CK 19 +#define CSI_CK 20 +#define CSI_KER_CK 21 +#define RC48_CK 22 +#define LSI_CK 23 + +/* MCLOCK BANK */ +#define MCLK_BANK 28 +#define PER_CK 28 +#define PLLSRC 29 +#define SYS_CK 30 +#define TRACEIN_CK 31 + +/* ODF BANK */ +#define ODF_BANK 32 +#define PLL1_P 32 +#define PLL1_Q 33 +#define PLL1_R 34 +#define PLL2_P 35 +#define PLL2_Q 36 +#define PLL2_R 37 +#define PLL3_P 38 +#define PLL3_Q 39 +#define PLL3_R 40 + +/* MCO BANK */ +#define MCO_BANK 41 +#define MCO1 41 +#define MCO2 42 + +/* PERIF BANK */ +#define PERIF_BANK 50 +#define D1SRAM1_CK 50 +#define ITCM_CK 51 +#define DTCM2_CK 52 +#define DTCM1_CK 53 +#define FLITF_CK 54 +#define JPGDEC_CK 55 +#define DMA2D_CK 56 +#define MDMA_CK 57 +#define USB2ULPI_CK 58 +#define USB1ULPI_CK 59 +#define ETH1RX_CK 60 +#define ETH1TX_CK 61 +#define ETH1MAC_CK 62 +#define ART_CK 63 +#define DMA2_CK 64 +#define DMA1_CK 65 +#define D2SRAM3_CK 66 +#define D2SRAM2_CK 67 +#define D2SRAM1_CK 68 +#define HASH_CK 69 +#define CRYPT_CK 70 +#define CAMITF_CK 71 +#define BKPRAM_CK 72 +#define HSEM_CK 73 +#define BDMA_CK 74 +#define CRC_CK 75 +#define GPIOK_CK 76 +#define GPIOJ_CK 77 +#define GPIOI_CK 78 +#define GPIOH_CK 79 +#define GPIOG_CK 80 +#define GPIOF_CK 81 +#define GPIOE_CK 82 +#define GPIOD_CK 83 +#define GPIOC_CK 84 +#define GPIOB_CK 85 +#define GPIOA_CK 86 +#define WWDG1_CK 87 +#define DAC12_CK 88 +#define WWDG2_CK 89 +#define TIM14_CK 90 +#define TIM13_CK 91 +#define TIM12_CK 92 +#define TIM7_CK 93 +#define TIM6_CK 94 +#define TIM5_CK 95 +#define TIM4_CK 96 +#define TIM3_CK 97 +#define TIM2_CK 98 +#define MDIOS_CK 99 +#define OPAMP_CK 100 +#define CRS_CK 101 +#define TIM17_CK 102 +#define TIM16_CK 103 +#define TIM15_CK 104 +#define TIM8_CK 105 +#define TIM1_CK 106 +#define TMPSENS_CK 107 +#define RTCAPB_CK 108 +#define VREF_CK 109 +#define COMP12_CK 110 +#define SYSCFG_CK 111 +/* must be equal to last peripheral clock index */ +#define LAST_PERIF_BANK SYSCFG_CK + +/* KERNEL BANK */ +#define KERN_BANK 120 +#define SDMMC1_CK 120 +#define QUADSPI_CK 121 +#define FMC_CK 122 +#define USB2OTG_CK 123 +#define USB1OTG_CK 124 +#define ADC12_CK 125 +#define SDMMC2_CK 126 +#define RNG_CK 127 +#define ADC3_CK 128 +#define DSI_CK 129 +#define LTDC_CK 130 +#define USART8_CK 131 +#define USART7_CK 132 +#define HDMICEC_CK 133 +#define I2C3_CK 134 +#define I2C2_CK 135 +#define I2C1_CK 136 +#define UART5_CK 137 +#define UART4_CK 138 +#define USART3_CK 139 +#define USART2_CK 140 +#define SPDIFRX_CK 141 +#define SPI3_CK 142 +#define SPI2_CK 143 +#define LPTIM1_CK 144 +#define FDCAN_CK 145 +#define SWP_CK 146 +#define HRTIM_CK 147 +#define DFSDM1_CK 148 +#define SAI3_CK 149 +#define SAI2_CK 150 +#define SAI1_CK 151 +#define SPI5_CK 152 +#define SPI4_CK 153 +#define SPI1_CK 154 +#define USART6_CK 155 +#define USART1_CK 156 +#define SAI4B_CK 157 +#define SAI4A_CK 158 +#define LPTIM5_CK 159 +#define LPTIM4_CK 160 +#define LPTIM3_CK 161 +#define LPTIM2_CK 162 +#define I2C4_CK 163 +#define SPI6_CK 164 +#define LPUART1_CK 165 + +#define STM32H7_MAX_CLKS 166 diff --git a/roms/u-boot/include/dt-bindings/clock/stm32mp1-clks.h b/roms/u-boot/include/dt-bindings/clock/stm32mp1-clks.h new file mode 100644 index 000000000..4cdaf1358 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/stm32mp1-clks.h @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_ +#define _DT_BINDINGS_STM32MP1_CLKS_H_ + +/* OSCILLATOR clocks */ +#define CK_HSE 0 +#define CK_CSI 1 +#define CK_LSI 2 +#define CK_LSE 3 +#define CK_HSI 4 +#define CK_HSE_DIV2 5 + +/* Bus clocks */ +#define TIM2 6 +#define TIM3 7 +#define TIM4 8 +#define TIM5 9 +#define TIM6 10 +#define TIM7 11 +#define TIM12 12 +#define TIM13 13 +#define TIM14 14 +#define LPTIM1 15 +#define SPI2 16 +#define SPI3 17 +#define USART2 18 +#define USART3 19 +#define UART4 20 +#define UART5 21 +#define UART7 22 +#define UART8 23 +#define I2C1 24 +#define I2C2 25 +#define I2C3 26 +#define I2C5 27 +#define SPDIF 28 +#define CEC 29 +#define DAC12 30 +#define MDIO 31 +#define TIM1 32 +#define TIM8 33 +#define TIM15 34 +#define TIM16 35 +#define TIM17 36 +#define SPI1 37 +#define SPI4 38 +#define SPI5 39 +#define USART6 40 +#define SAI1 41 +#define SAI2 42 +#define SAI3 43 +#define DFSDM 44 +#define FDCAN 45 +#define LPTIM2 46 +#define LPTIM3 47 +#define LPTIM4 48 +#define LPTIM5 49 +#define SAI4 50 +#define SYSCFG 51 +#define VREF 52 +#define TMPSENS 53 +#define PMBCTRL 54 +#define HDP 55 +#define LTDC 56 +#define DSI 57 +#define IWDG2 58 +#define USBPHY 59 +#define STGENRO 60 +#define SPI6 61 +#define I2C4 62 +#define I2C6 63 +#define USART1 64 +#define RTCAPB 65 +#define TZC1 66 +#define TZPC 67 +#define IWDG1 68 +#define BSEC 69 +#define STGEN 70 +#define DMA1 71 +#define DMA2 72 +#define DMAMUX 73 +#define ADC12 74 +#define USBO 75 +#define SDMMC3 76 +#define DCMI 77 +#define CRYP2 78 +#define HASH2 79 +#define RNG2 80 +#define CRC2 81 +#define HSEM 82 +#define IPCC 83 +#define GPIOA 84 +#define GPIOB 85 +#define GPIOC 86 +#define GPIOD 87 +#define GPIOE 88 +#define GPIOF 89 +#define GPIOG 90 +#define GPIOH 91 +#define GPIOI 92 +#define GPIOJ 93 +#define GPIOK 94 +#define GPIOZ 95 +#define CRYP1 96 +#define HASH1 97 +#define RNG1 98 +#define BKPSRAM 99 +#define MDMA 100 +#define GPU 101 +#define ETHCK 102 +#define ETHTX 103 +#define ETHRX 104 +#define ETHMAC 105 +#define FMC 106 +#define QSPI 107 +#define SDMMC1 108 +#define SDMMC2 109 +#define CRC1 110 +#define USBH 111 +#define ETHSTP 112 +#define TZC2 113 + +/* Kernel clocks */ +#define SDMMC1_K 118 +#define SDMMC2_K 119 +#define SDMMC3_K 120 +#define FMC_K 121 +#define QSPI_K 122 +#define ETHCK_K 123 +#define RNG1_K 124 +#define RNG2_K 125 +#define GPU_K 126 +#define USBPHY_K 127 +#define STGEN_K 128 +#define SPDIF_K 129 +#define SPI1_K 130 +#define SPI2_K 131 +#define SPI3_K 132 +#define SPI4_K 133 +#define SPI5_K 134 +#define SPI6_K 135 +#define CEC_K 136 +#define I2C1_K 137 +#define I2C2_K 138 +#define I2C3_K 139 +#define I2C4_K 140 +#define I2C5_K 141 +#define I2C6_K 142 +#define LPTIM1_K 143 +#define LPTIM2_K 144 +#define LPTIM3_K 145 +#define LPTIM4_K 146 +#define LPTIM5_K 147 +#define USART1_K 148 +#define USART2_K 149 +#define USART3_K 150 +#define UART4_K 151 +#define UART5_K 152 +#define USART6_K 153 +#define UART7_K 154 +#define UART8_K 155 +#define DFSDM_K 156 +#define FDCAN_K 157 +#define SAI1_K 158 +#define SAI2_K 159 +#define SAI3_K 160 +#define SAI4_K 161 +#define ADC12_K 162 +#define DSI_K 163 +#define DSI_PX 164 +#define ADFSDM_K 165 +#define USBO_K 166 +#define LTDC_PX 167 +#define DAC12_K 168 +#define ETHPTP_K 169 + +/* PLL */ +#define PLL1 176 +#define PLL2 177 +#define PLL3 178 +#define PLL4 179 + +/* ODF */ +#define PLL1_P 180 +#define PLL1_Q 181 +#define PLL1_R 182 +#define PLL2_P 183 +#define PLL2_Q 184 +#define PLL2_R 185 +#define PLL3_P 186 +#define PLL3_Q 187 +#define PLL3_R 188 +#define PLL4_P 189 +#define PLL4_Q 190 +#define PLL4_R 191 + +/* AUX */ +#define RTC 192 + +/* MCLK */ +#define CK_PER 193 +#define CK_MPU 194 +#define CK_AXI 195 +#define CK_MCU 196 + +/* Time base */ +#define TIM2_K 197 +#define TIM3_K 198 +#define TIM4_K 199 +#define TIM5_K 200 +#define TIM6_K 201 +#define TIM7_K 202 +#define TIM12_K 203 +#define TIM13_K 204 +#define TIM14_K 205 +#define TIM1_K 206 +#define TIM8_K 207 +#define TIM15_K 208 +#define TIM16_K 209 +#define TIM17_K 210 + +/* MCO clocks */ +#define CK_MCO1 211 +#define CK_MCO2 212 + +/* TRACE & DEBUG clocks */ +#define CK_DBG 214 +#define CK_TRACE 215 + +/* DDR */ +#define DDRC1 220 +#define DDRC1LP 221 +#define DDRC2 222 +#define DDRC2LP 223 +#define DDRPHYC 224 +#define DDRPHYCLP 225 +#define DDRCAPB 226 +#define DDRCAPBLP 227 +#define AXIDCG 228 +#define DDRPHYCAPB 229 +#define DDRPHYCAPBLP 230 +#define DDRPERFM 231 + +#define STM32MP1_LAST_CLK 232 + +#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/stm32mp1-clksrc.h b/roms/u-boot/include/dt-bindings/clock/stm32mp1-clksrc.h new file mode 100644 index 000000000..002ad5351 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/stm32mp1-clksrc.h @@ -0,0 +1,284 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + */ + +#ifndef _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_ +#define _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_ + +/* PLL output is enable when x=1, with x=p,q or r */ +#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) + +/* st,clksrc: mandatory clock source */ + +#define CLK_MPU_HSI 0x00000200 +#define CLK_MPU_HSE 0x00000201 +#define CLK_MPU_PLL1P 0x00000202 +#define CLK_MPU_PLL1P_DIV 0x00000203 + +#define CLK_AXI_HSI 0x00000240 +#define CLK_AXI_HSE 0x00000241 +#define CLK_AXI_PLL2P 0x00000242 + +#define CLK_MCU_HSI 0x00000480 +#define CLK_MCU_HSE 0x00000481 +#define CLK_MCU_CSI 0x00000482 +#define CLK_MCU_PLL3P 0x00000483 + +#define CLK_PLL12_HSI 0x00000280 +#define CLK_PLL12_HSE 0x00000281 + +#define CLK_PLL3_HSI 0x00008200 +#define CLK_PLL3_HSE 0x00008201 +#define CLK_PLL3_CSI 0x00008202 + +#define CLK_PLL4_HSI 0x00008240 +#define CLK_PLL4_HSE 0x00008241 +#define CLK_PLL4_CSI 0x00008242 +#define CLK_PLL4_I2SCKIN 0x00008243 + +#define CLK_RTC_DISABLED 0x00001400 +#define CLK_RTC_LSE 0x00001401 +#define CLK_RTC_LSI 0x00001402 +#define CLK_RTC_HSE 0x00001403 + +#define CLK_MCO1_HSI 0x00008000 +#define CLK_MCO1_HSE 0x00008001 +#define CLK_MCO1_CSI 0x00008002 +#define CLK_MCO1_LSI 0x00008003 +#define CLK_MCO1_LSE 0x00008004 +#define CLK_MCO1_DISABLED 0x0000800F + +#define CLK_MCO2_MPU 0x00008040 +#define CLK_MCO2_AXI 0x00008041 +#define CLK_MCO2_MCU 0x00008042 +#define CLK_MCO2_PLL4P 0x00008043 +#define CLK_MCO2_HSE 0x00008044 +#define CLK_MCO2_HSI 0x00008045 +#define CLK_MCO2_DISABLED 0x0000804F + +/* st,pkcs: peripheral kernel clock source */ + +#define CLK_I2C12_PCLK1 0x00008C00 +#define CLK_I2C12_PLL4R 0x00008C01 +#define CLK_I2C12_HSI 0x00008C02 +#define CLK_I2C12_CSI 0x00008C03 +#define CLK_I2C12_DISABLED 0x00008C07 + +#define CLK_I2C35_PCLK1 0x00008C40 +#define CLK_I2C35_PLL4R 0x00008C41 +#define CLK_I2C35_HSI 0x00008C42 +#define CLK_I2C35_CSI 0x00008C43 +#define CLK_I2C35_DISABLED 0x00008C47 + +#define CLK_I2C46_PCLK5 0x00000C00 +#define CLK_I2C46_PLL3Q 0x00000C01 +#define CLK_I2C46_HSI 0x00000C02 +#define CLK_I2C46_CSI 0x00000C03 +#define CLK_I2C46_DISABLED 0x00000C07 + +#define CLK_SAI1_PLL4Q 0x00008C80 +#define CLK_SAI1_PLL3Q 0x00008C81 +#define CLK_SAI1_I2SCKIN 0x00008C82 +#define CLK_SAI1_CKPER 0x00008C83 +#define CLK_SAI1_PLL3R 0x00008C84 +#define CLK_SAI1_DISABLED 0x00008C87 + +#define CLK_SAI2_PLL4Q 0x00008CC0 +#define CLK_SAI2_PLL3Q 0x00008CC1 +#define CLK_SAI2_I2SCKIN 0x00008CC2 +#define CLK_SAI2_CKPER 0x00008CC3 +#define CLK_SAI2_SPDIF 0x00008CC4 +#define CLK_SAI2_PLL3R 0x00008CC5 +#define CLK_SAI2_DISABLED 0x00008CC7 + +#define CLK_SAI3_PLL4Q 0x00008D00 +#define CLK_SAI3_PLL3Q 0x00008D01 +#define CLK_SAI3_I2SCKIN 0x00008D02 +#define CLK_SAI3_CKPER 0x00008D03 +#define CLK_SAI3_PLL3R 0x00008D04 +#define CLK_SAI3_DISABLED 0x00008D07 + +#define CLK_SAI4_PLL4Q 0x00008D40 +#define CLK_SAI4_PLL3Q 0x00008D41 +#define CLK_SAI4_I2SCKIN 0x00008D42 +#define CLK_SAI4_CKPER 0x00008D43 +#define CLK_SAI4_PLL3R 0x00008D44 +#define CLK_SAI4_DISABLED 0x00008D47 + +#define CLK_SPI2S1_PLL4P 0x00008D80 +#define CLK_SPI2S1_PLL3Q 0x00008D81 +#define CLK_SPI2S1_I2SCKIN 0x00008D82 +#define CLK_SPI2S1_CKPER 0x00008D83 +#define CLK_SPI2S1_PLL3R 0x00008D84 +#define CLK_SPI2S1_DISABLED 0x00008D87 + +#define CLK_SPI2S23_PLL4P 0x00008DC0 +#define CLK_SPI2S23_PLL3Q 0x00008DC1 +#define CLK_SPI2S23_I2SCKIN 0x00008DC2 +#define CLK_SPI2S23_CKPER 0x00008DC3 +#define CLK_SPI2S23_PLL3R 0x00008DC4 +#define CLK_SPI2S23_DISABLED 0x00008DC7 + +#define CLK_SPI45_PCLK2 0x00008E00 +#define CLK_SPI45_PLL4Q 0x00008E01 +#define CLK_SPI45_HSI 0x00008E02 +#define CLK_SPI45_CSI 0x00008E03 +#define CLK_SPI45_HSE 0x00008E04 +#define CLK_SPI45_DISABLED 0x00008E07 + +#define CLK_SPI6_PCLK5 0x00000C40 +#define CLK_SPI6_PLL4Q 0x00000C41 +#define CLK_SPI6_HSI 0x00000C42 +#define CLK_SPI6_CSI 0x00000C43 +#define CLK_SPI6_HSE 0x00000C44 +#define CLK_SPI6_PLL3Q 0x00000C45 +#define CLK_SPI6_DISABLED 0x00000C47 + +#define CLK_UART6_PCLK2 0x00008E40 +#define CLK_UART6_PLL4Q 0x00008E41 +#define CLK_UART6_HSI 0x00008E42 +#define CLK_UART6_CSI 0x00008E43 +#define CLK_UART6_HSE 0x00008E44 +#define CLK_UART6_DISABLED 0x00008E47 + +#define CLK_UART24_PCLK1 0x00008E80 +#define CLK_UART24_PLL4Q 0x00008E81 +#define CLK_UART24_HSI 0x00008E82 +#define CLK_UART24_CSI 0x00008E83 +#define CLK_UART24_HSE 0x00008E84 +#define CLK_UART24_DISABLED 0x00008E87 + +#define CLK_UART35_PCLK1 0x00008EC0 +#define CLK_UART35_PLL4Q 0x00008EC1 +#define CLK_UART35_HSI 0x00008EC2 +#define CLK_UART35_CSI 0x00008EC3 +#define CLK_UART35_HSE 0x00008EC4 +#define CLK_UART35_DISABLED 0x00008EC7 + +#define CLK_UART78_PCLK1 0x00008F00 +#define CLK_UART78_PLL4Q 0x00008F01 +#define CLK_UART78_HSI 0x00008F02 +#define CLK_UART78_CSI 0x00008F03 +#define CLK_UART78_HSE 0x00008F04 +#define CLK_UART78_DISABLED 0x00008F07 + +#define CLK_UART1_PCLK5 0x00000C80 +#define CLK_UART1_PLL3Q 0x00000C81 +#define CLK_UART1_HSI 0x00000C82 +#define CLK_UART1_CSI 0x00000C83 +#define CLK_UART1_PLL4Q 0x00000C84 +#define CLK_UART1_HSE 0x00000C85 +#define CLK_UART1_DISABLED 0x00000C87 + +#define CLK_SDMMC12_HCLK6 0x00008F40 +#define CLK_SDMMC12_PLL3R 0x00008F41 +#define CLK_SDMMC12_PLL4P 0x00008F42 +#define CLK_SDMMC12_HSI 0x00008F43 +#define CLK_SDMMC12_DISABLED 0x00008F47 + +#define CLK_SDMMC3_HCLK2 0x00008F80 +#define CLK_SDMMC3_PLL3R 0x00008F81 +#define CLK_SDMMC3_PLL4P 0x00008F82 +#define CLK_SDMMC3_HSI 0x00008F83 +#define CLK_SDMMC3_DISABLED 0x00008F87 + +#define CLK_ETH_PLL4P 0x00008FC0 +#define CLK_ETH_PLL3Q 0x00008FC1 +#define CLK_ETH_DISABLED 0x00008FC3 + +#define CLK_QSPI_ACLK 0x00009000 +#define CLK_QSPI_PLL3R 0x00009001 +#define CLK_QSPI_PLL4P 0x00009002 +#define CLK_QSPI_CKPER 0x00009003 + +#define CLK_FMC_ACLK 0x00009040 +#define CLK_FMC_PLL3R 0x00009041 +#define CLK_FMC_PLL4P 0x00009042 +#define CLK_FMC_CKPER 0x00009043 + +#define CLK_FDCAN_HSE 0x000090C0 +#define CLK_FDCAN_PLL3Q 0x000090C1 +#define CLK_FDCAN_PLL4Q 0x000090C2 +#define CLK_FDCAN_PLL4R 0x000090C3 + +#define CLK_SPDIF_PLL4P 0x00009140 +#define CLK_SPDIF_PLL3Q 0x00009141 +#define CLK_SPDIF_HSI 0x00009142 +#define CLK_SPDIF_DISABLED 0x00009143 + +#define CLK_CEC_LSE 0x00009180 +#define CLK_CEC_LSI 0x00009181 +#define CLK_CEC_CSI_DIV122 0x00009182 +#define CLK_CEC_DISABLED 0x00009183 + +#define CLK_USBPHY_HSE 0x000091C0 +#define CLK_USBPHY_PLL4R 0x000091C1 +#define CLK_USBPHY_HSE_DIV2 0x000091C2 +#define CLK_USBPHY_DISABLED 0x000091C3 + +#define CLK_USBO_PLL4R 0x800091C0 +#define CLK_USBO_USBPHY 0x800091C1 + +#define CLK_RNG1_CSI 0x00000CC0 +#define CLK_RNG1_PLL4R 0x00000CC1 +#define CLK_RNG1_LSE 0x00000CC2 +#define CLK_RNG1_LSI 0x00000CC3 + +#define CLK_RNG2_CSI 0x00009200 +#define CLK_RNG2_PLL4R 0x00009201 +#define CLK_RNG2_LSE 0x00009202 +#define CLK_RNG2_LSI 0x00009203 + +#define CLK_CKPER_HSI 0x00000D00 +#define CLK_CKPER_CSI 0x00000D01 +#define CLK_CKPER_HSE 0x00000D02 +#define CLK_CKPER_DISABLED 0x00000D03 + +#define CLK_STGEN_HSI 0x00000D40 +#define CLK_STGEN_HSE 0x00000D41 +#define CLK_STGEN_DISABLED 0x00000D43 + +#define CLK_DSI_DSIPLL 0x00009240 +#define CLK_DSI_PLL4P 0x00009241 + +#define CLK_ADC_PLL4R 0x00009280 +#define CLK_ADC_CKPER 0x00009281 +#define CLK_ADC_PLL3Q 0x00009282 +#define CLK_ADC_DISABLED 0x00009283 + +#define CLK_LPTIM45_PCLK3 0x000092C0 +#define CLK_LPTIM45_PLL4P 0x000092C1 +#define CLK_LPTIM45_PLL3Q 0x000092C2 +#define CLK_LPTIM45_LSE 0x000092C3 +#define CLK_LPTIM45_LSI 0x000092C4 +#define CLK_LPTIM45_CKPER 0x000092C5 +#define CLK_LPTIM45_DISABLED 0x000092C7 + +#define CLK_LPTIM23_PCLK3 0x00009300 +#define CLK_LPTIM23_PLL4Q 0x00009301 +#define CLK_LPTIM23_CKPER 0x00009302 +#define CLK_LPTIM23_LSE 0x00009303 +#define CLK_LPTIM23_LSI 0x00009304 +#define CLK_LPTIM23_DISABLED 0x00009307 + +#define CLK_LPTIM1_PCLK1 0x00009340 +#define CLK_LPTIM1_PLL4P 0x00009341 +#define CLK_LPTIM1_PLL3Q 0x00009342 +#define CLK_LPTIM1_LSE 0x00009343 +#define CLK_LPTIM1_LSI 0x00009344 +#define CLK_LPTIM1_CKPER 0x00009345 +#define CLK_LPTIM1_DISABLED 0x00009347 + +/* define for st,pll /csg */ +#define SSCG_MODE_CENTER_SPREAD 0 +#define SSCG_MODE_DOWN_SPREAD 1 + +/* define for st,drive */ +#define LSEDRV_LOWEST 0 +#define LSEDRV_MEDIUM_LOW 1 +#define LSEDRV_MEDIUM_HIGH 2 +#define LSEDRV_HIGHEST 3 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/sun4i-a10-ccu.h b/roms/u-boot/include/dt-bindings/clock/sun4i-a10-ccu.h new file mode 100644 index 000000000..e4fa61be5 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun4i-a10-ccu.h @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2017 Priit Laes + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_ +#define _DT_BINDINGS_CLK_SUN4I_A10_H_ + +#define CLK_HOSC 1 +#define CLK_PLL_VIDEO0_2X 9 +#define CLK_PLL_VIDEO1_2X 18 +#define CLK_CPU 20 + +/* AHB Gates */ +#define CLK_AHB_OTG 26 +#define CLK_AHB_EHCI0 27 +#define CLK_AHB_OHCI0 28 +#define CLK_AHB_EHCI1 29 +#define CLK_AHB_OHCI1 30 +#define CLK_AHB_SS 31 +#define CLK_AHB_DMA 32 +#define CLK_AHB_BIST 33 +#define CLK_AHB_MMC0 34 +#define CLK_AHB_MMC1 35 +#define CLK_AHB_MMC2 36 +#define CLK_AHB_MMC3 37 +#define CLK_AHB_MS 38 +#define CLK_AHB_NAND 39 +#define CLK_AHB_SDRAM 40 +#define CLK_AHB_ACE 41 +#define CLK_AHB_EMAC 42 +#define CLK_AHB_TS 43 +#define CLK_AHB_SPI0 44 +#define CLK_AHB_SPI1 45 +#define CLK_AHB_SPI2 46 +#define CLK_AHB_SPI3 47 +#define CLK_AHB_PATA 48 +#define CLK_AHB_SATA 49 +#define CLK_AHB_GPS 50 +#define CLK_AHB_HSTIMER 51 +#define CLK_AHB_VE 52 +#define CLK_AHB_TVD 53 +#define CLK_AHB_TVE0 54 +#define CLK_AHB_TVE1 55 +#define CLK_AHB_LCD0 56 +#define CLK_AHB_LCD1 57 +#define CLK_AHB_CSI0 58 +#define CLK_AHB_CSI1 59 +#define CLK_AHB_HDMI0 60 +#define CLK_AHB_HDMI1 61 +#define CLK_AHB_DE_BE0 62 +#define CLK_AHB_DE_BE1 63 +#define CLK_AHB_DE_FE0 64 +#define CLK_AHB_DE_FE1 65 +#define CLK_AHB_GMAC 66 +#define CLK_AHB_MP 67 +#define CLK_AHB_GPU 68 + +/* APB0 Gates */ +#define CLK_APB0_CODEC 69 +#define CLK_APB0_SPDIF 70 +#define CLK_APB0_I2S0 71 +#define CLK_APB0_AC97 72 +#define CLK_APB0_I2S1 73 +#define CLK_APB0_PIO 74 +#define CLK_APB0_IR0 75 +#define CLK_APB0_IR1 76 +#define CLK_APB0_I2S2 77 +#define CLK_APB0_KEYPAD 78 + +/* APB1 Gates */ +#define CLK_APB1_I2C0 79 +#define CLK_APB1_I2C1 80 +#define CLK_APB1_I2C2 81 +#define CLK_APB1_I2C3 82 +#define CLK_APB1_CAN 83 +#define CLK_APB1_SCR 84 +#define CLK_APB1_PS20 85 +#define CLK_APB1_PS21 86 +#define CLK_APB1_I2C4 87 +#define CLK_APB1_UART0 88 +#define CLK_APB1_UART1 89 +#define CLK_APB1_UART2 90 +#define CLK_APB1_UART3 91 +#define CLK_APB1_UART4 92 +#define CLK_APB1_UART5 93 +#define CLK_APB1_UART6 94 +#define CLK_APB1_UART7 95 + +/* IP clocks */ +#define CLK_NAND 96 +#define CLK_MS 97 +#define CLK_MMC0 98 +#define CLK_MMC0_OUTPUT 99 +#define CLK_MMC0_SAMPLE 100 +#define CLK_MMC1 101 +#define CLK_MMC1_OUTPUT 102 +#define CLK_MMC1_SAMPLE 103 +#define CLK_MMC2 104 +#define CLK_MMC2_OUTPUT 105 +#define CLK_MMC2_SAMPLE 106 +#define CLK_MMC3 107 +#define CLK_MMC3_OUTPUT 108 +#define CLK_MMC3_SAMPLE 109 +#define CLK_TS 110 +#define CLK_SS 111 +#define CLK_SPI0 112 +#define CLK_SPI1 113 +#define CLK_SPI2 114 +#define CLK_PATA 115 +#define CLK_IR0 116 +#define CLK_IR1 117 +#define CLK_I2S0 118 +#define CLK_AC97 119 +#define CLK_SPDIF 120 +#define CLK_KEYPAD 121 +#define CLK_SATA 122 +#define CLK_USB_OHCI0 123 +#define CLK_USB_OHCI1 124 +#define CLK_USB_PHY 125 +#define CLK_GPS 126 +#define CLK_SPI3 127 +#define CLK_I2S1 128 +#define CLK_I2S2 129 + +/* DRAM Gates */ +#define CLK_DRAM_VE 130 +#define CLK_DRAM_CSI0 131 +#define CLK_DRAM_CSI1 132 +#define CLK_DRAM_TS 133 +#define CLK_DRAM_TVD 134 +#define CLK_DRAM_TVE0 135 +#define CLK_DRAM_TVE1 136 +#define CLK_DRAM_OUT 137 +#define CLK_DRAM_DE_FE1 138 +#define CLK_DRAM_DE_FE0 139 +#define CLK_DRAM_DE_BE0 140 +#define CLK_DRAM_DE_BE1 141 +#define CLK_DRAM_MP 142 +#define CLK_DRAM_ACE 143 + +/* Display Engine Clocks */ +#define CLK_DE_BE0 144 +#define CLK_DE_BE1 145 +#define CLK_DE_FE0 146 +#define CLK_DE_FE1 147 +#define CLK_DE_MP 148 +#define CLK_TCON0_CH0 149 +#define CLK_TCON1_CH0 150 +#define CLK_CSI_SCLK 151 +#define CLK_TVD_SCLK2 152 +#define CLK_TVD 153 +#define CLK_TCON0_CH1_SCLK2 154 +#define CLK_TCON0_CH1 155 +#define CLK_TCON1_CH1_SCLK2 156 +#define CLK_TCON1_CH1 157 +#define CLK_CSI0 158 +#define CLK_CSI1 159 +#define CLK_CODEC 160 +#define CLK_VE 161 +#define CLK_AVS 162 +#define CLK_ACE 163 +#define CLK_HDMI 164 +#define CLK_GPU 165 + +#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun4i-a10-pll2.h b/roms/u-boot/include/dt-bindings/clock/sun4i-a10-pll2.h new file mode 100644 index 000000000..071c8112d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun4i-a10-pll2.h @@ -0,0 +1,53 @@ +/* + * Copyright 2015 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ +#define __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ + +#define SUN4I_A10_PLL2_1X 0 +#define SUN4I_A10_PLL2_2X 1 +#define SUN4I_A10_PLL2_4X 2 +#define SUN4I_A10_PLL2_8X 3 + +#endif /* __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun50i-a64-ccu.h b/roms/u-boot/include/dt-bindings/clock/sun50i-a64-ccu.h new file mode 100644 index 000000000..318eb15c4 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun50i-a64-ccu.h @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2016 Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ +#define _DT_BINDINGS_CLK_SUN50I_A64_H_ + +#define CLK_PLL_VIDEO0 7 +#define CLK_PLL_PERIPH0 11 + +#define CLK_CPUX 21 +#define CLK_BUS_MIPI_DSI 28 +#define CLK_BUS_CE 29 +#define CLK_BUS_DMA 30 +#define CLK_BUS_MMC0 31 +#define CLK_BUS_MMC1 32 +#define CLK_BUS_MMC2 33 +#define CLK_BUS_NAND 34 +#define CLK_BUS_DRAM 35 +#define CLK_BUS_EMAC 36 +#define CLK_BUS_TS 37 +#define CLK_BUS_HSTIMER 38 +#define CLK_BUS_SPI0 39 +#define CLK_BUS_SPI1 40 +#define CLK_BUS_OTG 41 +#define CLK_BUS_EHCI0 42 +#define CLK_BUS_EHCI1 43 +#define CLK_BUS_OHCI0 44 +#define CLK_BUS_OHCI1 45 +#define CLK_BUS_VE 46 +#define CLK_BUS_TCON0 47 +#define CLK_BUS_TCON1 48 +#define CLK_BUS_DEINTERLACE 49 +#define CLK_BUS_CSI 50 +#define CLK_BUS_HDMI 51 +#define CLK_BUS_DE 52 +#define CLK_BUS_GPU 53 +#define CLK_BUS_MSGBOX 54 +#define CLK_BUS_SPINLOCK 55 +#define CLK_BUS_CODEC 56 +#define CLK_BUS_SPDIF 57 +#define CLK_BUS_PIO 58 +#define CLK_BUS_THS 59 +#define CLK_BUS_I2S0 60 +#define CLK_BUS_I2S1 61 +#define CLK_BUS_I2S2 62 +#define CLK_BUS_I2C0 63 +#define CLK_BUS_I2C1 64 +#define CLK_BUS_I2C2 65 +#define CLK_BUS_SCR 66 +#define CLK_BUS_UART0 67 +#define CLK_BUS_UART1 68 +#define CLK_BUS_UART2 69 +#define CLK_BUS_UART3 70 +#define CLK_BUS_UART4 71 +#define CLK_BUS_DBG 72 +#define CLK_THS 73 +#define CLK_NAND 74 +#define CLK_MMC0 75 +#define CLK_MMC1 76 +#define CLK_MMC2 77 +#define CLK_TS 78 +#define CLK_CE 79 +#define CLK_SPI0 80 +#define CLK_SPI1 81 +#define CLK_I2S0 82 +#define CLK_I2S1 83 +#define CLK_I2S2 84 +#define CLK_SPDIF 85 +#define CLK_USB_PHY0 86 +#define CLK_USB_PHY1 87 +#define CLK_USB_HSIC 88 +#define CLK_USB_HSIC_12M 89 + +#define CLK_USB_OHCI0 91 + +#define CLK_USB_OHCI1 93 + +#define CLK_DRAM_VE 95 +#define CLK_DRAM_CSI 96 +#define CLK_DRAM_DEINTERLACE 97 +#define CLK_DRAM_TS 98 +#define CLK_DE 99 +#define CLK_TCON0 100 +#define CLK_TCON1 101 +#define CLK_DEINTERLACE 102 +#define CLK_CSI_MISC 103 +#define CLK_CSI_SCLK 104 +#define CLK_CSI_MCLK 105 +#define CLK_VE 106 +#define CLK_AC_DIG 107 +#define CLK_AC_DIG_4X 108 +#define CLK_AVS 109 +#define CLK_HDMI 110 +#define CLK_HDMI_DDC 111 +#define CLK_MBUS 112 +#define CLK_DSI_DPHY 113 +#define CLK_GPU 114 + +#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun50i-h6-ccu.h b/roms/u-boot/include/dt-bindings/clock/sun50i-h6-ccu.h new file mode 100644 index 000000000..a1545cd60 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun50i-h6-ccu.h @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2017 Icenowy Zheng + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_ +#define _DT_BINDINGS_CLK_SUN50I_H6_H_ + +#define CLK_PLL_PERIPH0 3 + +#define CLK_CPUX 21 + +#define CLK_APB1 26 + +#define CLK_DE 29 +#define CLK_BUS_DE 30 +#define CLK_DEINTERLACE 31 +#define CLK_BUS_DEINTERLACE 32 +#define CLK_GPU 33 +#define CLK_BUS_GPU 34 +#define CLK_CE 35 +#define CLK_BUS_CE 36 +#define CLK_VE 37 +#define CLK_BUS_VE 38 +#define CLK_EMCE 39 +#define CLK_BUS_EMCE 40 +#define CLK_VP9 41 +#define CLK_BUS_VP9 42 +#define CLK_BUS_DMA 43 +#define CLK_BUS_MSGBOX 44 +#define CLK_BUS_SPINLOCK 45 +#define CLK_BUS_HSTIMER 46 +#define CLK_AVS 47 +#define CLK_BUS_DBG 48 +#define CLK_BUS_PSI 49 +#define CLK_BUS_PWM 50 +#define CLK_BUS_IOMMU 51 + +#define CLK_MBUS_DMA 53 +#define CLK_MBUS_VE 54 +#define CLK_MBUS_CE 55 +#define CLK_MBUS_TS 56 +#define CLK_MBUS_NAND 57 +#define CLK_MBUS_CSI 58 +#define CLK_MBUS_DEINTERLACE 59 + +#define CLK_NAND0 61 +#define CLK_NAND1 62 +#define CLK_BUS_NAND 63 +#define CLK_MMC0 64 +#define CLK_MMC1 65 +#define CLK_MMC2 66 +#define CLK_BUS_MMC0 67 +#define CLK_BUS_MMC1 68 +#define CLK_BUS_MMC2 69 +#define CLK_BUS_UART0 70 +#define CLK_BUS_UART1 71 +#define CLK_BUS_UART2 72 +#define CLK_BUS_UART3 73 +#define CLK_BUS_I2C0 74 +#define CLK_BUS_I2C1 75 +#define CLK_BUS_I2C2 76 +#define CLK_BUS_I2C3 77 +#define CLK_BUS_SCR0 78 +#define CLK_BUS_SCR1 79 +#define CLK_SPI0 80 +#define CLK_SPI1 81 +#define CLK_BUS_SPI0 82 +#define CLK_BUS_SPI1 83 +#define CLK_BUS_EMAC 84 +#define CLK_TS 85 +#define CLK_BUS_TS 86 +#define CLK_IR_TX 87 +#define CLK_BUS_IR_TX 88 +#define CLK_BUS_THS 89 +#define CLK_I2S3 90 +#define CLK_I2S0 91 +#define CLK_I2S1 92 +#define CLK_I2S2 93 +#define CLK_BUS_I2S0 94 +#define CLK_BUS_I2S1 95 +#define CLK_BUS_I2S2 96 +#define CLK_BUS_I2S3 97 +#define CLK_SPDIF 98 +#define CLK_BUS_SPDIF 99 +#define CLK_DMIC 100 +#define CLK_BUS_DMIC 101 +#define CLK_AUDIO_HUB 102 +#define CLK_BUS_AUDIO_HUB 103 +#define CLK_USB_OHCI0 104 +#define CLK_USB_PHY0 105 +#define CLK_USB_PHY1 106 +#define CLK_USB_OHCI3 107 +#define CLK_USB_PHY3 108 +#define CLK_USB_HSIC_12M 109 +#define CLK_USB_HSIC 110 +#define CLK_BUS_OHCI0 111 +#define CLK_BUS_OHCI3 112 +#define CLK_BUS_EHCI0 113 +#define CLK_BUS_XHCI 114 +#define CLK_BUS_EHCI3 115 +#define CLK_BUS_OTG 116 +#define CLK_PCIE_REF_100M 117 +#define CLK_PCIE_REF 118 +#define CLK_PCIE_REF_OUT 119 +#define CLK_PCIE_MAXI 120 +#define CLK_PCIE_AUX 121 +#define CLK_BUS_PCIE 122 +#define CLK_HDMI 123 +#define CLK_HDMI_SLOW 124 +#define CLK_HDMI_CEC 125 +#define CLK_BUS_HDMI 126 +#define CLK_BUS_TCON_TOP 127 +#define CLK_TCON_LCD0 128 +#define CLK_BUS_TCON_LCD0 129 +#define CLK_TCON_TV0 130 +#define CLK_BUS_TCON_TV0 131 +#define CLK_CSI_CCI 132 +#define CLK_CSI_TOP 133 +#define CLK_CSI_MCLK 134 +#define CLK_BUS_CSI 135 +#define CLK_HDCP 136 +#define CLK_BUS_HDCP 137 + +#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/roms/u-boot/include/dt-bindings/clock/sun50i-h6-r-ccu.h new file mode 100644 index 000000000..890368d25 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun50i-h6-r-ccu.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017 Icenowy Zheng + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ + +#define CLK_AR100 0 + +#define CLK_R_APB1 2 + +#define CLK_R_APB1_TIMER 4 +#define CLK_R_APB1_TWD 5 +#define CLK_R_APB1_PWM 6 +#define CLK_R_APB2_UART 7 +#define CLK_R_APB2_I2C 8 +#define CLK_R_APB1_IR 9 +#define CLK_R_APB1_W1 10 + +#define CLK_IR 11 +#define CLK_W1 12 + +#define CLK_R_APB2_RSB 13 + +#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun50i-h616-ccu.h b/roms/u-boot/include/dt-bindings/clock/sun50i-h616-ccu.h new file mode 100644 index 000000000..4fc08b0df --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2020 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_H616_H_ +#define _DT_BINDINGS_CLK_SUN50I_H616_H_ + +#define CLK_PLL_PERIPH0 4 + +#define CLK_CPUX 21 + +#define CLK_APB1 26 + +#define CLK_DE 29 +#define CLK_BUS_DE 30 +#define CLK_DEINTERLACE 31 +#define CLK_BUS_DEINTERLACE 32 +#define CLK_G2D 33 +#define CLK_BUS_G2D 34 +#define CLK_GPU0 35 +#define CLK_BUS_GPU 36 +#define CLK_GPU1 37 +#define CLK_CE 38 +#define CLK_BUS_CE 39 +#define CLK_VE 40 +#define CLK_BUS_VE 41 +#define CLK_BUS_DMA 42 +#define CLK_BUS_HSTIMER 43 +#define CLK_AVS 44 +#define CLK_BUS_DBG 45 +#define CLK_BUS_PSI 46 +#define CLK_BUS_PWM 47 +#define CLK_BUS_IOMMU 48 + +#define CLK_MBUS_DMA 50 +#define CLK_MBUS_VE 51 +#define CLK_MBUS_CE 52 +#define CLK_MBUS_TS 53 +#define CLK_MBUS_NAND 54 +#define CLK_MBUS_G2D 55 + +#define CLK_NAND0 57 +#define CLK_NAND1 58 +#define CLK_BUS_NAND 59 +#define CLK_MMC0 60 +#define CLK_MMC1 61 +#define CLK_MMC2 62 +#define CLK_BUS_MMC0 63 +#define CLK_BUS_MMC1 64 +#define CLK_BUS_MMC2 65 +#define CLK_BUS_UART0 66 +#define CLK_BUS_UART1 67 +#define CLK_BUS_UART2 68 +#define CLK_BUS_UART3 69 +#define CLK_BUS_UART4 70 +#define CLK_BUS_UART5 71 +#define CLK_BUS_I2C0 72 +#define CLK_BUS_I2C1 73 +#define CLK_BUS_I2C2 74 +#define CLK_BUS_I2C3 75 +#define CLK_BUS_I2C4 76 +#define CLK_SPI0 77 +#define CLK_SPI1 78 +#define CLK_BUS_SPI0 79 +#define CLK_BUS_SPI1 80 +#define CLK_EMAC_25M 81 +#define CLK_BUS_EMAC0 82 +#define CLK_BUS_EMAC1 83 +#define CLK_TS 84 +#define CLK_BUS_TS 85 +#define CLK_BUS_THS 86 +#define CLK_SPDIF 87 +#define CLK_BUS_SPDIF 88 +#define CLK_DMIC 89 +#define CLK_BUS_DMIC 90 +#define CLK_AUDIO_CODEC_1X 91 +#define CLK_AUDIO_CODEC_4X 92 +#define CLK_BUS_AUDIO_CODEC 93 +#define CLK_AUDIO_HUB 94 +#define CLK_BUS_AUDIO_HUB 95 +#define CLK_USB_OHCI0 96 +#define CLK_USB_PHY0 97 +#define CLK_USB_OHCI1 98 +#define CLK_USB_PHY1 99 +#define CLK_USB_OHCI2 100 +#define CLK_USB_PHY2 101 +#define CLK_USB_OHCI3 102 +#define CLK_USB_PHY3 103 +#define CLK_BUS_OHCI0 104 +#define CLK_BUS_OHCI1 105 +#define CLK_BUS_OHCI2 106 +#define CLK_BUS_OHCI3 107 +#define CLK_BUS_EHCI0 108 +#define CLK_BUS_EHCI1 109 +#define CLK_BUS_EHCI2 110 +#define CLK_BUS_EHCI3 111 +#define CLK_BUS_OTG 112 +#define CLK_BUS_KEYADC 113 +#define CLK_HDMI 114 +#define CLK_HDMI_SLOW 115 +#define CLK_HDMI_CEC 116 +#define CLK_BUS_HDMI 117 +#define CLK_BUS_TCON_TOP 118 +#define CLK_TCON_TV0 119 +#define CLK_TCON_TV1 120 +#define CLK_BUS_TCON_TV0 121 +#define CLK_BUS_TCON_TV1 122 +#define CLK_TVE0 123 +#define CLK_BUS_TVE_TOP 124 +#define CLK_BUS_TVE0 125 +#define CLK_HDCP 126 +#define CLK_BUS_HDCP 127 + +#endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun5i-ccu.h b/roms/u-boot/include/dt-bindings/clock/sun5i-ccu.h new file mode 100644 index 000000000..81f34d477 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun5i-ccu.h @@ -0,0 +1,106 @@ +/* + * Copyright 2016 Maxime Ripard + * + * Maxime Ripard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_SUN5I_H_ +#define _DT_BINDINGS_CLK_SUN5I_H_ + +#define CLK_HOSC 1 + +#define CLK_PLL_VIDEO0_2X 9 + +#define CLK_PLL_VIDEO1_2X 16 +#define CLK_CPU 17 + +#define CLK_AHB_OTG 23 +#define CLK_AHB_EHCI 24 +#define CLK_AHB_OHCI 25 +#define CLK_AHB_SS 26 +#define CLK_AHB_DMA 27 +#define CLK_AHB_BIST 28 +#define CLK_AHB_MMC0 29 +#define CLK_AHB_MMC1 30 +#define CLK_AHB_MMC2 31 +#define CLK_AHB_NAND 32 +#define CLK_AHB_SDRAM 33 +#define CLK_AHB_EMAC 34 +#define CLK_AHB_TS 35 +#define CLK_AHB_SPI0 36 +#define CLK_AHB_SPI1 37 +#define CLK_AHB_SPI2 38 +#define CLK_AHB_GPS 39 +#define CLK_AHB_HSTIMER 40 +#define CLK_AHB_VE 41 +#define CLK_AHB_TVE 42 +#define CLK_AHB_LCD 43 +#define CLK_AHB_CSI 44 +#define CLK_AHB_HDMI 45 +#define CLK_AHB_DE_BE 46 +#define CLK_AHB_DE_FE 47 +#define CLK_AHB_IEP 48 +#define CLK_AHB_GPU 49 +#define CLK_APB0_CODEC 50 +#define CLK_APB0_SPDIF 51 +#define CLK_APB0_I2S 52 +#define CLK_APB0_PIO 53 +#define CLK_APB0_IR 54 +#define CLK_APB0_KEYPAD 55 +#define CLK_APB1_I2C0 56 +#define CLK_APB1_I2C1 57 +#define CLK_APB1_I2C2 58 +#define CLK_APB1_UART0 59 +#define CLK_APB1_UART1 60 +#define CLK_APB1_UART2 61 +#define CLK_APB1_UART3 62 +#define CLK_NAND 63 +#define CLK_MMC0 64 +#define CLK_MMC1 65 +#define CLK_MMC2 66 +#define CLK_TS 67 +#define CLK_SS 68 +#define CLK_SPI0 69 +#define CLK_SPI1 70 +#define CLK_SPI2 71 +#define CLK_IR 72 +#define CLK_I2S 73 +#define CLK_SPDIF 74 +#define CLK_KEYPAD 75 +#define CLK_USB_OHCI 76 +#define CLK_USB_PHY0 77 +#define CLK_USB_PHY1 78 +#define CLK_GPS 79 +#define CLK_DRAM_VE 80 +#define CLK_DRAM_CSI 81 +#define CLK_DRAM_TS 82 +#define CLK_DRAM_TVE 83 +#define CLK_DRAM_DE_FE 84 +#define CLK_DRAM_DE_BE 85 +#define CLK_DRAM_ACE 86 +#define CLK_DRAM_IEP 87 +#define CLK_DE_BE 88 +#define CLK_DE_FE 89 +#define CLK_TCON_CH0 90 + +#define CLK_TCON_CH1 92 +#define CLK_CSI 93 +#define CLK_VE 94 +#define CLK_CODEC 95 +#define CLK_AVS 96 +#define CLK_HDMI 97 +#define CLK_GPU 98 + +#define CLK_IEP 100 + +#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun6i-a31-ccu.h b/roms/u-boot/include/dt-bindings/clock/sun6i-a31-ccu.h new file mode 100644 index 000000000..c5d133401 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun6i-a31-ccu.h @@ -0,0 +1,191 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_ +#define _DT_BINDINGS_CLK_SUN6I_A31_H_ + +#define CLK_PLL_VIDEO0_2X 7 + +#define CLK_PLL_PERIPH 10 + +#define CLK_PLL_VIDEO1_2X 13 + +#define CLK_CPU 18 + +#define CLK_AHB1_MIPIDSI 23 +#define CLK_AHB1_SS 24 +#define CLK_AHB1_DMA 25 +#define CLK_AHB1_MMC0 26 +#define CLK_AHB1_MMC1 27 +#define CLK_AHB1_MMC2 28 +#define CLK_AHB1_MMC3 29 +#define CLK_AHB1_NAND1 30 +#define CLK_AHB1_NAND0 31 +#define CLK_AHB1_SDRAM 32 +#define CLK_AHB1_EMAC 33 +#define CLK_AHB1_TS 34 +#define CLK_AHB1_HSTIMER 35 +#define CLK_AHB1_SPI0 36 +#define CLK_AHB1_SPI1 37 +#define CLK_AHB1_SPI2 38 +#define CLK_AHB1_SPI3 39 +#define CLK_AHB1_OTG 40 +#define CLK_AHB1_EHCI0 41 +#define CLK_AHB1_EHCI1 42 +#define CLK_AHB1_OHCI0 43 +#define CLK_AHB1_OHCI1 44 +#define CLK_AHB1_OHCI2 45 +#define CLK_AHB1_VE 46 +#define CLK_AHB1_LCD0 47 +#define CLK_AHB1_LCD1 48 +#define CLK_AHB1_CSI 49 +#define CLK_AHB1_HDMI 50 +#define CLK_AHB1_BE0 51 +#define CLK_AHB1_BE1 52 +#define CLK_AHB1_FE0 53 +#define CLK_AHB1_FE1 54 +#define CLK_AHB1_MP 55 +#define CLK_AHB1_GPU 56 +#define CLK_AHB1_DEU0 57 +#define CLK_AHB1_DEU1 58 +#define CLK_AHB1_DRC0 59 +#define CLK_AHB1_DRC1 60 + +#define CLK_APB1_CODEC 61 +#define CLK_APB1_SPDIF 62 +#define CLK_APB1_DIGITAL_MIC 63 +#define CLK_APB1_PIO 64 +#define CLK_APB1_DAUDIO0 65 +#define CLK_APB1_DAUDIO1 66 + +#define CLK_APB2_I2C0 67 +#define CLK_APB2_I2C1 68 +#define CLK_APB2_I2C2 69 +#define CLK_APB2_I2C3 70 +#define CLK_APB2_UART0 71 +#define CLK_APB2_UART1 72 +#define CLK_APB2_UART2 73 +#define CLK_APB2_UART3 74 +#define CLK_APB2_UART4 75 +#define CLK_APB2_UART5 76 + +#define CLK_NAND0 77 +#define CLK_NAND1 78 +#define CLK_MMC0 79 +#define CLK_MMC0_SAMPLE 80 +#define CLK_MMC0_OUTPUT 81 +#define CLK_MMC1 82 +#define CLK_MMC1_SAMPLE 83 +#define CLK_MMC1_OUTPUT 84 +#define CLK_MMC2 85 +#define CLK_MMC2_SAMPLE 86 +#define CLK_MMC2_OUTPUT 87 +#define CLK_MMC3 88 +#define CLK_MMC3_SAMPLE 89 +#define CLK_MMC3_OUTPUT 90 +#define CLK_TS 91 +#define CLK_SS 92 +#define CLK_SPI0 93 +#define CLK_SPI1 94 +#define CLK_SPI2 95 +#define CLK_SPI3 96 +#define CLK_DAUDIO0 97 +#define CLK_DAUDIO1 98 +#define CLK_SPDIF 99 +#define CLK_USB_PHY0 100 +#define CLK_USB_PHY1 101 +#define CLK_USB_PHY2 102 +#define CLK_USB_OHCI0 103 +#define CLK_USB_OHCI1 104 +#define CLK_USB_OHCI2 105 + +#define CLK_DRAM_VE 110 +#define CLK_DRAM_CSI_ISP 111 +#define CLK_DRAM_TS 112 +#define CLK_DRAM_DRC0 113 +#define CLK_DRAM_DRC1 114 +#define CLK_DRAM_DEU0 115 +#define CLK_DRAM_DEU1 116 +#define CLK_DRAM_FE0 117 +#define CLK_DRAM_FE1 118 +#define CLK_DRAM_BE0 119 +#define CLK_DRAM_BE1 120 +#define CLK_DRAM_MP 121 + +#define CLK_BE0 122 +#define CLK_BE1 123 +#define CLK_FE0 124 +#define CLK_FE1 125 +#define CLK_MP 126 +#define CLK_LCD0_CH0 127 +#define CLK_LCD1_CH0 128 +#define CLK_LCD0_CH1 129 +#define CLK_LCD1_CH1 130 +#define CLK_CSI0_SCLK 131 +#define CLK_CSI0_MCLK 132 +#define CLK_CSI1_MCLK 133 +#define CLK_VE 134 +#define CLK_CODEC 135 +#define CLK_AVS 136 +#define CLK_DIGITAL_MIC 137 +#define CLK_HDMI 138 +#define CLK_HDMI_DDC 139 +#define CLK_PS 140 + +#define CLK_MIPI_DSI 143 +#define CLK_MIPI_DSI_DPHY 144 +#define CLK_MIPI_CSI_DPHY 145 +#define CLK_IEP_DRC0 146 +#define CLK_IEP_DRC1 147 +#define CLK_IEP_DEU0 148 +#define CLK_IEP_DEU1 149 +#define CLK_GPU_CORE 150 +#define CLK_GPU_MEMORY 151 +#define CLK_GPU_HYD 152 +#define CLK_ATS 153 +#define CLK_TRACE 154 + +#define CLK_OUT_A 155 +#define CLK_OUT_B 156 +#define CLK_OUT_C 157 + +#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun7i-a20-ccu.h b/roms/u-boot/include/dt-bindings/clock/sun7i-a20-ccu.h new file mode 100644 index 000000000..045a5178d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun7i-a20-ccu.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2017 Priit Laes + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_ +#define _DT_BINDINGS_CLK_SUN7I_A20_H_ + +#include + +#define CLK_MBUS 166 +#define CLK_HDMI1_SLOW 167 +#define CLK_HDMI1 168 +#define CLK_OUT_A 169 +#define CLK_OUT_B 170 + +#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun8i-a23-a33-ccu.h b/roms/u-boot/include/dt-bindings/clock/sun8i-a23-a33-ccu.h new file mode 100644 index 000000000..f8222b6b2 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun8i-a23-a33-ccu.h @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2016 Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ +#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ + +#define CLK_CPUX 18 + +#define CLK_BUS_MIPI_DSI 23 +#define CLK_BUS_SS 24 +#define CLK_BUS_DMA 25 +#define CLK_BUS_MMC0 26 +#define CLK_BUS_MMC1 27 +#define CLK_BUS_MMC2 28 +#define CLK_BUS_NAND 29 +#define CLK_BUS_DRAM 30 +#define CLK_BUS_HSTIMER 31 +#define CLK_BUS_SPI0 32 +#define CLK_BUS_SPI1 33 +#define CLK_BUS_OTG 34 +#define CLK_BUS_EHCI 35 +#define CLK_BUS_OHCI 36 +#define CLK_BUS_VE 37 +#define CLK_BUS_LCD 38 +#define CLK_BUS_CSI 39 +#define CLK_BUS_DE_BE 40 +#define CLK_BUS_DE_FE 41 +#define CLK_BUS_GPU 42 +#define CLK_BUS_MSGBOX 43 +#define CLK_BUS_SPINLOCK 44 +#define CLK_BUS_DRC 45 +#define CLK_BUS_SAT 46 +#define CLK_BUS_CODEC 47 +#define CLK_BUS_PIO 48 +#define CLK_BUS_I2S0 49 +#define CLK_BUS_I2S1 50 +#define CLK_BUS_I2C0 51 +#define CLK_BUS_I2C1 52 +#define CLK_BUS_I2C2 53 +#define CLK_BUS_UART0 54 +#define CLK_BUS_UART1 55 +#define CLK_BUS_UART2 56 +#define CLK_BUS_UART3 57 +#define CLK_BUS_UART4 58 +#define CLK_NAND 59 +#define CLK_MMC0 60 +#define CLK_MMC0_SAMPLE 61 +#define CLK_MMC0_OUTPUT 62 +#define CLK_MMC1 63 +#define CLK_MMC1_SAMPLE 64 +#define CLK_MMC1_OUTPUT 65 +#define CLK_MMC2 66 +#define CLK_MMC2_SAMPLE 67 +#define CLK_MMC2_OUTPUT 68 +#define CLK_SS 69 +#define CLK_SPI0 70 +#define CLK_SPI1 71 +#define CLK_I2S0 72 +#define CLK_I2S1 73 +#define CLK_USB_PHY0 74 +#define CLK_USB_PHY1 75 +#define CLK_USB_HSIC 76 +#define CLK_USB_HSIC_12M 77 +#define CLK_USB_OHCI 78 + +#define CLK_DRAM_VE 80 +#define CLK_DRAM_CSI 81 +#define CLK_DRAM_DRC 82 +#define CLK_DRAM_DE_FE 83 +#define CLK_DRAM_DE_BE 84 +#define CLK_DE_BE 85 +#define CLK_DE_FE 86 +#define CLK_LCD_CH0 87 +#define CLK_LCD_CH1 88 +#define CLK_CSI_SCLK 89 +#define CLK_CSI_MCLK 90 +#define CLK_VE 91 +#define CLK_AC_DIG 92 +#define CLK_AC_DIG_4X 93 +#define CLK_AVS 94 + +#define CLK_DSI_SCLK 96 +#define CLK_DSI_DPHY 97 +#define CLK_DRC 98 +#define CLK_GPU 99 +#define CLK_ATS 100 + +#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun8i-a83t-ccu.h b/roms/u-boot/include/dt-bindings/clock/sun8i-a83t-ccu.h new file mode 100644 index 000000000..78af5085f --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun8i-a83t-ccu.h @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2017 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ +#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ + +#define CLK_PLL_PERIPH 6 + +#define CLK_PLL_DE 9 + +#define CLK_C0CPUX 11 +#define CLK_C1CPUX 12 + +#define CLK_BUS_MIPI_DSI 19 +#define CLK_BUS_SS 20 +#define CLK_BUS_DMA 21 +#define CLK_BUS_MMC0 22 +#define CLK_BUS_MMC1 23 +#define CLK_BUS_MMC2 24 +#define CLK_BUS_NAND 25 +#define CLK_BUS_DRAM 26 +#define CLK_BUS_EMAC 27 +#define CLK_BUS_HSTIMER 28 +#define CLK_BUS_SPI0 29 +#define CLK_BUS_SPI1 30 +#define CLK_BUS_OTG 31 +#define CLK_BUS_EHCI0 32 +#define CLK_BUS_EHCI1 33 +#define CLK_BUS_OHCI0 34 + +#define CLK_BUS_VE 35 +#define CLK_BUS_TCON0 36 +#define CLK_BUS_TCON1 37 +#define CLK_BUS_CSI 38 +#define CLK_BUS_HDMI 39 +#define CLK_BUS_DE 40 +#define CLK_BUS_GPU 41 +#define CLK_BUS_MSGBOX 42 +#define CLK_BUS_SPINLOCK 43 + +#define CLK_BUS_SPDIF 44 +#define CLK_BUS_PIO 45 +#define CLK_BUS_I2S0 46 +#define CLK_BUS_I2S1 47 +#define CLK_BUS_I2S2 48 +#define CLK_BUS_TDM 49 + +#define CLK_BUS_I2C0 50 +#define CLK_BUS_I2C1 51 +#define CLK_BUS_I2C2 52 +#define CLK_BUS_UART0 53 +#define CLK_BUS_UART1 54 +#define CLK_BUS_UART2 55 +#define CLK_BUS_UART3 56 +#define CLK_BUS_UART4 57 + +#define CLK_NAND 59 +#define CLK_MMC0 60 +#define CLK_MMC0_SAMPLE 61 +#define CLK_MMC0_OUTPUT 62 +#define CLK_MMC1 63 +#define CLK_MMC1_SAMPLE 64 +#define CLK_MMC1_OUTPUT 65 +#define CLK_MMC2 66 +#define CLK_MMC2_SAMPLE 67 +#define CLK_MMC2_OUTPUT 68 +#define CLK_SS 69 +#define CLK_SPI0 70 +#define CLK_SPI1 71 +#define CLK_I2S0 72 +#define CLK_I2S1 73 +#define CLK_I2S2 74 +#define CLK_TDM 75 +#define CLK_SPDIF 76 +#define CLK_USB_PHY0 77 +#define CLK_USB_PHY1 78 +#define CLK_USB_HSIC 79 +#define CLK_USB_HSIC_12M 80 +#define CLK_USB_OHCI0 81 + +#define CLK_DRAM_VE 83 +#define CLK_DRAM_CSI 84 + +#define CLK_TCON0 85 +#define CLK_TCON1 86 +#define CLK_CSI_MISC 87 +#define CLK_MIPI_CSI 88 +#define CLK_CSI_MCLK 89 +#define CLK_CSI_SCLK 90 +#define CLK_VE 91 +#define CLK_AVS 92 +#define CLK_HDMI 93 +#define CLK_HDMI_SLOW 94 + +#define CLK_MIPI_DSI0 96 +#define CLK_MIPI_DSI1 97 +#define CLK_GPU_CORE 98 +#define CLK_GPU_MEMORY 99 +#define CLK_GPU_HYD 100 + +#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun8i-de2.h b/roms/u-boot/include/dt-bindings/clock/sun8i-de2.h new file mode 100644 index 000000000..7768f73b0 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun8i-de2.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Icenowy Zheng + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ +#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ + +#define CLK_BUS_MIXER0 0 +#define CLK_BUS_MIXER1 1 +#define CLK_BUS_WB 2 + +#define CLK_MIXER0 6 +#define CLK_MIXER1 7 +#define CLK_WB 8 + +#define CLK_BUS_ROT 9 +#define CLK_ROT 10 + +#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun8i-h3-ccu.h b/roms/u-boot/include/dt-bindings/clock/sun8i-h3-ccu.h new file mode 100644 index 000000000..30d2d1537 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun8i-h3-ccu.h @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2016 Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_ +#define _DT_BINDINGS_CLK_SUN8I_H3_H_ + +#define CLK_PLL_VIDEO 6 + +#define CLK_PLL_PERIPH0 9 + +#define CLK_CPUX 14 + +#define CLK_BUS_CE 20 +#define CLK_BUS_DMA 21 +#define CLK_BUS_MMC0 22 +#define CLK_BUS_MMC1 23 +#define CLK_BUS_MMC2 24 +#define CLK_BUS_NAND 25 +#define CLK_BUS_DRAM 26 +#define CLK_BUS_EMAC 27 +#define CLK_BUS_TS 28 +#define CLK_BUS_HSTIMER 29 +#define CLK_BUS_SPI0 30 +#define CLK_BUS_SPI1 31 +#define CLK_BUS_OTG 32 +#define CLK_BUS_EHCI0 33 +#define CLK_BUS_EHCI1 34 +#define CLK_BUS_EHCI2 35 +#define CLK_BUS_EHCI3 36 +#define CLK_BUS_OHCI0 37 +#define CLK_BUS_OHCI1 38 +#define CLK_BUS_OHCI2 39 +#define CLK_BUS_OHCI3 40 +#define CLK_BUS_VE 41 +#define CLK_BUS_TCON0 42 +#define CLK_BUS_TCON1 43 +#define CLK_BUS_DEINTERLACE 44 +#define CLK_BUS_CSI 45 +#define CLK_BUS_TVE 46 +#define CLK_BUS_HDMI 47 +#define CLK_BUS_DE 48 +#define CLK_BUS_GPU 49 +#define CLK_BUS_MSGBOX 50 +#define CLK_BUS_SPINLOCK 51 +#define CLK_BUS_CODEC 52 +#define CLK_BUS_SPDIF 53 +#define CLK_BUS_PIO 54 +#define CLK_BUS_THS 55 +#define CLK_BUS_I2S0 56 +#define CLK_BUS_I2S1 57 +#define CLK_BUS_I2S2 58 +#define CLK_BUS_I2C0 59 +#define CLK_BUS_I2C1 60 +#define CLK_BUS_I2C2 61 +#define CLK_BUS_UART0 62 +#define CLK_BUS_UART1 63 +#define CLK_BUS_UART2 64 +#define CLK_BUS_UART3 65 +#define CLK_BUS_SCR0 66 +#define CLK_BUS_EPHY 67 +#define CLK_BUS_DBG 68 + +#define CLK_THS 69 +#define CLK_NAND 70 +#define CLK_MMC0 71 +#define CLK_MMC0_SAMPLE 72 +#define CLK_MMC0_OUTPUT 73 +#define CLK_MMC1 74 +#define CLK_MMC1_SAMPLE 75 +#define CLK_MMC1_OUTPUT 76 +#define CLK_MMC2 77 +#define CLK_MMC2_SAMPLE 78 +#define CLK_MMC2_OUTPUT 79 +#define CLK_TS 80 +#define CLK_CE 81 +#define CLK_SPI0 82 +#define CLK_SPI1 83 +#define CLK_I2S0 84 +#define CLK_I2S1 85 +#define CLK_I2S2 86 +#define CLK_SPDIF 87 +#define CLK_USB_PHY0 88 +#define CLK_USB_PHY1 89 +#define CLK_USB_PHY2 90 +#define CLK_USB_PHY3 91 +#define CLK_USB_OHCI0 92 +#define CLK_USB_OHCI1 93 +#define CLK_USB_OHCI2 94 +#define CLK_USB_OHCI3 95 + +#define CLK_DRAM_VE 97 +#define CLK_DRAM_CSI 98 +#define CLK_DRAM_DEINTERLACE 99 +#define CLK_DRAM_TS 100 +#define CLK_DE 101 +#define CLK_TCON0 102 +#define CLK_TVE 103 +#define CLK_DEINTERLACE 104 +#define CLK_CSI_MISC 105 +#define CLK_CSI_SCLK 106 +#define CLK_CSI_MCLK 107 +#define CLK_VE 108 +#define CLK_AC_DIG 109 +#define CLK_AVS 110 +#define CLK_HDMI 111 +#define CLK_HDMI_DDC 112 +#define CLK_MBUS 113 +#define CLK_GPU 114 + +/* New clocks imported in H5 */ +#define CLK_BUS_SCR1 115 + +#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun8i-r-ccu.h b/roms/u-boot/include/dt-bindings/clock/sun8i-r-ccu.h new file mode 100644 index 000000000..779d20aa0 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun8i-r-ccu.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2016 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ + +#define CLK_AR100 0 + +#define CLK_APB0_PIO 3 +#define CLK_APB0_IR 4 +#define CLK_APB0_TIMER 5 +#define CLK_APB0_RSB 6 +#define CLK_APB0_UART 7 +/* 8 is reserved for CLK_APB0_W1 on A31 */ +#define CLK_APB0_I2C 9 +#define CLK_APB0_TWD 10 + +#define CLK_IR 11 + +#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun8i-r40-ccu.h b/roms/u-boot/include/dt-bindings/clock/sun8i-r40-ccu.h new file mode 100644 index 000000000..d7337b55a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun8i-r40-ccu.h @@ -0,0 +1,191 @@ +/* + * Copyright (C) 2017 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_ +#define _DT_BINDINGS_CLK_SUN8I_R40_H_ + +#define CLK_PLL_VIDEO0 7 + +#define CLK_PLL_VIDEO1 16 + +#define CLK_CPU 24 + +#define CLK_BUS_MIPI_DSI 29 +#define CLK_BUS_CE 30 +#define CLK_BUS_DMA 31 +#define CLK_BUS_MMC0 32 +#define CLK_BUS_MMC1 33 +#define CLK_BUS_MMC2 34 +#define CLK_BUS_MMC3 35 +#define CLK_BUS_NAND 36 +#define CLK_BUS_DRAM 37 +#define CLK_BUS_EMAC 38 +#define CLK_BUS_TS 39 +#define CLK_BUS_HSTIMER 40 +#define CLK_BUS_SPI0 41 +#define CLK_BUS_SPI1 42 +#define CLK_BUS_SPI2 43 +#define CLK_BUS_SPI3 44 +#define CLK_BUS_SATA 45 +#define CLK_BUS_OTG 46 +#define CLK_BUS_EHCI0 47 +#define CLK_BUS_EHCI1 48 +#define CLK_BUS_EHCI2 49 +#define CLK_BUS_OHCI0 50 +#define CLK_BUS_OHCI1 51 +#define CLK_BUS_OHCI2 52 +#define CLK_BUS_VE 53 +#define CLK_BUS_MP 54 +#define CLK_BUS_DEINTERLACE 55 +#define CLK_BUS_CSI0 56 +#define CLK_BUS_CSI1 57 +#define CLK_BUS_HDMI1 58 +#define CLK_BUS_HDMI0 59 +#define CLK_BUS_DE 60 +#define CLK_BUS_TVE0 61 +#define CLK_BUS_TVE1 62 +#define CLK_BUS_TVE_TOP 63 +#define CLK_BUS_GMAC 64 +#define CLK_BUS_GPU 65 +#define CLK_BUS_TVD0 66 +#define CLK_BUS_TVD1 67 +#define CLK_BUS_TVD2 68 +#define CLK_BUS_TVD3 69 +#define CLK_BUS_TVD_TOP 70 +#define CLK_BUS_TCON_LCD0 71 +#define CLK_BUS_TCON_LCD1 72 +#define CLK_BUS_TCON_TV0 73 +#define CLK_BUS_TCON_TV1 74 +#define CLK_BUS_TCON_TOP 75 +#define CLK_BUS_CODEC 76 +#define CLK_BUS_SPDIF 77 +#define CLK_BUS_AC97 78 +#define CLK_BUS_PIO 79 +#define CLK_BUS_IR0 80 +#define CLK_BUS_IR1 81 +#define CLK_BUS_THS 82 +#define CLK_BUS_KEYPAD 83 +#define CLK_BUS_I2S0 84 +#define CLK_BUS_I2S1 85 +#define CLK_BUS_I2S2 86 +#define CLK_BUS_I2C0 87 +#define CLK_BUS_I2C1 88 +#define CLK_BUS_I2C2 89 +#define CLK_BUS_I2C3 90 +#define CLK_BUS_CAN 91 +#define CLK_BUS_SCR 92 +#define CLK_BUS_PS20 93 +#define CLK_BUS_PS21 94 +#define CLK_BUS_I2C4 95 +#define CLK_BUS_UART0 96 +#define CLK_BUS_UART1 97 +#define CLK_BUS_UART2 98 +#define CLK_BUS_UART3 99 +#define CLK_BUS_UART4 100 +#define CLK_BUS_UART5 101 +#define CLK_BUS_UART6 102 +#define CLK_BUS_UART7 103 +#define CLK_BUS_DBG 104 + +#define CLK_THS 105 +#define CLK_NAND 106 +#define CLK_MMC0 107 +#define CLK_MMC1 108 +#define CLK_MMC2 109 +#define CLK_MMC3 110 +#define CLK_TS 111 +#define CLK_CE 112 +#define CLK_SPI0 113 +#define CLK_SPI1 114 +#define CLK_SPI2 115 +#define CLK_SPI3 116 +#define CLK_I2S0 117 +#define CLK_I2S1 118 +#define CLK_I2S2 119 +#define CLK_AC97 120 +#define CLK_SPDIF 121 +#define CLK_KEYPAD 122 +#define CLK_SATA 123 +#define CLK_USB_PHY0 124 +#define CLK_USB_PHY1 125 +#define CLK_USB_PHY2 126 +#define CLK_USB_OHCI0 127 +#define CLK_USB_OHCI1 128 +#define CLK_USB_OHCI2 129 +#define CLK_IR0 130 +#define CLK_IR1 131 + +#define CLK_DRAM_VE 133 +#define CLK_DRAM_CSI0 134 +#define CLK_DRAM_CSI1 135 +#define CLK_DRAM_TS 136 +#define CLK_DRAM_TVD 137 +#define CLK_DRAM_MP 138 +#define CLK_DRAM_DEINTERLACE 139 +#define CLK_DE 140 +#define CLK_MP 141 +#define CLK_TCON_LCD0 142 +#define CLK_TCON_LCD1 143 +#define CLK_TCON_TV0 144 +#define CLK_TCON_TV1 145 +#define CLK_DEINTERLACE 146 +#define CLK_CSI1_MCLK 147 +#define CLK_CSI_SCLK 148 +#define CLK_CSI0_MCLK 149 +#define CLK_VE 150 +#define CLK_CODEC 151 +#define CLK_AVS 152 +#define CLK_HDMI 153 +#define CLK_HDMI_SLOW 154 +#define CLK_MBUS 155 +#define CLK_DSI_DPHY 156 +#define CLK_TVE0 157 +#define CLK_TVE1 158 +#define CLK_TVD0 159 +#define CLK_TVD1 160 +#define CLK_TVD2 161 +#define CLK_TVD3 162 +#define CLK_GPU 163 +#define CLK_OUTA 164 +#define CLK_OUTB 165 + +#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun8i-tcon-top.h b/roms/u-boot/include/dt-bindings/clock/sun8i-tcon-top.h new file mode 100644 index 000000000..25164d767 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun8i-tcon-top.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* Copyright (C) 2018 Jernej Skrabec */ + +#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ +#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ + +#define CLK_TCON_TOP_TV0 0 +#define CLK_TCON_TOP_TV1 1 +#define CLK_TCON_TOP_DSI 2 + +#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun8i-v3s-ccu.h b/roms/u-boot/include/dt-bindings/clock/sun8i-v3s-ccu.h new file mode 100644 index 000000000..c0d5d5599 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun8i-v3s-ccu.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2016 Icenowy Zheng + * + * Based on sun8i-h3-ccu.h, which is: + * Copyright (C) 2016 Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_ +#define _DT_BINDINGS_CLK_SUN8I_V3S_H_ + +#define CLK_CPU 14 + +#define CLK_BUS_CE 20 +#define CLK_BUS_DMA 21 +#define CLK_BUS_MMC0 22 +#define CLK_BUS_MMC1 23 +#define CLK_BUS_MMC2 24 +#define CLK_BUS_DRAM 25 +#define CLK_BUS_EMAC 26 +#define CLK_BUS_HSTIMER 27 +#define CLK_BUS_SPI0 28 +#define CLK_BUS_OTG 29 +#define CLK_BUS_EHCI0 30 +#define CLK_BUS_OHCI0 31 +#define CLK_BUS_VE 32 +#define CLK_BUS_TCON0 33 +#define CLK_BUS_CSI 34 +#define CLK_BUS_DE 35 +#define CLK_BUS_CODEC 36 +#define CLK_BUS_PIO 37 +#define CLK_BUS_I2C0 38 +#define CLK_BUS_I2C1 39 +#define CLK_BUS_UART0 40 +#define CLK_BUS_UART1 41 +#define CLK_BUS_UART2 42 +#define CLK_BUS_EPHY 43 +#define CLK_BUS_DBG 44 + +#define CLK_MMC0 45 +#define CLK_MMC0_SAMPLE 46 +#define CLK_MMC0_OUTPUT 47 +#define CLK_MMC1 48 +#define CLK_MMC1_SAMPLE 49 +#define CLK_MMC1_OUTPUT 50 +#define CLK_MMC2 51 +#define CLK_MMC2_SAMPLE 52 +#define CLK_MMC2_OUTPUT 53 +#define CLK_CE 54 +#define CLK_SPI0 55 +#define CLK_USB_PHY0 56 +#define CLK_USB_OHCI0 57 + +#define CLK_DRAM_VE 59 +#define CLK_DRAM_CSI 60 +#define CLK_DRAM_EHCI 61 +#define CLK_DRAM_OHCI 62 +#define CLK_DE 63 +#define CLK_TCON0 64 +#define CLK_CSI_MISC 65 +#define CLK_CSI0_MCLK 66 +#define CLK_CSI1_SCLK 67 +#define CLK_CSI1_MCLK 68 +#define CLK_VE 69 +#define CLK_AC_DIG 70 +#define CLK_AVS 71 + +#define CLK_MIPI_CSI 73 + +#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun9i-a80-ccu.h b/roms/u-boot/include/dt-bindings/clock/sun9i-a80-ccu.h new file mode 100644 index 000000000..6ea1492a7 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun9i-a80-ccu.h @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ +#define _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ + +#define CLK_PLL_AUDIO 2 +#define CLK_PLL_PERIPH0 3 + +#define CLK_C0CPUX 12 +#define CLK_C1CPUX 13 + +#define CLK_OUT_A 27 +#define CLK_OUT_B 28 + +#define CLK_NAND0_0 29 +#define CLK_NAND0_1 30 +#define CLK_NAND1_0 31 +#define CLK_NAND1_1 32 +#define CLK_MMC0 33 +#define CLK_MMC0_SAMPLE 34 +#define CLK_MMC0_OUTPUT 35 +#define CLK_MMC1 36 +#define CLK_MMC1_SAMPLE 37 +#define CLK_MMC1_OUTPUT 38 +#define CLK_MMC2 39 +#define CLK_MMC2_SAMPLE 40 +#define CLK_MMC2_OUTPUT 41 +#define CLK_MMC3 42 +#define CLK_MMC3_SAMPLE 43 +#define CLK_MMC3_OUTPUT 44 +#define CLK_TS 45 +#define CLK_SS 46 +#define CLK_SPI0 47 +#define CLK_SPI1 48 +#define CLK_SPI2 49 +#define CLK_SPI3 50 +#define CLK_I2S0 51 +#define CLK_I2S1 52 +#define CLK_SPDIF 53 +#define CLK_SDRAM 54 +#define CLK_DE 55 +#define CLK_EDP 56 +#define CLK_MP 57 +#define CLK_LCD0 58 +#define CLK_LCD1 59 +#define CLK_MIPI_DSI0 60 +#define CLK_MIPI_DSI1 61 +#define CLK_HDMI 62 +#define CLK_HDMI_SLOW 63 +#define CLK_MIPI_CSI 64 +#define CLK_CSI_ISP 65 +#define CLK_CSI_MISC 66 +#define CLK_CSI0_MCLK 67 +#define CLK_CSI1_MCLK 68 +#define CLK_FD 69 +#define CLK_VE 70 +#define CLK_AVS 71 +#define CLK_GPU_CORE 72 +#define CLK_GPU_MEMORY 73 +#define CLK_GPU_AXI 74 +#define CLK_SATA 75 +#define CLK_AC97 76 +#define CLK_MIPI_HSI 77 +#define CLK_GPADC 78 +#define CLK_CIR_TX 79 + +#define CLK_BUS_FD 80 +#define CLK_BUS_VE 81 +#define CLK_BUS_GPU_CTRL 82 +#define CLK_BUS_SS 83 +#define CLK_BUS_MMC 84 +#define CLK_BUS_NAND0 85 +#define CLK_BUS_NAND1 86 +#define CLK_BUS_SDRAM 87 +#define CLK_BUS_MIPI_HSI 88 +#define CLK_BUS_SATA 89 +#define CLK_BUS_TS 90 +#define CLK_BUS_SPI0 91 +#define CLK_BUS_SPI1 92 +#define CLK_BUS_SPI2 93 +#define CLK_BUS_SPI3 94 + +#define CLK_BUS_OTG 95 +#define CLK_BUS_USB 96 +#define CLK_BUS_GMAC 97 +#define CLK_BUS_MSGBOX 98 +#define CLK_BUS_SPINLOCK 99 +#define CLK_BUS_HSTIMER 100 +#define CLK_BUS_DMA 101 + +#define CLK_BUS_LCD0 102 +#define CLK_BUS_LCD1 103 +#define CLK_BUS_EDP 104 +#define CLK_BUS_CSI 105 +#define CLK_BUS_HDMI 106 +#define CLK_BUS_DE 107 +#define CLK_BUS_MP 108 +#define CLK_BUS_MIPI_DSI 109 + +#define CLK_BUS_SPDIF 110 +#define CLK_BUS_PIO 111 +#define CLK_BUS_AC97 112 +#define CLK_BUS_I2S0 113 +#define CLK_BUS_I2S1 114 +#define CLK_BUS_LRADC 115 +#define CLK_BUS_GPADC 116 +#define CLK_BUS_TWD 117 +#define CLK_BUS_CIR_TX 118 + +#define CLK_BUS_I2C0 119 +#define CLK_BUS_I2C1 120 +#define CLK_BUS_I2C2 121 +#define CLK_BUS_I2C3 122 +#define CLK_BUS_I2C4 123 +#define CLK_BUS_UART0 124 +#define CLK_BUS_UART1 125 +#define CLK_BUS_UART2 126 +#define CLK_BUS_UART3 127 +#define CLK_BUS_UART4 128 +#define CLK_BUS_UART5 129 + +#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun9i-a80-de.h b/roms/u-boot/include/dt-bindings/clock/sun9i-a80-de.h new file mode 100644 index 000000000..3dad6c3cd --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun9i-a80-de.h @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ +#define _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ + +#define CLK_FE0 0 +#define CLK_FE1 1 +#define CLK_FE2 2 +#define CLK_IEP_DEU0 3 +#define CLK_IEP_DEU1 4 +#define CLK_BE0 5 +#define CLK_BE1 6 +#define CLK_BE2 7 +#define CLK_IEP_DRC0 8 +#define CLK_IEP_DRC1 9 +#define CLK_MERGE 10 + +#define CLK_DRAM_FE0 11 +#define CLK_DRAM_FE1 12 +#define CLK_DRAM_FE2 13 +#define CLK_DRAM_DEU0 14 +#define CLK_DRAM_DEU1 15 +#define CLK_DRAM_BE0 16 +#define CLK_DRAM_BE1 17 +#define CLK_DRAM_BE2 18 +#define CLK_DRAM_DRC0 19 +#define CLK_DRAM_DRC1 20 + +#define CLK_BUS_FE0 21 +#define CLK_BUS_FE1 22 +#define CLK_BUS_FE2 23 +#define CLK_BUS_DEU0 24 +#define CLK_BUS_DEU1 25 +#define CLK_BUS_BE0 26 +#define CLK_BUS_BE1 27 +#define CLK_BUS_BE2 28 +#define CLK_BUS_DRC0 29 +#define CLK_BUS_DRC1 30 + +#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/sun9i-a80-usb.h b/roms/u-boot/include/dt-bindings/clock/sun9i-a80-usb.h new file mode 100644 index 000000000..783a60d2c --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/sun9i-a80-usb.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ +#define _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ + +#define CLK_BUS_HCI0 0 +#define CLK_USB_OHCI0 1 +#define CLK_BUS_HCI1 2 +#define CLK_BUS_HCI2 3 +#define CLK_USB_OHCI2 4 + +#define CLK_USB0_PHY 5 +#define CLK_USB1_HSIC 6 +#define CLK_USB1_PHY 7 +#define CLK_USB2_HSIC 8 +#define CLK_USB2_PHY 9 +#define CLK_USB_HSIC 10 + +#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ */ diff --git a/roms/u-boot/include/dt-bindings/clock/tegra114-car.h b/roms/u-boot/include/dt-bindings/clock/tegra114-car.h new file mode 100644 index 000000000..534c03f8a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/tegra114-car.h @@ -0,0 +1,343 @@ +/* + * This header provides constants for binding nvidia,tegra114-car. + * + * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + * registers. These IDs often match those in the CAR's RST_DEVICES registers, + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + * this case, those clocks are assigned IDs above 160 in order to highlight + * this issue. Implementations that interpret these clock IDs as bit values + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + * explicitly handle these special cases. + * + * The balance of the clocks controlled by the CAR are assigned IDs of 160 and + * above. + */ + +#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H +#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H + +/* 0 */ +/* 1 */ +/* 2 */ +/* 3 */ +#define TEGRA114_CLK_RTC 4 +#define TEGRA114_CLK_TIMER 5 +#define TEGRA114_CLK_UARTA 6 +/* 7 (register bit affects uartb and vfir) */ +/* 8 */ +#define TEGRA114_CLK_SDMMC2 9 +/* 10 (register bit affects spdif_in and spdif_out) */ +#define TEGRA114_CLK_I2S1 11 +#define TEGRA114_CLK_I2C1 12 +#define TEGRA114_CLK_NDFLASH 13 +#define TEGRA114_CLK_SDMMC1 14 +#define TEGRA114_CLK_SDMMC4 15 +/* 16 */ +#define TEGRA114_CLK_PWM 17 +#define TEGRA114_CLK_I2S2 18 +#define TEGRA114_CLK_EPP 19 +/* 20 (register bit affects vi and vi_sensor) */ +#define TEGRA114_CLK_GR2D 21 +#define TEGRA114_CLK_USBD 22 +#define TEGRA114_CLK_ISP 23 +#define TEGRA114_CLK_GR3D 24 +/* 25 */ +#define TEGRA114_CLK_DISP2 26 +#define TEGRA114_CLK_DISP1 27 +#define TEGRA114_CLK_HOST1X 28 +#define TEGRA114_CLK_VCP 29 +#define TEGRA114_CLK_I2S0 30 +/* 31 */ + +#define TEGRA114_CLK_MC 32 +/* 33 */ +#define TEGRA114_CLK_APBDMA 34 +/* 35 */ +#define TEGRA114_CLK_KBC 36 +/* 37 */ +/* 38 */ +/* 39 (register bit affects fuse and fuse_burn) */ +#define TEGRA114_CLK_KFUSE 40 +#define TEGRA114_CLK_SBC1 41 +#define TEGRA114_CLK_NOR 42 +/* 43 */ +#define TEGRA114_CLK_SBC2 44 +/* 45 */ +#define TEGRA114_CLK_SBC3 46 +#define TEGRA114_CLK_I2C5 47 +#define TEGRA114_CLK_DSIA 48 +/* 49 */ +#define TEGRA114_CLK_MIPI 50 +#define TEGRA114_CLK_HDMI 51 +#define TEGRA114_CLK_CSI 52 +/* 53 */ +#define TEGRA114_CLK_I2C2 54 +#define TEGRA114_CLK_UARTC 55 +#define TEGRA114_CLK_MIPI_CAL 56 +#define TEGRA114_CLK_EMC 57 +#define TEGRA114_CLK_USB2 58 +#define TEGRA114_CLK_USB3 59 +/* 60 */ +#define TEGRA114_CLK_VDE 61 +#define TEGRA114_CLK_BSEA 62 +#define TEGRA114_CLK_BSEV 63 + +/* 64 */ +#define TEGRA114_CLK_UARTD 65 +/* 66 */ +#define TEGRA114_CLK_I2C3 67 +#define TEGRA114_CLK_SBC4 68 +#define TEGRA114_CLK_SDMMC3 69 +/* 70 */ +#define TEGRA114_CLK_OWR 71 +/* 72 */ +#define TEGRA114_CLK_CSITE 73 +/* 74 */ +/* 75 */ +#define TEGRA114_CLK_LA 76 +#define TEGRA114_CLK_TRACE 77 +#define TEGRA114_CLK_SOC_THERM 78 +#define TEGRA114_CLK_DTV 79 +#define TEGRA114_CLK_NDSPEED 80 +#define TEGRA114_CLK_I2CSLOW 81 +#define TEGRA114_CLK_DSIB 82 +#define TEGRA114_CLK_TSEC 83 +/* 84 */ +/* 85 */ +/* 86 */ +/* 87 */ +/* 88 */ +#define TEGRA114_CLK_XUSB_HOST 89 +/* 90 */ +#define TEGRA114_CLK_MSENC 91 +#define TEGRA114_CLK_CSUS 92 +/* 93 */ +/* 94 */ +/* 95 (bit affects xusb_dev and xusb_dev_src) */ + +/* 96 */ +/* 97 */ +/* 98 */ +#define TEGRA114_CLK_MSELECT 99 +#define TEGRA114_CLK_TSENSOR 100 +#define TEGRA114_CLK_I2S3 101 +#define TEGRA114_CLK_I2S4 102 +#define TEGRA114_CLK_I2C4 103 +#define TEGRA114_CLK_SBC5 104 +#define TEGRA114_CLK_SBC6 105 +#define TEGRA114_CLK_D_AUDIO 106 +#define TEGRA114_CLK_APBIF 107 +#define TEGRA114_CLK_DAM0 108 +#define TEGRA114_CLK_DAM1 109 +#define TEGRA114_CLK_DAM2 110 +#define TEGRA114_CLK_HDA2CODEC_2X 111 +/* 112 */ +#define TEGRA114_CLK_AUDIO0_2X 113 +#define TEGRA114_CLK_AUDIO1_2X 114 +#define TEGRA114_CLK_AUDIO2_2X 115 +#define TEGRA114_CLK_AUDIO3_2X 116 +#define TEGRA114_CLK_AUDIO4_2X 117 +#define TEGRA114_CLK_SPDIF_2X 118 +#define TEGRA114_CLK_ACTMON 119 +#define TEGRA114_CLK_EXTERN1 120 +#define TEGRA114_CLK_EXTERN2 121 +#define TEGRA114_CLK_EXTERN3 122 +/* 123 */ +/* 124 */ +#define TEGRA114_CLK_HDA 125 +/* 126 */ +#define TEGRA114_CLK_SE 127 + +#define TEGRA114_CLK_HDA2HDMI 128 +/* 129 */ +/* 130 */ +/* 131 */ +/* 132 */ +/* 133 */ +/* 134 */ +/* 135 */ +/* 136 */ +/* 137 */ +/* 138 */ +/* 139 */ +/* 140 */ +/* 141 */ +/* 142 */ +/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ +/* xusb_host_src and xusb_ss_src) */ +#define TEGRA114_CLK_CILAB 144 +#define TEGRA114_CLK_CILCD 145 +#define TEGRA114_CLK_CILE 146 +#define TEGRA114_CLK_DSIALP 147 +#define TEGRA114_CLK_DSIBLP 148 +/* 149 */ +#define TEGRA114_CLK_DDS 150 +/* 151 */ +#define TEGRA114_CLK_DP2 152 +#define TEGRA114_CLK_AMX 153 +#define TEGRA114_CLK_ADX 154 +/* 155 (bit affects dfll_ref and dfll_soc) */ +#define TEGRA114_CLK_XUSB_SS 156 +/* 157 */ +/* 158 */ +/* 159 */ + +/* 160 */ +/* 161 */ +/* 162 */ +/* 163 */ +/* 164 */ +/* 165 */ +/* 166 */ +/* 167 */ +/* 168 */ +/* 169 */ +/* 170 */ +/* 171 */ +/* 172 */ +/* 173 */ +/* 174 */ +/* 175 */ +/* 176 */ +/* 177 */ +/* 178 */ +/* 179 */ +/* 180 */ +/* 181 */ +/* 182 */ +/* 183 */ +/* 184 */ +/* 185 */ +/* 186 */ +/* 187 */ +/* 188 */ +/* 189 */ +/* 190 */ +/* 191 */ + +#define TEGRA114_CLK_UARTB 192 +#define TEGRA114_CLK_VFIR 193 +#define TEGRA114_CLK_SPDIF_IN 194 +#define TEGRA114_CLK_SPDIF_OUT 195 +#define TEGRA114_CLK_VI 196 +#define TEGRA114_CLK_VI_SENSOR 197 +#define TEGRA114_CLK_FUSE 198 +#define TEGRA114_CLK_FUSE_BURN 199 +#define TEGRA114_CLK_CLK_32K 200 +#define TEGRA114_CLK_CLK_M 201 +#define TEGRA114_CLK_CLK_M_DIV2 202 +#define TEGRA114_CLK_CLK_M_DIV4 203 +#define TEGRA114_CLK_PLL_REF 204 +#define TEGRA114_CLK_PLL_C 205 +#define TEGRA114_CLK_PLL_C_OUT1 206 +#define TEGRA114_CLK_PLL_C2 207 +#define TEGRA114_CLK_PLL_C3 208 +#define TEGRA114_CLK_PLL_M 209 +#define TEGRA114_CLK_PLL_M_OUT1 210 +#define TEGRA114_CLK_PLL_P 211 +#define TEGRA114_CLK_PLL_P_OUT1 212 +#define TEGRA114_CLK_PLL_P_OUT2 213 +#define TEGRA114_CLK_PLL_P_OUT3 214 +#define TEGRA114_CLK_PLL_P_OUT4 215 +#define TEGRA114_CLK_PLL_A 216 +#define TEGRA114_CLK_PLL_A_OUT0 217 +#define TEGRA114_CLK_PLL_D 218 +#define TEGRA114_CLK_PLL_D_OUT0 219 +#define TEGRA114_CLK_PLL_D2 220 +#define TEGRA114_CLK_PLL_D2_OUT0 221 +#define TEGRA114_CLK_PLL_U 222 +#define TEGRA114_CLK_PLL_U_480M 223 + +#define TEGRA114_CLK_PLL_U_60M 224 +#define TEGRA114_CLK_PLL_U_48M 225 +#define TEGRA114_CLK_PLL_U_12M 226 +#define TEGRA114_CLK_PLL_X 227 +#define TEGRA114_CLK_PLL_X_OUT0 228 +#define TEGRA114_CLK_PLL_RE_VCO 229 +#define TEGRA114_CLK_PLL_RE_OUT 230 +#define TEGRA114_CLK_PLL_E_OUT0 231 +#define TEGRA114_CLK_SPDIF_IN_SYNC 232 +#define TEGRA114_CLK_I2S0_SYNC 233 +#define TEGRA114_CLK_I2S1_SYNC 234 +#define TEGRA114_CLK_I2S2_SYNC 235 +#define TEGRA114_CLK_I2S3_SYNC 236 +#define TEGRA114_CLK_I2S4_SYNC 237 +#define TEGRA114_CLK_VIMCLK_SYNC 238 +#define TEGRA114_CLK_AUDIO0 239 +#define TEGRA114_CLK_AUDIO1 240 +#define TEGRA114_CLK_AUDIO2 241 +#define TEGRA114_CLK_AUDIO3 242 +#define TEGRA114_CLK_AUDIO4 243 +#define TEGRA114_CLK_SPDIF 244 +#define TEGRA114_CLK_CLK_OUT_1 245 +#define TEGRA114_CLK_CLK_OUT_2 246 +#define TEGRA114_CLK_CLK_OUT_3 247 +#define TEGRA114_CLK_BLINK 248 +/* 249 */ +/* 250 */ +/* 251 */ +#define TEGRA114_CLK_XUSB_HOST_SRC 252 +#define TEGRA114_CLK_XUSB_FALCON_SRC 253 +#define TEGRA114_CLK_XUSB_FS_SRC 254 +#define TEGRA114_CLK_XUSB_SS_SRC 255 + +#define TEGRA114_CLK_XUSB_DEV_SRC 256 +#define TEGRA114_CLK_XUSB_DEV 257 +#define TEGRA114_CLK_XUSB_HS_SRC 258 +#define TEGRA114_CLK_SCLK 259 +#define TEGRA114_CLK_HCLK 260 +#define TEGRA114_CLK_PCLK 261 +#define TEGRA114_CLK_CCLK_G 262 +#define TEGRA114_CLK_CCLK_LP 263 +#define TEGRA114_CLK_DFLL_REF 264 +#define TEGRA114_CLK_DFLL_SOC 265 +/* 266 */ +/* 267 */ +/* 268 */ +/* 269 */ +/* 270 */ +/* 271 */ +/* 272 */ +/* 273 */ +/* 274 */ +/* 275 */ +/* 276 */ +/* 277 */ +/* 278 */ +/* 279 */ +/* 280 */ +/* 281 */ +/* 282 */ +/* 283 */ +/* 284 */ +/* 285 */ +/* 286 */ +/* 287 */ + +/* 288 */ +/* 289 */ +/* 290 */ +/* 291 */ +/* 292 */ +/* 293 */ +/* 294 */ +/* 295 */ +/* 296 */ +/* 297 */ +/* 298 */ +/* 299 */ +#define TEGRA114_CLK_AUDIO0_MUX 300 +#define TEGRA114_CLK_AUDIO1_MUX 301 +#define TEGRA114_CLK_AUDIO2_MUX 302 +#define TEGRA114_CLK_AUDIO3_MUX 303 +#define TEGRA114_CLK_AUDIO4_MUX 304 +#define TEGRA114_CLK_SPDIF_MUX 305 +#define TEGRA114_CLK_CLK_OUT_1_MUX 306 +#define TEGRA114_CLK_CLK_OUT_2_MUX 307 +#define TEGRA114_CLK_CLK_OUT_3_MUX 308 +#define TEGRA114_CLK_DSIA_MUX 309 +#define TEGRA114_CLK_DSIB_MUX 310 +#define TEGRA114_CLK_XUSB_SS_DIV2 311 +#define TEGRA114_CLK_CLK_MAX 312 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/tegra124-car-common.h b/roms/u-boot/include/dt-bindings/clock/tegra124-car-common.h new file mode 100644 index 000000000..a21560905 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/tegra124-car-common.h @@ -0,0 +1,345 @@ +/* + * This header provides constants for binding nvidia,tegra124-car or + * nvidia,tegra132-car. + * + * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + * registers. These IDs often match those in the CAR's RST_DEVICES registers, + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + * this case, those clocks are assigned IDs above 185 in order to highlight + * this issue. Implementations that interpret these clock IDs as bit values + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + * explicitly handle these special cases. + * + * The balance of the clocks controlled by the CAR are assigned IDs of 185 and + * above. + */ + +#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H +#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H + +/* 0 */ +/* 1 */ +/* 2 */ +#define TEGRA124_CLK_ISPB 3 +#define TEGRA124_CLK_RTC 4 +#define TEGRA124_CLK_TIMER 5 +#define TEGRA124_CLK_UARTA 6 +/* 7 (register bit affects uartb and vfir) */ +/* 8 */ +#define TEGRA124_CLK_SDMMC2 9 +/* 10 (register bit affects spdif_in and spdif_out) */ +#define TEGRA124_CLK_I2S1 11 +#define TEGRA124_CLK_I2C1 12 +/* 13 */ +#define TEGRA124_CLK_SDMMC1 14 +#define TEGRA124_CLK_SDMMC4 15 +/* 16 */ +#define TEGRA124_CLK_PWM 17 +#define TEGRA124_CLK_I2S2 18 +/* 20 (register bit affects vi and vi_sensor) */ +/* 21 */ +#define TEGRA124_CLK_USBD 22 +#define TEGRA124_CLK_ISP 23 +/* 26 */ +/* 25 */ +#define TEGRA124_CLK_DISP2 26 +#define TEGRA124_CLK_DISP1 27 +#define TEGRA124_CLK_HOST1X 28 +#define TEGRA124_CLK_VCP 29 +#define TEGRA124_CLK_I2S0 30 +/* 31 */ + +#define TEGRA124_CLK_MC 32 +/* 33 */ +#define TEGRA124_CLK_APBDMA 34 +/* 35 */ +#define TEGRA124_CLK_KBC 36 +/* 37 */ +/* 38 */ +/* 39 (register bit affects fuse and fuse_burn) */ +#define TEGRA124_CLK_KFUSE 40 +#define TEGRA124_CLK_SBC1 41 +#define TEGRA124_CLK_NOR 42 +/* 43 */ +#define TEGRA124_CLK_SBC2 44 +/* 45 */ +#define TEGRA124_CLK_SBC3 46 +#define TEGRA124_CLK_I2C5 47 +#define TEGRA124_CLK_DSIA 48 +/* 49 */ +#define TEGRA124_CLK_MIPI 50 +#define TEGRA124_CLK_HDMI 51 +#define TEGRA124_CLK_CSI 52 +/* 53 */ +#define TEGRA124_CLK_I2C2 54 +#define TEGRA124_CLK_UARTC 55 +#define TEGRA124_CLK_MIPI_CAL 56 +#define TEGRA124_CLK_EMC 57 +#define TEGRA124_CLK_USB2 58 +#define TEGRA124_CLK_USB3 59 +/* 60 */ +#define TEGRA124_CLK_VDE 61 +#define TEGRA124_CLK_BSEA 62 +#define TEGRA124_CLK_BSEV 63 + +/* 64 */ +#define TEGRA124_CLK_UARTD 65 +/* 66 */ +#define TEGRA124_CLK_I2C3 67 +#define TEGRA124_CLK_SBC4 68 +#define TEGRA124_CLK_SDMMC3 69 +#define TEGRA124_CLK_PCIE 70 +#define TEGRA124_CLK_OWR 71 +#define TEGRA124_CLK_AFI 72 +#define TEGRA124_CLK_CSITE 73 +/* 74 */ +/* 75 */ +#define TEGRA124_CLK_LA 76 +#define TEGRA124_CLK_TRACE 77 +#define TEGRA124_CLK_SOC_THERM 78 +#define TEGRA124_CLK_DTV 79 +/* 80 */ +#define TEGRA124_CLK_I2CSLOW 81 +#define TEGRA124_CLK_DSIB 82 +#define TEGRA124_CLK_TSEC 83 +/* 84 */ +/* 85 */ +/* 86 */ +/* 87 */ +/* 88 */ +#define TEGRA124_CLK_XUSB_HOST 89 +/* 90 */ +#define TEGRA124_CLK_MSENC 91 +#define TEGRA124_CLK_CSUS 92 +/* 93 */ +/* 94 */ +/* 95 (bit affects xusb_dev and xusb_dev_src) */ + +/* 96 */ +/* 97 */ +/* 98 */ +#define TEGRA124_CLK_MSELECT 99 +#define TEGRA124_CLK_TSENSOR 100 +#define TEGRA124_CLK_I2S3 101 +#define TEGRA124_CLK_I2S4 102 +#define TEGRA124_CLK_I2C4 103 +#define TEGRA124_CLK_SBC5 104 +#define TEGRA124_CLK_SBC6 105 +#define TEGRA124_CLK_D_AUDIO 106 +#define TEGRA124_CLK_APBIF 107 +#define TEGRA124_CLK_DAM0 108 +#define TEGRA124_CLK_DAM1 109 +#define TEGRA124_CLK_DAM2 110 +#define TEGRA124_CLK_HDA2CODEC_2X 111 +/* 112 */ +#define TEGRA124_CLK_AUDIO0_2X 113 +#define TEGRA124_CLK_AUDIO1_2X 114 +#define TEGRA124_CLK_AUDIO2_2X 115 +#define TEGRA124_CLK_AUDIO3_2X 116 +#define TEGRA124_CLK_AUDIO4_2X 117 +#define TEGRA124_CLK_SPDIF_2X 118 +#define TEGRA124_CLK_ACTMON 119 +#define TEGRA124_CLK_EXTERN1 120 +#define TEGRA124_CLK_EXTERN2 121 +#define TEGRA124_CLK_EXTERN3 122 +#define TEGRA124_CLK_SATA_OOB 123 +#define TEGRA124_CLK_SATA 124 +#define TEGRA124_CLK_HDA 125 +/* 126 */ +#define TEGRA124_CLK_SE 127 + +#define TEGRA124_CLK_HDA2HDMI 128 +#define TEGRA124_CLK_SATA_COLD 129 +/* 130 */ +/* 131 */ +/* 132 */ +/* 133 */ +/* 134 */ +/* 135 */ +/* 136 */ +/* 137 */ +/* 138 */ +/* 139 */ +/* 140 */ +/* 141 */ +/* 142 */ +/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ +/* xusb_host_src and xusb_ss_src) */ +#define TEGRA124_CLK_CILAB 144 +#define TEGRA124_CLK_CILCD 145 +#define TEGRA124_CLK_CILE 146 +#define TEGRA124_CLK_DSIALP 147 +#define TEGRA124_CLK_DSIBLP 148 +#define TEGRA124_CLK_ENTROPY 149 +#define TEGRA124_CLK_DDS 150 +/* 151 */ +#define TEGRA124_CLK_DP2 152 +#define TEGRA124_CLK_AMX 153 +#define TEGRA124_CLK_ADX 154 +/* 155 (bit affects dfll_ref and dfll_soc) */ +#define TEGRA124_CLK_XUSB_SS 156 +/* 157 */ +/* 158 */ +/* 159 */ + +/* 160 */ +/* 161 */ +/* 162 */ +/* 163 */ +/* 164 */ +/* 165 */ +#define TEGRA124_CLK_I2C6 166 +/* 167 */ +/* 168 */ +/* 169 */ +/* 170 */ +#define TEGRA124_CLK_VIM2_CLK 171 +/* 172 */ +/* 173 */ +/* 174 */ +/* 175 */ +#define TEGRA124_CLK_HDMI_AUDIO 176 +#define TEGRA124_CLK_CLK72MHZ 177 +#define TEGRA124_CLK_VIC03 178 +/* 179 */ +#define TEGRA124_CLK_ADX1 180 +#define TEGRA124_CLK_DPAUX 181 +#define TEGRA124_CLK_SOR0 182 +/* 183 */ +#define TEGRA124_CLK_GPU 184 +#define TEGRA124_CLK_AMX1 185 +/* 186 */ +/* 187 */ +/* 188 */ +/* 189 */ +/* 190 */ +/* 191 */ +#define TEGRA124_CLK_UARTB 192 +#define TEGRA124_CLK_VFIR 193 +#define TEGRA124_CLK_SPDIF_IN 194 +#define TEGRA124_CLK_SPDIF_OUT 195 +#define TEGRA124_CLK_VI 196 +#define TEGRA124_CLK_VI_SENSOR 197 +#define TEGRA124_CLK_FUSE 198 +#define TEGRA124_CLK_FUSE_BURN 199 +#define TEGRA124_CLK_CLK_32K 200 +#define TEGRA124_CLK_CLK_M 201 +#define TEGRA124_CLK_CLK_M_DIV2 202 +#define TEGRA124_CLK_CLK_M_DIV4 203 +#define TEGRA124_CLK_PLL_REF 204 +#define TEGRA124_CLK_PLL_C 205 +#define TEGRA124_CLK_PLL_C_OUT1 206 +#define TEGRA124_CLK_PLL_C2 207 +#define TEGRA124_CLK_PLL_C3 208 +#define TEGRA124_CLK_PLL_M 209 +#define TEGRA124_CLK_PLL_M_OUT1 210 +#define TEGRA124_CLK_PLL_P 211 +#define TEGRA124_CLK_PLL_P_OUT1 212 +#define TEGRA124_CLK_PLL_P_OUT2 213 +#define TEGRA124_CLK_PLL_P_OUT3 214 +#define TEGRA124_CLK_PLL_P_OUT4 215 +#define TEGRA124_CLK_PLL_A 216 +#define TEGRA124_CLK_PLL_A_OUT0 217 +#define TEGRA124_CLK_PLL_D 218 +#define TEGRA124_CLK_PLL_D_OUT0 219 +#define TEGRA124_CLK_PLL_D2 220 +#define TEGRA124_CLK_PLL_D2_OUT0 221 +#define TEGRA124_CLK_PLL_U 222 +#define TEGRA124_CLK_PLL_U_480M 223 + +#define TEGRA124_CLK_PLL_U_60M 224 +#define TEGRA124_CLK_PLL_U_48M 225 +#define TEGRA124_CLK_PLL_U_12M 226 +/* 227 */ +/* 228 */ +#define TEGRA124_CLK_PLL_RE_VCO 229 +#define TEGRA124_CLK_PLL_RE_OUT 230 +#define TEGRA124_CLK_PLL_E 231 +#define TEGRA124_CLK_SPDIF_IN_SYNC 232 +#define TEGRA124_CLK_I2S0_SYNC 233 +#define TEGRA124_CLK_I2S1_SYNC 234 +#define TEGRA124_CLK_I2S2_SYNC 235 +#define TEGRA124_CLK_I2S3_SYNC 236 +#define TEGRA124_CLK_I2S4_SYNC 237 +#define TEGRA124_CLK_VIMCLK_SYNC 238 +#define TEGRA124_CLK_AUDIO0 239 +#define TEGRA124_CLK_AUDIO1 240 +#define TEGRA124_CLK_AUDIO2 241 +#define TEGRA124_CLK_AUDIO3 242 +#define TEGRA124_CLK_AUDIO4 243 +#define TEGRA124_CLK_SPDIF 244 +#define TEGRA124_CLK_CLK_OUT_1 245 +#define TEGRA124_CLK_CLK_OUT_2 246 +#define TEGRA124_CLK_CLK_OUT_3 247 +#define TEGRA124_CLK_BLINK 248 +/* 249 */ +/* 250 */ +/* 251 */ +#define TEGRA124_CLK_XUSB_HOST_SRC 252 +#define TEGRA124_CLK_XUSB_FALCON_SRC 253 +#define TEGRA124_CLK_XUSB_FS_SRC 254 +#define TEGRA124_CLK_XUSB_SS_SRC 255 + +#define TEGRA124_CLK_XUSB_DEV_SRC 256 +#define TEGRA124_CLK_XUSB_DEV 257 +#define TEGRA124_CLK_XUSB_HS_SRC 258 +#define TEGRA124_CLK_SCLK 259 +#define TEGRA124_CLK_HCLK 260 +#define TEGRA124_CLK_PCLK 261 +/* 262 */ +/* 263 */ +#define TEGRA124_CLK_DFLL_REF 264 +#define TEGRA124_CLK_DFLL_SOC 265 +#define TEGRA124_CLK_VI_SENSOR2 266 +#define TEGRA124_CLK_PLL_P_OUT5 267 +#define TEGRA124_CLK_CML0 268 +#define TEGRA124_CLK_CML1 269 +#define TEGRA124_CLK_PLL_C4 270 +#define TEGRA124_CLK_PLL_DP 271 +#define TEGRA124_CLK_PLL_E_MUX 272 +#define TEGRA124_CLK_PLL_D_DSI_OUT 273 +/* 274 */ +/* 275 */ +/* 276 */ +/* 277 */ +/* 278 */ +/* 279 */ +/* 280 */ +/* 281 */ +/* 282 */ +/* 283 */ +/* 284 */ +/* 285 */ +/* 286 */ +/* 287 */ + +/* 288 */ +/* 289 */ +/* 290 */ +/* 291 */ +/* 292 */ +/* 293 */ +/* 294 */ +/* 295 */ +/* 296 */ +/* 297 */ +/* 298 */ +/* 299 */ +#define TEGRA124_CLK_AUDIO0_MUX 300 +#define TEGRA124_CLK_AUDIO1_MUX 301 +#define TEGRA124_CLK_AUDIO2_MUX 302 +#define TEGRA124_CLK_AUDIO3_MUX 303 +#define TEGRA124_CLK_AUDIO4_MUX 304 +#define TEGRA124_CLK_SPDIF_MUX 305 +#define TEGRA124_CLK_CLK_OUT_1_MUX 306 +#define TEGRA124_CLK_CLK_OUT_2_MUX 307 +#define TEGRA124_CLK_CLK_OUT_3_MUX 308 +/* 309 */ +/* 310 */ +#define TEGRA124_CLK_SOR0_LVDS 311 +#define TEGRA124_CLK_XUSB_SS_DIV2 312 + +#define TEGRA124_CLK_PLL_M_UD 313 +#define TEGRA124_CLK_PLL_C_UD 314 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/tegra124-car.h b/roms/u-boot/include/dt-bindings/clock/tegra124-car.h new file mode 100644 index 000000000..2860737f0 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/tegra124-car.h @@ -0,0 +1,19 @@ +/* + * This header provides Tegra124-specific constants for binding + * nvidia,tegra124-car. + */ + +#include + +#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H +#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H + +#define TEGRA124_CLK_PLL_X 227 +#define TEGRA124_CLK_PLL_X_OUT0 228 + +#define TEGRA124_CLK_CCLK_G 262 +#define TEGRA124_CLK_CCLK_LP 263 + +#define TEGRA124_CLK_CLK_MAX 315 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/tegra186-clock.h b/roms/u-boot/include/dt-bindings/clock/tegra186-clock.h new file mode 100644 index 000000000..f73d32098 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/tegra186-clock.h @@ -0,0 +1,940 @@ +/** @file */ + +#ifndef _MACH_T186_CLK_T186_H +#define _MACH_T186_CLK_T186_H + +/** + * @defgroup clock_ids Clock Identifiers + * @{ + * @defgroup extern_input external input clocks + * @{ + * @def TEGRA186_CLK_OSC + * @def TEGRA186_CLK_CLK_32K + * @def TEGRA186_CLK_DTV_INPUT + * @def TEGRA186_CLK_SOR0_PAD_CLKOUT + * @def TEGRA186_CLK_SOR1_PAD_CLKOUT + * @def TEGRA186_CLK_I2S1_SYNC_INPUT + * @def TEGRA186_CLK_I2S2_SYNC_INPUT + * @def TEGRA186_CLK_I2S3_SYNC_INPUT + * @def TEGRA186_CLK_I2S4_SYNC_INPUT + * @def TEGRA186_CLK_I2S5_SYNC_INPUT + * @def TEGRA186_CLK_I2S6_SYNC_INPUT + * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT + * @} + * + * @defgroup extern_output external output clocks + * @{ + * @def TEGRA186_CLK_EXTPERIPH1 + * @def TEGRA186_CLK_EXTPERIPH2 + * @def TEGRA186_CLK_EXTPERIPH3 + * @def TEGRA186_CLK_EXTPERIPH4 + * @} + * + * @defgroup display_clks display related clocks + * @{ + * @def TEGRA186_CLK_CEC + * @def TEGRA186_CLK_DSIC + * @def TEGRA186_CLK_DSIC_LP + * @def TEGRA186_CLK_DSID + * @def TEGRA186_CLK_DSID_LP + * @def TEGRA186_CLK_DPAUX1 + * @def TEGRA186_CLK_DPAUX + * @def TEGRA186_CLK_HDA2HDMICODEC + * @def TEGRA186_CLK_NVDISPLAY_DISP + * @def TEGRA186_CLK_NVDISPLAY_DSC + * @def TEGRA186_CLK_NVDISPLAY_P0 + * @def TEGRA186_CLK_NVDISPLAY_P1 + * @def TEGRA186_CLK_NVDISPLAY_P2 + * @def TEGRA186_CLK_NVDISPLAYHUB + * @def TEGRA186_CLK_SOR_SAFE + * @def TEGRA186_CLK_SOR0 + * @def TEGRA186_CLK_SOR0_OUT + * @def TEGRA186_CLK_SOR1 + * @def TEGRA186_CLK_SOR1_OUT + * @def TEGRA186_CLK_DSI + * @def TEGRA186_CLK_MIPI_CAL + * @def TEGRA186_CLK_DSIA_LP + * @def TEGRA186_CLK_DSIB + * @def TEGRA186_CLK_DSIB_LP + * @} + * + * @defgroup camera_clks camera related clocks + * @{ + * @def TEGRA186_CLK_NVCSI + * @def TEGRA186_CLK_NVCSILP + * @def TEGRA186_CLK_VI + * @} + * + * @defgroup audio_clks audio related clocks + * @{ + * @def TEGRA186_CLK_ACLK + * @def TEGRA186_CLK_ADSP + * @def TEGRA186_CLK_ADSPNEON + * @def TEGRA186_CLK_AHUB + * @def TEGRA186_CLK_APE + * @def TEGRA186_CLK_APB2APE + * @def TEGRA186_CLK_AUD_MCLK + * @def TEGRA186_CLK_DMIC1 + * @def TEGRA186_CLK_DMIC2 + * @def TEGRA186_CLK_DMIC3 + * @def TEGRA186_CLK_DMIC4 + * @def TEGRA186_CLK_DSPK1 + * @def TEGRA186_CLK_DSPK2 + * @def TEGRA186_CLK_HDA + * @def TEGRA186_CLK_HDA2CODEC_2X + * @def TEGRA186_CLK_I2S1 + * @def TEGRA186_CLK_I2S2 + * @def TEGRA186_CLK_I2S3 + * @def TEGRA186_CLK_I2S4 + * @def TEGRA186_CLK_I2S5 + * @def TEGRA186_CLK_I2S6 + * @def TEGRA186_CLK_MAUD + * @def TEGRA186_CLK_PLL_A_OUT0 + * @def TEGRA186_CLK_SPDIF_DOUBLER + * @def TEGRA186_CLK_SPDIF_IN + * @def TEGRA186_CLK_SPDIF_OUT + * @def TEGRA186_CLK_SYNC_DMIC1 + * @def TEGRA186_CLK_SYNC_DMIC2 + * @def TEGRA186_CLK_SYNC_DMIC3 + * @def TEGRA186_CLK_SYNC_DMIC4 + * @def TEGRA186_CLK_SYNC_DMIC5 + * @def TEGRA186_CLK_SYNC_DSPK1 + * @def TEGRA186_CLK_SYNC_DSPK2 + * @def TEGRA186_CLK_SYNC_I2S1 + * @def TEGRA186_CLK_SYNC_I2S2 + * @def TEGRA186_CLK_SYNC_I2S3 + * @def TEGRA186_CLK_SYNC_I2S4 + * @def TEGRA186_CLK_SYNC_I2S5 + * @def TEGRA186_CLK_SYNC_I2S6 + * @def TEGRA186_CLK_SYNC_SPDIF + * @} + * + * @defgroup uart_clks UART clocks + * @{ + * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL + * @def TEGRA186_CLK_UARTA + * @def TEGRA186_CLK_UARTB + * @def TEGRA186_CLK_UARTC + * @def TEGRA186_CLK_UARTD + * @def TEGRA186_CLK_UARTE + * @def TEGRA186_CLK_UARTF + * @def TEGRA186_CLK_UARTG + * @def TEGRA186_CLK_UART_FST_MIPI_CAL + * @} + * + * @defgroup i2c_clks I2C clocks + * @{ + * @def TEGRA186_CLK_AON_I2C_SLOW + * @def TEGRA186_CLK_I2C1 + * @def TEGRA186_CLK_I2C2 + * @def TEGRA186_CLK_I2C3 + * @def TEGRA186_CLK_I2C4 + * @def TEGRA186_CLK_I2C5 + * @def TEGRA186_CLK_I2C6 + * @def TEGRA186_CLK_I2C8 + * @def TEGRA186_CLK_I2C9 + * @def TEGRA186_CLK_I2C1 + * @def TEGRA186_CLK_I2C12 + * @def TEGRA186_CLK_I2C13 + * @def TEGRA186_CLK_I2C14 + * @def TEGRA186_CLK_I2C_SLOW + * @def TEGRA186_CLK_VI_I2C + * @} + * + * @defgroup spi_clks SPI clocks + * @{ + * @def TEGRA186_CLK_SPI1 + * @def TEGRA186_CLK_SPI2 + * @def TEGRA186_CLK_SPI3 + * @def TEGRA186_CLK_SPI4 + * @} + * + * @defgroup storage storage related clocks + * @{ + * @def TEGRA186_CLK_SATA + * @def TEGRA186_CLK_SATA_OOB + * @def TEGRA186_CLK_SATA_IOBIST + * @def TEGRA186_CLK_SDMMC_LEGACY_TM + * @def TEGRA186_CLK_SDMMC1 + * @def TEGRA186_CLK_SDMMC2 + * @def TEGRA186_CLK_SDMMC3 + * @def TEGRA186_CLK_SDMMC4 + * @def TEGRA186_CLK_QSPI + * @def TEGRA186_CLK_QSPI_OUT + * @def TEGRA186_CLK_UFSDEV_REF + * @def TEGRA186_CLK_UFSHC + * @} + * + * @defgroup pwm_clks PWM clocks + * @{ + * @def TEGRA186_CLK_PWM1 + * @def TEGRA186_CLK_PWM2 + * @def TEGRA186_CLK_PWM3 + * @def TEGRA186_CLK_PWM4 + * @def TEGRA186_CLK_PWM5 + * @def TEGRA186_CLK_PWM6 + * @def TEGRA186_CLK_PWM7 + * @def TEGRA186_CLK_PWM8 + * @} + * + * @defgroup plls PLLs and related clocks + * @{ + * @def TEGRA186_CLK_PLLREFE_OUT_GATED + * @def TEGRA186_CLK_PLLREFE_OUT1 + * @def TEGRA186_CLK_PLLD_OUT1 + * @def TEGRA186_CLK_PLLP_OUT0 + * @def TEGRA186_CLK_PLLP_OUT5 + * @def TEGRA186_CLK_PLLA + * @def TEGRA186_CLK_PLLE_PWRSEQ + * @def TEGRA186_CLK_PLLA_OUT1 + * @def TEGRA186_CLK_PLLREFE_REF + * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ + * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ + * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH + * @def TEGRA186_CLK_PLLREFE_PEX + * @def TEGRA186_CLK_PLLREFE_IDDQ + * @def TEGRA186_CLK_PLLC_OUT_AON + * @def TEGRA186_CLK_PLLC_OUT_ISP + * @def TEGRA186_CLK_PLLC_OUT_VE + * @def TEGRA186_CLK_PLLC4_OUT + * @def TEGRA186_CLK_PLLREFE_OUT + * @def TEGRA186_CLK_PLLREFE_PLL_REF + * @def TEGRA186_CLK_PLLE + * @def TEGRA186_CLK_PLLC + * @def TEGRA186_CLK_PLLP + * @def TEGRA186_CLK_PLLD + * @def TEGRA186_CLK_PLLD2 + * @def TEGRA186_CLK_PLLREFE_VCO + * @def TEGRA186_CLK_PLLC2 + * @def TEGRA186_CLK_PLLC3 + * @def TEGRA186_CLK_PLLDP + * @def TEGRA186_CLK_PLLC4_VCO + * @def TEGRA186_CLK_PLLA1 + * @def TEGRA186_CLK_PLLNVCSI + * @def TEGRA186_CLK_PLLDISPHUB + * @def TEGRA186_CLK_PLLD3 + * @def TEGRA186_CLK_PLLBPMPCAM + * @def TEGRA186_CLK_PLLAON + * @def TEGRA186_CLK_PLLU + * @def TEGRA186_CLK_PLLC4_VCO_DIV2 + * @def TEGRA186_CLK_PLL_REF + * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5 + * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ + * @def TEGRA186_CLK_PLL_U_48M + * @def TEGRA186_CLK_PLL_U_480M + * @def TEGRA186_CLK_PLLC4_OUT0 + * @def TEGRA186_CLK_PLLC4_OUT1 + * @def TEGRA186_CLK_PLLC4_OUT2 + * @def TEGRA186_CLK_PLLC4_OUT_MUX + * @def TEGRA186_CLK_DFLLDISP_DIV + * @def TEGRA186_CLK_PLLDISPHUB_DIV + * @def TEGRA186_CLK_PLLP_DIV8 + * @} + * + * @defgroup nafll_clks NAFLL clock sources + * @{ + * @def TEGRA186_CLK_NAFLL_AXI_CBB + * @def TEGRA186_CLK_NAFLL_BCPU + * @def TEGRA186_CLK_NAFLL_BPMP + * @def TEGRA186_CLK_NAFLL_DISP + * @def TEGRA186_CLK_NAFLL_GPU + * @def TEGRA186_CLK_NAFLL_ISP + * @def TEGRA186_CLK_NAFLL_MCPU + * @def TEGRA186_CLK_NAFLL_NVDEC + * @def TEGRA186_CLK_NAFLL_NVENC + * @def TEGRA186_CLK_NAFLL_NVJPG + * @def TEGRA186_CLK_NAFLL_SCE + * @def TEGRA186_CLK_NAFLL_SE + * @def TEGRA186_CLK_NAFLL_TSEC + * @def TEGRA186_CLK_NAFLL_TSECB + * @def TEGRA186_CLK_NAFLL_VI + * @def TEGRA186_CLK_NAFLL_VIC + * @} + * + * @defgroup mphy MPHY related clocks + * @{ + * @def TEGRA186_CLK_MPHY_L0_RX_SYMB + * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT + * @def TEGRA186_CLK_MPHY_L0_TX_SYMB + * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT + * @def TEGRA186_CLK_MPHY_L0_RX_ANA + * @def TEGRA186_CLK_MPHY_L1_RX_ANA + * @def TEGRA186_CLK_MPHY_IOBIST + * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF + * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED + * @} + * + * @defgroup eavb EAVB related clocks + * @{ + * @def TEGRA186_CLK_EQOS_AXI + * @def TEGRA186_CLK_EQOS_PTP_REF + * @def TEGRA186_CLK_EQOS_RX + * @def TEGRA186_CLK_EQOS_RX_INPUT + * @def TEGRA186_CLK_EQOS_TX + * @} + * + * @defgroup usb USB related clocks + * @{ + * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT + * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT + * @def TEGRA186_CLK_HSIC_TRK + * @def TEGRA186_CLK_USB2_TRK + * @def TEGRA186_CLK_USB2_HSIC_TRK + * @def TEGRA186_CLK_XUSB_CORE_SS + * @def TEGRA186_CLK_XUSB_CORE_DEV + * @def TEGRA186_CLK_XUSB_FALCON + * @def TEGRA186_CLK_XUSB_FS + * @def TEGRA186_CLK_XUSB + * @def TEGRA186_CLK_XUSB_DEV + * @def TEGRA186_CLK_XUSB_HOST + * @def TEGRA186_CLK_XUSB_SS + * @} + * + * @defgroup bigblock compute block related clocks + * @{ + * @def TEGRA186_CLK_GPCCLK + * @def TEGRA186_CLK_GPC2CLK + * @def TEGRA186_CLK_GPU + * @def TEGRA186_CLK_HOST1X + * @def TEGRA186_CLK_ISP + * @def TEGRA186_CLK_NVDEC + * @def TEGRA186_CLK_NVENC + * @def TEGRA186_CLK_NVJPG + * @def TEGRA186_CLK_SE + * @def TEGRA186_CLK_TSEC + * @def TEGRA186_CLK_TSECB + * @def TEGRA186_CLK_VIC + * @} + * + * @defgroup can CAN bus related clocks + * @{ + * @def TEGRA186_CLK_CAN1 + * @def TEGRA186_CLK_CAN1_HOST + * @def TEGRA186_CLK_CAN2 + * @def TEGRA186_CLK_CAN2_HOST + * @} + * + * @defgroup system basic system clocks + * @{ + * @def TEGRA186_CLK_ACTMON + * @def TEGRA186_CLK_AON_APB + * @def TEGRA186_CLK_AON_CPU_NIC + * @def TEGRA186_CLK_AON_NIC + * @def TEGRA186_CLK_AXI_CBB + * @def TEGRA186_CLK_BPMP_APB + * @def TEGRA186_CLK_BPMP_CPU_NIC + * @def TEGRA186_CLK_BPMP_NIC_RATE + * @def TEGRA186_CLK_CLK_M + * @def TEGRA186_CLK_EMC + * @def TEGRA186_CLK_MSS_ENCRYPT + * @def TEGRA186_CLK_SCE_APB + * @def TEGRA186_CLK_SCE_CPU_NIC + * @def TEGRA186_CLK_SCE_NIC + * @def TEGRA186_CLK_TSC + * @} + * + * @defgroup pcie_clks PCIe related clocks + * @{ + * @def TEGRA186_CLK_AFI + * @def TEGRA186_CLK_PCIE + * @def TEGRA186_CLK_PCIE2_IOBIST + * @def TEGRA186_CLK_PCIERX0 + * @def TEGRA186_CLK_PCIERX1 + * @def TEGRA186_CLK_PCIERX2 + * @def TEGRA186_CLK_PCIERX3 + * @def TEGRA186_CLK_PCIERX4 + * @} + */ + +/** @brief output of gate CLK_ENB_FUSE */ +#define TEGRA186_CLK_FUSE 0 +/** + * @brief It's not what you think + * @details output of gate CLK_ENB_GPU. This output connects to the GPU + * pwrclk. @warning: This is almost certainly not the clock you think + * it is. If you're looking for the clock of the graphics engine, see + * TEGRA186_GPCCLK + */ +#define TEGRA186_CLK_GPU 1 +/** @brief output of gate CLK_ENB_PCIE */ +#define TEGRA186_CLK_PCIE 3 +/** @brief output of the divider IPFS_CLK_DIVISOR */ +#define TEGRA186_CLK_AFI 4 +/** @brief output of gate CLK_ENB_PCIE2_IOBIST */ +#define TEGRA186_CLK_PCIE2_IOBIST 5 +/** @brief output of gate CLK_ENB_PCIERX0*/ +#define TEGRA186_CLK_PCIERX0 6 +/** @brief output of gate CLK_ENB_PCIERX1*/ +#define TEGRA186_CLK_PCIERX1 7 +/** @brief output of gate CLK_ENB_PCIERX2*/ +#define TEGRA186_CLK_PCIERX2 8 +/** @brief output of gate CLK_ENB_PCIERX3*/ +#define TEGRA186_CLK_PCIERX3 9 +/** @brief output of gate CLK_ENB_PCIERX4*/ +#define TEGRA186_CLK_PCIERX4 10 +/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */ +#define TEGRA186_CLK_PLLC_OUT_ISP 11 +/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */ +#define TEGRA186_CLK_PLLC_OUT_VE 12 +/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */ +#define TEGRA186_CLK_PLLC_OUT_AON 13 +/** @brief output of gate CLK_ENB_SOR_SAFE */ +#define TEGRA186_CLK_SOR_SAFE 39 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ +#define TEGRA186_CLK_I2S2 42 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ +#define TEGRA186_CLK_I2S3 43 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */ +#define TEGRA186_CLK_SPDIF_IN 44 +/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */ +#define TEGRA186_CLK_SPDIF_DOUBLER 45 +/** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */ +#define TEGRA186_CLK_SPI3 46 +/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */ +#define TEGRA186_CLK_I2C1 47 +/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */ +#define TEGRA186_CLK_I2C5 48 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */ +#define TEGRA186_CLK_SPI1 49 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */ +#define TEGRA186_CLK_ISP 50 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */ +#define TEGRA186_CLK_VI 51 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */ +#define TEGRA186_CLK_SDMMC1 52 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */ +#define TEGRA186_CLK_SDMMC2 53 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ +#define TEGRA186_CLK_SDMMC4 54 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ +#define TEGRA186_CLK_UARTA 55 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */ +#define TEGRA186_CLK_UARTB 56 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ +#define TEGRA186_CLK_HOST1X 57 +/** + * @brief controls the EMC clock frequency. + * @details Doing a clk_set_rate on this clock will select the + * appropriate clock source, program the source rate and execute a + * specific sequence to switch to the new clock source for both memory + * controllers. This can be used to control the balance between memory + * throughput and memory controller power. + */ +#define TEGRA186_CLK_EMC 58 +/* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */ +#define TEGRA186_CLK_EXTPERIPH4 73 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */ +#define TEGRA186_CLK_SPI4 74 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ +#define TEGRA186_CLK_I2C3 75 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */ +#define TEGRA186_CLK_SDMMC3 76 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */ +#define TEGRA186_CLK_UARTD 77 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ +#define TEGRA186_CLK_I2S1 79 +/** output of gate CLK_ENB_DTV */ +#define TEGRA186_CLK_DTV 80 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */ +#define TEGRA186_CLK_TSEC 81 +/** @brief output of gate CLK_ENB_DP2 */ +#define TEGRA186_CLK_DP2 82 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ +#define TEGRA186_CLK_I2S4 84 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ +#define TEGRA186_CLK_I2S5 85 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ +#define TEGRA186_CLK_I2C4 86 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ +#define TEGRA186_CLK_AHUB 87 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */ +#define TEGRA186_CLK_HDA2CODEC_2X 88 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */ +#define TEGRA186_CLK_EXTPERIPH1 89 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */ +#define TEGRA186_CLK_EXTPERIPH2 90 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */ +#define TEGRA186_CLK_EXTPERIPH3 91 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */ +#define TEGRA186_CLK_I2C_SLOW 92 +/** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ +#define TEGRA186_CLK_SOR1 93 +/** @brief output of gate CLK_ENB_CEC */ +#define TEGRA186_CLK_CEC 94 +/** @brief output of gate CLK_ENB_DPAUX1 */ +#define TEGRA186_CLK_DPAUX1 95 +/** @brief output of gate CLK_ENB_DPAUX */ +#define TEGRA186_CLK_DPAUX 96 +/** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ +#define TEGRA186_CLK_SOR0 97 +/** @brief output of gate CLK_ENB_HDA2HDMICODEC */ +#define TEGRA186_CLK_HDA2HDMICODEC 98 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */ +#define TEGRA186_CLK_SATA 99 +/** @brief output of gate CLK_ENB_SATA_OOB */ +#define TEGRA186_CLK_SATA_OOB 100 +/** @brief output of gate CLK_ENB_SATA_IOBIST */ +#define TEGRA186_CLK_SATA_IOBIST 101 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */ +#define TEGRA186_CLK_HDA 102 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */ +#define TEGRA186_CLK_SE 103 +/** @brief output of gate CLK_ENB_APB2APE */ +#define TEGRA186_CLK_APB2APE 104 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ +#define TEGRA186_CLK_APE 105 +/** @brief output of gate CLK_ENB_IQC1 */ +#define TEGRA186_CLK_IQC1 106 +/** @brief output of gate CLK_ENB_IQC2 */ +#define TEGRA186_CLK_IQC2 107 +/** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */ +#define TEGRA186_CLK_PLLREFE_OUT 108 +/** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */ +#define TEGRA186_CLK_PLLREFE_PLL_REF 109 +/** @brief output of gate CLK_ENB_PLLC4_OUT */ +#define TEGRA186_CLK_PLLC4_OUT 110 +/** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB 111 +/** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_DEV 112 +/** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_HOST 113 +/** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_SS 114 +/** @brief output of gate CLK_ENB_DSI */ +#define TEGRA186_CLK_DSI 115 +/** @brief output of gate CLK_ENB_MIPI_CAL */ +#define TEGRA186_CLK_MIPI_CAL 116 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */ +#define TEGRA186_CLK_DSIA_LP 117 +/** @brief output of gate CLK_ENB_DSIB */ +#define TEGRA186_CLK_DSIB 118 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */ +#define TEGRA186_CLK_DSIB_LP 119 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ +#define TEGRA186_CLK_DMIC1 122 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ +#define TEGRA186_CLK_DMIC2 123 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ +#define TEGRA186_CLK_AUD_MCLK 124 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ +#define TEGRA186_CLK_I2C6 125 +/**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */ +#define TEGRA186_CLK_UART_FST_MIPI_CAL 126 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ +#define TEGRA186_CLK_VIC 127 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */ +#define TEGRA186_CLK_SDMMC_LEGACY_TM 128 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ +#define TEGRA186_CLK_NVDEC 129 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */ +#define TEGRA186_CLK_NVJPG 130 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */ +#define TEGRA186_CLK_NVENC 131 +/** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ +#define TEGRA186_CLK_QSPI 132 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */ +#define TEGRA186_CLK_VI_I2C 133 +/** @brief output of gate CLK_ENB_HSIC_TRK */ +#define TEGRA186_CLK_HSIC_TRK 134 +/** @brief output of gate CLK_ENB_USB2_TRK */ +#define TEGRA186_CLK_USB2_TRK 135 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */ +#define TEGRA186_CLK_MAUD 136 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */ +#define TEGRA186_CLK_TSECB 137 +/** @brief output of gate CLK_ENB_ADSP */ +#define TEGRA186_CLK_ADSP 138 +/** @brief output of gate CLK_ENB_ADSPNEON */ +#define TEGRA186_CLK_ADSPNEON 139 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */ +#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140 +/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */ +#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */ +#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142 +/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */ +#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143 +/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */ +#define TEGRA186_CLK_MPHY_L0_RX_ANA 144 +/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */ +#define TEGRA186_CLK_MPHY_L1_RX_ANA 145 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */ +#define TEGRA186_CLK_MPHY_IOBIST 146 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */ +#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */ +#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */ +#define TEGRA186_CLK_AXI_CBB 149 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ +#define TEGRA186_CLK_DMIC3 150 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ +#define TEGRA186_CLK_DMIC4 151 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ +#define TEGRA186_CLK_DSPK1 152 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ +#define TEGRA186_CLK_DSPK2 153 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ +#define TEGRA186_CLK_I2S6 154 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */ +#define TEGRA186_CLK_NVDISPLAY_P0 155 +/** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */ +#define TEGRA186_CLK_NVDISPLAY_DISP 156 +/** @brief output of gate CLK_ENB_NVDISPLAY_DSC */ +#define TEGRA186_CLK_NVDISPLAY_DSC 157 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */ +#define TEGRA186_CLK_NVDISPLAYHUB 158 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */ +#define TEGRA186_CLK_NVDISPLAY_P1 159 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */ +#define TEGRA186_CLK_NVDISPLAY_P2 160 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */ +#define TEGRA186_CLK_TACH 166 +/** @brief output of gate CLK_ENB_EQOS */ +#define TEGRA186_CLK_EQOS_AXI 167 +/** @brief output of gate CLK_ENB_EQOS_RX */ +#define TEGRA186_CLK_EQOS_RX 168 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */ +#define TEGRA186_CLK_UFSHC 178 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */ +#define TEGRA186_CLK_UFSDEV_REF 179 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */ +#define TEGRA186_CLK_NVCSI 180 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */ +#define TEGRA186_CLK_NVCSILP 181 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ +#define TEGRA186_CLK_I2C7 182 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ +#define TEGRA186_CLK_I2C9 183 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */ +#define TEGRA186_CLK_I2C12 184 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */ +#define TEGRA186_CLK_I2C13 185 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */ +#define TEGRA186_CLK_I2C14 186 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ +#define TEGRA186_CLK_PWM1 187 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ +#define TEGRA186_CLK_PWM2 188 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ +#define TEGRA186_CLK_PWM3 189 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ +#define TEGRA186_CLK_PWM5 190 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ +#define TEGRA186_CLK_PWM6 191 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ +#define TEGRA186_CLK_PWM7 192 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ +#define TEGRA186_CLK_PWM8 193 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */ +#define TEGRA186_CLK_UARTE 194 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */ +#define TEGRA186_CLK_UARTF 195 +/** @deprecated */ +#define TEGRA186_CLK_DBGAPB 196 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */ +#define TEGRA186_CLK_BPMP_CPU_NIC 197 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */ +#define TEGRA186_CLK_BPMP_APB 199 +/** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */ +#define TEGRA186_CLK_ACTMON 201 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */ +#define TEGRA186_CLK_AON_CPU_NIC 208 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */ +#define TEGRA186_CLK_CAN1 210 +/** @brief output of gate CLK_ENB_CAN1_HOST */ +#define TEGRA186_CLK_CAN1_HOST 211 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */ +#define TEGRA186_CLK_CAN2 212 +/** @brief output of gate CLK_ENB_CAN2_HOST */ +#define TEGRA186_CLK_CAN2_HOST 213 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */ +#define TEGRA186_CLK_AON_APB 214 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */ +#define TEGRA186_CLK_UARTC 215 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */ +#define TEGRA186_CLK_UARTG 216 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */ +#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ +#define TEGRA186_CLK_I2C2 218 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ +#define TEGRA186_CLK_I2C8 219 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */ +#define TEGRA186_CLK_I2C10 220 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */ +#define TEGRA186_CLK_AON_I2C_SLOW 221 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */ +#define TEGRA186_CLK_SPI2 222 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */ +#define TEGRA186_CLK_DMIC5 223 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */ +#define TEGRA186_CLK_AON_TOUCH 224 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ +#define TEGRA186_CLK_PWM4 225 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */ +#define TEGRA186_CLK_TSC 226 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */ +#define TEGRA186_CLK_MSS_ENCRYPT 227 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */ +#define TEGRA186_CLK_SCE_CPU_NIC 228 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */ +#define TEGRA186_CLK_SCE_APB 230 +/** @brief output of gate CLK_ENB_DSIC */ +#define TEGRA186_CLK_DSIC 231 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */ +#define TEGRA186_CLK_DSIC_LP 232 +/** @brief output of gate CLK_ENB_DSID */ +#define TEGRA186_CLK_DSID 233 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */ +#define TEGRA186_CLK_DSID_LP 234 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */ +#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */ +#define TEGRA186_CLK_SPDIF_OUT 238 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */ +#define TEGRA186_CLK_EQOS_PTP_REF 239 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */ +#define TEGRA186_CLK_EQOS_TX 240 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */ +#define TEGRA186_CLK_USB2_HSIC_TRK 241 +/** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_CORE_SS 242 +/** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_CORE_DEV 243 +/** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_FALCON 244 +/** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_FS 245 +/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ +#define TEGRA186_CLK_PLL_A_OUT0 246 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ +#define TEGRA186_CLK_SYNC_I2S1 247 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ +#define TEGRA186_CLK_SYNC_I2S2 248 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ +#define TEGRA186_CLK_SYNC_I2S3 249 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ +#define TEGRA186_CLK_SYNC_I2S4 250 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ +#define TEGRA186_CLK_SYNC_I2S5 251 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ +#define TEGRA186_CLK_SYNC_I2S6 252 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ +#define TEGRA186_CLK_SYNC_DSPK1 253 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ +#define TEGRA186_CLK_SYNC_DSPK2 254 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ +#define TEGRA186_CLK_SYNC_DMIC1 255 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ +#define TEGRA186_CLK_SYNC_DMIC2 256 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ +#define TEGRA186_CLK_SYNC_DMIC3 257 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ +#define TEGRA186_CLK_SYNC_DMIC4 259 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */ +#define TEGRA186_CLK_SYNC_SPDIF 260 +/** @brief output of gate CLK_ENB_PLLREFE_OUT */ +#define TEGRA186_CLK_PLLREFE_OUT_GATED 261 +/** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs: + * * VCO/pdiv defined by this clock object + * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT + */ +#define TEGRA186_CLK_PLLREFE_OUT1 262 +#define TEGRA186_CLK_PLLD_OUT1 267 +/** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */ +#define TEGRA186_CLK_PLLP_OUT0 269 +/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */ +#define TEGRA186_CLK_PLLP_OUT5 270 +/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ +#define TEGRA186_CLK_PLLA 271 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */ +#define TEGRA186_CLK_ACLK 273 +/** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */ +#define TEGRA186_CLK_PLL_U_48M 274 +/** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */ +#define TEGRA186_CLK_PLL_U_480M 275 +/** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */ +#define TEGRA186_CLK_PLLC4_OUT0 276 +/** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */ +#define TEGRA186_CLK_PLLC4_OUT1 277 +/** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */ +#define TEGRA186_CLK_PLLC4_OUT2 278 +/** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */ +#define TEGRA186_CLK_PLLC4_OUT_MUX 279 +/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ +#define TEGRA186_CLK_DFLLDISP_DIV 284 +/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ +#define TEGRA186_CLK_PLLDISPHUB_DIV 285 +/** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */ +#define TEGRA186_CLK_PLLP_DIV8 286 +/** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */ +#define TEGRA186_CLK_BPMP_NIC 287 +/** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */ +#define TEGRA186_CLK_PLL_A_OUT1 288 +/** @deprecated */ +#define TEGRA186_CLK_GPC2CLK 289 +/** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */ +#define TEGRA186_CLK_KFUSE 293 +/** + * @brief controls the PLLE hardware sequencer. + * @details This clock only has enable and disable methods. When the + * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by + * hw based on the control signals from the PCIe, SATA and XUSB + * clocks. When the PLLE hw sequencer is disabled, the state of PLLE + * is controlled by sw using clk_enable/clk_disable on + * TEGRA186_CLK_PLLE. + */ +#define TEGRA186_CLK_PLLE_PWRSEQ 294 +/** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */ +#define TEGRA186_CLK_PLLREFE_REF 295 +/** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ +#define TEGRA186_CLK_SOR0_OUT 296 +/** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ +#define TEGRA186_CLK_SOR1_OUT 297 +/** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */ +#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298 +/** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */ +#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */ +#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */ +#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303 +/** @brief controls the UPHY_PLL0 hardware sqeuencer */ +#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304 +/** @brief controls the UPHY_PLL1 hardware sqeuencer */ +#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305 +/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */ +#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306 +/** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */ +#define TEGRA186_CLK_PLLREFE_PEX 307 +/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */ +#define TEGRA186_CLK_PLLREFE_IDDQ 308 +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ +#define TEGRA186_CLK_QSPI_OUT 309 +/** + * @brief GPC2CLK-div-2 + * @details fixed /2 divider. Output frequency is + * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the + * frequency at which the GPU graphics engine runs. */ +#define TEGRA186_CLK_GPCCLK 310 +/** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */ +#define TEGRA186_CLK_AON_NIC 450 +/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */ +#define TEGRA186_CLK_SCE_NIC 451 +/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */ +#define TEGRA186_CLK_PLLE 512 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */ +#define TEGRA186_CLK_PLLC 513 +/** Fixed 408MHz PLL for use by peripheral clocks */ +#define TEGRA186_CLK_PLLP 516 +/** @deprecated */ +#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */ +#define TEGRA186_CLK_PLLD 518 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */ +#define TEGRA186_CLK_PLLD2 519 +/** + * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE. + * @details Note that this clock only controls the VCO output, before + * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more + * information. + */ +#define TEGRA186_CLK_PLLREFE_VCO 520 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */ +#define TEGRA186_CLK_PLLC2 521 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */ +#define TEGRA186_CLK_PLLC3 522 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */ +#define TEGRA186_CLK_PLLDP 523 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ +#define TEGRA186_CLK_PLLC4_VCO 524 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */ +#define TEGRA186_CLK_PLLA1 525 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */ +#define TEGRA186_CLK_PLLNVCSI 526 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */ +#define TEGRA186_CLK_PLLDISPHUB 527 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */ +#define TEGRA186_CLK_PLLD3 528 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */ +#define TEGRA186_CLK_PLLBPMPCAM 531 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */ +#define TEGRA186_CLK_PLLAON 532 +/** Fixed frequency 960MHz PLL for USB and EAVB */ +#define TEGRA186_CLK_PLLU 533 +/** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */ +#define TEGRA186_CLK_PLLC4_VCO_DIV2 535 +/** @brief NAFLL clock source for AXI_CBB */ +#define TEGRA186_CLK_NAFLL_AXI_CBB 564 +/** @brief NAFLL clock source for BPMP */ +#define TEGRA186_CLK_NAFLL_BPMP 565 +/** @brief NAFLL clock source for ISP */ +#define TEGRA186_CLK_NAFLL_ISP 566 +/** @brief NAFLL clock source for NVDEC */ +#define TEGRA186_CLK_NAFLL_NVDEC 567 +/** @brief NAFLL clock source for NVENC */ +#define TEGRA186_CLK_NAFLL_NVENC 568 +/** @brief NAFLL clock source for NVJPG */ +#define TEGRA186_CLK_NAFLL_NVJPG 569 +/** @brief NAFLL clock source for SCE */ +#define TEGRA186_CLK_NAFLL_SCE 570 +/** @brief NAFLL clock source for SE */ +#define TEGRA186_CLK_NAFLL_SE 571 +/** @brief NAFLL clock source for TSEC */ +#define TEGRA186_CLK_NAFLL_TSEC 572 +/** @brief NAFLL clock source for TSECB */ +#define TEGRA186_CLK_NAFLL_TSECB 573 +/** @brief NAFLL clock source for VI */ +#define TEGRA186_CLK_NAFLL_VI 574 +/** @brief NAFLL clock source for VIC */ +#define TEGRA186_CLK_NAFLL_VIC 575 +/** @brief NAFLL clock source for DISP */ +#define TEGRA186_CLK_NAFLL_DISP 576 +/** @brief NAFLL clock source for GPU */ +#define TEGRA186_CLK_NAFLL_GPU 577 +/** @brief NAFLL clock source for M-CPU cluster */ +#define TEGRA186_CLK_NAFLL_MCPU 578 +/** @brief NAFLL clock source for B-CPU cluster */ +#define TEGRA186_CLK_NAFLL_BCPU 579 +/** @brief input from Tegra's CLK_32K_IN pad */ +#define TEGRA186_CLK_CLK_32K 608 +/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */ +#define TEGRA186_CLK_CLK_M 609 +/** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */ +#define TEGRA186_CLK_PLL_REF 610 +/** @brief input from Tegra's XTAL_IN */ +#define TEGRA186_CLK_OSC 612 +/** @brief clock recovered from EAVB input */ +#define TEGRA186_CLK_EQOS_RX_INPUT 613 +/** @brief clock recovered from DTV input */ +#define TEGRA186_CLK_DTV_INPUT 614 +/** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/ +#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615 +/** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/ +#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616 +/** @brief clock recovered from I2S1 input */ +#define TEGRA186_CLK_I2S1_SYNC_INPUT 617 +/** @brief clock recovered from I2S2 input */ +#define TEGRA186_CLK_I2S2_SYNC_INPUT 618 +/** @brief clock recovered from I2S3 input */ +#define TEGRA186_CLK_I2S3_SYNC_INPUT 619 +/** @brief clock recovered from I2S4 input */ +#define TEGRA186_CLK_I2S4_SYNC_INPUT 620 +/** @brief clock recovered from I2S5 input */ +#define TEGRA186_CLK_I2S5_SYNC_INPUT 621 +/** @brief clock recovered from I2S6 input */ +#define TEGRA186_CLK_I2S6_SYNC_INPUT 622 +/** @brief clock recovered from SPDIFIN input */ +#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623 + +/** + * @brief subject to change + * @details maximum clock identifier value plus one. + */ +#define TEGRA186_CLK_CLK_MAX 624 + +/** @} */ + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/tegra20-car.h b/roms/u-boot/include/dt-bindings/clock/tegra20-car.h new file mode 100644 index 000000000..04500b243 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/tegra20-car.h @@ -0,0 +1,158 @@ +/* + * This header provides constants for binding nvidia,tegra20-car. + * + * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + * registers. These IDs often match those in the CAR's RST_DEVICES registers, + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + * this case, those clocks are assigned IDs above 95 in order to highlight + * this issue. Implementations that interpret these clock IDs as bit values + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + * explicitly handle these special cases. + * + * The balance of the clocks controlled by the CAR are assigned IDs of 96 and + * above. + */ + +#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H +#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H + +#define TEGRA20_CLK_CPU 0 +/* 1 */ +/* 2 */ +#define TEGRA20_CLK_AC97 3 +#define TEGRA20_CLK_RTC 4 +#define TEGRA20_CLK_TIMER 5 +#define TEGRA20_CLK_UARTA 6 +/* 7 (register bit affects uart2 and vfir) */ +#define TEGRA20_CLK_GPIO 8 +#define TEGRA20_CLK_SDMMC2 9 +/* 10 (register bit affects spdif_in and spdif_out) */ +#define TEGRA20_CLK_I2S1 11 +#define TEGRA20_CLK_I2C1 12 +#define TEGRA20_CLK_NDFLASH 13 +#define TEGRA20_CLK_SDMMC1 14 +#define TEGRA20_CLK_SDMMC4 15 +#define TEGRA20_CLK_TWC 16 +#define TEGRA20_CLK_PWM 17 +#define TEGRA20_CLK_I2S2 18 +#define TEGRA20_CLK_EPP 19 +/* 20 (register bit affects vi and vi_sensor) */ +#define TEGRA20_CLK_GR2D 21 +#define TEGRA20_CLK_USBD 22 +#define TEGRA20_CLK_ISP 23 +#define TEGRA20_CLK_GR3D 24 +#define TEGRA20_CLK_IDE 25 +#define TEGRA20_CLK_DISP2 26 +#define TEGRA20_CLK_DISP1 27 +#define TEGRA20_CLK_HOST1X 28 +#define TEGRA20_CLK_VCP 29 +/* 30 */ +#define TEGRA20_CLK_CACHE2 31 + +#define TEGRA20_CLK_MC 32 +#define TEGRA20_CLK_AHBDMA 33 +#define TEGRA20_CLK_APBDMA 34 +/* 35 */ +#define TEGRA20_CLK_KBC 36 +#define TEGRA20_CLK_STAT_MON 37 +#define TEGRA20_CLK_PMC 38 +#define TEGRA20_CLK_FUSE 39 +#define TEGRA20_CLK_KFUSE 40 +#define TEGRA20_CLK_SBC1 41 +#define TEGRA20_CLK_NOR 42 +#define TEGRA20_CLK_SPI 43 +#define TEGRA20_CLK_SBC2 44 +#define TEGRA20_CLK_XIO 45 +#define TEGRA20_CLK_SBC3 46 +#define TEGRA20_CLK_DVC 47 +#define TEGRA20_CLK_DSI 48 +/* 49 (register bit affects tvo and cve) */ +#define TEGRA20_CLK_MIPI 50 +#define TEGRA20_CLK_HDMI 51 +#define TEGRA20_CLK_CSI 52 +#define TEGRA20_CLK_TVDAC 53 +#define TEGRA20_CLK_I2C2 54 +#define TEGRA20_CLK_UARTC 55 +/* 56 */ +#define TEGRA20_CLK_EMC 57 +#define TEGRA20_CLK_USB2 58 +#define TEGRA20_CLK_USB3 59 +#define TEGRA20_CLK_MPE 60 +#define TEGRA20_CLK_VDE 61 +#define TEGRA20_CLK_BSEA 62 +#define TEGRA20_CLK_BSEV 63 + +#define TEGRA20_CLK_SPEEDO 64 +#define TEGRA20_CLK_UARTD 65 +#define TEGRA20_CLK_UARTE 66 +#define TEGRA20_CLK_I2C3 67 +#define TEGRA20_CLK_SBC4 68 +#define TEGRA20_CLK_SDMMC3 69 +#define TEGRA20_CLK_PEX 70 +#define TEGRA20_CLK_OWR 71 +#define TEGRA20_CLK_AFI 72 +#define TEGRA20_CLK_CSITE 73 +/* 74 */ +#define TEGRA20_CLK_AVPUCQ 75 +#define TEGRA20_CLK_LA 76 +/* 77 */ +/* 78 */ +/* 79 */ +/* 80 */ +/* 81 */ +/* 82 */ +/* 83 */ +#define TEGRA20_CLK_IRAMA 84 +#define TEGRA20_CLK_IRAMB 85 +#define TEGRA20_CLK_IRAMC 86 +#define TEGRA20_CLK_IRAMD 87 +#define TEGRA20_CLK_CRAM2 88 +#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */ +#define TEGRA20_CLK_CLK_D 90 +/* 91 */ +#define TEGRA20_CLK_CSUS 92 +#define TEGRA20_CLK_CDEV2 93 +#define TEGRA20_CLK_CDEV1 94 +/* 95 */ + +#define TEGRA20_CLK_UARTB 96 +#define TEGRA20_CLK_VFIR 97 +#define TEGRA20_CLK_SPDIF_IN 98 +#define TEGRA20_CLK_SPDIF_OUT 99 +#define TEGRA20_CLK_VI 100 +#define TEGRA20_CLK_VI_SENSOR 101 +#define TEGRA20_CLK_TVO 102 +#define TEGRA20_CLK_CVE 103 +#define TEGRA20_CLK_OSC 104 +#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */ +#define TEGRA20_CLK_CLK_M 106 +#define TEGRA20_CLK_SCLK 107 +#define TEGRA20_CLK_CCLK 108 +#define TEGRA20_CLK_HCLK 109 +#define TEGRA20_CLK_PCLK 110 +#define TEGRA20_CLK_BLINK 111 +#define TEGRA20_CLK_PLL_A 112 +#define TEGRA20_CLK_PLL_A_OUT0 113 +#define TEGRA20_CLK_PLL_C 114 +#define TEGRA20_CLK_PLL_C_OUT1 115 +#define TEGRA20_CLK_PLL_D 116 +#define TEGRA20_CLK_PLL_D_OUT0 117 +#define TEGRA20_CLK_PLL_E 118 +#define TEGRA20_CLK_PLL_M 119 +#define TEGRA20_CLK_PLL_M_OUT1 120 +#define TEGRA20_CLK_PLL_P 121 +#define TEGRA20_CLK_PLL_P_OUT1 122 +#define TEGRA20_CLK_PLL_P_OUT2 123 +#define TEGRA20_CLK_PLL_P_OUT3 124 +#define TEGRA20_CLK_PLL_P_OUT4 125 +#define TEGRA20_CLK_PLL_S 126 +#define TEGRA20_CLK_PLL_U 127 + +#define TEGRA20_CLK_PLL_X 128 +#define TEGRA20_CLK_COP 129 /* a/k/a avp */ +#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */ +#define TEGRA20_CLK_PLL_REF 131 +#define TEGRA20_CLK_TWD 132 +#define TEGRA20_CLK_CLK_MAX 133 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/tegra210-car.h b/roms/u-boot/include/dt-bindings/clock/tegra210-car.h new file mode 100644 index 000000000..bd3530e56 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/tegra210-car.h @@ -0,0 +1,401 @@ +/* + * This header provides constants for binding nvidia,tegra210-car. + * + * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + * registers. These IDs often match those in the CAR's RST_DEVICES registers, + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + * this case, those clocks are assigned IDs above 224 in order to highlight + * this issue. Implementations that interpret these clock IDs as bit values + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + * explicitly handle these special cases. + * + * The balance of the clocks controlled by the CAR are assigned IDs of 224 and + * above. + */ + +#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H +#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H + +/* 0 */ +/* 1 */ +/* 2 */ +#define TEGRA210_CLK_ISPB 3 +#define TEGRA210_CLK_RTC 4 +#define TEGRA210_CLK_TIMER 5 +#define TEGRA210_CLK_UARTA 6 +/* 7 (register bit affects uartb and vfir) */ +#define TEGRA210_CLK_GPIO 8 +#define TEGRA210_CLK_SDMMC2 9 +/* 10 (register bit affects spdif_in and spdif_out) */ +#define TEGRA210_CLK_I2S1 11 +#define TEGRA210_CLK_I2C1 12 +/* 13 */ +#define TEGRA210_CLK_SDMMC1 14 +#define TEGRA210_CLK_SDMMC4 15 +/* 16 */ +#define TEGRA210_CLK_PWM 17 +#define TEGRA210_CLK_I2S2 18 +/* 19 */ +/* 20 (register bit affects vi and vi_sensor) */ +/* 21 */ +#define TEGRA210_CLK_USBD 22 +#define TEGRA210_CLK_ISP 23 +/* 24 */ +/* 25 */ +#define TEGRA210_CLK_DISP2 26 +#define TEGRA210_CLK_DISP1 27 +#define TEGRA210_CLK_HOST1X 28 +/* 29 */ +#define TEGRA210_CLK_I2S0 30 +/* 31 */ + +#define TEGRA210_CLK_MC 32 +#define TEGRA210_CLK_AHBDMA 33 +#define TEGRA210_CLK_APBDMA 34 +/* 35 */ +/* 36 */ +/* 37 */ +#define TEGRA210_CLK_PMC 38 +/* 39 (register bit affects fuse and fuse_burn) */ +#define TEGRA210_CLK_KFUSE 40 +#define TEGRA210_CLK_SBC1 41 +/* 42 */ +/* 43 */ +#define TEGRA210_CLK_SBC2 44 +/* 45 */ +#define TEGRA210_CLK_SBC3 46 +#define TEGRA210_CLK_I2C5 47 +#define TEGRA210_CLK_DSIA 48 +/* 49 */ +/* 50 */ +/* 51 */ +#define TEGRA210_CLK_CSI 52 +/* 53 */ +#define TEGRA210_CLK_I2C2 54 +#define TEGRA210_CLK_UARTC 55 +#define TEGRA210_CLK_MIPI_CAL 56 +#define TEGRA210_CLK_EMC 57 +#define TEGRA210_CLK_USB2 58 +/* 59 */ +/* 60 */ +/* 61 */ +/* 62 */ +#define TEGRA210_CLK_BSEV 63 + +/* 64 */ +#define TEGRA210_CLK_UARTD 65 +/* 66 */ +#define TEGRA210_CLK_I2C3 67 +#define TEGRA210_CLK_SBC4 68 +#define TEGRA210_CLK_SDMMC3 69 +#define TEGRA210_CLK_PCIE 70 +#define TEGRA210_CLK_OWR 71 +#define TEGRA210_CLK_AFI 72 +#define TEGRA210_CLK_CSITE 73 +/* 74 */ +/* 75 */ +/* 76 */ +/* 77 */ +#define TEGRA210_CLK_SOC_THERM 78 +#define TEGRA210_CLK_DTV 79 +/* 80 */ +#define TEGRA210_CLK_I2CSLOW 81 +#define TEGRA210_CLK_DSIB 82 +#define TEGRA210_CLK_TSEC 83 +/* 84 */ +/* 85 */ +/* 86 */ +/* 87 */ +/* 88 */ +#define TEGRA210_CLK_XUSB_HOST 89 +/* 90 */ +/* 91 */ +#define TEGRA210_CLK_CSUS 92 +/* 93 */ +/* 94 */ +/* 95 (bit affects xusb_dev and xusb_dev_src) */ + +/* 96 */ +/* 97 */ +/* 98 */ +#define TEGRA210_CLK_MSELECT 99 +#define TEGRA210_CLK_TSENSOR 100 +#define TEGRA210_CLK_I2S3 101 +#define TEGRA210_CLK_I2S4 102 +#define TEGRA210_CLK_I2C4 103 +/* 104 */ +/* 105 */ +#define TEGRA210_CLK_D_AUDIO 106 +#define TEGRA210_CLK_APB2APE 107 +/* 108 */ +/* 109 */ +/* 110 */ +#define TEGRA210_CLK_HDA2CODEC_2X 111 +/* 112 */ +/* 113 */ +/* 114 */ +/* 115 */ +/* 116 */ +/* 117 */ +#define TEGRA210_CLK_SPDIF_2X 118 +#define TEGRA210_CLK_ACTMON 119 +#define TEGRA210_CLK_EXTERN1 120 +#define TEGRA210_CLK_EXTERN2 121 +#define TEGRA210_CLK_EXTERN3 122 +#define TEGRA210_CLK_SATA_OOB 123 +#define TEGRA210_CLK_SATA 124 +#define TEGRA210_CLK_HDA 125 +/* 126 */ +/* 127 */ + +#define TEGRA210_CLK_HDA2HDMI 128 +/* 129 */ +/* 130 */ +/* 131 */ +/* 132 */ +/* 133 */ +/* 134 */ +/* 135 */ +/* 136 */ +/* 137 */ +/* 138 */ +/* 139 */ +/* 140 */ +/* 141 */ +/* 142 */ +/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */ +#define TEGRA210_CLK_XUSB_GATE 143 +#define TEGRA210_CLK_CILAB 144 +#define TEGRA210_CLK_CILCD 145 +#define TEGRA210_CLK_CILE 146 +#define TEGRA210_CLK_DSIALP 147 +#define TEGRA210_CLK_DSIBLP 148 +#define TEGRA210_CLK_ENTROPY 149 +/* 150 */ +/* 151 */ +/* 152 */ +/* 153 */ +/* 154 */ +/* 155 (bit affects dfll_ref and dfll_soc) */ +#define TEGRA210_CLK_XUSB_SS 156 +/* 157 */ +/* 158 */ +/* 159 */ + +/* 160 */ +#define TEGRA210_CLK_DMIC1 161 +#define TEGRA210_CLK_DMIC2 162 +/* 163 */ +/* 164 */ +/* 165 */ +#define TEGRA210_CLK_I2C6 166 +/* 167 */ +/* 168 */ +/* 169 */ +/* 170 */ +#define TEGRA210_CLK_VIM2_CLK 171 +/* 172 */ +#define TEGRA210_CLK_MIPIBIF 173 +/* 174 */ +/* 175 */ +/* 176 */ +#define TEGRA210_CLK_CLK72MHZ 177 +#define TEGRA210_CLK_VIC03 178 +/* 179 */ +/* 180 */ +#define TEGRA210_CLK_DPAUX 181 +#define TEGRA210_CLK_SOR0 182 +#define TEGRA210_CLK_SOR1 183 +#define TEGRA210_CLK_GPU 184 +#define TEGRA210_CLK_DBGAPB 185 +/* 186 */ +#define TEGRA210_CLK_PLL_P_OUT_ADSP 187 +/* 188 */ +#define TEGRA210_CLK_PLL_G_REF 189 +/* 190 */ +/* 191 */ + +/* 192 */ +#define TEGRA210_CLK_SDMMC_LEGACY 193 +#define TEGRA210_CLK_NVDEC 194 +#define TEGRA210_CLK_NVJPG 195 +/* 196 */ +#define TEGRA210_CLK_DMIC3 197 +#define TEGRA210_CLK_APE 198 +/* 199 */ +/* 200 */ +/* 201 */ +#define TEGRA210_CLK_MAUD 202 +/* 203 */ +/* 204 */ +/* 205 */ +#define TEGRA210_CLK_TSECB 206 +#define TEGRA210_CLK_DPAUX1 207 +#define TEGRA210_CLK_VI_I2C 208 +#define TEGRA210_CLK_HSIC_TRK 209 +#define TEGRA210_CLK_USB2_TRK 210 +#define TEGRA210_CLK_QSPI 211 +#define TEGRA210_CLK_UARTAPE 212 +/* 213 */ +/* 214 */ +/* 215 */ +/* 216 */ +/* 217 */ +/* 218 */ +#define TEGRA210_CLK_NVENC 219 +/* 220 */ +/* 221 */ +#define TEGRA210_CLK_SOR_SAFE 222 +#define TEGRA210_CLK_PLL_P_OUT_CPU 223 + + +#define TEGRA210_CLK_UARTB 224 +#define TEGRA210_CLK_VFIR 225 +#define TEGRA210_CLK_SPDIF_IN 226 +#define TEGRA210_CLK_SPDIF_OUT 227 +#define TEGRA210_CLK_VI 228 +#define TEGRA210_CLK_VI_SENSOR 229 +#define TEGRA210_CLK_FUSE 230 +#define TEGRA210_CLK_FUSE_BURN 231 +#define TEGRA210_CLK_CLK_32K 232 +#define TEGRA210_CLK_CLK_M 233 +#define TEGRA210_CLK_CLK_M_DIV2 234 +#define TEGRA210_CLK_CLK_M_DIV4 235 +#define TEGRA210_CLK_PLL_REF 236 +#define TEGRA210_CLK_PLL_C 237 +#define TEGRA210_CLK_PLL_C_OUT1 238 +#define TEGRA210_CLK_PLL_C2 239 +#define TEGRA210_CLK_PLL_C3 240 +#define TEGRA210_CLK_PLL_M 241 +#define TEGRA210_CLK_PLL_M_OUT1 242 +#define TEGRA210_CLK_PLL_P 243 +#define TEGRA210_CLK_PLL_P_OUT1 244 +#define TEGRA210_CLK_PLL_P_OUT2 245 +#define TEGRA210_CLK_PLL_P_OUT3 246 +#define TEGRA210_CLK_PLL_P_OUT4 247 +#define TEGRA210_CLK_PLL_A 248 +#define TEGRA210_CLK_PLL_A_OUT0 249 +#define TEGRA210_CLK_PLL_D 250 +#define TEGRA210_CLK_PLL_D_OUT0 251 +#define TEGRA210_CLK_PLL_D2 252 +#define TEGRA210_CLK_PLL_D2_OUT0 253 +#define TEGRA210_CLK_PLL_U 254 +#define TEGRA210_CLK_PLL_U_480M 255 + +#define TEGRA210_CLK_PLL_U_60M 256 +#define TEGRA210_CLK_PLL_U_48M 257 +/* 258 */ +#define TEGRA210_CLK_PLL_X 259 +#define TEGRA210_CLK_PLL_X_OUT0 260 +#define TEGRA210_CLK_PLL_RE_VCO 261 +#define TEGRA210_CLK_PLL_RE_OUT 262 +#define TEGRA210_CLK_PLL_E 263 +#define TEGRA210_CLK_SPDIF_IN_SYNC 264 +#define TEGRA210_CLK_I2S0_SYNC 265 +#define TEGRA210_CLK_I2S1_SYNC 266 +#define TEGRA210_CLK_I2S2_SYNC 267 +#define TEGRA210_CLK_I2S3_SYNC 268 +#define TEGRA210_CLK_I2S4_SYNC 269 +#define TEGRA210_CLK_VIMCLK_SYNC 270 +#define TEGRA210_CLK_AUDIO0 271 +#define TEGRA210_CLK_AUDIO1 272 +#define TEGRA210_CLK_AUDIO2 273 +#define TEGRA210_CLK_AUDIO3 274 +#define TEGRA210_CLK_AUDIO4 275 +#define TEGRA210_CLK_SPDIF 276 +#define TEGRA210_CLK_CLK_OUT_1 277 +#define TEGRA210_CLK_CLK_OUT_2 278 +#define TEGRA210_CLK_CLK_OUT_3 279 +#define TEGRA210_CLK_BLINK 280 +/* 281 */ +/* 282 */ +/* 283 */ +#define TEGRA210_CLK_XUSB_HOST_SRC 284 +#define TEGRA210_CLK_XUSB_FALCON_SRC 285 +#define TEGRA210_CLK_XUSB_FS_SRC 286 +#define TEGRA210_CLK_XUSB_SS_SRC 287 + +#define TEGRA210_CLK_XUSB_DEV_SRC 288 +#define TEGRA210_CLK_XUSB_DEV 289 +#define TEGRA210_CLK_XUSB_HS_SRC 290 +#define TEGRA210_CLK_SCLK 291 +#define TEGRA210_CLK_HCLK 292 +#define TEGRA210_CLK_PCLK 293 +#define TEGRA210_CLK_CCLK_G 294 +#define TEGRA210_CLK_CCLK_LP 295 +#define TEGRA210_CLK_DFLL_REF 296 +#define TEGRA210_CLK_DFLL_SOC 297 +#define TEGRA210_CLK_VI_SENSOR2 298 +#define TEGRA210_CLK_PLL_P_OUT5 299 +#define TEGRA210_CLK_CML0 300 +#define TEGRA210_CLK_CML1 301 +#define TEGRA210_CLK_PLL_C4 302 +#define TEGRA210_CLK_PLL_DP 303 +#define TEGRA210_CLK_PLL_E_MUX 304 +#define TEGRA210_CLK_PLL_MB 305 +#define TEGRA210_CLK_PLL_A1 306 +#define TEGRA210_CLK_PLL_D_DSI_OUT 307 +#define TEGRA210_CLK_PLL_C4_OUT0 308 +#define TEGRA210_CLK_PLL_C4_OUT1 309 +#define TEGRA210_CLK_PLL_C4_OUT2 310 +#define TEGRA210_CLK_PLL_C4_OUT3 311 +#define TEGRA210_CLK_PLL_U_OUT 312 +#define TEGRA210_CLK_PLL_U_OUT1 313 +#define TEGRA210_CLK_PLL_U_OUT2 314 +#define TEGRA210_CLK_USB2_HSIC_TRK 315 +#define TEGRA210_CLK_PLL_P_OUT_HSIO 316 +#define TEGRA210_CLK_PLL_P_OUT_XUSB 317 +#define TEGRA210_CLK_XUSB_SSP_SRC 318 +#define TEGRA210_CLK_PLL_RE_OUT1 319 +/* 320 */ +/* 321 */ +/* 322 */ +/* 323 */ +/* 324 */ +/* 325 */ +/* 326 */ +/* 327 */ +/* 328 */ +/* 329 */ +/* 330 */ +/* 331 */ +/* 332 */ +/* 333 */ +/* 334 */ +/* 335 */ +/* 336 */ +/* 337 */ +/* 338 */ +/* 339 */ +/* 340 */ +/* 341 */ +/* 342 */ +/* 343 */ +/* 344 */ +/* 345 */ +/* 346 */ +/* 347 */ +/* 348 */ +/* 349 */ + +#define TEGRA210_CLK_AUDIO0_MUX 350 +#define TEGRA210_CLK_AUDIO1_MUX 351 +#define TEGRA210_CLK_AUDIO2_MUX 352 +#define TEGRA210_CLK_AUDIO3_MUX 353 +#define TEGRA210_CLK_AUDIO4_MUX 354 +#define TEGRA210_CLK_SPDIF_MUX 355 +#define TEGRA210_CLK_CLK_OUT_1_MUX 356 +#define TEGRA210_CLK_CLK_OUT_2_MUX 357 +#define TEGRA210_CLK_CLK_OUT_3_MUX 358 +#define TEGRA210_CLK_DSIA_MUX 359 +#define TEGRA210_CLK_DSIB_MUX 360 +#define TEGRA210_CLK_SOR0_LVDS 361 +#define TEGRA210_CLK_XUSB_SS_DIV2 362 + +#define TEGRA210_CLK_PLL_M_UD 363 +#define TEGRA210_CLK_PLL_C_UD 364 +#define TEGRA210_CLK_SCLK_MUX 365 + +#define TEGRA210_CLK_CLK_MAX 366 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/tegra30-car.h b/roms/u-boot/include/dt-bindings/clock/tegra30-car.h new file mode 100644 index 000000000..889e49ba0 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/tegra30-car.h @@ -0,0 +1,273 @@ +/* + * This header provides constants for binding nvidia,tegra30-car. + * + * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + * registers. These IDs often match those in the CAR's RST_DEVICES registers, + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + * this case, those clocks are assigned IDs above 160 in order to highlight + * this issue. Implementations that interpret these clock IDs as bit values + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + * explicitly handle these special cases. + * + * The balance of the clocks controlled by the CAR are assigned IDs of 160 and + * above. + */ + +#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H +#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H + +#define TEGRA30_CLK_CPU 0 +/* 1 */ +/* 2 */ +/* 3 */ +#define TEGRA30_CLK_RTC 4 +#define TEGRA30_CLK_TIMER 5 +#define TEGRA30_CLK_UARTA 6 +/* 7 (register bit affects uartb and vfir) */ +#define TEGRA30_CLK_GPIO 8 +#define TEGRA30_CLK_SDMMC2 9 +/* 10 (register bit affects spdif_in and spdif_out) */ +#define TEGRA30_CLK_I2S1 11 +#define TEGRA30_CLK_I2C1 12 +#define TEGRA30_CLK_NDFLASH 13 +#define TEGRA30_CLK_SDMMC1 14 +#define TEGRA30_CLK_SDMMC4 15 +/* 16 */ +#define TEGRA30_CLK_PWM 17 +#define TEGRA30_CLK_I2S2 18 +#define TEGRA30_CLK_EPP 19 +/* 20 (register bit affects vi and vi_sensor) */ +#define TEGRA30_CLK_GR2D 21 +#define TEGRA30_CLK_USBD 22 +#define TEGRA30_CLK_ISP 23 +#define TEGRA30_CLK_GR3D 24 +/* 25 */ +#define TEGRA30_CLK_DISP2 26 +#define TEGRA30_CLK_DISP1 27 +#define TEGRA30_CLK_HOST1X 28 +#define TEGRA30_CLK_VCP 29 +#define TEGRA30_CLK_I2S0 30 +#define TEGRA30_CLK_COP_CACHE 31 + +#define TEGRA30_CLK_MC 32 +#define TEGRA30_CLK_AHBDMA 33 +#define TEGRA30_CLK_APBDMA 34 +/* 35 */ +#define TEGRA30_CLK_KBC 36 +#define TEGRA30_CLK_STATMON 37 +#define TEGRA30_CLK_PMC 38 +/* 39 (register bit affects fuse and fuse_burn) */ +#define TEGRA30_CLK_KFUSE 40 +#define TEGRA30_CLK_SBC1 41 +#define TEGRA30_CLK_NOR 42 +/* 43 */ +#define TEGRA30_CLK_SBC2 44 +/* 45 */ +#define TEGRA30_CLK_SBC3 46 +#define TEGRA30_CLK_I2C5 47 +#define TEGRA30_CLK_DSIA 48 +/* 49 (register bit affects cve and tvo) */ +#define TEGRA30_CLK_MIPI 50 +#define TEGRA30_CLK_HDMI 51 +#define TEGRA30_CLK_CSI 52 +#define TEGRA30_CLK_TVDAC 53 +#define TEGRA30_CLK_I2C2 54 +#define TEGRA30_CLK_UARTC 55 +/* 56 */ +#define TEGRA30_CLK_EMC 57 +#define TEGRA30_CLK_USB2 58 +#define TEGRA30_CLK_USB3 59 +#define TEGRA30_CLK_MPE 60 +#define TEGRA30_CLK_VDE 61 +#define TEGRA30_CLK_BSEA 62 +#define TEGRA30_CLK_BSEV 63 + +#define TEGRA30_CLK_SPEEDO 64 +#define TEGRA30_CLK_UARTD 65 +#define TEGRA30_CLK_UARTE 66 +#define TEGRA30_CLK_I2C3 67 +#define TEGRA30_CLK_SBC4 68 +#define TEGRA30_CLK_SDMMC3 69 +#define TEGRA30_CLK_PCIE 70 +#define TEGRA30_CLK_OWR 71 +#define TEGRA30_CLK_AFI 72 +#define TEGRA30_CLK_CSITE 73 +/* 74 */ +#define TEGRA30_CLK_AVPUCQ 75 +#define TEGRA30_CLK_LA 76 +/* 77 */ +/* 78 */ +#define TEGRA30_CLK_DTV 79 +#define TEGRA30_CLK_NDSPEED 80 +#define TEGRA30_CLK_I2CSLOW 81 +#define TEGRA30_CLK_DSIB 82 +/* 83 */ +#define TEGRA30_CLK_IRAMA 84 +#define TEGRA30_CLK_IRAMB 85 +#define TEGRA30_CLK_IRAMC 86 +#define TEGRA30_CLK_IRAMD 87 +#define TEGRA30_CLK_CRAM2 88 +/* 89 */ +#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ +/* 91 */ +#define TEGRA30_CLK_CSUS 92 +#define TEGRA30_CLK_CDEV2 93 +#define TEGRA30_CLK_CDEV1 94 +/* 95 */ + +#define TEGRA30_CLK_CPU_G 96 +#define TEGRA30_CLK_CPU_LP 97 +#define TEGRA30_CLK_GR3D2 98 +#define TEGRA30_CLK_MSELECT 99 +#define TEGRA30_CLK_TSENSOR 100 +#define TEGRA30_CLK_I2S3 101 +#define TEGRA30_CLK_I2S4 102 +#define TEGRA30_CLK_I2C4 103 +#define TEGRA30_CLK_SBC5 104 +#define TEGRA30_CLK_SBC6 105 +#define TEGRA30_CLK_D_AUDIO 106 +#define TEGRA30_CLK_APBIF 107 +#define TEGRA30_CLK_DAM0 108 +#define TEGRA30_CLK_DAM1 109 +#define TEGRA30_CLK_DAM2 110 +#define TEGRA30_CLK_HDA2CODEC_2X 111 +#define TEGRA30_CLK_ATOMICS 112 +#define TEGRA30_CLK_AUDIO0_2X 113 +#define TEGRA30_CLK_AUDIO1_2X 114 +#define TEGRA30_CLK_AUDIO2_2X 115 +#define TEGRA30_CLK_AUDIO3_2X 116 +#define TEGRA30_CLK_AUDIO4_2X 117 +#define TEGRA30_CLK_SPDIF_2X 118 +#define TEGRA30_CLK_ACTMON 119 +#define TEGRA30_CLK_EXTERN1 120 +#define TEGRA30_CLK_EXTERN2 121 +#define TEGRA30_CLK_EXTERN3 122 +#define TEGRA30_CLK_SATA_OOB 123 +#define TEGRA30_CLK_SATA 124 +#define TEGRA30_CLK_HDA 125 +/* 126 */ +#define TEGRA30_CLK_SE 127 + +#define TEGRA30_CLK_HDA2HDMI 128 +#define TEGRA30_CLK_SATA_COLD 129 +/* 130 */ +/* 131 */ +/* 132 */ +/* 133 */ +/* 134 */ +/* 135 */ +/* 136 */ +/* 137 */ +/* 138 */ +/* 139 */ +/* 140 */ +/* 141 */ +/* 142 */ +/* 143 */ +/* 144 */ +/* 145 */ +/* 146 */ +/* 147 */ +/* 148 */ +/* 149 */ +/* 150 */ +/* 151 */ +/* 152 */ +/* 153 */ +/* 154 */ +/* 155 */ +/* 156 */ +/* 157 */ +/* 158 */ +/* 159 */ + +#define TEGRA30_CLK_UARTB 160 +#define TEGRA30_CLK_VFIR 161 +#define TEGRA30_CLK_SPDIF_IN 162 +#define TEGRA30_CLK_SPDIF_OUT 163 +#define TEGRA30_CLK_VI 164 +#define TEGRA30_CLK_VI_SENSOR 165 +#define TEGRA30_CLK_FUSE 166 +#define TEGRA30_CLK_FUSE_BURN 167 +#define TEGRA30_CLK_CVE 168 +#define TEGRA30_CLK_TVO 169 +#define TEGRA30_CLK_CLK_32K 170 +#define TEGRA30_CLK_CLK_M 171 +#define TEGRA30_CLK_CLK_M_DIV2 172 +#define TEGRA30_CLK_CLK_M_DIV4 173 +#define TEGRA30_CLK_PLL_REF 174 +#define TEGRA30_CLK_PLL_C 175 +#define TEGRA30_CLK_PLL_C_OUT1 176 +#define TEGRA30_CLK_PLL_M 177 +#define TEGRA30_CLK_PLL_M_OUT1 178 +#define TEGRA30_CLK_PLL_P 179 +#define TEGRA30_CLK_PLL_P_OUT1 180 +#define TEGRA30_CLK_PLL_P_OUT2 181 +#define TEGRA30_CLK_PLL_P_OUT3 182 +#define TEGRA30_CLK_PLL_P_OUT4 183 +#define TEGRA30_CLK_PLL_A 184 +#define TEGRA30_CLK_PLL_A_OUT0 185 +#define TEGRA30_CLK_PLL_D 186 +#define TEGRA30_CLK_PLL_D_OUT0 187 +#define TEGRA30_CLK_PLL_D2 188 +#define TEGRA30_CLK_PLL_D2_OUT0 189 +#define TEGRA30_CLK_PLL_U 190 +#define TEGRA30_CLK_PLL_X 191 + +#define TEGRA30_CLK_PLL_X_OUT0 192 +#define TEGRA30_CLK_PLL_E 193 +#define TEGRA30_CLK_SPDIF_IN_SYNC 194 +#define TEGRA30_CLK_I2S0_SYNC 195 +#define TEGRA30_CLK_I2S1_SYNC 196 +#define TEGRA30_CLK_I2S2_SYNC 197 +#define TEGRA30_CLK_I2S3_SYNC 198 +#define TEGRA30_CLK_I2S4_SYNC 199 +#define TEGRA30_CLK_VIMCLK_SYNC 200 +#define TEGRA30_CLK_AUDIO0 201 +#define TEGRA30_CLK_AUDIO1 202 +#define TEGRA30_CLK_AUDIO2 203 +#define TEGRA30_CLK_AUDIO3 204 +#define TEGRA30_CLK_AUDIO4 205 +#define TEGRA30_CLK_SPDIF 206 +#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ +#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ +#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ +#define TEGRA30_CLK_SCLK 210 +#define TEGRA30_CLK_BLINK 211 +#define TEGRA30_CLK_CCLK_G 212 +#define TEGRA30_CLK_CCLK_LP 213 +#define TEGRA30_CLK_TWD 214 +#define TEGRA30_CLK_CML0 215 +#define TEGRA30_CLK_CML1 216 +#define TEGRA30_CLK_HCLK 217 +#define TEGRA30_CLK_PCLK 218 +/* 219 */ +/* 220 */ +/* 221 */ +/* 222 */ +/* 223 */ + +/* 288 */ +/* 289 */ +/* 290 */ +/* 291 */ +/* 292 */ +/* 293 */ +/* 294 */ +/* 295 */ +/* 296 */ +/* 297 */ +/* 298 */ +/* 299 */ +#define TEGRA30_CLK_CLK_OUT_1_MUX 300 +#define TEGRA30_CLK_CLK_OUT_2_MUX 301 +#define TEGRA30_CLK_CLK_OUT_3_MUX 302 +#define TEGRA30_CLK_AUDIO0_MUX 303 +#define TEGRA30_CLK_AUDIO1_MUX 304 +#define TEGRA30_CLK_AUDIO2_MUX 305 +#define TEGRA30_CLK_AUDIO3_MUX 306 +#define TEGRA30_CLK_AUDIO4_MUX 307 +#define TEGRA30_CLK_SPDIF_MUX 308 +#define TEGRA30_CLK_CLK_MAX 309 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ diff --git a/roms/u-boot/include/dt-bindings/clock/xlnx-versal-clk.h b/roms/u-boot/include/dt-bindings/clock/xlnx-versal-clk.h new file mode 100644 index 000000000..264d634d2 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/xlnx-versal-clk.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Xilinx Inc. + * + */ + +#ifndef _DT_BINDINGS_CLK_VERSAL_H +#define _DT_BINDINGS_CLK_VERSAL_H + +#define PMC_PLL 1 +#define APU_PLL 2 +#define RPU_PLL 3 +#define CPM_PLL 4 +#define NOC_PLL 5 +#define PLL_MAX 6 +#define PMC_PRESRC 7 +#define PMC_POSTCLK 8 +#define PMC_PLL_OUT 9 +#define PPLL 10 +#define NOC_PRESRC 11 +#define NOC_POSTCLK 12 +#define NOC_PLL_OUT 13 +#define NPLL 14 +#define APU_PRESRC 15 +#define APU_POSTCLK 16 +#define APU_PLL_OUT 17 +#define APLL 18 +#define RPU_PRESRC 19 +#define RPU_POSTCLK 20 +#define RPU_PLL_OUT 21 +#define RPLL 22 +#define CPM_PRESRC 23 +#define CPM_POSTCLK 24 +#define CPM_PLL_OUT 25 +#define CPLL 26 +#define PPLL_TO_XPD 27 +#define NPLL_TO_XPD 28 +#define APLL_TO_XPD 29 +#define RPLL_TO_XPD 30 +#define EFUSE_REF 31 +#define SYSMON_REF 32 +#define IRO_SUSPEND_REF 33 +#define USB_SUSPEND 34 +#define SWITCH_TIMEOUT 35 +#define RCLK_PMC 36 +#define RCLK_LPD 37 +#define WDT 38 +#define TTC0 39 +#define TTC1 40 +#define TTC2 41 +#define TTC3 42 +#define GEM_TSU 43 +#define GEM_TSU_LB 44 +#define MUXED_IRO_DIV2 45 +#define MUXED_IRO_DIV4 46 +#define PSM_REF 47 +#define GEM0_RX 48 +#define GEM0_TX 49 +#define GEM1_RX 50 +#define GEM1_TX 51 +#define CPM_CORE_REF 52 +#define CPM_LSBUS_REF 53 +#define CPM_DBG_REF 54 +#define CPM_AUX0_REF 55 +#define CPM_AUX1_REF 56 +#define QSPI_REF 57 +#define OSPI_REF 58 +#define SDIO0_REF 59 +#define SDIO1_REF 60 +#define PMC_LSBUS_REF 61 +#define I2C_REF 62 +#define TEST_PATTERN_REF 63 +#define DFT_OSC_REF 64 +#define PMC_PL0_REF 65 +#define PMC_PL1_REF 66 +#define PMC_PL2_REF 67 +#define PMC_PL3_REF 68 +#define CFU_REF 69 +#define SPARE_REF 70 +#define NPI_REF 71 +#define HSM0_REF 72 +#define HSM1_REF 73 +#define SD_DLL_REF 74 +#define FPD_TOP_SWITCH 75 +#define FPD_LSBUS 76 +#define ACPU 77 +#define DBG_TRACE 78 +#define DBG_FPD 79 +#define LPD_TOP_SWITCH 80 +#define ADMA 81 +#define LPD_LSBUS 82 +#define CPU_R5 83 +#define CPU_R5_CORE 84 +#define CPU_R5_OCM 85 +#define CPU_R5_OCM2 86 +#define IOU_SWITCH 87 +#define GEM0_REF 88 +#define GEM1_REF 89 +#define GEM_TSU_REF 90 +#define USB0_BUS_REF 91 +#define UART0_REF 92 +#define UART1_REF 93 +#define SPI0_REF 94 +#define SPI1_REF 95 +#define CAN0_REF 96 +#define CAN1_REF 97 +#define I2C0_REF 98 +#define I2C1_REF 99 +#define DBG_LPD 100 +#define TIMESTAMP_REF 101 +#define DBG_TSTMP 102 +#define CPM_TOPSW_REF 103 +#define USB3_DUAL_REF 104 +#define OUTCLK_MAX 105 +#define REF_CLK 106 +#define PL_ALT_REF_CLK 107 +#define MUXED_IRO 108 +#define PL_EXT 109 +#define PL_LB 110 +#define MIO_50_OR_51 111 +#define MIO_24_OR_25 112 + +#endif diff --git a/roms/u-boot/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/roms/u-boot/include/dt-bindings/clock/xlnx-zynqmp-clk.h new file mode 100644 index 000000000..cdc4c0b9a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Xilinx Zynq MPSoC Firmware layer + * + * Copyright (C) 2014-2018 Xilinx, Inc. + * + */ + +#ifndef _DT_BINDINGS_CLK_ZYNQMP_H +#define _DT_BINDINGS_CLK_ZYNQMP_H + +#define IOPLL 0 +#define RPLL 1 +#define APLL 2 +#define DPLL 3 +#define VPLL 4 +#define IOPLL_TO_FPD 5 +#define RPLL_TO_FPD 6 +#define APLL_TO_LPD 7 +#define DPLL_TO_LPD 8 +#define VPLL_TO_LPD 9 +#define ACPU 10 +#define ACPU_HALF 11 +#define DBF_FPD 12 +#define DBF_LPD 13 +#define DBG_TRACE 14 +#define DBG_TSTMP 15 +#define DP_VIDEO_REF 16 +#define DP_AUDIO_REF 17 +#define DP_STC_REF 18 +#define GDMA_REF 19 +#define DPDMA_REF 20 +#define DDR_REF 21 +#define SATA_REF 22 +#define PCIE_REF 23 +#define GPU_REF 24 +#define GPU_PP0_REF 25 +#define GPU_PP1_REF 26 +#define TOPSW_MAIN 27 +#define TOPSW_LSBUS 28 +#define GTGREF0_REF 29 +#define LPD_SWITCH 30 +#define LPD_LSBUS 31 +#define USB0_BUS_REF 32 +#define USB1_BUS_REF 33 +#define USB3_DUAL_REF 34 +#define USB0 35 +#define USB1 36 +#define CPU_R5 37 +#define CPU_R5_CORE 38 +#define CSU_SPB 39 +#define CSU_PLL 40 +#define PCAP 41 +#define IOU_SWITCH 42 +#define GEM_TSU_REF 43 +#define GEM_TSU 44 +#define GEM0_TX 45 +#define GEM1_TX 46 +#define GEM2_TX 47 +#define GEM3_TX 48 +#define GEM0_RX 49 +#define GEM1_RX 50 +#define GEM2_RX 51 +#define GEM3_RX 52 +#define QSPI_REF 53 +#define SDIO0_REF 54 +#define SDIO1_REF 55 +#define UART0_REF 56 +#define UART1_REF 57 +#define SPI0_REF 58 +#define SPI1_REF 59 +#define NAND_REF 60 +#define I2C0_REF 61 +#define I2C1_REF 62 +#define CAN0_REF 63 +#define CAN1_REF 64 +#define CAN0 65 +#define CAN1 66 +#define DLL_REF 67 +#define ADMA_REF 68 +#define TIMESTAMP_REF 69 +#define AMS_REF 70 +#define PL0_REF 71 +#define PL1_REF 72 +#define PL2_REF 73 +#define PL3_REF 74 +#define WDT 75 +#define IOPLL_INT 76 +#define IOPLL_PRE_SRC 77 +#define IOPLL_HALF 78 +#define IOPLL_INT_MUX 79 +#define IOPLL_POST_SRC 80 +#define RPLL_INT 81 +#define RPLL_PRE_SRC 82 +#define RPLL_HALF 83 +#define RPLL_INT_MUX 84 +#define RPLL_POST_SRC 85 +#define APLL_INT 86 +#define APLL_PRE_SRC 87 +#define APLL_HALF 88 +#define APLL_INT_MUX 89 +#define APLL_POST_SRC 90 +#define DPLL_INT 91 +#define DPLL_PRE_SRC 92 +#define DPLL_HALF 93 +#define DPLL_INT_MUX 94 +#define DPLL_POST_SRC 95 +#define VPLL_INT 96 +#define VPLL_PRE_SRC 97 +#define VPLL_HALF 98 +#define VPLL_INT_MUX 99 +#define VPLL_POST_SRC 100 +#define CAN0_MIO 101 +#define CAN1_MIO 102 +#define ACPU_FULL 103 +#define GEM0_REF 104 +#define GEM1_REF 105 +#define GEM2_REF 106 +#define GEM3_REF 107 +#define GEM0_REF_UNG 108 +#define GEM1_REF_UNG 109 +#define GEM2_REF_UNG 110 +#define GEM3_REF_UNG 111 +#define LPD_WDT 112 + +#endif diff --git a/roms/u-boot/include/dt-bindings/comphy/comphy_data.h b/roms/u-boot/include/dt-bindings/comphy/comphy_data.h new file mode 100644 index 000000000..8353a7874 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/comphy/comphy_data.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015-2016 Marvell International Ltd. + */ + +#ifndef _COMPHY_DATA_H_ +#define _COMPHY_DATA_H_ + +#define COMPHY_SPEED_1_25G 0 +#define COMPHY_SPEED_2_5G 1 +#define COMPHY_SPEED_3_125G 2 +#define COMPHY_SPEED_5G 3 +#define COMPHY_SPEED_5_15625G 4 +#define COMPHY_SPEED_6G 5 +#define COMPHY_SPEED_10_3125G 6 +#define COMPHY_SPEED_MAX 7 +#define COMPHY_SPEED_INVALID 0xff + +#define COMPHY_TYPE_UNCONNECTED 0 +#define COMPHY_TYPE_PEX0 1 +#define COMPHY_TYPE_PEX1 2 +#define COMPHY_TYPE_PEX2 3 +#define COMPHY_TYPE_PEX3 4 +#define COMPHY_TYPE_SATA0 5 +#define COMPHY_TYPE_SATA1 6 +#define COMPHY_TYPE_SGMII0 7 +#define COMPHY_TYPE_SGMII1 8 +#define COMPHY_TYPE_SGMII2 9 +#define COMPHY_TYPE_USB3 10 +#define COMPHY_TYPE_USB3_HOST0 11 +#define COMPHY_TYPE_USB3_HOST1 12 +#define COMPHY_TYPE_USB3_DEVICE 13 +#define COMPHY_TYPE_RXAUI0 14 +#define COMPHY_TYPE_RXAUI1 15 +#define COMPHY_TYPE_SFI0 16 +#define COMPHY_TYPE_SFI1 17 +#define COMPHY_TYPE_AP 18 +#define COMPHY_TYPE_IGNORE 19 +#define COMPHY_TYPE_MAX 20 +#define COMPHY_TYPE_INVALID 0xff + +#define COMPHY_POLARITY_NO_INVERT 0 +#define COMPHY_POLARITY_TXD_INVERT 1 +#define COMPHY_POLARITY_RXD_INVERT 2 +#define COMPHY_POLARITY_ALL_INVERT \ + (COMPHY_POLARITY_TXD_INVERT | COMPHY_POLARITY_RXD_INVERT) + +#define UTMI_PHY_TO_USB3_HOST0 0 +#define UTMI_PHY_TO_USB3_HOST1 1 +#define UTMI_PHY_TO_USB3_DEVICE0 2 +#define UTMI_PHY_INVALID 0xff + +#endif /* _COMPHY_DATA_H_ */ + diff --git a/roms/u-boot/include/dt-bindings/display/tda998x.h b/roms/u-boot/include/dt-bindings/display/tda998x.h new file mode 100644 index 000000000..746831ff3 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/display/tda998x.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_TDA998X_H +#define _DT_BINDINGS_TDA998X_H + +#define TDA998x_SPDIF 1 +#define TDA998x_I2S 2 + +#endif /*_DT_BINDINGS_TDA998X_H */ diff --git a/roms/u-boot/include/dt-bindings/dma/at91.h b/roms/u-boot/include/dt-bindings/dma/at91.h new file mode 100644 index 000000000..ab6cbba45 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/dma/at91.h @@ -0,0 +1,52 @@ +/* + * This header provides macros for at91 dma bindings. + * + * Copyright (C) 2013 Ludovic Desroches + * + * GPLv2 only + */ + +#ifndef __DT_BINDINGS_AT91_DMA_H__ +#define __DT_BINDINGS_AT91_DMA_H__ + +/* ---------- HDMAC ---------- */ + +/* + * Source and/or destination peripheral ID + */ +#define AT91_DMA_CFG_PER_ID_MASK (0xff) +#define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK) + +/* + * FIFO configuration: it defines when a request is serviced. + */ +#define AT91_DMA_CFG_FIFOCFG_OFFSET (8) +#define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET) +#define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */ +#define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ +#define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ + + +/* ---------- XDMAC ---------- */ +#define AT91_XDMAC_DT_MEM_IF_MASK (0x1) +#define AT91_XDMAC_DT_MEM_IF_OFFSET (13) +#define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \ + << AT91_XDMAC_DT_MEM_IF_OFFSET) +#define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \ + & AT91_XDMAC_DT_MEM_IF_MASK) + +#define AT91_XDMAC_DT_PER_IF_MASK (0x1) +#define AT91_XDMAC_DT_PER_IF_OFFSET (14) +#define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \ + << AT91_XDMAC_DT_PER_IF_OFFSET) +#define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \ + & AT91_XDMAC_DT_PER_IF_MASK) + +#define AT91_XDMAC_DT_PERID_MASK (0x7f) +#define AT91_XDMAC_DT_PERID_OFFSET (24) +#define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \ + << AT91_XDMAC_DT_PERID_OFFSET) +#define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ + & AT91_XDMAC_DT_PERID_MASK) + +#endif /* __DT_BINDINGS_AT91_DMA_H__ */ diff --git a/roms/u-boot/include/dt-bindings/dma/bcm6318-dma.h b/roms/u-boot/include/dt-bindings/dma/bcm6318-dma.h new file mode 100644 index 000000000..ad7c5ac2d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/dma/bcm6318-dma.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + */ + +#ifndef __DT_BINDINGS_DMA_BCM6318_H +#define __DT_BINDINGS_DMA_BCM6318_H + +#define BCM6318_DMA_ENETSW_RX 0 +#define BCM6318_DMA_ENETSW_TX 1 + +#endif /* __DT_BINDINGS_DMA_BCM6318_H */ diff --git a/roms/u-boot/include/dt-bindings/dma/bcm63268-dma.h b/roms/u-boot/include/dt-bindings/dma/bcm63268-dma.h new file mode 100644 index 000000000..7d027119e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/dma/bcm63268-dma.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + */ + +#ifndef __DT_BINDINGS_DMA_BCM63268_H +#define __DT_BINDINGS_DMA_BCM63268_H + +#define BCM63268_DMA_ENETSW_RX 0 +#define BCM63268_DMA_ENETSW_TX 1 + +#endif /* __DT_BINDINGS_DMA_BCM63268_H */ diff --git a/roms/u-boot/include/dt-bindings/dma/bcm6328-dma.h b/roms/u-boot/include/dt-bindings/dma/bcm6328-dma.h new file mode 100644 index 000000000..7494df2fe --- /dev/null +++ b/roms/u-boot/include/dt-bindings/dma/bcm6328-dma.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + */ + +#ifndef __DT_BINDINGS_DMA_BCM6328_H +#define __DT_BINDINGS_DMA_BCM6328_H + +#define BCM6328_DMA_ENETSW_RX 0 +#define BCM6328_DMA_ENETSW_TX 1 + +#endif /* __DT_BINDINGS_DMA_BCM6328_H */ diff --git a/roms/u-boot/include/dt-bindings/dma/bcm6338-dma.h b/roms/u-boot/include/dt-bindings/dma/bcm6338-dma.h new file mode 100644 index 000000000..f2e0b2044 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/dma/bcm6338-dma.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + */ + +#ifndef __DT_BINDINGS_DMA_BCM6338_H +#define __DT_BINDINGS_DMA_BCM6338_H + +#define BCM6338_DMA_ENET_RX 0 +#define BCM6338_DMA_ENET_TX 1 + +#endif /* __DT_BINDINGS_DMA_BCM6338_H */ diff --git a/roms/u-boot/include/dt-bindings/dma/bcm6348-dma.h b/roms/u-boot/include/dt-bindings/dma/bcm6348-dma.h new file mode 100644 index 000000000..36c2ffd41 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/dma/bcm6348-dma.h @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + */ + +#ifndef __DT_BINDINGS_DMA_BCM6348_H +#define __DT_BINDINGS_DMA_BCM6348_H + +#define BCM6348_DMA_ENET0_RX 0 +#define BCM6348_DMA_ENET0_TX 1 +#define BCM6348_DMA_ENET1_RX 2 +#define BCM6348_DMA_ENET1_TX 3 + +#endif /* __DT_BINDINGS_DMA_BCM6348_H */ diff --git a/roms/u-boot/include/dt-bindings/dma/bcm6358-dma.h b/roms/u-boot/include/dt-bindings/dma/bcm6358-dma.h new file mode 100644 index 000000000..3118b9da0 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/dma/bcm6358-dma.h @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + */ + +#ifndef __DT_BINDINGS_DMA_BCM6358_H +#define __DT_BINDINGS_DMA_BCM6358_H + +#define BCM6358_DMA_ENET0_RX 0 +#define BCM6358_DMA_ENET0_TX 1 +#define BCM6358_DMA_ENET1_RX 2 +#define BCM6358_DMA_ENET1_TX 3 + +#endif /* __DT_BINDINGS_DMA_BCM6358_H */ diff --git a/roms/u-boot/include/dt-bindings/dma/bcm6362-dma.h b/roms/u-boot/include/dt-bindings/dma/bcm6362-dma.h new file mode 100644 index 000000000..1e62236da --- /dev/null +++ b/roms/u-boot/include/dt-bindings/dma/bcm6362-dma.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + */ + +#ifndef __DT_BINDINGS_DMA_BCM6362_H +#define __DT_BINDINGS_DMA_BCM6362_H + +#define BCM6362_DMA_ENETSW_RX 0 +#define BCM6362_DMA_ENETSW_TX 1 + +#endif /* __DT_BINDINGS_DMA_BCM6362_H */ diff --git a/roms/u-boot/include/dt-bindings/dma/bcm6368-dma.h b/roms/u-boot/include/dt-bindings/dma/bcm6368-dma.h new file mode 100644 index 000000000..36c6caa0e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/dma/bcm6368-dma.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + */ + +#ifndef __DT_BINDINGS_DMA_BCM6368_H +#define __DT_BINDINGS_DMA_BCM6368_H + +#define BCM6368_DMA_ENETSW_RX 0 +#define BCM6368_DMA_ENETSW_TX 1 + +#endif /* __DT_BINDINGS_DMA_BCM6368_H */ diff --git a/roms/u-boot/include/dt-bindings/dma/sun4i-a10.h b/roms/u-boot/include/dt-bindings/dma/sun4i-a10.h new file mode 100644 index 000000000..8caba9ef7 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/dma/sun4i-a10.h @@ -0,0 +1,56 @@ +/* + * Copyright 2014 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __DT_BINDINGS_DMA_SUN4I_A10_H_ +#define __DT_BINDINGS_DMA_SUN4I_A10_H_ + +#define SUN4I_DMA_NORMAL 0 +#define SUN4I_DMA_DEDICATED 1 + +#endif /* __DT_BINDINGS_DMA_SUN4I_A10_H_ */ diff --git a/roms/u-boot/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h b/roms/u-boot/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h new file mode 100644 index 000000000..3719cda56 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright 2019 Laurent Pinchart + */ + +#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ +#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ + +#define ZYNQMP_DPDMA_VIDEO0 0 +#define ZYNQMP_DPDMA_VIDEO1 1 +#define ZYNQMP_DPDMA_VIDEO2 2 +#define ZYNQMP_DPDMA_GRAPHICS 3 +#define ZYNQMP_DPDMA_AUDIO0 4 +#define ZYNQMP_DPDMA_AUDIO1 5 + +#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ diff --git a/roms/u-boot/include/dt-bindings/gpio/gpio.h b/roms/u-boot/include/dt-bindings/gpio/gpio.h new file mode 100644 index 000000000..c029467e8 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/gpio/gpio.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for most GPIO bindings. + * + * Most GPIO bindings include a flags cell as part of the GPIO specifier. + * In most cases, the format of the flags cell uses the standard values + * defined in this header. + */ + +#ifndef _DT_BINDINGS_GPIO_GPIO_H +#define _DT_BINDINGS_GPIO_GPIO_H + +/* Bit 0 express polarity */ +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/* Bit 1 express single-endedness */ +#define GPIO_PUSH_PULL 0 +#define GPIO_SINGLE_ENDED 2 + +/* Bit 2 express Open drain or open source */ +#define GPIO_LINE_OPEN_SOURCE 0 +#define GPIO_LINE_OPEN_DRAIN 4 + +/* + * Open Drain/Collector is the combination of single-ended open drain interface. + * Open Source/Emitter is the combination of single-ended open source interface. + */ +#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) +#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) + +/* Bit 3 express GPIO suspend/resume and reset persistence */ +#define GPIO_PERSISTENT 0 +#define GPIO_TRANSITORY 8 + +/* Bit 4 express pull up */ +#define GPIO_PULL_UP 16 + +/* Bit 5 express pull down */ +#define GPIO_PULL_DOWN 32 + +#endif diff --git a/roms/u-boot/include/dt-bindings/gpio/meson-axg-gpio.h b/roms/u-boot/include/dt-bindings/gpio/meson-axg-gpio.h new file mode 100644 index 000000000..25bb1fffa --- /dev/null +++ b/roms/u-boot/include/dt-bindings/gpio/meson-axg-gpio.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H +#define _DT_BINDINGS_MESON_AXG_GPIO_H + +/* First GPIO chip */ +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIOAO_10 10 +#define GPIOAO_11 11 +#define GPIOAO_12 12 +#define GPIOAO_13 13 +#define GPIO_TEST_N 14 + +/* Second GPIO chip */ +#define GPIOZ_0 0 +#define GPIOZ_1 1 +#define GPIOZ_2 2 +#define GPIOZ_3 3 +#define GPIOZ_4 4 +#define GPIOZ_5 5 +#define GPIOZ_6 6 +#define GPIOZ_7 7 +#define GPIOZ_8 8 +#define GPIOZ_9 9 +#define GPIOZ_10 10 +#define BOOT_0 11 +#define BOOT_1 12 +#define BOOT_2 13 +#define BOOT_3 14 +#define BOOT_4 15 +#define BOOT_5 16 +#define BOOT_6 17 +#define BOOT_7 18 +#define BOOT_8 19 +#define BOOT_9 20 +#define BOOT_10 21 +#define BOOT_11 22 +#define BOOT_12 23 +#define BOOT_13 24 +#define BOOT_14 25 +#define GPIOA_0 26 +#define GPIOA_1 27 +#define GPIOA_2 28 +#define GPIOA_3 29 +#define GPIOA_4 30 +#define GPIOA_5 31 +#define GPIOA_6 32 +#define GPIOA_7 33 +#define GPIOA_8 34 +#define GPIOA_9 35 +#define GPIOA_10 36 +#define GPIOA_11 37 +#define GPIOA_12 38 +#define GPIOA_13 39 +#define GPIOA_14 40 +#define GPIOA_15 41 +#define GPIOA_16 42 +#define GPIOA_17 43 +#define GPIOA_18 44 +#define GPIOA_19 45 +#define GPIOA_20 46 +#define GPIOX_0 47 +#define GPIOX_1 48 +#define GPIOX_2 49 +#define GPIOX_3 50 +#define GPIOX_4 51 +#define GPIOX_5 52 +#define GPIOX_6 53 +#define GPIOX_7 54 +#define GPIOX_8 55 +#define GPIOX_9 56 +#define GPIOX_10 57 +#define GPIOX_11 58 +#define GPIOX_12 59 +#define GPIOX_13 60 +#define GPIOX_14 61 +#define GPIOX_15 62 +#define GPIOX_16 63 +#define GPIOX_17 64 +#define GPIOX_18 65 +#define GPIOX_19 66 +#define GPIOX_20 67 +#define GPIOX_21 68 +#define GPIOX_22 69 +#define GPIOY_0 70 +#define GPIOY_1 71 +#define GPIOY_2 72 +#define GPIOY_3 73 +#define GPIOY_4 74 +#define GPIOY_5 75 +#define GPIOY_6 76 +#define GPIOY_7 77 +#define GPIOY_8 78 +#define GPIOY_9 79 +#define GPIOY_10 80 +#define GPIOY_11 81 +#define GPIOY_12 82 +#define GPIOY_13 83 +#define GPIOY_14 84 +#define GPIOY_15 85 + +#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */ diff --git a/roms/u-boot/include/dt-bindings/gpio/meson-g12a-gpio.h b/roms/u-boot/include/dt-bindings/gpio/meson-g12a-gpio.h new file mode 100644 index 000000000..f7bd69350 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/gpio/meson-g12a-gpio.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen + */ + +#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H +#define _DT_BINDINGS_MESON_G12A_GPIO_H + +/* First GPIO chip */ +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIOAO_10 10 +#define GPIOAO_11 11 +#define GPIOE_0 12 +#define GPIOE_1 13 +#define GPIOE_2 14 + +/* Second GPIO chip */ +#define GPIOZ_0 0 +#define GPIOZ_1 1 +#define GPIOZ_2 2 +#define GPIOZ_3 3 +#define GPIOZ_4 4 +#define GPIOZ_5 5 +#define GPIOZ_6 6 +#define GPIOZ_7 7 +#define GPIOZ_8 8 +#define GPIOZ_9 9 +#define GPIOZ_10 10 +#define GPIOZ_11 11 +#define GPIOZ_12 12 +#define GPIOZ_13 13 +#define GPIOZ_14 14 +#define GPIOZ_15 15 +#define GPIOH_0 16 +#define GPIOH_1 17 +#define GPIOH_2 18 +#define GPIOH_3 19 +#define GPIOH_4 20 +#define GPIOH_5 21 +#define GPIOH_6 22 +#define GPIOH_7 23 +#define GPIOH_8 24 +#define BOOT_0 25 +#define BOOT_1 26 +#define BOOT_2 27 +#define BOOT_3 28 +#define BOOT_4 29 +#define BOOT_5 30 +#define BOOT_6 31 +#define BOOT_7 32 +#define BOOT_8 33 +#define BOOT_9 34 +#define BOOT_10 35 +#define BOOT_11 36 +#define BOOT_12 37 +#define BOOT_13 38 +#define BOOT_14 39 +#define BOOT_15 40 +#define GPIOC_0 41 +#define GPIOC_1 42 +#define GPIOC_2 43 +#define GPIOC_3 44 +#define GPIOC_4 45 +#define GPIOC_5 46 +#define GPIOC_6 47 +#define GPIOC_7 48 +#define GPIOA_0 49 +#define GPIOA_1 50 +#define GPIOA_2 51 +#define GPIOA_3 52 +#define GPIOA_4 53 +#define GPIOA_5 54 +#define GPIOA_6 55 +#define GPIOA_7 56 +#define GPIOA_8 57 +#define GPIOA_9 58 +#define GPIOA_10 59 +#define GPIOA_11 60 +#define GPIOA_12 61 +#define GPIOA_13 62 +#define GPIOA_14 63 +#define GPIOA_15 64 +#define GPIOX_0 65 +#define GPIOX_1 66 +#define GPIOX_2 67 +#define GPIOX_3 68 +#define GPIOX_4 69 +#define GPIOX_5 70 +#define GPIOX_6 71 +#define GPIOX_7 72 +#define GPIOX_8 73 +#define GPIOX_9 74 +#define GPIOX_10 75 +#define GPIOX_11 76 +#define GPIOX_12 77 +#define GPIOX_13 78 +#define GPIOX_14 79 +#define GPIOX_15 80 +#define GPIOX_16 81 +#define GPIOX_17 82 +#define GPIOX_18 83 +#define GPIOX_19 84 + +#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */ diff --git a/roms/u-boot/include/dt-bindings/gpio/meson-gxbb-gpio.h b/roms/u-boot/include/dt-bindings/gpio/meson-gxbb-gpio.h new file mode 100644 index 000000000..489c75b27 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/gpio/meson-gxbb-gpio.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * GPIO definitions for Amlogic Meson GXBB SoCs + * + * Copyright (C) 2016 Endless Mobile, Inc. + * Author: Carlo Caione + */ + +#ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H +#define _DT_BINDINGS_MESON_GXBB_GPIO_H + +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIOAO_10 10 +#define GPIOAO_11 11 +#define GPIOAO_12 12 +#define GPIOAO_13 13 +#define GPIO_TEST_N 14 + +#define GPIOZ_0 0 +#define GPIOZ_1 1 +#define GPIOZ_2 2 +#define GPIOZ_3 3 +#define GPIOZ_4 4 +#define GPIOZ_5 5 +#define GPIOZ_6 6 +#define GPIOZ_7 7 +#define GPIOZ_8 8 +#define GPIOZ_9 9 +#define GPIOZ_10 10 +#define GPIOZ_11 11 +#define GPIOZ_12 12 +#define GPIOZ_13 13 +#define GPIOZ_14 14 +#define GPIOZ_15 15 +#define GPIOH_0 16 +#define GPIOH_1 17 +#define GPIOH_2 18 +#define GPIOH_3 19 +#define BOOT_0 20 +#define BOOT_1 21 +#define BOOT_2 22 +#define BOOT_3 23 +#define BOOT_4 24 +#define BOOT_5 25 +#define BOOT_6 26 +#define BOOT_7 27 +#define BOOT_8 28 +#define BOOT_9 29 +#define BOOT_10 30 +#define BOOT_11 31 +#define BOOT_12 32 +#define BOOT_13 33 +#define BOOT_14 34 +#define BOOT_15 35 +#define BOOT_16 36 +#define BOOT_17 37 +#define CARD_0 38 +#define CARD_1 39 +#define CARD_2 40 +#define CARD_3 41 +#define CARD_4 42 +#define CARD_5 43 +#define CARD_6 44 +#define GPIODV_0 45 +#define GPIODV_1 46 +#define GPIODV_2 47 +#define GPIODV_3 48 +#define GPIODV_4 49 +#define GPIODV_5 50 +#define GPIODV_6 51 +#define GPIODV_7 52 +#define GPIODV_8 53 +#define GPIODV_9 54 +#define GPIODV_10 55 +#define GPIODV_11 56 +#define GPIODV_12 57 +#define GPIODV_13 58 +#define GPIODV_14 59 +#define GPIODV_15 60 +#define GPIODV_16 61 +#define GPIODV_17 62 +#define GPIODV_18 63 +#define GPIODV_19 64 +#define GPIODV_20 65 +#define GPIODV_21 66 +#define GPIODV_22 67 +#define GPIODV_23 68 +#define GPIODV_24 69 +#define GPIODV_25 70 +#define GPIODV_26 71 +#define GPIODV_27 72 +#define GPIODV_28 73 +#define GPIODV_29 74 +#define GPIOY_0 75 +#define GPIOY_1 76 +#define GPIOY_2 77 +#define GPIOY_3 78 +#define GPIOY_4 79 +#define GPIOY_5 80 +#define GPIOY_6 81 +#define GPIOY_7 82 +#define GPIOY_8 83 +#define GPIOY_9 84 +#define GPIOY_10 85 +#define GPIOY_11 86 +#define GPIOY_12 87 +#define GPIOY_13 88 +#define GPIOY_14 89 +#define GPIOY_15 90 +#define GPIOY_16 91 +#define GPIOX_0 92 +#define GPIOX_1 93 +#define GPIOX_2 94 +#define GPIOX_3 95 +#define GPIOX_4 96 +#define GPIOX_5 97 +#define GPIOX_6 98 +#define GPIOX_7 99 +#define GPIOX_8 100 +#define GPIOX_9 101 +#define GPIOX_10 102 +#define GPIOX_11 103 +#define GPIOX_12 104 +#define GPIOX_13 105 +#define GPIOX_14 106 +#define GPIOX_15 107 +#define GPIOX_16 108 +#define GPIOX_17 109 +#define GPIOX_18 110 +#define GPIOX_19 111 +#define GPIOX_20 112 +#define GPIOX_21 113 +#define GPIOX_22 114 +#define GPIOCLK_0 115 +#define GPIOCLK_1 116 +#define GPIOCLK_2 117 +#define GPIOCLK_3 118 + +#endif diff --git a/roms/u-boot/include/dt-bindings/gpio/meson-gxl-gpio.h b/roms/u-boot/include/dt-bindings/gpio/meson-gxl-gpio.h new file mode 100644 index 000000000..0a001ae48 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/gpio/meson-gxl-gpio.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * GPIO definitions for Amlogic Meson GXL SoCs + * + * Copyright (C) 2016 Endless Mobile, Inc. + * Author: Carlo Caione + */ + +#ifndef _DT_BINDINGS_MESON_GXL_GPIO_H +#define _DT_BINDINGS_MESON_GXL_GPIO_H + +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIO_TEST_N 10 + +#define GPIOZ_0 0 +#define GPIOZ_1 1 +#define GPIOZ_2 2 +#define GPIOZ_3 3 +#define GPIOZ_4 4 +#define GPIOZ_5 5 +#define GPIOZ_6 6 +#define GPIOZ_7 7 +#define GPIOZ_8 8 +#define GPIOZ_9 9 +#define GPIOZ_10 10 +#define GPIOZ_11 11 +#define GPIOZ_12 12 +#define GPIOZ_13 13 +#define GPIOZ_14 14 +#define GPIOZ_15 15 +#define GPIOH_0 16 +#define GPIOH_1 17 +#define GPIOH_2 18 +#define GPIOH_3 19 +#define GPIOH_4 20 +#define GPIOH_5 21 +#define GPIOH_6 22 +#define GPIOH_7 23 +#define GPIOH_8 24 +#define GPIOH_9 25 +#define BOOT_0 26 +#define BOOT_1 27 +#define BOOT_2 28 +#define BOOT_3 29 +#define BOOT_4 30 +#define BOOT_5 31 +#define BOOT_6 32 +#define BOOT_7 33 +#define BOOT_8 34 +#define BOOT_9 35 +#define BOOT_10 36 +#define BOOT_11 37 +#define BOOT_12 38 +#define BOOT_13 39 +#define BOOT_14 40 +#define BOOT_15 41 +#define CARD_0 42 +#define CARD_1 43 +#define CARD_2 44 +#define CARD_3 45 +#define CARD_4 46 +#define CARD_5 47 +#define CARD_6 48 +#define GPIODV_0 49 +#define GPIODV_1 50 +#define GPIODV_2 51 +#define GPIODV_3 52 +#define GPIODV_4 53 +#define GPIODV_5 54 +#define GPIODV_6 55 +#define GPIODV_7 56 +#define GPIODV_8 57 +#define GPIODV_9 58 +#define GPIODV_10 59 +#define GPIODV_11 60 +#define GPIODV_12 61 +#define GPIODV_13 62 +#define GPIODV_14 63 +#define GPIODV_15 64 +#define GPIODV_16 65 +#define GPIODV_17 66 +#define GPIODV_18 67 +#define GPIODV_19 68 +#define GPIODV_20 69 +#define GPIODV_21 70 +#define GPIODV_22 71 +#define GPIODV_23 72 +#define GPIODV_24 73 +#define GPIODV_25 74 +#define GPIODV_26 75 +#define GPIODV_27 76 +#define GPIODV_28 77 +#define GPIODV_29 78 +#define GPIOX_0 79 +#define GPIOX_1 80 +#define GPIOX_2 81 +#define GPIOX_3 82 +#define GPIOX_4 83 +#define GPIOX_5 84 +#define GPIOX_6 85 +#define GPIOX_7 86 +#define GPIOX_8 87 +#define GPIOX_9 88 +#define GPIOX_10 89 +#define GPIOX_11 90 +#define GPIOX_12 91 +#define GPIOX_13 92 +#define GPIOX_14 93 +#define GPIOX_15 94 +#define GPIOX_16 95 +#define GPIOX_17 96 +#define GPIOX_18 97 +#define GPIOCLK_0 98 +#define GPIOCLK_1 99 + +#endif diff --git a/roms/u-boot/include/dt-bindings/gpio/sandbox-gpio.h b/roms/u-boot/include/dt-bindings/gpio/sandbox-gpio.h new file mode 100644 index 000000000..e4bfdb3ce --- /dev/null +++ b/roms/u-boot/include/dt-bindings/gpio/sandbox-gpio.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for binding sandbox,gpio + * + */ +#ifndef _DT_BINDINGS_GPIO_SANDBOX_GPIO_H +#define _DT_BINDINGS_GPIO_SANDBOX_GPIO_H + +/* + * Add a specific binding for sandbox gpio. + * The value need to be after the generic defines of + * dt-bindings/gpio/gpio.h + */ + +/* Bit 16 express GPIO input mode */ +#define GPIO_IN 0x10000 + +/* Bit 17 express GPIO output mode */ +#define GPIO_OUT 0x20000 + +/* Bit 18 express GPIO output is active */ +#define GPIO_OUT_ACTIVE 0x40000 + +#endif diff --git a/roms/u-boot/include/dt-bindings/gpio/tegra-gpio.h b/roms/u-boot/include/dt-bindings/gpio/tegra-gpio.h new file mode 100644 index 000000000..a1c09e88e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/gpio/tegra-gpio.h @@ -0,0 +1,51 @@ +/* + * This header provides constants for binding nvidia,tegra*-gpio. + * + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below + * provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H +#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H + +#include + +#define TEGRA_GPIO_PORT_A 0 +#define TEGRA_GPIO_PORT_B 1 +#define TEGRA_GPIO_PORT_C 2 +#define TEGRA_GPIO_PORT_D 3 +#define TEGRA_GPIO_PORT_E 4 +#define TEGRA_GPIO_PORT_F 5 +#define TEGRA_GPIO_PORT_G 6 +#define TEGRA_GPIO_PORT_H 7 +#define TEGRA_GPIO_PORT_I 8 +#define TEGRA_GPIO_PORT_J 9 +#define TEGRA_GPIO_PORT_K 10 +#define TEGRA_GPIO_PORT_L 11 +#define TEGRA_GPIO_PORT_M 12 +#define TEGRA_GPIO_PORT_N 13 +#define TEGRA_GPIO_PORT_O 14 +#define TEGRA_GPIO_PORT_P 15 +#define TEGRA_GPIO_PORT_Q 16 +#define TEGRA_GPIO_PORT_R 17 +#define TEGRA_GPIO_PORT_S 18 +#define TEGRA_GPIO_PORT_T 19 +#define TEGRA_GPIO_PORT_U 20 +#define TEGRA_GPIO_PORT_V 21 +#define TEGRA_GPIO_PORT_W 22 +#define TEGRA_GPIO_PORT_X 23 +#define TEGRA_GPIO_PORT_Y 24 +#define TEGRA_GPIO_PORT_Z 25 +#define TEGRA_GPIO_PORT_AA 26 +#define TEGRA_GPIO_PORT_BB 27 +#define TEGRA_GPIO_PORT_CC 28 +#define TEGRA_GPIO_PORT_DD 29 +#define TEGRA_GPIO_PORT_EE 30 +#define TEGRA_GPIO_PORT_FF 31 + +#define TEGRA_GPIO(port, offset) \ + ((TEGRA_GPIO_PORT_##port * 8) + offset) + +#endif diff --git a/roms/u-boot/include/dt-bindings/gpio/tegra186-gpio.h b/roms/u-boot/include/dt-bindings/gpio/tegra186-gpio.h new file mode 100644 index 000000000..83a19dc7e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/gpio/tegra186-gpio.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * This header provides constants for binding nvidia,tegra186-gpio*. + * + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below + * provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H +#define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H + +#include + +/* GPIOs implemented by main GPIO controller */ +#define TEGRA_MAIN_GPIO_PORT_A 0 +#define TEGRA_MAIN_GPIO_PORT_B 1 +#define TEGRA_MAIN_GPIO_PORT_C 2 +#define TEGRA_MAIN_GPIO_PORT_D 3 +#define TEGRA_MAIN_GPIO_PORT_E 4 +#define TEGRA_MAIN_GPIO_PORT_F 5 +#define TEGRA_MAIN_GPIO_PORT_G 6 +#define TEGRA_MAIN_GPIO_PORT_H 7 +#define TEGRA_MAIN_GPIO_PORT_I 8 +#define TEGRA_MAIN_GPIO_PORT_J 9 +#define TEGRA_MAIN_GPIO_PORT_K 10 +#define TEGRA_MAIN_GPIO_PORT_L 11 +#define TEGRA_MAIN_GPIO_PORT_M 12 +#define TEGRA_MAIN_GPIO_PORT_N 13 +#define TEGRA_MAIN_GPIO_PORT_O 14 +#define TEGRA_MAIN_GPIO_PORT_P 15 +#define TEGRA_MAIN_GPIO_PORT_Q 16 +#define TEGRA_MAIN_GPIO_PORT_R 17 +#define TEGRA_MAIN_GPIO_PORT_T 18 +#define TEGRA_MAIN_GPIO_PORT_X 19 +#define TEGRA_MAIN_GPIO_PORT_Y 20 +#define TEGRA_MAIN_GPIO_PORT_BB 21 +#define TEGRA_MAIN_GPIO_PORT_CC 22 + +#define TEGRA_MAIN_GPIO(port, offset) \ + ((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset) + +/* GPIOs implemented by AON GPIO controller */ +#define TEGRA_AON_GPIO_PORT_S 0 +#define TEGRA_AON_GPIO_PORT_U 1 +#define TEGRA_AON_GPIO_PORT_V 2 +#define TEGRA_AON_GPIO_PORT_W 3 +#define TEGRA_AON_GPIO_PORT_Z 4 +#define TEGRA_AON_GPIO_PORT_AA 5 +#define TEGRA_AON_GPIO_PORT_EE 6 +#define TEGRA_AON_GPIO_PORT_FF 7 + +#define TEGRA_AON_GPIO(port, offset) \ + ((TEGRA_AON_GPIO_PORT_##port * 8) + offset) + +#endif diff --git a/roms/u-boot/include/dt-bindings/gpio/uniphier-gpio.h b/roms/u-boot/include/dt-bindings/gpio/uniphier-gpio.h new file mode 100644 index 000000000..9f0ad174f --- /dev/null +++ b/roms/u-boot/include/dt-bindings/gpio/uniphier-gpio.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * Author: Masahiro Yamada + */ + +#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H +#define _DT_BINDINGS_GPIO_UNIPHIER_H + +#define UNIPHIER_GPIO_LINES_PER_BANK 8 + +#define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15) + +#define UNIPHIER_GPIO_PORT(bank, line) \ + ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line)) + +#define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n)) + +#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */ diff --git a/roms/u-boot/include/dt-bindings/gpio/x86-gpio.h b/roms/u-boot/include/dt-bindings/gpio/x86-gpio.h new file mode 100644 index 000000000..3998a8e0c --- /dev/null +++ b/roms/u-boot/include/dt-bindings/gpio/x86-gpio.h @@ -0,0 +1,43 @@ +/* + * This header provides constants for binding intel,x86-pinctrl. + */ + +#ifndef _DT_BINDINGS_GPIO_X86_GPIO_H +#define _DT_BINDINGS_GPIO_X86_GPIO_H + +#include + +#define GPIO_MODE_NATIVE 0 +#define GPIO_MODE_GPIO 1 + +#define GPIO_MODE_FUNC0 0 +#define GPIO_MODE_FUNC1 1 +#define GPIO_MODE_FUNC2 2 +#define GPIO_MODE_FUNC3 3 +#define GPIO_MODE_FUNC4 4 +#define GPIO_MODE_FUNC5 5 +#define GPIO_MODE_FUNC6 6 + +#define PIN_INPUT 0 +#define PIN_OUTPUT 1 + +#define PIN_INPUT_NOPULL 0 +#define PIN_INPUT_PULLUP 1 +#define PIN_INPUT_PULLDOWN 2 + +#define PULL_STR_2K 0 +#define PULL_STR_20K 2 + +#define ROUTE_SCI 0 +#define ROUTE_SMI 1 + +#define OWNER_ACPI 0 +#define OWNER_GPIO 1 + +#define PIRQ_APIC_MASK 0 +#define PIRQ_APIC_ROUTE 1 + +#define TRIGGER_EDGE 0 +#define TRIGGER_LEVEL 1 + +#endif diff --git a/roms/u-boot/include/dt-bindings/input/gpio-keys.h b/roms/u-boot/include/dt-bindings/input/gpio-keys.h new file mode 100644 index 000000000..8962df79e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/input/gpio-keys.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for gpio keys bindings. + */ + +#ifndef _DT_BINDINGS_GPIO_KEYS_H +#define _DT_BINDINGS_GPIO_KEYS_H + +#define EV_ACT_ANY 0x00 /* asserted or deasserted */ +#define EV_ACT_ASSERTED 0x01 /* asserted */ +#define EV_ACT_DEASSERTED 0x02 /* deasserted */ + +#endif /* _DT_BINDINGS_GPIO_KEYS_H */ diff --git a/roms/u-boot/include/dt-bindings/input/input.h b/roms/u-boot/include/dt-bindings/input/input.h new file mode 100644 index 000000000..a21413324 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/input/input.h @@ -0,0 +1,17 @@ +/* + * This header provides constants for most input bindings. + * + * Most input bindings include key code, matrix key code format. + * In most cases, key code and matrix key code format uses + * the standard values/macro defined in this header. + */ + +#ifndef _DT_BINDINGS_INPUT_INPUT_H +#define _DT_BINDINGS_INPUT_INPUT_H + +#include "linux-event-codes.h" + +#define MATRIX_KEY(row, col, code) \ + ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) + +#endif /* _DT_BINDINGS_INPUT_INPUT_H */ diff --git a/roms/u-boot/include/dt-bindings/input/linux-event-codes.h b/roms/u-boot/include/dt-bindings/input/linux-event-codes.h new file mode 100644 index 000000000..87cf351ba --- /dev/null +++ b/roms/u-boot/include/dt-bindings/input/linux-event-codes.h @@ -0,0 +1,805 @@ +/* + * Input event codes + * + * *** IMPORTANT *** + * This file is not only included from C-code but also from devicetree source + * files. As such this file MUST only contain comments and defines. + * + * Copyright (c) 1999-2002 Vojtech Pavlik + * Copyright (c) 2015 Hans de Goede + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ +#ifndef _UAPI_INPUT_EVENT_CODES_H +#define _UAPI_INPUT_EVENT_CODES_H + +/* + * Device properties and quirks + */ + +#define INPUT_PROP_POINTER 0x00 /* needs a pointer */ +#define INPUT_PROP_DIRECT 0x01 /* direct input devices */ +#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ +#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ +#define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ +#define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ +#define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ + +#define INPUT_PROP_MAX 0x1f +#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) + +/* + * Event types + */ + +#define EV_SYN 0x00 +#define EV_KEY 0x01 +#define EV_REL 0x02 +#define EV_ABS 0x03 +#define EV_MSC 0x04 +#define EV_SW 0x05 +#define EV_LED 0x11 +#define EV_SND 0x12 +#define EV_REP 0x14 +#define EV_FF 0x15 +#define EV_PWR 0x16 +#define EV_FF_STATUS 0x17 +#define EV_MAX 0x1f +#define EV_CNT (EV_MAX+1) + +/* + * Synchronization events. + */ + +#define SYN_REPORT 0 +#define SYN_CONFIG 1 +#define SYN_MT_REPORT 2 +#define SYN_DROPPED 3 +#define SYN_MAX 0xf +#define SYN_CNT (SYN_MAX+1) + +/* + * Keys and buttons + * + * Most of the keys/buttons are modeled after USB HUT 1.12 + * (see http://www.usb.org/developers/hidpage). + * Abbreviations in the comments: + * AC - Application Control + * AL - Application Launch Button + * SC - System Control + */ + +#define KEY_RESERVED 0 +#define KEY_ESC 1 +#define KEY_1 2 +#define KEY_2 3 +#define KEY_3 4 +#define KEY_4 5 +#define KEY_5 6 +#define KEY_6 7 +#define KEY_7 8 +#define KEY_8 9 +#define KEY_9 10 +#define KEY_0 11 +#define KEY_MINUS 12 +#define KEY_EQUAL 13 +#define KEY_BACKSPACE 14 +#define KEY_TAB 15 +#define KEY_Q 16 +#define KEY_W 17 +#define KEY_E 18 +#define KEY_R 19 +#define KEY_T 20 +#define KEY_Y 21 +#define KEY_U 22 +#define KEY_I 23 +#define KEY_O 24 +#define KEY_P 25 +#define KEY_LEFTBRACE 26 +#define KEY_RIGHTBRACE 27 +#define KEY_ENTER 28 +#define KEY_LEFTCTRL 29 +#define KEY_A 30 +#define KEY_S 31 +#define KEY_D 32 +#define KEY_F 33 +#define KEY_G 34 +#define KEY_H 35 +#define KEY_J 36 +#define KEY_K 37 +#define KEY_L 38 +#define KEY_SEMICOLON 39 +#define KEY_APOSTROPHE 40 +#define KEY_GRAVE 41 +#define KEY_LEFTSHIFT 42 +#define KEY_BACKSLASH 43 +#define KEY_Z 44 +#define KEY_X 45 +#define KEY_C 46 +#define KEY_V 47 +#define KEY_B 48 +#define KEY_N 49 +#define KEY_M 50 +#define KEY_COMMA 51 +#define KEY_DOT 52 +#define KEY_SLASH 53 +#define KEY_RIGHTSHIFT 54 +#define KEY_KPASTERISK 55 +#define KEY_LEFTALT 56 +#define KEY_SPACE 57 +#define KEY_CAPSLOCK 58 +#define KEY_F1 59 +#define KEY_F2 60 +#define KEY_F3 61 +#define KEY_F4 62 +#define KEY_F5 63 +#define KEY_F6 64 +#define KEY_F7 65 +#define KEY_F8 66 +#define KEY_F9 67 +#define KEY_F10 68 +#define KEY_NUMLOCK 69 +#define KEY_SCROLLLOCK 70 +#define KEY_KP7 71 +#define KEY_KP8 72 +#define KEY_KP9 73 +#define KEY_KPMINUS 74 +#define KEY_KP4 75 +#define KEY_KP5 76 +#define KEY_KP6 77 +#define KEY_KPPLUS 78 +#define KEY_KP1 79 +#define KEY_KP2 80 +#define KEY_KP3 81 +#define KEY_KP0 82 +#define KEY_KPDOT 83 + +#define KEY_ZENKAKUHANKAKU 85 +#define KEY_102ND 86 +#define KEY_F11 87 +#define KEY_F12 88 +#define KEY_RO 89 +#define KEY_KATAKANA 90 +#define KEY_HIRAGANA 91 +#define KEY_HENKAN 92 +#define KEY_KATAKANAHIRAGANA 93 +#define KEY_MUHENKAN 94 +#define KEY_KPJPCOMMA 95 +#define KEY_KPENTER 96 +#define KEY_RIGHTCTRL 97 +#define KEY_KPSLASH 98 +#define KEY_SYSRQ 99 +#define KEY_RIGHTALT 100 +#define KEY_LINEFEED 101 +#define KEY_HOME 102 +#define KEY_UP 103 +#define KEY_PAGEUP 104 +#define KEY_LEFT 105 +#define KEY_RIGHT 106 +#define KEY_END 107 +#define KEY_DOWN 108 +#define KEY_PAGEDOWN 109 +#define KEY_INSERT 110 +#define KEY_DELETE 111 +#define KEY_MACRO 112 +#define KEY_MUTE 113 +#define KEY_VOLUMEDOWN 114 +#define KEY_VOLUMEUP 115 +#define KEY_POWER 116 /* SC System Power Down */ +#define KEY_KPEQUAL 117 +#define KEY_KPPLUSMINUS 118 +#define KEY_PAUSE 119 +#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ + +#define KEY_KPCOMMA 121 +#define KEY_HANGEUL 122 +#define KEY_HANGUEL KEY_HANGEUL +#define KEY_HANJA 123 +#define KEY_YEN 124 +#define KEY_LEFTMETA 125 +#define KEY_RIGHTMETA 126 +#define KEY_COMPOSE 127 + +#define KEY_STOP 128 /* AC Stop */ +#define KEY_AGAIN 129 +#define KEY_PROPS 130 /* AC Properties */ +#define KEY_UNDO 131 /* AC Undo */ +#define KEY_FRONT 132 +#define KEY_COPY 133 /* AC Copy */ +#define KEY_OPEN 134 /* AC Open */ +#define KEY_PASTE 135 /* AC Paste */ +#define KEY_FIND 136 /* AC Search */ +#define KEY_CUT 137 /* AC Cut */ +#define KEY_HELP 138 /* AL Integrated Help Center */ +#define KEY_MENU 139 /* Menu (show menu) */ +#define KEY_CALC 140 /* AL Calculator */ +#define KEY_SETUP 141 +#define KEY_SLEEP 142 /* SC System Sleep */ +#define KEY_WAKEUP 143 /* System Wake Up */ +#define KEY_FILE 144 /* AL Local Machine Browser */ +#define KEY_SENDFILE 145 +#define KEY_DELETEFILE 146 +#define KEY_XFER 147 +#define KEY_PROG1 148 +#define KEY_PROG2 149 +#define KEY_WWW 150 /* AL Internet Browser */ +#define KEY_MSDOS 151 +#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ +#define KEY_SCREENLOCK KEY_COFFEE +#define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ +#define KEY_DIRECTION KEY_ROTATE_DISPLAY +#define KEY_CYCLEWINDOWS 154 +#define KEY_MAIL 155 +#define KEY_BOOKMARKS 156 /* AC Bookmarks */ +#define KEY_COMPUTER 157 +#define KEY_BACK 158 /* AC Back */ +#define KEY_FORWARD 159 /* AC Forward */ +#define KEY_CLOSECD 160 +#define KEY_EJECTCD 161 +#define KEY_EJECTCLOSECD 162 +#define KEY_NEXTSONG 163 +#define KEY_PLAYPAUSE 164 +#define KEY_PREVIOUSSONG 165 +#define KEY_STOPCD 166 +#define KEY_RECORD 167 +#define KEY_REWIND 168 +#define KEY_PHONE 169 /* Media Select Telephone */ +#define KEY_ISO 170 +#define KEY_CONFIG 171 /* AL Consumer Control Configuration */ +#define KEY_HOMEPAGE 172 /* AC Home */ +#define KEY_REFRESH 173 /* AC Refresh */ +#define KEY_EXIT 174 /* AC Exit */ +#define KEY_MOVE 175 +#define KEY_EDIT 176 +#define KEY_SCROLLUP 177 +#define KEY_SCROLLDOWN 178 +#define KEY_KPLEFTPAREN 179 +#define KEY_KPRIGHTPAREN 180 +#define KEY_NEW 181 /* AC New */ +#define KEY_REDO 182 /* AC Redo/Repeat */ + +#define KEY_F13 183 +#define KEY_F14 184 +#define KEY_F15 185 +#define KEY_F16 186 +#define KEY_F17 187 +#define KEY_F18 188 +#define KEY_F19 189 +#define KEY_F20 190 +#define KEY_F21 191 +#define KEY_F22 192 +#define KEY_F23 193 +#define KEY_F24 194 + +#define KEY_PLAYCD 200 +#define KEY_PAUSECD 201 +#define KEY_PROG3 202 +#define KEY_PROG4 203 +#define KEY_DASHBOARD 204 /* AL Dashboard */ +#define KEY_SUSPEND 205 +#define KEY_CLOSE 206 /* AC Close */ +#define KEY_PLAY 207 +#define KEY_FASTFORWARD 208 +#define KEY_BASSBOOST 209 +#define KEY_PRINT 210 /* AC Print */ +#define KEY_HP 211 +#define KEY_CAMERA 212 +#define KEY_SOUND 213 +#define KEY_QUESTION 214 +#define KEY_EMAIL 215 +#define KEY_CHAT 216 +#define KEY_SEARCH 217 +#define KEY_CONNECT 218 +#define KEY_FINANCE 219 /* AL Checkbook/Finance */ +#define KEY_SPORT 220 +#define KEY_SHOP 221 +#define KEY_ALTERASE 222 +#define KEY_CANCEL 223 /* AC Cancel */ +#define KEY_BRIGHTNESSDOWN 224 +#define KEY_BRIGHTNESSUP 225 +#define KEY_MEDIA 226 + +#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video + outputs (Monitor/LCD/TV-out/etc) */ +#define KEY_KBDILLUMTOGGLE 228 +#define KEY_KBDILLUMDOWN 229 +#define KEY_KBDILLUMUP 230 + +#define KEY_SEND 231 /* AC Send */ +#define KEY_REPLY 232 /* AC Reply */ +#define KEY_FORWARDMAIL 233 /* AC Forward Msg */ +#define KEY_SAVE 234 /* AC Save */ +#define KEY_DOCUMENTS 235 + +#define KEY_BATTERY 236 + +#define KEY_BLUETOOTH 237 +#define KEY_WLAN 238 +#define KEY_UWB 239 + +#define KEY_UNKNOWN 240 + +#define KEY_VIDEO_NEXT 241 /* drive next video source */ +#define KEY_VIDEO_PREV 242 /* drive previous video source */ +#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ +#define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual + brightness control is off, + rely on ambient */ +#define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO +#define KEY_DISPLAY_OFF 245 /* display device to off state */ + +#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ +#define KEY_WIMAX KEY_WWAN +#define KEY_RFKILL 247 /* Key that controls all radios */ + +#define KEY_MICMUTE 248 /* Mute / unmute the microphone */ + +/* Code 255 is reserved for special needs of AT keyboard driver */ + +#define BTN_MISC 0x100 +#define BTN_0 0x100 +#define BTN_1 0x101 +#define BTN_2 0x102 +#define BTN_3 0x103 +#define BTN_4 0x104 +#define BTN_5 0x105 +#define BTN_6 0x106 +#define BTN_7 0x107 +#define BTN_8 0x108 +#define BTN_9 0x109 + +#define BTN_MOUSE 0x110 +#define BTN_LEFT 0x110 +#define BTN_RIGHT 0x111 +#define BTN_MIDDLE 0x112 +#define BTN_SIDE 0x113 +#define BTN_EXTRA 0x114 +#define BTN_FORWARD 0x115 +#define BTN_BACK 0x116 +#define BTN_TASK 0x117 + +#define BTN_JOYSTICK 0x120 +#define BTN_TRIGGER 0x120 +#define BTN_THUMB 0x121 +#define BTN_THUMB2 0x122 +#define BTN_TOP 0x123 +#define BTN_TOP2 0x124 +#define BTN_PINKIE 0x125 +#define BTN_BASE 0x126 +#define BTN_BASE2 0x127 +#define BTN_BASE3 0x128 +#define BTN_BASE4 0x129 +#define BTN_BASE5 0x12a +#define BTN_BASE6 0x12b +#define BTN_DEAD 0x12f + +#define BTN_GAMEPAD 0x130 +#define BTN_SOUTH 0x130 +#define BTN_A BTN_SOUTH +#define BTN_EAST 0x131 +#define BTN_B BTN_EAST +#define BTN_C 0x132 +#define BTN_NORTH 0x133 +#define BTN_X BTN_NORTH +#define BTN_WEST 0x134 +#define BTN_Y BTN_WEST +#define BTN_Z 0x135 +#define BTN_TL 0x136 +#define BTN_TR 0x137 +#define BTN_TL2 0x138 +#define BTN_TR2 0x139 +#define BTN_SELECT 0x13a +#define BTN_START 0x13b +#define BTN_MODE 0x13c +#define BTN_THUMBL 0x13d +#define BTN_THUMBR 0x13e + +#define BTN_DIGI 0x140 +#define BTN_TOOL_PEN 0x140 +#define BTN_TOOL_RUBBER 0x141 +#define BTN_TOOL_BRUSH 0x142 +#define BTN_TOOL_PENCIL 0x143 +#define BTN_TOOL_AIRBRUSH 0x144 +#define BTN_TOOL_FINGER 0x145 +#define BTN_TOOL_MOUSE 0x146 +#define BTN_TOOL_LENS 0x147 +#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ +#define BTN_TOUCH 0x14a +#define BTN_STYLUS 0x14b +#define BTN_STYLUS2 0x14c +#define BTN_TOOL_DOUBLETAP 0x14d +#define BTN_TOOL_TRIPLETAP 0x14e +#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ + +#define BTN_WHEEL 0x150 +#define BTN_GEAR_DOWN 0x150 +#define BTN_GEAR_UP 0x151 + +#define KEY_OK 0x160 +#define KEY_SELECT 0x161 +#define KEY_GOTO 0x162 +#define KEY_CLEAR 0x163 +#define KEY_POWER2 0x164 +#define KEY_OPTION 0x165 +#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ +#define KEY_TIME 0x167 +#define KEY_VENDOR 0x168 +#define KEY_ARCHIVE 0x169 +#define KEY_PROGRAM 0x16a /* Media Select Program Guide */ +#define KEY_CHANNEL 0x16b +#define KEY_FAVORITES 0x16c +#define KEY_EPG 0x16d +#define KEY_PVR 0x16e /* Media Select Home */ +#define KEY_MHP 0x16f +#define KEY_LANGUAGE 0x170 +#define KEY_TITLE 0x171 +#define KEY_SUBTITLE 0x172 +#define KEY_ANGLE 0x173 +#define KEY_ZOOM 0x174 +#define KEY_MODE 0x175 +#define KEY_KEYBOARD 0x176 +#define KEY_SCREEN 0x177 +#define KEY_PC 0x178 /* Media Select Computer */ +#define KEY_TV 0x179 /* Media Select TV */ +#define KEY_TV2 0x17a /* Media Select Cable */ +#define KEY_VCR 0x17b /* Media Select VCR */ +#define KEY_VCR2 0x17c /* VCR Plus */ +#define KEY_SAT 0x17d /* Media Select Satellite */ +#define KEY_SAT2 0x17e +#define KEY_CD 0x17f /* Media Select CD */ +#define KEY_TAPE 0x180 /* Media Select Tape */ +#define KEY_RADIO 0x181 +#define KEY_TUNER 0x182 /* Media Select Tuner */ +#define KEY_PLAYER 0x183 +#define KEY_TEXT 0x184 +#define KEY_DVD 0x185 /* Media Select DVD */ +#define KEY_AUX 0x186 +#define KEY_MP3 0x187 +#define KEY_AUDIO 0x188 /* AL Audio Browser */ +#define KEY_VIDEO 0x189 /* AL Movie Browser */ +#define KEY_DIRECTORY 0x18a +#define KEY_LIST 0x18b +#define KEY_MEMO 0x18c /* Media Select Messages */ +#define KEY_CALENDAR 0x18d +#define KEY_RED 0x18e +#define KEY_GREEN 0x18f +#define KEY_YELLOW 0x190 +#define KEY_BLUE 0x191 +#define KEY_CHANNELUP 0x192 /* Channel Increment */ +#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ +#define KEY_FIRST 0x194 +#define KEY_LAST 0x195 /* Recall Last */ +#define KEY_AB 0x196 +#define KEY_NEXT 0x197 +#define KEY_RESTART 0x198 +#define KEY_SLOW 0x199 +#define KEY_SHUFFLE 0x19a +#define KEY_BREAK 0x19b +#define KEY_PREVIOUS 0x19c +#define KEY_DIGITS 0x19d +#define KEY_TEEN 0x19e +#define KEY_TWEN 0x19f +#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ +#define KEY_GAMES 0x1a1 /* Media Select Games */ +#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ +#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ +#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ +#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ +#define KEY_EDITOR 0x1a6 /* AL Text Editor */ +#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ +#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ +#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ +#define KEY_DATABASE 0x1aa /* AL Database App */ +#define KEY_NEWS 0x1ab /* AL Newsreader */ +#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ +#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ +#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ +#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ +#define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE +#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ +#define KEY_LOGOFF 0x1b1 /* AL Logoff */ + +#define KEY_DOLLAR 0x1b2 +#define KEY_EURO 0x1b3 + +#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ +#define KEY_FRAMEFORWARD 0x1b5 +#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ +#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ +#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ +#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ +#define KEY_IMAGES 0x1ba /* AL Image Browser */ + +#define KEY_DEL_EOL 0x1c0 +#define KEY_DEL_EOS 0x1c1 +#define KEY_INS_LINE 0x1c2 +#define KEY_DEL_LINE 0x1c3 + +#define KEY_FN 0x1d0 +#define KEY_FN_ESC 0x1d1 +#define KEY_FN_F1 0x1d2 +#define KEY_FN_F2 0x1d3 +#define KEY_FN_F3 0x1d4 +#define KEY_FN_F4 0x1d5 +#define KEY_FN_F5 0x1d6 +#define KEY_FN_F6 0x1d7 +#define KEY_FN_F7 0x1d8 +#define KEY_FN_F8 0x1d9 +#define KEY_FN_F9 0x1da +#define KEY_FN_F10 0x1db +#define KEY_FN_F11 0x1dc +#define KEY_FN_F12 0x1dd +#define KEY_FN_1 0x1de +#define KEY_FN_2 0x1df +#define KEY_FN_D 0x1e0 +#define KEY_FN_E 0x1e1 +#define KEY_FN_F 0x1e2 +#define KEY_FN_S 0x1e3 +#define KEY_FN_B 0x1e4 + +#define KEY_BRL_DOT1 0x1f1 +#define KEY_BRL_DOT2 0x1f2 +#define KEY_BRL_DOT3 0x1f3 +#define KEY_BRL_DOT4 0x1f4 +#define KEY_BRL_DOT5 0x1f5 +#define KEY_BRL_DOT6 0x1f6 +#define KEY_BRL_DOT7 0x1f7 +#define KEY_BRL_DOT8 0x1f8 +#define KEY_BRL_DOT9 0x1f9 +#define KEY_BRL_DOT10 0x1fa + +#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ +#define KEY_NUMERIC_1 0x201 /* and other keypads */ +#define KEY_NUMERIC_2 0x202 +#define KEY_NUMERIC_3 0x203 +#define KEY_NUMERIC_4 0x204 +#define KEY_NUMERIC_5 0x205 +#define KEY_NUMERIC_6 0x206 +#define KEY_NUMERIC_7 0x207 +#define KEY_NUMERIC_8 0x208 +#define KEY_NUMERIC_9 0x209 +#define KEY_NUMERIC_STAR 0x20a +#define KEY_NUMERIC_POUND 0x20b +#define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ +#define KEY_NUMERIC_B 0x20d +#define KEY_NUMERIC_C 0x20e +#define KEY_NUMERIC_D 0x20f + +#define KEY_CAMERA_FOCUS 0x210 +#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ + +#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ +#define KEY_TOUCHPAD_ON 0x213 +#define KEY_TOUCHPAD_OFF 0x214 + +#define KEY_CAMERA_ZOOMIN 0x215 +#define KEY_CAMERA_ZOOMOUT 0x216 +#define KEY_CAMERA_UP 0x217 +#define KEY_CAMERA_DOWN 0x218 +#define KEY_CAMERA_LEFT 0x219 +#define KEY_CAMERA_RIGHT 0x21a + +#define KEY_ATTENDANT_ON 0x21b +#define KEY_ATTENDANT_OFF 0x21c +#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ +#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ + +#define BTN_DPAD_UP 0x220 +#define BTN_DPAD_DOWN 0x221 +#define BTN_DPAD_LEFT 0x222 +#define BTN_DPAD_RIGHT 0x223 + +#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ + +#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ +#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ +#define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ +#define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ +#define KEY_APPSELECT 0x244 /* AL Select Task/Application */ +#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ +#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ + +#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ +#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ + +#define KEY_KBDINPUTASSIST_PREV 0x260 +#define KEY_KBDINPUTASSIST_NEXT 0x261 +#define KEY_KBDINPUTASSIST_PREVGROUP 0x262 +#define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 +#define KEY_KBDINPUTASSIST_ACCEPT 0x264 +#define KEY_KBDINPUTASSIST_CANCEL 0x265 + +#define BTN_TRIGGER_HAPPY 0x2c0 +#define BTN_TRIGGER_HAPPY1 0x2c0 +#define BTN_TRIGGER_HAPPY2 0x2c1 +#define BTN_TRIGGER_HAPPY3 0x2c2 +#define BTN_TRIGGER_HAPPY4 0x2c3 +#define BTN_TRIGGER_HAPPY5 0x2c4 +#define BTN_TRIGGER_HAPPY6 0x2c5 +#define BTN_TRIGGER_HAPPY7 0x2c6 +#define BTN_TRIGGER_HAPPY8 0x2c7 +#define BTN_TRIGGER_HAPPY9 0x2c8 +#define BTN_TRIGGER_HAPPY10 0x2c9 +#define BTN_TRIGGER_HAPPY11 0x2ca +#define BTN_TRIGGER_HAPPY12 0x2cb +#define BTN_TRIGGER_HAPPY13 0x2cc +#define BTN_TRIGGER_HAPPY14 0x2cd +#define BTN_TRIGGER_HAPPY15 0x2ce +#define BTN_TRIGGER_HAPPY16 0x2cf +#define BTN_TRIGGER_HAPPY17 0x2d0 +#define BTN_TRIGGER_HAPPY18 0x2d1 +#define BTN_TRIGGER_HAPPY19 0x2d2 +#define BTN_TRIGGER_HAPPY20 0x2d3 +#define BTN_TRIGGER_HAPPY21 0x2d4 +#define BTN_TRIGGER_HAPPY22 0x2d5 +#define BTN_TRIGGER_HAPPY23 0x2d6 +#define BTN_TRIGGER_HAPPY24 0x2d7 +#define BTN_TRIGGER_HAPPY25 0x2d8 +#define BTN_TRIGGER_HAPPY26 0x2d9 +#define BTN_TRIGGER_HAPPY27 0x2da +#define BTN_TRIGGER_HAPPY28 0x2db +#define BTN_TRIGGER_HAPPY29 0x2dc +#define BTN_TRIGGER_HAPPY30 0x2dd +#define BTN_TRIGGER_HAPPY31 0x2de +#define BTN_TRIGGER_HAPPY32 0x2df +#define BTN_TRIGGER_HAPPY33 0x2e0 +#define BTN_TRIGGER_HAPPY34 0x2e1 +#define BTN_TRIGGER_HAPPY35 0x2e2 +#define BTN_TRIGGER_HAPPY36 0x2e3 +#define BTN_TRIGGER_HAPPY37 0x2e4 +#define BTN_TRIGGER_HAPPY38 0x2e5 +#define BTN_TRIGGER_HAPPY39 0x2e6 +#define BTN_TRIGGER_HAPPY40 0x2e7 + +/* We avoid low common keys in module aliases so they don't get huge. */ +#define KEY_MIN_INTERESTING KEY_MUTE +#define KEY_MAX 0x2ff +#define KEY_CNT (KEY_MAX+1) + +/* + * Relative axes + */ + +#define REL_X 0x00 +#define REL_Y 0x01 +#define REL_Z 0x02 +#define REL_RX 0x03 +#define REL_RY 0x04 +#define REL_RZ 0x05 +#define REL_HWHEEL 0x06 +#define REL_DIAL 0x07 +#define REL_WHEEL 0x08 +#define REL_MISC 0x09 +#define REL_MAX 0x0f +#define REL_CNT (REL_MAX+1) + +/* + * Absolute axes + */ + +#define ABS_X 0x00 +#define ABS_Y 0x01 +#define ABS_Z 0x02 +#define ABS_RX 0x03 +#define ABS_RY 0x04 +#define ABS_RZ 0x05 +#define ABS_THROTTLE 0x06 +#define ABS_RUDDER 0x07 +#define ABS_WHEEL 0x08 +#define ABS_GAS 0x09 +#define ABS_BRAKE 0x0a +#define ABS_HAT0X 0x10 +#define ABS_HAT0Y 0x11 +#define ABS_HAT1X 0x12 +#define ABS_HAT1Y 0x13 +#define ABS_HAT2X 0x14 +#define ABS_HAT2Y 0x15 +#define ABS_HAT3X 0x16 +#define ABS_HAT3Y 0x17 +#define ABS_PRESSURE 0x18 +#define ABS_DISTANCE 0x19 +#define ABS_TILT_X 0x1a +#define ABS_TILT_Y 0x1b +#define ABS_TOOL_WIDTH 0x1c + +#define ABS_VOLUME 0x20 + +#define ABS_MISC 0x28 + +#define ABS_MT_SLOT 0x2f /* MT slot being modified */ +#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ +#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ +#define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ +#define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ +#define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ +#define ABS_MT_POSITION_X 0x35 /* Center X touch position */ +#define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ +#define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ +#define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ +#define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ +#define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ +#define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ +#define ABS_MT_TOOL_X 0x3c /* Center X tool position */ +#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ + + +#define ABS_MAX 0x3f +#define ABS_CNT (ABS_MAX+1) + +/* + * Switch events + */ + +#define SW_LID 0x00 /* set = lid shut */ +#define SW_TABLET_MODE 0x01 /* set = tablet mode */ +#define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ +#define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" + set = radio enabled */ +#define SW_RADIO SW_RFKILL_ALL /* deprecated */ +#define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ +#define SW_DOCK 0x05 /* set = plugged into dock */ +#define SW_LINEOUT_INSERT 0x06 /* set = inserted */ +#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ +#define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ +#define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ +#define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ +#define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ +#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ +#define SW_LINEIN_INSERT 0x0d /* set = inserted */ +#define SW_MUTE_DEVICE 0x0e /* set = device disabled */ +#define SW_MAX 0x0f +#define SW_CNT (SW_MAX+1) + +/* + * Misc events + */ + +#define MSC_SERIAL 0x00 +#define MSC_PULSELED 0x01 +#define MSC_GESTURE 0x02 +#define MSC_RAW 0x03 +#define MSC_SCAN 0x04 +#define MSC_TIMESTAMP 0x05 +#define MSC_MAX 0x07 +#define MSC_CNT (MSC_MAX+1) + +/* + * LEDs + */ + +#define LED_NUML 0x00 +#define LED_CAPSL 0x01 +#define LED_SCROLLL 0x02 +#define LED_COMPOSE 0x03 +#define LED_KANA 0x04 +#define LED_SLEEP 0x05 +#define LED_SUSPEND 0x06 +#define LED_MUTE 0x07 +#define LED_MISC 0x08 +#define LED_MAIL 0x09 +#define LED_CHARGING 0x0a +#define LED_MAX 0x0f +#define LED_CNT (LED_MAX+1) + +/* + * Autorepeat values + */ + +#define REP_DELAY 0x00 +#define REP_PERIOD 0x01 +#define REP_MAX 0x01 +#define REP_CNT (REP_MAX+1) + +/* + * Sounds + */ + +#define SND_CLICK 0x00 +#define SND_BELL 0x01 +#define SND_TONE 0x02 +#define SND_MAX 0x07 +#define SND_CNT (SND_MAX+1) + +#endif diff --git a/roms/u-boot/include/dt-bindings/interrupt-controller/arm-gic.h b/roms/u-boot/include/dt-bindings/interrupt-controller/arm-gic.h new file mode 100644 index 000000000..35b6f69b7 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/interrupt-controller/arm-gic.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * This header provides constants for the ARM GIC. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H + +#include + +/* interrupt specifier cell 0 */ + +#define GIC_SPI 0 +#define GIC_PPI 1 + +/* + * Interrupt specifier cell 2. + * The flags in irq.h are valid, plus those below. + */ +#define GIC_CPU_MASK_RAW(x) ((x) << 8) +#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) + +#endif diff --git a/roms/u-boot/include/dt-bindings/interrupt-controller/irq-st.h b/roms/u-boot/include/dt-bindings/interrupt-controller/irq-st.h new file mode 100644 index 000000000..6baa9ad26 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/interrupt-controller/irq-st.h @@ -0,0 +1,30 @@ +/* + * include/linux/irqchip/irq-st.h + * + * Copyright (C) 2014 STMicroelectronics All Rights Reserved + * + * Author: Lee Jones + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H + +#define ST_IRQ_SYSCFG_EXT_0 0 +#define ST_IRQ_SYSCFG_EXT_1 1 +#define ST_IRQ_SYSCFG_EXT_2 2 +#define ST_IRQ_SYSCFG_CTI_0 3 +#define ST_IRQ_SYSCFG_CTI_1 4 +#define ST_IRQ_SYSCFG_PMU_0 5 +#define ST_IRQ_SYSCFG_PMU_1 6 +#define ST_IRQ_SYSCFG_pl310_L2 7 +#define ST_IRQ_SYSCFG_DISABLED 0xFFFFFFFF + +#define ST_IRQ_SYSCFG_EXT_1_INV 0x1 +#define ST_IRQ_SYSCFG_EXT_2_INV 0x2 +#define ST_IRQ_SYSCFG_EXT_3_INV 0x4 + +#endif diff --git a/roms/u-boot/include/dt-bindings/interrupt-controller/irq.h b/roms/u-boot/include/dt-bindings/interrupt-controller/irq.h new file mode 100644 index 000000000..33a1003c5 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/interrupt-controller/irq.h @@ -0,0 +1,19 @@ +/* + * This header provides constants for most IRQ bindings. + * + * Most IRQ bindings include a flags cell as part of the IRQ specifier. + * In most cases, the format of the flags cell uses the standard values + * defined in this header. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H + +#define IRQ_TYPE_NONE 0 +#define IRQ_TYPE_EDGE_RISING 1 +#define IRQ_TYPE_EDGE_FALLING 2 +#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) +#define IRQ_TYPE_LEVEL_HIGH 4 +#define IRQ_TYPE_LEVEL_LOW 8 + +#endif diff --git a/roms/u-boot/include/dt-bindings/interrupt-controller/mips-gic.h b/roms/u-boot/include/dt-bindings/interrupt-controller/mips-gic.h new file mode 100644 index 000000000..cf35a577e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/interrupt-controller/mips-gic.h @@ -0,0 +1,9 @@ +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H + +#include + +#define GIC_SHARED 0 +#define GIC_LOCAL 1 + +#endif diff --git a/roms/u-boot/include/dt-bindings/interrupt-controller/x86-irq.h b/roms/u-boot/include/dt-bindings/interrupt-controller/x86-irq.h new file mode 100644 index 000000000..9e0b4612e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/interrupt-controller/x86-irq.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + * + * This provides additional flags used by x86. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_X86_IRQ_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_X86_IRQ_H + +#define X86_IRQ_TYPE_SHARED (1 << 4) +#define X86_IRQ_TYPE_WAKE (1 << 5) + +#endif diff --git a/roms/u-boot/include/dt-bindings/interrupt-router/intel-irq.h b/roms/u-boot/include/dt-bindings/interrupt-router/intel-irq.h new file mode 100644 index 000000000..2d1e671c1 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/interrupt-router/intel-irq.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015, Bin Meng + */ + +#ifndef _DT_BINDINGS_INTEL_IRQ_H_ +#define _DT_BINDINGS_INTEL_IRQ_H_ + +/* PCI interrupt pin */ +#define INTA 1 +#define INTB 2 +#define INTC 3 +#define INTD 4 + +/* PIRQs */ +#define PIRQA 0 +#define PIRQB 1 +#define PIRQC 2 +#define PIRQD 3 +#define PIRQE 4 +#define PIRQF 5 +#define PIRQG 6 +#define PIRQH 7 + +/* PCI bdf encoding */ +#ifndef PCI_BDF +#define PCI_BDF(b, d, f) ((b) << 16 | (d) << 11 | (f) << 8) +#endif + +#endif /* _DT_BINDINGS_INTEL_IRQ_H_ */ diff --git a/roms/u-boot/include/dt-bindings/leds/common.h b/roms/u-boot/include/dt-bindings/leds/common.h new file mode 100644 index 000000000..9e1256a7c --- /dev/null +++ b/roms/u-boot/include/dt-bindings/leds/common.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides macros for the common LEDs device tree bindings. + * + * Copyright (C) 2015, Samsung Electronics Co., Ltd. + * Author: Jacek Anaszewski + * + * Copyright (C) 2019 Jacek Anaszewski + */ + +#ifndef __DT_BINDINGS_LEDS_H +#define __DT_BINDINGS_LEDS_H + +/* External trigger type */ +#define LEDS_TRIG_TYPE_EDGE 0 +#define LEDS_TRIG_TYPE_LEVEL 1 + +/* Boost modes */ +#define LEDS_BOOST_OFF 0 +#define LEDS_BOOST_ADAPTIVE 1 +#define LEDS_BOOST_FIXED 2 + +/* Standard LED colors */ +#define LED_COLOR_ID_WHITE 0 +#define LED_COLOR_ID_RED 1 +#define LED_COLOR_ID_GREEN 2 +#define LED_COLOR_ID_BLUE 3 +#define LED_COLOR_ID_AMBER 4 +#define LED_COLOR_ID_VIOLET 5 +#define LED_COLOR_ID_YELLOW 6 +#define LED_COLOR_ID_IR 7 +#define LED_COLOR_ID_MAX 8 + +/* Standard LED functions */ +#define LED_FUNCTION_ACTIVITY "activity" +#define LED_FUNCTION_ALARM "alarm" +#define LED_FUNCTION_BACKLIGHT "backlight" +#define LED_FUNCTION_BLUETOOTH "bluetooth" +#define LED_FUNCTION_BOOT "boot" +#define LED_FUNCTION_CPU "cpu" +#define LED_FUNCTION_CAPSLOCK "capslock" +#define LED_FUNCTION_CHARGING "charging" +#define LED_FUNCTION_DEBUG "debug" +#define LED_FUNCTION_DISK "disk" +#define LED_FUNCTION_DISK_ACTIVITY "disk-activity" +#define LED_FUNCTION_DISK_ERR "disk-err" +#define LED_FUNCTION_DISK_READ "disk-read" +#define LED_FUNCTION_DISK_WRITE "disk-write" +#define LED_FUNCTION_FAULT "fault" +#define LED_FUNCTION_FLASH "flash" +#define LED_FUNCTION_HEARTBEAT "heartbeat" +#define LED_FUNCTION_INDICATOR "indicator" +#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight" +#define LED_FUNCTION_LAN "lan" +#define LED_FUNCTION_MAIL "mail" +#define LED_FUNCTION_MTD "mtd" +#define LED_FUNCTION_MICMUTE "micmute" +#define LED_FUNCTION_MUTE "mute" +#define LED_FUNCTION_NUMLOCK "numlock" +#define LED_FUNCTION_PANIC "panic" +#define LED_FUNCTION_PROGRAMMING "programming" +#define LED_FUNCTION_POWER "power" +#define LED_FUNCTION_RX "rx" +#define LED_FUNCTION_SD "sd" +#define LED_FUNCTION_SCROLLLOCK "scrolllock" +#define LED_FUNCTION_STANDBY "standby" +#define LED_FUNCTION_STATUS "status" +#define LED_FUNCTION_TORCH "torch" +#define LED_FUNCTION_TX "tx" +#define LED_FUNCTION_USB "usb" +#define LED_FUNCTION_WAN "wan" +#define LED_FUNCTION_WLAN "wlan" +#define LED_FUNCTION_WPS "wps" + +#endif /* __DT_BINDINGS_LEDS_H */ diff --git a/roms/u-boot/include/dt-bindings/leds/leds-netxbig.h b/roms/u-boot/include/dt-bindings/leds/leds-netxbig.h new file mode 100644 index 000000000..92658b031 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/leds/leds-netxbig.h @@ -0,0 +1,18 @@ +/* + * This header provides constants for netxbig LED bindings. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef _DT_BINDINGS_LEDS_NETXBIG_H +#define _DT_BINDINGS_LEDS_NETXBIG_H + +#define NETXBIG_LED_OFF 0 +#define NETXBIG_LED_ON 1 +#define NETXBIG_LED_SATA 2 +#define NETXBIG_LED_TIMER1 3 +#define NETXBIG_LED_TIMER2 4 + +#endif /* _DT_BINDINGS_LEDS_NETXBIG_H */ diff --git a/roms/u-boot/include/dt-bindings/leds/leds-ns2.h b/roms/u-boot/include/dt-bindings/leds/leds-ns2.h new file mode 100644 index 000000000..fd615749e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/leds/leds-ns2.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_LEDS_NS2_H +#define _DT_BINDINGS_LEDS_NS2_H + +#define NS_V2_LED_OFF 0 +#define NS_V2_LED_ON 1 +#define NS_V2_LED_SATA 2 + +#endif diff --git a/roms/u-boot/include/dt-bindings/leds/leds-pca9532.h b/roms/u-boot/include/dt-bindings/leds/leds-pca9532.h new file mode 100644 index 000000000..4d917aab7 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/leds/leds-pca9532.h @@ -0,0 +1,18 @@ +/* + * This header provides constants for pca9532 LED bindings. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef _DT_BINDINGS_LEDS_PCA9532_H +#define _DT_BINDINGS_LEDS_PCA9532_H + +#define PCA9532_TYPE_NONE 0 +#define PCA9532_TYPE_LED 1 +#define PCA9532_TYPE_N2100_BEEP 2 +#define PCA9532_TYPE_GPIO 3 +#define PCA9532_LED_TIMER2 4 + +#endif /* _DT_BINDINGS_LEDS_PCA9532_H */ diff --git a/roms/u-boot/include/dt-bindings/mailbox/tegra186-hsp.h b/roms/u-boot/include/dt-bindings/mailbox/tegra186-hsp.h new file mode 100644 index 000000000..b4864325d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/mailbox/tegra186-hsp.h @@ -0,0 +1,19 @@ +/* + * This header provides constants for binding nvidia,tegra186-hsp. + * + * The number with HSP_DB_MASTER prefix indicates the bit that is + * associated with a master ID in the doorbell registers. + */ + +#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H +#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H + +#define HSP_MBOX_TYPE_DB 0x0 +#define HSP_MBOX_TYPE_SM 0x1 +#define HSP_MBOX_TYPE_SS 0x2 +#define HSP_MBOX_TYPE_AS 0x3 + +#define HSP_DB_MASTER_CCPLEX 17 +#define HSP_DB_MASTER_BPMP 19 + +#endif diff --git a/roms/u-boot/include/dt-bindings/media/omap3-isp.h b/roms/u-boot/include/dt-bindings/media/omap3-isp.h new file mode 100644 index 000000000..4e4208462 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/media/omap3-isp.h @@ -0,0 +1,22 @@ +/* + * include/dt-bindings/media/omap3-isp.h + * + * Copyright (C) 2015 Sakari Ailus + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#ifndef __DT_BINDINGS_OMAP3_ISP_H__ +#define __DT_BINDINGS_OMAP3_ISP_H__ + +#define OMAP3ISP_PHY_TYPE_COMPLEX_IO 0 +#define OMAP3ISP_PHY_TYPE_CSIPHY 1 + +#endif /* __DT_BINDINGS_OMAP3_ISP_H__ */ diff --git a/roms/u-boot/include/dt-bindings/media/tda1997x.h b/roms/u-boot/include/dt-bindings/media/tda1997x.h new file mode 100644 index 000000000..bd9fbd718 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/media/tda1997x.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 Gateworks Corporation + */ +#ifndef _DT_BINDINGS_MEDIA_TDA1997X_H +#define _DT_BINDINGS_MEDIA_TDA1997X_H + +/* TDA19973 36bit Video Port control registers */ +#define TDA1997X_VP36_35_32 0 +#define TDA1997X_VP36_31_28 1 +#define TDA1997X_VP36_27_24 2 +#define TDA1997X_VP36_23_20 3 +#define TDA1997X_VP36_19_16 4 +#define TDA1997X_VP36_15_12 5 +#define TDA1997X_VP36_11_08 6 +#define TDA1997X_VP36_07_04 7 +#define TDA1997X_VP36_03_00 8 + +/* TDA19971 24bit Video Port control registers */ +#define TDA1997X_VP24_V23_20 0 +#define TDA1997X_VP24_V19_16 1 +#define TDA1997X_VP24_V15_12 3 +#define TDA1997X_VP24_V11_08 4 +#define TDA1997X_VP24_V07_04 6 +#define TDA1997X_VP24_V03_00 7 + +/* Pin groups */ +#define TDA1997X_VP_OUT_EN 0x80 /* enable output group */ +#define TDA1997X_VP_HIZ 0x40 /* hi-Z output group when not used */ +#define TDA1997X_VP_SWP 0x10 /* pin-swap output group */ +#define TDA1997X_R_CR_CBCR_3_0 (0 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_R_CR_CBCR_7_4 (1 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_R_CR_CBCR_11_8 (2 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_B_CB_3_0 (3 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_B_CB_7_4 (4 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_B_CB_11_8 (5 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_G_Y_3_0 (6 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_G_Y_7_4 (7 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_G_Y_11_8 (8 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +/* pinswapped groups */ +#define TDA1997X_R_CR_CBCR_3_0_S (TDA1997X_R_CR_CBCR_3_0 | TDA1997X_VP_SWAP) +#define TDA1997X_R_CR_CBCR_7_4_S (TDA1997X_R_CR_CBCR_7_4 | TDA1997X_VP_SWAP) +#define TDA1997X_R_CR_CBCR_11_8_S (TDA1997X_R_CR_CBCR_11_8 | TDA1997X_VP_SWAP) +#define TDA1997X_B_CB_3_0_S (TDA1997X_B_CB_3_0 | TDA1997X_VP_SWAP) +#define TDA1997X_B_CB_7_4_S (TDA1997X_B_CB_7_4 | TDA1997X_VP_SWAP) +#define TDA1997X_B_CB_11_8_S (TDA1997X_B_CB_11_8 | TDA1997X_VP_SWAP) +#define TDA1997X_G_Y_3_0_S (TDA1997X_G_Y_3_0 | TDA1997X_VP_SWAP) +#define TDA1997X_G_Y_7_4_S (TDA1997X_G_Y_7_4 | TDA1997X_VP_SWAP) +#define TDA1997X_G_Y_11_8_S (TDA1997X_G_Y_11_8 | TDA1997X_VP_SWAP) + +/* Audio bus DAI format */ +#define TDA1997X_I2S16 1 /* I2S 16bit */ +#define TDA1997X_I2S32 2 /* I2S 32bit */ +#define TDA1997X_SPDIF 3 /* SPDIF */ +#define TDA1997X_OBA 4 /* One Bit Audio */ +#define TDA1997X_DST 5 /* Direct Stream Transfer */ +#define TDA1997X_I2S16_HBR 6 /* HBR straight in I2S 16bit mode */ +#define TDA1997X_I2S16_HBR_DEMUX 7 /* HBR demux in I2S 16bit mode */ +#define TDA1997X_I2S32_HBR_DEMUX 8 /* HBR demux in I2S 32bit mode */ +#define TDA1997X_SPDIF_HBR_DEMUX 9 /* HBR demux in SPDIF mode */ + +/* Audio bus channel layout */ +#define TDA1997X_LAYOUT0 0 /* 2-channel */ +#define TDA1997X_LAYOUT1 1 /* 8-channel */ + +/* Audio bus clock */ +#define TDA1997X_ACLK_16FS 0 +#define TDA1997X_ACLK_32FS 1 +#define TDA1997X_ACLK_64FS 2 +#define TDA1997X_ACLK_128FS 3 +#define TDA1997X_ACLK_256FS 4 +#define TDA1997X_ACLK_512FS 5 + +#endif /* _DT_BINDINGS_MEDIA_TDA1997X_H */ diff --git a/roms/u-boot/include/dt-bindings/memory/bcm-ns3-mc.h b/roms/u-boot/include/dt-bindings/memory/bcm-ns3-mc.h new file mode 100644 index 000000000..84795ec27 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/memory/bcm-ns3-mc.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Broadcom + */ + +#ifndef DT_BINDINGS_BCM_NS3_MC_H +#define DT_BINDINGS_BCM_NS3_MC_H + +/* + * +--------+----------+ 0x8b000000 + * | NITRO CRASH DUMP | 32MB + * +--------+----------+ 0x8d000000 + * | SHMEM (NS) | 16 MB + * +-------------------+ 0x8e000000 + * | | TEE_RAM(S)| 4MB + * + TZDRAM +----------+ 0x8e400000 + * | | TA_RAM(S) | 12MB + * +--------+----------+ 0x8f000000 + * | BL31 + TMON + LPM | + * | memory | 1MB + * +-------------------+ 0x8f100000 + */ + +#define BCM_NS3_MEM_NITRO_CRASH_START 0x8ae00000 +#define BCM_NS3_MEM_NITRO_CRASH_LEN 0x21fffff +#define BCM_NS3_MEM_NITRO_CRASH_SIZE 0x2200000 + +#define BCM_NS3_MEM_SHARE_START 0x8d000000 +#define BCM_NS3_MEM_SHARE_LEN 0x020fffff + +/* ATF/U-boot/Linux error logs */ +#define BCM_NS3_MEM_ELOG_START 0x8f113000 +#define BCM_NS3_MEM_ELOG_LEN 0x00100000 + +/* CRMU Page table memroy */ +#define BCM_NS3_MEM_CRMU_PT_START 0x880000000 +#define BCM_NS3_MEM_CRMU_PT_LEN 0x200000 + +/* default memory starting address and length */ +#define BCM_NS3_MEM_START 0x80000000UL +#define BCM_NS3_MEM_LEN 0x80000000UL +#define BCM_NS3_MEM_END (BCM_NS3_MEM_START + BCM_NS3_MEM_LEN) + +/* memory starting address and length for BANK_1 */ +#define BCM_NS3_BANK_1_MEM_START 0x880000000UL +#define BCM_NS3_BANK_1_MEM_LEN 0x180000000UL + +/* memory layout information */ +#define BCM_NS3_DDR_INFO_BASE 0x8f220000 +#define BCM_NS3_DDR_INFO_RSVD_LEN 0x1000 +#define BCM_NS3_DDR_INFO_LEN 73 +#define BCM_NS3_DDR_INFO_SIG 0x42434d44 +#define BCM_NS3_MAX_NR_BANKS 4 + +#define BCM_NS3_GIC_LPI_BASE 0x8ad70000 +#define BCM_NS3_MEM_RSVE_START BCM_NS3_GIC_LPI_BASE +#define BCM_NS3_MEM_RSVE_END ((BCM_NS3_MEM_ELOG_START + \ + BCM_NS3_MEM_ELOG_LEN) - \ + BCM_NS3_MEM_RSVE_START) + +#define BCM_NS3_CRMU_PGT_START 0x880000000UL +#define BCM_NS3_CRMU_PGT_SIZE 0x100000 +#endif diff --git a/roms/u-boot/include/dt-bindings/memory/imxrt-sdram.h b/roms/u-boot/include/dt-bindings/memory/imxrt-sdram.h new file mode 100644 index 000000000..acb35bce2 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/memory/imxrt-sdram.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#ifndef DT_BINDINGS_IMXRT_SDRAM_H +#define DT_BINDINGS_IMXRT_SDRAM_H + +#define MEM_SIZE_4K 0x00 +#define MEM_SIZE_8K 0x01 +#define MEM_SIZE_16K 0x02 +#define MEM_SIZE_32K 0x03 +#define MEM_SIZE_64K 0x04 +#define MEM_SIZE_128K 0x05 +#define MEM_SIZE_256K 0x06 +#define MEM_SIZE_512K 0x07 +#define MEM_SIZE_1M 0x08 +#define MEM_SIZE_2M 0x09 +#define MEM_SIZE_4M 0x0A +#define MEM_SIZE_8M 0x0B +#define MEM_SIZE_16M 0x0C +#define MEM_SIZE_32M 0x0D +#define MEM_SIZE_64M 0x0E +#define MEM_SIZE_128M 0x0F +#define MEM_SIZE_256M 0x10 +#define MEM_SIZE_512M 0x11 +#define MEM_SIZE_1G 0x12 +#define MEM_SIZE_2G 0x13 +#define MEM_SIZE_4G 0x14 + +#define MUX_A8_SDRAM_A8 0x0 +#define MUX_A8_NAND_CE 0x1 +#define MUX_A8_NOR_CE 0x2 +#define MUX_A8_PSRAM_CE 0x3 +#define MUX_A8_DBI_CSX 0x4 + +#define MUX_CSX0_NOR_PSRAM_A24 0x0 +#define MUX_CSX0_SDRAM_CS1 0x1 +#define MUX_CSX0_SDRAM_CS2 0x2 +#define MUX_CSX0_SDRAM_CS3 0x3 +#define MUX_CSX0_NAND_CE 0x4 +#define MUX_CSX0_NOR_CE 0x5 +#define MUX_CSX0_PSRAM_CE 0x6 +#define MUX_CSX0_DBI_CSX 0x7 + +#define MUX_CSX1_NOR_PSRAM_A25 0x0 +#define MUX_CSX1_SDRAM_CS1 0x1 +#define MUX_CSX1_SDRAM_CS2 0x2 +#define MUX_CSX1_SDRAM_CS3 0x3 +#define MUX_CSX1_NAND_CE 0x4 +#define MUX_CSX1_NOR_CE 0x5 +#define MUX_CSX1_PSRAM_CE 0x6 +#define MUX_CSX1_DBI_CSX 0x7 + +#define MUX_CSX2_NOR_PSRAM_A26 0x0 +#define MUX_CSX2_SDRAM_CS1 0x1 +#define MUX_CSX2_SDRAM_CS2 0x2 +#define MUX_CSX2_SDRAM_CS3 0x3 +#define MUX_CSX2_NAND_CE 0x4 +#define MUX_CSX2_NOR_CE 0x5 +#define MUX_CSX2_PSRAM_CE 0x6 +#define MUX_CSX2_DBI_CSX 0x7 + +#define MUX_CSX3_NOR_PSRAM_A27 0x0 +#define MUX_CSX3_SDRAM_CS1 0x1 +#define MUX_CSX3_SDRAM_CS2 0x2 +#define MUX_CSX3_SDRAM_CS3 0x3 +#define MUX_CSX3_NAND_CE 0x4 +#define MUX_CSX3_NOR_CE 0x5 +#define MUX_CSX3_PSRAM_CE 0x6 +#define MUX_CSX3_DBI_CSX 0x7 + +#define MUX_RDY_NAND_RDY_WAIT 0x0 +#define MUX_RDY_SDRAM_CS1 0x1 +#define MUX_RDY_SDRAM_CS2 0x2 +#define MUX_RDY_SDRAM_CS3 0x3 +#define MUX_RDY_NOR_CE 0x4 +#define MUX_RDY_PSRAM_CE 0x5 +#define MUX_RDY_DBI_CSX 0x6 +#define MUX_RDY_NOR_PSRAM_A27 0x7 + +#define MEM_WIDTH_8BITS 0x0 +#define MEM_WIDTH_16BITS 0x1 + +#define BL_1 0x0 +#define BL_2 0x1 +#define BL_4 0x2 +#define BL_8 0x3 + +#define COL_12BITS 0x0 +#define COL_11BITS 0x1 +#define COL_10BITS 0x2 +#define COL_9BITS 0x3 + +#define CL_1 0x0 +#define CL_2 0x2 +#define CL_3 0x3 + +#endif diff --git a/roms/u-boot/include/dt-bindings/memory/mpc83xx-sdram.h b/roms/u-boot/include/dt-bindings/memory/mpc83xx-sdram.h new file mode 100644 index 000000000..7d4ce01cc --- /dev/null +++ b/roms/u-boot/include/dt-bindings/memory/mpc83xx-sdram.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#ifndef DT_BINDINGS_MPC83XX_SDRAM_H +#define DT_BINDINGS_MPC83XX_SDRAM_H + +/* DDR Control Driver register */ + +#define DSO_DISABLE 0 +#define DSO_ENABLE 1 + +#define DSO_P_IMPEDANCE_HIGHEST_Z 0x0 +#define DSO_P_IMPEDANCE_MUCH_HIGHER_Z 0x8 +#define DSO_P_IMPEDANCE_HIGHER_Z 0xC +#define DSO_P_IMPEDANCE_NOMINAL 0xE +#define DSO_P_IMPEDANCE_LOWER_Z 0xF + +#define DSO_N_IMPEDANCE_HIGHEST_Z 0x0 +#define DSO_N_IMPEDANCE_MUCH_HIGHER_Z 0x8 +#define DSO_N_IMPEDANCE_HIGHER_Z 0xC +#define DSO_N_IMPEDANCE_NOMINAL 0xE +#define DSO_N_IMPEDANCE_LOWER_Z 0xF + +#define ODT_TERMINATION_75_OHM 0 +#define ODT_TERMINATION_150_OHM 1 + +#define DDR_TYPE_DDR2_1_8_VOLT 0 +#define DDR_TYPE_DDR1_2_5_VOLT 1 + +#define MVREF_SEL_EXTERNAL 0 +#define MVREF_SEL_INTERNAL_GVDD 1 + +#define M_ODR_ENABLE 0 +#define M_ODR_DISABLE 1 + +/* CS config register */ + +#define AUTO_PRECHARGE_ENABLE 0x00800000 +#define AUTO_PRECHARGE_DISABLE 0x00000000 + +#define ODT_RD_NEVER 0x00000000 +#define ODT_RD_ONLY_CURRENT 0x00100000 +#define ODT_RD_ONLY_OTHER_CS 0x00200000 +#define ODT_RD_ONLY_OTHER_DIMM 0x00300000 +#define ODT_RD_ALL 0x00400000 + +#define ODT_WR_NEVER 0x00000000 +#define ODT_WR_ONLY_CURRENT 0x00010000 +#define ODT_WR_ONLY_OTHER_CS 0x00020000 +#define ODT_WR_ONLY_OTHER_DIMM 0x00030000 +#define ODT_WR_ALL 0x00040000 + +/* DDR SDRAM Clock Control register */ + +#define CLOCK_ADJUST_025 0x01000000 +#define CLOCK_ADJUST_05 0x02000000 +#define CLOCK_ADJUST_075 0x03000000 +#define CLOCK_ADJUST_1 0x04000000 + +#define CASLAT_20 0x3 /* CAS latency = 2.0 */ +#define CASLAT_25 0x4 /* CAS latency = 2.5 */ +#define CASLAT_30 0x5 /* CAS latency = 3.0 */ +#define CASLAT_35 0x6 /* CAS latency = 3.5 */ +#define CASLAT_40 0x7 /* CAS latency = 4.0 */ +#define CASLAT_45 0x8 /* CAS latency = 4.5 */ +#define CASLAT_50 0x9 /* CAS latency = 5.0 */ +#define CASLAT_55 0xa /* CAS latency = 5.5 */ +#define CASLAT_60 0xb /* CAS latency = 6.0 */ +#define CASLAT_65 0xc /* CAS latency = 6.5 */ +#define CASLAT_70 0xd /* CAS latency = 7.0 */ +#define CASLAT_75 0xe /* CAS latency = 7.5 */ +#define CASLAT_80 0xf /* CAS latency = 8.0 */ + +/* DDR SDRAM Timing Configuration 2 register */ + +#define READ_LAT_PLUS_1 0x0 +#define READ_LAT 0x2 +#define READ_LAT_PLUS_1_4 0x3 +#define READ_LAT_PLUS_1_2 0x4 +#define READ_LAT_PLUS_3_4 0x5 +#define READ_LAT_PLUS_5_4 0x7 +#define READ_LAT_PLUS_3_2 0x8 +#define READ_LAT_PLUS_7_4 0x9 +#define READ_LAT_PLUS_2 0xA +#define READ_LAT_PLUS_9_4 0xB +#define READ_LAT_PLUS_5_2 0xC +#define READ_LAT_PLUS_11_4 0xD +#define READ_LAT_PLUS_3 0xE +#define READ_LAT_PLUS_13_4 0xF +#define READ_LAT_PLUS_7_2 0x10 +#define READ_LAT_PLUS_15_4 0x11 +#define READ_LAT_PLUS_4 0x12 +#define READ_LAT_PLUS_17_4 0x13 +#define READ_LAT_PLUS_9_2 0x14 +#define READ_LAT_PLUS_19_4 0x15 + +#define CLOCK_DELAY_0 0x0 +#define CLOCK_DELAY_1_4 0x1 +#define CLOCK_DELAY_1_2 0x2 +#define CLOCK_DELAY_3_4 0x3 +#define CLOCK_DELAY_1 0x4 +#define CLOCK_DELAY_5_4 0x5 +#define CLOCK_DELAY_3_2 0x6 + +/* DDR SDRAM Control Configuration */ + +#define SREN_DISABLE 0x0 +#define SREN_ENABLE 0x1 + +#define ECC_DISABLE 0x0 +#define ECC_ENABLE 0x1 + +#define RD_DISABLE 0x0 +#define RD_ENABLE 0x1 + +#define TYPE_DDR1 0x2 +#define TYPE_DDR2 0x3 + +#define DYN_PWR_DISABLE 0x0 +#define DYN_PWR_ENABLE 0x1 + +#define DATA_BUS_WIDTH_16 0x1 +#define DATA_BUS_WIDTH_32 0x2 + +#define NCAP_DISABLE 0x0 +#define NCAP_ENABLE 0x1 + +#define TIMING_1T 0x0 +#define TIMING_2T 0x1 + +#define INTERLEAVE_NONE 0x0 +#define INTERLEAVE_1_AND_2 0x1 + +#define PRECHARGE_MA_10 0x0 +#define PRECHARGE_MA_8 0x1 + +#define STRENGTH_FULL 0x0 +#define STRENGTH_HALF 0x1 + +#define INITIALIZATION_DONT_BYPASS 0x0 +#define INITIALIZATION_BYPASS 0x1 + +/* DDR SDRAM Control Configuration 2 register */ + +#define MODE_NORMAL 0x0 +#define MODE_REFRESH 0x1 + +#define DLL_RESET_ENABLE 0x0 +#define DLL_RESET_DISABLE 0x1 + +#define DQS_TRUE 0x0 + +#define ODT_ASSERT_NEVER 0x0 +#define ODT_ASSERT_WRITES 0x1 +#define ODT_ASSERT_READS 0x2 +#define ODT_ASSERT_ALWAYS 0x3 + +#endif diff --git a/roms/u-boot/include/dt-bindings/memory/rk3368-dmc.h b/roms/u-boot/include/dt-bindings/memory/rk3368-dmc.h new file mode 100644 index 000000000..b06ffde71 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/memory/rk3368-dmc.h @@ -0,0 +1,30 @@ +#ifndef DT_BINDINGS_RK3368_DMC_H +#define DT_BINDINGS_RK3368_DMC_H + +#define DMC_MSCH_CBDR 0x0 +#define DMC_MSCH_CBRD 0x1 +#define DMC_MSCH_CRBD 0x2 + +#define DDR3_800D 0 +#define DDR3_800E 1 +#define DDR3_1066E 2 +#define DDR3_1066F 3 +#define DDR3_1066G 4 +#define DDR3_1333F 5 +#define DDR3_1333G 6 +#define DDR3_1333H 7 +#define DDR3_1333J 8 +#define DDR3_1600G 9 +#define DDR3_1600H 10 +#define DDR3_1600J 11 +#define DDR3_1600K 12 +#define DDR3_1866J 13 +#define DDR3_1866K 14 +#define DDR3_1866L 15 +#define DDR3_1866M 16 +#define DDR3_2133K 17 +#define DDR3_2133L 18 +#define DDR3_2133M 19 +#define DDR3_2133N 20 + +#endif diff --git a/roms/u-boot/include/dt-bindings/memory/stm32-sdram.h b/roms/u-boot/include/dt-bindings/memory/stm32-sdram.h new file mode 100644 index 000000000..90ef2e159 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/memory/stm32-sdram.h @@ -0,0 +1,48 @@ +#ifndef DT_BINDINGS_STM32_SDRAM_H +#define DT_BINDINGS_STM32_SDRAM_H + +#define NO_COL_8 0x0 +#define NO_COL_9 0x1 +#define NO_COL_10 0x2 +#define NO_COL_11 0x3 + +#define NO_ROW_11 0x0 +#define NO_ROW_12 0x1 +#define NO_ROW_13 0x2 + +#define MWIDTH_8 0x0 +#define MWIDTH_16 0x1 +#define MWIDTH_32 0x2 +#define BANKS_2 0x0 +#define BANKS_4 0x1 +#define CAS_1 0x1 +#define CAS_2 0x2 +#define CAS_3 0x3 +#define SDCLK_DIS 0x0 +#define SDCLK_2 0x2 +#define SDCLK_3 0x3 +#define RD_BURST_EN 0x1 +#define RD_BURST_DIS 0x0 +#define RD_PIPE_DL_0 0x0 +#define RD_PIPE_DL_1 0x1 +#define RD_PIPE_DL_2 0x2 + +/* Timing = value +1 cycles */ +#define TMRD_1 (1 - 1) +#define TMRD_2 (2 - 1) +#define TMRD_3 (3 - 1) +#define TXSR_1 (1 - 1) +#define TXSR_6 (6 - 1) +#define TXSR_7 (7 - 1) +#define TXSR_8 (8 - 1) +#define TRAS_1 (1 - 1) +#define TRAS_4 (4 - 1) +#define TRAS_6 (6 - 1) +#define TRC_6 (6 - 1) +#define TWR_1 (1 - 1) +#define TWR_2 (2 - 1) +#define TRP_2 (2 - 1) +#define TRCD_1 (1 - 1) +#define TRCD_2 (2 - 1) + +#endif diff --git a/roms/u-boot/include/dt-bindings/memory/tegra114-mc.h b/roms/u-boot/include/dt-bindings/memory/tegra114-mc.h new file mode 100644 index 000000000..8f48985a3 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/memory/tegra114-mc.h @@ -0,0 +1,25 @@ +#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H +#define DT_BINDINGS_MEMORY_TEGRA114_MC_H + +#define TEGRA_SWGROUP_PTC 0 +#define TEGRA_SWGROUP_DC 1 +#define TEGRA_SWGROUP_DCB 2 +#define TEGRA_SWGROUP_EPP 3 +#define TEGRA_SWGROUP_G2 4 +#define TEGRA_SWGROUP_AVPC 5 +#define TEGRA_SWGROUP_NV 6 +#define TEGRA_SWGROUP_HDA 7 +#define TEGRA_SWGROUP_HC 8 +#define TEGRA_SWGROUP_MSENC 9 +#define TEGRA_SWGROUP_PPCS 10 +#define TEGRA_SWGROUP_VDE 11 +#define TEGRA_SWGROUP_MPCORELP 12 +#define TEGRA_SWGROUP_MPCORE 13 +#define TEGRA_SWGROUP_VI 14 +#define TEGRA_SWGROUP_ISP 15 +#define TEGRA_SWGROUP_XUSB_HOST 16 +#define TEGRA_SWGROUP_XUSB_DEV 17 +#define TEGRA_SWGROUP_EMUCIF 18 +#define TEGRA_SWGROUP_TSEC 19 + +#endif diff --git a/roms/u-boot/include/dt-bindings/memory/tegra124-mc.h b/roms/u-boot/include/dt-bindings/memory/tegra124-mc.h new file mode 100644 index 000000000..7d8ee798f --- /dev/null +++ b/roms/u-boot/include/dt-bindings/memory/tegra124-mc.h @@ -0,0 +1,31 @@ +#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H +#define DT_BINDINGS_MEMORY_TEGRA124_MC_H + +#define TEGRA_SWGROUP_PTC 0 +#define TEGRA_SWGROUP_DC 1 +#define TEGRA_SWGROUP_DCB 2 +#define TEGRA_SWGROUP_AFI 3 +#define TEGRA_SWGROUP_AVPC 4 +#define TEGRA_SWGROUP_HDA 5 +#define TEGRA_SWGROUP_HC 6 +#define TEGRA_SWGROUP_MSENC 7 +#define TEGRA_SWGROUP_PPCS 8 +#define TEGRA_SWGROUP_SATA 9 +#define TEGRA_SWGROUP_VDE 10 +#define TEGRA_SWGROUP_MPCORELP 11 +#define TEGRA_SWGROUP_MPCORE 12 +#define TEGRA_SWGROUP_ISP2 13 +#define TEGRA_SWGROUP_XUSB_HOST 14 +#define TEGRA_SWGROUP_XUSB_DEV 15 +#define TEGRA_SWGROUP_ISP2B 16 +#define TEGRA_SWGROUP_TSEC 17 +#define TEGRA_SWGROUP_A9AVP 18 +#define TEGRA_SWGROUP_GPU 19 +#define TEGRA_SWGROUP_SDMMC1A 20 +#define TEGRA_SWGROUP_SDMMC2A 21 +#define TEGRA_SWGROUP_SDMMC3A 22 +#define TEGRA_SWGROUP_SDMMC4A 23 +#define TEGRA_SWGROUP_VIC 24 +#define TEGRA_SWGROUP_VI 25 + +#endif diff --git a/roms/u-boot/include/dt-bindings/memory/tegra210-mc.h b/roms/u-boot/include/dt-bindings/memory/tegra210-mc.h new file mode 100644 index 000000000..d1731bc14 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/memory/tegra210-mc.h @@ -0,0 +1,36 @@ +#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H +#define DT_BINDINGS_MEMORY_TEGRA210_MC_H + +#define TEGRA_SWGROUP_PTC 0 +#define TEGRA_SWGROUP_DC 1 +#define TEGRA_SWGROUP_DCB 2 +#define TEGRA_SWGROUP_AFI 3 +#define TEGRA_SWGROUP_AVPC 4 +#define TEGRA_SWGROUP_HDA 5 +#define TEGRA_SWGROUP_HC 6 +#define TEGRA_SWGROUP_NVENC 7 +#define TEGRA_SWGROUP_PPCS 8 +#define TEGRA_SWGROUP_SATA 9 +#define TEGRA_SWGROUP_MPCORE 10 +#define TEGRA_SWGROUP_ISP2 11 +#define TEGRA_SWGROUP_XUSB_HOST 12 +#define TEGRA_SWGROUP_XUSB_DEV 13 +#define TEGRA_SWGROUP_ISP2B 14 +#define TEGRA_SWGROUP_TSEC 15 +#define TEGRA_SWGROUP_A9AVP 16 +#define TEGRA_SWGROUP_GPU 17 +#define TEGRA_SWGROUP_SDMMC1A 18 +#define TEGRA_SWGROUP_SDMMC2A 19 +#define TEGRA_SWGROUP_SDMMC3A 20 +#define TEGRA_SWGROUP_SDMMC4A 21 +#define TEGRA_SWGROUP_VIC 22 +#define TEGRA_SWGROUP_VI 23 +#define TEGRA_SWGROUP_NVDEC 24 +#define TEGRA_SWGROUP_APE 25 +#define TEGRA_SWGROUP_NVJPG 26 +#define TEGRA_SWGROUP_SE 27 +#define TEGRA_SWGROUP_AXIAP 28 +#define TEGRA_SWGROUP_ETR 29 +#define TEGRA_SWGROUP_TSECB 30 + +#endif diff --git a/roms/u-boot/include/dt-bindings/memory/tegra30-mc.h b/roms/u-boot/include/dt-bindings/memory/tegra30-mc.h new file mode 100644 index 000000000..502beb03d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/memory/tegra30-mc.h @@ -0,0 +1,24 @@ +#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H +#define DT_BINDINGS_MEMORY_TEGRA30_MC_H + +#define TEGRA_SWGROUP_PTC 0 +#define TEGRA_SWGROUP_DC 1 +#define TEGRA_SWGROUP_DCB 2 +#define TEGRA_SWGROUP_EPP 3 +#define TEGRA_SWGROUP_G2 4 +#define TEGRA_SWGROUP_MPE 5 +#define TEGRA_SWGROUP_VI 6 +#define TEGRA_SWGROUP_AFI 7 +#define TEGRA_SWGROUP_AVPC 8 +#define TEGRA_SWGROUP_NV 9 +#define TEGRA_SWGROUP_NV2 10 +#define TEGRA_SWGROUP_HDA 11 +#define TEGRA_SWGROUP_HC 12 +#define TEGRA_SWGROUP_PPCS 13 +#define TEGRA_SWGROUP_SATA 14 +#define TEGRA_SWGROUP_VDE 15 +#define TEGRA_SWGROUP_MPCORELP 16 +#define TEGRA_SWGROUP_MPCORE 17 +#define TEGRA_SWGROUP_ISP 18 + +#endif diff --git a/roms/u-boot/include/dt-bindings/mfd/dbx500-prcmu.h b/roms/u-boot/include/dt-bindings/mfd/dbx500-prcmu.h new file mode 100644 index 000000000..0404bcc47 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/mfd/dbx500-prcmu.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for the PRCMU bindings. + * + */ + +#ifndef _DT_BINDINGS_MFD_PRCMU_H +#define _DT_BINDINGS_MFD_PRCMU_H + +/* + * Clock identifiers. + */ +#define ARMCLK 0 +#define PRCMU_ACLK 1 +#define PRCMU_SVAMMCSPCLK 2 +#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */ +#define PRCMU_SIACLK 3 +#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */ +#define PRCMU_SGACLK 4 +#define PRCMU_UARTCLK 5 +#define PRCMU_MSP02CLK 6 +#define PRCMU_MSP1CLK 7 +#define PRCMU_I2CCLK 8 +#define PRCMU_SDMMCCLK 9 +#define PRCMU_SLIMCLK 10 +#define PRCMU_CAMCLK 10 /* DBx540 only. */ +#define PRCMU_PER1CLK 11 +#define PRCMU_PER2CLK 12 +#define PRCMU_PER3CLK 13 +#define PRCMU_PER5CLK 14 +#define PRCMU_PER6CLK 15 +#define PRCMU_PER7CLK 16 +#define PRCMU_LCDCLK 17 +#define PRCMU_BMLCLK 18 +#define PRCMU_HSITXCLK 19 +#define PRCMU_HSIRXCLK 20 +#define PRCMU_HDMICLK 21 +#define PRCMU_APEATCLK 22 +#define PRCMU_APETRACECLK 23 +#define PRCMU_MCDECLK 24 +#define PRCMU_IPI2CCLK 25 +#define PRCMU_DSIALTCLK 26 +#define PRCMU_DMACLK 27 +#define PRCMU_B2R2CLK 28 +#define PRCMU_TVCLK 29 +#define SPARE_UNIPROCLK 30 +#define PRCMU_SSPCLK 31 +#define PRCMU_RNGCLK 32 +#define PRCMU_UICCCLK 33 +#define PRCMU_G1CLK 34 /* DBx540 only. */ +#define PRCMU_HVACLK 35 /* DBx540 only. */ +#define PRCMU_SPARE1CLK 36 +#define PRCMU_SPARE2CLK 37 + +#define PRCMU_NUM_REG_CLOCKS 38 + +#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS +#define PRCMU_SYSCLK 39 +#define PRCMU_CDCLK 40 +#define PRCMU_TIMCLK 41 +#define PRCMU_PLLSOC0 42 +#define PRCMU_PLLSOC1 43 +#define PRCMU_ARMSS 44 +#define PRCMU_PLLDDR 45 + +/* DSI Clocks */ +#define PRCMU_PLLDSI 46 +#define PRCMU_DSI0CLK 47 +#define PRCMU_DSI1CLK 48 +#define PRCMU_DSI0ESCCLK 49 +#define PRCMU_DSI1ESCCLK 50 +#define PRCMU_DSI2ESCCLK 51 + +/* LCD DSI PLL - Ux540 only */ +#define PRCMU_PLLDSI_LCD 52 +#define PRCMU_DSI0CLK_LCD 53 +#define PRCMU_DSI1CLK_LCD 54 +#define PRCMU_DSI0ESCCLK_LCD 55 +#define PRCMU_DSI1ESCCLK_LCD 56 +#define PRCMU_DSI2ESCCLK_LCD 57 + +#define PRCMU_NUM_CLKS 58 + +#endif diff --git a/roms/u-boot/include/dt-bindings/mfd/k210-sysctl.h b/roms/u-boot/include/dt-bindings/mfd/k210-sysctl.h new file mode 100644 index 000000000..bfc918d3b --- /dev/null +++ b/roms/u-boot/include/dt-bindings/mfd/k210-sysctl.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Sean Anderson + */ + +#ifndef K210_SYSCTL_H +#define K210_SYSCTL_H + +/* Taken from kendryte-standalone-sdk/lib/drivers/include/sysctl.h */ +#define K210_SYSCTL_GIT_ID 0x00 /* Git short commit id */ +#define K210_SYSCTL_UART_BAUD 0x04 /* Default UARTHS baud rate */ +#define K210_SYSCTL_PLL0 0x08 /* PLL0 controller */ +#define K210_SYSCTL_PLL1 0x0C /* PLL1 controller */ +#define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */ +#define K210_SYSCTL_PLL_LOCK 0x18 /* PLL lock tester */ +#define K210_SYSCTL_ROM_ERROR 0x1C /* AXI ROM detector */ +#define K210_SYSCTL_SEL0 0x20 /* Clock select controller 0 */ +#define K210_SYSCTL_SEL1 0x24 /* Clock select controller 1 */ +#define K210_SYSCTL_EN_CENT 0x28 /* Central clock enable */ +#define K210_SYSCTL_EN_PERI 0x2C /* Peripheral clock enable */ +#define K210_SYSCTL_SOFT_RESET 0x30 /* Soft reset ctrl */ +#define K210_SYSCTL_PERI_RESET 0x34 /* Peripheral reset controller */ +#define K210_SYSCTL_THR0 0x38 /* Clock threshold controller 0 */ +#define K210_SYSCTL_THR1 0x3C /* Clock threshold controller 1 */ +#define K210_SYSCTL_THR2 0x40 /* Clock threshold controller 2 */ +#define K210_SYSCTL_THR3 0x44 /* Clock threshold controller 3 */ +#define K210_SYSCTL_THR4 0x48 /* Clock threshold controller 4 */ +#define K210_SYSCTL_THR5 0x4C /* Clock threshold controller 5 */ +#define K210_SYSCTL_THR6 0x50 /* Clock threshold controller 6 */ +#define K210_SYSCTL_MISC 0x54 /* Miscellaneous controller */ +#define K210_SYSCTL_PERI 0x58 /* Peripheral controller */ +#define K210_SYSCTL_SPI_SLEEP 0x5C /* SPI sleep controller */ +#define K210_SYSCTL_RESET_STAT 0x60 /* Reset source status */ +#define K210_SYSCTL_DMA_SEL0 0x64 /* DMA handshake selector 0 */ +#define K210_SYSCTL_DMA_SEL1 0x68 /* DMA handshake selector 1 */ +#define K210_SYSCTL_POWER_SEL 0x6C /* IO Power Mode Select controller */ + +#endif /* K210_SYSCTL_H */ diff --git a/roms/u-boot/include/dt-bindings/mfd/st,stpmic1.h b/roms/u-boot/include/dt-bindings/mfd/st,stpmic1.h new file mode 100644 index 000000000..321cd0879 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/mfd/st,stpmic1.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Philippe Peurichard , + * Pascal Paillet for STMicroelectronics. + */ + +#ifndef __DT_BINDINGS_STPMIC1_H__ +#define __DT_BINDINGS_STPMIC1_H__ + +/* IRQ definitions */ +#define IT_PONKEY_F 0 +#define IT_PONKEY_R 1 +#define IT_WAKEUP_F 2 +#define IT_WAKEUP_R 3 +#define IT_VBUS_OTG_F 4 +#define IT_VBUS_OTG_R 5 +#define IT_SWOUT_F 6 +#define IT_SWOUT_R 7 + +#define IT_CURLIM_BUCK1 8 +#define IT_CURLIM_BUCK2 9 +#define IT_CURLIM_BUCK3 10 +#define IT_CURLIM_BUCK4 11 +#define IT_OCP_OTG 12 +#define IT_OCP_SWOUT 13 +#define IT_OCP_BOOST 14 +#define IT_OVP_BOOST 15 + +#define IT_CURLIM_LDO1 16 +#define IT_CURLIM_LDO2 17 +#define IT_CURLIM_LDO3 18 +#define IT_CURLIM_LDO4 19 +#define IT_CURLIM_LDO5 20 +#define IT_CURLIM_LDO6 21 +#define IT_SHORT_SWOTG 22 +#define IT_SHORT_SWOUT 23 + +#define IT_TWARN_F 24 +#define IT_TWARN_R 25 +#define IT_VINLOW_F 26 +#define IT_VINLOW_R 27 +#define IT_SWIN_F 30 +#define IT_SWIN_R 31 + +/* BUCK MODES definitions */ +#define STPMIC1_BUCK_MODE_NORMAL 0 +#define STPMIC1_BUCK_MODE_LP 2 + +#endif /* __DT_BINDINGS_STPMIC1_H__ */ diff --git a/roms/u-boot/include/dt-bindings/mfd/st-lpc.h b/roms/u-boot/include/dt-bindings/mfd/st-lpc.h new file mode 100644 index 000000000..d05894afa --- /dev/null +++ b/roms/u-boot/include/dt-bindings/mfd/st-lpc.h @@ -0,0 +1,16 @@ +/* + * This header provides shared DT/Driver defines for ST's LPC device + * + * Copyright (C) 2014 STMicroelectronics -- All Rights Reserved + * + * Author: Lee Jones for STMicroelectronics + */ + +#ifndef __DT_BINDINGS_ST_LPC_H__ +#define __DT_BINDINGS_ST_LPC_H__ + +#define ST_LPC_MODE_RTC 0 +#define ST_LPC_MODE_WDT 1 +#define ST_LPC_MODE_CLKSRC 2 + +#endif /* __DT_BINDINGS_ST_LPC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/mfd/stm32f4-rcc.h b/roms/u-boot/include/dt-bindings/mfd/stm32f4-rcc.h new file mode 100644 index 000000000..36448a561 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/mfd/stm32f4-rcc.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for the STM32F4 RCC IP + */ + +#ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H +#define _DT_BINDINGS_MFD_STM32F4_RCC_H + +/* AHB1 */ +#define STM32F4_RCC_AHB1_GPIOA 0 +#define STM32F4_RCC_AHB1_GPIOB 1 +#define STM32F4_RCC_AHB1_GPIOC 2 +#define STM32F4_RCC_AHB1_GPIOD 3 +#define STM32F4_RCC_AHB1_GPIOE 4 +#define STM32F4_RCC_AHB1_GPIOF 5 +#define STM32F4_RCC_AHB1_GPIOG 6 +#define STM32F4_RCC_AHB1_GPIOH 7 +#define STM32F4_RCC_AHB1_GPIOI 8 +#define STM32F4_RCC_AHB1_GPIOJ 9 +#define STM32F4_RCC_AHB1_GPIOK 10 +#define STM32F4_RCC_AHB1_CRC 12 +#define STM32F4_RCC_AHB1_BKPSRAM 18 +#define STM32F4_RCC_AHB1_CCMDATARAM 20 +#define STM32F4_RCC_AHB1_DMA1 21 +#define STM32F4_RCC_AHB1_DMA2 22 +#define STM32F4_RCC_AHB1_DMA2D 23 +#define STM32F4_RCC_AHB1_ETHMAC 25 +#define STM32F4_RCC_AHB1_ETHMACTX 26 +#define STM32F4_RCC_AHB1_ETHMACRX 27 +#define STM32F4_RCC_AHB1_ETHMACPTP 28 +#define STM32F4_RCC_AHB1_OTGHS 29 +#define STM32F4_RCC_AHB1_OTGHSULPI 30 + +#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) +#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) + +/* AHB2 */ +#define STM32F4_RCC_AHB2_DCMI 0 +#define STM32F4_RCC_AHB2_CRYP 4 +#define STM32F4_RCC_AHB2_HASH 5 +#define STM32F4_RCC_AHB2_RNG 6 +#define STM32F4_RCC_AHB2_OTGFS 7 + +#define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) +#define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) + +/* AHB3 */ +#define STM32F4_RCC_AHB3_FMC 0 +#define STM32F4_RCC_AHB3_QSPI 1 + +#define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) +#define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) + +/* APB1 */ +#define STM32F4_RCC_APB1_TIM2 0 +#define STM32F4_RCC_APB1_TIM3 1 +#define STM32F4_RCC_APB1_TIM4 2 +#define STM32F4_RCC_APB1_TIM5 3 +#define STM32F4_RCC_APB1_TIM6 4 +#define STM32F4_RCC_APB1_TIM7 5 +#define STM32F4_RCC_APB1_TIM12 6 +#define STM32F4_RCC_APB1_TIM13 7 +#define STM32F4_RCC_APB1_TIM14 8 +#define STM32F4_RCC_APB1_WWDG 11 +#define STM32F4_RCC_APB1_SPI2 14 +#define STM32F4_RCC_APB1_SPI3 15 +#define STM32F4_RCC_APB1_UART2 17 +#define STM32F4_RCC_APB1_UART3 18 +#define STM32F4_RCC_APB1_UART4 19 +#define STM32F4_RCC_APB1_UART5 20 +#define STM32F4_RCC_APB1_I2C1 21 +#define STM32F4_RCC_APB1_I2C2 22 +#define STM32F4_RCC_APB1_I2C3 23 +#define STM32F4_RCC_APB1_CAN1 25 +#define STM32F4_RCC_APB1_CAN2 26 +#define STM32F4_RCC_APB1_PWR 28 +#define STM32F4_RCC_APB1_DAC 29 +#define STM32F4_RCC_APB1_UART7 30 +#define STM32F4_RCC_APB1_UART8 31 + +#define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) +#define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) + +/* APB2 */ +#define STM32F4_RCC_APB2_TIM1 0 +#define STM32F4_RCC_APB2_TIM8 1 +#define STM32F4_RCC_APB2_USART1 4 +#define STM32F4_RCC_APB2_USART6 5 +#define STM32F4_RCC_APB2_ADC1 8 +#define STM32F4_RCC_APB2_ADC2 9 +#define STM32F4_RCC_APB2_ADC3 10 +#define STM32F4_RCC_APB2_SDIO 11 +#define STM32F4_RCC_APB2_SPI1 12 +#define STM32F4_RCC_APB2_SPI4 13 +#define STM32F4_RCC_APB2_SYSCFG 14 +#define STM32F4_RCC_APB2_TIM9 16 +#define STM32F4_RCC_APB2_TIM10 17 +#define STM32F4_RCC_APB2_TIM11 18 +#define STM32F4_RCC_APB2_SPI5 20 +#define STM32F4_RCC_APB2_SPI6 21 +#define STM32F4_RCC_APB2_SAI1 22 +#define STM32F4_RCC_APB2_LTDC 26 +#define STM32F4_RCC_APB2_DSI 27 + +#define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) +#define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) + +#endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */ diff --git a/roms/u-boot/include/dt-bindings/mfd/stm32f7-rcc.h b/roms/u-boot/include/dt-bindings/mfd/stm32f7-rcc.h new file mode 100644 index 000000000..ba5cb7456 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/mfd/stm32f7-rcc.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for the STM32F7 RCC IP + */ + +#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H +#define _DT_BINDINGS_MFD_STM32F7_RCC_H + +/* AHB1 */ +#define STM32F7_RCC_AHB1_GPIOA 0 +#define STM32F7_RCC_AHB1_GPIOB 1 +#define STM32F7_RCC_AHB1_GPIOC 2 +#define STM32F7_RCC_AHB1_GPIOD 3 +#define STM32F7_RCC_AHB1_GPIOE 4 +#define STM32F7_RCC_AHB1_GPIOF 5 +#define STM32F7_RCC_AHB1_GPIOG 6 +#define STM32F7_RCC_AHB1_GPIOH 7 +#define STM32F7_RCC_AHB1_GPIOI 8 +#define STM32F7_RCC_AHB1_GPIOJ 9 +#define STM32F7_RCC_AHB1_GPIOK 10 +#define STM32F7_RCC_AHB1_CRC 12 +#define STM32F7_RCC_AHB1_BKPSRAM 18 +#define STM32F7_RCC_AHB1_DTCMRAM 20 +#define STM32F7_RCC_AHB1_DMA1 21 +#define STM32F7_RCC_AHB1_DMA2 22 +#define STM32F7_RCC_AHB1_DMA2D 23 +#define STM32F7_RCC_AHB1_ETHMAC 25 +#define STM32F7_RCC_AHB1_ETHMACTX 26 +#define STM32F7_RCC_AHB1_ETHMACRX 27 +#define STM32FF_RCC_AHB1_ETHMACPTP 28 +#define STM32F7_RCC_AHB1_OTGHS 29 +#define STM32F7_RCC_AHB1_OTGHSULPI 30 + +#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) +#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) + + +/* AHB2 */ +#define STM32F7_RCC_AHB2_DCMI 0 +#define STM32F7_RCC_AHB2_CRYP 4 +#define STM32F7_RCC_AHB2_HASH 5 +#define STM32F7_RCC_AHB2_RNG 6 +#define STM32F7_RCC_AHB2_OTGFS 7 + +#define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) +#define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) + +/* AHB3 */ +#define STM32F7_RCC_AHB3_FMC 0 +#define STM32F7_RCC_AHB3_QSPI 1 + +#define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) +#define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) + +/* APB1 */ +#define STM32F7_RCC_APB1_TIM2 0 +#define STM32F7_RCC_APB1_TIM3 1 +#define STM32F7_RCC_APB1_TIM4 2 +#define STM32F7_RCC_APB1_TIM5 3 +#define STM32F7_RCC_APB1_TIM6 4 +#define STM32F7_RCC_APB1_TIM7 5 +#define STM32F7_RCC_APB1_TIM12 6 +#define STM32F7_RCC_APB1_TIM13 7 +#define STM32F7_RCC_APB1_TIM14 8 +#define STM32F7_RCC_APB1_LPTIM1 9 +#define STM32F7_RCC_APB1_WWDG 11 +#define STM32F7_RCC_APB1_SPI2 14 +#define STM32F7_RCC_APB1_SPI3 15 +#define STM32F7_RCC_APB1_SPDIFRX 16 +#define STM32F7_RCC_APB1_UART2 17 +#define STM32F7_RCC_APB1_UART3 18 +#define STM32F7_RCC_APB1_UART4 19 +#define STM32F7_RCC_APB1_UART5 20 +#define STM32F7_RCC_APB1_I2C1 21 +#define STM32F7_RCC_APB1_I2C2 22 +#define STM32F7_RCC_APB1_I2C3 23 +#define STM32F7_RCC_APB1_I2C4 24 +#define STM32F7_RCC_APB1_CAN1 25 +#define STM32F7_RCC_APB1_CAN2 26 +#define STM32F7_RCC_APB1_CEC 27 +#define STM32F7_RCC_APB1_PWR 28 +#define STM32F7_RCC_APB1_DAC 29 +#define STM32F7_RCC_APB1_UART7 30 +#define STM32F7_RCC_APB1_UART8 31 + +#define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) +#define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80) + +/* APB2 */ +#define STM32F7_RCC_APB2_TIM1 0 +#define STM32F7_RCC_APB2_TIM8 1 +#define STM32F7_RCC_APB2_USART1 4 +#define STM32F7_RCC_APB2_USART6 5 +#define STM32F7_RCC_APB2_SDMMC2 7 +#define STM32F7_RCC_APB2_ADC1 8 +#define STM32F7_RCC_APB2_ADC2 9 +#define STM32F7_RCC_APB2_ADC3 10 +#define STM32F7_RCC_APB2_SDMMC1 11 +#define STM32F7_RCC_APB2_SPI1 12 +#define STM32F7_RCC_APB2_SPI4 13 +#define STM32F7_RCC_APB2_SYSCFG 14 +#define STM32F7_RCC_APB2_TIM9 16 +#define STM32F7_RCC_APB2_TIM10 17 +#define STM32F7_RCC_APB2_TIM11 18 +#define STM32F7_RCC_APB2_SPI5 20 +#define STM32F7_RCC_APB2_SPI6 21 +#define STM32F7_RCC_APB2_SAI1 22 +#define STM32F7_RCC_APB2_SAI2 23 +#define STM32F7_RCC_APB2_LTDC 26 +#define STM32F7_RCC_APB2_DSI 27 + +#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) +#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) + +#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */ diff --git a/roms/u-boot/include/dt-bindings/mfd/stm32h7-rcc.h b/roms/u-boot/include/dt-bindings/mfd/stm32h7-rcc.h new file mode 100644 index 000000000..06e8476bf --- /dev/null +++ b/roms/u-boot/include/dt-bindings/mfd/stm32h7-rcc.h @@ -0,0 +1,138 @@ +/* + * This header provides constants for the STM32H7 RCC IP + */ + +#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H +#define _DT_BINDINGS_MFD_STM32H7_RCC_H + +/* AHB3 */ +#define STM32H7_RCC_AHB3_MDMA 0 +#define STM32H7_RCC_AHB3_DMA2D 4 +#define STM32H7_RCC_AHB3_JPGDEC 5 +#define STM32H7_RCC_AHB3_FMC 12 +#define STM32H7_RCC_AHB3_QUADSPI 14 +#define STM32H7_RCC_AHB3_SDMMC1 16 +#define STM32H7_RCC_AHB3_CPU 31 +#define STM32H7_RCC_AHB3_CPU1 31 + +#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) + +/* AHB1 */ +#define STM32H7_RCC_AHB1_DMA1 0 +#define STM32H7_RCC_AHB1_DMA2 1 +#define STM32H7_RCC_AHB1_ADC12 5 +#define STM32H7_RCC_AHB1_ART 14 +#define STM32H7_RCC_AHB1_ETH1MAC 15 +#define STM32H7_RCC_AHB1_USB1OTG 25 +#define STM32H7_RCC_AHB1_USB2OTG 27 +#define STM32H7_RCC_AHB1_CPU2 31 + +#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8)) + +/* AHB2 */ +#define STM32H7_RCC_AHB2_CAMITF 0 +#define STM32H7_RCC_AHB2_CRYPT 4 +#define STM32H7_RCC_AHB2_HASH 5 +#define STM32H7_RCC_AHB2_RNG 6 +#define STM32H7_RCC_AHB2_SDMMC2 9 + +#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8)) + +/* AHB4 */ +#define STM32H7_RCC_AHB4_GPIOA 0 +#define STM32H7_RCC_AHB4_GPIOB 1 +#define STM32H7_RCC_AHB4_GPIOC 2 +#define STM32H7_RCC_AHB4_GPIOD 3 +#define STM32H7_RCC_AHB4_GPIOE 4 +#define STM32H7_RCC_AHB4_GPIOF 5 +#define STM32H7_RCC_AHB4_GPIOG 6 +#define STM32H7_RCC_AHB4_GPIOH 7 +#define STM32H7_RCC_AHB4_GPIOI 8 +#define STM32H7_RCC_AHB4_GPIOJ 9 +#define STM32H7_RCC_AHB4_GPIOK 10 +#define STM32H7_RCC_AHB4_CRC 19 +#define STM32H7_RCC_AHB4_BDMA 21 +#define STM32H7_RCC_AHB4_ADC3 24 +#define STM32H7_RCC_AHB4_HSEM 25 + +#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) + +/* APB3 */ +#define STM32H7_RCC_APB3_LTDC 3 +#define STM32H7_RCC_APB3_DSI 4 + +#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8)) + +/* APB1L */ +#define STM32H7_RCC_APB1L_TIM2 0 +#define STM32H7_RCC_APB1L_TIM3 1 +#define STM32H7_RCC_APB1L_TIM4 2 +#define STM32H7_RCC_APB1L_TIM5 3 +#define STM32H7_RCC_APB1L_TIM6 4 +#define STM32H7_RCC_APB1L_TIM7 5 +#define STM32H7_RCC_APB1L_TIM12 6 +#define STM32H7_RCC_APB1L_TIM13 7 +#define STM32H7_RCC_APB1L_TIM14 8 +#define STM32H7_RCC_APB1L_LPTIM1 9 +#define STM32H7_RCC_APB1L_SPI2 14 +#define STM32H7_RCC_APB1L_SPI3 15 +#define STM32H7_RCC_APB1L_SPDIF_RX 16 +#define STM32H7_RCC_APB1L_USART2 17 +#define STM32H7_RCC_APB1L_USART3 18 +#define STM32H7_RCC_APB1L_UART4 19 +#define STM32H7_RCC_APB1L_UART5 20 +#define STM32H7_RCC_APB1L_I2C1 21 +#define STM32H7_RCC_APB1L_I2C2 22 +#define STM32H7_RCC_APB1L_I2C3 23 +#define STM32H7_RCC_APB1L_HDMICEC 27 +#define STM32H7_RCC_APB1L_DAC12 29 +#define STM32H7_RCC_APB1L_USART7 30 +#define STM32H7_RCC_APB1L_USART8 31 + +#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8)) + +/* APB1H */ +#define STM32H7_RCC_APB1H_CRS 1 +#define STM32H7_RCC_APB1H_SWP 2 +#define STM32H7_RCC_APB1H_OPAMP 4 +#define STM32H7_RCC_APB1H_MDIOS 5 +#define STM32H7_RCC_APB1H_FDCAN 8 + +#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8)) + +/* APB2 */ +#define STM32H7_RCC_APB2_TIM1 0 +#define STM32H7_RCC_APB2_TIM8 1 +#define STM32H7_RCC_APB2_USART1 4 +#define STM32H7_RCC_APB2_USART6 5 +#define STM32H7_RCC_APB2_SPI1 12 +#define STM32H7_RCC_APB2_SPI4 13 +#define STM32H7_RCC_APB2_TIM15 16 +#define STM32H7_RCC_APB2_TIM16 17 +#define STM32H7_RCC_APB2_TIM17 18 +#define STM32H7_RCC_APB2_SPI5 20 +#define STM32H7_RCC_APB2_SAI1 22 +#define STM32H7_RCC_APB2_SAI2 23 +#define STM32H7_RCC_APB2_SAI3 24 +#define STM32H7_RCC_APB2_DFSDM1 28 +#define STM32H7_RCC_APB2_HRTIM 29 + +#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8)) + +/* APB4 */ +#define STM32H7_RCC_APB4_SYSCFG 1 +#define STM32H7_RCC_APB4_LPUART1 3 +#define STM32H7_RCC_APB4_SPI6 5 +#define STM32H7_RCC_APB4_I2C4 7 +#define STM32H7_RCC_APB4_LPTIM2 9 +#define STM32H7_RCC_APB4_LPTIM3 10 +#define STM32H7_RCC_APB4_LPTIM4 11 +#define STM32H7_RCC_APB4_LPTIM5 12 +#define STM32H7_RCC_APB4_COMP12 14 +#define STM32H7_RCC_APB4_VREF 15 +#define STM32H7_RCC_APB4_SAI4 21 +#define STM32H7_RCC_APB4_TMPSENS 26 + +#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8)) + +#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */ diff --git a/roms/u-boot/include/dt-bindings/mrc/quark.h b/roms/u-boot/include/dt-bindings/mrc/quark.h new file mode 100644 index 000000000..c763e74b5 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/mrc/quark.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015, Bin Meng + * + * Intel Quark MRC bindings include several properties + * as part of an Intel Quark MRC node. In most cases, + * the value of these properties uses the standard values + * defined in this header. + */ + +#ifndef _DT_BINDINGS_QRK_MRC_H_ +#define _DT_BINDINGS_QRK_MRC_H_ + +/* MRC platform data flags */ +#define MRC_FLAG_ECC_EN 0x00000001 +#define MRC_FLAG_SCRAMBLE_EN 0x00000002 +#define MRC_FLAG_MEMTEST_EN 0x00000004 +/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */ +#define MRC_FLAG_TOP_TREE_EN 0x00000008 +/* If set ODR signal is asserted to DRAM devices on writes */ +#define MRC_FLAG_WR_ODT_EN 0x00000010 + +/* DRAM width */ +#define DRAM_WIDTH_X8 0 +#define DRAM_WIDTH_X16 1 +#define DRAM_WIDTH_X32 2 + +/* DRAM speed */ +#define DRAM_FREQ_800 0 +#define DRAM_FREQ_1066 1 + +/* DRAM type */ +#define DRAM_TYPE_DDR3 0 +#define DRAM_TYPE_DDR3L 1 + +/* DRAM rank mask */ +#define DRAM_RANK(n) (1 << (n)) + +/* DRAM channel mask */ +#define DRAM_CHANNEL(n) (1 << (n)) + +/* DRAM channel width */ +#define DRAM_CHANNEL_WIDTH_X8 0 +#define DRAM_CHANNEL_WIDTH_X16 1 +#define DRAM_CHANNEL_WIDTH_X32 2 + +/* DRAM address mode */ +#define DRAM_ADDR_MODE0 0 +#define DRAM_ADDR_MODE1 1 +#define DRAM_ADDR_MODE2 2 + +/* DRAM refresh rate */ +#define DRAM_REFRESH_RATE_195US 1 +#define DRAM_REFRESH_RATE_39US 2 +#define DRAM_REFRESH_RATE_785US 3 + +/* DRAM SR temprature range */ +#define DRAM_SRT_RANGE_NORMAL 0 +#define DRAM_SRT_RANGE_EXTENDED 1 + +/* DRAM ron value */ +#define DRAM_RON_34OHM 0 +#define DRAM_RON_40OHM 1 + +/* DRAM rtt nom value */ +#define DRAM_RTT_NOM_40OHM 0 +#define DRAM_RTT_NOM_60OHM 1 +#define DRAM_RTT_NOM_120OHM 2 + +/* DRAM rd odt value */ +#define DRAM_RD_ODT_OFF 0 +#define DRAM_RD_ODT_60OHM 1 +#define DRAM_RD_ODT_120OHM 2 +#define DRAM_RD_ODT_180OHM 3 + +/* DRAM density */ +#define DRAM_DENSITY_512M 0 +#define DRAM_DENSITY_1G 1 +#define DRAM_DENSITY_2G 2 +#define DRAM_DENSITY_4G 3 + +#endif /* _DT_BINDINGS_QRK_MRC_H_ */ diff --git a/roms/u-boot/include/dt-bindings/mscc/jr2_data.h b/roms/u-boot/include/dt-bindings/mscc/jr2_data.h new file mode 100644 index 000000000..2f06fc5c5 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/mscc/jr2_data.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _JR2_DATA_H_ +#define _JR2_DATA_H_ + +#define SERDES1G(x) (x) +#define SERDES1G_MAX SERDES1G(10) +#define SERDES6G(x) (SERDES1G_MAX + 1 + (x)) +#define SERDES6G_MAX SERDES6G(17) +#define SERDES_MAX (SERDES6G_MAX + 1) + +/* similar with phy_interface_t */ +#define PHY_MODE_SGMII 2 +#define PHY_MODE_QSGMII 4 + +#endif diff --git a/roms/u-boot/include/dt-bindings/mscc/luton_data.h b/roms/u-boot/include/dt-bindings/mscc/luton_data.h new file mode 100644 index 000000000..e48856772 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/mscc/luton_data.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Microsemi Corporation + */ + +#ifndef _LUTON_DATA_H_ +#define _LUTON_DATA_H_ + +#define SERDES6G(x) (x) +#define SERDES6G_MAX SERDES6G(5) +#define SERDES_MAX (SERDES6G_MAX) + +/* similar with phy_interface_t */ +#define PHY_MODE_SGMII 2 +#define PHY_MODE_QSGMII 4 + +#endif diff --git a/roms/u-boot/include/dt-bindings/mscc/ocelot_data.h b/roms/u-boot/include/dt-bindings/mscc/ocelot_data.h new file mode 100644 index 000000000..7a5a1bf36 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/mscc/ocelot_data.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Microsemi Corporation + */ + +#ifndef _OCELOT_DATA_H_ +#define _OCELOT_DATA_H_ + +#define SERDES1G(x) (x) +#define SERDES1G_MAX SERDES1G(7) +#define SERDES6G(x) (SERDES1G_MAX + 1 + (x)) +#define SERDES6G_MAX SERDES6G(11) +#define SERDES_MAX (SERDES6G_MAX + 1) + +/* similar with phy_interface_t */ +#define PHY_MODE_SGMII 2 +#define PHY_MODE_QSGMII 4 + +#endif diff --git a/roms/u-boot/include/dt-bindings/mscc/serval_data.h b/roms/u-boot/include/dt-bindings/mscc/serval_data.h new file mode 100644 index 000000000..b374fda05 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/mscc/serval_data.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _SERVAL_DATA_H_ +#define _SERVAL_DATA_H_ + +#define SERDES1G(x) (x) +#define SERDES1G_MAX SERDES1G(9) +#define SERDES6G(x) (SERDES1G_MAX + 1 + (x)) +#define SERDES6G_MAX SERDES6G(11) +#define SERDES_MAX (SERDES6G_MAX + 1) + +/* similar with phy_interface_t */ +#define PHY_MODE_SGMII 2 +#define PHY_MODE_QSGMII 4 + +#endif diff --git a/roms/u-boot/include/dt-bindings/mux/mux.h b/roms/u-boot/include/dt-bindings/mux/mux.h new file mode 100644 index 000000000..042719218 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/mux/mux.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for most Multiplexer bindings. + * + * Most Multiplexer bindings specify an idle state. In most cases, the + * the multiplexer can be left as is when idle, and in some cases it can + * disconnect the input/output and leave the multiplexer in a high + * impedance state. + */ + +#ifndef _DT_BINDINGS_MUX_MUX_H +#define _DT_BINDINGS_MUX_MUX_H + +#define MUX_IDLE_AS_IS (-1) +#define MUX_IDLE_DISCONNECT (-2) + +#endif diff --git a/roms/u-boot/include/dt-bindings/mux/ti-serdes.h b/roms/u-boot/include/dt-bindings/mux/ti-serdes.h new file mode 100644 index 000000000..9047ec6bd --- /dev/null +++ b/roms/u-boot/include/dt-bindings/mux/ti-serdes.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for SERDES MUX for TI SoCs + */ + +#ifndef _DT_BINDINGS_MUX_TI_SERDES +#define _DT_BINDINGS_MUX_TI_SERDES + +/* J721E */ + +#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 +#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 +#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 +#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 + +#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 +#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 +#define J721E_SERDES0_LANE1_USB3_0 0x2 +#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 + +#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 +#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 +#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 +#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 + +#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 +#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 +#define J721E_SERDES1_LANE1_USB3_1 0x2 +#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 + +#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 +#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 +#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 +#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 + +#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 +#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 +#define J721E_SERDES2_LANE1_USB3_1 0x2 +#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 + +#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 +#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 +#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 +#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 + +#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 +#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 +#define J721E_SERDES3_LANE1_USB3_0 0x2 +#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 + +#define J721E_SERDES4_LANE0_EDP_LANE0 0x0 +#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 +#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 +#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 + +#define J721E_SERDES4_LANE1_EDP_LANE1 0x0 +#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 +#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 +#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 + +#define J721E_SERDES4_LANE2_EDP_LANE2 0x0 +#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 +#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 +#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 + +#define J721E_SERDES4_LANE3_EDP_LANE3 0x0 +#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 +#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 +#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 + +/* J7200 */ + +#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 +#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 +#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 +#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 +#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 +#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 +#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 +#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 +#define J7200_SERDES0_LANE3_USB 0x2 +#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 + +#endif /* _DT_BINDINGS_MUX_TI_SERDES */ diff --git a/roms/u-boot/include/dt-bindings/net/microchip-lan78xx.h b/roms/u-boot/include/dt-bindings/net/microchip-lan78xx.h new file mode 100644 index 000000000..0742ff075 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/net/microchip-lan78xx.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_MICROCHIP_LAN78XX_H +#define _DT_BINDINGS_MICROCHIP_LAN78XX_H + +/* LED modes for LAN7800/LAN7850 embedded PHY */ + +#define LAN78XX_LINK_ACTIVITY 0 +#define LAN78XX_LINK_1000_ACTIVITY 1 +#define LAN78XX_LINK_100_ACTIVITY 2 +#define LAN78XX_LINK_10_ACTIVITY 3 +#define LAN78XX_LINK_100_1000_ACTIVITY 4 +#define LAN78XX_LINK_10_1000_ACTIVITY 5 +#define LAN78XX_LINK_10_100_ACTIVITY 6 +#define LAN78XX_DUPLEX_COLLISION 8 +#define LAN78XX_COLLISION 9 +#define LAN78XX_ACTIVITY 10 +#define LAN78XX_AUTONEG_FAULT 12 +#define LAN78XX_FORCE_LED_OFF 14 +#define LAN78XX_FORCE_LED_ON 15 + +#endif diff --git a/roms/u-boot/include/dt-bindings/net/mscc-phy-vsc8531.h b/roms/u-boot/include/dt-bindings/net/mscc-phy-vsc8531.h new file mode 100644 index 000000000..61f5287d7 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/net/mscc-phy-vsc8531.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Device Tree constants for Microsemi VSC8531 PHY + * + * Author: Nagaraju Lakkaraju + * + * Copyright (c) 2017 Microsemi Corporation + */ + +#ifndef _DT_BINDINGS_MSCC_VSC8531_H +#define _DT_BINDINGS_MSCC_VSC8531_H + +/* PHY LED Modes */ +#define VSC8531_LINK_ACTIVITY 0 +#define VSC8531_LINK_1000_ACTIVITY 1 +#define VSC8531_LINK_100_ACTIVITY 2 +#define VSC8531_LINK_10_ACTIVITY 3 +#define VSC8531_LINK_100_1000_ACTIVITY 4 +#define VSC8531_LINK_10_1000_ACTIVITY 5 +#define VSC8531_LINK_10_100_ACTIVITY 6 +#define VSC8584_LINK_100FX_1000X_ACTIVITY 7 +#define VSC8531_DUPLEX_COLLISION 8 +#define VSC8531_COLLISION 9 +#define VSC8531_ACTIVITY 10 +#define VSC8584_100FX_1000X_ACTIVITY 11 +#define VSC8531_AUTONEG_FAULT 12 +#define VSC8531_SERIAL_MODE 13 +#define VSC8531_FORCE_LED_OFF 14 +#define VSC8531_FORCE_LED_ON 15 + +#define VSC8531_RGMII_CLK_DELAY_0_2_NS 0 +#define VSC8531_RGMII_CLK_DELAY_0_8_NS 1 +#define VSC8531_RGMII_CLK_DELAY_1_1_NS 2 +#define VSC8531_RGMII_CLK_DELAY_1_7_NS 3 +#define VSC8531_RGMII_CLK_DELAY_2_0_NS 4 +#define VSC8531_RGMII_CLK_DELAY_2_3_NS 5 +#define VSC8531_RGMII_CLK_DELAY_2_6_NS 6 +#define VSC8531_RGMII_CLK_DELAY_3_4_NS 7 + +#endif diff --git a/roms/u-boot/include/dt-bindings/net/qca-ar803x.h b/roms/u-boot/include/dt-bindings/net/qca-ar803x.h new file mode 100644 index 000000000..9c046c724 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/net/qca-ar803x.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Device Tree constants for the Qualcomm Atheros AR803x PHYs + */ + +#ifndef _DT_BINDINGS_QCA_AR803X_H +#define _DT_BINDINGS_QCA_AR803X_H + +#define AR803X_STRENGTH_FULL 0 +#define AR803X_STRENGTH_HALF 1 +#define AR803X_STRENGTH_QUARTER 2 + +#endif diff --git a/roms/u-boot/include/dt-bindings/net/ti-dp83867.h b/roms/u-boot/include/dt-bindings/net/ti-dp83867.h new file mode 100644 index 000000000..cde5aa7e2 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/net/ti-dp83867.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * TI DP83867 PHY drivers + * + */ + +#ifndef _DT_BINDINGS_TI_DP83867_H +#define _DT_BINDINGS_TI_DP83867_H + +/* PHY CTRL bits */ +#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 +#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 +#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 +#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 + +/* RGMIIDCTL internal delay for rx and tx */ +#define DP83867_RGMIIDCTL_250_PS 0x0 +#define DP83867_RGMIIDCTL_500_PS 0x1 +#define DP83867_RGMIIDCTL_750_PS 0x2 +#define DP83867_RGMIIDCTL_1_NS 0x3 +#define DP83867_RGMIIDCTL_1_25_NS 0x4 +#define DP83867_RGMIIDCTL_1_50_NS 0x5 +#define DP83867_RGMIIDCTL_1_75_NS 0x6 +#define DP83867_RGMIIDCTL_2_00_NS 0x7 +#define DP83867_RGMIIDCTL_2_25_NS 0x8 +#define DP83867_RGMIIDCTL_2_50_NS 0x9 +#define DP83867_RGMIIDCTL_2_75_NS 0xa +#define DP83867_RGMIIDCTL_3_00_NS 0xb +#define DP83867_RGMIIDCTL_3_25_NS 0xc +#define DP83867_RGMIIDCTL_3_50_NS 0xd +#define DP83867_RGMIIDCTL_3_75_NS 0xe +#define DP83867_RGMIIDCTL_4_00_NS 0xf + +/* IO_MUX_CFG - Clock output selection */ +#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 +#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 +#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 +#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 +#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 +#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 +#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 +#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 +#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 +#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 +#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA +#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB +#define DP83867_CLK_O_SEL_REF_CLK 0xC +/* Special flag to indicate clock should be off */ +#define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF +#endif diff --git a/roms/u-boot/include/dt-bindings/phy/phy-am654-serdes.h b/roms/u-boot/include/dt-bindings/phy/phy-am654-serdes.h new file mode 100644 index 000000000..e8d901729 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/phy/phy-am654-serdes.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for AM654 SERDES. + */ + +#ifndef _DT_BINDINGS_AM654_SERDES +#define _DT_BINDINGS_AM654_SERDES + +#define AM654_SERDES_CMU_REFCLK 0 +#define AM654_SERDES_LO_REFCLK 1 +#define AM654_SERDES_RO_REFCLK 2 + +#endif /* _DT_BINDINGS_AM654_SERDES */ diff --git a/roms/u-boot/include/dt-bindings/phy/phy.h b/roms/u-boot/include/dt-bindings/phy/phy.h new file mode 100644 index 000000000..7e657da45 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/phy/phy.h @@ -0,0 +1,23 @@ +/* + * + * This header provides constants for the phy framework + * + * Copyright (C) 2014 STMicroelectronics + * Author: Gabriel Fernandez + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _DT_BINDINGS_PHY +#define _DT_BINDINGS_PHY + +#define PHY_NONE 0 +#define PHY_TYPE_SATA 1 +#define PHY_TYPE_PCIE 2 +#define PHY_TYPE_USB2 3 +#define PHY_TYPE_USB3 4 +#define PHY_TYPE_UFS 5 +#define PHY_TYPE_DP 6 +#define PHY_TYPE_XPCS 7 +#define PHY_TYPE_SGMII 8 + +#endif /* _DT_BINDINGS_PHY */ diff --git a/roms/u-boot/include/dt-bindings/pinctrl/am33xx.h b/roms/u-boot/include/dt-bindings/pinctrl/am33xx.h new file mode 100644 index 000000000..226f77246 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/am33xx.h @@ -0,0 +1,43 @@ +/* + * This header provides constants specific to AM33XX pinctrl bindings. + */ + +#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H +#define _DT_BINDINGS_PINCTRL_AM33XX_H + +#include + +/* am33xx specific mux bit defines */ +#undef PULL_ENA +#undef INPUT_EN + +#define PULL_DISABLE (1 << 3) +#define INPUT_EN (1 << 5) +#define SLEWCTRL_SLOW (1 << 6) +#define SLEWCTRL_FAST 0 + +/* update macro depending on INPUT_EN and PULL_ENA */ +#undef PIN_OUTPUT +#undef PIN_OUTPUT_PULLUP +#undef PIN_OUTPUT_PULLDOWN +#undef PIN_INPUT +#undef PIN_INPUT_PULLUP +#undef PIN_INPUT_PULLDOWN + +#define PIN_OUTPUT (PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (PULL_UP) +#define PIN_OUTPUT_PULLDOWN 0 +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN) + +/* undef non-existing modes */ +#undef PIN_OFF_NONE +#undef PIN_OFF_OUTPUT_HIGH +#undef PIN_OFF_OUTPUT_LOW +#undef PIN_OFF_INPUT_PULLUP +#undef PIN_OFF_INPUT_PULLDOWN +#undef PIN_OFF_WAKEUPENABLE + +#endif + diff --git a/roms/u-boot/include/dt-bindings/pinctrl/am43xx.h b/roms/u-boot/include/dt-bindings/pinctrl/am43xx.h new file mode 100644 index 000000000..292c2ebf5 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/am43xx.h @@ -0,0 +1,39 @@ +/* + * This header provides constants specific to AM43XX pinctrl bindings. + */ + +#ifndef _DT_BINDINGS_PINCTRL_AM43XX_H +#define _DT_BINDINGS_PINCTRL_AM43XX_H + +#define MUX_MODE0 0 +#define MUX_MODE1 1 +#define MUX_MODE2 2 +#define MUX_MODE3 3 +#define MUX_MODE4 4 +#define MUX_MODE5 5 +#define MUX_MODE6 6 +#define MUX_MODE7 7 +#define MUX_MODE8 8 + +#define PULL_DISABLE (1 << 16) +#define PULL_UP (1 << 17) +#define INPUT_EN (1 << 18) +#define SLEWCTRL_SLOW (1 << 19) +#define SLEWCTRL_FAST 0 +#define DS0_PULL_UP_DOWN_EN (1 << 27) +#define WAKEUP_ENABLE (1 << 29) + +#define PIN_OUTPUT (PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (PULL_UP) +#define PIN_OUTPUT_PULLDOWN 0 +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN) + +/* + * Macro to allow using the absolute physical address instead of the + * padconf registers instead of the offset from padconf base. + */ +#define AM4372_IOPAD(pa, val) (((pa) & 0xffff) - 0x0800) (val) + +#endif diff --git a/roms/u-boot/include/dt-bindings/pinctrl/at91.h b/roms/u-boot/include/dt-bindings/pinctrl/at91.h new file mode 100644 index 000000000..3831f91fb --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/at91.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * This header provides constants for most at91 pinctrl bindings. + * + * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD + */ + +#ifndef __DT_BINDINGS_AT91_PINCTRL_H__ +#define __DT_BINDINGS_AT91_PINCTRL_H__ + +#define AT91_PINCTRL_NONE (0 << 0) +#define AT91_PINCTRL_PULL_UP (1 << 0) +#define AT91_PINCTRL_MULTI_DRIVE (1 << 1) +#define AT91_PINCTRL_DEGLITCH (1 << 2) +#define AT91_PINCTRL_PULL_DOWN (1 << 3) +#define AT91_PINCTRL_DIS_SCHMIT (1 << 4) +#define AT91_PINCTRL_OUTPUT (1 << 7) +#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8) +#define AT91_PINCTRL_SLEWRATE (1 << 9) +#define AT91_PINCTRL_DEBOUNCE (1 << 16) +#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17) + +#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH) + +#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT (0x0 << 5) +#define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5) +#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5) +#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5) + +#define AT91_PINCTRL_SLEWRATE_DIS (0x0 << 9) +#define AT91_PINCTRL_SLEWRATE_ENA (0x1 << 9) + +#define AT91_PIOA 0 +#define AT91_PIOB 1 +#define AT91_PIOC 2 +#define AT91_PIOD 3 +#define AT91_PIOE 4 + +#define AT91_PERIPH_GPIO 0 +#define AT91_PERIPH_A 1 +#define AT91_PERIPH_B 2 +#define AT91_PERIPH_C 3 +#define AT91_PERIPH_D 4 + +#define ATMEL_PIO_DRVSTR_LO 1 +#define ATMEL_PIO_DRVSTR_ME 2 +#define ATMEL_PIO_DRVSTR_HI 3 + +#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */ diff --git a/roms/u-boot/include/dt-bindings/pinctrl/bcm2835.h b/roms/u-boot/include/dt-bindings/pinctrl/bcm2835.h new file mode 100644 index 000000000..b5b2654a0 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/bcm2835.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Header providing constants for bcm2835 pinctrl bindings. + * + * Copyright (C) 2015 Stefan Wahren + */ + +#ifndef __DT_BINDINGS_PINCTRL_BCM2835_H__ +#define __DT_BINDINGS_PINCTRL_BCM2835_H__ + +/* brcm,function property */ +#define BCM2835_FSEL_GPIO_IN 0 +#define BCM2835_FSEL_GPIO_OUT 1 +#define BCM2835_FSEL_ALT5 2 +#define BCM2835_FSEL_ALT4 3 +#define BCM2835_FSEL_ALT0 4 +#define BCM2835_FSEL_ALT1 5 +#define BCM2835_FSEL_ALT2 6 +#define BCM2835_FSEL_ALT3 7 + +/* brcm,pull property */ +#define BCM2835_PUD_OFF 0 +#define BCM2835_PUD_DOWN 1 +#define BCM2835_PUD_UP 2 + +#endif /* __DT_BINDINGS_PINCTRL_BCM2835_H__ */ diff --git a/roms/u-boot/include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h b/roms/u-boot/include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h new file mode 100644 index 000000000..81ebd58ca --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Broadcom. + */ + +#ifndef __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__ +#define __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__ + +/* Alternate functions available in MUX controller */ +#define MODE_NITRO 0 +#define MODE_NAND 1 +#define MODE_PNOR 2 +#define MODE_GPIO 3 + +/* Pad configuration attribute */ +#define PAD_SLEW_RATE_ENA BIT(0) +#define PAD_SLEW_RATE_ENA_MASK BIT(0) + +#define PAD_DRIVE_STRENGTH_2_MA (0 << 1) +#define PAD_DRIVE_STRENGTH_4_MA BIT(1) +#define PAD_DRIVE_STRENGTH_6_MA (2 << 1) +#define PAD_DRIVE_STRENGTH_8_MA (3 << 1) +#define PAD_DRIVE_STRENGTH_10_MA (4 << 1) +#define PAD_DRIVE_STRENGTH_12_MA (5 << 1) +#define PAD_DRIVE_STRENGTH_14_MA (6 << 1) +#define PAD_DRIVE_STRENGTH_16_MA (7 << 1) +#define PAD_DRIVE_STRENGTH_MASK (7 << 1) + +#define PAD_PULL_UP_ENA BIT(4) +#define PAD_PULL_UP_ENA_MASK BIT(4) + +#define PAD_PULL_DOWN_ENA BIT(5) +#define PAD_PULL_DOWN_ENA_MASK BIT(5) + +#define PAD_INPUT_PATH_DIS BIT(6) +#define PAD_INPUT_PATH_DIS_MASK BIT(6) + +#define PAD_HYSTERESIS_ENA BIT(7) +#define PAD_HYSTERESIS_ENA_MASK BIT(7) + +#endif diff --git a/roms/u-boot/include/dt-bindings/pinctrl/dra.h b/roms/u-boot/include/dt-bindings/pinctrl/dra.h new file mode 100644 index 000000000..18ec5df5a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/dra.h @@ -0,0 +1,80 @@ +/* + * This header provides constants for DRA pinctrl bindings. + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Rajendra Nayak + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _DT_BINDINGS_PINCTRL_DRA_H +#define _DT_BINDINGS_PINCTRL_DRA_H + +/* DRA7 mux mode options for each pin. See TRM for options */ +#define MUX_MODE0 0x0 +#define MUX_MODE1 0x1 +#define MUX_MODE2 0x2 +#define MUX_MODE3 0x3 +#define MUX_MODE4 0x4 +#define MUX_MODE5 0x5 +#define MUX_MODE6 0x6 +#define MUX_MODE7 0x7 +#define MUX_MODE8 0x8 +#define MUX_MODE9 0x9 +#define MUX_MODE10 0xa +#define MUX_MODE11 0xb +#define MUX_MODE12 0xc +#define MUX_MODE13 0xd +#define MUX_MODE14 0xe +#define MUX_MODE15 0xf + +/* Certain pins need virtual mode, but note: they may glitch */ +#define MUX_VIRTUAL_MODE0 (MODE_SELECT | (0x0 << 4)) +#define MUX_VIRTUAL_MODE1 (MODE_SELECT | (0x1 << 4)) +#define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4)) +#define MUX_VIRTUAL_MODE3 (MODE_SELECT | (0x3 << 4)) +#define MUX_VIRTUAL_MODE4 (MODE_SELECT | (0x4 << 4)) +#define MUX_VIRTUAL_MODE5 (MODE_SELECT | (0x5 << 4)) +#define MUX_VIRTUAL_MODE6 (MODE_SELECT | (0x6 << 4)) +#define MUX_VIRTUAL_MODE7 (MODE_SELECT | (0x7 << 4)) +#define MUX_VIRTUAL_MODE8 (MODE_SELECT | (0x8 << 4)) +#define MUX_VIRTUAL_MODE9 (MODE_SELECT | (0x9 << 4)) +#define MUX_VIRTUAL_MODE10 (MODE_SELECT | (0xa << 4)) +#define MUX_VIRTUAL_MODE11 (MODE_SELECT | (0xb << 4)) +#define MUX_VIRTUAL_MODE12 (MODE_SELECT | (0xc << 4)) +#define MUX_VIRTUAL_MODE13 (MODE_SELECT | (0xd << 4)) +#define MUX_VIRTUAL_MODE14 (MODE_SELECT | (0xe << 4)) +#define MUX_VIRTUAL_MODE15 (MODE_SELECT | (0xf << 4)) + +#define MODE_SELECT (1 << 8) + +#define PULL_ENA (0 << 16) +#define PULL_DIS (1 << 16) +#define PULL_UP (1 << 17) +#define INPUT_EN (1 << 18) +#define SLEWCONTROL (1 << 19) +#define WAKEUP_EN (1 << 24) +#define WAKEUP_EVENT (1 << 25) + +/* Active pin states */ +#define PIN_OUTPUT (0 | PULL_DIS) +#define PIN_OUTPUT_PULLUP (PULL_UP) +#define PIN_OUTPUT_PULLDOWN (0) +#define PIN_INPUT (INPUT_EN | PULL_DIS) +#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL) +#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) + +/* + * Macro to allow using the absolute physical address instead of the + * padconf registers instead of the offset from padconf base. + */ +#define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val) + +/* DRA7 IODELAY configuration parameters */ +#define A_DELAY_PS(val) ((val) & 0xffff) +#define G_DELAY_PS(val) ((val) & 0xffff) +#endif + diff --git a/roms/u-boot/include/dt-bindings/pinctrl/hisi.h b/roms/u-boot/include/dt-bindings/pinctrl/hisi.h new file mode 100644 index 000000000..0359bfdc9 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/hisi.h @@ -0,0 +1,74 @@ +/* + * This header provides constants for hisilicon pinctrl bindings. + * + * Copyright (c) 2015 Hisilicon Limited. + * Copyright (c) 2015 Linaro Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_PINCTRL_HISI_H +#define _DT_BINDINGS_PINCTRL_HISI_H + +/* iomg bit definition */ +#define MUX_M0 0 +#define MUX_M1 1 +#define MUX_M2 2 +#define MUX_M3 3 +#define MUX_M4 4 +#define MUX_M5 5 +#define MUX_M6 6 +#define MUX_M7 7 + +/* iocg bit definition */ +#define PULL_MASK (3) +#define PULL_DIS (0) +#define PULL_UP (1 << 0) +#define PULL_DOWN (1 << 1) + +/* drive strength definition */ +#define DRIVE_MASK (7 << 4) +#define DRIVE1_02MA (0 << 4) +#define DRIVE1_04MA (1 << 4) +#define DRIVE1_08MA (2 << 4) +#define DRIVE1_10MA (3 << 4) +#define DRIVE2_02MA (0 << 4) +#define DRIVE2_04MA (1 << 4) +#define DRIVE2_08MA (2 << 4) +#define DRIVE2_10MA (3 << 4) +#define DRIVE3_04MA (0 << 4) +#define DRIVE3_08MA (1 << 4) +#define DRIVE3_12MA (2 << 4) +#define DRIVE3_16MA (3 << 4) +#define DRIVE3_20MA (4 << 4) +#define DRIVE3_24MA (5 << 4) +#define DRIVE3_32MA (6 << 4) +#define DRIVE3_40MA (7 << 4) +#define DRIVE4_02MA (0 << 4) +#define DRIVE4_04MA (2 << 4) +#define DRIVE4_08MA (4 << 4) +#define DRIVE4_10MA (6 << 4) + +/* drive strength definition for hi3660 */ +#define DRIVE6_MASK (15 << 4) +#define DRIVE6_04MA (0 << 4) +#define DRIVE6_12MA (4 << 4) +#define DRIVE6_19MA (8 << 4) +#define DRIVE6_27MA (10 << 4) +#define DRIVE6_32MA (15 << 4) +#define DRIVE7_02MA (0 << 4) +#define DRIVE7_04MA (1 << 4) +#define DRIVE7_06MA (2 << 4) +#define DRIVE7_08MA (3 << 4) +#define DRIVE7_10MA (4 << 4) +#define DRIVE7_12MA (5 << 4) +#define DRIVE7_14MA (6 << 4) +#define DRIVE7_16MA (7 << 4) +#endif diff --git a/roms/u-boot/include/dt-bindings/pinctrl/k210-pinctrl.h b/roms/u-boot/include/dt-bindings/pinctrl/k210-pinctrl.h new file mode 100644 index 000000000..26c1f23b0 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/k210-pinctrl.h @@ -0,0 +1,277 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Sean Anderson + */ + +#ifndef DT_K210_PINCTRL_H +#define DT_K210_PINCTRL_H + +/* + * Full list of FPIOA functions from + * kendryte-standalone-sdk/lib/drivers/include/fpioa.h + */ +#define K210_PCF_MASK GENMASK(7, 0) +#define K210_PCF_JTAG_TCLK 0 /* JTAG Test Clock */ +#define K210_PCF_JTAG_TDI 1 /* JTAG Test Data In */ +#define K210_PCF_JTAG_TMS 2 /* JTAG Test Mode Select */ +#define K210_PCF_JTAG_TDO 3 /* JTAG Test Data Out */ +#define K210_PCF_SPI0_D0 4 /* SPI0 Data 0 */ +#define K210_PCF_SPI0_D1 5 /* SPI0 Data 1 */ +#define K210_PCF_SPI0_D2 6 /* SPI0 Data 2 */ +#define K210_PCF_SPI0_D3 7 /* SPI0 Data 3 */ +#define K210_PCF_SPI0_D4 8 /* SPI0 Data 4 */ +#define K210_PCF_SPI0_D5 9 /* SPI0 Data 5 */ +#define K210_PCF_SPI0_D6 10 /* SPI0 Data 6 */ +#define K210_PCF_SPI0_D7 11 /* SPI0 Data 7 */ +#define K210_PCF_SPI0_SS0 12 /* SPI0 Chip Select 0 */ +#define K210_PCF_SPI0_SS1 13 /* SPI0 Chip Select 1 */ +#define K210_PCF_SPI0_SS2 14 /* SPI0 Chip Select 2 */ +#define K210_PCF_SPI0_SS3 15 /* SPI0 Chip Select 3 */ +#define K210_PCF_SPI0_ARB 16 /* SPI0 Arbitration */ +#define K210_PCF_SPI0_SCLK 17 /* SPI0 Serial Clock */ +#define K210_PCF_UARTHS_RX 18 /* UART High speed Receiver */ +#define K210_PCF_UARTHS_TX 19 /* UART High speed Transmitter */ +#define K210_PCF_RESV6 20 /* Reserved function */ +#define K210_PCF_RESV7 21 /* Reserved function */ +#define K210_PCF_CLK_SPI1 22 /* Clock SPI1 */ +#define K210_PCF_CLK_I2C1 23 /* Clock I2C1 */ +#define K210_PCF_GPIOHS0 24 /* GPIO High speed 0 */ +#define K210_PCF_GPIOHS1 25 /* GPIO High speed 1 */ +#define K210_PCF_GPIOHS2 26 /* GPIO High speed 2 */ +#define K210_PCF_GPIOHS3 27 /* GPIO High speed 3 */ +#define K210_PCF_GPIOHS4 28 /* GPIO High speed 4 */ +#define K210_PCF_GPIOHS5 29 /* GPIO High speed 5 */ +#define K210_PCF_GPIOHS6 30 /* GPIO High speed 6 */ +#define K210_PCF_GPIOHS7 31 /* GPIO High speed 7 */ +#define K210_PCF_GPIOHS8 32 /* GPIO High speed 8 */ +#define K210_PCF_GPIOHS9 33 /* GPIO High speed 9 */ +#define K210_PCF_GPIOHS10 34 /* GPIO High speed 10 */ +#define K210_PCF_GPIOHS11 35 /* GPIO High speed 11 */ +#define K210_PCF_GPIOHS12 36 /* GPIO High speed 12 */ +#define K210_PCF_GPIOHS13 37 /* GPIO High speed 13 */ +#define K210_PCF_GPIOHS14 38 /* GPIO High speed 14 */ +#define K210_PCF_GPIOHS15 39 /* GPIO High speed 15 */ +#define K210_PCF_GPIOHS16 40 /* GPIO High speed 16 */ +#define K210_PCF_GPIOHS17 41 /* GPIO High speed 17 */ +#define K210_PCF_GPIOHS18 42 /* GPIO High speed 18 */ +#define K210_PCF_GPIOHS19 43 /* GPIO High speed 19 */ +#define K210_PCF_GPIOHS20 44 /* GPIO High speed 20 */ +#define K210_PCF_GPIOHS21 45 /* GPIO High speed 21 */ +#define K210_PCF_GPIOHS22 46 /* GPIO High speed 22 */ +#define K210_PCF_GPIOHS23 47 /* GPIO High speed 23 */ +#define K210_PCF_GPIOHS24 48 /* GPIO High speed 24 */ +#define K210_PCF_GPIOHS25 49 /* GPIO High speed 25 */ +#define K210_PCF_GPIOHS26 50 /* GPIO High speed 26 */ +#define K210_PCF_GPIOHS27 51 /* GPIO High speed 27 */ +#define K210_PCF_GPIOHS28 52 /* GPIO High speed 28 */ +#define K210_PCF_GPIOHS29 53 /* GPIO High speed 29 */ +#define K210_PCF_GPIOHS30 54 /* GPIO High speed 30 */ +#define K210_PCF_GPIOHS31 55 /* GPIO High speed 31 */ +#define K210_PCF_GPIO0 56 /* GPIO pin 0 */ +#define K210_PCF_GPIO1 57 /* GPIO pin 1 */ +#define K210_PCF_GPIO2 58 /* GPIO pin 2 */ +#define K210_PCF_GPIO3 59 /* GPIO pin 3 */ +#define K210_PCF_GPIO4 60 /* GPIO pin 4 */ +#define K210_PCF_GPIO5 61 /* GPIO pin 5 */ +#define K210_PCF_GPIO6 62 /* GPIO pin 6 */ +#define K210_PCF_GPIO7 63 /* GPIO pin 7 */ +#define K210_PCF_UART1_RX 64 /* UART1 Receiver */ +#define K210_PCF_UART1_TX 65 /* UART1 Transmitter */ +#define K210_PCF_UART2_RX 66 /* UART2 Receiver */ +#define K210_PCF_UART2_TX 67 /* UART2 Transmitter */ +#define K210_PCF_UART3_RX 68 /* UART3 Receiver */ +#define K210_PCF_UART3_TX 69 /* UART3 Transmitter */ +#define K210_PCF_SPI1_D0 70 /* SPI1 Data 0 */ +#define K210_PCF_SPI1_D1 71 /* SPI1 Data 1 */ +#define K210_PCF_SPI1_D2 72 /* SPI1 Data 2 */ +#define K210_PCF_SPI1_D3 73 /* SPI1 Data 3 */ +#define K210_PCF_SPI1_D4 74 /* SPI1 Data 4 */ +#define K210_PCF_SPI1_D5 75 /* SPI1 Data 5 */ +#define K210_PCF_SPI1_D6 76 /* SPI1 Data 6 */ +#define K210_PCF_SPI1_D7 77 /* SPI1 Data 7 */ +#define K210_PCF_SPI1_SS0 78 /* SPI1 Chip Select 0 */ +#define K210_PCF_SPI1_SS1 79 /* SPI1 Chip Select 1 */ +#define K210_PCF_SPI1_SS2 80 /* SPI1 Chip Select 2 */ +#define K210_PCF_SPI1_SS3 81 /* SPI1 Chip Select 3 */ +#define K210_PCF_SPI1_ARB 82 /* SPI1 Arbitration */ +#define K210_PCF_SPI1_SCLK 83 /* SPI1 Serial Clock */ +#define K210_PCF_SPI2_D0 84 /* SPI2 Data 0 */ +#define K210_PCF_SPI2_SS 85 /* SPI2 Select */ +#define K210_PCF_SPI2_SCLK 86 /* SPI2 Serial Clock */ +#define K210_PCF_I2S0_MCLK 87 /* I2S0 Master Clock */ +#define K210_PCF_I2S0_SCLK 88 /* I2S0 Serial Clock(BCLK) */ +#define K210_PCF_I2S0_WS 89 /* I2S0 Word Select(LRCLK) */ +#define K210_PCF_I2S0_IN_D0 90 /* I2S0 Serial Data Input 0 */ +#define K210_PCF_I2S0_IN_D1 91 /* I2S0 Serial Data Input 1 */ +#define K210_PCF_I2S0_IN_D2 92 /* I2S0 Serial Data Input 2 */ +#define K210_PCF_I2S0_IN_D3 93 /* I2S0 Serial Data Input 3 */ +#define K210_PCF_I2S0_OUT_D0 94 /* I2S0 Serial Data Output 0 */ +#define K210_PCF_I2S0_OUT_D1 95 /* I2S0 Serial Data Output 1 */ +#define K210_PCF_I2S0_OUT_D2 96 /* I2S0 Serial Data Output 2 */ +#define K210_PCF_I2S0_OUT_D3 97 /* I2S0 Serial Data Output 3 */ +#define K210_PCF_I2S1_MCLK 98 /* I2S1 Master Clock */ +#define K210_PCF_I2S1_SCLK 99 /* I2S1 Serial Clock(BCLK) */ +#define K210_PCF_I2S1_WS 100 /* I2S1 Word Select(LRCLK) */ +#define K210_PCF_I2S1_IN_D0 101 /* I2S1 Serial Data Input 0 */ +#define K210_PCF_I2S1_IN_D1 102 /* I2S1 Serial Data Input 1 */ +#define K210_PCF_I2S1_IN_D2 103 /* I2S1 Serial Data Input 2 */ +#define K210_PCF_I2S1_IN_D3 104 /* I2S1 Serial Data Input 3 */ +#define K210_PCF_I2S1_OUT_D0 105 /* I2S1 Serial Data Output 0 */ +#define K210_PCF_I2S1_OUT_D1 106 /* I2S1 Serial Data Output 1 */ +#define K210_PCF_I2S1_OUT_D2 107 /* I2S1 Serial Data Output 2 */ +#define K210_PCF_I2S1_OUT_D3 108 /* I2S1 Serial Data Output 3 */ +#define K210_PCF_I2S2_MCLK 109 /* I2S2 Master Clock */ +#define K210_PCF_I2S2_SCLK 110 /* I2S2 Serial Clock(BCLK) */ +#define K210_PCF_I2S2_WS 111 /* I2S2 Word Select(LRCLK) */ +#define K210_PCF_I2S2_IN_D0 112 /* I2S2 Serial Data Input 0 */ +#define K210_PCF_I2S2_IN_D1 113 /* I2S2 Serial Data Input 1 */ +#define K210_PCF_I2S2_IN_D2 114 /* I2S2 Serial Data Input 2 */ +#define K210_PCF_I2S2_IN_D3 115 /* I2S2 Serial Data Input 3 */ +#define K210_PCF_I2S2_OUT_D0 116 /* I2S2 Serial Data Output 0 */ +#define K210_PCF_I2S2_OUT_D1 117 /* I2S2 Serial Data Output 1 */ +#define K210_PCF_I2S2_OUT_D2 118 /* I2S2 Serial Data Output 2 */ +#define K210_PCF_I2S2_OUT_D3 119 /* I2S2 Serial Data Output 3 */ +#define K210_PCF_RESV0 120 /* Reserved function */ +#define K210_PCF_RESV1 121 /* Reserved function */ +#define K210_PCF_RESV2 122 /* Reserved function */ +#define K210_PCF_RESV3 123 /* Reserved function */ +#define K210_PCF_RESV4 124 /* Reserved function */ +#define K210_PCF_RESV5 125 /* Reserved function */ +#define K210_PCF_I2C0_SCLK 126 /* I2C0 Serial Clock */ +#define K210_PCF_I2C0_SDA 127 /* I2C0 Serial Data */ +#define K210_PCF_I2C1_SCLK 128 /* I2C1 Serial Clock */ +#define K210_PCF_I2C1_SDA 129 /* I2C1 Serial Data */ +#define K210_PCF_I2C2_SCLK 130 /* I2C2 Serial Clock */ +#define K210_PCF_I2C2_SDA 131 /* I2C2 Serial Data */ +#define K210_PCF_DVP_XCLK 132 /* DVP System Clock */ +#define K210_PCF_DVP_RST 133 /* DVP System Reset */ +#define K210_PCF_DVP_PWDN 134 /* DVP Power Down Mode */ +#define K210_PCF_DVP_VSYNC 135 /* DVP Vertical Sync */ +#define K210_PCF_DVP_HSYNC 136 /* DVP Horizontal Sync */ +#define K210_PCF_DVP_PCLK 137 /* Pixel Clock */ +#define K210_PCF_DVP_D0 138 /* Data Bit 0 */ +#define K210_PCF_DVP_D1 139 /* Data Bit 1 */ +#define K210_PCF_DVP_D2 140 /* Data Bit 2 */ +#define K210_PCF_DVP_D3 141 /* Data Bit 3 */ +#define K210_PCF_DVP_D4 142 /* Data Bit 4 */ +#define K210_PCF_DVP_D5 143 /* Data Bit 5 */ +#define K210_PCF_DVP_D6 144 /* Data Bit 6 */ +#define K210_PCF_DVP_D7 145 /* Data Bit 7 */ +#define K210_PCF_SCCB_SCLK 146 /* Serial Camera Control Bus Clock */ +#define K210_PCF_SCCB_SDA 147 /* Serial Camera Control Bus Data */ +#define K210_PCF_UART1_CTS 148 /* UART1 Clear To Send */ +#define K210_PCF_UART1_DSR 149 /* UART1 Data Set Ready */ +#define K210_PCF_UART1_DCD 150 /* UART1 Data Carrier Detect */ +#define K210_PCF_UART1_RI 151 /* UART1 Ring Indicator */ +#define K210_PCF_UART1_SIR_IN 152 /* UART1 Serial Infrared Input */ +#define K210_PCF_UART1_DTR 153 /* UART1 Data Terminal Ready */ +#define K210_PCF_UART1_RTS 154 /* UART1 Request To Send */ +#define K210_PCF_UART1_OUT2 155 /* UART1 User-designated Output 2 */ +#define K210_PCF_UART1_OUT1 156 /* UART1 User-designated Output 1 */ +#define K210_PCF_UART1_SIR_OUT 157 /* UART1 Serial Infrared Output */ +#define K210_PCF_UART1_BAUD 158 /* UART1 Transmit Clock Output */ +#define K210_PCF_UART1_RE 159 /* UART1 Receiver Output Enable */ +#define K210_PCF_UART1_DE 160 /* UART1 Driver Output Enable */ +#define K210_PCF_UART1_RS485_EN 161 /* UART1 RS485 Enable */ +#define K210_PCF_UART2_CTS 162 /* UART2 Clear To Send */ +#define K210_PCF_UART2_DSR 163 /* UART2 Data Set Ready */ +#define K210_PCF_UART2_DCD 164 /* UART2 Data Carrier Detect */ +#define K210_PCF_UART2_RI 165 /* UART2 Ring Indicator */ +#define K210_PCF_UART2_SIR_IN 166 /* UART2 Serial Infrared Input */ +#define K210_PCF_UART2_DTR 167 /* UART2 Data Terminal Ready */ +#define K210_PCF_UART2_RTS 168 /* UART2 Request To Send */ +#define K210_PCF_UART2_OUT2 169 /* UART2 User-designated Output 2 */ +#define K210_PCF_UART2_OUT1 170 /* UART2 User-designated Output 1 */ +#define K210_PCF_UART2_SIR_OUT 171 /* UART2 Serial Infrared Output */ +#define K210_PCF_UART2_BAUD 172 /* UART2 Transmit Clock Output */ +#define K210_PCF_UART2_RE 173 /* UART2 Receiver Output Enable */ +#define K210_PCF_UART2_DE 174 /* UART2 Driver Output Enable */ +#define K210_PCF_UART2_RS485_EN 175 /* UART2 RS485 Enable */ +#define K210_PCF_UART3_CTS 176 /* UART3 Clear To Send */ +#define K210_PCF_UART3_DSR 177 /* UART3 Data Set Ready */ +#define K210_PCF_UART3_DCD 178 /* UART3 Data Carrier Detect */ +#define K210_PCF_UART3_RI 179 /* UART3 Ring Indicator */ +#define K210_PCF_UART3_SIR_IN 180 /* UART3 Serial Infrared Input */ +#define K210_PCF_UART3_DTR 181 /* UART3 Data Terminal Ready */ +#define K210_PCF_UART3_RTS 182 /* UART3 Request To Send */ +#define K210_PCF_UART3_OUT2 183 /* UART3 User-designated Output 2 */ +#define K210_PCF_UART3_OUT1 184 /* UART3 User-designated Output 1 */ +#define K210_PCF_UART3_SIR_OUT 185 /* UART3 Serial Infrared Output */ +#define K210_PCF_UART3_BAUD 186 /* UART3 Transmit Clock Output */ +#define K210_PCF_UART3_RE 187 /* UART3 Receiver Output Enable */ +#define K210_PCF_UART3_DE 188 /* UART3 Driver Output Enable */ +#define K210_PCF_UART3_RS485_EN 189 /* UART3 RS485 Enable */ +#define K210_PCF_TIMER0_TOGGLE1 190 /* TIMER0 Toggle Output 1 */ +#define K210_PCF_TIMER0_TOGGLE2 191 /* TIMER0 Toggle Output 2 */ +#define K210_PCF_TIMER0_TOGGLE3 192 /* TIMER0 Toggle Output 3 */ +#define K210_PCF_TIMER0_TOGGLE4 193 /* TIMER0 Toggle Output 4 */ +#define K210_PCF_TIMER1_TOGGLE1 194 /* TIMER1 Toggle Output 1 */ +#define K210_PCF_TIMER1_TOGGLE2 195 /* TIMER1 Toggle Output 2 */ +#define K210_PCF_TIMER1_TOGGLE3 196 /* TIMER1 Toggle Output 3 */ +#define K210_PCF_TIMER1_TOGGLE4 197 /* TIMER1 Toggle Output 4 */ +#define K210_PCF_TIMER2_TOGGLE1 198 /* TIMER2 Toggle Output 1 */ +#define K210_PCF_TIMER2_TOGGLE2 199 /* TIMER2 Toggle Output 2 */ +#define K210_PCF_TIMER2_TOGGLE3 200 /* TIMER2 Toggle Output 3 */ +#define K210_PCF_TIMER2_TOGGLE4 201 /* TIMER2 Toggle Output 4 */ +#define K210_PCF_CLK_SPI2 202 /* Clock SPI2 */ +#define K210_PCF_CLK_I2C2 203 /* Clock I2C2 */ +#define K210_PCF_INTERNAL0 204 /* Internal function signal 0 */ +#define K210_PCF_INTERNAL1 205 /* Internal function signal 1 */ +#define K210_PCF_INTERNAL2 206 /* Internal function signal 2 */ +#define K210_PCF_INTERNAL3 207 /* Internal function signal 3 */ +#define K210_PCF_INTERNAL4 208 /* Internal function signal 4 */ +#define K210_PCF_INTERNAL5 209 /* Internal function signal 5 */ +#define K210_PCF_INTERNAL6 210 /* Internal function signal 6 */ +#define K210_PCF_INTERNAL7 211 /* Internal function signal 7 */ +#define K210_PCF_INTERNAL8 212 /* Internal function signal 8 */ +#define K210_PCF_INTERNAL9 213 /* Internal function signal 9 */ +#define K210_PCF_INTERNAL10 214 /* Internal function signal 10 */ +#define K210_PCF_INTERNAL11 215 /* Internal function signal 11 */ +#define K210_PCF_INTERNAL12 216 /* Internal function signal 12 */ +#define K210_PCF_INTERNAL13 217 /* Internal function signal 13 */ +#define K210_PCF_INTERNAL14 218 /* Internal function signal 14 */ +#define K210_PCF_INTERNAL15 219 /* Internal function signal 15 */ +#define K210_PCF_INTERNAL16 220 /* Internal function signal 16 */ +#define K210_PCF_INTERNAL17 221 /* Internal function signal 17 */ +#define K210_PCF_CONSTANT 222 /* Constant function */ +#define K210_PCF_INTERNAL18 223 /* Internal function signal 18 */ +#define K210_PCF_DEBUG0 224 /* Debug function 0 */ +#define K210_PCF_DEBUG1 225 /* Debug function 1 */ +#define K210_PCF_DEBUG2 226 /* Debug function 2 */ +#define K210_PCF_DEBUG3 227 /* Debug function 3 */ +#define K210_PCF_DEBUG4 228 /* Debug function 4 */ +#define K210_PCF_DEBUG5 229 /* Debug function 5 */ +#define K210_PCF_DEBUG6 230 /* Debug function 6 */ +#define K210_PCF_DEBUG7 231 /* Debug function 7 */ +#define K210_PCF_DEBUG8 232 /* Debug function 8 */ +#define K210_PCF_DEBUG9 233 /* Debug function 9 */ +#define K210_PCF_DEBUG10 234 /* Debug function 10 */ +#define K210_PCF_DEBUG11 235 /* Debug function 11 */ +#define K210_PCF_DEBUG12 236 /* Debug function 12 */ +#define K210_PCF_DEBUG13 237 /* Debug function 13 */ +#define K210_PCF_DEBUG14 238 /* Debug function 14 */ +#define K210_PCF_DEBUG15 239 /* Debug function 15 */ +#define K210_PCF_DEBUG16 240 /* Debug function 16 */ +#define K210_PCF_DEBUG17 241 /* Debug function 17 */ +#define K210_PCF_DEBUG18 242 /* Debug function 18 */ +#define K210_PCF_DEBUG19 243 /* Debug function 19 */ +#define K210_PCF_DEBUG20 244 /* Debug function 20 */ +#define K210_PCF_DEBUG21 245 /* Debug function 21 */ +#define K210_PCF_DEBUG22 246 /* Debug function 22 */ +#define K210_PCF_DEBUG23 247 /* Debug function 23 */ +#define K210_PCF_DEBUG24 248 /* Debug function 24 */ +#define K210_PCF_DEBUG25 249 /* Debug function 25 */ +#define K210_PCF_DEBUG26 250 /* Debug function 26 */ +#define K210_PCF_DEBUG27 251 /* Debug function 27 */ +#define K210_PCF_DEBUG28 252 /* Debug function 28 */ +#define K210_PCF_DEBUG29 253 /* Debug function 29 */ +#define K210_PCF_DEBUG30 254 /* Debug function 30 */ +#define K210_PCF_DEBUG31 255 /* Debug function 31 */ + +#define K210_FPIOA(pin, func) (((pin) << 16) | (func)) +#define K210_FPIOA_DO(pin, func) (((pin) << 16) | (1 << 8) | (func)) + +#define K210_PC_POWER_3V3 0 +#define K210_PC_POWER_1V8 1 + +#endif /* DT_K210_PINCTRL_H */ diff --git a/roms/u-boot/include/dt-bindings/pinctrl/k3.h b/roms/u-boot/include/dt-bindings/pinctrl/k3.h new file mode 100644 index 000000000..e6cb1d054 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/k3.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for TI K3-AM65 pinctrl bindings. + * + * Copyright (C) 2018-2021 Texas Instruments + */ +#ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H +#define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H + +#define PULL_DISABLE (1 << 16) +#define PULL_UP (1 << 17) +#define INPUT_EN (1 << 18) +#define SLEWCTRL_200MHZ 0 +#define SLEWCTRL_150MHZ (1 << 19) +#define SLEWCTRL_100MHZ (2 << 19) +#define SLEWCTRL_50MHZ (3 << 19) +#define TX_DIS (1 << 21) +#define ISO_OVR (1 << 22) +#define ISO_BYPASS (1 << 23) +#define DS_EN (1 << 24) +#define DS_INPUT (1 << 25) +#define DS_FORCE_OUT_HIGH (1 << 26) +#define DS_PULL_UP_DOWN_EN 0 +#define DS_PULL_UP_DOWN_DIS (1 << 27) +#define DS_PULL_UP_SEL (1 << 28) +#define WAKEUP_ENABLE (1 << 29) + +#define PIN_OUTPUT (PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (PULL_UP) +#define PIN_OUTPUT_PULLDOWN 0 +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN) + +#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#endif diff --git a/roms/u-boot/include/dt-bindings/pinctrl/omap.h b/roms/u-boot/include/dt-bindings/pinctrl/omap.h new file mode 100644 index 000000000..58fe28f15 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/omap.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for OMAP pinctrl bindings. + * + * Copyright (C) 2009 Nokia + * Copyright (C) 2009-2010 Texas Instruments + */ + +#ifndef _DT_BINDINGS_PINCTRL_OMAP_H +#define _DT_BINDINGS_PINCTRL_OMAP_H + +/* 34xx mux mode options for each pin. See TRM for options */ +#define MUX_MODE0 0 +#define MUX_MODE1 1 +#define MUX_MODE2 2 +#define MUX_MODE3 3 +#define MUX_MODE4 4 +#define MUX_MODE5 5 +#define MUX_MODE6 6 +#define MUX_MODE7 7 + +/* 24xx/34xx mux bit defines */ +#define PULL_ENA (1 << 3) +#define PULL_UP (1 << 4) +#define ALTELECTRICALSEL (1 << 5) + +/* 34xx specific mux bit defines */ +#define INPUT_EN (1 << 8) +#define OFF_EN (1 << 9) +#define OFFOUT_EN (1 << 10) +#define OFFOUT_VAL (1 << 11) +#define OFF_PULL_EN (1 << 12) +#define OFF_PULL_UP (1 << 13) +#define WAKEUP_EN (1 << 14) + +/* 44xx specific mux bit defines */ +#define WAKEUP_EVENT (1 << 15) + +/* Active pin states */ +#define PIN_OUTPUT 0 +#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) +#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) +#define PIN_INPUT INPUT_EN +#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) + +/* Off mode states */ +#define PIN_OFF_NONE 0 +#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL) +#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) +#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP) +#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN) +#define PIN_OFF_WAKEUPENABLE WAKEUP_EN + +/* + * Macros to allow using the absolute physical address instead of the + * padconf registers instead of the offset from padconf base. + */ +#define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset)) + +#define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) +#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) +#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) +#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) +#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) +#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) +#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) +#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) +#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) + +/* + * Macros to allow using the offset from the padconf physical address + * instead of the offset from padconf base. + */ +#define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset)) + +#define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) +#define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) + +/* + * Define some commonly used pins configured by the boards. + * Note that some boards use alternative pins, so check + * the schematics before using these. + */ +#define OMAP3_UART1_RX 0x152 +#define OMAP3_UART2_RX 0x14a +#define OMAP3_UART3_RX 0x16e +#define OMAP4_UART2_RX 0xdc +#define OMAP4_UART3_RX 0x104 +#define OMAP4_UART4_RX 0x11c + +#endif + diff --git a/roms/u-boot/include/dt-bindings/pinctrl/pads-imx8qm.h b/roms/u-boot/include/dt-bindings/pinctrl/pads-imx8qm.h new file mode 100644 index 000000000..e980fd55e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/pads-imx8qm.h @@ -0,0 +1,961 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_PADS_H +#define SC_PADS_H + +#define SC_P_SIM0_CLK 0 /* DMA.SIM0.CLK, LSIO.GPIO0.IO00 */ +#define SC_P_SIM0_RST 1 /* DMA.SIM0.RST, LSIO.GPIO0.IO01 */ +#define SC_P_SIM0_IO 2 /* DMA.SIM0.IO, LSIO.GPIO0.IO02 */ +#define SC_P_SIM0_PD 3 /* DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */ +#define SC_P_SIM0_POWER_EN 4 /* DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */ +#define SC_P_SIM0_GPIO0_00 5 /* DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /* */ +#define SC_P_M40_I2C0_SCL 7 /* M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */ +#define SC_P_M40_I2C0_SDA 8 /* M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */ +#define SC_P_M40_GPIO0_00 9 /* M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */ +#define SC_P_M40_GPIO0_01 10 /* M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */ +#define SC_P_M41_I2C0_SCL 11 /* M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */ +#define SC_P_M41_I2C0_SDA 12 /* M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */ +#define SC_P_M41_GPIO0_00 13 /* M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */ +#define SC_P_M41_GPIO0_01 14 /* M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */ +#define SC_P_GPT0_CLK 15 /* LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */ +#define SC_P_GPT0_CAPTURE 16 /* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */ +#define SC_P_GPT0_COMPARE 17 /* LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */ +#define SC_P_GPT1_CLK 18 /* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */ +#define SC_P_GPT1_CAPTURE 19 /* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */ +#define SC_P_GPT1_COMPARE 20 /* LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */ +#define SC_P_UART0_RX 21 /* DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */ +#define SC_P_UART0_TX 22 /* DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */ +#define SC_P_UART0_RTS_B 23 /* DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */ +#define SC_P_UART0_CTS_B 24 /* DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */ +#define SC_P_UART1_TX 25 /* DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */ +#define SC_P_UART1_RX 26 /* DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */ +#define SC_P_UART1_RTS_B 27 /* DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */ +#define SC_P_UART1_CTS_B 28 /* DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 /* */ +#define SC_P_SCU_PMIC_MEMC_ON 30 /* SCU.GPIO0.IOXX_PMIC_MEMC_ON */ +#define SC_P_SCU_WDOG_OUT 31 /* SCU.WDOG0.WDOG_OUT */ +#define SC_P_PMIC_I2C_SDA 32 /* SCU.PMIC_I2C.SDA */ +#define SC_P_PMIC_I2C_SCL 33 /* SCU.PMIC_I2C.SCL */ +#define SC_P_PMIC_EARLY_WARNING 34 /* SCU.PMIC_EARLY_WARNING */ +#define SC_P_PMIC_INT_B 35 /* SCU.DSC.PMIC_INT_B */ +#define SC_P_SCU_GPIO0_00 36 /* SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */ +#define SC_P_SCU_GPIO0_01 37 /* SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */ +#define SC_P_SCU_GPIO0_02 38 /* SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */ +#define SC_P_SCU_GPIO0_03 39 /* SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */ +#define SC_P_SCU_GPIO0_04 40 /* SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */ +#define SC_P_SCU_GPIO0_05 41 /* SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */ +#define SC_P_SCU_GPIO0_06 42 /* SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */ +#define SC_P_SCU_GPIO0_07 43 /* SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */ +#define SC_P_SCU_BOOT_MODE0 44 /* SCU.DSC.BOOT_MODE0 */ +#define SC_P_SCU_BOOT_MODE1 45 /* SCU.DSC.BOOT_MODE1 */ +#define SC_P_SCU_BOOT_MODE2 46 /* SCU.DSC.BOOT_MODE2 */ +#define SC_P_SCU_BOOT_MODE3 47 /* SCU.DSC.BOOT_MODE3 */ +#define SC_P_SCU_BOOT_MODE4 48 /* SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */ +#define SC_P_SCU_BOOT_MODE5 49 /* SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */ +#define SC_P_LVDS0_GPIO00 50 /* LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */ +#define SC_P_LVDS0_GPIO01 51 /* LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */ +#define SC_P_LVDS0_I2C0_SCL 52 /* LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */ +#define SC_P_LVDS0_I2C0_SDA 53 /* LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */ +#define SC_P_LVDS0_I2C1_SCL 54 /* LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */ +#define SC_P_LVDS0_I2C1_SDA 55 /* LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */ +#define SC_P_LVDS1_GPIO00 56 /* LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */ +#define SC_P_LVDS1_GPIO01 57 /* LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */ +#define SC_P_LVDS1_I2C0_SCL 58 /* LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */ +#define SC_P_LVDS1_I2C0_SDA 59 /* LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */ +#define SC_P_LVDS1_I2C1_SCL 60 /* LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */ +#define SC_P_LVDS1_I2C1_SDA 61 /* LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 /* */ +#define SC_P_MIPI_DSI0_I2C0_SCL 63 /* MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */ +#define SC_P_MIPI_DSI0_I2C0_SDA 64 /* MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */ +#define SC_P_MIPI_DSI0_GPIO0_00 65 /* MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */ +#define SC_P_MIPI_DSI0_GPIO0_01 66 /* MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */ +#define SC_P_MIPI_DSI1_I2C0_SCL 67 /* MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */ +#define SC_P_MIPI_DSI1_I2C0_SDA 68 /* MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */ +#define SC_P_MIPI_DSI1_GPIO0_00 69 /* MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */ +#define SC_P_MIPI_DSI1_GPIO0_01 70 /* MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 /* */ +#define SC_P_MIPI_CSI0_MCLK_OUT 72 /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */ +#define SC_P_MIPI_CSI0_I2C0_SCL 73 /* MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */ +#define SC_P_MIPI_CSI0_I2C0_SDA 74 /* MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */ +#define SC_P_MIPI_CSI0_GPIO0_00 75 /* MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */ +#define SC_P_MIPI_CSI0_GPIO0_01 76 /* MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */ +#define SC_P_MIPI_CSI1_MCLK_OUT 77 /* MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */ +#define SC_P_MIPI_CSI1_GPIO0_00 78 /* MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */ +#define SC_P_MIPI_CSI1_GPIO0_01 79 /* MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */ +#define SC_P_MIPI_CSI1_I2C0_SCL 80 /* MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */ +#define SC_P_MIPI_CSI1_I2C0_SDA 81 /* MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */ +#define SC_P_HDMI_TX0_TS_SCL 82 /* HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */ +#define SC_P_HDMI_TX0_TS_SDA 83 /* HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */ +#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /* */ +#define SC_P_ESAI1_FSR 85 /* AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */ +#define SC_P_ESAI1_FST 86 /* AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */ +#define SC_P_ESAI1_SCKR 87 /* AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */ +#define SC_P_ESAI1_SCKT 88 /* AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */ +#define SC_P_ESAI1_TX0 89 /* AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */ +#define SC_P_ESAI1_TX1 90 /* AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */ +#define SC_P_ESAI1_TX2_RX3 91 /* AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */ +#define SC_P_ESAI1_TX3_RX2 92 /* AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */ +#define SC_P_ESAI1_TX4_RX1 93 /* AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */ +#define SC_P_ESAI1_TX5_RX0 94 /* AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */ +#define SC_P_SPDIF0_RX 95 /* AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */ +#define SC_P_SPDIF0_TX 96 /* AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */ +#define SC_P_SPDIF0_EXT_CLK 97 /* AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */ +#define SC_P_SPI3_SCK 98 /* DMA.SPI3.SCK, LSIO.GPIO2.IO17 */ +#define SC_P_SPI3_SDO 99 /* DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */ +#define SC_P_SPI3_SDI 100 /* DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */ +#define SC_P_SPI3_CS0 101 /* DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */ +#define SC_P_SPI3_CS1 102 /* DMA.SPI3.CS1, LSIO.GPIO2.IO21 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 /* */ +#define SC_P_ESAI0_FSR 104 /* AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */ +#define SC_P_ESAI0_FST 105 /* AUD.ESAI0.FST, LSIO.GPIO2.IO23 */ +#define SC_P_ESAI0_SCKR 106 /* AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */ +#define SC_P_ESAI0_SCKT 107 /* AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */ +#define SC_P_ESAI0_TX0 108 /* AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */ +#define SC_P_ESAI0_TX1 109 /* AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */ +#define SC_P_ESAI0_TX2_RX3 110 /* AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */ +#define SC_P_ESAI0_TX3_RX2 111 /* AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */ +#define SC_P_ESAI0_TX4_RX1 112 /* AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */ +#define SC_P_ESAI0_TX5_RX0 113 /* AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */ +#define SC_P_MCLK_IN0 114 /* AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */ +#define SC_P_MCLK_OUT0 115 /* AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /* */ +#define SC_P_SPI0_SCK 117 /* DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */ +#define SC_P_SPI0_SDO 118 /* DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */ +#define SC_P_SPI0_SDI 119 /* DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */ +#define SC_P_SPI0_CS0 120 /* DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */ +#define SC_P_SPI0_CS1 121 /* DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */ +#define SC_P_SPI2_SCK 122 /* DMA.SPI2.SCK, LSIO.GPIO3.IO07 */ +#define SC_P_SPI2_SDO 123 /* DMA.SPI2.SDO, LSIO.GPIO3.IO08 */ +#define SC_P_SPI2_SDI 124 /* DMA.SPI2.SDI, LSIO.GPIO3.IO09 */ +#define SC_P_SPI2_CS0 125 /* DMA.SPI2.CS0, LSIO.GPIO3.IO10 */ +#define SC_P_SPI2_CS1 126 /* DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */ +#define SC_P_SAI1_RXC 127 /* AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */ +#define SC_P_SAI1_RXD 128 /* AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */ +#define SC_P_SAI1_RXFS 129 /* AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */ +#define SC_P_SAI1_TXC 130 /* AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */ +#define SC_P_SAI1_TXD 131 /* AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */ +#define SC_P_SAI1_TXFS 132 /* AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 /* */ +#define SC_P_ADC_IN7 134 /* DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */ +#define SC_P_ADC_IN6 135 /* DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */ +#define SC_P_ADC_IN5 136 /* DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */ +#define SC_P_ADC_IN4 137 /* DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */ +#define SC_P_ADC_IN3 138 /* DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */ +#define SC_P_ADC_IN2 139 /* DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */ +#define SC_P_ADC_IN1 140 /* DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */ +#define SC_P_ADC_IN0 141 /* DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */ +#define SC_P_MLB_SIG 142 /* CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */ +#define SC_P_MLB_CLK 143 /* CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */ +#define SC_P_MLB_DATA 144 /* CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 /* */ +#define SC_P_FLEXCAN0_RX 146 /* DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */ +#define SC_P_FLEXCAN0_TX 147 /* DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */ +#define SC_P_FLEXCAN1_RX 148 /* DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */ +#define SC_P_FLEXCAN1_TX 149 /* DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */ +#define SC_P_FLEXCAN2_RX 150 /* DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */ +#define SC_P_FLEXCAN2_TX 151 /* DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 /* */ +#define SC_P_USB_SS3_TC0 153 /* DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */ +#define SC_P_USB_SS3_TC1 154 /* DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 155 /* DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */ +#define SC_P_USB_SS3_TC3 156 /* DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157 /* */ +#define SC_P_USDHC1_RESET_B 158 /* CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */ +#define SC_P_USDHC1_VSELECT 159 /* CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */ +#define SC_P_USDHC2_RESET_B 160 /* CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */ +#define SC_P_USDHC2_VSELECT 161 /* CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */ +#define SC_P_USDHC2_WP 162 /* CONN.USDHC2.WP, LSIO.GPIO4.IO11 */ +#define SC_P_USDHC2_CD_B 163 /* CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 /* */ +#define SC_P_ENET0_MDIO 165 /* CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */ +#define SC_P_ENET0_MDC 166 /* CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */ +#define SC_P_ENET0_REFCLK_125M_25M 167 /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */ +#define SC_P_ENET1_REFCLK_125M_25M 168 /* CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */ +#define SC_P_ENET1_MDIO 169 /* CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */ +#define SC_P_ENET1_MDC 170 /* CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 /* */ +#define SC_P_QSPI1A_SS0_B 172 /* LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */ +#define SC_P_QSPI1A_SS1_B 173 /* LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */ +#define SC_P_QSPI1A_SCLK 174 /* LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */ +#define SC_P_QSPI1A_DQS 175 /* LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */ +#define SC_P_QSPI1A_DATA3 176 /* LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */ +#define SC_P_QSPI1A_DATA2 177 /* LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */ +#define SC_P_QSPI1A_DATA1 178 /* LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */ +#define SC_P_QSPI1A_DATA0 179 /* LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /* */ +#define SC_P_QSPI0A_DATA0 181 /* LSIO.QSPI0A.DATA0 */ +#define SC_P_QSPI0A_DATA1 182 /* LSIO.QSPI0A.DATA1 */ +#define SC_P_QSPI0A_DATA2 183 /* LSIO.QSPI0A.DATA2 */ +#define SC_P_QSPI0A_DATA3 184 /* LSIO.QSPI0A.DATA3 */ +#define SC_P_QSPI0A_DQS 185 /* LSIO.QSPI0A.DQS */ +#define SC_P_QSPI0A_SS0_B 186 /* LSIO.QSPI0A.SS0_B */ +#define SC_P_QSPI0A_SS1_B 187 /* LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */ +#define SC_P_QSPI0A_SCLK 188 /* LSIO.QSPI0A.SCLK */ +#define SC_P_QSPI0B_SCLK 189 /* LSIO.QSPI0B.SCLK */ +#define SC_P_QSPI0B_DATA0 190 /* LSIO.QSPI0B.DATA0 */ +#define SC_P_QSPI0B_DATA1 191 /* LSIO.QSPI0B.DATA1 */ +#define SC_P_QSPI0B_DATA2 192 /* LSIO.QSPI0B.DATA2 */ +#define SC_P_QSPI0B_DATA3 193 /* LSIO.QSPI0B.DATA3 */ +#define SC_P_QSPI0B_DQS 194 /* LSIO.QSPI0B.DQS */ +#define SC_P_QSPI0B_SS0_B 195 /* LSIO.QSPI0B.SS0_B */ +#define SC_P_QSPI0B_SS1_B 196 /* LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 /* */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */ +#define SC_P_PCIE_CTRL0_WAKE_B 199 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */ +#define SC_P_PCIE_CTRL0_PERST_B 200 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */ +#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /* HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */ +#define SC_P_PCIE_CTRL1_WAKE_B 202 /* HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */ +#define SC_P_PCIE_CTRL1_PERST_B 203 /* HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /* */ +#define SC_P_USB_HSIC0_DATA 205 /* CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */ +#define SC_P_USB_HSIC0_STROBE 206 /* CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */ +#define SC_P_CALIBRATION_0_HSIC 207 /* */ +#define SC_P_CALIBRATION_1_HSIC 208 /* */ +#define SC_P_EMMC0_CLK 209 /* CONN.EMMC0.CLK, CONN.NAND.READY_B */ +#define SC_P_EMMC0_CMD 210 /* CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */ +#define SC_P_EMMC0_DATA0 211 /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */ +#define SC_P_EMMC0_DATA1 212 /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */ +#define SC_P_EMMC0_DATA2 213 /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */ +#define SC_P_EMMC0_DATA3 214 /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */ +#define SC_P_EMMC0_DATA4 215 /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */ +#define SC_P_EMMC0_DATA5 216 /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */ +#define SC_P_EMMC0_DATA6 217 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */ +#define SC_P_EMMC0_DATA7 218 /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */ +#define SC_P_EMMC0_STROBE 219 /* CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */ +#define SC_P_EMMC0_RESET_B 220 /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /* */ +#define SC_P_USDHC1_CLK 222 /* CONN.USDHC1.CLK, AUD.MQS.R */ +#define SC_P_USDHC1_CMD 223 /* CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */ +#define SC_P_USDHC1_DATA0 224 /* CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */ +#define SC_P_USDHC1_DATA1 225 /* CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */ +#define SC_P_CTL_NAND_RE_P_N 226 /* */ +#define SC_P_USDHC1_DATA2 227 /* CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */ +#define SC_P_USDHC1_DATA3 228 /* CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */ +#define SC_P_CTL_NAND_DQS_P_N 229 /* */ +#define SC_P_USDHC1_DATA4 230 /* CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */ +#define SC_P_USDHC1_DATA5 231 /* CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */ +#define SC_P_USDHC1_DATA6 232 /* CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */ +#define SC_P_USDHC1_DATA7 233 /* CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */ +#define SC_P_USDHC1_STROBE 234 /* CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /* */ +#define SC_P_USDHC2_CLK 236 /* CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */ +#define SC_P_USDHC2_CMD 237 /* CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */ +#define SC_P_USDHC2_DATA0 238 /* CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */ +#define SC_P_USDHC2_DATA1 239 /* CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */ +#define SC_P_USDHC2_DATA2 240 /* CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */ +#define SC_P_USDHC2_DATA3 241 /* CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 /* */ +#define SC_P_ENET0_RGMII_TXC 243 /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */ +#define SC_P_ENET0_RGMII_TX_CTL 244 /* CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */ +#define SC_P_ENET0_RGMII_TXD0 245 /* CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */ +#define SC_P_ENET0_RGMII_TXD1 246 /* CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */ +#define SC_P_ENET0_RGMII_TXD2 247 /* CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */ +#define SC_P_ENET0_RGMII_TXD3 248 /* CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */ +#define SC_P_ENET0_RGMII_RXC 249 /* CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */ +#define SC_P_ENET0_RGMII_RX_CTL 250 /* CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */ +#define SC_P_ENET0_RGMII_RXD0 251 /* CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */ +#define SC_P_ENET0_RGMII_RXD1 252 /* CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */ +#define SC_P_ENET0_RGMII_RXD2 253 /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */ +#define SC_P_ENET0_RGMII_RXD3 254 /* CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /* */ +#define SC_P_ENET1_RGMII_TXC 256 /* CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */ +#define SC_P_ENET1_RGMII_TX_CTL 257 /* CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */ +#define SC_P_ENET1_RGMII_TXD0 258 /* CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */ +#define SC_P_ENET1_RGMII_TXD1 259 /* CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */ +#define SC_P_ENET1_RGMII_TXD2 260 /* CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */ +#define SC_P_ENET1_RGMII_TXD3 261 /* CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */ +#define SC_P_ENET1_RGMII_RXC 262 /* CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */ +#define SC_P_ENET1_RGMII_RX_CTL 263 /* CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */ +#define SC_P_ENET1_RGMII_RXD0 264 /* CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */ +#define SC_P_ENET1_RGMII_RXD1 265 /* CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */ +#define SC_P_ENET1_RGMII_RXD2 266 /* CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */ +#define SC_P_ENET1_RGMII_RXD3 267 /* CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /* */ +/*@}*/ + +/*! + * @name Pad Mux Definitions + * format: name padid padmux + */ +/*@{*/ +#define SC_P_SIM0_CLK_DMA_SIM0_CLK SC_P_SIM0_CLK 0 +#define SC_P_SIM0_CLK_LSIO_GPIO0_IO00 SC_P_SIM0_CLK 3 +#define SC_P_SIM0_RST_DMA_SIM0_RST SC_P_SIM0_RST 0 +#define SC_P_SIM0_RST_LSIO_GPIO0_IO01 SC_P_SIM0_RST 3 +#define SC_P_SIM0_IO_DMA_SIM0_IO SC_P_SIM0_IO 0 +#define SC_P_SIM0_IO_LSIO_GPIO0_IO02 SC_P_SIM0_IO 3 +#define SC_P_SIM0_PD_DMA_SIM0_PD SC_P_SIM0_PD 0 +#define SC_P_SIM0_PD_DMA_I2C3_SCL SC_P_SIM0_PD 1 +#define SC_P_SIM0_PD_LSIO_GPIO0_IO03 SC_P_SIM0_PD 3 +#define SC_P_SIM0_POWER_EN_DMA_SIM0_POWER_EN SC_P_SIM0_POWER_EN 0 +#define SC_P_SIM0_POWER_EN_DMA_I2C3_SDA SC_P_SIM0_POWER_EN 1 +#define SC_P_SIM0_POWER_EN_LSIO_GPIO0_IO04 SC_P_SIM0_POWER_EN 3 +#define SC_P_SIM0_GPIO0_00_DMA_SIM0_POWER_EN SC_P_SIM0_GPIO0_00 0 +#define SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05 SC_P_SIM0_GPIO0_00 3 +#define SC_P_M40_I2C0_SCL_M40_I2C0_SCL SC_P_M40_I2C0_SCL 0 +#define SC_P_M40_I2C0_SCL_M40_UART0_RX SC_P_M40_I2C0_SCL 1 +#define SC_P_M40_I2C0_SCL_M40_GPIO0_IO02 SC_P_M40_I2C0_SCL 2 +#define SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06 SC_P_M40_I2C0_SCL 3 +#define SC_P_M40_I2C0_SDA_M40_I2C0_SDA SC_P_M40_I2C0_SDA 0 +#define SC_P_M40_I2C0_SDA_M40_UART0_TX SC_P_M40_I2C0_SDA 1 +#define SC_P_M40_I2C0_SDA_M40_GPIO0_IO03 SC_P_M40_I2C0_SDA 2 +#define SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07 SC_P_M40_I2C0_SDA 3 +#define SC_P_M40_GPIO0_00_M40_GPIO0_IO00 SC_P_M40_GPIO0_00 0 +#define SC_P_M40_GPIO0_00_M40_TPM0_CH0 SC_P_M40_GPIO0_00 1 +#define SC_P_M40_GPIO0_00_DMA_UART4_RX SC_P_M40_GPIO0_00 2 +#define SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 SC_P_M40_GPIO0_00 3 +#define SC_P_M40_GPIO0_01_M40_GPIO0_IO01 SC_P_M40_GPIO0_01 0 +#define SC_P_M40_GPIO0_01_M40_TPM0_CH1 SC_P_M40_GPIO0_01 1 +#define SC_P_M40_GPIO0_01_DMA_UART4_TX SC_P_M40_GPIO0_01 2 +#define SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 SC_P_M40_GPIO0_01 3 +#define SC_P_M41_I2C0_SCL_M41_I2C0_SCL SC_P_M41_I2C0_SCL 0 +#define SC_P_M41_I2C0_SCL_M41_UART0_RX SC_P_M41_I2C0_SCL 1 +#define SC_P_M41_I2C0_SCL_M41_GPIO0_IO02 SC_P_M41_I2C0_SCL 2 +#define SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10 SC_P_M41_I2C0_SCL 3 +#define SC_P_M41_I2C0_SDA_M41_I2C0_SDA SC_P_M41_I2C0_SDA 0 +#define SC_P_M41_I2C0_SDA_M41_UART0_TX SC_P_M41_I2C0_SDA 1 +#define SC_P_M41_I2C0_SDA_M41_GPIO0_IO03 SC_P_M41_I2C0_SDA 2 +#define SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11 SC_P_M41_I2C0_SDA 3 +#define SC_P_M41_GPIO0_00_M41_GPIO0_IO00 SC_P_M41_GPIO0_00 0 +#define SC_P_M41_GPIO0_00_M41_TPM0_CH0 SC_P_M41_GPIO0_00 1 +#define SC_P_M41_GPIO0_00_DMA_UART3_RX SC_P_M41_GPIO0_00 2 +#define SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12 SC_P_M41_GPIO0_00 3 +#define SC_P_M41_GPIO0_01_M41_GPIO0_IO01 SC_P_M41_GPIO0_01 0 +#define SC_P_M41_GPIO0_01_M41_TPM0_CH1 SC_P_M41_GPIO0_01 1 +#define SC_P_M41_GPIO0_01_DMA_UART3_TX SC_P_M41_GPIO0_01 2 +#define SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13 SC_P_M41_GPIO0_01 3 +#define SC_P_GPT0_CLK_LSIO_GPT0_CLK SC_P_GPT0_CLK 0 +#define SC_P_GPT0_CLK_DMA_I2C1_SCL SC_P_GPT0_CLK 1 +#define SC_P_GPT0_CLK_LSIO_KPP0_COL4 SC_P_GPT0_CLK 2 +#define SC_P_GPT0_CLK_LSIO_GPIO0_IO14 SC_P_GPT0_CLK 3 +#define SC_P_GPT0_CAPTURE_LSIO_GPT0_CAPTURE SC_P_GPT0_CAPTURE 0 +#define SC_P_GPT0_CAPTURE_DMA_I2C1_SDA SC_P_GPT0_CAPTURE 1 +#define SC_P_GPT0_CAPTURE_LSIO_KPP0_COL5 SC_P_GPT0_CAPTURE 2 +#define SC_P_GPT0_CAPTURE_LSIO_GPIO0_IO15 SC_P_GPT0_CAPTURE 3 +#define SC_P_GPT0_COMPARE_LSIO_GPT0_COMPARE SC_P_GPT0_COMPARE 0 +#define SC_P_GPT0_COMPARE_LSIO_PWM3_OUT SC_P_GPT0_COMPARE 1 +#define SC_P_GPT0_COMPARE_LSIO_KPP0_COL6 SC_P_GPT0_COMPARE 2 +#define SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16 SC_P_GPT0_COMPARE 3 +#define SC_P_GPT1_CLK_LSIO_GPT1_CLK SC_P_GPT1_CLK 0 +#define SC_P_GPT1_CLK_DMA_I2C2_SCL SC_P_GPT1_CLK 1 +#define SC_P_GPT1_CLK_LSIO_KPP0_COL7 SC_P_GPT1_CLK 2 +#define SC_P_GPT1_CLK_LSIO_GPIO0_IO17 SC_P_GPT1_CLK 3 +#define SC_P_GPT1_CAPTURE_LSIO_GPT1_CAPTURE SC_P_GPT1_CAPTURE 0 +#define SC_P_GPT1_CAPTURE_DMA_I2C2_SDA SC_P_GPT1_CAPTURE 1 +#define SC_P_GPT1_CAPTURE_LSIO_KPP0_ROW4 SC_P_GPT1_CAPTURE 2 +#define SC_P_GPT1_CAPTURE_LSIO_GPIO0_IO18 SC_P_GPT1_CAPTURE 3 +#define SC_P_GPT1_COMPARE_LSIO_GPT1_COMPARE SC_P_GPT1_COMPARE 0 +#define SC_P_GPT1_COMPARE_LSIO_PWM2_OUT SC_P_GPT1_COMPARE 1 +#define SC_P_GPT1_COMPARE_LSIO_KPP0_ROW5 SC_P_GPT1_COMPARE 2 +#define SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19 SC_P_GPT1_COMPARE 3 +#define SC_P_UART0_RX_DMA_UART0_RX SC_P_UART0_RX 0 +#define SC_P_UART0_RX_SCU_UART0_RX SC_P_UART0_RX 1 +#define SC_P_UART0_RX_LSIO_GPIO0_IO20 SC_P_UART0_RX 3 +#define SC_P_UART0_TX_DMA_UART0_TX SC_P_UART0_TX 0 +#define SC_P_UART0_TX_SCU_UART0_TX SC_P_UART0_TX 1 +#define SC_P_UART0_TX_LSIO_GPIO0_IO21 SC_P_UART0_TX 3 +#define SC_P_UART0_RTS_B_DMA_UART0_RTS_B SC_P_UART0_RTS_B 0 +#define SC_P_UART0_RTS_B_LSIO_PWM0_OUT SC_P_UART0_RTS_B 1 +#define SC_P_UART0_RTS_B_DMA_UART2_RX SC_P_UART0_RTS_B 2 +#define SC_P_UART0_RTS_B_LSIO_GPIO0_IO22 SC_P_UART0_RTS_B 3 +#define SC_P_UART0_CTS_B_DMA_UART0_CTS_B SC_P_UART0_CTS_B 0 +#define SC_P_UART0_CTS_B_LSIO_PWM1_OUT SC_P_UART0_CTS_B 1 +#define SC_P_UART0_CTS_B_DMA_UART2_TX SC_P_UART0_CTS_B 2 +#define SC_P_UART0_CTS_B_LSIO_GPIO0_IO23 SC_P_UART0_CTS_B 3 +#define SC_P_UART1_TX_DMA_UART1_TX SC_P_UART1_TX 0 +#define SC_P_UART1_TX_DMA_SPI3_SCK SC_P_UART1_TX 1 +#define SC_P_UART1_TX_LSIO_GPIO0_IO24 SC_P_UART1_TX 3 +#define SC_P_UART1_RX_DMA_UART1_RX SC_P_UART1_RX 0 +#define SC_P_UART1_RX_DMA_SPI3_SDO SC_P_UART1_RX 1 +#define SC_P_UART1_RX_LSIO_GPIO0_IO25 SC_P_UART1_RX 3 +#define SC_P_UART1_RTS_B_DMA_UART1_RTS_B SC_P_UART1_RTS_B 0 +#define SC_P_UART1_RTS_B_DMA_SPI3_SDI SC_P_UART1_RTS_B 1 +#define SC_P_UART1_RTS_B_DMA_UART1_CTS_B SC_P_UART1_RTS_B 2 +#define SC_P_UART1_RTS_B_LSIO_GPIO0_IO26 SC_P_UART1_RTS_B 3 +#define SC_P_UART1_CTS_B_DMA_UART1_CTS_B SC_P_UART1_CTS_B 0 +#define SC_P_UART1_CTS_B_DMA_SPI3_CS0 SC_P_UART1_CTS_B 1 +#define SC_P_UART1_CTS_B_DMA_UART1_RTS_B SC_P_UART1_CTS_B 2 +#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO27 SC_P_UART1_CTS_B 3 +#define SC_P_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON SC_P_SCU_PMIC_MEMC_ON 0 +#define SC_P_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT SC_P_SCU_WDOG_OUT 0 +#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0 +#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0 +#define SC_P_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING SC_P_PMIC_EARLY_WARNING 0 +#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0 +#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0 +#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1 +#define SC_P_SCU_GPIO0_00_LSIO_GPIO0_IO28 SC_P_SCU_GPIO0_00 3 +#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0 +#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1 +#define SC_P_SCU_GPIO0_01_LSIO_GPIO0_IO29 SC_P_SCU_GPIO0_01 3 +#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IO02 SC_P_SCU_GPIO0_02 0 +#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON SC_P_SCU_GPIO0_02 1 +#define SC_P_SCU_GPIO0_02_LSIO_GPIO0_IO30 SC_P_SCU_GPIO0_02 3 +#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IO03 SC_P_SCU_GPIO0_03 0 +#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON SC_P_SCU_GPIO0_03 1 +#define SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 SC_P_SCU_GPIO0_03 3 +#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IO04 SC_P_SCU_GPIO0_04 0 +#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON SC_P_SCU_GPIO0_04 1 +#define SC_P_SCU_GPIO0_04_LSIO_GPIO1_IO00 SC_P_SCU_GPIO0_04 3 +#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IO05 SC_P_SCU_GPIO0_05 0 +#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON SC_P_SCU_GPIO0_05 1 +#define SC_P_SCU_GPIO0_05_LSIO_GPIO1_IO01 SC_P_SCU_GPIO0_05 3 +#define SC_P_SCU_GPIO0_06_SCU_GPIO0_IO06 SC_P_SCU_GPIO0_06 0 +#define SC_P_SCU_GPIO0_06_SCU_TPM0_CH0 SC_P_SCU_GPIO0_06 1 +#define SC_P_SCU_GPIO0_06_LSIO_GPIO1_IO02 SC_P_SCU_GPIO0_06 3 +#define SC_P_SCU_GPIO0_07_SCU_GPIO0_IO07 SC_P_SCU_GPIO0_07 0 +#define SC_P_SCU_GPIO0_07_SCU_TPM0_CH1 SC_P_SCU_GPIO0_07 1 +#define SC_P_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_GPIO0_07 2 +#define SC_P_SCU_GPIO0_07_LSIO_GPIO1_IO03 SC_P_SCU_GPIO0_07 3 +#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0 +#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0 +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0 +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0 +#define SC_P_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4 SC_P_SCU_BOOT_MODE4 0 +#define SC_P_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE4 1 +#define SC_P_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5 SC_P_SCU_BOOT_MODE5 0 +#define SC_P_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE5 1 +#define SC_P_LVDS0_GPIO00_LVDS0_GPIO0_IO00 SC_P_LVDS0_GPIO00 0 +#define SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT SC_P_LVDS0_GPIO00 1 +#define SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04 SC_P_LVDS0_GPIO00 3 +#define SC_P_LVDS0_GPIO01_LVDS0_GPIO0_IO01 SC_P_LVDS0_GPIO01 0 +#define SC_P_LVDS0_GPIO01_LSIO_GPIO1_IO05 SC_P_LVDS0_GPIO01 3 +#define SC_P_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL SC_P_LVDS0_I2C0_SCL 0 +#define SC_P_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02 SC_P_LVDS0_I2C0_SCL 1 +#define SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 SC_P_LVDS0_I2C0_SCL 3 +#define SC_P_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA SC_P_LVDS0_I2C0_SDA 0 +#define SC_P_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03 SC_P_LVDS0_I2C0_SDA 1 +#define SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 SC_P_LVDS0_I2C0_SDA 3 +#define SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL SC_P_LVDS0_I2C1_SCL 0 +#define SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX SC_P_LVDS0_I2C1_SCL 1 +#define SC_P_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08 SC_P_LVDS0_I2C1_SCL 3 +#define SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA SC_P_LVDS0_I2C1_SDA 0 +#define SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX SC_P_LVDS0_I2C1_SDA 1 +#define SC_P_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09 SC_P_LVDS0_I2C1_SDA 3 +#define SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00 SC_P_LVDS1_GPIO00 0 +#define SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT SC_P_LVDS1_GPIO00 1 +#define SC_P_LVDS1_GPIO00_LSIO_GPIO1_IO10 SC_P_LVDS1_GPIO00 3 +#define SC_P_LVDS1_GPIO01_LVDS1_GPIO0_IO01 SC_P_LVDS1_GPIO01 0 +#define SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 SC_P_LVDS1_GPIO01 3 +#define SC_P_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL SC_P_LVDS1_I2C0_SCL 0 +#define SC_P_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02 SC_P_LVDS1_I2C0_SCL 1 +#define SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 SC_P_LVDS1_I2C0_SCL 3 +#define SC_P_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA SC_P_LVDS1_I2C0_SDA 0 +#define SC_P_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03 SC_P_LVDS1_I2C0_SDA 1 +#define SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 SC_P_LVDS1_I2C0_SDA 3 +#define SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL SC_P_LVDS1_I2C1_SCL 0 +#define SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX SC_P_LVDS1_I2C1_SCL 1 +#define SC_P_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14 SC_P_LVDS1_I2C1_SCL 3 +#define SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA SC_P_LVDS1_I2C1_SDA 0 +#define SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX SC_P_LVDS1_I2C1_SDA 1 +#define SC_P_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15 SC_P_LVDS1_I2C1_SDA 3 +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0 +#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16 SC_P_MIPI_DSI0_I2C0_SCL 3 +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0 +#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17 SC_P_MIPI_DSI0_I2C0_SDA 3 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 1 +#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18 SC_P_MIPI_DSI0_GPIO0_00 3 +#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0 +#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 SC_P_MIPI_DSI0_GPIO0_01 3 +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0 +#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 SC_P_MIPI_DSI1_I2C0_SCL 3 +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0 +#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 SC_P_MIPI_DSI1_I2C0_SDA 3 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 1 +#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 SC_P_MIPI_DSI1_GPIO0_00 3 +#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0 +#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 SC_P_MIPI_DSI1_GPIO0_01 3 +#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0 +#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 SC_P_MIPI_CSI0_MCLK_OUT 3 +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0 +#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_CSI0_I2C0_SCL 3 +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0 +#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_CSI0_I2C0_SDA 3 +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0 +#define SC_P_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1 +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 2 +#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_CSI0_GPIO0_00 3 +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0 +#define SC_P_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1 +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 2 +#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_CSI0_GPIO0_01 3 +#define SC_P_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT SC_P_MIPI_CSI1_MCLK_OUT 0 +#define SC_P_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 SC_P_MIPI_CSI1_MCLK_OUT 3 +#define SC_P_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 SC_P_MIPI_CSI1_GPIO0_00 0 +#define SC_P_MIPI_CSI1_GPIO0_00_DMA_UART4_RX SC_P_MIPI_CSI1_GPIO0_00 1 +#define SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 SC_P_MIPI_CSI1_GPIO0_00 3 +#define SC_P_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 SC_P_MIPI_CSI1_GPIO0_01 0 +#define SC_P_MIPI_CSI1_GPIO0_01_DMA_UART4_TX SC_P_MIPI_CSI1_GPIO0_01 1 +#define SC_P_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 SC_P_MIPI_CSI1_GPIO0_01 3 +#define SC_P_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL SC_P_MIPI_CSI1_I2C0_SCL 0 +#define SC_P_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00 SC_P_MIPI_CSI1_I2C0_SCL 3 +#define SC_P_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA SC_P_MIPI_CSI1_I2C0_SDA 0 +#define SC_P_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01 SC_P_MIPI_CSI1_I2C0_SDA 3 +#define SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL SC_P_HDMI_TX0_TS_SCL 0 +#define SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL SC_P_HDMI_TX0_TS_SCL 1 +#define SC_P_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02 SC_P_HDMI_TX0_TS_SCL 3 +#define SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA SC_P_HDMI_TX0_TS_SDA 0 +#define SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA SC_P_HDMI_TX0_TS_SDA 1 +#define SC_P_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03 SC_P_HDMI_TX0_TS_SDA 3 +#define SC_P_ESAI1_FSR_AUD_ESAI1_FSR SC_P_ESAI1_FSR 0 +#define SC_P_ESAI1_FSR_LSIO_GPIO2_IO04 SC_P_ESAI1_FSR 3 +#define SC_P_ESAI1_FST_AUD_ESAI1_FST SC_P_ESAI1_FST 0 +#define SC_P_ESAI1_FST_AUD_SPDIF0_EXT_CLK SC_P_ESAI1_FST 1 +#define SC_P_ESAI1_FST_LSIO_GPIO2_IO05 SC_P_ESAI1_FST 3 +#define SC_P_ESAI1_SCKR_AUD_ESAI1_SCKR SC_P_ESAI1_SCKR 0 +#define SC_P_ESAI1_SCKR_LSIO_GPIO2_IO06 SC_P_ESAI1_SCKR 3 +#define SC_P_ESAI1_SCKT_AUD_ESAI1_SCKT SC_P_ESAI1_SCKT 0 +#define SC_P_ESAI1_SCKT_AUD_SAI2_RXC SC_P_ESAI1_SCKT 1 +#define SC_P_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK SC_P_ESAI1_SCKT 2 +#define SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 SC_P_ESAI1_SCKT 3 +#define SC_P_ESAI1_TX0_AUD_ESAI1_TX0 SC_P_ESAI1_TX0 0 +#define SC_P_ESAI1_TX0_AUD_SAI2_RXD SC_P_ESAI1_TX0 1 +#define SC_P_ESAI1_TX0_AUD_SPDIF0_RX SC_P_ESAI1_TX0 2 +#define SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 SC_P_ESAI1_TX0 3 +#define SC_P_ESAI1_TX1_AUD_ESAI1_TX1 SC_P_ESAI1_TX1 0 +#define SC_P_ESAI1_TX1_AUD_SAI2_RXFS SC_P_ESAI1_TX1 1 +#define SC_P_ESAI1_TX1_AUD_SPDIF0_TX SC_P_ESAI1_TX1 2 +#define SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 SC_P_ESAI1_TX1 3 +#define SC_P_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3 SC_P_ESAI1_TX2_RX3 0 +#define SC_P_ESAI1_TX2_RX3_AUD_SPDIF0_RX SC_P_ESAI1_TX2_RX3 1 +#define SC_P_ESAI1_TX2_RX3_LSIO_GPIO2_IO10 SC_P_ESAI1_TX2_RX3 3 +#define SC_P_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2 SC_P_ESAI1_TX3_RX2 0 +#define SC_P_ESAI1_TX3_RX2_AUD_SPDIF0_TX SC_P_ESAI1_TX3_RX2 1 +#define SC_P_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 SC_P_ESAI1_TX3_RX2 3 +#define SC_P_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1 SC_P_ESAI1_TX4_RX1 0 +#define SC_P_ESAI1_TX4_RX1_LSIO_GPIO2_IO12 SC_P_ESAI1_TX4_RX1 3 +#define SC_P_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0 SC_P_ESAI1_TX5_RX0 0 +#define SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 SC_P_ESAI1_TX5_RX0 3 +#define SC_P_SPDIF0_RX_AUD_SPDIF0_RX SC_P_SPDIF0_RX 0 +#define SC_P_SPDIF0_RX_AUD_MQS_R SC_P_SPDIF0_RX 1 +#define SC_P_SPDIF0_RX_AUD_ACM_MCLK_IN1 SC_P_SPDIF0_RX 2 +#define SC_P_SPDIF0_RX_LSIO_GPIO2_IO14 SC_P_SPDIF0_RX 3 +#define SC_P_SPDIF0_TX_AUD_SPDIF0_TX SC_P_SPDIF0_TX 0 +#define SC_P_SPDIF0_TX_AUD_MQS_L SC_P_SPDIF0_TX 1 +#define SC_P_SPDIF0_TX_AUD_ACM_MCLK_OUT1 SC_P_SPDIF0_TX 2 +#define SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 SC_P_SPDIF0_TX 3 +#define SC_P_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0 +#define SC_P_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0 SC_P_SPDIF0_EXT_CLK 1 +#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 SC_P_SPDIF0_EXT_CLK 3 +#define SC_P_SPI3_SCK_DMA_SPI3_SCK SC_P_SPI3_SCK 0 +#define SC_P_SPI3_SCK_LSIO_GPIO2_IO17 SC_P_SPI3_SCK 3 +#define SC_P_SPI3_SDO_DMA_SPI3_SDO SC_P_SPI3_SDO 0 +#define SC_P_SPI3_SDO_DMA_FTM_CH0 SC_P_SPI3_SDO 1 +#define SC_P_SPI3_SDO_LSIO_GPIO2_IO18 SC_P_SPI3_SDO 3 +#define SC_P_SPI3_SDI_DMA_SPI3_SDI SC_P_SPI3_SDI 0 +#define SC_P_SPI3_SDI_DMA_FTM_CH1 SC_P_SPI3_SDI 1 +#define SC_P_SPI3_SDI_LSIO_GPIO2_IO19 SC_P_SPI3_SDI 3 +#define SC_P_SPI3_CS0_DMA_SPI3_CS0 SC_P_SPI3_CS0 0 +#define SC_P_SPI3_CS0_DMA_FTM_CH2 SC_P_SPI3_CS0 1 +#define SC_P_SPI3_CS0_LSIO_GPIO2_IO20 SC_P_SPI3_CS0 3 +#define SC_P_SPI3_CS1_DMA_SPI3_CS1 SC_P_SPI3_CS1 0 +#define SC_P_SPI3_CS1_LSIO_GPIO2_IO21 SC_P_SPI3_CS1 3 +#define SC_P_ESAI0_FSR_AUD_ESAI0_FSR SC_P_ESAI0_FSR 0 +#define SC_P_ESAI0_FSR_LSIO_GPIO2_IO22 SC_P_ESAI0_FSR 3 +#define SC_P_ESAI0_FST_AUD_ESAI0_FST SC_P_ESAI0_FST 0 +#define SC_P_ESAI0_FST_LSIO_GPIO2_IO23 SC_P_ESAI0_FST 3 +#define SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR SC_P_ESAI0_SCKR 0 +#define SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24 SC_P_ESAI0_SCKR 3 +#define SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT SC_P_ESAI0_SCKT 0 +#define SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25 SC_P_ESAI0_SCKT 3 +#define SC_P_ESAI0_TX0_AUD_ESAI0_TX0 SC_P_ESAI0_TX0 0 +#define SC_P_ESAI0_TX0_LSIO_GPIO2_IO26 SC_P_ESAI0_TX0 3 +#define SC_P_ESAI0_TX1_AUD_ESAI0_TX1 SC_P_ESAI0_TX1 0 +#define SC_P_ESAI0_TX1_LSIO_GPIO2_IO27 SC_P_ESAI0_TX1 3 +#define SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0 +#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 SC_P_ESAI0_TX2_RX3 3 +#define SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0 +#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 SC_P_ESAI0_TX3_RX2 3 +#define SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0 +#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 SC_P_ESAI0_TX4_RX1 3 +#define SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0 +#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 SC_P_ESAI0_TX5_RX0 3 +#define SC_P_MCLK_IN0_AUD_ACM_MCLK_IN0 SC_P_MCLK_IN0 0 +#define SC_P_MCLK_IN0_AUD_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1 +#define SC_P_MCLK_IN0_AUD_ESAI1_RX_HF_CLK SC_P_MCLK_IN0 2 +#define SC_P_MCLK_IN0_LSIO_GPIO3_IO00 SC_P_MCLK_IN0 3 +#define SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0 +#define SC_P_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1 +#define SC_P_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK SC_P_MCLK_OUT0 2 +#define SC_P_MCLK_OUT0_LSIO_GPIO3_IO01 SC_P_MCLK_OUT0 3 +#define SC_P_SPI0_SCK_DMA_SPI0_SCK SC_P_SPI0_SCK 0 +#define SC_P_SPI0_SCK_AUD_SAI0_RXC SC_P_SPI0_SCK 1 +#define SC_P_SPI0_SCK_LSIO_GPIO3_IO02 SC_P_SPI0_SCK 3 +#define SC_P_SPI0_SDO_DMA_SPI0_SDO SC_P_SPI0_SDO 0 +#define SC_P_SPI0_SDO_AUD_SAI0_TXD SC_P_SPI0_SDO 1 +#define SC_P_SPI0_SDO_LSIO_GPIO3_IO03 SC_P_SPI0_SDO 3 +#define SC_P_SPI0_SDI_DMA_SPI0_SDI SC_P_SPI0_SDI 0 +#define SC_P_SPI0_SDI_AUD_SAI0_RXD SC_P_SPI0_SDI 1 +#define SC_P_SPI0_SDI_LSIO_GPIO3_IO04 SC_P_SPI0_SDI 3 +#define SC_P_SPI0_CS0_DMA_SPI0_CS0 SC_P_SPI0_CS0 0 +#define SC_P_SPI0_CS0_AUD_SAI0_RXFS SC_P_SPI0_CS0 1 +#define SC_P_SPI0_CS0_LSIO_GPIO3_IO05 SC_P_SPI0_CS0 3 +#define SC_P_SPI0_CS1_DMA_SPI0_CS1 SC_P_SPI0_CS1 0 +#define SC_P_SPI0_CS1_AUD_SAI0_TXC SC_P_SPI0_CS1 1 +#define SC_P_SPI0_CS1_LSIO_GPIO3_IO06 SC_P_SPI0_CS1 3 +#define SC_P_SPI2_SCK_DMA_SPI2_SCK SC_P_SPI2_SCK 0 +#define SC_P_SPI2_SCK_LSIO_GPIO3_IO07 SC_P_SPI2_SCK 3 +#define SC_P_SPI2_SDO_DMA_SPI2_SDO SC_P_SPI2_SDO 0 +#define SC_P_SPI2_SDO_LSIO_GPIO3_IO08 SC_P_SPI2_SDO 3 +#define SC_P_SPI2_SDI_DMA_SPI2_SDI SC_P_SPI2_SDI 0 +#define SC_P_SPI2_SDI_LSIO_GPIO3_IO09 SC_P_SPI2_SDI 3 +#define SC_P_SPI2_CS0_DMA_SPI2_CS0 SC_P_SPI2_CS0 0 +#define SC_P_SPI2_CS0_LSIO_GPIO3_IO10 SC_P_SPI2_CS0 3 +#define SC_P_SPI2_CS1_DMA_SPI2_CS1 SC_P_SPI2_CS1 0 +#define SC_P_SPI2_CS1_AUD_SAI0_TXFS SC_P_SPI2_CS1 1 +#define SC_P_SPI2_CS1_LSIO_GPIO3_IO11 SC_P_SPI2_CS1 3 +#define SC_P_SAI1_RXC_AUD_SAI1_RXC SC_P_SAI1_RXC 0 +#define SC_P_SAI1_RXC_AUD_SAI0_TXD SC_P_SAI1_RXC 1 +#define SC_P_SAI1_RXC_LSIO_GPIO3_IO12 SC_P_SAI1_RXC 3 +#define SC_P_SAI1_RXD_AUD_SAI1_RXD SC_P_SAI1_RXD 0 +#define SC_P_SAI1_RXD_AUD_SAI0_TXFS SC_P_SAI1_RXD 1 +#define SC_P_SAI1_RXD_LSIO_GPIO3_IO13 SC_P_SAI1_RXD 3 +#define SC_P_SAI1_RXFS_AUD_SAI1_RXFS SC_P_SAI1_RXFS 0 +#define SC_P_SAI1_RXFS_AUD_SAI0_RXD SC_P_SAI1_RXFS 1 +#define SC_P_SAI1_RXFS_LSIO_GPIO3_IO14 SC_P_SAI1_RXFS 3 +#define SC_P_SAI1_TXC_AUD_SAI1_TXC SC_P_SAI1_TXC 0 +#define SC_P_SAI1_TXC_AUD_SAI0_TXC SC_P_SAI1_TXC 1 +#define SC_P_SAI1_TXC_LSIO_GPIO3_IO15 SC_P_SAI1_TXC 3 +#define SC_P_SAI1_TXD_AUD_SAI1_TXD SC_P_SAI1_TXD 0 +#define SC_P_SAI1_TXD_AUD_SAI1_RXC SC_P_SAI1_TXD 1 +#define SC_P_SAI1_TXD_LSIO_GPIO3_IO16 SC_P_SAI1_TXD 3 +#define SC_P_SAI1_TXFS_AUD_SAI1_TXFS SC_P_SAI1_TXFS 0 +#define SC_P_SAI1_TXFS_AUD_SAI1_RXFS SC_P_SAI1_TXFS 1 +#define SC_P_SAI1_TXFS_LSIO_GPIO3_IO17 SC_P_SAI1_TXFS 3 +#define SC_P_ADC_IN7_DMA_ADC1_IN3 SC_P_ADC_IN7 0 +#define SC_P_ADC_IN7_DMA_SPI1_CS1 SC_P_ADC_IN7 1 +#define SC_P_ADC_IN7_LSIO_KPP0_ROW3 SC_P_ADC_IN7 2 +#define SC_P_ADC_IN7_LSIO_GPIO3_IO25 SC_P_ADC_IN7 3 +#define SC_P_ADC_IN6_DMA_ADC1_IN2 SC_P_ADC_IN6 0 +#define SC_P_ADC_IN6_DMA_SPI1_CS0 SC_P_ADC_IN6 1 +#define SC_P_ADC_IN6_LSIO_KPP0_ROW2 SC_P_ADC_IN6 2 +#define SC_P_ADC_IN6_LSIO_GPIO3_IO24 SC_P_ADC_IN6 3 +#define SC_P_ADC_IN5_DMA_ADC1_IN1 SC_P_ADC_IN5 0 +#define SC_P_ADC_IN5_DMA_SPI1_SDI SC_P_ADC_IN5 1 +#define SC_P_ADC_IN5_LSIO_KPP0_ROW1 SC_P_ADC_IN5 2 +#define SC_P_ADC_IN5_LSIO_GPIO3_IO23 SC_P_ADC_IN5 3 +#define SC_P_ADC_IN4_DMA_ADC1_IN0 SC_P_ADC_IN4 0 +#define SC_P_ADC_IN4_DMA_SPI1_SDO SC_P_ADC_IN4 1 +#define SC_P_ADC_IN4_LSIO_KPP0_ROW0 SC_P_ADC_IN4 2 +#define SC_P_ADC_IN4_LSIO_GPIO3_IO22 SC_P_ADC_IN4 3 +#define SC_P_ADC_IN3_DMA_ADC0_IN3 SC_P_ADC_IN3 0 +#define SC_P_ADC_IN3_DMA_SPI1_SCK SC_P_ADC_IN3 1 +#define SC_P_ADC_IN3_LSIO_KPP0_COL3 SC_P_ADC_IN3 2 +#define SC_P_ADC_IN3_LSIO_GPIO3_IO21 SC_P_ADC_IN3 3 +#define SC_P_ADC_IN2_DMA_ADC0_IN2 SC_P_ADC_IN2 0 +#define SC_P_ADC_IN2_LSIO_KPP0_COL2 SC_P_ADC_IN2 2 +#define SC_P_ADC_IN2_LSIO_GPIO3_IO20 SC_P_ADC_IN2 3 +#define SC_P_ADC_IN1_DMA_ADC0_IN1 SC_P_ADC_IN1 0 +#define SC_P_ADC_IN1_LSIO_KPP0_COL1 SC_P_ADC_IN1 2 +#define SC_P_ADC_IN1_LSIO_GPIO3_IO19 SC_P_ADC_IN1 3 +#define SC_P_ADC_IN0_DMA_ADC0_IN0 SC_P_ADC_IN0 0 +#define SC_P_ADC_IN0_LSIO_KPP0_COL0 SC_P_ADC_IN0 2 +#define SC_P_ADC_IN0_LSIO_GPIO3_IO18 SC_P_ADC_IN0 3 +#define SC_P_MLB_SIG_CONN_MLB_SIG SC_P_MLB_SIG 0 +#define SC_P_MLB_SIG_AUD_SAI3_RXC SC_P_MLB_SIG 1 +#define SC_P_MLB_SIG_LSIO_GPIO3_IO26 SC_P_MLB_SIG 3 +#define SC_P_MLB_CLK_CONN_MLB_CLK SC_P_MLB_CLK 0 +#define SC_P_MLB_CLK_AUD_SAI3_RXFS SC_P_MLB_CLK 1 +#define SC_P_MLB_CLK_LSIO_GPIO3_IO27 SC_P_MLB_CLK 3 +#define SC_P_MLB_DATA_CONN_MLB_DATA SC_P_MLB_DATA 0 +#define SC_P_MLB_DATA_AUD_SAI3_RXD SC_P_MLB_DATA 1 +#define SC_P_MLB_DATA_LSIO_GPIO3_IO28 SC_P_MLB_DATA 3 +#define SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0 +#define SC_P_FLEXCAN0_RX_LSIO_GPIO3_IO29 SC_P_FLEXCAN0_RX 3 +#define SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0 +#define SC_P_FLEXCAN0_TX_LSIO_GPIO3_IO30 SC_P_FLEXCAN0_TX 3 +#define SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0 +#define SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 SC_P_FLEXCAN1_RX 3 +#define SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0 +#define SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 SC_P_FLEXCAN1_TX 3 +#define SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0 +#define SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 SC_P_FLEXCAN2_RX 3 +#define SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0 +#define SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 SC_P_FLEXCAN2_TX 3 +#define SC_P_USB_SS3_TC0_DMA_I2C1_SCL SC_P_USB_SS3_TC0 0 +#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1 +#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 3 +#define SC_P_USB_SS3_TC1_DMA_I2C1_SCL SC_P_USB_SS3_TC1 0 +#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1 +#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 3 +#define SC_P_USB_SS3_TC2_DMA_I2C1_SDA SC_P_USB_SS3_TC2 0 +#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1 +#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 3 +#define SC_P_USB_SS3_TC3_DMA_I2C1_SDA SC_P_USB_SS3_TC3 0 +#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1 +#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 3 +#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0 +#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 SC_P_USDHC1_RESET_B 3 +#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0 +#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 SC_P_USDHC1_VSELECT 3 +#define SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B SC_P_USDHC2_RESET_B 0 +#define SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 SC_P_USDHC2_RESET_B 3 +#define SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT SC_P_USDHC2_VSELECT 0 +#define SC_P_USDHC2_VSELECT_LSIO_GPIO4_IO10 SC_P_USDHC2_VSELECT 3 +#define SC_P_USDHC2_WP_CONN_USDHC2_WP SC_P_USDHC2_WP 0 +#define SC_P_USDHC2_WP_LSIO_GPIO4_IO11 SC_P_USDHC2_WP 3 +#define SC_P_USDHC2_CD_B_CONN_USDHC2_CD_B SC_P_USDHC2_CD_B 0 +#define SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 SC_P_USDHC2_CD_B 3 +#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0 +#define SC_P_ENET0_MDIO_DMA_I2C4_SDA SC_P_ENET0_MDIO 1 +#define SC_P_ENET0_MDIO_LSIO_GPIO4_IO13 SC_P_ENET0_MDIO 3 +#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0 +#define SC_P_ENET0_MDC_DMA_I2C4_SCL SC_P_ENET0_MDC 1 +#define SC_P_ENET0_MDC_LSIO_GPIO4_IO14 SC_P_ENET0_MDC 3 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1 +#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 SC_P_ENET0_REFCLK_125M_25M 3 +#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M SC_P_ENET1_REFCLK_125M_25M 0 +#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET1_REFCLK_125M_25M 1 +#define SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 SC_P_ENET1_REFCLK_125M_25M 3 +#define SC_P_ENET1_MDIO_CONN_ENET1_MDIO SC_P_ENET1_MDIO 0 +#define SC_P_ENET1_MDIO_DMA_I2C4_SDA SC_P_ENET1_MDIO 1 +#define SC_P_ENET1_MDIO_LSIO_GPIO4_IO17 SC_P_ENET1_MDIO 3 +#define SC_P_ENET1_MDC_CONN_ENET1_MDC SC_P_ENET1_MDC 0 +#define SC_P_ENET1_MDC_DMA_I2C4_SCL SC_P_ENET1_MDC 1 +#define SC_P_ENET1_MDC_LSIO_GPIO4_IO18 SC_P_ENET1_MDC 3 +#define SC_P_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI1A_SS0_B 0 +#define SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 SC_P_QSPI1A_SS0_B 3 +#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI1A_SS1_B 0 +#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2 SC_P_QSPI1A_SS1_B 1 +#define SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 SC_P_QSPI1A_SS1_B 3 +#define SC_P_QSPI1A_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI1A_SCLK 0 +#define SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21 SC_P_QSPI1A_SCLK 3 +#define SC_P_QSPI1A_DQS_LSIO_QSPI1A_DQS SC_P_QSPI1A_DQS 0 +#define SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 SC_P_QSPI1A_DQS 3 +#define SC_P_QSPI1A_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI1A_DATA3 0 +#define SC_P_QSPI1A_DATA3_DMA_I2C1_SDA SC_P_QSPI1A_DATA3 1 +#define SC_P_QSPI1A_DATA3_CONN_USB_OTG1_OC SC_P_QSPI1A_DATA3 2 +#define SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 SC_P_QSPI1A_DATA3 3 +#define SC_P_QSPI1A_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI1A_DATA2 0 +#define SC_P_QSPI1A_DATA2_DMA_I2C1_SCL SC_P_QSPI1A_DATA2 1 +#define SC_P_QSPI1A_DATA2_CONN_USB_OTG2_PWR SC_P_QSPI1A_DATA2 2 +#define SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 SC_P_QSPI1A_DATA2 3 +#define SC_P_QSPI1A_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI1A_DATA1 0 +#define SC_P_QSPI1A_DATA1_DMA_I2C1_SDA SC_P_QSPI1A_DATA1 1 +#define SC_P_QSPI1A_DATA1_CONN_USB_OTG2_OC SC_P_QSPI1A_DATA1 2 +#define SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 SC_P_QSPI1A_DATA1 3 +#define SC_P_QSPI1A_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI1A_DATA0 0 +#define SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 SC_P_QSPI1A_DATA0 3 +#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0 +#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0 +#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0 +#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0 +#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0 +#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0 +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0 +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2 SC_P_QSPI0A_SS1_B 1 +#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0 +#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0 +#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0 +#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0 +#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0 +#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0 +#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0 +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2 SC_P_QSPI0B_SS1_B 1 +#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0 +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 SC_P_PCIE_CTRL0_CLKREQ_B 3 +#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0 +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 SC_P_PCIE_CTRL0_WAKE_B 3 +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0 +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 SC_P_PCIE_CTRL0_PERST_B 3 +#define SC_P_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B SC_P_PCIE_CTRL1_CLKREQ_B 0 +#define SC_P_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA SC_P_PCIE_CTRL1_CLKREQ_B 1 +#define SC_P_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC SC_P_PCIE_CTRL1_CLKREQ_B 2 +#define SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 SC_P_PCIE_CTRL1_CLKREQ_B 3 +#define SC_P_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B SC_P_PCIE_CTRL1_WAKE_B 0 +#define SC_P_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL SC_P_PCIE_CTRL1_WAKE_B 1 +#define SC_P_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR SC_P_PCIE_CTRL1_WAKE_B 2 +#define SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 SC_P_PCIE_CTRL1_WAKE_B 3 +#define SC_P_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B SC_P_PCIE_CTRL1_PERST_B 0 +#define SC_P_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL SC_P_PCIE_CTRL1_PERST_B 1 +#define SC_P_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR SC_P_PCIE_CTRL1_PERST_B 2 +#define SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 SC_P_PCIE_CTRL1_PERST_B 3 +#define SC_P_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA SC_P_USB_HSIC0_DATA 0 +#define SC_P_USB_HSIC0_DATA_DMA_I2C1_SDA SC_P_USB_HSIC0_DATA 1 +#define SC_P_USB_HSIC0_DATA_LSIO_GPIO5_IO01 SC_P_USB_HSIC0_DATA 3 +#define SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE SC_P_USB_HSIC0_STROBE 0 +#define SC_P_USB_HSIC0_STROBE_DMA_I2C1_SCL SC_P_USB_HSIC0_STROBE 1 +#define SC_P_USB_HSIC0_STROBE_LSIO_GPIO5_IO02 SC_P_USB_HSIC0_STROBE 3 +#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0 +#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1 +#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0 +#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1 +#define SC_P_EMMC0_CMD_AUD_MQS_R SC_P_EMMC0_CMD 2 +#define SC_P_EMMC0_CMD_LSIO_GPIO5_IO03 SC_P_EMMC0_CMD 3 +#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0 +#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1 +#define SC_P_EMMC0_DATA0_LSIO_GPIO5_IO04 SC_P_EMMC0_DATA0 3 +#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0 +#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1 +#define SC_P_EMMC0_DATA1_LSIO_GPIO5_IO05 SC_P_EMMC0_DATA1 3 +#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0 +#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1 +#define SC_P_EMMC0_DATA2_LSIO_GPIO5_IO06 SC_P_EMMC0_DATA2 3 +#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0 +#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1 +#define SC_P_EMMC0_DATA3_LSIO_GPIO5_IO07 SC_P_EMMC0_DATA3 3 +#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0 +#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1 +#define SC_P_EMMC0_DATA4_LSIO_GPIO5_IO08 SC_P_EMMC0_DATA4 3 +#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0 +#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1 +#define SC_P_EMMC0_DATA5_LSIO_GPIO5_IO09 SC_P_EMMC0_DATA5 3 +#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0 +#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1 +#define SC_P_EMMC0_DATA6_LSIO_GPIO5_IO10 SC_P_EMMC0_DATA6 3 +#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0 +#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1 +#define SC_P_EMMC0_DATA7_LSIO_GPIO5_IO11 SC_P_EMMC0_DATA7 3 +#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0 +#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1 +#define SC_P_EMMC0_STROBE_LSIO_GPIO5_IO12 SC_P_EMMC0_STROBE 3 +#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0 +#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1 +#define SC_P_EMMC0_RESET_B_CONN_USDHC1_VSELECT SC_P_EMMC0_RESET_B 2 +#define SC_P_EMMC0_RESET_B_LSIO_GPIO5_IO13 SC_P_EMMC0_RESET_B 3 +#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0 +#define SC_P_USDHC1_CLK_AUD_MQS_R SC_P_USDHC1_CLK 1 +#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0 +#define SC_P_USDHC1_CMD_AUD_MQS_L SC_P_USDHC1_CMD 1 +#define SC_P_USDHC1_CMD_LSIO_GPIO5_IO14 SC_P_USDHC1_CMD 3 +#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0 +#define SC_P_USDHC1_DATA0_CONN_NAND_RE_N SC_P_USDHC1_DATA0 1 +#define SC_P_USDHC1_DATA0_LSIO_GPIO5_IO15 SC_P_USDHC1_DATA0 3 +#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0 +#define SC_P_USDHC1_DATA1_CONN_NAND_RE_P SC_P_USDHC1_DATA1 1 +#define SC_P_USDHC1_DATA1_LSIO_GPIO5_IO16 SC_P_USDHC1_DATA1 3 +#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0 +#define SC_P_USDHC1_DATA2_CONN_NAND_DQS_N SC_P_USDHC1_DATA2 1 +#define SC_P_USDHC1_DATA2_LSIO_GPIO5_IO17 SC_P_USDHC1_DATA2 3 +#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0 +#define SC_P_USDHC1_DATA3_CONN_NAND_DQS_P SC_P_USDHC1_DATA3 1 +#define SC_P_USDHC1_DATA3_LSIO_GPIO5_IO18 SC_P_USDHC1_DATA3 3 +#define SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 SC_P_USDHC1_DATA4 0 +#define SC_P_USDHC1_DATA4_CONN_NAND_CE0_B SC_P_USDHC1_DATA4 1 +#define SC_P_USDHC1_DATA4_AUD_MQS_R SC_P_USDHC1_DATA4 2 +#define SC_P_USDHC1_DATA4_LSIO_GPIO5_IO19 SC_P_USDHC1_DATA4 3 +#define SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 SC_P_USDHC1_DATA5 0 +#define SC_P_USDHC1_DATA5_CONN_NAND_RE_B SC_P_USDHC1_DATA5 1 +#define SC_P_USDHC1_DATA5_AUD_MQS_L SC_P_USDHC1_DATA5 2 +#define SC_P_USDHC1_DATA5_LSIO_GPIO5_IO20 SC_P_USDHC1_DATA5 3 +#define SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 SC_P_USDHC1_DATA6 0 +#define SC_P_USDHC1_DATA6_CONN_NAND_WE_B SC_P_USDHC1_DATA6 1 +#define SC_P_USDHC1_DATA6_CONN_USDHC1_WP SC_P_USDHC1_DATA6 2 +#define SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 SC_P_USDHC1_DATA6 3 +#define SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 SC_P_USDHC1_DATA7 0 +#define SC_P_USDHC1_DATA7_CONN_NAND_ALE SC_P_USDHC1_DATA7 1 +#define SC_P_USDHC1_DATA7_CONN_USDHC1_CD_B SC_P_USDHC1_DATA7 2 +#define SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 SC_P_USDHC1_DATA7 3 +#define SC_P_USDHC1_STROBE_CONN_USDHC1_STROBE SC_P_USDHC1_STROBE 0 +#define SC_P_USDHC1_STROBE_CONN_NAND_CE1_B SC_P_USDHC1_STROBE 1 +#define SC_P_USDHC1_STROBE_CONN_USDHC1_RESET_B SC_P_USDHC1_STROBE 2 +#define SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23 SC_P_USDHC1_STROBE 3 +#define SC_P_USDHC2_CLK_CONN_USDHC2_CLK SC_P_USDHC2_CLK 0 +#define SC_P_USDHC2_CLK_AUD_MQS_R SC_P_USDHC2_CLK 1 +#define SC_P_USDHC2_CLK_LSIO_GPIO5_IO24 SC_P_USDHC2_CLK 3 +#define SC_P_USDHC2_CMD_CONN_USDHC2_CMD SC_P_USDHC2_CMD 0 +#define SC_P_USDHC2_CMD_AUD_MQS_L SC_P_USDHC2_CMD 1 +#define SC_P_USDHC2_CMD_LSIO_GPIO5_IO25 SC_P_USDHC2_CMD 3 +#define SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 SC_P_USDHC2_DATA0 0 +#define SC_P_USDHC2_DATA0_DMA_UART4_RX SC_P_USDHC2_DATA0 1 +#define SC_P_USDHC2_DATA0_LSIO_GPIO5_IO26 SC_P_USDHC2_DATA0 3 +#define SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 SC_P_USDHC2_DATA1 0 +#define SC_P_USDHC2_DATA1_DMA_UART4_TX SC_P_USDHC2_DATA1 1 +#define SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27 SC_P_USDHC2_DATA1 3 +#define SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 SC_P_USDHC2_DATA2 0 +#define SC_P_USDHC2_DATA2_DMA_UART4_CTS_B SC_P_USDHC2_DATA2 1 +#define SC_P_USDHC2_DATA2_LSIO_GPIO5_IO28 SC_P_USDHC2_DATA2 3 +#define SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 SC_P_USDHC2_DATA3 0 +#define SC_P_USDHC2_DATA3_DMA_UART4_RTS_B SC_P_USDHC2_DATA3 1 +#define SC_P_USDHC2_DATA3_LSIO_GPIO5_IO29 SC_P_USDHC2_DATA3 3 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2 +#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 SC_P_ENET0_RGMII_TXC 3 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0 +#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 SC_P_ENET0_RGMII_TX_CTL 3 +#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0 +#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 SC_P_ENET0_RGMII_TXD0 3 +#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0 +#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 SC_P_ENET0_RGMII_TXD1 3 +#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0 +#define SC_P_ENET0_RGMII_TXD2_DMA_UART3_TX SC_P_ENET0_RGMII_TXD2 1 +#define SC_P_ENET0_RGMII_TXD2_VPU_TSI_S1_VID SC_P_ENET0_RGMII_TXD2 2 +#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 SC_P_ENET0_RGMII_TXD2 3 +#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0 +#define SC_P_ENET0_RGMII_TXD3_DMA_UART3_RTS_B SC_P_ENET0_RGMII_TXD3 1 +#define SC_P_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC SC_P_ENET0_RGMII_TXD3 2 +#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 SC_P_ENET0_RGMII_TXD3 3 +#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0 +#define SC_P_ENET0_RGMII_RXC_DMA_UART3_CTS_B SC_P_ENET0_RGMII_RXC 1 +#define SC_P_ENET0_RGMII_RXC_VPU_TSI_S1_DATA SC_P_ENET0_RGMII_RXC 2 +#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 SC_P_ENET0_RGMII_RXC 3 +#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0 +#define SC_P_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID SC_P_ENET0_RGMII_RX_CTL 2 +#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 SC_P_ENET0_RGMII_RX_CTL 3 +#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0 +#define SC_P_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC SC_P_ENET0_RGMII_RXD0 2 +#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 SC_P_ENET0_RGMII_RXD0 3 +#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0 +#define SC_P_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA SC_P_ENET0_RGMII_RXD1 2 +#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 SC_P_ENET0_RGMII_RXD1 3 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1 +#define SC_P_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK SC_P_ENET0_RGMII_RXD2 2 +#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 SC_P_ENET0_RGMII_RXD2 3 +#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0 +#define SC_P_ENET0_RGMII_RXD3_DMA_UART3_RX SC_P_ENET0_RGMII_RXD3 1 +#define SC_P_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET0_RGMII_RXD3 2 +#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 SC_P_ENET0_RGMII_RXD3 3 +#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC SC_P_ENET1_RGMII_TXC 0 +#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT SC_P_ENET1_RGMII_TXC 1 +#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN SC_P_ENET1_RGMII_TXC 2 +#define SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 SC_P_ENET1_RGMII_TXC 3 +#define SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL SC_P_ENET1_RGMII_TX_CTL 0 +#define SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 SC_P_ENET1_RGMII_TX_CTL 3 +#define SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 SC_P_ENET1_RGMII_TXD0 0 +#define SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 SC_P_ENET1_RGMII_TXD0 3 +#define SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 SC_P_ENET1_RGMII_TXD1 0 +#define SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 SC_P_ENET1_RGMII_TXD1 3 +#define SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 SC_P_ENET1_RGMII_TXD2 0 +#define SC_P_ENET1_RGMII_TXD2_DMA_UART3_TX SC_P_ENET1_RGMII_TXD2 1 +#define SC_P_ENET1_RGMII_TXD2_VPU_TSI_S1_VID SC_P_ENET1_RGMII_TXD2 2 +#define SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 SC_P_ENET1_RGMII_TXD2 3 +#define SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 SC_P_ENET1_RGMII_TXD3 0 +#define SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B SC_P_ENET1_RGMII_TXD3 1 +#define SC_P_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC SC_P_ENET1_RGMII_TXD3 2 +#define SC_P_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15 SC_P_ENET1_RGMII_TXD3 3 +#define SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC SC_P_ENET1_RGMII_RXC 0 +#define SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B SC_P_ENET1_RGMII_RXC 1 +#define SC_P_ENET1_RGMII_RXC_VPU_TSI_S1_DATA SC_P_ENET1_RGMII_RXC 2 +#define SC_P_ENET1_RGMII_RXC_LSIO_GPIO6_IO16 SC_P_ENET1_RGMII_RXC 3 +#define SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL SC_P_ENET1_RGMII_RX_CTL 0 +#define SC_P_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID SC_P_ENET1_RGMII_RX_CTL 2 +#define SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 SC_P_ENET1_RGMII_RX_CTL 3 +#define SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 SC_P_ENET1_RGMII_RXD0 0 +#define SC_P_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC SC_P_ENET1_RGMII_RXD0 2 +#define SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 SC_P_ENET1_RGMII_RXD0 3 +#define SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 SC_P_ENET1_RGMII_RXD1 0 +#define SC_P_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA SC_P_ENET1_RGMII_RXD1 2 +#define SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 SC_P_ENET1_RGMII_RXD1 3 +#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 SC_P_ENET1_RGMII_RXD2 0 +#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER SC_P_ENET1_RGMII_RXD2 1 +#define SC_P_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK SC_P_ENET1_RGMII_RXD2 2 +#define SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 SC_P_ENET1_RGMII_RXD2 3 +#define SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 SC_P_ENET1_RGMII_RXD3 0 +#define SC_P_ENET1_RGMII_RXD3_DMA_UART3_RX SC_P_ENET1_RGMII_RXD3 1 +#define SC_P_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET1_RGMII_RXD3 2 +#define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 SC_P_ENET1_RGMII_RXD3 3 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0 + +#endif /* SC_PADS_H */ diff --git a/roms/u-boot/include/dt-bindings/pinctrl/pads-imx8qxp.h b/roms/u-boot/include/dt-bindings/pinctrl/pads-imx8qxp.h new file mode 100644 index 000000000..41f4fe564 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/pads-imx8qxp.h @@ -0,0 +1,757 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef _SC_PADS_H +#define _SC_PADS_H + +#define SC_P_PCIE_CTRL0_PERST_B 0 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */ +#define SC_P_PCIE_CTRL0_WAKE_B 2 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /* */ +#define SC_P_USB_SS3_TC0 4 /* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */ +#define SC_P_USB_SS3_TC1 5 /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 6 /* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */ +#define SC_P_USB_SS3_TC3 7 /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /* */ +#define SC_P_EMMC0_CLK 9 /* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */ +#define SC_P_EMMC0_CMD 10 /* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */ +#define SC_P_EMMC0_DATA0 11 /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */ +#define SC_P_EMMC0_DATA1 12 /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */ +#define SC_P_EMMC0_DATA2 13 /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */ +#define SC_P_EMMC0_DATA3 14 /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /* */ +#define SC_P_EMMC0_DATA4 16 /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */ +#define SC_P_EMMC0_DATA5 17 /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */ +#define SC_P_EMMC0_DATA6 18 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */ +#define SC_P_EMMC0_DATA7 19 /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */ +#define SC_P_EMMC0_STROBE 20 /* CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */ +#define SC_P_EMMC0_RESET_B 21 /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /* */ +#define SC_P_USDHC1_RESET_B 23 /* CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */ +#define SC_P_USDHC1_VSELECT 24 /* CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */ +#define SC_P_CTL_NAND_RE_P_N 25 /* */ +#define SC_P_USDHC1_WP 26 /* CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */ +#define SC_P_USDHC1_CD_B 27 /* CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */ +#define SC_P_CTL_NAND_DQS_P_N 28 /* */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /* */ +#define SC_P_USDHC1_CLK 30 /* CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */ +#define SC_P_USDHC1_CMD 31 /* CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */ +#define SC_P_USDHC1_DATA0 32 /* CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */ +#define SC_P_USDHC1_DATA1 33 /* CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */ +#define SC_P_USDHC1_DATA2 34 /* CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */ +#define SC_P_USDHC1_DATA3 35 /* CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /* */ +#define SC_P_ENET0_RGMII_TXC 37 /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */ +#define SC_P_ENET0_RGMII_TX_CTL 38 /* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */ +#define SC_P_ENET0_RGMII_TXD0 39 /* CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */ +#define SC_P_ENET0_RGMII_TXD1 40 /* CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */ +#define SC_P_ENET0_RGMII_TXD2 41 /* CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */ +#define SC_P_ENET0_RGMII_TXD3 42 /* CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /* */ +#define SC_P_ENET0_RGMII_RXC 44 /* CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */ +#define SC_P_ENET0_RGMII_RX_CTL 45 /* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */ +#define SC_P_ENET0_RGMII_RXD0 46 /* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */ +#define SC_P_ENET0_RGMII_RXD1 47 /* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */ +#define SC_P_ENET0_RGMII_RXD2 48 /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */ +#define SC_P_ENET0_RGMII_RXD3 49 /* CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /* */ +#define SC_P_ENET0_REFCLK_125M_25M 51 /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */ +#define SC_P_ENET0_MDIO 52 /* CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */ +#define SC_P_ENET0_MDC 53 /* CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /* */ +#define SC_P_ESAI0_FSR 55 /* ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */ +#define SC_P_ESAI0_FST 56 /* ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */ +#define SC_P_ESAI0_SCKR 57 /* ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */ +#define SC_P_ESAI0_SCKT 58 /* ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */ +#define SC_P_ESAI0_TX0 59 /* ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */ +#define SC_P_ESAI0_TX1 60 /* ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */ +#define SC_P_ESAI0_TX2_RX3 61 /* ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */ +#define SC_P_ESAI0_TX3_RX2 62 /* ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */ +#define SC_P_ESAI0_TX4_RX1 63 /* ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */ +#define SC_P_ESAI0_TX5_RX0 64 /* ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */ +#define SC_P_SPDIF0_RX 65 /* ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */ +#define SC_P_SPDIF0_TX 66 /* ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */ +#define SC_P_SPDIF0_EXT_CLK 67 /* ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /* */ +#define SC_P_SPI3_SCK 69 /* ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */ +#define SC_P_SPI3_SDO 70 /* ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */ +#define SC_P_SPI3_SDI 71 /* ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */ +#define SC_P_SPI3_CS0 72 /* ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */ +#define SC_P_SPI3_CS1 73 /* ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */ +#define SC_P_MCLK_IN1 74 /* ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */ +#define SC_P_MCLK_IN0 75 /* ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */ +#define SC_P_MCLK_OUT0 76 /* ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */ +#define SC_P_UART1_TX 77 /* ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */ +#define SC_P_UART1_RX 78 /* ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */ +#define SC_P_UART1_RTS_B 79 /* ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */ +#define SC_P_UART1_CTS_B 80 /* ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /* */ +#define SC_P_SAI0_TXD 82 /* ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */ +#define SC_P_SAI0_TXC 83 /* ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */ +#define SC_P_SAI0_RXD 84 /* ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */ +#define SC_P_SAI0_TXFS 85 /* ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */ +#define SC_P_SAI1_RXD 86 /* ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */ +#define SC_P_SAI1_RXC 87 /* ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */ +#define SC_P_SAI1_RXFS 88 /* ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */ +#define SC_P_SPI2_CS0 89 /* ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */ +#define SC_P_SPI2_SDO 90 /* ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */ +#define SC_P_SPI2_SDI 91 /* ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */ +#define SC_P_SPI2_SCK 92 /* ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */ +#define SC_P_SPI0_SCK 93 /* ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */ +#define SC_P_SPI0_SDI 94 /* ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */ +#define SC_P_SPI0_SDO 95 /* ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */ +#define SC_P_SPI0_CS1 96 /* ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */ +#define SC_P_SPI0_CS0 97 /* ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /* */ +#define SC_P_ADC_IN1 99 /* ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */ +#define SC_P_ADC_IN0 100 /* ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */ +#define SC_P_ADC_IN3 101 /* ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */ +#define SC_P_ADC_IN2 102 /* ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */ +#define SC_P_ADC_IN5 103 /* ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */ +#define SC_P_ADC_IN4 104 /* ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */ +#define SC_P_FLEXCAN0_RX 105 /* ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */ +#define SC_P_FLEXCAN0_TX 106 /* ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */ +#define SC_P_FLEXCAN1_RX 107 /* ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */ +#define SC_P_FLEXCAN1_TX 108 /* ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */ +#define SC_P_FLEXCAN2_RX 109 /* ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */ +#define SC_P_FLEXCAN2_TX 110 /* ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */ +#define SC_P_UART0_RX 111 /* ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */ +#define SC_P_UART0_TX 112 /* ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */ +#define SC_P_UART2_TX 113 /* ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */ +#define SC_P_UART2_RX 114 /* ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /* */ +#define SC_P_MIPI_DSI0_I2C0_SCL 116 /* MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */ +#define SC_P_MIPI_DSI0_I2C0_SDA 117 /* MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */ +#define SC_P_MIPI_DSI0_GPIO0_00 118 /* MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */ +#define SC_P_MIPI_DSI0_GPIO0_01 119 /* MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */ +#define SC_P_MIPI_DSI1_I2C0_SCL 120 /* MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */ +#define SC_P_MIPI_DSI1_I2C0_SDA 121 /* MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */ +#define SC_P_MIPI_DSI1_GPIO0_00 122 /* MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */ +#define SC_P_MIPI_DSI1_GPIO0_01 123 /* MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /* */ +#define SC_P_JTAG_TRST_B 125 /* SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */ +#define SC_P_PMIC_I2C_SCL 126 /* SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */ +#define SC_P_PMIC_I2C_SDA 127 /* SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */ +#define SC_P_PMIC_INT_B 128 /* SCU.DSC.PMIC_INT_B */ +#define SC_P_SCU_GPIO0_00 129 /* SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */ +#define SC_P_SCU_GPIO0_01 130 /* SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */ +#define SC_P_SCU_PMIC_STANDBY 131 /* SCU.DSC.PMIC_STANDBY */ +#define SC_P_SCU_BOOT_MODE0 132 /* SCU.DSC.BOOT_MODE0 */ +#define SC_P_SCU_BOOT_MODE1 133 /* SCU.DSC.BOOT_MODE1 */ +#define SC_P_SCU_BOOT_MODE2 134 /* SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */ +#define SC_P_SCU_BOOT_MODE3 135 /* SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */ +#define SC_P_CSI_D00 136 /* CI_PI.D02, ADMA.SAI0.RXC */ +#define SC_P_CSI_D01 137 /* CI_PI.D03, ADMA.SAI0.RXD */ +#define SC_P_CSI_D02 138 /* CI_PI.D04, ADMA.SAI0.RXFS */ +#define SC_P_CSI_D03 139 /* CI_PI.D05, ADMA.SAI2.RXC */ +#define SC_P_CSI_D04 140 /* CI_PI.D06, ADMA.SAI2.RXD */ +#define SC_P_CSI_D05 141 /* CI_PI.D07, ADMA.SAI2.RXFS */ +#define SC_P_CSI_D06 142 /* CI_PI.D08, ADMA.SAI3.RXC */ +#define SC_P_CSI_D07 143 /* CI_PI.D09, ADMA.SAI3.RXD */ +#define SC_P_CSI_HSYNC 144 /* CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */ +#define SC_P_CSI_VSYNC 145 /* CI_PI.VSYNC, CI_PI.D01 */ +#define SC_P_CSI_PCLK 146 /* CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */ +#define SC_P_CSI_MCLK 147 /* CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */ +#define SC_P_CSI_EN 148 /* CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */ +#define SC_P_CSI_RESET 149 /* CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /* */ +#define SC_P_MIPI_CSI0_MCLK_OUT 151 /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */ +#define SC_P_MIPI_CSI0_I2C0_SCL 152 /* MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */ +#define SC_P_MIPI_CSI0_I2C0_SDA 153 /* MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */ +#define SC_P_MIPI_CSI0_GPIO0_01 154 /* MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */ +#define SC_P_MIPI_CSI0_GPIO0_00 155 /* MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */ +#define SC_P_QSPI0A_DATA0 156 /* LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */ +#define SC_P_QSPI0A_DATA1 157 /* LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */ +#define SC_P_QSPI0A_DATA2 158 /* LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */ +#define SC_P_QSPI0A_DATA3 159 /* LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */ +#define SC_P_QSPI0A_DQS 160 /* LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */ +#define SC_P_QSPI0A_SS0_B 161 /* LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */ +#define SC_P_QSPI0A_SS1_B 162 /* LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */ +#define SC_P_QSPI0A_SCLK 163 /* LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /* */ +#define SC_P_QSPI0B_SCLK 165 /* LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */ +#define SC_P_QSPI0B_DATA0 166 /* LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */ +#define SC_P_QSPI0B_DATA1 167 /* LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */ +#define SC_P_QSPI0B_DATA2 168 /* LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */ +#define SC_P_QSPI0B_DATA3 169 /* LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */ +#define SC_P_QSPI0B_DQS 170 /* LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */ +#define SC_P_QSPI0B_SS0_B 171 /* LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */ +#define SC_P_QSPI0B_SS1_B 172 /* LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /* */ +/*@}*/ + +/*! + * @name Pad Mux Definitions + * format: name padid padmux + */ +/*@{*/ +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0 +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 SC_P_PCIE_CTRL0_PERST_B 4 +#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0 +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 SC_P_PCIE_CTRL0_CLKREQ_B 4 +#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0 +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 SC_P_PCIE_CTRL0_WAKE_B 4 +#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL SC_P_USB_SS3_TC0 0 +#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1 +#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC0 2 +#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 4 +#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL SC_P_USB_SS3_TC1 0 +#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1 +#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 4 +#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA SC_P_USB_SS3_TC2 0 +#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1 +#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC SC_P_USB_SS3_TC2 2 +#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 4 +#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA SC_P_USB_SS3_TC3 0 +#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1 +#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 4 +#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0 +#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1 +#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07 SC_P_EMMC0_CLK 4 +#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0 +#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1 +#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08 SC_P_EMMC0_CMD 4 +#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0 +#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1 +#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09 SC_P_EMMC0_DATA0 4 +#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0 +#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1 +#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10 SC_P_EMMC0_DATA1 4 +#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0 +#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1 +#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11 SC_P_EMMC0_DATA2 4 +#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0 +#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1 +#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12 SC_P_EMMC0_DATA3 4 +#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0 +#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1 +#define SC_P_EMMC0_DATA4_CONN_EMMC0_WP SC_P_EMMC0_DATA4 3 +#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13 SC_P_EMMC0_DATA4 4 +#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0 +#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1 +#define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT SC_P_EMMC0_DATA5 3 +#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14 SC_P_EMMC0_DATA5 4 +#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0 +#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1 +#define SC_P_EMMC0_DATA6_CONN_MLB_CLK SC_P_EMMC0_DATA6 3 +#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15 SC_P_EMMC0_DATA6 4 +#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0 +#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1 +#define SC_P_EMMC0_DATA7_CONN_MLB_SIG SC_P_EMMC0_DATA7 3 +#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16 SC_P_EMMC0_DATA7 4 +#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0 +#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1 +#define SC_P_EMMC0_STROBE_CONN_MLB_DATA SC_P_EMMC0_STROBE 3 +#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17 SC_P_EMMC0_STROBE 4 +#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0 +#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1 +#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 SC_P_EMMC0_RESET_B 4 +#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0 +#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N SC_P_USDHC1_RESET_B 1 +#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK SC_P_USDHC1_RESET_B 2 +#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 SC_P_USDHC1_RESET_B 4 +#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0 +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P SC_P_USDHC1_VSELECT 1 +#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO SC_P_USDHC1_VSELECT 2 +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B SC_P_USDHC1_VSELECT 3 +#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20 SC_P_USDHC1_VSELECT 4 +#define SC_P_USDHC1_WP_CONN_USDHC1_WP SC_P_USDHC1_WP 0 +#define SC_P_USDHC1_WP_CONN_NAND_DQS_N SC_P_USDHC1_WP 1 +#define SC_P_USDHC1_WP_ADMA_SPI2_SDI SC_P_USDHC1_WP 2 +#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21 SC_P_USDHC1_WP 4 +#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B SC_P_USDHC1_CD_B 0 +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P SC_P_USDHC1_CD_B 1 +#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0 SC_P_USDHC1_CD_B 2 +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS SC_P_USDHC1_CD_B 3 +#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 SC_P_USDHC1_CD_B 4 +#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0 +#define SC_P_USDHC1_CLK_ADMA_UART3_RX SC_P_USDHC1_CLK 2 +#define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 SC_P_USDHC1_CLK 4 +#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0 +#define SC_P_USDHC1_CMD_CONN_NAND_CE0_B SC_P_USDHC1_CMD 1 +#define SC_P_USDHC1_CMD_ADMA_MQS_R SC_P_USDHC1_CMD 2 +#define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 SC_P_USDHC1_CMD 4 +#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0 +#define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B SC_P_USDHC1_DATA0 1 +#define SC_P_USDHC1_DATA0_ADMA_MQS_L SC_P_USDHC1_DATA0 2 +#define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 SC_P_USDHC1_DATA0 4 +#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0 +#define SC_P_USDHC1_DATA1_CONN_NAND_RE_B SC_P_USDHC1_DATA1 1 +#define SC_P_USDHC1_DATA1_ADMA_UART3_TX SC_P_USDHC1_DATA1 2 +#define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 SC_P_USDHC1_DATA1 4 +#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0 +#define SC_P_USDHC1_DATA2_CONN_NAND_WE_B SC_P_USDHC1_DATA2 1 +#define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B SC_P_USDHC1_DATA2 2 +#define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 SC_P_USDHC1_DATA2 4 +#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0 +#define SC_P_USDHC1_DATA3_CONN_NAND_ALE SC_P_USDHC1_DATA3 1 +#define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B SC_P_USDHC1_DATA3 2 +#define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 SC_P_USDHC1_DATA3 4 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2 +#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B SC_P_ENET0_RGMII_TXC 3 +#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 SC_P_ENET0_RGMII_TXC 4 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B SC_P_ENET0_RGMII_TX_CTL 3 +#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 SC_P_ENET0_RGMII_TX_CTL 4 +#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0 +#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT SC_P_ENET0_RGMII_TXD0 3 +#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 SC_P_ENET0_RGMII_TXD0 4 +#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0 +#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP SC_P_ENET0_RGMII_TXD1 3 +#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 SC_P_ENET0_RGMII_TXD1 4 +#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0 +#define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK SC_P_ENET0_RGMII_TXD2 1 +#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B SC_P_ENET0_RGMII_TXD2 2 +#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B SC_P_ENET0_RGMII_TXD2 3 +#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 SC_P_ENET0_RGMII_TXD2 4 +#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0 +#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG SC_P_ENET0_RGMII_TXD3 1 +#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2 +#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0 +#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0 +#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA SC_P_ENET0_RGMII_RXC 1 +#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2 +#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK SC_P_ENET0_RGMII_RXC 3 +#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 SC_P_ENET0_RGMII_RXC 4 +#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0 +#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD SC_P_ENET0_RGMII_RX_CTL 3 +#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 SC_P_ENET0_RGMII_RX_CTL 4 +#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0 +#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 SC_P_ENET0_RGMII_RXD0 3 +#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 SC_P_ENET0_RGMII_RXD0 4 +#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0 +#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 SC_P_ENET0_RGMII_RXD1 3 +#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 SC_P_ENET0_RGMII_RXD1 4 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1 +#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 SC_P_ENET0_RGMII_RXD2 3 +#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 SC_P_ENET0_RGMII_RXD2 4 +#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0 +#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2 +#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3 +#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET0_REFCLK_125M_25M 2 +#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 SC_P_ENET0_REFCLK_125M_25M 4 +#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0 +#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA SC_P_ENET0_MDIO 1 +#define SC_P_ENET0_MDIO_CONN_ENET1_MDIO SC_P_ENET0_MDIO 2 +#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 SC_P_ENET0_MDIO 4 +#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0 +#define SC_P_ENET0_MDC_ADMA_I2C3_SCL SC_P_ENET0_MDC 1 +#define SC_P_ENET0_MDC_CONN_ENET1_MDC SC_P_ENET0_MDC 2 +#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11 SC_P_ENET0_MDC 4 +#define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR SC_P_ESAI0_FSR 0 +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT SC_P_ESAI0_FSR 1 +#define SC_P_ESAI0_FSR_ADMA_LCDIF_D00 SC_P_ESAI0_FSR 2 +#define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC SC_P_ESAI0_FSR 3 +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN SC_P_ESAI0_FSR 4 +#define SC_P_ESAI0_FST_ADMA_ESAI0_FST SC_P_ESAI0_FST 0 +#define SC_P_ESAI0_FST_CONN_MLB_CLK SC_P_ESAI0_FST 1 +#define SC_P_ESAI0_FST_ADMA_LCDIF_D01 SC_P_ESAI0_FST 2 +#define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 SC_P_ESAI0_FST 3 +#define SC_P_ESAI0_FST_LSIO_GPIO0_IO01 SC_P_ESAI0_FST 4 +#define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR SC_P_ESAI0_SCKR 0 +#define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 SC_P_ESAI0_SCKR 2 +#define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL SC_P_ESAI0_SCKR 3 +#define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02 SC_P_ESAI0_SCKR 4 +#define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT SC_P_ESAI0_SCKT 0 +#define SC_P_ESAI0_SCKT_CONN_MLB_SIG SC_P_ESAI0_SCKT 1 +#define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 SC_P_ESAI0_SCKT 2 +#define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 SC_P_ESAI0_SCKT 3 +#define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03 SC_P_ESAI0_SCKT 4 +#define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 SC_P_ESAI0_TX0 0 +#define SC_P_ESAI0_TX0_CONN_MLB_DATA SC_P_ESAI0_TX0 1 +#define SC_P_ESAI0_TX0_ADMA_LCDIF_D04 SC_P_ESAI0_TX0 2 +#define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC SC_P_ESAI0_TX0 3 +#define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 SC_P_ESAI0_TX0 4 +#define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 SC_P_ESAI0_TX1 0 +#define SC_P_ESAI0_TX1_ADMA_LCDIF_D05 SC_P_ESAI0_TX1 2 +#define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 SC_P_ESAI0_TX1 3 +#define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 SC_P_ESAI0_TX1 4 +#define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0 +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER SC_P_ESAI0_TX2_RX3 1 +#define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 SC_P_ESAI0_TX2_RX3 2 +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 SC_P_ESAI0_TX2_RX3 3 +#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 SC_P_ESAI0_TX2_RX3 4 +#define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0 +#define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 SC_P_ESAI0_TX3_RX2 2 +#define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 SC_P_ESAI0_TX3_RX2 3 +#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 SC_P_ESAI0_TX3_RX2 4 +#define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0 +#define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 SC_P_ESAI0_TX4_RX1 2 +#define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 SC_P_ESAI0_TX4_RX1 3 +#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 SC_P_ESAI0_TX4_RX1 4 +#define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0 +#define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 SC_P_ESAI0_TX5_RX0 2 +#define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 SC_P_ESAI0_TX5_RX0 3 +#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 SC_P_ESAI0_TX5_RX0 4 +#define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX SC_P_SPDIF0_RX 0 +#define SC_P_SPDIF0_RX_ADMA_MQS_R SC_P_SPDIF0_RX 1 +#define SC_P_SPDIF0_RX_ADMA_LCDIF_D10 SC_P_SPDIF0_RX 2 +#define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 SC_P_SPDIF0_RX 3 +#define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10 SC_P_SPDIF0_RX 4 +#define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX SC_P_SPDIF0_TX 0 +#define SC_P_SPDIF0_TX_ADMA_MQS_L SC_P_SPDIF0_TX 1 +#define SC_P_SPDIF0_TX_ADMA_LCDIF_D11 SC_P_SPDIF0_TX 2 +#define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL SC_P_SPDIF0_TX 3 +#define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11 SC_P_SPDIF0_TX 4 +#define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0 +#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 SC_P_SPDIF0_EXT_CLK 2 +#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M SC_P_SPDIF0_EXT_CLK 3 +#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 SC_P_SPDIF0_EXT_CLK 4 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK 0 +#define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK 2 +#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK 4 +#define SC_P_SPI3_SDO_ADMA_SPI3_SDO SC_P_SPI3_SDO 0 +#define SC_P_SPI3_SDO_ADMA_LCDIF_D14 SC_P_SPI3_SDO 2 +#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14 SC_P_SPI3_SDO 4 +#define SC_P_SPI3_SDI_ADMA_SPI3_SDI SC_P_SPI3_SDI 0 +#define SC_P_SPI3_SDI_ADMA_LCDIF_D15 SC_P_SPI3_SDI 2 +#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15 SC_P_SPI3_SDI 4 +#define SC_P_SPI3_CS0_ADMA_SPI3_CS0 SC_P_SPI3_CS0 0 +#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1 SC_P_SPI3_CS0 1 +#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC SC_P_SPI3_CS0 2 +#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16 SC_P_SPI3_CS0 4 +#define SC_P_SPI3_CS1_ADMA_SPI3_CS1 SC_P_SPI3_CS1 0 +#define SC_P_SPI3_CS1_ADMA_I2C3_SCL SC_P_SPI3_CS1 1 +#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET SC_P_SPI3_CS1 2 +#define SC_P_SPI3_CS1_ADMA_SPI2_CS0 SC_P_SPI3_CS1 3 +#define SC_P_SPI3_CS1_ADMA_LCDIF_D16 SC_P_SPI3_CS1 4 +#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1 SC_P_MCLK_IN1 0 +#define SC_P_MCLK_IN1_ADMA_I2C3_SDA SC_P_MCLK_IN1 1 +#define SC_P_MCLK_IN1_ADMA_LCDIF_EN SC_P_MCLK_IN1 2 +#define SC_P_MCLK_IN1_ADMA_SPI2_SCK SC_P_MCLK_IN1 3 +#define SC_P_MCLK_IN1_ADMA_LCDIF_D17 SC_P_MCLK_IN1 4 +#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0 SC_P_MCLK_IN0 0 +#define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1 +#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC SC_P_MCLK_IN0 2 +#define SC_P_MCLK_IN0_ADMA_SPI2_SDI SC_P_MCLK_IN0 3 +#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19 SC_P_MCLK_IN0 4 +#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0 +#define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1 +#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK SC_P_MCLK_OUT0 2 +#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO SC_P_MCLK_OUT0 3 +#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20 SC_P_MCLK_OUT0 4 +#define SC_P_UART1_TX_ADMA_UART1_TX SC_P_UART1_TX 0 +#define SC_P_UART1_TX_LSIO_PWM0_OUT SC_P_UART1_TX 1 +#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE SC_P_UART1_TX 2 +#define SC_P_UART1_TX_LSIO_GPIO0_IO21 SC_P_UART1_TX 4 +#define SC_P_UART1_RX_ADMA_UART1_RX SC_P_UART1_RX 0 +#define SC_P_UART1_RX_LSIO_PWM1_OUT SC_P_UART1_RX 1 +#define SC_P_UART1_RX_LSIO_GPT0_COMPARE SC_P_UART1_RX 2 +#define SC_P_UART1_RX_LSIO_GPT1_CLK SC_P_UART1_RX 3 +#define SC_P_UART1_RX_LSIO_GPIO0_IO22 SC_P_UART1_RX 4 +#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B SC_P_UART1_RTS_B 0 +#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT SC_P_UART1_RTS_B 1 +#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16 SC_P_UART1_RTS_B 2 +#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE SC_P_UART1_RTS_B 3 +#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK SC_P_UART1_RTS_B 4 +#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B SC_P_UART1_CTS_B 0 +#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT SC_P_UART1_CTS_B 1 +#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17 SC_P_UART1_CTS_B 2 +#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE SC_P_UART1_CTS_B 3 +#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24 SC_P_UART1_CTS_B 4 +#define SC_P_SAI0_TXD_ADMA_SAI0_TXD SC_P_SAI0_TXD 0 +#define SC_P_SAI0_TXD_ADMA_SAI1_RXC SC_P_SAI0_TXD 1 +#define SC_P_SAI0_TXD_ADMA_SPI1_SDO SC_P_SAI0_TXD 2 +#define SC_P_SAI0_TXD_ADMA_LCDIF_D18 SC_P_SAI0_TXD 3 +#define SC_P_SAI0_TXD_LSIO_GPIO0_IO25 SC_P_SAI0_TXD 4 +#define SC_P_SAI0_TXC_ADMA_SAI0_TXC SC_P_SAI0_TXC 0 +#define SC_P_SAI0_TXC_ADMA_SAI1_TXD SC_P_SAI0_TXC 1 +#define SC_P_SAI0_TXC_ADMA_SPI1_SDI SC_P_SAI0_TXC 2 +#define SC_P_SAI0_TXC_ADMA_LCDIF_D19 SC_P_SAI0_TXC 3 +#define SC_P_SAI0_TXC_LSIO_GPIO0_IO26 SC_P_SAI0_TXC 4 +#define SC_P_SAI0_RXD_ADMA_SAI0_RXD SC_P_SAI0_RXD 0 +#define SC_P_SAI0_RXD_ADMA_SAI1_RXFS SC_P_SAI0_RXD 1 +#define SC_P_SAI0_RXD_ADMA_SPI1_CS0 SC_P_SAI0_RXD 2 +#define SC_P_SAI0_RXD_ADMA_LCDIF_D20 SC_P_SAI0_RXD 3 +#define SC_P_SAI0_RXD_LSIO_GPIO0_IO27 SC_P_SAI0_RXD 4 +#define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS SC_P_SAI0_TXFS 0 +#define SC_P_SAI0_TXFS_ADMA_SPI2_CS1 SC_P_SAI0_TXFS 1 +#define SC_P_SAI0_TXFS_ADMA_SPI1_SCK SC_P_SAI0_TXFS 2 +#define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 SC_P_SAI0_TXFS 4 +#define SC_P_SAI1_RXD_ADMA_SAI1_RXD SC_P_SAI1_RXD 0 +#define SC_P_SAI1_RXD_ADMA_SAI0_RXFS SC_P_SAI1_RXD 1 +#define SC_P_SAI1_RXD_ADMA_SPI1_CS1 SC_P_SAI1_RXD 2 +#define SC_P_SAI1_RXD_ADMA_LCDIF_D21 SC_P_SAI1_RXD 3 +#define SC_P_SAI1_RXD_LSIO_GPIO0_IO29 SC_P_SAI1_RXD 4 +#define SC_P_SAI1_RXC_ADMA_SAI1_RXC SC_P_SAI1_RXC 0 +#define SC_P_SAI1_RXC_ADMA_SAI1_TXC SC_P_SAI1_RXC 1 +#define SC_P_SAI1_RXC_ADMA_LCDIF_D22 SC_P_SAI1_RXC 3 +#define SC_P_SAI1_RXC_LSIO_GPIO0_IO30 SC_P_SAI1_RXC 4 +#define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS SC_P_SAI1_RXFS 0 +#define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS SC_P_SAI1_RXFS 1 +#define SC_P_SAI1_RXFS_ADMA_LCDIF_D23 SC_P_SAI1_RXFS 3 +#define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 SC_P_SAI1_RXFS 4 +#define SC_P_SPI2_CS0_ADMA_SPI2_CS0 SC_P_SPI2_CS0 0 +#define SC_P_SPI2_CS0_LSIO_GPIO1_IO00 SC_P_SPI2_CS0 4 +#define SC_P_SPI2_SDO_ADMA_SPI2_SDO SC_P_SPI2_SDO 0 +#define SC_P_SPI2_SDO_LSIO_GPIO1_IO01 SC_P_SPI2_SDO 4 +#define SC_P_SPI2_SDI_ADMA_SPI2_SDI SC_P_SPI2_SDI 0 +#define SC_P_SPI2_SDI_LSIO_GPIO1_IO02 SC_P_SPI2_SDI 4 +#define SC_P_SPI2_SCK_ADMA_SPI2_SCK SC_P_SPI2_SCK 0 +#define SC_P_SPI2_SCK_LSIO_GPIO1_IO03 SC_P_SPI2_SCK 4 +#define SC_P_SPI0_SCK_ADMA_SPI0_SCK SC_P_SPI0_SCK 0 +#define SC_P_SPI0_SCK_ADMA_SAI0_TXC SC_P_SPI0_SCK 1 +#define SC_P_SPI0_SCK_M40_I2C0_SCL SC_P_SPI0_SCK 2 +#define SC_P_SPI0_SCK_M40_GPIO0_IO00 SC_P_SPI0_SCK 3 +#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04 SC_P_SPI0_SCK 4 +#define SC_P_SPI0_SDI_ADMA_SPI0_SDI SC_P_SPI0_SDI 0 +#define SC_P_SPI0_SDI_ADMA_SAI0_TXD SC_P_SPI0_SDI 1 +#define SC_P_SPI0_SDI_M40_TPM0_CH0 SC_P_SPI0_SDI 2 +#define SC_P_SPI0_SDI_M40_GPIO0_IO02 SC_P_SPI0_SDI 3 +#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05 SC_P_SPI0_SDI 4 +#define SC_P_SPI0_SDO_ADMA_SPI0_SDO SC_P_SPI0_SDO 0 +#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS SC_P_SPI0_SDO 1 +#define SC_P_SPI0_SDO_M40_I2C0_SDA SC_P_SPI0_SDO 2 +#define SC_P_SPI0_SDO_M40_GPIO0_IO01 SC_P_SPI0_SDO 3 +#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06 SC_P_SPI0_SDO 4 +#define SC_P_SPI0_CS1_ADMA_SPI0_CS1 SC_P_SPI0_CS1 0 +#define SC_P_SPI0_CS1_ADMA_SAI0_RXC SC_P_SPI0_CS1 1 +#define SC_P_SPI0_CS1_ADMA_SAI1_TXD SC_P_SPI0_CS1 2 +#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT SC_P_SPI0_CS1 3 +#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07 SC_P_SPI0_CS1 4 +#define SC_P_SPI0_CS0_ADMA_SPI0_CS0 SC_P_SPI0_CS0 0 +#define SC_P_SPI0_CS0_ADMA_SAI0_RXD SC_P_SPI0_CS0 1 +#define SC_P_SPI0_CS0_M40_TPM0_CH1 SC_P_SPI0_CS0 2 +#define SC_P_SPI0_CS0_M40_GPIO0_IO03 SC_P_SPI0_CS0 3 +#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08 SC_P_SPI0_CS0 4 +#define SC_P_ADC_IN1_ADMA_ADC_IN1 SC_P_ADC_IN1 0 +#define SC_P_ADC_IN1_M40_I2C0_SDA SC_P_ADC_IN1 1 +#define SC_P_ADC_IN1_M40_GPIO0_IO01 SC_P_ADC_IN1 2 +#define SC_P_ADC_IN1_LSIO_GPIO1_IO09 SC_P_ADC_IN1 4 +#define SC_P_ADC_IN0_ADMA_ADC_IN0 SC_P_ADC_IN0 0 +#define SC_P_ADC_IN0_M40_I2C0_SCL SC_P_ADC_IN0 1 +#define SC_P_ADC_IN0_M40_GPIO0_IO00 SC_P_ADC_IN0 2 +#define SC_P_ADC_IN0_LSIO_GPIO1_IO10 SC_P_ADC_IN0 4 +#define SC_P_ADC_IN3_ADMA_ADC_IN3 SC_P_ADC_IN3 0 +#define SC_P_ADC_IN3_M40_UART0_TX SC_P_ADC_IN3 1 +#define SC_P_ADC_IN3_M40_GPIO0_IO03 SC_P_ADC_IN3 2 +#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 SC_P_ADC_IN3 3 +#define SC_P_ADC_IN3_LSIO_GPIO1_IO11 SC_P_ADC_IN3 4 +#define SC_P_ADC_IN2_ADMA_ADC_IN2 SC_P_ADC_IN2 0 +#define SC_P_ADC_IN2_M40_UART0_RX SC_P_ADC_IN2 1 +#define SC_P_ADC_IN2_M40_GPIO0_IO02 SC_P_ADC_IN2 2 +#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0 SC_P_ADC_IN2 3 +#define SC_P_ADC_IN2_LSIO_GPIO1_IO12 SC_P_ADC_IN2 4 +#define SC_P_ADC_IN5_ADMA_ADC_IN5 SC_P_ADC_IN5 0 +#define SC_P_ADC_IN5_M40_TPM0_CH1 SC_P_ADC_IN5 1 +#define SC_P_ADC_IN5_M40_GPIO0_IO05 SC_P_ADC_IN5 2 +#define SC_P_ADC_IN5_LSIO_GPIO1_IO13 SC_P_ADC_IN5 4 +#define SC_P_ADC_IN4_ADMA_ADC_IN4 SC_P_ADC_IN4 0 +#define SC_P_ADC_IN4_M40_TPM0_CH0 SC_P_ADC_IN4 1 +#define SC_P_ADC_IN4_M40_GPIO0_IO04 SC_P_ADC_IN4 2 +#define SC_P_ADC_IN4_LSIO_GPIO1_IO14 SC_P_ADC_IN4 4 +#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0 +#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC SC_P_FLEXCAN0_RX 1 +#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B SC_P_FLEXCAN0_RX 2 +#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC SC_P_FLEXCAN0_RX 3 +#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15 SC_P_FLEXCAN0_RX 4 +#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0 +#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD SC_P_FLEXCAN0_TX 1 +#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B SC_P_FLEXCAN0_TX 2 +#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS SC_P_FLEXCAN0_TX 3 +#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16 SC_P_FLEXCAN0_TX 4 +#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0 +#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS SC_P_FLEXCAN1_RX 1 +#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2 SC_P_FLEXCAN1_RX 2 +#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD SC_P_FLEXCAN1_RX 3 +#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 SC_P_FLEXCAN1_RX 4 +#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0 +#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC SC_P_FLEXCAN1_TX 1 +#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 SC_P_FLEXCAN1_TX 2 +#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD SC_P_FLEXCAN1_TX 3 +#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 SC_P_FLEXCAN1_TX 4 +#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0 +#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD SC_P_FLEXCAN2_RX 1 +#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX SC_P_FLEXCAN2_RX 2 +#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS SC_P_FLEXCAN2_RX 3 +#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19 SC_P_FLEXCAN2_RX 4 +#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0 +#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS SC_P_FLEXCAN2_TX 1 +#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX SC_P_FLEXCAN2_TX 2 +#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC SC_P_FLEXCAN2_TX 3 +#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20 SC_P_FLEXCAN2_TX 4 +#define SC_P_UART0_RX_ADMA_UART0_RX SC_P_UART0_RX 0 +#define SC_P_UART0_RX_ADMA_MQS_R SC_P_UART0_RX 1 +#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX SC_P_UART0_RX 2 +#define SC_P_UART0_RX_SCU_UART0_RX SC_P_UART0_RX 3 +#define SC_P_UART0_RX_LSIO_GPIO1_IO21 SC_P_UART0_RX 4 +#define SC_P_UART0_TX_ADMA_UART0_TX SC_P_UART0_TX 0 +#define SC_P_UART0_TX_ADMA_MQS_L SC_P_UART0_TX 1 +#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX SC_P_UART0_TX 2 +#define SC_P_UART0_TX_SCU_UART0_TX SC_P_UART0_TX 3 +#define SC_P_UART0_TX_LSIO_GPIO1_IO22 SC_P_UART0_TX 4 +#define SC_P_UART2_TX_ADMA_UART2_TX SC_P_UART2_TX 0 +#define SC_P_UART2_TX_ADMA_FTM_CH1 SC_P_UART2_TX 1 +#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX SC_P_UART2_TX 2 +#define SC_P_UART2_TX_LSIO_GPIO1_IO23 SC_P_UART2_TX 4 +#define SC_P_UART2_RX_ADMA_UART2_RX SC_P_UART2_RX 0 +#define SC_P_UART2_RX_ADMA_FTM_CH0 SC_P_UART2_RX 1 +#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX SC_P_UART2_RX 2 +#define SC_P_UART2_RX_LSIO_GPIO1_IO24 SC_P_UART2_RX 4 +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0 +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 SC_P_MIPI_DSI0_I2C0_SCL 1 +#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_DSI0_I2C0_SCL 4 +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0 +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 SC_P_MIPI_DSI0_I2C0_SDA 1 +#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_DSI0_I2C0_SDA 4 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0 +#define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL SC_P_MIPI_DSI0_GPIO0_00 1 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 2 +#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_DSI0_GPIO0_00 4 +#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0 +#define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA SC_P_MIPI_DSI0_GPIO0_01 1 +#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_DSI0_GPIO0_01 4 +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0 +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 SC_P_MIPI_DSI1_I2C0_SCL 1 +#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 SC_P_MIPI_DSI1_I2C0_SCL 4 +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0 +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 SC_P_MIPI_DSI1_I2C0_SDA 1 +#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 SC_P_MIPI_DSI1_I2C0_SDA 4 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0 +#define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL SC_P_MIPI_DSI1_GPIO0_00 1 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 2 +#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 SC_P_MIPI_DSI1_GPIO0_00 4 +#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0 +#define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA SC_P_MIPI_DSI1_GPIO0_01 1 +#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 SC_P_MIPI_DSI1_GPIO0_01 4 +#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B SC_P_JTAG_TRST_B 0 +#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT SC_P_JTAG_TRST_B 1 +#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0 +#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON SC_P_PMIC_I2C_SCL 1 +#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01 SC_P_PMIC_I2C_SCL 4 +#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0 +#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON SC_P_PMIC_I2C_SDA 1 +#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02 SC_P_PMIC_I2C_SDA 4 +#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0 +#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0 +#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1 +#define SC_P_SCU_GPIO0_00_M40_UART0_RX SC_P_SCU_GPIO0_00 2 +#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX SC_P_SCU_GPIO0_00 3 +#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 SC_P_SCU_GPIO0_00 4 +#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0 +#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1 +#define SC_P_SCU_GPIO0_01_M40_UART0_TX SC_P_SCU_GPIO0_01 2 +#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX SC_P_SCU_GPIO0_01 3 +#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT SC_P_SCU_GPIO0_01 4 +#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY SC_P_SCU_PMIC_STANDBY 0 +#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0 +#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0 +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0 +#define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE2 1 +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0 +#define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE3 1 +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_BOOT_MODE3 3 +#define SC_P_CSI_D00_CI_PI_D02 SC_P_CSI_D00 0 +#define SC_P_CSI_D00_ADMA_SAI0_RXC SC_P_CSI_D00 2 +#define SC_P_CSI_D01_CI_PI_D03 SC_P_CSI_D01 0 +#define SC_P_CSI_D01_ADMA_SAI0_RXD SC_P_CSI_D01 2 +#define SC_P_CSI_D02_CI_PI_D04 SC_P_CSI_D02 0 +#define SC_P_CSI_D02_ADMA_SAI0_RXFS SC_P_CSI_D02 2 +#define SC_P_CSI_D03_CI_PI_D05 SC_P_CSI_D03 0 +#define SC_P_CSI_D03_ADMA_SAI2_RXC SC_P_CSI_D03 2 +#define SC_P_CSI_D04_CI_PI_D06 SC_P_CSI_D04 0 +#define SC_P_CSI_D04_ADMA_SAI2_RXD SC_P_CSI_D04 2 +#define SC_P_CSI_D05_CI_PI_D07 SC_P_CSI_D05 0 +#define SC_P_CSI_D05_ADMA_SAI2_RXFS SC_P_CSI_D05 2 +#define SC_P_CSI_D06_CI_PI_D08 SC_P_CSI_D06 0 +#define SC_P_CSI_D06_ADMA_SAI3_RXC SC_P_CSI_D06 2 +#define SC_P_CSI_D07_CI_PI_D09 SC_P_CSI_D07 0 +#define SC_P_CSI_D07_ADMA_SAI3_RXD SC_P_CSI_D07 2 +#define SC_P_CSI_HSYNC_CI_PI_HSYNC SC_P_CSI_HSYNC 0 +#define SC_P_CSI_HSYNC_CI_PI_D00 SC_P_CSI_HSYNC 1 +#define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS SC_P_CSI_HSYNC 2 +#define SC_P_CSI_VSYNC_CI_PI_VSYNC SC_P_CSI_VSYNC 0 +#define SC_P_CSI_VSYNC_CI_PI_D01 SC_P_CSI_VSYNC 1 +#define SC_P_CSI_PCLK_CI_PI_PCLK SC_P_CSI_PCLK 0 +#define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL SC_P_CSI_PCLK 1 +#define SC_P_CSI_PCLK_ADMA_SPI1_SCK SC_P_CSI_PCLK 3 +#define SC_P_CSI_PCLK_LSIO_GPIO3_IO00 SC_P_CSI_PCLK 4 +#define SC_P_CSI_MCLK_CI_PI_MCLK SC_P_CSI_MCLK 0 +#define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA SC_P_CSI_MCLK 1 +#define SC_P_CSI_MCLK_ADMA_SPI1_SDO SC_P_CSI_MCLK 3 +#define SC_P_CSI_MCLK_LSIO_GPIO3_IO01 SC_P_CSI_MCLK 4 +#define SC_P_CSI_EN_CI_PI_EN SC_P_CSI_EN 0 +#define SC_P_CSI_EN_CI_PI_I2C_SCL SC_P_CSI_EN 1 +#define SC_P_CSI_EN_ADMA_I2C3_SCL SC_P_CSI_EN 2 +#define SC_P_CSI_EN_ADMA_SPI1_SDI SC_P_CSI_EN 3 +#define SC_P_CSI_EN_LSIO_GPIO3_IO02 SC_P_CSI_EN 4 +#define SC_P_CSI_RESET_CI_PI_RESET SC_P_CSI_RESET 0 +#define SC_P_CSI_RESET_CI_PI_I2C_SDA SC_P_CSI_RESET 1 +#define SC_P_CSI_RESET_ADMA_I2C3_SDA SC_P_CSI_RESET 2 +#define SC_P_CSI_RESET_ADMA_SPI1_CS0 SC_P_CSI_RESET 3 +#define SC_P_CSI_RESET_LSIO_GPIO3_IO03 SC_P_CSI_RESET 4 +#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0 +#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 SC_P_MIPI_CSI0_MCLK_OUT 4 +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0 +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 SC_P_MIPI_CSI0_I2C0_SCL 1 +#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 SC_P_MIPI_CSI0_I2C0_SCL 4 +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0 +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 SC_P_MIPI_CSI0_I2C0_SDA 1 +#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 SC_P_MIPI_CSI0_I2C0_SDA 4 +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0 +#define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1 +#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 SC_P_MIPI_CSI0_GPIO0_01 4 +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0 +#define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1 +#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 SC_P_MIPI_CSI0_GPIO0_00 4 +#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0 +#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 SC_P_QSPI0A_DATA0 4 +#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0 +#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 SC_P_QSPI0A_DATA1 4 +#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0 +#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 SC_P_QSPI0A_DATA2 4 +#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0 +#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 SC_P_QSPI0A_DATA3 4 +#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0 +#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 SC_P_QSPI0A_DQS 4 +#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0 +#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 SC_P_QSPI0A_SS0_B 4 +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0 +#define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 SC_P_QSPI0A_SS1_B 4 +#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0 +#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 SC_P_QSPI0A_SCLK 4 +#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0 +#define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI0B_SCLK 1 +#define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0 SC_P_QSPI0B_SCLK 2 +#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 SC_P_QSPI0B_SCLK 4 +#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0 +#define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI0B_DATA0 1 +#define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1 SC_P_QSPI0B_DATA0 2 +#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 SC_P_QSPI0B_DATA0 4 +#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0 +#define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI0B_DATA1 1 +#define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2 SC_P_QSPI0B_DATA1 2 +#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 SC_P_QSPI0B_DATA1 4 +#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0 +#define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI0B_DATA2 1 +#define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3 SC_P_QSPI0B_DATA2 2 +#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 SC_P_QSPI0B_DATA2 4 +#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0 +#define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI0B_DATA3 1 +#define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0 SC_P_QSPI0B_DATA3 2 +#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 SC_P_QSPI0B_DATA3 4 +#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0 +#define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS SC_P_QSPI0B_DQS 1 +#define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1 SC_P_QSPI0B_DQS 2 +#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 SC_P_QSPI0B_DQS 4 +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0 +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI0B_SS0_B 1 +#define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2 SC_P_QSPI0B_SS0_B 2 +#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 SC_P_QSPI0B_SS0_B 4 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI0B_SS1_B 1 +#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3 SC_P_QSPI0B_SS1_B 2 +#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4 + +#endif /* _SC_PADS_H */ diff --git a/roms/u-boot/include/dt-bindings/pinctrl/pinctrl-snapdragon.h b/roms/u-boot/include/dt-bindings/pinctrl/pinctrl-snapdragon.h new file mode 100644 index 000000000..615affb6f --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/pinctrl-snapdragon.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This header provides constants for Qualcomm Snapdragon pinctrl bindings. + * + * (C) Copyright 2018 Ramon Fried + * + */ + +#ifndef _DT_BINDINGS_PINCTRL_SNAPDRAGON_H +#define _DT_BINDINGS_PINCTRL_SNAPDRAGON_H + +/* GPIO Drive Strength */ +#define DRIVE_STRENGTH_2MA 0 +#define DRIVE_STRENGTH_4MA 1 +#define DRIVE_STRENGTH_6MA 2 +#define DRIVE_STRENGTH_8MA 3 +#define DRIVE_STRENGTH_10MA 4 +#define DRIVE_STRENGTH_12MA 5 +#define DRIVE_STRENGTH_14MA 6 +#define DRIVE_STRENGTH_16MA 7 + +#endif diff --git a/roms/u-boot/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h b/roms/u-boot/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h new file mode 100644 index 000000000..914d56da9 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h @@ -0,0 +1,7 @@ +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H +#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1 + +#define TEGRA_XUSB_PADCTL_PCIE 0 +#define TEGRA_XUSB_PADCTL_SATA 1 + +#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */ diff --git a/roms/u-boot/include/dt-bindings/pinctrl/pinctrl-tegra.h b/roms/u-boot/include/dt-bindings/pinctrl/pinctrl-tegra.h new file mode 100644 index 000000000..c9b57408d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/pinctrl-tegra.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for Tegra pinctrl bindings. + * + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * Author: Laxman Dewangan + */ + +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H +#define _DT_BINDINGS_PINCTRL_TEGRA_H + +/* + * Enable/disable for diffeent dt properties. This is applicable for + * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, + * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. + */ +#define TEGRA_PIN_DISABLE 0 +#define TEGRA_PIN_ENABLE 1 + +#define TEGRA_PIN_PULL_NONE 0 +#define TEGRA_PIN_PULL_DOWN 1 +#define TEGRA_PIN_PULL_UP 2 + +/* Low power mode driver */ +#define TEGRA_PIN_LP_DRIVE_DIV_8 0 +#define TEGRA_PIN_LP_DRIVE_DIV_4 1 +#define TEGRA_PIN_LP_DRIVE_DIV_2 2 +#define TEGRA_PIN_LP_DRIVE_DIV_1 3 + +/* Rising/Falling slew rate */ +#define TEGRA_PIN_SLEW_RATE_FASTEST 0 +#define TEGRA_PIN_SLEW_RATE_FAST 1 +#define TEGRA_PIN_SLEW_RATE_SLOW 2 +#define TEGRA_PIN_SLEW_RATE_SLOWEST 3 + +#endif diff --git a/roms/u-boot/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/roms/u-boot/include/dt-bindings/pinctrl/pinctrl-zynqmp.h new file mode 100644 index 000000000..cdb215734 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/pinctrl-zynqmp.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * MIO pin configuration defines for Xilinx ZynqMP + * + * Copyright (C) 2020 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H +#define _DT_BINDINGS_PINCTRL_ZYNQMP_H + +/* Bit value for different voltage levels */ +#define IO_STANDARD_LVCMOS33 0 +#define IO_STANDARD_LVCMOS18 1 + +/* Bit values for Slew Rates */ +#define SLEW_RATE_FAST 0 +#define SLEW_RATE_SLOW 1 + +#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ diff --git a/roms/u-boot/include/dt-bindings/pinctrl/pins-imx8mq.h b/roms/u-boot/include/dt-bindings/pinctrl/pins-imx8mq.h new file mode 100644 index 000000000..0e1d67d41 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/pins-imx8mq.h @@ -0,0 +1,632 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DTS_IMX8MQ_PINFUNC_H +#define __DTS_IMX8MQ_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ + +#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 +#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 +#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 +#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 +#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 +#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 +#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 +#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 +#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 +#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 +#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 +#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 +#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 +#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 +#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 +#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 +#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 +#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 +#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 +#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 +#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 +#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0 + +#endif /* __DTS_IMX8MQ_PINFUNC_H */ diff --git a/roms/u-boot/include/dt-bindings/pinctrl/pins-imxrt1020.h b/roms/u-boot/include/dt-bindings/pinctrl/pins-imxrt1020.h new file mode 100644 index 000000000..b3a833bde --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/pins-imxrt1020.h @@ -0,0 +1,761 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 + * Author(s): Giulio Benetti + */ + +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H +#define _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H + +#define IMX_PAD_SION 0x40000000 + +/* + * The pin function ID is a tuple of + * + */ + +#define MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x188 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_00_QTIMER2_TIMER0 0x014 0x188 0x420 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_00_LPUART4_CTS_B 0x014 0x188 0x3E0 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_00_SPDIF_SR_CLK 0x014 0x188 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x188 0x3B0 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_00_GPIO2_IO00 0x014 0x188 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_00_FLEXCAN1_TX 0x014 0x188 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_00_PIT_TRIGGER02 0x014 0x188 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x18C 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_01_QTIMER2_TIMER1 0x018 0x18C 0x424 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_01_LPUART4_RTS_B 0x018 0x18C 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_01_SPDIF_OUT 0x018 0x18C 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x18C 0x3AC 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_01_GPIO2_IO01 0x018 0x18C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_01_FLEXCAN1_RX 0x018 0x18C 0x320 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_01_PIT_TRIGGER03 0x018 0x18C 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x190 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_02_QTIMER2_TIMER2 0x01C 0x190 0x428 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_02_LPUART4_TX 0x01C 0x190 0x3E8 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_02_SPDIF_LOCK 0x01C 0x190 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x190 0x3B8 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_02_GPIO2_IO02 0x01C 0x190 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_02_LPI2C1_SCL 0x01C 0x190 0x37C 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x194 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_03_QTIMER2_TIMER3 0x020 0x194 0x42C 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_03_LPUART4_RX 0x020 0x194 0x3E4 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_03_SPDIF_EXT_CLK 0x020 0x194 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x194 0x3B4 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_03_GPIO2_IO03 0x020 0x194 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_03_LPI2C1_SDA 0x020 0x194 0x380 0x6 0x1 + +#define MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x198 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_04_XBAR1_INOUT04 0x024 0x198 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_04_SPDIF_OUT 0x024 0x198 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK 0x024 0x198 0x464 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16 0x024 0x198 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_04_GPIO2_IO04 0x024 0x198 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x19C 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_05_XBAR1_INOUT05 0x028 0x19C 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_05_SPDIF_IN 0x028 0x19C 0x488 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x19C 0x468 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17 0x028 0x19C 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_05_GPIO2_IO05 0x028 0x19C 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x1A0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_06_XBAR1_INOUT06 0x02C 0x1A0 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_06_LPUART3_TX 0x02C 0x1A0 0x3DC 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_06_SAI2_TX_DATA 0x02C 0x1A0 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18 0x02C 0x1A0 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_06_GPIO2_IO06 0x02C 0x1A0 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x1A4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_07_XBAR1_INOUT07 0x030 0x1A4 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_07_LPUART3_RX 0x030 0x1A4 0x3D8 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC 0x030 0x1A4 0x460 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19 0x030 0x1A4 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_07_GPIO2_IO07 0x030 0x1A4 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x1A8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_08_XBAR1_INOUT08 0x034 0x1A8 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_08_FLEXCAN2_TX 0x034 0x1A8 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x1A8 0x45C 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20 0x034 0x1A8 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_08_GPIO2_IO08 0x034 0x1A8 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x1AC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_09_XBAR1_INOUT09 0x038 0x1AC 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_09_FLEXCAN2_RX 0x038 0x1AC 0x324 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK 0x038 0x1AC 0x458 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21 0x038 0x1AC 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_09_GPIO2_IO09 0x038 0x1AC 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_10_SEMC_CAS 0x03C 0x1B0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_10_XBAR1_INOUT10 0x03C 0x1B0 0x4B0 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_10_LPI2C4_SDA 0x03C 0x1B0 0x398 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_10_SAI1_TX_SYNC 0x03C 0x1B0 0x450 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_10_LPSPI2_SCK 0x03C 0x1B0 0x3B0 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_10_GPIO2_IO10 0x03C 0x1B0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMX00 0x03C 0x1B0 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_11_SEMC_RAS 0x040 0x1B4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_11_XBAR1_INOUT11 0x040 0x1B4 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_11_LPI2C4_SCL 0x040 0x1B4 0x394 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_11_SAI1_TX_BCLK 0x040 0x1B4 0x44C 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_11_LPSPI2_PCS0 0x040 0x1B4 0x3AC 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_11_GPIO2_IO11 0x040 0x1B4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMX01 0x040 0x1B4 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_12_SEMC_CS0 0x044 0x1B8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_12_XBAR1_INOUT12 0x044 0x1B8 0x4B4 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_12_LPUART6_TX 0x044 0x1B8 0x3F8 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_12_SAI1_TX_DATA00 0x044 0x1B8 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_12_LPSPI2_SDO 0x044 0x1B8 0x3B8 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_12_GPIO2_IO12 0x044 0x1B8 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_12_FLEXPWM2_PWMX02 0x044 0x1B8 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_13_SEMC_BA0 0x048 0x1BC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_13_XBAR1_INOUT13 0x048 0x1BC 0x4B8 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_13_LPUART6_RX 0x048 0x1BC 0x3F4 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_13_SAI1_RX_DATA00 0x048 0x1BC 0x438 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_13_LPSPI2_SDI 0x048 0x1BC 0x3B4 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_13_GPIO2_IO13 0x048 0x1BC 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_13_FLEXPWM2_PWMX03 0x048 0x1BC 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_13_CCM_PMIC_RDY 0x048 0x1BC 0x300 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_14_SEMC_BA1 0x04C 0x1C0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_14_XBAR1_INOUT14 0x04C 0x1C0 0x4A0 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_14_LPUART6_CTS_B 0x04C 0x1C0 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_14_SAI1_RX_BCLK 0x04C 0x1C0 0x434 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x1C0 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_14_GPIO2_IO14 0x04C 0x1C0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_14_FLEXCAN1_TX 0x04C 0x1C0 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_15_SEMC_ADDR10 0x050 0x1C4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_15_XBAR1_INOUT15 0x050 0x1C4 0x4A4 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_15_LPUART6_RTS_B 0x050 0x1C4 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_15_SAI1_RX_SYNC 0x050 0x1C4 0x448 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_15_WDOG1_B 0x050 0x1C4 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_15_GPIO2_IO15 0x050 0x1C4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_15_FLEXCAN1_RX 0x050 0x1C4 0x320 0x6 0x3 + +#define MXRT1020_IOMUXC_GPIO_EMC_16_SEMC_ADDR00 0x054 0x1C8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_16_MQS_RIGHT 0x054 0x1C8 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_16_SAI2_MCLK 0x054 0x1C8 0x454 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_16_GPIO2_IO16 0x054 0x1C8 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE00 0x054 0x1C8 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_17_SEMC_ADDR01 0x058 0x1CC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_17_MQS_LEFT 0x058 0x1CC 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_17_SAI3_MCLK 0x058 0x1CC 0x46C 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_17_GPIO2_IO17 0x058 0x1CC 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE01 0x058 0x1CC 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_18_SEMC_ADDR02 0x05C 0x1D0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_18_XBAR1_INOUT16 0x05C 0x1D0 0x4A8 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_18_LPI2C2_SDA 0x05C 0x1D0 0x388 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC 0x05C 0x1D0 0x448 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22 0x05C 0x1D0 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_18_GPIO2_IO18 0x05C 0x1D0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_18_SRC_BT_CFG00 0x05C 0x1D0 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_19_SEMC_ADDR03 0x060 0x1D4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_19_XBAR1_INOUT17 0x060 0x1D4 0x4AC 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_19_LPI2C2_SCL 0x060 0x1D4 0x384 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK 0x060 0x1D4 0x434 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23 0x060 0x1D4 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_19_GPIO2_IO19 0x060 0x1D4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_19_SRC_BT_CFG01 0x060 0x1D4 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_20_SEMC_ADDR04 0x064 0x1D8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA03 0x064 0x1D8 0x334 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_20_LPUART2_CTS_B 0x064 0x1D8 0x3CC 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_20_SAI1_MCLK 0x064 0x1D8 0x430 0x3 0x3 +#define MXRT1020_IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24 0x064 0x1D8 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_20_GPIO2_IO20 0x064 0x1D8 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_20_SRC_BT_CFG02 0x064 0x1D8 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_21_SEMC_ADDR05 0x068 0x1DC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB03 0x068 0x1DC 0x344 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_21_LPUART2_RTS_B 0x068 0x1DC 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_21_SAI1_RX_DATA00 0x068 0x1DC 0x438 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25 0x068 0x1DC 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_21_GPIO2_IO21 0x068 0x1DC 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_21_SRC_BT_CFG03 0x068 0x1DC 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_22_SEMC_ADDR06 0x06C 0x1E0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA02 0x06C 0x1E0 0x330 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_22_LPUART2_TX 0x06C 0x1E0 0x3D4 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_22_SAI1_TX_DATA03 0x06C 0x1E0 0x43C 0x3 0x1 + +#define MXRT1020_IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26 0x06C 0x1E0 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_22_GPIO2_IO22 0x06C 0x1E0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_22_SRC_BT_CFG04 0x06C 0x1E0 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_23_SEMC_ADDR07 0x070 0x1E4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB02 0x070 0x1E4 0x340 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_23_LPUART2_RX 0x070 0x1E4 0x3D0 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_23_SAI1_TX_DATA02 0x070 0x1E4 0x440 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27 0x070 0x1E4 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_23_GPIO2_IO23 0x070 0x1E4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_23_SRC_BT_CFG05 0x070 0x1E4 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_24_SEMC_ADDR08 0x074 0x1E8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA01 0x074 0x1E8 0x32C 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_24_LPUART8_CTS_B 0x074 0x1E8 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_24_SAI1_TX_DATA01 0x074 0x1E8 0x444 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28 0x074 0x1E8 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_24_GPIO2_IO24 0x074 0x1E8 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_24_SRC_BT_CFG06 0x074 0x1E8 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_25_SEMC_ADDR09 0x078 0x1EC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB01 0x078 0x1EC 0x33C 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_25_LPUART8_RTS_B 0x078 0x1EC 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_25_SAI1_TX_DATA00 0x078 0x1EC 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29 0x078 0x1EC 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_25_GPIO2_IO25 0x078 0x1EC 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_25_SRC_BT_CFG07 0x078 0x1EC 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_26_SEMC_ADDR11 0x07C 0x1F0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA00 0x07C 0x1F0 0x328 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_26_LPUART8_TX 0x07C 0x1F0 0x408 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK 0x07C 0x1F0 0x44C 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30 0x07C 0x1F0 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_26_GPIO2_IO26 0x07C 0x1F0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_26_SRC_BT_CFG08 0x07C 0x1F0 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_27_SEMC_ADDR12 0x080 0x1F4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB00 0x080 0x1F4 0x338 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_27_LPUART8_RX 0x080 0x1F4 0x404 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC 0x080 0x1F4 0x450 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31 0x080 0x1F4 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_27_GPIO2_IO27 0x080 0x1F4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_27_SRC_BT_CFG09 0x080 0x1F4 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_28_SEMC_DQS 0x084 0x1F8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_28_FLEXPWM2_PWMA03 0x084 0x1F8 0x354 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_28_XBAR1_INOUT18 0x084 0x1F8 0x4BC 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_28_SAI3_MCLK 0x084 0x1F8 0x46C 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_28_EWM_OUT_B 0x084 0x1F8 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_28_GPIO2_IO28 0x084 0x1F8 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_28_GPT2_CAPTURE2 0x084 0x1F8 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMX00 0x084 0x1F8 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_29_SEMC_CKE 0x088 0x1FC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_29_FLEXPWM2_PWMB03 0x088 0x1FC 0x364 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_29_XBAR1_INOUT19 0x088 0x1FC 0x4C0 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_29_SAI3_RX_BCLK 0x088 0x1FC 0x470 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_29_WDOG2_RST_B_DEB 0x088 0x1FC 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_29_GPIO2_IO29 0x088 0x1FC 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_29_GPT2_COMPARE2 0x088 0x1FC 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_29_FLEXPWM1_PWMX01 0x088 0x1FC 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_30_SEMC_CLK 0x08C 0x200 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_30_FLEXPWM2_PWMA02 0x08C 0x200 0x350 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_30_LPUART4_CTS_B 0x08C 0x200 0x3E0 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_30_SAI3_RX_SYNC 0x08C 0x200 0x478 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_30_WDOG1_RST_B_DEB 0x08C 0x200 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_30_GPIO2_IO30 0x08C 0x200 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_30_GPT2_COMPARE3 0x08C 0x200 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_30_FLEXPWM1_PWMX02 0x08C 0x200 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_31_SEMC_DM01 0x090 0x204 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_31_FLEXPWM2_PWMB02 0x090 0x204 0x360 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_31_LPUART4_RTS_B 0x090 0x204 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_31_SAI3_RX_DATA 0x090 0x204 0x474 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_31_WDOG2_B 0x090 0x204 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_31_GPIO2_IO31 0x090 0x204 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_31_GPT2_CLK 0x090 0x204 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_31_FLEXPWM1_PWMX03 0x090 0x204 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_32_SEMC_DATA08 0x094 0x208 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0 0x094 0x208 0x410 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_32_LPUART4_TX 0x094 0x208 0x3E8 0x2 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_32_SAI3_TX_DATA 0x094 0x208 0x000 0x3 0x4 +#define MXRT1020_IOMUXC_GPIO_EMC_32_LPSPI4_SCK 0x094 0x208 0x3C0 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_32_GPIO3_IO00 0x094 0x208 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_32_REF_24M_OUT 0x094 0x208 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_33_SEMC_DATA09 0x098 0x20C 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1 0x098 0x20C 0x414 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_33_LPUART4_RX 0x098 0x20C 0x3E4 0x2 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK 0x098 0x20C 0x47C 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_33_LPSPI4_PCS0 0x098 0x20C 0x3BC 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_33_GPIO3_IO01 0x098 0x20C 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_34_SEMC_DATA10 0x09C 0x210 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2 0x09C 0x210 0x418 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_34_LPUART7_TX 0x09C 0x210 0x400 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC 0x09C 0x210 0x480 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_34_LPSPI4_SDO 0x09C 0x210 0x3C8 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_34_GPIO3_IO02 0x09C 0x210 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_34_ENET_CRS 0x09C 0x210 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_35_SEMC_DATA11 0x0A0 0x214 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3 0x0A0 0x214 0x41C 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_35_LPUART7_RX 0x0A0 0x214 0x3FC 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_35_USDHC2_WP 0x0A0 0x214 0x49C 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_35_LPSPI4_SDI 0x0A0 0x214 0x3C4 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_35_GPIO3_IO03 0x0A0 0x214 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_35_ENET_COL 0x0A0 0x214 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_36_SEMC_DATA12 0x0A4 0x218 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_36_FLEXPWM2_PWMA01 0x0A4 0x218 0x34C 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_36_LPUART5_CTS_B 0x0A4 0x218 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_36_CCM_PMIC_RDY 0x0A4 0x218 0x300 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_36_LPSPI4_PCS1 0x0A4 0x218 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_36_GPIO3_IO04 0x0A4 0x218 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_36_ENET_RX_CLK 0x0A4 0x218 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x218 0x494 0x7 0x4 + +#define MXRT1020_IOMUXC_GPIO_EMC_37_SEMC_DATA13 0x0A8 0x21C 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_37_FLEXPWM2_PWMB01 0x0A8 0x21C 0x35C 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_37_LPUART5_RTS_B 0x0A8 0x21C 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_37_MQS_RIGHT 0x0A8 0x21C 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_37_LPSPI4_PCS2 0x0A8 0x21C 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_37_GPIO3_IO05 0x0A8 0x21C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_37_ENET_RDATA03 0x0A8 0x21C 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_37_USDHC1_VSELECT 0x0A8 0x21C 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_38_SEMC_DATA14 0x0AC 0x220 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_38_FLEXPWM2_PWMA00 0x0AC 0x220 0x348 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_38_LPUART5_TX 0x0AC 0x220 0x3F0 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_38_MQS_LEFT 0x0AC 0x220 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_38_LPSPI4_PCS3 0x0AC 0x220 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_38_GPIO3_IO06 0x0AC 0x220 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_38_ENET_RDATA02 0x0AC 0x220 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_38_USDHC1_CD_B 0x0AC 0x220 0x490 0x7 0x3 + +#define MXRT1020_IOMUXC_GPIO_EMC_39_SEMC_DATA15 0x0B0 0x224 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_39_FLEXPWM2_PWMB00 0x0B0 0x224 0x358 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_39_LPUART5_RX 0x0B0 0x224 0x3EC 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_39_USB_OTG1_OC 0x0B0 0x224 0x48C 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x224 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_39_GPIO3_IO07 0x0B0 0x224 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_39_ENET_TX_ER 0x0B0 0x224 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_39_GPT1_CLK 0x0B0 0x224 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_40_SEMC_CSX00 0x0B4 0x228 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_40_XBAR1_INOUT18 0x0B4 0x228 0x4BC 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_40_SPDIF_OUT 0x0B4 0x228 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_40_USB_OTG1_ID 0x0B4 0x228 0x2FC 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_40_ENET_MDIO 0x0B4 0x228 0x308 0x4 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_40_GPIO3_IO08 0x0B4 0x228 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_40_ENET_TDATA03 0x0B4 0x228 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_40_GPT1_COMPARE3 0x0B4 0x228 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_41_SEMC_READY 0x0B8 0x22C 0x484 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_41_XBAR1_INOUT19 0x0B8 0x22C 0x4C0 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_41_SPDIF_IN 0x0B8 0x22C 0x488 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_41_USB_OTG1_PWR 0x0B8 0x22C 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_41_ENET_MDC 0x0B8 0x22C 0x000 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_41_GPIO3_IO09 0x0B8 0x22C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_41_ENET_TDATA02 0x0B8 0x22C 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_41_GPT1_COMPARE2 0x0B8 0x22C 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_00_JTAG_TMS 0x0BC 0x230 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x230 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1 0x0BC 0x230 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_01_JTAG_TCK 0x0C0 0x234 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x234 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2 0x0C0 0x234 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_02_JTAG_MOD 0x0C4 0x238 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x238 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1 0x0C4 0x238 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_03_JTAG_TDI 0x0C8 0x23C 0x000 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_03_USDHC2_CD_B 0x0C8 0x23C 0x498 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_03_WDOG1_B 0x0C8 0x23C 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_03_SAI1_MCLK 0x0C8 0x23C 0x430 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_03_USDHC1_WP 0x0C8 0x23C 0x494 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x23C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x23C 0x48C 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY 0x0C8 0x23C 0x300 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_04_JTAG_TDO 0x0CC 0x240 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_04_FLEXCAN1_TX 0x0CC 0x240 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_04_USDHC1_WP 0x0CC 0x240 0x494 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_04_QTIMER2_TIMER0 0x0CC 0x240 0x420 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_04_ENET_MDIO 0x0CC 0x240 0x308 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x240 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR 0x0CC 0x240 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_04_EWM_OUT_B 0x0CC 0x240 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB 0x0D0 0x244 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_05_FLEXCAN1_RX 0x0D0 0x244 0x320 0x1 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B0_05_USDHC1_CD_B 0x0D0 0x244 0x490 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_05_QTIMER2_TIMER1 0x0D0 0x244 0x424 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_05_ENET_MDC 0x0D0 0x244 0x000 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x244 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID 0x0D0 0x244 0x2FC 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_05_NMI_GLUE_NMI 0x0D0 0x244 0x40C 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER00 0x0D4 0x248 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_06_MQS_RIGHT 0x0D4 0x248 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_06_LPUART1_TX 0x0D4 0x248 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_06_QTIMER2_TIMER2 0x0D4 0x248 0x428 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA03 0x0D4 0x248 0x354 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x248 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_06_REF_32K_OUT 0x0D4 0x248 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER01 0x0D8 0x24C 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_07_MQS_LEFT 0x0D8 0x24C 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_07_LPUART1_RX 0x0D8 0x24C 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_07_QTIMER2_TIMER3 0x0D8 0x24C 0x42C 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_07_FLEXPWM2_PWMB03 0x0D8 0x24C 0x364 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x24C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_07_REF_24M_OUT 0x0D8 0x24C 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK 0x0DC 0x250 0x31C 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL 0x0DC 0x250 0x38C 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B 0x0DC 0x250 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_08_KPP_COL00 0x0DC 0x250 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1 0x0DC 0x250 0x304 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x250 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV 0x0DC 0x250 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_09_ENET_RDATA01 0x0E0 0x254 0x310 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA 0x0E0 0x254 0x390 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B 0x0E0 0x254 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_09_KPP_ROW00 0x0E0 0x254 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x254 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV 0x0E0 0x254 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_10_ENET_RDATA00 0x0E4 0x258 0x30C 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK 0x0E4 0x258 0x3A0 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_10_LPUART5_TX 0x0E4 0x258 0x3F0 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_10_KPP_COL01 0x0E4 0x258 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA02 0x0E4 0x258 0x350 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x258 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_10_ARM_CM7_TRACE_CLK 0x0E4 0x258 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_11_ENET_RX_EN 0x0E8 0x25C 0x314 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 0x0E8 0x25C 0x39C 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_11_LPUART5_RX 0x0E8 0x25C 0x3EC 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_11_KPP_ROW01 0x0E8 0x25C 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_11_FLEXPWM2_PWMB02 0x0E8 0x25C 0x360 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x25C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_11_ARM_CM7_TRACE_SWO 0x0E8 0x25C 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_12_ENET_RX_ER 0x0EC 0x260 0x318 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO 0x0EC 0x260 0x3A8 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B 0x0EC 0x260 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_12_KPP_COL02 0x0EC 0x260 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA01 0x0EC 0x260 0x34C 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x260 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_12_ARM_CM7_TRACE00 0x0EC 0x260 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_12_SNVS_HP_VIO_5_CTL 0x0EC 0x260 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_13_ENET_TX_EN 0x0F0 0x264 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI 0x0F0 0x264 0x3A4 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B 0x0F0 0x264 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_13_KPP_ROW02 0x0F0 0x264 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_13_FLEXPWM2_PWMB01 0x0F0 0x264 0x35C 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x264 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_13_ARM_CM7_TRACE01 0x0F0 0x264 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_13_SNVS_HP_VIO_5_B 0x0F0 0x264 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_14_ENET_TDATA00 0x0F4 0x268 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x268 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_14_LPUART3_TX 0x0F4 0x268 0x3DC 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_14_KPP_COL03 0x0F4 0x268 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_14_FLEXPWM2_PWMA00 0x0F4 0x268 0x348 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x268 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_14_ARM_CM7_TRACE02 0x0F4 0x268 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_14_WDOG1_ANY 0x0F4 0x268 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_15_ENET_TDATA01 0x0F8 0x26C 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x26C 0x324 0x1 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B0_15_LPUART3_RX 0x0F8 0x26C 0x3D8 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_15_KPP_ROW03 0x0F8 0x26C 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_15_FLEXPWM2_PWMB00 0x0F8 0x26C 0x358 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x26C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_15_ARM_CM7_TRACE03 0x0F8 0x26C 0x000 0x6 0x2 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_00_SEMC_READY 0x0FC 0x270 0x484 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA03 0x0FC 0x270 0x374 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXCAN2_TX 0x0FC 0x270 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_00_SAI1_MCLK 0x0FC 0x270 0x430 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXIO1_FLEXIO15 0x0FC 0x270 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x270 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_00_ENET_1588_EVENT2_OUT 0x0FC 0x270 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_00_KPP_COL04 0x0FC 0x270 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_01_SEMC_CSX00 0x100 0x274 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK 0x100 0x274 0x378 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXCAN2_RX 0x100 0x274 0x324 0x2 0x3 +#define MXRT1020_IOMUXC_GPIO_AD_B1_01_SAI1_TX_BCLK 0x100 0x274 0x44C 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXIO1_FLEXIO14 0x100 0x274 0x000 0x4 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x274 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_01_ENET_1588_EVENT2_IN 0x100 0x274 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_01_KPP_ROW04 0x100 0x274 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_02_SEMC_CSX01 0x104 0x278 0x000 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA00 0x104 0x278 0x368 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_02_LPSPI4_SCK 0x104 0x278 0x3C0 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_02_SAI1_TX_SYNC 0x104 0x278 0x450 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B1_02_FLEXIO1_FLEXIO13 0x104 0x278 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x278 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT3_OUT 0x104 0x278 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_02_KPP_COL05 0x104 0x278 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_03_SEMC_CSX02 0x108 0x27C 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA02 0x108 0x27C 0x370 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_03_LPSPI4_PCS0 0x108 0x27C 0x3BC 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_03_SAI1_TX_DATA00 0x108 0x27C 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_03_FLEXIO1_FLEXIO12 0x108 0x27C 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x27C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT3_IN 0x108 0x27C 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_03_KPP_ROW05 0x108 0x27C 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_04_SEMC_CSX03 0x10C 0x280 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA01 0x10C 0x280 0x36C 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_04_LPSPI4_SDO 0x10C 0x280 0x3C8 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_04_SAI1_RX_SYNC 0x10C 0x280 0x448 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_04_FLEXIO1_FLEXIO11 0x10C 0x280 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x280 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_04_LPSPI1_PCS1 0x10C 0x280 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_04_KPP_COL06 0x10C 0x280 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_05_USDHC1_WP 0x110 0x284 0x494 0x0 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B 0x110 0x284 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_05_LPSPI4_SDI 0x110 0x284 0x3C4 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_05_SAI1_RX_DATA00 0x110 0x284 0x438 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_05_FLEXIO1_FLEXIO10 0x110 0x284 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x284 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_05_LPSPI1_PCS2 0x110 0x284 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_05_KPP_ROW06 0x110 0x284 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_06_USDHC1_RESET_B 0x114 0x288 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_06_FLEXPWM1_PWMA00 0x114 0x288 0x328 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_06_LPUART2_CTS_B 0x114 0x288 0x3CC 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_06_SAI1_RX_BCLK 0x114 0x288 0x434 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_06_FLEXIO1_FLEXIO09 0x114 0x288 0x000 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x288 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_06_LPSPI1_PCS3 0x114 0x288 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_06_KPP_COL07 0x114 0x288 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_07_USDHC1_VSELECT 0x118 0x28C 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_07_FLEXPWM1_PWMB00 0x118 0x28C 0x338 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_07_LPUART2_RTS_B 0x118 0x28C 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_07_SAI1_TX_DATA01 0x118 0x28C 0x444 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_07_FLEXIO1_FLEXIO08 0x118 0x28C 0x000 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x28C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_07_LPSPI3_PCS3 0x118 0x28C 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_07_KPP_ROW07 0x118 0x28C 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL 0x11C 0x290 0x384 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_08_FLEXPWM1_PWMA01 0x11C 0x290 0x32C 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_08_LPUART2_TX 0x11C 0x290 0x3D4 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_08_SAI1_TX_DATA02 0x11C 0x290 0x440 0x3 0x3 +#define MXRT1020_IOMUXC_GPIO_AD_B1_08_FLEXIO1_FLEXIO07 0x11C 0x290 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x290 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_08_LPSPI3_PCS2 0x11C 0x290 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_08_XBAR1_INOUT12 0x11C 0x290 0x4B4 0x7 0x1 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA 0x120 0x294 0x388 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_09_FLEXPWM1_PWMB01 0x120 0x294 0x33C 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_09_LPUART2_RX 0x120 0x294 0x3D0 0x2 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B1_09_SAI1_TX_DATA03 0x120 0x294 0x43C 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_09_FLEXIO1_FLEXIO26 0x120 0x294 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x294 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_09_LPSPI3_PCS1 0x120 0x294 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_09_XBAR1_INOUT13 0x120 0x294 0x4B8 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR 0x124 0x298 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA02 0x124 0x298 0x330 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_10_LPUART4_TX 0x124 0x298 0x3E8 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_10_USDHC1_CD_B 0x124 0x298 0x490 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05 0x124 0x298 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x298 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1 0x124 0x298 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID 0x128 0x29C 0x2FC 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB02 0x128 0x29C 0x340 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_11_LPUART4_RX 0x128 0x29C 0x3E4 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_11_USDHC1_WP 0x128 0x29C 0x494 0x3 0x3 +#define MXRT1020_IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04 0x128 0x29C 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x29C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1 0x128 0x29C 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC 0x12C 0x2A0 0x48C 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x2A0 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK 0x12C 0x2A0 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_12_USDHC2_CD_B 0x12C 0x2A0 0x498 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03 0x12C 0x2A0 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x2A0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA03 0x12C 0x2A0 0x334 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ 0x130 0x2A4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x2A4 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0 0x130 0x2A4 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_13_USDHC2_WP 0x130 0x2A4 0x49C 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02 0x130 0x2A4 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x2A4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB03 0x130 0x2A4 0x344 0x6 0x1 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL 0x134 0x2A8 0x37C 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x2A8 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x2A8 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_14_ENET_1588_EVENT0_OUT 0x134 0x2A8 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01 0x134 0x2A8 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x2A8 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA 0x138 0x2AC 0x380 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x2AC 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI 0x138 0x2AC 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_15_ENET_1588_EVENT0_IN 0x138 0x2AC 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00 0x138 0x2AC 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x2AC 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2 0x13C 0x2B0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_00_QTIMER1_TIMER0 0x13C 0x2B0 0x410 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_00_SAI1_MCLK 0x13C 0x2B0 0x430 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_00_SAI2_MCLK 0x13C 0x2B0 0x454 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x13C 0x2B0 0x38C 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_00_GPIO3_IO13 0x13C 0x2B0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x13C 0x2B0 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT14 0x13C 0x2B0 0x4A0 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3 0x140 0x2B4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_01_QTIMER1_TIMER1 0x140 0x2B4 0x414 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_01_REF_24M_OUT 0x140 0x2B4 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_01_SAI2_RX_SYNC 0x140 0x2B4 0x460 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x140 0x2B4 0x390 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_01_GPIO3_IO14 0x140 0x2B4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x140 0x2B4 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT15 0x140 0x2B4 0x4A4 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B0_02_USDHC1_CMD 0x144 0x2B8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_02_QTIMER1_TIMER2 0x144 0x2B8 0x418 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_02_LPUART7_CTS_B 0x144 0x2B8 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_02_SAI2_RX_BCLK 0x144 0x2B8 0x458 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_02_LPSPI1_SCK 0x144 0x2B8 0x3A0 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_02_GPIO3_IO15 0x144 0x2B8 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_02_ENET_MDIO 0x144 0x2B8 0x308 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT16 0x144 0x2B8 0x4A8 0x7 0x1 + +#define MXRT1020_IOMUXC_GPIO_SD_B0_03_USDHC1_CLK 0x148 0x2BC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_03_QTIMER1_TIMER3 0x148 0x2BC 0x41C 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_03_LPUART7_RTS_B 0x148 0x2BC 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_03_SAI2_RX_DATA 0x148 0x2BC 0x45C 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_03_LPSPI1_PCS0 0x148 0x2BC 0x39C 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_03_GPIO3_IO16 0x148 0x2BC 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_03_ENET_MDC 0x148 0x2BC 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0 0x14C 0x2C0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_04_FLEXCAN2_TX 0x14C 0x2C0 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_04_LPUART7_TX 0x14C 0x2C0 0x400 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_04_SAI2_TX_DATA 0x14C 0x2C0 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_04_LPSPI1_SDO 0x14C 0x2C0 0x3A8 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_04_GPIO3_IO17 0x14C 0x2C0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x14C 0x2C0 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1 0x150 0x2C4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_05_FLEXCAN2_RX 0x150 0x2C4 0x324 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_05_LPUART7_RX 0x150 0x2C4 0x3FC 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_05_SAI2_TX_BCLK 0x150 0x2C4 0x464 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_05_LPSPI1_SDI 0x150 0x2C4 0x3A4 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_05_GPIO3_IO18 0x150 0x2C4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x150 0x2C4 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B 0x154 0x2C8 0x490 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_RESET_B 0x154 0x2C8 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_06_REF_32K_OUT 0x154 0x2C8 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_06_SAI2_TX_SYNC 0x154 0x2C8 0x468 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_06_WDOG1_B 0x154 0x2C8 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_06_GPIO3_IO19 0x154 0x2C8 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_06_XBAR1_INOUT17 0x154 0x2C8 0x4AC 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA2 0x158 0x2CC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA03 0x158 0x2CC 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_00_LPUART6_TX 0x158 0x2CC 0x3F8 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT10 0x158 0x2CC 0x4B0 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX 0x158 0x2CC 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 0x158 0x2CC 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA3 0x15C 0x2D0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK 0x15C 0x2D0 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_01_LPUART6_RX 0x15C 0x2D0 0x3F4 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B 0x15C 0x2D0 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX 0x15C 0x2D0 0x320 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 0x15C 0x2D0 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_02_USDHC2_CMD 0x160 0x2D4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA00 0x160 0x2D4 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_02_LPUART8_TX 0x160 0x2D4 0x408 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL 0x160 0x2D4 0x394 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_02_ENET_1588_EVENT1_OUT 0x160 0x2D4 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 0x160 0x2D4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_02_CCM_CLKO1 0x160 0x2D4 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_03_USDHC2_CLK 0x164 0x2D8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA02 0x164 0x2D8 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_03_LPUART8_RX 0x164 0x2D8 0x404 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA 0x164 0x2D8 0x398 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_SD_B1_03_ENET_1588_EVENT1_IN 0x164 0x2D8 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 0x164 0x2D8 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_03_CCM_CLKO2 0x164 0x2D8 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_04_USDHC2_DATA0 0x168 0x2DC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA01 0x168 0x2DC 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_04_ENET_TX_CLK 0x168 0x2DC 0x31C 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_04_ENET_REF_CLK1 0x168 0x2DC 0x304 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_04_EWM_OUT_B 0x168 0x2DC 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 0x168 0x2DC 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_04_CCM_WAIT 0x168 0x2DC 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_05_USDHC2_DATA1 0x16C 0x2E0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x16C 0x2E0 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_05_ENET_RDATA01 0x16C 0x2E0 0x310 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_05_SAI3_MCLK 0x16C 0x2E0 0x46C 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B 0x16C 0x2E0 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 0x16C 0x2E0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY 0x16C 0x2E0 0x300 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_06_USDHC2_CD_B 0x170 0x2E4 0x498 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03 0x170 0x2E4 0x374 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_06_ENET_RDATA00 0x170 0x2E4 0x30C 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK 0x170 0x2E4 0x47C 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x170 0x2E4 0x3AC 0x4 0x2 +#define MXRT1020_IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 0x170 0x2E4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_06_CCM_STOP 0x170 0x2E4 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_07_USDHC2_RESET_B 0x174 0x2E8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x174 0x2E8 0x378 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_07_ENET_RX_EN 0x174 0x2E8 0x314 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC 0x174 0x2E8 0x480 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x174 0x2E8 0x3B0 0x4 0x2 +#define MXRT1020_IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 0x174 0x2E8 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x178 0x2EC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00 0x178 0x2EC 0x368 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_08_ENET_RX_ER 0x178 0x2EC 0x318 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA 0x178 0x2EC 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x178 0x2EC 0x3B8 0x4 0x2 +#define MXRT1020_IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 0x178 0x2EC 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x17C 0x2F0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02 0x17C 0x2F0 0x370 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_09_ENET_TX_EN 0x17C 0x2F0 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK 0x17C 0x2F0 0x470 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x17C 0x2F0 0x3B4 0x4 0x2 +#define MXRT1020_IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 0x17C 0x2F0 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x180 0x2F4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01 0x180 0x2F4 0x36C 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_10_ENET_TDATA00 0x180 0x2F4 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC 0x180 0x2F4 0x478 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x180 0x2F4 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 0x180 0x2F4 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x184 0x2F8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B 0x184 0x2F8 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_11_ENET_TDATA01 0x184 0x2F8 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA 0x184 0x2F8 0x474 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x184 0x2F8 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 0x184 0x2F8 0x000 0x5 0x0 + +#endif /* _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H */ diff --git a/roms/u-boot/include/dt-bindings/pinctrl/pins-imxrt1050.h b/roms/u-boot/include/dt-bindings/pinctrl/pins-imxrt1050.h new file mode 100644 index 000000000..a29031ab3 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/pins-imxrt1050.h @@ -0,0 +1,993 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H +#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H + +#define IMX_PAD_SION 0x40000000 + +/* + * The pin function ID is a tuple of + * + */ + +#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x478 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x5C0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x488 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x5B0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x47C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x5B8 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x48C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x5BC 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x480 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x5B4 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x490 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x4E8 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x640 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x4E4 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x5D8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x454 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x654 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x538 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x658 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x5C8 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x580 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x4A0 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x584 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x588 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x544 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x56C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x4E0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x574 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x4DC 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x578 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x458 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x54C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x548 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x45C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x554 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x46C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x550 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x460 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x4F0 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x470 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x4F8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x4F4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x4EC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x55C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x558 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4 +#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x630 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x5D4 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x638 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x5D8 0x6 0x1 + +#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x63C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x608 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x454 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x564 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x464 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x560 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x5E0 0x6 0x1 + +#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x5CC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x644 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x510 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x484 0x0 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x648 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x518 0x7 0x1 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x64C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x554 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x514 0x7 0x1 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x62C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x550 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x5D0 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x50C 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x5C4 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x5C0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x62C 0x6 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x5B4 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x630 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x5BC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x654 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x5B8 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x634 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x658 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x454 0x1 0x3 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x5B0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x638 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x464 0x1 0x3 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x63C 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x1 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x4E4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x568 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x4E8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x5CC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x640 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x650 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x57C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x4CC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x5D8 0x6 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x580 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x4D0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x584 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x530 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x5D4 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x5D0 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x588 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x52C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x5C8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x5E0 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x4C4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x534 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x5E8 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x4C0 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x5EC 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x494 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x5E4 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x4A4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x498 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x58C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x5DC 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x4B4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x564 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x5A4 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x608 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x4B0 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x560 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x590 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x4AC 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x50C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x594 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x5F8 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x4A8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x514 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x5FC 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x4C8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x518 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x5A8 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x600 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x510 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x5AC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x604 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x51C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x524 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x528 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x56C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3 +#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x520 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x570 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x4D4 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x574 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x4D8 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x57C 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x478 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x580 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x488 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x584 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x47C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x53C 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x48C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x538 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x480 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x598 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x5A0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x58C 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x5A4 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x644 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x544 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x594 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x454 0x6 0x4 + +#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x648 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x540 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x464 0x6 0x4 + +#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x64C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x5A8 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x62C 0x1 0x3 +#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x5AC 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x484 0x6 0x3 + +#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x51C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x524 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x528 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x520 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x578 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3 + +#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x588 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1 + +#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x54C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x5D4 0x6 0x2 + +#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x548 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x5D8 0x6 0x3 + +#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x49C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x60C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x4A0 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x610 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x458 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x4DC 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x614 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x4F0 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x4E0 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x618 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x4EC 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x45C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x61C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x4F8 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x46C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x620 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x4F4 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x460 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x564 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x624 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x470 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x560 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x628 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x5F4 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x4C4 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x454 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x598 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x544 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x5F0 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x4C0 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x464 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x59C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x540 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x5EC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x4BC 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x5A0 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x5E8 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x4B8 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x484 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x58C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x5DC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x4CC 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x5A4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x5E4 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x4A4 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x4D0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x590 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x594 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x4FC 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x4C8 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x500 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x5F8 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x4A8 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x55C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x5A8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x508 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x5FC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x4AC 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x558 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x5AC 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x504 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x600 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x4B0 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x52C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x4D8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x604 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x4B4 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x530 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x4D4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0 + +#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */ diff --git a/roms/u-boot/include/dt-bindings/pinctrl/r7s72100-pinctrl.h b/roms/u-boot/include/dt-bindings/pinctrl/r7s72100-pinctrl.h new file mode 100644 index 000000000..31ee37610 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/r7s72100-pinctrl.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Defines macros and constants for Renesas RZ/A1 pin controller pin + * muxing functions. + */ +#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H +#define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H + +#define RZA1_PINS_PER_PORT 16 + +/* + * Create the pin index from its bank and position numbers and store in + * the upper 16 bits the alternate function identifier + */ +#define RZA1_PINMUX(b, p, f) \ + ((b) * RZA1_PINS_PER_PORT + (p) | ((f) << 16)) + +#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */ diff --git a/roms/u-boot/include/dt-bindings/pinctrl/rockchip.h b/roms/u-boot/include/dt-bindings/pinctrl/rockchip.h new file mode 100644 index 000000000..1c28d6cb1 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/rockchip.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Header providing constants for Rockchip pinctrl bindings. + * + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner + */ + +#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ +#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ + +#define RK_GPIO0 0 +#define RK_GPIO1 1 +#define RK_GPIO2 2 +#define RK_GPIO3 3 +#define RK_GPIO4 4 +#define RK_GPIO6 6 + +#define RK_PA0 0 +#define RK_PA1 1 +#define RK_PA2 2 +#define RK_PA3 3 +#define RK_PA4 4 +#define RK_PA5 5 +#define RK_PA6 6 +#define RK_PA7 7 +#define RK_PB0 8 +#define RK_PB1 9 +#define RK_PB2 10 +#define RK_PB3 11 +#define RK_PB4 12 +#define RK_PB5 13 +#define RK_PB6 14 +#define RK_PB7 15 +#define RK_PC0 16 +#define RK_PC1 17 +#define RK_PC2 18 +#define RK_PC3 19 +#define RK_PC4 20 +#define RK_PC5 21 +#define RK_PC6 22 +#define RK_PC7 23 +#define RK_PD0 24 +#define RK_PD1 25 +#define RK_PD2 26 +#define RK_PD3 27 +#define RK_PD4 28 +#define RK_PD5 29 +#define RK_PD6 30 +#define RK_PD7 31 + +#define RK_FUNC_GPIO 0 +#define RK_FUNC_1 1 +#define RK_FUNC_2 2 +#define RK_FUNC_3 3 +#define RK_FUNC_4 4 +#define RK_FUNC_5 5 +#define RK_FUNC_6 6 + +#endif diff --git a/roms/u-boot/include/dt-bindings/pinctrl/sandbox-pinmux.h b/roms/u-boot/include/dt-bindings/pinctrl/sandbox-pinmux.h new file mode 100644 index 000000000..891af072e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/sandbox-pinmux.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Sean Anderson + */ + +#ifndef SANDBOX_PINMUX_H +#define SANDBOX_PINMUX_H + +#define SANDBOX_PINMUX_UART 0 +#define SANDBOX_PINMUX_I2C 1 +#define SANDBOX_PINMUX_SPI 2 +#define SANDBOX_PINMUX_I2S 3 +#define SANDBOX_PINMUX_GPIO 4 +#define SANDBOX_PINMUX_CS 5 +#define SANDBOX_PINMUX_PWM 6 + +#define SANDBOX_PINMUX(pin, func) ((func) << 16 | (pin)) + +#endif /* SANDBOX_PINMUX_H */ diff --git a/roms/u-boot/include/dt-bindings/pinctrl/stm32-pinfunc.h b/roms/u-boot/include/dt-bindings/pinctrl/stm32-pinfunc.h new file mode 100644 index 000000000..e6fb8ada3 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Torgue Alexandre for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32_PINFUNC_H +#define _DT_BINDINGS_STM32_PINFUNC_H + +/* define PIN modes */ +#define GPIO 0x0 +#define AF0 0x1 +#define AF1 0x2 +#define AF2 0x3 +#define AF3 0x4 +#define AF4 0x5 +#define AF5 0x6 +#define AF6 0x7 +#define AF7 0x8 +#define AF8 0x9 +#define AF9 0xa +#define AF10 0xb +#define AF11 0xc +#define AF12 0xd +#define AF13 0xe +#define AF14 0xf +#define AF15 0x10 +#define ANALOG 0x11 + +/* define Pins number*/ +#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line)) + +#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode)) + +/* package information */ +#define STM32MP_PKG_AA 0x1 +#define STM32MP_PKG_AB 0x2 +#define STM32MP_PKG_AC 0x4 +#define STM32MP_PKG_AD 0x8 + +#endif /* _DT_BINDINGS_STM32_PINFUNC_H */ + diff --git a/roms/u-boot/include/dt-bindings/pinctrl/sun4i-a10.h b/roms/u-boot/include/dt-bindings/pinctrl/sun4i-a10.h new file mode 100644 index 000000000..f7553c143 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pinctrl/sun4i-a10.h @@ -0,0 +1,62 @@ +/* + * Copyright 2014 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ +#define __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ + +#define SUN4I_PINCTRL_10_MA 0 +#define SUN4I_PINCTRL_20_MA 1 +#define SUN4I_PINCTRL_30_MA 2 +#define SUN4I_PINCTRL_40_MA 3 + +#define SUN4I_PINCTRL_NO_PULL 0 +#define SUN4I_PINCTRL_PULL_UP 1 +#define SUN4I_PINCTRL_PULL_DOWN 2 + +#endif /* __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ */ diff --git a/roms/u-boot/include/dt-bindings/pmic/sandbox_pmic.h b/roms/u-boot/include/dt-bindings/pmic/sandbox_pmic.h new file mode 100644 index 000000000..749c0d1f6 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pmic/sandbox_pmic.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak + */ + +#ifndef _DT_BINDINGS_SANDBOX_PMIC_H_ +#define _DT_BINDINGS_SANDBOX_PMIC_H_ + +/* + * Sandbox PMIC - prepare reset values + * To provide the default (reset) values as in the real hardware, + * the registers are set in i2c pmic emul driver's probe() method. + * The default values are defined as below. + */ + +/* Buck operation mode IDs */ +#define BUCK_OM_OFF 0 +#define BUCK_OM_ON 1 +#define BUCK_OM_PWM 2 +#define BUCK_OM_COUNT 3 + +/* Ldo operation mode IDs */ +#define LDO_OM_OFF 0 +#define LDO_OM_ON 1 +#define LDO_OM_SLEEP 2 +#define LDO_OM_STANDBY 3 +#define LDO_OM_COUNT 4 + +/* [Value uV/uA]/[Mode ID] to register */ +#define VAL2REG(min, step, val) (((val) - (min)) / (step)) +#define VAL2OMREG(x) (x) + +#endif diff --git a/roms/u-boot/include/dt-bindings/power-domain/bcm6318-power-domain.h b/roms/u-boot/include/dt-bindings/power-domain/bcm6318-power-domain.h new file mode 100644 index 000000000..b213cae9a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power-domain/bcm6318-power-domain.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + */ + +#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6318_H +#define __DT_BINDINGS_POWER_DOMAIN_BCM6318_H + +#define BCM6318_PWR_PCIE 0 +#define BCM6318_PWR_USB 1 + +#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6318_H */ diff --git a/roms/u-boot/include/dt-bindings/power-domain/bcm63268-power-domain.h b/roms/u-boot/include/dt-bindings/power-domain/bcm63268-power-domain.h new file mode 100644 index 000000000..7208506d5 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power-domain/bcm63268-power-domain.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM63268_H +#define __DT_BINDINGS_POWER_DOMAIN_BCM63268_H + +#define BCM63268_PWR_SAR 0 +#define BCM63268_PWR_IPSEC 1 +#define BCM63268_PWR_MIPS 2 +#define BCM63268_PWR_DECT 3 +#define BCM63268_PWR_USBH 4 +#define BCM63268_PWR_USBD 5 +#define BCM63268_PWR_ROBOSW 6 +#define BCM63268_PWR_PCM 7 +#define BCM63268_PWR_PERIPH 8 +#define BCM63268_PWR_VDSL_PHY 9 +#define BCM63268_PWR_VDSL_MIPS 10 +#define BCM63268_PWR_FAP 11 +#define BCM63268_PWR_PCIE 12 +#define BCM63268_PWR_WLAN_PADS 13 + +#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM63268_H */ diff --git a/roms/u-boot/include/dt-bindings/power-domain/bcm6328-power-domain.h b/roms/u-boot/include/dt-bindings/power-domain/bcm6328-power-domain.h new file mode 100644 index 000000000..6b4b19988 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power-domain/bcm6328-power-domain.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + */ + +#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6328_H +#define __DT_BINDINGS_POWER_DOMAIN_BCM6328_H + +#define BCM6328_PWR_ADSL2_MIPS 0 +#define BCM6328_PWR_ADSL2_PHY 1 +#define BCM6328_PWR_ADSL2_AFE 2 +#define BCM6328_PWR_SAR 3 +#define BCM6328_PWR_PCM 4 +#define BCM6328_PWR_USBD 5 +#define BCM6328_PWR_USBH 6 +#define BCM6328_PWR_PCIE 7 +#define BCM6328_PWR_ROBOSW 8 +#define BCM6328_PWR_EPHY 9 + +#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6328_H */ diff --git a/roms/u-boot/include/dt-bindings/power-domain/bcm6362-power-domain.h b/roms/u-boot/include/dt-bindings/power-domain/bcm6362-power-domain.h new file mode 100644 index 000000000..1a708a9ad --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power-domain/bcm6362-power-domain.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + */ + +#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6362_H +#define __DT_BINDINGS_POWER_DOMAIN_BCM6362_H + +#define BCM6362_PWR_SAR 0 +#define BCM6362_PWR_IPSEC 1 +#define BCM6362_PWR_MIPS 2 +#define BCM6362_PWR_DECT 3 +#define BCM6362_PWR_USBH 4 +#define BCM6362_PWR_USBD 5 +#define BCM6362_PWR_ROBOSW 6 +#define BCM6362_PWR_PCM 7 +#define BCM6362_PWR_PERIPH 8 +#define BCM6362_PWR_ADSL_PHY 9 +#define BCM6362_PWR_GMII_PADS 10 +#define BCM6362_PWR_FAP 11 +#define BCM6362_PWR_PCIE 12 +#define BCM6362_PWR_WLAN_PADS 13 + +#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6362_H */ diff --git a/roms/u-boot/include/dt-bindings/power-domain/rk3288.h b/roms/u-boot/include/dt-bindings/power-domain/rk3288.h new file mode 100644 index 000000000..ca68c1147 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power-domain/rk3288.h @@ -0,0 +1,11 @@ +#ifndef __DT_BINDINGS_POWER_DOMAIN_RK3288_H__ +#define __DT_BINDINGS_POWER_DOMAIN_RK3288_H__ + +/* RK3288 power domain index */ +#define RK3288_PD_GPU 0 +#define RK3288_PD_VIO 1 +#define RK3288_PD_VIDEO 2 +#define RK3288_PD_HEVC 3 +#define RK3288_PD_PERI 4 + +#endif diff --git a/roms/u-boot/include/dt-bindings/power/imx7-power.h b/roms/u-boot/include/dt-bindings/power/imx7-power.h new file mode 100644 index 000000000..3a181e410 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/imx7-power.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2017 Impinj + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_IMX7_POWER_H__ +#define __DT_BINDINGS_IMX7_POWER_H__ + +#define IMX7_POWER_DOMAIN_MIPI_PHY 0 +#define IMX7_POWER_DOMAIN_PCIE_PHY 1 +#define IMX7_POWER_DOMAIN_USB_HSIC_PHY 2 + +#endif diff --git a/roms/u-boot/include/dt-bindings/power/imx8mm-power.h b/roms/u-boot/include/dt-bindings/power/imx8mm-power.h new file mode 100644 index 000000000..fc9c2e16a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/imx8mm-power.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Pengutronix, Lucas Stach + */ + +#ifndef __DT_BINDINGS_IMX8MM_POWER_H__ +#define __DT_BINDINGS_IMX8MM_POWER_H__ + +#define IMX8MM_POWER_DOMAIN_HSIOMIX 0 +#define IMX8MM_POWER_DOMAIN_PCIE 1 +#define IMX8MM_POWER_DOMAIN_OTG1 2 +#define IMX8MM_POWER_DOMAIN_OTG2 3 +#define IMX8MM_POWER_DOMAIN_GPUMIX 4 +#define IMX8MM_POWER_DOMAIN_GPU 5 +#define IMX8MM_POWER_DOMAIN_VPUMIX 6 +#define IMX8MM_POWER_DOMAIN_VPUG1 7 +#define IMX8MM_POWER_DOMAIN_VPUG2 8 +#define IMX8MM_POWER_DOMAIN_VPUH1 9 +#define IMX8MM_POWER_DOMAIN_DISPMIX 10 +#define IMX8MM_POWER_DOMAIN_MIPI 11 + +#endif diff --git a/roms/u-boot/include/dt-bindings/power/imx8mn-power.h b/roms/u-boot/include/dt-bindings/power/imx8mn-power.h new file mode 100644 index 000000000..102ee85a9 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/imx8mn-power.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Compass Electronics Group, LLC + */ + +#ifndef __DT_BINDINGS_IMX8MN_POWER_H__ +#define __DT_BINDINGS_IMX8MN_POWER_H__ + +#define IMX8MN_POWER_DOMAIN_HSIOMIX 0 +#define IMX8MN_POWER_DOMAIN_OTG1 1 +#define IMX8MN_POWER_DOMAIN_GPUMIX 2 +#define IMX8MN_POWER_DOMAIN_DISPMIX 3 +#define IMX8MN_POWER_DOMAIN_MIPI 4 + +#endif diff --git a/roms/u-boot/include/dt-bindings/power/imx8mq-power.h b/roms/u-boot/include/dt-bindings/power/imx8mq-power.h new file mode 100755 index 000000000..8a513bd91 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/imx8mq-power.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2018 Pengutronix, Lucas Stach + */ + +#ifndef __DT_BINDINGS_IMX8MQ_POWER_H__ +#define __DT_BINDINGS_IMX8MQ_POWER_H__ + +#define IMX8M_POWER_DOMAIN_MIPI 0 +#define IMX8M_POWER_DOMAIN_PCIE1 1 +#define IMX8M_POWER_DOMAIN_USB_OTG1 2 +#define IMX8M_POWER_DOMAIN_USB_OTG2 3 +#define IMX8M_POWER_DOMAIN_DDR1 4 +#define IMX8M_POWER_DOMAIN_GPU 5 +#define IMX8M_POWER_DOMAIN_VPU 6 +#define IMX8M_POWER_DOMAIN_DISP 7 +#define IMX8M_POWER_DOMAIN_MIPI_CSI1 8 +#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9 +#define IMX8M_POWER_DOMAIN_PCIE2 10 + +#endif diff --git a/roms/u-boot/include/dt-bindings/power/meson-axg-power.h b/roms/u-boot/include/dt-bindings/power/meson-axg-power.h new file mode 100644 index 000000000..e5243884b --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/meson-axg-power.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2020 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef _DT_BINDINGS_MESON_AXG_POWER_H +#define _DT_BINDINGS_MESON_AXG_POWER_H + +#define PWRC_AXG_VPU_ID 0 +#define PWRC_AXG_ETHERNET_MEM_ID 1 +#define PWRC_AXG_AUDIO_ID 2 + +#endif diff --git a/roms/u-boot/include/dt-bindings/power/meson-g12a-power.h b/roms/u-boot/include/dt-bindings/power/meson-g12a-power.h new file mode 100644 index 000000000..bb5e67a84 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/meson-g12a-power.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef _DT_BINDINGS_MESON_G12A_POWER_H +#define _DT_BINDINGS_MESON_G12A_POWER_H + +#define PWRC_G12A_VPU_ID 0 +#define PWRC_G12A_ETH_ID 1 + +#endif diff --git a/roms/u-boot/include/dt-bindings/power/meson-gxbb-power.h b/roms/u-boot/include/dt-bindings/power/meson-gxbb-power.h new file mode 100644 index 000000000..1262dac69 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/meson-gxbb-power.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef _DT_BINDINGS_MESON_GXBB_POWER_H +#define _DT_BINDINGS_MESON_GXBB_POWER_H + +#define PWRC_GXBB_VPU_ID 0 +#define PWRC_GXBB_ETHERNET_MEM_ID 1 + +#endif diff --git a/roms/u-boot/include/dt-bindings/power/meson-sm1-power.h b/roms/u-boot/include/dt-bindings/power/meson-sm1-power.h new file mode 100644 index 000000000..a020ab00c --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/meson-sm1-power.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef _DT_BINDINGS_MESON_SM1_POWER_H +#define _DT_BINDINGS_MESON_SM1_POWER_H + +#define PWRC_SM1_VPU_ID 0 +#define PWRC_SM1_NNA_ID 1 +#define PWRC_SM1_USB_ID 2 +#define PWRC_SM1_PCIE_ID 3 +#define PWRC_SM1_GE2D_ID 4 +#define PWRC_SM1_AUDIO_ID 5 +#define PWRC_SM1_ETH_ID 6 + +#endif diff --git a/roms/u-boot/include/dt-bindings/power/mt7623-power.h b/roms/u-boot/include/dt-bindings/power/mt7623-power.h new file mode 100644 index 000000000..0e73bb43a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/mt7623-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_MT7623_POWER_H +#define _DT_BINDINGS_MT7623_POWER_H + +#define MT7623_POWER_DOMAIN_CONN 0 +#define MT7623_POWER_DOMAIN_DISP 1 +#define MT7623_POWER_DOMAIN_MFG 2 +#define MT7623_POWER_DOMAIN_VDEC 3 +#define MT7623_POWER_DOMAIN_ISP 4 +#define MT7623_POWER_DOMAIN_BDP 5 +#define MT7623_POWER_DOMAIN_ETH 6 +#define MT7623_POWER_DOMAIN_HIF 7 +#define MT7623_POWER_DOMAIN_IFR_MSC 8 + +#endif /* _DT_BINDINGS_MT7623_POWER_H */ diff --git a/roms/u-boot/include/dt-bindings/power/mt7629-power.h b/roms/u-boot/include/dt-bindings/power/mt7629-power.h new file mode 100644 index 000000000..c7e613050 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/mt7629-power.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_MT7629_POWER_H +#define _DT_BINDINGS_MT7629_POWER_H + +#define MT7629_POWER_DOMAIN_ETHSYS 0 +#define MT7629_POWER_DOMAIN_HIF0 1 +#define MT7629_POWER_DOMAIN_HIF1 2 + +#endif /* _DT_BINDINGS_MT7629_POWER_H */ diff --git a/roms/u-boot/include/dt-bindings/power/px30-power.h b/roms/u-boot/include/dt-bindings/power/px30-power.h new file mode 100644 index 000000000..30917a99a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/px30-power.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__ +#define __DT_BINDINGS_POWER_PX30_POWER_H__ + +/* VD_CORE */ +#define PX30_PD_A35_0 0 +#define PX30_PD_A35_1 1 +#define PX30_PD_A35_2 2 +#define PX30_PD_A35_3 3 +#define PX30_PD_SCU 4 + +/* VD_LOGIC */ +#define PX30_PD_USB 5 +#define PX30_PD_DDR 6 +#define PX30_PD_SDCARD 7 +#define PX30_PD_CRYPTO 8 +#define PX30_PD_GMAC 9 +#define PX30_PD_MMC_NAND 10 +#define PX30_PD_VPU 11 +#define PX30_PD_VO 12 +#define PX30_PD_VI 13 +#define PX30_PD_GPU 14 + +/* VD_PMU */ +#define PX30_PD_PMU 15 + +#endif diff --git a/roms/u-boot/include/dt-bindings/power/r8a774a1-sysc.h b/roms/u-boot/include/dt-bindings/power/r8a774a1-sysc.h new file mode 100644 index 000000000..d35183557 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/r8a774a1-sysc.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774A1_PD_CA57_CPU0 0 +#define R8A774A1_PD_CA57_CPU1 1 +#define R8A774A1_PD_CA53_CPU0 5 +#define R8A774A1_PD_CA53_CPU1 6 +#define R8A774A1_PD_CA53_CPU2 7 +#define R8A774A1_PD_CA53_CPU3 8 +#define R8A774A1_PD_CA57_SCU 12 +#define R8A774A1_PD_A3VC 14 +#define R8A774A1_PD_3DG_A 17 +#define R8A774A1_PD_3DG_B 18 +#define R8A774A1_PD_CA53_SCU 21 +#define R8A774A1_PD_A2VC0 25 +#define R8A774A1_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774A1_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/power/r8a774b1-sysc.h b/roms/u-boot/include/dt-bindings/power/r8a774b1-sysc.h new file mode 100644 index 000000000..96afda044 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/r8a774b1-sysc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774B1_PD_CA57_CPU0 0 +#define R8A774B1_PD_CA57_CPU1 1 +#define R8A774B1_PD_A3VP 9 +#define R8A774B1_PD_CA57_SCU 12 +#define R8A774B1_PD_A3VC 14 +#define R8A774B1_PD_3DG_A 17 +#define R8A774B1_PD_3DG_B 18 +#define R8A774B1_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774B1_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/power/r8a774c0-sysc.h b/roms/u-boot/include/dt-bindings/power/r8a774c0-sysc.h new file mode 100644 index 000000000..dd0cd656d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/r8a774c0-sysc.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774C0_PD_CA53_CPU0 5 +#define R8A774C0_PD_CA53_CPU1 6 +#define R8A774C0_PD_A3VC 14 +#define R8A774C0_PD_3DG_A 17 +#define R8A774C0_PD_3DG_B 18 +#define R8A774C0_PD_CA53_SCU 21 +#define R8A774C0_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774C0_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/power/r8a774e1-sysc.h b/roms/u-boot/include/dt-bindings/power/r8a774e1-sysc.h new file mode 100644 index 000000000..7edb8161d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/r8a774e1-sysc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774E1_PD_CA57_CPU0 0 +#define R8A774E1_PD_CA57_CPU1 1 +#define R8A774E1_PD_CA57_CPU2 2 +#define R8A774E1_PD_CA57_CPU3 3 +#define R8A774E1_PD_CA53_CPU0 5 +#define R8A774E1_PD_CA53_CPU1 6 +#define R8A774E1_PD_CA53_CPU2 7 +#define R8A774E1_PD_CA53_CPU3 8 +#define R8A774E1_PD_A3VP 9 +#define R8A774E1_PD_CA57_SCU 12 +#define R8A774E1_PD_A3VC 14 +#define R8A774E1_PD_3DG_A 17 +#define R8A774E1_PD_3DG_B 18 +#define R8A774E1_PD_3DG_C 19 +#define R8A774E1_PD_3DG_D 20 +#define R8A774E1_PD_CA53_SCU 21 +#define R8A774E1_PD_3DG_E 22 +#define R8A774E1_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774E1_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/power/r8a7790-sysc.h b/roms/u-boot/include/dt-bindings/power/r8a7790-sysc.h new file mode 100644 index 000000000..bcb490570 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/r8a7790-sysc.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2016 Glider bvba + */ +#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7790_PD_CA15_CPU0 0 +#define R8A7790_PD_CA15_CPU1 1 +#define R8A7790_PD_CA15_CPU2 2 +#define R8A7790_PD_CA15_CPU3 3 +#define R8A7790_PD_CA7_CPU0 5 +#define R8A7790_PD_CA7_CPU1 6 +#define R8A7790_PD_CA7_CPU2 7 +#define R8A7790_PD_CA7_CPU3 8 +#define R8A7790_PD_CA15_SCU 12 +#define R8A7790_PD_SH_4A 16 +#define R8A7790_PD_RGX 20 +#define R8A7790_PD_CA7_SCU 21 +#define R8A7790_PD_IMP 24 + +/* Always-on power area */ +#define R8A7790_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/power/r8a7791-sysc.h b/roms/u-boot/include/dt-bindings/power/r8a7791-sysc.h new file mode 100644 index 000000000..1d20fae42 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/r8a7791-sysc.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2016 Glider bvba + */ +#ifndef __DT_BINDINGS_POWER_R8A7791_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7791_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7791_PD_CA15_CPU0 0 +#define R8A7791_PD_CA15_CPU1 1 +#define R8A7791_PD_CA15_SCU 12 +#define R8A7791_PD_SH_4A 16 +#define R8A7791_PD_SGX 20 + +/* Always-on power area */ +#define R8A7791_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7791_SYSC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/power/r8a7792-sysc.h b/roms/u-boot/include/dt-bindings/power/r8a7792-sysc.h new file mode 100644 index 000000000..dd3a4667c --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/r8a7792-sysc.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2016 Cogent Embedded Inc. + */ +#ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7792_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7792_PD_CA15_CPU0 0 +#define R8A7792_PD_CA15_CPU1 1 +#define R8A7792_PD_CA15_SCU 12 +#define R8A7792_PD_SGX 20 +#define R8A7792_PD_IMP 24 + +/* Always-on power area */ +#define R8A7792_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7792_SYSC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/power/r8a7793-sysc.h b/roms/u-boot/include/dt-bindings/power/r8a7793-sysc.h new file mode 100644 index 000000000..056998c63 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/r8a7793-sysc.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2016 Glider bvba + */ +#ifndef __DT_BINDINGS_POWER_R8A7793_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7793_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + * + * Note that R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. + */ + +#define R8A7793_PD_CA15_CPU0 0 +#define R8A7793_PD_CA15_CPU1 1 +#define R8A7793_PD_CA15_SCU 12 +#define R8A7793_PD_SH_4A 16 +#define R8A7793_PD_SGX 20 + +/* Always-on power area */ +#define R8A7793_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7793_SYSC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/power/r8a7794-sysc.h b/roms/u-boot/include/dt-bindings/power/r8a7794-sysc.h new file mode 100644 index 000000000..862241c2d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/r8a7794-sysc.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2016 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7794_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7794_PD_CA7_CPU0 5 +#define R8A7794_PD_CA7_CPU1 6 +#define R8A7794_PD_SH_4A 16 +#define R8A7794_PD_SGX 20 +#define R8A7794_PD_CA7_SCU 21 + +/* Always-on power area */ +#define R8A7794_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7794_SYSC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/power/r8a7795-sysc.h b/roms/u-boot/include/dt-bindings/power/r8a7795-sysc.h new file mode 100644 index 000000000..ad679eeda --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/r8a7795-sysc.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2016 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7795_PD_CA57_CPU0 0 +#define R8A7795_PD_CA57_CPU1 1 +#define R8A7795_PD_CA57_CPU2 2 +#define R8A7795_PD_CA57_CPU3 3 +#define R8A7795_PD_CA53_CPU0 5 +#define R8A7795_PD_CA53_CPU1 6 +#define R8A7795_PD_CA53_CPU2 7 +#define R8A7795_PD_CA53_CPU3 8 +#define R8A7795_PD_A3VP 9 +#define R8A7795_PD_CA57_SCU 12 +#define R8A7795_PD_CR7 13 +#define R8A7795_PD_A3VC 14 +#define R8A7795_PD_3DG_A 17 +#define R8A7795_PD_3DG_B 18 +#define R8A7795_PD_3DG_C 19 +#define R8A7795_PD_3DG_D 20 +#define R8A7795_PD_CA53_SCU 21 +#define R8A7795_PD_3DG_E 22 +#define R8A7795_PD_A3IR 24 +#define R8A7795_PD_A2VC0 25 /* ES1.x only */ +#define R8A7795_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A7795_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/power/r8a7796-sysc.h b/roms/u-boot/include/dt-bindings/power/r8a7796-sysc.h new file mode 100644 index 000000000..5b4daab44 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/r8a7796-sysc.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2016 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7796_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7796_PD_CA57_CPU0 0 +#define R8A7796_PD_CA57_CPU1 1 +#define R8A7796_PD_CA53_CPU0 5 +#define R8A7796_PD_CA53_CPU1 6 +#define R8A7796_PD_CA53_CPU2 7 +#define R8A7796_PD_CA53_CPU3 8 +#define R8A7796_PD_CA57_SCU 12 +#define R8A7796_PD_CR7 13 +#define R8A7796_PD_A3VC 14 +#define R8A7796_PD_3DG_A 17 +#define R8A7796_PD_3DG_B 18 +#define R8A7796_PD_CA53_SCU 21 +#define R8A7796_PD_A3IR 24 +#define R8A7796_PD_A2VC0 25 +#define R8A7796_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A7796_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7796_SYSC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/power/r8a77965-sysc.h b/roms/u-boot/include/dt-bindings/power/r8a77965-sysc.h new file mode 100644 index 000000000..de82d8a15 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/r8a77965-sysc.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Jacopo Mondi + * Copyright (C) 2016 Glider bvba + */ + +#ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77965_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77965_PD_CA57_CPU0 0 +#define R8A77965_PD_CA57_CPU1 1 +#define R8A77965_PD_A3VP 9 +#define R8A77965_PD_CA57_SCU 12 +#define R8A77965_PD_CR7 13 +#define R8A77965_PD_A3VC 14 +#define R8A77965_PD_3DG_A 17 +#define R8A77965_PD_3DG_B 18 +#define R8A77965_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A77965_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/power/r8a77970-sysc.h b/roms/u-boot/include/dt-bindings/power/r8a77970-sysc.h new file mode 100644 index 000000000..85cc5f23c --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/r8a77970-sysc.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2017 Cogent Embedded Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77970_PD_CA53_CPU0 5 +#define R8A77970_PD_CA53_CPU1 6 +#define R8A77970_PD_CA53_SCU 21 +#define R8A77970_PD_A2IR0 23 +#define R8A77970_PD_A3IR 24 +#define R8A77970_PD_A2IR1 27 +#define R8A77970_PD_A2DP 28 +#define R8A77970_PD_A2CN 29 +#define R8A77970_PD_A2SC0 30 +#define R8A77970_PD_A2SC1 31 + +/* Always-on power area */ +#define R8A77970_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/power/r8a77980-sysc.h b/roms/u-boot/include/dt-bindings/power/r8a77980-sysc.h new file mode 100644 index 000000000..e12c8587b --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/r8a77980-sysc.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ +#ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77980_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77980_PD_A2SC2 0 +#define R8A77980_PD_A2SC3 1 +#define R8A77980_PD_A2SC4 2 +#define R8A77980_PD_A2DP0 3 +#define R8A77980_PD_A2DP1 4 +#define R8A77980_PD_CA53_CPU0 5 +#define R8A77980_PD_CA53_CPU1 6 +#define R8A77980_PD_CA53_CPU2 7 +#define R8A77980_PD_CA53_CPU3 8 +#define R8A77980_PD_A2CN 10 +#define R8A77980_PD_A3VIP0 11 +#define R8A77980_PD_A2IR5 12 +#define R8A77980_PD_CR7 13 +#define R8A77980_PD_A2IR4 15 +#define R8A77980_PD_CA53_SCU 21 +#define R8A77980_PD_A2IR0 23 +#define R8A77980_PD_A3IR 24 +#define R8A77980_PD_A3VIP1 25 +#define R8A77980_PD_A3VIP2 26 +#define R8A77980_PD_A2IR1 27 +#define R8A77980_PD_A2IR2 28 +#define R8A77980_PD_A2IR3 29 +#define R8A77980_PD_A2SC0 30 +#define R8A77980_PD_A2SC1 31 + +/* Always-on power area */ +#define R8A77980_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/power/r8a77990-sysc.h b/roms/u-boot/include/dt-bindings/power/r8a77990-sysc.h new file mode 100644 index 000000000..944d85bee --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/r8a77990-sysc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77990_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77990_PD_CA53_CPU0 5 +#define R8A77990_PD_CA53_CPU1 6 +#define R8A77990_PD_CR7 13 +#define R8A77990_PD_A3VC 14 +#define R8A77990_PD_3DG_A 17 +#define R8A77990_PD_3DG_B 18 +#define R8A77990_PD_CA53_SCU 21 +#define R8A77990_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A77990_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/power/r8a77995-sysc.h b/roms/u-boot/include/dt-bindings/power/r8a77995-sysc.h new file mode 100644 index 000000000..09d0ed575 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/r8a77995-sysc.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2017 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77995_PD_CA53_CPU0 5 +#define R8A77995_PD_CA53_SCU 21 + +/* Always-on power area */ +#define R8A77995_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */ diff --git a/roms/u-boot/include/dt-bindings/power/raspberrypi-power.h b/roms/u-boot/include/dt-bindings/power/raspberrypi-power.h new file mode 100644 index 000000000..b3ff8e09a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/raspberrypi-power.h @@ -0,0 +1,41 @@ +/* + * Copyright © 2015 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H +#define _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H + +/* These power domain indices are the firmware interface's indices + * minus one. + */ +#define RPI_POWER_DOMAIN_I2C0 0 +#define RPI_POWER_DOMAIN_I2C1 1 +#define RPI_POWER_DOMAIN_I2C2 2 +#define RPI_POWER_DOMAIN_VIDEO_SCALER 3 +#define RPI_POWER_DOMAIN_VPU1 4 +#define RPI_POWER_DOMAIN_HDMI 5 +#define RPI_POWER_DOMAIN_USB 6 +#define RPI_POWER_DOMAIN_VEC 7 +#define RPI_POWER_DOMAIN_JPEG 8 +#define RPI_POWER_DOMAIN_H264 9 +#define RPI_POWER_DOMAIN_V3D 10 +#define RPI_POWER_DOMAIN_ISP 11 +#define RPI_POWER_DOMAIN_UNICAM0 12 +#define RPI_POWER_DOMAIN_UNICAM1 13 +#define RPI_POWER_DOMAIN_CCP2RX 14 +#define RPI_POWER_DOMAIN_CSI2 15 +#define RPI_POWER_DOMAIN_CPI 16 +#define RPI_POWER_DOMAIN_DSI0 17 +#define RPI_POWER_DOMAIN_DSI1 18 +#define RPI_POWER_DOMAIN_TRANSPOSER 19 +#define RPI_POWER_DOMAIN_CCP2TX 20 +#define RPI_POWER_DOMAIN_CDP 21 +#define RPI_POWER_DOMAIN_ARM 22 + +#define RPI_POWER_DOMAIN_COUNT 23 + +#endif /* _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H */ diff --git a/roms/u-boot/include/dt-bindings/power/rk3328-power.h b/roms/u-boot/include/dt-bindings/power/rk3328-power.h new file mode 100644 index 000000000..02e3d7fc1 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/rk3328-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__ +#define __DT_BINDINGS_POWER_RK3328_POWER_H__ + +/** + * RK3328 idle id Summary. + */ +#define RK3328_PD_CORE 0 +#define RK3328_PD_GPU 1 +#define RK3328_PD_BUS 2 +#define RK3328_PD_MSCH 3 +#define RK3328_PD_PERI 4 +#define RK3328_PD_VIDEO 5 +#define RK3328_PD_HEVC 6 +#define RK3328_PD_SYS 7 +#define RK3328_PD_VPU 8 +#define RK3328_PD_VIO 9 + +#endif diff --git a/roms/u-boot/include/dt-bindings/power/rk3399-power.h b/roms/u-boot/include/dt-bindings/power/rk3399-power.h new file mode 100644 index 000000000..168b3bfbd --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/rk3399-power.h @@ -0,0 +1,53 @@ +#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__ +#define __DT_BINDINGS_POWER_RK3399_POWER_H__ + +/* VD_CORE_L */ +#define RK3399_PD_A53_L0 0 +#define RK3399_PD_A53_L1 1 +#define RK3399_PD_A53_L2 2 +#define RK3399_PD_A53_L3 3 +#define RK3399_PD_SCU_L 4 + +/* VD_CORE_B */ +#define RK3399_PD_A72_B0 5 +#define RK3399_PD_A72_B1 6 +#define RK3399_PD_SCU_B 7 + +/* VD_LOGIC */ +#define RK3399_PD_TCPD0 8 +#define RK3399_PD_TCPD1 9 +#define RK3399_PD_CCI 10 +#define RK3399_PD_CCI0 11 +#define RK3399_PD_CCI1 12 +#define RK3399_PD_PERILP 13 +#define RK3399_PD_PERIHP 14 +#define RK3399_PD_VIO 15 +#define RK3399_PD_VO 16 +#define RK3399_PD_VOPB 17 +#define RK3399_PD_VOPL 18 +#define RK3399_PD_ISP0 19 +#define RK3399_PD_ISP1 20 +#define RK3399_PD_HDCP 21 +#define RK3399_PD_GMAC 22 +#define RK3399_PD_EMMC 23 +#define RK3399_PD_USB3 24 +#define RK3399_PD_EDP 25 +#define RK3399_PD_GIC 26 +#define RK3399_PD_SD 27 +#define RK3399_PD_SDIOAUDIO 28 +#define RK3399_PD_ALIVE 29 + +/* VD_CENTER */ +#define RK3399_PD_CENTER 30 +#define RK3399_PD_VCODEC 31 +#define RK3399_PD_VDU 32 +#define RK3399_PD_RGA 33 +#define RK3399_PD_IEP 34 + +/* VD_GPU */ +#define RK3399_PD_GPU 35 + +/* VD_PMU */ +#define RK3399_PD_PMU 36 + +#endif diff --git a/roms/u-boot/include/dt-bindings/power/tegra186-powergate.h b/roms/u-boot/include/dt-bindings/power/tegra186-powergate.h new file mode 100644 index 000000000..17e754985 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/tegra186-powergate.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2015-2016, NVIDIA CORPORATION. + */ + +#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H +#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H + +#define TEGRA186_POWER_DOMAIN_AUD 0 +#define TEGRA186_POWER_DOMAIN_DFD 1 +#define TEGRA186_POWER_DOMAIN_DISP 2 +#define TEGRA186_POWER_DOMAIN_DISPB 3 +#define TEGRA186_POWER_DOMAIN_DISPC 4 +#define TEGRA186_POWER_DOMAIN_ISPA 5 +#define TEGRA186_POWER_DOMAIN_NVDEC 6 +#define TEGRA186_POWER_DOMAIN_NVJPG 7 +#define TEGRA186_POWER_DOMAIN_MPE 8 +#define TEGRA186_POWER_DOMAIN_PCX 9 +#define TEGRA186_POWER_DOMAIN_SAX 10 +#define TEGRA186_POWER_DOMAIN_VE 11 +#define TEGRA186_POWER_DOMAIN_VIC 12 +#define TEGRA186_POWER_DOMAIN_XUSBA 13 +#define TEGRA186_POWER_DOMAIN_XUSBB 14 +#define TEGRA186_POWER_DOMAIN_XUSBC 15 +#define TEGRA186_POWER_DOMAIN_GPU 43 +#define TEGRA186_POWER_DOMAIN_MAX 44 + +#endif diff --git a/roms/u-boot/include/dt-bindings/power/xlnx-versal-power.h b/roms/u-boot/include/dt-bindings/power/xlnx-versal-power.h new file mode 100644 index 000000000..1b75175ed --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/xlnx-versal-power.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 - 2020 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_VERSAL_POWER_H +#define _DT_BINDINGS_VERSAL_POWER_H + +#define PM_DEV_USB_0 (0x18224018U) +#define PM_DEV_GEM_0 (0x18224019U) +#define PM_DEV_GEM_1 (0x1822401aU) +#define PM_DEV_SPI_0 (0x1822401bU) +#define PM_DEV_SPI_1 (0x1822401cU) +#define PM_DEV_I2C_0 (0x1822401dU) +#define PM_DEV_I2C_1 (0x1822401eU) +#define PM_DEV_CAN_FD_0 (0x1822401fU) +#define PM_DEV_CAN_FD_1 (0x18224020U) +#define PM_DEV_UART_0 (0x18224021U) +#define PM_DEV_UART_1 (0x18224022U) +#define PM_DEV_GPIO (0x18224023U) +#define PM_DEV_TTC_0 (0x18224024U) +#define PM_DEV_TTC_1 (0x18224025U) +#define PM_DEV_TTC_2 (0x18224026U) +#define PM_DEV_TTC_3 (0x18224027U) +#define PM_DEV_SWDT_FPD (0x18224029U) +#define PM_DEV_OSPI (0x1822402aU) +#define PM_DEV_QSPI (0x1822402bU) +#define PM_DEV_GPIO_PMC (0x1822402cU) +#define PM_DEV_SDIO_0 (0x1822402eU) +#define PM_DEV_SDIO_1 (0x1822402fU) +#define PM_DEV_RTC (0x18224034U) +#define PM_DEV_ADMA_0 (0x18224035U) +#define PM_DEV_ADMA_1 (0x18224036U) +#define PM_DEV_ADMA_2 (0x18224037U) +#define PM_DEV_ADMA_3 (0x18224038U) +#define PM_DEV_ADMA_4 (0x18224039U) +#define PM_DEV_ADMA_5 (0x1822403aU) +#define PM_DEV_ADMA_6 (0x1822403bU) +#define PM_DEV_ADMA_7 (0x1822403cU) +#define PM_DEV_AI (0x18224072U) + +#endif diff --git a/roms/u-boot/include/dt-bindings/power/xlnx-zynqmp-power.h b/roms/u-boot/include/dt-bindings/power/xlnx-zynqmp-power.h new file mode 100644 index 000000000..0d9a412fd --- /dev/null +++ b/roms/u-boot/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_ZYNQMP_POWER_H +#define _DT_BINDINGS_ZYNQMP_POWER_H + +#define PD_USB_0 22 +#define PD_USB_1 23 +#define PD_TTC_0 24 +#define PD_TTC_1 25 +#define PD_TTC_2 26 +#define PD_TTC_3 27 +#define PD_SATA 28 +#define PD_ETH_0 29 +#define PD_ETH_1 30 +#define PD_ETH_2 31 +#define PD_ETH_3 32 +#define PD_UART_0 33 +#define PD_UART_1 34 +#define PD_SPI_0 35 +#define PD_SPI_1 36 +#define PD_I2C_0 37 +#define PD_I2C_1 38 +#define PD_SD_0 39 +#define PD_SD_1 40 +#define PD_DP 41 +#define PD_GDMA 42 +#define PD_ADMA 43 +#define PD_NAND 44 +#define PD_QSPI 45 +#define PD_GPIO 46 +#define PD_CAN_0 47 +#define PD_CAN_1 48 +#define PD_GPU 58 +#define PD_PCIE 59 + +#endif diff --git a/roms/u-boot/include/dt-bindings/pwm/pwm.h b/roms/u-boot/include/dt-bindings/pwm/pwm.h new file mode 100644 index 000000000..96f49e822 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/pwm/pwm.h @@ -0,0 +1,14 @@ +/* + * This header provides constants for most PWM bindings. + * + * Most PWM bindings can include a flags cell as part of the PWM specifier. + * In most cases, the format of the flags cell uses the standard values + * defined in this header. + */ + +#ifndef _DT_BINDINGS_PWM_PWM_H +#define _DT_BINDINGS_PWM_PWM_H + +#define PWM_POLARITY_INVERTED (1 << 0) + +#endif diff --git a/roms/u-boot/include/dt-bindings/regulator/dlg,da9063-regulator.h b/roms/u-boot/include/dt-bindings/regulator/dlg,da9063-regulator.h new file mode 100644 index 000000000..1de710dd0 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/regulator/dlg,da9063-regulator.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_REGULATOR_DLG_DA9063_H +#define _DT_BINDINGS_REGULATOR_DLG_DA9063_H + +/* + * These buck mode constants may be used to specify values in device tree + * properties (e.g. regulator-initial-mode). + * A description of the following modes is in the manufacturers datasheet. + */ + +#define DA9063_BUCK_MODE_SLEEP 1 +#define DA9063_BUCK_MODE_SYNC 2 +#define DA9063_BUCK_MODE_AUTO 3 + +#endif diff --git a/roms/u-boot/include/dt-bindings/regulator/maxim,max77802.h b/roms/u-boot/include/dt-bindings/regulator/maxim,max77802.h new file mode 100644 index 000000000..cf28631d7 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/regulator/maxim,max77802.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for the Maxim 77802 PMIC regulators + */ + +#ifndef _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H +#define _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H + +/* Regulator operating modes */ +#define MAX77802_OPMODE_LP 1 +#define MAX77802_OPMODE_NORMAL 3 + +#endif /* _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H */ diff --git a/roms/u-boot/include/dt-bindings/reset/actions,s700-reset.h b/roms/u-boot/include/dt-bindings/reset/actions,s700-reset.h new file mode 100644 index 000000000..5e3b16b8e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/actions,s700-reset.h @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +// +// Device Tree binding constants for Actions Semi S700 Reset Management Unit +// +// Copyright (c) 2018 Linaro Ltd. + +#ifndef __DT_BINDINGS_ACTIONS_S700_RESET_H +#define __DT_BINDINGS_ACTIONS_S700_RESET_H + +#define RESET_AUDIO 0 +#define RESET_CSI 1 +#define RESET_DE 2 +#define RESET_DSI 3 +#define RESET_GPIO 4 +#define RESET_I2C0 5 +#define RESET_I2C1 6 +#define RESET_I2C2 7 +#define RESET_I2C3 8 +#define RESET_KEY 9 +#define RESET_LCD0 10 +#define RESET_SI 11 +#define RESET_SPI0 12 +#define RESET_SPI1 13 +#define RESET_SPI2 14 +#define RESET_SPI3 15 +#define RESET_UART0 16 +#define RESET_UART1 17 +#define RESET_UART2 18 +#define RESET_UART3 19 +#define RESET_UART4 20 +#define RESET_UART5 21 +#define RESET_UART6 22 + +#endif /* __DT_BINDINGS_ACTIONS_S700_RESET_H */ diff --git a/roms/u-boot/include/dt-bindings/reset/actions,s900-reset.h b/roms/u-boot/include/dt-bindings/reset/actions,s900-reset.h new file mode 100644 index 000000000..42c19d02e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/actions,s900-reset.h @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +// +// Device Tree binding constants for Actions Semi S900 Reset Management Unit +// +// Copyright (c) 2018 Linaro Ltd. + +#ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H +#define __DT_BINDINGS_ACTIONS_S900_RESET_H + +#define RESET_CHIPID 0 +#define RESET_CPU_SCNT 1 +#define RESET_SRAMI 2 +#define RESET_DDR_CTL_PHY 3 +#define RESET_DMAC 4 +#define RESET_GPIO 5 +#define RESET_BISP_AXI 6 +#define RESET_CSI0 7 +#define RESET_CSI1 8 +#define RESET_DE 9 +#define RESET_DSI 10 +#define RESET_GPU3D_PA 11 +#define RESET_GPU3D_PB 12 +#define RESET_HDE 13 +#define RESET_I2C0 14 +#define RESET_I2C1 15 +#define RESET_I2C2 16 +#define RESET_I2C3 17 +#define RESET_I2C4 18 +#define RESET_I2C5 19 +#define RESET_IMX 20 +#define RESET_NANDC0 21 +#define RESET_NANDC1 22 +#define RESET_SD0 23 +#define RESET_SD1 24 +#define RESET_SD2 25 +#define RESET_SD3 26 +#define RESET_SPI0 27 +#define RESET_SPI1 28 +#define RESET_SPI2 29 +#define RESET_SPI3 30 +#define RESET_UART0 31 +#define RESET_UART1 32 +#define RESET_UART2 33 +#define RESET_UART3 34 +#define RESET_UART4 35 +#define RESET_UART5 36 +#define RESET_UART6 37 +#define RESET_HDMI 38 +#define RESET_LVDS 39 +#define RESET_EDP 40 +#define RESET_USB2HUB 41 +#define RESET_USB2HSIC 42 +#define RESET_USB3 43 +#define RESET_PCM1 44 +#define RESET_AUDIO 45 +#define RESET_PCM0 46 +#define RESET_SE 47 +#define RESET_GIC 48 +#define RESET_DDR_CTL_PHY_AXI 49 +#define RESET_CMU_DDR 50 +#define RESET_DMM 51 +#define RESET_HDCP2TX 52 +#define RESET_ETHERNET 53 + +#endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */ diff --git a/roms/u-boot/include/dt-bindings/reset/altr,rst-mgr-a10.h b/roms/u-boot/include/dt-bindings/reset/altr,rst-mgr-a10.h new file mode 100644 index 000000000..acb0bbf4f --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/altr,rst-mgr-a10.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2014, Steffen Trumtrar + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define WDS_RESET 2 +#define SCUPER_RESET 3 + +/* PER0MODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define EMAC2_RESET 34 +#define USB0_RESET 35 +#define USB1_RESET 36 +#define NAND_RESET 37 +#define QSPI_RESET 38 +#define SDMMC_RESET 39 +#define EMAC0_OCP_RESET 40 +#define EMAC1_OCP_RESET 41 +#define EMAC2_OCP_RESET 42 +#define USB0_OCP_RESET 43 +#define USB1_OCP_RESET 44 +#define NAND_OCP_RESET 45 +#define QSPI_OCP_RESET 46 +#define SDMMC_OCP_RESET 47 +#define DMA_RESET 48 +#define SPIM0_RESET 49 +#define SPIM1_RESET 50 +#define SPIS0_RESET 51 +#define SPIS1_RESET 52 +#define DMA_OCP_RESET 53 +#define EMAC_PTP_RESET 54 +/* 55 is empty*/ +#define DMAIF0_RESET 56 +#define DMAIF1_RESET 57 +#define DMAIF2_RESET 58 +#define DMAIF3_RESET 59 +#define DMAIF4_RESET 60 +#define DMAIF5_RESET 61 +#define DMAIF6_RESET 62 +#define DMAIF7_RESET 63 + +/* PER1MODRST */ +#define L4WD0_RESET 64 +#define L4WD1_RESET 65 +#define L4SYSTIMER0_RESET 66 +#define L4SYSTIMER1_RESET 67 +#define SPTIMER0_RESET 68 +#define SPTIMER1_RESET 69 +/* 70-71 is reserved */ +#define I2C0_RESET 72 +#define I2C1_RESET 73 +#define I2C2_RESET 74 +#define I2C3_RESET 75 +#define I2C4_RESET 76 +/* 77-79 is reserved */ +#define UART0_RESET 80 +#define UART1_RESET 81 +/* 82-87 is reserved */ +#define GPIO0_RESET 88 +#define GPIO1_RESET 89 +#define GPIO2_RESET 90 + +/* BRGMODRST */ +#define HPS2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2HPS_RESET 98 +#define F2SSDRAM0_RESET 99 +#define F2SSDRAM1_RESET 100 +#define F2SSDRAM2_RESET 101 +#define DDRSCH_RESET 102 + +/* SYSMODRST*/ +#define ROM_RESET 128 +#define OCRAM_RESET 129 +/* 130 is reserved */ +#define FPGAMGR_RESET 131 +#define S2F_RESET 132 +#define SYSDBG_RESET 133 +#define OCRAM_OCP_RESET 134 + +/* COLDMODRST */ +#define CLKMGRCOLD_RESET 160 +/* 161-162 is reserved */ +#define S2FCOLD_RESET 163 +#define TIMESTAMPCOLD_RESET 164 +#define TAPCOLD_RESET 165 +#define HMCCOLD_RESET 166 +#define IOMGRCOLD_RESET 167 + +/* NRSTMODRST */ +#define NRSTPINOE_RESET 192 + +/* DBGMODRST */ +#define DBG_RESET 224 +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/altr,rst-mgr-s10.h b/roms/u-boot/include/dt-bindings/reset/altr,rst-mgr-s10.h new file mode 100644 index 000000000..1fdcf8ae1 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/altr,rst-mgr-s10.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016-2018 Intel Corporation. All rights reserved + * Copyright (C) 2016 Altera Corporation. All rights reserved + * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define CPU2_RESET 2 +#define CPU3_RESET 3 + +/* PER0MODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define EMAC2_RESET 34 +#define USB0_RESET 35 +#define USB1_RESET 36 +#define NAND_RESET 37 +/* 38 is empty */ +#define SDMMC_RESET 39 +#define EMAC0_OCP_RESET 40 +#define EMAC1_OCP_RESET 41 +#define EMAC2_OCP_RESET 42 +#define USB0_OCP_RESET 43 +#define USB1_OCP_RESET 44 +#define NAND_OCP_RESET 45 +/* 46 is empty */ +#define SDMMC_OCP_RESET 47 +#define DMA_RESET 48 +#define SPIM0_RESET 49 +#define SPIM1_RESET 50 +#define SPIS0_RESET 51 +#define SPIS1_RESET 52 +#define DMA_OCP_RESET 53 +#define EMAC_PTP_RESET 54 +/* 55 is empty*/ +#define DMAIF0_RESET 56 +#define DMAIF1_RESET 57 +#define DMAIF2_RESET 58 +#define DMAIF3_RESET 59 +#define DMAIF4_RESET 60 +#define DMAIF5_RESET 61 +#define DMAIF6_RESET 62 +#define DMAIF7_RESET 63 + +/* PER1MODRST */ +#define WATCHDOG0_RESET 64 +#define WATCHDOG1_RESET 65 +#define WATCHDOG2_RESET 66 +#define WATCHDOG3_RESET 67 +#define L4SYSTIMER0_RESET 68 +#define L4SYSTIMER1_RESET 69 +#define SPTIMER0_RESET 70 +#define SPTIMER1_RESET 71 +#define I2C0_RESET 72 +#define I2C1_RESET 73 +#define I2C2_RESET 74 +#define I2C3_RESET 75 +#define I2C4_RESET 76 +/* 77-79 is empty */ +#define UART0_RESET 80 +#define UART1_RESET 81 +/* 82-87 is empty */ +#define GPIO0_RESET 88 +#define GPIO1_RESET 89 + +/* BRGMODRST */ +#define SOC2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2SOC_RESET 98 +#define F2SSDRAM0_RESET 99 +#define F2SSDRAM1_RESET 100 +#define F2SSDRAM2_RESET 101 +#define DDRSCH_RESET 102 + +/* COLDMODRST */ +#define CPUPO0_RESET 160 +#define CPUPO1_RESET 161 +#define CPUPO2_RESET 162 +#define CPUPO3_RESET 163 +/* 164-167 is empty */ +#define L2_RESET 168 + +/* DBGMODRST */ +#define DBG_RESET 224 +#define CSDAP_RESET 225 + +/* TAPMODRST */ +#define TAP_RESET 256 + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/altr,rst-mgr.h b/roms/u-boot/include/dt-bindings/reset/altr,rst-mgr.h new file mode 100644 index 000000000..5b7ad7396 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/altr,rst-mgr.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2014, Steffen Trumtrar + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define WDS_RESET 2 +#define SCUPER_RESET 3 +#define L2_RESET 4 + +/* PERMODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define USB0_RESET 34 +#define USB1_RESET 35 +#define NAND_RESET 36 +#define QSPI_RESET 37 +#define L4WD0_RESET 38 +#define L4WD1_RESET 39 +#define OSC1TIMER0_RESET 40 +#define OSC1TIMER1_RESET 41 +#define SPTIMER0_RESET 42 +#define SPTIMER1_RESET 43 +#define I2C0_RESET 44 +#define I2C1_RESET 45 +#define I2C2_RESET 46 +#define I2C3_RESET 47 +#define UART0_RESET 48 +#define UART1_RESET 49 +#define SPIM0_RESET 50 +#define SPIM1_RESET 51 +#define SPIS0_RESET 52 +#define SPIS1_RESET 53 +#define SDMMC_RESET 54 +#define CAN0_RESET 55 +#define CAN1_RESET 56 +#define GPIO0_RESET 57 +#define GPIO1_RESET 58 +#define GPIO2_RESET 59 +#define DMA_RESET 60 +#define SDR_RESET 61 + +/* PER2MODRST */ +#define DMAIF0_RESET 64 +#define DMAIF1_RESET 65 +#define DMAIF2_RESET 66 +#define DMAIF3_RESET 67 +#define DMAIF4_RESET 68 +#define DMAIF5_RESET 69 +#define DMAIF6_RESET 70 +#define DMAIF7_RESET 71 + +/* BRGMODRST */ +#define HPS2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2HPS_RESET 98 + +/* MISCMODRST*/ +#define ROM_RESET 128 +#define OCRAM_RESET 129 +#define SYSMGR_RESET 130 +#define SYSMGRCOLD_RESET 131 +#define FPGAMGR_RESET 132 +#define ACPIDMAP_RESET 133 +#define S2F_RESET 134 +#define S2FCOLD_RESET 135 +#define NRSTPIN_RESET 136 +#define TIMESTAMPCOLD_RESET 137 +#define CLKMGRCOLD_RESET 138 +#define SCANMGR_RESET 139 +#define FRZCTRLCOLD_RESET 140 +#define SYSDBG_RESET 141 +#define DBG_RESET 142 +#define TAPCOLD_RESET 143 +#define SDRCOLD_RESET 144 + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/roms/u-boot/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h new file mode 100644 index 000000000..1ef807856 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) + * + * Copyright (c) 2018 Baylibre SAS. + * Author: Jerome Brunet + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H +#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H + +#define AXG_ARB_TODDR_A 0 +#define AXG_ARB_TODDR_B 1 +#define AXG_ARB_TODDR_C 2 +#define AXG_ARB_FRDDR_A 3 +#define AXG_ARB_FRDDR_B 4 +#define AXG_ARB_FRDDR_C 5 +#define AXG_ARB_TODDR_D 6 +#define AXG_ARB_FRDDR_D 7 + +#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */ diff --git a/roms/u-boot/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/roms/u-boot/include/dt-bindings/reset/amlogic,meson-axg-reset.h new file mode 100644 index 000000000..0f2e0fe45 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/amlogic,meson-axg-reset.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong + * + * Copyright (c) 2017 Amlogic, inc. + * Author: Yixun Lan + * + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H + +/* RESET0 */ +#define RESET_HIU 0 +#define RESET_PCIE_A 1 +#define RESET_PCIE_B 2 +#define RESET_DDR_TOP 3 +/* 4 */ +#define RESET_VIU 5 +#define RESET_PCIE_PHY 6 +#define RESET_PCIE_APB 7 +/* 8 */ +/* 9 */ +#define RESET_VENC 10 +#define RESET_ASSIST 11 +/* 12 */ +#define RESET_VCBUS 13 +/* 14 */ +/* 15 */ +#define RESET_GIC 16 +#define RESET_CAPB3_DECODE 17 +/* 18-21 */ +#define RESET_SYS_CPU_CAPB3 22 +#define RESET_CBUS_CAPB3 23 +#define RESET_AHB_CNTL 24 +#define RESET_AHB_DATA 25 +#define RESET_VCBUS_CLK81 26 +#define RESET_MMC 27 +/* 28-31 */ +/* RESET1 */ +/* 32 */ +/* 33 */ +#define RESET_USB_OTG 34 +#define RESET_DDR 35 +#define RESET_AO_RESET 36 +/* 37 */ +#define RESET_AHB_SRAM 38 +/* 39 */ +/* 40 */ +#define RESET_DMA 41 +#define RESET_ISA 42 +#define RESET_ETHERNET 43 +/* 44 */ +#define RESET_SD_EMMC_B 45 +#define RESET_SD_EMMC_C 46 +#define RESET_ROM_BOOT 47 +#define RESET_SYS_CPU_0 48 +#define RESET_SYS_CPU_1 49 +#define RESET_SYS_CPU_2 50 +#define RESET_SYS_CPU_3 51 +#define RESET_SYS_CPU_CORE_0 52 +#define RESET_SYS_CPU_CORE_1 53 +#define RESET_SYS_CPU_CORE_2 54 +#define RESET_SYS_CPU_CORE_3 55 +#define RESET_SYS_PLL_DIV 56 +#define RESET_SYS_CPU_AXI 57 +#define RESET_SYS_CPU_L2 58 +#define RESET_SYS_CPU_P 59 +#define RESET_SYS_CPU_MBIST 60 +/* 61-63 */ +/* RESET2 */ +/* 64 */ +/* 65 */ +#define RESET_AUDIO 66 +/* 67 */ +#define RESET_MIPI_HOST 68 +#define RESET_AUDIO_LOCKER 69 +#define RESET_GE2D 70 +/* 71-76 */ +#define RESET_AO_CPU_RESET 77 +/* 78-95 */ +/* RESET3 */ +#define RESET_RING_OSCILLATOR 96 +/* 97-127 */ +/* RESET4 */ +/* 128 */ +/* 129 */ +#define RESET_MIPI_PHY 130 +/* 131-140 */ +#define RESET_VENCL 141 +#define RESET_I2C_MASTER_2 142 +#define RESET_I2C_MASTER_1 143 +/* 144-159 */ +/* RESET5 */ +/* 160-191 */ +/* RESET6 */ +#define RESET_PERIPHS_GENERAL 192 +#define RESET_PERIPHS_SPICC 193 +/* 194 */ +/* 195 */ +#define RESET_PERIPHS_I2C_MASTER_0 196 +/* 197-200 */ +#define RESET_PERIPHS_UART_0 201 +#define RESET_PERIPHS_UART_1 202 +/* 203-204 */ +#define RESET_PERIPHS_SPI_0 205 +#define RESET_PERIPHS_I2C_MASTER_3 206 +/* 207-223 */ +/* RESET7 */ +#define RESET_USB_DDR_0 224 +#define RESET_USB_DDR_1 225 +#define RESET_USB_DDR_2 226 +#define RESET_USB_DDR_3 227 +/* 228 */ +#define RESET_DEVICE_MMC_ARB 229 +/* 230 */ +#define RESET_VID_LOCK 231 +#define RESET_A9_DMC_PIPEL 232 +#define RESET_DMC_VPU_PIPEL 233 +/* 234-255 */ + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/roms/u-boot/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h new file mode 100644 index 000000000..f805129ca --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Jerome Brunet + * + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H + +#define AUD_RESET_PDM 0 +#define AUD_RESET_TDMIN_A 1 +#define AUD_RESET_TDMIN_B 2 +#define AUD_RESET_TDMIN_C 3 +#define AUD_RESET_TDMIN_LB 4 +#define AUD_RESET_LOOPBACK 5 +#define AUD_RESET_TODDR_A 6 +#define AUD_RESET_TODDR_B 7 +#define AUD_RESET_TODDR_C 8 +#define AUD_RESET_FRDDR_A 9 +#define AUD_RESET_FRDDR_B 10 +#define AUD_RESET_FRDDR_C 11 +#define AUD_RESET_TDMOUT_A 12 +#define AUD_RESET_TDMOUT_B 13 +#define AUD_RESET_TDMOUT_C 14 +#define AUD_RESET_SPDIFOUT 15 +#define AUD_RESET_SPDIFOUT_B 16 +#define AUD_RESET_SPDIFIN 17 +#define AUD_RESET_EQDRC 18 +#define AUD_RESET_RESAMPLE 19 +#define AUD_RESET_DDRARB 20 +#define AUD_RESET_POWDET 21 +#define AUD_RESET_TORAM 22 +#define AUD_RESET_TOACODEC 23 +#define AUD_RESET_TOHDMITX 24 +#define AUD_RESET_CLKTREE 25 + +/* SM1 added resets */ +#define AUD_RESET_RESAMPLE_B 26 +#define AUD_RESET_TOVAD 27 +#define AUD_RESET_LOCKER 28 +#define AUD_RESET_SPDIFIN_LB 29 +#define AUD_RESET_FRATV 30 +#define AUD_RESET_FRHDMIRX 31 +#define AUD_RESET_FRDDR_D 32 +#define AUD_RESET_TODDR_D 33 +#define AUD_RESET_LOOPBACK_B 34 +#define AUD_RESET_EARCTX 35 +#define AUD_RESET_EARCRX 36 +#define AUD_RESET_FRDDR_E 37 +#define AUD_RESET_TODDR_E 38 + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/roms/u-boot/include/dt-bindings/reset/amlogic,meson-g12a-reset.h new file mode 100644 index 000000000..6d487c5eb --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/amlogic,meson-g12a-reset.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Jerome Brunet + * + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H + +/* RESET0 */ +#define RESET_HIU 0 +/* 1 */ +#define RESET_DOS 2 +/* 3-4 */ +#define RESET_VIU 5 +#define RESET_AFIFO 6 +#define RESET_VID_PLL_DIV 7 +/* 8-9 */ +#define RESET_VENC 10 +#define RESET_ASSIST 11 +#define RESET_PCIE_CTRL_A 12 +#define RESET_VCBUS 13 +#define RESET_PCIE_PHY 14 +#define RESET_PCIE_APB 15 +#define RESET_GIC 16 +#define RESET_CAPB3_DECODE 17 +/* 18 */ +#define RESET_HDMITX_CAPB3 19 +#define RESET_DVALIN_CAPB3 20 +#define RESET_DOS_CAPB3 21 +/* 22 */ +#define RESET_CBUS_CAPB3 23 +#define RESET_AHB_CNTL 24 +#define RESET_AHB_DATA 25 +#define RESET_VCBUS_CLK81 26 +/* 27-31 */ +/* RESET1 */ +/* 32 */ +#define RESET_DEMUX 33 +#define RESET_USB 34 +#define RESET_DDR 35 +/* 36 */ +#define RESET_BT656 37 +#define RESET_AHB_SRAM 38 +/* 39 */ +#define RESET_PARSER 40 +/* 41 */ +#define RESET_ISA 42 +#define RESET_ETHERNET 43 +#define RESET_SD_EMMC_A 44 +#define RESET_SD_EMMC_B 45 +#define RESET_SD_EMMC_C 46 +/* 47 */ +#define RESET_USB_PHY20 48 +#define RESET_USB_PHY21 49 +/* 50-60 */ +#define RESET_AUDIO_CODEC 61 +/* 62-63 */ +/* RESET2 */ +/* 64 */ +#define RESET_AUDIO 65 +#define RESET_HDMITX_PHY 66 +/* 67 */ +#define RESET_MIPI_DSI_HOST 68 +#define RESET_ALOCKER 69 +#define RESET_GE2D 70 +#define RESET_PARSER_REG 71 +#define RESET_PARSER_FETCH 72 +#define RESET_CTL 73 +#define RESET_PARSER_TOP 74 +/* 75-77 */ +#define RESET_DVALIN 78 +#define RESET_HDMITX 79 +/* 80-95 */ +/* RESET3 */ +/* 96-95 */ +#define RESET_DEMUX_TOP 105 +#define RESET_DEMUX_DES_PL 106 +#define RESET_DEMUX_S2P_0 107 +#define RESET_DEMUX_S2P_1 108 +#define RESET_DEMUX_0 109 +#define RESET_DEMUX_1 110 +#define RESET_DEMUX_2 111 +/* 112-127 */ +/* RESET4 */ +/* 128-129 */ +#define RESET_MIPI_DSI_PHY 130 +/* 131-132 */ +#define RESET_RDMA 133 +#define RESET_VENCI 134 +#define RESET_VENCP 135 +/* 136 */ +#define RESET_VDAC 137 +/* 138-139 */ +#define RESET_VDI6 140 +#define RESET_VENCL 141 +#define RESET_I2C_M1 142 +#define RESET_I2C_M2 143 +/* 144-159 */ +/* RESET5 */ +/* 160-191 */ +/* RESET6 */ +#define RESET_GEN 192 +#define RESET_SPICC0 193 +#define RESET_SC 194 +#define RESET_SANA_3 195 +#define RESET_I2C_M0 196 +#define RESET_TS_PLL 197 +#define RESET_SPICC1 198 +#define RESET_STREAM 199 +#define RESET_TS_CPU 200 +#define RESET_UART0 201 +#define RESET_UART1_2 202 +#define RESET_ASYNC0 203 +#define RESET_ASYNC1 204 +#define RESET_SPIFC0 205 +#define RESET_I2C_M3 206 +/* 207-223 */ +/* RESET7 */ +#define RESET_USB_DDR_0 224 +#define RESET_USB_DDR_1 225 +#define RESET_USB_DDR_2 226 +#define RESET_USB_DDR_3 227 +#define RESET_TS_GPU 228 +#define RESET_DEVICE_MMC_ARB 229 +#define RESET_DVALIN_DMC_PIPL 230 +#define RESET_VID_LOCK 231 +#define RESET_NIC_DMC_PIPL 232 +#define RESET_DMC_VPU_PIPL 233 +#define RESET_GE2D_DMC_PIPL 234 +#define RESET_HCODEC_DMC_PIPL 235 +#define RESET_WAVE420_DMC_PIPL 236 +#define RESET_HEVCF_DMC_PIPL 237 +/* 238-255 */ + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/roms/u-boot/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h new file mode 100644 index 000000000..883bfd3bc --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong + */ +#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H + +/* RESET0 */ +#define RESET_HIU 0 +/* 1 */ +#define RESET_DOS_RESET 2 +#define RESET_DDR_TOP 3 +#define RESET_DCU_RESET 4 +#define RESET_VIU 5 +#define RESET_AIU 6 +#define RESET_VID_PLL_DIV 7 +/* 8 */ +#define RESET_PMUX 9 +#define RESET_VENC 10 +#define RESET_ASSIST 11 +#define RESET_AFIFO2 12 +#define RESET_VCBUS 13 +/* 14 */ +/* 15 */ +#define RESET_GIC 16 +#define RESET_CAPB3_DECODE 17 +#define RESET_NAND_CAPB3 18 +#define RESET_HDMITX_CAPB3 19 +#define RESET_MALI_CAPB3 20 +#define RESET_DOS_CAPB3 21 +#define RESET_SYS_CPU_CAPB3 22 +#define RESET_CBUS_CAPB3 23 +#define RESET_AHB_CNTL 24 +#define RESET_AHB_DATA 25 +#define RESET_VCBUS_CLK81 26 +#define RESET_MMC 27 +#define RESET_MIPI_0 28 +#define RESET_MIPI_1 29 +#define RESET_MIPI_2 30 +#define RESET_MIPI_3 31 +/* RESET1 */ +#define RESET_CPPM 32 +#define RESET_DEMUX 33 +#define RESET_USB_OTG 34 +#define RESET_DDR 35 +#define RESET_AO_RESET 36 +#define RESET_BT656 37 +#define RESET_AHB_SRAM 38 +/* 39 */ +#define RESET_PARSER 40 +#define RESET_BLKMV 41 +#define RESET_ISA 42 +#define RESET_ETHERNET 43 +#define RESET_SD_EMMC_A 44 +#define RESET_SD_EMMC_B 45 +#define RESET_SD_EMMC_C 46 +#define RESET_ROM_BOOT 47 +#define RESET_SYS_CPU_0 48 +#define RESET_SYS_CPU_1 49 +#define RESET_SYS_CPU_2 50 +#define RESET_SYS_CPU_3 51 +#define RESET_SYS_CPU_CORE_0 52 +#define RESET_SYS_CPU_CORE_1 53 +#define RESET_SYS_CPU_CORE_2 54 +#define RESET_SYS_CPU_CORE_3 55 +#define RESET_SYS_PLL_DIV 56 +#define RESET_SYS_CPU_AXI 57 +#define RESET_SYS_CPU_L2 58 +#define RESET_SYS_CPU_P 59 +#define RESET_SYS_CPU_MBIST 60 +#define RESET_ACODEC 61 +/* 62 */ +/* 63 */ +/* RESET2 */ +#define RESET_VD_RMEM 64 +#define RESET_AUDIN 65 +#define RESET_HDMI_TX 66 +/* 67 */ +/* 68 */ +/* 69 */ +#define RESET_GE2D 70 +#define RESET_PARSER_REG 71 +#define RESET_PARSER_FETCH 72 +#define RESET_PARSER_CTL 73 +#define RESET_PARSER_TOP 74 +/* 75 */ +/* 76 */ +#define RESET_AO_CPU_RESET 77 +#define RESET_MALI 78 +#define RESET_HDMI_SYSTEM_RESET 79 +/* 80-95 */ +/* RESET3 */ +#define RESET_RING_OSCILLATOR 96 +#define RESET_SYS_CPU 97 +#define RESET_EFUSE 98 +#define RESET_SYS_CPU_BVCI 99 +#define RESET_AIFIFO 100 +#define RESET_TVFE 101 +#define RESET_AHB_BRIDGE_CNTL 102 +/* 103 */ +#define RESET_AUDIO_DAC 104 +#define RESET_DEMUX_TOP 105 +#define RESET_DEMUX_DES 106 +#define RESET_DEMUX_S2P_0 107 +#define RESET_DEMUX_S2P_1 108 +#define RESET_DEMUX_RESET_0 109 +#define RESET_DEMUX_RESET_1 110 +#define RESET_DEMUX_RESET_2 111 +/* 112-127 */ +/* RESET4 */ +/* 128 */ +/* 129 */ +/* 130 */ +/* 131 */ +#define RESET_DVIN_RESET 132 +#define RESET_RDMA 133 +#define RESET_VENCI 134 +#define RESET_VENCP 135 +/* 136 */ +#define RESET_VDAC 137 +#define RESET_RTC 138 +/* 139 */ +#define RESET_VDI6 140 +#define RESET_VENCL 141 +#define RESET_I2C_MASTER_2 142 +#define RESET_I2C_MASTER_1 143 +/* 144-159 */ +/* RESET5 */ +/* 160-191 */ +/* RESET6 */ +#define RESET_PERIPHS_GENERAL 192 +#define RESET_PERIPHS_SPICC 193 +#define RESET_PERIPHS_SMART_CARD 194 +#define RESET_PERIPHS_SAR_ADC 195 +#define RESET_PERIPHS_I2C_MASTER_0 196 +#define RESET_SANA 197 +/* 198 */ +#define RESET_PERIPHS_STREAM_INTERFACE 199 +#define RESET_PERIPHS_SDIO 200 +#define RESET_PERIPHS_UART_0 201 +#define RESET_PERIPHS_UART_1_2 202 +#define RESET_PERIPHS_ASYNC_0 203 +#define RESET_PERIPHS_ASYNC_1 204 +#define RESET_PERIPHS_SPI_0 205 +#define RESET_PERIPHS_SDHC 206 +#define RESET_UART_SLIP 207 +/* 208-223 */ +/* RESET7 */ +#define RESET_USB_DDR_0 224 +#define RESET_USB_DDR_1 225 +#define RESET_USB_DDR_2 226 +#define RESET_USB_DDR_3 227 +/* 228 */ +#define RESET_DEVICE_MMC_ARB 229 +/* 230 */ +#define RESET_VID_LOCK 231 +#define RESET_A9_DMC_PIPEL 232 +/* 233-255 */ + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/ast2500-reset.h b/roms/u-boot/include/dt-bindings/reset/ast2500-reset.h new file mode 100644 index 000000000..cc85a31ed --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/ast2500-reset.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 Google, Inc + * Copyright 2020 ASPEED Technology Inc. + */ + +#ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_ +#define _ABI_MACH_ASPEED_AST2500_RESET_H_ + +#define ASPEED_RESET_CRT1 (37) +#define ASPEED_RESET_RESERVED36 (36) +#define ASPEED_RESET_RESERVED35 (35) +#define ASPEED_RESET_RESERVED34 (34) +#define ASPEED_RESET_RESERVED33 (33) +#define ASPEED_RESET_RESERVED32 (32) +#define ASPEED_RESET_RESERVED31 (31) +#define ASPEED_RESET_RESERVED30 (30) +#define ASPEED_RESET_RESERVED29 (29) +#define ASPEED_RESET_RESERVED28 (28) +#define ASPEED_RESET_RESERVED27 (27) +#define ASPEED_RESET_RESERVED26 (26) +#define ASPEED_RESET_XDMA (25) +#define ASPEED_RESET_MCTP (24) +#define ASPEED_RESET_ADC (23) +#define ASPEED_RESET_JTAG_MASTER (22) +#define ASPEED_RESET_RESERVED21 (21) +#define ASPEED_RESET_RESERVED20 (20) +#define ASPEED_RESET_RESERVED19 (19) +#define ASPEED_RESET_MIC (18) +#define ASPEED_RESET_RESERVED17 (17) +#define ASPEED_RESET_SDIO (16) +#define ASPEED_RESET_UHCI (15) +#define ASPEED_RESET_EHCI_P1 (14) +#define ASPEED_RESET_CRT (13) +#define ASPEED_RESET_MAC2 (12) +#define ASPEED_RESET_MAC1 (11) +#define ASPEED_RESET_PECI (10) +#define ASPEED_RESET_PWM (9) +#define ASPEED_RESET_PCI_VGA (8) +#define ASPEED_RESET_2D (7) +#define ASPEED_RESET_VIDEO (6) +#define ASPEED_RESET_LPC_ESPI (5) +#define ASPEED_RESET_HACE (4) +#define ASPEED_RESET_EHCI_P2 (3) +#define ASPEED_RESET_I2C (2) +#define ASPEED_RESET_AHB (1) +#define ASPEED_RESET_SDRAM (0) + +#endif /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/ast2600-reset.h b/roms/u-boot/include/dt-bindings/reset/ast2600-reset.h new file mode 100644 index 000000000..b6d0f7991 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/ast2600-reset.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#ifndef _ABI_MACH_ASPEED_AST2600_RESET_H_ +#define _ABI_MACH_ASPEED_AST2600_RESET_H_ + +#define ASPEED_RESET_FSI (59) +#define ASPEED_RESET_RESERVED58 (58) +#define ASPEED_RESET_RESERVED57 (57) +#define ASPEED_RESET_SD (56) +#define ASPEED_RESET_ADC (55) +#define ASPEED_RESET_JTAG_MASTER2 (54) +#define ASPEED_RESET_MAC4 (53) +#define ASPEED_RESET_MAC3 (52) +#define ASPEED_RESET_RESERVE51 (51) +#define ASPEED_RESET_RESERVE50 (50) +#define ASPEED_RESET_RESERVE49 (49) +#define ASPEED_RESET_RESERVE48 (48) +#define ASPEED_RESET_RESERVE47 (47) +#define ASPEED_RESET_RESERVE46 (46) +#define ASPEED_RESET_I3C5 (45) +#define ASPEED_RESET_I3C4 (44) +#define ASPEED_RESET_I3C3 (43) +#define ASPEED_RESET_I3C2 (42) +#define ASPEED_RESET_I3C1 (41) +#define ASPEED_RESET_I3C0 (40) +#define ASPEED_RESET_I3C_DMA (39) +#define ASPEED_RESET_RESERVED38 (38) +#define ASPEED_RESET_PWM (37) +#define ASPEED_RESET_PECI (36) +#define ASPEED_RESET_MII (35) +#define ASPEED_RESET_I2C (34) +#define ASPEED_RESET_RESERVED33 (33) +#define ASPEED_RESET_LPC_ESPI (32) +#define ASPEED_RESET_H2X (31) +#define ASPEED_RESET_GP_MCU (30) +#define ASPEED_RESET_DP_MCU (29) +#define ASPEED_RESET_DP (28) +#define ASPEED_RESET_RC_XDMA (27) +#define ASPEED_RESET_GRAPHICS (26) +#define ASPEED_RESET_DEV_XDMA (25) +#define ASPEED_RESET_DEV_MCTP (24) +#define ASPEED_RESET_RC_MCTP (23) +#define ASPEED_RESET_JTAG_MASTER (22) +#define ASPEED_RESET_PCIE_DEV_OE (21) +#define ASPEED_RESET_PCIE_DEV_O (20) +#define ASPEED_RESET_PCIE_RC_OE (19) +#define ASPEED_RESET_PCIE_RC_O (18) +#define ASPEED_RESET_RESERVED17 (17) +#define ASPEED_RESET_EMMC (16) +#define ASPEED_RESET_UHCI (15) +#define ASPEED_RESET_EHCI_P1 (14) +#define ASPEED_RESET_CRT (13) +#define ASPEED_RESET_MAC2 (12) +#define ASPEED_RESET_MAC1 (11) +#define ASPEED_RESET_RESERVED10 (10) +#define ASPEED_RESET_RVAS (9) +#define ASPEED_RESET_PCI_VGA (8) +#define ASPEED_RESET_2D (7) +#define ASPEED_RESET_VIDEO (6) +#define ASPEED_RESET_PCI_DP (5) +#define ASPEED_RESET_HACE (4) +#define ASPEED_RESET_EHCI_P2 (3) +#define ASPEED_RESET_RESERVED2 (2) +#define ASPEED_RESET_AHB (1) +#define ASPEED_RESET_SDRAM (0) + +#endif /* _ABI_MACH_ASPEED_AST2600_RESET_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/axg-aoclkc.h b/roms/u-boot/include/dt-bindings/reset/axg-aoclkc.h new file mode 100644 index 000000000..d342c0b6b --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/axg-aoclkc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Qiufang Dai + */ + +#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK +#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK + +#define RESET_AO_REMOTE 0 +#define RESET_AO_I2C_MASTER 1 +#define RESET_AO_I2C_SLAVE 2 +#define RESET_AO_UART1 3 +#define RESET_AO_UART2 4 +#define RESET_AO_IR_BLASTER 5 + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/bcm3380-reset.h b/roms/u-boot/include/dt-bindings/reset/bcm3380-reset.h new file mode 100644 index 000000000..4cbf4d289 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/bcm3380-reset.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from Broadcom GPL Source Code: + * Copyright (C) Broadcom Corporation + */ + +#ifndef __DT_BINDINGS_RESET_BCM3380_H +#define __DT_BINDINGS_RESET_BCM3380_H + +#define BCM3380_RST0_SPI 0 +#define BCM3380_RST0_PCM 13 + +#endif /* __DT_BINDINGS_RESET_BCM3380_H */ diff --git a/roms/u-boot/include/dt-bindings/reset/bcm6318-reset.h b/roms/u-boot/include/dt-bindings/reset/bcm6318-reset.h new file mode 100644 index 000000000..1422500f8 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/bcm6318-reset.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_RESET_BCM6318_H +#define __DT_BINDINGS_RESET_BCM6318_H + +#define BCM6318_RST_SPI 0 +#define BCM6318_RST_EPHY 1 +#define BCM6318_RST_SAR 2 +#define BCM6318_RST_ENETSW 3 +#define BCM6318_RST_USBD 4 +#define BCM6318_RST_USBH 5 +#define BCM6318_RST_PCIE_CORE 6 +#define BCM6318_RST_PCIE 7 +#define BCM6318_RST_PCIE_EXT 8 +#define BCM6318_RST_PCIE_HARD 9 +#define BCM6318_RST_ADSL 10 +#define BCM6318_RST_PHYMIPS 11 +#define BCM6318_RST_HOSTMIPS 11 + +#endif /* __DT_BINDINGS_RESET_BCM6318_H */ diff --git a/roms/u-boot/include/dt-bindings/reset/bcm63268-reset.h b/roms/u-boot/include/dt-bindings/reset/bcm63268-reset.h new file mode 100644 index 000000000..a45abed1c --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/bcm63268-reset.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_RESET_BCM63268_H +#define __DT_BINDINGS_RESET_BCM63268_H + +#define BCM63268_RST_SPI 0 +#define BCM63268_RST_IPSEC 1 +#define BCM63268_RST_EPHY 2 +#define BCM63268_RST_SAR 3 +#define BCM63268_RST_ENETSW 4 +#define BCM63268_RST_USBS 5 +#define BCM63268_RST_USBH 6 +#define BCM63268_RST_PCM 7 +#define BCM63268_RST_PCIE_CORE 8 +#define BCM63268_RST_PCIE 9 +#define BCM63268_RST_PCIE_EXT 10 +#define BCM63268_RST_WLAN_SHIM 11 +#define BCM63268_RST_DDR_PHY 12 +#define BCM63268_RST_FAP0 13 +#define BCM63268_RST_WLAN_UBUS 14 +#define BCM63268_RST_DECT 15 +#define BCM63268_RST_FAP1 16 +#define BCM63268_RST_PCIE_HARD 17 +#define BCM63268_RST_GPHY 18 + +#endif /* __DT_BINDINGS_RESET_BCM63268_H */ diff --git a/roms/u-boot/include/dt-bindings/reset/bcm6328-reset.h b/roms/u-boot/include/dt-bindings/reset/bcm6328-reset.h new file mode 100644 index 000000000..f2dd4f79c --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/bcm6328-reset.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_RESET_BCM6328_H +#define __DT_BINDINGS_RESET_BCM6328_H + +#define BCM6328_RST_SPI 0 +#define BCM6328_RST_EPHY 1 +#define BCM6328_RST_SAR 2 +#define BCM6328_RST_ENETSW 3 +#define BCM6328_RST_USBS 4 +#define BCM6328_RST_USBH 5 +#define BCM6328_RST_PCM 6 +#define BCM6328_RST_PCIE_CORE 7 +#define BCM6328_RST_PCIE 8 +#define BCM6328_RST_PCIE_EXT 9 +#define BCM6328_RST_PCIE_HARD 10 + +#endif /* __DT_BINDINGS_RESET_BCM6328_H */ diff --git a/roms/u-boot/include/dt-bindings/reset/bcm6338-reset.h b/roms/u-boot/include/dt-bindings/reset/bcm6338-reset.h new file mode 100644 index 000000000..4aec7a4b5 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/bcm6338-reset.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_RESET_BCM6338_H +#define __DT_BINDINGS_RESET_BCM6338_H + +#define BCM6338_RST_SPI 0 +#define BCM6338_RST_ENET 2 +#define BCM6338_RST_USBH 3 +#define BCM6338_RST_USBS 4 +#define BCM6338_RST_ADSL 5 +#define BCM6338_RST_DMAMEM 6 +#define BCM6338_RST_SAR 7 +#define BCM6338_RST_ACLC 8 +#define BCM6338_RST_ADSL_MIPS 10 + +#endif /* __DT_BINDINGS_RESET_BCM6338_H */ diff --git a/roms/u-boot/include/dt-bindings/reset/bcm6348-reset.h b/roms/u-boot/include/dt-bindings/reset/bcm6348-reset.h new file mode 100644 index 000000000..b298c1831 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/bcm6348-reset.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_RESET_BCM6348_H +#define __DT_BINDINGS_RESET_BCM6348_H + +#define BCM6348_RST_SPI 0 +#define BCM6348_RST_ENET 2 +#define BCM6348_RST_USBH 3 +#define BCM6348_RST_USBS 4 +#define BCM6348_RST_ADSL 5 +#define BCM6348_RST_DMAMEM 6 +#define BCM6348_RST_SAR 7 +#define BCM6348_RST_ACLC 8 +#define BCM6348_RST_ADSL_MIPS 10 + +#endif /* __DT_BINDINGS_RESET_BCM6348_H */ diff --git a/roms/u-boot/include/dt-bindings/reset/bcm6358-reset.h b/roms/u-boot/include/dt-bindings/reset/bcm6358-reset.h new file mode 100644 index 000000000..075706eff --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/bcm6358-reset.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_RESET_BCM6358_H +#define __DT_BINDINGS_RESET_BCM6358_H + +#define BCM6358_RST_SPI 0 +#define BCM6358_RST_ENET 2 +#define BCM6358_RST_MPI 3 +#define BCM6358_RST_EPHY 6 +#define BCM6358_RST_SAR 7 +#define BCM6358_RST_USBH 12 +#define BCM6358_RST_PCM 13 +#define BCM6358_RST_ADSL 14 + +#endif /* __DT_BINDINGS_RESET_BCM6358_H */ diff --git a/roms/u-boot/include/dt-bindings/reset/bcm6362-reset.h b/roms/u-boot/include/dt-bindings/reset/bcm6362-reset.h new file mode 100644 index 000000000..8202e4991 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/bcm6362-reset.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_RESET_BCM6362_H +#define __DT_BINDINGS_RESET_BCM6362_H + +#define BCM6362_RST_SPI 0 +#define BCM6362_RST_IPSEC 1 +#define BCM6362_RST_EPHY 2 +#define BCM6362_RST_SAR 3 +#define BCM6362_RST_ENETSW 4 +#define BCM6362_RST_USBD 5 +#define BCM6362_RST_USBH 6 +#define BCM6362_RST_PCM 7 +#define BCM6362_RST_PCIE_CORE 8 +#define BCM6362_RST_PCIE 9 +#define BCM6362_RST_PCIE_EXT 10 +#define BCM6362_RST_WLAN_SHIM 11 +#define BCM6362_RST_DDR_PHY 12 +#define BCM6362_RST_FAP 13 +#define BCM6362_RST_WLAN_UBUS 14 + +#endif /* __DT_BINDINGS_RESET_BCM6362_H */ diff --git a/roms/u-boot/include/dt-bindings/reset/bcm6368-reset.h b/roms/u-boot/include/dt-bindings/reset/bcm6368-reset.h new file mode 100644 index 000000000..0038a7ccf --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/bcm6368-reset.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_RESET_BCM6368_H +#define __DT_BINDINGS_RESET_BCM6368_H + +#define BCM6368_RST_SPI 0 +#define BCM6368_RST_MPI 3 +#define BCM6368_RST_IPSEC 4 +#define BCM6368_RST_EPHY 6 +#define BCM6368_RST_SAR 7 +#define BCM6368_RST_SWITCH 10 +#define BCM6368_RST_USBD 11 +#define BCM6368_RST_USBH 12 +#define BCM6368_RST_PCM 13 + +#endif /* __DT_BINDINGS_RESET_BCM6368_H */ diff --git a/roms/u-boot/include/dt-bindings/reset/g12a-aoclkc.h b/roms/u-boot/include/dt-bindings/reset/g12a-aoclkc.h new file mode 100644 index 000000000..bd2e23371 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/g12a-aoclkc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK +#define DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK + +#define RESET_AO_IR_IN 0 +#define RESET_AO_UART 1 +#define RESET_AO_I2C_M 2 +#define RESET_AO_I2C_S 3 +#define RESET_AO_SAR_ADC 4 +#define RESET_AO_UART2 5 +#define RESET_AO_IR_OUT 6 + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/gxbb-aoclkc.h b/roms/u-boot/include/dt-bindings/reset/gxbb-aoclkc.h new file mode 100644 index 000000000..9e3fd60c3 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/gxbb-aoclkc.h @@ -0,0 +1,66 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + * The full GNU General Public License is included in this distribution + * in the file called COPYING. + * + * BSD LICENSE + * + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK +#define DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK + +#define RESET_AO_REMOTE 0 +#define RESET_AO_I2C_MASTER 1 +#define RESET_AO_I2C_SLAVE 2 +#define RESET_AO_UART1 3 +#define RESET_AO_UART2 4 +#define RESET_AO_IR_BLASTER 5 + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/imx7-reset.h b/roms/u-boot/include/dt-bindings/reset/imx7-reset.h new file mode 100644 index 000000000..bb92452ff --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/imx7-reset.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017 Impinj, Inc. + * + * Author: Andrey Smirnov + */ + +#ifndef DT_BINDING_RESET_IMX7_H +#define DT_BINDING_RESET_IMX7_H + +#define IMX7_RESET_A7_CORE_POR_RESET0 0 +#define IMX7_RESET_A7_CORE_POR_RESET1 1 +#define IMX7_RESET_A7_CORE_RESET0 2 +#define IMX7_RESET_A7_CORE_RESET1 3 +#define IMX7_RESET_A7_DBG_RESET0 4 +#define IMX7_RESET_A7_DBG_RESET1 5 +#define IMX7_RESET_A7_ETM_RESET0 6 +#define IMX7_RESET_A7_ETM_RESET1 7 +#define IMX7_RESET_A7_SOC_DBG_RESET 8 +#define IMX7_RESET_A7_L2RESET 9 +#define IMX7_RESET_SW_M4C_RST 10 +#define IMX7_RESET_SW_M4P_RST 11 +#define IMX7_RESET_EIM_RST 12 +#define IMX7_RESET_HSICPHY_PORT_RST 13 +#define IMX7_RESET_USBPHY1_POR 14 +#define IMX7_RESET_USBPHY1_PORT_RST 15 +#define IMX7_RESET_USBPHY2_POR 16 +#define IMX7_RESET_USBPHY2_PORT_RST 17 +#define IMX7_RESET_MIPI_PHY_MRST 18 +#define IMX7_RESET_MIPI_PHY_SRST 19 + +/* + * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN + * and PCIEPHY_G_RST + */ +#define IMX7_RESET_PCIEPHY 20 +#define IMX7_RESET_PCIEPHY_PERST 21 + +/* + * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it + * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht + * of as one + */ +#define IMX7_RESET_PCIE_CTRL_APPS_EN 22 +#define IMX7_RESET_DDRC_PRST 23 +#define IMX7_RESET_DDRC_CORE_RST 24 + +#define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25 + +#define IMX7_RESET_NUM 26 + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/imx8mq-reset.h b/roms/u-boot/include/dt-bindings/reset/imx8mq-reset.h new file mode 100755 index 000000000..9a301082d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/imx8mq-reset.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + * + * Author: Andrey Smirnov + */ + +#ifndef DT_BINDING_RESET_IMX8MQ_H +#define DT_BINDING_RESET_IMX8MQ_H + +#define IMX8MQ_RESET_A53_CORE_POR_RESET0 0 +#define IMX8MQ_RESET_A53_CORE_POR_RESET1 1 +#define IMX8MQ_RESET_A53_CORE_POR_RESET2 2 +#define IMX8MQ_RESET_A53_CORE_POR_RESET3 3 +#define IMX8MQ_RESET_A53_CORE_RESET0 4 +#define IMX8MQ_RESET_A53_CORE_RESET1 5 +#define IMX8MQ_RESET_A53_CORE_RESET2 6 +#define IMX8MQ_RESET_A53_CORE_RESET3 7 +#define IMX8MQ_RESET_A53_DBG_RESET0 8 +#define IMX8MQ_RESET_A53_DBG_RESET1 9 +#define IMX8MQ_RESET_A53_DBG_RESET2 10 +#define IMX8MQ_RESET_A53_DBG_RESET3 11 +#define IMX8MQ_RESET_A53_ETM_RESET0 12 +#define IMX8MQ_RESET_A53_ETM_RESET1 13 +#define IMX8MQ_RESET_A53_ETM_RESET2 14 +#define IMX8MQ_RESET_A53_ETM_RESET3 15 +#define IMX8MQ_RESET_A53_SOC_DBG_RESET 16 +#define IMX8MQ_RESET_A53_L2RESET 17 +#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18 +#define IMX8MQ_RESET_OTG1_PHY_RESET 19 +#define IMX8MQ_RESET_OTG2_PHY_RESET 20 +#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 +#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 +#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 +#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 +#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 +#define IMX8MQ_RESET_PCIEPHY 26 +#define IMX8MQ_RESET_PCIEPHY_PERST 27 +#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 +#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 +#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_DISP_RESET 31 +#define IMX8MQ_RESET_GPU_RESET 32 +#define IMX8MQ_RESET_VPU_RESET 33 +#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_DDRC1_PRST 44 +#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 +#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 +#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */ + +#define IMX8MQ_RESET_NUM 50 + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/k210-sysctl.h b/roms/u-boot/include/dt-bindings/reset/k210-sysctl.h new file mode 100644 index 000000000..12bb3880d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/k210-sysctl.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Sean Anderson + */ + +#ifndef RESET_K210_SYSCTL_H +#define RESET_K210_SYSCTL_H + +#define K210_RST_ROM 0 +#define K210_RST_DMA 1 +#define K210_RST_AI 2 +#define K210_RST_DVP 3 +#define K210_RST_FFT 4 +#define K210_RST_GPIO 5 +#define K210_RST_SPI0 6 +#define K210_RST_SPI1 7 +#define K210_RST_SPI2 8 +#define K210_RST_SPI3 9 +#define K210_RST_I2S0 10 +#define K210_RST_I2S1 11 +#define K210_RST_I2S2 12 +#define K210_RST_I2C0 13 +#define K210_RST_I2C1 14 +#define K210_RST_I2C2 15 +#define K210_RST_UART1 16 +#define K210_RST_UART2 17 +#define K210_RST_UART3 18 +#define K210_RST_AES 19 +#define K210_RST_FPIOA 20 +#define K210_RST_TIMER0 21 +#define K210_RST_TIMER1 22 +#define K210_RST_TIMER2 23 +#define K210_RST_WDT0 24 +#define K210_RST_WDT1 25 +#define K210_RST_SHA 26 +#define K210_RST_RTC 29 + +#endif /* RESET_K210_SYSCTL_H */ diff --git a/roms/u-boot/include/dt-bindings/reset/mt7620-reset.h b/roms/u-boot/include/dt-bindings/reset/mt7620-reset.h new file mode 100644 index 000000000..3096b29cd --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/mt7620-reset.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao + */ + +#ifndef _DT_BINDINGS_MT7620_RESET_H_ +#define _DT_BINDINGS_MT7620_RESET_H_ + +#define PPE_RST 31 +#define SDHC_RST 30 +#define MIPS_CNT_RST 28 +#define PCIE_RST 26 +#define UHST_RST 25 +#define EPHY_RST 24 +#define ESW_RST 23 +#define UDEV_RST 22 +#define FE_RST 21 +#define WLAN_RST 20 +#define UARTL_RST 19 +#define SPI_RST 18 +#define I2S_RST 17 +#define I2C_RST 16 +#define NAND_RST 15 +#define DMA_RST 14 +#define PIO_RST 13 +#define UARTF_RST 12 +#define PCM_RST 11 +#define MC_RST 10 +#define INTC_RST 9 +#define TIMER_RST 8 +#define SYS_RST 0 + +#endif /* _DT_BINDINGS_MT7620_RESET_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/mt7623-reset.h b/roms/u-boot/include/dt-bindings/reset/mt7623-reset.h new file mode 100644 index 000000000..a859a5b26 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/mt7623-reset.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_MTK_RESET_H_ +#define _DT_BINDINGS_MTK_RESET_H_ + +/* ETHSYS resets */ +#define ETHSYS_PPE_RST 31 +#define ETHSYS_GMAC_RST 23 +#define ETHSYS_FE_RST 6 +#define ETHSYS_MCM_RST 2 +#define ETHSYS_SYS_RST 0 + +/* HIFSYS resets */ +#define HIFSYS_PCIE2_RST 26 +#define HIFSYS_PCIE1_RST 25 +#define HIFSYS_PCIE0_RST 24 +#define HIFSYS_UPHY1_RST 22 +#define HIFSYS_UPHY0_RST 21 +#define HIFSYS_UHOST1_RST 4 +#define HIFSYS_UHOST0_RST 3 + +#endif /* _DT_BINDINGS_MTK_RESET_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/mt7628-reset.h b/roms/u-boot/include/dt-bindings/reset/mt7628-reset.h new file mode 100644 index 000000000..2a674c1ea --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/mt7628-reset.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * Author: Weijie Gao + */ + +#ifndef _DT_BINDINGS_MT7628_RESET_H_ +#define _DT_BINDINGS_MT7628_RESET_H_ + +#define MT7628_PWM_RST 31 +#define MT7628_SDXC_RST 30 +#define MT7628_CRYPTO_RST 29 +#define MT7628_AUX_STCK_RST 28 +#define MT7628_PCIE_RST 26 +#define MT7628_EPHY_RST 24 +#define MT7628_ETH_RST 23 +#define MT7628_UPHY_RST 22 +#define MT7628_UART2_RST 20 +#define MT7628_UART1_RST 19 +#define MT7628_SPI_RST 18 +#define MT7628_I2S_RST 17 +#define MT7628_I2C_RST 16 +#define MT7628_GDMA_RST 14 +#define MT7628_PIO_RST 13 +#define MT7628_UART0_RST 12 +#define MT7628_PCM_RST 11 +#define MT7628_MC_RST 10 +#define MT7628_INT_RST 9 +#define MT7628_TIMER_RST 8 +#define MT7628_HIF_RST 5 +#define MT7628_WIFI_RST 4 +#define MT7628_SPIS_RST 3 +#define MT7628_SYS_RST 0 + +#endif /* _DT_BINDINGS_MT7628_RESET_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/mt7629-reset.h b/roms/u-boot/include/dt-bindings/reset/mt7629-reset.h new file mode 100644 index 000000000..311a5cb3d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/mt7629-reset.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_MTK_RESET_H_ +#define _DT_BINDINGS_MTK_RESET_H_ + +/* PCIe/SATA Subsystem resets */ +#define MT7622_SATA_PHY_REG_RST 12 +#define MT7622_SATA_PHY_SW_RST 13 +#define MT7622_SATA_AXI_BUS_RST 15 +#define PCIE1_CORE_RST 19 +#define PCIE1_MMIO_RST 20 +#define PCIE1_HRST 21 +#define PCIE1_USER_RST 22 +#define PCIE1_PIPE_RST 23 +#define PCIE0_CORE_RST 27 +#define PCIE0_MMIO_RST 28 +#define PCIE0_HRST 29 +#define PCIE0_USER_RST 30 +#define PCIE0_PIPE_RST 31 + +/* SSUSB Subsystem resets */ +#define SSUSB_PHY_PWR_RST 3 +#define SSUSB_MAC_PWR_RST 4 + +/* ETH Subsystem resets */ +#define ETHSYS_SYS_RST 0 +#define ETHSYS_MCM_RST 2 +#define ETHSYS_HSDMA_RST 5 +#define ETHSYS_FE_RST 6 +#define ETHSYS_ESW_RST 16 +#define ETHSYS_GMAC_RST 23 +#define ETHSYS_EPHY_RST 24 +#define ETHSYS_CRYPTO_RST 29 +#define ETHSYS_PPE_RST 31 + +#endif /* _DT_BINDINGS_MTK_RESET_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/qcom,ipq4019-reset.h b/roms/u-boot/include/dt-bindings/reset/qcom,ipq4019-reset.h new file mode 100644 index 000000000..ed047d740 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/qcom,ipq4019-reset.h @@ -0,0 +1,92 @@ +/* Copyright (c) 2015 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +#ifndef __QCOM_RESET_IPQ4019_H__ +#define __QCOM_RESET_IPQ4019_H__ + +#define WIFI0_CPU_INIT_RESET 0 +#define WIFI0_RADIO_SRIF_RESET 1 +#define WIFI0_RADIO_WARM_RESET 2 +#define WIFI0_RADIO_COLD_RESET 3 +#define WIFI0_CORE_WARM_RESET 4 +#define WIFI0_CORE_COLD_RESET 5 +#define WIFI1_CPU_INIT_RESET 6 +#define WIFI1_RADIO_SRIF_RESET 7 +#define WIFI1_RADIO_WARM_RESET 8 +#define WIFI1_RADIO_COLD_RESET 9 +#define WIFI1_CORE_WARM_RESET 10 +#define WIFI1_CORE_COLD_RESET 11 +#define USB3_UNIPHY_PHY_ARES 12 +#define USB3_HSPHY_POR_ARES 13 +#define USB3_HSPHY_S_ARES 14 +#define USB2_HSPHY_POR_ARES 15 +#define USB2_HSPHY_S_ARES 16 +#define PCIE_PHY_AHB_ARES 17 +#define PCIE_AHB_ARES 18 +#define PCIE_PWR_ARES 19 +#define PCIE_PIPE_STICKY_ARES 20 +#define PCIE_AXI_M_STICKY_ARES 21 +#define PCIE_PHY_ARES 22 +#define PCIE_PARF_XPU_ARES 23 +#define PCIE_AXI_S_XPU_ARES 24 +#define PCIE_AXI_M_VMIDMT_ARES 25 +#define PCIE_PIPE_ARES 26 +#define PCIE_AXI_S_ARES 27 +#define PCIE_AXI_M_ARES 28 +#define ESS_RESET 29 +#define GCC_BLSP1_BCR 30 +#define GCC_BLSP1_QUP1_BCR 31 +#define GCC_BLSP1_UART1_BCR 32 +#define GCC_BLSP1_QUP2_BCR 33 +#define GCC_BLSP1_UART2_BCR 34 +#define GCC_BIMC_BCR 35 +#define GCC_TLMM_BCR 36 +#define GCC_IMEM_BCR 37 +#define GCC_ESS_BCR 38 +#define GCC_PRNG_BCR 39 +#define GCC_BOOT_ROM_BCR 40 +#define GCC_CRYPTO_BCR 41 +#define GCC_SDCC1_BCR 42 +#define GCC_SEC_CTRL_BCR 43 +#define GCC_AUDIO_BCR 44 +#define GCC_QPIC_BCR 45 +#define GCC_PCIE_BCR 46 +#define GCC_USB2_BCR 47 +#define GCC_USB2_PHY_BCR 48 +#define GCC_USB3_BCR 49 +#define GCC_USB3_PHY_BCR 50 +#define GCC_SYSTEM_NOC_BCR 51 +#define GCC_PCNOC_BCR 52 +#define GCC_DCD_BCR 53 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 54 +#define GCC_SNOC_BUS_TIMEOUT1_BCR 55 +#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 +#define GCC_SNOC_BUS_TIMEOUT3_BCR 57 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 +#define GCC_TCSR_BCR 68 +#define GCC_QDSS_BCR 69 +#define GCC_MPM_BCR 70 +#define GCC_SPDM_BCR 71 + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/raspberrypi,firmware-reset.h b/roms/u-boot/include/dt-bindings/reset/raspberrypi,firmware-reset.h new file mode 100644 index 000000000..1a4f4c792 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/raspberrypi,firmware-reset.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 Nicolas Saenz Julienne + * Author: Nicolas Saenz Julienne + */ + +#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H +#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H + +#define RASPBERRYPI_FIRMWARE_RESET_ID_USB 0 +#define RASPBERRYPI_FIRMWARE_RESET_NUM_IDS 1 + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/sifive-fu540-prci.h b/roms/u-boot/include/dt-bindings/reset/sifive-fu540-prci.h new file mode 100644 index 000000000..89aa5b667 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sifive-fu540-prci.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Sifive, Inc. + * Author: Sagar Kadam + */ + +#ifndef __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H +#define __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H + +/* Reset indexes for use by device tree data and the PRCI driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/sifive-fu740-prci.h b/roms/u-boot/include/dt-bindings/reset/sifive-fu740-prci.h new file mode 100644 index 000000000..02210f410 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sifive-fu740-prci.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2020-2021 Sifive, Inc. + * Author: Pragnesh Patel + */ + +#ifndef __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H +#define __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H + +/* Reset indexes for use by device tree data and the PRCI driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +#define PRCI_RST_PCIE_POWER_UP_N 4 +#define PRCI_RST_GEMGXL_N 5 +#define PRCI_RST_CLTX_N 6 + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/snps,hsdk-reset.h b/roms/u-boot/include/dt-bindings/reset/snps,hsdk-reset.h new file mode 100644 index 000000000..e1a643e4b --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/snps,hsdk-reset.h @@ -0,0 +1,17 @@ +/** + * This header provides index for the HSDK reset controller. + */ +#ifndef _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK +#define _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK + +#define HSDK_APB_RESET 0 +#define HSDK_AXI_RESET 1 +#define HSDK_ETH_RESET 2 +#define HSDK_USB_RESET 3 +#define HSDK_SDIO_RESET 4 +#define HSDK_HDMI_RESET 5 +#define HSDK_GFX_RESET 6 +#define HSDK_DMAC_RESET 7 +#define HSDK_EBI_RESET 8 + +#endif /*_DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK*/ diff --git a/roms/u-boot/include/dt-bindings/reset/stih407-resets.h b/roms/u-boot/include/dt-bindings/reset/stih407-resets.h new file mode 100644 index 000000000..4ab3a1c94 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/stih407-resets.h @@ -0,0 +1,65 @@ +/* + * This header provides constants for the reset controller + * based peripheral powerdown requests on the STMicroelectronics + * STiH407 SoC. + */ +#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407 +#define _DT_BINDINGS_RESET_CONTROLLER_STIH407 + +/* Powerdown requests control 0 */ +#define STIH407_EMISS_POWERDOWN 0 +#define STIH407_NAND_POWERDOWN 1 + +/* Synp GMAC PowerDown */ +#define STIH407_ETH1_POWERDOWN 2 + +/* Powerdown requests control 1 */ +#define STIH407_USB3_POWERDOWN 3 +#define STIH407_USB2_PORT1_POWERDOWN 4 +#define STIH407_USB2_PORT0_POWERDOWN 5 +#define STIH407_PCIE1_POWERDOWN 6 +#define STIH407_PCIE0_POWERDOWN 7 +#define STIH407_SATA1_POWERDOWN 8 +#define STIH407_SATA0_POWERDOWN 9 + +/* Reset defines */ +#define STIH407_ETH1_SOFTRESET 0 +#define STIH407_MMC1_SOFTRESET 1 +#define STIH407_PICOPHY_SOFTRESET 2 +#define STIH407_IRB_SOFTRESET 3 +#define STIH407_PCIE0_SOFTRESET 4 +#define STIH407_PCIE1_SOFTRESET 5 +#define STIH407_SATA0_SOFTRESET 6 +#define STIH407_SATA1_SOFTRESET 7 +#define STIH407_MIPHY0_SOFTRESET 8 +#define STIH407_MIPHY1_SOFTRESET 9 +#define STIH407_MIPHY2_SOFTRESET 10 +#define STIH407_SATA0_PWR_SOFTRESET 11 +#define STIH407_SATA1_PWR_SOFTRESET 12 +#define STIH407_DELTA_SOFTRESET 13 +#define STIH407_BLITTER_SOFTRESET 14 +#define STIH407_HDTVOUT_SOFTRESET 15 +#define STIH407_HDQVDP_SOFTRESET 16 +#define STIH407_VDP_AUX_SOFTRESET 17 +#define STIH407_COMPO_SOFTRESET 18 +#define STIH407_HDMI_TX_PHY_SOFTRESET 19 +#define STIH407_JPEG_DEC_SOFTRESET 20 +#define STIH407_VP8_DEC_SOFTRESET 21 +#define STIH407_GPU_SOFTRESET 22 +#define STIH407_HVA_SOFTRESET 23 +#define STIH407_ERAM_HVA_SOFTRESET 24 +#define STIH407_LPM_SOFTRESET 25 +#define STIH407_KEYSCAN_SOFTRESET 26 +#define STIH407_USB2_PORT0_SOFTRESET 27 +#define STIH407_USB2_PORT1_SOFTRESET 28 +#define STIH407_ST231_AUD_SOFTRESET 29 +#define STIH407_ST231_DMU_SOFTRESET 30 +#define STIH407_ST231_GP0_SOFTRESET 31 +#define STIH407_ST231_GP1_SOFTRESET 32 + +/* Picophy reset defines */ +#define STIH407_PICOPHY0_RESET 0 +#define STIH407_PICOPHY1_RESET 1 +#define STIH407_PICOPHY2_RESET 2 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */ diff --git a/roms/u-boot/include/dt-bindings/reset/stm32mp1-resets.h b/roms/u-boot/include/dt-bindings/reset/stm32mp1-resets.h new file mode 100644 index 000000000..702da37a2 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/stm32mp1-resets.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP1_RESET_H_ +#define _DT_BINDINGS_STM32MP1_RESET_H_ + +#define MCU_HOLD_BOOT_R 2144 +#define LTDC_R 3072 +#define DSI_R 3076 +#define DDRPERFM_R 3080 +#define USBPHY_R 3088 +#define SPI6_R 3136 +#define I2C4_R 3138 +#define I2C6_R 3139 +#define USART1_R 3140 +#define STGEN_R 3156 +#define GPIOZ_R 3200 +#define CRYP1_R 3204 +#define HASH1_R 3205 +#define RNG1_R 3206 +#define AXIM_R 3216 +#define GPU_R 3269 +#define ETHMAC_R 3274 +#define FMC_R 3276 +#define QSPI_R 3278 +#define SDMMC1_R 3280 +#define SDMMC2_R 3281 +#define CRC1_R 3284 +#define USBH_R 3288 +#define MDMA_R 3328 +#define MCU_R 8225 +#define TIM2_R 19456 +#define TIM3_R 19457 +#define TIM4_R 19458 +#define TIM5_R 19459 +#define TIM6_R 19460 +#define TIM7_R 19461 +#define TIM12_R 16462 +#define TIM13_R 16463 +#define TIM14_R 16464 +#define LPTIM1_R 19465 +#define SPI2_R 19467 +#define SPI3_R 19468 +#define USART2_R 19470 +#define USART3_R 19471 +#define UART4_R 19472 +#define UART5_R 19473 +#define UART7_R 19474 +#define UART8_R 19475 +#define I2C1_R 19477 +#define I2C2_R 19478 +#define I2C3_R 19479 +#define I2C5_R 19480 +#define SPDIF_R 19482 +#define CEC_R 19483 +#define DAC12_R 19485 +#define MDIO_R 19847 +#define TIM1_R 19520 +#define TIM8_R 19521 +#define TIM15_R 19522 +#define TIM16_R 19523 +#define TIM17_R 19524 +#define SPI1_R 19528 +#define SPI4_R 19529 +#define SPI5_R 19530 +#define USART6_R 19533 +#define SAI1_R 19536 +#define SAI2_R 19537 +#define SAI3_R 19538 +#define DFSDM_R 19540 +#define FDCAN_R 19544 +#define LPTIM2_R 19584 +#define LPTIM3_R 19585 +#define LPTIM4_R 19586 +#define LPTIM5_R 19587 +#define SAI4_R 19592 +#define SYSCFG_R 19595 +#define VREF_R 19597 +#define TMPSENS_R 19600 +#define PMBCTRL_R 19601 +#define DMA1_R 19648 +#define DMA2_R 19649 +#define DMAMUX_R 19650 +#define ADC12_R 19653 +#define USBO_R 19656 +#define SDMMC3_R 19664 +#define CAMITF_R 19712 +#define CRYP2_R 19716 +#define HASH2_R 19717 +#define RNG2_R 19718 +#define CRC2_R 19719 +#define HSEM_R 19723 +#define MBOX_R 19724 +#define GPIOA_R 19776 +#define GPIOB_R 19777 +#define GPIOC_R 19778 +#define GPIOD_R 19779 +#define GPIOE_R 19780 +#define GPIOF_R 19781 +#define GPIOG_R 19782 +#define GPIOH_R 19783 +#define GPIOI_R 19784 +#define GPIOJ_R 19785 +#define GPIOK_R 19786 + +#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun4i-a10-ccu.h b/roms/u-boot/include/dt-bindings/reset/sun4i-a10-ccu.h new file mode 100644 index 000000000..5f4480bed --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun4i-a10-ccu.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2017 Priit Laes + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN4I_A10_H +#define _DT_BINDINGS_RST_SUN4I_A10_H + +#define RST_USB_PHY0 1 +#define RST_USB_PHY1 2 +#define RST_USB_PHY2 3 +#define RST_GPS 4 +#define RST_DE_BE0 5 +#define RST_DE_BE1 6 +#define RST_DE_FE0 7 +#define RST_DE_FE1 8 +#define RST_DE_MP 9 +#define RST_TVE0 10 +#define RST_TCON0 11 +#define RST_TVE1 12 +#define RST_TCON1 13 +#define RST_CSI0 14 +#define RST_CSI1 15 +#define RST_VE 16 +#define RST_ACE 17 +#define RST_LVDS 18 +#define RST_GPU 19 +#define RST_HDMI_H 20 +#define RST_HDMI_SYS 21 +#define RST_HDMI_AUDIO_DMA 22 + +#endif /* DT_BINDINGS_RST_SUN4I_A10_H */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun50i-a64-ccu.h b/roms/u-boot/include/dt-bindings/reset/sun50i-a64-ccu.h new file mode 100644 index 000000000..db60b29dd --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun50i-a64-ccu.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2016 Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_ +#define _DT_BINDINGS_RST_SUN50I_A64_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_USB_HSIC 2 +#define RST_DRAM 3 +#define RST_MBUS 4 +#define RST_BUS_MIPI_DSI 5 +#define RST_BUS_CE 6 +#define RST_BUS_DMA 7 +#define RST_BUS_MMC0 8 +#define RST_BUS_MMC1 9 +#define RST_BUS_MMC2 10 +#define RST_BUS_NAND 11 +#define RST_BUS_DRAM 12 +#define RST_BUS_EMAC 13 +#define RST_BUS_TS 14 +#define RST_BUS_HSTIMER 15 +#define RST_BUS_SPI0 16 +#define RST_BUS_SPI1 17 +#define RST_BUS_OTG 18 +#define RST_BUS_EHCI0 19 +#define RST_BUS_EHCI1 20 +#define RST_BUS_OHCI0 21 +#define RST_BUS_OHCI1 22 +#define RST_BUS_VE 23 +#define RST_BUS_TCON0 24 +#define RST_BUS_TCON1 25 +#define RST_BUS_DEINTERLACE 26 +#define RST_BUS_CSI 27 +#define RST_BUS_HDMI0 28 +#define RST_BUS_HDMI1 29 +#define RST_BUS_DE 30 +#define RST_BUS_GPU 31 +#define RST_BUS_MSGBOX 32 +#define RST_BUS_SPINLOCK 33 +#define RST_BUS_DBG 34 +#define RST_BUS_LVDS 35 +#define RST_BUS_CODEC 36 +#define RST_BUS_SPDIF 37 +#define RST_BUS_THS 38 +#define RST_BUS_I2S0 39 +#define RST_BUS_I2S1 40 +#define RST_BUS_I2S2 41 +#define RST_BUS_I2C0 42 +#define RST_BUS_I2C1 43 +#define RST_BUS_I2C2 44 +#define RST_BUS_SCR 45 +#define RST_BUS_UART0 46 +#define RST_BUS_UART1 47 +#define RST_BUS_UART2 48 +#define RST_BUS_UART3 49 +#define RST_BUS_UART4 50 + +#endif /* _DT_BINDINGS_RST_SUN50I_A64_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun50i-h6-ccu.h b/roms/u-boot/include/dt-bindings/reset/sun50i-h6-ccu.h new file mode 100644 index 000000000..81106f455 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun50i-h6-ccu.h @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2017 Icenowy Zheng + */ + +#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_ +#define _DT_BINDINGS_RESET_SUN50I_H6_H_ + +#define RST_MBUS 0 +#define RST_BUS_DE 1 +#define RST_BUS_DEINTERLACE 2 +#define RST_BUS_GPU 3 +#define RST_BUS_CE 4 +#define RST_BUS_VE 5 +#define RST_BUS_EMCE 6 +#define RST_BUS_VP9 7 +#define RST_BUS_DMA 8 +#define RST_BUS_MSGBOX 9 +#define RST_BUS_SPINLOCK 10 +#define RST_BUS_HSTIMER 11 +#define RST_BUS_DBG 12 +#define RST_BUS_PSI 13 +#define RST_BUS_PWM 14 +#define RST_BUS_IOMMU 15 +#define RST_BUS_DRAM 16 +#define RST_BUS_NAND 17 +#define RST_BUS_MMC0 18 +#define RST_BUS_MMC1 19 +#define RST_BUS_MMC2 20 +#define RST_BUS_UART0 21 +#define RST_BUS_UART1 22 +#define RST_BUS_UART2 23 +#define RST_BUS_UART3 24 +#define RST_BUS_I2C0 25 +#define RST_BUS_I2C1 26 +#define RST_BUS_I2C2 27 +#define RST_BUS_I2C3 28 +#define RST_BUS_SCR0 29 +#define RST_BUS_SCR1 30 +#define RST_BUS_SPI0 31 +#define RST_BUS_SPI1 32 +#define RST_BUS_EMAC 33 +#define RST_BUS_TS 34 +#define RST_BUS_IR_TX 35 +#define RST_BUS_THS 36 +#define RST_BUS_I2S0 37 +#define RST_BUS_I2S1 38 +#define RST_BUS_I2S2 39 +#define RST_BUS_I2S3 40 +#define RST_BUS_SPDIF 41 +#define RST_BUS_DMIC 42 +#define RST_BUS_AUDIO_HUB 43 +#define RST_USB_PHY0 44 +#define RST_USB_PHY1 45 +#define RST_USB_PHY3 46 +#define RST_USB_HSIC 47 +#define RST_BUS_OHCI0 48 +#define RST_BUS_OHCI3 49 +#define RST_BUS_EHCI0 50 +#define RST_BUS_XHCI 51 +#define RST_BUS_EHCI3 52 +#define RST_BUS_OTG 53 +#define RST_BUS_PCIE 54 +#define RST_PCIE_POWERUP 55 +#define RST_BUS_HDMI 56 +#define RST_BUS_HDMI_SUB 57 +#define RST_BUS_TCON_TOP 58 +#define RST_BUS_TCON_LCD0 59 +#define RST_BUS_TCON_TV0 60 +#define RST_BUS_CSI 61 +#define RST_BUS_HDCP 62 + +#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/roms/u-boot/include/dt-bindings/reset/sun50i-h6-r-ccu.h new file mode 100644 index 000000000..7950e799c --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun50i-h6-r-ccu.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2016 Icenowy Zheng + */ + +#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ + +#define RST_R_APB1_TIMER 0 +#define RST_R_APB1_TWD 1 +#define RST_R_APB1_PWM 2 +#define RST_R_APB2_UART 3 +#define RST_R_APB2_I2C 4 +#define RST_R_APB1_IR 5 +#define RST_R_APB1_W1 6 +#define RST_R_APB2_RSB 7 + +#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun50i-h616-ccu.h b/roms/u-boot/include/dt-bindings/reset/sun50i-h616-ccu.h new file mode 100644 index 000000000..cb6285a8d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun50i-h616-ccu.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2020 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_RESET_SUN50I_H616_H_ +#define _DT_BINDINGS_RESET_SUN50I_H616_H_ + +#define RST_MBUS 0 +#define RST_BUS_DE 1 +#define RST_BUS_DEINTERLACE 2 +#define RST_BUS_GPU 3 +#define RST_BUS_CE 4 +#define RST_BUS_VE 5 +#define RST_BUS_DMA 6 +#define RST_BUS_HSTIMER 7 +#define RST_BUS_DBG 8 +#define RST_BUS_PSI 9 +#define RST_BUS_PWM 10 +#define RST_BUS_IOMMU 11 +#define RST_BUS_DRAM 12 +#define RST_BUS_NAND 13 +#define RST_BUS_MMC0 14 +#define RST_BUS_MMC1 15 +#define RST_BUS_MMC2 16 +#define RST_BUS_UART0 17 +#define RST_BUS_UART1 18 +#define RST_BUS_UART2 19 +#define RST_BUS_UART3 20 +#define RST_BUS_UART4 21 +#define RST_BUS_UART5 22 +#define RST_BUS_I2C0 23 +#define RST_BUS_I2C1 24 +#define RST_BUS_I2C2 25 +#define RST_BUS_I2C3 26 +#define RST_BUS_I2C4 27 +#define RST_BUS_SPI0 28 +#define RST_BUS_SPI1 29 +#define RST_BUS_EMAC0 30 +#define RST_BUS_EMAC1 31 +#define RST_BUS_TS 32 +#define RST_BUS_THS 33 +#define RST_BUS_SPDIF 34 +#define RST_BUS_DMIC 35 +#define RST_BUS_AUDIO_CODEC 36 +#define RST_BUS_AUDIO_HUB 37 +#define RST_USB_PHY0 38 +#define RST_USB_PHY1 39 +#define RST_USB_PHY2 40 +#define RST_USB_PHY3 41 +#define RST_BUS_OHCI0 42 +#define RST_BUS_OHCI1 43 +#define RST_BUS_OHCI2 44 +#define RST_BUS_OHCI3 45 +#define RST_BUS_EHCI0 46 +#define RST_BUS_EHCI1 47 +#define RST_BUS_EHCI2 48 +#define RST_BUS_EHCI3 49 +#define RST_BUS_OTG 50 +#define RST_BUS_HDMI 51 +#define RST_BUS_HDMI_SUB 52 +#define RST_BUS_TCON_TOP 53 +#define RST_BUS_TCON_TV0 54 +#define RST_BUS_TCON_TV1 55 +#define RST_BUS_TVE_TOP 56 +#define RST_BUS_TVE0 57 +#define RST_BUS_HDCP 58 +#define RST_BUS_KEYADC 59 + +#endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun5i-ccu.h b/roms/u-boot/include/dt-bindings/reset/sun5i-ccu.h new file mode 100644 index 000000000..c2b9726b5 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun5i-ccu.h @@ -0,0 +1,32 @@ +/* + * Copyright 2016 Maxime Ripard + * + * Maxime Ripard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _RST_SUN5I_H_ +#define _RST_SUN5I_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_GPS 2 +#define RST_DE_BE 3 +#define RST_DE_FE 4 +#define RST_TVE 5 +#define RST_LCD 6 +#define RST_CSI 7 +#define RST_VE 8 +#define RST_GPU 9 +#define RST_IEP 10 + +#endif /* _RST_SUN5I_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun6i-a31-ccu.h b/roms/u-boot/include/dt-bindings/reset/sun6i-a31-ccu.h new file mode 100644 index 000000000..fbff365ed --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun6i-a31-ccu.h @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN6I_A31_H_ +#define _DT_BINDINGS_RST_SUN6I_A31_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_USB_PHY2 2 + +#define RST_AHB1_MIPI_DSI 3 +#define RST_AHB1_SS 4 +#define RST_AHB1_DMA 5 +#define RST_AHB1_MMC0 6 +#define RST_AHB1_MMC1 7 +#define RST_AHB1_MMC2 8 +#define RST_AHB1_MMC3 9 +#define RST_AHB1_NAND1 10 +#define RST_AHB1_NAND0 11 +#define RST_AHB1_SDRAM 12 +#define RST_AHB1_EMAC 13 +#define RST_AHB1_TS 14 +#define RST_AHB1_HSTIMER 15 +#define RST_AHB1_SPI0 16 +#define RST_AHB1_SPI1 17 +#define RST_AHB1_SPI2 18 +#define RST_AHB1_SPI3 19 +#define RST_AHB1_OTG 20 +#define RST_AHB1_EHCI0 21 +#define RST_AHB1_EHCI1 22 +#define RST_AHB1_OHCI0 23 +#define RST_AHB1_OHCI1 24 +#define RST_AHB1_OHCI2 25 +#define RST_AHB1_VE 26 +#define RST_AHB1_LCD0 27 +#define RST_AHB1_LCD1 28 +#define RST_AHB1_CSI 29 +#define RST_AHB1_HDMI 30 +#define RST_AHB1_BE0 31 +#define RST_AHB1_BE1 32 +#define RST_AHB1_FE0 33 +#define RST_AHB1_FE1 34 +#define RST_AHB1_MP 35 +#define RST_AHB1_GPU 36 +#define RST_AHB1_DEU0 37 +#define RST_AHB1_DEU1 38 +#define RST_AHB1_DRC0 39 +#define RST_AHB1_DRC1 40 +#define RST_AHB1_LVDS 41 + +#define RST_APB1_CODEC 42 +#define RST_APB1_SPDIF 43 +#define RST_APB1_DIGITAL_MIC 44 +#define RST_APB1_DAUDIO0 45 +#define RST_APB1_DAUDIO1 46 +#define RST_APB2_I2C0 47 +#define RST_APB2_I2C1 48 +#define RST_APB2_I2C2 49 +#define RST_APB2_I2C3 50 +#define RST_APB2_UART0 51 +#define RST_APB2_UART1 52 +#define RST_APB2_UART2 53 +#define RST_APB2_UART3 54 +#define RST_APB2_UART4 55 +#define RST_APB2_UART5 56 + +#endif /* _DT_BINDINGS_RST_SUN6I_A31_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun8i-a23-a33-ccu.h b/roms/u-boot/include/dt-bindings/reset/sun8i-a23-a33-ccu.h new file mode 100644 index 000000000..6121f2b0c --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun8i-a23-a33-ccu.h @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2016 Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN8I_A23_A33_H_ +#define _DT_BINDINGS_RST_SUN8I_A23_A33_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_USB_HSIC 2 +#define RST_MBUS 3 +#define RST_BUS_MIPI_DSI 4 +#define RST_BUS_SS 5 +#define RST_BUS_DMA 6 +#define RST_BUS_MMC0 7 +#define RST_BUS_MMC1 8 +#define RST_BUS_MMC2 9 +#define RST_BUS_NAND 10 +#define RST_BUS_DRAM 11 +#define RST_BUS_HSTIMER 12 +#define RST_BUS_SPI0 13 +#define RST_BUS_SPI1 14 +#define RST_BUS_OTG 15 +#define RST_BUS_EHCI 16 +#define RST_BUS_OHCI 17 +#define RST_BUS_VE 18 +#define RST_BUS_LCD 19 +#define RST_BUS_CSI 20 +#define RST_BUS_DE_BE 21 +#define RST_BUS_DE_FE 22 +#define RST_BUS_GPU 23 +#define RST_BUS_MSGBOX 24 +#define RST_BUS_SPINLOCK 25 +#define RST_BUS_DRC 26 +#define RST_BUS_SAT 27 +#define RST_BUS_LVDS 28 +#define RST_BUS_CODEC 29 +#define RST_BUS_I2S0 30 +#define RST_BUS_I2S1 31 +#define RST_BUS_I2C0 32 +#define RST_BUS_I2C1 33 +#define RST_BUS_I2C2 34 +#define RST_BUS_UART0 35 +#define RST_BUS_UART1 36 +#define RST_BUS_UART2 37 +#define RST_BUS_UART3 38 +#define RST_BUS_UART4 39 + +#endif /* _DT_BINDINGS_RST_SUN8I_A23_A33_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun8i-a83t-ccu.h b/roms/u-boot/include/dt-bindings/reset/sun8i-a83t-ccu.h new file mode 100644 index 000000000..784f6e116 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun8i-a83t-ccu.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2017 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ +#define _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_USB_HSIC 2 + +#define RST_DRAM 3 +#define RST_MBUS 4 + +#define RST_BUS_MIPI_DSI 5 +#define RST_BUS_SS 6 +#define RST_BUS_DMA 7 +#define RST_BUS_MMC0 8 +#define RST_BUS_MMC1 9 +#define RST_BUS_MMC2 10 +#define RST_BUS_NAND 11 +#define RST_BUS_DRAM 12 +#define RST_BUS_EMAC 13 +#define RST_BUS_HSTIMER 14 +#define RST_BUS_SPI0 15 +#define RST_BUS_SPI1 16 +#define RST_BUS_OTG 17 +#define RST_BUS_EHCI0 18 +#define RST_BUS_EHCI1 19 +#define RST_BUS_OHCI0 20 + +#define RST_BUS_VE 21 +#define RST_BUS_TCON0 22 +#define RST_BUS_TCON1 23 +#define RST_BUS_CSI 24 +#define RST_BUS_HDMI0 25 +#define RST_BUS_HDMI1 26 +#define RST_BUS_DE 27 +#define RST_BUS_GPU 28 +#define RST_BUS_MSGBOX 29 +#define RST_BUS_SPINLOCK 30 + +#define RST_BUS_LVDS 31 + +#define RST_BUS_SPDIF 32 +#define RST_BUS_I2S0 33 +#define RST_BUS_I2S1 34 +#define RST_BUS_I2S2 35 +#define RST_BUS_TDM 36 + +#define RST_BUS_I2C0 37 +#define RST_BUS_I2C1 38 +#define RST_BUS_I2C2 39 +#define RST_BUS_UART0 40 +#define RST_BUS_UART1 41 +#define RST_BUS_UART2 42 +#define RST_BUS_UART3 43 +#define RST_BUS_UART4 44 + +#endif /* _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun8i-de2.h b/roms/u-boot/include/dt-bindings/reset/sun8i-de2.h new file mode 100644 index 000000000..1c36a6ac8 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun8i-de2.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2016 Icenowy Zheng + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#ifndef _DT_BINDINGS_RESET_SUN8I_DE2_H_ +#define _DT_BINDINGS_RESET_SUN8I_DE2_H_ + +#define RST_MIXER0 0 +#define RST_MIXER1 1 +#define RST_WB 2 +#define RST_ROT 3 + +#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun8i-h3-ccu.h b/roms/u-boot/include/dt-bindings/reset/sun8i-h3-ccu.h new file mode 100644 index 000000000..484c2a229 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun8i-h3-ccu.h @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2016 Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN8I_H3_H_ +#define _DT_BINDINGS_RST_SUN8I_H3_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_USB_PHY2 2 +#define RST_USB_PHY3 3 + +#define RST_MBUS 4 + +#define RST_BUS_CE 5 +#define RST_BUS_DMA 6 +#define RST_BUS_MMC0 7 +#define RST_BUS_MMC1 8 +#define RST_BUS_MMC2 9 +#define RST_BUS_NAND 10 +#define RST_BUS_DRAM 11 +#define RST_BUS_EMAC 12 +#define RST_BUS_TS 13 +#define RST_BUS_HSTIMER 14 +#define RST_BUS_SPI0 15 +#define RST_BUS_SPI1 16 +#define RST_BUS_OTG 17 +#define RST_BUS_EHCI0 18 +#define RST_BUS_EHCI1 19 +#define RST_BUS_EHCI2 20 +#define RST_BUS_EHCI3 21 +#define RST_BUS_OHCI0 22 +#define RST_BUS_OHCI1 23 +#define RST_BUS_OHCI2 24 +#define RST_BUS_OHCI3 25 +#define RST_BUS_VE 26 +#define RST_BUS_TCON0 27 +#define RST_BUS_TCON1 28 +#define RST_BUS_DEINTERLACE 29 +#define RST_BUS_CSI 30 +#define RST_BUS_TVE 31 +#define RST_BUS_HDMI0 32 +#define RST_BUS_HDMI1 33 +#define RST_BUS_DE 34 +#define RST_BUS_GPU 35 +#define RST_BUS_MSGBOX 36 +#define RST_BUS_SPINLOCK 37 +#define RST_BUS_DBG 38 +#define RST_BUS_EPHY 39 +#define RST_BUS_CODEC 40 +#define RST_BUS_SPDIF 41 +#define RST_BUS_THS 42 +#define RST_BUS_I2S0 43 +#define RST_BUS_I2S1 44 +#define RST_BUS_I2S2 45 +#define RST_BUS_I2C0 46 +#define RST_BUS_I2C1 47 +#define RST_BUS_I2C2 48 +#define RST_BUS_UART0 49 +#define RST_BUS_UART1 50 +#define RST_BUS_UART2 51 +#define RST_BUS_UART3 52 +#define RST_BUS_SCR0 53 + +/* New resets imported in H5 */ +#define RST_BUS_SCR1 54 + +#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun8i-r-ccu.h b/roms/u-boot/include/dt-bindings/reset/sun8i-r-ccu.h new file mode 100644 index 000000000..4ba64f3d6 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun8i-r-ccu.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2016 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_ + +#define RST_APB0_IR 0 +#define RST_APB0_TIMER 1 +#define RST_APB0_RSB 2 +#define RST_APB0_UART 3 +/* 4 is reserved for RST_APB0_W1 on A31 */ +#define RST_APB0_I2C 5 + +#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun8i-r40-ccu.h b/roms/u-boot/include/dt-bindings/reset/sun8i-r40-ccu.h new file mode 100644 index 000000000..c5ebcf667 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun8i-r40-ccu.h @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2017 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN8I_R40_H_ +#define _DT_BINDINGS_RST_SUN8I_R40_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_USB_PHY2 2 + +#define RST_DRAM 3 +#define RST_MBUS 4 + +#define RST_BUS_MIPI_DSI 5 +#define RST_BUS_CE 6 +#define RST_BUS_DMA 7 +#define RST_BUS_MMC0 8 +#define RST_BUS_MMC1 9 +#define RST_BUS_MMC2 10 +#define RST_BUS_MMC3 11 +#define RST_BUS_NAND 12 +#define RST_BUS_DRAM 13 +#define RST_BUS_EMAC 14 +#define RST_BUS_TS 15 +#define RST_BUS_HSTIMER 16 +#define RST_BUS_SPI0 17 +#define RST_BUS_SPI1 18 +#define RST_BUS_SPI2 19 +#define RST_BUS_SPI3 20 +#define RST_BUS_SATA 21 +#define RST_BUS_OTG 22 +#define RST_BUS_EHCI0 23 +#define RST_BUS_EHCI1 24 +#define RST_BUS_EHCI2 25 +#define RST_BUS_OHCI0 26 +#define RST_BUS_OHCI1 27 +#define RST_BUS_OHCI2 28 +#define RST_BUS_VE 29 +#define RST_BUS_MP 30 +#define RST_BUS_DEINTERLACE 31 +#define RST_BUS_CSI0 32 +#define RST_BUS_CSI1 33 +#define RST_BUS_HDMI0 34 +#define RST_BUS_HDMI1 35 +#define RST_BUS_DE 36 +#define RST_BUS_TVE0 37 +#define RST_BUS_TVE1 38 +#define RST_BUS_TVE_TOP 39 +#define RST_BUS_GMAC 40 +#define RST_BUS_GPU 41 +#define RST_BUS_TVD0 42 +#define RST_BUS_TVD1 43 +#define RST_BUS_TVD2 44 +#define RST_BUS_TVD3 45 +#define RST_BUS_TVD_TOP 46 +#define RST_BUS_TCON_LCD0 47 +#define RST_BUS_TCON_LCD1 48 +#define RST_BUS_TCON_TV0 49 +#define RST_BUS_TCON_TV1 50 +#define RST_BUS_TCON_TOP 51 +#define RST_BUS_DBG 52 +#define RST_BUS_LVDS 53 +#define RST_BUS_CODEC 54 +#define RST_BUS_SPDIF 55 +#define RST_BUS_AC97 56 +#define RST_BUS_IR0 57 +#define RST_BUS_IR1 58 +#define RST_BUS_THS 59 +#define RST_BUS_KEYPAD 60 +#define RST_BUS_I2S0 61 +#define RST_BUS_I2S1 62 +#define RST_BUS_I2S2 63 +#define RST_BUS_I2C0 64 +#define RST_BUS_I2C1 65 +#define RST_BUS_I2C2 66 +#define RST_BUS_I2C3 67 +#define RST_BUS_CAN 68 +#define RST_BUS_SCR 69 +#define RST_BUS_PS20 70 +#define RST_BUS_PS21 71 +#define RST_BUS_I2C4 72 +#define RST_BUS_UART0 73 +#define RST_BUS_UART1 74 +#define RST_BUS_UART2 75 +#define RST_BUS_UART3 76 +#define RST_BUS_UART4 77 +#define RST_BUS_UART5 78 +#define RST_BUS_UART6 79 +#define RST_BUS_UART7 80 + +#endif /* _DT_BINDINGS_RST_SUN8I_R40_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun8i-v3s-ccu.h b/roms/u-boot/include/dt-bindings/reset/sun8i-v3s-ccu.h new file mode 100644 index 000000000..b58ef21a2 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun8i-v3s-ccu.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2016 Icenowy Zheng + * + * Based on sun8i-v3s-ccu.h, which is + * Copyright (C) 2016 Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN8I_V3S_H_ +#define _DT_BINDINGS_RST_SUN8I_V3S_H_ + +#define RST_USB_PHY0 0 + +#define RST_MBUS 1 + +#define RST_BUS_CE 5 +#define RST_BUS_DMA 6 +#define RST_BUS_MMC0 7 +#define RST_BUS_MMC1 8 +#define RST_BUS_MMC2 9 +#define RST_BUS_DRAM 11 +#define RST_BUS_EMAC 12 +#define RST_BUS_HSTIMER 14 +#define RST_BUS_SPI0 15 +#define RST_BUS_OTG 17 +#define RST_BUS_EHCI0 18 +#define RST_BUS_OHCI0 22 +#define RST_BUS_VE 26 +#define RST_BUS_TCON0 27 +#define RST_BUS_CSI 30 +#define RST_BUS_DE 34 +#define RST_BUS_DBG 38 +#define RST_BUS_EPHY 39 +#define RST_BUS_CODEC 40 +#define RST_BUS_I2C0 46 +#define RST_BUS_I2C1 47 +#define RST_BUS_UART0 49 +#define RST_BUS_UART1 50 +#define RST_BUS_UART2 51 + +#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun9i-a80-ccu.h b/roms/u-boot/include/dt-bindings/reset/sun9i-a80-ccu.h new file mode 100644 index 000000000..4b8df4b36 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun9i-a80-ccu.h @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ +#define _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ + +#define RST_BUS_FD 0 +#define RST_BUS_VE 1 +#define RST_BUS_GPU_CTRL 2 +#define RST_BUS_SS 3 +#define RST_BUS_MMC 4 +#define RST_BUS_NAND0 5 +#define RST_BUS_NAND1 6 +#define RST_BUS_SDRAM 7 +#define RST_BUS_SATA 8 +#define RST_BUS_TS 9 +#define RST_BUS_SPI0 10 +#define RST_BUS_SPI1 11 +#define RST_BUS_SPI2 12 +#define RST_BUS_SPI3 13 + +#define RST_BUS_OTG 14 +#define RST_BUS_OTG_PHY 15 +#define RST_BUS_MIPI_HSI 16 +#define RST_BUS_GMAC 17 +#define RST_BUS_MSGBOX 18 +#define RST_BUS_SPINLOCK 19 +#define RST_BUS_HSTIMER 20 +#define RST_BUS_DMA 21 + +#define RST_BUS_LCD0 22 +#define RST_BUS_LCD1 23 +#define RST_BUS_EDP 24 +#define RST_BUS_LVDS 25 +#define RST_BUS_CSI 26 +#define RST_BUS_HDMI0 27 +#define RST_BUS_HDMI1 28 +#define RST_BUS_DE 29 +#define RST_BUS_MP 30 +#define RST_BUS_GPU 31 +#define RST_BUS_MIPI_DSI 32 + +#define RST_BUS_SPDIF 33 +#define RST_BUS_AC97 34 +#define RST_BUS_I2S0 35 +#define RST_BUS_I2S1 36 +#define RST_BUS_LRADC 37 +#define RST_BUS_GPADC 38 +#define RST_BUS_CIR_TX 39 + +#define RST_BUS_I2C0 40 +#define RST_BUS_I2C1 41 +#define RST_BUS_I2C2 42 +#define RST_BUS_I2C3 43 +#define RST_BUS_I2C4 44 +#define RST_BUS_UART0 45 +#define RST_BUS_UART1 46 +#define RST_BUS_UART2 47 +#define RST_BUS_UART3 48 +#define RST_BUS_UART4 49 +#define RST_BUS_UART5 50 + +#endif /* _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun9i-a80-de.h b/roms/u-boot/include/dt-bindings/reset/sun9i-a80-de.h new file mode 100644 index 000000000..205072770 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun9i-a80-de.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ +#define _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ + +#define RST_FE0 0 +#define RST_FE1 1 +#define RST_FE2 2 +#define RST_DEU0 3 +#define RST_DEU1 4 +#define RST_BE0 5 +#define RST_BE1 6 +#define RST_BE2 7 +#define RST_DRC0 8 +#define RST_DRC1 9 +#define RST_MERGE 10 + +#endif /* _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/sun9i-a80-usb.h b/roms/u-boot/include/dt-bindings/reset/sun9i-a80-usb.h new file mode 100644 index 000000000..ee492864c --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/sun9i-a80-usb.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ +#define _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ + +#define RST_USB0_HCI 0 +#define RST_USB1_HCI 1 +#define RST_USB2_HCI 2 + +#define RST_USB0_PHY 3 +#define RST_USB1_HSIC 4 +#define RST_USB1_PHY 5 +#define RST_USB2_HSIC 6 +#define RST_USB2_PHY 7 + +#endif /* _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ */ diff --git a/roms/u-boot/include/dt-bindings/reset/tegra124-car.h b/roms/u-boot/include/dt-bindings/reset/tegra124-car.h new file mode 100644 index 000000000..070e4f6e7 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/tegra124-car.h @@ -0,0 +1,12 @@ +/* + * This header provides Tegra124-specific constants for binding + * nvidia,tegra124-car. + */ + +#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H +#define _DT_BINDINGS_RESET_TEGRA124_CAR_H + +#define TEGRA124_RESET(x) (6 * 32 + (x)) +#define TEGRA124_RST_DFLL_DVCO TEGRA124_RESET(0) + +#endif /* _DT_BINDINGS_RESET_TEGRA124_CAR_H */ diff --git a/roms/u-boot/include/dt-bindings/reset/tegra186-reset.h b/roms/u-boot/include/dt-bindings/reset/tegra186-reset.h new file mode 100644 index 000000000..7efec9200 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/tegra186-reset.h @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. + */ + +#ifndef _ABI_MACH_T186_RESET_T186_H_ +#define _ABI_MACH_T186_RESET_T186_H_ + +#define TEGRA186_RESET_ACTMON 0 +#define TEGRA186_RESET_AFI 1 +#define TEGRA186_RESET_CEC 2 +#define TEGRA186_RESET_CSITE 3 +#define TEGRA186_RESET_DP2 4 +#define TEGRA186_RESET_DPAUX 5 +#define TEGRA186_RESET_DSI 6 +#define TEGRA186_RESET_DSIB 7 +#define TEGRA186_RESET_DTV 8 +#define TEGRA186_RESET_DVFS 9 +#define TEGRA186_RESET_ENTROPY 10 +#define TEGRA186_RESET_EXTPERIPH1 11 +#define TEGRA186_RESET_EXTPERIPH2 12 +#define TEGRA186_RESET_EXTPERIPH3 13 +#define TEGRA186_RESET_GPU 14 +#define TEGRA186_RESET_HDA 15 +#define TEGRA186_RESET_HDA2CODEC_2X 16 +#define TEGRA186_RESET_HDA2HDMICODEC 17 +#define TEGRA186_RESET_HOST1X 18 +#define TEGRA186_RESET_I2C1 19 +#define TEGRA186_RESET_I2C2 20 +#define TEGRA186_RESET_I2C3 21 +#define TEGRA186_RESET_I2C4 22 +#define TEGRA186_RESET_I2C5 23 +#define TEGRA186_RESET_I2C6 24 +#define TEGRA186_RESET_ISP 25 +#define TEGRA186_RESET_KFUSE 26 +#define TEGRA186_RESET_LA 27 +#define TEGRA186_RESET_MIPI_CAL 28 +#define TEGRA186_RESET_PCIE 29 +#define TEGRA186_RESET_PCIEXCLK 30 +#define TEGRA186_RESET_SATA 31 +#define TEGRA186_RESET_SATACOLD 32 +#define TEGRA186_RESET_SDMMC1 33 +#define TEGRA186_RESET_SDMMC2 34 +#define TEGRA186_RESET_SDMMC3 35 +#define TEGRA186_RESET_SDMMC4 36 +#define TEGRA186_RESET_SE 37 +#define TEGRA186_RESET_SOC_THERM 38 +#define TEGRA186_RESET_SOR0 39 +#define TEGRA186_RESET_SPI1 40 +#define TEGRA186_RESET_SPI2 41 +#define TEGRA186_RESET_SPI3 42 +#define TEGRA186_RESET_SPI4 43 +#define TEGRA186_RESET_TMR 44 +#define TEGRA186_RESET_TRIG_SYS 45 +#define TEGRA186_RESET_TSEC 46 +#define TEGRA186_RESET_UARTA 47 +#define TEGRA186_RESET_UARTB 48 +#define TEGRA186_RESET_UARTC 49 +#define TEGRA186_RESET_UARTD 50 +#define TEGRA186_RESET_VI 51 +#define TEGRA186_RESET_VIC 52 +#define TEGRA186_RESET_XUSB_DEV 53 +#define TEGRA186_RESET_XUSB_HOST 54 +#define TEGRA186_RESET_XUSB_PADCTL 55 +#define TEGRA186_RESET_XUSB_SS 56 +#define TEGRA186_RESET_AON_APB 57 +#define TEGRA186_RESET_AXI_CBB 58 +#define TEGRA186_RESET_BPMP_APB 59 +#define TEGRA186_RESET_CAN1 60 +#define TEGRA186_RESET_CAN2 61 +#define TEGRA186_RESET_DMIC5 62 +#define TEGRA186_RESET_DSIC 63 +#define TEGRA186_RESET_DSID 64 +#define TEGRA186_RESET_EMC_EMC 65 +#define TEGRA186_RESET_EMC_MEM 66 +#define TEGRA186_RESET_EMCSB_EMC 67 +#define TEGRA186_RESET_EMCSB_MEM 68 +#define TEGRA186_RESET_EQOS 69 +#define TEGRA186_RESET_GPCDMA 70 +#define TEGRA186_RESET_GPIO_CTL0 71 +#define TEGRA186_RESET_GPIO_CTL1 72 +#define TEGRA186_RESET_GPIO_CTL2 73 +#define TEGRA186_RESET_GPIO_CTL3 74 +#define TEGRA186_RESET_GPIO_CTL4 75 +#define TEGRA186_RESET_GPIO_CTL5 76 +#define TEGRA186_RESET_I2C10 77 +#define TEGRA186_RESET_I2C12 78 +#define TEGRA186_RESET_I2C13 79 +#define TEGRA186_RESET_I2C14 80 +#define TEGRA186_RESET_I2C7 81 +#define TEGRA186_RESET_I2C8 82 +#define TEGRA186_RESET_I2C9 83 +#define TEGRA186_RESET_JTAG2AXI 84 +#define TEGRA186_RESET_MPHY_IOBIST 85 +#define TEGRA186_RESET_MPHY_L0_RX 86 +#define TEGRA186_RESET_MPHY_L0_TX 87 +#define TEGRA186_RESET_NVCSI 88 +#define TEGRA186_RESET_NVDISPLAY0_HEAD0 89 +#define TEGRA186_RESET_NVDISPLAY0_HEAD1 90 +#define TEGRA186_RESET_NVDISPLAY0_HEAD2 91 +#define TEGRA186_RESET_NVDISPLAY0_MISC 92 +#define TEGRA186_RESET_NVDISPLAY0_WGRP0 93 +#define TEGRA186_RESET_NVDISPLAY0_WGRP1 94 +#define TEGRA186_RESET_NVDISPLAY0_WGRP2 95 +#define TEGRA186_RESET_NVDISPLAY0_WGRP3 96 +#define TEGRA186_RESET_NVDISPLAY0_WGRP4 97 +#define TEGRA186_RESET_NVDISPLAY0_WGRP5 98 +#define TEGRA186_RESET_PWM1 99 +#define TEGRA186_RESET_PWM2 100 +#define TEGRA186_RESET_PWM3 101 +#define TEGRA186_RESET_PWM4 102 +#define TEGRA186_RESET_PWM5 103 +#define TEGRA186_RESET_PWM6 104 +#define TEGRA186_RESET_PWM7 105 +#define TEGRA186_RESET_PWM8 106 +#define TEGRA186_RESET_SCE_APB 107 +#define TEGRA186_RESET_SOR1 108 +#define TEGRA186_RESET_TACH 109 +#define TEGRA186_RESET_TSC 110 +#define TEGRA186_RESET_UARTF 111 +#define TEGRA186_RESET_UARTG 112 +#define TEGRA186_RESET_UFSHC 113 +#define TEGRA186_RESET_UFSHC_AXI_M 114 +#define TEGRA186_RESET_UPHY 115 +#define TEGRA186_RESET_ADSP 116 +#define TEGRA186_RESET_ADSPDBG 117 +#define TEGRA186_RESET_ADSPINTF 118 +#define TEGRA186_RESET_ADSPNEON 119 +#define TEGRA186_RESET_ADSPPERIPH 120 +#define TEGRA186_RESET_ADSPSCU 121 +#define TEGRA186_RESET_ADSPWDT 122 +#define TEGRA186_RESET_APE 123 +#define TEGRA186_RESET_DPAUX1 124 +#define TEGRA186_RESET_NVDEC 125 +#define TEGRA186_RESET_NVENC 126 +#define TEGRA186_RESET_NVJPG 127 +#define TEGRA186_RESET_PEX_USB_UPHY 128 +#define TEGRA186_RESET_QSPI 129 +#define TEGRA186_RESET_TSECB 130 +#define TEGRA186_RESET_VI_I2C 131 +#define TEGRA186_RESET_UARTE 132 +#define TEGRA186_RESET_TOP_GTE 133 +#define TEGRA186_RESET_SHSP 134 +#define TEGRA186_RESET_PEX_USB_UPHY_L5 135 +#define TEGRA186_RESET_PEX_USB_UPHY_L4 136 +#define TEGRA186_RESET_PEX_USB_UPHY_L3 137 +#define TEGRA186_RESET_PEX_USB_UPHY_L2 138 +#define TEGRA186_RESET_PEX_USB_UPHY_L1 139 +#define TEGRA186_RESET_PEX_USB_UPHY_L0 140 +#define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141 +#define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142 +#define TEGRA186_RESET_TSCTNVI 143 +#define TEGRA186_RESET_EXTPERIPH4 144 +#define TEGRA186_RESET_DSIPADCTL 145 +#define TEGRA186_RESET_AUD_MCLK 146 +#define TEGRA186_RESET_MPHY_CLK_CTL 147 +#define TEGRA186_RESET_MPHY_L1_RX 148 +#define TEGRA186_RESET_MPHY_L1_TX 149 +#define TEGRA186_RESET_UFSHC_LP 150 +#define TEGRA186_RESET_BPMP_NIC 151 +#define TEGRA186_RESET_BPMP_NSYSPORESET 152 +#define TEGRA186_RESET_BPMP_NRESET 153 +#define TEGRA186_RESET_BPMP_DBGRESETN 154 +#define TEGRA186_RESET_BPMP_PRESETDBGN 155 +#define TEGRA186_RESET_BPMP_PM 156 +#define TEGRA186_RESET_BPMP_CVC 157 +#define TEGRA186_RESET_BPMP_DMA 158 +#define TEGRA186_RESET_BPMP_HSP 159 +#define TEGRA186_RESET_TSCTNBPMP 160 +#define TEGRA186_RESET_BPMP_TKE 161 +#define TEGRA186_RESET_BPMP_GTE 162 +#define TEGRA186_RESET_BPMP_PM_ACTMON 163 +#define TEGRA186_RESET_AON_NIC 164 +#define TEGRA186_RESET_AON_NSYSPORESET 165 +#define TEGRA186_RESET_AON_NRESET 166 +#define TEGRA186_RESET_AON_DBGRESETN 167 +#define TEGRA186_RESET_AON_PRESETDBGN 168 +#define TEGRA186_RESET_AON_ACTMON 169 +#define TEGRA186_RESET_AOPM 170 +#define TEGRA186_RESET_AOVC 171 +#define TEGRA186_RESET_AON_DMA 172 +#define TEGRA186_RESET_AON_GPIO 173 +#define TEGRA186_RESET_AON_HSP 174 +#define TEGRA186_RESET_TSCTNAON 175 +#define TEGRA186_RESET_AON_TKE 176 +#define TEGRA186_RESET_AON_GTE 177 +#define TEGRA186_RESET_SCE_NIC 178 +#define TEGRA186_RESET_SCE_NSYSPORESET 179 +#define TEGRA186_RESET_SCE_NRESET 180 +#define TEGRA186_RESET_SCE_DBGRESETN 181 +#define TEGRA186_RESET_SCE_PRESETDBGN 182 +#define TEGRA186_RESET_SCE_ACTMON 183 +#define TEGRA186_RESET_SCE_PM 184 +#define TEGRA186_RESET_SCE_DMA 185 +#define TEGRA186_RESET_SCE_HSP 186 +#define TEGRA186_RESET_TSCTNSCE 187 +#define TEGRA186_RESET_SCE_TKE 188 +#define TEGRA186_RESET_SCE_GTE 189 +#define TEGRA186_RESET_SCE_CFG 190 +#define TEGRA186_RESET_ADSP_ALL 191 +/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */ +#define TEGRA186_RESET_UFSHC_LP_SEQ 192 +#define TEGRA186_RESET_SIZE 193 + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/ti-syscon.h b/roms/u-boot/include/dt-bindings/reset/ti-syscon.h new file mode 100644 index 000000000..884fd91df --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/ti-syscon.h @@ -0,0 +1,38 @@ +/* + * TI Syscon Reset definitions + * + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__ +#define __DT_BINDINGS_RESET_TI_SYSCON_H__ + +/* + * The reset does not support the feature and corresponding + * values are not valid + */ +#define ASSERT_NONE (1 << 0) +#define DEASSERT_NONE (1 << 1) +#define STATUS_NONE (1 << 2) + +/* When set this function is activated by setting(vs clearing) this bit */ +#define ASSERT_SET (1 << 3) +#define DEASSERT_SET (1 << 4) +#define STATUS_SET (1 << 5) + +/* The following are the inverse of the above and are added for consistency */ +#define ASSERT_CLEAR (0 << 3) +#define DEASSERT_CLEAR (0 << 4) +#define STATUS_CLEAR (0 << 5) + +#endif diff --git a/roms/u-boot/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/roms/u-boot/include/dt-bindings/reset/xlnx-zynqmp-resets.h new file mode 100644 index 000000000..d44525b9f --- /dev/null +++ b/roms/u-boot/include/dt-bindings/reset/xlnx-zynqmp-resets.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H +#define _DT_BINDINGS_ZYNQMP_RESETS_H + +#define ZYNQMP_RESET_PCIE_CFG 0 +#define ZYNQMP_RESET_PCIE_BRIDGE 1 +#define ZYNQMP_RESET_PCIE_CTRL 2 +#define ZYNQMP_RESET_DP 3 +#define ZYNQMP_RESET_SWDT_CRF 4 +#define ZYNQMP_RESET_AFI_FM5 5 +#define ZYNQMP_RESET_AFI_FM4 6 +#define ZYNQMP_RESET_AFI_FM3 7 +#define ZYNQMP_RESET_AFI_FM2 8 +#define ZYNQMP_RESET_AFI_FM1 9 +#define ZYNQMP_RESET_AFI_FM0 10 +#define ZYNQMP_RESET_GDMA 11 +#define ZYNQMP_RESET_GPU_PP1 12 +#define ZYNQMP_RESET_GPU_PP0 13 +#define ZYNQMP_RESET_GPU 14 +#define ZYNQMP_RESET_GT 15 +#define ZYNQMP_RESET_SATA 16 +#define ZYNQMP_RESET_ACPU3_PWRON 17 +#define ZYNQMP_RESET_ACPU2_PWRON 18 +#define ZYNQMP_RESET_ACPU1_PWRON 19 +#define ZYNQMP_RESET_ACPU0_PWRON 20 +#define ZYNQMP_RESET_APU_L2 21 +#define ZYNQMP_RESET_ACPU3 22 +#define ZYNQMP_RESET_ACPU2 23 +#define ZYNQMP_RESET_ACPU1 24 +#define ZYNQMP_RESET_ACPU0 25 +#define ZYNQMP_RESET_DDR 26 +#define ZYNQMP_RESET_APM_FPD 27 +#define ZYNQMP_RESET_SOFT 28 +#define ZYNQMP_RESET_GEM0 29 +#define ZYNQMP_RESET_GEM1 30 +#define ZYNQMP_RESET_GEM2 31 +#define ZYNQMP_RESET_GEM3 32 +#define ZYNQMP_RESET_QSPI 33 +#define ZYNQMP_RESET_UART0 34 +#define ZYNQMP_RESET_UART1 35 +#define ZYNQMP_RESET_SPI0 36 +#define ZYNQMP_RESET_SPI1 37 +#define ZYNQMP_RESET_SDIO0 38 +#define ZYNQMP_RESET_SDIO1 39 +#define ZYNQMP_RESET_CAN0 40 +#define ZYNQMP_RESET_CAN1 41 +#define ZYNQMP_RESET_I2C0 42 +#define ZYNQMP_RESET_I2C1 43 +#define ZYNQMP_RESET_TTC0 44 +#define ZYNQMP_RESET_TTC1 45 +#define ZYNQMP_RESET_TTC2 46 +#define ZYNQMP_RESET_TTC3 47 +#define ZYNQMP_RESET_SWDT_CRL 48 +#define ZYNQMP_RESET_NAND 49 +#define ZYNQMP_RESET_ADMA 50 +#define ZYNQMP_RESET_GPIO 51 +#define ZYNQMP_RESET_IOU_CC 52 +#define ZYNQMP_RESET_TIMESTAMP 53 +#define ZYNQMP_RESET_RPU_R50 54 +#define ZYNQMP_RESET_RPU_R51 55 +#define ZYNQMP_RESET_RPU_AMBA 56 +#define ZYNQMP_RESET_OCM 57 +#define ZYNQMP_RESET_RPU_PGE 58 +#define ZYNQMP_RESET_USB0_CORERESET 59 +#define ZYNQMP_RESET_USB1_CORERESET 60 +#define ZYNQMP_RESET_USB0_HIBERRESET 61 +#define ZYNQMP_RESET_USB1_HIBERRESET 62 +#define ZYNQMP_RESET_USB0_APB 63 +#define ZYNQMP_RESET_USB1_APB 64 +#define ZYNQMP_RESET_IPI 65 +#define ZYNQMP_RESET_APM_LPD 66 +#define ZYNQMP_RESET_RTC 67 +#define ZYNQMP_RESET_SYSMON 68 +#define ZYNQMP_RESET_AFI_FM6 69 +#define ZYNQMP_RESET_LPD_SWDT 70 +#define ZYNQMP_RESET_FPD 71 +#define ZYNQMP_RESET_RPU_DBG1 72 +#define ZYNQMP_RESET_RPU_DBG0 73 +#define ZYNQMP_RESET_DBG_LPD 74 +#define ZYNQMP_RESET_DBG_FPD 75 +#define ZYNQMP_RESET_APLL 76 +#define ZYNQMP_RESET_DPLL 77 +#define ZYNQMP_RESET_VPLL 78 +#define ZYNQMP_RESET_IOPLL 79 +#define ZYNQMP_RESET_RPLL 80 +#define ZYNQMP_RESET_GPO3_PL_0 81 +#define ZYNQMP_RESET_GPO3_PL_1 82 +#define ZYNQMP_RESET_GPO3_PL_2 83 +#define ZYNQMP_RESET_GPO3_PL_3 84 +#define ZYNQMP_RESET_GPO3_PL_4 85 +#define ZYNQMP_RESET_GPO3_PL_5 86 +#define ZYNQMP_RESET_GPO3_PL_6 87 +#define ZYNQMP_RESET_GPO3_PL_7 88 +#define ZYNQMP_RESET_GPO3_PL_8 89 +#define ZYNQMP_RESET_GPO3_PL_9 90 +#define ZYNQMP_RESET_GPO3_PL_10 91 +#define ZYNQMP_RESET_GPO3_PL_11 92 +#define ZYNQMP_RESET_GPO3_PL_12 93 +#define ZYNQMP_RESET_GPO3_PL_13 94 +#define ZYNQMP_RESET_GPO3_PL_14 95 +#define ZYNQMP_RESET_GPO3_PL_15 96 +#define ZYNQMP_RESET_GPO3_PL_16 97 +#define ZYNQMP_RESET_GPO3_PL_17 98 +#define ZYNQMP_RESET_GPO3_PL_18 99 +#define ZYNQMP_RESET_GPO3_PL_19 100 +#define ZYNQMP_RESET_GPO3_PL_20 101 +#define ZYNQMP_RESET_GPO3_PL_21 102 +#define ZYNQMP_RESET_GPO3_PL_22 103 +#define ZYNQMP_RESET_GPO3_PL_23 104 +#define ZYNQMP_RESET_GPO3_PL_24 105 +#define ZYNQMP_RESET_GPO3_PL_25 106 +#define ZYNQMP_RESET_GPO3_PL_26 107 +#define ZYNQMP_RESET_GPO3_PL_27 108 +#define ZYNQMP_RESET_GPO3_PL_28 109 +#define ZYNQMP_RESET_GPO3_PL_29 110 +#define ZYNQMP_RESET_GPO3_PL_30 111 +#define ZYNQMP_RESET_GPO3_PL_31 112 +#define ZYNQMP_RESET_RPU_LS 113 +#define ZYNQMP_RESET_PS_ONLY 114 +#define ZYNQMP_RESET_PL 115 +#define ZYNQMP_RESET_PS_PL0 116 +#define ZYNQMP_RESET_PS_PL1 117 +#define ZYNQMP_RESET_PS_PL2 118 +#define ZYNQMP_RESET_PS_PL3 119 + +#endif diff --git a/roms/u-boot/include/dt-bindings/soc/bcm2835-pm.h b/roms/u-boot/include/dt-bindings/soc/bcm2835-pm.h new file mode 100644 index 000000000..153d75b8d --- /dev/null +++ b/roms/u-boot/include/dt-bindings/soc/bcm2835-pm.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +#ifndef _DT_BINDINGS_ARM_BCM2835_PM_H +#define _DT_BINDINGS_ARM_BCM2835_PM_H + +#define BCM2835_POWER_DOMAIN_GRAFX 0 +#define BCM2835_POWER_DOMAIN_GRAFX_V3D 1 +#define BCM2835_POWER_DOMAIN_IMAGE 2 +#define BCM2835_POWER_DOMAIN_IMAGE_PERI 3 +#define BCM2835_POWER_DOMAIN_IMAGE_ISP 4 +#define BCM2835_POWER_DOMAIN_IMAGE_H264 5 +#define BCM2835_POWER_DOMAIN_USB 6 +#define BCM2835_POWER_DOMAIN_DSI0 7 +#define BCM2835_POWER_DOMAIN_DSI1 8 +#define BCM2835_POWER_DOMAIN_CAM0 9 +#define BCM2835_POWER_DOMAIN_CAM1 10 +#define BCM2835_POWER_DOMAIN_CCP2TX 11 +#define BCM2835_POWER_DOMAIN_HDMI 12 + +#define BCM2835_POWER_DOMAIN_COUNT 13 + +#define BCM2835_RESET_V3D 0 +#define BCM2835_RESET_ISP 1 +#define BCM2835_RESET_H264 2 + +#define BCM2835_RESET_COUNT 3 + +#endif /* _DT_BINDINGS_ARM_BCM2835_PM_H */ diff --git a/roms/u-boot/include/dt-bindings/soc/imx8_pd.h b/roms/u-boot/include/dt-bindings/soc/imx8_pd.h new file mode 100644 index 000000000..682b608ee --- /dev/null +++ b/roms/u-boot/include/dt-bindings/soc/imx8_pd.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __DT_BINDINGS_IMX8_PD_H +#define __DT_BINDINGS_IMX8_PD_H + +/*! + * These defines are used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ +#define PD_DC_0 dc0_power_domain +#define PD_DC_0_PLL_0 dc0_pll0 +#define PD_DC_0_PLL_1 dc0_pll1 +#define PD_LVDS0 lvds0_power_domain +#define PD_LVDS0_I2C0 lvds0_i2c0 +#define PD_LVDS0_I2C1 lvds0_i2c1 +#define PD_LVDS0_PWM lvds0_pwm +#define PD_LVDS0_PWM lvds0_pwm +#define PD_LVDS0_GPIO lvds0_gpio +#define PD_DC_1 dc1_power_domain +#define PD_DC_1_PLL_0 dc1_pll0 +#define PD_DC_1_PLL_1 dc1_pll1 +#define PD_LVDS1 lvds1_power_domain +#define PD_LVDS1_I2C0 lvds1_i2c0 +#define PD_LVDS1_I2C1 lvds1_i2c1 +#define PD_LVDS1_PWM lvds1_pwm +#define PD_LVDS1_GPIO lvds1_gpio + +#define PD_DMA dma_power_domain +#define PD_DMA_SPI_0 dma_spi0 +#define PD_DMA_SPI_1 dma_spi1 +#define PD_DMA_SPI_2 dma_spi2 +#define PD_DMA_SPI_3 dma_spi3 +#define PD_DMA_UART0 dma_lpuart0 +#define PD_DMA_UART1 dma_lpuart1 +#define PD_DMA_UART2 dma_lpuart2 +#define PD_DMA_UART3 dma_lpuart3 +#define PD_DMA_UART4 dma_lpuart4 +#define PD_DMA_EMVSIM_0 dma_emvsim0 +#define PD_DMA_EMVSIM_1 dma_emvsim1 +#define PD_DMA_I2C_0 dma_lpi2c0 +#define PD_DMA_I2C_1 dma_lpi2c1 +#define PD_DMA_I2C_2 dma_lpi2c2 +#define PD_DMA_I2C_3 dma_lpi2c3 +#define PD_DMA_I2C_4 dma_lpi2c4 +#define PD_DMA_ADC_0 dma_adc0 +#define PD_DMA_ADC_1 dma_adc1 +#define PD_DMA_FTM_0 dma_ftm0 +#define PD_DMA_FTM_1 dma_ftm1 +#define PD_DMA_CAN_0 dma_flexcan0 +#define PD_DMA_CAN_1 dma_flexcan1 +#define PD_DMA_CAN_2 dma_flexcan2 +#define PD_DMA_PWM_0 dma_pwm0 +#define PD_DMA_LCD_0 dma_lcd0 + +#define PD_HSIO hsio_power_domain +#define PD_HSIO_PCIE_A hsio_pcie0 +#define PD_HSIO_PCIE_B hsio_pcie1 +#define PD_HSIO_SATA_0 hsio_sata0 +#define PD_HSIO_GPIO hsio_gpio + +#define PD_LCD_0 lcd0_power_domain +#define PD_LCD_0_I2C_0 lcd0_i2c0 +#define PD_LCD_0_I2C_1 lcd0_i2c1 +#define PD_LCD_PWM_0 lcd0_pwm0 + +#define PD_LSIO lsio_power_domain +#define PD_LSIO_GPIO_0 lsio_gpio0 +#define PD_LSIO_GPIO_1 lsio_gpio1 +#define PD_LSIO_GPIO_2 lsio_gpio2 +#define PD_LSIO_GPIO_3 lsio_gpio3 +#define PD_LSIO_GPIO_4 lsio_gpio4 +#define PD_LSIO_GPIO_5 lsio_gpio5 +#define PD_LSIO_GPIO_6 lsio_gpio6 +#define PD_LSIO_GPIO_7 lsio_gpio7 +#define PD_LSIO_GPT_0 lsio_gpt0 +#define PD_LSIO_GPT_1 lsio_gpt1 +#define PD_LSIO_GPT_2 lsio_gpt2 +#define PD_LSIO_GPT_3 lsio_gpt3 +#define PD_LSIO_GPT_4 lsio_gpt4 +#define PD_LSIO_KPP lsio_kpp +#define PD_LSIO_FSPI_0 lsio_fspi0 +#define PD_LSIO_FSPI_1 lsio_fspi1 +#define PD_LSIO_PWM_0 lsio_pwm0 +#define PD_LSIO_PWM_1 lsio_pwm1 +#define PD_LSIO_PWM_2 lsio_pwm2 +#define PD_LSIO_PWM_3 lsio_pwm3 +#define PD_LSIO_PWM_4 lsio_pwm4 +#define PD_LSIO_PWM_5 lsio_pwm5 +#define PD_LSIO_PWM_6 lsio_pwm6 +#define PD_LSIO_PWM_7 lsio_pwm7 + +#define PD_CONN connectivity_power_domain +#define PD_CONN_SDHC_0 conn_sdhc0 +#define PD_CONN_SDHC_1 conn_sdhc1 +#define PD_CONN_SDHC_2 conn_sdhc2 +#define PD_CONN_ENET_0 conn_enet0 +#define PD_CONN_ENET_1 conn_enet1 +#define PD_CONN_MLB_0 conn_mlb0 +#define PD_CONN_DMA_4_CH0 conn_dma4_ch0 +#define PD_CONN_DMA_4_CH1 conn_dma4_ch1 +#define PD_CONN_DMA_4_CH2 conn_dma4_ch2 +#define PD_CONN_DMA_4_CH3 conn_dma4_ch3 +#define PD_CONN_DMA_4_CH4 conn_dma4_ch4 +#define PD_CONN_USB_0 conn_usb0 +#define PD_CONN_USB_1 conn_usb1 +#define PD_CONN_USB_0_PHY conn_usb0_phy +#define PD_CONN_USB_2 conn_usb2 +#define PD_CONN_USB_2_PHY conn_usb2_phy +#define PD_CONN_NAND conn_nand + +#define PD_AUDIO audio_power_domain +#define PD_AUD_SAI_0 audio_sai0 +#define PD_AUD_SAI_1 audio_sai1 +#define PD_AUD_SAI_2 audio_sai2 +#define PD_AUD_ASRC_0 audio_asrc0 +#define PD_AUD_ASRC_1 audio_asrc1 +#define PD_AUD_ESAI_0 audio_esai0 +#define PD_AUD_ESAI_1 audio_esai1 +#define PD_AUD_SPDIF_0 audio_spdif0 +#define PD_AUD_SPDIF_1 audio_spdif1 +#define PD_AUD_SAI_3 audio_sai3 +#define PD_AUD_SAI_4 audio_sai4 +#define PD_AUD_SAI_5 audio_sai5 +#define PD_AUD_SAI_6 audio_sai6 +#define PD_AUD_SAI_7 audio_sai7 +#define PD_AUD_GPT_5 audio_gpt5 +#define PD_AUD_GPT_6 audio_gpt6 +#define PD_AUD_GPT_7 audio_gpt7 +#define PD_AUD_GPT_8 audio_gpt8 +#define PD_AUD_GPT_9 audio_gpt9 +#define PD_AUD_GPT_10 audio_gpt10 +#define PD_AUD_AMIX audio_amix +#define PD_AUD_MQS_0 audio_mqs0 +#define PD_AUD_HIFI audio_hifi +#define PD_AUD_OCRAM audio_ocram +#define PD_AUD_MCLK_OUT_0 audio_mclkout0 +#define PD_AUD_MCLK_OUT_1 audio_mclkout1 +#define PD_AUD_AUDIO_PLL_0 audio_audiopll0 +#define PD_AUD_AUDIO_PLL_1 audio_audiopll1 +#define PD_AUD_AUDIO_CLK_0 audio_audioclk0 +#define PD_AUD_AUDIO_CLK_1 audio_audioclk1 + +#define PD_IMAGING imaging_power_domain +#define PD_IMAGING_JPEG_DEC imaging_jpeg_dec +#define PD_IMAGING_JPEG_ENC imaging_jpeg_enc +#define PD_IMAGING_PDMA0 PD_IMAGING +#define PD_IMAGING_PDMA1 imaging_pdma1 +#define PD_IMAGING_PDMA2 imaging_pdma2 +#define PD_IMAGING_PDMA3 imaging_pdma3 +#define PD_IMAGING_PDMA4 imaging_pdma4 +#define PD_IMAGING_PDMA5 imaging_pdma5 +#define PD_IMAGING_PDMA6 imaging_pdma6 +#define PD_IMAGING_PDMA7 imaging_pdma7 + +#define PD_MIPI_0_DSI mipi0_dsi_power_domain +#define PD_MIPI_0_DSI_I2C0 mipi0_dsi_i2c0 +#define PD_MIPI_0_DSI_I2C1 mipi0_dsi_i2c1 +#define PD_MIPI_0_DSI_PWM0 mipi0_dsi_pwm0 +#define PD_MIPI_1_DSI mipi1_dsi_power_domain +#define PD_MIPI_1_DSI_I2C0 mipi1_dsi_i2c0 +#define PD_MIPI_1_DSI_I2C1 mipi1_dsi_i2c1 +#define PD_MIPI_1_DSI_PWM0 mipi1_dsi_pwm0 + +#define PD_MIPI_CSI0 mipi_csi0_power_domain +#define PD_MIPI_CSI0_PWM mipi_csi0_pwm +#define PD_MIPI_CSI0_I2C mipi_csi0_i2c +#define PD_MIPI_CSI1 mipi_csi1_power_domain +#define PD_MIPI_CSI1_PWM_0 mipi_csi1_pwm +#define PD_MIPI_CSI1_I2C_0 mipi_csi1_i2c + +#define PD_HDMI hdmi_power_domain +#define PD_HDMI_I2C_0 hdmi_i2c +#define PD_HDMI_PWM_0 hdmi_pwm +#define PD_HDMI_GPIO_0 hdmi_gpio + +#define PD_HDMI_RX hdmi_rx_power_domain +#define PD_HDMI_RX_I2C hdmi_rx_i2c +#define PD_HDMI_RX_PWM hdmi_rx_pwm + +#define PD_CM40 cm40_power_domain +#define PD_CM40_I2C cm40_i2c +#define PD_CM40_INTMUX cm40_intmux + +#endif /* __DT_BINDINGS_IMX8_PD_H */ diff --git a/roms/u-boot/include/dt-bindings/soc/imx_rsrc.h b/roms/u-boot/include/dt-bindings/soc/imx_rsrc.h new file mode 100644 index 000000000..fb6878f6e --- /dev/null +++ b/roms/u-boot/include/dt-bindings/soc/imx_rsrc.h @@ -0,0 +1,558 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef DT_BINDINGS_RSCRC_IMX_H +#define DT_BINDINGS_RSCRC_IMX_H + +/*! + * These defines are used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ +#define SC_R_A53 0 +#define SC_R_A53_0 1 +#define SC_R_A53_1 2 +#define SC_R_A53_2 3 +#define SC_R_A53_3 4 +#define SC_R_A72 5 +#define SC_R_A72_0 6 +#define SC_R_A72_1 7 +#define SC_R_A72_2 8 +#define SC_R_A72_3 9 +#define SC_R_CCI 10 +#define SC_R_DB 11 +#define SC_R_DRC_0 12 +#define SC_R_DRC_1 13 +#define SC_R_GIC_SMMU 14 +#define SC_R_IRQSTR_M4_0 15 +#define SC_R_IRQSTR_M4_1 16 +#define SC_R_SMMU 17 +#define SC_R_GIC 18 +#define SC_R_DC_0_BLIT0 19 +#define SC_R_DC_0_BLIT1 20 +#define SC_R_DC_0_BLIT2 21 +#define SC_R_DC_0_BLIT_OUT 22 +#define SC_R_DC_0_CAPTURE0 23 +#define SC_R_DC_0_CAPTURE1 24 +#define SC_R_DC_0_WARP 25 +#define SC_R_DC_0_INTEGRAL0 26 +#define SC_R_DC_0_INTEGRAL1 27 +#define SC_R_DC_0_VIDEO0 28 +#define SC_R_DC_0_VIDEO1 29 +#define SC_R_DC_0_FRAC0 30 +#define SC_R_DC_0_FRAC1 31 +#define SC_R_DC_0 32 +#define SC_R_GPU_2_PID0 33 +#define SC_R_DC_0_PLL_0 34 +#define SC_R_DC_0_PLL_1 35 +#define SC_R_DC_1_BLIT0 36 +#define SC_R_DC_1_BLIT1 37 +#define SC_R_DC_1_BLIT2 38 +#define SC_R_DC_1_BLIT_OUT 39 +#define SC_R_DC_1_CAPTURE0 40 +#define SC_R_DC_1_CAPTURE1 41 +#define SC_R_DC_1_WARP 42 +#define SC_R_DC_1_INTEGRAL0 43 +#define SC_R_DC_1_INTEGRAL1 44 +#define SC_R_DC_1_VIDEO0 45 +#define SC_R_DC_1_VIDEO1 46 +#define SC_R_DC_1_FRAC0 47 +#define SC_R_DC_1_FRAC1 48 +#define SC_R_DC_1 49 +#define SC_R_GPU_3_PID0 50 +#define SC_R_DC_1_PLL_0 51 +#define SC_R_DC_1_PLL_1 52 +#define SC_R_SPI_0 53 +#define SC_R_SPI_1 54 +#define SC_R_SPI_2 55 +#define SC_R_SPI_3 56 +#define SC_R_UART_0 57 +#define SC_R_UART_1 58 +#define SC_R_UART_2 59 +#define SC_R_UART_3 60 +#define SC_R_UART_4 61 +#define SC_R_EMVSIM_0 62 +#define SC_R_EMVSIM_1 63 +#define SC_R_DMA_0_CH0 64 +#define SC_R_DMA_0_CH1 65 +#define SC_R_DMA_0_CH2 66 +#define SC_R_DMA_0_CH3 67 +#define SC_R_DMA_0_CH4 68 +#define SC_R_DMA_0_CH5 69 +#define SC_R_DMA_0_CH6 70 +#define SC_R_DMA_0_CH7 71 +#define SC_R_DMA_0_CH8 72 +#define SC_R_DMA_0_CH9 73 +#define SC_R_DMA_0_CH10 74 +#define SC_R_DMA_0_CH11 75 +#define SC_R_DMA_0_CH12 76 +#define SC_R_DMA_0_CH13 77 +#define SC_R_DMA_0_CH14 78 +#define SC_R_DMA_0_CH15 79 +#define SC_R_DMA_0_CH16 80 +#define SC_R_DMA_0_CH17 81 +#define SC_R_DMA_0_CH18 82 +#define SC_R_DMA_0_CH19 83 +#define SC_R_DMA_0_CH20 84 +#define SC_R_DMA_0_CH21 85 +#define SC_R_DMA_0_CH22 86 +#define SC_R_DMA_0_CH23 87 +#define SC_R_DMA_0_CH24 88 +#define SC_R_DMA_0_CH25 89 +#define SC_R_DMA_0_CH26 90 +#define SC_R_DMA_0_CH27 91 +#define SC_R_DMA_0_CH28 92 +#define SC_R_DMA_0_CH29 93 +#define SC_R_DMA_0_CH30 94 +#define SC_R_DMA_0_CH31 95 +#define SC_R_I2C_0 96 +#define SC_R_I2C_1 97 +#define SC_R_I2C_2 98 +#define SC_R_I2C_3 99 +#define SC_R_I2C_4 100 +#define SC_R_ADC_0 101 +#define SC_R_ADC_1 102 +#define SC_R_FTM_0 103 +#define SC_R_FTM_1 104 +#define SC_R_CAN_0 105 +#define SC_R_CAN_1 106 +#define SC_R_CAN_2 107 +#define SC_R_DMA_1_CH0 108 +#define SC_R_DMA_1_CH1 109 +#define SC_R_DMA_1_CH2 110 +#define SC_R_DMA_1_CH3 111 +#define SC_R_DMA_1_CH4 112 +#define SC_R_DMA_1_CH5 113 +#define SC_R_DMA_1_CH6 114 +#define SC_R_DMA_1_CH7 115 +#define SC_R_DMA_1_CH8 116 +#define SC_R_DMA_1_CH9 117 +#define SC_R_DMA_1_CH10 118 +#define SC_R_DMA_1_CH11 119 +#define SC_R_DMA_1_CH12 120 +#define SC_R_DMA_1_CH13 121 +#define SC_R_DMA_1_CH14 122 +#define SC_R_DMA_1_CH15 123 +#define SC_R_DMA_1_CH16 124 +#define SC_R_DMA_1_CH17 125 +#define SC_R_DMA_1_CH18 126 +#define SC_R_DMA_1_CH19 127 +#define SC_R_DMA_1_CH20 128 +#define SC_R_DMA_1_CH21 129 +#define SC_R_DMA_1_CH22 130 +#define SC_R_DMA_1_CH23 131 +#define SC_R_DMA_1_CH24 132 +#define SC_R_DMA_1_CH25 133 +#define SC_R_DMA_1_CH26 134 +#define SC_R_DMA_1_CH27 135 +#define SC_R_DMA_1_CH28 136 +#define SC_R_DMA_1_CH29 137 +#define SC_R_DMA_1_CH30 138 +#define SC_R_DMA_1_CH31 139 +#define SC_R_UNUSED1 140 +#define SC_R_UNUSED2 141 +#define SC_R_UNUSED3 142 +#define SC_R_UNUSED4 143 +#define SC_R_GPU_0_PID0 144 +#define SC_R_GPU_0_PID1 145 +#define SC_R_GPU_0_PID2 146 +#define SC_R_GPU_0_PID3 147 +#define SC_R_GPU_1_PID0 148 +#define SC_R_GPU_1_PID1 149 +#define SC_R_GPU_1_PID2 150 +#define SC_R_GPU_1_PID3 151 +#define SC_R_PCIE_A 152 +#define SC_R_SERDES_0 153 +#define SC_R_MATCH_0 154 +#define SC_R_MATCH_1 155 +#define SC_R_MATCH_2 156 +#define SC_R_MATCH_3 157 +#define SC_R_MATCH_4 158 +#define SC_R_MATCH_5 159 +#define SC_R_MATCH_6 160 +#define SC_R_MATCH_7 161 +#define SC_R_MATCH_8 162 +#define SC_R_MATCH_9 163 +#define SC_R_MATCH_10 164 +#define SC_R_MATCH_11 165 +#define SC_R_MATCH_12 166 +#define SC_R_MATCH_13 167 +#define SC_R_MATCH_14 168 +#define SC_R_PCIE_B 169 +#define SC_R_SATA_0 170 +#define SC_R_SERDES_1 171 +#define SC_R_HSIO_GPIO 172 +#define SC_R_MATCH_15 173 +#define SC_R_MATCH_16 174 +#define SC_R_MATCH_17 175 +#define SC_R_MATCH_18 176 +#define SC_R_MATCH_19 177 +#define SC_R_MATCH_20 178 +#define SC_R_MATCH_21 179 +#define SC_R_MATCH_22 180 +#define SC_R_MATCH_23 181 +#define SC_R_MATCH_24 182 +#define SC_R_MATCH_25 183 +#define SC_R_MATCH_26 184 +#define SC_R_MATCH_27 185 +#define SC_R_MATCH_28 186 +#define SC_R_LCD_0 187 +#define SC_R_LCD_0_PWM_0 188 +#define SC_R_LCD_0_I2C_0 189 +#define SC_R_LCD_0_I2C_1 190 +#define SC_R_PWM_0 191 +#define SC_R_PWM_1 192 +#define SC_R_PWM_2 193 +#define SC_R_PWM_3 194 +#define SC_R_PWM_4 195 +#define SC_R_PWM_5 196 +#define SC_R_PWM_6 197 +#define SC_R_PWM_7 198 +#define SC_R_GPIO_0 199 +#define SC_R_GPIO_1 200 +#define SC_R_GPIO_2 201 +#define SC_R_GPIO_3 202 +#define SC_R_GPIO_4 203 +#define SC_R_GPIO_5 204 +#define SC_R_GPIO_6 205 +#define SC_R_GPIO_7 206 +#define SC_R_GPT_0 207 +#define SC_R_GPT_1 208 +#define SC_R_GPT_2 209 +#define SC_R_GPT_3 210 +#define SC_R_GPT_4 211 +#define SC_R_KPP 212 +#define SC_R_MU_0A 213 +#define SC_R_MU_1A 214 +#define SC_R_MU_2A 215 +#define SC_R_MU_3A 216 +#define SC_R_MU_4A 217 +#define SC_R_MU_5A 218 +#define SC_R_MU_6A 219 +#define SC_R_MU_7A 220 +#define SC_R_MU_8A 221 +#define SC_R_MU_9A 222 +#define SC_R_MU_10A 223 +#define SC_R_MU_11A 224 +#define SC_R_MU_12A 225 +#define SC_R_MU_13A 226 +#define SC_R_MU_5B 227 +#define SC_R_MU_6B 228 +#define SC_R_MU_7B 229 +#define SC_R_MU_8B 230 +#define SC_R_MU_9B 231 +#define SC_R_MU_10B 232 +#define SC_R_MU_11B 233 +#define SC_R_MU_12B 234 +#define SC_R_MU_13B 235 +#define SC_R_ROM_0 236 +#define SC_R_FSPI_0 237 +#define SC_R_FSPI_1 238 +#define SC_R_IEE 239 +#define SC_R_IEE_R0 240 +#define SC_R_IEE_R1 241 +#define SC_R_IEE_R2 242 +#define SC_R_IEE_R3 243 +#define SC_R_IEE_R4 244 +#define SC_R_IEE_R5 245 +#define SC_R_IEE_R6 246 +#define SC_R_IEE_R7 247 +#define SC_R_SDHC_0 248 +#define SC_R_SDHC_1 249 +#define SC_R_SDHC_2 250 +#define SC_R_ENET_0 251 +#define SC_R_ENET_1 252 +#define SC_R_MLB_0 253 +#define SC_R_DMA_2_CH0 254 +#define SC_R_DMA_2_CH1 255 +#define SC_R_DMA_2_CH2 256 +#define SC_R_DMA_2_CH3 257 +#define SC_R_DMA_2_CH4 258 +#define SC_R_USB_0 259 +#define SC_R_USB_1 260 +#define SC_R_USB_0_PHY 261 +#define SC_R_USB_2 262 +#define SC_R_USB_2_PHY 263 +#define SC_R_DTCP 264 +#define SC_R_NAND 265 +#define SC_R_LVDS_0 266 +#define SC_R_LVDS_0_PWM_0 267 +#define SC_R_LVDS_0_I2C_0 268 +#define SC_R_LVDS_0_I2C_1 269 +#define SC_R_LVDS_1 270 +#define SC_R_LVDS_1_PWM_0 271 +#define SC_R_LVDS_1_I2C_0 272 +#define SC_R_LVDS_1_I2C_1 273 +#define SC_R_LVDS_2 274 +#define SC_R_LVDS_2_PWM_0 275 +#define SC_R_LVDS_2_I2C_0 276 +#define SC_R_LVDS_2_I2C_1 277 +#define SC_R_M4_0_PID0 278 +#define SC_R_M4_0_PID1 279 +#define SC_R_M4_0_PID2 280 +#define SC_R_M4_0_PID3 281 +#define SC_R_M4_0_PID4 282 +#define SC_R_M4_0_RGPIO 283 +#define SC_R_M4_0_SEMA42 284 +#define SC_R_M4_0_TPM 285 +#define SC_R_M4_0_PIT 286 +#define SC_R_M4_0_UART 287 +#define SC_R_M4_0_I2C 288 +#define SC_R_M4_0_INTMUX 289 +#define SC_R_M4_0_SIM 290 +#define SC_R_M4_0_WDOG 291 +#define SC_R_M4_0_MU_0B 292 +#define SC_R_M4_0_MU_0A0 293 +#define SC_R_M4_0_MU_0A1 294 +#define SC_R_M4_0_MU_0A2 295 +#define SC_R_M4_0_MU_0A3 296 +#define SC_R_M4_0_MU_1A 297 +#define SC_R_M4_1_PID0 298 +#define SC_R_M4_1_PID1 299 +#define SC_R_M4_1_PID2 300 +#define SC_R_M4_1_PID3 301 +#define SC_R_M4_1_PID4 302 +#define SC_R_M4_1_RGPIO 303 +#define SC_R_M4_1_SEMA42 304 +#define SC_R_M4_1_TPM 305 +#define SC_R_M4_1_PIT 306 +#define SC_R_M4_1_UART 307 +#define SC_R_M4_1_I2C 308 +#define SC_R_M4_1_INTMUX 309 +#define SC_R_M4_1_SIM 310 +#define SC_R_M4_1_WDOG 311 +#define SC_R_M4_1_MU_0B 312 +#define SC_R_M4_1_MU_0A0 313 +#define SC_R_M4_1_MU_0A1 314 +#define SC_R_M4_1_MU_0A2 315 +#define SC_R_M4_1_MU_0A3 316 +#define SC_R_M4_1_MU_1A 317 +#define SC_R_SAI_0 318 +#define SC_R_SAI_1 319 +#define SC_R_SAI_2 320 +#define SC_R_IRQSTR_SCU2 321 +#define SC_R_IRQSTR_DSP 322 +#define SC_R_UNUSED5 323 +#define SC_R_OCRAM 324 +#define SC_R_AUDIO_PLL_0 325 +#define SC_R_PI_0 326 +#define SC_R_PI_0_PWM_0 327 +#define SC_R_PI_0_PWM_1 328 +#define SC_R_PI_0_I2C_0 329 +#define SC_R_PI_0_PLL 330 +#define SC_R_PI_1 331 +#define SC_R_PI_1_PWM_0 332 +#define SC_R_PI_1_PWM_1 333 +#define SC_R_PI_1_I2C_0 334 +#define SC_R_PI_1_PLL 335 +#define SC_R_SC_PID0 336 +#define SC_R_SC_PID1 337 +#define SC_R_SC_PID2 338 +#define SC_R_SC_PID3 339 +#define SC_R_SC_PID4 340 +#define SC_R_SC_SEMA42 341 +#define SC_R_SC_TPM 342 +#define SC_R_SC_PIT 343 +#define SC_R_SC_UART 344 +#define SC_R_SC_I2C 345 +#define SC_R_SC_MU_0B 346 +#define SC_R_SC_MU_0A0 347 +#define SC_R_SC_MU_0A1 348 +#define SC_R_SC_MU_0A2 349 +#define SC_R_SC_MU_0A3 350 +#define SC_R_SC_MU_1A 351 +#define SC_R_SYSCNT_RD 352 +#define SC_R_SYSCNT_CMP 353 +#define SC_R_DEBUG 354 +#define SC_R_SYSTEM 355 +#define SC_R_SNVS 356 +#define SC_R_OTP 357 +#define SC_R_VPU_PID0 358 +#define SC_R_VPU_PID1 359 +#define SC_R_VPU_PID2 360 +#define SC_R_VPU_PID3 361 +#define SC_R_VPU_PID4 362 +#define SC_R_VPU_PID5 363 +#define SC_R_VPU_PID6 364 +#define SC_R_VPU_PID7 365 +#define SC_R_VPU_UART 366 +#define SC_R_VPUCORE 367 +#define SC_R_VPUCORE_0 368 +#define SC_R_VPUCORE_1 369 +#define SC_R_VPUCORE_2 370 +#define SC_R_VPUCORE_3 371 +#define SC_R_DMA_4_CH0 372 +#define SC_R_DMA_4_CH1 373 +#define SC_R_DMA_4_CH2 374 +#define SC_R_DMA_4_CH3 375 +#define SC_R_DMA_4_CH4 376 +#define SC_R_ISI_CH0 377 +#define SC_R_ISI_CH1 378 +#define SC_R_ISI_CH2 379 +#define SC_R_ISI_CH3 380 +#define SC_R_ISI_CH4 381 +#define SC_R_ISI_CH5 382 +#define SC_R_ISI_CH6 383 +#define SC_R_ISI_CH7 384 +#define SC_R_MJPEG_DEC_S0 385 +#define SC_R_MJPEG_DEC_S1 386 +#define SC_R_MJPEG_DEC_S2 387 +#define SC_R_MJPEG_DEC_S3 388 +#define SC_R_MJPEG_ENC_S0 389 +#define SC_R_MJPEG_ENC_S1 390 +#define SC_R_MJPEG_ENC_S2 391 +#define SC_R_MJPEG_ENC_S3 392 +#define SC_R_MIPI_0 393 +#define SC_R_MIPI_0_PWM_0 394 +#define SC_R_MIPI_0_I2C_0 395 +#define SC_R_MIPI_0_I2C_1 396 +#define SC_R_MIPI_1 397 +#define SC_R_MIPI_1_PWM_0 398 +#define SC_R_MIPI_1_I2C_0 399 +#define SC_R_MIPI_1_I2C_1 400 +#define SC_R_CSI_0 401 +#define SC_R_CSI_0_PWM_0 402 +#define SC_R_CSI_0_I2C_0 403 +#define SC_R_CSI_1 404 +#define SC_R_CSI_1_PWM_0 405 +#define SC_R_CSI_1_I2C_0 406 +#define SC_R_HDMI 407 +#define SC_R_HDMI_I2S 408 +#define SC_R_HDMI_I2C_0 409 +#define SC_R_HDMI_PLL_0 410 +#define SC_R_HDMI_RX 411 +#define SC_R_HDMI_RX_BYPASS 412 +#define SC_R_HDMI_RX_I2C_0 413 +#define SC_R_ASRC_0 414 +#define SC_R_ESAI_0 415 +#define SC_R_SPDIF_0 416 +#define SC_R_SPDIF_1 417 +#define SC_R_SAI_3 418 +#define SC_R_SAI_4 419 +#define SC_R_SAI_5 420 +#define SC_R_GPT_5 421 +#define SC_R_GPT_6 422 +#define SC_R_GPT_7 423 +#define SC_R_GPT_8 424 +#define SC_R_GPT_9 425 +#define SC_R_GPT_10 426 +#define SC_R_DMA_2_CH5 427 +#define SC_R_DMA_2_CH6 428 +#define SC_R_DMA_2_CH7 429 +#define SC_R_DMA_2_CH8 430 +#define SC_R_DMA_2_CH9 431 +#define SC_R_DMA_2_CH10 432 +#define SC_R_DMA_2_CH11 433 +#define SC_R_DMA_2_CH12 434 +#define SC_R_DMA_2_CH13 435 +#define SC_R_DMA_2_CH14 436 +#define SC_R_DMA_2_CH15 437 +#define SC_R_DMA_2_CH16 438 +#define SC_R_DMA_2_CH17 439 +#define SC_R_DMA_2_CH18 440 +#define SC_R_DMA_2_CH19 441 +#define SC_R_DMA_2_CH20 442 +#define SC_R_DMA_2_CH21 443 +#define SC_R_DMA_2_CH22 444 +#define SC_R_DMA_2_CH23 445 +#define SC_R_DMA_2_CH24 446 +#define SC_R_DMA_2_CH25 447 +#define SC_R_DMA_2_CH26 448 +#define SC_R_DMA_2_CH27 449 +#define SC_R_DMA_2_CH28 450 +#define SC_R_DMA_2_CH29 451 +#define SC_R_DMA_2_CH30 452 +#define SC_R_DMA_2_CH31 453 +#define SC_R_ASRC_1 454 +#define SC_R_ESAI_1 455 +#define SC_R_SAI_6 456 +#define SC_R_SAI_7 457 +#define SC_R_AMIX 458 +#define SC_R_MQS_0 459 +#define SC_R_DMA_3_CH0 460 +#define SC_R_DMA_3_CH1 461 +#define SC_R_DMA_3_CH2 462 +#define SC_R_DMA_3_CH3 463 +#define SC_R_DMA_3_CH4 464 +#define SC_R_DMA_3_CH5 465 +#define SC_R_DMA_3_CH6 466 +#define SC_R_DMA_3_CH7 467 +#define SC_R_DMA_3_CH8 468 +#define SC_R_DMA_3_CH9 469 +#define SC_R_DMA_3_CH10 470 +#define SC_R_DMA_3_CH11 471 +#define SC_R_DMA_3_CH12 472 +#define SC_R_DMA_3_CH13 473 +#define SC_R_DMA_3_CH14 474 +#define SC_R_DMA_3_CH15 475 +#define SC_R_DMA_3_CH16 476 +#define SC_R_DMA_3_CH17 477 +#define SC_R_DMA_3_CH18 478 +#define SC_R_DMA_3_CH19 479 +#define SC_R_DMA_3_CH20 480 +#define SC_R_DMA_3_CH21 481 +#define SC_R_DMA_3_CH22 482 +#define SC_R_DMA_3_CH23 483 +#define SC_R_DMA_3_CH24 484 +#define SC_R_DMA_3_CH25 485 +#define SC_R_DMA_3_CH26 486 +#define SC_R_DMA_3_CH27 487 +#define SC_R_DMA_3_CH28 488 +#define SC_R_DMA_3_CH29 489 +#define SC_R_DMA_3_CH30 490 +#define SC_R_DMA_3_CH31 491 +#define SC_R_AUDIO_PLL_1 492 +#define SC_R_AUDIO_CLK_0 493 +#define SC_R_AUDIO_CLK_1 494 +#define SC_R_MCLK_OUT_0 495 +#define SC_R_MCLK_OUT_1 496 +#define SC_R_PMIC_0 497 +#define SC_R_PMIC_1 498 +#define SC_R_SECO 499 +#define SC_R_CAAM_JR1 500 +#define SC_R_CAAM_JR2 501 +#define SC_R_CAAM_JR3 502 +#define SC_R_SECO_MU_2 503 +#define SC_R_SECO_MU_3 504 +#define SC_R_SECO_MU_4 505 +#define SC_R_HDMI_RX_PWM_0 506 +#define SC_R_A35 507 +#define SC_R_A35_0 508 +#define SC_R_A35_1 509 +#define SC_R_A35_2 510 +#define SC_R_A35_3 511 +#define SC_R_DSP 512 +#define SC_R_DSP_RAM 513 +#define SC_R_CAAM_JR1_OUT 514 +#define SC_R_CAAM_JR2_OUT 515 +#define SC_R_CAAM_JR3_OUT 516 +#define SC_R_VPU_DEC_0 517 +#define SC_R_VPU_ENC_0 518 +#define SC_R_CAAM_JR0 519 +#define SC_R_CAAM_JR0_OUT 520 +#define SC_R_PMIC_2 521 +#define SC_R_DBLOGIC 522 +#define SC_R_HDMI_PLL_1 523 +#define SC_R_BOARD_R0 524 +#define SC_R_BOARD_R1 525 +#define SC_R_BOARD_R2 526 +#define SC_R_BOARD_R3 527 +#define SC_R_BOARD_R4 528 +#define SC_R_BOARD_R5 529 +#define SC_R_BOARD_R6 530 +#define SC_R_BOARD_R7 531 +#define SC_R_MJPEG_DEC_MP 532 +#define SC_R_MJPEG_ENC_MP 533 +#define SC_R_VPU_TS_0 534 +#define SC_R_VPU_MU_0 535 +#define SC_R_VPU_MU_1 536 +#define SC_R_VPU_MU_2 537 +#define SC_R_VPU_MU_3 538 +#define SC_R_VPU_ENC_1 539 +#define SC_R_VPU 540 +#define SC_R_LAST 541 +#define SC_R_NONE 0xFFF0 + +#endif /* DT_BINDINGS_RSCRC_IMX_H */ diff --git a/roms/u-boot/include/dt-bindings/soc/rockchip,boot-mode.h b/roms/u-boot/include/dt-bindings/soc/rockchip,boot-mode.h new file mode 100644 index 000000000..4b0914c09 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/soc/rockchip,boot-mode.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ROCKCHIP_BOOT_MODE_H +#define __ROCKCHIP_BOOT_MODE_H + +/*high 24 bits is tag, low 8 bits is type*/ +#define REBOOT_FLAG 0x5242C300 +/* normal boot */ +#define BOOT_NORMAL (REBOOT_FLAG + 0) +/* enter bootloader rockusb mode */ +#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1) +/* enter recovery */ +#define BOOT_RECOVERY (REBOOT_FLAG + 3) + /* enter fastboot mode */ +#define BOOT_FASTBOOT (REBOOT_FLAG + 9) + +#endif diff --git a/roms/u-boot/include/dt-bindings/soc/ti,sci_pm_domain.h b/roms/u-boot/include/dt-bindings/soc/ti,sci_pm_domain.h new file mode 100644 index 000000000..8f2a7360b --- /dev/null +++ b/roms/u-boot/include/dt-bindings/soc/ti,sci_pm_domain.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __DT_BINDINGS_TI_SCI_PM_DOMAIN_H +#define __DT_BINDINGS_TI_SCI_PM_DOMAIN_H + +#define TI_SCI_PD_EXCLUSIVE 1 +#define TI_SCI_PD_SHARED 0 + +#endif /* __DT_BINDINGS_TI_SCI_PM_DOMAIN_H */ diff --git a/roms/u-boot/include/dt-bindings/sound/azalia.h b/roms/u-boot/include/dt-bindings/sound/azalia.h new file mode 100644 index 000000000..10ace3ef5 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/sound/azalia.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Intel HDA audio codec config. This is a mechanicm to configure codecs when + * using Intel HDA audio. + * + * Copyright 2018 Google LLC + * Written by Simon Glass + */ + +#ifndef __AZALIA_H +#define __AZALIA_H + +#define AZALIA_CODEC_SHIFT 28 +#define AZALIA_NID_SHIFT 20 +#define AZALIA_VERB_SHIFT 8 + +/* Supported opcodes */ +#define AZALIA_OPCODE_CONFIG_DEFAULT 0x71c +#define AZALIA_OPCODE_IMPL_ID 0x720 +#define AZALIA_OPCODE_READ_PARAM 0xf00 + +#define AZALIA_PARAM_VENDOR_ID 0 + +/* Generate the register value to write a particular byte of a 32-bit value */ +#define AZALIA_SET_BYTE(codec, nid, opcode, val, byte) \ + ((codec) << AZALIA_CODEC_SHIFT | \ + (nid) << AZALIA_NID_SHIFT | \ + ((opcode) + (byte)) << AZALIA_VERB_SHIFT | \ + (((val) >> ((byte) * 8)) & 0xff)) + +/* Generate the register value to write all bytes of a 32-bit value */ +#define AZALIA_WORD(codec, nid, opcode, val) \ + (AZALIA_SET_BYTE(codec, nid, opcode, val, 0) | \ + AZALIA_SET_BYTE(codec, nid, opcode, val, 1) | \ + AZALIA_SET_BYTE(codec, nid, opcode, val, 2) | \ + AZALIA_SET_BYTE(codec, nid, opcode, val, 3)) + +#define AZALIA_PIN_CFG(codec, nid, val) \ + AZALIA_WORD(codec, nid, AZALIA_OPCODE_CONFIG_DEFAULT, val) + +#define AZALIA_SUBVENDOR(codec, val) \ + AZALIA_WORD(codec, 1, AZALIA_OPCODE_IMPL_ID, val) + +#endif /* __AZALIA_H */ diff --git a/roms/u-boot/include/dt-bindings/sound/fsl-imx-audmux.h b/roms/u-boot/include/dt-bindings/sound/fsl-imx-audmux.h new file mode 100644 index 000000000..15f138beb --- /dev/null +++ b/roms/u-boot/include/dt-bindings/sound/fsl-imx-audmux.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_FSL_IMX_AUDMUX_H +#define __DT_FSL_IMX_AUDMUX_H + +#define MX27_AUDMUX_HPCR1_SSI0 0 +#define MX27_AUDMUX_HPCR2_SSI1 1 +#define MX27_AUDMUX_HPCR3_SSI_PINS_4 2 +#define MX27_AUDMUX_PPCR1_SSI_PINS_1 3 +#define MX27_AUDMUX_PPCR2_SSI_PINS_2 4 +#define MX27_AUDMUX_PPCR3_SSI_PINS_3 5 + +#define MX31_AUDMUX_PORT1_SSI0 0 +#define MX31_AUDMUX_PORT2_SSI1 1 +#define MX31_AUDMUX_PORT3_SSI_PINS_3 2 +#define MX31_AUDMUX_PORT4_SSI_PINS_4 3 +#define MX31_AUDMUX_PORT5_SSI_PINS_5 4 +#define MX31_AUDMUX_PORT6_SSI_PINS_6 5 +#define MX31_AUDMUX_PORT7_SSI_PINS_7 6 + +#define MX51_AUDMUX_PORT1_SSI0 0 +#define MX51_AUDMUX_PORT2_SSI1 1 +#define MX51_AUDMUX_PORT3 2 +#define MX51_AUDMUX_PORT4 3 +#define MX51_AUDMUX_PORT5 4 +#define MX51_AUDMUX_PORT6 5 +#define MX51_AUDMUX_PORT7 6 + +/* + * TFCSEL/RFCSEL (i.MX27) or TFSEL/TCSEL/RFSEL/RCSEL (i.MX31/51/53/6Q) + * can be sourced from Rx/Tx. + */ +#define IMX_AUDMUX_RXFS 0x8 +#define IMX_AUDMUX_RXCLK 0x8 + +/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */ +#define IMX_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff) +#define IMX_AUDMUX_V1_PCR_INMEN (1 << 8) +#define IMX_AUDMUX_V1_PCR_TXRXEN (1 << 10) +#define IMX_AUDMUX_V1_PCR_SYN (1 << 12) +#define IMX_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13) +#define IMX_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20) +#define IMX_AUDMUX_V1_PCR_RCLKDIR (1 << 24) +#define IMX_AUDMUX_V1_PCR_RFSDIR (1 << 25) +#define IMX_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26) +#define IMX_AUDMUX_V1_PCR_TCLKDIR (1 << 30) +#define IMX_AUDMUX_V1_PCR_TFSDIR (1 << 31) + +/* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */ +#define IMX_AUDMUX_V2_PTCR_TFSDIR (1 << 31) +#define IMX_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27) +#define IMX_AUDMUX_V2_PTCR_TCLKDIR (1 << 26) +#define IMX_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22) +#define IMX_AUDMUX_V2_PTCR_RFSDIR (1 << 21) +#define IMX_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17) +#define IMX_AUDMUX_V2_PTCR_RCLKDIR (1 << 16) +#define IMX_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12) +#define IMX_AUDMUX_V2_PTCR_SYN (1 << 11) + +#define IMX_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13) +#define IMX_AUDMUX_V2_PDCR_TXRXEN (1 << 12) +#define IMX_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8) +#define IMX_AUDMUX_V2_PDCR_INMMASK(x) ((x) & 0xff) + +#endif /* __DT_FSL_IMX_AUDMUX_H */ diff --git a/roms/u-boot/include/dt-bindings/sound/meson-aiu.h b/roms/u-boot/include/dt-bindings/sound/meson-aiu.h new file mode 100644 index 000000000..1051b8af2 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/sound/meson-aiu.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_MESON_AIU_H +#define __DT_MESON_AIU_H + +#define AIU_CPU 0 +#define AIU_HDMI 1 +#define AIU_ACODEC 2 + +#define CPU_I2S_FIFO 0 +#define CPU_SPDIF_FIFO 1 +#define CPU_I2S_ENCODER 2 +#define CPU_SPDIF_ENCODER 3 + +#define CTRL_I2S 0 +#define CTRL_PCM 1 +#define CTRL_OUT 2 + +#endif /* __DT_MESON_AIU_H */ diff --git a/roms/u-boot/include/dt-bindings/sound/meson-g12a-toacodec.h b/roms/u-boot/include/dt-bindings/sound/meson-g12a-toacodec.h new file mode 100644 index 000000000..69d7a7559 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/sound/meson-g12a-toacodec.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_MESON_G12A_TOACODEC_H +#define __DT_MESON_G12A_TOACODEC_H + +#define TOACODEC_IN_A 0 +#define TOACODEC_IN_B 1 +#define TOACODEC_IN_C 2 +#define TOACODEC_OUT 3 + +#endif /* __DT_MESON_G12A_TOACODEC_H */ diff --git a/roms/u-boot/include/dt-bindings/sound/meson-g12a-tohdmitx.h b/roms/u-boot/include/dt-bindings/sound/meson-g12a-tohdmitx.h new file mode 100644 index 000000000..c5e1f48d3 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/sound/meson-g12a-tohdmitx.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_MESON_G12A_TOHDMITX_H +#define __DT_MESON_G12A_TOHDMITX_H + +#define TOHDMITX_I2S_IN_A 0 +#define TOHDMITX_I2S_IN_B 1 +#define TOHDMITX_I2S_IN_C 2 +#define TOHDMITX_I2S_OUT 3 +#define TOHDMITX_SPDIF_IN_A 4 +#define TOHDMITX_SPDIF_IN_B 5 +#define TOHDMITX_SPDIF_OUT 6 + +#endif /* __DT_MESON_G12A_TOHDMITX_H */ diff --git a/roms/u-boot/include/dt-bindings/sound/nhlt.h b/roms/u-boot/include/dt-bindings/sound/nhlt.h new file mode 100644 index 000000000..dad69c24b --- /dev/null +++ b/roms/u-boot/include/dt-bindings/sound/nhlt.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef _DT_BINDINGS_SOUND_NHLT_H +#define _DT_BINDINGS_SOUND_NHLT_H + +/* See Table 2-1. NHLT Endpoint Descriptor in the NHLT Specification (0.8.1) */ +#define NHLT_VID 0x8086 +#define NHLT_DID_DMIC 0xae20 +#define NHLT_DID_BT 0xae30 +#define NHLT_DID_SSP 0xae34 + +/* Hardware links available to use for codecs */ +#define AUDIO_LINK_SSP0 0 +#define AUDIO_LINK_SSP1 1 +#define AUDIO_LINK_SSP2 2 +#define AUDIO_LINK_SSP3 3 +#define AUDIO_LINK_SSP4 4 +#define AUDIO_LINK_SSP5 5 +#define AUDIO_LINK_DMIC 6 + +#endif /* _DT_BINDINGS_SOUND_NHLT_H */ diff --git a/roms/u-boot/include/dt-bindings/sound/tlv320aic31xx-micbias.h b/roms/u-boot/include/dt-bindings/sound/tlv320aic31xx-micbias.h new file mode 100644 index 000000000..f5cb772ab --- /dev/null +++ b/roms/u-boot/include/dt-bindings/sound/tlv320aic31xx-micbias.h @@ -0,0 +1,8 @@ +#ifndef __DT_TLV320AIC31XX_MICBIAS_H +#define __DT_TLV320AIC31XX_MICBIAS_H + +#define MICBIAS_2_0V 1 +#define MICBIAS_2_5V 2 +#define MICBIAS_AVDDV 3 + +#endif /* __DT_TLV320AIC31XX_MICBIAS_H */ diff --git a/roms/u-boot/include/dt-bindings/thermal/tegra124-soctherm.h b/roms/u-boot/include/dt-bindings/thermal/tegra124-soctherm.h new file mode 100644 index 000000000..729ab9fc3 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/thermal/tegra124-soctherm.h @@ -0,0 +1,14 @@ +/* + * This header provides constants for binding nvidia,tegra124-soctherm. + */ + +#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H +#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H + +#define TEGRA124_SOCTHERM_SENSOR_CPU 0 +#define TEGRA124_SOCTHERM_SENSOR_MEM 1 +#define TEGRA124_SOCTHERM_SENSOR_GPU 2 +#define TEGRA124_SOCTHERM_SENSOR_PLLX 3 +#define TEGRA124_SOCTHERM_SENSOR_NUM 4 + +#endif diff --git a/roms/u-boot/include/dt-bindings/thermal/thermal.h b/roms/u-boot/include/dt-bindings/thermal/thermal.h new file mode 100644 index 000000000..bc7babb1a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/thermal/thermal.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * This header provides constants for most thermal bindings. + * + * Copyright (C) 2013 Texas Instruments + * Eduardo Valentin + */ + +#ifndef _DT_BINDINGS_THERMAL_THERMAL_H +#define _DT_BINDINGS_THERMAL_THERMAL_H + +/* On cooling devices upper and lower limits */ +#define THERMAL_NO_LIMIT (~0) + +#endif + diff --git a/roms/u-boot/include/dt-bindings/usb/pd.h b/roms/u-boot/include/dt-bindings/usb/pd.h new file mode 100644 index 000000000..985f2bbd4 --- /dev/null +++ b/roms/u-boot/include/dt-bindings/usb/pd.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_POWER_DELIVERY_H +#define __DT_POWER_DELIVERY_H + +/* Power delivery Power Data Object definitions */ +#define PDO_TYPE_FIXED 0 +#define PDO_TYPE_BATT 1 +#define PDO_TYPE_VAR 2 +#define PDO_TYPE_APDO 3 + +#define PDO_TYPE_SHIFT 30 +#define PDO_TYPE_MASK 0x3 + +#define PDO_TYPE(t) ((t) << PDO_TYPE_SHIFT) + +#define PDO_VOLT_MASK 0x3ff +#define PDO_CURR_MASK 0x3ff +#define PDO_PWR_MASK 0x3ff + +#define PDO_FIXED_DUAL_ROLE (1 << 29) /* Power role swap supported */ +#define PDO_FIXED_SUSPEND (1 << 28) /* USB Suspend supported (Source) */ +#define PDO_FIXED_HIGHER_CAP (1 << 28) /* Requires more than vSafe5V (Sink) */ +#define PDO_FIXED_EXTPOWER (1 << 27) /* Externally powered */ +#define PDO_FIXED_USB_COMM (1 << 26) /* USB communications capable */ +#define PDO_FIXED_DATA_SWAP (1 << 25) /* Data role swap supported */ +#define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */ + +#define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) +#define PDO_FIXED_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT) + +#define PDO_FIXED(mv, ma, flags) \ + (PDO_TYPE(PDO_TYPE_FIXED) | (flags) | \ + PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma)) + +#define VSAFE5V 5000 /* mv units */ + +#define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */ +#define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */ + +#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) +#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT) +#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT) + +#define PDO_BATT(min_mv, max_mv, max_mw) \ + (PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) | \ + PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw)) + +#define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */ +#define PDO_VAR_MIN_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */ + +#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT) +#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT) +#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT) + +#define PDO_VAR(min_mv, max_mv, max_ma) \ + (PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \ + PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma)) + +#define APDO_TYPE_PPS 0 + +#define PDO_APDO_TYPE_SHIFT 28 /* Only valid value currently is 0x0 - PPS */ +#define PDO_APDO_TYPE_MASK 0x3 + +#define PDO_APDO_TYPE(t) ((t) << PDO_APDO_TYPE_SHIFT) + +#define PDO_PPS_APDO_MAX_VOLT_SHIFT 17 /* 100mV units */ +#define PDO_PPS_APDO_MIN_VOLT_SHIFT 8 /* 100mV units */ +#define PDO_PPS_APDO_MAX_CURR_SHIFT 0 /* 50mA units */ + +#define PDO_PPS_APDO_VOLT_MASK 0xff +#define PDO_PPS_APDO_CURR_MASK 0x7f + +#define PDO_PPS_APDO_MIN_VOLT(mv) \ + ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MIN_VOLT_SHIFT) +#define PDO_PPS_APDO_MAX_VOLT(mv) \ + ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MAX_VOLT_SHIFT) +#define PDO_PPS_APDO_MAX_CURR(ma) \ + ((((ma) / 50) & PDO_PPS_APDO_CURR_MASK) << PDO_PPS_APDO_MAX_CURR_SHIFT) + +#define PDO_PPS_APDO(min_mv, max_mv, max_ma) \ + (PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) | \ + PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) | \ + PDO_PPS_APDO_MAX_CURR(max_ma)) + + #endif /* __DT_POWER_DELIVERY_H */ diff --git a/roms/u-boot/include/dt-bindings/video/rk3288.h b/roms/u-boot/include/dt-bindings/video/rk3288.h new file mode 100644 index 000000000..7bfd2473a --- /dev/null +++ b/roms/u-boot/include/dt-bindings/video/rk3288.h @@ -0,0 +1,11 @@ +#ifndef __DT_BINDINGS_VIDEO_RK3288_H__ +#define __DT_BINDINGS_VIDEO_RK3288_H__ + +#define LVDS_OUTPUT_RGB 0 +#define LVDS_OUTPUT_SINGLE 1 +#define LVDS_OUTPUT_DUAL 2 + +#define LVDS_FORMAT_VESA 0 +#define LVDS_FORMAT_JEIDA 1 + +#endif diff --git a/roms/u-boot/include/dt-structs.h b/roms/u-boot/include/dt-structs.h new file mode 100644 index 000000000..f9ccaf56a --- /dev/null +++ b/roms/u-boot/include/dt-structs.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2016 Google, Inc + */ + +#ifndef __DT_STRUCTS +#define __DT_STRUCTS + +/* These structures may only be used in SPL */ +#if CONFIG_IS_ENABLED(OF_PLATDATA) +struct driver_info; + +struct phandle_0_arg { + uint idx; + int arg[0]; +}; + +struct phandle_1_arg { + uint idx; + int arg[1]; +}; + +struct phandle_2_arg { + uint idx; + int arg[2]; +}; + +#include +#include +#endif + +#endif diff --git a/roms/u-boot/include/dt_table.h b/roms/u-boot/include/dt_table.h new file mode 100644 index 000000000..7fb16e900 --- /dev/null +++ b/roms/u-boot/include/dt_table.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * This is from the Android Project, + * Repository: https://android.googlesource.com/platform/system/libufdt + * File: utils/src/dt_table.h + * Commit: 2626d8b9e4d8e8c6cc67ceb1dc4e05a47779785c + * Copyright (C) 2017 The Android Open Source Project + */ + +#ifndef DT_TABLE_H +#define DT_TABLE_H + +#include + +#define DT_TABLE_MAGIC 0xd7b7ab1e +#define DT_TABLE_DEFAULT_PAGE_SIZE 2048 +#define DT_TABLE_DEFAULT_VERSION 0 + +struct dt_table_header { + u32 magic; /* DT_TABLE_MAGIC */ + u32 total_size; /* includes dt_table_header + all dt_table_entry + * and all dtb/dtbo + */ + u32 header_size; /* sizeof(dt_table_header) */ + + u32 dt_entry_size; /* sizeof(dt_table_entry) */ + u32 dt_entry_count; /* number of dt_table_entry */ + u32 dt_entries_offset; /* offset to the first dt_table_entry + * from head of dt_table_header. + * The value will be equal to header_size if + * no padding is appended + */ + u32 page_size; /* flash page size we assume */ + u32 version; /* DTBO image version, the current version is 0. + * The version will be incremented when the + * dt_table_header struct is updated. + */ +}; + +struct dt_table_entry { + u32 dt_size; + u32 dt_offset; /* offset from head of dt_table_header */ + + u32 id; /* optional, must be zero if unused */ + u32 rev; /* optional, must be zero if unused */ + u32 custom[4]; /* optional, must be zero if unused */ +}; + +#endif diff --git a/roms/u-boot/include/dw_hdmi.h b/roms/u-boot/include/dw_hdmi.h new file mode 100644 index 000000000..8acae3839 --- /dev/null +++ b/roms/u-boot/include/dw_hdmi.h @@ -0,0 +1,560 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * (C) Copyright 2017 Jernej Skrabec + */ + +#ifndef _DW_HDMI_H +#define _DW_HDMI_H + +#include + +#define HDMI_EDID_BLOCK_SIZE 128 + +/* Identification Registers */ +#define HDMI_DESIGN_ID 0x0000 +#define HDMI_REVISION_ID 0x0001 +#define HDMI_PRODUCT_ID0 0x0002 +#define HDMI_PRODUCT_ID1 0x0003 +#define HDMI_CONFIG0_ID 0x0004 +#define HDMI_CONFIG1_ID 0x0005 +#define HDMI_CONFIG2_ID 0x0006 +#define HDMI_CONFIG3_ID 0x0007 + +/* Interrupt Registers */ +#define HDMI_IH_FC_STAT0 0x0100 +#define HDMI_IH_FC_STAT1 0x0101 +#define HDMI_IH_FC_STAT2 0x0102 +#define HDMI_IH_AS_STAT0 0x0103 +#define HDMI_IH_PHY_STAT0 0x0104 +#define HDMI_IH_I2CM_STAT0 0x0105 +#define HDMI_IH_CEC_STAT0 0x0106 +#define HDMI_IH_VP_STAT0 0x0107 +#define HDMI_IH_I2CMPHY_STAT0 0x0108 +#define HDMI_IH_AHBDMAAUD_STAT0 0x0109 + +#define HDMI_IH_MUTE_FC_STAT0 0x0180 +#define HDMI_IH_MUTE_FC_STAT1 0x0181 +#define HDMI_IH_MUTE_FC_STAT2 0x0182 +#define HDMI_IH_MUTE_AS_STAT0 0x0183 +#define HDMI_IH_MUTE_PHY_STAT0 0x0184 +#define HDMI_IH_MUTE_I2CM_STAT0 0x0185 +#define HDMI_IH_MUTE_CEC_STAT0 0x0186 +#define HDMI_IH_MUTE_VP_STAT0 0x0187 +#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188 +#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189 +#define HDMI_IH_MUTE 0x01FF + +/* Video Sample Registers */ +#define HDMI_TX_INVID0 0x0200 +#define HDMI_TX_INSTUFFING 0x0201 +#define HDMI_TX_GYDATA0 0x0202 +#define HDMI_TX_GYDATA1 0x0203 +#define HDMI_TX_RCRDATA0 0x0204 +#define HDMI_TX_RCRDATA1 0x0205 +#define HDMI_TX_BCBDATA0 0x0206 +#define HDMI_TX_BCBDATA1 0x0207 + +/* Video Packetizer Registers */ +#define HDMI_VP_STATUS 0x0800 +#define HDMI_VP_PR_CD 0x0801 +#define HDMI_VP_STUFF 0x0802 +#define HDMI_VP_REMAP 0x0803 +#define HDMI_VP_CONF 0x0804 +#define HDMI_VP_STAT 0x0805 +#define HDMI_VP_INT 0x0806 +#define HDMI_VP_MASK 0x0807 +#define HDMI_VP_POL 0x0808 + +/* Frame Composer Registers */ +#define HDMI_FC_INVIDCONF 0x1000 +#define HDMI_FC_INHACTV0 0x1001 +#define HDMI_FC_INHACTV1 0x1002 +#define HDMI_FC_INHBLANK0 0x1003 +#define HDMI_FC_INHBLANK1 0x1004 +#define HDMI_FC_INVACTV0 0x1005 +#define HDMI_FC_INVACTV1 0x1006 +#define HDMI_FC_INVBLANK 0x1007 +#define HDMI_FC_HSYNCINDELAY0 0x1008 +#define HDMI_FC_HSYNCINDELAY1 0x1009 +#define HDMI_FC_HSYNCINWIDTH0 0x100A +#define HDMI_FC_HSYNCINWIDTH1 0x100B +#define HDMI_FC_VSYNCINDELAY 0x100C +#define HDMI_FC_VSYNCINWIDTH 0x100D +#define HDMI_FC_INFREQ0 0x100E +#define HDMI_FC_INFREQ1 0x100F +#define HDMI_FC_INFREQ2 0x1010 +#define HDMI_FC_CTRLDUR 0x1011 +#define HDMI_FC_EXCTRLDUR 0x1012 +#define HDMI_FC_EXCTRLSPAC 0x1013 +#define HDMI_FC_CH0PREAM 0x1014 +#define HDMI_FC_CH1PREAM 0x1015 +#define HDMI_FC_CH2PREAM 0x1016 +#define HDMI_FC_AVICONF3 0x1017 +#define HDMI_FC_GCP 0x1018 +#define HDMI_FC_AVICONF0 0x1019 +#define HDMI_FC_AVICONF1 0x101A +#define HDMI_FC_AVICONF2 0x101B +#define HDMI_FC_AVIVID 0x101C +#define HDMI_FC_AVIETB0 0x101D +#define HDMI_FC_AVIETB1 0x101E +#define HDMI_FC_AVISBB0 0x101F +#define HDMI_FC_AVISBB1 0x1020 +#define HDMI_FC_AVIELB0 0x1021 +#define HDMI_FC_AVIELB1 0x1022 +#define HDMI_FC_AVISRB0 0x1023 +#define HDMI_FC_AVISRB1 0x1024 +#define HDMI_FC_AUDICONF0 0x1025 +#define HDMI_FC_AUDICONF1 0x1026 +#define HDMI_FC_AUDICONF2 0x1027 +#define HDMI_FC_AUDICONF3 0x1028 +#define HDMI_FC_VSDIEEEID0 0x1029 +#define HDMI_FC_VSDSIZE 0x102A + +/* HDMI Source PHY Registers */ +#define HDMI_PHY_CONF0 0x3000 +#define HDMI_PHY_TST0 0x3001 +#define HDMI_PHY_TST1 0x3002 +#define HDMI_PHY_TST2 0x3003 +#define HDMI_PHY_STAT0 0x3004 +#define HDMI_PHY_INT0 0x3005 +#define HDMI_PHY_MASK0 0x3006 +#define HDMI_PHY_POL0 0x3007 + +/* HDMI Master PHY Registers */ +#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020 +#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021 +#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022 +#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023 +#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024 +#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025 +#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026 +#define HDMI_PHY_I2CM_INT_ADDR 0x3027 +#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028 +#define HDMI_PHY_I2CM_DIV_ADDR 0x3029 +#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a +#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b +#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c +#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d +#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e +#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f +#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030 +#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031 +#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032 + +/* Audio Sampler Registers */ +#define HDMI_AUD_CONF0 0x3100 +#define HDMI_AUD_CONF1 0x3101 +#define HDMI_AUD_INT 0x3102 +#define HDMI_AUD_CONF2 0x3103 +#define HDMI_AUD_INT1 0x3104 +#define HDMI_AUD_N1 0x3200 +#define HDMI_AUD_N2 0x3201 +#define HDMI_AUD_N3 0x3202 +#define HDMI_AUD_CTS1 0x3203 +#define HDMI_AUD_CTS2 0x3204 +#define HDMI_AUD_CTS3 0x3205 +#define HDMI_AUD_INPUTCLKFS 0x3206 +#define HDMI_AUD_SPDIFINT 0x3302 +#define HDMI_AUD_CONF0_HBR 0x3400 +#define HDMI_AUD_HBR_STATUS 0x3401 +#define HDMI_AUD_HBR_INT 0x3402 +#define HDMI_AUD_HBR_POL 0x3403 +#define HDMI_AUD_HBR_MASK 0x3404 + +/* Main Controller Registers */ +#define HDMI_MC_SFRDIV 0x4000 +#define HDMI_MC_CLKDIS 0x4001 +#define HDMI_MC_SWRSTZ 0x4002 +#define HDMI_MC_OPCTRL 0x4003 +#define HDMI_MC_FLOWCTRL 0x4004 +#define HDMI_MC_PHYRSTZ 0x4005 +#define HDMI_MC_LOCKONCLOCK 0x4006 +#define HDMI_MC_HEACPHY_RST 0x4007 + +/* Color Space Converter Registers */ +#define HDMI_CSC_CFG 0x4100 +#define HDMI_CSC_SCALE 0x4101 +#define HDMI_CSC_COEF_A1_MSB 0x4102 +#define HDMI_CSC_COEF_A1_LSB 0x4103 +#define HDMI_CSC_COEF_A2_MSB 0x4104 +#define HDMI_CSC_COEF_A2_LSB 0x4105 +#define HDMI_CSC_COEF_A3_MSB 0x4106 +#define HDMI_CSC_COEF_A3_LSB 0x4107 +#define HDMI_CSC_COEF_A4_MSB 0x4108 +#define HDMI_CSC_COEF_A4_LSB 0x4109 +#define HDMI_CSC_COEF_B1_MSB 0x410A +#define HDMI_CSC_COEF_B1_LSB 0x410B +#define HDMI_CSC_COEF_B2_MSB 0x410C +#define HDMI_CSC_COEF_B2_LSB 0x410D +#define HDMI_CSC_COEF_B3_MSB 0x410E +#define HDMI_CSC_COEF_B3_LSB 0x410F +#define HDMI_CSC_COEF_B4_MSB 0x4110 +#define HDMI_CSC_COEF_B4_LSB 0x4111 +#define HDMI_CSC_COEF_C1_MSB 0x4112 +#define HDMI_CSC_COEF_C1_LSB 0x4113 +#define HDMI_CSC_COEF_C2_MSB 0x4114 +#define HDMI_CSC_COEF_C2_LSB 0x4115 +#define HDMI_CSC_COEF_C3_MSB 0x4116 +#define HDMI_CSC_COEF_C3_LSB 0x4117 +#define HDMI_CSC_COEF_C4_MSB 0x4118 +#define HDMI_CSC_COEF_C4_LSB 0x4119 + +/* I2C Master Registers (E-DDC) */ +#define HDMI_I2CM_SLAVE 0x7E00 +#define HDMI_I2CM_ADDRESS 0x7E01 +#define HDMI_I2CM_DATAO 0x7E02 +#define HDMI_I2CM_DATAI 0x7E03 +#define HDMI_I2CM_OPERATION 0x7E04 +#define HDMI_I2CM_INT 0x7E05 +#define HDMI_I2CM_CTLINT 0x7E06 +#define HDMI_I2CM_DIV 0x7E07 +#define HDMI_I2CM_SEGADDR 0x7E08 +#define HDMI_I2CM_SOFTRSTZ 0x7E09 +#define HDMI_I2CM_SEGPTR 0x7E0A +#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B +#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C +#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D +#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E +#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F +#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10 +#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11 +#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12 +#define HDMI_I2CM_BUF0 0x7E20 + +enum { + /* HDMI PHY registers define */ + PHY_OPMODE_PLLCFG = 0x06, + PHY_CKCALCTRL = 0x05, + PHY_CKSYMTXCTRL = 0x09, + PHY_VLEVCTRL = 0x0e, + PHY_PLLCURRCTRL = 0x10, + PHY_PLLPHBYCTRL = 0x13, + PHY_PLLGMPCTRL = 0x15, + PHY_PLLCLKBISTPHASE = 0x17, + PHY_TXTERM = 0x19, + + /* ih_phy_stat0 field values */ + HDMI_IH_PHY_STAT0_HPD = 0x1, + + /* ih_mute field values */ + HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, + HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, + + /* tx_invid0 field values */ + HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, + HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f, + HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, + + /* tx_instuffing field values */ + HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, + HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, + + /* vp_pr_cd field values */ + HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0, + HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f, + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, + + /* vp_stuff field values */ + HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, + HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, + HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, + HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, + HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, + HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, + HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, + HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, + + /* vp_conf field values */ + HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, + HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, + HDMI_VP_CONF_PP_EN_ENMASK = 0x20, + HDMI_VP_CONF_PP_EN_DISABLE = 0x00, + HDMI_VP_CONF_PR_EN_MASK = 0x10, + HDMI_VP_CONF_PR_EN_DISABLE = 0x00, + HDMI_VP_CONF_YCC422_EN_MASK = 0x8, + HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, + HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, + HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, + HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, + HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, + + /* vp_remap field values */ + HDMI_VP_REMAP_YCC422_16BIT = 0x0, + + /* fc_invidconf field values */ + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, + HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, + HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, + HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, + HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, + HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, + + + /* fc_aviconf0-fc_aviconf3 field values */ + HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, + HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, + HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, + HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, + HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, + HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, + HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, + HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c, + HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, + HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, + HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, + HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c, + HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, + HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, + HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, + HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, + + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, + HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0, + HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, + HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, + HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, + HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0, + + HDMI_FC_AVICONF2_SCALING_MASK = 0x03, + HDMI_FC_AVICONF2_SCALING_NONE = 0x00, + HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, + HDMI_FC_AVICONF2_SCALING_VERT = 0x02, + HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03, + HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c, + HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, + HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, + HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, + HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, + HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, + HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, + + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, + HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c, + HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, + HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, + + /* fc_gcp field values*/ + HDMI_FC_GCP_SET_AVMUTE = 0x02, + HDMI_FC_GCP_CLEAR_AVMUTE = 0x01, + + /* phy_conf0 field values */ + HDMI_PHY_CONF0_PDZ_MASK = 0x80, + HDMI_PHY_CONF0_PDZ_OFFSET = 7, + HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, + HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, + HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20, + HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5, + HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, + HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, + HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, + HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, + HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, + HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, + HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, + HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, + + /* phy_tst0 field values */ + HDMI_PHY_TST0_TSTCLR_MASK = 0x20, + HDMI_PHY_TST0_TSTCLR_OFFSET = 5, + + /* phy_stat0 field values */ + HDMI_PHY_HPD = 0x02, + HDMI_PHY_TX_PHY_LOCK = 0x01, + + /* phy_i2cm_slave_addr field values */ + HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, + + /* phy_i2cm_operation_addr field values */ + HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, + + /* hdmi_phy_i2cm_int_addr */ + HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, + + /* hdmi_phy_i2cm_ctlint_addr */ + HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, + + /* aud_conf0 field values */ + HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80, + HDMI_AUD_CONF0_I2S_SELECT = 0x20, + HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01, + HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02, + HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04, + HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08, + + /* aud_conf0 field values */ + HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0, + HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10, + + /* aud_n3 field values */ + HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80, + HDMI_AUD_N3_AUDN19_16_MASK = 0x0f, + + /* aud_cts3 field values */ + HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, + HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, + HDMI_AUD_CTS3_N_SHIFT_1 = 0, + HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, + HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, + HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, + HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, + HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, + HDMI_AUD_CTS3_CTS_MANUAL = 0x10, + HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, + + /* aud_inputclkfs filed values */ + HDMI_AUD_INPUTCLKFS_128 = 0x0, + + /* mc_clkdis field values */ + HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40, + HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20, + HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10, + HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, + HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4, + HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, + HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, + + /* mc_swrstz field values */ + HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08, + HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, + + /* mc_flowctrl field values */ + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, + + /* mc_phyrstz field values */ + HDMI_MC_PHYRSTZ_ASSERT = 0x0, + HDMI_MC_PHYRSTZ_DEASSERT = 0x1, + + /* mc_heacphy_rst field values */ + HDMI_MC_HEACPHY_RST_ASSERT = 0x1, + + /* i2cm filed values */ + HDMI_I2CM_SLAVE_DDC_ADDR = 0x50, + HDMI_I2CM_SEGADDR_DDC = 0x30, + HDMI_I2CM_OP_RD8_EXT = 0x2, + HDMI_I2CM_OP_RD8 = 0x1, + HDMI_I2CM_DIV_FAST_STD_MODE = 0x8, + HDMI_I2CM_DIV_FAST_MODE = 0x8, + HDMI_I2CM_DIV_STD_MODE = 0x0, + HDMI_I2CM_SOFTRSTZ_MASK = 0x1, + + /* CSC_CFG field values */ + HDMI_CSC_CFG_INTMODE_MASK = 0x30, + HDMI_CSC_CFG_INTMODE_OFFSET = 4, + HDMI_CSC_CFG_INTMODE_DISABLE = 0x00, + HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10, + HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20, + HDMI_CSC_CFG_DECMODE_MASK = 0x3, + HDMI_CSC_CFG_DECMODE_OFFSET = 0, + HDMI_CSC_CFG_DECMODE_DISABLE = 0x0, + HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1, + HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2, + HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3, + + /* CSC_SCALE field values */ + HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70, + HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03, +}; + +struct hdmi_mpll_config { + u64 mpixelclock; + /* Mode of Operation and PLL Dividers Control Register */ + u32 cpce; + /* PLL Gmp Control Register */ + u32 gmp; + /* PLL Current Control Register */ + u32 curr; +}; + +struct hdmi_phy_config { + u64 mpixelclock; + u32 sym_ctr; /* clock symbol and transmitter control */ + u32 term; /* transmission termination value */ + u32 vlev_ctr; /* voltage level control */ +}; + +struct hdmi_vmode { + bool mdataenablepolarity; + + unsigned int mpixelclock; + unsigned int mpixelrepetitioninput; + unsigned int mpixelrepetitionoutput; +}; + +struct hdmi_data_info { + unsigned int enc_in_bus_format; + unsigned int enc_out_bus_format; + unsigned int enc_in_encoding; + unsigned int enc_out_encoding; + unsigned int pix_repet_factor; + unsigned int hdcp_enable; + struct hdmi_vmode video_mode; +}; + +struct dw_hdmi { + ulong ioaddr; + const struct hdmi_mpll_config *mpll_cfg; + const struct hdmi_phy_config *phy_cfg; + u8 i2c_clk_high; + u8 i2c_clk_low; + u8 reg_io_width; + struct hdmi_data_info hdmi_data; + struct udevice *ddc_bus; + + int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); + void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset); + u8 (*read_reg)(struct dw_hdmi *hdmi, int offset); +}; + +int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock); +int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi); +void dw_hdmi_phy_init(struct dw_hdmi *hdmi); + +int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid); +int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size); +void dw_hdmi_init(struct dw_hdmi *hdmi); + +#endif diff --git a/roms/u-boot/include/dwc3-omap-uboot.h b/roms/u-boot/include/dwc3-omap-uboot.h new file mode 100644 index 000000000..7c982e379 --- /dev/null +++ b/roms/u-boot/include/dwc3-omap-uboot.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* include/dwc3_omap_uboot.h + * + * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com + * + * Designware SuperSpeed OMAP Glue uboot init + */ + +#ifndef __DWC3_OMAP_UBOOT_H_ +#define __DWC3_OMAP_UBOOT_H_ + +#include + +enum omap_dwc3_vbus_id_status { + OMAP_DWC3_ID_FLOAT, + OMAP_DWC3_ID_GROUND, + OMAP_DWC3_VBUS_OFF, + OMAP_DWC3_VBUS_VALID, +}; + +struct dwc3_omap_device { + void *base; + int index; + enum dwc3_omap_utmi_mode utmi_mode; + enum omap_dwc3_vbus_id_status vbus_id_status; +}; + +int dwc3_omap_uboot_init(struct dwc3_omap_device *dev); +void dwc3_omap_uboot_exit(int index); +int dwc3_omap_uboot_interrupt_status(int index); +#endif /* __DWC3_OMAP_UBOOT_H_ */ diff --git a/roms/u-boot/include/dwc3-sti-glue.h b/roms/u-boot/include/dwc3-sti-glue.h new file mode 100644 index 000000000..546ffbaf7 --- /dev/null +++ b/roms/u-boot/include/dwc3-sti-glue.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, for STMicroelectronics. + */ + +#ifndef __DWC3_STI_UBOOT_H_ +#define __DWC3_STI_UBOOT_H_ + +/* glue registers */ +#include +#define CLKRST_CTRL 0x00 +#define AUX_CLK_EN BIT(0) +#define SW_PIPEW_RESET_N BIT(4) +#define EXT_CFG_RESET_N BIT(8) + +#define XHCI_REVISION BIT(12) + +#define USB2_VBUS_MNGMNT_SEL1 0x2C +#define USB2_VBUS_UTMIOTG 0x1 + +#define SEL_OVERRIDE_VBUSVALID(n) ((n) << 0) +#define SEL_OVERRIDE_POWERPRESENT(n) ((n) << 4) +#define SEL_OVERRIDE_BVALID(n) ((n) << 8) + +/* Static DRD configuration */ +#define USB3_CONTROL_MASK 0xf77 + +#define USB3_DEVICE_NOT_HOST BIT(0) +#define USB3_FORCE_VBUSVALID BIT(1) +#define USB3_DELAY_VBUSVALID BIT(2) +#define USB3_SEL_FORCE_OPMODE BIT(4) +#define USB3_FORCE_OPMODE(n) ((n) << 5) +#define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8) +#define USB3_FORCE_DPPULLDOWN2 BIT(9) +#define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10) +#define USB3_FORCE_DMPULLDOWN2 BIT(11) + +int sti_dwc3_init(enum usb_dr_mode mode); + +#endif /* __DWC3_STI_UBOOT_H_ */ diff --git a/roms/u-boot/include/dwc3-uboot.h b/roms/u-boot/include/dwc3-uboot.h new file mode 100644 index 000000000..e08530ec4 --- /dev/null +++ b/roms/u-boot/include/dwc3-uboot.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* include/dwc3-uboot.h + * + * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com + * + * Designware SuperSpeed USB uboot init + */ + +#ifndef __DWC3_UBOOT_H_ +#define __DWC3_UBOOT_H_ + +#include +#include +#include + +struct dwc3_device { + unsigned long base; + enum usb_dr_mode dr_mode; + enum usb_phy_interface hsphy_mode; + u32 maximum_speed; + unsigned tx_fifo_resize:1; + unsigned has_lpm_erratum; + u8 lpm_nyet_threshold; + unsigned is_utmi_l1_suspend; + u8 hird_threshold; + unsigned disable_scramble_quirk; + unsigned u2exit_lfps_quirk; + unsigned u2ss_inp3_quirk; + unsigned req_p1p2p3_quirk; + unsigned del_p1p2p3_quirk; + unsigned del_phy_power_chg_quirk; + unsigned lfps_filter_quirk; + unsigned rx_detect_poll_quirk; + unsigned dis_u3_susphy_quirk; + unsigned dis_u2_susphy_quirk; + unsigned dis_del_phy_power_chg_quirk; + unsigned dis_tx_ipgap_linecheck_quirk; + unsigned dis_enblslpm_quirk; + unsigned dis_u2_freeclk_exists_quirk; + unsigned tx_de_emphasis_quirk; + unsigned tx_de_emphasis; + int index; +}; + +int dwc3_uboot_init(struct dwc3_device *dev); +void dwc3_uboot_exit(int index); +void dwc3_uboot_handle_interrupt(int index); + +struct phy; +#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB) +int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys); +int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys); +#else +static inline int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys) +{ + return -ENOTSUPP; +} + +static inline int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys) +{ + return -ENOTSUPP; +} +#endif + +#endif /* __DWC3_UBOOT_H_ */ diff --git a/roms/u-boot/include/dwc_ahsata.h b/roms/u-boot/include/dwc_ahsata.h new file mode 100644 index 000000000..2aa93427f --- /dev/null +++ b/roms/u-boot/include/dwc_ahsata.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 Google, Inc + * Written by Simon Glass + */ + +#ifndef __DWC_AHSATA_H__ +#define __DWC_AHSATA_H__ + +int dwc_ahsata_bus_reset(struct udevice *dev); +int dwc_ahsata_probe(struct udevice *dev); +int dwc_ahsata_scan(struct udevice *dev); +int dwc_ahsata_port_status(struct udevice *dev, int port); + +#endif diff --git a/roms/u-boot/include/dwmmc.h b/roms/u-boot/include/dwmmc.h new file mode 100644 index 000000000..5fc8ed839 --- /dev/null +++ b/roms/u-boot/include/dwmmc.h @@ -0,0 +1,311 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Jaehoon Chung + */ + +#ifndef __DWMMC_HW_H +#define __DWMMC_HW_H + +#include +#include +#include +#include + +#define DWMCI_CTRL 0x000 +#define DWMCI_PWREN 0x004 +#define DWMCI_CLKDIV 0x008 +#define DWMCI_CLKSRC 0x00C +#define DWMCI_CLKENA 0x010 +#define DWMCI_TMOUT 0x014 +#define DWMCI_CTYPE 0x018 +#define DWMCI_BLKSIZ 0x01C +#define DWMCI_BYTCNT 0x020 +#define DWMCI_INTMASK 0x024 +#define DWMCI_CMDARG 0x028 +#define DWMCI_CMD 0x02C +#define DWMCI_RESP0 0x030 +#define DWMCI_RESP1 0x034 +#define DWMCI_RESP2 0x038 +#define DWMCI_RESP3 0x03C +#define DWMCI_MINTSTS 0x040 +#define DWMCI_RINTSTS 0x044 +#define DWMCI_STATUS 0x048 +#define DWMCI_FIFOTH 0x04C +#define DWMCI_CDETECT 0x050 +#define DWMCI_WRTPRT 0x054 +#define DWMCI_GPIO 0x058 +#define DWMCI_TCMCNT 0x05C +#define DWMCI_TBBCNT 0x060 +#define DWMCI_DEBNCE 0x064 +#define DWMCI_USRID 0x068 +#define DWMCI_VERID 0x06C +#define DWMCI_HCON 0x070 +#define DWMCI_UHS_REG 0x074 +#define DWMCI_BMOD 0x080 +#define DWMCI_PLDMND 0x084 +#define DWMCI_DBADDR 0x088 +#define DWMCI_IDSTS 0x08C +#define DWMCI_IDINTEN 0x090 +#define DWMCI_DSCADDR 0x094 +#define DWMCI_BUFADDR 0x098 +#define DWMCI_DATA 0x200 + +/* Interrupt Mask register */ +#define DWMCI_INTMSK_ALL 0xffffffff +#define DWMCI_INTMSK_RE (1 << 1) +#define DWMCI_INTMSK_CDONE (1 << 2) +#define DWMCI_INTMSK_DTO (1 << 3) +#define DWMCI_INTMSK_TXDR (1 << 4) +#define DWMCI_INTMSK_RXDR (1 << 5) +#define DWMCI_INTMSK_RCRC (1 << 6) +#define DWMCI_INTMSK_DCRC (1 << 7) +#define DWMCI_INTMSK_RTO (1 << 8) +#define DWMCI_INTMSK_DRTO (1 << 9) +#define DWMCI_INTMSK_HTO (1 << 10) +#define DWMCI_INTMSK_FRUN (1 << 11) +#define DWMCI_INTMSK_HLE (1 << 12) +#define DWMCI_INTMSK_SBE (1 << 13) +#define DWMCI_INTMSK_ACD (1 << 14) +#define DWMCI_INTMSK_EBE (1 << 15) + +/* Raw interrupt Regsiter */ +#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\ + DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC) +#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO) +/* CTRL register */ +#define DWMCI_CTRL_RESET (1 << 0) +#define DWMCI_CTRL_FIFO_RESET (1 << 1) +#define DWMCI_CTRL_DMA_RESET (1 << 2) +#define DWMCI_DMA_EN (1 << 5) +#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10) +#define DWMCI_IDMAC_EN (1 << 25) +#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\ + DWMCI_CTRL_DMA_RESET) + +/* CMD register */ +#define DWMCI_CMD_RESP_EXP (1 << 6) +#define DWMCI_CMD_RESP_LENGTH (1 << 7) +#define DWMCI_CMD_CHECK_CRC (1 << 8) +#define DWMCI_CMD_DATA_EXP (1 << 9) +#define DWMCI_CMD_RW (1 << 10) +#define DWMCI_CMD_SEND_STOP (1 << 12) +#define DWMCI_CMD_ABORT_STOP (1 << 14) +#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13) +#define DWMCI_CMD_UPD_CLK (1 << 21) +#define DWMCI_CMD_USE_HOLD_REG (1 << 29) +#define DWMCI_CMD_START (1 << 31) + +/* CLKENA register */ +#define DWMCI_CLKEN_ENABLE (1 << 0) +#define DWMCI_CLKEN_LOW_PWR (1 << 16) + +/* Card-type registe */ +#define DWMCI_CTYPE_1BIT 0 +#define DWMCI_CTYPE_4BIT (1 << 0) +#define DWMCI_CTYPE_8BIT (1 << 16) + +/* Status Register */ +#define DWMCI_FIFO_EMPTY (1 << 2) +#define DWMCI_FIFO_FULL (1 << 3) +#define DWMCI_BUSY (1 << 9) +#define DWMCI_FIFO_MASK 0x1fff +#define DWMCI_FIFO_SHIFT 17 + +/* FIFOTH Register */ +#define MSIZE(x) ((x) << 28) +#define RX_WMARK(x) ((x) << 16) +#define TX_WMARK(x) (x) +#define RX_WMARK_SHIFT 16 +#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT) + +#define DWMCI_IDMAC_OWN (1 << 31) +#define DWMCI_IDMAC_CH (1 << 4) +#define DWMCI_IDMAC_FS (1 << 3) +#define DWMCI_IDMAC_LD (1 << 2) + +/* Bus Mode Register */ +#define DWMCI_BMOD_IDMAC_RESET (1 << 0) +#define DWMCI_BMOD_IDMAC_FB (1 << 1) +#define DWMCI_BMOD_IDMAC_EN (1 << 7) + +/* UHS register */ +#define DWMCI_DDR_MODE (1 << 16) + +/* Internal IDMAC interrupt defines */ +#define DWMCI_IDINTEN_RI BIT(1) +#define DWMCI_IDINTEN_TI BIT(0) + +#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | \ + DWMCI_IDINTEN_RI) + +/* quirks */ +#define DWMCI_QUIRK_DISABLE_SMU (1 << 0) + +/** + * struct dwmci_host - Information about a designware MMC host + * + * @name: Device name + * @ioaddr: Base I/O address of controller + * @quirks: Quick flags - see DWMCI_QUIRK_... + * @caps: Capabilities - see MMC_MODE_... + * @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL + * @div: Arbitrary clock divider value for use by controller + * @dev_index: Arbitrary device index for use by controller + * @dev_id: Arbitrary device ID for use by controller + * @buswidth: Bus width in bits (8 or 4) + * @fifoth_val: Value for FIFOTH register (or 0 to leave unset) + * @mmc: Pointer to generic MMC structure for this device + * @priv: Private pointer for use by controller + */ +struct dwmci_host { + const char *name; + void *ioaddr; + unsigned int quirks; + unsigned int caps; + unsigned int version; + unsigned int clock; + unsigned int bus_hz; + unsigned int div; + int dev_index; + int dev_id; + int buswidth; + u32 fifoth_val; + struct mmc *mmc; + void *priv; + + int (*clksel)(struct dwmci_host *host); + void (*board_init)(struct dwmci_host *host); + + /** + * Get / set a particular MMC clock frequency + * + * This is used to request the current clock frequency of the clock + * that drives the DWMMC peripheral. The caller will then use this + * information to work out the divider it needs to achieve the + * required MMC bus clock frequency. If you want to handle the + * clock external to DWMMC, use @freq to select the frequency and + * return that value too. Then DWMMC will put itself in bypass mode. + * + * @host: DWMMC host + * @freq: Frequency the host is trying to achieve + */ + unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq); +#ifndef CONFIG_BLK + struct mmc_config cfg; +#endif + + /* use fifo mode to read and write data */ + bool fifo_mode; +}; + +struct dwmci_idmac { + u32 flags; + u32 cnt; + u32 addr; + u32 next_addr; +} __aligned(ARCH_DMA_MINALIGN); + +static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val) +{ + writel(val, host->ioaddr + reg); +} + +static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val) +{ + writew(val, host->ioaddr + reg); +} + +static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val) +{ + writeb(val, host->ioaddr + reg); +} +static inline u32 dwmci_readl(struct dwmci_host *host, int reg) +{ + return readl(host->ioaddr + reg); +} + +static inline u16 dwmci_readw(struct dwmci_host *host, int reg) +{ + return readw(host->ioaddr + reg); +} + +static inline u8 dwmci_readb(struct dwmci_host *host, int reg) +{ + return readb(host->ioaddr + reg); +} + +#ifdef CONFIG_BLK +/** + * dwmci_setup_cfg() - Set up the configuration for DWMMC + * + * This is used to set up a DWMMC device when you are using CONFIG_BLK. + * + * This should be called from your MMC driver's probe() method once you have + * the information required. + * + * Generally your driver will have a platform data structure which holds both + * the configuration (struct mmc_config) and the MMC device info (struct mmc). + * For example: + * + * struct rockchip_mmc_plat { + * struct mmc_config cfg; + * struct mmc mmc; + * }; + * + * ... + * + * Inside U_BOOT_DRIVER(): + * .plat_auto = sizeof(struct rockchip_mmc_plat), + * + * To access platform data: + * struct rockchip_mmc_plat *plat = dev_get_plat(dev); + * + * See rockchip_dw_mmc.c for an example. + * + * @cfg: Configuration structure to fill in (generally &plat->mmc) + * @host: DWMMC host + * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) + * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) + */ +void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, + u32 max_clk, u32 min_clk); + +/** + * dwmci_bind() - Set up a new MMC block device + * + * This is used to set up a DWMMC block device when you are using CONFIG_BLK. + * It should be called from your driver's bind() method. + * + * See rockchip_dw_mmc.c for an example. + * + * @dev: Device to set up + * @mmc: Pointer to mmc structure (normally &plat->mmc) + * @cfg: Empty configuration structure (generally &plat->cfg). This is + * normally all zeroes at this point. The only purpose of passing + * this in is to set mmc->cfg to it. + * @return 0 if OK, -ve if the block device could not be created + */ +int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); + +#else +/** + * add_dwmci() - Add a new DWMMC interface + * + * This is used when you are not using CONFIG_BLK. Convert your driver over! + * + * @host: DWMMC host structure + * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) + * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) + * @return 0 if OK, -ve on error + */ +int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk); +#endif /* !CONFIG_BLK */ + +#ifdef CONFIG_DM_MMC +/* Export the operations to drivers */ +int dwmci_probe(struct udevice *dev); +extern const struct dm_mmc_ops dm_dwmci_ops; +#endif + +#endif /* __DWMMC_HW_H */ diff --git a/roms/u-boot/include/e500.h b/roms/u-boot/include/e500.h new file mode 100644 index 000000000..255f46bf1 --- /dev/null +++ b/roms/u-boot/include/e500.h @@ -0,0 +1,47 @@ +/* + * Copyright 2003 Motorola,Inc. + * Xianghua Xiao(x.xiao@motorola.com) + */ + +#ifndef __E500_H__ +#define __E500_H__ + +#ifndef __ASSEMBLY__ + +typedef struct +{ + unsigned long freq_processor[CONFIG_MAX_CPUS]; +#ifdef CONFIG_HETROGENOUS_CLUSTERS + unsigned long freq_processor_dsp[CONFIG_MAX_DSP_CPUS]; +#endif + unsigned long freq_systembus; + unsigned long freq_ddrbus; + unsigned long freq_localbus; + unsigned long freq_qe; +#ifdef CONFIG_SYS_DPAA_FMAN + unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; +#endif +#ifdef CONFIG_SYS_DPAA_QBMAN + unsigned long freq_qman; +#endif +#ifdef CONFIG_SYS_DPAA_PME + unsigned long freq_pme; +#endif +#ifdef CONFIG_SYS_CPRI + unsigned long freq_cpri; +#endif +#ifdef CONFIG_SYS_MAPLE + unsigned long freq_maple; + unsigned long freq_maple_ulb; + unsigned long freq_maple_etvpe; +#endif +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + unsigned char diff_sysclk; +#endif +} MPC85xx_SYS_INFO; + +#endif /* _ASMLANGUAGE */ + +#define RESET_VECTOR 0xfffffffc + +#endif /* __E500_H__ */ diff --git a/roms/u-boot/include/ec_commands.h b/roms/u-boot/include/ec_commands.h new file mode 100644 index 000000000..36f4a02f9 --- /dev/null +++ b/roms/u-boot/include/ec_commands.h @@ -0,0 +1,4642 @@ +/* Copyright (c) 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Host communication command constants for Chrome EC */ + +#ifndef __CROS_EC_COMMANDS_H +#define __CROS_EC_COMMANDS_H + +/* + * Protocol overview + * + * request: CMD [ P0 P1 P2 ... Pn S ] + * response: ERR [ P0 P1 P2 ... Pn S ] + * + * where the bytes are defined as follow : + * - CMD is the command code. (defined by EC_CMD_ constants) + * - ERR is the error code. (defined by EC_RES_ constants) + * - Px is the optional payload. + * it is not sent if the error code is not success. + * (defined by ec_params_ and ec_response_ structures) + * - S is the checksum which is the sum of all payload bytes. + * + * On LPC, CMD and ERR are sent/received at EC_LPC_ADDR_KERNEL|USER_CMD + * and the payloads are sent/received at EC_LPC_ADDR_KERNEL|USER_PARAM. + * On I2C, all bytes are sent serially in the same message. + */ + +/* + * Current version of this protocol + * + * TODO(crosbug.com/p/11223): This is effectively useless; protocol is + * determined in other ways. Remove this once the kernel code no longer + * depends on it. + */ +#define EC_PROTO_VERSION 0x00000002 + +/* Command version mask */ +#define EC_VER_MASK(version) (1UL << (version)) + +/* I/O addresses for ACPI commands */ +#define EC_LPC_ADDR_ACPI_DATA 0x62 +#define EC_LPC_ADDR_ACPI_CMD 0x66 + +/* I/O addresses for host command */ +#define EC_LPC_ADDR_HOST_DATA 0x200 +#define EC_LPC_ADDR_HOST_CMD 0x204 + +/* I/O addresses for host command args and params */ +/* Protocol version 2 */ +#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */ +#define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is + * EC_PROTO2_MAX_PARAM_SIZE */ +/* Protocol version 3 */ +#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */ +#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */ + +/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff + * and they tell the kernel that so we have to think of it as two parts. */ +#define EC_HOST_CMD_REGION0 0x800 +#define EC_HOST_CMD_REGION1 0x880 +#define EC_HOST_CMD_REGION_SIZE 0x80 + +/* EC command register bit functions */ +#define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */ +#define EC_LPC_CMDR_PENDING (1 << 1) /* Write pending to EC */ +#define EC_LPC_CMDR_BUSY (1 << 2) /* EC is busy processing a command */ +#define EC_LPC_CMDR_CMD (1 << 3) /* Last host write was a command */ +#define EC_LPC_CMDR_ACPI_BRST (1 << 4) /* Burst mode (not used) */ +#define EC_LPC_CMDR_SCI (1 << 5) /* SCI event is pending */ +#define EC_LPC_CMDR_SMI (1 << 6) /* SMI event is pending */ + +/* MEC uses 0x800/0x804 as register/index pair, thus an 8-byte resource */ +#define MEC_EMI_BASE 0x800 +#define MEC_EMI_SIZE 8 + +#define EC_LPC_ADDR_MEMMAP 0x900 +#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */ +#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */ + +/* The offset address of each type of data in mapped memory. */ +#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */ +#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */ +#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */ +#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */ +#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */ +#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */ +#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */ +#define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */ +#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */ +#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */ +/* Unused 0x28 - 0x2f */ +#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */ +/* Unused 0x31 - 0x33 */ +#define EC_MEMMAP_HOST_EVENTS 0x34 /* 32 bits */ +/* Reserve 0x38 - 0x3f for additional host event-related stuff */ +/* Battery values are all 32 bits */ +#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */ +#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */ +#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */ +#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, defined below */ +#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */ +#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */ +#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */ +#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */ +/* Strings are all 8 bytes (EC_MEMMAP_TEXT_MAX) */ +#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */ +#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */ +#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */ +#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */ +#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */ +/* Unused 0x84 - 0x8f */ +#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/ +/* Unused 0x91 */ +#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometers data 0x92 - 0x9f */ +/* 0x92: Lid Angle if available, LID_ANGLE_UNRELIABLE otherwise */ +/* 0x94 - 0x99: 1st Accelerometer */ +/* 0x9a - 0x9f: 2nd Accelerometer */ +#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */ +/* Unused 0xa6 - 0xdf */ + +/* + * ACPI is unable to access memory mapped data at or above this offset due to + * limitations of the ACPI protocol. Do not place data in the range 0xe0 - 0xfe + * which might be needed by ACPI. + */ +#define EC_MEMMAP_NO_ACPI 0xe0 + +/* Define the format of the accelerometer mapped memory status byte. */ +#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f +#define EC_MEMMAP_ACC_STATUS_BUSY_BIT (1 << 4) +#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT (1 << 7) + +/* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */ +#define EC_TEMP_SENSOR_ENTRIES 16 +/* + * Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B. + * + * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2. + */ +#define EC_TEMP_SENSOR_B_ENTRIES 8 + +/* Special values for mapped temperature sensors */ +#define EC_TEMP_SENSOR_NOT_PRESENT 0xff +#define EC_TEMP_SENSOR_ERROR 0xfe +#define EC_TEMP_SENSOR_NOT_POWERED 0xfd +#define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc +/* + * The offset of temperature value stored in mapped memory. This allows + * reporting a temperature range of 200K to 454K = -73C to 181C. + */ +#define EC_TEMP_SENSOR_OFFSET 200 + +/* + * Number of ALS readings at EC_MEMMAP_ALS + */ +#define EC_ALS_ENTRIES 2 + +/* + * The default value a temperature sensor will return when it is present but + * has not been read this boot. This is a reasonable number to avoid + * triggering alarms on the host. + */ +#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET) + +#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */ +#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */ +#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */ + +/* Battery bit flags at EC_MEMMAP_BATT_FLAG. */ +#define EC_BATT_FLAG_AC_PRESENT 0x01 +#define EC_BATT_FLAG_BATT_PRESENT 0x02 +#define EC_BATT_FLAG_DISCHARGING 0x04 +#define EC_BATT_FLAG_CHARGING 0x08 +#define EC_BATT_FLAG_LEVEL_CRITICAL 0x10 + +/* Switch flags at EC_MEMMAP_SWITCHES */ +#define EC_SWITCH_LID_OPEN 0x01 +#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 +#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04 +/* Was recovery requested via keyboard; now unused. */ +#define EC_SWITCH_IGNORE1 0x08 +/* Recovery requested via dedicated signal (from servo board) */ +#define EC_SWITCH_DEDICATED_RECOVERY 0x10 +/* Was fake developer mode switch; now unused. Remove in next refactor. */ +#define EC_SWITCH_IGNORE0 0x20 + +/* Host command interface flags */ +/* Host command interface supports LPC args (LPC interface only) */ +#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01 +/* Host command interface supports version 3 protocol */ +#define EC_HOST_CMD_FLAG_VERSION_3 0x02 + +/* Wireless switch flags */ +#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */ +#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */ +#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */ +#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */ +#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */ + +/*****************************************************************************/ +/* + * ACPI commands + * + * These are valid ONLY on the ACPI command/data port. + */ + +/* + * ACPI Read Embedded Controller + * + * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*). + * + * Use the following sequence: + * + * - Write EC_CMD_ACPI_READ to EC_LPC_ADDR_ACPI_CMD + * - Wait for EC_LPC_CMDR_PENDING bit to clear + * - Write address to EC_LPC_ADDR_ACPI_DATA + * - Wait for EC_LPC_CMDR_DATA bit to set + * - Read value from EC_LPC_ADDR_ACPI_DATA + */ +#define EC_CMD_ACPI_READ 0x0080 + +/* + * ACPI Write Embedded Controller + * + * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*). + * + * Use the following sequence: + * + * - Write EC_CMD_ACPI_WRITE to EC_LPC_ADDR_ACPI_CMD + * - Wait for EC_LPC_CMDR_PENDING bit to clear + * - Write address to EC_LPC_ADDR_ACPI_DATA + * - Wait for EC_LPC_CMDR_PENDING bit to clear + * - Write value to EC_LPC_ADDR_ACPI_DATA + */ +#define EC_CMD_ACPI_WRITE 0x0081 + +/* + * ACPI Burst Enable Embedded Controller + * + * This enables burst mode on the EC to allow the host to issue several + * commands back-to-back. While in this mode, writes to mapped multi-byte + * data are locked out to ensure data consistency. + */ +#define EC_CMD_ACPI_BURST_ENABLE 0x0082 + +/* + * ACPI Burst Disable Embedded Controller + * + * This disables burst mode on the EC and stops preventing EC writes to mapped + * multi-byte data. + */ +#define EC_CMD_ACPI_BURST_DISABLE 0x0083 + +/* + * ACPI Query Embedded Controller + * + * This clears the lowest-order bit in the currently pending host events, and + * sets the result code to the 1-based index of the bit (event 0x00000001 = 1, + * event 0x80000000 = 32), or 0 if no event was pending. + */ +#define EC_CMD_ACPI_QUERY_EVENT 0x0084 + +/* Valid addresses in ACPI memory space, for read/write commands */ + +/* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */ +#define EC_ACPI_MEM_VERSION 0x00 +/* + * Test location; writing value here updates test compliment byte to (0xff - + * value). + */ +#define EC_ACPI_MEM_TEST 0x01 +/* Test compliment; writes here are ignored. */ +#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 + +/* Keyboard backlight brightness percent (0 - 100) */ +#define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03 +/* DPTF Target Fan Duty (0-100, 0xff for auto/none) */ +#define EC_ACPI_MEM_FAN_DUTY 0x04 + +/* + * DPTF temp thresholds. Any of the EC's temp sensors can have up to two + * independent thresholds attached to them. The current value of the ID + * register determines which sensor is affected by the THRESHOLD and COMMIT + * registers. The THRESHOLD register uses the same EC_TEMP_SENSOR_OFFSET scheme + * as the memory-mapped sensors. The COMMIT register applies those settings. + * + * The spec does not mandate any way to read back the threshold settings + * themselves, but when a threshold is crossed the AP needs a way to determine + * which sensor(s) are responsible. Each reading of the ID register clears and + * returns one sensor ID that has crossed one of its threshold (in either + * direction) since the last read. A value of 0xFF means "no new thresholds + * have tripped". Setting or enabling the thresholds for a sensor will clear + * the unread event count for that sensor. + */ +#define EC_ACPI_MEM_TEMP_ID 0x05 +#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06 +#define EC_ACPI_MEM_TEMP_COMMIT 0x07 +/* + * Here are the bits for the COMMIT register: + * bit 0 selects the threshold index for the chosen sensor (0/1) + * bit 1 enables/disables the selected threshold (0 = off, 1 = on) + * Each write to the commit register affects one threshold. + */ +#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK (1 << 0) +#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK (1 << 1) +/* + * Example: + * + * Set the thresholds for sensor 2 to 50 C and 60 C: + * write 2 to [0x05] -- select temp sensor 2 + * write 0x7b to [0x06] -- C_TO_K(50) - EC_TEMP_SENSOR_OFFSET + * write 0x2 to [0x07] -- enable threshold 0 with this value + * write 0x85 to [0x06] -- C_TO_K(60) - EC_TEMP_SENSOR_OFFSET + * write 0x3 to [0x07] -- enable threshold 1 with this value + * + * Disable the 60 C threshold, leaving the 50 C threshold unchanged: + * write 2 to [0x05] -- select temp sensor 2 + * write 0x1 to [0x07] -- disable threshold 1 + */ + +/* DPTF battery charging current limit */ +#define EC_ACPI_MEM_CHARGING_LIMIT 0x08 + +/* Charging limit is specified in 64 mA steps */ +#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64 +/* Value to disable DPTF battery charging limit */ +#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff + +/* + * Report device orientation + * bit 0 device is tablet mode + */ +#define EC_ACPI_MEM_DEVICE_ORIENTATION 0x09 +#define EC_ACPI_MEM_DEVICE_TABLET_MODE 0x01 + +/* + * ACPI addresses 0x20 - 0xff map to EC_MEMMAP offset 0x00 - 0xdf. This data + * is read-only from the AP. Added in EC_ACPI_MEM_VERSION 2. + */ +#define EC_ACPI_MEM_MAPPED_BEGIN 0x20 +#define EC_ACPI_MEM_MAPPED_SIZE 0xe0 + +/* Current version of ACPI memory address space */ +#define EC_ACPI_MEM_VERSION_CURRENT 2 + + +/* + * This header file is used in coreboot both in C and ACPI code. The ACPI code + * is pre-processed to handle constants but the ASL compiler is unable to + * handle actual C code so keep it separate. + */ +#ifndef __ACPI__ + +/* + * Define __packed if someone hasn't beat us to it. Linux kernel style + * checking prefers __packed over __attribute__((packed)). + */ +#ifndef __packed +#define __packed __attribute__((packed)) +#endif + +#ifndef __aligned +#define __aligned(x) __attribute__((aligned(x))) +#endif + +/* + * Attributes for EC request and response packets. Just defining __packed + * results in inefficient assembly code on ARM, if the structure is actually + * 32-bit aligned, as it should be for all buffers. + * + * Be very careful when adding these to existing structures. They will round + * up the structure size to the specified boundary. + * + * Also be very careful to make that if a structure is included in some other + * parent structure that the alignment will still be true given the packing of + * the parent structure. This is particularly important if the sub-structure + * will be passed as a pointer to another function, since that function will + * not know about the misaligment caused by the parent structure's packing. + * + * Also be very careful using __packed - particularly when nesting non-packed + * structures inside packed ones. In fact, DO NOT use __packed directly; + * always use one of these attributes. + * + * Once everything is annotated properly, the following search strings should + * not return ANY matches in this file other than right here: + * + * "__packed" - generates inefficient code; all sub-structs must also be packed + * + * "struct [^_]" - all structs should be annotated, except for structs that are + * members of other structs/unions (and their original declarations should be + * annotated). + */ +#ifdef CONFIG_HOSTCMD_ALIGNED + +/* + * Packed structures where offset and size are always aligned to 1, 2, or 4 + * byte boundary. + */ +#define __ec_align1 __packed +#define __ec_align2 __packed __aligned(2) +#define __ec_align4 __packed __aligned(4) + +/* + * Packed structure which must be under-aligned, because its size is not a + * 4-byte multiple. This is sub-optimal because it forces byte-wise access + * of all multi-byte fields in it, even though they are themselves aligned. + * + * In theory, we could duplicate the structure with __aligned(4) for accessing + * its members, but use the __packed version for sizeof(). + */ +#define __ec_align_size1 __packed + +/* + * Packed structure which must be under-aligned, because its offset inside a + * parent structure is not a 4-byte multiple. + */ +#define __ec_align_offset1 __packed +#define __ec_align_offset2 __packed __aligned(2) + +/* + * Structures which are complicated enough that I'm skipping them on the first + * pass. They are effectively unchanged from their previous definitions. + * + * TODO(rspangler): Figure out what to do with these. It's likely necessary + * to work out the size and offset of each member and add explicit padding to + * maintain those. + */ +#define __ec_todo_packed __packed +#define __ec_todo_unpacked + +#else /* !CONFIG_HOSTCMD_ALIGNED */ + +/* + * Packed structures make no assumption about alignment, so they do inefficient + * byte-wise reads. + */ +#define __ec_align1 __packed +#define __ec_align2 __packed +#define __ec_align4 __packed +#define __ec_align_size1 __packed +#define __ec_align_offset1 __packed +#define __ec_align_offset2 __packed +#define __ec_todo_packed __packed +#define __ec_todo_unpacked + +#endif /* !CONFIG_HOSTCMD_ALIGNED */ + +/* LPC command status byte masks */ +/* EC has written a byte in the data register and host hasn't read it yet */ +#define EC_LPC_STATUS_TO_HOST 0x01 +/* Host has written a command/data byte and the EC hasn't read it yet */ +#define EC_LPC_STATUS_FROM_HOST 0x02 +/* EC is processing a command */ +#define EC_LPC_STATUS_PROCESSING 0x04 +/* Last write to EC was a command, not data */ +#define EC_LPC_STATUS_LAST_CMD 0x08 +/* EC is in burst mode */ +#define EC_LPC_STATUS_BURST_MODE 0x10 +/* SCI event is pending (requesting SCI query) */ +#define EC_LPC_STATUS_SCI_PENDING 0x20 +/* SMI event is pending (requesting SMI query) */ +#define EC_LPC_STATUS_SMI_PENDING 0x40 +/* (reserved) */ +#define EC_LPC_STATUS_RESERVED 0x80 + +/* + * EC is busy. This covers both the EC processing a command, and the host has + * written a new command but the EC hasn't picked it up yet. + */ +#define EC_LPC_STATUS_BUSY_MASK \ + (EC_LPC_STATUS_FROM_HOST | EC_LPC_STATUS_PROCESSING) + +/* Host command response codes (16-bit). Note that response codes should be + * stored in a uint16_t rather than directly in a value of this type. + */ +enum ec_status { + EC_RES_SUCCESS = 0, + EC_RES_INVALID_COMMAND = 1, + EC_RES_ERROR = 2, + EC_RES_INVALID_PARAM = 3, + EC_RES_ACCESS_DENIED = 4, + EC_RES_INVALID_RESPONSE = 5, + EC_RES_INVALID_VERSION = 6, + EC_RES_INVALID_CHECKSUM = 7, + EC_RES_IN_PROGRESS = 8, /* Accepted, command in progress */ + EC_RES_UNAVAILABLE = 9, /* No response available */ + EC_RES_TIMEOUT = 10, /* We got a timeout */ + EC_RES_OVERFLOW = 11, /* Table / data overflow */ + EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */ + EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */ + EC_RES_RESPONSE_TOO_BIG = 14, /* Response was too big to handle */ + EC_RES_BUS_ERROR = 15, /* Communications bus error */ + EC_RES_BUSY = 16 /* Up but too busy. Should retry */ +}; + +/* + * Host event codes. Note these are 1-based, not 0-based, because ACPI query + * EC command uses code 0 to mean "no event pending". We explicitly specify + * each value in the enum listing so they won't change if we delete/insert an + * item or rearrange the list (it needs to be stable across platforms, not + * just within a single compiled instance). + */ +enum host_event_code { + EC_HOST_EVENT_LID_CLOSED = 1, + EC_HOST_EVENT_LID_OPEN = 2, + EC_HOST_EVENT_POWER_BUTTON = 3, + EC_HOST_EVENT_AC_CONNECTED = 4, + EC_HOST_EVENT_AC_DISCONNECTED = 5, + EC_HOST_EVENT_BATTERY_LOW = 6, + EC_HOST_EVENT_BATTERY_CRITICAL = 7, + EC_HOST_EVENT_BATTERY = 8, + EC_HOST_EVENT_THERMAL_THRESHOLD = 9, + /* Event generated by a device attached to the EC */ + EC_HOST_EVENT_DEVICE = 10, + EC_HOST_EVENT_THERMAL = 11, + EC_HOST_EVENT_USB_CHARGER = 12, + EC_HOST_EVENT_KEY_PRESSED = 13, + /* + * EC has finished initializing the host interface. The host can check + * for this event following sending a EC_CMD_REBOOT_EC command to + * determine when the EC is ready to accept subsequent commands. + */ + EC_HOST_EVENT_INTERFACE_READY = 14, + /* Keyboard recovery combo has been pressed */ + EC_HOST_EVENT_KEYBOARD_RECOVERY = 15, + + /* Shutdown due to thermal overload */ + EC_HOST_EVENT_THERMAL_SHUTDOWN = 16, + /* Shutdown due to battery level too low */ + EC_HOST_EVENT_BATTERY_SHUTDOWN = 17, + + /* Suggest that the AP throttle itself */ + EC_HOST_EVENT_THROTTLE_START = 18, + /* Suggest that the AP resume normal speed */ + EC_HOST_EVENT_THROTTLE_STOP = 19, + + /* Hang detect logic detected a hang and host event timeout expired */ + EC_HOST_EVENT_HANG_DETECT = 20, + /* Hang detect logic detected a hang and warm rebooted the AP */ + EC_HOST_EVENT_HANG_REBOOT = 21, + + /* PD MCU triggering host event */ + EC_HOST_EVENT_PD_MCU = 22, + + /* Battery Status flags have changed */ + EC_HOST_EVENT_BATTERY_STATUS = 23, + + /* EC encountered a panic, triggering a reset */ + EC_HOST_EVENT_PANIC = 24, + + /* Keyboard fastboot combo has been pressed */ + EC_HOST_EVENT_KEYBOARD_FASTBOOT = 25, + + /* EC RTC event occurred */ + EC_HOST_EVENT_RTC = 26, + + /* Emulate MKBP event */ + EC_HOST_EVENT_MKBP = 27, + + /* EC desires to change state of host-controlled USB mux */ + EC_HOST_EVENT_USB_MUX = 28, + + /* TABLET/LAPTOP mode event*/ + EC_HOST_EVENT_MODE_CHANGE = 29, + + /* Keyboard recovery combo with hardware reinitialization */ + EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT = 30, + + /* + * Reserve this last bit to indicate that at least one bit in a + * secondary host event word is set. See crbug.com/633646. + */ + EC_HOST_EVENT_EXTENDED = 31, + + /* + * The high bit of the event mask is not used as a host event code. If + * it reads back as set, then the entire event mask should be + * considered invalid by the host. This can happen when reading the + * raw event status via EC_MEMMAP_HOST_EVENTS but the LPC interface is + * not initialized on the EC, or improperly configured on the host. + */ + EC_HOST_EVENT_INVALID = 32 +}; +/* Host event mask */ +#define EC_HOST_EVENT_MASK(event_code) (1ULL << ((event_code) - 1)) + +/* Arguments at EC_LPC_ADDR_HOST_ARGS */ +struct __ec_align4 ec_lpc_host_args { + uint8_t flags; + uint8_t command_version; + uint8_t data_size; + /* + * Checksum; sum of command + flags + command_version + data_size + + * all params/response data bytes. + */ + uint8_t checksum; +}; + +/* Flags for ec_lpc_host_args.flags */ +/* + * Args are from host. Data area at EC_LPC_ADDR_HOST_PARAM contains command + * params. + * + * If EC gets a command and this flag is not set, this is an old-style command. + * Command version is 0 and params from host are at EC_LPC_ADDR_OLD_PARAM with + * unknown length. EC must respond with an old-style response (that is, + * without setting EC_HOST_ARGS_FLAG_TO_HOST). + */ +#define EC_HOST_ARGS_FLAG_FROM_HOST 0x01 +/* + * Args are from EC. Data area at EC_LPC_ADDR_HOST_PARAM contains response. + * + * If EC responds to a command and this flag is not set, this is an old-style + * response. Command version is 0 and response data from EC is at + * EC_LPC_ADDR_OLD_PARAM with unknown length. + */ +#define EC_HOST_ARGS_FLAG_TO_HOST 0x02 + +/*****************************************************************************/ +/* + * Byte codes returned by EC over SPI interface. + * + * These can be used by the AP to debug the EC interface, and to determine + * when the EC is not in a state where it will ever get around to responding + * to the AP. + * + * Example of sequence of bytes read from EC for a current good transfer: + * 1. - - AP asserts chip select (CS#) + * 2. EC_SPI_OLD_READY - AP sends first byte(s) of request + * 3. - - EC starts handling CS# interrupt + * 4. EC_SPI_RECEIVING - AP sends remaining byte(s) of request + * 5. EC_SPI_PROCESSING - EC starts processing request; AP is clocking in + * bytes looking for EC_SPI_FRAME_START + * 6. - - EC finishes processing and sets up response + * 7. EC_SPI_FRAME_START - AP reads frame byte + * 8. (response packet) - AP reads response packet + * 9. EC_SPI_PAST_END - Any additional bytes read by AP + * 10 - - AP deasserts chip select + * 11 - - EC processes CS# interrupt and sets up DMA for + * next request + * + * If the AP is waiting for EC_SPI_FRAME_START and sees any value other than + * the following byte values: + * EC_SPI_OLD_READY + * EC_SPI_RX_READY + * EC_SPI_RECEIVING + * EC_SPI_PROCESSING + * + * Then the EC found an error in the request, or was not ready for the request + * and lost data. The AP should give up waiting for EC_SPI_FRAME_START, + * because the EC is unable to tell when the AP is done sending its request. + */ + +/* + * Framing byte which precedes a response packet from the EC. After sending a + * request, the AP will clock in bytes until it sees the framing byte, then + * clock in the response packet. + */ +#define EC_SPI_FRAME_START 0xec + +/* + * Padding bytes which are clocked out after the end of a response packet. + */ +#define EC_SPI_PAST_END 0xed + +/* + * EC is ready to receive, and has ignored the byte sent by the AP. EC expects + * that the AP will send a valid packet header (starting with + * EC_COMMAND_PROTOCOL_3) in the next 32 bytes. + */ +#define EC_SPI_RX_READY 0xf8 + +/* + * EC has started receiving the request from the AP, but hasn't started + * processing it yet. + */ +#define EC_SPI_RECEIVING 0xf9 + +/* EC has received the entire request from the AP and is processing it. */ +#define EC_SPI_PROCESSING 0xfa + +/* + * EC received bad data from the AP, such as a packet header with an invalid + * length. EC will ignore all data until chip select deasserts. + */ +#define EC_SPI_RX_BAD_DATA 0xfb + +/* + * EC received data from the AP before it was ready. That is, the AP asserted + * chip select and started clocking data before the EC was ready to receive it. + * EC will ignore all data until chip select deasserts. + */ +#define EC_SPI_NOT_READY 0xfc + +/* + * EC was ready to receive a request from the AP. EC has treated the byte sent + * by the AP as part of a request packet, or (for old-style ECs) is processing + * a fully received packet but is not ready to respond yet. + */ +#define EC_SPI_OLD_READY 0xfd + +/*****************************************************************************/ + +/* + * Protocol version 2 for I2C and SPI send a request this way: + * + * 0 EC_CMD_VERSION0 + (command version) + * 1 Command number + * 2 Length of params = N + * 3..N+2 Params, if any + * N+3 8-bit checksum of bytes 0..N+2 + * + * The corresponding response is: + * + * 0 Result code (EC_RES_*) + * 1 Length of params = M + * 2..M+1 Params, if any + * M+2 8-bit checksum of bytes 0..M+1 + */ +#define EC_PROTO2_REQUEST_HEADER_BYTES 3 +#define EC_PROTO2_REQUEST_TRAILER_BYTES 1 +#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \ + EC_PROTO2_REQUEST_TRAILER_BYTES) + +#define EC_PROTO2_RESPONSE_HEADER_BYTES 2 +#define EC_PROTO2_RESPONSE_TRAILER_BYTES 1 +#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \ + EC_PROTO2_RESPONSE_TRAILER_BYTES) + +/* Parameter length was limited by the LPC interface */ +#define EC_PROTO2_MAX_PARAM_SIZE 0xfc + +/* Maximum request and response packet sizes for protocol version 2 */ +#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \ + EC_PROTO2_MAX_PARAM_SIZE) +#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \ + EC_PROTO2_MAX_PARAM_SIZE) + +/*****************************************************************************/ + +/* + * Value written to legacy command port / prefix byte to indicate protocol + * 3+ structs are being used. Usage is bus-dependent. + */ +#define EC_COMMAND_PROTOCOL_3 0xda + +#define EC_HOST_REQUEST_VERSION 3 + +/* Version 3 request from host */ +struct __ec_align4 ec_host_request { + /* Structure version (=3) + * + * EC will return EC_RES_INVALID_HEADER if it receives a header with a + * version it doesn't know how to parse. + */ + uint8_t struct_version; + + /* + * Checksum of request and data; sum of all bytes including checksum + * should total to 0. + */ + uint8_t checksum; + + /* Command code */ + uint16_t command; + + /* Command version */ + uint8_t command_version; + + /* Unused byte in current protocol version; set to 0 */ + uint8_t reserved; + + /* Length of data which follows this header */ + uint16_t data_len; +}; + +#define EC_HOST_RESPONSE_VERSION 3 + +/* Version 3 response from EC */ +struct __ec_align4 ec_host_response { + /* Structure version (=3) */ + uint8_t struct_version; + + /* + * Checksum of response and data; sum of all bytes including checksum + * should total to 0. + */ + uint8_t checksum; + + /* Result code (EC_RES_*) */ + uint16_t result; + + /* Length of data which follows this header */ + uint16_t data_len; + + /* Unused bytes in current protocol version; set to 0 */ + uint16_t reserved; +}; + +/*****************************************************************************/ +/* + * Notes on commands: + * + * Each command is an 16-bit command value. Commands which take params or + * return response data specify structures for that data. If no structure is + * specified, the command does not input or output data, respectively. + * Parameter/response length is implicit in the structs. Some underlying + * communication protocols (I2C, SPI) may add length or checksum headers, but + * those are implementation-dependent and not defined here. + * + * All commands MUST be #defined to be 4-digit UPPER CASE hex values + * (e.g., 0x00AB, not 0xab) for CONFIG_HOSTCMD_SECTION_SORTED to work. + */ + +/*****************************************************************************/ +/* General / test commands */ + +/* + * Get protocol version, used to deal with non-backward compatible protocol + * changes. + */ +#define EC_CMD_PROTO_VERSION 0x0000 + +struct __ec_align4 ec_response_proto_version { + uint32_t version; +}; + +/* + * Hello. This is a simple command to test the EC is responsive to + * commands. + */ +#define EC_CMD_HELLO 0x0001 + +struct __ec_align4 ec_params_hello { + uint32_t in_data; /* Pass anything here */ +}; + +struct __ec_align4 ec_response_hello { + uint32_t out_data; /* Output will be in_data + 0x01020304 */ +}; + +/* Get version number */ +#define EC_CMD_GET_VERSION 0x0002 + +enum ec_current_image { + EC_IMAGE_UNKNOWN = 0, + EC_IMAGE_RO, + EC_IMAGE_RW +}; + +struct __ec_align4 ec_response_get_version { + /* Null-terminated version strings for RO, RW */ + char version_string_ro[32]; + char version_string_rw[32]; + char reserved[32]; /* Was previously RW-B string */ + uint32_t current_image; /* One of ec_current_image */ +}; + +/* Read test */ +#define EC_CMD_READ_TEST 0x0003 + +struct __ec_align4 ec_params_read_test { + uint32_t offset; /* Starting value for read buffer */ + uint32_t size; /* Size to read in bytes */ +}; + +struct __ec_align4 ec_response_read_test { + uint32_t data[32]; +}; + +/* + * Get build information + * + * Response is null-terminated string. + */ +#define EC_CMD_GET_BUILD_INFO 0x0004 + +/* Get chip info */ +#define EC_CMD_GET_CHIP_INFO 0x0005 + +struct __ec_align4 ec_response_get_chip_info { + /* Null-terminated strings */ + char vendor[32]; + char name[32]; + char revision[32]; /* Mask version */ +}; + +/* Get board HW version */ +#define EC_CMD_GET_BOARD_VERSION 0x0006 + +struct __ec_align2 ec_response_board_version { + uint16_t board_version; /* A monotonously incrementing number. */ +}; + +/* + * Read memory-mapped data. + * + * This is an alternate interface to memory-mapped data for bus protocols + * which don't support direct-mapped memory - I2C, SPI, etc. + * + * Response is params.size bytes of data. + */ +#define EC_CMD_READ_MEMMAP 0x0007 + +struct __ec_align1 ec_params_read_memmap { + uint8_t offset; /* Offset in memmap (EC_MEMMAP_*) */ + uint8_t size; /* Size to read in bytes */ +}; + +/* Read versions supported for a command */ +#define EC_CMD_GET_CMD_VERSIONS 0x0008 + +struct __ec_align1 ec_params_get_cmd_versions { + uint8_t cmd; /* Command to check */ +}; + +struct __ec_align2 ec_params_get_cmd_versions_v1 { + uint16_t cmd; /* Command to check */ +}; + +struct __ec_align4 ec_response_get_cmd_versions { + /* + * Mask of supported versions; use EC_VER_MASK() to compare with a + * desired version. + */ + uint32_t version_mask; +}; + +/* + * Check EC communications status (busy). This is needed on i2c/spi but not + * on lpc since it has its own out-of-band busy indicator. + * + * lpc must read the status from the command register. Attempting this on + * lpc will overwrite the args/parameter space and corrupt its data. + */ +#define EC_CMD_GET_COMMS_STATUS 0x0009 + +/* Avoid using ec_status which is for return values */ +enum ec_comms_status { + EC_COMMS_STATUS_PROCESSING = 1 << 0, /* Processing cmd */ +}; + +struct __ec_align4 ec_response_get_comms_status { + uint32_t flags; /* Mask of enum ec_comms_status */ +}; + +/* Fake a variety of responses, purely for testing purposes. */ +#define EC_CMD_TEST_PROTOCOL 0x000A + +/* Tell the EC what to send back to us. */ +struct __ec_align4 ec_params_test_protocol { + uint32_t ec_result; + uint32_t ret_len; + uint8_t buf[32]; +}; + +/* Here it comes... */ +struct __ec_align4 ec_response_test_protocol { + uint8_t buf[32]; +}; + +/* Get protocol information */ +#define EC_CMD_GET_PROTOCOL_INFO 0x000B + +/* Flags for ec_response_get_protocol_info.flags */ +/* EC_RES_IN_PROGRESS may be returned if a command is slow */ +#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0) + +struct __ec_align4 ec_response_get_protocol_info { + /* Fields which exist if at least protocol version 3 supported */ + + /* Bitmask of protocol versions supported (1 << n means version n)*/ + uint32_t protocol_versions; + + /* Maximum request packet size, in bytes */ + uint16_t max_request_packet_size; + + /* Maximum response packet size, in bytes */ + uint16_t max_response_packet_size; + + /* Flags; see EC_PROTOCOL_INFO_* */ + uint32_t flags; +}; + + +/*****************************************************************************/ +/* Get/Set miscellaneous values */ + +/* The upper byte of .flags tells what to do (nothing means "get") */ +#define EC_GSV_SET 0x80000000 + +/* The lower three bytes of .flags identifies the parameter, if that has + meaning for an individual command. */ +#define EC_GSV_PARAM_MASK 0x00ffffff + +struct __ec_align4 ec_params_get_set_value { + uint32_t flags; + uint32_t value; +}; + +struct __ec_align4 ec_response_get_set_value { + uint32_t flags; + uint32_t value; +}; + +/* More than one command can use these structs to get/set parameters. */ +#define EC_CMD_GSV_PAUSE_IN_S5 0x000C + +/*****************************************************************************/ +/* List the features supported by the firmware */ +#define EC_CMD_GET_FEATURES 0x000D + +/* Supported features */ +enum ec_feature_code { + /* + * This image contains a limited set of features. Another image + * in RW partition may support more features. + */ + EC_FEATURE_LIMITED = 0, + /* + * Commands for probing/reading/writing/erasing the flash in the + * EC are present. + */ + EC_FEATURE_FLASH = 1, + /* + * Can control the fan speed directly. + */ + EC_FEATURE_PWM_FAN = 2, + /* + * Can control the intensity of the keyboard backlight. + */ + EC_FEATURE_PWM_KEYB = 3, + /* + * Support Google lightbar, introduced on Pixel. + */ + EC_FEATURE_LIGHTBAR = 4, + /* Control of LEDs */ + EC_FEATURE_LED = 5, + /* Exposes an interface to control gyro and sensors. + * The host goes through the EC to access these sensors. + * In addition, the EC may provide composite sensors, like lid angle. + */ + EC_FEATURE_MOTION_SENSE = 6, + /* The keyboard is controlled by the EC */ + EC_FEATURE_KEYB = 7, + /* The AP can use part of the EC flash as persistent storage. */ + EC_FEATURE_PSTORE = 8, + /* The EC monitors BIOS port 80h, and can return POST codes. */ + EC_FEATURE_PORT80 = 9, + /* + * Thermal management: include TMP specific commands. + * Higher level than direct fan control. + */ + EC_FEATURE_THERMAL = 10, + /* Can switch the screen backlight on/off */ + EC_FEATURE_BKLIGHT_SWITCH = 11, + /* Can switch the wifi module on/off */ + EC_FEATURE_WIFI_SWITCH = 12, + /* Monitor host events, through for example SMI or SCI */ + EC_FEATURE_HOST_EVENTS = 13, + /* The EC exposes GPIO commands to control/monitor connected devices. */ + EC_FEATURE_GPIO = 14, + /* The EC can send i2c messages to downstream devices. */ + EC_FEATURE_I2C = 15, + /* Command to control charger are included */ + EC_FEATURE_CHARGER = 16, + /* Simple battery support. */ + EC_FEATURE_BATTERY = 17, + /* + * Support Smart battery protocol + * (Common Smart Battery System Interface Specification) + */ + EC_FEATURE_SMART_BATTERY = 18, + /* EC can detect when the host hangs. */ + EC_FEATURE_HANG_DETECT = 19, + /* Report power information, for pit only */ + EC_FEATURE_PMU = 20, + /* Another Cros EC device is present downstream of this one */ + EC_FEATURE_SUB_MCU = 21, + /* Support USB Power delivery (PD) commands */ + EC_FEATURE_USB_PD = 22, + /* Control USB multiplexer, for audio through USB port for instance. */ + EC_FEATURE_USB_MUX = 23, + /* Motion Sensor code has an internal software FIFO */ + EC_FEATURE_MOTION_SENSE_FIFO = 24, + /* Support temporary secure vstore */ + EC_FEATURE_VSTORE = 25, + /* EC decides on USB-C SS mux state, muxes configured by host */ + EC_FEATURE_USBC_SS_MUX_VIRTUAL = 26, + /* EC has RTC feature that can be controlled by host commands */ + EC_FEATURE_RTC = 27, + /* The MCU exposes a Fingerprint sensor */ + EC_FEATURE_FINGERPRINT = 28, + /* The MCU exposes a Touchpad */ + EC_FEATURE_TOUCHPAD = 29, + /* The MCU has RWSIG task enabled */ + EC_FEATURE_RWSIG = 30, + /* EC has device events support */ + EC_FEATURE_DEVICE_EVENT = 31, + /* EC supports the unified wake masks for LPC/eSPI systems */ + EC_FEATURE_UNIFIED_WAKE_MASKS = 32, + /* EC supports 64-bit host events */ + EC_FEATURE_HOST_EVENT64 = 33, + /* EC runs code in RAM (not in place, a.k.a. XIP) */ + EC_FEATURE_EXEC_IN_RAM = 34, + /* EC supports CEC commands */ + EC_FEATURE_CEC = 35, + /* EC supports tight sensor timestamping. */ + EC_FEATURE_MOTION_SENSE_TIGHT_TIMESTAMPS = 36, + /* + * EC supports tablet mode detection aligned to Chrome and allows + * setting of threshold by host command using + * MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. + */ + EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37, + /* + * Early Firmware Selection ver.2. Enabled by CONFIG_VBOOT_EFS2. + * Note this is a RO feature. So, a query (EC_CMD_GET_FEATURES) should + * be sent to RO to be precise. + */ + EC_FEATURE_EFS2 = 38, + /* The MCU is a System Companion Processor (SCP). */ + EC_FEATURE_SCP = 39, + /* The MCU is an Integrated Sensor Hub */ + EC_FEATURE_ISH = 40, + /* New TCPMv2 TYPEC_ prefaced commands supported */ + EC_FEATURE_TYPEC_CMD = 41, + /* + * The EC will wait for direction from the AP to enter Type-C alternate + * modes or USB4. + */ + EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY = 42, + /* + * The EC will wait for an acknowledge from the AP after setting the + * mux. + */ + EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43, +}; + +#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) +#define EC_FEATURE_MASK_1(event_code) BIT(event_code - 32) + +struct ec_response_get_features { + uint32_t flags[2]; +} __ec_align4; + +/*****************************************************************************/ +/* Get the board's SKU ID from EC */ +#define EC_CMD_GET_SKU_ID 0x000E + +/* Set SKU ID from AP */ +#define EC_CMD_SET_SKU_ID 0x000F + +struct __ec_align4 ec_sku_id_info { + uint32_t sku_id; +}; + +/*****************************************************************************/ +/* Flash commands */ + +/* Get flash info */ +#define EC_CMD_FLASH_INFO 0x0010 +#define EC_VER_FLASH_INFO 2 + +/* Version 0 returns these fields */ +struct __ec_align4 ec_response_flash_info { + /* Usable flash size, in bytes */ + uint32_t flash_size; + /* + * Write block size. Write offset and size must be a multiple + * of this. + */ + uint32_t write_block_size; + /* + * Erase block size. Erase offset and size must be a multiple + * of this. + */ + uint32_t erase_block_size; + /* + * Protection block size. Protection offset and size must be a + * multiple of this. + */ + uint32_t protect_block_size; +}; + +/* Flags for version 1+ flash info command */ +/* EC flash erases bits to 0 instead of 1 */ +#define EC_FLASH_INFO_ERASE_TO_0 (1 << 0) + +/* Flash must be selected for read/write/erase operations to succeed. This may + * be necessary on a chip where write/erase can be corrupted by other board + * activity, or where the chip needs to enable some sort of programming voltage, + * or where the read/write/erase operations require cleanly suspending other + * chip functionality. */ +#define EC_FLASH_INFO_SELECT_REQUIRED (1 << 1) + +/* + * Version 1 returns the same initial fields as version 0, with additional + * fields following. + * + * gcc anonymous structs don't seem to get along with the __packed directive; + * if they did we'd define the version 0 structure as a sub-structure of this + * one. + * + * Version 2 supports flash banks of different sizes: + * The caller specified the number of banks it has preallocated + * (num_banks_desc) + * The EC returns the number of banks describing the flash memory. + * It adds banks descriptions up to num_banks_desc. + */ +struct __ec_align4 ec_response_flash_info_1 { + /* Version 0 fields; see above for description */ + uint32_t flash_size; + uint32_t write_block_size; + uint32_t erase_block_size; + uint32_t protect_block_size; + + /* Version 1 adds these fields: */ + /* + * Ideal write size in bytes. Writes will be fastest if size is + * exactly this and offset is a multiple of this. For example, an EC + * may have a write buffer which can do half-page operations if data is + * aligned, and a slower word-at-a-time write mode. + */ + uint32_t write_ideal_size; + + /* Flags; see EC_FLASH_INFO_* */ + uint32_t flags; +}; + +struct __ec_align4 ec_params_flash_info_2 { + /* Number of banks to describe */ + uint16_t num_banks_desc; + /* Reserved; set 0; ignore on read */ + uint8_t reserved[2]; +}; + +struct ec_flash_bank { + /* Number of sector is in this bank. */ + uint16_t count; + /* Size in power of 2 of each sector (8 --> 256 bytes) */ + uint8_t size_exp; + /* Minimal write size for the sectors in this bank */ + uint8_t write_size_exp; + /* Erase size for the sectors in this bank */ + uint8_t erase_size_exp; + /* Size for write protection, usually identical to erase size. */ + uint8_t protect_size_exp; + /* Reserved; set 0; ignore on read */ + uint8_t reserved[2]; +}; + +struct __ec_align4 ec_response_flash_info_2 { + /* Total flash in the EC. */ + uint32_t flash_size; + /* Flags; see EC_FLASH_INFO_* */ + uint32_t flags; + /* Maximum size to use to send data to write to the EC. */ + uint32_t write_ideal_size; + /* Number of banks present in the EC. */ + uint16_t num_banks_total; + /* Number of banks described in banks array. */ + uint16_t num_banks_desc; + struct ec_flash_bank banks[0]; +}; + +/* + * Read flash + * + * Response is params.size bytes of data. + */ +#define EC_CMD_FLASH_READ 0x0011 + +struct __ec_align4 ec_params_flash_read { + uint32_t offset; /* Byte offset to read */ + uint32_t size; /* Size to read in bytes */ +}; + +/* Write flash */ +#define EC_CMD_FLASH_WRITE 0x0012 +#define EC_VER_FLASH_WRITE 1 + +/* Version 0 of the flash command supported only 64 bytes of data */ +#define EC_FLASH_WRITE_VER0_SIZE 64 + +struct __ec_align4 ec_params_flash_write { + uint32_t offset; /* Byte offset to write */ + uint32_t size; /* Size to write in bytes */ + /* Followed by data to write */ +}; + +/* Erase flash */ +#define EC_CMD_FLASH_ERASE 0x0013 + +/* v0 */ +struct __ec_align4 ec_params_flash_erase { + uint32_t offset; /* Byte offset to erase */ + uint32_t size; /* Size to erase in bytes */ +}; + + +#define EC_VER_FLASH_WRITE 1 +/* v1 add async erase: + * subcommands can returns: + * EC_RES_SUCCESS : erased (see ERASE_SECTOR_ASYNC case below). + * EC_RES_INVALID_PARAM : offset/size are not aligned on a erase boundary. + * EC_RES_ERROR : other errors. + * EC_RES_BUSY : an existing erase operation is in progress. + * EC_RES_ACCESS_DENIED: Trying to erase running image. + * + * When ERASE_SECTOR_ASYNC returns EC_RES_SUCCESS, the operation is just + * properly queued. The user must call ERASE_GET_RESULT subcommand to get + * the proper result. + * When ERASE_GET_RESULT returns EC_RES_BUSY, the caller must wait and send + * ERASE_GET_RESULT again to get the result of ERASE_SECTOR_ASYNC. + * ERASE_GET_RESULT command may timeout on EC where flash access is not + * permitted while erasing. (For instance, STM32F4). + */ +enum ec_flash_erase_cmd { + FLASH_ERASE_SECTOR, /* Erase and wait for result */ + FLASH_ERASE_SECTOR_ASYNC, /* Erase and return immediately. */ + FLASH_ERASE_GET_RESULT, /* Ask for last erase result */ +}; + +struct __ec_align4 ec_params_flash_erase_v1 { + /* One of ec_flash_erase_cmd. */ + uint8_t cmd; + /* Pad byte; currently always contains 0 */ + uint8_t reserved; + /* No flags defined yet; set to 0 */ + uint16_t flag; + /* Same as v0 parameters. */ + struct ec_params_flash_erase params; +}; + +/* + * Get/set flash protection. + * + * If mask!=0, sets/clear the requested bits of flags. Depending on the + * firmware write protect GPIO, not all flags will take effect immediately; + * some flags require a subsequent hard reset to take effect. Check the + * returned flags bits to see what actually happened. + * + * If mask=0, simply returns the current flags state. + */ +#define EC_CMD_FLASH_PROTECT 0x0015 +#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */ + +/* Flags for flash protection */ +/* RO flash code protected when the EC boots */ +#define EC_FLASH_PROTECT_RO_AT_BOOT (1 << 0) +/* + * RO flash code protected now. If this bit is set, at-boot status cannot + * be changed. + */ +#define EC_FLASH_PROTECT_RO_NOW (1 << 1) +/* Entire flash code protected now, until reboot. */ +#define EC_FLASH_PROTECT_ALL_NOW (1 << 2) +/* Flash write protect GPIO is asserted now */ +#define EC_FLASH_PROTECT_GPIO_ASSERTED (1 << 3) +/* Error - at least one bank of flash is stuck locked, and cannot be unlocked */ +#define EC_FLASH_PROTECT_ERROR_STUCK (1 << 4) +/* + * Error - flash protection is in inconsistent state. At least one bank of + * flash which should be protected is not protected. Usually fixed by + * re-requesting the desired flags, or by a hard reset if that fails. + */ +#define EC_FLASH_PROTECT_ERROR_INCONSISTENT (1 << 5) +/* Entire flash code protected when the EC boots */ +#define EC_FLASH_PROTECT_ALL_AT_BOOT (1 << 6) +/* RW flash code protected when the EC boots */ +#define EC_FLASH_PROTECT_RW_AT_BOOT (1 << 7) +/* RW flash code protected now. */ +#define EC_FLASH_PROTECT_RW_NOW (1 << 8) +/* Rollback information flash region protected when the EC boots */ +#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT (1 << 9) +/* Rollback information flash region protected now */ +#define EC_FLASH_PROTECT_ROLLBACK_NOW (1 << 10) + +struct __ec_align4 ec_params_flash_protect { + uint32_t mask; /* Bits in flags to apply */ + uint32_t flags; /* New flags to apply */ +}; + +struct __ec_align4 ec_response_flash_protect { + /* Current value of flash protect flags */ + uint32_t flags; + /* + * Flags which are valid on this platform. This allows the caller + * to distinguish between flags which aren't set vs. flags which can't + * be set on this platform. + */ + uint32_t valid_flags; + /* Flags which can be changed given the current protection state */ + uint32_t writable_flags; +}; + +/* + * Note: commands 0x14 - 0x19 version 0 were old commands to get/set flash + * write protect. These commands may be reused with version > 0. + */ + +/* Get the region offset/size */ +#define EC_CMD_FLASH_REGION_INFO 0x0016 +#define EC_VER_FLASH_REGION_INFO 1 + +enum ec_flash_region { + /* Region which holds read-only EC image */ + EC_FLASH_REGION_RO = 0, + /* Region which holds active rewritable EC image */ + EC_FLASH_REGION_ACTIVE, + /* + * Region which should be write-protected in the factory (a superset of + * EC_FLASH_REGION_RO) + */ + EC_FLASH_REGION_WP_RO, + /* Region which holds updatable image */ + EC_FLASH_REGION_UPDATE, + /* Number of regions */ + EC_FLASH_REGION_COUNT, +}; + +struct __ec_align4 ec_params_flash_region_info { + uint32_t region; /* enum ec_flash_region */ +}; + +struct __ec_align4 ec_response_flash_region_info { + uint32_t offset; + uint32_t size; +}; + +/* Read/write VbNvContext */ +#define EC_CMD_VBNV_CONTEXT 0x0017 +#define EC_VER_VBNV_CONTEXT 1 +#define EC_VBNV_BLOCK_SIZE 16 +#define EC_VBNV_BLOCK_SIZE_V2 64 + +enum ec_vbnvcontext_op { + EC_VBNV_CONTEXT_OP_READ, + EC_VBNV_CONTEXT_OP_WRITE, +}; + +struct __ec_align4 ec_params_vbnvcontext { + uint32_t op; + uint8_t block[EC_VBNV_BLOCK_SIZE_V2]; +}; + +struct __ec_align4 ec_response_vbnvcontext { + uint8_t block[EC_VBNV_BLOCK_SIZE_V2]; +}; + + +/* Get SPI flash information */ +#define EC_CMD_FLASH_SPI_INFO 0x0018 + +struct __ec_align1 ec_response_flash_spi_info { + /* JEDEC info from command 0x9F (manufacturer, memory type, size) */ + uint8_t jedec[3]; + + /* Pad byte; currently always contains 0 */ + uint8_t reserved0; + + /* Manufacturer / device ID from command 0x90 */ + uint8_t mfr_dev_id[2]; + + /* Status registers from command 0x05 and 0x35 */ + uint8_t sr1, sr2; +}; + + +/* Select flash during flash operations */ +#define EC_CMD_FLASH_SELECT 0x0019 + +struct __ec_align4 ec_params_flash_select { + /* 1 to select flash, 0 to deselect flash */ + uint8_t select; +}; + +/*****************************************************************************/ +/* PWM commands */ + +/* Get fan target RPM */ +#define EC_CMD_PWM_GET_FAN_TARGET_RPM 0x0020 + +struct __ec_align4 ec_response_pwm_get_fan_rpm { + uint32_t rpm; +}; + +/* Set target fan RPM */ +#define EC_CMD_PWM_SET_FAN_TARGET_RPM 0x0021 + +/* Version 0 of input params */ +struct __ec_align4 ec_params_pwm_set_fan_target_rpm_v0 { + uint32_t rpm; +}; + +/* Version 1 of input params */ +struct __ec_align_size1 ec_params_pwm_set_fan_target_rpm_v1 { + uint32_t rpm; + uint8_t fan_idx; +}; + +/* Get keyboard backlight */ +/* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */ +#define EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT 0x0022 + +struct __ec_align1 ec_response_pwm_get_keyboard_backlight { + uint8_t percent; + uint8_t enabled; +}; + +/* Set keyboard backlight */ +/* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */ +#define EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT 0x0023 + +struct __ec_align1 ec_params_pwm_set_keyboard_backlight { + uint8_t percent; +}; + +/* Set target fan PWM duty cycle */ +#define EC_CMD_PWM_SET_FAN_DUTY 0x0024 + +/* Version 0 of input params */ +struct __ec_align4 ec_params_pwm_set_fan_duty_v0 { + uint32_t percent; +}; + +/* Version 1 of input params */ +struct __ec_align_size1 ec_params_pwm_set_fan_duty_v1 { + uint32_t percent; + uint8_t fan_idx; +}; + +#define EC_CMD_PWM_SET_DUTY 0x0025 +/* 16 bit duty cycle, 0xffff = 100% */ +#define EC_PWM_MAX_DUTY 0xffff + +enum ec_pwm_type { + /* All types, indexed by board-specific enum pwm_channel */ + EC_PWM_TYPE_GENERIC = 0, + /* Keyboard backlight */ + EC_PWM_TYPE_KB_LIGHT, + /* Display backlight */ + EC_PWM_TYPE_DISPLAY_LIGHT, + EC_PWM_TYPE_COUNT, +}; + +struct __ec_align4 ec_params_pwm_set_duty { + uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ + uint8_t pwm_type; /* ec_pwm_type */ + uint8_t index; /* Type-specific index, or 0 if unique */ +}; + +#define EC_CMD_PWM_GET_DUTY 0x0026 + +struct __ec_align1 ec_params_pwm_get_duty { + uint8_t pwm_type; /* ec_pwm_type */ + uint8_t index; /* Type-specific index, or 0 if unique */ +}; + +struct __ec_align2 ec_response_pwm_get_duty { + uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ +}; + +/*****************************************************************************/ +/* + * Lightbar commands. This looks worse than it is. Since we only use one HOST + * command to say "talk to the lightbar", we put the "and tell it to do X" part + * into a subcommand. We'll make separate structs for subcommands with + * different input args, so that we know how much to expect. + */ +#define EC_CMD_LIGHTBAR_CMD 0x0028 + +struct __ec_todo_unpacked rgb_s { + uint8_t r, g, b; +}; + +#define LB_BATTERY_LEVELS 4 +/* List of tweakable parameters. NOTE: It's __packed so it can be sent in a + * host command, but the alignment is the same regardless. Keep it that way. + */ +struct __ec_todo_packed lightbar_params_v0 { + /* Timing */ + int32_t google_ramp_up; + int32_t google_ramp_down; + int32_t s3s0_ramp_up; + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0s3_ramp_down; + int32_t s3_sleep_for; + int32_t s3_ramp_up; + int32_t s3_ramp_down; + + /* Oscillation */ + uint8_t new_s0; + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ + + /* Brightness limits based on the backlight and AC. */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ + + /* Battery level thresholds */ + uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; + + /* Map [AC][battery_level] to color index */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + + /* Color palette */ + struct rgb_s color[8]; /* 0-3 are Google colors */ +}; + +struct __ec_todo_packed lightbar_params_v1 { + /* Timing */ + int32_t google_ramp_up; + int32_t google_ramp_down; + int32_t s3s0_ramp_up; + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0s3_ramp_down; + int32_t s3_sleep_for; + int32_t s3_ramp_up; + int32_t s3_ramp_down; + int32_t s5_ramp_up; + int32_t s5_ramp_down; + int32_t tap_tick_delay; + int32_t tap_gate_delay; + int32_t tap_display_time; + + /* Tap-for-battery params */ + uint8_t tap_pct_red; + uint8_t tap_pct_green; + uint8_t tap_seg_min_on; + uint8_t tap_seg_max_on; + uint8_t tap_seg_osc; + uint8_t tap_idx[3]; + + /* Oscillation */ + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ + + /* Brightness limits based on the backlight and AC. */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ + + /* Battery level thresholds */ + uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; + + /* Map [AC][battery_level] to color index */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + + /* s5: single color pulse on inhibited power-up */ + uint8_t s5_idx; + + /* Color palette */ + struct rgb_s color[8]; /* 0-3 are Google colors */ +}; + +/* Lightbar command params v2 + * crbug.com/467716 + * + * lightbar_parms_v1 was too big for i2c, therefore in v2, we split them up by + * logical groups to make it more manageable ( < 120 bytes). + * + * NOTE: Each of these groups must be less than 120 bytes. + */ + +struct __ec_todo_packed lightbar_params_v2_timing { + /* Timing */ + int32_t google_ramp_up; + int32_t google_ramp_down; + int32_t s3s0_ramp_up; + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0s3_ramp_down; + int32_t s3_sleep_for; + int32_t s3_ramp_up; + int32_t s3_ramp_down; + int32_t s5_ramp_up; + int32_t s5_ramp_down; + int32_t tap_tick_delay; + int32_t tap_gate_delay; + int32_t tap_display_time; +}; + +struct __ec_todo_packed lightbar_params_v2_tap { + /* Tap-for-battery params */ + uint8_t tap_pct_red; + uint8_t tap_pct_green; + uint8_t tap_seg_min_on; + uint8_t tap_seg_max_on; + uint8_t tap_seg_osc; + uint8_t tap_idx[3]; +}; + +struct __ec_todo_packed lightbar_params_v2_oscillation { + /* Oscillation */ + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ +}; + +struct __ec_todo_packed lightbar_params_v2_brightness { + /* Brightness limits based on the backlight and AC. */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ +}; + +struct __ec_todo_packed lightbar_params_v2_thresholds { + /* Battery level thresholds */ + uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; +}; + +struct __ec_todo_packed lightbar_params_v2_colors { + /* Map [AC][battery_level] to color index */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + + /* s5: single color pulse on inhibited power-up */ + uint8_t s5_idx; + + /* Color palette */ + struct rgb_s color[8]; /* 0-3 are Google colors */ +}; + +/* Lightbyte program. */ +#define EC_LB_PROG_LEN 192 +struct __ec_todo_unpacked lightbar_program { + uint8_t size; + uint8_t data[EC_LB_PROG_LEN]; +}; + +struct __ec_todo_packed ec_params_lightbar { + uint8_t cmd; /* Command (see enum lightbar_command) */ + union { + struct __ec_todo_unpacked { + /* no args */ + } dump, off, on, init, get_seq, get_params_v0, get_params_v1, + version, get_brightness, get_demo, suspend, resume, + get_params_v2_timing, get_params_v2_tap, + get_params_v2_osc, get_params_v2_bright, + get_params_v2_thlds, get_params_v2_colors; + + struct __ec_todo_unpacked { + uint8_t num; + } set_brightness, seq, demo; + + struct __ec_todo_unpacked { + uint8_t ctrl, reg, value; + } reg; + + struct __ec_todo_unpacked { + uint8_t led, red, green, blue; + } set_rgb; + + struct __ec_todo_unpacked { + uint8_t led; + } get_rgb; + + struct __ec_todo_unpacked { + uint8_t enable; + } manual_suspend_ctrl; + + struct lightbar_params_v0 set_params_v0; + struct lightbar_params_v1 set_params_v1; + + struct lightbar_params_v2_timing set_v2par_timing; + struct lightbar_params_v2_tap set_v2par_tap; + struct lightbar_params_v2_oscillation set_v2par_osc; + struct lightbar_params_v2_brightness set_v2par_bright; + struct lightbar_params_v2_thresholds set_v2par_thlds; + struct lightbar_params_v2_colors set_v2par_colors; + + struct lightbar_program set_program; + }; +}; + +struct __ec_todo_packed ec_response_lightbar { + union { + struct __ec_todo_unpacked { + struct __ec_todo_unpacked { + uint8_t reg; + uint8_t ic0; + uint8_t ic1; + } vals[23]; + } dump; + + struct __ec_todo_unpacked { + uint8_t num; + } get_seq, get_brightness, get_demo; + + struct lightbar_params_v0 get_params_v0; + struct lightbar_params_v1 get_params_v1; + + + struct lightbar_params_v2_timing get_params_v2_timing; + struct lightbar_params_v2_tap get_params_v2_tap; + struct lightbar_params_v2_oscillation get_params_v2_osc; + struct lightbar_params_v2_brightness get_params_v2_bright; + struct lightbar_params_v2_thresholds get_params_v2_thlds; + struct lightbar_params_v2_colors get_params_v2_colors; + + struct __ec_todo_unpacked { + uint32_t num; + uint32_t flags; + } version; + + struct __ec_todo_unpacked { + uint8_t red, green, blue; + } get_rgb; + + struct __ec_todo_unpacked { + /* no return params */ + } off, on, init, set_brightness, seq, reg, set_rgb, + demo, set_params_v0, set_params_v1, + set_program, manual_suspend_ctrl, suspend, resume, + set_v2par_timing, set_v2par_tap, + set_v2par_osc, set_v2par_bright, set_v2par_thlds, + set_v2par_colors; + }; +}; + +/* Lightbar commands */ +enum lightbar_command { + LIGHTBAR_CMD_DUMP = 0, + LIGHTBAR_CMD_OFF = 1, + LIGHTBAR_CMD_ON = 2, + LIGHTBAR_CMD_INIT = 3, + LIGHTBAR_CMD_SET_BRIGHTNESS = 4, + LIGHTBAR_CMD_SEQ = 5, + LIGHTBAR_CMD_REG = 6, + LIGHTBAR_CMD_SET_RGB = 7, + LIGHTBAR_CMD_GET_SEQ = 8, + LIGHTBAR_CMD_DEMO = 9, + LIGHTBAR_CMD_GET_PARAMS_V0 = 10, + LIGHTBAR_CMD_SET_PARAMS_V0 = 11, + LIGHTBAR_CMD_VERSION = 12, + LIGHTBAR_CMD_GET_BRIGHTNESS = 13, + LIGHTBAR_CMD_GET_RGB = 14, + LIGHTBAR_CMD_GET_DEMO = 15, + LIGHTBAR_CMD_GET_PARAMS_V1 = 16, + LIGHTBAR_CMD_SET_PARAMS_V1 = 17, + LIGHTBAR_CMD_SET_PROGRAM = 18, + LIGHTBAR_CMD_MANUAL_SUSPEND_CTRL = 19, + LIGHTBAR_CMD_SUSPEND = 20, + LIGHTBAR_CMD_RESUME = 21, + LIGHTBAR_CMD_GET_PARAMS_V2_TIMING = 22, + LIGHTBAR_CMD_SET_PARAMS_V2_TIMING = 23, + LIGHTBAR_CMD_GET_PARAMS_V2_TAP = 24, + LIGHTBAR_CMD_SET_PARAMS_V2_TAP = 25, + LIGHTBAR_CMD_GET_PARAMS_V2_OSCILLATION = 26, + LIGHTBAR_CMD_SET_PARAMS_V2_OSCILLATION = 27, + LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS = 28, + LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS = 29, + LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS = 30, + LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS = 31, + LIGHTBAR_CMD_GET_PARAMS_V2_COLORS = 32, + LIGHTBAR_CMD_SET_PARAMS_V2_COLORS = 33, + LIGHTBAR_NUM_CMDS +}; + +/*****************************************************************************/ +/* LED control commands */ + +#define EC_CMD_LED_CONTROL 0x0029 + +enum ec_led_id { + /* LED to indicate battery state of charge */ + EC_LED_ID_BATTERY_LED = 0, + /* + * LED to indicate system power state (on or in suspend). + * May be on power button or on C-panel. + */ + EC_LED_ID_POWER_LED, + /* LED on power adapter or its plug */ + EC_LED_ID_ADAPTER_LED, + /* LED to indicate left side */ + EC_LED_ID_LEFT_LED, + /* LED to indicate right side */ + EC_LED_ID_RIGHT_LED, + /* LED to indicate recovery mode with HW_REINIT */ + EC_LED_ID_RECOVERY_HW_REINIT_LED, + /* LED to indicate sysrq debug mode. */ + EC_LED_ID_SYSRQ_DEBUG_LED, + + EC_LED_ID_COUNT +}; + +/* LED control flags */ +#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */ +#define EC_LED_FLAGS_AUTO (1 << 1) /* Switch LED back to automatic control */ + +enum ec_led_colors { + EC_LED_COLOR_RED = 0, + EC_LED_COLOR_GREEN, + EC_LED_COLOR_BLUE, + EC_LED_COLOR_YELLOW, + EC_LED_COLOR_WHITE, + EC_LED_COLOR_AMBER, + + EC_LED_COLOR_COUNT +}; + +struct __ec_align1 ec_params_led_control { + uint8_t led_id; /* Which LED to control */ + uint8_t flags; /* Control flags */ + + uint8_t brightness[EC_LED_COLOR_COUNT]; +}; + +struct __ec_align1 ec_response_led_control { + /* + * Available brightness value range. + * + * Range 0 means color channel not present. + * Range 1 means on/off control. + * Other values means the LED is control by PWM. + */ + uint8_t brightness_range[EC_LED_COLOR_COUNT]; +}; + +/*****************************************************************************/ +/* Verified boot commands */ + +/* + * Note: command code 0x29 version 0 was VBOOT_CMD in Link EVT; it may be + * reused for other purposes with version > 0. + */ + +/* Verified boot hash command */ +#define EC_CMD_VBOOT_HASH 0x002A + +struct __ec_align4 ec_params_vboot_hash { + uint8_t cmd; /* enum ec_vboot_hash_cmd */ + uint8_t hash_type; /* enum ec_vboot_hash_type */ + uint8_t nonce_size; /* Nonce size; may be 0 */ + uint8_t reserved0; /* Reserved; set 0 */ + uint32_t offset; /* Offset in flash to hash */ + uint32_t size; /* Number of bytes to hash */ + uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */ +}; + +struct __ec_align4 ec_response_vboot_hash { + uint8_t status; /* enum ec_vboot_hash_status */ + uint8_t hash_type; /* enum ec_vboot_hash_type */ + uint8_t digest_size; /* Size of hash digest in bytes */ + uint8_t reserved0; /* Ignore; will be 0 */ + uint32_t offset; /* Offset in flash which was hashed */ + uint32_t size; /* Number of bytes hashed */ + uint8_t hash_digest[64]; /* Hash digest data */ +}; + +enum ec_vboot_hash_cmd { + EC_VBOOT_HASH_GET = 0, /* Get current hash status */ + EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */ + EC_VBOOT_HASH_START = 2, /* Start computing a new hash */ + EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */ +}; + +enum ec_vboot_hash_type { + EC_VBOOT_HASH_TYPE_SHA256 = 0, /* SHA-256 */ +}; + +enum ec_vboot_hash_status { + EC_VBOOT_HASH_STATUS_NONE = 0, /* No hash (not started, or aborted) */ + EC_VBOOT_HASH_STATUS_DONE = 1, /* Finished computing a hash */ + EC_VBOOT_HASH_STATUS_BUSY = 2, /* Busy computing a hash */ +}; + +/* + * Special values for offset for EC_VBOOT_HASH_START and EC_VBOOT_HASH_RECALC. + * If one of these is specified, the EC will automatically update offset and + * size to the correct values for the specified image (RO or RW). + */ +#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe +#define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd +#define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc + +/*****************************************************************************/ +/* + * Motion sense commands. We'll make separate structs for sub-commands with + * different input args, so that we know how much to expect. + */ +#define EC_CMD_MOTION_SENSE_CMD 0x002B + +/* Motion sense commands */ +enum motionsense_command { + /* + * Dump command returns all motion sensor data including motion sense + * module flags and individual sensor flags. + */ + MOTIONSENSE_CMD_DUMP = 0, + + /* + * Info command returns data describing the details of a given sensor, + * including enum motionsensor_type, enum motionsensor_location, and + * enum motionsensor_chip. + */ + MOTIONSENSE_CMD_INFO = 1, + + /* + * EC Rate command is a setter/getter command for the EC sampling rate + * in milliseconds. + * It is per sensor, the EC run sample task at the minimum of all + * sensors EC_RATE. + * For sensors without hardware FIFO, EC_RATE should be equals to 1/ODR + * to collect all the sensor samples. + * For sensor with hardware FIFO, EC_RATE is used as the maximal delay + * to process of all motion sensors in milliseconds. + */ + MOTIONSENSE_CMD_EC_RATE = 2, + + /* + * Sensor ODR command is a setter/getter command for the output data + * rate of a specific motion sensor in millihertz. + */ + MOTIONSENSE_CMD_SENSOR_ODR = 3, + + /* + * Sensor range command is a setter/getter command for the range of + * a specified motion sensor in +/-G's or +/- deg/s. + */ + MOTIONSENSE_CMD_SENSOR_RANGE = 4, + + /* + * Setter/getter command for the keyboard wake angle. When the lid + * angle is greater than this value, keyboard wake is disabled in S3, + * and when the lid angle goes less than this value, keyboard wake is + * enabled. Note, the lid angle measurement is an approximate, + * un-calibrated value, hence the wake angle isn't exact. + */ + MOTIONSENSE_CMD_KB_WAKE_ANGLE = 5, + + /* + * Returns a single sensor data. + */ + MOTIONSENSE_CMD_DATA = 6, + + /* + * Return sensor fifo info. + */ + MOTIONSENSE_CMD_FIFO_INFO = 7, + + /* + * Insert a flush element in the fifo and return sensor fifo info. + * The host can use that element to synchronize its operation. + */ + MOTIONSENSE_CMD_FIFO_FLUSH = 8, + + /* + * Return a portion of the fifo. + */ + MOTIONSENSE_CMD_FIFO_READ = 9, + + /* + * Perform low level calibration. + * On sensors that support it, ask to do offset calibration. + */ + MOTIONSENSE_CMD_PERFORM_CALIB = 10, + + /* + * Sensor Offset command is a setter/getter command for the offset + * used for calibration. + * The offsets can be calculated by the host, or via + * PERFORM_CALIB command. + */ + MOTIONSENSE_CMD_SENSOR_OFFSET = 11, + + /* + * List available activities for a MOTION sensor. + * Indicates if they are enabled or disabled. + */ + MOTIONSENSE_CMD_LIST_ACTIVITIES = 12, + + /* + * Activity management + * Enable/Disable activity recognition. + */ + MOTIONSENSE_CMD_SET_ACTIVITY = 13, + + /* + * Lid Angle + */ + MOTIONSENSE_CMD_LID_ANGLE = 14, + + /* + * Allow the FIFO to trigger interrupt via MKBP events. + * By default the FIFO does not send interrupt to process the FIFO + * until the AP is ready or it is coming from a wakeup sensor. + */ + MOTIONSENSE_CMD_FIFO_INT_ENABLE = 15, + + /* + * Spoof the readings of the sensors. The spoofed readings can be set + * to arbitrary values, or will lock to the last read actual values. + */ + MOTIONSENSE_CMD_SPOOF = 16, + + /* Number of motionsense sub-commands. */ + MOTIONSENSE_NUM_CMDS +}; + +/* List of motion sensor types. */ +enum motionsensor_type { + MOTIONSENSE_TYPE_ACCEL = 0, + MOTIONSENSE_TYPE_GYRO = 1, + MOTIONSENSE_TYPE_MAG = 2, + MOTIONSENSE_TYPE_PROX = 3, + MOTIONSENSE_TYPE_LIGHT = 4, + MOTIONSENSE_TYPE_ACTIVITY = 5, + MOTIONSENSE_TYPE_BARO = 6, + MOTIONSENSE_TYPE_MAX, +}; + +/* List of motion sensor locations. */ +enum motionsensor_location { + MOTIONSENSE_LOC_BASE = 0, + MOTIONSENSE_LOC_LID = 1, + MOTIONSENSE_LOC_MAX, +}; + +/* List of motion sensor chips. */ +enum motionsensor_chip { + MOTIONSENSE_CHIP_KXCJ9 = 0, + MOTIONSENSE_CHIP_LSM6DS0 = 1, + MOTIONSENSE_CHIP_BMI160 = 2, + MOTIONSENSE_CHIP_SI1141 = 3, + MOTIONSENSE_CHIP_SI1142 = 4, + MOTIONSENSE_CHIP_SI1143 = 5, + MOTIONSENSE_CHIP_KX022 = 6, + MOTIONSENSE_CHIP_L3GD20H = 7, + MOTIONSENSE_CHIP_BMA255 = 8, + MOTIONSENSE_CHIP_BMP280 = 9, + MOTIONSENSE_CHIP_OPT3001 = 10, +}; + +struct __ec_todo_packed ec_response_motion_sensor_data { + /* Flags for each sensor. */ + uint8_t flags; + /* sensor number the data comes from */ + uint8_t sensor_num; + /* Each sensor is up to 3-axis. */ + union { + int16_t data[3]; + struct __ec_todo_packed { + uint16_t reserved; + uint32_t timestamp; + }; + struct __ec_todo_unpacked { + uint8_t activity; /* motionsensor_activity */ + uint8_t state; + int16_t add_info[2]; + }; + }; +}; + +/* Note: used in ec_response_get_next_data */ +struct __ec_todo_packed ec_response_motion_sense_fifo_info { + /* Size of the fifo */ + uint16_t size; + /* Amount of space used in the fifo */ + uint16_t count; + /* Timestamp recorded in us */ + uint32_t timestamp; + /* Total amount of vector lost */ + uint16_t total_lost; + /* Lost events since the last fifo_info, per sensors */ + uint16_t lost[0]; +}; + +struct __ec_todo_packed ec_response_motion_sense_fifo_data { + uint32_t number_data; + struct ec_response_motion_sensor_data data[0]; +}; + +/* List supported activity recognition */ +enum motionsensor_activity { + MOTIONSENSE_ACTIVITY_RESERVED = 0, + MOTIONSENSE_ACTIVITY_SIG_MOTION = 1, + MOTIONSENSE_ACTIVITY_DOUBLE_TAP = 2, +}; + +struct __ec_todo_unpacked ec_motion_sense_activity { + uint8_t sensor_num; + uint8_t activity; /* one of enum motionsensor_activity */ + uint8_t enable; /* 1: enable, 0: disable */ + uint8_t reserved; + uint16_t parameters[3]; /* activity dependent parameters */ +}; + +/* Module flag masks used for the dump sub-command. */ +#define MOTIONSENSE_MODULE_FLAG_ACTIVE (1<<0) + +/* Sensor flag masks used for the dump sub-command. */ +#define MOTIONSENSE_SENSOR_FLAG_PRESENT (1<<0) + +/* + * Flush entry for synchronization. + * data contains time stamp + */ +#define MOTIONSENSE_SENSOR_FLAG_FLUSH (1<<0) +#define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP (1<<1) +#define MOTIONSENSE_SENSOR_FLAG_WAKEUP (1<<2) +#define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE (1<<3) + +/* + * Send this value for the data element to only perform a read. If you + * send any other value, the EC will interpret it as data to set and will + * return the actual value set. + */ +#define EC_MOTION_SENSE_NO_VALUE -1 + +#define EC_MOTION_SENSE_INVALID_CALIB_TEMP 0x8000 + +/* MOTIONSENSE_CMD_SENSOR_OFFSET subcommand flag */ +/* Set Calibration information */ +#define MOTION_SENSE_SET_OFFSET 1 + +#define LID_ANGLE_UNRELIABLE 500 + +enum motionsense_spoof_mode { + /* Disable spoof mode. */ + MOTIONSENSE_SPOOF_MODE_DISABLE = 0, + + /* Enable spoof mode, but use provided component values. */ + MOTIONSENSE_SPOOF_MODE_CUSTOM, + + /* Enable spoof mode, but use the current sensor values. */ + MOTIONSENSE_SPOOF_MODE_LOCK_CURRENT, + + /* Query the current spoof mode status for the sensor. */ + MOTIONSENSE_SPOOF_MODE_QUERY, +}; + +struct __ec_todo_packed ec_params_motion_sense { + uint8_t cmd; + union { + /* Used for MOTIONSENSE_CMD_DUMP */ + struct __ec_todo_unpacked { + /* + * Maximal number of sensor the host is expecting. + * 0 means the host is only interested in the number + * of sensors controlled by the EC. + */ + uint8_t max_sensor_count; + } dump; + + /* + * Used for MOTIONSENSE_CMD_KB_WAKE_ANGLE. + */ + struct __ec_todo_unpacked { + /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. + * kb_wake_angle: angle to wakup AP. + */ + int16_t data; + } kb_wake_angle; + + /* Used for MOTIONSENSE_CMD_INFO, MOTIONSENSE_CMD_DATA + * and MOTIONSENSE_CMD_PERFORM_CALIB. */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + } info, info_3, data, fifo_flush, perform_calib, + list_activities; + + /* + * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR + * and MOTIONSENSE_CMD_SENSOR_RANGE. + */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + + /* Rounding flag, true for round-up, false for down. */ + uint8_t roundup; + + uint16_t reserved; + + /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. */ + int32_t data; + } ec_rate, sensor_odr, sensor_range; + + /* Used for MOTIONSENSE_CMD_SENSOR_OFFSET */ + struct __ec_todo_packed { + uint8_t sensor_num; + + /* + * bit 0: If set (MOTION_SENSE_SET_OFFSET), set + * the calibration information in the EC. + * If unset, just retrieve calibration information. + */ + uint16_t flags; + + /* + * Temperature at calibration, in units of 0.01 C + * 0x8000: invalid / unknown. + * 0x0: 0C + * 0x7fff: +327.67C + */ + int16_t temp; + + /* + * Offset for calibration. + * Unit: + * Accelerometer: 1/1024 g + * Gyro: 1/1024 deg/s + * Compass: 1/16 uT + */ + int16_t offset[3]; + } sensor_offset; + + /* Used for MOTIONSENSE_CMD_FIFO_INFO */ + struct __ec_todo_unpacked { + } fifo_info; + + /* Used for MOTIONSENSE_CMD_FIFO_READ */ + struct __ec_todo_unpacked { + /* + * Number of expected vector to return. + * EC may return less or 0 if none available. + */ + uint32_t max_data_vector; + } fifo_read; + + struct ec_motion_sense_activity set_activity; + + /* Used for MOTIONSENSE_CMD_LID_ANGLE */ + struct __ec_todo_unpacked { + } lid_angle; + + /* Used for MOTIONSENSE_CMD_FIFO_INT_ENABLE */ + struct __ec_todo_unpacked { + /* + * 1: enable, 0 disable fifo, + * EC_MOTION_SENSE_NO_VALUE return value. + */ + int8_t enable; + } fifo_int_enable; + + /* Used for MOTIONSENSE_CMD_SPOOF */ + struct __ec_todo_packed { + uint8_t sensor_id; + + /* See enum motionsense_spoof_mode. */ + uint8_t spoof_enable; + + /* Ignored, used for alignment. */ + uint8_t reserved; + + /* Individual component values to spoof. */ + int16_t components[3]; + } spoof; + }; +}; + +struct __ec_todo_packed ec_response_motion_sense { + union { + /* Used for MOTIONSENSE_CMD_DUMP */ + struct __ec_todo_unpacked { + /* Flags representing the motion sensor module. */ + uint8_t module_flags; + + /* Number of sensors managed directly by the EC */ + uint8_t sensor_count; + + /* + * sensor data is truncated if response_max is too small + * for holding all the data. + */ + struct ec_response_motion_sensor_data sensor[0]; + } dump; + + /* Used for MOTIONSENSE_CMD_INFO. */ + struct __ec_todo_unpacked { + /* Should be element of enum motionsensor_type. */ + uint8_t type; + + /* Should be element of enum motionsensor_location. */ + uint8_t location; + + /* Should be element of enum motionsensor_chip. */ + uint8_t chip; + } info; + + /* Used for MOTIONSENSE_CMD_INFO version 3 */ + struct __ec_todo_unpacked { + /* Should be element of enum motionsensor_type. */ + uint8_t type; + + /* Should be element of enum motionsensor_location. */ + uint8_t location; + + /* Should be element of enum motionsensor_chip. */ + uint8_t chip; + + /* Minimum sensor sampling frequency */ + uint32_t min_frequency; + + /* Maximum sensor sampling frequency */ + uint32_t max_frequency; + + /* Max number of sensor events that could be in fifo */ + uint32_t fifo_max_event_count; + } info_3; + + /* Used for MOTIONSENSE_CMD_DATA */ + struct ec_response_motion_sensor_data data; + + /* + * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR, + * MOTIONSENSE_CMD_SENSOR_RANGE, + * MOTIONSENSE_CMD_KB_WAKE_ANGLE, + * MOTIONSENSE_CMD_FIFO_INT_ENABLE and + * MOTIONSENSE_CMD_SPOOF. + */ + struct __ec_todo_unpacked { + /* Current value of the parameter queried. */ + int32_t ret; + } ec_rate, sensor_odr, sensor_range, kb_wake_angle, + fifo_int_enable, spoof; + + /* Used for MOTIONSENSE_CMD_SENSOR_OFFSET */ + struct __ec_todo_unpacked { + int16_t temp; + int16_t offset[3]; + } sensor_offset, perform_calib; + + struct ec_response_motion_sense_fifo_info fifo_info, fifo_flush; + + struct ec_response_motion_sense_fifo_data fifo_read; + + struct __ec_todo_packed { + uint16_t reserved; + uint32_t enabled; + uint32_t disabled; + } list_activities; + + struct __ec_todo_unpacked { + } set_activity; + + /* Used for MOTIONSENSE_CMD_LID_ANGLE */ + struct __ec_todo_unpacked { + /* + * Angle between 0 and 360 degree if available, + * LID_ANGLE_UNRELIABLE otherwise. + */ + uint16_t value; + } lid_angle; + }; +}; + +/*****************************************************************************/ +/* Force lid open command */ + +/* Make lid event always open */ +#define EC_CMD_FORCE_LID_OPEN 0x002C + +struct __ec_align1 ec_params_force_lid_open { + uint8_t enabled; +}; + +/*****************************************************************************/ +/* Configure the behavior of the power button */ +#define EC_CMD_CONFIG_POWER_BUTTON 0x002D + +enum ec_config_power_button_flags { + /* Enable/Disable power button pulses for x86 devices */ + EC_POWER_BUTTON_ENABLE_PULSE = (1 << 0), +}; + +struct __ec_align1 ec_params_config_power_button { + /* See enum ec_config_power_button_flags */ + uint8_t flags; +}; + +/*****************************************************************************/ +/* USB charging control commands */ + +/* Set USB port charging mode */ +#define EC_CMD_USB_CHARGE_SET_MODE 0x0030 + +struct __ec_align1 ec_params_usb_charge_set_mode { + uint8_t usb_port_id; + uint8_t mode; +}; + +/*****************************************************************************/ +/* Persistent storage for host */ + +/* Maximum bytes that can be read/written in a single command */ +#define EC_PSTORE_SIZE_MAX 64 + +/* Get persistent storage info */ +#define EC_CMD_PSTORE_INFO 0x0040 + +struct __ec_align4 ec_response_pstore_info { + /* Persistent storage size, in bytes */ + uint32_t pstore_size; + /* Access size; read/write offset and size must be a multiple of this */ + uint32_t access_size; +}; + +/* + * Read persistent storage + * + * Response is params.size bytes of data. + */ +#define EC_CMD_PSTORE_READ 0x0041 + +struct __ec_align4 ec_params_pstore_read { + uint32_t offset; /* Byte offset to read */ + uint32_t size; /* Size to read in bytes */ +}; + +/* Write persistent storage */ +#define EC_CMD_PSTORE_WRITE 0x0042 + +struct __ec_align4 ec_params_pstore_write { + uint32_t offset; /* Byte offset to write */ + uint32_t size; /* Size to write in bytes */ + uint8_t data[EC_PSTORE_SIZE_MAX]; +}; + +/*****************************************************************************/ +/* Real-time clock */ + +/* RTC params and response structures */ +struct __ec_align4 ec_params_rtc { + uint32_t time; +}; + +struct __ec_align4 ec_response_rtc { + uint32_t time; +}; + +/* These use ec_response_rtc */ +#define EC_CMD_RTC_GET_VALUE 0x0044 +#define EC_CMD_RTC_GET_ALARM 0x0045 + +/* These all use ec_params_rtc */ +#define EC_CMD_RTC_SET_VALUE 0x0046 +#define EC_CMD_RTC_SET_ALARM 0x0047 + +/* Pass as time param to SET_ALARM to clear the current alarm */ +#define EC_RTC_ALARM_CLEAR 0 + +/*****************************************************************************/ +/* Port80 log access */ + +/* Maximum entries that can be read/written in a single command */ +#define EC_PORT80_SIZE_MAX 32 + +/* Get last port80 code from previous boot */ +#define EC_CMD_PORT80_LAST_BOOT 0x0048 +#define EC_CMD_PORT80_READ 0x0048 + +enum ec_port80_subcmd { + EC_PORT80_GET_INFO = 0, + EC_PORT80_READ_BUFFER, +}; + +struct __ec_todo_packed ec_params_port80_read { + uint16_t subcmd; + union { + struct __ec_todo_unpacked { + uint32_t offset; + uint32_t num_entries; + } read_buffer; + }; +}; + +struct __ec_todo_packed ec_response_port80_read { + union { + struct __ec_todo_unpacked { + uint32_t writes; + uint32_t history_size; + uint32_t last_boot; + } get_info; + struct __ec_todo_unpacked { + uint16_t codes[EC_PORT80_SIZE_MAX]; + } data; + }; +}; + +struct __ec_align2 ec_response_port80_last_boot { + uint16_t code; +}; + +/*****************************************************************************/ +/* Temporary secure storage for host verified boot use */ + +/* Number of bytes in a vstore slot */ +#define EC_VSTORE_SLOT_SIZE 64 + +/* Maximum number of vstore slots */ +#define EC_VSTORE_SLOT_MAX 32 + +/* Get persistent storage info */ +#define EC_CMD_VSTORE_INFO 0x0049 +struct __ec_align_size1 ec_response_vstore_info { + /* Indicates which slots are locked */ + uint32_t slot_locked; + /* Total number of slots available */ + uint8_t slot_count; +}; + +/* + * Read temporary secure storage + * + * Response is EC_VSTORE_SLOT_SIZE bytes of data. + */ +#define EC_CMD_VSTORE_READ 0x004A + +struct __ec_align1 ec_params_vstore_read { + uint8_t slot; /* Slot to read from */ +}; + +struct __ec_align1 ec_response_vstore_read { + uint8_t data[EC_VSTORE_SLOT_SIZE]; +}; + +/* + * Write temporary secure storage and lock it. + */ +#define EC_CMD_VSTORE_WRITE 0x004B + +struct __ec_align1 ec_params_vstore_write { + uint8_t slot; /* Slot to write to */ + uint8_t data[EC_VSTORE_SLOT_SIZE]; +}; + +/*****************************************************************************/ +/* Thermal engine commands. Note that there are two implementations. We'll + * reuse the command number, but the data and behavior is incompatible. + * Version 0 is what originally shipped on Link. + * Version 1 separates the CPU thermal limits from the fan control. + */ + +#define EC_CMD_THERMAL_SET_THRESHOLD 0x0050 +#define EC_CMD_THERMAL_GET_THRESHOLD 0x0051 + +/* The version 0 structs are opaque. You have to know what they are for + * the get/set commands to make any sense. + */ + +/* Version 0 - set */ +struct __ec_align2 ec_params_thermal_set_threshold { + uint8_t sensor_type; + uint8_t threshold_id; + uint16_t value; +}; + +/* Version 0 - get */ +struct __ec_align1 ec_params_thermal_get_threshold { + uint8_t sensor_type; + uint8_t threshold_id; +}; + +struct __ec_align2 ec_response_thermal_get_threshold { + uint16_t value; +}; + + +/* The version 1 structs are visible. */ +enum ec_temp_thresholds { + EC_TEMP_THRESH_WARN = 0, + EC_TEMP_THRESH_HIGH, + EC_TEMP_THRESH_HALT, + + EC_TEMP_THRESH_COUNT +}; + +/* + * Thermal configuration for one temperature sensor. Temps are in degrees K. + * Zero values will be silently ignored by the thermal task. + * + * Note that this structure is a sub-structure of + * ec_params_thermal_set_threshold_v1, but maintains its alignment there. + */ +struct __ec_align4 ec_thermal_config { + uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */ + uint32_t temp_fan_off; /* no active cooling needed */ + uint32_t temp_fan_max; /* max active cooling needed */ +}; + +/* Version 1 - get config for one sensor. */ +struct __ec_align4 ec_params_thermal_get_threshold_v1 { + uint32_t sensor_num; +}; +/* This returns a struct ec_thermal_config */ + +/* Version 1 - set config for one sensor. + * Use read-modify-write for best results! */ +struct __ec_align4 ec_params_thermal_set_threshold_v1 { + uint32_t sensor_num; + struct ec_thermal_config cfg; +}; +/* This returns no data */ + +/****************************************************************************/ + +/* Toggle automatic fan control */ +#define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x0052 + +/* Version 1 of input params */ +struct __ec_align1 ec_params_auto_fan_ctrl_v1 { + uint8_t fan_idx; +}; + +/* Get/Set TMP006 calibration data */ +#define EC_CMD_TMP006_GET_CALIBRATION 0x0053 +#define EC_CMD_TMP006_SET_CALIBRATION 0x0054 + +/* + * The original TMP006 calibration only needed four params, but now we need + * more. Since the algorithm is nothing but magic numbers anyway, we'll leave + * the params opaque. The v1 "get" response will include the algorithm number + * and how many params it requires. That way we can change the EC code without + * needing to update this file. We can also use a different algorithm on each + * sensor. + */ + +/* This is the same struct for both v0 and v1. */ +struct __ec_align1 ec_params_tmp006_get_calibration { + uint8_t index; +}; + +/* Version 0 */ +struct __ec_align4 ec_response_tmp006_get_calibration_v0 { + float s0; + float b0; + float b1; + float b2; +}; + +struct __ec_align4 ec_params_tmp006_set_calibration_v0 { + uint8_t index; + uint8_t reserved[3]; + float s0; + float b0; + float b1; + float b2; +}; + +/* Version 1 */ +struct __ec_align4 ec_response_tmp006_get_calibration_v1 { + uint8_t algorithm; + uint8_t num_params; + uint8_t reserved[2]; + float val[0]; +}; + +struct __ec_align4 ec_params_tmp006_set_calibration_v1 { + uint8_t index; + uint8_t algorithm; + uint8_t num_params; + uint8_t reserved; + float val[0]; +}; + + +/* Read raw TMP006 data */ +#define EC_CMD_TMP006_GET_RAW 0x0055 + +struct __ec_align1 ec_params_tmp006_get_raw { + uint8_t index; +}; + +struct __ec_align4 ec_response_tmp006_get_raw { + int32_t t; /* In 1/100 K */ + int32_t v; /* In nV */ +}; + +/*****************************************************************************/ +/* MKBP - Matrix KeyBoard Protocol */ + +/* + * Read key state + * + * Returns raw data for keyboard cols; see ec_response_mkbp_info.cols for + * expected response size. + * + * NOTE: This has been superseded by EC_CMD_MKBP_GET_NEXT_EVENT. If you wish + * to obtain the instantaneous state, use EC_CMD_MKBP_INFO with the type + * EC_MKBP_INFO_CURRENT and event EC_MKBP_EVENT_KEY_MATRIX. + */ +#define EC_CMD_MKBP_STATE 0x0060 + +/* + * Provide information about various MKBP things. See enum ec_mkbp_info_type. + */ +#define EC_CMD_MKBP_INFO 0x0061 + +struct __ec_align_size1 ec_response_mkbp_info { + uint32_t rows; + uint32_t cols; + /* Formerly "switches", which was 0. */ + uint8_t reserved; +}; + +struct __ec_align1 ec_params_mkbp_info { + uint8_t info_type; + uint8_t event_type; +}; + +enum ec_mkbp_info_type { + /* + * Info about the keyboard matrix: number of rows and columns. + * + * Returns struct ec_response_mkbp_info. + */ + EC_MKBP_INFO_KBD = 0, + + /* + * For buttons and switches, info about which specifically are + * supported. event_type must be set to one of the values in enum + * ec_mkbp_event. + * + * For EC_MKBP_EVENT_BUTTON and EC_MKBP_EVENT_SWITCH, returns a 4 byte + * bitmask indicating which buttons or switches are present. See the + * bit inidices below. + */ + EC_MKBP_INFO_SUPPORTED = 1, + + /* + * Instantaneous state of buttons and switches. + * + * event_type must be set to one of the values in enum ec_mkbp_event. + * + * For EC_MKBP_EVENT_KEY_MATRIX, returns uint8_t key_matrix[13] + * indicating the current state of the keyboard matrix. + * + * For EC_MKBP_EVENT_HOST_EVENT, return uint32_t host_event, the raw + * event state. + * + * For EC_MKBP_EVENT_BUTTON, returns uint32_t buttons, indicating the + * state of supported buttons. + * + * For EC_MKBP_EVENT_SWITCH, returns uint32_t switches, indicating the + * state of supported switches. + */ + EC_MKBP_INFO_CURRENT = 2, +}; + +/* Simulate key press */ +#define EC_CMD_MKBP_SIMULATE_KEY 0x0062 + +struct __ec_align1 ec_params_mkbp_simulate_key { + uint8_t col; + uint8_t row; + uint8_t pressed; +}; + +/* Configure keyboard scanning */ +#define EC_CMD_MKBP_SET_CONFIG 0x0064 +#define EC_CMD_MKBP_GET_CONFIG 0x0065 + +/* flags */ +enum mkbp_config_flags { + EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */ +}; + +enum mkbp_config_valid { + EC_MKBP_VALID_SCAN_PERIOD = 1 << 0, + EC_MKBP_VALID_POLL_TIMEOUT = 1 << 1, + EC_MKBP_VALID_MIN_POST_SCAN_DELAY = 1 << 3, + EC_MKBP_VALID_OUTPUT_SETTLE = 1 << 4, + EC_MKBP_VALID_DEBOUNCE_DOWN = 1 << 5, + EC_MKBP_VALID_DEBOUNCE_UP = 1 << 6, + EC_MKBP_VALID_FIFO_MAX_DEPTH = 1 << 7, +}; + +/* + * Configuration for our key scanning algorithm. + * + * Note that this is used as a sub-structure of + * ec_{params/response}_mkbp_get_config. + */ +struct __ec_align_size1 ec_mkbp_config { + uint32_t valid_mask; /* valid fields */ + uint8_t flags; /* some flags (enum mkbp_config_flags) */ + uint8_t valid_flags; /* which flags are valid */ + uint16_t scan_period_us; /* period between start of scans */ + /* revert to interrupt mode after no activity for this long */ + uint32_t poll_timeout_us; + /* + * minimum post-scan relax time. Once we finish a scan we check + * the time until we are due to start the next one. If this time is + * shorter this field, we use this instead. + */ + uint16_t min_post_scan_delay_us; + /* delay between setting up output and waiting for it to settle */ + uint16_t output_settle_us; + uint16_t debounce_down_us; /* time for debounce on key down */ + uint16_t debounce_up_us; /* time for debounce on key up */ + /* maximum depth to allow for fifo (0 = no keyscan output) */ + uint8_t fifo_max_depth; +}; + +struct __ec_align_size1 ec_params_mkbp_set_config { + struct ec_mkbp_config config; +}; + +struct __ec_align_size1 ec_response_mkbp_get_config { + struct ec_mkbp_config config; +}; + +/* Run the key scan emulation */ +#define EC_CMD_KEYSCAN_SEQ_CTRL 0x0066 + +enum ec_keyscan_seq_cmd { + EC_KEYSCAN_SEQ_STATUS = 0, /* Get status information */ + EC_KEYSCAN_SEQ_CLEAR = 1, /* Clear sequence */ + EC_KEYSCAN_SEQ_ADD = 2, /* Add item to sequence */ + EC_KEYSCAN_SEQ_START = 3, /* Start running sequence */ + EC_KEYSCAN_SEQ_COLLECT = 4, /* Collect sequence summary data */ +}; + +enum ec_collect_flags { + /* + * Indicates this scan was processed by the EC. Due to timing, some + * scans may be skipped. + */ + EC_KEYSCAN_SEQ_FLAG_DONE = 1 << 0, +}; + +struct __ec_align1 ec_collect_item { + uint8_t flags; /* some flags (enum ec_collect_flags) */ +}; + +struct __ec_todo_packed ec_params_keyscan_seq_ctrl { + uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */ + union { + struct __ec_align1 { + uint8_t active; /* still active */ + uint8_t num_items; /* number of items */ + /* Current item being presented */ + uint8_t cur_item; + } status; + struct __ec_todo_unpacked { + /* + * Absolute time for this scan, measured from the + * start of the sequence. + */ + uint32_t time_us; + uint8_t scan[0]; /* keyscan data */ + } add; + struct __ec_align1 { + uint8_t start_item; /* First item to return */ + uint8_t num_items; /* Number of items to return */ + } collect; + }; +}; + +struct __ec_todo_packed ec_result_keyscan_seq_ctrl { + union { + struct __ec_todo_unpacked { + uint8_t num_items; /* Number of items */ + /* Data for each item */ + struct ec_collect_item item[0]; + } collect; + }; +}; + +/* + * Get the next pending MKBP event. + * + * Returns EC_RES_UNAVAILABLE if there is no event pending. + */ +#define EC_CMD_GET_NEXT_EVENT 0x0067 + +enum ec_mkbp_event { + /* Keyboard matrix changed. The event data is the new matrix state. */ + EC_MKBP_EVENT_KEY_MATRIX = 0, + + /* New host event. The event data is 4 bytes of host event flags. */ + EC_MKBP_EVENT_HOST_EVENT = 1, + + /* New Sensor FIFO data. The event data is fifo_info structure. */ + EC_MKBP_EVENT_SENSOR_FIFO = 2, + + /* The state of the non-matrixed buttons have changed. */ + EC_MKBP_EVENT_BUTTON = 3, + + /* The state of the switches have changed. */ + EC_MKBP_EVENT_SWITCH = 4, + + /* New Fingerprint sensor event, the event data is fp_events bitmap. */ + EC_MKBP_EVENT_FINGERPRINT = 5, + + /* + * Sysrq event: send emulated sysrq. The event data is sysrq, + * corresponding to the key to be pressed. + */ + EC_MKBP_EVENT_SYSRQ = 6, + + /* Number of MKBP events */ + EC_MKBP_EVENT_COUNT, +}; + +union __ec_align_offset1 ec_response_get_next_data { + uint8_t key_matrix[13]; + + /* Unaligned */ + uint32_t host_event; + + struct __ec_todo_unpacked { + /* For aligning the fifo_info */ + uint8_t reserved[3]; + struct ec_response_motion_sense_fifo_info info; + } sensor_fifo; + + uint32_t buttons; + + uint32_t switches; + + uint32_t fp_events; + + uint32_t sysrq; +}; + +struct __ec_align1 ec_response_get_next_event { + uint8_t event_type; + /* Followed by event data if any */ + union ec_response_get_next_data data; +}; + +/* Bit indices for buttons and switches.*/ +/* Buttons */ +#define EC_MKBP_POWER_BUTTON 0 +#define EC_MKBP_VOL_UP 1 +#define EC_MKBP_VOL_DOWN 2 +#define EC_MKBP_RECOVERY 3 + +/* Switches */ +#define EC_MKBP_LID_OPEN 0 +#define EC_MKBP_TABLET_MODE 1 + +/* Run keyboard factory test scanning */ +#define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068 + +struct __ec_align2 ec_response_keyboard_factory_test { + uint16_t shorted; /* Keyboard pins are shorted */ +}; + +/* Fingerprint events in 'fp_events' for EC_MKBP_EVENT_FINGERPRINT */ +#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF) +#define EC_MKBP_FP_FINGER_DOWN (1 << 29) +#define EC_MKBP_FP_FINGER_UP (1 << 30) +#define EC_MKBP_FP_IMAGE_READY (1 << 31) + +/*****************************************************************************/ +/* Temperature sensor commands */ + +/* Read temperature sensor info */ +#define EC_CMD_TEMP_SENSOR_GET_INFO 0x0070 + +struct __ec_align1 ec_params_temp_sensor_get_info { + uint8_t id; +}; + +struct __ec_align1 ec_response_temp_sensor_get_info { + char sensor_name[32]; + uint8_t sensor_type; +}; + +/*****************************************************************************/ + +/* + * Note: host commands 0x80 - 0x87 are reserved to avoid conflict with ACPI + * commands accidentally sent to the wrong interface. See the ACPI section + * below. + */ + +/*****************************************************************************/ +/* Host event commands */ + + +/* Obsolete. New implementation should use EC_CMD_PROGRAM_HOST_EVENT instead */ +/* + * Host event mask params and response structures, shared by all of the host + * event commands below. + */ +struct __ec_align4 ec_params_host_event_mask { + uint32_t mask; +}; + +struct __ec_align4 ec_response_host_event_mask { + uint32_t mask; +}; + +/* These all use ec_response_host_event_mask */ +#define EC_CMD_HOST_EVENT_GET_B 0x0087 +#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088 +#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089 +#define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x008D + +/* These all use ec_params_host_event_mask */ +#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A +#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B +#define EC_CMD_HOST_EVENT_CLEAR 0x008C +#define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x008E +#define EC_CMD_HOST_EVENT_CLEAR_B 0x008F + +/* + * Unified host event programming interface - Should be used by newer versions + * of BIOS/OS to program host events and masks + */ + +struct __ec_align4 ec_params_host_event { + + /* Action requested by host - one of enum ec_host_event_action. */ + uint8_t action; + + /* + * Mask type that the host requested the action on - one of + * enum ec_host_event_mask_type. + */ + uint8_t mask_type; + + /* Set to 0, ignore on read */ + uint16_t reserved; + + /* Value to be used in case of set operations. */ + uint64_t value; +}; + +/* + * Response structure returned by EC_CMD_HOST_EVENT. + * Update the value on a GET request. Set to 0 on GET/CLEAR + */ + +struct __ec_align4 ec_response_host_event { + + /* Mask value in case of get operation */ + uint64_t value; +}; + +enum ec_host_event_action { + /* + * params.value is ignored. Value of mask_type populated + * in response.value + */ + EC_HOST_EVENT_GET, + + /* Bits in params.value are set */ + EC_HOST_EVENT_SET, + + /* Bits in params.value are cleared */ + EC_HOST_EVENT_CLEAR, +}; + +enum ec_host_event_mask_type { + + /* Main host event copy */ + EC_HOST_EVENT_MAIN, + + /* Copy B of host events */ + EC_HOST_EVENT_B, + + /* SCI Mask */ + EC_HOST_EVENT_SCI_MASK, + + /* SMI Mask */ + EC_HOST_EVENT_SMI_MASK, + + /* Mask of events that should be always reported in hostevents */ + EC_HOST_EVENT_ALWAYS_REPORT_MASK, + + /* Active wake mask */ + EC_HOST_EVENT_ACTIVE_WAKE_MASK, + + /* Lazy wake mask for S0ix */ + EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX, + + /* Lazy wake mask for S3 */ + EC_HOST_EVENT_LAZY_WAKE_MASK_S3, + + /* Lazy wake mask for S5 */ + EC_HOST_EVENT_LAZY_WAKE_MASK_S5, +}; + +#define EC_CMD_HOST_EVENT 0x00A4 + +/*****************************************************************************/ +/* Switch commands */ + +/* Enable/disable LCD backlight */ +#define EC_CMD_SWITCH_ENABLE_BKLIGHT 0x0090 + +struct __ec_align1 ec_params_switch_enable_backlight { + uint8_t enabled; +}; + +/* Enable/disable WLAN/Bluetooth */ +#define EC_CMD_SWITCH_ENABLE_WIRELESS 0x0091 +#define EC_VER_SWITCH_ENABLE_WIRELESS 1 + +/* Version 0 params; no response */ +struct __ec_align1 ec_params_switch_enable_wireless_v0 { + uint8_t enabled; +}; + +/* Version 1 params */ +struct __ec_align1 ec_params_switch_enable_wireless_v1 { + /* Flags to enable now */ + uint8_t now_flags; + + /* Which flags to copy from now_flags */ + uint8_t now_mask; + + /* + * Flags to leave enabled in S3, if they're on at the S0->S3 + * transition. (Other flags will be disabled by the S0->S3 + * transition.) + */ + uint8_t suspend_flags; + + /* Which flags to copy from suspend_flags */ + uint8_t suspend_mask; +}; + +/* Version 1 response */ +struct __ec_align1 ec_response_switch_enable_wireless_v1 { + /* Flags to enable now */ + uint8_t now_flags; + + /* Flags to leave enabled in S3 */ + uint8_t suspend_flags; +}; + +/*****************************************************************************/ +/* GPIO commands. Only available on EC if write protect has been disabled. */ + +/* Set GPIO output value */ +#define EC_CMD_GPIO_SET 0x0092 + +struct __ec_align1 ec_params_gpio_set { + char name[32]; + uint8_t val; +}; + +/* Get GPIO value */ +#define EC_CMD_GPIO_GET 0x0093 + +/* Version 0 of input params and response */ +struct __ec_align1 ec_params_gpio_get { + char name[32]; +}; + +struct __ec_align1 ec_response_gpio_get { + uint8_t val; +}; + +/* Version 1 of input params and response */ +struct __ec_align1 ec_params_gpio_get_v1 { + uint8_t subcmd; + union { + struct __ec_align1 { + char name[32]; + } get_value_by_name; + struct __ec_align1 { + uint8_t index; + } get_info; + }; +}; + +struct __ec_todo_packed ec_response_gpio_get_v1 { + union { + struct __ec_align1 { + uint8_t val; + } get_value_by_name, get_count; + struct __ec_todo_unpacked { + uint8_t val; + char name[32]; + uint32_t flags; + } get_info; + }; +}; + +enum gpio_get_subcmd { + EC_GPIO_GET_BY_NAME = 0, + EC_GPIO_GET_COUNT = 1, + EC_GPIO_GET_INFO = 2, +}; + +/*****************************************************************************/ +/* I2C commands. Only available when flash write protect is unlocked. */ + +/* + * CAUTION: These commands are deprecated, and are not supported anymore in EC + * builds >= 8398.0.0 (see crosbug.com/p/23570). + * + * Use EC_CMD_I2C_PASSTHRU instead. + */ + +/* Read I2C bus */ +#define EC_CMD_I2C_READ 0x0094 + +struct __ec_align_size1 ec_params_i2c_read { + uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ + uint8_t read_size; /* Either 8 or 16. */ + uint8_t port; + uint8_t offset; +}; + +struct __ec_align2 ec_response_i2c_read { + uint16_t data; +}; + +/* Write I2C bus */ +#define EC_CMD_I2C_WRITE 0x0095 + +struct __ec_align_size1 ec_params_i2c_write { + uint16_t data; + uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ + uint8_t write_size; /* Either 8 or 16. */ + uint8_t port; + uint8_t offset; +}; + +/*****************************************************************************/ +/* Charge state commands. Only available when flash write protect unlocked. */ + +/* Force charge state machine to stop charging the battery or force it to + * discharge the battery. + */ +#define EC_CMD_CHARGE_CONTROL 0x0096 +#define EC_VER_CHARGE_CONTROL 1 + +enum ec_charge_control_mode { + CHARGE_CONTROL_NORMAL = 0, + CHARGE_CONTROL_IDLE, + CHARGE_CONTROL_DISCHARGE, +}; + +struct __ec_align4 ec_params_charge_control { + uint32_t mode; /* enum charge_control_mode */ +}; + +/*****************************************************************************/ +/* Console commands. Only available when flash write protect is unlocked. */ + +/* Snapshot console output buffer for use by EC_CMD_CONSOLE_READ. */ +#define EC_CMD_CONSOLE_SNAPSHOT 0x0097 + +/* + * Read data from the saved snapshot. If the subcmd parameter is + * CONSOLE_READ_NEXT, this will return data starting from the beginning of + * the latest snapshot. If it is CONSOLE_READ_RECENT, it will start from the + * end of the previous snapshot. + * + * The params are only looked at in version >= 1 of this command. Prior + * versions will just default to CONSOLE_READ_NEXT behavior. + * + * Response is null-terminated string. Empty string, if there is no more + * remaining output. + */ +#define EC_CMD_CONSOLE_READ 0x0098 + +enum ec_console_read_subcmd { + CONSOLE_READ_NEXT = 0, + CONSOLE_READ_RECENT +}; + +struct __ec_align1 ec_params_console_read_v1 { + uint8_t subcmd; /* enum ec_console_read_subcmd */ +}; + +/*****************************************************************************/ + +/* + * Cut off battery power immediately or after the host has shut down. + * + * return EC_RES_INVALID_COMMAND if unsupported by a board/battery. + * EC_RES_SUCCESS if the command was successful. + * EC_RES_ERROR if the cut off command failed. + */ +#define EC_CMD_BATTERY_CUT_OFF 0x0099 + +#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN (1 << 0) + +struct __ec_align1 ec_params_battery_cutoff { + uint8_t flags; +}; + +/*****************************************************************************/ +/* USB port mux control. */ + +/* + * Switch USB mux or return to automatic switching. + */ +#define EC_CMD_USB_MUX 0x009A + +struct __ec_align1 ec_params_usb_mux { + uint8_t mux; +}; + +/*****************************************************************************/ +/* LDOs / FETs control. */ + +enum ec_ldo_state { + EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */ + EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */ +}; + +/* + * Switch on/off a LDO. + */ +#define EC_CMD_LDO_SET 0x009B + +struct __ec_align1 ec_params_ldo_set { + uint8_t index; + uint8_t state; +}; + +/* + * Get LDO state. + */ +#define EC_CMD_LDO_GET 0x009C + +struct __ec_align1 ec_params_ldo_get { + uint8_t index; +}; + +struct __ec_align1 ec_response_ldo_get { + uint8_t state; +}; + +/*****************************************************************************/ +/* Power info. */ + +/* + * Get power info. + */ +#define EC_CMD_POWER_INFO 0x009D + +struct __ec_align4 ec_response_power_info { + uint32_t usb_dev_type; + uint16_t voltage_ac; + uint16_t voltage_system; + uint16_t current_system; + uint16_t usb_current_limit; +}; + +/*****************************************************************************/ +/* I2C passthru command */ + +#define EC_CMD_I2C_PASSTHRU 0x009E + +/* Read data; if not present, message is a write */ +#define EC_I2C_FLAG_READ (1 << 15) + +/* Mask for address */ +#define EC_I2C_ADDR_MASK 0x3ff + +#define EC_I2C_STATUS_NAK (1 << 0) /* Transfer was not acknowledged */ +#define EC_I2C_STATUS_TIMEOUT (1 << 1) /* Timeout during transfer */ + +/* Any error */ +#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) + +struct __ec_align2 ec_params_i2c_passthru_msg { + uint16_t addr_flags; /* I2C slave address (7 or 10 bits) and flags */ + uint16_t len; /* Number of bytes to read or write */ +}; + +struct __ec_align2 ec_params_i2c_passthru { + uint8_t port; /* I2C port number */ + uint8_t num_msgs; /* Number of messages */ + struct ec_params_i2c_passthru_msg msg[]; + /* Data to write for all messages is concatenated here */ +}; + +struct __ec_align1 ec_response_i2c_passthru { + uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */ + uint8_t num_msgs; /* Number of messages processed */ + uint8_t data[]; /* Data read by messages concatenated here */ +}; + +/*****************************************************************************/ +/* Power button hang detect */ + +#define EC_CMD_HANG_DETECT 0x009F + +/* Reasons to start hang detection timer */ +/* Power button pressed */ +#define EC_HANG_START_ON_POWER_PRESS (1 << 0) + +/* Lid closed */ +#define EC_HANG_START_ON_LID_CLOSE (1 << 1) + + /* Lid opened */ +#define EC_HANG_START_ON_LID_OPEN (1 << 2) + +/* Start of AP S3->S0 transition (booting or resuming from suspend) */ +#define EC_HANG_START_ON_RESUME (1 << 3) + +/* Reasons to cancel hang detection */ + +/* Power button released */ +#define EC_HANG_STOP_ON_POWER_RELEASE (1 << 8) + +/* Any host command from AP received */ +#define EC_HANG_STOP_ON_HOST_COMMAND (1 << 9) + +/* Stop on end of AP S0->S3 transition (suspending or shutting down) */ +#define EC_HANG_STOP_ON_SUSPEND (1 << 10) + +/* + * If this flag is set, all the other fields are ignored, and the hang detect + * timer is started. This provides the AP a way to start the hang timer + * without reconfiguring any of the other hang detect settings. Note that + * you must previously have configured the timeouts. + */ +#define EC_HANG_START_NOW (1 << 30) + +/* + * If this flag is set, all the other fields are ignored (including + * EC_HANG_START_NOW). This provides the AP a way to stop the hang timer + * without reconfiguring any of the other hang detect settings. + */ +#define EC_HANG_STOP_NOW (1 << 31) + +struct __ec_align4 ec_params_hang_detect { + /* Flags; see EC_HANG_* */ + uint32_t flags; + + /* Timeout in msec before generating host event, if enabled */ + uint16_t host_event_timeout_msec; + + /* Timeout in msec before generating warm reboot, if enabled */ + uint16_t warm_reboot_timeout_msec; +}; + +/*****************************************************************************/ +/* Commands for battery charging */ + +/* + * This is the single catch-all host command to exchange data regarding the + * charge state machine (v2 and up). + */ +#define EC_CMD_CHARGE_STATE 0x00A0 + +/* Subcommands for this host command */ +enum charge_state_command { + CHARGE_STATE_CMD_GET_STATE, + CHARGE_STATE_CMD_GET_PARAM, + CHARGE_STATE_CMD_SET_PARAM, + CHARGE_STATE_NUM_CMDS +}; + +/* + * Known param numbers are defined here. Ranges are reserved for board-specific + * params, which are handled by the particular implementations. + */ +enum charge_state_params { + CS_PARAM_CHG_VOLTAGE, /* charger voltage limit */ + CS_PARAM_CHG_CURRENT, /* charger current limit */ + CS_PARAM_CHG_INPUT_CURRENT, /* charger input current limit */ + CS_PARAM_CHG_STATUS, /* charger-specific status */ + CS_PARAM_CHG_OPTION, /* charger-specific options */ + CS_PARAM_LIMIT_POWER, /* + * Check if power is limited due to + * low battery and / or a weak external + * charger. READ ONLY. + */ + /* How many so far? */ + CS_NUM_BASE_PARAMS, + + /* Range for CONFIG_CHARGER_PROFILE_OVERRIDE params */ + CS_PARAM_CUSTOM_PROFILE_MIN = 0x10000, + CS_PARAM_CUSTOM_PROFILE_MAX = 0x1ffff, + + /* Other custom param ranges go here... */ +}; + +struct __ec_todo_packed ec_params_charge_state { + uint8_t cmd; /* enum charge_state_command */ + union { + struct __ec_align1 { + /* no args */ + } get_state; + + struct __ec_todo_unpacked { + uint32_t param; /* enum charge_state_param */ + } get_param; + + struct __ec_todo_unpacked { + uint32_t param; /* param to set */ + uint32_t value; /* value to set */ + } set_param; + }; +}; + +struct __ec_align4 ec_response_charge_state { + union { + struct __ec_align4 { + int ac; + int chg_voltage; + int chg_current; + int chg_input_current; + int batt_state_of_charge; + } get_state; + + struct __ec_align4 { + uint32_t value; + } get_param; + struct __ec_align4 { + /* no return values */ + } set_param; + }; +}; + + +/* + * Set maximum battery charging current. + */ +#define EC_CMD_CHARGE_CURRENT_LIMIT 0x00A1 + +struct __ec_align4 ec_params_current_limit { + uint32_t limit; /* in mA */ +}; + +/* + * Set maximum external voltage / current. + */ +#define EC_CMD_EXTERNAL_POWER_LIMIT 0x00A2 + +/* Command v0 is used only on Spring and is obsolete + unsupported */ +struct __ec_align2 ec_params_external_power_limit_v1 { + uint16_t current_lim; /* in mA, or EC_POWER_LIMIT_NONE to clear limit */ + uint16_t voltage_lim; /* in mV, or EC_POWER_LIMIT_NONE to clear limit */ +}; + +#define EC_POWER_LIMIT_NONE 0xffff + +/* + * Set maximum voltage & current of a dedicated charge port + */ +#define EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT 0x00A3 + +struct __ec_align2 ec_params_dedicated_charger_limit { + uint16_t current_lim; /* in mA */ + uint16_t voltage_lim; /* in mV */ +}; + +/*****************************************************************************/ +/* Hibernate/Deep Sleep Commands */ + +/* Set the delay before going into hibernation. */ +#define EC_CMD_HIBERNATION_DELAY 0x00A8 + +struct __ec_align4 ec_params_hibernation_delay { + /* + * Seconds to wait in G3 before hibernate. Pass in 0 to read the + * current settings without changing them. + */ + uint32_t seconds; +}; + +struct __ec_align4 ec_response_hibernation_delay { + /* + * The current time in seconds in which the system has been in the G3 + * state. This value is reset if the EC transitions out of G3. + */ + uint32_t time_g3; + + /* + * The current time remaining in seconds until the EC should hibernate. + * This value is also reset if the EC transitions out of G3. + */ + uint32_t time_remaining; + + /* + * The current time in seconds that the EC should wait in G3 before + * hibernating. + */ + uint32_t hibernate_delay; +}; + +/* Inform the EC when entering a sleep state */ +#define EC_CMD_HOST_SLEEP_EVENT 0x00A9 + +enum host_sleep_event { + HOST_SLEEP_EVENT_S3_SUSPEND = 1, + HOST_SLEEP_EVENT_S3_RESUME = 2, + HOST_SLEEP_EVENT_S0IX_SUSPEND = 3, + HOST_SLEEP_EVENT_S0IX_RESUME = 4 +}; + +struct __ec_align1 ec_params_host_sleep_event { + uint8_t sleep_event; +}; + +/*****************************************************************************/ +/* Device events */ +#define EC_CMD_DEVICE_EVENT 0x00AA + +enum ec_device_event { + EC_DEVICE_EVENT_TRACKPAD, + EC_DEVICE_EVENT_DSP, + EC_DEVICE_EVENT_WIFI, +}; + +enum ec_device_event_param { + /* Get and clear pending device events */ + EC_DEVICE_EVENT_PARAM_GET_CURRENT_EVENTS, + /* Get device event mask */ + EC_DEVICE_EVENT_PARAM_GET_ENABLED_EVENTS, + /* Set device event mask */ + EC_DEVICE_EVENT_PARAM_SET_ENABLED_EVENTS, +}; + +#define EC_DEVICE_EVENT_MASK(event_code) (1UL << (event_code % 32)) + +struct __ec_align_size1 ec_params_device_event { + uint32_t event_mask; + uint8_t param; +}; + +struct __ec_align4 ec_response_device_event { + uint32_t event_mask; +}; + +/*****************************************************************************/ +/* Smart battery pass-through */ + +/* Get / Set 16-bit smart battery registers */ +#define EC_CMD_SB_READ_WORD 0x00B0 +#define EC_CMD_SB_WRITE_WORD 0x00B1 + +/* Get / Set string smart battery parameters + * formatted as SMBUS "block". + */ +#define EC_CMD_SB_READ_BLOCK 0x00B2 +#define EC_CMD_SB_WRITE_BLOCK 0x00B3 + +struct __ec_align1 ec_params_sb_rd { + uint8_t reg; +}; + +struct __ec_align2 ec_response_sb_rd_word { + uint16_t value; +}; + +struct __ec_align1 ec_params_sb_wr_word { + uint8_t reg; + uint16_t value; +}; + +struct __ec_align1 ec_response_sb_rd_block { + uint8_t data[32]; +}; + +struct __ec_align1 ec_params_sb_wr_block { + uint8_t reg; + uint16_t data[32]; +}; + +/*****************************************************************************/ +/* Battery vendor parameters + * + * Get or set vendor-specific parameters in the battery. Implementations may + * differ between boards or batteries. On a set operation, the response + * contains the actual value set, which may be rounded or clipped from the + * requested value. + */ + +#define EC_CMD_BATTERY_VENDOR_PARAM 0x00B4 + +enum ec_battery_vendor_param_mode { + BATTERY_VENDOR_PARAM_MODE_GET = 0, + BATTERY_VENDOR_PARAM_MODE_SET, +}; + +struct __ec_align_size1 ec_params_battery_vendor_param { + uint32_t param; + uint32_t value; + uint8_t mode; +}; + +struct __ec_align4 ec_response_battery_vendor_param { + uint32_t value; +}; + +/*****************************************************************************/ +/* + * Smart Battery Firmware Update Commands + */ +#define EC_CMD_SB_FW_UPDATE 0x00B5 + +enum ec_sb_fw_update_subcmd { + EC_SB_FW_UPDATE_PREPARE = 0x0, + EC_SB_FW_UPDATE_INFO = 0x1, /*query sb info */ + EC_SB_FW_UPDATE_BEGIN = 0x2, /*check if protected */ + EC_SB_FW_UPDATE_WRITE = 0x3, /*check if protected */ + EC_SB_FW_UPDATE_END = 0x4, + EC_SB_FW_UPDATE_STATUS = 0x5, + EC_SB_FW_UPDATE_PROTECT = 0x6, + EC_SB_FW_UPDATE_MAX = 0x7, +}; + +#define SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE 32 +#define SB_FW_UPDATE_CMD_STATUS_SIZE 2 +#define SB_FW_UPDATE_CMD_INFO_SIZE 8 + +struct __ec_align4 ec_sb_fw_update_header { + uint16_t subcmd; /* enum ec_sb_fw_update_subcmd */ + uint16_t fw_id; /* firmware id */ +}; + +struct __ec_align4 ec_params_sb_fw_update { + struct ec_sb_fw_update_header hdr; + union { + /* EC_SB_FW_UPDATE_PREPARE = 0x0 */ + /* EC_SB_FW_UPDATE_INFO = 0x1 */ + /* EC_SB_FW_UPDATE_BEGIN = 0x2 */ + /* EC_SB_FW_UPDATE_END = 0x4 */ + /* EC_SB_FW_UPDATE_STATUS = 0x5 */ + /* EC_SB_FW_UPDATE_PROTECT = 0x6 */ + struct __ec_align4 { + /* no args */ + } dummy; + + /* EC_SB_FW_UPDATE_WRITE = 0x3 */ + struct __ec_align4 { + uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE]; + } write; + }; +}; + +struct __ec_align1 ec_response_sb_fw_update { + union { + /* EC_SB_FW_UPDATE_INFO = 0x1 */ + struct __ec_align1 { + uint8_t data[SB_FW_UPDATE_CMD_INFO_SIZE]; + } info; + + /* EC_SB_FW_UPDATE_STATUS = 0x5 */ + struct __ec_align1 { + uint8_t data[SB_FW_UPDATE_CMD_STATUS_SIZE]; + } status; + }; +}; + +/* + * Entering Verified Boot Mode Command + * Default mode is VBOOT_MODE_NORMAL if EC did not receive this command. + * Valid Modes are: normal, developer, and recovery. + */ +#define EC_CMD_ENTERING_MODE 0x00B6 + +struct __ec_align4 ec_params_entering_mode { + int vboot_mode; +}; + +#define VBOOT_MODE_NORMAL 0 +#define VBOOT_MODE_DEVELOPER 1 +#define VBOOT_MODE_RECOVERY 2 + +/*****************************************************************************/ +/* + * I2C passthru protection command: Protects I2C tunnels against access on + * certain addresses (board-specific). + */ +#define EC_CMD_I2C_PASSTHRU_PROTECT 0x00B7 + +enum ec_i2c_passthru_protect_subcmd { + EC_CMD_I2C_PASSTHRU_PROTECT_STATUS = 0x0, + EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE = 0x1, +}; + +struct __ec_align1 ec_params_i2c_passthru_protect { + uint8_t subcmd; + uint8_t port; /* I2C port number */ +}; + +struct __ec_align1 ec_response_i2c_passthru_protect { + uint8_t status; /* Status flags (0: unlocked, 1: locked) */ +}; + +/*****************************************************************************/ +/* System commands */ + +/* + * TODO(crosbug.com/p/23747): This is a confusing name, since it doesn't + * necessarily reboot the EC. Rename to "image" or something similar? + */ +#define EC_CMD_REBOOT_EC 0x00D2 + +/* Command */ +enum ec_reboot_cmd { + EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */ + EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */ + EC_REBOOT_JUMP_RW = 2, /* Jump to RW without rebooting */ + /* (command 3 was jump to RW-B) */ + EC_REBOOT_COLD = 4, /* Cold-reboot */ + EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ + EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ + EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_OFF flag */ +}; + +/* Flags for ec_params_reboot_ec.reboot_flags */ +#define EC_REBOOT_FLAG_RESERVED0 (1 << 0) /* Was recovery request */ +#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN (1 << 1) /* Reboot after AP shutdown */ +#define EC_REBOOT_FLAG_SWITCH_RW_SLOT (1 << 2) /* Switch RW slot */ + +struct __ec_align1 ec_params_reboot_ec { + uint8_t cmd; /* enum ec_reboot_cmd */ + uint8_t flags; /* See EC_REBOOT_FLAG_* */ +}; + +/* + * Get information on last EC panic. + * + * Returns variable-length platform-dependent panic information. See panic.h + * for details. + */ +#define EC_CMD_GET_PANIC_INFO 0x00D3 + +/*****************************************************************************/ +/* + * Special commands + * + * These do not follow the normal rules for commands. See each command for + * details. + */ + +/* + * Reboot NOW + * + * This command will work even when the EC LPC interface is busy, because the + * reboot command is processed at interrupt level. Note that when the EC + * reboots, the host will reboot too, so there is no response to this command. + * + * Use EC_CMD_REBOOT_EC to reboot the EC more politely. + */ +#define EC_CMD_REBOOT 0x00D1 /* Think "die" */ + +/* + * Resend last response (not supported on LPC). + * + * Returns EC_RES_UNAVAILABLE if there is no response available - for example, + * there was no previous command, or the previous command's response was too + * big to save. + */ +#define EC_CMD_RESEND_RESPONSE 0x00DB + +/* + * This header byte on a command indicate version 0. Any header byte less + * than this means that we are talking to an old EC which doesn't support + * versioning. In that case, we assume version 0. + * + * Header bytes greater than this indicate a later version. For example, + * EC_CMD_VERSION0 + 1 means we are using version 1. + * + * The old EC interface must not use commands 0xdc or higher. + */ +#define EC_CMD_VERSION0 0x00DC + +/*****************************************************************************/ +/* + * PD commands + * + * These commands are for PD MCU communication. + */ + +/* EC to PD MCU exchange status command */ +#define EC_CMD_PD_EXCHANGE_STATUS 0x0100 +#define EC_VER_PD_EXCHANGE_STATUS 2 + +enum pd_charge_state { + PD_CHARGE_NO_CHANGE = 0, /* Don't change charge state */ + PD_CHARGE_NONE, /* No charging allowed */ + PD_CHARGE_5V, /* 5V charging only */ + PD_CHARGE_MAX /* Charge at max voltage */ +}; + +/* Status of EC being sent to PD */ +#define EC_STATUS_HIBERNATING (1 << 0) + +struct __ec_align1 ec_params_pd_status { + uint8_t status; /* EC status */ + int8_t batt_soc; /* battery state of charge */ + uint8_t charge_state; /* charging state (from enum pd_charge_state) */ +}; + +/* Status of PD being sent back to EC */ +#define PD_STATUS_HOST_EVENT (1 << 0) /* Forward host event to AP */ +#define PD_STATUS_IN_RW (1 << 1) /* Running RW image */ +#define PD_STATUS_JUMPED_TO_IMAGE (1 << 2) /* Current image was jumped to */ +#define PD_STATUS_TCPC_ALERT_0 (1 << 3) /* Alert active in port 0 TCPC */ +#define PD_STATUS_TCPC_ALERT_1 (1 << 4) /* Alert active in port 1 TCPC */ +#define PD_STATUS_TCPC_ALERT_2 (1 << 5) /* Alert active in port 2 TCPC */ +#define PD_STATUS_TCPC_ALERT_3 (1 << 6) /* Alert active in port 3 TCPC */ +#define PD_STATUS_EC_INT_ACTIVE (PD_STATUS_TCPC_ALERT_0 | \ + PD_STATUS_TCPC_ALERT_1 | \ + PD_STATUS_HOST_EVENT) +struct __ec_align_size1 ec_response_pd_status { + uint32_t curr_lim_ma; /* input current limit */ + uint16_t status; /* PD MCU status */ + int8_t active_charge_port; /* active charging port */ +}; + +/* AP to PD MCU host event status command, cleared on read */ +#define EC_CMD_PD_HOST_EVENT_STATUS 0x0104 + +/* PD MCU host event status bits */ +#define PD_EVENT_UPDATE_DEVICE (1 << 0) +#define PD_EVENT_POWER_CHANGE (1 << 1) +#define PD_EVENT_IDENTITY_RECEIVED (1 << 2) +#define PD_EVENT_DATA_SWAP (1 << 3) +struct __ec_align4 ec_response_host_event_status { + uint32_t status; /* PD MCU host event status */ +}; + +/* Set USB type-C port role and muxes */ +#define EC_CMD_USB_PD_CONTROL 0x0101 + +enum usb_pd_control_role { + USB_PD_CTRL_ROLE_NO_CHANGE = 0, + USB_PD_CTRL_ROLE_TOGGLE_ON = 1, /* == AUTO */ + USB_PD_CTRL_ROLE_TOGGLE_OFF = 2, + USB_PD_CTRL_ROLE_FORCE_SINK = 3, + USB_PD_CTRL_ROLE_FORCE_SOURCE = 4, + USB_PD_CTRL_ROLE_COUNT +}; + +enum usb_pd_control_mux { + USB_PD_CTRL_MUX_NO_CHANGE = 0, + USB_PD_CTRL_MUX_NONE = 1, + USB_PD_CTRL_MUX_USB = 2, + USB_PD_CTRL_MUX_DP = 3, + USB_PD_CTRL_MUX_DOCK = 4, + USB_PD_CTRL_MUX_AUTO = 5, + USB_PD_CTRL_MUX_COUNT +}; + +enum usb_pd_control_swap { + USB_PD_CTRL_SWAP_NONE = 0, + USB_PD_CTRL_SWAP_DATA = 1, + USB_PD_CTRL_SWAP_POWER = 2, + USB_PD_CTRL_SWAP_VCONN = 3, + USB_PD_CTRL_SWAP_COUNT +}; + +struct __ec_align1 ec_params_usb_pd_control { + uint8_t port; + uint8_t role; + uint8_t mux; + uint8_t swap; +}; + +#define PD_CTRL_RESP_ENABLED_COMMS (1 << 0) /* Communication enabled */ +#define PD_CTRL_RESP_ENABLED_CONNECTED (1 << 1) /* Device connected */ +#define PD_CTRL_RESP_ENABLED_PD_CAPABLE (1 << 2) /* Partner is PD capable */ + +#define PD_CTRL_RESP_ROLE_POWER (1 << 0) /* 0=SNK/1=SRC */ +#define PD_CTRL_RESP_ROLE_DATA (1 << 1) /* 0=UFP/1=DFP */ +#define PD_CTRL_RESP_ROLE_VCONN (1 << 2) /* Vconn status */ +#define PD_CTRL_RESP_ROLE_DR_POWER (1 << 3) /* Partner is dualrole power */ +#define PD_CTRL_RESP_ROLE_DR_DATA (1 << 4) /* Partner is dualrole data */ +#define PD_CTRL_RESP_ROLE_USB_COMM (1 << 5) /* Partner USB comm capable */ +#define PD_CTRL_RESP_ROLE_EXT_POWERED (1 << 6) /* Partner externally powerd */ + +struct __ec_align1 ec_response_usb_pd_control { + uint8_t enabled; + uint8_t role; + uint8_t polarity; + uint8_t state; +}; + +struct __ec_align1 ec_response_usb_pd_control_v1 { + uint8_t enabled; + uint8_t role; + uint8_t polarity; + char state[32]; +}; + +#define EC_CMD_USB_PD_PORTS 0x0102 + +/* Maximum number of PD ports on a device, num_ports will be <= this */ +#define EC_USB_PD_MAX_PORTS 8 + +struct __ec_align1 ec_response_usb_pd_ports { + uint8_t num_ports; +}; + +#define EC_CMD_USB_PD_POWER_INFO 0x0103 + +#define PD_POWER_CHARGING_PORT 0xff +struct __ec_align1 ec_params_usb_pd_power_info { + uint8_t port; +}; + +enum usb_chg_type { + USB_CHG_TYPE_NONE, + USB_CHG_TYPE_PD, + USB_CHG_TYPE_C, + USB_CHG_TYPE_PROPRIETARY, + USB_CHG_TYPE_BC12_DCP, + USB_CHG_TYPE_BC12_CDP, + USB_CHG_TYPE_BC12_SDP, + USB_CHG_TYPE_OTHER, + USB_CHG_TYPE_VBUS, + USB_CHG_TYPE_UNKNOWN, +}; +enum usb_power_roles { + USB_PD_PORT_POWER_DISCONNECTED, + USB_PD_PORT_POWER_SOURCE, + USB_PD_PORT_POWER_SINK, + USB_PD_PORT_POWER_SINK_NOT_CHARGING, +}; + +struct __ec_align2 usb_chg_measures { + uint16_t voltage_max; + uint16_t voltage_now; + uint16_t current_max; + uint16_t current_lim; +}; + +struct __ec_align4 ec_response_usb_pd_power_info { + uint8_t role; + uint8_t type; + uint8_t dualrole; + uint8_t reserved1; + struct usb_chg_measures meas; + uint32_t max_power; +}; + +/* Write USB-PD device FW */ +#define EC_CMD_USB_PD_FW_UPDATE 0x0110 + +enum usb_pd_fw_update_cmds { + USB_PD_FW_REBOOT, + USB_PD_FW_FLASH_ERASE, + USB_PD_FW_FLASH_WRITE, + USB_PD_FW_ERASE_SIG, +}; + +struct __ec_align4 ec_params_usb_pd_fw_update { + uint16_t dev_id; + uint8_t cmd; + uint8_t port; + uint32_t size; /* Size to write in bytes */ + /* Followed by data to write */ +}; + +/* Write USB-PD Accessory RW_HASH table entry */ +#define EC_CMD_USB_PD_RW_HASH_ENTRY 0x0111 +/* RW hash is first 20 bytes of SHA-256 of RW section */ +#define PD_RW_HASH_SIZE 20 +struct __ec_align1 ec_params_usb_pd_rw_hash_entry { + uint16_t dev_id; + uint8_t dev_rw_hash[PD_RW_HASH_SIZE]; + uint8_t reserved; /* For alignment of current_image + * TODO(rspangler) but it's not aligned! + * Should have been reserved[2]. */ + uint32_t current_image; /* One of ec_current_image */ +}; + +/* Read USB-PD Accessory info */ +#define EC_CMD_USB_PD_DEV_INFO 0x0112 + +struct __ec_align1 ec_params_usb_pd_info_request { + uint8_t port; +}; + +/* Read USB-PD Device discovery info */ +#define EC_CMD_USB_PD_DISCOVERY 0x0113 +struct __ec_align_size1 ec_params_usb_pd_discovery_entry { + uint16_t vid; /* USB-IF VID */ + uint16_t pid; /* USB-IF PID */ + uint8_t ptype; /* product type (hub,periph,cable,ama) */ +}; + +/* Override default charge behavior */ +#define EC_CMD_PD_CHARGE_PORT_OVERRIDE 0x0114 + +/* Negative port parameters have special meaning */ +enum usb_pd_override_ports { + OVERRIDE_DONT_CHARGE = -2, + OVERRIDE_OFF = -1, + /* [0, CONFIG_USB_PD_PORT_COUNT): Port# */ +}; + +struct __ec_align2 ec_params_charge_port_override { + int16_t override_port; /* Override port# */ +}; + +/* Read (and delete) one entry of PD event log */ +#define EC_CMD_PD_GET_LOG_ENTRY 0x0115 + +struct __ec_align4 ec_response_pd_log { + uint32_t timestamp; /* relative timestamp in milliseconds */ + uint8_t type; /* event type : see PD_EVENT_xx below */ + uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */ + uint16_t data; /* type-defined data payload */ + uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */ +}; + + +/* The timestamp is the microsecond counter shifted to get about a ms. */ +#define PD_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */ + +#define PD_LOG_SIZE_MASK 0x1f +#define PD_LOG_PORT_MASK 0xe0 +#define PD_LOG_PORT_SHIFT 5 +#define PD_LOG_PORT_SIZE(port, size) (((port) << PD_LOG_PORT_SHIFT) | \ + ((size) & PD_LOG_SIZE_MASK)) +#define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT) +#define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK) + +/* PD event log : entry types */ +/* PD MCU events */ +#define PD_EVENT_MCU_BASE 0x00 +#define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE+0) +#define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE+1) +/* Reserved for custom board event */ +#define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE+2) +/* PD generic accessory events */ +#define PD_EVENT_ACC_BASE 0x20 +#define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE+0) +#define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE+1) +/* PD power supply events */ +#define PD_EVENT_PS_BASE 0x40 +#define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE+0) +/* PD video dongles events */ +#define PD_EVENT_VIDEO_BASE 0x60 +#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE+0) +#define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE+1) +/* Returned in the "type" field, when there is no entry available */ +#define PD_EVENT_NO_ENTRY 0xff + +/* + * PD_EVENT_MCU_CHARGE event definition : + * the payload is "struct usb_chg_measures" + * the data field contains the port state flags as defined below : + */ +/* Port partner is a dual role device */ +#define CHARGE_FLAGS_DUAL_ROLE (1 << 15) +/* Port is the pending override port */ +#define CHARGE_FLAGS_DELAYED_OVERRIDE (1 << 14) +/* Port is the override port */ +#define CHARGE_FLAGS_OVERRIDE (1 << 13) +/* Charger type */ +#define CHARGE_FLAGS_TYPE_SHIFT 3 +#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT) +/* Power delivery role */ +#define CHARGE_FLAGS_ROLE_MASK (7 << 0) + +/* + * PD_EVENT_PS_FAULT data field flags definition : + */ +#define PS_FAULT_OCP 1 +#define PS_FAULT_FAST_OCP 2 +#define PS_FAULT_OVP 3 +#define PS_FAULT_DISCH 4 + +/* + * PD_EVENT_VIDEO_CODEC payload is "struct mcdp_info". + */ +struct __ec_align4 mcdp_version { + uint8_t major; + uint8_t minor; + uint16_t build; +}; + +struct __ec_align4 mcdp_info { + uint8_t family[2]; + uint8_t chipid[2]; + struct mcdp_version irom; + struct mcdp_version fw; +}; + +/* struct mcdp_info field decoding */ +#define MCDP_CHIPID(chipid) ((chipid[0] << 8) | chipid[1]) +#define MCDP_FAMILY(family) ((family[0] << 8) | family[1]) + +/* Get/Set USB-PD Alternate mode info */ +#define EC_CMD_USB_PD_GET_AMODE 0x0116 +struct __ec_align_size1 ec_params_usb_pd_get_mode_request { + uint16_t svid_idx; /* SVID index to get */ + uint8_t port; /* port */ +}; + +struct __ec_align4 ec_params_usb_pd_get_mode_response { + uint16_t svid; /* SVID */ + uint16_t opos; /* Object Position */ + uint32_t vdo[6]; /* Mode VDOs */ +}; + +#define EC_CMD_USB_PD_SET_AMODE 0x0117 + +enum pd_mode_cmd { + PD_EXIT_MODE = 0, + PD_ENTER_MODE = 1, + /* Not a command. Do NOT remove. */ + PD_MODE_CMD_COUNT, +}; + +struct __ec_align4 ec_params_usb_pd_set_mode_request { + uint32_t cmd; /* enum pd_mode_cmd */ + uint16_t svid; /* SVID to set */ + uint8_t opos; /* Object Position */ + uint8_t port; /* port */ +}; + +/* Ask the PD MCU to record a log of a requested type */ +#define EC_CMD_PD_WRITE_LOG_ENTRY 0x0118 + +struct __ec_align1 ec_params_pd_write_log_entry { + uint8_t type; /* event type : see PD_EVENT_xx above */ + uint8_t port; /* port#, or 0 for events unrelated to a given port */ +}; + + +/* Control USB-PD chip */ +#define EC_CMD_PD_CONTROL 0x0119 + +enum ec_pd_control_cmd { + PD_SUSPEND = 0, /* Suspend the PD chip (EC: stop talking to PD) */ + PD_RESUME, /* Resume the PD chip (EC: start talking to PD) */ + PD_RESET, /* Force reset the PD chip */ + PD_CONTROL_DISABLE /* Disable further calls to this command */ +}; + +struct __ec_align1 ec_params_pd_control { + uint8_t chip; /* chip id (should be 0) */ + uint8_t subcmd; +}; + +/* Get info about USB-C SS muxes */ +#define EC_CMD_USB_PD_MUX_INFO 0x011A + +struct __ec_align1 ec_params_usb_pd_mux_info { + uint8_t port; /* USB-C port number */ +}; + +/* Flags representing mux state */ +#define USB_PD_MUX_USB_ENABLED (1 << 0) +#define USB_PD_MUX_DP_ENABLED (1 << 1) +#define USB_PD_MUX_POLARITY_INVERTED (1 << 2) +#define USB_PD_MUX_HPD_IRQ (1 << 3) + +struct __ec_align1 ec_response_usb_pd_mux_info { + uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ +}; + +#define EC_CMD_PD_CHIP_INFO 0x011B + +struct __ec_align1 ec_params_pd_chip_info { + uint8_t port; /* USB-C port number */ + uint8_t renew; /* Force renewal */ +}; + +struct __ec_align2 ec_response_pd_chip_info { + uint16_t vendor_id; + uint16_t product_id; + uint16_t device_id; + union { + uint8_t fw_version_string[8]; + uint64_t fw_version_number; + }; +}; + +/* Run RW signature verification and get status */ +#define EC_CMD_RWSIG_CHECK_STATUS 0x011C + +struct __ec_align4 ec_response_rwsig_check_status { + uint32_t status; +}; + +/* For controlling RWSIG task */ +#define EC_CMD_RWSIG_ACTION 0x011D + +enum rwsig_action { + RWSIG_ACTION_ABORT = 0, /* Abort RWSIG and prevent jumping */ + RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */ +}; + +struct __ec_align4 ec_params_rwsig_action { + uint32_t action; +}; + +/* Run verification on a slot */ +#define EC_CMD_EFS_VERIFY 0x011E + +struct __ec_align1 ec_params_efs_verify { + uint8_t region; /* enum ec_flash_region */ +}; + +/* + * Retrieve info from Cros Board Info store. Response is based on the data + * type. Integers return a uint32. Strings return a string, using the response + * size to determine how big it is. + */ +#define EC_CMD_GET_CROS_BOARD_INFO 0x011F +/* + * Write info into Cros Board Info on EEPROM. Write fails if the board has + * hardware write-protect enabled. + */ +#define EC_CMD_SET_CROS_BOARD_INFO 0x0120 + +enum cbi_data_tag { + CBI_TAG_BOARD_VERSION = 0, /* uint16_t or uint8_t[] = {minor,major} */ + CBI_TAG_OEM_ID = 1, /* uint8_t */ + CBI_TAG_SKU_ID = 2, /* uint8_t */ + CBI_TAG_COUNT, +}; + +/* + * Flags to control read operation + * + * RELOAD: Invalidate cache and read data from EEPROM. Useful to verify + * write was successful without reboot. + */ +#define CBI_GET_RELOAD (1 << 0) + +struct __ec_align4 ec_params_get_cbi { + uint32_t type; /* enum cbi_data_tag */ + uint32_t flag; /* CBI_GET_* */ +}; + +/* + * Flags to control write behavior. + * + * NO_SYNC: Makes EC update data in RAM but skip writing to EEPROM. It's + * useful when writing multiple fields in a row. + * INIT: Needs to be set when creating a new CBI from scratch. All fields + * will be initialized to zero first. + */ +#define CBI_SET_NO_SYNC (1 << 0) +#define CBI_SET_INIT (1 << 1) + +struct __ec_align1 ec_params_set_cbi { + uint32_t tag; /* enum cbi_data_tag */ + uint32_t flag; /* CBI_SET_* */ + uint32_t size; /* Data size */ + uint8_t data[]; /* For string and raw data */ +}; + +/*****************************************************************************/ +/* The command range 0x200-0x2FF is reserved for Rotor. */ + +/*****************************************************************************/ +/* + * Reserve a range of host commands for the CR51 firmware. + */ +#define EC_CMD_CR51_BASE 0x0300 +#define EC_CMD_CR51_LAST 0x03FF + +/*****************************************************************************/ +/* Fingerprint MCU commands: range 0x0400-0x040x */ + +/* Fingerprint SPI sensor passthru command: prototyping ONLY */ +#define EC_CMD_FP_PASSTHRU 0x0400 + +#define EC_FP_FLAG_NOT_COMPLETE 0x1 + +struct __ec_align2 ec_params_fp_passthru { + uint16_t len; /* Number of bytes to write then read */ + uint16_t flags; /* EC_FP_FLAG_xxx */ + uint8_t data[]; /* Data to send */ +}; + +/* Fingerprint sensor configuration command: prototyping ONLY */ +#define EC_CMD_FP_SENSOR_CONFIG 0x0401 + +#define EC_FP_SENSOR_CONFIG_MAX_REGS 16 + +struct __ec_align2 ec_params_fp_sensor_config { + uint8_t count; /* Number of setup registers */ + /* + * the value to send to each of the 'count' setup registers + * is stored in the 'data' array for 'len' bytes just after + * the previous one. + */ + uint8_t len[EC_FP_SENSOR_CONFIG_MAX_REGS]; + uint8_t data[]; +}; + +/* Configure the Fingerprint MCU behavior */ +#define EC_CMD_FP_MODE 0x0402 + +/* Put the sensor in its lowest power mode */ +#define FP_MODE_DEEPSLEEP (1<<0) +/* Wait to see a finger on the sensor */ +#define FP_MODE_FINGER_DOWN (1<<1) +/* Poll until the finger has left the sensor */ +#define FP_MODE_FINGER_UP (1<<2) +/* Capture the current finger image */ +#define FP_MODE_CAPTURE (1<<3) +/* special value: don't change anything just read back current mode */ +#define FP_MODE_DONT_CHANGE (1<<31) + +struct __ec_align4 ec_params_fp_mode { + uint32_t mode; /* as defined by FP_MODE_ constants */ + /* TBD */ +}; + +struct __ec_align4 ec_response_fp_mode { + uint32_t mode; /* as defined by FP_MODE_ constants */ + /* TBD */ +}; + +/* Retrieve Fingerprint sensor information */ +#define EC_CMD_FP_INFO 0x0403 + +struct __ec_align2 ec_response_fp_info { + /* Sensor identification */ + uint32_t vendor_id; + uint32_t product_id; + uint32_t model_id; + uint32_t version; + /* Image frame characteristics */ + uint32_t frame_size; + uint32_t pixel_format; /* using V4L2_PIX_FMT_ */ + uint16_t width; + uint16_t height; + uint16_t bpp; +}; + +/* Get the last captured finger frame: TODO: will be AES-encrypted */ +#define EC_CMD_FP_FRAME 0x0404 + +struct __ec_align4 ec_params_fp_frame { + uint32_t offset; + uint32_t size; +}; + +/*****************************************************************************/ +/* Touchpad MCU commands: range 0x0500-0x05FF */ + +/* Perform touchpad self test */ +#define EC_CMD_TP_SELF_TEST 0x0500 + +/* Get number of frame types, and the size of each type */ +#define EC_CMD_TP_FRAME_INFO 0x0501 + +struct __ec_align4 ec_response_tp_frame_info { + uint32_t n_frames; + uint32_t frame_sizes[0]; +}; + +/* Create a snapshot of current frame readings */ +#define EC_CMD_TP_FRAME_SNAPSHOT 0x0502 + +/* Read the frame */ +#define EC_CMD_TP_FRAME_GET 0x0503 + +struct __ec_align4 ec_params_tp_frame_get { + uint32_t frame_index; + uint32_t offset; + uint32_t size; +}; + +/*****************************************************************************/ +/* + * Reserve a range of host commands for board-specific, experimental, or + * special purpose features. These can be (re)used without updating this file. + * + * CAUTION: Don't go nuts with this. Shipping products should document ALL + * their EC commands for easier development, testing, debugging, and support. + * + * All commands MUST be #defined to be 4-digit UPPER CASE hex values + * (e.g., 0x00AB, not 0xab) for CONFIG_HOSTCMD_SECTION_SORTED to work. + * + * In your experimental code, you may want to do something like this: + * + * #define EC_CMD_MAGIC_FOO 0x0000 + * #define EC_CMD_MAGIC_BAR 0x0001 + * #define EC_CMD_MAGIC_HEY 0x0002 + * + * DECLARE_PRIVATE_HOST_COMMAND(EC_CMD_MAGIC_FOO, magic_foo_handler, + * EC_VER_MASK(0); + * + * DECLARE_PRIVATE_HOST_COMMAND(EC_CMD_MAGIC_BAR, magic_bar_handler, + * EC_VER_MASK(0); + * + * DECLARE_PRIVATE_HOST_COMMAND(EC_CMD_MAGIC_HEY, magic_hey_handler, + * EC_VER_MASK(0); + */ +#define EC_CMD_BOARD_SPECIFIC_BASE 0x3E00 +#define EC_CMD_BOARD_SPECIFIC_LAST 0x3FFF + +/* + * Given the private host command offset, calculate the true private host + * command value. + */ +#define EC_PRIVATE_HOST_COMMAND_VALUE(command) \ + (EC_CMD_BOARD_SPECIFIC_BASE + (command)) + +/*****************************************************************************/ +/* + * Passthru commands + * + * Some platforms have sub-processors chained to each other. For example. + * + * AP <--> EC <--> PD MCU + * + * The top 2 bits of the command number are used to indicate which device the + * command is intended for. Device 0 is always the device receiving the + * command; other device mapping is board-specific. + * + * When a device receives a command to be passed to a sub-processor, it passes + * it on with the device number set back to 0. This allows the sub-processor + * to remain blissfully unaware of whether the command originated on the next + * device up the chain, or was passed through from the AP. + * + * In the above example, if the AP wants to send command 0x0002 to the PD MCU, + * AP sends command 0x4002 to the EC + * EC sends command 0x0002 to the PD MCU + * EC forwards PD MCU response back to the AP + */ + +/* Offset and max command number for sub-device n */ +#define EC_CMD_PASSTHRU_OFFSET(n) (0x4000 * (n)) +#define EC_CMD_PASSTHRU_MAX(n) (EC_CMD_PASSTHRU_OFFSET(n) + 0x3fff) + +/*****************************************************************************/ +/* + * Deprecated constants. These constants have been renamed for clarity. The + * meaning and size has not changed. Programs that use the old names should + * switch to the new names soon, as the old names may not be carried forward + * forever. + */ +#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE +#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1 +#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE + +#endif /* !__ACPI__ && !__KERNEL__ */ + +#endif /* __CROS_EC_COMMANDS_H */ diff --git a/roms/u-boot/include/edid.h b/roms/u-boot/include/edid.h new file mode 100644 index 000000000..256273306 --- /dev/null +++ b/roms/u-boot/include/edid.h @@ -0,0 +1,345 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * (C) Copyright 2010 + * Petr Stetiar + * + * Contains stolen code from ddcprobe project which is: + * Copyright (C) Nalin Dahyabhai + */ + +#ifndef __EDID_H_ +#define __EDID_H_ + +#include + +/* Size of the EDID data */ +#define EDID_SIZE 128 +#define EDID_EXT_SIZE 256 + +/* OUI of HDMI vendor specific data block */ +#define HDMI_IEEE_OUI 0x000c03 + +#define GET_BIT(_x, _pos) \ + (((_x) >> (_pos)) & 1) +#define GET_BITS(_x, _pos_msb, _pos_lsb) \ + (((_x) >> (_pos_lsb)) & ((1 << ((_pos_msb) - (_pos_lsb) + 1)) - 1)) + +/* Aspect ratios used in EDID info. */ +enum edid_aspect { + ASPECT_625 = 0, + ASPECT_75, + ASPECT_8, + ASPECT_5625, +}; + +/* Detailed timing information used in EDID v1.x */ +struct edid_detailed_timing { + unsigned char pixel_clock[2]; +#define EDID_DETAILED_TIMING_PIXEL_CLOCK(_x) \ + (((((uint32_t)(_x).pixel_clock[1]) << 8) + \ + (_x).pixel_clock[0]) * 10000) + unsigned char horizontal_active; + unsigned char horizontal_blanking; + unsigned char horizontal_active_blanking_hi; +#define EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(_x) \ + ((GET_BITS((_x).horizontal_active_blanking_hi, 7, 4) << 8) + \ + (_x).horizontal_active) +#define EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(_x) \ + ((GET_BITS((_x).horizontal_active_blanking_hi, 3, 0) << 8) + \ + (_x).horizontal_blanking) + unsigned char vertical_active; + unsigned char vertical_blanking; + unsigned char vertical_active_blanking_hi; +#define EDID_DETAILED_TIMING_VERTICAL_ACTIVE(_x) \ + ((GET_BITS((_x).vertical_active_blanking_hi, 7, 4) << 8) + \ + (_x).vertical_active) +#define EDID_DETAILED_TIMING_VERTICAL_BLANKING(_x) \ + ((GET_BITS((_x).vertical_active_blanking_hi, 3, 0) << 8) + \ + (_x).vertical_blanking) + unsigned char hsync_offset; + unsigned char hsync_pulse_width; + unsigned char vsync_offset_pulse_width; + unsigned char hsync_vsync_offset_pulse_width_hi; +#define EDID_DETAILED_TIMING_HSYNC_OFFSET(_x) \ + ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 7, 6) << 8) + \ + (_x).hsync_offset) +#define EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(_x) \ + ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 5, 4) << 8) + \ + (_x).hsync_pulse_width) +#define EDID_DETAILED_TIMING_VSYNC_OFFSET(_x) \ + ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 3, 2) << 4) + \ + GET_BITS((_x).vsync_offset_pulse_width, 7, 4)) +#define EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(_x) \ + ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 1, 0) << 4) + \ + GET_BITS((_x).vsync_offset_pulse_width, 3, 0)) + unsigned char himage_size; + unsigned char vimage_size; + unsigned char himage_vimage_size_hi; +#define EDID_DETAILED_TIMING_HIMAGE_SIZE(_x) \ + ((GET_BITS((_x).himage_vimage_size_hi, 7, 4) << 8) + (_x).himage_size) +#define EDID_DETAILED_TIMING_VIMAGE_SIZE(_x) \ + ((GET_BITS((_x).himage_vimage_size_hi, 3, 0) << 8) + (_x).vimage_size) + unsigned char hborder; + unsigned char vborder; + unsigned char flags; +#define EDID_DETAILED_TIMING_FLAG_INTERLACED(_x) \ + GET_BIT((_x).flags, 7) +#define EDID_DETAILED_TIMING_FLAG_STEREO(_x) \ + GET_BITS((_x).flags, 6, 5) +#define EDID_DETAILED_TIMING_FLAG_DIGITAL_COMPOSITE(_x) \ + GET_BITS((_x).flags, 4, 3) +#define EDID_DETAILED_TIMING_FLAG_POLARITY(_x) \ + GET_BITS((_x).flags, 2, 1) +#define EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(_x) \ + GET_BIT((_x).flags, 2) +#define EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(_x) \ + GET_BIT((_x).flags, 1) +#define EDID_DETAILED_TIMING_FLAG_INTERLEAVED(_x) \ + GET_BIT((_x).flags, 0) +} __attribute__ ((__packed__)); + +enum edid_monitor_descriptor_types { + EDID_MONITOR_DESCRIPTOR_SERIAL = 0xff, + EDID_MONITOR_DESCRIPTOR_ASCII = 0xfe, + EDID_MONITOR_DESCRIPTOR_RANGE = 0xfd, + EDID_MONITOR_DESCRIPTOR_NAME = 0xfc, +}; + +struct edid_monitor_descriptor { + uint16_t zero_flag_1; + unsigned char zero_flag_2; + unsigned char type; + unsigned char zero_flag_3; + union { + char string[13]; + struct { + unsigned char vertical_min; + unsigned char vertical_max; + unsigned char horizontal_min; + unsigned char horizontal_max; + unsigned char pixel_clock_max; + unsigned char gtf_data[8]; + } range_data; + } data; +} __attribute__ ((__packed__)); + +struct edid1_info { + unsigned char header[8]; + unsigned char manufacturer_name[2]; +#define EDID1_INFO_MANUFACTURER_NAME_ZERO(_x) \ + GET_BIT(((_x).manufacturer_name[0]), 7) +#define EDID1_INFO_MANUFACTURER_NAME_CHAR1(_x) \ + GET_BITS(((_x).manufacturer_name[0]), 6, 2) +#define EDID1_INFO_MANUFACTURER_NAME_CHAR2(_x) \ + ((GET_BITS(((_x).manufacturer_name[0]), 1, 0) << 3) + \ + GET_BITS(((_x).manufacturer_name[1]), 7, 5)) +#define EDID1_INFO_MANUFACTURER_NAME_CHAR3(_x) \ + GET_BITS(((_x).manufacturer_name[1]), 4, 0) + unsigned char product_code[2]; +#define EDID1_INFO_PRODUCT_CODE(_x) \ + (((uint16_t)(_x).product_code[1] << 8) + (_x).product_code[0]) + unsigned char serial_number[4]; +#define EDID1_INFO_SERIAL_NUMBER(_x) \ + (((uint32_t)(_x).serial_number[3] << 24) + \ + ((_x).serial_number[2] << 16) + ((_x).serial_number[1] << 8) + \ + (_x).serial_number[0]) + unsigned char week; + unsigned char year; + unsigned char version; + unsigned char revision; + unsigned char video_input_definition; +#define EDID1_INFO_VIDEO_INPUT_DIGITAL(_x) \ + GET_BIT(((_x).video_input_definition), 7) +#define EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(_x) \ + GET_BITS(((_x).video_input_definition), 6, 5) +#define EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(_x) \ + GET_BIT(((_x).video_input_definition), 4) +#define EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(_x) \ + GET_BIT(((_x).video_input_definition), 3) +#define EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(_x) \ + GET_BIT(((_x).video_input_definition), 2) +#define EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(_x) \ + GET_BIT(((_x).video_input_definition), 1) +#define EDID1_INFO_VIDEO_INPUT_SERRATION_V(_x) \ + GET_BIT(((_x).video_input_definition), 0) + unsigned char max_size_horizontal; + unsigned char max_size_vertical; + unsigned char gamma; + unsigned char feature_support; +#define EDID1_INFO_FEATURE_STANDBY(_x) \ + GET_BIT(((_x).feature_support), 7) +#define EDID1_INFO_FEATURE_SUSPEND(_x) \ + GET_BIT(((_x).feature_support), 6) +#define EDID1_INFO_FEATURE_ACTIVE_OFF(_x) \ + GET_BIT(((_x).feature_support), 5) +#define EDID1_INFO_FEATURE_DISPLAY_TYPE(_x) \ + GET_BITS(((_x).feature_support), 4, 3) +#define EDID1_INFO_FEATURE_RGB(_x) \ + GET_BIT(((_x).feature_support), 2) +#define EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(_x) \ + GET_BIT(((_x).feature_support), 1) +#define EDID1_INFO_FEATURE_DEFAULT_GTF_SUPPORT(_x) \ + GET_BIT(((_x).feature_support), 0) + unsigned char color_characteristics[10]; + unsigned char established_timings[3]; +#define EDID1_INFO_ESTABLISHED_TIMING_720X400_70(_x) \ + GET_BIT(((_x).established_timings[0]), 7) +#define EDID1_INFO_ESTABLISHED_TIMING_720X400_88(_x) \ + GET_BIT(((_x).established_timings[0]), 6) +#define EDID1_INFO_ESTABLISHED_TIMING_640X480_60(_x) \ + GET_BIT(((_x).established_timings[0]), 5) +#define EDID1_INFO_ESTABLISHED_TIMING_640X480_67(_x) \ + GET_BIT(((_x).established_timings[0]), 4) +#define EDID1_INFO_ESTABLISHED_TIMING_640X480_72(_x) \ + GET_BIT(((_x).established_timings[0]), 3) +#define EDID1_INFO_ESTABLISHED_TIMING_640X480_75(_x) \ + GET_BIT(((_x).established_timings[0]), 2) +#define EDID1_INFO_ESTABLISHED_TIMING_800X600_56(_x) \ + GET_BIT(((_x).established_timings[0]), 1) +#define EDID1_INFO_ESTABLISHED_TIMING_800X600_60(_x) \ + GET_BIT(((_x).established_timings[0]), 0) +#define EDID1_INFO_ESTABLISHED_TIMING_800X600_72(_x) \ + GET_BIT(((_x).established_timings[1]), 7) +#define EDID1_INFO_ESTABLISHED_TIMING_800X600_75(_x) \ + GET_BIT(((_x).established_timings[1]), 6) +#define EDID1_INFO_ESTABLISHED_TIMING_832X624_75(_x) \ + GET_BIT(((_x).established_timings[1]), 5) +#define EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(_x) \ + GET_BIT(((_x).established_timings[1]), 4) +#define EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(_x) \ + GET_BIT(((_x).established_timings[1]), 3) +#define EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(_x) \ + GET_BIT(((_x).established_timings[1]), 2) +#define EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(_x) \ + GET_BIT(((_x).established_timings[1]), 1) +#define EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(_x) \ + GET_BIT(((_x).established_timings[1]), 0) +#define EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(_x) \ + GET_BIT(((_x).established_timings[2]), 7) + struct { + unsigned char xresolution; + unsigned char aspect_vfreq; + } __attribute__((__packed__)) standard_timings[8]; +#define EDID1_INFO_STANDARD_TIMING_XRESOLUTION(_x, _i) \ + (((_x).standard_timings[_i]).xresolution) +#define EDID1_INFO_STANDARD_TIMING_ASPECT(_x, _i) \ + GET_BITS(((_x).standard_timings[_i].aspect_vfreq), 7, 6) +#define EDID1_INFO_STANDARD_TIMING_VFREQ(_x, _i) \ + GET_BITS(((_x).standard_timings[_i].aspect_vfreq), 5, 0) + union { + unsigned char timing[72]; + struct edid_monitor_descriptor descriptor[4]; + } monitor_details; + unsigned char extension_flag; + unsigned char checksum; +} __attribute__ ((__packed__)); + +enum edid_cea861_db_types { + EDID_CEA861_DB_AUDIO = 0x01, + EDID_CEA861_DB_VIDEO = 0x02, + EDID_CEA861_DB_VENDOR = 0x03, + EDID_CEA861_DB_SPEAKER = 0x04, +}; + +struct edid_cea861_info { + unsigned char extension_tag; +#define EDID_CEA861_EXTENSION_TAG 0x02 + unsigned char revision; + unsigned char dtd_offset; + unsigned char dtd_count; +#define EDID_CEA861_SUPPORTS_UNDERSCAN(_x) \ + GET_BIT(((_x).dtd_count), 7) +#define EDID_CEA861_SUPPORTS_BASIC_AUDIO(_x) \ + GET_BIT(((_x).dtd_count), 6) +#define EDID_CEA861_SUPPORTS_YUV444(_x) \ + GET_BIT(((_x).dtd_count), 5) +#define EDID_CEA861_SUPPORTS_YUV422(_x) \ + GET_BIT(((_x).dtd_count), 4) +#define EDID_CEA861_DTD_COUNT(_x) \ + GET_BITS(((_x).dtd_count), 3, 0) + unsigned char data[124]; +#define EDID_CEA861_DB_TYPE(_x, offset) \ + GET_BITS((_x).data[offset], 7, 5) +#define EDID_CEA861_DB_LEN(_x, offset) \ + GET_BITS((_x).data[offset], 4, 0) +} __attribute__ ((__packed__)); + +/** + * Print the EDID info. + * + * @param edid_info The EDID info to be printed + */ +void edid_print_info(struct edid1_info *edid_info); + +/** + * Check the EDID info. + * + * @param info The EDID info to be checked + * @return 0 on valid, or -1 on invalid + */ +int edid_check_info(struct edid1_info *info); + +/** + * Check checksum of a 128 bytes EDID data block + * + * @param edid_block EDID block data + * + * @return 0 on success, or a negative errno on error + */ +int edid_check_checksum(u8 *edid_block); + +/** + * Get the horizontal and vertical rate ranges of the monitor. + * + * @param edid The EDID info + * @param hmin Returns the minimum horizontal rate + * @param hmax Returns the maxium horizontal rate + * @param vmin Returns the minimum vertical rate + * @param vmax Returns the maxium vertical rate + * @return 0 on success, or -1 on error + */ +int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, + unsigned int *hmax, unsigned int *vmin, + unsigned int *vmax); + +struct display_timing; + +/** + * edid_get_timing_validate() - Get basic digital display parameters with + * mode selection callback + * + * @param buf Buffer containing EDID data + * @param buf_size Size of buffer in bytes + * @param timing Place to put preferring timing information + * @param panel_bits_per_colourp Place to put the number of bits per + * colour supported by the panel. This will be set to + * -1 if not available + * @param mode_valid Callback validating mode, returning true is mode is + * supported, false otherwise. + * @parem valid_priv Pointer to private data for mode_valid callback + * @return 0 if timings are OK, -ve on error + */ +int edid_get_timing_validate(u8 *buf, int buf_size, + struct display_timing *timing, + int *panel_bits_per_colourp, + bool (*mode_valid)(void *priv, + const struct display_timing *timing), + void *mode_valid_priv); + +/** + * edid_get_timing() - Get basic digital display parameters + * + * @param buf Buffer containing EDID data + * @param buf_size Size of buffer in bytes + * @param timing Place to put preferring timing information + * @param panel_bits_per_colourp Place to put the number of bits per + * colour supported by the panel. This will be set to + * -1 if not available + * @return 0 if timings are OK, -ve on error + */ +int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, + int *panel_bits_per_colourp); + +#endif /* __EDID_H_ */ diff --git a/roms/u-boot/include/eeprom.h b/roms/u-boot/include/eeprom.h new file mode 100644 index 000000000..6820844ce --- /dev/null +++ b/roms/u-boot/include/eeprom.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef __EEPROM_LEGACY_H +#define __EEPROM_LEGACY_H + +#if defined(CONFIG_CMD_EEPROM) || defined(CONFIG_ENV_IS_IN_EEPROM) +void eeprom_init(int bus); +int eeprom_read(uint dev_addr, uint offset, uchar *buffer, uint cnt); +int eeprom_write(uint dev_addr, uint offset, uchar *buffer, uint cnt); +#else +/* + * Some EEPROM code is depecated because it used the legacy I2C interface. Add + * some macros here so we don't have to touch every one of those uses + */ +#define eeprom_init(bus) +#define eeprom_read(dev_addr, offset, buffer, cnt) (-ENOSYS) +#define eeprom_write(dev_addr, offset, buffer, cnt) (-ENOSYS) +#endif + +#if !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) +# define CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR +#endif + +#endif diff --git a/roms/u-boot/include/eeprom_field.h b/roms/u-boot/include/eeprom_field.h new file mode 100644 index 000000000..05c0d1459 --- /dev/null +++ b/roms/u-boot/include/eeprom_field.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009-2016 CompuLab, Ltd. + * + * Authors: Nikita Kiryanov + * Igor Grinberg + */ + +#ifndef _FIELD_ +#define _FIELD_ + +#define PRINT_FIELD_SEGMENT "%-30s" + +struct eeprom_field { + char *name; + int size; + unsigned char *buf; + + void (*print)(const struct eeprom_field *eeprom_field); + int (*update)(struct eeprom_field *eeprom_field, char *value); +}; + +void eeprom_field_print_bin(const struct eeprom_field *field); +int eeprom_field_update_bin(struct eeprom_field *field, char *value); + +void eeprom_field_print_bin_rev(const struct eeprom_field *field); +int eeprom_field_update_bin_rev(struct eeprom_field *field, char *value); + +void eeprom_field_print_mac(const struct eeprom_field *field); +int eeprom_field_update_mac(struct eeprom_field *field, char *value); + +void eeprom_field_print_ascii(const struct eeprom_field *field); +int eeprom_field_update_ascii(struct eeprom_field *field, char *value); + +void eeprom_field_print_reserved(const struct eeprom_field *field); +int eeprom_field_update_reserved(struct eeprom_field *field, char *value); + +#endif diff --git a/roms/u-boot/include/eeprom_layout.h b/roms/u-boot/include/eeprom_layout.h new file mode 100644 index 000000000..730d963ab --- /dev/null +++ b/roms/u-boot/include/eeprom_layout.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009-2016 CompuLab, Ltd. + * + * Authors: Nikita Kiryanov + * Igor Grinberg + */ + +#ifndef _LAYOUT_ +#define _LAYOUT_ + +#define RESERVED_FIELDS NULL +#define LAYOUT_VERSION_UNRECOGNIZED -1 +#define LAYOUT_VERSION_AUTODETECT -2 + +struct eeprom_layout { + struct eeprom_field *fields; + int num_of_fields; + int layout_version; + unsigned char *data; + int data_size; + void (*print)(const struct eeprom_layout *eeprom_layout); + int (*update)(struct eeprom_layout *eeprom_layout, char *field_name, + char *new_data); +}; + +void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf, + unsigned int buf_size, int layout_version); +__weak void __eeprom_layout_assign(struct eeprom_layout *layout, + int layout_version); + +#endif diff --git a/roms/u-boot/include/efi.h b/roms/u-boot/include/efi.h new file mode 100644 index 000000000..6417a9b8c --- /dev/null +++ b/roms/u-boot/include/efi.h @@ -0,0 +1,493 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Extensible Firmware Interface + * Based on 'Extensible Firmware Interface Specification' version 0.9, + * April 30, 1999 + * + * Copyright (C) 1999 VA Linux Systems + * Copyright (C) 1999 Walt Drummond + * Copyright (C) 1999, 2002-2003 Hewlett-Packard Co. + * David Mosberger-Tang + * Stephane Eranian + * + * From include/linux/efi.h in kernel 4.1 with some additions/subtractions + */ + +#ifndef _EFI_H +#define _EFI_H + +#include +#include +#include + +/* Type INTN in UEFI specification */ +#define efi_intn_t ssize_t +/* Type UINTN in UEFI specification*/ +#define efi_uintn_t size_t + +/* + * EFI on x86_64 uses the Microsoft ABI which is not the default for GCC. + * + * There are two scenarios for EFI on x86_64: building a 64-bit EFI stub + * codes (CONFIG_EFI_STUB_64BIT) and building a 64-bit U-Boot (CONFIG_X86_64). + * Either needs to be properly built with the '-m64' compiler flag, and hence + * it is enough to only check the compiler provided define __x86_64__ here. + */ +#ifdef __x86_64__ +#define EFIAPI __attribute__((ms_abi)) +#define efi_va_list __builtin_ms_va_list +#define efi_va_start __builtin_ms_va_start +#define efi_va_arg __builtin_va_arg +#define efi_va_end __builtin_ms_va_end +#else +#define EFIAPI asmlinkage +#define efi_va_list va_list +#define efi_va_start va_start +#define efi_va_arg va_arg +#define efi_va_end va_end +#endif /* __x86_64__ */ + +#define EFI32_LOADER_SIGNATURE "EL32" +#define EFI64_LOADER_SIGNATURE "EL64" + +struct efi_device_path; + +typedef struct { + u8 b[16]; +} efi_guid_t __attribute__((aligned(8))); + +#define EFI_BITS_PER_LONG (sizeof(long) * 8) + +/* Bit mask for EFI status code with error */ +#define EFI_ERROR_MASK (1UL << (EFI_BITS_PER_LONG - 1)) +/* Status codes returned by EFI protocols */ +#define EFI_SUCCESS 0 +#define EFI_LOAD_ERROR (EFI_ERROR_MASK | 1) +#define EFI_INVALID_PARAMETER (EFI_ERROR_MASK | 2) +#define EFI_UNSUPPORTED (EFI_ERROR_MASK | 3) +#define EFI_BAD_BUFFER_SIZE (EFI_ERROR_MASK | 4) +#define EFI_BUFFER_TOO_SMALL (EFI_ERROR_MASK | 5) +#define EFI_NOT_READY (EFI_ERROR_MASK | 6) +#define EFI_DEVICE_ERROR (EFI_ERROR_MASK | 7) +#define EFI_WRITE_PROTECTED (EFI_ERROR_MASK | 8) +#define EFI_OUT_OF_RESOURCES (EFI_ERROR_MASK | 9) +#define EFI_VOLUME_CORRUPTED (EFI_ERROR_MASK | 10) +#define EFI_VOLUME_FULL (EFI_ERROR_MASK | 11) +#define EFI_NO_MEDIA (EFI_ERROR_MASK | 12) +#define EFI_MEDIA_CHANGED (EFI_ERROR_MASK | 13) +#define EFI_NOT_FOUND (EFI_ERROR_MASK | 14) +#define EFI_ACCESS_DENIED (EFI_ERROR_MASK | 15) +#define EFI_NO_RESPONSE (EFI_ERROR_MASK | 16) +#define EFI_NO_MAPPING (EFI_ERROR_MASK | 17) +#define EFI_TIMEOUT (EFI_ERROR_MASK | 18) +#define EFI_NOT_STARTED (EFI_ERROR_MASK | 19) +#define EFI_ALREADY_STARTED (EFI_ERROR_MASK | 20) +#define EFI_ABORTED (EFI_ERROR_MASK | 21) +#define EFI_ICMP_ERROR (EFI_ERROR_MASK | 22) +#define EFI_TFTP_ERROR (EFI_ERROR_MASK | 23) +#define EFI_PROTOCOL_ERROR (EFI_ERROR_MASK | 24) +#define EFI_INCOMPATIBLE_VERSION (EFI_ERROR_MASK | 25) +#define EFI_SECURITY_VIOLATION (EFI_ERROR_MASK | 26) +#define EFI_CRC_ERROR (EFI_ERROR_MASK | 27) +#define EFI_END_OF_MEDIA (EFI_ERROR_MASK | 28) +#define EFI_END_OF_FILE (EFI_ERROR_MASK | 31) +#define EFI_INVALID_LANGUAGE (EFI_ERROR_MASK | 32) +#define EFI_COMPROMISED_DATA (EFI_ERROR_MASK | 33) +#define EFI_IP_ADDRESS_CONFLICT (EFI_ERROR_MASK | 34) +#define EFI_HTTP_ERROR (EFI_ERROR_MASK | 35) + +#define EFI_WARN_UNKNOWN_GLYPH 1 +#define EFI_WARN_DELETE_FAILURE 2 +#define EFI_WARN_WRITE_FAILURE 3 +#define EFI_WARN_BUFFER_TOO_SMALL 4 +#define EFI_WARN_STALE_DATA 5 +#define EFI_WARN_FILE_SYSTEM 6 +#define EFI_WARN_RESET_REQUIRED 7 + +typedef unsigned long efi_status_t; +typedef u64 efi_physical_addr_t; +typedef u64 efi_virtual_addr_t; +typedef struct efi_object *efi_handle_t; + +#define EFI_GUID(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ + {{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, \ + ((a) >> 24) & 0xff, \ + (b) & 0xff, ((b) >> 8) & 0xff, \ + (c) & 0xff, ((c) >> 8) & 0xff, \ + (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } } + +/* Generic EFI table header */ +struct efi_table_hdr { + u64 signature; + u32 revision; + u32 headersize; + u32 crc32; + u32 reserved; +}; + +/* Enumeration of memory types introduced in UEFI */ +enum efi_mem_type { + EFI_RESERVED_MEMORY_TYPE, + /* + * The code portions of a loaded application. + * (Note that UEFI OS loaders are UEFI applications.) + */ + EFI_LOADER_CODE, + /* + * The data portions of a loaded application and + * the default data allocation type used by an application + * to allocate pool memory. + */ + EFI_LOADER_DATA, + /* The code portions of a loaded Boot Services Driver */ + EFI_BOOT_SERVICES_CODE, + /* + * The data portions of a loaded Boot Services Driver and + * the default data allocation type used by a Boot Services + * Driver to allocate pool memory. + */ + EFI_BOOT_SERVICES_DATA, + /* The code portions of a loaded Runtime Services Driver */ + EFI_RUNTIME_SERVICES_CODE, + /* + * The data portions of a loaded Runtime Services Driver and + * the default data allocation type used by a Runtime Services + * Driver to allocate pool memory. + */ + EFI_RUNTIME_SERVICES_DATA, + /* Free (unallocated) memory */ + EFI_CONVENTIONAL_MEMORY, + /* Memory in which errors have been detected */ + EFI_UNUSABLE_MEMORY, + /* Memory that holds the ACPI tables */ + EFI_ACPI_RECLAIM_MEMORY, + /* Address space reserved for use by the firmware */ + EFI_ACPI_MEMORY_NVS, + /* + * Used by system firmware to request that a memory-mapped IO region + * be mapped by the OS to a virtual address so it can be accessed by + * EFI runtime services. + */ + EFI_MMAP_IO, + /* + * System memory-mapped IO region that is used to translate + * memory cycles to IO cycles by the processor. + */ + EFI_MMAP_IO_PORT, + /* + * Address space reserved by the firmware for code that is + * part of the processor. + */ + EFI_PAL_CODE, + /* + * Byte addressable non-volatile memory. + */ + EFI_PERSISTENT_MEMORY_TYPE, + /* + * Unaccepted memory must be accepted by boot target before usage. + */ + EFI_UNACCEPTED_MEMORY_TYPE, + + EFI_MAX_MEMORY_TYPE, +}; + +/* Attribute values */ +#define EFI_MEMORY_UC ((u64)0x0000000000000001ULL) /* uncached */ +#define EFI_MEMORY_WC ((u64)0x0000000000000002ULL) /* write-coalescing */ +#define EFI_MEMORY_WT ((u64)0x0000000000000004ULL) /* write-through */ +#define EFI_MEMORY_WB ((u64)0x0000000000000008ULL) /* write-back */ +#define EFI_MEMORY_UCE ((u64)0x0000000000000010ULL) /* uncached, exported */ +#define EFI_MEMORY_WP ((u64)0x0000000000001000ULL) /* write-protect */ +#define EFI_MEMORY_RP ((u64)0x0000000000002000ULL) /* read-protect */ +#define EFI_MEMORY_XP ((u64)0x0000000000004000ULL) /* execute-protect */ +#define EFI_MEMORY_NV ((u64)0x0000000000008000ULL) /* non-volatile */ +#define EFI_MEMORY_MORE_RELIABLE \ + ((u64)0x0000000000010000ULL) /* higher reliability */ +#define EFI_MEMORY_RO ((u64)0x0000000000020000ULL) /* read-only */ +#define EFI_MEMORY_SP ((u64)0x0000000000040000ULL) /* specific-purpose memory (SPM) */ +#define EFI_MEMORY_CPU_CRYPTO ((u64)0x0000000000080000ULL) /* cryptographically protectable */ +#define EFI_MEMORY_RUNTIME ((u64)0x8000000000000000ULL) /* range requires runtime mapping */ +#define EFI_MEM_DESC_VERSION 1 + +#define EFI_PAGE_SHIFT 12 +#define EFI_PAGE_SIZE (1ULL << EFI_PAGE_SHIFT) +#define EFI_PAGE_MASK (EFI_PAGE_SIZE - 1) + +struct efi_mem_desc { + u32 type; + u32 reserved; + efi_physical_addr_t physical_start; + efi_virtual_addr_t virtual_start; + u64 num_pages; + u64 attribute; +}; + +#define EFI_MEMORY_DESCRIPTOR_VERSION 1 + +/* Allocation types for calls to boottime->allocate_pages*/ +#define EFI_ALLOCATE_ANY_PAGES 0 +#define EFI_ALLOCATE_MAX_ADDRESS 1 +#define EFI_ALLOCATE_ADDRESS 2 +#define EFI_MAX_ALLOCATE_TYPE 3 + +/* Types and defines for Time Services */ +#define EFI_TIME_ADJUST_DAYLIGHT 0x1 +#define EFI_TIME_IN_DAYLIGHT 0x2 +#define EFI_UNSPECIFIED_TIMEZONE 0x07ff + +struct efi_time { + u16 year; + u8 month; + u8 day; + u8 hour; + u8 minute; + u8 second; + u8 pad1; + u32 nanosecond; + s16 timezone; + u8 daylight; + u8 pad2; +}; + +struct efi_time_cap { + u32 resolution; + u32 accuracy; + u8 sets_to_zero; +}; + +enum efi_locate_search_type { + ALL_HANDLES, + BY_REGISTER_NOTIFY, + BY_PROTOCOL +}; + +struct efi_open_protocol_info_entry { + efi_handle_t agent_handle; + efi_handle_t controller_handle; + u32 attributes; + u32 open_count; +}; + +enum efi_entry_t { + EFIET_END, /* Signals this is the last (empty) entry */ + EFIET_MEMORY_MAP, + EFIET_GOP_MODE, + EFIET_SYS_TABLE, + + /* Number of entries */ + EFIET_MEMORY_COUNT, +}; + +#define EFI_TABLE_VERSION 1 + +/** + * struct efi_info_hdr - Header for the EFI info table + * + * @version: EFI_TABLE_VERSION + * @hdr_size: Size of this struct in bytes + * @total_size: Total size of this header plus following data + * @spare: Spare space for expansion + */ +struct efi_info_hdr { + u32 version; + u32 hdr_size; + u32 total_size; + u32 spare[5]; +}; + +/** + * struct efi_entry_hdr - Header for a table entry + * + * @type: enum eft_entry_t + * @size size of entry bytes excluding header and padding + * @addr: address of this entry (0 if it follows the header ) + * @link: size of entry including header and padding + * @spare1: Spare space for expansion + * @spare2: Spare space for expansion + */ +struct efi_entry_hdr { + u32 type; + u32 size; + u64 addr; + u32 link; + u32 spare1; + u64 spare2; +}; + +/** + * struct efi_entry_memmap - a memory map table passed to U-Boot + * + * @version: EFI's memory map table version + * @desc_size: EFI's size of each memory descriptor + * @spare: Spare space for expansion + * @desc: An array of descriptors, each @desc_size bytes apart + */ +struct efi_entry_memmap { + u32 version; + u32 desc_size; + u64 spare; + struct efi_mem_desc desc[]; +}; + +/** + * struct efi_entry_gopmode - a GOP mode table passed to U-Boot + * + * @fb_base: EFI's framebuffer base address + * @fb_size: EFI's framebuffer size + * @info_size: GOP mode info structure size + * @info: Start address of the GOP mode info structure + */ +struct efi_entry_gopmode { + efi_physical_addr_t fb_base; + /* + * Not like the ones in 'struct efi_gop_mode' which are 'unsigned + * long', @fb_size and @info_size have to be 'u64' here. As the EFI + * stub codes may have different bit size from the U-Boot payload, + * using 'long' will cause mismatch between the producer (stub) and + * the consumer (payload). + */ + u64 fb_size; + u64 info_size; + /* + * We cannot directly use 'struct efi_gop_mode_info info[]' here as + * it causes compiler to complain: array type has incomplete element + * type 'struct efi_gop_mode_info'. + */ + struct /* efi_gop_mode_info */ { + u32 version; + u32 width; + u32 height; + u32 pixel_format; + u32 pixel_bitmask[4]; + u32 pixels_per_scanline; + } info[]; +}; + +/** + * struct efi_entry_systable - system table passed to U-Boot + * + * @sys_table: EFI system table address + */ +struct efi_entry_systable { + efi_physical_addr_t sys_table; +}; + +static inline struct efi_mem_desc *efi_get_next_mem_desc( + struct efi_entry_memmap *map, struct efi_mem_desc *desc) +{ + return (struct efi_mem_desc *)((ulong)desc + map->desc_size); +} + +struct efi_priv { + efi_handle_t parent_image; + struct efi_device_path *device_path; + struct efi_system_table *sys_table; + struct efi_boot_services *boot; + struct efi_runtime_services *run; + bool use_pool_for_malloc; + unsigned long ram_base; + unsigned int image_data_type; + struct efi_info_hdr *info; + unsigned int info_size; + void *next_hdr; +}; + +/* Base address of the EFI image */ +extern char image_base[]; + +/* Start and end of U-Boot image (for payload) */ +extern char _binary_u_boot_bin_start[], _binary_u_boot_bin_end[]; + +/* + * Variable Attributes + */ +#define EFI_VARIABLE_NON_VOLATILE 0x0000000000000001 +#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x0000000000000002 +#define EFI_VARIABLE_RUNTIME_ACCESS 0x0000000000000004 +#define EFI_VARIABLE_HARDWARE_ERROR_RECORD 0x0000000000000008 +#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS 0x0000000000000010 +#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS 0x0000000000000020 +#define EFI_VARIABLE_APPEND_WRITE 0x0000000000000040 + +#define EFI_VARIABLE_MASK (EFI_VARIABLE_NON_VOLATILE | \ + EFI_VARIABLE_BOOTSERVICE_ACCESS | \ + EFI_VARIABLE_RUNTIME_ACCESS | \ + EFI_VARIABLE_HARDWARE_ERROR_RECORD | \ + EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS | \ + EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS | \ + EFI_VARIABLE_APPEND_WRITE) + +/** + * efi_get_sys_table() - Get access to the main EFI system table + * + * @return pointer to EFI system table + */ + +struct efi_system_table *efi_get_sys_table(void); + +/** + * efi_get_ram_base() - Find the base of RAM + * + * This is used when U-Boot is built as an EFI application. + * + * @return the base of RAM as known to U-Boot + */ +unsigned long efi_get_ram_base(void); + +/** + * efi_init() - Set up ready for use of EFI boot services + * + * @priv: Pointer to our private EFI structure to fill in + * @banner: Banner to display when starting + * @image: The image handle passed to efi_main() + * @sys_table: The EFI system table pointer passed to efi_main() + */ +int efi_init(struct efi_priv *priv, const char *banner, efi_handle_t image, + struct efi_system_table *sys_table); + +/** + * efi_malloc() - Allocate some memory from EFI + * + * @priv: Pointer to private EFI structure + * @size: Number of bytes to allocate + * @retp: Return EFI status result + * @return pointer to memory allocated, or NULL on error + */ +void *efi_malloc(struct efi_priv *priv, int size, efi_status_t *retp); + +/** + * efi_free() - Free memory allocated from EFI + * + * @priv: Pointer to private EFI structure + * @ptr: Pointer to memory to free + */ +void efi_free(struct efi_priv *priv, void *ptr); + +/** + * efi_puts() - Write out a string to the EFI console + * + * @priv: Pointer to private EFI structure + * @str: String to write (note this is a ASCII, not unicode) + */ +void efi_puts(struct efi_priv *priv, const char *str); + +/** + * efi_putc() - Write out a character to the EFI console + * + * @priv: Pointer to private EFI structure + * @ch: Character to write (note this is not unicode) + */ +void efi_putc(struct efi_priv *priv, const char ch); + +/** + * efi_info_get() - get an entry from an EFI table + * + * @type: Entry type to search for + * @datap: Returns pointer to entry data + * @sizep: Returns pointer to entry size + * @return 0 if OK, -ENODATA if there is no table, -ENOENT if there is no entry + * of the requested type, -EPROTONOSUPPORT if the table has the wrong version + */ +int efi_info_get(enum efi_entry_t type, void **datap, int *sizep); + +#endif /* _LINUX_EFI_H */ diff --git a/roms/u-boot/include/efi_api.h b/roms/u-boot/include/efi_api.h new file mode 100644 index 000000000..18a1adf02 --- /dev/null +++ b/roms/u-boot/include/efi_api.h @@ -0,0 +1,1995 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Extensible Firmware Interface + * Based on 'Extensible Firmware Interface Specification' version 0.9, + * April 30, 1999 + * + * Copyright (C) 1999 VA Linux Systems + * Copyright (C) 1999 Walt Drummond + * Copyright (C) 1999, 2002-2003 Hewlett-Packard Co. + * David Mosberger-Tang + * Stephane Eranian + * + * From include/linux/efi.h in kernel 4.1 with some additions/subtractions + */ + +#ifndef _EFI_API_H +#define _EFI_API_H + +#include +#include +#include + +#ifdef CONFIG_EFI_LOADER +#include +#endif + +/* UEFI spec version 2.8 */ +#define EFI_SPECIFICATION_VERSION (2 << 16 | 80) + +/* Types and defines for EFI CreateEvent */ +enum efi_timer_delay { + EFI_TIMER_STOP = 0, + EFI_TIMER_PERIODIC = 1, + EFI_TIMER_RELATIVE = 2 +}; + +typedef void *efi_hii_handle_t; +typedef u16 *efi_string_t; +typedef u16 efi_string_id_t; +typedef u32 efi_hii_font_style_t; +typedef u16 efi_question_id_t; +typedef u16 efi_image_id_t; +typedef u16 efi_form_id_t; + +#define EVT_TIMER 0x80000000 +#define EVT_RUNTIME 0x40000000 +#define EVT_NOTIFY_WAIT 0x00000100 +#define EVT_NOTIFY_SIGNAL 0x00000200 +#define EVT_SIGNAL_EXIT_BOOT_SERVICES 0x00000201 +#define EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE 0x60000202 + +#define TPL_APPLICATION 0x04 +#define TPL_CALLBACK 0x08 +#define TPL_NOTIFY 0x10 +#define TPL_HIGH_LEVEL 0x1F + +struct efi_event; + +/* OsIndicationsSupported flags */ +#define EFI_OS_INDICATIONS_BOOT_TO_FW_UI 0x0000000000000001 +#define EFI_OS_INDICATIONS_TIMESTAMP_REVOCATION 0x0000000000000002 +#define EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED 0x0000000000000004 +#define EFI_OS_INDICATIONS_FMP_CAPSULE_SUPPORTED 0x0000000000000008 +#define EFI_OS_INDICATIONS_CAPSULE_RESULT_VAR_SUPPORTED 0x0000000000000010 +#define EFI_OS_INDICATIONS_START_OS_RECOVERY 0x0000000000000020 +#define EFI_OS_INDICATIONS_START_PLATFORM_RECOVERY 0x0000000000000040 +#define EFI_OS_INDICATIONS_JSON_CONFIG_DATA_REFRESH 0x0000000000000080 + +/* EFI Boot Services table */ +#define EFI_BOOT_SERVICES_SIGNATURE 0x56524553544f4f42 +struct efi_boot_services { + struct efi_table_hdr hdr; + efi_status_t (EFIAPI *raise_tpl)(efi_uintn_t new_tpl); + void (EFIAPI *restore_tpl)(efi_uintn_t old_tpl); + + efi_status_t (EFIAPI *allocate_pages)(int, int, efi_uintn_t, + efi_physical_addr_t *); + efi_status_t (EFIAPI *free_pages)(efi_physical_addr_t, efi_uintn_t); + efi_status_t (EFIAPI *get_memory_map)(efi_uintn_t *memory_map_size, + struct efi_mem_desc *desc, + efi_uintn_t *key, + efi_uintn_t *desc_size, + u32 *desc_version); + efi_status_t (EFIAPI *allocate_pool)(int, efi_uintn_t, void **); + efi_status_t (EFIAPI *free_pool)(void *); + + efi_status_t (EFIAPI *create_event)(uint32_t type, + efi_uintn_t notify_tpl, + void (EFIAPI *notify_function) ( + struct efi_event *event, + void *context), + void *notify_context, struct efi_event **event); + efi_status_t (EFIAPI *set_timer)(struct efi_event *event, + enum efi_timer_delay type, + uint64_t trigger_time); + efi_status_t (EFIAPI *wait_for_event)(efi_uintn_t number_of_events, + struct efi_event **event, + efi_uintn_t *index); + efi_status_t (EFIAPI *signal_event)(struct efi_event *event); + efi_status_t (EFIAPI *close_event)(struct efi_event *event); + efi_status_t (EFIAPI *check_event)(struct efi_event *event); +#define EFI_NATIVE_INTERFACE 0x00000000 + efi_status_t (EFIAPI *install_protocol_interface)( + efi_handle_t *handle, const efi_guid_t *protocol, + int protocol_interface_type, void *protocol_interface); + efi_status_t (EFIAPI *reinstall_protocol_interface)( + efi_handle_t handle, const efi_guid_t *protocol, + void *old_interface, void *new_interface); + efi_status_t (EFIAPI *uninstall_protocol_interface)( + efi_handle_t handle, const efi_guid_t *protocol, + void *protocol_interface); + efi_status_t (EFIAPI *handle_protocol)( + efi_handle_t handle, const efi_guid_t *protocol, + void **protocol_interface); + void *reserved; + efi_status_t (EFIAPI *register_protocol_notify)( + const efi_guid_t *protocol, struct efi_event *event, + void **registration); + efi_status_t (EFIAPI *locate_handle)( + enum efi_locate_search_type search_type, + const efi_guid_t *protocol, void *search_key, + efi_uintn_t *buffer_size, efi_handle_t *buffer); + efi_status_t (EFIAPI *locate_device_path)(const efi_guid_t *protocol, + struct efi_device_path **device_path, + efi_handle_t *device); + efi_status_t (EFIAPI *install_configuration_table)( + efi_guid_t *guid, void *table); + + efi_status_t (EFIAPI *load_image)(bool boot_policiy, + efi_handle_t parent_image, + struct efi_device_path *file_path, void *source_buffer, + efi_uintn_t source_size, efi_handle_t *image); + efi_status_t (EFIAPI *start_image)(efi_handle_t handle, + efi_uintn_t *exitdata_size, + u16 **exitdata); + efi_status_t (EFIAPI *exit)(efi_handle_t handle, + efi_status_t exit_status, + efi_uintn_t exitdata_size, u16 *exitdata); + efi_status_t (EFIAPI *unload_image)(efi_handle_t image_handle); + efi_status_t (EFIAPI *exit_boot_services)(efi_handle_t image_handle, + efi_uintn_t map_key); + + efi_status_t (EFIAPI *get_next_monotonic_count)(u64 *count); + efi_status_t (EFIAPI *stall)(unsigned long usecs); + efi_status_t (EFIAPI *set_watchdog_timer)(unsigned long timeout, + uint64_t watchdog_code, unsigned long data_size, + uint16_t *watchdog_data); + efi_status_t(EFIAPI *connect_controller)(efi_handle_t controller_handle, + efi_handle_t *driver_image_handle, + struct efi_device_path *remaining_device_path, + bool recursive); + efi_status_t (EFIAPI *disconnect_controller)( + efi_handle_t controller_handle, + efi_handle_t driver_image_handle, + efi_handle_t child_handle); +#define EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL 0x00000001 +#define EFI_OPEN_PROTOCOL_GET_PROTOCOL 0x00000002 +#define EFI_OPEN_PROTOCOL_TEST_PROTOCOL 0x00000004 +#define EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER 0x00000008 +#define EFI_OPEN_PROTOCOL_BY_DRIVER 0x00000010 +#define EFI_OPEN_PROTOCOL_EXCLUSIVE 0x00000020 + efi_status_t (EFIAPI *open_protocol)(efi_handle_t handle, + const efi_guid_t *protocol, void **interface, + efi_handle_t agent_handle, + efi_handle_t controller_handle, u32 attributes); + efi_status_t (EFIAPI *close_protocol)( + efi_handle_t handle, const efi_guid_t *protocol, + efi_handle_t agent_handle, + efi_handle_t controller_handle); + efi_status_t(EFIAPI *open_protocol_information)(efi_handle_t handle, + const efi_guid_t *protocol, + struct efi_open_protocol_info_entry **entry_buffer, + efi_uintn_t *entry_count); + efi_status_t (EFIAPI *protocols_per_handle)(efi_handle_t handle, + efi_guid_t ***protocol_buffer, + efi_uintn_t *protocols_buffer_count); + efi_status_t (EFIAPI *locate_handle_buffer) ( + enum efi_locate_search_type search_type, + const efi_guid_t *protocol, void *search_key, + efi_uintn_t *no_handles, efi_handle_t **buffer); + efi_status_t (EFIAPI *locate_protocol)(const efi_guid_t *protocol, + void *registration, void **protocol_interface); + efi_status_t (EFIAPI *install_multiple_protocol_interfaces)( + efi_handle_t *handle, ...); + efi_status_t (EFIAPI *uninstall_multiple_protocol_interfaces)( + efi_handle_t handle, ...); + efi_status_t (EFIAPI *calculate_crc32)(const void *data, + efi_uintn_t data_size, + u32 *crc32); + void (EFIAPI *copy_mem)(void *destination, const void *source, + size_t length); + void (EFIAPI *set_mem)(void *buffer, size_t size, uint8_t value); + efi_status_t (EFIAPI *create_event_ex)( + uint32_t type, efi_uintn_t notify_tpl, + void (EFIAPI *notify_function) ( + struct efi_event *event, + void *context), + void *notify_context, + efi_guid_t *event_group, + struct efi_event **event); +}; + +/* Types and defines for EFI ResetSystem */ +enum efi_reset_type { + EFI_RESET_COLD = 0, + EFI_RESET_WARM = 1, + EFI_RESET_SHUTDOWN = 2, + EFI_RESET_PLATFORM_SPECIFIC = 3, +}; + +/* EFI Runtime Services table */ +#define EFI_RUNTIME_SERVICES_SIGNATURE 0x56524553544e5552ULL + +#define CAPSULE_FLAGS_PERSIST_ACROSS_RESET 0x00010000 +#define CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE 0x00020000 +#define CAPSULE_FLAGS_INITIATE_RESET 0x00040000 + +#define CAPSULE_SUPPORT_AUTHENTICATION 0x0000000000000001 +#define CAPSULE_SUPPORT_DEPENDENCY 0x0000000000000002 + +#define EFI_CAPSULE_REPORT_GUID \ + EFI_GUID(0x39b68c46, 0xf7fb, 0x441b, 0xb6, 0xec, \ + 0x16, 0xb0, 0xf6, 0x98, 0x21, 0xf3) + +#define EFI_MEMORY_RANGE_CAPSULE_GUID \ + EFI_GUID(0xde9f0ec, 0x88b6, 0x428f, 0x97, 0x7a, \ + 0x25, 0x8f, 0x1d, 0xe, 0x5e, 0x72) + +#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID \ + EFI_GUID(0x6dcbd5ed, 0xe82d, 0x4c44, 0xbd, 0xa1, \ + 0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a) + +struct efi_capsule_header { + efi_guid_t capsule_guid; + u32 header_size; + u32 flags; + u32 capsule_image_size; +} __packed; + +struct efi_capsule_result_variable_header { + u32 variable_total_size; + u32 reserved; + efi_guid_t capsule_guid; + struct efi_time capsule_processed; + efi_status_t capsule_status; +} __packed; + +struct efi_memory_range { + efi_physical_addr_t address; + u64 length; +}; + +struct efi_memory_range_capsule { + struct efi_capsule_header *header; + /* EFI_MEMORY_TYPE: 0x80000000-0xFFFFFFFF */ + enum efi_mem_type os_requested_memory_type; + u64 number_of_memory_ranges; + struct efi_memory_range memory_ranges[]; +} __packed; + +struct efi_firmware_management_capsule_header { + u32 version; + u16 embedded_driver_count; + u16 payload_item_count; + u64 item_offset_list[]; +} __packed; + +struct efi_firmware_management_capsule_image_header { + u32 version; + efi_guid_t update_image_type_id; + u8 update_image_index; + u8 reserved[3]; + u32 update_image_size; + u32 update_vendor_code_size; + u64 update_hardware_instance; + u64 image_capsule_support; +} __packed; + +struct efi_capsule_result_variable_fmp { + u16 version; + u8 payload_index; + u8 update_image_index; + efi_guid_t update_image_type_id; + // u16 capsule_file_name[]; + // u16 capsule_target[]; +} __packed; + +#define EFI_RT_SUPPORTED_GET_TIME 0x0001 +#define EFI_RT_SUPPORTED_SET_TIME 0x0002 +#define EFI_RT_SUPPORTED_GET_WAKEUP_TIME 0x0004 +#define EFI_RT_SUPPORTED_SET_WAKEUP_TIME 0x0008 +#define EFI_RT_SUPPORTED_GET_VARIABLE 0x0010 +#define EFI_RT_SUPPORTED_GET_NEXT_VARIABLE_NAME 0x0020 +#define EFI_RT_SUPPORTED_SET_VARIABLE 0x0040 +#define EFI_RT_SUPPORTED_SET_VIRTUAL_ADDRESS_MAP 0x0080 +#define EFI_RT_SUPPORTED_CONVERT_POINTER 0x0100 +#define EFI_RT_SUPPORTED_GET_NEXT_HIGH_MONOTONIC_COUNT 0x0200 +#define EFI_RT_SUPPORTED_RESET_SYSTEM 0x0400 +#define EFI_RT_SUPPORTED_UPDATE_CAPSULE 0x0800 +#define EFI_RT_SUPPORTED_QUERY_CAPSULE_CAPABILITIES 0x1000 +#define EFI_RT_SUPPORTED_QUERY_VARIABLE_INFO 0x2000 + +#define EFI_RT_PROPERTIES_TABLE_GUID \ + EFI_GUID(0xeb66918a, 0x7eef, 0x402a, 0x84, 0x2e, \ + 0x93, 0x1d, 0x21, 0xc3, 0x8a, 0xe9) + +#define EFI_RT_PROPERTIES_TABLE_VERSION 0x1 + +struct efi_rt_properties_table { + u16 version; + u16 length; + u32 runtime_services_supported; +}; + +#define EFI_OPTIONAL_PTR 0x00000001 + +struct efi_runtime_services { + struct efi_table_hdr hdr; + efi_status_t (EFIAPI *get_time)(struct efi_time *time, + struct efi_time_cap *capabilities); + efi_status_t (EFIAPI *set_time)(struct efi_time *time); + efi_status_t (EFIAPI *get_wakeup_time)(char *enabled, char *pending, + struct efi_time *time); + efi_status_t (EFIAPI *set_wakeup_time)(char enabled, + struct efi_time *time); + efi_status_t (EFIAPI *set_virtual_address_map)( + efi_uintn_t memory_map_size, + efi_uintn_t descriptor_size, + uint32_t descriptor_version, + struct efi_mem_desc *virtmap); + efi_status_t (EFIAPI *convert_pointer)( + efi_uintn_t debug_disposition, void **address); + efi_status_t (EFIAPI *get_variable)(u16 *variable_name, + const efi_guid_t *vendor, + u32 *attributes, + efi_uintn_t *data_size, void *data); + efi_status_t (EFIAPI *get_next_variable_name)( + efi_uintn_t *variable_name_size, + u16 *variable_name, efi_guid_t *vendor); + efi_status_t (EFIAPI *set_variable)(u16 *variable_name, + const efi_guid_t *vendor, + u32 attributes, + efi_uintn_t data_size, + const void *data); + efi_status_t (EFIAPI *get_next_high_mono_count)( + uint32_t *high_count); + void (EFIAPI *reset_system)(enum efi_reset_type reset_type, + efi_status_t reset_status, + unsigned long data_size, void *reset_data); + efi_status_t (EFIAPI *update_capsule)( + struct efi_capsule_header **capsule_header_array, + efi_uintn_t capsule_count, + u64 scatter_gather_list); + efi_status_t (EFIAPI *query_capsule_caps)( + struct efi_capsule_header **capsule_header_array, + efi_uintn_t capsule_count, + u64 *maximum_capsule_size, + u32 *reset_type); + efi_status_t (EFIAPI *query_variable_info)( + u32 attributes, + u64 *maximum_variable_storage_size, + u64 *remaining_variable_storage_size, + u64 *maximum_variable_size); +}; + +/* EFI event group GUID definitions */ +#define EFI_EVENT_GROUP_EXIT_BOOT_SERVICES \ + EFI_GUID(0x27abf055, 0xb1b8, 0x4c26, 0x80, 0x48, \ + 0x74, 0x8f, 0x37, 0xba, 0xa2, 0xdf) + +#define EFI_EVENT_GROUP_VIRTUAL_ADDRESS_CHANGE \ + EFI_GUID(0x13fa7698, 0xc831, 0x49c7, 0x87, 0xea, \ + 0x8f, 0x43, 0xfc, 0xc2, 0x51, 0x96) + +#define EFI_EVENT_GROUP_MEMORY_MAP_CHANGE \ + EFI_GUID(0x78bee926, 0x692f, 0x48fd, 0x9e, 0xdb, \ + 0x01, 0x42, 0x2e, 0xf0, 0xd7, 0xab) + +#define EFI_EVENT_GROUP_READY_TO_BOOT \ + EFI_GUID(0x7ce88fb3, 0x4bd7, 0x4679, 0x87, 0xa8, \ + 0xa8, 0xd8, 0xde, 0xe5, 0x0d, 0x2b) + +#define EFI_EVENT_GROUP_RESET_SYSTEM \ + EFI_GUID(0x62da6a56, 0x13fb, 0x485a, 0xa8, 0xda, \ + 0xa3, 0xdd, 0x79, 0x12, 0xcb, 0x6b) + +/* EFI Configuration Table and GUID definitions */ +#define NULL_GUID \ + EFI_GUID(0x00000000, 0x0000, 0x0000, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00) + +#define EFI_GLOBAL_VARIABLE_GUID \ + EFI_GUID(0x8be4df61, 0x93ca, 0x11d2, 0xaa, 0x0d, \ + 0x00, 0xe0, 0x98, 0x03, 0x2b, 0x8c) + +#define EFI_IMAGE_SECURITY_DATABASE_GUID \ + EFI_GUID(0xd719b2cb, 0x3d3a, 0x4596, 0xa3, 0xbc, \ + 0xda, 0xd0, 0x0e, 0x67, 0x65, 0x6f) + +#define EFI_FDT_GUID \ + EFI_GUID(0xb1b621d5, 0xf19c, 0x41a5, \ + 0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0) + +#define EFI_ACPI_TABLE_GUID \ + EFI_GUID(0x8868e871, 0xe4f1, 0x11d3, \ + 0xbc, 0x22, 0x00, 0x80, 0xc7, 0x3c, 0x88, 0x81) + +#define SMBIOS_TABLE_GUID \ + EFI_GUID(0xeb9d2d31, 0x2d88, 0x11d3, \ + 0x9a, 0x16, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d) + +#define EFI_LOAD_FILE_PROTOCOL_GUID \ + EFI_GUID(0x56ec3091, 0x954c, 0x11d2, \ + 0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b) + +#define EFI_LOAD_FILE2_PROTOCOL_GUID \ + EFI_GUID(0x4006c0c1, 0xfcb3, 0x403e, \ + 0x99, 0x6d, 0x4a, 0x6c, 0x87, 0x24, 0xe0, 0x6d) + +#define EFI_TCG2_FINAL_EVENTS_TABLE_GUID \ + EFI_GUID(0x1e2ed096, 0x30e2, 0x4254, 0xbd, \ + 0x89, 0x86, 0x3b, 0xbe, 0xf8, 0x23, 0x25) + +struct efi_configuration_table { + efi_guid_t guid; + void *table; +} __packed; + +#define EFI_SYSTEM_TABLE_SIGNATURE ((u64)0x5453595320494249ULL) + +struct efi_system_table { + struct efi_table_hdr hdr; + u16 *fw_vendor; /* physical addr of wchar_t vendor string */ + u32 fw_revision; + efi_handle_t con_in_handle; + struct efi_simple_text_input_protocol *con_in; + efi_handle_t con_out_handle; + struct efi_simple_text_output_protocol *con_out; + efi_handle_t stderr_handle; + struct efi_simple_text_output_protocol *std_err; + struct efi_runtime_services *runtime; + struct efi_boot_services *boottime; + efi_uintn_t nr_tables; + struct efi_configuration_table *tables; +}; + +#define EFI_LOADED_IMAGE_PROTOCOL_GUID \ + EFI_GUID(0x5b1b31a1, 0x9562, 0x11d2, \ + 0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b) + +#define EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL_GUID \ + EFI_GUID(0xbc62157e, 0x3e33, 0x4fec, \ + 0x99, 0x20, 0x2d, 0x3b, 0x36, 0xd7, 0x50, 0xdf) + +#define EFI_LOADED_IMAGE_PROTOCOL_REVISION 0x1000 + +struct efi_loaded_image { + u32 revision; + void *parent_handle; + struct efi_system_table *system_table; + efi_handle_t device_handle; + struct efi_device_path *file_path; + void *reserved; + u32 load_options_size; + void *load_options; + void *image_base; + aligned_u64 image_size; + unsigned int image_code_type; + unsigned int image_data_type; + efi_status_t (EFIAPI *unload)(efi_handle_t image_handle); +}; + +#define EFI_DEVICE_PATH_PROTOCOL_GUID \ + EFI_GUID(0x09576e91, 0x6d3f, 0x11d2, \ + 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b) + +#define DEVICE_PATH_TYPE_END 0x7f +# define DEVICE_PATH_SUB_TYPE_INSTANCE_END 0x01 +# define DEVICE_PATH_SUB_TYPE_END 0xff + +struct efi_device_path { + u8 type; + u8 sub_type; + u16 length; +} __packed; + +struct efi_mac_addr { + u8 addr[32]; +} __packed; + +#define DEVICE_PATH_TYPE_HARDWARE_DEVICE 0x01 +# define DEVICE_PATH_SUB_TYPE_MEMORY 0x03 +# define DEVICE_PATH_SUB_TYPE_VENDOR 0x04 + +struct efi_device_path_memory { + struct efi_device_path dp; + u32 memory_type; + u64 start_address; + u64 end_address; +} __packed; + +struct efi_device_path_vendor { + struct efi_device_path dp; + efi_guid_t guid; + u8 vendor_data[]; +} __packed; + +#define DEVICE_PATH_TYPE_ACPI_DEVICE 0x02 +# define DEVICE_PATH_SUB_TYPE_ACPI_DEVICE 0x01 + +#define EFI_PNP_ID(ID) (u32)(((ID) << 16) | 0x41D0) +#define EISA_PNP_ID(ID) EFI_PNP_ID(ID) +#define EISA_PNP_NUM(ID) ((ID) >> 16) + +struct efi_device_path_acpi_path { + struct efi_device_path dp; + u32 hid; + u32 uid; +} __packed; + +#define DEVICE_PATH_TYPE_MESSAGING_DEVICE 0x03 +# define DEVICE_PATH_SUB_TYPE_MSG_ATAPI 0x01 +# define DEVICE_PATH_SUB_TYPE_MSG_SCSI 0x02 +# define DEVICE_PATH_SUB_TYPE_MSG_USB 0x05 +# define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR 0x0b +# define DEVICE_PATH_SUB_TYPE_MSG_UART 0x0e +# define DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS 0x0f +# define DEVICE_PATH_SUB_TYPE_MSG_SATA 0x12 +# define DEVICE_PATH_SUB_TYPE_MSG_NVME 0x17 +# define DEVICE_PATH_SUB_TYPE_MSG_SD 0x1a +# define DEVICE_PATH_SUB_TYPE_MSG_MMC 0x1d + +struct efi_device_path_atapi { + struct efi_device_path dp; + u8 primary_secondary; + u8 slave_master; + u16 logical_unit_number; +} __packed; + +struct efi_device_path_scsi { + struct efi_device_path dp; + u16 target_id; + u16 logical_unit_number; +} __packed; + +struct efi_device_path_uart { + struct efi_device_path dp; + u32 reserved; + u64 baud_rate; + u8 data_bits; + u8 parity; + u8 stop_bits; +} __packed; + +struct efi_device_path_usb { + struct efi_device_path dp; + u8 parent_port_number; + u8 usb_interface; +} __packed; + +struct efi_device_path_sata { + struct efi_device_path dp; + u16 hba_port; + u16 port_multiplier_port; + u16 logical_unit_number; +} __packed; + +struct efi_device_path_mac_addr { + struct efi_device_path dp; + struct efi_mac_addr mac; + u8 if_type; +} __packed; + +struct efi_device_path_usb_class { + struct efi_device_path dp; + u16 vendor_id; + u16 product_id; + u8 device_class; + u8 device_subclass; + u8 device_protocol; +} __packed; + +struct efi_device_path_sd_mmc_path { + struct efi_device_path dp; + u8 slot_number; +} __packed; + +struct efi_device_path_nvme { + struct efi_device_path dp; + u32 ns_id; + u8 eui64[8]; +} __packed; + +#define DEVICE_PATH_TYPE_MEDIA_DEVICE 0x04 +# define DEVICE_PATH_SUB_TYPE_HARD_DRIVE_PATH 0x01 +# define DEVICE_PATH_SUB_TYPE_CDROM_PATH 0x02 +# define DEVICE_PATH_SUB_TYPE_VENDOR_PATH 0x03 +# define DEVICE_PATH_SUB_TYPE_FILE_PATH 0x04 + +struct efi_device_path_hard_drive_path { + struct efi_device_path dp; + u32 partition_number; + u64 partition_start; + u64 partition_end; + u8 partition_signature[16]; + u8 partmap_type; + u8 signature_type; +} __packed; + +struct efi_device_path_cdrom_path { + struct efi_device_path dp; + u32 boot_entry; + u64 partition_start; + u64 partition_size; +} __packed; + +struct efi_device_path_file_path { + struct efi_device_path dp; + u16 str[]; +} __packed; + +#define EFI_BLOCK_IO_PROTOCOL_GUID \ + EFI_GUID(0x964e5b21, 0x6459, 0x11d2, \ + 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b) + +struct efi_block_io_media { + u32 media_id; + char removable_media; + char media_present; + char logical_partition; + char read_only; + char write_caching; + u8 pad[3]; + u32 block_size; + u32 io_align; + u8 pad2[4]; + u64 last_block; + /* Added in revision 2 of the protocol */ + u64 lowest_aligned_lba; + u32 logical_blocks_per_physical_block; + /* Added in revision 3 of the protocol */ + u32 optimal_transfer_length_granualarity; +}; + +#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001 +#define EFI_BLOCK_IO_PROTOCOL_REVISION3 0x0002001f + +struct efi_block_io { + u64 revision; + struct efi_block_io_media *media; + efi_status_t (EFIAPI *reset)(struct efi_block_io *this, + char extended_verification); + efi_status_t (EFIAPI *read_blocks)(struct efi_block_io *this, + u32 media_id, u64 lba, efi_uintn_t buffer_size, + void *buffer); + efi_status_t (EFIAPI *write_blocks)(struct efi_block_io *this, + u32 media_id, u64 lba, efi_uintn_t buffer_size, + void *buffer); + efi_status_t (EFIAPI *flush_blocks)(struct efi_block_io *this); +}; + +struct simple_text_output_mode { + s32 max_mode; + s32 mode; + s32 attribute; + s32 cursor_column; + s32 cursor_row; + bool cursor_visible; +}; + +#define EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID \ + EFI_GUID(0x387477c2, 0x69c7, 0x11d2, \ + 0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b) + +#define EFI_BLACK 0x00 +#define EFI_BLUE 0x01 +#define EFI_GREEN 0x02 +#define EFI_CYAN 0x03 +#define EFI_RED 0x04 +#define EFI_MAGENTA 0x05 +#define EFI_BROWN 0x06 +#define EFI_LIGHTGRAY 0x07 +#define EFI_BRIGHT 0x08 +#define EFI_DARKGRAY 0x08 +#define EFI_LIGHTBLUE 0x09 +#define EFI_LIGHTGREEN 0x0a +#define EFI_LIGHTCYAN 0x0b +#define EFI_LIGHTRED 0x0c +#define EFI_LIGHTMAGENTA 0x0d +#define EFI_YELLOW 0x0e +#define EFI_WHITE 0x0f +#define EFI_BACKGROUND_BLACK 0x00 +#define EFI_BACKGROUND_BLUE 0x10 +#define EFI_BACKGROUND_GREEN 0x20 +#define EFI_BACKGROUND_CYAN 0x30 +#define EFI_BACKGROUND_RED 0x40 +#define EFI_BACKGROUND_MAGENTA 0x50 +#define EFI_BACKGROUND_BROWN 0x60 +#define EFI_BACKGROUND_LIGHTGRAY 0x70 + +/* extract foreground color from EFI attribute */ +#define EFI_ATTR_FG(attr) ((attr) & 0x07) +/* treat high bit of FG as bright/bold (similar to edk2) */ +#define EFI_ATTR_BOLD(attr) (((attr) >> 3) & 0x01) +/* extract background color from EFI attribute */ +#define EFI_ATTR_BG(attr) (((attr) >> 4) & 0x7) + +struct efi_simple_text_output_protocol { + efi_status_t (EFIAPI *reset)( + struct efi_simple_text_output_protocol *this, + char extended_verification); + efi_status_t (EFIAPI *output_string)( + struct efi_simple_text_output_protocol *this, + const u16 *str); + efi_status_t (EFIAPI *test_string)( + struct efi_simple_text_output_protocol *this, + const u16 *str); + efi_status_t(EFIAPI *query_mode)( + struct efi_simple_text_output_protocol *this, + unsigned long mode_number, unsigned long *columns, + unsigned long *rows); + efi_status_t(EFIAPI *set_mode)( + struct efi_simple_text_output_protocol *this, + unsigned long mode_number); + efi_status_t(EFIAPI *set_attribute)( + struct efi_simple_text_output_protocol *this, + unsigned long attribute); + efi_status_t(EFIAPI *clear_screen) ( + struct efi_simple_text_output_protocol *this); + efi_status_t(EFIAPI *set_cursor_position) ( + struct efi_simple_text_output_protocol *this, + unsigned long column, unsigned long row); + efi_status_t(EFIAPI *enable_cursor)( + struct efi_simple_text_output_protocol *this, + bool enable); + struct simple_text_output_mode *mode; +}; + +#define EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL_GUID \ + EFI_GUID(0xdd9e7534, 0x7762, 0x4698, \ + 0x8c, 0x14, 0xf5, 0x85, 0x17, 0xa6, 0x25, 0xaa) + +struct efi_input_key { + u16 scan_code; + s16 unicode_char; +}; + +#define EFI_SHIFT_STATE_INVALID 0x00000000 +#define EFI_RIGHT_SHIFT_PRESSED 0x00000001 +#define EFI_LEFT_SHIFT_PRESSED 0x00000002 +#define EFI_RIGHT_CONTROL_PRESSED 0x00000004 +#define EFI_LEFT_CONTROL_PRESSED 0x00000008 +#define EFI_RIGHT_ALT_PRESSED 0x00000010 +#define EFI_LEFT_ALT_PRESSED 0x00000020 +#define EFI_RIGHT_LOGO_PRESSED 0x00000040 +#define EFI_LEFT_LOGO_PRESSED 0x00000080 +#define EFI_MENU_KEY_PRESSED 0x00000100 +#define EFI_SYS_REQ_PRESSED 0x00000200 +#define EFI_SHIFT_STATE_VALID 0x80000000 + +#define EFI_TOGGLE_STATE_INVALID 0x00 +#define EFI_SCROLL_LOCK_ACTIVE 0x01 +#define EFI_NUM_LOCK_ACTIVE 0x02 +#define EFI_CAPS_LOCK_ACTIVE 0x04 +#define EFI_KEY_STATE_EXPOSED 0x40 +#define EFI_TOGGLE_STATE_VALID 0x80 + +struct efi_key_state { + u32 key_shift_state; + u8 key_toggle_state; +}; + +struct efi_key_data { + struct efi_input_key key; + struct efi_key_state key_state; +}; + +struct efi_simple_text_input_ex_protocol { + efi_status_t (EFIAPI *reset) ( + struct efi_simple_text_input_ex_protocol *this, + bool extended_verification); + efi_status_t (EFIAPI *read_key_stroke_ex) ( + struct efi_simple_text_input_ex_protocol *this, + struct efi_key_data *key_data); + struct efi_event *wait_for_key_ex; + efi_status_t (EFIAPI *set_state) ( + struct efi_simple_text_input_ex_protocol *this, + u8 *key_toggle_state); + efi_status_t (EFIAPI *register_key_notify) ( + struct efi_simple_text_input_ex_protocol *this, + struct efi_key_data *key_data, + efi_status_t (EFIAPI *key_notify_function)( + struct efi_key_data *key_data), + void **notify_handle); + efi_status_t (EFIAPI *unregister_key_notify) ( + struct efi_simple_text_input_ex_protocol *this, + void *notification_handle); +}; + +#define EFI_SIMPLE_TEXT_INPUT_PROTOCOL_GUID \ + EFI_GUID(0x387477c1, 0x69c7, 0x11d2, \ + 0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b) + +struct efi_simple_text_input_protocol { + efi_status_t(EFIAPI *reset)(struct efi_simple_text_input_protocol *this, + bool extended_verification); + efi_status_t(EFIAPI *read_key_stroke)( + struct efi_simple_text_input_protocol *this, + struct efi_input_key *key); + struct efi_event *wait_for_key; +}; + +#define EFI_DEVICE_PATH_TO_TEXT_PROTOCOL_GUID \ + EFI_GUID(0x8b843e20, 0x8132, 0x4852, \ + 0x90, 0xcc, 0x55, 0x1a, 0x4e, 0x4a, 0x7f, 0x1c) + +struct efi_device_path_to_text_protocol { + uint16_t *(EFIAPI *convert_device_node_to_text)( + struct efi_device_path *device_node, + bool display_only, + bool allow_shortcuts); + uint16_t *(EFIAPI *convert_device_path_to_text)( + struct efi_device_path *device_path, + bool display_only, + bool allow_shortcuts); +}; + +#define EFI_DEVICE_PATH_UTILITIES_PROTOCOL_GUID \ + EFI_GUID(0x0379be4e, 0xd706, 0x437d, \ + 0xb0, 0x37, 0xed, 0xb8, 0x2f, 0xb7, 0x72, 0xa4) + +struct efi_device_path_utilities_protocol { + efi_uintn_t (EFIAPI *get_device_path_size)( + const struct efi_device_path *device_path); + struct efi_device_path *(EFIAPI *duplicate_device_path)( + const struct efi_device_path *device_path); + struct efi_device_path *(EFIAPI *append_device_path)( + const struct efi_device_path *src1, + const struct efi_device_path *src2); + struct efi_device_path *(EFIAPI *append_device_node)( + const struct efi_device_path *device_path, + const struct efi_device_path *device_node); + struct efi_device_path *(EFIAPI *append_device_path_instance)( + const struct efi_device_path *device_path, + const struct efi_device_path *device_path_instance); + struct efi_device_path *(EFIAPI *get_next_device_path_instance)( + struct efi_device_path **device_path_instance, + efi_uintn_t *device_path_instance_size); + bool (EFIAPI *is_device_path_multi_instance)( + const struct efi_device_path *device_path); + struct efi_device_path *(EFIAPI *create_device_node)( + uint8_t node_type, + uint8_t node_sub_type, + uint16_t node_length); +}; + +/* + * Human Interface Infrastructure (HII) + */ +struct efi_hii_package_list_header { + efi_guid_t package_list_guid; + u32 package_length; +} __packed; + +/** + * struct efi_hii_package_header - EFI HII package header + * + * @fields: 'fields' replaces the bit-fields defined in the EFI + * specification to to avoid possible compiler incompatibilities:: + * + * u32 length:24; + * u32 type:8; + */ +struct efi_hii_package_header { + u32 fields; +} __packed; + +#define __EFI_HII_PACKAGE_LEN_SHIFT 0 +#define __EFI_HII_PACKAGE_TYPE_SHIFT 24 +#define __EFI_HII_PACKAGE_LEN_MASK 0xffffff +#define __EFI_HII_PACKAGE_TYPE_MASK 0xff + +#define EFI_HII_PACKAGE_TYPE_ALL 0x00 +#define EFI_HII_PACKAGE_TYPE_GUID 0x01 +#define EFI_HII_PACKAGE_FORMS 0x02 +#define EFI_HII_PACKAGE_STRINGS 0x04 +#define EFI_HII_PACKAGE_FONTS 0x05 +#define EFI_HII_PACKAGE_IMAGES 0x06 +#define EFI_HII_PACKAGE_SIMPLE_FONTS 0x07 +#define EFI_HII_PACKAGE_DEVICE_PATH 0x08 +#define EFI_HII_PACKAGE_KEYBOARD_LAYOUT 0x09 +#define EFI_HII_PACKAGE_ANIMATIONS 0x0A +#define EFI_HII_PACKAGE_END 0xDF +#define EFI_HII_PACKAGE_TYPE_SYSTEM_BEGIN 0xE0 +#define EFI_HII_PACKAGE_TYPE_SYSTEM_END 0xFF + +/* + * HII GUID package + */ +struct efi_hii_guid_package { + struct efi_hii_package_header header; + efi_guid_t guid; + char data[]; +} __packed; + +/* + * HII string package + */ +struct efi_hii_strings_package { + struct efi_hii_package_header header; + u32 header_size; + u32 string_info_offset; + u16 language_window[16]; + efi_string_id_t language_name; + u8 language[]; +} __packed; + +struct efi_hii_string_block { + u8 block_type; + /* u8 block_body[]; */ +} __packed; + +#define EFI_HII_SIBT_END 0x00 +#define EFI_HII_SIBT_STRING_SCSU 0x10 +#define EFI_HII_SIBT_STRING_SCSU_FONT 0x11 +#define EFI_HII_SIBT_STRINGS_SCSU 0x12 +#define EFI_HII_SIBT_STRINGS_SCSU_FONT 0x13 +#define EFI_HII_SIBT_STRING_UCS2 0x14 +#define EFI_HII_SIBT_STRING_UCS2_FONT 0x15 +#define EFI_HII_SIBT_STRINGS_UCS2 0x16 +#define EFI_HII_SIBT_STRINGS_UCS2_FONT 0x17 +#define EFI_HII_SIBT_DUPLICATE 0x20 +#define EFI_HII_SIBT_SKIP2 0x21 +#define EFI_HII_SIBT_SKIP1 0x22 +#define EFI_HII_SIBT_EXT1 0x30 +#define EFI_HII_SIBT_EXT2 0x31 +#define EFI_HII_SIBT_EXT4 0x32 +#define EFI_HII_SIBT_FONT 0x40 + +struct efi_hii_sibt_string_ucs2_block { + struct efi_hii_string_block header; + u16 string_text[]; +} __packed; + +static inline struct efi_hii_string_block * +efi_hii_sibt_string_ucs2_block_next(struct efi_hii_sibt_string_ucs2_block *blk) +{ + return ((void *)blk) + sizeof(*blk) + + (u16_strlen(blk->string_text) + 1) * 2; +} + +/* + * HII forms package + * TODO: full scope of definitions + */ +struct efi_hii_time { + u8 hour; + u8 minute; + u8 second; +}; + +struct efi_hii_date { + u16 year; + u8 month; + u8 day; +}; + +struct efi_hii_ref { + efi_question_id_t question_id; + efi_form_id_t form_id; + efi_guid_t form_set_guid; + efi_string_id_t device_path; +}; + +union efi_ifr_type_value { + u8 u8; // EFI_IFR_TYPE_NUM_SIZE_8 + u16 u16; // EFI_IFR_TYPE_NUM_SIZE_16 + u32 u32; // EFI_IFR_TYPE_NUM_SIZE_32 + u64 u64; // EFI_IFR_TYPE_NUM_SIZE_64 + bool b; // EFI_IFR_TYPE_BOOLEAN + struct efi_hii_time time; // EFI_IFR_TYPE_TIME + struct efi_hii_date date; // EFI_IFR_TYPE_DATE + efi_string_id_t string; // EFI_IFR_TYPE_STRING, EFI_IFR_TYPE_ACTION + struct efi_hii_ref ref; // EFI_IFR_TYPE_REF + // u8 buffer[]; // EFI_IFR_TYPE_BUFFER +}; + +#define EFI_IFR_TYPE_NUM_SIZE_8 0x00 +#define EFI_IFR_TYPE_NUM_SIZE_16 0x01 +#define EFI_IFR_TYPE_NUM_SIZE_32 0x02 +#define EFI_IFR_TYPE_NUM_SIZE_64 0x03 +#define EFI_IFR_TYPE_BOOLEAN 0x04 +#define EFI_IFR_TYPE_TIME 0x05 +#define EFI_IFR_TYPE_DATE 0x06 +#define EFI_IFR_TYPE_STRING 0x07 +#define EFI_IFR_TYPE_OTHER 0x08 +#define EFI_IFR_TYPE_UNDEFINED 0x09 +#define EFI_IFR_TYPE_ACTION 0x0A +#define EFI_IFR_TYPE_BUFFER 0x0B +#define EFI_IFR_TYPE_REF 0x0C +#define EFI_IFR_OPTION_DEFAULT 0x10 +#define EFI_IFR_OPTION_DEFAULT_MFG 0x20 + +#define EFI_IFR_ONE_OF_OPTION_OP 0x09 + +struct efi_ifr_op_header { + u8 opCode; + u8 length:7; + u8 scope:1; +}; + +struct efi_ifr_one_of_option { + struct efi_ifr_op_header header; + efi_string_id_t option; + u8 flags; + u8 type; + union efi_ifr_type_value value; +}; + +typedef efi_uintn_t efi_browser_action_t; + +#define EFI_BROWSER_ACTION_REQUEST_NONE 0 +#define EFI_BROWSER_ACTION_REQUEST_RESET 1 +#define EFI_BROWSER_ACTION_REQUEST_SUBMIT 2 +#define EFI_BROWSER_ACTION_REQUEST_EXIT 3 +#define EFI_BROWSER_ACTION_REQUEST_FORM_SUBMIT_EXIT 4 +#define EFI_BROWSER_ACTION_REQUEST_FORM_DISCARD_EXIT 5 +#define EFI_BROWSER_ACTION_REQUEST_FORM_APPLY 6 +#define EFI_BROWSER_ACTION_REQUEST_FORM_DISCARD 7 +#define EFI_BROWSER_ACTION_REQUEST_RECONNECT 8 + +typedef efi_uintn_t efi_browser_action_request_t; + +#define EFI_BROWSER_ACTION_CHANGING 0 +#define EFI_BROWSER_ACTION_CHANGED 1 +#define EFI_BROWSER_ACTION_RETRIEVE 2 +#define EFI_BROWSER_ACTION_FORM_OPEN 3 +#define EFI_BROWSER_ACTION_FORM_CLOSE 4 +#define EFI_BROWSER_ACTION_SUBMITTED 5 +#define EFI_BROWSER_ACTION_DEFAULT_STANDARD 0x1000 +#define EFI_BROWSER_ACTION_DEFAULT_MANUFACTURING 0x1001 +#define EFI_BROWSER_ACTION_DEFAULT_SAFE 0x1002 +#define EFI_BROWSER_ACTION_DEFAULT_PLATFORM 0x2000 +#define EFI_BROWSER_ACTION_DEFAULT_HARDWARE 0x3000 +#define EFI_BROWSER_ACTION_DEFAULT_FIRMWARE 0x4000 + +/* + * HII keyboard package + */ +typedef enum { + EFI_KEY_LCTRL, EFI_KEY_A0, EFI_KEY_LALT, EFI_KEY_SPACE_BAR, + EFI_KEY_A2, EFI_KEY_A3, EFI_KEY_A4, EFI_KEY_RCTRL, EFI_KEY_LEFT_ARROW, + EFI_KEY_DOWN_ARROW, EFI_KEY_RIGHT_ARROW, EFI_KEY_ZERO, + EFI_KEY_PERIOD, EFI_KEY_ENTER, EFI_KEY_LSHIFT, EFI_KEY_B0, + EFI_KEY_B1, EFI_KEY_B2, EFI_KEY_B3, EFI_KEY_B4, EFI_KEY_B5, EFI_KEY_B6, + EFI_KEY_B7, EFI_KEY_B8, EFI_KEY_B9, EFI_KEY_B10, EFI_KEY_RSHIFT, + EFI_KEY_UP_ARROW, EFI_KEY_ONE, EFI_KEY_TWO, EFI_KEY_THREE, + EFI_KEY_CAPS_LOCK, EFI_KEY_C1, EFI_KEY_C2, EFI_KEY_C3, EFI_KEY_C4, + EFI_KEY_C5, EFI_KEY_C6, EFI_KEY_C7, EFI_KEY_C8, EFI_KEY_C9, + EFI_KEY_C10, EFI_KEY_C11, EFI_KEY_C12, EFI_KEY_FOUR, EFI_KEY_FIVE, + EFI_KEY_SIX, EFI_KEY_PLUS, EFI_KEY_TAB, EFI_KEY_D1, EFI_KEY_D2, + EFI_KEY_D3, EFI_KEY_D4, EFI_KEY_D5, EFI_KEY_D6, EFI_KEY_D7, EFI_KEY_D8, + EFI_KEY_D9, EFI_KEY_D10, EFI_KEY_D11, EFI_KEY_D12, EFI_KEY_D13, + EFI_KEY_DEL, EFI_KEY_END, EFI_KEY_PG_DN, EFI_KEY_SEVEN, EFI_KEY_EIGHT, + EFI_KEY_NINE, EFI_KEY_E0, EFI_KEY_E1, EFI_KEY_E2, EFI_KEY_E3, + EFI_KEY_E4, EFI_KEY_E5, EFI_KEY_E6, EFI_KEY_E7, EFI_KEY_E8, EFI_KEY_E9, + EFI_KEY_E10, EFI_KEY_E11, EFI_KEY_E12, EFI_KEY_BACK_SPACE, + EFI_KEY_INS, EFI_KEY_HOME, EFI_KEY_PG_UP, EFI_KEY_NLCK, EFI_KEY_SLASH, + EFI_KEY_ASTERISK, EFI_KEY_MINUS, EFI_KEY_ESC, EFI_KEY_F1, EFI_KEY_F2, + EFI_KEY_F3, EFI_KEY_F4, EFI_KEY_F5, EFI_KEY_F6, EFI_KEY_F7, EFI_KEY_F8, + EFI_KEY_F9, EFI_KEY_F10, EFI_KEY_F11, EFI_KEY_F12, EFI_KEY_PRINT, + EFI_KEY_SLCK, EFI_KEY_PAUSE, +} efi_key; + +struct efi_key_descriptor { + u32 key; + u16 unicode; + u16 shifted_unicode; + u16 alt_gr_unicode; + u16 shifted_alt_gr_unicode; + u16 modifier; + u16 affected_attribute; +} __packed; + +struct efi_hii_keyboard_layout { + u16 layout_length; + efi_guid_t guid; + u32 layout_descriptor_string_offset; + u8 descriptor_count; + struct efi_key_descriptor descriptors[]; +} __packed; + +struct efi_hii_keyboard_package { + struct efi_hii_package_header header; + u16 layout_count; + struct efi_hii_keyboard_layout layout[]; +} __packed; + +/* + * HII protocols + */ +#define EFI_HII_STRING_PROTOCOL_GUID \ + EFI_GUID(0x0fd96974, 0x23aa, 0x4cdc, \ + 0xb9, 0xcb, 0x98, 0xd1, 0x77, 0x50, 0x32, 0x2a) + +struct efi_font_info { + efi_hii_font_style_t font_style; + u16 font_size; + u16 font_name[1]; +}; + +struct efi_hii_string_protocol { + efi_status_t(EFIAPI *new_string)( + const struct efi_hii_string_protocol *this, + efi_hii_handle_t package_list, + efi_string_id_t *string_id, + const u8 *language, + const u16 *language_name, + const efi_string_t string, + const struct efi_font_info *string_font_info); + efi_status_t(EFIAPI *get_string)( + const struct efi_hii_string_protocol *this, + const u8 *language, + efi_hii_handle_t package_list, + efi_string_id_t string_id, + efi_string_t string, + efi_uintn_t *string_size, + struct efi_font_info **string_font_info); + efi_status_t(EFIAPI *set_string)( + const struct efi_hii_string_protocol *this, + efi_hii_handle_t package_list, + efi_string_id_t string_id, + const u8 *language, + const efi_string_t string, + const struct efi_font_info *string_font_info); + efi_status_t(EFIAPI *get_languages)( + const struct efi_hii_string_protocol *this, + efi_hii_handle_t package_list, + u8 *languages, + efi_uintn_t *languages_size); + efi_status_t(EFIAPI *get_secondary_languages)( + const struct efi_hii_string_protocol *this, + efi_hii_handle_t package_list, + const u8 *primary_language, + u8 *secondary_languages, + efi_uintn_t *secondary_languages_size); +}; + +#define EFI_HII_DATABASE_PROTOCOL_GUID \ + EFI_GUID(0xef9fc172, 0xa1b2, 0x4693, \ + 0xb3, 0x27, 0x6d, 0x32, 0xfc, 0x41, 0x60, 0x42) + +struct efi_hii_database_protocol { + efi_status_t(EFIAPI *new_package_list)( + const struct efi_hii_database_protocol *this, + const struct efi_hii_package_list_header *package_list, + const efi_handle_t driver_handle, + efi_hii_handle_t *handle); + efi_status_t(EFIAPI *remove_package_list)( + const struct efi_hii_database_protocol *this, + efi_hii_handle_t handle); + efi_status_t(EFIAPI *update_package_list)( + const struct efi_hii_database_protocol *this, + efi_hii_handle_t handle, + const struct efi_hii_package_list_header *package_list); + efi_status_t(EFIAPI *list_package_lists)( + const struct efi_hii_database_protocol *this, + u8 package_type, + const efi_guid_t *package_guid, + efi_uintn_t *handle_buffer_length, + efi_hii_handle_t *handle); + efi_status_t(EFIAPI *export_package_lists)( + const struct efi_hii_database_protocol *this, + efi_hii_handle_t handle, + efi_uintn_t *buffer_size, + struct efi_hii_package_list_header *buffer); + efi_status_t(EFIAPI *register_package_notify)( + const struct efi_hii_database_protocol *this, + u8 package_type, + const efi_guid_t *package_guid, + const void *package_notify_fn, + efi_uintn_t notify_type, + efi_handle_t *notify_handle); + efi_status_t(EFIAPI *unregister_package_notify)( + const struct efi_hii_database_protocol *this, + efi_handle_t notification_handle + ); + efi_status_t(EFIAPI *find_keyboard_layouts)( + const struct efi_hii_database_protocol *this, + u16 *key_guid_buffer_length, + efi_guid_t *key_guid_buffer); + efi_status_t(EFIAPI *get_keyboard_layout)( + const struct efi_hii_database_protocol *this, + efi_guid_t *key_guid, + u16 *keyboard_layout_length, + struct efi_hii_keyboard_layout *keyboard_layout); + efi_status_t(EFIAPI *set_keyboard_layout)( + const struct efi_hii_database_protocol *this, + efi_guid_t *key_guid); + efi_status_t(EFIAPI *get_package_list_handle)( + const struct efi_hii_database_protocol *this, + efi_hii_handle_t package_list_handle, + efi_handle_t *driver_handle); +}; + +#define EFI_HII_CONFIG_ROUTING_PROTOCOL_GUID \ + EFI_GUID(0x587e72d7, 0xcc50, 0x4f79, \ + 0x82, 0x09, 0xca, 0x29, 0x1f, 0xc1, 0xa1, 0x0f) + +struct efi_hii_config_routing_protocol { + efi_status_t(EFIAPI *extract_config)( + const struct efi_hii_config_routing_protocol *this, + const efi_string_t request, + efi_string_t *progress, + efi_string_t *results); + efi_status_t(EFIAPI *export_config)( + const struct efi_hii_config_routing_protocol *this, + efi_string_t *results); + efi_status_t(EFIAPI *route_config)( + const struct efi_hii_config_routing_protocol *this, + const efi_string_t configuration, + efi_string_t *progress); + efi_status_t(EFIAPI *block_to_config)( + const struct efi_hii_config_routing_protocol *this, + const efi_string_t config_request, + const uint8_t *block, + const efi_uintn_t block_size, + efi_string_t *config, + efi_string_t *progress); + efi_status_t(EFIAPI *config_to_block)( + const struct efi_hii_config_routing_protocol *this, + const efi_string_t config_resp, + const uint8_t *block, + const efi_uintn_t *block_size, + efi_string_t *progress); + efi_status_t(EFIAPI *get_alt_config)( + const struct efi_hii_config_routing_protocol *this, + const efi_string_t config_resp, + const efi_guid_t *guid, + const efi_string_t name, + const struct efi_device_path *device_path, + const efi_string_t alt_cfg_id, + efi_string_t *alt_cfg_resp); +}; + +#define EFI_HII_CONFIG_ACCESS_PROTOCOL_GUID \ + EFI_GUID(0x330d4706, 0xf2a0, 0x4e4f, \ + 0xa3, 0x69, 0xb6, 0x6f, 0xa8, 0xd5, 0x43, 0x85) + +struct efi_hii_config_access_protocol { + efi_status_t(EFIAPI *extract_config_access)( + const struct efi_hii_config_access_protocol *this, + const efi_string_t request, + efi_string_t *progress, + efi_string_t *results); + efi_status_t(EFIAPI *route_config_access)( + const struct efi_hii_config_access_protocol *this, + const efi_string_t configuration, + efi_string_t *progress); + efi_status_t(EFIAPI *form_callback)( + const struct efi_hii_config_access_protocol *this, + efi_browser_action_t action, + efi_question_id_t question_id, + u8 type, + union efi_ifr_type_value *value, + efi_browser_action_request_t *action_request); +}; + +#define EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID \ + EFI_GUID(0x9042a9de, 0x23dc, 0x4a38, \ + 0x96, 0xfb, 0x7a, 0xde, 0xd0, 0x80, 0x51, 0x6a) + +#define EFI_GOT_RGBA8 0 +#define EFI_GOT_BGRA8 1 +#define EFI_GOT_BITMASK 2 + +struct efi_gop_mode_info { + u32 version; + u32 width; + u32 height; + u32 pixel_format; + u32 pixel_bitmask[4]; + u32 pixels_per_scanline; +}; + +struct efi_gop_mode { + u32 max_mode; + u32 mode; + struct efi_gop_mode_info *info; + unsigned long info_size; + efi_physical_addr_t fb_base; + unsigned long fb_size; +}; + +struct efi_gop_pixel { + u8 blue; + u8 green; + u8 red; + u8 reserved; +}; + +#define EFI_BLT_VIDEO_FILL 0 +#define EFI_BLT_VIDEO_TO_BLT_BUFFER 1 +#define EFI_BLT_BUFFER_TO_VIDEO 2 +#define EFI_BLT_VIDEO_TO_VIDEO 3 + +struct efi_gop { + efi_status_t (EFIAPI *query_mode)(struct efi_gop *this, u32 mode_number, + efi_uintn_t *size_of_info, + struct efi_gop_mode_info **info); + efi_status_t (EFIAPI *set_mode)(struct efi_gop *this, u32 mode_number); + efi_status_t (EFIAPI *blt)(struct efi_gop *this, + struct efi_gop_pixel *buffer, + u32 operation, efi_uintn_t sx, + efi_uintn_t sy, efi_uintn_t dx, + efi_uintn_t dy, efi_uintn_t width, + efi_uintn_t height, efi_uintn_t delta); + struct efi_gop_mode *mode; +}; + +#define EFI_SIMPLE_NETWORK_PROTOCOL_GUID \ + EFI_GUID(0xa19832b9, 0xac25, 0x11d3, \ + 0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d) + +struct efi_mac_address { + char mac_addr[32]; +}; + +struct efi_ip_address { + u8 ip_addr[16]; +} __attribute__((aligned(4))); + +enum efi_simple_network_state { + EFI_NETWORK_STOPPED, + EFI_NETWORK_STARTED, + EFI_NETWORK_INITIALIZED, +}; + +struct efi_simple_network_mode { + enum efi_simple_network_state state; + u32 hwaddr_size; + u32 media_header_size; + u32 max_packet_size; + u32 nvram_size; + u32 nvram_access_size; + u32 receive_filter_mask; + u32 receive_filter_setting; + u32 max_mcast_filter_count; + u32 mcast_filter_count; + struct efi_mac_address mcast_filter[16]; + struct efi_mac_address current_address; + struct efi_mac_address broadcast_address; + struct efi_mac_address permanent_address; + u8 if_type; + u8 mac_changeable; + u8 multitx_supported; + u8 media_present_supported; + u8 media_present; +}; + +/* receive_filters bit mask */ +#define EFI_SIMPLE_NETWORK_RECEIVE_UNICAST 0x01 +#define EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST 0x02 +#define EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST 0x04 +#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS 0x08 +#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST 0x10 + +/* interrupt status bit mask */ +#define EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT 0x01 +#define EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT 0x02 +#define EFI_SIMPLE_NETWORK_COMMAND_INTERRUPT 0x04 +#define EFI_SIMPLE_NETWORK_SOFTWARE_INTERRUPT 0x08 + +/* revision of the simple network protocol */ +#define EFI_SIMPLE_NETWORK_PROTOCOL_REVISION 0x00010000 + +struct efi_simple_network { + u64 revision; + efi_status_t (EFIAPI *start)(struct efi_simple_network *this); + efi_status_t (EFIAPI *stop)(struct efi_simple_network *this); + efi_status_t (EFIAPI *initialize)(struct efi_simple_network *this, + ulong extra_rx, ulong extra_tx); + efi_status_t (EFIAPI *reset)(struct efi_simple_network *this, + int extended_verification); + efi_status_t (EFIAPI *shutdown)(struct efi_simple_network *this); + efi_status_t (EFIAPI *receive_filters)(struct efi_simple_network *this, + u32 enable, u32 disable, int reset_mcast_filter, + ulong mcast_filter_count, + struct efi_mac_address *mcast_filter); + efi_status_t (EFIAPI *station_address)(struct efi_simple_network *this, + int reset, struct efi_mac_address *new_mac); + efi_status_t (EFIAPI *statistics)(struct efi_simple_network *this, + int reset, ulong *stat_size, void *stat_table); + efi_status_t (EFIAPI *mcastiptomac)(struct efi_simple_network *this, + int ipv6, struct efi_ip_address *ip, + struct efi_mac_address *mac); + efi_status_t (EFIAPI *nvdata)(struct efi_simple_network *this, + int read_write, ulong offset, ulong buffer_size, + char *buffer); + efi_status_t (EFIAPI *get_status)(struct efi_simple_network *this, + u32 *int_status, void **txbuf); + efi_status_t (EFIAPI *transmit)(struct efi_simple_network *this, + size_t header_size, size_t buffer_size, void *buffer, + struct efi_mac_address *src_addr, + struct efi_mac_address *dest_addr, u16 *protocol); + efi_status_t (EFIAPI *receive)(struct efi_simple_network *this, + size_t *header_size, size_t *buffer_size, void *buffer, + struct efi_mac_address *src_addr, + struct efi_mac_address *dest_addr, u16 *protocol); + struct efi_event *wait_for_packet; + struct efi_simple_network_mode *mode; + /* private fields */ + u32 int_status; +}; + +#define EFI_PXE_BASE_CODE_PROTOCOL_GUID \ + EFI_GUID(0x03c4e603, 0xac28, 0x11d3, \ + 0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d) + +#define EFI_PXE_BASE_CODE_PROTOCOL_REVISION 0x00010000 +#define EFI_PXE_BASE_CODE_MAX_IPCNT 8 + +struct efi_pxe_packet { + u8 packet[1472]; +}; + +struct efi_pxe_mode { + u8 started; + u8 ipv6_available; + u8 ipv6_supported; + u8 using_ipv6; + u8 bis_supported; + u8 bis_detected; + u8 auto_arp; + u8 send_guid; + u8 dhcp_discover_valid; + u8 dhcp_ack_received; + u8 proxy_offer_received; + u8 pxe_discover_valid; + u8 pxe_reply_received; + u8 pxe_bis_reply_received; + u8 icmp_error_received; + u8 tftp_error_received; + u8 make_callbacks; + u8 ttl; + u8 tos; + u8 pad; + struct efi_ip_address station_ip; + struct efi_ip_address subnet_mask; + struct efi_pxe_packet dhcp_discover; + struct efi_pxe_packet dhcp_ack; + struct efi_pxe_packet proxy_offer; + struct efi_pxe_packet pxe_discover; + struct efi_pxe_packet pxe_reply; +}; + +struct efi_pxe_base_code_srvlist { + u16 type; + u8 accept_any_response; + u8 reserved; + struct efi_ip_address ip_addr; +}; + +struct efi_pxe_base_code_discover_info { + u8 use_m_cast; + u8 use_b_cast; + u8 use_u_cast; + u8 must_use_list; + struct efi_ip_address server_m_cast_ip; + u16 ip_cnt; + struct efi_pxe_base_code_srvlist srv_list[]; +}; + +struct efi_pxe_base_code_mtftp_info { + struct efi_ip_address m_cast_ip; + u16 cport; + u16 sport; + u16 listen_timeout; + u16 transit_timeout; +}; + +struct efi_pxe_base_code_filter { + u8 filters; + u8 ip_cnt; + u16 reserved; + struct efi_ip_address ip_list[EFI_PXE_BASE_CODE_MAX_IPCNT]; +}; + +struct efi_pxe_base_code_dhcpv4_packet { + u8 bootp_op_code; + u8 bootp_hw_type; + u8 bootp_addr_len; + u8 bootp_gate_hops; + u32 bootp_ident; + u16 bootp_seconds; + u16 bootp_flags; + u8 bootp_ci_addr[4]; + u8 bootp_yi_addr[4]; + u8 bootp_si_addr[4]; + u8 bootp_gi_addr[4]; + u8 bootp_hw_addr[16]; + u8 bootp_srv_name[64]; + u8 bootp_boot_file[128]; + u32 dhcp_magick; + u8 dhcp_options[56]; +}; + +struct efi_pxe_base_code_dhcpv6_packet { + u8 message_type; + u8 transaction_id[3]; + u8 dhcp_options[1024]; +}; + +typedef union { + u8 raw[1472]; + struct efi_pxe_base_code_dhcpv4_packet dhcpv4; + struct efi_pxe_base_code_dhcpv6_packet dhcpv6; +} EFI_PXE_BASE_CODE_PACKET; + +struct efi_pxe_base_code_protocol { + u64 revision; + efi_status_t (EFIAPI *start)(struct efi_pxe_base_code_protocol *this, + u8 use_ipv6); + efi_status_t (EFIAPI *stop)(struct efi_pxe_base_code_protocol *this); + efi_status_t (EFIAPI *dhcp)(struct efi_pxe_base_code_protocol *this, + u8 sort_offers); + efi_status_t (EFIAPI *discover)( + struct efi_pxe_base_code_protocol *this, + u16 type, u16 *layer, u8 bis, + struct efi_pxe_base_code_discover_info *info); + efi_status_t (EFIAPI *mtftp)( + struct efi_pxe_base_code_protocol *this, + u32 operation, void *buffer_ptr, + u8 overwrite, efi_uintn_t *buffer_size, + struct efi_ip_address server_ip, char *filename, + struct efi_pxe_base_code_mtftp_info *info, + u8 dont_use_buffer); + efi_status_t (EFIAPI *udp_write)( + struct efi_pxe_base_code_protocol *this, + u16 op_flags, struct efi_ip_address *dest_ip, + u16 *dest_port, + struct efi_ip_address *gateway_ip, + struct efi_ip_address *src_ip, u16 *src_port, + efi_uintn_t *header_size, void *header_ptr, + efi_uintn_t *buffer_size, void *buffer_ptr); + efi_status_t (EFIAPI *udp_read)( + struct efi_pxe_base_code_protocol *this, + u16 op_flags, struct efi_ip_address *dest_ip, + u16 *dest_port, struct efi_ip_address *src_ip, + u16 *src_port, efi_uintn_t *header_size, + void *header_ptr, efi_uintn_t *buffer_size, + void *buffer_ptr); + efi_status_t (EFIAPI *set_ip_filter)( + struct efi_pxe_base_code_protocol *this, + struct efi_pxe_base_code_filter *new_filter); + efi_status_t (EFIAPI *arp)(struct efi_pxe_base_code_protocol *this, + struct efi_ip_address *ip_addr, + struct efi_mac_address *mac_addr); + efi_status_t (EFIAPI *set_parameters)( + struct efi_pxe_base_code_protocol *this, + u8 *new_auto_arp, u8 *new_send_guid, + u8 *new_ttl, u8 *new_tos, + u8 *new_make_callback); + efi_status_t (EFIAPI *set_station_ip)( + struct efi_pxe_base_code_protocol *this, + struct efi_ip_address *new_station_ip, + struct efi_ip_address *new_subnet_mask); + efi_status_t (EFIAPI *set_packets)( + struct efi_pxe_base_code_protocol *this, + u8 *new_dhcp_discover_valid, + u8 *new_dhcp_ack_received, + u8 *new_proxy_offer_received, + u8 *new_pxe_discover_valid, + u8 *new_pxe_reply_received, + u8 *new_pxe_bis_reply_received, + EFI_PXE_BASE_CODE_PACKET *new_dchp_discover, + EFI_PXE_BASE_CODE_PACKET *new_dhcp_acc, + EFI_PXE_BASE_CODE_PACKET *new_proxy_offer, + EFI_PXE_BASE_CODE_PACKET *new_pxe_discover, + EFI_PXE_BASE_CODE_PACKET *new_pxe_reply, + EFI_PXE_BASE_CODE_PACKET *new_pxe_bis_reply); + struct efi_pxe_mode *mode; +}; + +#define EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID \ + EFI_GUID(0x964e5b22, 0x6459, 0x11d2, \ + 0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b) +#define EFI_FILE_PROTOCOL_REVISION 0x00010000 +#define EFI_FILE_PROTOCOL_REVISION2 0x00020000 +#define EFI_FILE_PROTOCOL_LATEST_REVISION EFI_FILE_PROTOCOL_REVISION2 + +struct efi_file_io_token { + struct efi_event *event; + efi_status_t status; + efi_uintn_t buffer_size; + void *buffer;}; + +struct efi_file_handle { + u64 rev; + efi_status_t (EFIAPI *open)(struct efi_file_handle *this, + struct efi_file_handle **new_handle, + u16 *file_name, u64 open_mode, u64 attributes); + efi_status_t (EFIAPI *close)(struct efi_file_handle *this); + efi_status_t (EFIAPI *delete)(struct efi_file_handle *this); + efi_status_t (EFIAPI *read)(struct efi_file_handle *this, + efi_uintn_t *buffer_size, void *buffer); + efi_status_t (EFIAPI *write)(struct efi_file_handle *this, + efi_uintn_t *buffer_size, void *buffer); + efi_status_t (EFIAPI *getpos)(struct efi_file_handle *this, + u64 *pos); + efi_status_t (EFIAPI *setpos)(struct efi_file_handle *this, + u64 pos); + efi_status_t (EFIAPI *getinfo)(struct efi_file_handle *this, + const efi_guid_t *info_type, efi_uintn_t *buffer_size, + void *buffer); + efi_status_t (EFIAPI *setinfo)(struct efi_file_handle *this, + const efi_guid_t *info_type, efi_uintn_t buffer_size, + void *buffer); + efi_status_t (EFIAPI *flush)(struct efi_file_handle *this); + efi_status_t (EFIAPI *open_ex)(struct efi_file_handle *this, + struct efi_file_handle **new_handle, + u16 *file_name, u64 open_mode, u64 attributes, + struct efi_file_io_token *token); + efi_status_t (EFIAPI *read_ex)(struct efi_file_handle *this, + struct efi_file_io_token *token); + efi_status_t (EFIAPI *write_ex)(struct efi_file_handle *this, + struct efi_file_io_token *token); + efi_status_t (EFIAPI *flush_ex)(struct efi_file_handle *this, + struct efi_file_io_token *token); +}; + +#define EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION 0x00010000 + +struct efi_simple_file_system_protocol { + u64 rev; + efi_status_t (EFIAPI *open_volume)(struct efi_simple_file_system_protocol *this, + struct efi_file_handle **root); +}; + +#define EFI_FILE_INFO_GUID \ + EFI_GUID(0x9576e92, 0x6d3f, 0x11d2, \ + 0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b) + +#define EFI_FILE_SYSTEM_INFO_GUID \ + EFI_GUID(0x09576e93, 0x6d3f, 0x11d2, \ + 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b) + +#define EFI_FILE_SYSTEM_VOLUME_LABEL_ID \ + EFI_GUID(0xdb47d7d3, 0xfe81, 0x11d3, \ + 0x9a, 0x35, 0x00, 0x90, 0x27, 0x3f, 0xC1, 0x4d) + +#define EFI_FILE_MODE_READ 0x0000000000000001 +#define EFI_FILE_MODE_WRITE 0x0000000000000002 +#define EFI_FILE_MODE_CREATE 0x8000000000000000 + +#define EFI_FILE_READ_ONLY 0x0000000000000001 +#define EFI_FILE_HIDDEN 0x0000000000000002 +#define EFI_FILE_SYSTEM 0x0000000000000004 +#define EFI_FILE_RESERVED 0x0000000000000008 +#define EFI_FILE_DIRECTORY 0x0000000000000010 +#define EFI_FILE_ARCHIVE 0x0000000000000020 +#define EFI_FILE_VALID_ATTR 0x0000000000000037 + +struct efi_file_info { + u64 size; + u64 file_size; + u64 physical_size; + struct efi_time create_time; + struct efi_time last_access_time; + struct efi_time modification_time; + u64 attribute; + u16 file_name[0]; +}; + +struct efi_file_system_info { + u64 size; + u8 read_only; + u64 volume_size; + u64 free_space; + u32 block_size; + u16 volume_label[0]; +}; + +#define EFI_DRIVER_BINDING_PROTOCOL_GUID \ + EFI_GUID(0x18a031ab, 0xb443, 0x4d1a,\ + 0xa5, 0xc0, 0x0c, 0x09, 0x26, 0x1e, 0x9f, 0x71) +struct efi_driver_binding_protocol { + efi_status_t (EFIAPI * supported)( + struct efi_driver_binding_protocol *this, + efi_handle_t controller_handle, + struct efi_device_path *remaining_device_path); + efi_status_t (EFIAPI * start)( + struct efi_driver_binding_protocol *this, + efi_handle_t controller_handle, + struct efi_device_path *remaining_device_path); + efi_status_t (EFIAPI * stop)( + struct efi_driver_binding_protocol *this, + efi_handle_t controller_handle, + efi_uintn_t number_of_children, + efi_handle_t *child_handle_buffer); + u32 version; + efi_handle_t image_handle; + efi_handle_t driver_binding_handle; +}; + +/* Current version of the Unicode collation protocol */ +#define EFI_UNICODE_COLLATION_PROTOCOL2_GUID \ + EFI_GUID(0xa4c751fc, 0x23ae, 0x4c3e, \ + 0x92, 0xe9, 0x49, 0x64, 0xcf, 0x63, 0xf3, 0x49) +struct efi_unicode_collation_protocol { + efi_intn_t (EFIAPI *stri_coll)( + struct efi_unicode_collation_protocol *this, u16 *s1, u16 *s2); + bool (EFIAPI *metai_match)(struct efi_unicode_collation_protocol *this, + const u16 *string, const u16 *patter); + void (EFIAPI *str_lwr)(struct efi_unicode_collation_protocol + *this, u16 *string); + void (EFIAPI *str_upr)(struct efi_unicode_collation_protocol *this, + u16 *string); + void (EFIAPI *fat_to_str)(struct efi_unicode_collation_protocol *this, + efi_uintn_t fat_size, char *fat, u16 *string); + bool (EFIAPI *str_to_fat)(struct efi_unicode_collation_protocol *this, + const u16 *string, efi_uintn_t fat_size, + char *fat); + char *supported_languages; +}; + +struct efi_load_file_protocol { + efi_status_t (EFIAPI *load_file)(struct efi_load_file_protocol *this, + struct efi_device_path *file_path, + bool boot_policy, + efi_uintn_t *buffer_size, + void *buffer); +}; + +struct efi_system_resource_entry { + efi_guid_t fw_class; + u32 fw_type; + u32 fw_version; + u32 lowest_supported_fw_version; + u32 capsule_flags; + u32 last_attempt_version; + u32 last_attempt_status; +} __packed; + +struct efi_system_resource_table { + u32 fw_resource_count; + u32 fw_resource_count_max; + u64 fw_resource_version; + struct efi_system_resource_entry entries[]; +} __packed; + +/* Boot manager load options */ +#define LOAD_OPTION_ACTIVE 0x00000001 +#define LOAD_OPTION_FORCE_RECONNECT 0x00000002 +#define LOAD_OPTION_HIDDEN 0x00000008 +/* All values 0x00000200-0x00001F00 are reserved */ +#define LOAD_OPTION_CATEGORY 0x00001F00 +#define LOAD_OPTION_CATEGORY_BOOT 0x00000000 +#define LOAD_OPTION_CATEGORY_APP 0x00000100 + +/* + * System Resource Table + */ +/* Firmware Type Definitions */ +#define ESRT_FW_TYPE_UNKNOWN 0x00000000 +#define ESRT_FW_TYPE_SYSTEMFIRMWARE 0x00000001 +#define ESRT_FW_TYPE_DEVICEFIRMWARE 0x00000002 +#define ESRT_FW_TYPE_UEFIDRIVER 0x00000003 + +#define EFI_SYSTEM_RESOURCE_TABLE_GUID\ + EFI_GUID(0xb122a263, 0x3661, 0x4f68,\ + 0x99, 0x29, 0x78, 0xf8, 0xb0, 0xd6, 0x21, 0x80) + +/* Last Attempt Status Values */ +#define LAST_ATTEMPT_STATUS_SUCCESS 0x00000000 +#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL 0x00000001 +#define LAST_ATTEMPT_STATUS_ERROR_INSUFFICIENT_RESOURCES 0x00000002 +#define LAST_ATTEMPT_STATUS_ERROR_INCORRECT_VERSION 0x00000003 +#define LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT 0x00000004 +#define LAST_ATTEMPT_STATUS_ERROR_AUTH_ERROR 0x00000005 +#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_AC 0x00000006 +#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_BATT 0x00000007 +#define LAST_ATTEMPT_STATUS_ERROR_UNSATISFIED_DEPENDENCIES 0x00000008 + +/* + * The LastAttemptStatus values of 0x1000 - 0x4000 are reserved for vendor + * usage. + */ +#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MIN 0x00001000 +#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MAX 0x00004000 + +/* Certificate types in signature database */ +#define EFI_CERT_SHA256_GUID \ + EFI_GUID(0xc1c41626, 0x504c, 0x4092, 0xac, 0xa9, \ + 0x41, 0xf9, 0x36, 0x93, 0x43, 0x28) +#define EFI_CERT_RSA2048_GUID \ + EFI_GUID(0x3c5766e8, 0x269c, 0x4e34, 0xaa, 0x14, \ + 0xed, 0x77, 0x6e, 0x85, 0xb3, 0xb6) +#define EFI_CERT_X509_GUID \ + EFI_GUID(0xa5c059a1, 0x94e4, 0x4aa7, 0x87, 0xb5, \ + 0xab, 0x15, 0x5c, 0x2b, 0xf0, 0x72) +#define EFI_CERT_X509_SHA256_GUID \ + EFI_GUID(0x3bd2a492, 0x96c0, 0x4079, 0xb4, 0x20, \ + 0xfc, 0xf9, 0x8e, 0xf1, 0x03, 0xed) +#define EFI_CERT_TYPE_PKCS7_GUID \ + EFI_GUID(0x4aafd29d, 0x68df, 0x49ee, 0x8a, 0xa9, \ + 0x34, 0x7d, 0x37, 0x56, 0x65, 0xa7) + +/** + * win_certificate_uefi_guid - A certificate that encapsulates + * a GUID-specific signature + * + * @hdr: Windows certificate header + * @cert_type: Certificate type + * @cert_data: Certificate data + */ +struct win_certificate_uefi_guid { + WIN_CERTIFICATE hdr; + efi_guid_t cert_type; + u8 cert_data[]; +} __attribute__((__packed__)); + +/** + * efi_variable_authentication_2 - A time-based authentication method + * descriptor + * + * This structure describes an authentication information for + * a variable with EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS + * and should be included as part of a variable's value. + * Only EFI_CERT_TYPE_PKCS7_GUID is accepted. + * + * @time_stamp: Descriptor's time stamp + * @auth_info: Authentication info + */ +struct efi_variable_authentication_2 { + struct efi_time time_stamp; + struct win_certificate_uefi_guid auth_info; +} __attribute__((__packed__)); + +/** + * efi_firmware_image_authentication - Capsule authentication method + * descriptor + * + * This structure describes an authentication information for + * a capsule with IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED set + * and should be included as part of the capsule. + * Only EFI_CERT_TYPE_PKCS7_GUID is accepted. + * + * @monotonic_count: Count to prevent replay + * @auth_info: Authentication info + */ +struct efi_firmware_image_authentication { + uint64_t monotonic_count; + struct win_certificate_uefi_guid auth_info; +} __attribute__((__packed__)); + + +/** + * efi_signature_data - A format of signature + * + * This structure describes a single signature in signature database. + * + * @signature_owner: Signature owner + * @signature_data: Signature data + */ +struct efi_signature_data { + efi_guid_t signature_owner; + u8 signature_data[]; +} __attribute__((__packed__)); + +/** + * efi_signature_list - A format of signature database + * + * This structure describes a list of signatures with the same type. + * An authenticated variable's value is a concatenation of one or more + * efi_signature_list's. + * + * @signature_type: Signature type + * @signature_list_size: Size of signature list + * @signature_header_size: Size of signature header + * @signature_size: Size of signature + */ +struct efi_signature_list { + efi_guid_t signature_type; + u32 signature_list_size; + u32 signature_header_size; + u32 signature_size; +/* u8 signature_header[signature_header_size]; */ +/* struct efi_signature_data signatures[...][signature_size]; */ +} __attribute__((__packed__)); + +/* + * Firmware management protocol + */ +#define EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GUID \ + EFI_GUID(0x86c77a67, 0x0b97, 0x4633, 0xa1, 0x87, \ + 0x49, 0x10, 0x4d, 0x06, 0x85, 0xc7) + +#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID \ + EFI_GUID(0xae13ff2d, 0x9ad4, 0x4e25, 0x9a, 0xc8, \ + 0x6d, 0x80, 0xb3, 0xb2, 0x21, 0x47) + +#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID \ + EFI_GUID(0xe2bb9c06, 0x70e9, 0x4b14, 0x97, 0xa3, \ + 0x5a, 0x79, 0x13, 0x17, 0x6e, 0x3f) + +#define IMAGE_ATTRIBUTE_IMAGE_UPDATABLE 0x0000000000000001 +#define IMAGE_ATTRIBUTE_RESET_REQUIRED 0x0000000000000002 +#define IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED 0x0000000000000004 +#define IMAGE_ATTRIBUTE_IN_USE 0x0000000000000008 +#define IMAGE_ATTRIBUTE_UEFI_IMAGE 0x0000000000000010 +#define IMAGE_ATTRIBUTE_DEPENDENCY 0x0000000000000020 + +#define IMAGE_COMPATIBILITY_CHECK_SUPPORTED 0x0000000000000001 + +#define IMAGE_UPDATABLE_VALID 0x0000000000000001 +#define IMAGE_UPDATABLE_INVALID 0x0000000000000002 +#define IMAGE_UPDATABLE_INVALID_TYPE 0x0000000000000004 +#define IMAGE_UPDATABLE_INVALID_OLLD 0x0000000000000008 +#define IMAGE_UPDATABLE_VALID_WITH_VENDOR_CODE 0x0000000000000010 + +#define PACKAGE_ATTRIBUTE_VERSION_UPDATABLE 0x0000000000000001 +#define PACKAGE_ATTRIBUTE_RESET_REQUIRED 0x0000000000000002 +#define PACKAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED 0x0000000000000004 + +#define EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION 4 + +typedef struct efi_firmware_image_dependencies { + u8 dependencies[0]; +} efi_firmware_image_dep_t; + +struct efi_firmware_image_descriptor { + u8 image_index; + efi_guid_t image_type_id; + u64 image_id; + u16 *image_id_name; + u32 version; + u16 *version_name; + efi_uintn_t size; + u64 attributes_supported; + u64 attributes_setting; + u64 compatibilities; + u32 lowest_supported_image_version; + u32 last_attempt_version; + u32 last_attempt_status; + u64 hardware_instance; + efi_firmware_image_dep_t *dependencies; +}; + +struct efi_firmware_management_protocol { + efi_status_t (EFIAPI *get_image_info)( + struct efi_firmware_management_protocol *this, + efi_uintn_t *image_info_size, + struct efi_firmware_image_descriptor *image_info, + u32 *descriptor_version, + u8 *descriptor_count, + efi_uintn_t *descriptor_size, + u32 *package_version, + u16 **package_version_name); + efi_status_t (EFIAPI *get_image)( + struct efi_firmware_management_protocol *this, + u8 image_index, + void *image, + efi_uintn_t *image_size); + efi_status_t (EFIAPI *set_image)( + struct efi_firmware_management_protocol *this, + u8 image_index, + const void *image, + efi_uintn_t image_size, + const void *vendor_code, + efi_status_t (*progress)(efi_uintn_t completion), + u16 **abort_reason); + efi_status_t (EFIAPI *check_image)( + struct efi_firmware_management_protocol *this, + u8 image_index, + const void *image, + efi_uintn_t *image_size, + u32 *image_updatable); + efi_status_t (EFIAPI *get_package_info)( + struct efi_firmware_management_protocol *this, + u32 *package_version, + u16 **package_version_name, + u32 *package_version_name_maxlen, + u64 *attributes_supported, + u64 *attributes_setting); + efi_status_t (EFIAPI *set_package_info)( + struct efi_firmware_management_protocol *this, + const void *image, + efi_uintn_t *image_size, + const void *vendor_code, + u32 package_version, + const u16 *package_version_name); +}; + +#endif diff --git a/roms/u-boot/include/efi_driver.h b/roms/u-boot/include/efi_driver.h new file mode 100644 index 000000000..2b62219c5 --- /dev/null +++ b/roms/u-boot/include/efi_driver.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * EFI application loader + * + * Copyright (c) 2017 Heinrich Schuchardt + */ + +#ifndef _EFI_DRIVER_H +#define _EFI_DRIVER_H 1 + +#include + +/* + * Operations supported by an EFI driver with respect to the EFI uclass + * + * @protocol The GUID of the protocol which is consumed by the + * driver. This GUID is used by the EFI uclass in the + * supports() and start() methods of the + * EFI_DRIVER_BINDING_PROTOCOL. + * @child_protocol Protocol supported by the child handles generated by + * the EFI driver. + * @bind Function called by the EFI uclass to attach the + * driver to EFI driver to a handle. + */ +struct efi_driver_ops { + const efi_guid_t *protocol; + const efi_guid_t *child_protocol; + int (*bind)(efi_handle_t handle, void *interface); +}; + +/* + * This structure adds internal fields to the driver binding protocol. + */ +struct efi_driver_binding_extended_protocol { + struct efi_driver_binding_protocol bp; + const struct efi_driver_ops *ops; +}; + +#endif /* _EFI_DRIVER_H */ diff --git a/roms/u-boot/include/efi_dt_fixup.h b/roms/u-boot/include/efi_dt_fixup.h new file mode 100644 index 000000000..9066e8dd8 --- /dev/null +++ b/roms/u-boot/include/efi_dt_fixup.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * EFI_DT_FIXUP_PROTOCOL + * + * Copyright (c) 2020 Heinrich Schuchardt + */ + +#include + +#define EFI_DT_FIXUP_PROTOCOL_GUID \ + EFI_GUID(0xe617d64c, 0xfe08, 0x46da, 0xf4, 0xdc, \ + 0xbb, 0xd5, 0x87, 0x0c, 0x73, 0x00) + +#define EFI_DT_FIXUP_PROTOCOL_REVISION 0x00010000 + +/* Add nodes and update properties */ +#define EFI_DT_APPLY_FIXUPS 0x00000001 +/* + * Reserve memory according to the /reserved-memory node + * and the memory reservation block + */ +#define EFI_DT_RESERVE_MEMORY 0x00000002 +/* Install the device-tree as configuration table */ +#define EFI_DT_INSTALL_TABLE 0x00000004 + +#define EFI_DT_ALL (EFI_DT_APPLY_FIXUPS | \ + EFI_DT_RESERVE_MEMORY | \ + EFI_DT_INSTALL_TABLE) + +struct efi_dt_fixup_protocol { + u64 revision; + efi_status_t (EFIAPI *fixup) (struct efi_dt_fixup_protocol *this, + void *dtb, + efi_uintn_t *buffer_size, + u32 flags); +}; + +extern struct efi_dt_fixup_protocol efi_dt_fixup_prot; +extern const efi_guid_t efi_guid_dt_fixup_protocol; diff --git a/roms/u-boot/include/efi_load_initrd.h b/roms/u-boot/include/efi_load_initrd.h new file mode 100644 index 000000000..478ae807c --- /dev/null +++ b/roms/u-boot/include/efi_load_initrd.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2020, Linaro Limited + */ + +#if !defined _EFI_LOAD_INITRD_H_ +#define _EFI_LOAD_INITRD_H_ + +#include +#include + +/* + * Vendor GUID used by Linux to identify the handle with the + * EFI_LOAD_FILE2_PROTOCOL and load an initial ramdisk. + */ +#define EFI_INITRD_MEDIA_GUID \ + EFI_GUID(0x5568e427, 0x68fc, 0x4f3d, \ + 0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68) + +struct efi_initrd_dp { + struct efi_device_path_vendor vendor; + struct efi_device_path end; +} __packed; + +#endif diff --git a/roms/u-boot/include/efi_loader.h b/roms/u-boot/include/efi_loader.h new file mode 100644 index 000000000..b81180cfd --- /dev/null +++ b/roms/u-boot/include/efi_loader.h @@ -0,0 +1,976 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * EFI application loader + * + * Copyright (c) 2016 Alexander Graf + */ + +#ifndef _EFI_LOADER_H +#define _EFI_LOADER_H 1 + +#include +#include +#include +#include +#include +#include +#include + +struct blk_desc; + +static inline int guidcmp(const void *g1, const void *g2) +{ + return memcmp(g1, g2, sizeof(efi_guid_t)); +} + +static inline void *guidcpy(void *dst, const void *src) +{ + return memcpy(dst, src, sizeof(efi_guid_t)); +} + +/* No need for efi loader support in SPL */ +#if CONFIG_IS_ENABLED(EFI_LOADER) + +#include +#include + +/* Maximum number of configuration tables */ +#define EFI_MAX_CONFIGURATION_TABLES 16 + +/* GUID used by the root node */ +#define U_BOOT_GUID \ + EFI_GUID(0xe61d73b9, 0xa384, 0x4acc, \ + 0xae, 0xab, 0x82, 0xe8, 0x28, 0xf3, 0x62, 0x8b) +/* GUID used as host device on sandbox */ +#define U_BOOT_HOST_DEV_GUID \ + EFI_GUID(0xbbe4e671, 0x5773, 0x4ea1, \ + 0x9a, 0xab, 0x3a, 0x7d, 0xbf, 0x40, 0xc4, 0x82) +/* GUID used as root for virtio devices */ +#define U_BOOT_VIRTIO_DEV_GUID \ + EFI_GUID(0x63293792, 0xadf5, 0x9325, \ + 0xb9, 0x9f, 0x4e, 0x0e, 0x45, 0x5c, 0x1b, 0x1e) + +/* Use internal device tree when starting UEFI application */ +#define EFI_FDT_USE_INTERNAL NULL + +/* Root node */ +extern efi_handle_t efi_root; + +/* Set to EFI_SUCCESS when initialized */ +extern efi_status_t efi_obj_list_initialized; + +/* Flag used by the selftest to avoid detaching devices in ExitBootServices() */ +extern bool efi_st_keep_devices; + +/* EFI system partition */ +extern struct efi_system_partition { + enum if_type if_type; + int devnum; + u8 part; +} efi_system_partition; + +int __efi_entry_check(void); +int __efi_exit_check(void); +const char *__efi_nesting(void); +const char *__efi_nesting_inc(void); +const char *__efi_nesting_dec(void); + +/* + * Enter the u-boot world from UEFI: + */ +#define EFI_ENTRY(format, ...) do { \ + assert(__efi_entry_check()); \ + debug("%sEFI: Entry %s(" format ")\n", __efi_nesting_inc(), \ + __func__, ##__VA_ARGS__); \ + } while(0) + +/* + * Exit the u-boot world back to UEFI: + */ +#define EFI_EXIT(ret) ({ \ + typeof(ret) _r = ret; \ + debug("%sEFI: Exit: %s: %u\n", __efi_nesting_dec(), \ + __func__, (u32)((uintptr_t) _r & ~EFI_ERROR_MASK)); \ + assert(__efi_exit_check()); \ + _r; \ + }) + +/* + * Call non-void UEFI function from u-boot and retrieve return value: + */ +#define EFI_CALL(exp) ({ \ + debug("%sEFI: Call: %s\n", __efi_nesting_inc(), #exp); \ + assert(__efi_exit_check()); \ + typeof(exp) _r = exp; \ + assert(__efi_entry_check()); \ + debug("%sEFI: %lu returned by %s\n", __efi_nesting_dec(), \ + (unsigned long)((uintptr_t)_r & ~EFI_ERROR_MASK), #exp); \ + _r; \ +}) + +/* + * Call void UEFI function from u-boot: + */ +#define EFI_CALL_VOID(exp) do { \ + debug("%sEFI: Call: %s\n", __efi_nesting_inc(), #exp); \ + assert(__efi_exit_check()); \ + exp; \ + assert(__efi_entry_check()); \ + debug("%sEFI: Return From: %s\n", __efi_nesting_dec(), #exp); \ + } while(0) + +/* + * Write an indented message with EFI prefix + */ +#define EFI_PRINT(format, ...) ({ \ + debug("%sEFI: " format, __efi_nesting(), \ + ##__VA_ARGS__); \ + }) + +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define EFI_CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE +#else +/* Just use the greatest cache flush alignment requirement I'm aware of */ +#define EFI_CACHELINE_SIZE 128 +#endif + +/* Key identifying current memory map */ +extern efi_uintn_t efi_memory_map_key; + +extern struct efi_runtime_services efi_runtime_services; +extern struct efi_system_table systab; + +extern struct efi_simple_text_output_protocol efi_con_out; +extern struct efi_simple_text_input_protocol efi_con_in; +extern struct efi_console_control_protocol efi_console_control; +extern const struct efi_device_path_to_text_protocol efi_device_path_to_text; +/* implementation of the EFI_DEVICE_PATH_UTILITIES_PROTOCOL */ +extern const struct efi_device_path_utilities_protocol + efi_device_path_utilities; +/* current version of the EFI_UNICODE_COLLATION_PROTOCOL */ +extern const struct efi_unicode_collation_protocol + efi_unicode_collation_protocol2; +extern const struct efi_hii_config_routing_protocol efi_hii_config_routing; +extern const struct efi_hii_config_access_protocol efi_hii_config_access; +extern const struct efi_hii_database_protocol efi_hii_database; +extern const struct efi_hii_string_protocol efi_hii_string; + +uint16_t *efi_dp_str(struct efi_device_path *dp); + +/* GUID of the U-Boot root node */ +extern const efi_guid_t efi_u_boot_guid; +#ifdef CONFIG_SANDBOX +/* GUID of U-Boot host device on sandbox */ +extern const efi_guid_t efi_guid_host_dev; +#endif +/* GUID of the EFI_BLOCK_IO_PROTOCOL */ +extern const efi_guid_t efi_block_io_guid; +extern const efi_guid_t efi_global_variable_guid; +extern const efi_guid_t efi_guid_console_control; +extern const efi_guid_t efi_guid_device_path; +/* GUID of the EFI_DRIVER_BINDING_PROTOCOL */ +extern const efi_guid_t efi_guid_driver_binding_protocol; +/* event group ExitBootServices() invoked */ +extern const efi_guid_t efi_guid_event_group_exit_boot_services; +/* event group SetVirtualAddressMap() invoked */ +extern const efi_guid_t efi_guid_event_group_virtual_address_change; +/* event group memory map changed */ +extern const efi_guid_t efi_guid_event_group_memory_map_change; +/* event group boot manager about to boot */ +extern const efi_guid_t efi_guid_event_group_ready_to_boot; +/* event group ResetSystem() invoked (before ExitBootServices) */ +extern const efi_guid_t efi_guid_event_group_reset_system; +/* GUID of the device tree table */ +extern const efi_guid_t efi_guid_fdt; +extern const efi_guid_t efi_guid_loaded_image; +extern const efi_guid_t efi_guid_loaded_image_device_path; +extern const efi_guid_t efi_guid_device_path_to_text_protocol; +extern const efi_guid_t efi_simple_file_system_protocol_guid; +extern const efi_guid_t efi_file_info_guid; +/* GUID for file system information */ +extern const efi_guid_t efi_file_system_info_guid; +extern const efi_guid_t efi_guid_device_path_utilities_protocol; +/* GUID of the deprecated Unicode collation protocol */ +extern const efi_guid_t efi_guid_unicode_collation_protocol; +/* GUIDs of the Load File and Load File2 protocol */ +extern const efi_guid_t efi_guid_load_file_protocol; +extern const efi_guid_t efi_guid_load_file2_protocol; +/* GUID of the Unicode collation protocol */ +extern const efi_guid_t efi_guid_unicode_collation_protocol2; +extern const efi_guid_t efi_guid_hii_config_routing_protocol; +extern const efi_guid_t efi_guid_hii_config_access_protocol; +extern const efi_guid_t efi_guid_hii_database_protocol; +extern const efi_guid_t efi_guid_hii_string_protocol; +/* GUIDs for authentication */ +extern const efi_guid_t efi_guid_image_security_database; +extern const efi_guid_t efi_guid_sha256; +extern const efi_guid_t efi_guid_cert_x509; +extern const efi_guid_t efi_guid_cert_x509_sha256; +extern const efi_guid_t efi_guid_cert_type_pkcs7; + +/* GUID of RNG protocol */ +extern const efi_guid_t efi_guid_rng_protocol; +/* GUID of capsule update result */ +extern const efi_guid_t efi_guid_capsule_report; +/* GUID of firmware management protocol */ +extern const efi_guid_t efi_guid_firmware_management_protocol; +/* GUID for the ESRT */ +extern const efi_guid_t efi_esrt_guid; + +extern char __efi_runtime_start[], __efi_runtime_stop[]; +extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[]; + +/** + * struct efi_open_protocol_info_item - open protocol info item + * + * When a protocol is opened a open protocol info entry is created. + * These are maintained in a list. + * + * @link: link to the list of open protocol info entries of a protocol + * @info: information about the opening of a protocol + */ +struct efi_open_protocol_info_item { + struct list_head link; + struct efi_open_protocol_info_entry info; +}; + +/** + * struct efi_handler - single protocol interface of a handle + * + * When the UEFI payload wants to open a protocol on an object to get its + * interface (usually a struct with callback functions), this struct maps the + * protocol GUID to the respective protocol interface + * + * @link: link to the list of protocols of a handle + * @guid: GUID of the protocol + * @protocol_interface: protocol interface + * @open_infos: link to the list of open protocol info items + */ +struct efi_handler { + struct list_head link; + const efi_guid_t *guid; + void *protocol_interface; + struct list_head open_infos; +}; + +/** + * enum efi_object_type - type of EFI object + * + * In UnloadImage we must be able to identify if the handle relates to a + * started image. + */ +enum efi_object_type { + /** @EFI_OBJECT_TYPE_UNDEFINED: undefined image type */ + EFI_OBJECT_TYPE_UNDEFINED = 0, + /** @EFI_OBJECT_TYPE_U_BOOT_FIRMWARE: U-Boot firmware */ + EFI_OBJECT_TYPE_U_BOOT_FIRMWARE, + /** @EFI_OBJECT_TYPE_LOADED_IMAGE: loaded image (not started) */ + EFI_OBJECT_TYPE_LOADED_IMAGE, + /** @EFI_OBJECT_TYPE_STARTED_IMAGE: started image */ + EFI_OBJECT_TYPE_STARTED_IMAGE, +}; + +/** + * struct efi_object - dereferenced EFI handle + * + * @link: pointers to put the handle into a linked list + * @protocols: linked list with the protocol interfaces installed on this + * handle + * @type: image type if the handle relates to an image + * + * UEFI offers a flexible and expandable object model. The objects in the UEFI + * API are devices, drivers, and loaded images. struct efi_object is our storage + * structure for these objects. + * + * When including this structure into a larger structure always put it first so + * that when deleting a handle the whole encompassing structure can be freed. + * + * A pointer to this structure is referred to as a handle. Typedef efi_handle_t + * has been created for such pointers. + */ +struct efi_object { + /* Every UEFI object is part of a global object list */ + struct list_head link; + /* The list of protocols */ + struct list_head protocols; + enum efi_object_type type; +}; + +enum efi_image_auth_status { + EFI_IMAGE_AUTH_FAILED = 0, + EFI_IMAGE_AUTH_PASSED, +}; + +/** + * struct efi_loaded_image_obj - handle of a loaded image + * + * @header: EFI object header + * @exit_status: exit status passed to Exit() + * @exit_data_size: exit data size passed to Exit() + * @exit_data: exit data passed to Exit() + * @exit_jmp: long jump buffer for returning from started image + * @entry: entry address of the relocated image + * @image_type: indicates if the image is an applicition or a driver + * @auth_status: indicates if the image is authenticated + */ +struct efi_loaded_image_obj { + struct efi_object header; + efi_status_t *exit_status; + efi_uintn_t *exit_data_size; + u16 **exit_data; + struct jmp_buf_data *exit_jmp; + EFIAPI efi_status_t (*entry)(efi_handle_t image_handle, + struct efi_system_table *st); + u16 image_type; + enum efi_image_auth_status auth_status; +}; + +/** + * struct efi_event + * + * @link: Link to list of all events + * @queue_link: Link to the list of queued events + * @type: Type of event, see efi_create_event + * @notify_tpl: Task priority level of notifications + * @notify_function: Function to call when the event is triggered + * @notify_context: Data to be passed to the notify function + * @group: Event group + * @trigger_time: Period of the timer + * @trigger_next: Next time to trigger the timer + * @trigger_type: Type of timer, see efi_set_timer + * @is_signaled: The event occurred. The event is in the signaled state. + */ +struct efi_event { + struct list_head link; + struct list_head queue_link; + uint32_t type; + efi_uintn_t notify_tpl; + void (EFIAPI *notify_function)(struct efi_event *event, void *context); + void *notify_context; + const efi_guid_t *group; + u64 trigger_next; + u64 trigger_time; + enum efi_timer_delay trigger_type; + bool is_signaled; +}; + +/* This list contains all UEFI objects we know of */ +extern struct list_head efi_obj_list; +/* List of all events */ +extern struct list_head efi_events; + +/** + * struct efi_protocol_notification - handle for notified protocol + * + * When a protocol interface is installed for which an event was registered with + * the RegisterProtocolNotify() service this structure is used to hold the + * handle on which the protocol interface was installed. + * + * @link: link to list of all handles notified for this event + * @handle: handle on which the notified protocol interface was installed + */ +struct efi_protocol_notification { + struct list_head link; + efi_handle_t handle; +}; + +/** + * struct efi_register_notify_event - event registered by + * RegisterProtocolNotify() + * + * The address of this structure serves as registration value. + * + * @link: link to list of all registered events + * @event: registered event. The same event may registered for multiple + * GUIDs. + * @protocol: protocol for which the event is registered + * @handles: linked list of all handles on which the notified protocol was + * installed + */ +struct efi_register_notify_event { + struct list_head link; + struct efi_event *event; + efi_guid_t protocol; + struct list_head handles; +}; + +/* List of all events registered by RegisterProtocolNotify() */ +extern struct list_head efi_register_notify_events; + +/* Initialize efi execution environment */ +efi_status_t efi_init_obj_list(void); +/* Install device tree */ +efi_status_t efi_install_fdt(void *fdt); +/* Run loaded UEFI image */ +efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size); +/* Initialize variable services */ +efi_status_t efi_init_variables(void); +/* Notify ExitBootServices() is called */ +void efi_variables_boot_exit_notify(void); +/* Called by bootefi to initialize root node */ +efi_status_t efi_root_node_register(void); +/* Called by bootefi to initialize runtime */ +efi_status_t efi_initialize_system_table(void); +/* efi_runtime_detach() - detach unimplemented runtime functions */ +void efi_runtime_detach(void); +/* efi_convert_pointer() - convert pointer to virtual address */ +efi_status_t EFIAPI efi_convert_pointer(efi_uintn_t debug_disposition, + void **address); +/* Carve out DT reserved memory ranges */ +void efi_carve_out_dt_rsv(void *fdt); +/* Called by bootefi to make console interface available */ +efi_status_t efi_console_register(void); +/* Called by bootefi to make all disk storage accessible as EFI objects */ +efi_status_t efi_disk_register(void); +/* Called by efi_init_obj_list() to install EFI_RNG_PROTOCOL */ +efi_status_t efi_rng_register(void); +/* Called by efi_init_obj_list() to install EFI_TCG2_PROTOCOL */ +efi_status_t efi_tcg2_register(void); +/* measure the pe-coff image, extend PCR and add Event Log */ +efi_status_t tcg2_measure_pe_image(void *efi, u64 efi_size, + struct efi_loaded_image_obj *handle, + struct efi_loaded_image *loaded_image_info); +/* Create handles and protocols for the partitions of a block device */ +int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc, + const char *if_typename, int diskid, + const char *pdevname); +/* Check if it is EFI system partition */ +bool efi_disk_is_system_part(efi_handle_t handle); +/* Called by bootefi to make GOP (graphical) interface available */ +efi_status_t efi_gop_register(void); +/* Called by bootefi to make the network interface available */ +efi_status_t efi_net_register(void); +/* Called by bootefi to make the watchdog available */ +efi_status_t efi_watchdog_register(void); +efi_status_t efi_initrd_register(void); +void efi_initrd_deregister(void); +/* Called by bootefi to make SMBIOS tables available */ +/** + * efi_acpi_register() - write out ACPI tables + * + * Called by bootefi to make ACPI tables available + * + * @return 0 if OK, -ENOMEM if no memory is available for the tables + */ +efi_status_t efi_acpi_register(void); +/** + * efi_smbios_register() - write out SMBIOS tables + * + * Called by bootefi to make SMBIOS tables available + * + * @return 0 if OK, -ENOMEM if no memory is available for the tables + */ +efi_status_t efi_smbios_register(void); + +struct efi_simple_file_system_protocol * +efi_fs_from_path(struct efi_device_path *fp); + +/* Called by networking code to memorize the dhcp ack package */ +void efi_net_set_dhcp_ack(void *pkt, int len); +/* Called by efi_set_watchdog_timer to reset the timer */ +efi_status_t efi_set_watchdog(unsigned long timeout); + +/* Called from places to check whether a timer expired */ +void efi_timer_check(void); +/* Check if a buffer contains a PE-COFF image */ +efi_status_t efi_check_pe(void *buffer, size_t size, void **nt_header); +/* PE loader implementation */ +efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, + void *efi, size_t efi_size, + struct efi_loaded_image *loaded_image_info); +/* Called once to store the pristine gd pointer */ +void efi_save_gd(void); +/* Special case handler for error/abort that just tries to dtrt to get + * back to u-boot world */ +void efi_restore_gd(void); +/* Call this to relocate the runtime section to an address space */ +void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map); +/* Call this to set the current device name */ +void efi_set_bootdev(const char *dev, const char *devnr, const char *path, + void *buffer, size_t buffer_size); +/* Add a new object to the object list. */ +void efi_add_handle(efi_handle_t obj); +/* Create handle */ +efi_status_t efi_create_handle(efi_handle_t *handle); +/* Delete handle */ +void efi_delete_handle(efi_handle_t obj); +/* Call this to validate a handle and find the EFI object for it */ +struct efi_object *efi_search_obj(const efi_handle_t handle); +/* Load image */ +efi_status_t EFIAPI efi_load_image(bool boot_policy, + efi_handle_t parent_image, + struct efi_device_path *file_path, + void *source_buffer, + efi_uintn_t source_size, + efi_handle_t *image_handle); +/* Start image */ +efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle, + efi_uintn_t *exit_data_size, + u16 **exit_data); +/* Unload image */ +efi_status_t EFIAPI efi_unload_image(efi_handle_t image_handle); +/* Find a protocol on a handle */ +efi_status_t efi_search_protocol(const efi_handle_t handle, + const efi_guid_t *protocol_guid, + struct efi_handler **handler); +/* Install new protocol on a handle */ +efi_status_t efi_add_protocol(const efi_handle_t handle, + const efi_guid_t *protocol, + void *protocol_interface); +/* Open protocol */ +efi_status_t efi_protocol_open(struct efi_handler *handler, + void **protocol_interface, void *agent_handle, + void *controller_handle, uint32_t attributes); + +/* Delete protocol from a handle */ +efi_status_t efi_remove_protocol(const efi_handle_t handle, + const efi_guid_t *protocol, + void *protocol_interface); +/* Delete all protocols from a handle */ +efi_status_t efi_remove_all_protocols(const efi_handle_t handle); +/* Install multiple protocol interfaces */ +efi_status_t EFIAPI efi_install_multiple_protocol_interfaces + (efi_handle_t *handle, ...); +/* Get handles that support a given protocol */ +efi_status_t EFIAPI efi_locate_handle_buffer( + enum efi_locate_search_type search_type, + const efi_guid_t *protocol, void *search_key, + efi_uintn_t *no_handles, efi_handle_t **buffer); +/* Close an previously opened protocol interface */ +efi_status_t EFIAPI efi_close_protocol(efi_handle_t handle, + const efi_guid_t *protocol, + efi_handle_t agent_handle, + efi_handle_t controller_handle); +/* Open a protocol interface */ +efi_status_t EFIAPI efi_handle_protocol(efi_handle_t handle, + const efi_guid_t *protocol, + void **protocol_interface); +/* Call this to create an event */ +efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl, + void (EFIAPI *notify_function) ( + struct efi_event *event, + void *context), + void *notify_context, efi_guid_t *group, + struct efi_event **event); +/* Call this to set a timer */ +efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type, + uint64_t trigger_time); +/* Call this to signal an event */ +void efi_signal_event(struct efi_event *event); + +/* open file system: */ +struct efi_simple_file_system_protocol *efi_simple_file_system( + struct blk_desc *desc, int part, struct efi_device_path *dp); + +/* open file from device-path: */ +struct efi_file_handle *efi_file_from_path(struct efi_device_path *fp); + +/* Registers a callback function for a notification event. */ +efi_status_t EFIAPI efi_register_protocol_notify(const efi_guid_t *protocol, + struct efi_event *event, + void **registration); +efi_status_t efi_file_size(struct efi_file_handle *fh, efi_uintn_t *size); + +/* get a device path from a Boot#### option */ +struct efi_device_path *efi_get_dp_from_boot(const efi_guid_t guid); + +/** + * efi_size_in_pages() - convert size in bytes to size in pages + * + * This macro returns the number of EFI memory pages required to hold 'size' + * bytes. + * + * @size: size in bytes + * Return: size in pages + */ +#define efi_size_in_pages(size) (((size) + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT) +/* Generic EFI memory allocator, call this to get memory */ +void *efi_alloc(uint64_t len, int memory_type); +/* More specific EFI memory allocator, called by EFI payloads */ +efi_status_t efi_allocate_pages(int type, int memory_type, efi_uintn_t pages, + uint64_t *memory); +/* EFI memory free function. */ +efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages); +/* EFI memory allocator for small allocations */ +efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size, + void **buffer); +/* EFI pool memory free function. */ +efi_status_t efi_free_pool(void *buffer); +/* Returns the EFI memory map */ +efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size, + struct efi_mem_desc *memory_map, + efi_uintn_t *map_key, + efi_uintn_t *descriptor_size, + uint32_t *descriptor_version); +/* Adds a range into the EFI memory map */ +efi_status_t efi_add_memory_map(u64 start, u64 size, int memory_type); +/* Adds a conventional range into the EFI memory map */ +efi_status_t efi_add_conventional_memory_map(u64 ram_start, u64 ram_end, + u64 ram_top); + +/* Called by board init to initialize the EFI drivers */ +efi_status_t efi_driver_init(void); +/* Called by board init to initialize the EFI memory map */ +int efi_memory_init(void); +/* Adds new or overrides configuration table entry to the system table */ +efi_status_t efi_install_configuration_table(const efi_guid_t *guid, void *table); +/* Sets up a loaded image */ +efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path, + struct efi_device_path *file_path, + struct efi_loaded_image_obj **handle_ptr, + struct efi_loaded_image **info_ptr); +/* Print information about all loaded images */ +void efi_print_image_infos(void *pc); + +#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER +extern void *efi_bounce_buffer; +#define EFI_LOADER_BOUNCE_BUFFER_SIZE (64 * 1024 * 1024) +#endif + + +struct efi_device_path *efi_dp_next(const struct efi_device_path *dp); +int efi_dp_match(const struct efi_device_path *a, + const struct efi_device_path *b); +struct efi_object *efi_dp_find_obj(struct efi_device_path *dp, + struct efi_device_path **rem); +/* get size of the first device path instance excluding end node */ +efi_uintn_t efi_dp_instance_size(const struct efi_device_path *dp); +/* size of multi-instance device path excluding end node */ +efi_uintn_t efi_dp_size(const struct efi_device_path *dp); +struct efi_device_path *efi_dp_dup(const struct efi_device_path *dp); +struct efi_device_path *efi_dp_append(const struct efi_device_path *dp1, + const struct efi_device_path *dp2); +struct efi_device_path *efi_dp_append_node(const struct efi_device_path *dp, + const struct efi_device_path *node); +/* Create a device path node of given type, sub-type, length */ +struct efi_device_path *efi_dp_create_device_node(const u8 type, + const u8 sub_type, + const u16 length); +/* Append device path instance */ +struct efi_device_path *efi_dp_append_instance( + const struct efi_device_path *dp, + const struct efi_device_path *dpi); +/* Get next device path instance */ +struct efi_device_path *efi_dp_get_next_instance(struct efi_device_path **dp, + efi_uintn_t *size); +/* Check if a device path contains muliple instances */ +bool efi_dp_is_multi_instance(const struct efi_device_path *dp); + +struct efi_device_path *efi_dp_from_part(struct blk_desc *desc, int part); +/* Create a device node for a block device partition. */ +struct efi_device_path *efi_dp_part_node(struct blk_desc *desc, int part); +struct efi_device_path *efi_dp_from_file(struct blk_desc *desc, int part, + const char *path); +struct efi_device_path *efi_dp_from_eth(void); +struct efi_device_path *efi_dp_from_mem(uint32_t mem_type, + uint64_t start_address, + uint64_t end_address); +/* Determine the last device path node that is not the end node. */ +const struct efi_device_path *efi_dp_last_node( + const struct efi_device_path *dp); +efi_status_t efi_dp_split_file_path(struct efi_device_path *full_path, + struct efi_device_path **device_path, + struct efi_device_path **file_path); +efi_status_t efi_dp_from_name(const char *dev, const char *devnr, + const char *path, + struct efi_device_path **device, + struct efi_device_path **file); +ssize_t efi_dp_check_length(const struct efi_device_path *dp, + const size_t maxlen); + +#define EFI_DP_TYPE(_dp, _type, _subtype) \ + (((_dp)->type == DEVICE_PATH_TYPE_##_type) && \ + ((_dp)->sub_type == DEVICE_PATH_SUB_TYPE_##_subtype)) + +/** + * __efi_runtime_data - declares a non-const variable for EFI runtime section + * + * This macro indicates that a variable is non-const and should go into the + * EFI runtime section, and thus still be available when the OS is running. + * + * Only use on variables not declared const. + * + * Example: + * + * :: + * + * static __efi_runtime_data my_computed_table[256]; + */ +#define __efi_runtime_data __section(".data.efi_runtime") + +/** + * __efi_runtime_rodata - declares a read-only variable for EFI runtime section + * + * This macro indicates that a variable is read-only (const) and should go into + * the EFI runtime section, and thus still be available when the OS is running. + * + * Only use on variables also declared const. + * + * Example: + * + * :: + * + * static const __efi_runtime_rodata my_const_table[] = { 1, 2, 3 }; + */ +#define __efi_runtime_rodata __section(".rodata.efi_runtime") + +/** + * __efi_runtime - declares a function for EFI runtime section + * + * This macro indicates that a function should go into the EFI runtime section, + * and thus still be available when the OS is running. + * + * Example: + * + * :: + * + * static __efi_runtime compute_my_table(void); + */ +#define __efi_runtime __section(".text.efi_runtime") + +/* Indicate supported runtime services */ +efi_status_t efi_init_runtime_supported(void); + +/* Update CRC32 in table header */ +void __efi_runtime efi_update_table_header_crc32(struct efi_table_hdr *table); + +/* Call this with mmio_ptr as the _pointer_ to a pointer to an MMIO region + * to make it available at runtime */ +efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len); + +/* Boards may provide the functions below to implement RTS functionality */ + +void __efi_runtime EFIAPI efi_reset_system( + enum efi_reset_type reset_type, + efi_status_t reset_status, + unsigned long data_size, void *reset_data); + +/* Architecture specific initialization of the EFI subsystem */ +efi_status_t efi_reset_system_init(void); + +efi_status_t __efi_runtime EFIAPI efi_get_time( + struct efi_time *time, + struct efi_time_cap *capabilities); + +efi_status_t __efi_runtime EFIAPI efi_set_time(struct efi_time *time); + +#ifdef CONFIG_CMD_BOOTEFI_SELFTEST +/* + * Entry point for the tests of the EFI API. + * It is called by 'bootefi selftest' + */ +efi_status_t EFIAPI efi_selftest(efi_handle_t image_handle, + struct efi_system_table *systab); +#endif + +efi_status_t EFIAPI efi_get_variable(u16 *variable_name, + const efi_guid_t *vendor, u32 *attributes, + efi_uintn_t *data_size, void *data); +efi_status_t EFIAPI efi_get_next_variable_name(efi_uintn_t *variable_name_size, + u16 *variable_name, + efi_guid_t *vendor); +efi_status_t EFIAPI efi_set_variable(u16 *variable_name, + const efi_guid_t *vendor, u32 attributes, + efi_uintn_t data_size, const void *data); + +efi_status_t EFIAPI efi_query_variable_info( + u32 attributes, u64 *maximum_variable_storage_size, + u64 *remaining_variable_storage_size, + u64 *maximum_variable_size); + +void *efi_get_var(u16 *name, const efi_guid_t *vendor, efi_uintn_t *size); + +/* + * See section 3.1.3 in the v2.7 UEFI spec for more details on + * the layout of EFI_LOAD_OPTION. In short it is: + * + * typedef struct _EFI_LOAD_OPTION { + * UINT32 Attributes; + * UINT16 FilePathListLength; + * // CHAR16 Description[]; <-- variable length, NULL terminated + * // EFI_DEVICE_PATH_PROTOCOL FilePathList[]; + * <-- FilePathListLength bytes + * // UINT8 OptionalData[]; + * } EFI_LOAD_OPTION; + */ +struct efi_load_option { + u32 attributes; + u16 file_path_length; + u16 *label; + struct efi_device_path *file_path; + const u8 *optional_data; +}; + +struct efi_device_path *efi_dp_from_lo(struct efi_load_option *lo, + efi_uintn_t *size, efi_guid_t guid); +struct efi_device_path *efi_dp_concat(const struct efi_device_path *dp1, + const struct efi_device_path *dp2); +efi_status_t efi_deserialize_load_option(struct efi_load_option *lo, u8 *data, + efi_uintn_t *size); +unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8 **data); +efi_status_t efi_set_load_options(efi_handle_t handle, + efi_uintn_t load_options_size, + void *load_options); +efi_status_t efi_bootmgr_load(efi_handle_t *handle, void **load_options); + +/** + * struct efi_image_regions - A list of memory regions + * + * @max: Maximum number of regions + * @num: Number of regions + * @reg: array of regions + */ +struct efi_image_regions { + int max; + int num; + struct image_region reg[]; +}; + +/** + * struct efi_sig_data - A decoded data of struct efi_signature_data + * + * This structure represents an internal form of signature in + * signature database. A listed list may represent a signature list. + * + * @next: Pointer to next entry + * @owner: Signature owner + * @data: Pointer to signature data + * @size: Size of signature data + */ +struct efi_sig_data { + struct efi_sig_data *next; + efi_guid_t owner; + void *data; + size_t size; +}; + +/** + * struct efi_signature_store - A decoded data of signature database + * + * This structure represents an internal form of signature database. + * + * @next: Pointer to next entry + * @sig_type: Signature type + * @sig_data_list: Pointer to signature list + */ +struct efi_signature_store { + struct efi_signature_store *next; + efi_guid_t sig_type; + struct efi_sig_data *sig_data_list; +}; + +struct x509_certificate; +struct pkcs7_message; + +bool efi_signature_lookup_digest(struct efi_image_regions *regs, + struct efi_signature_store *db); +bool efi_signature_verify(struct efi_image_regions *regs, + struct pkcs7_message *msg, + struct efi_signature_store *db, + struct efi_signature_store *dbx); +static inline bool efi_signature_verify_one(struct efi_image_regions *regs, + struct pkcs7_message *msg, + struct efi_signature_store *db) +{ + return efi_signature_verify(regs, msg, db, NULL); +} +bool efi_signature_check_signers(struct pkcs7_message *msg, + struct efi_signature_store *dbx); + +efi_status_t efi_image_region_add(struct efi_image_regions *regs, + const void *start, const void *end, + int nocheck); + +void efi_sigstore_free(struct efi_signature_store *sigstore); +struct efi_signature_store *efi_build_signature_store(void *sig_list, + efi_uintn_t size); +struct efi_signature_store *efi_sigstore_parse_sigdb(u16 *name); + +bool efi_secure_boot_enabled(void); + +bool efi_capsule_auth_enabled(void); + +void *efi_prepare_aligned_image(void *efi, u64 *efi_size); + +bool efi_image_parse(void *efi, size_t len, struct efi_image_regions **regp, + WIN_CERTIFICATE **auth, size_t *auth_len); + +struct pkcs7_message *efi_parse_pkcs7_header(const void *buf, + size_t buflen, + u8 **tmpbuf); + +/* runtime implementation of memcpy() */ +void efi_memcpy_runtime(void *dest, const void *src, size_t n); + +/* commonly used helper function */ +u16 *efi_create_indexed_name(u16 *buffer, size_t buffer_size, const char *name, + unsigned int index); + +extern const struct efi_firmware_management_protocol efi_fmp_fit; +extern const struct efi_firmware_management_protocol efi_fmp_raw; + +/* Capsule update */ +efi_status_t EFIAPI efi_update_capsule( + struct efi_capsule_header **capsule_header_array, + efi_uintn_t capsule_count, + u64 scatter_gather_list); +efi_status_t EFIAPI efi_query_capsule_caps( + struct efi_capsule_header **capsule_header_array, + efi_uintn_t capsule_count, + u64 *maximum_capsule_size, + u32 *reset_type); + +efi_status_t efi_capsule_authenticate(const void *capsule, + efi_uintn_t capsule_size, + void **image, efi_uintn_t *image_size); + +#define EFI_CAPSULE_DIR L"\\EFI\\UpdateCapsule\\" + +/* Hook at initialization */ +efi_status_t efi_launch_capsules(void); + +#else /* CONFIG_IS_ENABLED(EFI_LOADER) */ + +/* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */ +#define __efi_runtime_data +#define __efi_runtime_rodata +#define __efi_runtime +static inline efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len) +{ + return EFI_SUCCESS; +} + +/* No loader configured, stub out EFI_ENTRY */ +static inline void efi_restore_gd(void) { } +static inline void efi_set_bootdev(const char *dev, const char *devnr, + const char *path, void *buffer, + size_t buffer_size) { } +static inline void efi_net_set_dhcp_ack(void *pkt, int len) { } +static inline void efi_print_image_infos(void *pc) { } +static inline efi_status_t efi_launch_capsules(void) +{ + return EFI_SUCCESS; +} + +#endif /* CONFIG_IS_ENABLED(EFI_LOADER) */ + +/** + * Install the ESRT system table. + * + * @return status code + */ +efi_status_t efi_esrt_register(void); + +/** + * efi_esrt_populate() - Populates the ESRT entries from the FMP instances + * present in the system. + * If an ESRT already exists, the old ESRT is replaced in the system table. + * The memory of the old ESRT is deallocated. + * + * Return: + * - EFI_SUCCESS if the ESRT is correctly created + * - error code otherwise. + */ +efi_status_t efi_esrt_populate(void); +efi_status_t efi_load_capsule_drivers(void); +#endif /* _EFI_LOADER_H */ diff --git a/roms/u-boot/include/efi_rng.h b/roms/u-boot/include/efi_rng.h new file mode 100644 index 000000000..35f59678c --- /dev/null +++ b/roms/u-boot/include/efi_rng.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019, Linaro Limited + */ + +#if !defined _EFI_RNG_H_ +#define _EFI_RNG_H_ + +#include +#include + +/* EFI random number generation protocol related GUID definitions */ +#define EFI_RNG_PROTOCOL_GUID \ + EFI_GUID(0x3152bca5, 0xeade, 0x433d, 0x86, 0x2e, \ + 0xc0, 0x1c, 0xdc, 0x29, 0x1f, 0x44) + +#define EFI_RNG_ALGORITHM_RAW \ + EFI_GUID(0xe43176d7, 0xb6e8, 0x4827, 0xb7, 0x84, \ + 0x7f, 0xfd, 0xc4, 0xb6, 0x85, 0x61) + +struct efi_rng_protocol { + efi_status_t (EFIAPI *get_info)(struct efi_rng_protocol *protocol, + efi_uintn_t *rng_algorithm_list_size, + efi_guid_t *rng_algorithm_list); + efi_status_t (EFIAPI *get_rng)(struct efi_rng_protocol *protocol, + efi_guid_t *rng_algorithm, + efi_uintn_t rng_value_length, uint8_t *rng_value); +}; + +efi_status_t platform_get_rng_device(struct udevice **dev); + +#endif /* _EFI_RNG_H_ */ diff --git a/roms/u-boot/include/efi_selftest.h b/roms/u-boot/include/efi_selftest.h new file mode 100644 index 000000000..94ceb1473 --- /dev/null +++ b/roms/u-boot/include/efi_selftest.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * EFI application loader + * + * Copyright (c) 2017 Heinrich Schuchardt + */ + +#ifndef _EFI_SELFTEST_H +#define _EFI_SELFTEST_H + +#include +#include +#include +#include +#include + +#define EFI_ST_SUCCESS 0 +#define EFI_ST_FAILURE 1 +#define EFI_ST_SUCCESS_STR L"SUCCESS" + +/** + * efi_st_printf() - print a message + * + * @...: format string followed by fields to print + */ +#define efi_st_printf(...) \ + (efi_st_printc(-1, __VA_ARGS__)) + +/** + * efi_st_error() - prints an error message + * + * @...: format string followed by fields to print + */ +#define efi_st_error(...) \ + (efi_st_printc(EFI_LIGHTRED, "%s(%u):\nERROR: ", __FILE__, __LINE__), \ + efi_st_printc(EFI_LIGHTRED, __VA_ARGS__)) + +/** + * efi_st_todo() - prints a TODO message + * + * @...: format string followed by fields to print + */ +#define efi_st_todo(...) \ + (efi_st_printc(EFI_YELLOW, "%s(%u):\nTODO: ", __FILE__, __LINE__), \ + efi_st_printc(EFI_YELLOW, __VA_ARGS__)) \ + +/** + * enum efi_test_phase - phase when test will be executed + * + * A test may be setup and executed at boottime, + * it may be setup at boottime and executed at runtime, + * or it may be setup and executed at runtime. + */ +enum efi_test_phase { + /** + * @EFI_EXECUTE_BEFORE_BOOTTIME_EXIT: + * + * Setup, execute, and teardown are executed before ExitBootServices(). + */ + EFI_EXECUTE_BEFORE_BOOTTIME_EXIT = 1, + /** + * @EFI_SETUP_BEFORE_BOOTTIME_EXIT: + * + * Setup is executed before ExitBootServices() while execute, and + * teardown are executed after ExitBootServices(). + */ + EFI_SETUP_BEFORE_BOOTTIME_EXIT, + /** + * @EFI_SETTING_VIRTUAL_ADDRESS_MAP: + * + * Execute calls SetVirtualAddressMap(). Setup is executed before + * ExitBootServices() while execute is executed after + * ExitBootServices(), and after the execute of tests marked as + * @EFI_SETUP_BEFORE_BOOTTIME_EXIT. Teardown is executed thereafter. + */ + EFI_SETTING_VIRTUAL_ADDRESS_MAP, +}; + +extern struct efi_simple_text_output_protocol *con_out; +extern struct efi_simple_text_input_protocol *con_in; + +/** + * efi_st_exit_boot_services() - exit the boot services + * + * * The size of the memory map is determined. + * * Pool memory is allocated to copy the memory map. + * * The memory map is copied and the map key is obtained. + * * The map key is used to exit the boot services. + */ +void efi_st_exit_boot_services(void); + +/** + * efi_st_printc() - print a colored message + * + * @color: color, see constants in efi_api.h, use -1 for no color + * @fmt: printf style format string + * @...: arguments to be printed + */ +void efi_st_printc(int color, const char *fmt, ...) + __attribute__ ((format (__printf__, 2, 3))); + +/** + * efi_st_translate_char() - translate a Unicode character to a string + * + * @code: Unicode character + * Return: string + */ +u16 *efi_st_translate_char(u16 code); + +/** + * efi_st_translate_code() - translate a scan code to a human readable string + * + * This function translates the scan code returned by the simple text input + * protocol to a human readable string, e.g. 0x04 is translated to L"Left". + * + * @code: scan code + * Return: Unicode string + */ +u16 *efi_st_translate_code(u16 code); + +/** + * efi_st_strcmp_16_8() - compare an u16 string to a char string + * + * This function compares each u16 value to the char value at the same + * position. This function is only useful for ANSI strings. + * + * @buf1: u16 string + * @buf2: char string + * Return: 0 if both buffers contain equivalent strings + */ +int efi_st_strcmp_16_8(const u16 *buf1, const char *buf2); + +/** + * efi_st_get_key() - reads an Unicode character from the input device + * + * Return: Unicode character + */ +u16 efi_st_get_key(void); + +/** + * struct efi_unit_test - EFI unit test + * + * The &struct efi_unit_test structure provides a interface to an EFI unit test. + * + * @name: name of the unit test used in the user interface + * @phase: specifies when setup and execute are executed + * @setup: set up function of the unit test + * @execute: execute function of the unit test + * @teardown: tear down function of the unit test + * @on_request: flag indicating that the test shall only be executed on request + */ +struct efi_unit_test { + const char *name; + const enum efi_test_phase phase; + int (*setup)(const efi_handle_t handle, + const struct efi_system_table *systable); + int (*execute)(void); + int (*teardown)(void); + bool on_request; +}; + +/** + * EFI_UNIT_TEST() - macro to declare a new EFI unit test + * + * The macro EFI_UNIT_TEST() declares an EFI unit test using the &struct + * efi_unit_test structure. The test is added to a linker generated list which + * is evaluated by the 'bootefi selftest' command. + * + * @__name: string identifying the unit test in the linker generated list + */ +#define EFI_UNIT_TEST(__name) \ + ll_entry_declare(struct efi_unit_test, __name, efi_unit_test) + +#endif /* _EFI_SELFTEST_H */ diff --git a/roms/u-boot/include/efi_tcg2.h b/roms/u-boot/include/efi_tcg2.h new file mode 100644 index 000000000..bcfb98168 --- /dev/null +++ b/roms/u-boot/include/efi_tcg2.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Defines data structures and APIs that allow an OS to interact with UEFI + * firmware to query information about the device + * + * Copyright (c) 2020, Linaro Limited + */ + +#if !defined _EFI_TCG2_PROTOCOL_H_ +#define _EFI_TCG2_PROTOCOL_H_ + +#include +#include + +#define EFI_TCG2_PROTOCOL_GUID \ + EFI_GUID(0x607f766c, 0x7455, 0x42be, 0x93, \ + 0x0b, 0xe4, 0xd7, 0x6d, 0xb2, 0x72, 0x0f) + +/* TPMV2 only */ +#define TCG2_EVENT_LOG_FORMAT_TCG_2 0x00000002 +#define EFI_TCG2_EXTEND_ONLY 0x0000000000000001 +#define PE_COFF_IMAGE 0x0000000000000010 + +/* Algorithm Registry */ +#define EFI_TCG2_BOOT_HASH_ALG_SHA1 0x00000001 +#define EFI_TCG2_BOOT_HASH_ALG_SHA256 0x00000002 +#define EFI_TCG2_BOOT_HASH_ALG_SHA384 0x00000004 +#define EFI_TCG2_BOOT_HASH_ALG_SHA512 0x00000008 +#define EFI_TCG2_BOOT_HASH_ALG_SM3_256 0x00000010 + +#define EFI_TCG2_FINAL_EVENTS_TABLE_VERSION 1 + +#define TPM2_EVENT_LOG_SIZE CONFIG_EFI_TCG2_PROTOCOL_EVENTLOG_SIZE + +typedef u32 efi_tcg_event_log_bitmap; +typedef u32 efi_tcg_event_log_format; +typedef u32 efi_tcg_event_algorithm_bitmap; + +struct efi_tcg2_version { + u8 major; + u8 minor; +}; + +struct efi_tcg2_event_header { + u32 header_size; + u16 header_version; + u32 pcr_index; + u32 event_type; +} __packed; + +struct efi_tcg2_event { + u32 size; + struct efi_tcg2_event_header header; + u8 event[]; +} __packed; + +struct uefi_image_load_event { + efi_physical_addr_t image_location_in_memory; + u64 image_length_in_memory; + u64 image_link_time_address; + u64 length_of_device_path; + struct efi_device_path device_path[]; +}; + +struct efi_tcg2_boot_service_capability { + u8 size; + struct efi_tcg2_version structure_version; + struct efi_tcg2_version protocol_version; + efi_tcg_event_algorithm_bitmap hash_algorithm_bitmap; + efi_tcg_event_log_bitmap supported_event_logs; + u8 tpm_present_flag; + u16 max_command_size; + u16 max_response_size; + u32 manufacturer_id; + u32 number_of_pcr_banks; + efi_tcg_event_algorithm_bitmap active_pcr_banks; +}; + +#define boot_service_capability_min \ + sizeof(struct efi_tcg2_boot_service_capability) - \ + offsetof(struct efi_tcg2_boot_service_capability, number_of_pcr_banks) + +#define TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03 "Spec ID Event03" +#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2 2 +#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 0 +#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2 2 + +/** + * struct TCG_EfiSpecIdEventAlgorithmSize + * + * @algorithm_id: algorithm defined in enum tpm2_algorithms + * @digest_size: size of the algorithm + */ +struct tcg_efi_spec_id_event_algorithm_size { + u16 algorithm_id; + u16 digest_size; +} __packed; + +/** + * struct TCG_EfiSpecIDEventStruct + * + * @signature: signature, set to Spec ID Event03 + * @platform_class: class defined in TCG ACPI Specification + * Client Common Header. + * @spec_version_minor: minor version + * @spec_version_major: major version + * @spec_version_errata: major version + * @uintn_size: size of the efi_uintn_t fields used in various + * data structures used in this specification. + * 0x01 indicates u32 and 0x02 indicates u64 + * @number_of_algorithms: hashing algorithms used in this event log + * @digest_sizes: array of number_of_algorithms pairs + * 1st member defines the algorithm id + * 2nd member defines the algorithm size + * @vendor_info_size: size in bytes for vendor specific info + * @vendor_info: vendor specific info + */ +struct tcg_efi_spec_id_event { + u8 signature[16]; + u32 platform_class; + u8 spec_version_minor; + u8 spec_version_major; + u8 spec_errata; + u8 uintn_size; + u32 number_of_algorithms; + struct tcg_efi_spec_id_event_algorithm_size digest_sizes[TPM2_NUM_PCR_BANKS]; + u8 vendor_info_size; + /* U-Boot does not provide any vendor info */ + u8 vendor_info[]; +} __packed; + +/** + * struct tdEFI_TCG2_FINAL_EVENTS_TABLE + * @version: version number for this structure + * @number_of_events: number of events recorded after invocation of + * GetEventLog() + * @event: List of events of type tcg_pcr_event2 + */ +struct efi_tcg2_final_events_table { + u64 version; + u64 number_of_events; + struct tcg_pcr_event2 event[]; +}; + +struct efi_tcg2_protocol { + efi_status_t (EFIAPI * get_capability)(struct efi_tcg2_protocol *this, + struct efi_tcg2_boot_service_capability *capability); + efi_status_t (EFIAPI * get_eventlog)(struct efi_tcg2_protocol *this, + efi_tcg_event_log_format log_format, + u64 *event_log_location, u64 *event_log_last_entry, + bool *event_log_truncated); + efi_status_t (EFIAPI * hash_log_extend_event)(struct efi_tcg2_protocol *this, + u64 flags, + efi_physical_addr_t data_to_hash, + u64 data_to_hash_len, + struct efi_tcg2_event *efi_tcg_event); + efi_status_t (EFIAPI * submit_command)(struct efi_tcg2_protocol *this, + u32 input_parameter_block_size, + u8 *input_parameter_block, + u32 output_parameter_block_size, + u8 *output_parameter_block); + efi_status_t (EFIAPI * get_active_pcr_banks)(struct efi_tcg2_protocol *this, + u32 *active_pcr_banks); + efi_status_t (EFIAPI * set_active_pcr_banks)(struct efi_tcg2_protocol *this, + u32 active_pcr_banks); + efi_status_t (EFIAPI * get_result_of_set_active_pcr_banks)(struct efi_tcg2_protocol *this, + u32 *operation_present, + u32 *response); +}; +#endif diff --git a/roms/u-boot/include/efi_variable.h b/roms/u-boot/include/efi_variable.h new file mode 100644 index 000000000..4623a6414 --- /dev/null +++ b/roms/u-boot/include/efi_variable.h @@ -0,0 +1,320 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2020, Heinrich Schuchardt + */ + +#ifndef _EFI_VARIABLE_H +#define _EFI_VARIABLE_H + +#include + +#define EFI_VARIABLE_READ_ONLY BIT(31) + +enum efi_auth_var_type { + EFI_AUTH_VAR_NONE = 0, + EFI_AUTH_VAR_PK, + EFI_AUTH_VAR_KEK, + EFI_AUTH_VAR_DB, + EFI_AUTH_VAR_DBX, + EFI_AUTH_VAR_DBT, + EFI_AUTH_VAR_DBR, +}; + +/** + * efi_get_variable() - retrieve value of a UEFI variable + * + * @variable_name: name of the variable + * @vendor: vendor GUID + * @attributes: attributes of the variable + * @data_size: size of the buffer to which the variable value is copied + * @data: buffer to which the variable value is copied + * @timep: authentication time (seconds since start of epoch) + * Return: status code + */ +efi_status_t efi_get_variable_int(u16 *variable_name, const efi_guid_t *vendor, + u32 *attributes, efi_uintn_t *data_size, + void *data, u64 *timep); + +/** + * efi_set_variable() - set value of a UEFI variable + * + * @variable_name: name of the variable + * @vendor: vendor GUID + * @attributes: attributes of the variable + * @data_size: size of the buffer with the variable value + * @data: buffer with the variable value + * @ro_check: check the read only read only bit in attributes + * Return: status code + */ +efi_status_t efi_set_variable_int(u16 *variable_name, const efi_guid_t *vendor, + u32 attributes, efi_uintn_t data_size, + const void *data, bool ro_check); + +/** + * efi_get_next_variable_name_int() - enumerate the current variable names + * + * @variable_name_size: size of variable_name buffer in byte + * @variable_name: name of uefi variable's name in u16 + * @vendor: vendor's guid + * + * See the Unified Extensible Firmware Interface (UEFI) specification for + * details. + * + * Return: status code + */ +efi_status_t efi_get_next_variable_name_int(efi_uintn_t *variable_name_size, + u16 *variable_name, + efi_guid_t *vendor); + +/** + * efi_query_variable_info_int() - get information about EFI variables + * + * This function implements the QueryVariableInfo() runtime service. + * + * See the Unified Extensible Firmware Interface (UEFI) specification for + * details. + * + * @attributes: bitmask to select variables to be + * queried + * @maximum_variable_storage_size: maximum size of storage area for the + * selected variable types + * @remaining_variable_storage_size: remaining size of storage are for the + * selected variable types + * @maximum_variable_size: maximum size of a variable of the + * selected type + * Returns: status code + */ +efi_status_t efi_query_variable_info_int(u32 attributes, + u64 *maximum_variable_storage_size, + u64 *remaining_variable_storage_size, + u64 *maximum_variable_size); + +#define EFI_VAR_FILE_NAME "ubootefi.var" + +#define EFI_VAR_BUF_SIZE CONFIG_EFI_VAR_BUF_SIZE + +/* + * This constant identifies the file format for storing UEFI variables in + * struct efi_var_file. + */ +#define EFI_VAR_FILE_MAGIC 0x0161566966456255 /* UbEfiVa, version 1 */ + +/** + * struct efi_var_entry - UEFI variable file entry + * + * @length: length of enty, multiple of 8 + * @attr: variable attributes + * @time: authentication time (seconds since start of epoch) + * @guid: vendor GUID + * @name: UTF16 variable name + */ +struct efi_var_entry { + u32 length; + u32 attr; + u64 time; + efi_guid_t guid; + u16 name[]; +}; + +/** + * struct efi_var_file - file for storing UEFI variables + * + * @reserved: unused, may be overwritten by memory probing + * @magic: identifies file format, takes value %EFI_VAR_FILE_MAGIC + * @length: length including header + * @crc32: CRC32 without header + * @var: variables + */ +struct efi_var_file { + u64 reserved; + u64 magic; + u32 length; + u32 crc32; + struct efi_var_entry var[]; +}; + +/** + * efi_var_to_file() - save non-volatile variables as file + * + * File ubootefi.var is created on the EFI system partion. + * + * Return: status code + */ +efi_status_t efi_var_to_file(void); + +/** + * efi_var_collect() - collect variables in buffer + * + * A buffer is allocated and filled with variables in a format ready to be + * written to disk. + * + * @bufp: pointer to pointer of buffer with collected variables + * @lenp: pointer to length of buffer + * @check_attr_mask: bitmask with required attributes of variables to be collected. + * variables are only collected if all of the required + * attributes are set. + * Return: status code + */ +efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t *lenp, + u32 check_attr_mask); + +/** + * efi_var_restore() - restore EFI variables from buffer + * + * @buf: buffer + * Return: status code + */ +efi_status_t efi_var_restore(struct efi_var_file *buf); + +/** + * efi_var_from_file() - read variables from file + * + * File ubootefi.var is read from the EFI system partitions and the variables + * stored in the file are created. + * + * In case the file does not exist yet or a variable cannot be set EFI_SUCCESS + * is returned. + * + * Return: status code + */ +efi_status_t efi_var_from_file(void); + +/** + * efi_var_mem_init() - set-up variable list + * + * Return: status code + */ +efi_status_t efi_var_mem_init(void); + +/** + * efi_var_mem_find() - find a variable in the list + * + * @guid: GUID of the variable + * @name: name of the variable + * @next: on exit pointer to the next variable after the found one + * Return: found variable + */ +struct efi_var_entry *efi_var_mem_find(const efi_guid_t *guid, const u16 *name, + struct efi_var_entry **next); + +/** + * efi_var_mem_del() - delete a variable from the list of variables + * + * @var: variable to delete + */ +void efi_var_mem_del(struct efi_var_entry *var); + +/** + * efi_var_mem_ins() - append a variable to the list of variables + * + * The variable is appended without checking if a variable of the same name + * already exists. The two data buffers are concatenated. + * + * @variable_name: variable name + * @vendor: GUID + * @attributes: variable attributes + * @size1: size of the first data buffer + * @data1: first data buffer + * @size2: size of the second data field + * @data2: second data buffer + * @time: time of authentication (as seconds since start of epoch) + * Result: status code + */ +efi_status_t efi_var_mem_ins(u16 *variable_name, + const efi_guid_t *vendor, u32 attributes, + const efi_uintn_t size1, const void *data1, + const efi_uintn_t size2, const void *data2, + const u64 time); + +/** + * efi_var_mem_free() - determine free memory for variables + * + * Return: maximum data size plus variable name size + */ +u64 efi_var_mem_free(void); + +/** + * efi_init_secure_state - initialize secure boot state + * + * Return: status code + */ +efi_status_t efi_init_secure_state(void); + +/** + * efi_auth_var_get_type() - convert variable name and guid to enum + * + * @name: name of UEFI variable + * @guid: guid of UEFI variable + * Return: identifier for authentication related variables + */ +enum efi_auth_var_type efi_auth_var_get_type(u16 *name, const efi_guid_t *guid); + +/** + * efi_get_next_variable_name_mem() - Runtime common code across efi variable + * implementations for GetNextVariable() + * from the cached memory copy + * @variable_name_size: size of variable_name buffer in byte + * @variable_name: name of uefi variable's name in u16 + * @vendor: vendor's guid + * + * Return: status code + */ +efi_status_t __efi_runtime +efi_get_next_variable_name_mem(efi_uintn_t *variable_name_size, u16 *variable_name, + efi_guid_t *vendor); +/** + * efi_get_variable_mem() - Runtime common code across efi variable + * implementations for GetVariable() from + * the cached memory copy + * + * @variable_name: name of the variable + * @vendor: vendor GUID + * @attributes: attributes of the variable + * @data_size: size of the buffer to which the variable value is copied + * @data: buffer to which the variable value is copied + * @timep: authentication time (seconds since start of epoch) + * Return: status code + */ +efi_status_t __efi_runtime +efi_get_variable_mem(u16 *variable_name, const efi_guid_t *vendor, u32 *attributes, + efi_uintn_t *data_size, void *data, u64 *timep); + +/** + * efi_get_variable_runtime() - runtime implementation of GetVariable() + * + * @variable_name: name of the variable + * @guid: vendor GUID + * @attributes: attributes of the variable + * @data_size: size of the buffer to which the variable value is copied + * @data: buffer to which the variable value is copied + * Return: status code + */ +efi_status_t __efi_runtime EFIAPI +efi_get_variable_runtime(u16 *variable_name, const efi_guid_t *guid, + u32 *attributes, efi_uintn_t *data_size, void *data); + +/** + * efi_get_next_variable_name_runtime() - runtime implementation of + * GetNextVariable() + * + * @variable_name_size: size of variable_name buffer in byte + * @variable_name: name of uefi variable's name in u16 + * @guid: vendor's guid + * Return: status code + */ +efi_status_t __efi_runtime EFIAPI +efi_get_next_variable_name_runtime(efi_uintn_t *variable_name_size, + u16 *variable_name, efi_guid_t *guid); + +/** + * efi_var_buf_update() - udpate memory buffer for variables + * + * @var_buf: source buffer + * + * This function copies to the memory buffer for UEFI variables. Call this + * function in ExitBootServices() if memory backed variables are only used + * at runtime to fill the buffer. + */ +void efi_var_buf_update(struct efi_var_file *var_buf); + +#endif diff --git a/roms/u-boot/include/elf.h b/roms/u-boot/include/elf.h new file mode 100644 index 000000000..b04e746d6 --- /dev/null +++ b/roms/u-boot/include/elf.h @@ -0,0 +1,701 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 1995, 1996, 2001, 2002 + * Erik Theisen. All rights reserved. + */ + +/* This is the ELF ABI header file formerly known as "elf_abi.h" */ + +#ifndef _ELF_H +#define _ELF_H + +#ifndef __ASSEMBLY__ +#include "compiler.h" + +/* This version doesn't work for 64-bit ABIs - Erik */ + +/* These typedefs need to be handled better */ +typedef uint32_t Elf32_Addr; /* Unsigned program address */ +typedef uint32_t Elf32_Off; /* Unsigned file offset */ +typedef int32_t Elf32_Sword; /* Signed large integer */ +typedef uint32_t Elf32_Word; /* Unsigned large integer */ +typedef uint16_t Elf32_Half; /* Unsigned medium integer */ + +/* 64-bit ELF base types */ +typedef uint64_t Elf64_Addr; +typedef uint16_t Elf64_Half; +typedef int16_t Elf64_SHalf; +typedef uint64_t Elf64_Off; +typedef int32_t Elf64_Sword; +typedef uint32_t Elf64_Word; +typedef uint64_t Elf64_Xword; +typedef int64_t Elf64_Sxword; + +/* e_ident[] identification indexes */ +#define EI_MAG0 0 /* file ID */ +#define EI_MAG1 1 /* file ID */ +#define EI_MAG2 2 /* file ID */ +#define EI_MAG3 3 /* file ID */ +#define EI_CLASS 4 /* file class */ +#define EI_DATA 5 /* data encoding */ +#define EI_VERSION 6 /* ELF header version */ +#define EI_OSABI 7 /* OS/ABI specific ELF extensions */ +#define EI_ABIVERSION 8 /* ABI target version */ +#define EI_PAD 9 /* start of pad bytes */ +#define EI_NIDENT 16 /* Size of e_ident[] */ + +/* e_ident[] magic number */ +#define ELFMAG0 0x7f /* e_ident[EI_MAG0] */ +#define ELFMAG1 'E' /* e_ident[EI_MAG1] */ +#define ELFMAG2 'L' /* e_ident[EI_MAG2] */ +#define ELFMAG3 'F' /* e_ident[EI_MAG3] */ +#define ELFMAG "\177ELF" /* magic */ +#define SELFMAG 4 /* size of magic */ + +/* e_ident[] file class */ +#define ELFCLASSNONE 0 /* invalid */ +#define ELFCLASS32 1 /* 32-bit objs */ +#define ELFCLASS64 2 /* 64-bit objs */ +#define ELFCLASSNUM 3 /* number of classes */ + +/* e_ident[] data encoding */ +#define ELFDATANONE 0 /* invalid */ +#define ELFDATA2LSB 1 /* Little-Endian */ +#define ELFDATA2MSB 2 /* Big-Endian */ +#define ELFDATANUM 3 /* number of data encode defines */ + +/* e_ident[] OS/ABI specific ELF extensions */ +#define ELFOSABI_NONE 0 /* No extension specified */ +#define ELFOSABI_HPUX 1 /* Hewlett-Packard HP-UX */ +#define ELFOSABI_NETBSD 2 /* NetBSD */ +#define ELFOSABI_LINUX 3 /* Linux */ +#define ELFOSABI_SOLARIS 6 /* Sun Solaris */ +#define ELFOSABI_AIX 7 /* AIX */ +#define ELFOSABI_IRIX 8 /* IRIX */ +#define ELFOSABI_FREEBSD 9 /* FreeBSD */ +#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX */ +#define ELFOSABI_MODESTO 11 /* Novell Modesto */ +#define ELFOSABI_OPENBSD 12 /* OpenBSD */ +/* 64-255 Architecture-specific value range */ + +/* e_ident[] ABI Version */ +#define ELFABIVERSION 0 + +/* e_ident */ +#define IS_ELF(ehdr) ((ehdr).e_ident[EI_MAG0] == ELFMAG0 && \ + (ehdr).e_ident[EI_MAG1] == ELFMAG1 && \ + (ehdr).e_ident[EI_MAG2] == ELFMAG2 && \ + (ehdr).e_ident[EI_MAG3] == ELFMAG3) + +/* ELF Header */ +typedef struct { + unsigned char e_ident[EI_NIDENT]; /* ELF Identification */ + Elf32_Half e_type; /* object file type */ + Elf32_Half e_machine; /* machine */ + Elf32_Word e_version; /* object file version */ + Elf32_Addr e_entry; /* virtual entry point */ + Elf32_Off e_phoff; /* program header table offset */ + Elf32_Off e_shoff; /* section header table offset */ + Elf32_Word e_flags; /* processor-specific flags */ + Elf32_Half e_ehsize; /* ELF header size */ + Elf32_Half e_phentsize; /* program header entry size */ + Elf32_Half e_phnum; /* number of program header entries */ + Elf32_Half e_shentsize; /* section header entry size */ + Elf32_Half e_shnum; /* number of section header entries */ + Elf32_Half e_shstrndx; /* section header table's "section + header string table" entry offset */ +} Elf32_Ehdr; + +typedef struct { + unsigned char e_ident[EI_NIDENT]; /* ELF Identification */ + Elf64_Half e_type; /* object file type */ + Elf64_Half e_machine; /* machine */ + Elf64_Word e_version; /* object file version */ + Elf64_Addr e_entry; /* virtual entry point */ + Elf64_Off e_phoff; /* program header table offset */ + Elf64_Off e_shoff; /* section header table offset */ + Elf64_Word e_flags; /* processor-specific flags */ + Elf64_Half e_ehsize; /* ELF header size */ + Elf64_Half e_phentsize; /* program header entry size */ + Elf64_Half e_phnum; /* number of program header entries */ + Elf64_Half e_shentsize; /* section header entry size */ + Elf64_Half e_shnum; /* number of section header entries */ + Elf64_Half e_shstrndx; /* section header table's "section + header string table" entry offset */ +} Elf64_Ehdr; + +/* e_type */ +#define ET_NONE 0 /* No file type */ +#define ET_REL 1 /* relocatable file */ +#define ET_EXEC 2 /* executable file */ +#define ET_DYN 3 /* shared object file */ +#define ET_CORE 4 /* core file */ +#define ET_NUM 5 /* number of types */ +#define ET_LOOS 0xfe00 /* reserved range for operating */ +#define ET_HIOS 0xfeff /* system specific e_type */ +#define ET_LOPROC 0xff00 /* reserved range for processor */ +#define ET_HIPROC 0xffff /* specific e_type */ + +/* e_machine */ +#define EM_NONE 0 /* No Machine */ +#define EM_M32 1 /* AT&T WE 32100 */ +#define EM_SPARC 2 /* SPARC */ +#define EM_386 3 /* Intel 80386 */ +#define EM_68K 4 /* Motorola 68000 */ +#define EM_88K 5 /* Motorola 88000 */ +#if 0 +#define EM_486 6 /* RESERVED - was Intel 80486 */ +#endif +#define EM_860 7 /* Intel 80860 */ +#define EM_MIPS 8 /* MIPS R3000 Big-Endian only */ +#define EM_S370 9 /* IBM System/370 Processor */ +#define EM_MIPS_RS4_BE 10 /* MIPS R4000 Big-Endian */ +#if 0 +#define EM_SPARC64 11 /* RESERVED - was SPARC v9 + 64-bit unoffical */ +#endif +/* RESERVED 11-14 for future use */ +#define EM_PARISC 15 /* HPPA */ +/* RESERVED 16 for future use */ +#define EM_VPP500 17 /* Fujitsu VPP500 */ +#define EM_SPARC32PLUS 18 /* Enhanced instruction set SPARC */ +#define EM_960 19 /* Intel 80960 */ +#define EM_PPC 20 /* PowerPC */ +#define EM_PPC64 21 /* 64-bit PowerPC */ +#define EM_S390 22 /* IBM System/390 Processor */ +/* RESERVED 23-35 for future use */ +#define EM_V800 36 /* NEC V800 */ +#define EM_FR20 37 /* Fujitsu FR20 */ +#define EM_RH32 38 /* TRW RH-32 */ +#define EM_RCE 39 /* Motorola RCE */ +#define EM_ARM 40 /* Advanced Risc Machines ARM */ +#define EM_ALPHA 41 /* Digital Alpha */ +#define EM_SH 42 /* Hitachi SH */ +#define EM_SPARCV9 43 /* SPARC Version 9 */ +#define EM_TRICORE 44 /* Siemens TriCore embedded processor */ +#define EM_ARC 45 /* Argonaut RISC Core */ +#define EM_H8_300 46 /* Hitachi H8/300 */ +#define EM_H8_300H 47 /* Hitachi H8/300H */ +#define EM_H8S 48 /* Hitachi H8S */ +#define EM_H8_500 49 /* Hitachi H8/500 */ +#define EM_IA_64 50 /* Intel Merced */ +#define EM_MIPS_X 51 /* Stanford MIPS-X */ +#define EM_COLDFIRE 52 /* Motorola Coldfire */ +#define EM_68HC12 53 /* Motorola M68HC12 */ +#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ +#define EM_PCP 55 /* Siemens PCP */ +#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ +#define EM_NDR1 57 /* Denso NDR1 microprocessor */ +#define EM_STARCORE 58 /* Motorola Start*Core processor */ +#define EM_ME16 59 /* Toyota ME16 processor */ +#define EM_ST100 60 /* STMicroelectronic ST100 processor */ +#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ +#define EM_X86_64 62 /* AMD x86-64 */ +#define EM_PDSP 63 /* Sony DSP Processor */ +/* RESERVED 64,65 for future use */ +#define EM_FX66 66 /* Siemens FX66 microcontroller */ +#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ +#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ +#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ +#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ +#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ +#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ +#define EM_SVX 73 /* Silicon Graphics SVx */ +#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ +#define EM_VAX 75 /* Digital VAX */ +#define EM_CHRIS 76 /* Axis Communications embedded proc. */ +#define EM_JAVELIN 77 /* Infineon Technologies emb. proc. */ +#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ +#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ +#define EM_MMIX 80 /* Donald Knuth's edu 64-bit proc. */ +#define EM_HUANY 81 /* Harvard University mach-indep objs */ +#define EM_PRISM 82 /* SiTera Prism */ +#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ +#define EM_FR30 84 /* Fujitsu FR30 */ +#define EM_D10V 85 /* Mitsubishi DV10V */ +#define EM_D30V 86 /* Mitsubishi DV30V */ +#define EM_V850 87 /* NEC v850 */ +#define EM_M32R 88 /* Mitsubishi M32R */ +#define EM_MN10300 89 /* Matsushita MN10200 */ +#define EM_MN10200 90 /* Matsushita MN10200 */ +#define EM_PJ 91 /* picoJava */ +#define EM_NUM 92 /* number of machine types */ + +/* Version */ +#define EV_NONE 0 /* Invalid */ +#define EV_CURRENT 1 /* Current */ +#define EV_NUM 2 /* number of versions */ + +/* Section Header */ +typedef struct { + Elf32_Word sh_name; /* name - index into section header + string table section */ + Elf32_Word sh_type; /* type */ + Elf32_Word sh_flags; /* flags */ + Elf32_Addr sh_addr; /* address */ + Elf32_Off sh_offset; /* file offset */ + Elf32_Word sh_size; /* section size */ + Elf32_Word sh_link; /* section header table index link */ + Elf32_Word sh_info; /* extra information */ + Elf32_Word sh_addralign; /* address alignment */ + Elf32_Word sh_entsize; /* section entry size */ +} Elf32_Shdr; + +typedef struct { + Elf64_Word sh_name; /* name - index into section header + string table section */ + Elf64_Word sh_type; /* type */ + Elf64_Xword sh_flags; /* flags */ + Elf64_Addr sh_addr; /* address */ + Elf64_Off sh_offset; /* file offset */ + Elf64_Xword sh_size; /* section size */ + Elf64_Word sh_link; /* section header table index link */ + Elf64_Word sh_info; /* extra information */ + Elf64_Xword sh_addralign; /* address alignment */ + Elf64_Xword sh_entsize; /* section entry size */ +} Elf64_Shdr; + +/* Special Section Indexes */ +#define SHN_UNDEF 0 /* undefined */ +#define SHN_LORESERVE 0xff00 /* lower bounds of reserved indexes */ +#define SHN_LOPROC 0xff00 /* reserved range for processor */ +#define SHN_HIPROC 0xff1f /* specific section indexes */ +#define SHN_LOOS 0xff20 /* reserved range for operating */ +#define SHN_HIOS 0xff3f /* specific semantics */ +#define SHN_ABS 0xfff1 /* absolute value */ +#define SHN_COMMON 0xfff2 /* common symbol */ +#define SHN_XINDEX 0xffff /* Index is an extra table */ +#define SHN_HIRESERVE 0xffff /* upper bounds of reserved indexes */ + +/* sh_type */ +#define SHT_NULL 0 /* inactive */ +#define SHT_PROGBITS 1 /* program defined information */ +#define SHT_SYMTAB 2 /* symbol table section */ +#define SHT_STRTAB 3 /* string table section */ +#define SHT_RELA 4 /* relocation section with addends*/ +#define SHT_HASH 5 /* symbol hash table section */ +#define SHT_DYNAMIC 6 /* dynamic section */ +#define SHT_NOTE 7 /* note section */ +#define SHT_NOBITS 8 /* no space section */ +#define SHT_REL 9 /* relation section without addends */ +#define SHT_SHLIB 10 /* reserved - purpose unknown */ +#define SHT_DYNSYM 11 /* dynamic symbol table section */ +#define SHT_INIT_ARRAY 14 /* Array of constructors */ +#define SHT_FINI_ARRAY 15 /* Array of destructors */ +#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ +#define SHT_GROUP 17 /* Section group */ +#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ +#define SHT_NUM 19 /* number of section types */ +#define SHT_LOOS 0x60000000 /* Start OS-specific */ +#define SHT_HIOS 0x6fffffff /* End OS-specific */ +#define SHT_LOPROC 0x70000000 /* reserved range for processor */ +#define SHT_HIPROC 0x7fffffff /* specific section header types */ +#define SHT_LOUSER 0x80000000 /* reserved range for application */ +#define SHT_HIUSER 0xffffffff /* specific indexes */ + +/* Section names */ +#define ELF_BSS ".bss" /* uninitialized data */ +#define ELF_COMMENT ".comment" /* version control information */ +#define ELF_DATA ".data" /* initialized data */ +#define ELF_DATA1 ".data1" /* initialized data */ +#define ELF_DEBUG ".debug" /* debug */ +#define ELF_DYNAMIC ".dynamic" /* dynamic linking information */ +#define ELF_DYNSTR ".dynstr" /* dynamic string table */ +#define ELF_DYNSYM ".dynsym" /* dynamic symbol table */ +#define ELF_FINI ".fini" /* termination code */ +#define ELF_FINI_ARRAY ".fini_array" /* Array of destructors */ +#define ELF_GOT ".got" /* global offset table */ +#define ELF_HASH ".hash" /* symbol hash table */ +#define ELF_INIT ".init" /* initialization code */ +#define ELF_INIT_ARRAY ".init_array" /* Array of constuctors */ +#define ELF_INTERP ".interp" /* Pathname of program interpreter */ +#define ELF_LINE ".line" /* Symbolic line numnber information */ +#define ELF_NOTE ".note" /* Contains note section */ +#define ELF_PLT ".plt" /* Procedure linkage table */ +#define ELF_PREINIT_ARRAY ".preinit_array" /* Array of pre-constructors */ +#define ELF_REL_DATA ".rel.data" /* relocation data */ +#define ELF_REL_FINI ".rel.fini" /* relocation termination code */ +#define ELF_REL_INIT ".rel.init" /* relocation initialization code */ +#define ELF_REL_DYN ".rel.dyn" /* relocaltion dynamic link info */ +#define ELF_REL_RODATA ".rel.rodata" /* relocation read-only data */ +#define ELF_REL_TEXT ".rel.text" /* relocation code */ +#define ELF_RODATA ".rodata" /* read-only data */ +#define ELF_RODATA1 ".rodata1" /* read-only data */ +#define ELF_SHSTRTAB ".shstrtab" /* section header string table */ +#define ELF_STRTAB ".strtab" /* string table */ +#define ELF_SYMTAB ".symtab" /* symbol table */ +#define ELF_SYMTAB_SHNDX ".symtab_shndx"/* symbol table section index */ +#define ELF_TBSS ".tbss" /* thread local uninit data */ +#define ELF_TDATA ".tdata" /* thread local init data */ +#define ELF_TDATA1 ".tdata1" /* thread local init data */ +#define ELF_TEXT ".text" /* code */ + +/* Section Attribute Flags - sh_flags */ +#define SHF_WRITE 0x1 /* Writable */ +#define SHF_ALLOC 0x2 /* occupies memory */ +#define SHF_EXECINSTR 0x4 /* executable */ +#define SHF_MERGE 0x10 /* Might be merged */ +#define SHF_STRINGS 0x20 /* Contains NULL terminated strings */ +#define SHF_INFO_LINK 0x40 /* sh_info contains SHT index */ +#define SHF_LINK_ORDER 0x80 /* Preserve order after combining*/ +#define SHF_OS_NONCONFORMING 0x100 /* Non-standard OS specific handling */ +#define SHF_GROUP 0x200 /* Member of section group */ +#define SHF_TLS 0x400 /* Thread local storage */ +#define SHF_MASKOS 0x0ff00000 /* OS specific */ +#define SHF_MASKPROC 0xf0000000 /* reserved bits for processor */ + /* specific section attributes */ + +/* Section Group Flags */ +#define GRP_COMDAT 0x1 /* COMDAT group */ +#define GRP_MASKOS 0x0ff00000 /* Mask OS specific flags */ +#define GRP_MASKPROC 0xf0000000 /* Mask processor specific flags */ + +/* Symbol Table Entry */ +typedef struct { + Elf32_Word st_name; /* name - index into string table */ + Elf32_Addr st_value; /* symbol value */ + Elf32_Word st_size; /* symbol size */ + unsigned char st_info; /* type and binding */ + unsigned char st_other; /* 0 - no defined meaning */ + Elf32_Half st_shndx; /* section header index */ +} Elf32_Sym; + +/* Symbol table index */ +#define STN_UNDEF 0 /* undefined */ + +/* Extract symbol info - st_info */ +#define ELF32_ST_BIND(x) ((x) >> 4) +#define ELF32_ST_TYPE(x) (((unsigned int) x) & 0xf) +#define ELF32_ST_INFO(b,t) (((b) << 4) + ((t) & 0xf)) +#define ELF32_ST_VISIBILITY(x) ((x) & 0x3) + +/* Symbol Binding - ELF32_ST_BIND - st_info */ +#define STB_LOCAL 0 /* Local symbol */ +#define STB_GLOBAL 1 /* Global symbol */ +#define STB_WEAK 2 /* like global - lower precedence */ +#define STB_NUM 3 /* number of symbol bindings */ +#define STB_LOOS 10 /* reserved range for operating */ +#define STB_HIOS 12 /* system specific symbol bindings */ +#define STB_LOPROC 13 /* reserved range for processor */ +#define STB_HIPROC 15 /* specific symbol bindings */ + +/* Symbol type - ELF32_ST_TYPE - st_info */ +#define STT_NOTYPE 0 /* not specified */ +#define STT_OBJECT 1 /* data object */ +#define STT_FUNC 2 /* function */ +#define STT_SECTION 3 /* section */ +#define STT_FILE 4 /* file */ +#define STT_NUM 5 /* number of symbol types */ +#define STT_TLS 6 /* Thread local storage symbol */ +#define STT_LOOS 10 /* reserved range for operating */ +#define STT_HIOS 12 /* system specific symbol types */ +#define STT_LOPROC 13 /* reserved range for processor */ +#define STT_HIPROC 15 /* specific symbol types */ + +/* Symbol visibility - ELF32_ST_VISIBILITY - st_other */ +#define STV_DEFAULT 0 /* Normal visibility rules */ +#define STV_INTERNAL 1 /* Processor specific hidden class */ +#define STV_HIDDEN 2 /* Symbol unavailable in other mods */ +#define STV_PROTECTED 3 /* Not preemptible, not exported */ + +/* Relocation entry with implicit addend */ +typedef struct { + Elf32_Addr r_offset; /* offset of relocation */ + Elf32_Word r_info; /* symbol table index and type */ +} Elf32_Rel; + +/* Relocation entry with explicit addend */ +typedef struct { + Elf32_Addr r_offset; /* offset of relocation */ + Elf32_Word r_info; /* symbol table index and type */ + Elf32_Sword r_addend; +} Elf32_Rela; + +typedef struct { + Elf64_Addr r_offset; /* Location at which to apply the action */ + Elf64_Xword r_info; /* index and type of relocation */ +} Elf64_Rel; + +typedef struct { + Elf64_Addr r_offset; /* Location at which to apply the action */ + Elf64_Xword r_info; /* index and type of relocation */ + Elf64_Sxword r_addend; /* Constant addend used to compute value */ +} Elf64_Rela; + +/* Extract relocation info - r_info */ +#define ELF32_R_SYM(i) ((i) >> 8) +#define ELF32_R_TYPE(i) ((unsigned char) (i)) +#define ELF32_R_INFO(s,t) (((s) << 8) + (unsigned char)(t)) + +/* Program Header */ +typedef struct { + Elf32_Word p_type; /* segment type */ + Elf32_Off p_offset; /* segment offset */ + Elf32_Addr p_vaddr; /* virtual address of segment */ + Elf32_Addr p_paddr; /* physical address of segment */ + Elf32_Word p_filesz; /* number of bytes in file for seg */ + Elf32_Word p_memsz; /* number of bytes in mem. for seg */ + Elf32_Word p_flags; /* flags */ + Elf32_Word p_align; /* memory alignment */ +} Elf32_Phdr; + +typedef struct { + Elf64_Word p_type; /* segment type */ + Elf64_Word p_flags; /* flags */ + Elf64_Off p_offset; /* segment offset */ + Elf64_Addr p_vaddr; /* virtual address of segment */ + Elf64_Addr p_paddr; /* physical address of segment */ + Elf64_Xword p_filesz; /* number of bytes in file for seg */ + Elf64_Xword p_memsz; /* number of bytes in mem. for seg */ + Elf64_Xword p_align; /* memory alignment */ +} Elf64_Phdr; + +/* Segment types - p_type */ +#define PT_NULL 0 /* unused */ +#define PT_LOAD 1 /* loadable segment */ +#define PT_DYNAMIC 2 /* dynamic linking section */ +#define PT_INTERP 3 /* the RTLD */ +#define PT_NOTE 4 /* auxiliary information */ +#define PT_SHLIB 5 /* reserved - purpose undefined */ +#define PT_PHDR 6 /* program header */ +#define PT_TLS 7 /* Thread local storage template */ +#define PT_NUM 8 /* Number of segment types */ +#define PT_LOOS 0x60000000 /* reserved range for operating */ +#define PT_HIOS 0x6fffffff /* system specific segment types */ +#define PT_LOPROC 0x70000000 /* reserved range for processor */ +#define PT_HIPROC 0x7fffffff /* specific segment types */ + +/* Segment flags - p_flags */ +#define PF_X 0x1 /* Executable */ +#define PF_W 0x2 /* Writable */ +#define PF_R 0x4 /* Readable */ +#define PF_MASKOS 0x0ff00000 /* OS specific segment flags */ +#define PF_MASKPROC 0xf0000000 /* reserved bits for processor */ + /* specific segment flags */ +/* Dynamic structure */ +typedef struct { + Elf32_Sword d_tag; /* controls meaning of d_val */ + union { + Elf32_Word d_val; /* Multiple meanings - see d_tag */ + Elf32_Addr d_ptr; /* program virtual address */ + } d_un; +} Elf32_Dyn; + +extern Elf32_Dyn _DYNAMIC[]; + +typedef struct { + Elf64_Sxword d_tag; /* entry tag value */ + union { + Elf64_Xword d_val; + Elf64_Addr d_ptr; + } d_un; +} Elf64_Dyn; + +#define ELF64_R_SYM(i) ((i) >> 32) +#define ELF64_R_TYPE(i) ((i) & 0xffffffff) + +/* Dynamic Array Tags - d_tag */ +#define DT_NULL 0 /* marks end of _DYNAMIC array */ +#define DT_NEEDED 1 /* string table offset of needed lib */ +#define DT_PLTRELSZ 2 /* size of relocation entries in PLT */ +#define DT_PLTGOT 3 /* address PLT/GOT */ +#define DT_HASH 4 /* address of symbol hash table */ +#define DT_STRTAB 5 /* address of string table */ +#define DT_SYMTAB 6 /* address of symbol table */ +#define DT_RELA 7 /* address of relocation table */ +#define DT_RELASZ 8 /* size of relocation table */ +#define DT_RELAENT 9 /* size of relocation entry */ +#define DT_STRSZ 10 /* size of string table */ +#define DT_SYMENT 11 /* size of symbol table entry */ +#define DT_INIT 12 /* address of initialization func */ +#define DT_FINI 13 /* address of termination function */ +#define DT_SONAME 14 /* string table offset of shared obj */ +#define DT_RPATH 15 /* string table offset of library + search path */ +#define DT_SYMBOLIC 16 /* start sym search in shared obj */ +#define DT_REL 17 /* address of rel. tbl. w addends */ +#define DT_RELSZ 18 /* size of DT_REL relocation table */ +#define DT_RELENT 19 /* size of DT_REL relocation entry */ +#define DT_PLTREL 20 /* PLT referenced relocation entry */ +#define DT_DEBUG 21 /* bugger */ +#define DT_TEXTREL 22 /* Allow rel. mod. to unwritable seg */ +#define DT_JMPREL 23 /* add. of PLT's relocation entries */ +#define DT_BIND_NOW 24 /* Process relocations of object */ +#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ +#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ +#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ +#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ +#define DT_RUNPATH 29 /* Library search path */ +#define DT_FLAGS 30 /* Flags for the object being loaded */ +#define DT_ENCODING 32 /* Start of encoded range */ +#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ +#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ +#define DT_NUM 34 /* Number used */ +#define DT_LOOS 0x60000000 /* reserved range for OS */ +#define DT_HIOS 0x6fffffff /* specific dynamic array tags */ +#define DT_LOPROC 0x70000000 /* reserved range for processor */ +#define DT_HIPROC 0x7fffffff /* specific dynamic array tags */ + +/* Dynamic Tag Flags - d_un.d_val */ +#define DF_ORIGIN 0x01 /* Object may use DF_ORIGIN */ +#define DF_SYMBOLIC 0x02 /* Symbol resolutions starts here */ +#define DF_TEXTREL 0x04 /* Object contains text relocations */ +#define DF_BIND_NOW 0x08 /* No lazy binding for this object */ +#define DF_STATIC_TLS 0x10 /* Static thread local storage */ + +/* Standard ELF hashing function */ +unsigned long elf_hash(const unsigned char *name); + +#define ELF_TARG_VER 1 /* The ver for which this code is intended */ + +#endif /* __ASSEMBLER */ + +/* ELF register definitions */ +#define R_386_NONE 0 +#define R_386_32 1 +#define R_386_PC32 2 +#define R_386_GOT32 3 +#define R_386_PLT32 4 +#define R_386_COPY 5 +#define R_386_GLOB_DAT 6 +#define R_386_JMP_SLOT 7 +#define R_386_RELATIVE 8 +#define R_386_GOTOFF 9 +#define R_386_GOTPC 10 +#define R_386_NUM 11 + +/* x86-64 relocation types */ +#define R_X86_64_NONE 0 /* No reloc */ +#define R_X86_64_64 1 /* Direct 64 bit */ +#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ +#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ +#define R_X86_64_PLT32 4 /* 32 bit PLT address */ +#define R_X86_64_COPY 5 /* Copy symbol at runtime */ +#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ +#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ +#define R_X86_64_RELATIVE 8 /* Adjust by program base */ +/* 32 bit signed pc relative offset to GOT */ +#define R_X86_64_GOTPCREL 9 +#define R_X86_64_32 10 /* Direct 32 bit zero extended */ +#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ +#define R_X86_64_16 12 /* Direct 16 bit zero extended */ +#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ +#define R_X86_64_8 14 /* Direct 8 bit sign extended */ +#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ + +#define R_X86_64_NUM 16 + +/* + * XXX - PowerPC defines really don't belong in here, + * but we'll put them in for simplicity. + */ + +/* Values for Elf32/64_Ehdr.e_flags */ +#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ + +#define EF_PPC64_ELFV1_ABI 0x00000001 +#define EF_PPC64_ELFV2_ABI 0x00000002 + +/* Cygnus local bits below */ +#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ +#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib + flag */ + +/* PowerPC relocations defined by the ABIs */ +#define R_PPC_NONE 0 +#define R_PPC_ADDR32 1 /* 32bit absolute address */ +#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored */ +#define R_PPC_ADDR16 3 /* 16bit absolute address */ +#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ +#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ +#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ +#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ +#define R_PPC_ADDR14_BRTAKEN 8 +#define R_PPC_ADDR14_BRNTAKEN 9 +#define R_PPC_REL24 10 /* PC relative 26 bit */ +#define R_PPC_REL14 11 /* PC relative 16 bit */ +#define R_PPC_REL14_BRTAKEN 12 +#define R_PPC_REL14_BRNTAKEN 13 +#define R_PPC_GOT16 14 +#define R_PPC_GOT16_LO 15 +#define R_PPC_GOT16_HI 16 +#define R_PPC_GOT16_HA 17 +#define R_PPC_PLTREL24 18 +#define R_PPC_COPY 19 +#define R_PPC_GLOB_DAT 20 +#define R_PPC_JMP_SLOT 21 +#define R_PPC_RELATIVE 22 +#define R_PPC_LOCAL24PC 23 +#define R_PPC_UADDR32 24 +#define R_PPC_UADDR16 25 +#define R_PPC_REL32 26 +#define R_PPC_PLT32 27 +#define R_PPC_PLTREL32 28 +#define R_PPC_PLT16_LO 29 +#define R_PPC_PLT16_HI 30 +#define R_PPC_PLT16_HA 31 +#define R_PPC_SDAREL16 32 +#define R_PPC_SECTOFF 33 +#define R_PPC_SECTOFF_LO 34 +#define R_PPC_SECTOFF_HI 35 +#define R_PPC_SECTOFF_HA 36 +/* Keep this the last entry */ +#define R_PPC_NUM 37 + +/* + * The remaining relocs are from the Embedded ELF ABI, and are not + * in the SVR4 ELF ABI. + */ +#define R_PPC_EMB_NADDR32 101 +#define R_PPC_EMB_NADDR16 102 +#define R_PPC_EMB_NADDR16_LO 103 +#define R_PPC_EMB_NADDR16_HI 104 +#define R_PPC_EMB_NADDR16_HA 105 +#define R_PPC_EMB_SDAI16 106 +#define R_PPC_EMB_SDA2I16 107 +#define R_PPC_EMB_SDA2REL 108 +#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ +#define R_PPC_EMB_MRKREF 110 +#define R_PPC_EMB_RELSEC16 111 +#define R_PPC_EMB_RELST_LO 112 +#define R_PPC_EMB_RELST_HI 113 +#define R_PPC_EMB_RELST_HA 114 +#define R_PPC_EMB_BIT_FLD 115 +#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ + +/* Diab tool relocations */ +#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ +#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ +#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ +#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ +#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ +#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ + +/* + * This is a phony reloc to handle any old fashioned TOC16 references + * that may still be in object files. + */ +#define R_PPC_TOC16 255 + + /* ARM relocs */ +#define R_ARM_NONE 0 /* No reloc */ +#define R_ARM_RELATIVE 23 /* Adjust by program base */ + +/* AArch64 relocs */ +#define R_AARCH64_NONE 0 /* No relocation */ +#define R_AARCH64_RELATIVE 1027 /* Adjust by program base */ + +/* RISC-V relocations */ +#define R_RISCV_32 1 +#define R_RISCV_64 2 +#define R_RISCV_RELATIVE 3 + +#ifndef __ASSEMBLY__ +int valid_elf_image(unsigned long addr); +unsigned long load_elf64_image_phdr(unsigned long addr); +unsigned long load_elf64_image_shdr(unsigned long addr); +unsigned long load_elf_image_phdr(unsigned long addr); +unsigned long load_elf_image_shdr(unsigned long addr); +#endif + +#endif /* _ELF_H */ diff --git a/roms/u-boot/include/env.h b/roms/u-boot/include/env.h new file mode 100644 index 000000000..d5e2bcb53 --- /dev/null +++ b/roms/u-boot/include/env.h @@ -0,0 +1,393 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Common environment functions and definitions + * + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef __ENV_H +#define __ENV_H + +#include +#include +#include + +struct environment_s; + +/* Value for environment validity */ +enum env_valid { + ENV_INVALID, /* No valid environment */ + ENV_VALID, /* First or only environment is valid */ + ENV_REDUND, /* Redundant environment is valid */ +}; + +/** enum env_op - environment callback operation */ +enum env_op { + env_op_create, + env_op_delete, + env_op_overwrite, +}; + +/** struct env_clbk_tbl - declares a new callback */ +struct env_clbk_tbl { + const char *name; /* Callback name */ + int (*callback)(const char *name, const char *value, enum env_op op, + int flags); +}; + +/* + * Define a callback that can be associated with variables. + * when associated through the ".callbacks" environment variable, the callback + * will be executed any time the variable is inserted, overwritten, or deleted. + * + * For SPL these are silently dropped to reduce code size, since environment + * callbacks are not supported with SPL. + */ +#ifdef CONFIG_SPL_BUILD +#define U_BOOT_ENV_CALLBACK(name, callback) \ + static inline __maybe_unused void _u_boot_env_noop_##name(void) \ + { \ + (void)callback; \ + } +#else +#define U_BOOT_ENV_CALLBACK(name, callback) \ + ll_entry_declare(struct env_clbk_tbl, name, env_clbk) = \ + {#name, callback} +#endif + +/** enum env_redund_flags - Flags for the redundand_environment */ +enum env_redund_flags { + ENV_REDUND_OBSOLETE = 0, + ENV_REDUND_ACTIVE = 1, +}; + +/** + * env_get_id() - Gets a sequence number for the environment + * + * This value increments every time the environment changes, so can be used an + * an indication of this + * + * @return environment ID + */ +int env_get_id(void); + +/** + * env_init() - Set up the pre-relocation environment + * + * This locates the environment or uses the default if nothing is available. + * This must be called before env_get() will work. + * + * @return 0 if OK, -ENODEV if no environment drivers are enabled + */ +int env_init(void); + +/** + * env_relocate() - Set up the post-relocation environment + * + * This loads the environment into RAM so that it can be modified. This is + * called after relocation, before the environment is used + */ +void env_relocate(void); + +/** + * env_match() - Match a name / name=value pair + * + * This is used prior to relocation for finding envrionment variables + * + * @name: A simple 'name', or a 'name=value' pair. + * @index: The environment index for a 'name2=value2' pair. + * @return index for the value if the names match, else -1. + */ +int env_match(unsigned char *name, int index); + +/** + * env_get() - Look up the value of an environment variable + * + * In U-Boot proper this can be called before relocation (which is when the + * environment is loaded from storage, i.e. GD_FLG_ENV_READY is 0). In that + * case this function calls env_get_f(). + * + * @varname: Variable to look up + * @return value of variable, or NULL if not found + */ +char *env_get(const char *varname); + +/* + * Like env_get, but prints an error if envvar isn't defined in the + * environment. It always returns what env_get does, so it can be used in + * place of env_get without changing error handling otherwise. + * + * @varname: Variable to look up + * @return value of variable, or NULL if not found + */ +char *from_env(const char *envvar); + +/** + * env_get_f() - Look up the value of an environment variable (early) + * + * This function is called from env_get() if the environment has not been + * loaded yet (GD_FLG_ENV_READY flag is 0). Some environment locations will + * support reading the value (slowly) and some will not. + * + * @varname: Variable to look up + * @return value of variable, or NULL if not found + */ +int env_get_f(const char *name, char *buf, unsigned int len); + +/** + * env_get_yesno() - Read an environment variable as a boolean + * + * @return 1 if yes/true (Y/y/T/t), -1 if variable does not exist (i.e. default + * to true), 0 if otherwise + */ +int env_get_yesno(const char *var); + +/** + * env_set() - set an environment variable + * + * This sets or deletes the value of an environment variable. For setting the + * value the variable is created if it does not already exist. + * + * @varname: Variable to adjust + * @value: Value to set for the variable, or NULL or "" to delete the variable + * @return 0 if OK, 1 on error + */ +int env_set(const char *varname, const char *value); + +/** + * env_get_ulong() - Return an environment variable as an integer value + * + * Most U-Boot environment variables store hex values. For those which store + * (e.g.) base-10 integers, this function can be used to read the value. + * + * @name: Variable to look up + * @base: Base to use (e.g. 10 for base 10, 2 for binary) + * @default_val: Default value to return if no value is found + * @return the value found, or @default_val if none + */ +ulong env_get_ulong(const char *name, int base, ulong default_val); + +/** + * env_set_ulong() - set an environment variable to an integer + * + * @varname: Variable to adjust + * @value: Value to set for the variable (will be converted to a string) + * @return 0 if OK, 1 on error + */ +int env_set_ulong(const char *varname, ulong value); + +/** + * env_get_hex() - Return an environment variable as a hex value + * + * Decode an environment as a hex number (it may or may not have a 0x + * prefix). If the environment variable cannot be found, or does not start + * with hex digits, the default value is returned. + * + * @varname: Variable to decode + * @default_val: Value to return on error + */ +ulong env_get_hex(const char *varname, ulong default_val); + +/** + * env_set_hex() - set an environment variable to a hex value + * + * @varname: Variable to adjust + * @value: Value to set for the variable (will be converted to a hex string) + * @return 0 if OK, 1 on error + */ +int env_set_hex(const char *varname, ulong value); + +/** + * env_set_addr - Set an environment variable to an address in hex + * + * @varname: Environment variable to set + * @addr: Value to set it to + * @return 0 if ok, 1 on error + */ +static inline int env_set_addr(const char *varname, const void *addr) +{ + return env_set_hex(varname, (ulong)addr); +} + +/** + * env_complete() - return an auto-complete for environment variables + * + * @var: partial name to auto-complete + * @maxv: Maximum number of matches to return + * @cmdv: Returns a list of possible matches + * @maxsz: Size of buffer to use for matches + * @buf: Buffer to use for matches + * @dollar_comp: non-zero to wrap each match in ${...} + * @return number of matches found (in @cmdv) + */ +int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf, + bool dollar_comp); + +/** + * eth_env_get_enetaddr() - Get an ethernet address from the environmnet + * + * @name: Environment variable to get (e.g. "ethaddr") + * @enetaddr: Place to put MAC address (6 bytes) + * @return 0 if OK, 1 on error + */ +int eth_env_get_enetaddr(const char *name, uint8_t *enetaddr); + +/** + * eth_env_set_enetaddr() - Set an ethernet address in the environmnet + * + * @name: Environment variable to set (e.g. "ethaddr") + * @enetaddr: Pointer to MAC address to put into the variable (6 bytes) + * @return 0 if OK, 1 on error + */ +int eth_env_set_enetaddr(const char *name, const uint8_t *enetaddr); + +/** + * env_fix_drivers() - Updates envdriver as per relocation + */ +void env_fix_drivers(void); + +/** + * env_set_default_vars() - reset variables to their default value + * + * This resets individual variables to their value in the default environment + * + * @nvars: Number of variables to set/reset + * @vars: List of variables to set/reset + * @flags: Flags controlling matching (H_... - see search.h) + */ +int env_set_default_vars(int nvars, char *const vars[], int flags); + +/** + * env_load() - Load the environment from storage + * + * @return 0 if OK, -ve on error + */ +int env_load(void); + +/** + * env_reload() - Re-Load the environment from current storage + * + * @return 0 if OK, -ve on error + */ +int env_reload(void); + +/** + * env_save() - Save the environment to storage + * + * @return 0 if OK, -ve on error + */ +int env_save(void); + +/** + * env_erase() - Erase the environment on storage + * + * @return 0 if OK, -ve on error + */ +int env_erase(void); + +/** + * env_select() - Select the environment storage + * + * @return 0 if OK, -ve on error + */ +int env_select(const char *name); + +/** + * env_import() - Import from a binary representation into hash table + * + * This imports the environment from a buffer. The format for each variable is + * var=value\0 with a double \0 at the end of the buffer. + * + * @buf: Buffer containing the environment (struct environemnt_s *) + * @check: non-zero to check the CRC at the start of the environment, 0 to + * ignore it + * @flags: Flags controlling matching (H_... - see search.h) + * @return 0 if imported successfully, -ENOMSG if the CRC was bad, -EIO if + * something else went wrong + */ +int env_import(const char *buf, int check, int flags); + +/** + * env_export() - Export the environment to a buffer + * + * Export from hash table into binary representation + * + * @env_out: Buffer to contain the environment (must be large enough!) + * @return 0 if OK, 1 on error + */ +int env_export(struct environment_s *env_out); + +/** + * env_check_redund() - check the two redundant environments + * and find out, which is the valid one. + * + * @buf1: First environment (struct environemnt_s *) + * @buf1_read_fail: 0 if buf1 is valid, non-zero if invalid + * @buf2: Second environment (struct environemnt_s *) + * @buf2_read_fail: 0 if buf2 is valid, non-zero if invalid + * @return 0 if OK, + * -EIO if no environment is valid, + * -ENOMSG if the CRC was bad + */ + +int env_check_redund(const char *buf1, int buf1_read_fail, + const char *buf2, int buf2_read_fail); + +/** + * env_import_redund() - Select and import one of two redundant environments + * + * @buf1: First environment (struct environemnt_s *) + * @buf1_read_fail: 0 if buf1 is valid, non-zero if invalid + * @buf2: Second environment (struct environemnt_s *) + * @buf2_read_fail: 0 if buf2 is valid, non-zero if invalid + * @flags: Flags controlling matching (H_... - see search.h) + * @return 0 if OK, -EIO if no environment is valid, -ENOMSG if the CRC was bad + */ +int env_import_redund(const char *buf1, int buf1_read_fail, + const char *buf2, int buf2_read_fail, + int flags); + +/** + * env_get_default() - Look up a variable from the default environment + * + * @name: Variable to look up + * @return value if found, NULL if not found in default environment + */ +char *env_get_default(const char *name); + +/* [re]set to the default environment */ +void env_set_default(const char *s, int flags); + +/** + * env_get_char() - Get a character from the early environment + * + * This reads from the pre-relocation environment + * + * @index: Index of character to read (0 = first) + * @return character read, or -ve on error + */ +int env_get_char(int index); + +/** + * env_reloc() - Relocate the 'env' sub-commands + * + * This is used for those unfortunate archs with crappy toolchains + */ +void env_reloc(void); + + +/** + * env_import_fdt() - Import environment values from device tree blob + * + * This uses the value of the environment variable "env_fdt_path" as a + * path to an fdt node, whose property/value pairs are added to the + * environment. + */ +#ifdef CONFIG_ENV_IMPORT_FDT +void env_import_fdt(void); +#else +static inline void env_import_fdt(void) {} +#endif + +#endif diff --git a/roms/u-boot/include/env_attr.h b/roms/u-boot/include/env_attr.h new file mode 100644 index 000000000..e0846cccb --- /dev/null +++ b/roms/u-boot/include/env_attr.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Joe Hershberger, National Instruments, joe.hershberger@ni.com + */ + +#ifndef __ENV_ATTR_H__ +#define __ENV_ATTR_H__ + +#define ENV_ATTR_LIST_DELIM ',' +#define ENV_ATTR_SEP ':' + +/* + * env_attr_walk takes as input an "attr_list" that takes the form: + * attributes = [^,:\s]* + * entry = name[:attributes] + * list = entry[,list] + * It will call the "callback" function with the "name" and "attributes" + * The callback may return a non-0 to abort the list walk. + * This return value will be passed through to the caller. + * 0 is returned on success. + */ +int env_attr_walk(const char *attr_list, + int (*callback)(const char *name, const char *attributes, void *priv), + void *priv); + +/* + * env_attr_lookup takes as input an "attr_list" with the same form as above. + * It also takes as input a "name" to look for. + * If the name is found in the list, it's value is copied into "attributes". + * There is no protection on attributes being too small for the value. + * It returns -1 if attributes is NULL, 1 if "name" is not found, 2 if + * "attr_list" is NULL. + * Returns 0 on success. + */ +int env_attr_lookup(const char *attr_list, const char *name, char *attributes); + +#endif /* __ENV_ATTR_H__ */ diff --git a/roms/u-boot/include/env_callback.h b/roms/u-boot/include/env_callback.h new file mode 100644 index 000000000..05e9516a0 --- /dev/null +++ b/roms/u-boot/include/env_callback.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Joe Hershberger, National Instruments, joe.hershberger@ni.com + */ + +#ifndef __ENV_CALLBACK_H__ +#define __ENV_CALLBACK_H__ + +#include +#include +#include + +#define ENV_CALLBACK_VAR ".callbacks" + +/* Board configs can define additional static callback bindings */ +#ifndef CONFIG_ENV_CALLBACK_LIST_STATIC +#define CONFIG_ENV_CALLBACK_LIST_STATIC +#endif + +#ifdef CONFIG_SILENT_CONSOLE +#define SILENT_CALLBACK "silent:silent," +#else +#define SILENT_CALLBACK +#endif + +#ifdef CONFIG_SPLASHIMAGE_GUARD +#define SPLASHIMAGE_CALLBACK "splashimage:splashimage," +#else +#define SPLASHIMAGE_CALLBACK +#endif + +#ifdef CONFIG_REGEX +#define ENV_DOT_ESCAPE "\\" +#else +#define ENV_DOT_ESCAPE +#endif + +#ifdef CONFIG_CMD_DNS +#define DNS_CALLBACK "dnsip:dnsip," +#else +#define DNS_CALLBACK +#endif + +#ifdef CONFIG_NET +#define NET_CALLBACKS \ + "bootfile:bootfile," \ + "ipaddr:ipaddr," \ + "gatewayip:gatewayip," \ + "netmask:netmask," \ + "serverip:serverip," \ + "nvlan:nvlan," \ + "vlan:vlan," \ + DNS_CALLBACK \ + "eth" ETHADDR_WILDCARD "addr:ethaddr," +#else +#define NET_CALLBACKS +#endif + +/* + * This list of callback bindings is static, but may be overridden by defining + * a new association in the ".callbacks" environment variable. + */ +#define ENV_CALLBACK_LIST_STATIC ENV_DOT_ESCAPE ENV_CALLBACK_VAR ":callbacks," \ + ENV_DOT_ESCAPE ENV_FLAGS_VAR ":flags," \ + "baudrate:baudrate," \ + NET_CALLBACKS \ + "loadaddr:loadaddr," \ + SILENT_CALLBACK \ + SPLASHIMAGE_CALLBACK \ + "stdin:console,stdout:console,stderr:console," \ + "serial#:serialno," \ + CONFIG_ENV_CALLBACK_LIST_STATIC + +#ifndef CONFIG_SPL_BUILD +void env_callback_init(struct env_entry *var_entry); +#else +static inline void env_callback_init(struct env_entry *var_entry) +{ +} +#endif + +#endif /* __ENV_CALLBACK_H__ */ diff --git a/roms/u-boot/include/env_default.h b/roms/u-boot/include/env_default.h new file mode 100644 index 000000000..1ddd64ba8 --- /dev/null +++ b/roms/u-boot/include/env_default.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + */ + +#include +#include + +#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED +env_t embedded_environment __UBOOT_ENV_SECTION__(environment) = { + ENV_CRC, /* CRC Sum */ +#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT + 1, /* Flags: valid */ +#endif + { +#elif defined(DEFAULT_ENV_INSTANCE_STATIC) +static char default_environment[] = { +#elif defined(DEFAULT_ENV_IS_RW) +uchar default_environment[] = { +#else +const uchar default_environment[] = { +#endif +#ifndef CONFIG_USE_DEFAULT_ENV_FILE +#ifdef CONFIG_ENV_CALLBACK_LIST_DEFAULT + ENV_CALLBACK_VAR "=" CONFIG_ENV_CALLBACK_LIST_DEFAULT "\0" +#endif +#ifdef CONFIG_ENV_FLAGS_LIST_DEFAULT + ENV_FLAGS_VAR "=" CONFIG_ENV_FLAGS_LIST_DEFAULT "\0" +#endif +#ifdef CONFIG_USE_BOOTARGS + "bootargs=" CONFIG_BOOTARGS "\0" +#endif +#ifdef CONFIG_BOOTCOMMAND + "bootcmd=" CONFIG_BOOTCOMMAND "\0" +#endif +#ifdef CONFIG_RAMBOOTCOMMAND + "ramboot=" CONFIG_RAMBOOTCOMMAND "\0" +#endif +#ifdef CONFIG_NFSBOOTCOMMAND + "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0" +#endif +#if defined(CONFIG_BOOTDELAY) + "bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0" +#endif +#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0) + "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" +#endif +#ifdef CONFIG_LOADS_ECHO + "loads_echo=" __stringify(CONFIG_LOADS_ECHO) "\0" +#endif +#ifdef CONFIG_ETHPRIME + "ethprime=" CONFIG_ETHPRIME "\0" +#endif +#ifdef CONFIG_IPADDR + "ipaddr=" __stringify(CONFIG_IPADDR) "\0" +#endif +#ifdef CONFIG_SERVERIP + "serverip=" __stringify(CONFIG_SERVERIP) "\0" +#endif +#ifdef CONFIG_SYS_AUTOLOAD + "autoload=" CONFIG_SYS_AUTOLOAD "\0" +#endif +#ifdef CONFIG_PREBOOT + "preboot=" CONFIG_PREBOOT "\0" +#endif +#ifdef CONFIG_ROOTPATH + "rootpath=" CONFIG_ROOTPATH "\0" +#endif +#ifdef CONFIG_GATEWAYIP + "gatewayip=" __stringify(CONFIG_GATEWAYIP) "\0" +#endif +#ifdef CONFIG_NETMASK + "netmask=" __stringify(CONFIG_NETMASK) "\0" +#endif +#ifdef CONFIG_HOSTNAME + "hostname=" CONFIG_HOSTNAME "\0" +#endif +#ifdef CONFIG_BOOTFILE + "bootfile=" CONFIG_BOOTFILE "\0" +#endif +#ifdef CONFIG_LOADADDR + "loadaddr=" __stringify(CONFIG_LOADADDR) "\0" +#endif +#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) + "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0" +#endif +#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG + "arch=" CONFIG_SYS_ARCH "\0" +#ifdef CONFIG_SYS_CPU + "cpu=" CONFIG_SYS_CPU "\0" +#endif +#ifdef CONFIG_SYS_BOARD + "board=" CONFIG_SYS_BOARD "\0" + "board_name=" CONFIG_SYS_BOARD "\0" +#endif +#ifdef CONFIG_SYS_VENDOR + "vendor=" CONFIG_SYS_VENDOR "\0" +#endif +#ifdef CONFIG_SYS_SOC + "soc=" CONFIG_SYS_SOC "\0" +#endif +#ifdef CONFIG_ENV_IMPORT_FDT + "env_fdt_path=" CONFIG_ENV_FDT_PATH "\0" +#endif +#endif +#if defined(CONFIG_BOOTCOUNT_BOOTLIMIT) && (CONFIG_BOOTCOUNT_BOOTLIMIT > 0) + "bootlimit=" __stringify(CONFIG_BOOTCOUNT_BOOTLIMIT)"\0" +#endif +#ifdef CONFIG_EXTRA_ENV_SETTINGS + CONFIG_EXTRA_ENV_SETTINGS +#endif + "\0" +#else /* CONFIG_USE_DEFAULT_ENV_FILE */ +#include "generated/defaultenv_autogenerated.h" +#endif +#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED + } +#endif +}; diff --git a/roms/u-boot/include/env_flags.h b/roms/u-boot/include/env_flags.h new file mode 100644 index 000000000..313cb8c49 --- /dev/null +++ b/roms/u-boot/include/env_flags.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Joe Hershberger, National Instruments, joe.hershberger@ni.com + */ + +#ifndef __ENV_FLAGS_H__ +#define __ENV_FLAGS_H__ + +enum env_flags_vartype { + env_flags_vartype_string, + env_flags_vartype_decimal, + env_flags_vartype_hex, + env_flags_vartype_bool, +#ifdef CONFIG_CMD_NET + env_flags_vartype_ipaddr, + env_flags_vartype_macaddr, +#endif + env_flags_vartype_end +}; + +enum env_flags_varaccess { + env_flags_varaccess_any, + env_flags_varaccess_readonly, + env_flags_varaccess_writeonce, + env_flags_varaccess_changedefault, +#ifdef CONFIG_ENV_WRITEABLE_LIST + env_flags_varaccess_writeable, +#endif + env_flags_varaccess_end +}; + +#define ENV_FLAGS_VAR ".flags" +#define ENV_FLAGS_ATTR_MAX_LEN 2 +#define ENV_FLAGS_VARTYPE_LOC 0 +#define ENV_FLAGS_VARACCESS_LOC 1 + +#ifndef CONFIG_ENV_FLAGS_LIST_STATIC +#define CONFIG_ENV_FLAGS_LIST_STATIC "" +#endif + +#ifdef CONFIG_NET +#ifdef CONFIG_REGEX +#define ETHADDR_WILDCARD "\\d*" +#else +#define ETHADDR_WILDCARD +#endif +#ifdef CONFIG_ENV_OVERWRITE +#define ETHADDR_FLAGS "eth" ETHADDR_WILDCARD "addr:ma," +#else +#ifdef CONFIG_OVERWRITE_ETHADDR_ONCE +#define ETHADDR_FLAGS "eth" ETHADDR_WILDCARD "addr:mc," +#else +#define ETHADDR_FLAGS "eth" ETHADDR_WILDCARD "addr:mo," +#endif +#endif +#define NET_FLAGS \ + "ipaddr:i," \ + "gatewayip:i," \ + "netmask:i," \ + "serverip:i," \ + "nvlan:d," \ + "vlan:d," \ + "dnsip:i," +#else +#define ETHADDR_FLAGS +#define NET_FLAGS +#endif + +#ifndef CONFIG_ENV_OVERWRITE +#define SERIAL_FLAGS "serial#:so," +#else +#define SERIAL_FLAGS "" +#endif + +#define ENV_FLAGS_LIST_STATIC \ + ETHADDR_FLAGS \ + NET_FLAGS \ + SERIAL_FLAGS \ + CONFIG_ENV_FLAGS_LIST_STATIC + +#ifdef CONFIG_CMD_ENV_FLAGS +/* + * Print the whole list of available type flags. + */ +void env_flags_print_vartypes(void); +/* + * Print the whole list of available access flags. + */ +void env_flags_print_varaccess(void); +/* + * Return the name of the type. + */ +const char *env_flags_get_vartype_name(enum env_flags_vartype type); +/* + * Return the name of the access. + */ +const char *env_flags_get_varaccess_name(enum env_flags_varaccess access); +#endif + +/* + * Parse the flags string from a .flags attribute list into the vartype enum. + */ +enum env_flags_vartype env_flags_parse_vartype(const char *flags); +/* + * Parse the flags string from a .flags attribute list into the varaccess enum. + */ +enum env_flags_varaccess env_flags_parse_varaccess(const char *flags); +/* + * Parse the binary flags from a hash table entry into the varaccess enum. + */ +enum env_flags_varaccess env_flags_parse_varaccess_from_binflags(int binflags); + +#ifdef CONFIG_CMD_NET +/* + * Check if a string has the format of an Ethernet MAC address + */ +int eth_validate_ethaddr_str(const char *addr); +#endif + +#ifdef USE_HOSTCC +/* + * Look up the type of a variable directly from the .flags var. + */ +enum env_flags_vartype env_flags_get_type(const char *name); +/* + * Look up the access of a variable directly from the .flags var. + */ +enum env_flags_varaccess env_flags_get_access(const char *name); +/* + * Validate the newval for its type to conform with the requirements defined by + * its flags (directly looked at the .flags var). + */ +int env_flags_validate_type(const char *name, const char *newval); +/* + * Validate the newval for its access to conform with the requirements defined + * by its flags (directly looked at the .flags var). + */ +int env_flags_validate_access(const char *name, int check_mask); +/* + * Validate that the proposed access to variable "name" is valid according to + * the defined flags for that variable, if any. + */ +int env_flags_validate_varaccess(const char *name, int check_mask); +/* + * Validate the parameters passed to "env set" for type compliance + */ +int env_flags_validate_env_set_params(char *name, char *const val[], int count); + +#else /* !USE_HOSTCC */ + +#include +#include + +/* + * When adding a variable to the environment, initialize the flags for that + * variable. + */ +void env_flags_init(struct env_entry *var_entry); + +/* + * Validate the newval for to conform with the requirements defined by its flags + */ +int env_flags_validate(const struct env_entry *item, const char *newval, + enum env_op op, int flag); + +#endif /* USE_HOSTCC */ + +/* + * These are the binary flags used in the environment entry->flags variable to + * decribe properties of veriables in the table + */ +#define ENV_FLAGS_VARTYPE_BIN_MASK 0x00000007 +/* The actual variable type values use the enum value (within the mask) */ +#define ENV_FLAGS_VARACCESS_PREVENT_DELETE 0x00000008 +#define ENV_FLAGS_VARACCESS_PREVENT_CREATE 0x00000010 +#define ENV_FLAGS_VARACCESS_PREVENT_OVERWR 0x00000020 +#define ENV_FLAGS_VARACCESS_PREVENT_NONDEF_OVERWR 0x00000040 +#define ENV_FLAGS_VARACCESS_WRITEABLE 0x00000080 +#define ENV_FLAGS_VARACCESS_BIN_MASK 0x000000f8 + +#endif /* __ENV_FLAGS_H__ */ diff --git a/roms/u-boot/include/env_internal.h b/roms/u-boot/include/env_internal.h new file mode 100644 index 000000000..b7bddcb00 --- /dev/null +++ b/roms/u-boot/include/env_internal.h @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Internal environment header file. This includes direct access to environment + * information such as its size and offset, direct access to the default + * environment and embedded environment (if used). It also provides environment + * drivers with various declarations. + * + * It should not be included by board files, drivers and code other than that + * related to the environment implementation. + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef _ENV_INTERNAL_H_ +#define _ENV_INTERNAL_H_ + +#include + +/************************************************************************** + * + * The "environment" is stored as a list of '\0' terminated + * "name=value" strings. The end of the list is marked by a double + * '\0'. New entries are always added at the end. Deleting an entry + * shifts the remaining entries to the front. Replacing an entry is a + * combination of deleting the old value and adding the new one. + * + * The environment is preceded by a 32 bit CRC over the data part. + * + *************************************************************************/ + +#if defined(CONFIG_ENV_IS_IN_FLASH) +# if defined(CONFIG_ENV_ADDR_REDUND) && \ + ((CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE) && \ + (CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE) <= \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) +# define ENV_IS_EMBEDDED +# endif +# if (CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE) && \ + (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) <= \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +# define ENV_IS_EMBEDDED +# endif +# ifdef CONFIG_ENV_IS_EMBEDDED +# error "do not define CONFIG_ENV_IS_EMBEDDED in your board config" +# error "it is calculated automatically for you" +# endif +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +#if defined(CONFIG_ENV_IS_IN_NAND) +# if defined(CONFIG_ENV_OFFSET_OOB) +# ifdef CONFIG_ENV_OFFSET_REDUND +# error "CONFIG_ENV_OFFSET_REDUND is not supported when CONFIG_ENV_OFFSET_OOB" +# error "is set" +# endif +extern unsigned long nand_env_oob_offset; +# define CONFIG_ENV_OFFSET nand_env_oob_offset +# endif /* CONFIG_ENV_OFFSET_OOB */ +#endif /* CONFIG_ENV_IS_IN_NAND */ + +/* + * For the flash types where embedded env is supported, but it cannot be + * calculated automatically (i.e. NAND), take the board opt-in. + */ +#if defined(CONFIG_ENV_IS_EMBEDDED) && !defined(ENV_IS_EMBEDDED) +# define ENV_IS_EMBEDDED +#endif + +/* The build system likes to know if the env is embedded */ +#ifdef DO_DEPS_ONLY +# ifdef ENV_IS_EMBEDDED +# ifndef CONFIG_ENV_IS_EMBEDDED +# define CONFIG_ENV_IS_EMBEDDED +# endif +# endif +#endif + +#include "compiler.h" + +#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT +# define ENV_HEADER_SIZE (sizeof(uint32_t) + 1) +#else +# define ENV_HEADER_SIZE (sizeof(uint32_t)) +#endif + +#define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) + +/* + * If the environment is in RAM, allocate extra space for it in the malloc + * region. + */ +#if defined(CONFIG_ENV_IS_EMBEDDED) +#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN +#elif (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE < CONFIG_SYS_MONITOR_BASE) || \ + (CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) || \ + defined(CONFIG_ENV_IS_IN_NVRAM) +#define TOTAL_MALLOC_LEN (CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE) +#else +#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN +#endif + +typedef struct environment_s { + uint32_t crc; /* CRC32 over data bytes */ +#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT + unsigned char flags; /* active/obsolete flags ENVF_REDUND_ */ +#endif + unsigned char data[ENV_SIZE]; /* Environment data */ +} env_t; + +#ifdef ENV_IS_EMBEDDED +extern env_t embedded_environment; +#endif /* ENV_IS_EMBEDDED */ + +#ifdef DEFAULT_ENV_IS_RW +extern unsigned char default_environment[]; +#else +extern const unsigned char default_environment[]; +#endif + +#ifndef DO_DEPS_ONLY + +#include +#include +#include +#include + +enum env_location { + ENVL_UNKNOWN, + ENVL_EEPROM, + ENVL_EXT4, + ENVL_FAT, + ENVL_FLASH, + ENVL_MMC, + ENVL_NAND, + ENVL_NVRAM, + ENVL_ONENAND, + ENVL_REMOTE, + ENVL_SPI_FLASH, + ENVL_UBI, + ENVL_NOWHERE, + + ENVL_COUNT, +}; + +/* value for the various operations we want to perform on the env */ +enum env_operation { + ENVOP_GET_CHAR, /* we want to call the get_char function */ + ENVOP_INIT, /* we want to call the init function */ + ENVOP_LOAD, /* we want to call the load function */ + ENVOP_SAVE, /* we want to call the save function */ + ENVOP_ERASE, /* we want to call the erase function */ +}; + +struct env_driver { + const char *name; + enum env_location location; + + /** + * load() - Load the environment from storage + * + * This method is required for loading environment + * + * @return 0 if OK, -ve on error + */ + int (*load)(void); + + /** + * save() - Save the environment to storage + * + * This method is required for 'saveenv' to work. + * + * @return 0 if OK, -ve on error + */ + int (*save)(void); + + /** + * erase() - Erase the environment on storage + * + * This method is optional and required for 'eraseenv' to work. + * + * @return 0 if OK, -ve on error + */ + int (*erase)(void); + + /** + * init() - Set up the initial pre-relocation environment + * + * This method is optional. + * + * @return 0 if OK, -ENOENT if no initial environment could be found, + * other -ve on error + */ + int (*init)(void); +}; + +/* Declare a new environment location driver */ +#define U_BOOT_ENV_LOCATION(__name) \ + ll_entry_declare(struct env_driver, __name, env_driver) + +/* Declare the name of a location */ +#ifdef CONFIG_CMD_SAVEENV +#define ENV_NAME(_name) .name = _name, +#else +#define ENV_NAME(_name) +#endif + +#ifdef CONFIG_CMD_SAVEENV +#define env_save_ptr(x) x +#else +#define env_save_ptr(x) NULL +#endif + +#define ENV_SAVE_PTR(x) (CONFIG_IS_ENABLED(SAVEENV) ? (x) : NULL) +#define ENV_ERASE_PTR(x) (CONFIG_IS_ENABLED(CMD_ERASEENV) ? (x) : NULL) + +extern struct hsearch_data env_htab; + +/** + * env_ext4_get_intf() - Provide the interface for env in EXT4 + * + * It is a weak function allowing board to overidde the default interface for + * U-Boot env in EXT4: CONFIG_ENV_EXT4_INTERFACE + * + * @return string of interface, empty if not supported + */ +const char *env_ext4_get_intf(void); + +/** + * env_ext4_get_dev_part() - Provide the device and partition for env in EXT4 + * + * It is a weak function allowing board to overidde the default device and + * partition used for U-Boot env in EXT4: CONFIG_ENV_EXT4_DEVICE_AND_PART + * + * @return string of device and partition + */ +const char *env_ext4_get_dev_part(void); + +/** + * env_get_location()- Provide the best location for the U-Boot environment + * + * It is a weak function allowing board to overidde the environment location + * + * @op: operations performed on the environment + * @prio: priority between the multiple environments, 0 being the + * highest priority + * @return an enum env_location value on success, or -ve error code. + */ +enum env_location env_get_location(enum env_operation op, int prio); +#endif /* DO_DEPS_ONLY */ + +#endif /* _ENV_INTERNAL_H_ */ diff --git a/roms/u-boot/include/environment/distro/sf.h b/roms/u-boot/include/environment/distro/sf.h new file mode 100644 index 000000000..e793be06c --- /dev/null +++ b/roms/u-boot/include/environment/distro/sf.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Amarula Solutions(India) + * + * SF distro configurations. + */ + +#ifndef __DISTRO_SF_CONFIG_H +#define __DISTRO_SF_CONFIG_H + +#if CONFIG_IS_ENABLED(CMD_SF) +#define BOOTENV_SHARED_SF(devtypel) \ + #devtypel "_boot=" \ + "if " #devtypel " probe ${busnum}; then " \ + "devtype=" #devtypel "; " \ + "run scan_sf_for_scripts; " \ + "fi\0" +#define BOOTENV_DEV_SF(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "busnum=" #instance "; " \ + "run " #devtypel "_boot\0" +#define BOOTENV_DEV_NAME_SF(devtypeu, devtypel, instance) \ + #devtypel #instance " " +#else +#define BOOTENV_SHARED_SF(devtypel) +#define BOOTENV_DEV_SF \ + BOOT_TARGET_DEVICES_references_SF_without_CONFIG_CMD_SF +#define BOOTENV_DEV_NAME_SF \ + BOOT_TARGET_DEVICES_references_SF_without_CONFIG_CMD_SF + +#endif /* CONFIG_CMD_SF */ + +#define BOOTENV_SF \ + BOOTENV_SHARED_SF(sf) \ + "scan_sf_for_scripts=" \ + "${devtype} read ${scriptaddr} " \ + "${script_offset_f} ${script_size_f}; " \ + "source ${scriptaddr}; " \ + "echo SCRIPT FAILED: continuing...\0" + +#endif /* __DISTRO_SF_CONFIG_H */ diff --git a/roms/u-boot/include/environment/ti/boot.h b/roms/u-boot/include/environment/ti/boot.h new file mode 100644 index 000000000..a9d8f28d4 --- /dev/null +++ b/roms/u-boot/include/environment/ti/boot.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Boot related environment variable definitions on TI boards. + * + * (C) Copyright 2017 Linaro Ltd. + * Sam Protsenko + */ + +#ifndef __TI_BOOT_H +#define __TI_BOOT_H + +#include + +#ifndef CONSOLEDEV +#define CONSOLEDEV "ttyS2" +#endif + +#ifndef PARTS_DEFAULT +/* + * Default GPT tables for eMMC (Linux and Android). Notes: + * 1. Keep partitions aligned to erase group size (512 KiB) when possible + * 2. Keep partitions in sync with DFU_ALT_INFO_EMMC (see dfu.h) + * 3. Keep 'bootloader' partition (U-Boot proper) start address in sync with + * CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (see common/spl/Kconfig) + */ +#define PARTS_DEFAULT \ + /* Linux partitions */ \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=bootloader,start=384K,size=1792K,uuid=${uuid_gpt_bootloader};" \ + "name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs}\0" \ + /* Android partitions */ \ + "partitions_android=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \ + "name=bootloader,size=2048K,uuid=${uuid_gpt_bootloader};" \ + "name=uboot-env,start=2432K,size=256K,uuid=${uuid_gpt_reserved};" \ + "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ + "name=boot_a,size=20M,uuid=${uuid_gpt_boot_a};" \ + "name=boot_b,size=20M,uuid=${uuid_gpt_boot_b};" \ + "name=dtbo_a,size=8M,uuid=${uuid_gpt_dtbo_a};" \ + "name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b};" \ + "name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta_a};" \ + "name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta_b};" \ + "name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \ + "name=super,size=2560M,uuid=${uuid_gpt_super};" \ + "name=metadata,size=16M,uuid=${uuid_gpt_metadata};" \ + "name=userdata,size=-,uuid=${uuid_gpt_userdata}" +#endif /* PARTS_DEFAULT */ + +#if defined(CONFIG_CMD_AVB) +#define AVB_VERIFY_CHECK "if run avb_verify; then " \ + "echo AVB verification OK.;" \ + "set bootargs $bootargs $avb_bootargs;" \ + "else " \ + "echo AVB verification failed.;" \ + "exit; fi;" +#define AVB_VERIFY_CMD "avb_verify=avb init 1; avb verify $slot_suffix;\0" +#else +#define AVB_VERIFY_CHECK "" +#define AVB_VERIFY_CMD "" +#endif + +#define CONTROL_PARTITION "misc" + +#if defined(CONFIG_CMD_AB_SELECT) +#define AB_SELECT_SLOT \ + "if part number mmc 1 " CONTROL_PARTITION " control_part_number; " \ + "then " \ + "echo " CONTROL_PARTITION \ + " partition number:${control_part_number};" \ + "ab_select slot_name mmc ${mmcdev}:${control_part_number};" \ + "else " \ + "echo " CONTROL_PARTITION " partition not found;" \ + "exit;" \ + "fi;" \ + "setenv slot_suffix _${slot_name};" +#define AB_SELECT_ARGS \ + "setenv bootargs_ab androidboot.slot_suffix=${slot_suffix}; " \ + "echo A/B cmdline addition: ${bootargs_ab};" \ + "setenv bootargs ${bootargs} ${bootargs_ab};" +#else +#define AB_SELECT_SLOT "" +#define AB_SELECT_ARGS "" +#endif + +/* + * Prepares complete device tree blob for current board (for Android boot). + * + * Boot image or recovery image should be loaded into $loadaddr prior to running + * these commands. The logic of these commnads is next: + * + * 1. Read correct DTB for current SoC/board from boot image in $loadaddr + * to $fdtaddr + * 2. Merge all needed DTBO for current board from 'dtbo' partition into read + * DTB + * 3. User should provide $fdtaddr as 3rd argument to 'bootm' + */ +#define PREPARE_FDT \ + "echo Preparing FDT...; " \ + "if test $board_name = am57xx_evm_reva3; then " \ + "echo \" Reading DTBO partition...\"; " \ + "part start mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_start; " \ + "part size mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_size; " \ + "mmc read ${dtboaddr} ${p_dtbo_start} ${p_dtbo_size}; " \ + "echo \" Reading DTB for AM57x EVM RevA3...\"; " \ + "abootimg get dtb --index=0 dtb_start dtb_size; " \ + "cp.b $dtb_start $fdtaddr $dtb_size; " \ + "fdt addr $fdtaddr 0x80000; " \ + "echo \" Applying DTBOs for AM57x EVM RevA3...\"; " \ + "adtimg addr $dtboaddr; " \ + "adtimg get dt --index=0 dtbo0_addr dtbo0_size; " \ + "fdt apply $dtbo0_addr; " \ + "adtimg get dt --index=1 dtbo1_addr dtbo1_size; " \ + "fdt apply $dtbo1_addr; " \ + "elif test $board_name = beagle_x15_revc; then " \ + "echo \" Reading DTB for Beagle X15 RevC...\"; " \ + "abootimg get dtb --index=0 dtb_start dtb_size; " \ + "cp.b $dtb_start $fdtaddr $dtb_size; " \ + "fdt addr $fdtaddr 0x80000; " \ + "else " \ + "echo Error: Android boot is not supported for $board_name; " \ + "exit; " \ + "fi; " \ + +#define FASTBOOT_CMD \ + "echo Booting into fastboot ...; " \ + "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; " + +#define DEFAULT_COMMON_BOOT_TI_ARGS \ + "console=" CONSOLEDEV ",115200n8\0" \ + "fdtfile=undefined\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "usbtty=cdc_acm\0" \ + "vram=16M\0" \ + AVB_VERIFY_CMD \ + "partitions=" PARTS_DEFAULT "\0" \ + "optargs=\0" \ + "dofastboot=0\0" \ + "emmc_linux_boot=" \ + "echo Trying to boot Linux from eMMC ...; " \ + "setenv mmcdev 1; " \ + "setenv bootpart 1:2; " \ + "setenv mmcroot /dev/mmcblk0p2 rw; " \ + "run mmcboot;\0" \ + "emmc_android_boot=" \ + "setenv mmcdev 1; " \ + "mmc dev $mmcdev; " \ + "mmc rescan; " \ + AB_SELECT_SLOT \ + "if bcb load " __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) " " \ + CONTROL_PARTITION "; then " \ + "setenv ardaddr -; " \ + "if bcb test command = bootonce-bootloader; then " \ + "echo Android: Bootloader boot...; " \ + "bcb clear command; bcb store; " \ + FASTBOOT_CMD \ + "exit; " \ + "elif bcb test command = boot-recovery; then " \ + "echo Android: Recovery boot...; " \ + "setenv ardaddr $loadaddr;" \ + "setenv apart recovery; " \ + "else " \ + "echo Android: Normal boot...; " \ + "setenv ardaddr $loadaddr; " \ + "setenv apart boot${slot_suffix}; " \ + "fi; " \ + "else " \ + "echo Warning: BCB is corrupted or does not exist; " \ + "echo Android: Normal boot...; " \ + "fi; " \ + "setenv eval_bootargs setenv bootargs $bootargs; " \ + "run eval_bootargs; " \ + "setenv machid fe6; " \ + AVB_VERIFY_CHECK \ + AB_SELECT_ARGS \ + "if part start mmc $mmcdev $apart boot_start; then " \ + "part size mmc $mmcdev $apart boot_size; " \ + "mmc read $loadaddr $boot_start $boot_size; " \ + PREPARE_FDT \ + "bootm $loadaddr $ardaddr $fdtaddr; " \ + "else " \ + "echo $apart partition not found; " \ + "exit; " \ + "fi;\0" + +#ifdef CONFIG_OMAP54XX + +#define DEFAULT_FDT_TI_ARGS \ + "findfdt="\ + "if test $board_name = omap5_uevm; then " \ + "setenv fdtfile omap5-uevm.dtb; fi; " \ + "if test $board_name = dra7xx; then " \ + "setenv fdtfile dra7-evm.dtb; fi;" \ + "if test $board_name = dra72x-revc; then " \ + "setenv fdtfile dra72-evm-revc.dtb; fi;" \ + "if test $board_name = dra72x; then " \ + "setenv fdtfile dra72-evm.dtb; fi;" \ + "if test $board_name = dra71x; then " \ + "setenv fdtfile dra71-evm.dtb; fi;" \ + "if test $board_name = dra76x_acd; then " \ + "setenv fdtfile dra76-evm.dtb; fi;" \ + "if test $board_name = beagle_x15; then " \ + "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ + "if test $board_name = beagle_x15_revb1; then " \ + "setenv fdtfile am57xx-beagle-x15-revb1.dtb; fi;" \ + "if test $board_name = beagle_x15_revc; then " \ + "setenv fdtfile am57xx-beagle-x15-revc.dtb; fi;" \ + "if test $board_name = am5729_beagleboneai; then " \ + "setenv fdtfile am5729-beagleboneai.dtb; fi;" \ + "if test $board_name = am572x_idk; then " \ + "setenv fdtfile am572x-idk.dtb; fi;" \ + "if test $board_name = am574x_idk; then " \ + "setenv fdtfile am574x-idk.dtb; fi;" \ + "if test $board_name = am57xx_evm; then " \ + "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ + "if test $board_name = am57xx_evm_reva3; then " \ + "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ + "if test $board_name = am571x_idk; then " \ + "setenv fdtfile am571x-idk.dtb; fi;" \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree to use; fi; \0" + +#define CONFIG_BOOTCOMMAND \ + "if test ${dofastboot} -eq 1; then " \ + "echo Boot fastboot requested, resetting dofastboot ...;" \ + "setenv dofastboot 0; saveenv;" \ + FASTBOOT_CMD \ + "fi;" \ + "if test ${boot_fit} -eq 1; then " \ + "run update_to_fit;" \ + "fi;" \ + "run findfdt; " \ + "run envboot; " \ + "run mmcboot;" \ + "run emmc_linux_boot; " \ + "run emmc_android_boot; " \ + "" + +#endif /* CONFIG_OMAP54XX */ + +#endif /* __TI_BOOT_H */ diff --git a/roms/u-boot/include/environment/ti/dfu.h b/roms/u-boot/include/environment/ti/dfu.h new file mode 100644 index 000000000..3c9057010 --- /dev/null +++ b/roms/u-boot/include/environment/ti/dfu.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com + * + * Environment variable definitions for DFU on TI boards. + */ + +#ifndef __TI_DFU_H +#define __TI_DFU_H + +#define DFU_ALT_INFO_MMC \ + "dfu_alt_info_mmc=" \ + "boot part 0 1;" \ + "rootfs part 0 2;" \ + "MLO fat 0 1;" \ + "MLO.raw raw 0x100 0x200;" \ + "u-boot.img.raw raw 0x300 0x1000;" \ + "u-env.raw raw 0x1300 0x200;" \ + "spl-os-args.raw raw 0x1500 0x200;" \ + "spl-os-image.raw raw 0x1700 0x6900;" \ + "spl-os-args fat 0 1;" \ + "spl-os-image fat 0 1;" \ + "u-boot.img fat 0 1;" \ + "uEnv.txt fat 0 1\0" + +#define DFU_ALT_INFO_EMMC \ + "dfu_alt_info_emmc=" \ + "rawemmc raw 0 3751936;" \ + "boot part 1 1;" \ + "rootfs part 1 2;" \ + "MLO fat 1 1;" \ + "MLO.raw raw 0x100 0x200;" \ + "u-boot.img.raw raw 0x300 0x1000;" \ + "u-env.raw raw 0x1300 0x200;" \ + "spl-os-args.raw raw 0x1500 0x200;" \ + "spl-os-image.raw raw 0x1700 0x6900;" \ + "spl-os-args fat 1 1;" \ + "spl-os-image fat 1 1;" \ + "u-boot.img fat 1 1;" \ + "uEnv.txt fat 1 1\0" + +#ifdef CONFIG_MTD_RAW_NAND +#define DFU_ALT_INFO_NAND \ + "dfu_alt_info_nand=" \ + "SPL part 0 1;" \ + "SPL.backup1 part 0 2;" \ + "SPL.backup2 part 0 3;" \ + "SPL.backup3 part 0 4;" \ + "u-boot part 0 5;" \ + "u-boot-spl-os part 0 6;" \ + "kernel part 0 8;" \ + "rootfs part 0 9\0" +#else +#define DFU_ALT_INFO_NAND "" +#endif + +#define DFU_ALT_INFO_RAM \ + "dfu_alt_info_ram=" \ + "kernel ram 0x80200000 0x4000000;" \ + "fdt ram 0x80f80000 0x80000;" \ + "ramdisk ram 0x81000000 0x4000000\0" + +#define DFU_ALT_INFO_QSPI_XIP \ + "dfu_alt_info_qspi=" \ + "u-boot.bin raw 0x0 0x080000;" \ + "u-boot.backup raw 0x080000 0x080000;" \ + "u-boot-spl-os raw 0x100000 0x010000;" \ + "u-boot-env raw 0x110000 0x010000;" \ + "u-boot-env.backup raw 0x120000 0x010000;" \ + "kernel raw 0x130000 0x800000\0" + +#define DFU_ALT_INFO_QSPI \ + "dfu_alt_info_qspi=" \ + "MLO raw 0x0 0x040000;" \ + "u-boot.img raw 0x040000 0x0100000;" \ + "u-boot-spl-os raw 0x140000 0x080000;" \ + "u-boot-env raw 0x1C0000 0x010000;" \ + "u-boot-env.backup raw 0x1D0000 0x010000;" \ + "kernel raw 0x1E0000 0x800000\0" + +#endif /* __TI_DFU_H */ diff --git a/roms/u-boot/include/environment/ti/k3_dfu.h b/roms/u-boot/include/environment/ti/k3_dfu.h new file mode 100644 index 000000000..2f503b8de --- /dev/null +++ b/roms/u-boot/include/environment/ti/k3_dfu.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * + * Environment variable definitions for DFU on TI K3 SoCs. + * + */ + +#ifndef __TI_DFU_H +#define __TI_DFU_H + +#define DFU_ALT_INFO_MMC \ + "dfu_alt_info_mmc=" \ + "boot part 1 1;" \ + "rootfs part 1 2;" \ + "tiboot3.bin fat 1 1;" \ + "tispl.bin fat 1 1;" \ + "u-boot.img fat 1 1;" \ + "uEnv.txt fat 1 1;" \ + "sysfw.itb fat 1 1\0" + +#define DFU_ALT_INFO_EMMC \ + "dfu_alt_info_emmc=" \ + "rawemmc raw 0 0x800000 mmcpart 1;" \ + "rootfs part 0 1 mmcpart 0;" \ + "tiboot3.bin.raw raw 0x0 0x400 mmcpart 1;" \ + "tispl.bin.raw raw 0x400 0x1000 mmcpart 1;" \ + "u-boot.img.raw raw 0x1400 0x2000 mmcpart 1;" \ + "u-env.raw raw 0x3400 0x100 mmcpart 1;" \ + "sysfw.itb.raw raw 0x3600 0x800 mmcpart 1\0" + +#define DFU_ALT_INFO_OSPI \ + "dfu_alt_info_ospi=" \ + "tiboot3.bin raw 0x0 0x080000;" \ + "tispl.bin raw 0x080000 0x200000;" \ + "u-boot.img raw 0x280000 0x400000;" \ + "u-boot-env raw 0x680000 0x020000;" \ + "sysfw.itb raw 0x6c0000 0x100000;" \ + "rootfs raw 0x800000 0x3800000\0" + +#define DFU_ALT_INFO_RAM \ + "dfu_alt_info_ram=" \ + "tispl.bin ram 0x80080000 0x100000;" \ + "u-boot.img ram 0x81000000 0x100000\0" \ + +#endif /* __TI_DFU_H */ diff --git a/roms/u-boot/include/environment/ti/k3_rproc.h b/roms/u-boot/include/environment/ti/k3_rproc.h new file mode 100644 index 000000000..3418cb42b --- /dev/null +++ b/roms/u-boot/include/environment/ti/k3_rproc.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * + * rproc environment variable definitions for various TI K3 SoCs. + */ + +#ifndef __TI_RPROC_H +#define __TI_RPROC_H + +/* + * should contain a list of tuplies, + * override in board config files with the actual list + */ +#define DEFAULT_RPROCS "" + +#ifdef CONFIG_CMD_REMOTEPROC +#define EXTRA_ENV_RPROC_SETTINGS \ + "dorprocboot=0\0" \ + "boot_rprocs=" \ + "if test ${dorprocboot} -eq 1 && test ${boot} = mmc; then "\ + "rproc init;" \ + "run boot_rprocs_mmc;" \ + "fi;\0" \ + "rproc_load_and_boot_one=" \ + "if load mmc ${bootpart} $loadaddr ${rproc_fw}; then " \ + "if rproc load ${rproc_id} ${loadaddr} ${filesize}; then "\ + "rproc start ${rproc_id};" \ + "fi;" \ + "fi\0" \ + "boot_rprocs_mmc=" \ + "env set rproc_id;" \ + "env set rproc_fw;" \ + "for i in ${rproc_fw_binaries} ; do " \ + "if test -z \"${rproc_id}\" ; then " \ + "env set rproc_id $i;" \ + "else " \ + "env set rproc_fw $i;" \ + "run rproc_load_and_boot_one;" \ + "env set rproc_id;" \ + "env set rproc_fw;" \ + "fi;" \ + "done\0" \ + "rproc_fw_binaries=" \ + DEFAULT_RPROCS \ + "\0" +#else +#define EXTRA_ENV_RPROC_SETTINGS \ + "boot_rprocs= \0" +#endif /* CONFIG_CMD_REMOTEPROC */ + +#endif /* __TI_RPROC_H */ diff --git a/roms/u-boot/include/environment/ti/mmc.h b/roms/u-boot/include/environment/ti/mmc.h new file mode 100644 index 000000000..b86c8dc7a --- /dev/null +++ b/roms/u-boot/include/environment/ti/mmc.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com + * + * Environment variable definitions for MMC/SD on TI boards. + */ + +#ifndef __TI_MMC_H +#define __TI_MMC_H + +#define DEFAULT_MMC_TI_ARGS \ + "mmcdev=0\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "finduuid=part uuid mmc ${bootpart} uuid\0" \ + "args_mmc=run finduuid;setenv bootargs console=${console} " \ + "${optargs} " \ + "root=PARTUUID=${uuid} rw " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ + "bootenvfile=uEnv.txt\0" \ + "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}\0" \ + "loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "envboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootscript; then " \ + "run bootscript;" \ + "else " \ + "if run loadbootenv; then " \ + "echo Loaded env from ${bootenvfile};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "fi;" \ + "fi;\0" \ + "mmcloados=" \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "devnum=${mmcdev}; " \ + "devtype=mmc; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadimage; then " \ + "run args_mmc; " \ + "if test ${boot_fit} -eq 1; then " \ + "run run_fit; " \ + "else " \ + "run mmcloados;" \ + "fi;" \ + "fi;" \ + "fi;\0" + +#endif /* __TI_MMC_H */ diff --git a/roms/u-boot/include/environment/ti/nand.h b/roms/u-boot/include/environment/ti/nand.h new file mode 100644 index 000000000..f2482e8c3 --- /dev/null +++ b/roms/u-boot/include/environment/ti/nand.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * + * Environment variable definitions for NAND on TI boards. + */ + +#ifdef CONFIG_MTD_RAW_NAND +#define NANDARGS \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ + "nand read ${loadaddr} NAND.kernel; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" +#else +#define NANDARGS "" +#endif + diff --git a/roms/u-boot/include/environment/ti/spi.h b/roms/u-boot/include/environment/ti/spi.h new file mode 100644 index 000000000..1681dc863 --- /dev/null +++ b/roms/u-boot/include/environment/ti/spi.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com + * + * Environment variable definitions for SPI on TI boards. + */ + +#ifndef __TI_SPI_H +#define __TI_SPI_H + +#define KEYSTONE_SPI0_MTD_PARTS "spi0.0:1m(u-boot-spl)ro,-(misc);\0" +#define KEYSTONE_SPI1_MTD_PARTS "spi1.0:1m(u-boot-spl)ro,-(misc);\0" + +#endif diff --git a/roms/u-boot/include/environment/ti/ufs.h b/roms/u-boot/include/environment/ti/ufs.h new file mode 100644 index 000000000..6619ec9c8 --- /dev/null +++ b/roms/u-boot/include/environment/ti/ufs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * + * Environment variable definitions for UFS on TI boards. + */ + +#ifndef __TI_UFS_H +#define __TI_UFS_H + +#define DEFAULT_UFS_TI_ARGS \ + "scsirootfstype=ext4 rootwait\0" \ + "ufs_finduuid=part uuid scsi ${bootpart} uuid\0" \ + "args_ufs=setenv devtype scsi;setenv bootpart 1:1;" \ + "run ufs_finduuid;setenv bootargs console = ${console} " \ + "${optargs}" \ + "root=PARTUUID=${uuid} rw " \ + "rootfstype=${scsirootfstype};" \ + "setenv devtype scsi;" \ + "setenv bootpart 1:1\0" \ + "init_ufs=ufs init; scsi scan; run args_ufs\0" \ + "get_kern_ufs=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${name_kern}\0" \ + "get_fdt_ufs=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "get_overlay_ufs=" \ + "fdt address ${fdtaddr};" \ + "fdt resize 0x100000;" \ + "for overlay in $name_overlays;" \ + "do;" \ + "load scsi ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \ + "fdt apply ${dtboaddr};" \ + "done;\0" + +#endif diff --git a/roms/u-boot/include/errno.h b/roms/u-boot/include/errno.h new file mode 100644 index 000000000..652ad6730 --- /dev/null +++ b/roms/u-boot/include/errno.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Samsung Electronics + * Przemyslaw Marczak + */ +#ifndef _ERRNO_H +#define _ERRNO_H + +#include + +#ifdef __SANDBOX__ +#define __errno_asm_label asm("__u_boot_errno") +#else +#define __errno_asm_label +#endif + +extern int errno __errno_asm_label; + +#define __set_errno(val) do { errno = val; } while (0) + +/** + * errno_str() - get description for error number + * + * @errno: error number (negative in case of error) + * Return: string describing the error. If CONFIG_ERRNO_STR is not + * defined an empty string is returned. + */ +#ifdef CONFIG_ERRNO_STR +const char *errno_str(int errno); +#else +static const char error_message[] = ""; + +static inline const char *errno_str(int errno) +{ + return error_message; +} +#endif +#endif /* _ERRNO_H */ diff --git a/roms/u-boot/include/eth_phy.h b/roms/u-boot/include/eth_phy.h new file mode 100644 index 000000000..be6c88152 --- /dev/null +++ b/roms/u-boot/include/eth_phy.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef _eth_phy_h_ +#define _eth_phy_h_ + +#include + +struct udevice; + +int eth_phy_binds_nodes(struct udevice *eth_dev); +int eth_phy_set_mdio_bus(struct udevice *eth_dev, struct mii_dev *mdio_bus); +struct mii_dev *eth_phy_get_mdio_bus(struct udevice *eth_dev); +int eth_phy_get_addr(struct udevice *dev); + +#endif diff --git a/roms/u-boot/include/ethsw.h b/roms/u-boot/include/ethsw.h new file mode 100644 index 000000000..04e002d39 --- /dev/null +++ b/roms/u-boot/include/ethsw.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * Ethernet Switch commands + */ + +#ifndef _CMD_ETHSW_H_ +#define _CMD_ETHSW_H_ + +#define ETHSW_MAX_CMD_PARAMS 20 +#define ETHSW_CMD_PORT_ALL -1 +#define ETHSW_CMD_VLAN_ALL -1 +#define ETHSW_CMD_AGGR_GRP_NONE -1 + +/* IDs used to track keywords in a command */ +enum ethsw_keyword_id { + ethsw_id_key_end = -1, + ethsw_id_help, + ethsw_id_show, + ethsw_id_port, + ethsw_id_enable, + ethsw_id_disable, + ethsw_id_statistics, + ethsw_id_clear, + ethsw_id_learning, + ethsw_id_auto, + ethsw_id_vlan, + ethsw_id_fdb, + ethsw_id_add, + ethsw_id_del, + ethsw_id_flush, + ethsw_id_pvid, + ethsw_id_untagged, + ethsw_id_all, + ethsw_id_none, + ethsw_id_egress, + ethsw_id_tag, + ethsw_id_classified, + ethsw_id_shared, + ethsw_id_private, + ethsw_id_ingress, + ethsw_id_filtering, + ethsw_id_aggr, + ethsw_id_count, /* keep last */ +}; + +enum ethsw_keyword_opt_id { + ethsw_id_port_no = ethsw_id_count + 1, + ethsw_id_vlan_no, + ethsw_id_pvid_no, + ethsw_id_add_del_no, + ethsw_id_add_del_mac, + ethsw_id_aggr_no, + ethsw_id_count_all, /* keep last */ +}; + +struct ethsw_command_def { + int cmd_to_keywords[ETHSW_MAX_CMD_PARAMS]; + int cmd_keywords_nr; + int port; + int vid; + int aggr_grp; + uchar ethaddr[6]; + int (*cmd_function)(struct ethsw_command_def *parsed_cmd); +}; + +/* Structure to be created and initialized by an Ethernet Switch driver */ +struct ethsw_command_func { + const char *ethsw_name; + int (*port_enable)(struct ethsw_command_def *parsed_cmd); + int (*port_disable)(struct ethsw_command_def *parsed_cmd); + int (*port_show)(struct ethsw_command_def *parsed_cmd); + int (*port_stats)(struct ethsw_command_def *parsed_cmd); + int (*port_stats_clear)(struct ethsw_command_def *parsed_cmd); + int (*port_learn)(struct ethsw_command_def *parsed_cmd); + int (*port_learn_show)(struct ethsw_command_def *parsed_cmd); + int (*fdb_show)(struct ethsw_command_def *parsed_cmd); + int (*fdb_flush)(struct ethsw_command_def *parsed_cmd); + int (*fdb_entry_add)(struct ethsw_command_def *parsed_cmd); + int (*fdb_entry_del)(struct ethsw_command_def *parsed_cmd); + int (*pvid_show)(struct ethsw_command_def *parsed_cmd); + int (*pvid_set)(struct ethsw_command_def *parsed_cmd); + int (*vlan_show)(struct ethsw_command_def *parsed_cmd); + int (*vlan_set)(struct ethsw_command_def *parsed_cmd); + int (*port_untag_show)(struct ethsw_command_def *parsed_cmd); + int (*port_untag_set)(struct ethsw_command_def *parsed_cmd); + int (*port_egr_vlan_show)(struct ethsw_command_def *parsed_cmd); + int (*port_egr_vlan_set)(struct ethsw_command_def *parsed_cmd); + int (*vlan_learn_show)(struct ethsw_command_def *parsed_cmd); + int (*vlan_learn_set)(struct ethsw_command_def *parsed_cmd); + int (*port_ingr_filt_show)(struct ethsw_command_def *parsed_cmd); + int (*port_ingr_filt_set)(struct ethsw_command_def *parsed_cmd); + int (*port_aggr_show)(struct ethsw_command_def *parsed_cmd); + int (*port_aggr_set)(struct ethsw_command_def *parsed_cmd); +}; + +int ethsw_define_functions(const struct ethsw_command_func *cmd_func); + +#endif /* _CMD_ETHSW_H_ */ diff --git a/roms/u-boot/include/exception.h b/roms/u-boot/include/exception.h new file mode 100644 index 000000000..a7f21e73d --- /dev/null +++ b/roms/u-boot/include/exception.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * The 'exception' command can be used for testing exception handling. + * + * Copyright (c) 2018, Heinrich Schuchardt + */ + +#include + +static int do_exception(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct cmd_tbl *cp; + + if (argc != 2) + return CMD_RET_USAGE; + + /* drop sub-command parameter */ + argc--; + argv++; + + cp = find_cmd_tbl(argv[0], cmd_sub, ARRAY_SIZE(cmd_sub)); + + if (cp) + return cp->cmd(cmdtp, flag, argc, argv); + + return CMD_RET_USAGE; +} + +static int exception_complete(int argc, char *const argv[], char last_char, + int maxv, char *cmdv[]) +{ + int len = 0; + int i = 0; + struct cmd_tbl *cmdtp; + + switch (argc) { + case 1: + break; + case 2: + len = strlen(argv[1]); + break; + default: + return 0; + } + for (cmdtp = cmd_sub; cmdtp != cmd_sub + ARRAY_SIZE(cmd_sub); cmdtp++) { + if (i >= maxv - 1) + return i; + if (!strncmp(argv[1], cmdtp->name, len)) + cmdv[i++] = cmdtp->name; + } + cmdv[i] = NULL; + return i; +} + +U_BOOT_CMD_COMPLETE( + exception, 2, 0, do_exception, + "Forces an exception to occur", + exception_help_text, exception_complete +); diff --git a/roms/u-boot/include/exports.h b/roms/u-boot/include/exports.h new file mode 100644 index 000000000..550cafdc7 --- /dev/null +++ b/roms/u-boot/include/exports.h @@ -0,0 +1,81 @@ +#ifndef __EXPORTS_H__ +#define __EXPORTS_H__ + +#include +#include +#include + +#ifndef __ASSEMBLY__ +#ifdef CONFIG_PHY_AQUANTIA +#include +#include +#endif + +#include + +struct cmd_tbl; +struct spi_slave; + +/** + * jumptable_init() - Set up the jump table for use by the API + * + * It is called during the generic post-relocation init sequence. + * + * Return: 0 if OK + */ +int jumptable_init(void); + +/* These are declarations of exported functions available in C code */ +unsigned long get_version(void); +int getc(void); +int tstc(void); +void putc(const char); +void puts(const char*); +int printf(const char* fmt, ...); +void install_hdlr(int, interrupt_handler_t, void*); +void free_hdlr(int); +void *malloc(size_t); +#if !CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) +void free(void*); +#endif +void __udelay(unsigned long); +unsigned long get_timer(unsigned long); +int vprintf(const char *, va_list); +unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base); +int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); +char *env_get(const char *name); +int env_set(const char *varname, const char *value); +long simple_strtol(const char *cp, char **endp, unsigned int base); +int strcmp(const char *cs, const char *ct); +unsigned long ustrtoul(const char *cp, char **endp, unsigned int base); +unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base); +#if defined(CONFIG_CMD_I2C) && !CONFIG_IS_ENABLED(DM_I2C) +int i2c_write (uchar, uint, int , uchar* , int); +int i2c_read (uchar, uint, int , uchar* , int); +#endif +#ifdef CONFIG_PHY_AQUANTIA +struct mii_dev *mdio_get_current_dev(void); +struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, + phy_interface_t interface); +struct phy_device *mdio_phydev_for_ethname(const char *ethname); +int miiphy_set_current_dev(const char *devname); +#endif + +void app_startup(char * const *); + +#endif /* ifndef __ASSEMBLY__ */ + +struct jt_funcs { +#define EXPORT_FUNC(impl, res, func, ...) res(*func)(__VA_ARGS__); +#include <_exports.h> +#undef EXPORT_FUNC +}; + + +#define XF_VERSION 9 + +#if defined(CONFIG_X86) +extern gd_t *global_data; +#endif + +#endif /* __EXPORTS_H__ */ diff --git a/roms/u-boot/include/ext4fs.h b/roms/u-boot/include/ext4fs.h new file mode 100644 index 000000000..cb5d9cc0a --- /dev/null +++ b/roms/u-boot/include/ext4fs.h @@ -0,0 +1,169 @@ +/* + * (C) Copyright 2011 - 2012 Samsung Electronics + * EXT4 filesystem implementation in Uboot by + * Uma Shankar + * Manjunatha C Achar + * + * Ext4 Extent data structures are taken from original ext4 fs code + * as found in the linux kernel. + * + * Copyright (c) 2003-2006, Cluster File Systems, Inc, info@clusterfs.com + * Written by Alex Tomas + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __EXT4__ +#define __EXT4__ +#include + +struct disk_partition; + +#define EXT4_INDEX_FL 0x00001000 /* Inode uses hash tree index */ +#define EXT4_EXTENTS_FL 0x00080000 /* Inode uses extents */ +#define EXT4_EXT_MAGIC 0xf30a +#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM 0x0010 +#define EXT4_FEATURE_RO_COMPAT_METADATA_CSUM 0x0400 +#define EXT4_FEATURE_INCOMPAT_EXTENTS 0x0040 +#define EXT4_FEATURE_INCOMPAT_64BIT 0x0080 +#define EXT4_INDIRECT_BLOCKS 12 + +#define EXT4_BG_INODE_UNINIT 0x0001 +#define EXT4_BG_BLOCK_UNINIT 0x0002 +#define EXT4_BG_INODE_ZEROED 0x0004 + +/* + * ext4_inode has i_block array (60 bytes total). + * The first 12 bytes store ext4_extent_header; + * the remainder stores an array of ext4_extent. + */ + +/* + * This is the extent on-disk structure. + * It's used at the bottom of the tree. + */ +struct ext4_extent { + __le32 ee_block; /* first logical block extent covers */ + __le16 ee_len; /* number of blocks covered by extent */ + __le16 ee_start_hi; /* high 16 bits of physical block */ + __le32 ee_start_lo; /* low 32 bits of physical block */ +}; + +/* + * This is index on-disk structure. + * It's used at all the levels except the bottom. + */ +struct ext4_extent_idx { + __le32 ei_block; /* index covers logical blocks from 'block' */ + __le32 ei_leaf_lo; /* pointer to the physical block of the next * + * level. leaf or next index could be there */ + __le16 ei_leaf_hi; /* high 16 bits of physical block */ + __u16 ei_unused; +}; + +/* Each block (leaves and indexes), even inode-stored has header. */ +struct ext4_extent_header { + __le16 eh_magic; /* probably will support different formats */ + __le16 eh_entries; /* number of valid entries */ + __le16 eh_max; /* capacity of store in entries */ + __le16 eh_depth; /* has tree real underlying blocks? */ + __le32 eh_generation; /* generation of the tree */ +}; + +struct ext_filesystem { + /* Total Sector of partition */ + uint64_t total_sect; + /* Block size of partition */ + uint32_t blksz; + /* Inode size of partition */ + uint32_t inodesz; + /* Sectors per Block */ + uint32_t sect_perblk; + /* Group Descriptor size */ + uint16_t gdsize; + /* Group Descriptor Block Number */ + uint32_t gdtable_blkno; + /* Total block groups of partition */ + uint32_t no_blkgrp; + /* No of blocks required for bgdtable */ + uint32_t no_blk_pergdt; + /* Superblock */ + struct ext2_sblock *sb; + /* Block group descritpor table */ + char *gdtable; + + /* Block Bitmap Related */ + unsigned char **blk_bmaps; + long int curr_blkno; + uint16_t first_pass_bbmap; + + /* Inode Bitmap Related */ + unsigned char **inode_bmaps; + int curr_inode_no; + uint16_t first_pass_ibmap; + + /* Journal Related */ + + /* Block Device Descriptor */ + struct blk_desc *dev_desc; +}; + +struct ext_block_cache { + char *buf; + lbaint_t block; + int size; +}; + +extern struct ext2_data *ext4fs_root; +extern struct ext2fs_node *ext4fs_file; + +#if defined(CONFIG_EXT4_WRITE) +extern struct ext2_inode *g_parent_inode; +extern int gd_index; +extern int gindex; + +int ext4fs_init(void); +void ext4fs_deinit(void); +int ext4fs_filename_unlink(char *filename); +int ext4fs_write(const char *fname, const char *buffer, + unsigned long sizebytes, int type); +int ext4_write_file(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actwrite); +int ext4fs_create_link(const char *target, const char *fname); +#endif + +struct ext_filesystem *get_fs(void); +int ext4fs_open(const char *filename, loff_t *len); +int ext4fs_read(char *buf, loff_t offset, loff_t len, loff_t *actread); +int ext4fs_mount(unsigned part_length); +void ext4fs_close(void); +void ext4fs_reinit_global(void); +int ext4fs_ls(const char *dirname); +int ext4fs_exists(const char *filename); +int ext4fs_size(const char *filename, loff_t *size); +void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot); +int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf); +void ext4fs_set_blk_dev(struct blk_desc *rbdd, struct disk_partition *info); +long int read_allocated_block(struct ext2_inode *inode, int fileblock, + struct ext_block_cache *cache); +int ext4fs_probe(struct blk_desc *fs_dev_desc, + struct disk_partition *fs_partition); +int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actread); +int ext4_read_superblock(char *buffer); +int ext4fs_uuid(char *uuid_str); +void ext_cache_init(struct ext_block_cache *cache); +void ext_cache_fini(struct ext_block_cache *cache); +int ext_cache_read(struct ext_block_cache *cache, lbaint_t block, int size); +#endif diff --git a/roms/u-boot/include/ext_common.h b/roms/u-boot/include/ext_common.h new file mode 100644 index 000000000..30a0c2484 --- /dev/null +++ b/roms/u-boot/include/ext_common.h @@ -0,0 +1,224 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 - 2012 Samsung Electronics + * EXT4 filesystem implementation in Uboot by + * Uma Shankar + * Manjunatha C Achar + * + * Data structures and headers for ext4 support have been taken from + * ext2 ls load support in Uboot + * + * (C) Copyright 2004 + * esd gmbh + * Reinhard Arlt + * + * based on code from grub2 fs/ext2.c and fs/fshelp.c by + * GRUB -- GRand Unified Bootloader + * Copyright (C) 2003, 2004 Free Software Foundation, Inc. + */ + +#ifndef __EXT_COMMON__ +#define __EXT_COMMON__ + +#include + +struct cmd_tbl; + +#define SECTOR_SIZE 0x200 +#define LOG2_SECTOR_SIZE 9 + +/* Magic value used to identify an ext2 filesystem. */ +#define EXT2_MAGIC 0xEF53 +/* Amount of indirect blocks in an inode. */ +#define INDIRECT_BLOCKS 12 +/* Maximum lenght of a pathname. */ +#define EXT2_PATH_MAX 4096 +/* Maximum nesting of symlinks, used to prevent a loop. */ +#define EXT2_MAX_SYMLINKCNT 8 + +/* Filetype used in directory entry. */ +#define FILETYPE_UNKNOWN 0 +#define FILETYPE_REG 1 +#define FILETYPE_DIRECTORY 2 +#define FILETYPE_SYMLINK 7 + +/* Filetype information as used in inodes. */ +#define FILETYPE_INO_MASK 0170000 +#define FILETYPE_INO_REG 0100000 +#define FILETYPE_INO_DIRECTORY 0040000 +#define FILETYPE_INO_SYMLINK 0120000 +#define EXT2_ROOT_INO 2 /* Root inode */ + +/* The size of an ext2 block in bytes. */ +#define EXT2_BLOCK_SIZE(data) (1 << LOG2_BLOCK_SIZE(data)) + +/* Log2 size of ext2 block in bytes. */ +#define LOG2_BLOCK_SIZE(data) (le32_to_cpu \ + (data->sblock.log2_block_size) \ + + EXT2_MIN_BLOCK_LOG_SIZE) + +#define EXT2_FT_DIR 2 +#define SUCCESS 1 + +/* Macro-instructions used to manage several block sizes */ +#define EXT2_MIN_BLOCK_LOG_SIZE 10 /* 1024 */ +#define EXT2_MAX_BLOCK_LOG_SIZE 16 /* 65536 */ +#define EXT2_MIN_BLOCK_SIZE (1 << EXT2_MIN_BLOCK_LOG_SIZE) +#define EXT2_MAX_BLOCK_SIZE (1 << EXT2_MAX_BLOCK_LOG_SIZE) + +/* The ext2 superblock. */ +struct ext2_sblock { + __le32 total_inodes; + __le32 total_blocks; + __le32 reserved_blocks; + __le32 free_blocks; + __le32 free_inodes; + __le32 first_data_block; + __le32 log2_block_size; + __le32 log2_fragment_size; + __le32 blocks_per_group; + __le32 fragments_per_group; + __le32 inodes_per_group; + __le32 mtime; + __le32 utime; + __le16 mnt_count; + __le16 max_mnt_count; + __le16 magic; + __le16 fs_state; + __le16 error_handling; + __le16 minor_revision_level; + __le32 lastcheck; + __le32 checkinterval; + __le32 creator_os; + __le32 revision_level; + __le16 uid_reserved; + __le16 gid_reserved; + __le32 first_inode; + __le16 inode_size; + __le16 block_group_number; + __le32 feature_compatibility; + __le32 feature_incompat; + __le32 feature_ro_compat; + __le32 unique_id[4]; + char volume_name[16]; + char last_mounted_on[64]; + __le32 compression_info; + uint8_t prealloc_blocks; + uint8_t prealloc_dir_blocks; + __le16 reserved_gdt_blocks; + uint8_t journal_uuid[16]; + __le32 journal_inode; + __le32 journal_dev; + __le32 last_orphan; + __le32 hash_seed[4]; + uint8_t default_hash_version; + uint8_t journal_backup_type; + __le16 descriptor_size; + __le32 default_mount_options; + __le32 first_meta_block_group; + __le32 mkfs_time; + __le32 journal_blocks[17]; + __le32 total_blocks_high; + __le32 reserved_blocks_high; + __le32 free_blocks_high; + __le16 min_extra_inode_size; + __le16 want_extra_inode_size; + __le32 flags; + __le16 raid_stride; + __le16 mmp_interval; + __le64 mmp_block; + __le32 raid_stripe_width; + uint8_t log2_groups_per_flex; + uint8_t checksum_type; +}; + +struct ext2_block_group { + __le32 block_id; /* Blocks bitmap block */ + __le32 inode_id; /* Inodes bitmap block */ + __le32 inode_table_id; /* Inodes table block */ + __le16 free_blocks; /* Free blocks count */ + __le16 free_inodes; /* Free inodes count */ + __le16 used_dir_cnt; /* Directories count */ + __le16 bg_flags; + __le32 bg_exclude_bitmap; + __le16 bg_block_id_csum; + __le16 bg_inode_id_csum; + __le16 bg_itable_unused; /* Unused inodes count */ + __le16 bg_checksum; /* crc16(s_uuid+group_num+group_desc)*/ + /* following fields only exist if descriptor size is 64 */ + __le32 block_id_high; + __le32 inode_id_high; + __le32 inode_table_id_high; + __le16 free_blocks_high; + __le16 free_inodes_high; + __le16 used_dir_cnt_high; + __le16 bg_itable_unused_high; + __le32 bg_exclude_bitmap_high; + __le16 bg_block_id_csum_high; + __le16 bg_inode_id_csum_high; + __le32 bg_reserved; +}; + +/* The ext2 inode. */ +struct ext2_inode { + __le16 mode; + __le16 uid; + __le32 size; + __le32 atime; + __le32 ctime; + __le32 mtime; + __le32 dtime; + __le16 gid; + __le16 nlinks; + __le32 blockcnt; /* Blocks of either 512 or block_size bytes */ + __le32 flags; + __le32 osd1; + union { + struct datablocks { + __le32 dir_blocks[INDIRECT_BLOCKS]; + __le32 indir_block; + __le32 double_indir_block; + __le32 triple_indir_block; + } blocks; + char symlink[60]; + char inline_data[60]; + } b; + __le32 version; + __le32 acl; + __le32 size_high; /* previously dir_acl, but never used */ + __le32 fragment_addr; + __le32 osd2[3]; +}; + +/* The header of an ext2 directory entry. */ +struct ext2_dirent { + __le32 inode; + __le16 direntlen; + __u8 namelen; + __u8 filetype; +}; + +struct ext2fs_node { + struct ext2_data *data; + struct ext2_inode inode; + int ino; + int inode_read; +}; + +/* Information about a "mounted" ext2 filesystem. */ +struct ext2_data { + struct ext2_sblock sblock; + struct ext2_inode *inode; + struct ext2fs_node diropen; +}; + +extern lbaint_t part_offset; + +int do_ext2ls(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_ext2load(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_ext4_load(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); +int do_ext4_ls(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_ext4_write(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); +#endif diff --git a/roms/u-boot/include/extension_board.h b/roms/u-boot/include/extension_board.h new file mode 100644 index 000000000..c530a0ad8 --- /dev/null +++ b/roms/u-boot/include/extension_board.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 + * Köry Maincent, Bootlin, + */ + +#ifndef __EXTENSION_SUPPORT_H +#define __EXTENSION_SUPPORT_H + +struct extension { + struct list_head list; + char name[32]; + char owner[32]; + char version[32]; + char overlay[32]; + char other[32]; +}; + +/** + * extension_board_scan - Add system-specific function to scan extension board. + * @param extension_list List of extension board information to update. + * @return the number of extension. + * + * This function is called if CONFIG_CMD_EXTENSION is defined. + * Needs to fill the list extension_list with elements. + * Each element need to be allocated to an extension structure. + * + */ +int extension_board_scan(struct list_head *extension_list); + +#endif /* __EXTENSION_SUPPORT_H */ diff --git a/roms/u-boot/include/exynos_lcd.h b/roms/u-boot/include/exynos_lcd.h new file mode 100644 index 000000000..484bd3633 --- /dev/null +++ b/roms/u-boot/include/exynos_lcd.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * exynos_lcd.h - Exynos LCD Controller structures + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef _EXYNOS_LCD_H_ +#define _EXYNOS_LCD_H_ + +enum { + FIMD_RGB_INTERFACE = 1, + FIMD_CPU_INTERFACE = 2, +}; + +enum exynos_fb_rgb_mode_t { + MODE_RGB_P = 0, + MODE_BGR_P = 1, + MODE_RGB_S = 2, + MODE_BGR_S = 3, +}; + +typedef struct vidinfo { + ushort vl_col; /* Number of columns (i.e. 640) */ + ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ + ushort vl_width; /* Width of display area in millimeters */ + ushort vl_height; /* Height of display area in millimeters */ + + /* LCD configuration register */ + u_char vl_freq; /* Frequency */ + u_char vl_clkp; /* Clock polarity */ + u_char vl_oep; /* Output Enable polarity */ + u_char vl_hsp; /* Horizontal Sync polarity */ + u_char vl_vsp; /* Vertical Sync polarity */ + u_char vl_dp; /* Data polarity */ + u_char vl_bpix; /* Bits per pixel */ + + /* Horizontal control register. Timing from data sheet */ + u_char vl_hspw; /* Horz sync pulse width */ + u_char vl_hfpd; /* Wait before of line */ + u_char vl_hbpd; /* Wait end of line */ + + /* Vertical control register. */ + u_char vl_vspw; /* Vertical sync pulse width */ + u_char vl_vfpd; /* Wait before of frame */ + u_char vl_vbpd; /* Wait end of frame */ + u_char vl_cmd_allow_len; /* Wait end of frame */ + + unsigned int win_id; + unsigned int init_delay; + unsigned int power_on_delay; + unsigned int reset_delay; + unsigned int interface_mode; + unsigned int mipi_enabled; + unsigned int dp_enabled; + unsigned int cs_setup; + unsigned int wr_setup; + unsigned int wr_act; + unsigned int wr_hold; + unsigned int logo_on; + unsigned int logo_width; + unsigned int logo_height; + int logo_x_offset; + int logo_y_offset; + unsigned long logo_addr; + unsigned int rgb_mode; + unsigned int resolution; + + /* parent clock name(MPLL, EPLL or VPLL) */ + unsigned int pclk_name; + /* ratio value for source clock from parent clock. */ + unsigned int sclk_div; + + unsigned int dual_lcd_enabled; + struct exynos_fb *reg; + struct exynos_platform_mipi_dsim *dsim_platform_data_dt; +} vidinfo_t; + +#endif diff --git a/roms/u-boot/include/faraday/ftahbc020s.h b/roms/u-boot/include/faraday/ftahbc020s.h new file mode 100644 index 000000000..e628156c1 --- /dev/null +++ b/roms/u-boot/include/faraday/ftahbc020s.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + */ + +/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */ +#ifndef __FTAHBC020S_H +#define __FTAHBC202S_H + +/* Registers Offsets */ + +/* + * AHB Slave BSR, offset: n * 4, n=0~31 + */ +#ifndef __ASSEMBLY__ +struct ftahbc02s { + unsigned int s_bsr[32]; /* 0x00-0x7c - Slave n Base/Size Reg */ + unsigned int pcr; /* 0x80 - Priority Ctrl Reg */ + unsigned int tcrg; /* 0x84 - Transfer Ctrl Reg */ + unsigned int cr; /* 0x88 - Ctrl Reg */ +}; +#endif /* __ASSEMBLY__ */ + +/* + * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register + */ +#define FTAHBC020S_SLAVE_BSR_BASE(x) (((x) & 0xfff) << 20) +#define FTAHBC020S_SLAVE_BSR_SIZE(x) (((x) & 0xf) << 16) +/* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */ +#define FTAHBC020S_BSR_SIZE(x) (ffs(x) - 1) /* size of Addr Space */ + +/* + * FTAHBC020S_PCR - Priority Control Register + */ +#define FTAHBC020S_PCR_PLEVEL_(x) (1 << (x)) /* x: 1-15 */ + +/* + * FTAHBC020S_CR - Interrupt Control Register + */ +#define FTAHBC020S_CR_INTSTS (1 << 24) +#define FTAHBC020S_CR_RESP(x) (((x) & 0x3) << 20) +#define FTAHBC020S_CR_INTSMASK (1 << 16) +#define FTAHBC020S_CR_REMAP (1 << 0) + +#endif /* __FTAHBC020S_H */ diff --git a/roms/u-boot/include/faraday/ftpci100.h b/roms/u-boot/include/faraday/ftpci100.h new file mode 100644 index 000000000..8801bd135 --- /dev/null +++ b/roms/u-boot/include/faraday/ftpci100.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation + * + * Copyright (C) 2010 Andes Technology Corporation + * Gavin Guo, Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + */ + +#ifndef __FTPCI100_H +#define __FTPCI100_H + +/* AHB Control Registers */ +#include +struct ftpci100_ahbc { + unsigned int iosize; /* 0x00 - I/O Space Size Signal */ + unsigned int prot; /* 0x04 - AHB Protection */ + unsigned int rsved[8]; /* 0x08-0x24 - Reserved */ + unsigned int conf; /* 0x28 - PCI Configuration */ + unsigned int data; /* 0x2c - PCI Configuration DATA */ +}; + +/* + * FTPCI100_IOSIZE_REG's constant definitions + */ +#define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */ + +/* + * PCI Configuration Register + */ +#define PCI_INT_MASK 0x4c +#define PCI_MEM_BASE_SIZE1 0x50 +#define PCI_MEM_BASE_SIZE2 0x54 +#define PCI_MEM_BASE_SIZE3 0x58 + +/* + * PCI_INT_MASK's bit definitions + */ +#define PCI_INTA_ENABLE (1 << 22) +#define PCI_INTB_ENABLE (1 << 23) +#define PCI_INTC_ENABLE (1 << 24) +#define PCI_INTD_ENABLE (1 << 25) + +/* + * PCI_MEM_BASE_SIZE1's constant definitions + */ +#define FTPCI100_BASE_ADR_SIZE(x) ((ffs(x) - 1) << 16) /* 1M - 2048M */ + +#define FTPCI100_MAX_FUNCTIONS 20 +#define PCI_IRQ_LINES 4 + +#define MAX_BUS_NUM 256 +#define MAX_DEV_NUM 32 +#define MAX_FUN_NUM 8 + +#define PCI_MAX_BAR_PER_FUNC 6 + +/* + * PCI_MEM_SIZE + */ +#define FTPCI100_MEM_SIZE(x) (ffs(x) << 24) + +/* This definition is used by pci_ftpci_init() */ +#define FTPCI100_BRIDGE_VENDORID 0x159b +#define FTPCI100_BRIDGE_DEVICEID 0x4321 + +void pci_ftpci_init(void); + +struct pcibar { + unsigned int size; + unsigned int addr; +}; + +struct pci_config { + unsigned int bus; + unsigned int dev; /* device */ + unsigned int func; + unsigned int pin; + unsigned short v_id; /* vendor id */ + unsigned short d_id; /* device id */ + struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1]; +}; + +#endif diff --git a/roms/u-boot/include/faraday/ftpmu010.h b/roms/u-boot/include/faraday/ftpmu010.h new file mode 100644 index 000000000..8fc81f902 --- /dev/null +++ b/roms/u-boot/include/faraday/ftpmu010.h @@ -0,0 +1,234 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang + */ + +/* + * Power Management Unit + */ +#ifndef __FTPMU010_H +#define __FTPMU010_H + +#ifndef __ASSEMBLY__ +struct ftpmu010 { + unsigned int IDNMBR0; /* 0x00 */ + unsigned int reserved0; /* 0x04 */ + unsigned int OSCC; /* 0x08 */ + unsigned int PMODE; /* 0x0C */ + unsigned int PMCR; /* 0x10 */ + unsigned int PED; /* 0x14 */ + unsigned int PEDSR; /* 0x18 */ + unsigned int reserved1; /* 0x1C */ + unsigned int PMSR; /* 0x20 */ + unsigned int PGSR; /* 0x24 */ + unsigned int MFPSR; /* 0x28 */ + unsigned int MISC; /* 0x2C */ + unsigned int PDLLCR0; /* 0x30 */ + unsigned int PDLLCR1; /* 0x34 */ + unsigned int AHBMCLKOFF; /* 0x38 */ + unsigned int APBMCLKOFF; /* 0x3C */ + unsigned int DCSRCR0; /* 0x40 */ + unsigned int DCSRCR1; /* 0x44 */ + unsigned int DCSRCR2; /* 0x48 */ + unsigned int SDRAMHTC; /* 0x4C */ + unsigned int PSPR0; /* 0x50 */ + unsigned int PSPR1; /* 0x54 */ + unsigned int PSPR2; /* 0x58 */ + unsigned int PSPR3; /* 0x5C */ + unsigned int PSPR4; /* 0x60 */ + unsigned int PSPR5; /* 0x64 */ + unsigned int PSPR6; /* 0x68 */ + unsigned int PSPR7; /* 0x6C */ + unsigned int PSPR8; /* 0x70 */ + unsigned int PSPR9; /* 0x74 */ + unsigned int PSPR10; /* 0x78 */ + unsigned int PSPR11; /* 0x7C */ + unsigned int PSPR12; /* 0x80 */ + unsigned int PSPR13; /* 0x84 */ + unsigned int PSPR14; /* 0x88 */ + unsigned int PSPR15; /* 0x8C */ + unsigned int AHBDMA_RACCS; /* 0x90 */ + unsigned int reserved2; /* 0x94 */ + unsigned int reserved3; /* 0x98 */ + unsigned int JSS; /* 0x9C */ + unsigned int CFC_RACC; /* 0xA0 */ + unsigned int SSP1_RACC; /* 0xA4 */ + unsigned int UART1TX_RACC; /* 0xA8 */ + unsigned int UART1RX_RACC; /* 0xAC */ + unsigned int UART2TX_RACC; /* 0xB0 */ + unsigned int UART2RX_RACC; /* 0xB4 */ + unsigned int SDC_RACC; /* 0xB8 */ + unsigned int I2SAC97_RACC; /* 0xBC */ + unsigned int IRDATX_RACC; /* 0xC0 */ + unsigned int reserved4; /* 0xC4 */ + unsigned int USBD_RACC; /* 0xC8 */ + unsigned int IRDARX_RACC; /* 0xCC */ + unsigned int IRDA_RACC; /* 0xD0 */ + unsigned int ED0_RACC; /* 0xD4 */ + unsigned int ED1_RACC; /* 0xD8 */ +}; +#endif /* __ASSEMBLY__ */ + +/* + * ID Number 0 Register + */ +#define FTPMU010_ID_A320A 0x03200000 +#define FTPMU010_ID_A320C 0x03200010 +#define FTPMU010_ID_A320D 0x03200030 + +/* + * OSC Control Register + */ +#define FTPMU010_OSCC_OSCH_TRI (1 << 11) +#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) +#define FTPMU010_OSCC_OSCH_OFF (1 << 8) + +#define FTPMU010_OSCC_OSCL_TRI (1 << 3) +#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2) +#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) +#define FTPMU010_OSCC_OSCL_OFF (1 << 0) + +/* + * Power Mode Register + */ +#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) +#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7) +#define FTPMU010_PMODE_FCS (1 << 2) +#define FTPMU010_PMODE_TURBO (1 << 1) +#define FTPMU010_PMODE_SLEEP (1 << 0) + +/* + * Power Manager Status Register + */ +#define FTPMU010_PMSR_SMR (1 << 10) + +#define FTPMU010_PMSR_RDH (1 << 2) +#define FTPMU010_PMSR_PH (1 << 1) +#define FTPMU010_PMSR_CKEHLOW (1 << 0) + +/* + * Multi-Function Port Setting Register + */ +#define FTPMU010_MFPSR_DEBUGSEL (1 << 17) +#define FTPMU010_MFPSR_DMA0PINSEL (1 << 16) +#define FTPMU010_MFPSR_DMA1PINSEL (1 << 15) +#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) +#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) +#define FTPMU010_MFPSR_PWM1PINSEL (1 << 11) +#define FTPMU010_MFPSR_PWM0PINSEL (1 << 10) +#define FTPMU010_MFPSR_IRDACLKSEL (1 << 9) +#define FTPMU010_MFPSR_UARTCLKSEL (1 << 8) +#define FTPMU010_MFPSR_SSPCLKSEL (1 << 6) +#define FTPMU010_MFPSR_I2SCLKSEL (1 << 5) +#define FTPMU010_MFPSR_AC97CLKSEL (1 << 4) +#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) +#define FTPMU010_MFPSR_TRIAHBDIS (1 << 1) +#define FTPMU010_MFPSR_TRIAHBDBG (1 << 0) + +/* + * PLL/DLL Control Register 0 + * Note: + * 1. FTPMU010_PDLLCR0_HCLKOUTDIS: + * Datasheet indicated it starts at bit #21 which was wrong. + * 2. FTPMU010_PDLLCR0_DLLFRAG: + * Datasheet indicated it has 2 bit which was wrong. + */ +#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) +#define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) +#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) +#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) +#define FTPMU010_PDLLCR0_DLLDIS (1 << 16) +#define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12) +#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3) +#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) +#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) +#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) + +/* + * SDRAM Signal Hold Time Control Register + */ +#define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28) +#define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24) +#define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20) +#define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18) +#define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17) +#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16) +#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15) +#define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14) +#define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13) +#define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12) + +#ifndef __ASSEMBLY__ +void ftpmu010_32768osc_enable(void); +void ftpmu010_dlldis_disable(void); +void ftpmu010_mfpsr_diselect_dev(unsigned int dev); +void ftpmu010_mfpsr_select_dev(unsigned int dev); +void ftpmu010_sdram_clk_disable(unsigned int cr0); +void ftpmu010_sdramhtc_set(unsigned int val); +#endif + +#ifdef __ASSEMBLY__ +#define FTPMU010_IDNMBR0 0x00 +#define FTPMU010_reserved0 0x04 +#define FTPMU010_OSCC 0x08 +#define FTPMU010_PMODE 0x0C +#define FTPMU010_PMCR 0x10 +#define FTPMU010_PED 0x14 +#define FTPMU010_PEDSR 0x18 +#define FTPMU010_reserved1 0x1C +#define FTPMU010_PMSR 0x20 +#define FTPMU010_PGSR 0x24 +#define FTPMU010_MFPSR 0x28 +#define FTPMU010_MISC 0x2C +#define FTPMU010_PDLLCR0 0x30 +#define FTPMU010_PDLLCR1 0x34 +#define FTPMU010_AHBMCLKOFF 0x38 +#define FTPMU010_APBMCLKOFF 0x3C +#define FTPMU010_DCSRCR0 0x40 +#define FTPMU010_DCSRCR1 0x44 +#define FTPMU010_DCSRCR2 0x48 +#define FTPMU010_SDRAMHTC 0x4C +#define FTPMU010_PSPR0 0x50 +#define FTPMU010_PSPR1 0x54 +#define FTPMU010_PSPR2 0x58 +#define FTPMU010_PSPR3 0x5C +#define FTPMU010_PSPR4 0x60 +#define FTPMU010_PSPR5 0x64 +#define FTPMU010_PSPR6 0x68 +#define FTPMU010_PSPR7 0x6C +#define FTPMU010_PSPR8 0x70 +#define FTPMU010_PSPR9 0x74 +#define FTPMU010_PSPR10 0x78 +#define FTPMU010_PSPR11 0x7C +#define FTPMU010_PSPR12 0x80 +#define FTPMU010_PSPR13 0x84 +#define FTPMU010_PSPR14 0x88 +#define FTPMU010_PSPR15 0x8C +#define FTPMU010_AHBDMA_RACCS 0x90 +#define FTPMU010_reserved2 0x94 +#define FTPMU010_reserved3 0x98 +#define FTPMU010_JSS 0x9C +#define FTPMU010_CFC_RACC 0xA0 +#define FTPMU010_SSP1_RACC 0xA4 +#define FTPMU010_UART1TX_RACC 0xA8 +#define FTPMU010_UART1RX_RACC 0xAC +#define FTPMU010_UART2TX_RACC 0xB0 +#define FTPMU010_UART2RX_RACC 0xB4 +#define FTPMU010_SDC_RACC 0xB8 +#define FTPMU010_I2SAC97_RACC 0xBC +#define FTPMU010_IRDATX_RACC 0xC0 +#define FTPMU010_reserved4 0xC4 +#define FTPMU010_USBD_RACC 0xC8 +#define FTPMU010_IRDARX_RACC 0xCC +#define FTPMU010_IRDA_RACC 0xD0 +#define FTPMU010_ED0_RACC 0xD4 +#define FTPMU010_ED1_RACC 0xD8 +#endif /* __ASSEMBLY__ */ + +#endif /* __FTPMU010_H */ diff --git a/roms/u-boot/include/faraday/ftsdc010.h b/roms/u-boot/include/faraday/ftsdc010.h new file mode 100644 index 000000000..30726dab8 --- /dev/null +++ b/roms/u-boot/include/faraday/ftsdc010.h @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Faraday FTSDC010 Secure Digital Memory Card Host Controller + * + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + */ + +#ifndef __FTSDC010_H +#define __FTSDC010_H + +#ifndef __ASSEMBLY__ + +/* sd controller register */ +#include +struct ftsdc010_mmc { + unsigned int cmd; /* 0x00 - command reg */ + unsigned int argu; /* 0x04 - argument reg */ + unsigned int rsp0; /* 0x08 - response reg0 */ + unsigned int rsp1; /* 0x0c - response reg1 */ + unsigned int rsp2; /* 0x10 - response reg2 */ + unsigned int rsp3; /* 0x14 - response reg3 */ + unsigned int rsp_cmd; /* 0x18 - responded cmd reg */ + unsigned int dcr; /* 0x1c - data control reg */ + unsigned int dtr; /* 0x20 - data timer reg */ + unsigned int dlr; /* 0x24 - data length reg */ + unsigned int status; /* 0x28 - status reg */ + unsigned int clr; /* 0x2c - clear reg */ + unsigned int int_mask; /* 0x30 - intrrupt mask reg */ + unsigned int pcr; /* 0x34 - power control reg */ + unsigned int ccr; /* 0x38 - clock contorl reg */ + unsigned int bwr; /* 0x3c - bus width reg */ + unsigned int dwr; /* 0x40 - data window reg */ +#ifndef CONFIG_FTSDC010_SDIO + unsigned int feature; /* 0x44 - feature reg */ + unsigned int rev; /* 0x48 - revision reg */ +#else + unsigned int mmc_intr_time; /* 0x44 - MMC int resp time reg */ + unsigned int gpo; /* 0x48 - gerenal purpose output */ + unsigned int reserved[8]; /* 0x50 - 0x68 reserved */ + unsigned int sdio_ctrl1; /* 0x6c - SDIO control reg 1 */ + unsigned int sdio_ctrl2; /* 0x70 - SDIO control reg 2 */ + unsigned int sdio_status; /* 0x74 - SDIO status regi */ + unsigned int reserved1[9]; /* 0x78 - 0x98 reserved */ + unsigned int feature; /* 0x9c - feature reg */ + unsigned int rev; /* 0xa0 - revision reg */ +#endif /* CONFIG_FTSDC010_SDIO */ +}; + +struct mmc_host { + struct ftsdc010_mmc *reg; + unsigned int version; /* SDHCI spec. version */ + unsigned int clock; /* Current clock (MHz) */ + unsigned int fifo_len; /* bytes */ + unsigned int last_opcode; /* Last OP Code */ + unsigned int card_type; /* Card type */ +}; + +/* functions */ +int ftsdc010_mmc_init(int dev_index); + +#endif /* __ASSEMBLY__ */ + +/* global defines */ +#define FTSDC010_CMD_RETRY 0x100000 +#define FTSDC010_PIO_RETRY 100 /* pio retry times */ +#define FTSDC010_DELAY_UNIT 100 /* 100 us */ + +/* define from Linux kernel - include/linux/mmc/card.h */ +#define MMC_TYPE_SDIO 2 /* SDIO card */ + +/* define for mmc layer */ +#define MMC_DATA_BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ) + +/* this part is strange */ +#define FTSDC010_SDIO_CTRL1_REG 0x0000006C +#define FTSDC010_SDIO_CTRL2_REG 0x0000006C +#define FTSDC010_SDIO_STATUS_REG 0x00000070 + +/* 0x00 - command register */ +#define FTSDC010_CMD_IDX(x) (((x) & 0x3f) << 0) +#define FTSDC010_CMD_NEED_RSP (1 << 6) +#define FTSDC010_CMD_LONG_RSP (1 << 7) +#define FTSDC010_CMD_APP_CMD (1 << 8) +#define FTSDC010_CMD_CMD_EN (1 << 9) +#define FTSDC010_CMD_SDC_RST (1 << 10) +#define FTSDC010_CMD_MMC_INT_STOP (1 << 11) + +/* 0x18 - responded command register */ +#define FTSDC010_RSP_CMD_IDX(x) (((x) >> 0) & 0x3f) +#define FTSDC010_RSP_CMD_APP (1 << 6) + +/* 0x1c - data control register */ +#define FTSDC010_DCR_BLK_SIZE(x) (((x) & 0xf) << 0) +#define FTSDC010_DCR_DATA_WRITE (1 << 4) +#define FTSDC010_DCR_DMA_EN (1 << 5) +#define FTSDC010_DCR_DATA_EN (1 << 6) +#ifdef CONFIG_FTSDC010_SDIO +#define FTSDC010_DCR_FIFOTH (1 << 7) +#define FTSDC010_DCR_DMA_TYPE(x) (((x) & 0x3) << 8) +#define FTSDC010_DCR_FIFO_RST (1 << 10) +#endif /* CONFIG_FTSDC010_SDIO */ + +#define FTSDC010_DCR_DMA_TYPE_1 0x0 /* Single r/w */ +#define FTSDC010_DCR_DMA_TYPE_4 0x1 /* Burst 4 r/w */ +#define FTSDC010_DCR_DMA_TYPE_8 0x2 /* Burst 8 r/w */ + +#define FTSDC010_DCR_BLK_BYTES(x) (ffs(x) - 1) /* 1B - 2048B */ + +/* CPRM related define */ +#define FTSDC010_CPRM_DATA_CHANGE_ENDIAN_EN 0x000008 +#define FTSDC010_CPRM_DATA_SWAP_HL_EN 0x000010 + +/* 0x28 - status register */ +#define FTSDC010_STATUS_RSP_CRC_FAIL (1 << 0) +#define FTSDC010_STATUS_DATA_CRC_FAIL (1 << 1) +#define FTSDC010_STATUS_RSP_TIMEOUT (1 << 2) +#define FTSDC010_STATUS_DATA_TIMEOUT (1 << 3) +#define FTSDC010_STATUS_RSP_CRC_OK (1 << 4) +#define FTSDC010_STATUS_DATA_CRC_OK (1 << 5) +#define FTSDC010_STATUS_CMD_SEND (1 << 6) +#define FTSDC010_STATUS_DATA_END (1 << 7) +#define FTSDC010_STATUS_FIFO_URUN (1 << 8) +#define FTSDC010_STATUS_FIFO_ORUN (1 << 9) +#define FTSDC010_STATUS_CARD_CHANGE (1 << 10) +#define FTSDC010_STATUS_CARD_DETECT (1 << 11) +#define FTSDC010_STATUS_WRITE_PROT (1 << 12) +#ifdef CONFIG_FTSDC010_SDIO +#define FTSDC010_STATUS_CP_READY (1 << 13) /* reserved ? */ +#define FTSDC010_STATUS_CP_BUF_READY (1 << 14) /* reserved ? */ +#define FTSDC010_STATUS_PLAIN_TEXT_READY (1 << 15) /* reserved ? */ +#define FTSDC010_STATUS_SDIO_IRPT (1 << 16) /* SDIO card intr */ +#define FTSDC010_STATUS_DATA0_STATUS (1 << 17) +#endif /* CONFIG_FTSDC010_SDIO */ +#define FTSDC010_STATUS_RSP_ERROR \ + (FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_RSP_TIMEOUT) +#define FTSDC010_STATUS_RSP_MASK \ + (FTSDC010_STATUS_RSP_ERROR | FTSDC010_STATUS_RSP_CRC_OK) +#define FTSDC010_STATUS_DATA_ERROR \ + (FTSDC010_STATUS_DATA_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT) +#define FTSDC010_STATUS_DATA_MASK \ + (FTSDC010_STATUS_DATA_ERROR | FTSDC010_STATUS_DATA_CRC_OK \ + | FTSDC010_STATUS_DATA_END) + +/* 0x2c - clear register */ +#define FTSDC010_CLR_RSP_CRC_FAIL (1 << 0) +#define FTSDC010_CLR_DATA_CRC_FAIL (1 << 1) +#define FTSDC010_CLR_RSP_TIMEOUT (1 << 2) +#define FTSDC010_CLR_DATA_TIMEOUT (1 << 3) +#define FTSDC010_CLR_RSP_CRC_OK (1 << 4) +#define FTSDC010_CLR_DATA_CRC_OK (1 << 5) +#define FTSDC010_CLR_CMD_SEND (1 << 6) +#define FTSDC010_CLR_DATA_END (1 << 7) +#define FTSDC010_STATUS_FIFO_URUN (1 << 8) /* reserved ? */ +#define FTSDC010_STATUS_FIFO_ORUN (1 << 9) /* reserved ? */ +#define FTSDC010_CLR_CARD_CHANGE (1 << 10) +#ifdef CONFIG_FTSDC010_SDIO +#define FTSDC010_CLR_SDIO_IRPT (1 << 16) +#endif /* CONFIG_FTSDC010_SDIO */ + +/* 0x30 - interrupt mask register */ +#define FTSDC010_INT_MASK_RSP_CRC_FAIL (1 << 0) +#define FTSDC010_INT_MASK_DATA_CRC_FAIL (1 << 1) +#define FTSDC010_INT_MASK_RSP_TIMEOUT (1 << 2) +#define FTSDC010_INT_MASK_DATA_TIMEOUT (1 << 3) +#define FTSDC010_INT_MASK_RSP_CRC_OK (1 << 4) +#define FTSDC010_INT_MASK_DATA_CRC_OK (1 << 5) +#define FTSDC010_INT_MASK_CMD_SEND (1 << 6) +#define FTSDC010_INT_MASK_DATA_END (1 << 7) +#define FTSDC010_INT_MASK_FIFO_URUN (1 << 8) +#define FTSDC010_INT_MASK_FIFO_ORUN (1 << 9) +#define FTSDC010_INT_MASK_CARD_CHANGE (1 << 10) +#ifdef CONFIG_FTSDC010_SDIO +#define FTSDC010_INT_MASK_CP_READY (1 << 13) +#define FTSDC010_INT_MASK_CP_BUF_READY (1 << 14) +#define FTSDC010_INT_MASK_PLAIN_TEXT_READY (1 << 15) +#define FTSDC010_INT_MASK_SDIO_IRPT (1 << 16) +#define FTSDC010_STATUS_DATA0_STATUS (1 << 17) +#endif /* CONFIG_FTSDC010_SDIO */ + +/* ? */ +#define FTSDC010_CARD_INSERT 0x0 +#define FTSDC010_CARD_REMOVE FTSDC010_STATUS_REG_CARD_DETECT + +/* 0x34 - power control register */ +#define FTSDC010_PCR_POWER(x) (((x) & 0xf) << 0) +#define FTSDC010_PCR_POWER_ON (1 << 4) + +/* 0x38 - clock control register */ +#define FTSDC010_CCR_CLK_DIV(x) (((x) & 0x7f) << 0) +#define FTSDC010_CCR_CLK_SD (1 << 7) /* 0: MMC, 1: SD */ +#define FTSDC010_CCR_CLK_DIS (1 << 8) +#define FTSDC010_CCR_CLK_HISPD (1 << 9) /* high speed */ + +/* card type */ +#define FTSDC010_CARD_TYPE_SD FTSDC010_CLOCK_REG_CARD_TYPE +#define FTSDC010_CARD_TYPE_MMC 0x0 + +/* 0x3c - bus width register */ +#define FTSDC010_BWR_MODE_1BIT (1 << 0) /* 1 bit mode enabled */ +#define FTSDC010_BWR_MODE_8BIT (1 << 1) /* 8 bit mode enabled */ +#define FTSDC010_BWR_MODE_4BIT (1 << 2) /* 4 bit mode enabled */ +#define FTSDC010_BWR_MODE_MASK (7 << 0) +#define FTSDC010_BWR_MODE_SHIFT (0) +#define FTSDC010_BWR_CAPS_1BIT (0 << 3) /* 1 bits mode supported */ +#define FTSDC010_BWR_CAPS_4BIT (1 << 3) /* 1,4 bits mode supported */ +#define FTSDC010_BWR_CAPS_8BIT (2 << 3) /* 1,4,8 bits mode supported */ +#define FTSDC010_BWR_CAPS_MASK (3 << 3) +#define FTSDC010_BWR_CAPS_SHIFT (3) +#define FTSDC010_BWR_CARD_DETECT (1 << 5) + +/* 0x44 or 0x9c - feature register */ +#define FTSDC010_FEATURE_FIFO_DEPTH(x) (((x) >> 0) & 0xff) +#define FTSDC010_FEATURE_CPRM_FUNCTION (1 << 8) + +#define FTSDC010_FIFO_DEPTH_4 0x04 +#define FTSDC010_FIFO_DEPTH_8 0x08 +#define FTSDC010_FIFO_DEPTH_16 0x10 + +/* 0x48 or 0xa0 - revision register */ +#define FTSDC010_REV_REVISION(x) (((x) & 0xff) >> 0) +#define FTSDC010_REV_MINOR(x) (((x) & 0xff00) >> 8) +#define FTSDC010_REV_MAJOR(x) (((x) & 0xffff0000) >> 16) + +#ifdef CONFIG_FTSDC010_SDIO +/* 0x44 - general purpose output */ +#define FTSDC010_GPO_PORT(x) (((x) & 0xf) << 0) + +/* 0x6c - sdio control register 1 */ +#define FTSDC010_SDIO_CTRL1_SDIO_BLK_SIZE(x) (((x) & 0xfff) << 0) +#define FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE (1 << 12) +#define FTSDC010_SDIO_CTRL1_READ_WAIT_EN (1 << 13) +#define FTSDC010_SDIO_CTRL1_SDIO_ENABLE (1 << 14) +#define FTSDC010_SDIO_CTRL1_SDIO_BLK_NO(x) (((x) & 0x1ff) << 15) + +/* 0x70 - sdio control register 2 */ +#define FTSDC010_SDIO_CTRL2_SUSP_READ_WAIT (1 << 0) +#define FTSDC010_SDIO_CTRL2_SUSP_CMD_ABORT (1 << 1) + +/* 0x74 - sdio status register */ +#define FTSDC010_SDIO_STATUS_SDIO_BLK_CNT(x) (((x) >> 0) & 0x1ffff) +#define FTSDC010_SDIO_STATUS_FIFO_REMAIN_NO(x) (((x) >> 17) & 0xef) + +#endif /* CONFIG_FTSDC010_SDIO */ + +#endif /* __FTSDC010_H */ diff --git a/roms/u-boot/include/faraday/ftsdmc020.h b/roms/u-boot/include/faraday/ftsdmc020.h new file mode 100644 index 000000000..d74da16ef --- /dev/null +++ b/roms/u-boot/include/faraday/ftsdmc020.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang + */ + +/* + * SDRAM Controller + */ +#ifndef __FTSDMC020_H +#define __FTSDMC020_H + +#define FTSDMC020_OFFSET_TP0 0x00 +#define FTSDMC020_OFFSET_TP1 0x04 +#define FTSDMC020_OFFSET_CR 0x08 +#define FTSDMC020_OFFSET_BANK0_BSR 0x0C +#define FTSDMC020_OFFSET_BANK1_BSR 0x10 +#define FTSDMC020_OFFSET_BANK2_BSR 0x14 +#define FTSDMC020_OFFSET_BANK3_BSR 0x18 +#define FTSDMC020_OFFSET_BANK4_BSR 0x1C +#define FTSDMC020_OFFSET_BANK5_BSR 0x20 +#define FTSDMC020_OFFSET_BANK6_BSR 0x24 +#define FTSDMC020_OFFSET_BANK7_BSR 0x28 +#define FTSDMC020_OFFSET_ACR 0x34 + +/* + * Timing Parametet 0 Register + */ +#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) +#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) +#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) +#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) +#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) +#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) + +/* + * Timing Parametet 1 Register + */ +#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) +#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) +#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) + +/* + * Configuration Register + */ +#define FTSDMC020_CR_SREF (1 << 0) +#define FTSDMC020_CR_PWDN (1 << 1) +#define FTSDMC020_CR_ISMR (1 << 2) +#define FTSDMC020_CR_IREF (1 << 3) +#define FTSDMC020_CR_IPREC (1 << 4) +#define FTSDMC020_CR_REFTYPE (1 << 5) + +/* + * SDRAM External Bank Base/Size Register + */ +#define FTSDMC020_BANK_ENABLE (1 << 28) + +#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) + +#define FTSDMC020_BANK_DDW_X4 (0 << 12) +#define FTSDMC020_BANK_DDW_X8 (1 << 12) +#define FTSDMC020_BANK_DDW_X16 (2 << 12) +#define FTSDMC020_BANK_DDW_X32 (3 << 12) + +#define FTSDMC020_BANK_DSZ_16M (0 << 8) +#define FTSDMC020_BANK_DSZ_64M (1 << 8) +#define FTSDMC020_BANK_DSZ_128M (2 << 8) +#define FTSDMC020_BANK_DSZ_256M (3 << 8) + +#define FTSDMC020_BANK_MBW_8 (0 << 4) +#define FTSDMC020_BANK_MBW_16 (1 << 4) +#define FTSDMC020_BANK_MBW_32 (2 << 4) + +#define FTSDMC020_BANK_SIZE_1M 0x0 +#define FTSDMC020_BANK_SIZE_2M 0x1 +#define FTSDMC020_BANK_SIZE_4M 0x2 +#define FTSDMC020_BANK_SIZE_8M 0x3 +#define FTSDMC020_BANK_SIZE_16M 0x4 +#define FTSDMC020_BANK_SIZE_32M 0x5 +#define FTSDMC020_BANK_SIZE_64M 0x6 +#define FTSDMC020_BANK_SIZE_128M 0x7 +#define FTSDMC020_BANK_SIZE_256M 0x8 + +/* + * Arbiter Control Register + */ +#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) +#define FTSDMC020_ACR_TOE (1 << 8) + +#endif /* __FTSDMC020_H */ diff --git a/roms/u-boot/include/faraday/ftsdmc021.h b/roms/u-boot/include/faraday/ftsdmc021.h new file mode 100644 index 000000000..e0e5eb339 --- /dev/null +++ b/roms/u-boot/include/faraday/ftsdmc021.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang + * + * (C) Copyright 2011 Andes Technology Corp + * Macpaul Lin + */ + +/* + * FTSDMC021 - SDRAM Controller + */ +#ifndef __FTSDMC021_H +#define __FTSDMC021_H + +#ifndef __ASSEMBLY__ +#include +struct ftsdmc021 { + unsigned int tp1; /* 0x00 - SDRAM Timing Parameter 1 */ + unsigned int tp2; /* 0x04 - SDRAM Timing Parameter 2 */ + unsigned int cr1; /* 0x08 - SDRAM Configuration Reg 1 */ + unsigned int cr2; /* 0x0c - SDRAM Configuration Reg 2 */ + unsigned int bank0_bsr; /* 0x10 - Ext. Bank Base/Size Reg 0 */ + unsigned int bank1_bsr; /* 0x14 - Ext. Bank Base/Size Reg 1 */ + unsigned int bank2_bsr; /* 0x18 - Ext. Bank Base/Size Reg 2 */ + unsigned int bank3_bsr; /* 0x1c - Ext. Bank Base/Size Reg 3 */ + unsigned int bank4_bsr; /* 0x20 - Ext. Bank Base/Size Reg 4 */ + unsigned int bank5_bsr; /* 0x24 - Ext. Bank Base/Size Reg 5 */ + unsigned int bank6_bsr; /* 0x28 - Ext. Bank Base/Size Reg 6 */ + unsigned int bank7_bsr; /* 0x2c - Ext. Bank Base/Size Reg 7 */ + unsigned int ragr; /* 0x30 - Read Arbitration Group Reg */ + unsigned int frr; /* 0x34 - Flush Request Register */ + unsigned int ebisr; /* 0x38 - EBI Support Register */ + unsigned int rsved[25]; /* 0x3c-0x9c - Reserved */ + unsigned int crr; /* 0x100 - Controller Revision Reg */ + unsigned int cfr; /* 0x104 - Controller Feature Reg */ +}; +#endif /* __ASSEMBLY__ */ + +/* + * Timing Parameter 1 Register + */ +#define FTSDMC021_TP1_TCL(x) ((x) & 0x3) /* CAS Latency */ +#define FTSDMC021_TP1_TWR(x) (((x) & 0x3) << 4) /* W-Recovery Time */ +#define FTSDMC021_TP1_TRF(x) (((x) & 0xf) << 8) /* Auto-Refresh Cycle */ +#define FTSDMC021_TP1_TRCD(x) (((x) & 0x7) << 12) /* RAS-to-CAS Delay */ +#define FTSDMC021_TP1_TRP(x) (((x) & 0xf) << 16) /* Precharge Cycle */ +#define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20) + +/* + * Timing Parameter 2 Register + */ +#define FTSDMC021_TP2_REF_INTV(x) ((x) & 0xffff) /* Refresh interval */ +/* b(16:19) - Initial Refresh Times */ +#define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16) +/* b(20:23) - Initial Pre-Charge Times */ +#define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20) + +/* + * SDRAM Configuration Register 1 + */ +#define FTSDMC021_CR1_BNKSIZE(x) ((x) & 0xf) /* Bank Size */ +#define FTSDMC021_CR1_MBW(x) (((x) & 0x3) << 4) /* Bus Width */ +#define FTSDMC021_CR1_DSZ(x) (((x) & 0x7) << 8) /* SDRAM Size */ +#define FTSDMC021_CR1_DDW(x) (((x) & 0x3) << 12) /* Data Width */ +/* b(16) MA2T: Double Memory Address Cycle Enable */ +#define FTSDMC021_CR1_MA2T(x) (1 << 16) +/* The value of b(0:3)CR1: 1M-512M, must be power of 2 */ +#define FTSDMC021_BANK_SIZE(x) (ffs(x) - 1) + +/* + * Configuration Register 2 + */ +#define FTSDMC021_CR2_SREF (1 << 0) /* Self-Refresh Mode */ +#define FTSDMC021_CR2_PWDN (1 << 1) /* Power Down Operation Mode */ +#define FTSDMC021_CR2_ISMR (1 << 2) /* Start Set-Mode-Register */ +#define FTSDMC021_CR2_IREF (1 << 3) /* Init Refresh Start Flag */ +#define FTSDMC021_CR2_IPREC (1 << 4) /* Init Pre-Charge Start Flag */ +#define FTSDMC021_CR2_REFTYPE (1 << 5) + +/* + * SDRAM External Bank Base/Size Register + */ +#define FTSDMC021_BANK_ENABLE (1 << 12) + +/* 12-bit base address of external bank. + * Default value is 0x800. + * The 12-bit equals to the haddr[31:20] of AHB address bus. */ +#define FTSDMC021_BANK_BASE(x) ((x) & 0xfff) + +/* + * Read Arbitration Grant Window Register + */ +#define FTSDMC021_RAGR_CH1GW(x) (((x) & 0xff) << 0) +#define FTSDMC021_RAGR_CH2GW(x) (((x) & 0xff) << 4) +#define FTSDMC021_RAGR_CH3GW(x) (((x) & 0xff) << 8) +#define FTSDMC021_RAGR_CH4GW(x) (((x) & 0xff) << 12) +#define FTSDMC021_RAGR_CH5GW(x) (((x) & 0xff) << 16) +#define FTSDMC021_RAGR_CH6GW(x) (((x) & 0xff) << 20) +#define FTSDMC021_RAGR_CH7GW(x) (((x) & 0xff) << 24) +#define FTSDMC021_RAGR_CH8GW(x) (((x) & 0xff) << 28) + +/* + * Flush Request Register + */ +#define FTSDMC021_FRR_FLUSHCHN(x) (((x) & 0x7) << 0) +#define FTSDMC021_FRR_FLUSHCMPLT (1 << 3) /* Flush Req Flag */ + +/* + * External Bus Interface Support Register (EBISR) + */ +#define FTSDMC021_EBISR_MR(x) ((x) & 0xfff) /* Far-end mode */ +#define FTSDMC021_EBISR_PRSMR (1 << 12) /* Pre-SMR */ +#define FTSDMC021_EBISR_POPREC (1 << 13) +#define FTSDMC021_EBISR_POSMR (1 << 14) /* Post-SMR */ + +/* + * Controller Revision Register (CRR, Read Only) + */ +#define FTSDMC021_CRR_REV_VER (((x) >> 0) & 0xff) +#define FTSDMC021_CRR_MINOR_VER (((x) >> 8) & 0xff) +#define FTSDMC021_CRR_MAJOR_VER (((x) >> 16) & 0xff) + +/* + * Controller Feature Register (CFR, Read Only) + */ +#define FTSDMC021_CFR_EBNK (((x) >> 0) & 0xf) +#define FTSDMC021_CFR_CHN (((x) >> 8) & 0xf) +#define FTSDMC021_CFR_EBI (((x) >> 16) & 0x1) +#define FTSDMC021_CFR_CH1_FDEPTH (((x) >> 24) & 0x1) +#define FTSDMC021_CFR_CH2_FDEPTH (((x) >> 25) & 0x1) +#define FTSDMC021_CFR_CH3_FDEPTH (((x) >> 26) & 0x1) +#define FTSDMC021_CFR_CH4_FDEPTH (((x) >> 27) & 0x1) +#define FTSDMC021_CFR_CH5_FDEPTH (((x) >> 28) & 0x1) +#define FTSDMC021_CFR_CH6_FDEPTH (((x) >> 29) & 0x1) +#define FTSDMC021_CFR_CH7_FDEPTH (((x) >> 30) & 0x1) +#define FTSDMC021_CFR_CH8_FDEPTH (((x) >> 31) & 0x1) + +#endif /* __FTSDMC021_H */ diff --git a/roms/u-boot/include/faraday/ftsmc020.h b/roms/u-boot/include/faraday/ftsmc020.h new file mode 100644 index 000000000..f902a791e --- /dev/null +++ b/roms/u-boot/include/faraday/ftsmc020.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang + */ + +/* + * Static Memory Controller + */ +#ifndef __FTSMC020_H +#define __FTSMC020_H + +#ifndef __ASSEMBLY__ + +struct ftsmc020_bank { + unsigned int cr; + unsigned int tpr; +}; + +struct ftsmc020 { + struct ftsmc020_bank bank[4]; /* 0x00 - 0x1c */ + unsigned int pad[8]; /* 0x20 - 0x3c */ + unsigned int ssr; /* 0x40 */ +}; + +void ftsmc020_init(void); + +#endif /* __ASSEMBLY__ */ + +/* + * Memory Bank Configuration Register + */ +#define FTSMC020_BANK_ENABLE (1 << 28) +#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) + +#define FTSMC020_BANK_WPROT (1 << 11) + +#define FTSMC020_BANK_TYPE1 (1 << 10) +#define FTSMC020_BANK_TYPE2 (1 << 9) +#define FTSMC020_BANK_TYPE3 (1 << 8) + +#define FTSMC020_BANK_SIZE_32K (0xb << 4) +#define FTSMC020_BANK_SIZE_64K (0xc << 4) +#define FTSMC020_BANK_SIZE_128K (0xd << 4) +#define FTSMC020_BANK_SIZE_256K (0xe << 4) +#define FTSMC020_BANK_SIZE_512K (0xf << 4) +#define FTSMC020_BANK_SIZE_1M (0x0 << 4) +#define FTSMC020_BANK_SIZE_2M (0x1 << 4) +#define FTSMC020_BANK_SIZE_4M (0x2 << 4) +#define FTSMC020_BANK_SIZE_8M (0x3 << 4) +#define FTSMC020_BANK_SIZE_16M (0x4 << 4) +#define FTSMC020_BANK_SIZE_32M (0x5 << 4) +#define FTSMC020_BANK_SIZE_64M (0x6 << 4) + +#define FTSMC020_BANK_MBW_8 (0x0 << 0) +#define FTSMC020_BANK_MBW_16 (0x1 << 0) +#define FTSMC020_BANK_MBW_32 (0x2 << 0) + +/* + * Memory Bank Timing Parameter Register + */ +#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) +#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) +#define FTSMC020_TPR_RBE (1 << 20) +#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) +#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) +#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) +#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) +#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) +#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) +#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) + +#endif /* __FTSMC020_H */ diff --git a/roms/u-boot/include/faraday/fttmr010.h b/roms/u-boot/include/faraday/fttmr010.h new file mode 100644 index 000000000..ec1c9895f --- /dev/null +++ b/roms/u-boot/include/faraday/fttmr010.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang + */ + +/* + * Timer + */ +#ifndef __FTTMR010_H +#define __FTTMR010_H + +struct fttmr010 { + unsigned int timer1_counter; /* 0x00 */ + unsigned int timer1_load; /* 0x04 */ + unsigned int timer1_match1; /* 0x08 */ + unsigned int timer1_match2; /* 0x0c */ + unsigned int timer2_counter; /* 0x10 */ + unsigned int timer2_load; /* 0x14 */ + unsigned int timer2_match1; /* 0x18 */ + unsigned int timer2_match2; /* 0x1c */ + unsigned int timer3_counter; /* 0x20 */ + unsigned int timer3_load; /* 0x24 */ + unsigned int timer3_match1; /* 0x28 */ + unsigned int timer3_match2; /* 0x2c */ + unsigned int cr; /* 0x30 */ + unsigned int interrupt_state; /* 0x34 */ + unsigned int interrupt_mask; /* 0x38 */ +}; + +/* + * Timer Control Register + */ +#define FTTMR010_TM3_UPDOWN (1 << 11) +#define FTTMR010_TM2_UPDOWN (1 << 10) +#define FTTMR010_TM1_UPDOWN (1 << 9) +#define FTTMR010_TM3_OFENABLE (1 << 8) +#define FTTMR010_TM3_CLOCK (1 << 7) +#define FTTMR010_TM3_ENABLE (1 << 6) +#define FTTMR010_TM2_OFENABLE (1 << 5) +#define FTTMR010_TM2_CLOCK (1 << 4) +#define FTTMR010_TM2_ENABLE (1 << 3) +#define FTTMR010_TM1_OFENABLE (1 << 2) +#define FTTMR010_TM1_CLOCK (1 << 1) +#define FTTMR010_TM1_ENABLE (1 << 0) + +/* + * Timer Interrupt State & Mask Registers + */ +#define FTTMR010_TM3_OVERFLOW (1 << 8) +#define FTTMR010_TM3_MATCH2 (1 << 7) +#define FTTMR010_TM3_MATCH1 (1 << 6) +#define FTTMR010_TM2_OVERFLOW (1 << 5) +#define FTTMR010_TM2_MATCH2 (1 << 4) +#define FTTMR010_TM2_MATCH1 (1 << 3) +#define FTTMR010_TM1_OVERFLOW (1 << 2) +#define FTTMR010_TM1_MATCH2 (1 << 1) +#define FTTMR010_TM1_MATCH1 (1 << 0) + +#endif /* __FTTMR010_H */ diff --git a/roms/u-boot/include/faraday/ftwdt010_wdt.h b/roms/u-boot/include/faraday/ftwdt010_wdt.h new file mode 100644 index 000000000..20bf6d312 --- /dev/null +++ b/roms/u-boot/include/faraday/ftwdt010_wdt.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Watchdog driver for the FTWDT010 Watch Dog Driver + * + * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com) + * Based on sa1100_wdt.c by Oleg Drokin + * Based on SoftDog driver by Alan Cox + * + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + * + * 27/11/2004 Initial release, Faraday. + * 12/01/2011 Port to u-boot, Macpaul Lin. + */ + +#ifndef __FTWDT010_H +#define __FTWDT010_H + +struct ftwdt010_wdt { + unsigned int wdcounter; /* Counter Reg - 0x00 */ + unsigned int wdload; /* Counter Auto Reload Reg - 0x04 */ + unsigned int wdrestart; /* Counter Restart Reg - 0x08 */ + unsigned int wdcr; /* Control Reg - 0x0c */ + unsigned int wdstatus; /* Status Reg - 0x10 */ + unsigned int wdclear; /* Timer Clear - 0x14 */ + unsigned int wdintrlen; /* Interrupt Length - 0x18 */ +}; + +/* + * WDLOAD - Counter Auto Reload Register + * The Auto Reload Register is set to 0x03EF1480 (66Mhz) by default. + * Which means in a 66MHz system, the period of Watch Dog timer reset is + * one second. + */ +#define FTWDT010_WDLOAD(x) ((x) & 0xffffffff) + +/* + * WDRESTART - Watch Dog Timer Counter Restart Register + * If writing 0x5AB9 to WDRESTART register, Watch Dog timer will + * automatically reload WDLOAD to WDCOUNTER and restart counting. + */ +#define FTWDT010_WDRESTART_MAGIC 0x5AB9 + +/* WDCR - Watch Dog Timer Control Register */ +#define FTWDT010_WDCR_ENABLE (1 << 0) +#define FTWDT010_WDCR_RST (1 << 1) +#define FTWDT010_WDCR_INTR (1 << 2) +/* FTWDT010_WDCR_EXT bit: Watch Dog Timer External Signal Enable */ +#define FTWDT010_WDCR_EXT (1 << 3) +/* FTWDT010_WDCR_CLOCK bit: Clock Source: 0: PCLK, 1: EXTCLK. + * The clock source PCLK cannot be gated when system sleeps, even if + * WDCLOCK bit is turned on. + * + * Faraday's Watch Dog timer can be driven by an external clock. The + * programmer just needs to write one to WdCR[WdClock] bit. + * + * Note: There is a limitation between EXTCLK and PCLK: + * EXTCLK cycle time / PCLK cycle time > 2. + * If the system does not need an external clock, + * just keep WdCR[WdClock] bit in its default value. + */ +#define FTWDT010_WDCR_CLOCK (1 << 4) + +/* + * WDSTATUS - Watch Dog Timer Status Register + * This bit is set when the counter reaches Zero + */ +#define FTWDT010_WDSTATUS(x) ((x) & 0x1) + +/* + * WDCLEAR - Watch Dog Timer Clear Register + * Writing one to this register will clear WDSTATUS. + */ +#define FTWDT010_WDCLEAR (1 << 0) + +/* + * WDINTRLEN - Watch Dog Timer Interrupt Length + * This register controls the duration length of wd_rst, wd_intr and wd_ext. + * The default value is 0xFF. + */ +#define FTWDT010_WDINTRLEN(x) ((x) & 0xff) + +/* + * Variable timeout should be set in ms. + * (CONFIG_SYS_CLK_FREQ/1000) equals 1 ms. + * WDLOAD = timeout * TIMEOUT_FACTOR. + */ +#define FTWDT010_TIMEOUT_FACTOR (CONFIG_SYS_CLK_FREQ / 1000) /* 1 ms */ + +void ftwdt010_wdt_reset(void); +void ftwdt010_wdt_disable(void); + +#endif /* __FTWDT010_H */ diff --git a/roms/u-boot/include/fastboot-internal.h b/roms/u-boot/include/fastboot-internal.h new file mode 100644 index 000000000..bf2f2b3c8 --- /dev/null +++ b/roms/u-boot/include/fastboot-internal.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _FASTBOOT_INTERNAL_H_ +#define _FASTBOOT_INTERNAL_H_ + +/** + * fastboot_buf_addr - base address of the fastboot download buffer + */ +extern void *fastboot_buf_addr; + +/** + * fastboot_buf_size - size of the fastboot download buffer + */ +extern u32 fastboot_buf_size; + +/** + * fastboot_progress_callback - callback executed during long operations + */ +extern void (*fastboot_progress_callback)(const char *msg); + +/** + * fastboot_getvar() - Writes variable indicated by cmd_parameter to response. + * + * @cmd_parameter: Pointer to command parameter + * @response: Pointer to fastboot response buffer + * + * Look up cmd_parameter first as an environment variable of the form + * fastboot., if that exists return use its value to set + * response. + * + * Otherwise lookup the name of variable and execute the appropriate + * function to return the requested value. + */ +void fastboot_getvar(char *cmd_parameter, char *response); + +#endif diff --git a/roms/u-boot/include/fastboot.h b/roms/u-boot/include/fastboot.h new file mode 100644 index 000000000..57daaf129 --- /dev/null +++ b/roms/u-boot/include/fastboot.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2008 - 2009 + * Windriver, + * Tom Rix + * + * Copyright 2011 Sebastian Andrzej Siewior + * + * Copyright 2014 Linaro, Ltd. + * Rob Herring + */ +#ifndef _FASTBOOT_H_ +#define _FASTBOOT_H_ + +#define FASTBOOT_VERSION "0.4" + +/* The 64 defined bytes plus \0 */ +#define FASTBOOT_COMMAND_LEN (64 + 1) +#define FASTBOOT_RESPONSE_LEN (64 + 1) + +/** + * All known commands to fastboot + */ +enum { + FASTBOOT_COMMAND_GETVAR = 0, + FASTBOOT_COMMAND_DOWNLOAD, +#if CONFIG_IS_ENABLED(FASTBOOT_FLASH) + FASTBOOT_COMMAND_FLASH, + FASTBOOT_COMMAND_ERASE, +#endif + FASTBOOT_COMMAND_BOOT, + FASTBOOT_COMMAND_CONTINUE, + FASTBOOT_COMMAND_REBOOT, + FASTBOOT_COMMAND_REBOOT_BOOTLOADER, + FASTBOOT_COMMAND_REBOOT_FASTBOOTD, + FASTBOOT_COMMAND_REBOOT_RECOVERY, + FASTBOOT_COMMAND_SET_ACTIVE, +#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT) + FASTBOOT_COMMAND_OEM_FORMAT, +#endif +#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_PARTCONF) + FASTBOOT_COMMAND_OEM_PARTCONF, +#endif +#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_BOOTBUS) + FASTBOOT_COMMAND_OEM_BOOTBUS, +#endif +#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT) + FASTBOOT_COMMAND_ACMD, + FASTBOOT_COMMAND_UCMD, +#endif + + FASTBOOT_COMMAND_COUNT +}; + +/** + * Reboot reasons + */ +enum fastboot_reboot_reason { + FASTBOOT_REBOOT_REASON_BOOTLOADER, + FASTBOOT_REBOOT_REASON_FASTBOOTD, + FASTBOOT_REBOOT_REASON_RECOVERY, + FASTBOOT_REBOOT_REASONS_COUNT +}; + +/** + * fastboot_response() - Writes a response of the form "$tag$reason". + * + * @tag: The first part of the response + * @response: Pointer to fastboot response buffer + * @format: printf style format string + */ +void fastboot_response(const char *tag, char *response, + const char *format, ...) + __attribute__ ((format (__printf__, 3, 4))); + +/** + * fastboot_fail() - Write a FAIL response of the form "FAIL$reason". + * + * @reason: Pointer to returned reason string + * @response: Pointer to fastboot response buffer + */ +void fastboot_fail(const char *reason, char *response); + +/** + * fastboot_okay() - Write an OKAY response of the form "OKAY$reason". + * + * @reason: Pointer to returned reason string, or NULL to send a bare "OKAY" + * @response: Pointer to fastboot response buffer + */ +void fastboot_okay(const char *reason, char *response); + +/** + * fastboot_set_reboot_flag() - Set flag to indicate reboot-bootloader + * + * Set flag which indicates that we should reboot into the bootloader + * following the reboot that fastboot executes after this function. + * + * This function should be overridden in your board file with one + * which sets whatever flag your board specific Android bootloader flow + * requires in order to re-enter the bootloader. + */ +int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason); + +/** + * fastboot_set_progress_callback() - set progress callback + * + * @progress: Pointer to progress callback + * + * Set a callback which is invoked periodically during long running operations + * (flash and erase). This can be used (for example) by the UDP transport to + * send INFO responses to keep the client alive whilst those commands are + * executing. + */ +void fastboot_set_progress_callback(void (*progress)(const char *msg)); + +/* + * fastboot_init() - initialise new fastboot protocol session + * + * @buf_addr: Pointer to download buffer, or NULL for default + * @buf_size: Size of download buffer, or zero for default + */ +void fastboot_init(void *buf_addr, u32 buf_size); + +/** + * fastboot_boot() - Execute fastboot boot command + * + * If ${fastboot_bootcmd} is set, run that command to execute the boot + * process, if that returns, then exit the fastboot server and return + * control to the caller. + * + * Otherwise execute "bootm ", if that fails, reset + * the board. + */ +void fastboot_boot(void); + +/** + * fastboot_handle_command() - Handle fastboot command + * + * @cmd_string: Pointer to command string + * @response: Pointer to fastboot response buffer + * + * Return: Executed command, or -1 if not recognized + */ +int fastboot_handle_command(char *cmd_string, char *response); + +/** + * fastboot_data_remaining() - return bytes remaining in current transfer + * + * Return: Number of bytes left in the current download + */ +u32 fastboot_data_remaining(void); + +/** + * fastboot_data_download() - Copy image data to fastboot_buf_addr. + * + * @fastboot_data: Pointer to received fastboot data + * @fastboot_data_len: Length of received fastboot data + * @response: Pointer to fastboot response buffer + * + * Copies image data from fastboot_data to fastboot_buf_addr. Writes to + * response. fastboot_bytes_received is updated to indicate the number + * of bytes that have been transferred. + */ +void fastboot_data_download(const void *fastboot_data, + unsigned int fastboot_data_len, char *response); + +/** + * fastboot_data_complete() - Mark current transfer complete + * + * @response: Pointer to fastboot response buffer + * + * Set image_size and ${filesize} to the total size of the downloaded image. + */ +void fastboot_data_complete(char *response); + +#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT) +void fastboot_acmd_complete(void); +#endif +#endif /* _FASTBOOT_H_ */ diff --git a/roms/u-boot/include/fat.h b/roms/u-boot/include/fat.h new file mode 100644 index 000000000..bd8e450b3 --- /dev/null +++ b/roms/u-boot/include/fat.h @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * R/O (V)FAT 12/16/32 filesystem implementation by Marcus Sundberg + * + * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6 + * 2003-03-10 - kharris@nexus-tech.net - ported to u-boot + */ + +#ifndef _FAT_H_ +#define _FAT_H_ + +#include +#include +#include + +struct disk_partition; + +/* Maximum Long File Name length supported here is 128 UTF-16 code units */ +#define VFAT_MAXLEN_BYTES 256 /* Maximum LFN buffer in bytes */ +#define VFAT_MAXSEQ 9 /* Up to 9 of 13 2-byte UTF-16 entries */ +#define PREFETCH_BLOCKS 2 + +#define MAX_CLUSTSIZE CONFIG_FS_FAT_MAX_CLUSTSIZE + +#define DIRENTSPERCLUST ((mydata->clust_size * mydata->sect_size) / \ + sizeof(dir_entry)) + +#define FATBUFBLOCKS 6 +#define FATBUFSIZE (mydata->sect_size * FATBUFBLOCKS) +#define FAT12BUFSIZE ((FATBUFSIZE*2)/3) +#define FAT16BUFSIZE (FATBUFSIZE/2) +#define FAT32BUFSIZE (FATBUFSIZE/4) + +/* Maximum number of entry for long file name according to spec */ +#define MAX_LFN_SLOT 20 + +/* Filesystem identifiers */ +#define FAT12_SIGN "FAT12 " +#define FAT16_SIGN "FAT16 " +#define FAT32_SIGN "FAT32 " +#define SIGNLEN 8 + +/* File attributes */ +#define ATTR_RO 1 +#define ATTR_HIDDEN 2 +#define ATTR_SYS 4 +#define ATTR_VOLUME 8 +#define ATTR_DIR 16 +#define ATTR_ARCH 32 + +#define ATTR_VFAT (ATTR_RO | ATTR_HIDDEN | ATTR_SYS | ATTR_VOLUME) + +#define DELETED_FLAG ((char)0xe5) /* Marks deleted files when in name[0] */ +#define aRING 0x05 /* Used as special character in name[0] */ + +/* + * Indicates that the entry is the last long entry in a set of long + * dir entries + */ +#define LAST_LONG_ENTRY_MASK 0x40 + +#define ISDIRDELIM(c) ((c) == '/' || (c) == '\\') + +#define FSTYPE_NONE (-1) + +#if defined(__linux__) && defined(__KERNEL__) +#define FAT2CPU16 le16_to_cpu +#define FAT2CPU32 le32_to_cpu +#else +#if __LITTLE_ENDIAN +#define FAT2CPU16(x) (x) +#define FAT2CPU32(x) (x) +#else +#define FAT2CPU16(x) ((((x) & 0x00ff) << 8) | (((x) & 0xff00) >> 8)) +#define FAT2CPU32(x) ((((x) & 0x000000ff) << 24) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0xff000000) >> 24)) +#endif +#endif + +#define START(dent) (FAT2CPU16((dent)->start) \ + + (mydata->fatsize != 32 ? 0 : \ + (FAT2CPU16((dent)->starthi) << 16))) +#define IS_LAST_CLUST(x, fatsize) ((x) >= ((fatsize) != 32 ? \ + ((fatsize) != 16 ? 0xff8 : 0xfff8) : \ + 0xffffff8)) +#define CHECK_CLUST(x, fatsize) ((x) <= 1 || \ + (x) >= ((fatsize) != 32 ? \ + ((fatsize) != 16 ? 0xff0 : 0xfff0) : \ + 0xffffff0)) + +typedef struct boot_sector { + __u8 ignored[3]; /* Bootstrap code */ + char system_id[8]; /* Name of fs */ + __u8 sector_size[2]; /* Bytes/sector */ + __u8 cluster_size; /* Sectors/cluster */ + __u16 reserved; /* Number of reserved sectors */ + __u8 fats; /* Number of FATs */ + __u8 dir_entries[2]; /* Number of root directory entries */ + __u8 sectors[2]; /* Number of sectors */ + __u8 media; /* Media code */ + __u16 fat_length; /* Sectors/FAT */ + __u16 secs_track; /* Sectors/track */ + __u16 heads; /* Number of heads */ + __u32 hidden; /* Number of hidden sectors */ + __u32 total_sect; /* Number of sectors (if sectors == 0) */ + + /* FAT32 only */ + __u32 fat32_length; /* Sectors/FAT */ + __u16 flags; /* Bit 8: fat mirroring, low 4: active fat */ + __u8 version[2]; /* Filesystem version */ + __u32 root_cluster; /* First cluster in root directory */ + __u16 info_sector; /* Filesystem info sector */ + __u16 backup_boot; /* Backup boot sector */ + __u16 reserved2[6]; /* Unused */ +} boot_sector; + +typedef struct volume_info +{ + __u8 drive_number; /* BIOS drive number */ + __u8 reserved; /* Unused */ + __u8 ext_boot_sign; /* 0x29 if fields below exist (DOS 3.3+) */ + __u8 volume_id[4]; /* Volume ID number */ + char volume_label[11]; /* Volume label */ + char fs_type[8]; /* Typically FAT12, FAT16, or FAT32 */ + /* Boot code comes next, all but 2 bytes to fill up sector */ + /* Boot sign comes last, 2 bytes */ +} volume_info; + +/* see dir_entry::lcase: */ +#define CASE_LOWER_BASE 8 /* base (name) is lower case */ +#define CASE_LOWER_EXT 16 /* extension is lower case */ + +struct nameext { + char name[8]; + char ext[3]; +}; + +typedef struct dir_entry { + struct nameext nameext; /* Name and extension */ + __u8 attr; /* Attribute bits */ + __u8 lcase; /* Case for name and ext (CASE_LOWER_x) */ + __u8 ctime_ms; /* Creation time, milliseconds */ + __u16 ctime; /* Creation time */ + __u16 cdate; /* Creation date */ + __u16 adate; /* Last access date */ + __u16 starthi; /* High 16 bits of cluster in FAT32 */ + __u16 time,date,start;/* Time, date and first cluster */ + __u32 size; /* File size in bytes */ +} dir_entry; + +typedef struct dir_slot { + __u8 id; /* Sequence number for slot */ + __u8 name0_4[10]; /* First 5 characters in name */ + __u8 attr; /* Attribute byte */ + __u8 reserved; /* Unused */ + __u8 alias_checksum;/* Checksum for 8.3 alias */ + __u8 name5_10[12]; /* 6 more characters in name */ + __u16 start; /* Unused */ + __u8 name11_12[4]; /* Last 2 characters in name */ +} dir_slot; + +/* + * Private filesystem parameters + * + * Note: FAT buffer has to be 32 bit aligned + * (see FAT32 accesses) + */ +typedef struct { + __u8 *fatbuf; /* Current FAT buffer */ + int fatsize; /* Size of FAT in bits */ + __u32 fatlength; /* Length of FAT in sectors */ + __u16 fat_sect; /* Starting sector of the FAT */ + __u8 fat_dirty; /* Set if fatbuf has been modified */ + __u32 rootdir_sect; /* Start sector of root directory */ + __u16 sect_size; /* Size of sectors in bytes */ + __u16 clust_size; /* Size of clusters in sectors */ + int data_begin; /* The sector of the first cluster, can be negative */ + int fatbufnum; /* Used by get_fatent, init to -1 */ + int rootdir_size; /* Size of root dir for non-FAT32 */ + __u32 root_cluster; /* First cluster of root dir for FAT32 */ + u32 total_sect; /* Number of sectors */ + int fats; /* Number of FATs */ +} fsdata; + +struct fat_itr; +typedef struct fat_itr fat_itr; + +static inline u32 clust_to_sect(fsdata *fsdata, u32 clust) +{ + return fsdata->data_begin + clust * fsdata->clust_size; +} + +static inline u32 sect_to_clust(fsdata *fsdata, int sect) +{ + return (sect - fsdata->data_begin) / fsdata->clust_size; +} + +int file_fat_detectfs(void); +int fat_exists(const char *filename); +int fat_size(const char *filename, loff_t *size); +int file_fat_read_at(const char *filename, loff_t pos, void *buffer, + loff_t maxsize, loff_t *actread); +int file_fat_read(const char *filename, void *buffer, int maxsize); +int fat_set_blk_dev(struct blk_desc *rbdd, struct disk_partition *info); +int fat_register_device(struct blk_desc *dev_desc, int part_no); + +int file_fat_write(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actwrite); +int fat_read_file(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actread); +int fat_opendir(const char *filename, struct fs_dir_stream **dirsp); +int fat_readdir(struct fs_dir_stream *dirs, struct fs_dirent **dentp); +void fat_closedir(struct fs_dir_stream *dirs); +int fat_unlink(const char *filename); +int fat_mkdir(const char *dirname); +void fat_close(void); +void *fat_next_cluster(fat_itr *itr, unsigned int *nbytes); + +/** + * fat_uuid() - get FAT volume ID + * + * The FAT volume ID returned in @uuid_str as hexadecimal number in XXXX-XXXX + * format. + * + * @uuid_str: caller allocated buffer of at least 10 bytes for the volume ID + * Return: 0 on success + */ +int fat_uuid(char *uuid_str); + +#endif /* _FAT_H_ */ diff --git a/roms/u-boot/include/fb_mmc.h b/roms/u-boot/include/fb_mmc.h new file mode 100644 index 000000000..76ed7cd6b --- /dev/null +++ b/roms/u-boot/include/fb_mmc.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Broadcom Corporation. + */ + +#ifndef _FB_MMC_H_ +#define _FB_MMC_H_ + +struct blk_desc; +struct disk_partition; + +/** + * fastboot_mmc_get_part_info() - Lookup eMMC partion by name + * + * @part_name: Named partition to lookup + * @dev_desc: Pointer to returned blk_desc pointer + * @part_info: Pointer to returned struct disk_partition + * @response: Pointer to fastboot response buffer + */ +int fastboot_mmc_get_part_info(const char *part_name, + struct blk_desc **dev_desc, + struct disk_partition *part_info, + char *response); + +/** + * fastboot_mmc_flash_write() - Write image to eMMC for fastboot + * + * @cmd: Named partition to write image to + * @download_buffer: Pointer to image data + * @download_bytes: Size of image data + * @response: Pointer to fastboot response buffer + */ +void fastboot_mmc_flash_write(const char *cmd, void *download_buffer, + u32 download_bytes, char *response); +/** + * fastboot_mmc_flash_erase() - Erase eMMC for fastboot + * + * @cmd: Named partition to erase + * @response: Pointer to fastboot response buffer + */ +void fastboot_mmc_erase(const char *cmd, char *response); +#endif diff --git a/roms/u-boot/include/fb_nand.h b/roms/u-boot/include/fb_nand.h new file mode 100644 index 000000000..6d7999f26 --- /dev/null +++ b/roms/u-boot/include/fb_nand.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Broadcom Corporation. + * Copyright 2015 Free Electrons. + */ + +#ifndef _FB_NAND_H_ +#define _FB_NAND_H_ + +#include + +/** + * fastboot_nand_get_part_info() - Lookup NAND partion by name + * + * @part_name: Named device to lookup + * @part_info: Pointer to returned part_info pointer + * @response: Pointer to fastboot response buffer + */ +int fastboot_nand_get_part_info(const char *part_name, + struct part_info **part_info, char *response); + +/** + * fastboot_nand_flash_write() - Write image to NAND for fastboot + * + * @cmd: Named device to write image to + * @download_buffer: Pointer to image data + * @download_bytes: Size of image data + * @response: Pointer to fastboot response buffer + */ +void fastboot_nand_flash_write(const char *cmd, void *download_buffer, + u32 download_bytes, char *response); + +/** + * fastboot_nand_flash_erase() - Erase NAND for fastboot + * + * @cmd: Named device to erase + * @response: Pointer to fastboot response buffer + */ +void fastboot_nand_erase(const char *cmd, char *response); +#endif diff --git a/roms/u-boot/include/fdt.h b/roms/u-boot/include/fdt.h new file mode 100644 index 000000000..b97b3f2bc --- /dev/null +++ b/roms/u-boot/include/fdt.h @@ -0,0 +1 @@ +#include "../scripts/dtc/libfdt/fdt.h" diff --git a/roms/u-boot/include/fdt_region.h b/roms/u-boot/include/fdt_region.h new file mode 100644 index 000000000..ff7a1ccb9 --- /dev/null +++ b/roms/u-boot/include/fdt_region.h @@ -0,0 +1,304 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _FDT_REGION_H +#define _FDT_REGION_H + +#ifndef SWIG /* Not available in Python */ +struct fdt_region { + int offset; + int size; +}; + +/* + * Flags for fdt_find_regions() + * + * Add a region for the string table (always the last region) + */ +#define FDT_REG_ADD_STRING_TAB (1 << 0) + +/* + * Add all supernodes of a matching node/property, useful for creating a + * valid subset tree + */ +#define FDT_REG_SUPERNODES (1 << 1) + +/* Add the FDT_BEGIN_NODE tags of subnodes, including their names */ +#define FDT_REG_DIRECT_SUBNODES (1 << 2) + +/* Add all subnodes of a matching node */ +#define FDT_REG_ALL_SUBNODES (1 << 3) + +/* Add a region for the mem_rsvmap table (always the first region) */ +#define FDT_REG_ADD_MEM_RSVMAP (1 << 4) + +/* Indicates what an fdt part is (node, property, value) */ +#define FDT_IS_NODE (1 << 0) +#define FDT_IS_PROP (1 << 1) +#define FDT_IS_VALUE (1 << 2) /* not supported */ +#define FDT_IS_COMPAT (1 << 3) /* used internally */ +#define FDT_NODE_HAS_PROP (1 << 4) /* node contains prop */ + +#define FDT_ANY_GLOBAL (FDT_IS_NODE | FDT_IS_PROP | FDT_IS_VALUE | \ + FDT_IS_COMPAT) +#define FDT_IS_ANY 0x1f /* all the above */ + +/* We set a reasonable limit on the number of nested nodes */ +#define FDT_MAX_DEPTH 32 + +/* Decribes what we want to include from the current tag */ +enum want_t { + WANT_NOTHING, + WANT_NODES_ONLY, /* No properties */ + WANT_NODES_AND_PROPS, /* Everything for one level */ + WANT_ALL_NODES_AND_PROPS /* Everything for all levels */ +}; + +/* Keeps track of the state at parent nodes */ +struct fdt_subnode_stack { + int offset; /* Offset of node */ + enum want_t want; /* The 'want' value here */ + int included; /* 1 if we included this node, 0 if not */ +}; + +struct fdt_region_ptrs { + int depth; /* Current tree depth */ + int done; /* What we have completed scanning */ + enum want_t want; /* What we are currently including */ + char *end; /* Pointer to end of full node path */ + int nextoffset; /* Next node offset to check */ +}; + +/* The state of our finding algortihm */ +struct fdt_region_state { + struct fdt_subnode_stack stack[FDT_MAX_DEPTH]; /* node stack */ + struct fdt_region *region; /* Contains list of regions found */ + int count; /* Numnber of regions found */ + const void *fdt; /* FDT blob */ + int max_regions; /* Maximum regions to find */ + int can_merge; /* 1 if we can merge with previous region */ + int start; /* Start position of current region */ + struct fdt_region_ptrs ptrs; /* Pointers for what we are up to */ +}; + +/** + * fdt_find_regions() - find regions in device tree + * + * Given a list of nodes to include and properties to exclude, find + * the regions of the device tree which describe those included parts. + * + * The intent is to get a list of regions which will be invariant provided + * those parts are invariant. For example, if you request a list of regions + * for all nodes but exclude the property "data", then you will get the + * same region contents regardless of any change to "data" properties. + * + * This function can be used to produce a byte-stream to send to a hashing + * function to verify that critical parts of the FDT have not changed. + * + * Nodes which are given in 'inc' are included in the region list, as + * are the names of the immediate subnodes nodes (but not the properties + * or subnodes of those subnodes). + * + * For eaxample "/" means to include the root node, all root properties + * and the FDT_BEGIN_NODE and FDT_END_NODE of all subnodes of /. The latter + * ensures that we capture the names of the subnodes. In a hashing situation + * it prevents the root node from changing at all Any change to non-excluded + * properties, names of subnodes or number of subnodes would be detected. + * + * When used with FITs this provides the ability to hash and sign parts of + * the FIT based on different configurations in the FIT. Then it is + * impossible to change anything about that configuration (include images + * attached to the configuration), but it may be possible to add new + * configurations, new images or new signatures within the existing + * framework. + * + * Adding new properties to a device tree may result in the string table + * being extended (if the new property names are different from those + * already added). This function can optionally include a region for + * the string table so that this can be part of the hash too. + * + * The device tree header is not included in the list. + * + * @fdt: Device tree to check + * @inc: List of node paths to included + * @inc_count: Number of node paths in list + * @exc_prop: List of properties names to exclude + * @exc_prop_count: Number of properties in exclude list + * @region: Returns list of regions + * @max_region: Maximum length of region list + * @path: Pointer to a temporary string for the function to use for + * building path names + * @path_len: Length of path, must be large enough to hold the longest + * path in the tree + * @add_string_tab: 1 to add a region for the string table + * @return number of regions in list. If this is >max_regions then the + * region array was exhausted. You should increase max_regions and try + * the call again. + */ +int fdt_find_regions(const void *fdt, char * const inc[], int inc_count, + char * const exc_prop[], int exc_prop_count, + struct fdt_region region[], int max_regions, + char *path, int path_len, int add_string_tab); + +/** + * fdt_first_region() - find regions in device tree + * + * Given a nodes and properties to include and properties to exclude, find + * the regions of the device tree which describe those included parts. + * + * The use for this function is twofold. Firstly it provides a convenient + * way of performing a structure-aware grep of the tree. For example it is + * possible to grep for a node and get all the properties associated with + * that node. Trees can be subsetted easily, by specifying the nodes that + * are required, and then writing out the regions returned by this function. + * This is useful for small resource-constrained systems, such as boot + * loaders, which want to use an FDT but do not need to know about all of + * it. + * + * Secondly it makes it easy to hash parts of the tree and detect changes. + * The intent is to get a list of regions which will be invariant provided + * those parts are invariant. For example, if you request a list of regions + * for all nodes but exclude the property "data", then you will get the + * same region contents regardless of any change to "data" properties. + * + * This function can be used to produce a byte-stream to send to a hashing + * function to verify that critical parts of the FDT have not changed. + * Note that semantically null changes in order could still cause false + * hash misses. Such reordering might happen if the tree is regenerated + * from source, and nodes are reordered (the bytes-stream will be emitted + * in a different order and many hash functions will detect this). However + * if an existing tree is modified using libfdt functions, such as + * fdt_add_subnode() and fdt_setprop(), then this problem is avoided. + * + * The nodes/properties to include/exclude are defined by a function + * provided by the caller. This function is called for each node and + * property, and must return: + * + * 0 - to exclude this part + * 1 - to include this part + * -1 - for FDT_IS_PROP only: no information is available, so include + * if its containing node is included + * + * The last case is only used to deal with properties. Often a property is + * included if its containing node is included - this is the case where + * -1 is returned.. However if the property is specifically required to be + * included/excluded, then 0 or 1 can be returned. Note that including a + * property when the FDT_REG_SUPERNODES flag is given will force its + * containing node to be included since it is not valid to have a property + * that is not in a node. + * + * Using the information provided, the inclusion of a node can be controlled + * either by a node name or its compatible string, or any other property + * that the function can determine. + * + * As an example, including node "/" means to include the root node and all + * root properties. A flag provides a way of also including supernodes (of + * which there is none for the root node), and another flag includes + * immediate subnodes, so in this case we would get the FDT_BEGIN_NODE and + * FDT_END_NODE of all subnodes of /. + * + * The subnode feature helps in a hashing situation since it prevents the + * root node from changing at all. Any change to non-excluded properties, + * names of subnodes or number of subnodes would be detected. + * + * When used with FITs this provides the ability to hash and sign parts of + * the FIT based on different configurations in the FIT. Then it is + * impossible to change anything about that configuration (include images + * attached to the configuration), but it may be possible to add new + * configurations, new images or new signatures within the existing + * framework. + * + * Adding new properties to a device tree may result in the string table + * being extended (if the new property names are different from those + * already added). This function can optionally include a region for + * the string table so that this can be part of the hash too. This is always + * the last region. + * + * The FDT also has a mem_rsvmap table which can also be included, and is + * always the first region if so. + * + * The device tree header is not included in the region list. Since the + * contents of the FDT are changing (shrinking, often), the caller will need + * to regenerate the header anyway. + * + * @fdt: Device tree to check + * @h_include: Function to call to determine whether to include a part or + * not: + * + * @priv: Private pointer as passed to fdt_find_regions() + * @fdt: Pointer to FDT blob + * @offset: Offset of this node / property + * @type: Type of this part, FDT_IS_... + * @data: Pointer to data (node name, property name, compatible + * string, value (not yet supported) + * @size: Size of data, or 0 if none + * @return 0 to exclude, 1 to include, -1 if no information is + * available + * @priv: Private pointer passed to h_include + * @region: Returns list of regions, sorted by offset + * @max_regions: Maximum length of region list + * @path: Pointer to a temporary string for the function to use for + * building path names + * @path_len: Length of path, must be large enough to hold the longest + * path in the tree + * @flags: Various flags that control the region algortihm, see + * FDT_REG_... + * @return number of regions in list. If this is >max_regions then the + * region array was exhausted. You should increase max_regions and try + * the call again. Only the first max_regions elements are available in the + * array. + * + * On error a -ve value is return, which can be: + * + * -FDT_ERR_BADSTRUCTURE (too deep or more END tags than BEGIN tags + * -FDT_ERR_BADLAYOUT + * -FDT_ERR_NOSPACE (path area is too small) + */ +int fdt_first_region(const void *fdt, + int (*h_include)(void *priv, const void *fdt, int offset, + int type, const char *data, int size), + void *priv, struct fdt_region *region, + char *path, int path_len, int flags, + struct fdt_region_state *info); + +/** fdt_next_region() - find next region + * + * See fdt_first_region() for full description. This function finds the + * next region according to the provided parameters, which must be the same + * as passed to fdt_first_region(). + * + * This function can additionally return -FDT_ERR_NOTFOUND when there are no + * more regions + */ +int fdt_next_region(const void *fdt, + int (*h_include)(void *priv, const void *fdt, int offset, + int type, const char *data, int size), + void *priv, struct fdt_region *region, + char *path, int path_len, int flags, + struct fdt_region_state *info); + +/** + * fdt_add_alias_regions() - find aliases that point to existing regions + * + * Once a device tree grep is complete some of the nodes will be present + * and some will have been dropped. This function checks all the alias nodes + * to figure out which points point to nodes which are still present. These + * aliases need to be kept, along with the nodes they reference. + * + * Given a list of regions function finds the aliases that still apply and + * adds more regions to the list for these. This function is called after + * fdt_next_region() has finished returning regions and requires the same + * state. + * + * @fdt: Device tree file to reference + * @region: List of regions that will be kept + * @count: Number of regions + * @max_regions: Number of entries that can fit in @region + * @info: Region state as returned from fdt_next_region() + * @return new number of regions in @region (i.e. count + the number added) + * or -FDT_ERR_NOSPACE if there was not enough space. + */ +int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count, + int max_regions, struct fdt_region_state *info); +#endif /* SWIG */ + +#endif /* _FDT_REGION_H */ diff --git a/roms/u-boot/include/fdt_simplefb.h b/roms/u-boot/include/fdt_simplefb.h new file mode 100644 index 000000000..7cc305e1f --- /dev/null +++ b/roms/u-boot/include/fdt_simplefb.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Simplefb device tree support + * + * (C) Copyright 2015 + * Stephen Warren + */ + +#ifndef _FDT_SIMPLEFB_H_ +#define _FDT_SIMPLEFB_H_ +int lcd_dt_simplefb_add_node(void *blob); +int lcd_dt_simplefb_enable_existing_node(void *blob); +#endif diff --git a/roms/u-boot/include/fdt_support.h b/roms/u-boot/include/fdt_support.h new file mode 100644 index 000000000..1e4dbc0a8 --- /dev/null +++ b/roms/u-boot/include/fdt_support.h @@ -0,0 +1,391 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com + */ + +#ifndef __FDT_SUPPORT_H +#define __FDT_SUPPORT_H + +#ifdef CONFIG_OF_LIBFDT + +#include +#include + +/** + * arch_fixup_fdt() - Write arch-specific information to fdt + * + * Defined in arch/$(ARCH)/lib/bootm-fdt.c + * + * @blob: FDT blob to write to + * @return 0 if ok, or -ve FDT_ERR_... on failure + */ +int arch_fixup_fdt(void *blob); + +void ft_cpu_setup(void *blob, struct bd_info *bd); + +void ft_pci_setup(void *blob, struct bd_info *bd); + +u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell, + const char *prop, const u32 dflt); +u32 fdt_getprop_u32_default(const void *fdt, const char *path, + const char *prop, const u32 dflt); + +/** + * Add data to the root of the FDT before booting the OS. + * + * See doc/device-tree-bindings/root.txt + * + * @param fdt FDT address in memory + * @return 0 if ok, or -FDT_ERR_... on error + */ +int fdt_root(void *fdt); + +/** + * Add chosen data the FDT before booting the OS. + * + * In particular, this adds the kernel command line (bootargs) to the FDT. + * + * @param fdt FDT address in memory + * @return 0 if ok, or -FDT_ERR_... on error + */ +int fdt_chosen(void *fdt); + +/** + * Add initrd information to the FDT before booting the OS. + * + * @param fdt FDT address in memory + * @return 0 if ok, or -FDT_ERR_... on error + */ +int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end); + +void do_fixup_by_path(void *fdt, const char *path, const char *prop, + const void *val, int len, int create); +void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop, + u32 val, int create); + +static inline void do_fixup_by_path_string(void *fdt, const char *path, + const char *prop, const char *status) +{ + do_fixup_by_path(fdt, path, prop, status, strlen(status) + 1, 1); +} + +void do_fixup_by_prop(void *fdt, + const char *pname, const void *pval, int plen, + const char *prop, const void *val, int len, + int create); +void do_fixup_by_prop_u32(void *fdt, + const char *pname, const void *pval, int plen, + const char *prop, u32 val, int create); +void do_fixup_by_compat(void *fdt, const char *compat, + const char *prop, const void *val, int len, int create); +void do_fixup_by_compat_u32(void *fdt, const char *compat, + const char *prop, u32 val, int create); +/** + * Setup the memory node in the DT. Creates one if none was existing before. + * Calls fdt_fixup_memory_banks() to populate a single reg pair covering the + * whole memory. + * + * @param blob FDT blob to update + * @param start Begin of DRAM mapping in physical memory + * @param size Size of the single memory bank + * @return 0 if ok, or -1 or -FDT_ERR_... on error + */ +int fdt_fixup_memory(void *blob, u64 start, u64 size); + +/** + * Fill the DT memory node with multiple memory banks. + * Creates the node if none was existing before. + * If banks is 0, it will not touch the existing reg property. This allows + * boards to not mess with the existing DT setup, which may have been + * filled in properly before. + * + * @param blob FDT blob to update + * @param start Array of size to hold the start addresses. + * @param size Array of size to hold the size of each region. + * @param banks Number of memory banks to create. If 0, the reg + * property will be left untouched. + * @return 0 if ok, or -1 or -FDT_ERR_... on error + */ +#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY +int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks); +int fdt_set_usable_memory(void *blob, u64 start[], u64 size[], int banks); +#else +static inline int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], + int banks) +{ + return 0; +} +#endif + +void fdt_fixup_ethernet(void *fdt); +int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, + const void *val, int len, int create); +void fdt_fixup_qe_firmware(void *fdt); + +/** + * Update native-mode property of display-timings node to the phandle + * of the timings matching a display by name (case insensitive). + * + * see kernel Documentation/devicetree/bindings/video/display-timing.txt + * + * @param blob FDT blob to update + * @param path path within dt + * @param display name of display timing to match + * @return 0 if ok, or -FDT_ERR_... on error + */ +int fdt_fixup_display(void *blob, const char *path, const char *display); + +#if defined(CONFIG_USB_EHCI_FSL) || defined(CONFIG_USB_XHCI_FSL) +void fsl_fdt_fixup_dr_usb(void *blob, struct bd_info *bd); +#else +static inline void fsl_fdt_fixup_dr_usb(void *blob, struct bd_info *bd) {} +#endif /* defined(CONFIG_USB_EHCI_FSL) || defined(CONFIG_USB_XHCI_FSL) */ + +#if defined(CONFIG_SYS_FSL_SEC_COMPAT) +void fdt_fixup_crypto_node(void *blob, int sec_rev); +#else +static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {} +#endif + +/** + * Record information about a processed loadable in /fit-images (creating + * /fit-images if necessary). + * + * @param blob FDT blob to update + * @param index index of this loadable + * @param name name of the loadable + * @param load_addr address the loadable was loaded to + * @param size number of bytes loaded + * @param entry_point entry point (if specified, otherwise pass -1) + * @param type type (if specified, otherwise pass NULL) + * @param os os-type (if specified, otherwise pass NULL) + * @return 0 if ok, or -1 or -FDT_ERR_... on error + */ +int fdt_record_loadable(void *blob, u32 index, const char *name, + uintptr_t load_addr, u32 size, uintptr_t entry_point, + const char *type, const char *os); + +#ifdef CONFIG_PCI +#include +int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose); +#endif + +int fdt_find_or_add_subnode(void *fdt, int parentoffset, const char *name); + +/** + * Add board-specific data to the FDT before booting the OS. + * + * Use CONFIG_SYS_FDT_PAD to ensure there is sufficient space. + * This function is called if CONFIG_OF_BOARD_SETUP is defined + * + * @param blob FDT blob to update + * @param bd Pointer to board data + * @return 0 if ok, or -FDT_ERR_... on error + */ +int ft_board_setup(void *blob, struct bd_info *bd); + +/** + * board_fdt_chosen_bootargs() - Arbitrarily amend fdt kernel command line + * + * This is used for late modification of kernel command line arguments just + * before they are added into the /chosen node in flat device tree. + * + * @return: pointer to kernel command line arguments in memory + */ +char *board_fdt_chosen_bootargs(void); + +/* + * The keystone2 SOC requires all 32 bit aliased addresses to be converted + * to their 36 physical format. This has to happen after all fdt nodes + * are added or modified by the image_setup_libfdt(). The ft_board_setup_ex() + * called at the end of the image_setup_libfdt() is to do that convertion. + */ +void ft_board_setup_ex(void *blob, struct bd_info *bd); +void ft_cpu_setup(void *blob, struct bd_info *bd); +void ft_pci_setup(void *blob, struct bd_info *bd); + +/** + * Add system-specific data to the FDT before booting the OS. + * + * Use CONFIG_SYS_FDT_PAD to ensure there is sufficient space. + * This function is called if CONFIG_OF_SYSTEM_SETUP is defined + * + * @param blob FDT blob to update + * @param bd Pointer to board data + * @return 0 if ok, or -FDT_ERR_... on error + */ +int ft_system_setup(void *blob, struct bd_info *bd); + +void set_working_fdt_addr(ulong addr); + +/** + * shrink down the given blob to minimum size + some extrasize if required + * + * @param blob FDT blob to update + * @param extrasize additional bytes needed + * @return 0 if ok, or -FDT_ERR_... on error + */ +int fdt_shrink_to_minimum(void *blob, uint extrasize); +int fdt_increase_size(void *fdt, int add_len); + +int fdt_fixup_nor_flash_size(void *blob); + +struct node_info; +#if defined(CONFIG_FDT_FIXUP_PARTITIONS) +void fdt_fixup_mtdparts(void *fdt, const struct node_info *node_info, + int node_info_size); +#else +static inline void fdt_fixup_mtdparts(void *fdt, + const struct node_info *node_info, + int node_info_size) +{ +} +#endif + +void fdt_del_node_and_alias(void *blob, const char *alias); + +/** + * Translate an address from the DT into a CPU physical address + * + * The translation relies on the "ranges" property. + * + * @param blob Pointer to device tree blob + * @param node_offset Node DT offset + * @param in_addr Pointer to the address to translate + * @return translated address or OF_BAD_ADDR on error + */ +u64 fdt_translate_address(const void *blob, int node_offset, + const __be32 *in_addr); +/** + * Translate a DMA address from the DT into a CPU physical address + * + * The translation relies on the "dma-ranges" property. + * + * @param blob Pointer to device tree blob + * @param node_offset Node DT offset + * @param in_addr Pointer to the DMA address to translate + * @return translated DMA address or OF_BAD_ADDR on error + */ +u64 fdt_translate_dma_address(const void *blob, int node_offset, + const __be32 *in_addr); + +/** + * Get DMA ranges for a specifc node, this is useful to perform bus->cpu and + * cpu->bus address translations + * + * @param blob Pointer to device tree blob + * @param node_offset Node DT offset + * @param cpu Pointer to variable storing the range's cpu address + * @param bus Pointer to variable storing the range's bus address + * @param size Pointer to variable storing the range's size + * @return translated DMA address or OF_BAD_ADDR on error + */ +int fdt_get_dma_range(const void *blob, int node_offset, phys_addr_t *cpu, + dma_addr_t *bus, u64 *size); + +int fdt_node_offset_by_compat_reg(void *blob, const char *compat, + phys_addr_t compat_off); +int fdt_alloc_phandle(void *blob); +int fdt_set_phandle(void *fdt, int nodeoffset, uint32_t phandle); +unsigned int fdt_create_phandle(void *fdt, int nodeoffset); +int fdt_add_edid(void *blob, const char *compat, unsigned char *buf); + +int fdt_verify_alias_address(void *fdt, int anode, const char *alias, + u64 addr); +u64 fdt_get_base_address(const void *fdt, int node); +int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr, + uint64_t *addr, uint64_t *len); + +enum fdt_status { + FDT_STATUS_OKAY, + FDT_STATUS_DISABLED, + FDT_STATUS_FAIL, + FDT_STATUS_FAIL_ERROR_CODE, +}; +int fdt_set_node_status(void *fdt, int nodeoffset, + enum fdt_status status, unsigned int error_code); +static inline int fdt_status_okay(void *fdt, int nodeoffset) +{ + return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_OKAY, 0); +} +static inline int fdt_status_disabled(void *fdt, int nodeoffset) +{ + return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_DISABLED, 0); +} +static inline int fdt_status_fail(void *fdt, int nodeoffset) +{ + return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_FAIL, 0); +} + +int fdt_set_status_by_alias(void *fdt, const char *alias, + enum fdt_status status, unsigned int error_code); +static inline int fdt_status_okay_by_alias(void *fdt, const char *alias) +{ + return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_OKAY, 0); +} +static inline int fdt_status_disabled_by_alias(void *fdt, const char *alias) +{ + return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_DISABLED, 0); +} +static inline int fdt_status_fail_by_alias(void *fdt, const char *alias) +{ + return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_FAIL, 0); +} + +/* Helper to read a big number; size is in cells (not bytes) */ +static inline u64 fdt_read_number(const fdt32_t *cell, int size) +{ + u64 r = 0; + while (size--) + r = (r << 32) | fdt32_to_cpu(*(cell++)); + return r; +} + +void fdt_support_default_count_cells(const void *blob, int parentoffset, + int *addrc, int *sizec); +int ft_verify_fdt(void *fdt); +int arch_fixup_memory_node(void *blob); + +int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width, + u32 height, u32 stride, const char *format); + +int fdt_overlay_apply_verbose(void *fdt, void *fdto); + +int fdt_valid(struct fdt_header **blobp); + +/** + * fdt_get_cells_len() - Get the length of a type of cell in top-level nodes + * + * Returns the length of the cell type in bytes (4 or 8). + * + * @blob: Pointer to device tree blob + * @nr_cells_name: Name to lookup, e.g. "#address-cells" + */ +int fdt_get_cells_len(const void *blob, char *nr_cells_name); + +#endif /* ifdef CONFIG_OF_LIBFDT */ + +#ifdef USE_HOSTCC +int fdtdec_get_int(const void *blob, int node, const char *prop_name, + int default_val); + +/* + * Count child nodes of one parent node. + * + * @param blob FDT blob + * @param node parent node + * @return number of child node; 0 if there is not child node + */ +int fdtdec_get_child_count(const void *blob, int node); +#endif +#ifdef CONFIG_FMAN_ENET +int fdt_update_ethernet_dt(void *blob); +#endif +#ifdef CONFIG_FSL_MC_ENET +void fdt_fixup_board_enet(void *blob); +#endif +#ifdef CONFIG_CMD_PSTORE +void fdt_fixup_pstore(void *blob); +#endif +#endif /* ifndef __FDT_SUPPORT_H */ diff --git a/roms/u-boot/include/fdtdec.h b/roms/u-boot/include/fdtdec.h new file mode 100644 index 000000000..e0a49b1e5 --- /dev/null +++ b/roms/u-boot/include/fdtdec.h @@ -0,0 +1,1219 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#ifndef __fdtdec_h +#define __fdtdec_h + +/* + * This file contains convenience functions for decoding useful and + * enlightening information from FDTs. It is intended to be used by device + * drivers and board-specific code within U-Boot. It aims to reduce the + * amount of FDT munging required within U-Boot itself, so that driver code + * changes to support FDT are minimized. + */ + +#include +#include + +/* + * A typedef for a physical address. Note that fdt data is always big + * endian even on a litle endian machine. + */ +typedef phys_addr_t fdt_addr_t; +typedef phys_size_t fdt_size_t; + +#define FDT_ADDR_T_NONE (-1U) +#define FDT_SIZE_T_NONE (-1U) + +#ifdef CONFIG_PHYS_64BIT +#define fdt_addr_to_cpu(reg) be64_to_cpu(reg) +#define fdt_size_to_cpu(reg) be64_to_cpu(reg) +#define cpu_to_fdt_addr(reg) cpu_to_be64(reg) +#define cpu_to_fdt_size(reg) cpu_to_be64(reg) +typedef fdt64_t fdt_val_t; +#else +#define fdt_addr_to_cpu(reg) be32_to_cpu(reg) +#define fdt_size_to_cpu(reg) be32_to_cpu(reg) +#define cpu_to_fdt_addr(reg) cpu_to_be32(reg) +#define cpu_to_fdt_size(reg) cpu_to_be32(reg) +typedef fdt32_t fdt_val_t; +#endif + +/* Information obtained about memory from the FDT */ +struct fdt_memory { + fdt_addr_t start; + fdt_addr_t end; +}; + +struct bd_info; + +#ifdef CONFIG_SPL_BUILD +#define SPL_BUILD 1 +#else +#define SPL_BUILD 0 +#endif + +#ifdef CONFIG_OF_PRIOR_STAGE +extern phys_addr_t prior_stage_fdt_address; +#endif + +/* + * Information about a resource. start is the first address of the resource + * and end is the last address (inclusive). The length of the resource will + * be equal to: end - start + 1. + */ +struct fdt_resource { + fdt_addr_t start; + fdt_addr_t end; +}; + +enum fdt_pci_space { + FDT_PCI_SPACE_CONFIG = 0, + FDT_PCI_SPACE_IO = 0x01000000, + FDT_PCI_SPACE_MEM32 = 0x02000000, + FDT_PCI_SPACE_MEM64 = 0x03000000, + FDT_PCI_SPACE_MEM32_PREF = 0x42000000, + FDT_PCI_SPACE_MEM64_PREF = 0x43000000, +}; + +#define FDT_PCI_ADDR_CELLS 3 +#define FDT_PCI_SIZE_CELLS 2 +#define FDT_PCI_REG_SIZE \ + ((FDT_PCI_ADDR_CELLS + FDT_PCI_SIZE_CELLS) * sizeof(u32)) + +/* + * The Open Firmware spec defines PCI physical address as follows: + * + * bits# 31 .... 24 23 .... 16 15 .... 08 07 .... 00 + * + * phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr + * phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh + * phys.lo cell: llllllll llllllll llllllll llllllll + * + * where: + * + * n: is 0 if the address is relocatable, 1 otherwise + * p: is 1 if addressable region is prefetchable, 0 otherwise + * t: is 1 if the address is aliased (for non-relocatable I/O) below 1MB + * (for Memory), or below 64KB (for relocatable I/O) + * ss: is the space code, denoting the address space + * bbbbbbbb: is the 8-bit Bus Number + * ddddd: is the 5-bit Device Number + * fff: is the 3-bit Function Number + * rrrrrrrr: is the 8-bit Register Number + * hhhhhhhh: is a 32-bit unsigned number + * llllllll: is a 32-bit unsigned number + */ +struct fdt_pci_addr { + u32 phys_hi; + u32 phys_mid; + u32 phys_lo; +}; + +extern u8 __dtb_dt_begin[]; /* embedded device tree blob */ +extern u8 __dtb_dt_spl_begin[]; /* embedded device tree blob for SPL/TPL */ + +/** + * Compute the size of a resource. + * + * @param res the resource to operate on + * @return the size of the resource + */ +static inline fdt_size_t fdt_resource_size(const struct fdt_resource *res) +{ + return res->end - res->start + 1; +} + +/** + * Compat types that we know about and for which we might have drivers. + * Each is named COMPAT__ where is the directory + * within drivers. + */ +enum fdt_compat_id { + COMPAT_UNKNOWN, + COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */ + COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */ + COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */ + COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, + /* Tegra124 XUSB pad controller */ + COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL, + /* Tegra210 XUSB pad controller */ + COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */ + COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */ + COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */ + COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */ + COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */ + COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */ + COMPAT_SAMSUNG_EXYNOS_DWMMC, /* Exynos DWMMC controller */ + COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */ + COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ + COMPAT_INTEL_MICROCODE, /* Intel microcode update */ + COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ + COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */ + COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ + COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */ + COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ + COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ + COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ + COMPAT_SUNXI_NAND, /* SUNXI NAND controller */ + COMPAT_ALTERA_SOCFPGA_CLK, /* SoCFPGA Clock initialization */ + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE, /* SoCFPGA pinctrl-single */ + COMPAT_ALTERA_SOCFPGA_H2F_BRG, /* SoCFPGA hps2fpga bridge */ + COMPAT_ALTERA_SOCFPGA_LWH2F_BRG, /* SoCFPGA lwhps2fpga bridge */ + COMPAT_ALTERA_SOCFPGA_F2H_BRG, /* SoCFPGA fpga2hps bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR0, /* SoCFPGA fpga2SDRAM0 bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR1, /* SoCFPGA fpga2SDRAM1 bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2 bridge */ + COMPAT_ALTERA_SOCFPGA_FPGA0, /* SOCFPGA FPGA manager */ + COMPAT_ALTERA_SOCFPGA_NOC, /* SOCFPGA Arria 10 NOC */ + COMPAT_ALTERA_SOCFPGA_CLK_INIT, /* SOCFPGA Arria 10 clk init */ + + COMPAT_COUNT, +}; + +#define MAX_PHANDLE_ARGS 16 +struct fdtdec_phandle_args { + int node; + int args_count; + uint32_t args[MAX_PHANDLE_ARGS]; +}; + +/** + * fdtdec_parse_phandle_with_args() - Find a node pointed by phandle in a list + * + * This function is useful to parse lists of phandles and their arguments. + * + * Example: + * + * phandle1: node1 { + * #list-cells = <2>; + * } + * + * phandle2: node2 { + * #list-cells = <1>; + * } + * + * node3 { + * list = <&phandle1 1 2 &phandle2 3>; + * } + * + * To get a device_node of the `node2' node you may call this: + * fdtdec_parse_phandle_with_args(blob, node3, "list", "#list-cells", 0, 1, + * &args); + * + * (This function is a modified version of __of_parse_phandle_with_args() from + * Linux 3.18) + * + * @blob: Pointer to device tree + * @src_node: Offset of device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies the phandles' arguments count, + * or NULL to use @cells_count + * @cells_count: Cell count to use if @cells_name is NULL + * @index: index of a phandle to parse out + * @out_args: optional pointer to output arguments structure (will be filled) + * @return 0 on success (with @out_args filled out if not NULL), -ENOENT if + * @list_name does not exist, a phandle was not found, @cells_name + * could not be found, the arguments were truncated or there were too + * many arguments. + * + */ +int fdtdec_parse_phandle_with_args(const void *blob, int src_node, + const char *list_name, + const char *cells_name, + int cell_count, int index, + struct fdtdec_phandle_args *out_args); + +/** + * Find the next numbered alias for a peripheral. This is used to enumerate + * all the peripherals of a certain type. + * + * Do the first call with *upto = 0. Assuming /aliases/0 exists then + * this function will return a pointer to the node the alias points to, and + * then update *upto to 1. Next time you call this function, the next node + * will be returned. + * + * All nodes returned will match the compatible ID, as it is assumed that + * all peripherals use the same driver. + * + * @param blob FDT blob to use + * @param name Root name of alias to search for + * @param id Compatible ID to look for + * @return offset of next compatible node, or -FDT_ERR_NOTFOUND if no more + */ +int fdtdec_next_alias(const void *blob, const char *name, + enum fdt_compat_id id, int *upto); + +/** + * Find the compatible ID for a given node. + * + * Generally each node has at least one compatible string attached to it. + * This function looks through our list of known compatible strings and + * returns the corresponding ID which matches the compatible string. + * + * @param blob FDT blob to use + * @param node Node containing compatible string to find + * @return compatible ID, or COMPAT_UNKNOWN if we cannot find a match + */ +enum fdt_compat_id fdtdec_lookup(const void *blob, int node); + +/** + * Find the next compatible node for a peripheral. + * + * Do the first call with node = 0. This function will return a pointer to + * the next compatible node. Next time you call this function, pass the + * value returned, and the next node will be provided. + * + * @param blob FDT blob to use + * @param node Start node for search + * @param id Compatible ID to look for (enum fdt_compat_id) + * @return offset of next compatible node, or -FDT_ERR_NOTFOUND if no more + */ +int fdtdec_next_compatible(const void *blob, int node, + enum fdt_compat_id id); + +/** + * Find the next compatible subnode for a peripheral. + * + * Do the first call with node set to the parent and depth = 0. This + * function will return the offset of the next compatible node. Next time + * you call this function, pass the node value returned last time, with + * depth unchanged, and the next node will be provided. + * + * @param blob FDT blob to use + * @param node Start node for search + * @param id Compatible ID to look for (enum fdt_compat_id) + * @param depthp Current depth (set to 0 before first call) + * @return offset of next compatible node, or -FDT_ERR_NOTFOUND if no more + */ +int fdtdec_next_compatible_subnode(const void *blob, int node, + enum fdt_compat_id id, int *depthp); + +/* + * Look up an address property in a node and return the parsed address, and + * optionally the parsed size. + * + * This variant assumes a known and fixed number of cells are used to + * represent the address and size. + * + * You probably don't want to use this function directly except to parse + * non-standard properties, and never to parse the "reg" property. Instead, + * use one of the "auto" variants below, which automatically honor the + * #address-cells and #size-cells properties in the parent node. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param index which address to retrieve from a list of addresses. Often 0. + * @param na the number of cells used to represent an address + * @param ns the number of cells used to represent a size + * @param sizep a pointer to store the size into. Use NULL if not required + * @param translate Indicates whether to translate the returned value + * using the parent node's ranges property. + * @return address, if found, or FDT_ADDR_T_NONE if not + */ +fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node, + const char *prop_name, int index, int na, int ns, + fdt_size_t *sizep, bool translate); + +/* + * Look up an address property in a node and return the parsed address, and + * optionally the parsed size. + * + * This variant automatically determines the number of cells used to represent + * the address and size by parsing the provided parent node's #address-cells + * and #size-cells properties. + * + * @param blob FDT blob + * @param parent parent node of @node + * @param node node to examine + * @param prop_name name of property to find + * @param index which address to retrieve from a list of addresses. Often 0. + * @param sizep a pointer to store the size into. Use NULL if not required + * @param translate Indicates whether to translate the returned value + * using the parent node's ranges property. + * @return address, if found, or FDT_ADDR_T_NONE if not + */ +fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent, + int node, const char *prop_name, int index, fdt_size_t *sizep, + bool translate); + +/* + * Look up an address property in a node and return the parsed address, and + * optionally the parsed size. + * + * This variant automatically determines the number of cells used to represent + * the address and size by parsing the parent node's #address-cells + * and #size-cells properties. The parent node is automatically found. + * + * The automatic parent lookup implemented by this function is slow. + * Consequently, fdtdec_get_addr_size_auto_parent() should be used where + * possible. + * + * @param blob FDT blob + * @param parent parent node of @node + * @param node node to examine + * @param prop_name name of property to find + * @param index which address to retrieve from a list of addresses. Often 0. + * @param sizep a pointer to store the size into. Use NULL if not required + * @param translate Indicates whether to translate the returned value + * using the parent node's ranges property. + * @return address, if found, or FDT_ADDR_T_NONE if not + */ +fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node, + const char *prop_name, int index, fdt_size_t *sizep, + bool translate); + +/* + * Look up an address property in a node and return the parsed address. + * + * This variant hard-codes the number of cells used to represent the address + * and size based on sizeof(fdt_addr_t) and sizeof(fdt_size_t). It also + * always returns the first address value in the property (index 0). + * + * Use of this function is not recommended due to the hard-coding of cell + * counts. There is no programmatic validation that these hard-coded values + * actually match the device tree content in any way at all. This assumption + * can be satisfied by manually ensuring CONFIG_PHYS_64BIT is appropriately + * set in the U-Boot build and exercising strict control over DT content to + * ensure use of matching #address-cells/#size-cells properties. However, this + * approach is error-prone; those familiar with DT will not expect the + * assumption to exist, and could easily invalidate it. If the assumption is + * invalidated, this function will not report the issue, and debugging will + * be required. Instead, use fdtdec_get_addr_size_auto_parent(). + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @return address, if found, or FDT_ADDR_T_NONE if not + */ +fdt_addr_t fdtdec_get_addr(const void *blob, int node, + const char *prop_name); + +/* + * Look up an address property in a node and return the parsed address, and + * optionally the parsed size. + * + * This variant hard-codes the number of cells used to represent the address + * and size based on sizeof(fdt_addr_t) and sizeof(fdt_size_t). It also + * always returns the first address value in the property (index 0). + * + * Use of this function is not recommended due to the hard-coding of cell + * counts. There is no programmatic validation that these hard-coded values + * actually match the device tree content in any way at all. This assumption + * can be satisfied by manually ensuring CONFIG_PHYS_64BIT is appropriately + * set in the U-Boot build and exercising strict control over DT content to + * ensure use of matching #address-cells/#size-cells properties. However, this + * approach is error-prone; those familiar with DT will not expect the + * assumption to exist, and could easily invalidate it. If the assumption is + * invalidated, this function will not report the issue, and debugging will + * be required. Instead, use fdtdec_get_addr_size_auto_parent(). + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param sizep a pointer to store the size into. Use NULL if not required + * @return address, if found, or FDT_ADDR_T_NONE if not + */ +fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, + const char *prop_name, fdt_size_t *sizep); + +/** + * Look at the compatible property of a device node that represents a PCI + * device and extract pci vendor id and device id from it. + * + * @param blob FDT blob + * @param node node to examine + * @param vendor vendor id of the pci device + * @param device device id of the pci device + * @return 0 if ok, negative on error + */ +int fdtdec_get_pci_vendev(const void *blob, int node, + u16 *vendor, u16 *device); + +/** + * Look at the pci address of a device node that represents a PCI device + * and return base address of the pci device's registers. + * + * @param dev device to examine + * @param addr pci address in the form of fdt_pci_addr + * @param bar returns base address of the pci device's registers + * @return 0 if ok, negative on error + */ +int fdtdec_get_pci_bar32(const struct udevice *dev, struct fdt_pci_addr *addr, + u32 *bar); + +/** + * Look at the bus range property of a device node and return the pci bus + * range for this node. + * The property must hold one fdt_pci_addr with a length. + * @param blob FDT blob + * @param node node to examine + * @param res the resource structure to return the bus range + * @return 0 if ok, negative on error + */ + +int fdtdec_get_pci_bus_range(const void *blob, int node, + struct fdt_resource *res); + +/** + * Look up a 32-bit integer property in a node and return it. The property + * must have at least 4 bytes of data. The value of the first cell is + * returned. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param default_val default value to return if the property is not found + * @return integer value, if found, or default_val if not + */ +s32 fdtdec_get_int(const void *blob, int node, const char *prop_name, + s32 default_val); + +/** + * Unsigned version of fdtdec_get_int. The property must have at least + * 4 bytes of data. The value of the first cell is returned. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param default_val default value to return if the property is not found + * @return unsigned integer value, if found, or default_val if not + */ +unsigned int fdtdec_get_uint(const void *blob, int node, const char *prop_name, + unsigned int default_val); + +/** + * Get a variable-sized number from a property + * + * This reads a number from one or more cells. + * + * @param ptr Pointer to property + * @param cells Number of cells containing the number + * @return the value in the cells + */ +u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells); + +/** + * Look up a 64-bit integer property in a node and return it. The property + * must have at least 8 bytes of data (2 cells). The first two cells are + * concatenated to form a 8 bytes value, where the first cell is top half and + * the second cell is bottom half. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param default_val default value to return if the property is not found + * @return integer value, if found, or default_val if not + */ +uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name, + uint64_t default_val); + +/** + * Checks whether a node is enabled. + * This looks for a 'status' property. If this exists, then returns 1 if + * the status is 'ok' and 0 otherwise. If there is no status property, + * it returns 1 on the assumption that anything mentioned should be enabled + * by default. + * + * @param blob FDT blob + * @param node node to examine + * @return integer value 0 (not enabled) or 1 (enabled) + */ +int fdtdec_get_is_enabled(const void *blob, int node); + +/** + * Make sure we have a valid fdt available to control U-Boot. + * + * If not, a message is printed to the console if the console is ready. + * + * @return 0 if all ok, -1 if not + */ +int fdtdec_prepare_fdt(void); + +/** + * Checks that we have a valid fdt available to control U-Boot. + + * However, if not then for the moment nothing is done, since this function + * is called too early to panic(). + * + * @returns 0 + */ +int fdtdec_check_fdt(void); + +/** + * Find the nodes for a peripheral and return a list of them in the correct + * order. This is used to enumerate all the peripherals of a certain type. + * + * To use this, optionally set up a /aliases node with alias properties for + * a peripheral. For example, for usb you could have: + * + * aliases { + * usb0 = "/ehci@c5008000"; + * usb1 = "/ehci@c5000000"; + * }; + * + * Pass "usb" as the name to this function and will return a list of two + * nodes offsets: /ehci@c5008000 and ehci@c5000000. + * + * All nodes returned will match the compatible ID, as it is assumed that + * all peripherals use the same driver. + * + * If no alias node is found, then the node list will be returned in the + * order found in the fdt. If the aliases mention a node which doesn't + * exist, then this will be ignored. If nodes are found with no aliases, + * they will be added in any order. + * + * If there is a gap in the aliases, then this function return a 0 node at + * that position. The return value will also count these gaps. + * + * This function checks node properties and will not return nodes which are + * marked disabled (status = "disabled"). + * + * @param blob FDT blob to use + * @param name Root name of alias to search for + * @param id Compatible ID to look for + * @param node_list Place to put list of found nodes + * @param maxcount Maximum number of nodes to find + * @return number of nodes found on success, FDT_ERR_... on error + */ +int fdtdec_find_aliases_for_id(const void *blob, const char *name, + enum fdt_compat_id id, int *node_list, int maxcount); + +/* + * This function is similar to fdtdec_find_aliases_for_id() except that it + * adds to the node_list that is passed in. Any 0 elements are considered + * available for allocation - others are considered already used and are + * skipped. + * + * You can use this by calling fdtdec_find_aliases_for_id() with an + * uninitialised array, then setting the elements that are returned to -1, + * say, then calling this function, perhaps with a different compat id. + * Any elements you get back that are >0 are new nodes added by the call + * to this function. + * + * Note that if you have some nodes with aliases and some without, you are + * sailing close to the wind. The call to fdtdec_find_aliases_for_id() with + * one compat_id may fill in positions for which you have aliases defined + * for another compat_id. When you later call *this* function with the second + * compat_id, the alias positions may already be used. A debug warning may + * be generated in this case, but it is safest to define aliases for all + * nodes when you care about the ordering. + */ +int fdtdec_add_aliases_for_id(const void *blob, const char *name, + enum fdt_compat_id id, int *node_list, int maxcount); + +/** + * Get the alias sequence number of a node + * + * This works out whether a node is pointed to by an alias, and if so, the + * sequence number of that alias. Aliases are of the form where + * is the sequence number. For example spi2 would be sequence number + * 2. + * + * @param blob Device tree blob (if NULL, then error is returned) + * @param base Base name for alias (before the underscore) + * @param node Node to look up + * @param seqp This is set to the sequence number if one is found, + * but otherwise the value is left alone + * @return 0 if a sequence was found, -ve if not + */ +int fdtdec_get_alias_seq(const void *blob, const char *base, int node, + int *seqp); + +/** + * Get the highest alias number for susbystem. + * + * It parses all aliases and find out highest recorded alias for subsystem. + * Aliases are of the form where is the sequence number. + * + * @param blob Device tree blob (if NULL, then error is returned) + * @param base Base name for alias susbystem (before the number) + * + * @return 0 highest alias ID, -1 if not found + */ +int fdtdec_get_alias_highest_id(const void *blob, const char *base); + +/** + * Get a property from the /chosen node + * + * @param blob Device tree blob (if NULL, then NULL is returned) + * @param name Property name to look up + * @return Value of property, or NULL if it does not exist + */ +const char *fdtdec_get_chosen_prop(const void *blob, const char *name); + +/** + * Get the offset of the given /chosen node + * + * This looks up a property in /chosen containing the path to another node, + * then finds the offset of that node. + * + * @param blob Device tree blob (if NULL, then error is returned) + * @param name Property name, e.g. "stdout-path" + * @return Node offset referred to by that chosen node, or -ve FDT_ERR_... + */ +int fdtdec_get_chosen_node(const void *blob, const char *name); + +/* + * Get the name for a compatible ID + * + * @param id Compatible ID to look for + * @return compatible string for that id + */ +const char *fdtdec_get_compatible(enum fdt_compat_id id); + +/* Look up a phandle and follow it to its node. Then return the offset + * of that node. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @return node offset if found, -ve error code on error + */ +int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name); + +/** + * Look up a property in a node and return its contents in an integer + * array of given length. The property must have at least enough data for + * the array (4*count bytes). It may have more, but this will be ignored. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param array array to fill with data + * @param count number of array elements + * @return 0 if ok, or -FDT_ERR_NOTFOUND if the property is not found, + * or -FDT_ERR_BADLAYOUT if not enough data + */ +int fdtdec_get_int_array(const void *blob, int node, const char *prop_name, + u32 *array, int count); + +/** + * Look up a property in a node and return its contents in an integer + * array of given length. The property must exist but may have less data that + * expected (4*count bytes). It may have more, but this will be ignored. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param array array to fill with data + * @param count number of array elements + * @return number of array elements if ok, or -FDT_ERR_NOTFOUND if the + * property is not found + */ +int fdtdec_get_int_array_count(const void *blob, int node, + const char *prop_name, u32 *array, int count); + +/** + * Look up a property in a node and return a pointer to its contents as a + * unsigned int array of given length. The property must have at least enough + * data for the array ('count' cells). It may have more, but this will be + * ignored. The data is not copied. + * + * Note that you must access elements of the array with fdt32_to_cpu(), + * since the elements will be big endian even on a little endian machine. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param count number of array elements + * @return pointer to array if found, or NULL if the property is not + * found or there is not enough data + */ +const u32 *fdtdec_locate_array(const void *blob, int node, + const char *prop_name, int count); + +/** + * Look up a boolean property in a node and return it. + * + * A boolean properly is true if present in the device tree and false if not + * present, regardless of its value. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @return 1 if the properly is present; 0 if it isn't present + */ +int fdtdec_get_bool(const void *blob, int node, const char *prop_name); + +/* + * Count child nodes of one parent node. + * + * @param blob FDT blob + * @param node parent node + * @return number of child node; 0 if there is not child node + */ +int fdtdec_get_child_count(const void *blob, int node); + +/** + * Look in the FDT for a config item with the given name and return its value + * as a 32-bit integer. The property must have at least 4 bytes of data. The + * value of the first cell is returned. + * + * @param blob FDT blob to use + * @param prop_name Node property name + * @param default_val default value to return if the property is not found + * @return integer value, if found, or default_val if not + */ +int fdtdec_get_config_int(const void *blob, const char *prop_name, + int default_val); + +/** + * Look in the FDT for a config item with the given name + * and return whether it exists. + * + * @param blob FDT blob + * @param prop_name property name to look up + * @return 1, if it exists, or 0 if not + */ +int fdtdec_get_config_bool(const void *blob, const char *prop_name); + +/** + * Look in the FDT for a config item with the given name and return its value + * as a string. + * + * @param blob FDT blob + * @param prop_name property name to look up + * @returns property string, NULL on error. + */ +char *fdtdec_get_config_string(const void *blob, const char *prop_name); + +/* + * Look up a property in a node and return its contents in a byte + * array of given length. The property must have at least enough data for + * the array (count bytes). It may have more, but this will be ignored. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param array array to fill with data + * @param count number of array elements + * @return 0 if ok, or -FDT_ERR_MISSING if the property is not found, + * or -FDT_ERR_BADLAYOUT if not enough data + */ +int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name, + u8 *array, int count); + +/** + * Look up a property in a node and return a pointer to its contents as a + * byte array of given length. The property must have at least enough data + * for the array (count bytes). It may have more, but this will be ignored. + * The data is not copied. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param count number of array elements + * @return pointer to byte array if found, or NULL if the property is not + * found or there is not enough data + */ +const u8 *fdtdec_locate_byte_array(const void *blob, int node, + const char *prop_name, int count); + +/** + * Obtain an indexed resource from a device property. + * + * @param fdt FDT blob + * @param node node to examine + * @param property name of the property to parse + * @param index index of the resource to retrieve + * @param res returns the resource + * @return 0 if ok, negative on error + */ +int fdt_get_resource(const void *fdt, int node, const char *property, + unsigned int index, struct fdt_resource *res); + +/** + * Obtain a named resource from a device property. + * + * Look up the index of the name in a list of strings and return the resource + * at that index. + * + * @param fdt FDT blob + * @param node node to examine + * @param property name of the property to parse + * @param prop_names name of the property containing the list of names + * @param name the name of the entry to look up + * @param res returns the resource + */ +int fdt_get_named_resource(const void *fdt, int node, const char *property, + const char *prop_names, const char *name, + struct fdt_resource *res); + +/* Display timings from linux include/video/display_timing.h */ +enum display_flags { + DISPLAY_FLAGS_HSYNC_LOW = 1 << 0, + DISPLAY_FLAGS_HSYNC_HIGH = 1 << 1, + DISPLAY_FLAGS_VSYNC_LOW = 1 << 2, + DISPLAY_FLAGS_VSYNC_HIGH = 1 << 3, + + /* data enable flag */ + DISPLAY_FLAGS_DE_LOW = 1 << 4, + DISPLAY_FLAGS_DE_HIGH = 1 << 5, + /* drive data on pos. edge */ + DISPLAY_FLAGS_PIXDATA_POSEDGE = 1 << 6, + /* drive data on neg. edge */ + DISPLAY_FLAGS_PIXDATA_NEGEDGE = 1 << 7, + DISPLAY_FLAGS_INTERLACED = 1 << 8, + DISPLAY_FLAGS_DOUBLESCAN = 1 << 9, + DISPLAY_FLAGS_DOUBLECLK = 1 << 10, +}; + +/* + * A single signal can be specified via a range of minimal and maximal values + * with a typical value, that lies somewhere inbetween. + */ +struct timing_entry { + u32 min; + u32 typ; + u32 max; +}; + +/* + * Single "mode" entry. This describes one set of signal timings a display can + * have in one setting. This struct can later be converted to struct videomode + * (see include/video/videomode.h). As each timing_entry can be defined as a + * range, one struct display_timing may become multiple struct videomodes. + * + * Example: hsync active high, vsync active low + * + * Active Video + * Video ______________________XXXXXXXXXXXXXXXXXXXXXX_____________________ + * |<- sync ->|<- back ->|<----- active ----->|<- front ->|<- sync.. + * | | porch | | porch | + * + * HSync _|¯¯¯¯¯¯¯¯¯¯|___________________________________________|¯¯¯¯¯¯¯¯¯ + * + * VSync ¯|__________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_________ + */ +struct display_timing { + struct timing_entry pixelclock; + + struct timing_entry hactive; /* hor. active video */ + struct timing_entry hfront_porch; /* hor. front porch */ + struct timing_entry hback_porch; /* hor. back porch */ + struct timing_entry hsync_len; /* hor. sync len */ + + struct timing_entry vactive; /* ver. active video */ + struct timing_entry vfront_porch; /* ver. front porch */ + struct timing_entry vback_porch; /* ver. back porch */ + struct timing_entry vsync_len; /* ver. sync len */ + + enum display_flags flags; /* display flags */ + bool hdmi_monitor; /* is hdmi monitor? */ +}; + +/** + * fdtdec_decode_display_timing() - decode display timings + * + * Decode display timings from the supplied 'display-timings' node. + * See doc/device-tree-bindings/video/display-timing.txt for binding + * information. + * + * @param blob FDT blob + * @param node 'display-timing' node containing the timing subnodes + * @param index Index number to read (0=first timing subnode) + * @param config Place to put timings + * @return 0 if OK, -FDT_ERR_NOTFOUND if not found + */ +int fdtdec_decode_display_timing(const void *blob, int node, int index, + struct display_timing *config); + +/** + * fdtdec_setup_mem_size_base() - decode and setup gd->ram_size and + * gd->ram_start + * + * Decode the /memory 'reg' property to determine the size and start of the + * first memory bank, populate the global data with the size and start of the + * first bank of memory. + * + * This function should be called from a boards dram_init(). This helper + * function allows for boards to query the device tree for DRAM size and start + * address instead of hard coding the value in the case where the memory size + * and start address cannot be detected automatically. + * + * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or + * invalid + */ +int fdtdec_setup_mem_size_base(void); + +/** + * fdtdec_setup_mem_size_base_lowest() - decode and setup gd->ram_size and + * gd->ram_start by lowest available memory base + * + * Decode the /memory 'reg' property to determine the lowest start of the memory + * bank bank and populate the global data with it. + * + * This function should be called from a boards dram_init(). This helper + * function allows for boards to query the device tree for DRAM size and start + * address instead of hard coding the value in the case where the memory size + * and start address cannot be detected automatically. + * + * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or + * invalid + */ +int fdtdec_setup_mem_size_base_lowest(void); + +/** + * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram + * + * Decode the /memory 'reg' property to determine the address and size of the + * memory banks. Use this data to populate the global data board info with the + * phys address and size of memory banks. + * + * This function should be called from a boards dram_init_banksize(). This + * helper function allows for boards to query the device tree for memory bank + * information instead of hard coding the information in cases where it cannot + * be detected automatically. + * + * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or + * invalid + */ +int fdtdec_setup_memory_banksize(void); + +/** + * fdtdec_set_ethernet_mac_address() - set MAC address for default interface + * + * Looks up the default interface via the "ethernet" alias (in the /aliases + * node) and stores the given MAC in its "local-mac-address" property. This + * is useful on platforms that store the MAC address in a custom location. + * Board code can call this in the late init stage to make sure that the + * interface device tree node has the right MAC address configured for the + * Ethernet uclass to pick it up. + * + * Typically the FDT passed into this function will be U-Boot's control DTB. + * Given that a lot of code may be holding offsets to various nodes in that + * tree, this code will only set the "local-mac-address" property in-place, + * which means that it needs to exist and have space for the 6-byte address. + * This ensures that the operation is non-destructive and does not invalidate + * offsets that other drivers may be using. + * + * @param fdt FDT blob + * @param mac buffer containing the MAC address to set + * @param size size of MAC address + * @return 0 on success or a negative error code on failure + */ +int fdtdec_set_ethernet_mac_address(void *fdt, const u8 *mac, size_t size); + +/** + * fdtdec_set_phandle() - sets the phandle of a given node + * + * @param blob FDT blob + * @param node offset in the FDT blob of the node whose phandle is to + * be set + * @param phandle phandle to set for the given node + * @return 0 on success or a negative error code on failure + */ +static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) +{ + return fdt_setprop_u32(blob, node, "phandle", phandle); +} + +/** + * fdtdec_add_reserved_memory() - add or find a reserved-memory node + * + * If a reserved-memory node already exists for the given carveout, a phandle + * for that node will be returned. Otherwise a new node will be created and a + * phandle corresponding to it will be returned. + * + * See Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + * for details on how to use reserved memory regions. + * + * As an example, consider the following code snippet: + * + * struct fdt_memory fb = { + * .start = 0x92cb3000, + * .end = 0x934b2fff, + * }; + * uint32_t phandle; + * + * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle, false); + * + * This results in the following subnode being added to the top-level + * /reserved-memory node: + * + * reserved-memory { + * #address-cells = <0x00000002>; + * #size-cells = <0x00000002>; + * ranges; + * + * framebuffer@92cb3000 { + * reg = <0x00000000 0x92cb3000 0x00000000 0x00800000>; + * phandle = <0x0000004d>; + * }; + * }; + * + * If the top-level /reserved-memory node does not exist, it will be created. + * The phandle returned from the function call can be used to reference this + * reserved memory region from other nodes. + * + * See fdtdec_set_carveout() for a more elaborate example. + * + * @param blob FDT blob + * @param basename base name of the node to create + * @param carveout information about the carveout region + * @param phandlep return location for the phandle of the carveout region + * can be NULL if no phandle should be added + * @param no_map add "no-map" property if true + * @return 0 on success or a negative error code on failure + */ +int fdtdec_add_reserved_memory(void *blob, const char *basename, + const struct fdt_memory *carveout, + uint32_t *phandlep, bool no_map); + +/** + * fdtdec_get_carveout() - reads a carveout from an FDT + * + * Reads information about a carveout region from an FDT. The carveout is a + * referenced by its phandle that is read from a given property in a given + * node. + * + * @param blob FDT blob + * @param node name of a node + * @param name name of the property in the given node that contains + * the phandle for the carveout + * @param index index of the phandle for which to read the carveout + * @param carveout return location for the carveout information + * @return 0 on success or a negative error code on failure + */ +int fdtdec_get_carveout(const void *blob, const char *node, const char *name, + unsigned int index, struct fdt_memory *carveout); + +/** + * fdtdec_set_carveout() - sets a carveout region for a given node + * + * Sets a carveout region for a given node. If a reserved-memory node already + * exists for the carveout, the phandle for that node will be reused. If no + * such node exists, a new one will be created and a phandle to it stored in + * a specified property of the given node. + * + * As an example, consider the following code snippet: + * + * const char *node = "/host1x@50000000/dc@54240000"; + * struct fdt_memory fb = { + * .start = 0x92cb3000, + * .end = 0x934b2fff, + * }; + * + * fdtdec_set_carveout(fdt, node, "memory-region", 0, "framebuffer", &fb); + * + * dc@54200000 is a display controller and was set up by the bootloader to + * scan out the framebuffer specified by "fb". This would cause the following + * reserved memory region to be added: + * + * reserved-memory { + * #address-cells = <0x00000002>; + * #size-cells = <0x00000002>; + * ranges; + * + * framebuffer@92cb3000 { + * reg = <0x00000000 0x92cb3000 0x00000000 0x00800000>; + * phandle = <0x0000004d>; + * }; + * }; + * + * A "memory-region" property will also be added to the node referenced by the + * offset parameter. + * + * host1x@50000000 { + * ... + * + * dc@54240000 { + * ... + * memory-region = <0x0000004d>; + * ... + * }; + * + * ... + * }; + * + * @param blob FDT blob + * @param node name of the node to add the carveout to + * @param prop_name name of the property in which to store the phandle of + * the carveout + * @param index index of the phandle to store + * @param name base name of the reserved-memory node to create + * @param carveout information about the carveout to add + * @return 0 on success or a negative error code on failure + */ +int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, + unsigned int index, const char *name, + const struct fdt_memory *carveout); + +/** + * Set up the device tree ready for use + */ +int fdtdec_setup(void); + +/** + * Perform board-specific early DT adjustments + */ +int fdtdec_board_setup(const void *fdt_blob); + +#if CONFIG_IS_ENABLED(MULTI_DTB_FIT) +/** + * fdtdec_resetup() - Set up the device tree again + * + * The main difference with fdtdec_setup() is that it returns if the fdt has + * changed because a better match has been found. + * This is typically used for boards that rely on a DM driver to detect the + * board type. This function sould be called by the board code after the stuff + * needed by board_fit_config_name_match() to operate porperly is available. + * If this functions signals that a rescan is necessary, the board code must + * unbind all the drivers using dm_uninit() and then rescan the DT with + * dm_init_and_scan(). + * + * @param rescan Returns a flag indicating that fdt has changed and rescanning + * the fdt is required + * + * @return 0 if OK, -ve on error + */ +int fdtdec_resetup(int *rescan); +#endif + +/** + * Board-specific FDT initialization. Returns the address to a device tree blob. + * Called when CONFIG_OF_BOARD is defined, or if CONFIG_OF_SEPARATE is defined + * and the board implements it. + */ +void *board_fdt_blob_setup(void); + +/* + * Decode the size of memory + * + * RAM size is normally set in a /memory node and consists of a list of + * (base, size) cells in the 'reg' property. This information is used to + * determine the total available memory as well as the address and size + * of each bank. + * + * Optionally the memory configuration can vary depending on a board id, + * typically read from strapping resistors or an EEPROM on the board. + * + * Finally, memory size can be detected (within certain limits) by probing + * the available memory. It is safe to do so within the limits provides by + * the board's device tree information. This makes it possible to produce + * boards with different memory sizes, where the device tree specifies the + * maximum memory configuration, and the smaller memory configuration is + * probed. + * + * This function decodes that information, returning the memory base address, + * size and bank information. See the memory.txt binding for full + * documentation. + * + * @param blob Device tree blob + * @param area Name of node to check (NULL means "/memory") + * @param board_id Board ID to look up + * @param basep Returns base address of first memory bank (NULL to + * ignore) + * @param sizep Returns total memory size (NULL to ignore) + * @param bd Updated with the memory bank information (NULL to skip) + * @return 0 if OK, -ve on error + */ +int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, + phys_addr_t *basep, phys_size_t *sizep, + struct bd_info *bd); + +#endif diff --git a/roms/u-boot/include/fis.h b/roms/u-boot/include/fis.h new file mode 100644 index 000000000..419807f1f --- /dev/null +++ b/roms/u-boot/include/fis.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2008 Freescale Semiconductor, Inc. + * Dave Liu + */ + +#ifndef __FIS_H__ +#define __FIS_H__ +/* +* Register - Host to Device FIS +*/ +typedef struct sata_fis_h2d { + u8 fis_type; + u8 pm_port_c; + u8 command; + u8 features; + u8 lba_low; + u8 lba_mid; + u8 lba_high; + u8 device; + u8 lba_low_exp; + u8 lba_mid_exp; + u8 lba_high_exp; + u8 features_exp; + u8 sector_count; + u8 sector_count_exp; + u8 res1; + u8 control; + u8 res2[4]; +} __attribute__ ((packed)) sata_fis_h2d_t; + +/* +* Register - Host to Device FIS for read/write FPDMA queued +*/ +typedef struct sata_fis_h2d_ncq { + u8 fis_type; + u8 pm_port_c; + u8 command; + u8 sector_count_low; + u8 lba_low; + u8 lba_mid; + u8 lba_high; + u8 device; + u8 lba_low_exp; + u8 lba_mid_exp; + u8 lba_high_exp; + u8 sector_count_high; + u8 tag; + u8 res1; + u8 res2; + u8 control; + u8 res3[4]; +} __attribute__ ((packed)) sata_fis_h2d_ncq_t; + +/* +* Register - Device to Host FIS +*/ +typedef struct sata_fis_d2h { + u8 fis_type; + u8 pm_port_i; + u8 status; + u8 error; + u8 lba_low; + u8 lba_mid; + u8 lba_high; + u8 device; + u8 lba_low_exp; + u8 lba_mid_exp; + u8 lba_high_exp; + u8 res1; + u8 sector_count; + u8 sector_count_exp; + u8 res2[2]; + u8 res3[4]; +} __attribute__ ((packed)) sata_fis_d2h_t; + +/* +* DMA Setup - Device to Host or Host to Device FIS +*/ +typedef struct sata_fis_dma_setup { + u8 fis_type; + u8 pm_port_dir_int_act; + u8 res1; + u8 res2; + u32 dma_buffer_id_low; + u32 dma_buffer_id_high; + u32 res3; + u32 dma_buffer_offset; + u32 dma_transfer_count; + u32 res4; +} __attribute__ ((packed)) sata_fis_dma_setup_t; + +/* +* PIO Setup - Device to Host FIS +*/ +typedef struct sata_fis_pio_setup { + u8 fis_type; + u8 pm_port_dir_int; + u8 status; + u8 error; + u8 lba_low; + u8 lba_mid; + u8 lba_high; + u8 res1; + u8 lba_low_exp; + u8 lba_mid_exp; + u8 lba_high_exp; + u8 res2; + u8 sector_count; + u8 sector_count_exp; + u8 res3; + u8 e_status; + u16 transfer_count; + u16 res4; +} __attribute__ ((packed)) sata_fis_pio_setup_t; + +/* +* Data - Host to Device or Device to Host FIS +*/ +typedef struct sata_fis_data { + u8 fis_type; + u8 pm_port; + u8 res1; + u8 res2; + u32 data[2048]; +} __attribute__ ((packed)) sata_fis_data_t; + +/* fis_type - SATA FIS type + */ +enum sata_fis_type { + SATA_FIS_TYPE_REGISTER_H2D = 0x27, + SATA_FIS_TYPE_REGISTER_D2H = 0x34, + SATA_FIS_TYPE_DMA_ACT_D2H = 0x39, + SATA_FIS_TYPE_DMA_SETUP_BI = 0x41, + SATA_FIS_TYPE_DATA_BI = 0x46, + SATA_FIS_TYPE_BIST_ACT_BI = 0x58, + SATA_FIS_TYPE_PIO_SETUP_D2H = 0x5F, + SATA_FIS_TYPE_SET_DEVICE_BITS_D2H = 0xA1, +}; + +#endif /* __FIS_H__ */ diff --git a/roms/u-boot/include/flash.h b/roms/u-boot/include/flash.h new file mode 100644 index 000000000..42b18a604 --- /dev/null +++ b/roms/u-boot/include/flash.h @@ -0,0 +1,517 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef _FLASH_H_ +#define _FLASH_H_ + +#ifndef CONFIG_SYS_MAX_FLASH_SECT +#define CONFIG_SYS_MAX_FLASH_SECT 512 +#endif + +/*----------------------------------------------------------------------- + * FLASH Info: contains chip specific data, per FLASH bank + */ + +typedef struct { + ulong size; /* total bank size in bytes */ + ushort sector_count; /* number of erase units */ + ulong flash_id; /* combined device & manufacturer code */ + ulong start[CONFIG_SYS_MAX_FLASH_SECT]; /* virtual sector start address */ + uchar protect[CONFIG_SYS_MAX_FLASH_SECT]; /* sector protection status */ +#ifdef CONFIG_SYS_FLASH_CFI + uchar portwidth; /* the width of the port */ + uchar chipwidth; /* the width of the chip */ + uchar chip_lsb; /* extra Least Significant Bit in the */ + /* address of chip */ + ushort buffer_size; /* # of bytes in write buffer */ + ulong erase_blk_tout; /* maximum block erase timeout */ + ulong write_tout; /* maximum write timeout */ + ulong buffer_write_tout; /* maximum buffer write timeout */ + ushort vendor; /* the primary vendor id */ + ushort cmd_reset; /* vendor specific reset command */ + uchar cmd_erase_sector; /* vendor specific erase sect. command */ + ushort interface; /* used for x8/x16 adjustments */ + ushort legacy_unlock; /* support Intel legacy (un)locking */ + ushort manufacturer_id; /* manufacturer id */ + ushort device_id; /* device id */ + ushort device_id2; /* extended device id */ + ushort ext_addr; /* extended query table address */ + ushort cfi_version; /* cfi version */ + ushort cfi_offset; /* offset for cfi query */ + ulong addr_unlock1; /* unlock address 1 for AMD flash roms */ + ulong addr_unlock2; /* unlock address 2 for AMD flash roms */ + uchar sr_supported; /* status register supported */ + const char *name; /* human-readable name */ +#endif +#ifdef CONFIG_DM_MTD + struct mtd_info *mtd; +#endif +#ifdef CONFIG_CFI_FLASH /* DM-specific parts */ + struct udevice *dev; + phys_addr_t base; +#endif +} flash_info_t; + +extern flash_info_t flash_info[]; /* info for FLASH chips */ + +typedef unsigned long flash_sect_t; + +/* + * Values for the width of the port + */ +#define FLASH_CFI_8BIT 0x01 +#define FLASH_CFI_16BIT 0x02 +#define FLASH_CFI_32BIT 0x04 +#define FLASH_CFI_64BIT 0x08 +/* + * Values for the width of the chip + */ +#define FLASH_CFI_BY8 0x01 +#define FLASH_CFI_BY16 0x02 +#define FLASH_CFI_BY32 0x04 +#define FLASH_CFI_BY64 0x08 +/* + * Values for the flash device interface + */ +#define FLASH_CFI_X8 0x00 +#define FLASH_CFI_X16 0x01 +#define FLASH_CFI_X8X16 0x02 +#define FLASH_CFI_X16X32 0x05 + +/* convert between bit value and numeric value */ +#define CFI_FLASH_SHIFT_WIDTH 3 + +/* Prototypes */ + +unsigned long flash_init(void); +void flash_print_info(flash_info_t *info); +int flash_erase(flash_info_t *info, int s_first, int s_last); +int flash_sect_erase(ulong addr_first, ulong addr_last); +int flash_sect_protect(int flag, ulong addr_first, ulong addr_last); +int flash_sect_roundb(ulong *addr); +unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect); +void flash_set_verbose(uint v); + +/* common/flash.c */ +void flash_protect(int flag, ulong from, ulong to, flash_info_t *info); +int flash_write(char *src, ulong addr, ulong cnt); +flash_info_t *addr2info(ulong addr); +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt); + +/* drivers/mtd/cfi_mtd.c */ +#ifdef CONFIG_FLASH_CFI_MTD +extern int cfi_mtd_init(void); +#endif + +/* board/?/flash.c */ +#if defined(CONFIG_SYS_FLASH_PROTECTION) +extern int flash_real_protect(flash_info_t *info, long sector, int prot); +extern void flash_read_user_serial(flash_info_t * info, void * buffer, int offset, int len); +extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len); +#endif /* CONFIG_SYS_FLASH_PROTECTION */ + +#ifdef CONFIG_FLASH_CFI_LEGACY +extern ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info); +extern int jedec_flash_match(flash_info_t *info, ulong base); +#define CFI_CMDSET_AMD_LEGACY 0xFFF0 +#endif + +/** + * flash_perror() - Print a flash error + * + * @err: Error number of message to print (ERR_... as below) + */ +void flash_perror(int err); + +/*----------------------------------------------------------------------- + * return codes from flash_write(): + */ +#define ERR_OK 0 +#define ERR_TIMEOUT 1 +#define ERR_NOT_ERASED 2 +#define ERR_PROTECTED 4 +#define ERR_INVAL 8 +#define ERR_ALIGN 16 +#define ERR_UNKNOWN_FLASH_VENDOR 32 +#define ERR_UNKNOWN_FLASH_TYPE 64 +#define ERR_PROG_ERROR 128 +#define ERR_ABORTED 256 + +/*----------------------------------------------------------------------- + * Protection Flags for flash_protect(): + */ +#define FLAG_PROTECT_SET 0x01 +#define FLAG_PROTECT_CLEAR 0x02 +#define FLAG_PROTECT_INVALID 0x03 +/*----------------------------------------------------------------------- + * Set Environment according to label: + */ +#define FLAG_SETENV 0x80 + +/*----------------------------------------------------------------------- + * Device IDs + */ + +/* Manufacturers inside bank 0 have ids like 0x00xx00xx */ +#define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */ +#define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */ +#define ATM_MANUFACT 0x001F001F /* ATMEL */ +#define STM_MANUFACT 0x00200020 /* STM (Thomson) manuf. ID in D23.. -"- */ +#define SST_MANUFACT 0x00BF00BF /* SST manuf. ID in D23..D16, D7..D0 */ +#define MT_MANUFACT 0x00890089 /* MT manuf. ID in D23..D16, D7..D0 */ +#define INTEL_MANUFACT 0x00890089 /* INTEL manuf. ID in D23..D16, D7..D0 */ +#define INTEL_ALT_MANU 0x00B000B0 /* alternate INTEL namufacturer ID */ +#define MX_MANUFACT 0x00C200C2 /* MXIC manuf. ID in D23..D16, D7..D0 */ +#define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */ +#define MT2_MANUFACT 0x002C002C /* alternate MICRON manufacturer ID*/ +#define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */ +#define AMIC_MANUFACT 0x00370037 /* AMIC manuf. ID in D23..D16, D7..D0 */ +#define WINB_MANUFACT 0x00DA00DA /* Winbond manuf. ID in D23..D16, D7..D0 */ +#define EON_ALT_MANU 0x001C001C /* EON manuf. ID in D23..D16, D7..D0 */ + +/* Manufacturers inside bank 1 have ids like 0x01xx01xx */ +#define EON_MANUFACT 0x011C011C /* EON manuf. ID in D23..D16, D7..D0 */ + +/* Manufacturers inside bank 2 have ids like 0x02xx02xx */ + + /* Micron Technologies (INTEL compat.) */ +#define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */ +#define MT_ID_28F400_B 0x44714471 /* 28F400B3 ID ( 4 M, bottom boot sect) */ + +#define AMD_ID_LV040B 0x4F /* 29LV040B ID */ + /* 4 Mbit, 512K x 8, */ + /* 8 64K x 8 uniform sectors */ +#define AMD_ID_F033C 0xA3 /* 29LV033C ID */ + /* 32 Mbit, 4Mbits x 8, */ + /* 64 64K x 8 uniform sectors */ +#define AMD_ID_F065D 0x93 /* 29LV065D ID */ + /* 64 Mbit, 8Mbits x 8, */ + /* 126 64K x 8 uniform sectors */ +#define ATM_ID_LV040 0x13 /* 29LV040B ID */ + /* 4 Mbit, 512K x 8, */ + /* 8 64K x 8 uniform sectors */ +#define AMD_ID_F040B 0xA4 /* 29F040B ID */ + /* 4 Mbit, 512K x 8, */ + /* 8 64K x 8 uniform sectors */ +#define STM_ID_M29W040B 0xE3 /* M29W040B ID */ + /* 4 Mbit, 512K x 8, */ + /* 8 64K x 8 uniform sectors */ +#define AMD_ID_F080B 0xD5 /* 29F080 ID ( 1 M) */ + /* 8 Mbit, 512K x 16, */ + /* 8 64K x 16 uniform sectors */ +#define AMD_ID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */ +#define AMD_ID_F032B 0x41 /* 29F032 ID ( 4 M x 8) */ +#define AMD_ID_LV116DT 0xC7 /* 29LV116DT ( 2 M x 8, top boot sect) */ +#define AMD_ID_LV116DB 0x4C /* 29LV116DB ( 2 M x 8, bottom boot sect) */ +#define AMD_ID_LV016B 0xc8 /* 29LV016 ID ( 2 M x 8) */ + +#define AMD_ID_PL160CB 0x22452245 /* 29PL160CB ID (16 M, bottom boot sect */ + +#define AMD_ID_LV400T 0x22B922B9 /* 29LV400T ID ( 4 M, top boot sector) */ +#define AMD_ID_LV400B 0x22BA22BA /* 29LV400B ID ( 4 M, bottom boot sect) */ + +#define AMD_ID_LV033C 0xA3 /* 29LV033C ID ( 4 M x 8) */ +#define AMD_ID_LV065D 0x93 /* 29LV065D ID ( 8 M x 8) */ + +#define AMD_ID_LV800T 0x22DA22DA /* 29LV800T ID ( 8 M, top boot sector) */ +#define AMD_ID_LV800B 0x225B225B /* 29LV800B ID ( 8 M, bottom boot sect) */ + +#define AMD_ID_LV160T 0x22C422C4 /* 29LV160T ID (16 M, top boot sector) */ +#define AMD_ID_LV160B 0x22492249 /* 29LV160B ID (16 M, bottom boot sect) */ + +#define AMD_ID_DL163T 0x22282228 /* 29DL163T ID (16 M, top boot sector) */ +#define AMD_ID_DL163B 0x222B222B /* 29DL163B ID (16 M, bottom boot sect) */ + +#define AMD_ID_LV320T 0x22F622F6 /* 29LV320T ID (32 M, top boot sector) */ +#define MX_ID_LV320T 0x22A722A7 /* 29LV320T by Macronix, AMD compatible */ +#define AMD_ID_LV320B 0x22F922F9 /* 29LV320B ID (32 M, bottom boot sect) */ +#define MX_ID_LV320B 0x22A822A8 /* 29LV320B by Macronix, AMD compatible */ + +#define AMD_ID_DL322T 0x22552255 /* 29DL322T ID (32 M, top boot sector) */ +#define AMD_ID_DL322B 0x22562256 /* 29DL322B ID (32 M, bottom boot sect) */ +#define AMD_ID_DL323T 0x22502250 /* 29DL323T ID (32 M, top boot sector) */ +#define AMD_ID_DL323B 0x22532253 /* 29DL323B ID (32 M, bottom boot sect) */ +#define AMD_ID_DL324T 0x225C225C /* 29DL324T ID (32 M, top boot sector) */ +#define AMD_ID_DL324B 0x225F225F /* 29DL324B ID (32 M, bottom boot sect) */ + +#define AMD_ID_DL640 0x227E227E /* 29DL640D ID (64 M, dual boot sectors)*/ +#define AMD_ID_MIRROR 0x227E227E /* 1st ID word for MirrorBit family */ +#define AMD_ID_DL640G_2 0x22022202 /* 2nd ID word for AM29DL640G at 0x38 */ +#define AMD_ID_DL640G_3 0x22012201 /* 3rd ID word for AM29DL640G at 0x3c */ +#define AMD_ID_LV640U_2 0x220C220C /* 2nd ID word for AM29LV640M at 0x38 */ +#define AMD_ID_LV640U_3 0x22012201 /* 3rd ID word for AM29LV640M at 0x3c */ +#define AMD_ID_LV640MT_2 0x22102210 /* 2nd ID word for AM29LV640MT at 0x38 */ +#define AMD_ID_LV640MT_3 0x22012201 /* 3rd ID word for AM29LV640MT at 0x3c */ +#define AMD_ID_LV640MB_2 0x22102210 /* 2nd ID word for AM29LV640MB at 0x38 */ +#define AMD_ID_LV640MB_3 0x22002200 /* 3rd ID word for AM29LV640MB at 0x3c */ +#define AMD_ID_LV128U_2 0x22122212 /* 2nd ID word for AM29LV128M at 0x38 */ +#define AMD_ID_LV128U_3 0x22002200 /* 3rd ID word for AM29LV128M at 0x3c */ +#define AMD_ID_LV256U_2 0x22122212 /* 2nd ID word for AM29LV256M at 0x38 */ +#define AMD_ID_LV256U_3 0x22012201 /* 3rd ID word for AM29LV256M at 0x3c */ +#define AMD_ID_GL064M_2 0x22132213 /* 2nd ID word for S29GL064M-R6 */ +#define AMD_ID_GL064M_3 0x22012201 /* 3rd ID word for S29GL064M-R6 */ +#define AMD_ID_GL064MT_2 0x22102210 /* 2nd ID word for S29GL064M-R3 (top boot sector) */ +#define AMD_ID_GL064MT_3 0x22012201 /* 3rd ID word for S29GL064M-R3 (top boot sector) */ +#define AMD_ID_GL128N_2 0x22212221 /* 2nd ID word for S29GL128N */ +#define AMD_ID_GL128N_3 0x22012201 /* 3rd ID word for S29GL128N */ + + +#define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */ +#define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */ + +#define AMD_ID_LV640U 0x22D722D7 /* 29LV640U ID (64 M, uniform sectors) */ +#define AMD_ID_LV650U 0x22D722D7 /* 29LV650U ID (64 M, uniform sectors) */ + +#define ATM_ID_BV1614 0x000000C0 /* 49BV1614 ID */ +#define ATM_ID_BV1614A 0x000000C8 /* 49BV1614A ID */ +#define ATM_ID_BV6416 0x000000D6 /* 49BV6416 ID */ + +#define FUJI_ID_29F800BA 0x22582258 /* MBM29F800BA ID (8M) */ +#define FUJI_ID_29F800TA 0x22D622D6 /* MBM29F800TA ID (8M) */ +#define FUJI_ID_29LV650UE 0x22d722d7 /* MBM29LV650UE/651UE ID (8M = 128 x 32kWord) */ + +#define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */ +#define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */ +#define SST_ID_xF800A 0x27812781 /* 39xF800A ID ( 8M = 512K x 16 ) */ +#define SST_ID_xF160A 0x27822782 /* 39xF800A ID (16M = 1M x 16 ) */ +#define SST_ID_xF1601 0x234B234B /* 39xF1601 ID (16M = 1M x 16 ) */ +#define SST_ID_xF1602 0x234A234A /* 39xF1602 ID (16M = 1M x 16 ) */ +#define SST_ID_xF3201 0x235B235B /* 39xF3201 ID (32M = 2M x 16 ) */ +#define SST_ID_xF3202 0x235A235A /* 39xF3202 ID (32M = 2M x 16 ) */ +#define SST_ID_xF6401 0x236B236B /* 39xF6401 ID (64M = 4M x 16 ) */ +#define SST_ID_xF6402 0x236A236A /* 39xF6402 ID (64M = 4M x 16 ) */ +#define SST_ID_xF020 0xBFD6BFD6 /* 39xF020 ID (256KB = 2Mbit x 8) */ +#define SST_ID_xF040 0xBFD7BFD7 /* 39xF040 ID (512KB = 4Mbit x 8) */ + +#define STM_ID_F040B 0xE2 /* M29F040B ID ( 4M = 512K x 8 ) */ + /* 8 64K x 8 uniform sectors */ + +#define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */ +#define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */ +#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */ +#define STM_ID_29W320ET 0x22562256 /* M29W320ET ID (32 M, top boot sector) */ +#define STM_ID_29W320EB 0x22572257 /* M29W320EB ID (32 M, bottom boot sect)*/ +#define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */ +#define FLASH_PSD4256GV 0x00E9 /* PSD4256 Flash and CPLD combination */ + +#define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */ +#define INTEL_ID_28F800B3T 0x88928892 /* 8M = 512K x 16 top boot sector */ +#define INTEL_ID_28F800B3B 0x88938893 /* 8M = 512K x 16 bottom boot sector */ +#define INTEL_ID_28F160B3T 0x88908890 /* 16M = 1M x 16 top boot sector */ +#define INTEL_ID_28F160B3B 0x88918891 /* 16M = 1M x 16 bottom boot sector */ +#define INTEL_ID_28F320B3T 0x88968896 /* 32M = 2M x 16 top boot sector */ +#define INTEL_ID_28F320B3B 0x88978897 /* 32M = 2M x 16 bottom boot sector */ +#define INTEL_ID_28F640B3T 0x88988898 /* 64M = 4M x 16 top boot sector */ +#define INTEL_ID_28F640B3B 0x88998899 /* 64M = 4M x 16 bottom boot sector */ +#define INTEL_ID_28F160F3B 0x88F488F4 /* 16M = 1M x 16 bottom boot sector */ + +#define INTEL_ID_28F800C3T 0x88C088C0 /* 8M = 512K x 16 top boot sector */ +#define INTEL_ID_28F800C3B 0x88C188C1 /* 8M = 512K x 16 bottom boot sector */ +#define INTEL_ID_28F160C3T 0x88C288C2 /* 16M = 1M x 16 top boot sector */ +#define INTEL_ID_28F160C3B 0x88C388C3 /* 16M = 1M x 16 bottom boot sector */ +#define INTEL_ID_28F320C3T 0x88C488C4 /* 32M = 2M x 16 top boot sector */ +#define INTEL_ID_28F320C3B 0x88C588C5 /* 32M = 2M x 16 bottom boot sector */ +#define INTEL_ID_28F640C3T 0x88CC88CC /* 64M = 4M x 16 top boot sector */ +#define INTEL_ID_28F640C3B 0x88CD88CD /* 64M = 4M x 16 bottom boot sector */ + +#define INTEL_ID_28F128J3 0x89188918 /* 16M = 8M x 16 x 128 */ +#define INTEL_ID_28F320J5 0x00140014 /* 32M = 128K x 32 */ +#define INTEL_ID_28F640J5 0x00150015 /* 64M = 128K x 64 */ +#define INTEL_ID_28F320J3A 0x00160016 /* 32M = 128K x 32 */ +#define INTEL_ID_28F640J3A 0x00170017 /* 64M = 128K x 64 */ +#define INTEL_ID_28F128J3A 0x00180018 /* 128M = 128K x 128 */ +#define INTEL_ID_28F256J3A 0x001D001D /* 256M = 128K x 256 */ +#define INTEL_ID_28F256L18T 0x880D880D /* 256M = 128K x 255 + 32k x 4 */ +#define INTEL_ID_28F64K3 0x88018801 /* 64M = 32K x 255 + 32k x 4 */ +#define INTEL_ID_28F128K3 0x88028802 /* 128M = 64K x 255 + 32k x 4 */ +#define INTEL_ID_28F256K3 0x88038803 /* 256M = 128K x 255 + 32k x 4 */ +#define INTEL_ID_28F64P30T 0x88178817 /* 64M = 32K x 255 + 32k x 4 */ +#define INTEL_ID_28F64P30B 0x881A881A /* 64M = 32K x 255 + 32k x 4 */ +#define INTEL_ID_28F128P30T 0x88188818 /* 128M = 64K x 255 + 32k x 4 */ +#define INTEL_ID_28F128P30B 0x881B881B /* 128M = 64K x 255 + 32k x 4 */ +#define INTEL_ID_28F256P30T 0x88198819 /* 256M = 128K x 255 + 32k x 4 */ +#define INTEL_ID_28F256P30B 0x881C881C /* 256M = 128K x 255 + 32k x 4 */ + +#define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */ +#define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */ + +/* Note that the Sharp 28F016SC is compatible with the Intel E28F016SC */ +#define SHARP_ID_28F016SCL 0xAAAAAAAA /* LH28F016SCT-L95 2Mx8, 32 64k blocks */ +#define SHARP_ID_28F016SCZ 0xA0A0A0A0 /* LH28F016SCT-Z4 2Mx8, 32 64k blocks */ +#define SHARP_ID_28F008SC 0xA6A6A6A6 /* LH28F008SCT-L12 1Mx8, 16 64k blocks */ + /* LH28F008SCR-L85 1Mx8, 16 64k blocks */ + +#define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */ +#define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */ +#define NUMONYX_256MBIT 0x8922 /* Numonyx P33/30 256MBit 65nm */ + +/*----------------------------------------------------------------------- + * Internal FLASH identification codes + * + * Be careful when adding new type! Odd numbers are "bottom boot sector" types! + */ + +#define FLASH_AM040 0x0001 /* AMD Am29F040B, Am29LV040B */ + /* Bright Micro BM29F040 */ + /* Fujitsu MBM29F040A */ + /* STM M29W040B */ + /* SGS Thomson M29F040B */ + /* 8 64K x 8 uniform sectors */ +#define FLASH_AM400T 0x0002 /* AMD AM29LV400 */ +#define FLASH_AM400B 0x0003 +#define FLASH_AM800T 0x0004 /* AMD AM29LV800 */ +#define FLASH_AM800B 0x0005 +#define FLASH_AM116DT 0x0026 /* AMD AM29LV116DT (2Mx8bit) */ +#define FLASH_AM116DB 0x0027 /* AMD AM29LV116DB (2Mx8bit) */ +#define FLASH_AM160T 0x0006 /* AMD AM29LV160 */ +#define FLASH_AM160LV 0x0046 /* AMD29LV160DB (2M = 2Mx8bit ) */ +#define FLASH_AM160B 0x0007 +#define FLASH_AM320T 0x0008 /* AMD AM29LV320 */ +#define FLASH_AM320B 0x0009 + +#define FLASH_AM080 0x000A /* AMD Am29F080B */ + /* 16 64K x 8 uniform sectors */ + +#define FLASH_AMDL322T 0x0010 /* AMD AM29DL322 */ +#define FLASH_AMDL322B 0x0011 +#define FLASH_AMDL323T 0x0012 /* AMD AM29DL323 */ +#define FLASH_AMDL323B 0x0013 +#define FLASH_AMDL324T 0x0014 /* AMD AM29DL324 */ +#define FLASH_AMDL324B 0x0015 + +#define FLASH_AMDLV033C 0x0018 +#define FLASH_AMDLV065D 0x001A + +#define FLASH_AMDL640 0x0016 /* AMD AM29DL640D */ +#define FLASH_AMD016 0x0018 /* AMD AM29F016D */ +#define FLASH_AMDL640MB 0x0019 /* AMD AM29LV640MB (64M, bottom boot sect)*/ +#define FLASH_AMDL640MT 0x001A /* AMD AM29LV640MT (64M, top boot sect) */ + +#define FLASH_SST200A 0x0040 /* SST 39xF200A ID ( 2M = 128K x 16 ) */ +#define FLASH_SST400A 0x0042 /* SST 39xF400A ID ( 4M = 256K x 16 ) */ +#define FLASH_SST800A 0x0044 /* SST 39xF800A ID ( 8M = 512K x 16 ) */ +#define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */ +#define FLASH_SST320 0x0048 /* SST 39xF160A ID ( 16M = 1M x 16 ) */ +#define FLASH_SST640 0x004A /* SST 39xF160A ID ( 16M = 1M x 16 ) */ +#define FLASH_SST020 0x0024 /* SST 39xF020 ID (256KB = 2Mbit x 8 ) */ +#define FLASH_SST040 0x000E /* SST 39xF040 ID (512KB = 4Mbit x 8 ) */ + +#define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */ +#define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */ +#define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect)*/ +#define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom)*/ +#define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */ +#define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/ + +#define FLASH_MCHP100T 0x0060 /* MCHP internal (1M = 64K x 16) */ +#define FLASH_MCHP100B 0x0061 /* MCHP internal (1M = 64K x 16) */ + +#define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ +#define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ + +#define FLASH_INTEL800T 0x0074 /* INTEL 28F800B3T ( 8M = 512K x 16 ) */ +#define FLASH_INTEL800B 0x0075 /* INTEL 28F800B3B ( 8M = 512K x 16 ) */ +#define FLASH_INTEL160T 0x0076 /* INTEL 28F160B3T ( 16M = 1 M x 16 ) */ +#define FLASH_INTEL160B 0x0077 /* INTEL 28F160B3B ( 16M = 1 M x 16 ) */ +#define FLASH_INTEL320T 0x0078 /* INTEL 28F320B3T ( 32M = 2 M x 16 ) */ +#define FLASH_INTEL320B 0x0079 /* INTEL 28F320B3B ( 32M = 2 M x 16 ) */ +#define FLASH_INTEL640T 0x007A /* INTEL 28F320B3T ( 64M = 4 M x 16 ) */ +#define FLASH_INTEL640B 0x007B /* INTEL 28F320B3B ( 64M = 4 M x 16 ) */ + +#define FLASH_28F008S5 0x0080 /* Intel 28F008S5 ( 1M = 64K x 16 ) */ +#define FLASH_28F016SV 0x0081 /* Intel 28F016SV ( 16M = 512k x 32 ) */ +#define FLASH_28F800_B 0x0083 /* Intel E28F800B ( 1M = ? ) */ +#define FLASH_AM29F800B 0x0084 /* AMD Am29F800BB ( 1M = ? ) */ +#define FLASH_28F320J5 0x0085 /* Intel 28F320J5 ( 4M = 128K x 32 ) */ +#define FLASH_28F160S3 0x0086 /* Intel 28F160S3 ( 16M = 512K x 32 ) */ +#define FLASH_28F320S3 0x0088 /* Intel 28F320S3 ( 32M = 512K x 64 ) */ +#define FLASH_AM640U 0x0090 /* AMD Am29LV640U ( 64M = 4M x 16 ) */ +#define FLASH_AM033C 0x0091 /* AMD AM29LV033 ( 32M = 4M x 8 ) */ +#define FLASH_LH28F016SCT 0x0092 /* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */ +#define FLASH_28F160F3B 0x0093 /* Intel 28F160F3B ( 16M = 1M x 16 ) */ +#define FLASH_AM065D 0x0093 + +#define FLASH_28F640J5 0x0099 /* INTEL 28F640J5 ( 64M = 128K x 64) */ + +#define FLASH_28F800C3T 0x009A /* Intel 28F800C3T ( 8M = 512K x 16 ) */ +#define FLASH_28F800C3B 0x009B /* Intel 28F800C3B ( 8M = 512K x 16 ) */ +#define FLASH_28F160C3T 0x009C /* Intel 28F160C3T ( 16M = 1M x 16 ) */ +#define FLASH_28F160C3B 0x009D /* Intel 28F160C3B ( 16M = 1M x 16 ) */ +#define FLASH_28F320C3T 0x009E /* Intel 28F320C3T ( 32M = 2M x 16 ) */ +#define FLASH_28F320C3B 0x009F /* Intel 28F320C3B ( 32M = 2M x 16 ) */ +#define FLASH_28F640C3T 0x00A0 /* Intel 28F640C3T ( 64M = 4M x 16 ) */ +#define FLASH_28F640C3B 0x00A1 /* Intel 28F640C3B ( 64M = 4M x 16 ) */ +#define FLASH_AMLV320U 0x00A2 /* AMD 29LV320M ( 32M = 2M x 16 ) */ + +#define FLASH_AM033 0x00A3 /* AMD AmL033C90V1 (32M = 4M x 8) */ +#define FLASH_AM065 0x0093 /* AMD AmL065DU12RI (64M = 8M x 8) */ +#define FLASH_AT040 0x00A5 /* Amtel AT49LV040 (4M = 512K x 8) */ + +#define FLASH_AMLV640U 0x00A4 /* AMD 29LV640M ( 64M = 4M x 16 ) */ +#define FLASH_AMLV128U 0x00A6 /* AMD 29LV128M ( 128M = 8M x 16 ) */ +#define FLASH_AMLV320B 0x00A7 /* AMD 29LV320MB ( 32M = 2M x 16 ) */ +#define FLASH_AMLV320T 0x00A8 /* AMD 29LV320MT ( 32M = 2M x 16 ) */ +#define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */ +#define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */ +#define FLASH_MXLV320T 0x00AC /* MX 29LV320MT ( 32M = 2M x 16 ) */ +#define FLASH_28F256L18T 0x00B0 /* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */ +#define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */ +#define FLASH_AMDL163B 0x00B3 +#define FLASH_28F64K3 0x00B4 /* Intel 28F64K3 ( 64M) */ +#define FLASH_28F128K3 0x00B6 /* Intel 28F128K3 ( 128M = 8M x 16 ) */ +#define FLASH_28F256K3 0x00B8 /* Intel 28F256K3 ( 256M = 16M x 16 ) */ + +#define FLASH_28F320J3A 0x00C0 /* INTEL 28F320J3A ( 32M = 128K x 32) */ +#define FLASH_28F640J3A 0x00C2 /* INTEL 28F640J3A ( 64M = 128K x 64) */ +#define FLASH_28F128J3A 0x00C4 /* INTEL 28F128J3A (128M = 128K x 128) */ +#define FLASH_28F256J3A 0x00C6 /* INTEL 28F256J3A (256M = 128K x 256) */ + +#define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */ +#define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */ +#define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */ +#define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */ + +#define FLASH_STM32 0x00F2 /* STM32 Embedded Flash */ + +#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */ + + +/* manufacturer offsets + */ +#define FLASH_MAN_AMD 0x00000000 /* AMD */ +#define FLASH_MAN_FUJ 0x00010000 /* Fujitsu */ +#define FLASH_MAN_BM 0x00020000 /* Bright Microelectronics */ +#define FLASH_MAN_MX 0x00030000 /* MXIC */ +#define FLASH_MAN_STM 0x00040000 +#define FLASH_MAN_TOSH 0x00050000 /* Toshiba */ +#define FLASH_MAN_EXCEL 0x00060000 /* Excel Semiconductor */ +#define FLASH_MAN_SST 0x00100000 +#define FLASH_MAN_INTEL 0x00300000 +#define FLASH_MAN_MT 0x00400000 +#define FLASH_MAN_SHARP 0x00500000 +#define FLASH_MAN_ATM 0x00600000 +#define FLASH_MAN_CFI 0x01000000 +#define FLASH_MAN_MCHP 0x02000000 /* Microchip Technology */ + +#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */ +#define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */ + +#define FLASH_AMD_COMP 0x000FFFFF /* Up to this ID, FLASH is compatible */ + /* with AMD, Fujitsu and SST */ + /* (JEDEC standard commands ?) */ + +#define FLASH_BTYPE 0x0001 /* mask for bottom boot sector type */ + +/*----------------------------------------------------------------------- + * Timeout constants: + * + * We can't find any specifications for maximum chip erase times, + * so these values are guestimates. + */ +#define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */ +#define FLASH_WRITE_TIMEOUT 500 /* timeout for writes in ms */ + +#endif /* _FLASH_H_ */ diff --git a/roms/u-boot/include/fm_eth.h b/roms/u-boot/include/fm_eth.h new file mode 100644 index 000000000..44da014c6 --- /dev/null +++ b/roms/u-boot/include/fm_eth.h @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2009-2012 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + */ + +#ifndef __FM_ETH_H__ +#define __FM_ETH_H__ + +#include +#include +#include + +enum fm_port { + FM1_DTSEC1, + FM1_DTSEC2, + FM1_DTSEC3, + FM1_DTSEC4, + FM1_DTSEC5, + FM1_DTSEC6, + FM1_DTSEC9, + FM1_DTSEC10, + FM1_10GEC1, + FM1_10GEC2, + FM1_10GEC3, + FM1_10GEC4, + FM2_DTSEC1, + FM2_DTSEC2, + FM2_DTSEC3, + FM2_DTSEC4, + FM2_DTSEC5, + FM2_DTSEC6, + FM2_DTSEC9, + FM2_DTSEC10, + FM2_10GEC1, + FM2_10GEC2, + NUM_FM_PORTS, +}; + +enum fm_eth_type { + FM_ETH_1G_E, + FM_ETH_10G_E, +}; + +/* Historically, on FMan v3 platforms, the first MDIO bus has been used for + * Clause 22 PHYs and the second MDIO bus for 10G Clause 45 PHYs (thus the + * TGEC name). + * + * On LS1046A-FRWY, the QSGMII PHY is connected to the second MDIO bus, + * and no TGEC ports are present on-board. + */ +#ifdef CONFIG_SYS_FMAN_V3 +#ifdef CONFIG_TARGET_LS1046AFRWY +#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) +#else +#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000) +#endif +#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) +#if (CONFIG_SYS_NUM_FMAN == 2) +#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000) +#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000) +#endif +#else +#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120) +#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000) +#endif + +#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0" +#define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO" + +/* Fman ethernet info struct */ +#define FM_ETH_INFO_INITIALIZER(idx, pregs) \ + .fm = idx, \ + .phy_regs = (void *)pregs, \ + .enet_if = PHY_INTERFACE_MODE_NONE, \ + +#ifdef CONFIG_SYS_FMAN_V3 +#define FM_DTSEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_1G_E, \ + .port = FM##idx##_DTSEC##n, \ + .rx_port_id = RX_PORT_1G_BASE + n - 1, \ + .tx_port_id = TX_PORT_1G_BASE + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, memac[n-1]),\ +} + +#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION +#define FM_TGEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_10G_E, \ + .port = FM##idx##_10GEC##n, \ + .rx_port_id = RX_PORT_10G_BASE2 + n - 1, \ + .tx_port_id = TX_PORT_10G_BASE2 + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, memac[n-1]),\ +} +#else +#if (CONFIG_SYS_NUM_FMAN == 2) +#define FM_TGEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_10G_E, \ + .port = FM##idx##_10GEC##n, \ + .rx_port_id = RX_PORT_10G_BASE + n - 1, \ + .tx_port_id = TX_PORT_10G_BASE + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, memac[n-1+8]),\ +} +#else +#define FM_TGEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_10G_E, \ + .port = FM##idx##_10GEC##n, \ + .rx_port_id = RX_PORT_10G_BASE + n - 1, \ + .tx_port_id = TX_PORT_10G_BASE + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, memac[n-1+8]),\ +} +#endif +#endif + +#if (CONFIG_SYS_NUM_FM1_10GEC >= 3) +#define FM_TGEC_INFO_INITIALIZER2(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_10G_E, \ + .port = FM##idx##_10GEC##n, \ + .rx_port_id = RX_PORT_10G_BASE2 + n - 3, \ + .tx_port_id = TX_PORT_10G_BASE2 + n - 3, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, memac[n-1-2]),\ +} +#endif + +#else +#define FM_DTSEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_1G_E, \ + .port = FM##idx##_DTSEC##n, \ + .rx_port_id = RX_PORT_1G_BASE + n - 1, \ + .tx_port_id = TX_PORT_1G_BASE + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, mac_1g[n-1]),\ +} + +#define FM_TGEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_10G_E, \ + .port = FM##idx##_10GEC##n, \ + .rx_port_id = RX_PORT_10G_BASE + n - 1, \ + .tx_port_id = TX_PORT_10G_BASE + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, mac_10g[n-1]),\ +} +#endif +struct fm_eth_info { + u8 enabled; + u8 fm; + u8 num; + u8 phy_addr; + int index; + u16 rx_port_id; + u16 tx_port_id; + enum fm_port port; + enum fm_eth_type type; + void *phy_regs; + phy_interface_t enet_if; + u32 compat_offset; + struct mii_dev *bus; +}; + +struct tgec_mdio_info { + struct tgec_mdio_controller *regs; + char *name; +}; + +struct memac_mdio_info { + struct memac_mdio_controller *regs; + char *name; +}; + +int fm_tgec_mdio_init(struct bd_info *bis, struct tgec_mdio_info *info); +int fm_memac_mdio_init(struct bd_info *bis, struct memac_mdio_info *info); + +int fm_standard_init(struct bd_info *bis); +void fman_enet_init(void); +void fdt_fixup_fman_ethernet(void *fdt); +phy_interface_t fm_info_get_enet_if(enum fm_port port); +void fm_info_set_phy_address(enum fm_port port, int address); +int fm_info_get_phy_address(enum fm_port port); +void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus); +void fm_disable_port(enum fm_port port); +void fm_enable_port(enum fm_port port); +void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port, + unsigned int port_num, int phy_base_addr); +int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr, + unsigned int port_num, unsigned regnum); + +#endif diff --git a/roms/u-boot/include/fpga.h b/roms/u-boot/include/fpga.h new file mode 100644 index 000000000..ec5144334 --- /dev/null +++ b/roms/u-boot/include/fpga.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + */ + +#include /* for ulong typedef */ + +#ifndef _FPGA_H_ +#define _FPGA_H_ + +#ifndef CONFIG_MAX_FPGA_DEVICES +#define CONFIG_MAX_FPGA_DEVICES 5 +#endif + +/* fpga_xxxx function return value definitions */ +#define FPGA_SUCCESS 0 +#define FPGA_FAIL 1 + +/* device numbers must be non-negative */ +#define FPGA_INVALID_DEVICE -1 + +#define FPGA_ENC_USR_KEY 1 +#define FPGA_NO_ENC_OR_NO_AUTH 2 + +/* root data type defintions */ +typedef enum { /* typedef fpga_type */ + fpga_min_type, /* range check value */ + fpga_xilinx, /* Xilinx Family) */ + fpga_altera, /* unimplemented */ + fpga_lattice, /* Lattice family */ + fpga_undefined /* invalid range check value */ +} fpga_type; /* end, typedef fpga_type */ + +typedef struct { /* typedef fpga_desc */ + fpga_type devtype; /* switch value to select sub-functions */ + void *devdesc; /* real device descriptor */ +} fpga_desc; /* end, typedef fpga_desc */ + +typedef struct { /* typedef fpga_desc */ + unsigned int blocksize; + char *interface; + char *dev_part; + const char *filename; + int fstype; +} fpga_fs_info; + +struct fpga_secure_info { + u8 *userkey_addr; + u8 authflag; + u8 encflag; +}; + +typedef enum { + BIT_FULL = 0, + BIT_PARTIAL, + BIT_NONE = 0xFF, +} bitstream_type; + +/* root function definitions */ +void fpga_init(void); +int fpga_add(fpga_type devtype, void *desc); +int fpga_count(void); +const fpga_desc *const fpga_get_desc(int devnum); +int fpga_is_partial_data(int devnum, size_t img_len); +int fpga_load(int devnum, const void *buf, size_t bsize, + bitstream_type bstype); +int fpga_fsload(int devnum, const void *buf, size_t size, + fpga_fs_info *fpga_fsinfo); +int fpga_loads(int devnum, const void *buf, size_t size, + struct fpga_secure_info *fpga_sec_info); +int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype); +int fpga_dump(int devnum, const void *buf, size_t bsize); +int fpga_info(int devnum); +const fpga_desc *const fpga_validate(int devnum, const void *buf, + size_t bsize, char *fn); + +#endif /* _FPGA_H_ */ diff --git a/roms/u-boot/include/fs.h b/roms/u-boot/include/fs.h new file mode 100644 index 000000000..0794b50d1 --- /dev/null +++ b/roms/u-boot/include/fs.h @@ -0,0 +1,274 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + */ +#ifndef _FS_H +#define _FS_H + +#include + +struct cmd_tbl; + +#define FS_TYPE_ANY 0 +#define FS_TYPE_FAT 1 +#define FS_TYPE_EXT 2 +#define FS_TYPE_SANDBOX 3 +#define FS_TYPE_UBIFS 4 +#define FS_TYPE_BTRFS 5 +#define FS_TYPE_SQUASHFS 6 + +struct blk_desc; + +/** + * do_fat_fsload - Run the fatload command + * + * @cmdtp: Command information for fatload + * @flag: Command flags (CMD_FLAG_...) + * @argc: Number of arguments + * @argv: List of arguments + * @return result (see enum command_ret_t) + */ +int do_fat_fsload(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); + +/** + * do_ext2load - Run the ext2load command + * + * @cmdtp: Command information for ext2load + * @flag: Command flags (CMD_FLAG_...) + * @argc: Number of arguments + * @argv: List of arguments + * @return result (see enum command_ret_t) + */ +int do_ext2load(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); + +/* + * Tell the fs layer which block device an partition to use for future + * commands. This also internally identifies the filesystem that is present + * within the partition. The identification process may be limited to a + * specific filesystem type by passing FS_* in the fstype parameter. + * + * Returns 0 on success. + * Returns non-zero if there is an error accessing the disk or partition, or + * no known filesystem type could be recognized on it. + */ +int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype); + +/* + * fs_set_blk_dev_with_part - Set current block device + partition + * + * Similar to fs_set_blk_dev(), but useful for cases where you already + * know the blk_desc and part number. + * + * Returns 0 on success. + * Returns non-zero if invalid partition or error accessing the disk. + */ +int fs_set_blk_dev_with_part(struct blk_desc *desc, int part); + +/** + * fs_close() - Unset current block device and partition + * + * fs_close() closes the connection to a file system opened with either + * fs_set_blk_dev() or fs_set_dev_with_part(). + * + * Many file functions implicitly call fs_close(), e.g. fs_closedir(), + * fs_exist(), fs_ln(), fs_ls(), fs_mkdir(), fs_read(), fs_size(), fs_write(), + * fs_unlink(). + */ +void fs_close(void); + +/** + * fs_get_type() - Get type of current filesystem + * + * Return: filesystem type + * + * Returns filesystem type representing the current filesystem, or + * FS_TYPE_ANY for any unrecognised filesystem. + */ +int fs_get_type(void); + +/** + * fs_get_type_name() - Get type of current filesystem + * + * Return: Pointer to filesystem name + * + * Returns a string describing the current filesystem, or the sentinel + * "unsupported" for any unrecognised filesystem. + */ +const char *fs_get_type_name(void); + +/* + * Print the list of files on the partition previously set by fs_set_blk_dev(), + * in directory "dirname". + * + * Returns 0 on success. Returns non-zero on error. + */ +int fs_ls(const char *dirname); + +/* + * Determine whether a file exists + * + * Returns 1 if the file exists, 0 if it doesn't exist. + */ +int fs_exists(const char *filename); + +/* + * fs_size - Determine a file's size + * + * @filename: Name of the file + * @size: Size of file + * @return 0 if ok with valid *size, negative on error + */ +int fs_size(const char *filename, loff_t *size); + +/** + * fs_read() - read file from the partition previously set by fs_set_blk_dev() + * + * Note that not all filesystem drivers support either or both of offset != 0 + * and len != 0. + * + * @filename: full path of the file to read from + * @addr: address of the buffer to write to + * @offset: offset in the file from where to start reading + * @len: the number of bytes to read. Use 0 to read entire file. + * @actread: returns the actual number of bytes read + * Return: 0 if OK with valid *actread, -1 on error conditions + */ +int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len, + loff_t *actread); + +/** + * fs_write() - write file to the partition previously set by fs_set_blk_dev() + * + * Note that not all filesystem drivers support offset != 0. + * + * @filename: full path of the file to write to + * @addr: address of the buffer to read from + * @offset: offset in the file from where to start writing + * @len: the number of bytes to write + * @actwrite: returns the actual number of bytes written + * Return: 0 if OK with valid *actwrite, -1 on error conditions + */ +int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len, + loff_t *actwrite); + +/* + * Directory entry types, matches the subset of DT_x in posix readdir() + * which apply to u-boot. + */ +#define FS_DT_DIR 4 /* directory */ +#define FS_DT_REG 8 /* regular file */ +#define FS_DT_LNK 10 /* symbolic link */ + +/* + * A directory entry, returned by fs_readdir(). Returns information + * about the file/directory at the current directory entry position. + */ +struct fs_dirent { + unsigned type; /* one of FS_DT_x (not a mask) */ + loff_t size; /* size in bytes */ + char name[256]; +}; + +/* Note: fs_dir_stream should be treated as opaque to the user of fs layer */ +struct fs_dir_stream { + /* private to fs. layer: */ + struct blk_desc *desc; + int part; +}; + +/* + * fs_opendir - Open a directory + * + * @filename: the path to directory to open + * @return a pointer to the directory stream or NULL on error and errno + * set appropriately + */ +struct fs_dir_stream *fs_opendir(const char *filename); + +/* + * fs_readdir - Read the next directory entry in the directory stream. + * + * Works in an analogous way to posix readdir(). The previously returned + * directory entry is no longer valid after calling fs_readdir() again. + * After fs_closedir() is called, the returned directory entry is no + * longer valid. + * + * @dirs: the directory stream + * @return the next directory entry (only valid until next fs_readdir() or + * fs_closedir() call, do not attempt to free()) or NULL if the end of + * the directory is reached. + */ +struct fs_dirent *fs_readdir(struct fs_dir_stream *dirs); + +/* + * fs_closedir - close a directory stream + * + * @dirs: the directory stream + */ +void fs_closedir(struct fs_dir_stream *dirs); + +/* + * fs_unlink - delete a file or directory + * + * If a given name is a directory, it will be deleted only if it's empty + * + * @filename: Name of file or directory to delete + * @return 0 on success, -1 on error conditions + */ +int fs_unlink(const char *filename); + +/* + * fs_mkdir - Create a directory + * + * @filename: Name of directory to create + * @return 0 on success, -1 on error conditions + */ +int fs_mkdir(const char *filename); + +/* + * Common implementation for various filesystem commands, optionally limited + * to a specific filesystem type via the fstype parameter. + */ +int do_size(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], + int fstype); +int do_load(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], + int fstype); +int do_ls(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], + int fstype); +int file_exists(const char *dev_type, const char *dev_part, const char *file, + int fstype); +int do_save(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], + int fstype); +int do_rm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], + int fstype); +int do_mkdir(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], + int fstype); +int do_ln(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], + int fstype); + +/* + * Determine the UUID of the specified filesystem and print it. Optionally it is + * possible to store the UUID directly in env. + */ +int do_fs_uuid(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], + int fstype); + +/* + * Determine the type of the specified filesystem and print it. Optionally it is + * possible to store the type directly in env. + */ +int do_fs_type(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); + +/** + * do_fs_types - List supported filesystems. + * + * @cmdtp: Command information for fstypes + * @flag: Command flags (CMD_FLAG_...) + * @argc: Number of arguments + * @argv: List of arguments + * @return result (see enum command_ret_t) + */ +int do_fs_types(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]); + +#endif /* _FS_H */ diff --git a/roms/u-boot/include/fs_internal.h b/roms/u-boot/include/fs_internal.h new file mode 100644 index 000000000..3d4d25da9 --- /dev/null +++ b/roms/u-boot/include/fs_internal.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * 2017 by Marek Behun + * + * Derived from code in ext4/dev.c, which was based on reiserfs/dev.c + */ + +#ifndef __U_BOOT_FS_INTERNAL_H__ +#define __U_BOOT_FS_INTERNAL_H__ + +#include + +int fs_devread(struct blk_desc *, struct disk_partition *, lbaint_t, int, int, + char *); + +#endif /* __U_BOOT_FS_INTERNAL_H__ */ diff --git a/roms/u-boot/include/fs_loader.h b/roms/u-boot/include/fs_loader.h new file mode 100644 index 000000000..8de7cb18d --- /dev/null +++ b/roms/u-boot/include/fs_loader.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2018 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef _FS_LOADER_H_ +#define _FS_LOADER_H_ + +struct udevice; + +/** + * struct phandle_part - A place for storing phandle of node and its partition + * + * This holds information about a phandle of the block device, and its + * partition where the firmware would be loaded from. + * + * @phandle: Phandle of storage device node + * @partition: Partition of block device + */ +struct phandle_part { + u32 phandle; + u32 partition; +}; + +/** + * struct phandle_part - A place for storing all supported storage devices + * + * This holds information about all supported storage devices for driver use. + * + * @phandlepart: Attribute data for block device. + * @mtdpart: MTD partition for ubi partition. + * @ubivol: UBI volume-name for ubifsmount. + */ +struct device_plat { + struct phandle_part phandlepart; + char *mtdpart; + char *ubivol; +}; + +/** + * request_firmware_into_buf - Load firmware into a previously allocated buffer. + * @dev: An instance of a driver. + * @name: Name of firmware file. + * @buf: Address of buffer to load firmware into. + * @size: Size of buffer. + * @offset: Offset of a file for start reading into buffer. + * + * The firmware is loaded directly into the buffer pointed to by @buf. + * + * Return: Size of total read, negative value when error. + */ +int request_firmware_into_buf(struct udevice *dev, + const char *name, + void *buf, size_t size, u32 offset); +#endif diff --git a/roms/u-boot/include/fsl-mc/fsl_dpaa_fd.h b/roms/u-boot/include/fsl-mc/fsl_dpaa_fd.h new file mode 100644 index 000000000..159756f71 --- /dev/null +++ b/roms/u-boot/include/fsl-mc/fsl_dpaa_fd.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Freescale Semiconductor + */ +#ifndef __FSL_DPAA_FD_H +#define __FSL_DPAA_FD_H + +/* Place-holder for FDs, we represent it via the simplest form that we need for + * now. Different overlays may be needed to support different options, etc. (It + * is impractical to define One True Struct, because the resulting encoding + * routines (lots of read-modify-writes) would be worst-case performance whether + * or not circumstances required them.) */ +struct dpaa_fd { + union { + u32 words[8]; + struct dpaa_fd_simple { + u32 addr_lo; + u32 addr_hi; + u32 len; + /* offset in the MS 16 bits, BPID in the LS 16 bits */ + u32 bpid_offset; + u32 frc; /* frame context */ + /* "err", "va", "cbmt", "asal", [...] */ + u32 ctrl; + /* flow context */ + u32 flc_lo; + u32 flc_hi; + } simple; + }; +}; + +enum dpaa_fd_format { + dpaa_fd_single = 0, + dpaa_fd_list, + dpaa_fd_sg +}; + +static inline u64 ldpaa_fd_get_addr(const struct dpaa_fd *fd) +{ + return (u64)((((uint64_t)fd->simple.addr_hi) << 32) + + fd->simple.addr_lo); +} + +static inline void ldpaa_fd_set_addr(struct dpaa_fd *fd, u64 addr) +{ + fd->simple.addr_hi = upper_32_bits(addr); + fd->simple.addr_lo = lower_32_bits(addr); +} + +static inline u32 ldpaa_fd_get_len(const struct dpaa_fd *fd) +{ + return fd->simple.len; +} + +static inline void ldpaa_fd_set_len(struct dpaa_fd *fd, u32 len) +{ + fd->simple.len = len; +} + +static inline uint16_t ldpaa_fd_get_offset(const struct dpaa_fd *fd) +{ + return (uint16_t)(fd->simple.bpid_offset >> 16) & 0x0FFF; +} + +static inline void ldpaa_fd_set_offset(struct dpaa_fd *fd, uint16_t offset) +{ + fd->simple.bpid_offset &= 0xF000FFFF; + fd->simple.bpid_offset |= (u32)offset << 16; +} + +static inline uint16_t ldpaa_fd_get_bpid(const struct dpaa_fd *fd) +{ + return (uint16_t)(fd->simple.bpid_offset & 0xFFFF); +} + +static inline void ldpaa_fd_set_bpid(struct dpaa_fd *fd, uint16_t bpid) +{ + fd->simple.bpid_offset &= 0xFFFF0000; + fd->simple.bpid_offset |= (u32)bpid; +} + +/* When frames are dequeued, the FDs show up inside "dequeue" result structures + * (if at all, not all dequeue results contain valid FDs). This structure type + * is intentionally defined without internal detail, and the only reason it + * isn't declared opaquely (without size) is to allow the user to provide + * suitably-sized (and aligned) memory for these entries. */ +struct ldpaa_dq { + uint32_t dont_manipulate_directly[16]; +}; + +/* Parsing frame dequeue results */ +#define LDPAA_DQ_STAT_FQEMPTY 0x80 +#define LDPAA_DQ_STAT_HELDACTIVE 0x40 +#define LDPAA_DQ_STAT_FORCEELIGIBLE 0x20 +#define LDPAA_DQ_STAT_VALIDFRAME 0x10 +#define LDPAA_DQ_STAT_ODPVALID 0x04 +#define LDPAA_DQ_STAT_VOLATILE 0x02 +#define LDPAA_DQ_STAT_EXPIRED 0x01 +uint32_t ldpaa_dq_flags(const struct ldpaa_dq *); +static inline int ldpaa_dq_is_pull(const struct ldpaa_dq *dq) +{ + return (int)(ldpaa_dq_flags(dq) & LDPAA_DQ_STAT_VOLATILE); +} +static inline int ldpaa_dq_is_pull_complete( + const struct ldpaa_dq *dq) +{ + return (int)(ldpaa_dq_flags(dq) & LDPAA_DQ_STAT_EXPIRED); +} +/* seqnum/odpid are valid only if VALIDFRAME and ODPVALID flags are TRUE */ +uint16_t ldpaa_dq_seqnum(const struct ldpaa_dq *); +uint16_t ldpaa_dq_odpid(const struct ldpaa_dq *); +uint32_t ldpaa_dq_fqid(const struct ldpaa_dq *); +uint32_t ldpaa_dq_byte_count(const struct ldpaa_dq *); +uint32_t ldpaa_dq_frame_count(const struct ldpaa_dq *); +uint32_t ldpaa_dq_fqd_ctx_hi(const struct ldpaa_dq *); +uint32_t ldpaa_dq_fqd_ctx_lo(const struct ldpaa_dq *); +/* get the Frame Descriptor */ +const struct dpaa_fd *ldpaa_dq_fd(const struct ldpaa_dq *); + +#endif /* __FSL_DPAA_FD_H */ diff --git a/roms/u-boot/include/fsl-mc/fsl_dpbp.h b/roms/u-boot/include/fsl-mc/fsl_dpbp.h new file mode 100644 index 000000000..2278ac952 --- /dev/null +++ b/roms/u-boot/include/fsl-mc/fsl_dpbp.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale Layerscape MC I/O wrapper + * + * Copyright 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ +/*! + * @file fsl_dpbp.h + * @brief Data Path Buffer Pool API + */ +#ifndef __FSL_DPBP_H +#define __FSL_DPBP_H + +/* DPBP Version */ +#define DPBP_VER_MAJOR 3 +#define DPBP_VER_MINOR 3 + +/* Command IDs */ +#define DPBP_CMDID_CLOSE 0x8001 +#define DPBP_CMDID_OPEN 0x8041 +#define DPBP_CMDID_CREATE 0x9041 +#define DPBP_CMDID_DESTROY 0x9841 +#define DPBP_CMDID_GET_API_VERSION 0xa041 + +#define DPBP_CMDID_ENABLE 0x0021 +#define DPBP_CMDID_DISABLE 0x0031 +#define DPBP_CMDID_GET_ATTR 0x0041 +#define DPBP_CMDID_RESET 0x0051 +#define DPBP_CMDID_IS_ENABLED 0x0061 + +/* cmd, param, offset, width, type, arg_name */ +#define DPBP_CMD_OPEN(cmd, dpbp_id) \ + MC_CMD_OP(cmd, 0, 0, 32, int, dpbp_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPBP_RSP_GET_ATTRIBUTES(cmd, attr) \ +do { \ + MC_RSP_OP(cmd, 0, 16, 16, uint16_t, attr->bpid); \ + MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\ +} while (0) + +/* Data Path Buffer Pool API + * Contains initialization APIs and runtime control APIs for DPBP + */ + +struct fsl_mc_io; + +/** + * dpbp_open() - Open a control session for the specified object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpbp_id: DPBP unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpbp_create function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_open(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + int dpbp_id, + uint16_t *token); + +/** + * dpbp_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_close(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** + * struct dpbp_cfg - Structure representing DPBP configuration + * @options: place holder + */ +struct dpbp_cfg { + uint32_t options; +}; + +/** + * dpbp_create() - Create the DPBP object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @token: Returned token; use in subsequent API calls + * + * Create the DPBP object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpbp_open function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_create(struct fsl_mc_io *mc_io, + uint16_t dprc_token, + uint32_t cmd_flags, + const struct dpbp_cfg *cfg, + uint32_t *obj_id); + +/** + * dpbp_destroy() - Destroy the DPBP object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * Return: '0' on Success; error code otherwise. + */ +int dpbp_destroy(struct fsl_mc_io *mc_io, + uint16_t dprc_token, + uint32_t cmd_flags, + uint32_t obj_id); + +/** + * dpbp_enable() - Enable the DPBP. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_enable(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** + * dpbp_disable() - Disable the DPBP. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_disable(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** + * dpbp_is_enabled() - Check if the DPBP is enabled. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * @en: Returns '1' if object is enabled; '0' otherwise + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_is_enabled(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + int *en); + +/** + * dpbp_reset() - Reset the DPBP, returns the object to initial state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_reset(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + + +/** + * struct dpbp_attr - Structure representing DPBP attributes + * @id: DPBP object ID + * @version: DPBP version + * @bpid: Hardware buffer pool ID; should be used as an argument in + * acquire/release operations on buffers + */ +struct dpbp_attr { + uint32_t id; + uint16_t bpid; +}; + +/** + * dpbp_get_attributes - Retrieve DPBP attributes. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_get_attributes(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpbp_attr *attr); + +/** + * dpbp_get_api_version - Retrieve DPBP Major and Minor version info. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: DPBP major version + * @minor_ver: DPBP minor version + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_get_api_version(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 *major_ver, + u16 *minor_ver); + +/** @} */ + +#endif /* __FSL_DPBP_H */ diff --git a/roms/u-boot/include/fsl-mc/fsl_dpio.h b/roms/u-boot/include/fsl-mc/fsl_dpio.h new file mode 100644 index 000000000..7788e1962 --- /dev/null +++ b/roms/u-boot/include/fsl-mc/fsl_dpio.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#ifndef _FSL_DPIO_H +#define _FSL_DPIO_H + +/* DPIO Version */ +#define DPIO_VER_MAJOR 4 +#define DPIO_VER_MINOR 2 + +/* Command IDs */ +#define DPIO_CMDID_CLOSE 0x8001 +#define DPIO_CMDID_OPEN 0x8031 +#define DPIO_CMDID_CREATE 0x9031 +#define DPIO_CMDID_DESTROY 0x9831 +#define DPIO_CMDID_GET_API_VERSION 0xa031 + +#define DPIO_CMDID_ENABLE 0x0021 +#define DPIO_CMDID_DISABLE 0x0031 +#define DPIO_CMDID_GET_ATTR 0x0041 +#define DPIO_CMDID_RESET 0x0051 + +/* cmd, param, offset, width, type, arg_name */ +#define DPIO_CMD_OPEN(cmd, dpio_id) \ + MC_CMD_OP(cmd, 0, 0, 32, int, dpio_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPIO_CMD_CREATE(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 16, 2, enum dpio_channel_mode, \ + cfg->channel_mode);\ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->num_priorities);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPIO_RSP_GET_ATTR(cmd, attr) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\ + MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->qbman_portal_id);\ + MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->num_priorities);\ + MC_RSP_OP(cmd, 0, 56, 4, enum dpio_channel_mode, attr->channel_mode);\ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->qbman_portal_ce_offset);\ + MC_RSP_OP(cmd, 2, 0, 64, uint64_t, attr->qbman_portal_ci_offset);\ + MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->qbman_version);\ +} while (0) + +/* Data Path I/O Portal API + * Contains initialization APIs and runtime control APIs for DPIO + */ + +struct fsl_mc_io; + +/** + * dpio_open() - Open a control session for the specified object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpio_id: DPIO unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpio_create() function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_open(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint32_t dpio_id, + uint16_t *token); + +/** + * dpio_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPIO object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_close(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** + * enum dpio_channel_mode - DPIO notification channel mode + * @DPIO_NO_CHANNEL: No support for notification channel + * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a + * dedicated channel in the DPIO; user should point the queue's + * destination in the relevant interface to this DPIO + */ +enum dpio_channel_mode { + DPIO_NO_CHANNEL = 0, + DPIO_LOCAL_CHANNEL = 1, +}; + +/** + * struct dpio_cfg - Structure representing DPIO configuration + * @channel_mode: Notification channel mode + * @num_priorities: Number of priorities for the notification channel (1-8); + * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' + */ +struct dpio_cfg { + enum dpio_channel_mode channel_mode; + uint8_t num_priorities; +}; + +/** + * dpio_create() - Create the DPIO object. + * @mc_io: Pointer to MC portal's I/O object + * @token: Authentication token. + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @obj_id: Returned obj_id; use in subsequent API calls + * + * Create the DPIO object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpio_open() function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_create(struct fsl_mc_io *mc_io, + uint16_t token, + uint32_t cmd_flags, + const struct dpio_cfg *cfg, + uint32_t *obj_id); + +/** + * dpio_destroy() - Destroy the DPIO object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @token: Authentication token. + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @obj_id: Object ID of DPIO + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_destroy(struct fsl_mc_io *mc_io, + uint16_t token, + uint32_t cmd_flags, + uint32_t obj_id); + +/** + * dpio_enable() - Enable the DPIO, allow I/O portal operations. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPIO object + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_enable(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** + * dpio_disable() - Disable the DPIO, stop any I/O portal operation. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPIO object + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_disable(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** + * dpio_reset() - Reset the DPIO, returns the object to initial state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPIO object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_reset(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** + * struct dpio_attr - Structure representing DPIO attributes + * @id: DPIO object ID + * @version: DPIO version + * @qbman_portal_ce_offset: offset of the software portal cache-enabled area + * @qbman_portal_ci_offset: offset of the software portal cache-inhibited area + * @qbman_portal_id: Software portal ID + * @channel_mode: Notification channel mode + * @num_priorities: Number of priorities for the notification channel (1-8); + * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' + * @qbman_version: QBMAN version + */ +struct dpio_attr { + uint32_t id; + uint64_t qbman_portal_ce_offset; + uint64_t qbman_portal_ci_offset; + uint16_t qbman_portal_id; + enum dpio_channel_mode channel_mode; + uint8_t num_priorities; + uint32_t qbman_version; +}; + +/** + * dpio_get_attributes() - Retrieve DPIO attributes + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPIO object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_get_attributes(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpio_attr *attr); + +/** + * dpio_get_api_version - Retrieve DPIO Major and Minor version info. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: DPIO major version + * @minor_ver: DPIO minor version + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_get_api_version(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 *major_ver, + u16 *minor_ver); + +#endif /* _FSL_DPIO_H */ diff --git a/roms/u-boot/include/fsl-mc/fsl_dpmac.h b/roms/u-boot/include/fsl-mc/fsl_dpmac.h new file mode 100644 index 000000000..1cea123a3 --- /dev/null +++ b/roms/u-boot/include/fsl-mc/fsl_dpmac.h @@ -0,0 +1,476 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale Layerscape MC I/O wrapper + * + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * Author: Prabhakar Kushwaha + */ + +#ifndef __FSL_DPMAC_H +#define __FSL_DPMAC_H + +/* DPMAC Version */ +#define DPMAC_VER_MAJOR 4 +#define DPMAC_VER_MINOR 2 + +/* Command IDs */ +#define DPMAC_CMDID_CLOSE 0x8001 +#define DPMAC_CMDID_OPEN 0x80c1 +#define DPMAC_CMDID_CREATE 0x90c1 +#define DPMAC_CMDID_DESTROY 0x98c1 +#define DPMAC_CMDID_GET_API_VERSION 0xa0c1 + +#define DPMAC_CMDID_GET_ATTR 0x0041 +#define DPMAC_CMDID_RESET 0x0051 + +#define DPMAC_CMDID_MDIO_READ 0x0c01 +#define DPMAC_CMDID_MDIO_WRITE 0x0c11 +#define DPMAC_CMDID_GET_LINK_CFG 0x0c21 +#define DPMAC_CMDID_SET_LINK_STATE 0x0c31 +#define DPMAC_CMDID_GET_COUNTER 0x0c41 + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_CREATE(cmd, cfg) \ + MC_CMD_OP(cmd, 0, 0, 16, uint16_t, cfg->mac_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_OPEN(cmd, dpmac_id) \ + MC_CMD_OP(cmd, 0, 0, 32, int, dpmac_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_RSP_GET_ATTRIBUTES(cmd, attr) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 32, int, attr->phy_id);\ + MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\ + MC_RSP_OP(cmd, 1, 32, 8, enum dpmac_link_type, attr->link_type);\ + MC_RSP_OP(cmd, 1, 40, 8, enum dpmac_eth_if, attr->eth_if);\ + MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->max_rate);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_MDIO_READ(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \ + MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_RSP_MDIO_READ(cmd, data) \ + MC_RSP_OP(cmd, 0, 16, 16, uint16_t, data) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_MDIO_WRITE(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \ + MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \ + MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->data); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_RSP_GET_LINK_CFG(cmd, cfg) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \ + MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_SET_LINK_STATE(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \ + MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \ + MC_CMD_OP(cmd, 2, 0, 1, int, cfg->up); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_GET_COUNTER(cmd, type) \ + MC_CMD_OP(cmd, 1, 0, 64, enum dpmac_counter, type) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_RSP_GET_COUNTER(cmd, counter) \ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter) + +/* Data Path MAC API + * Contains initialization APIs and runtime control APIs for DPMAC + */ + +struct fsl_mc_io; + +/** + * dpmac_open() - Open a control session for the specified object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpmac_id: DPMAC unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpmac_create function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_open(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + int dpmac_id, + uint16_t *token); + +/** + * dpmac_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_close(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** + * enum dpmac_link_type - DPMAC link type + * @DPMAC_LINK_TYPE_NONE: No link + * @DPMAC_LINK_TYPE_FIXED: Link is fixed type + * @DPMAC_LINK_TYPE_PHY: Link by PHY ID + * @DPMAC_LINK_TYPE_BACKPLANE: Backplane link type + */ +enum dpmac_link_type { + DPMAC_LINK_TYPE_NONE, + DPMAC_LINK_TYPE_FIXED, + DPMAC_LINK_TYPE_PHY, + DPMAC_LINK_TYPE_BACKPLANE +}; + +/** + * enum dpmac_eth_if - DPMAC Ethrnet interface + * @DPMAC_ETH_IF_MII: MII interface + * @DPMAC_ETH_IF_RMII: RMII interface + * @DPMAC_ETH_IF_SMII: SMII interface + * @DPMAC_ETH_IF_GMII: GMII interface + * @DPMAC_ETH_IF_RGMII: RGMII interface + * @DPMAC_ETH_IF_SGMII: SGMII interface + * @DPMAC_ETH_IF_QSGMII: QSGMII interface + * @DPMAC_ETH_IF_XAUI: XAUI interface + * @DPMAC_ETH_IF_XFI: XFI interface + */ +enum dpmac_eth_if { + DPMAC_ETH_IF_MII, + DPMAC_ETH_IF_RMII, + DPMAC_ETH_IF_SMII, + DPMAC_ETH_IF_GMII, + DPMAC_ETH_IF_RGMII, + DPMAC_ETH_IF_SGMII, + DPMAC_ETH_IF_QSGMII, + DPMAC_ETH_IF_XAUI, + DPMAC_ETH_IF_XFI +}; + +/** + * struct dpmac_cfg - Structure representing DPMAC configuration + * @mac_id: Represents the Hardware MAC ID; in case of multiple WRIOP, + * the MAC IDs are continuous. + * For example: 2 WRIOPs, 16 MACs in each: + * MAC IDs for the 1st WRIOP: 1-16, + * MAC IDs for the 2nd WRIOP: 17-32. + */ +struct dpmac_cfg { + int mac_id; +}; + +/** + * dpmac_create() - Create the DPMAC object. + * @mc_io: Pointer to MC portal's I/O object + * @token: Authentication token. + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @obj_id: Returned obj_id; use in subsequent API calls + * + * Create the DPMAC object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpmac_open function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_create(struct fsl_mc_io *mc_io, + uint16_t token, + uint32_t cmd_flags, + const struct dpmac_cfg *cfg, + uint32_t *obj_id); + +/** + * dpmac_destroy() - Destroy the DPMAC object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @token: Authentication token. + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @obj_id: DPMAC object id + * + * Return: '0' on Success; error code otherwise. + */ +int dpmac_destroy(struct fsl_mc_io *mc_io, + uint16_t token, + uint32_t cmd_flags, + uint32_t obj_id); + +/* DPMAC IRQ Index and Events */ + +/* IRQ index */ +#define DPMAC_IRQ_INDEX 0 +/* IRQ event - indicates a change in link state */ +#define DPMAC_IRQ_EVENT_LINK_CFG_REQ 0x00000001 +/* irq event - Indicates that the link state changed */ +#define DPMAC_IRQ_EVENT_LINK_CHANGED 0x00000002 + +/** + * struct dpmac_attr - Structure representing DPMAC attributes + * @id: DPMAC object ID + * @phy_id: PHY ID + * @link_type: link type + * @eth_if: Ethernet interface + * @max_rate: Maximum supported rate - in Mbps + * @version: DPMAC version + */ +struct dpmac_attr { + int id; + int phy_id; + enum dpmac_link_type link_type; + enum dpmac_eth_if eth_if; + uint32_t max_rate; +}; + +/** + * dpmac_get_attributes - Retrieve DPMAC attributes. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_get_attributes(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_attr *attr); + +/** + * struct dpmac_mdio_cfg - DPMAC MDIO read/write parameters + * @phy_addr: MDIO device address + * @reg: Address of the register within the Clause 45 PHY device from which data + * is to be read + * @data: Data read/write from/to MDIO + */ +struct dpmac_mdio_cfg { + uint8_t phy_addr; + uint8_t reg; + uint16_t data; +}; + +/** + * dpmac_mdio_read() - Perform MDIO read transaction + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @cfg: Structure with MDIO transaction parameters + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_mdio_read(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_mdio_cfg *cfg); + +/** + * dpmac_mdio_write() - Perform MDIO write transaction + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @cfg: Structure with MDIO transaction parameters + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_mdio_write(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_mdio_cfg *cfg); + +/* DPMAC link configuration/state options */ + +/* Enable auto-negotiation */ +#define DPMAC_LINK_OPT_AUTONEG 0x0000000000000001ULL +/* Enable half-duplex mode */ +#define DPMAC_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL +/* Enable pause frames */ +#define DPMAC_LINK_OPT_PAUSE 0x0000000000000004ULL +/* Enable a-symmetric pause frames */ +#define DPMAC_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL + +/** + * struct dpmac_link_cfg - Structure representing DPMAC link configuration + * @rate: Link's rate - in Mbps + * @options: Enable/Disable DPMAC link cfg features (bitmap) + */ +struct dpmac_link_cfg { + uint32_t rate; + uint64_t options; +}; + +/** + * dpmac_get_link_cfg() - Get Ethernet link configuration + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @cfg: Returned structure with the link configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_get_link_cfg(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_link_cfg *cfg); + +/** + * struct dpmac_link_state - DPMAC link configuration request + * @rate: Rate in Mbps + * @options: Enable/Disable DPMAC link cfg features (bitmap) + * @up: Link state + */ +struct dpmac_link_state { + uint32_t rate; + uint64_t options; + int up; +}; + +/** + * dpmac_set_link_state() - Set the Ethernet link status + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @link_state: Link state configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_set_link_state(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_link_state *link_state); + +/** + * enum dpni_counter - DPNI counter types + * @DPMAC_CNT_ING_FRAME_64: counts 64-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_127: counts 65- to 127-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_255: counts 128- to 255-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_511: counts 256- to 511-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_1023: counts 512- to 1023-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_1518: counts 1024- to 1518-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_1519_MAX: counts 1519-octet frame and larger + * (up to max frame length specified), + * good or bad. + * @DPMAC_CNT_ING_FRAG: counts packet which is shorter than 64 octets received + * with a wrong CRC + * @DPMAC_CNT_ING_JABBER: counts packet longer than the maximum frame length + * specified, with a bad frame check sequence. + * @DPMAC_CNT_ING_FRAME_DISCARD: counts dropped packet due to internal errors. + * Occurs when a receive FIFO overflows. + * Includes also packets truncated as a result of + * the receive FIFO overflow. + * @DPMAC_CNT_ING_ALIGN_ERR: counts frame with an alignment error + * (optional used for wrong SFD) + * @DPMAC_CNT_EGR_UNDERSIZED: counts packet transmitted that was less than 64 + * octets long with a good CRC. + * @DPMAC_CNT_ING_OVERSIZED: counts packet longer than the maximum frame length + * specified, with a good frame check sequence. + * @DPMAC_CNT_ING_VALID_PAUSE_FRAME: counts valid pause frame (regular and PFC). + * @DPMAC_CNT_EGR_VALID_PAUSE_FRAME: counts valid pause frame transmitted + * (regular and PFC). + * @DPMAC_CNT_ING_BYTE: counts octet received except preamble for all valid + * frames and valid pause frames. + * @DPMAC_CNT_ING_MCAST_FRAME: counts received multicast frame + * @DPMAC_CNT_ING_BCAST_FRAME: counts received broadcast frame + * @DPMAC_CNT_ING_ALL_FRAME: counts each good or bad packet received. + * @DPMAC_CNT_ING_UCAST_FRAME: counts received unicast frame + * @DPMAC_CNT_ING_ERR_FRAME: counts frame received with an error + * (except for undersized/fragment frame) + * @DPMAC_CNT_EGR_BYTE: counts octet transmitted except preamble for all valid + * frames and valid pause frames transmitted. + * @DPMAC_CNT_EGR_MCAST_FRAME: counts transmitted multicast frame + * @DPMAC_CNT_EGR_BCAST_FRAME: counts transmitted broadcast frame + * @DPMAC_CNT_EGR_UCAST_FRAME: counts transmitted unicast frame + * @DPMAC_CNT_EGR_ERR_FRAME: counts frame transmitted with an error + * @DPMAC_CNT_ING_GOOD_FRAME: counts frame received without error, including + * pause frames. + */ +enum dpmac_counter { + DPMAC_CNT_ING_FRAME_64, + DPMAC_CNT_ING_FRAME_127, + DPMAC_CNT_ING_FRAME_255, + DPMAC_CNT_ING_FRAME_511, + DPMAC_CNT_ING_FRAME_1023, + DPMAC_CNT_ING_FRAME_1518, + DPMAC_CNT_ING_FRAME_1519_MAX, + DPMAC_CNT_ING_FRAG, + DPMAC_CNT_ING_JABBER, + DPMAC_CNT_ING_FRAME_DISCARD, + DPMAC_CNT_ING_ALIGN_ERR, + DPMAC_CNT_EGR_UNDERSIZED, + DPMAC_CNT_ING_OVERSIZED, + DPMAC_CNT_ING_VALID_PAUSE_FRAME, + DPMAC_CNT_EGR_VALID_PAUSE_FRAME, + DPMAC_CNT_ING_BYTE, + DPMAC_CNT_ING_MCAST_FRAME, + DPMAC_CNT_ING_BCAST_FRAME, + DPMAC_CNT_ING_ALL_FRAME, + DPMAC_CNT_ING_UCAST_FRAME, + DPMAC_CNT_ING_ERR_FRAME, + DPMAC_CNT_EGR_BYTE, + DPMAC_CNT_EGR_MCAST_FRAME, + DPMAC_CNT_EGR_BCAST_FRAME, + DPMAC_CNT_EGR_UCAST_FRAME, + DPMAC_CNT_EGR_ERR_FRAME, + DPMAC_CNT_ING_GOOD_FRAME +}; + +/** + * dpmac_get_counter() - Read a specific DPMAC counter + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @type: The requested counter + * @counter: Returned counter value + * + * Return: The requested counter; '0' otherwise. + */ +int dpmac_get_counter(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + enum dpmac_counter type, + uint64_t *counter); +/** + * dpmac_get_api_version - Retrieve DPMAC Major and Minor version info. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: DPMAC major version + * @minor_ver: DPMAC minor version + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_get_api_version(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t *major_ver, + uint16_t *minor_ver); + +#endif /* __FSL_DPMAC_H */ diff --git a/roms/u-boot/include/fsl-mc/fsl_dpmng.h b/roms/u-boot/include/fsl-mc/fsl_dpmng.h new file mode 100644 index 000000000..2148601e8 --- /dev/null +++ b/roms/u-boot/include/fsl-mc/fsl_dpmng.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright 2013-2015 Freescale Semiconductor Inc. + */ +#ifndef __FSL_DPMNG_H +#define __FSL_DPMNG_H + +/* Management Complex General API + * Contains general API for the Management Complex firmware + */ + +struct fsl_mc_io; + +/** + * Management Complex firmware version information + */ +#define MC_VER_MAJOR 9 +#define MC_VER_MINOR 0 + +/** + * struct mc_versoin + * @major: Major version number: incremented on API compatibility changes + * @minor: Minor version number: incremented on API additions (that are + * backward compatible); reset when major version is incremented + * @revision: Internal revision number: incremented on implementation changes + * and/or bug fixes that have no impact on API + */ +struct mc_version { + uint32_t major; + uint32_t minor; + uint32_t revision; +}; + +/** + * mc_get_version() - Retrieves the Management Complex firmware + * version information + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @mc_ver_info: Returned version information structure + * + * Return: '0' on Success; Error code otherwise. + */ +int mc_get_version(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + struct mc_version *mc_ver_info); + +#endif /* __FSL_DPMNG_H */ diff --git a/roms/u-boot/include/fsl-mc/fsl_dpni.h b/roms/u-boot/include/fsl-mc/fsl_dpni.h new file mode 100644 index 000000000..96d81d993 --- /dev/null +++ b/roms/u-boot/include/fsl-mc/fsl_dpni.h @@ -0,0 +1,1326 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ +#ifndef _FSL_DPNI_H +#define _FSL_DPNI_H + +/* DPNI Version */ +#define DPNI_VER_MAJOR 7 +#define DPNI_VER_MINOR 3 + +/* Command IDs */ +#define DPNI_CMDID_OPEN 0x8011 +#define DPNI_CMDID_CLOSE 0x8001 +#define DPNI_CMDID_CREATE 0x9011 +#define DPNI_CMDID_DESTROY 0x9811 +#define DPNI_CMDID_GET_API_VERSION 0xa011 + +#define DPNI_CMDID_ENABLE 0x0021 +#define DPNI_CMDID_DISABLE 0x0031 +#define DPNI_CMDID_GET_ATTR 0x0041 +#define DPNI_CMDID_RESET 0x0051 + +#define DPNI_CMDID_SET_POOLS 0x2002 +#define DPNI_CMDID_SET_BUFFER_LAYOUT 0x2651 +#define DPNI_CMDID_GET_BUFFER_LAYOUT 0x2641 +#define DPNI_CMDID_SET_ERRORS_BEHAVIOR 0x20B1 + +#define DPNI_CMDID_GET_QDID 0x2101 +#define DPNI_CMDID_GET_TX_DATA_OFFSET 0x2121 +#define DPNI_CMDID_GET_LINK_STATE 0x2151 +#define DPNI_CMDID_SET_LINK_CFG 0x21A1 + +#define DPNI_CMDID_SET_PRIM_MAC 0x2241 +#define DPNI_CMDID_GET_PRIM_MAC 0x2251 +#define DPNI_CMDID_ADD_MAC_ADDR 0x2261 +#define DPNI_CMDID_REMOVE_MAC_ADDR 0x2271 + +#define DPNI_CMDID_GET_STATISTICS 0x25D1 +#define DPNI_CMDID_RESET_STATISTICS 0x25E1 +#define DPNI_CMDID_GET_QUEUE 0x25F1 +#define DPNI_CMDID_SET_QUEUE 0x2601 +#define DPNI_CMDID_SET_TX_CONFIRMATION_MODE 0x2661 + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_OPEN(cmd, dpni_id) \ + MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_PREP_CFG(param, cfg) \ +do { \ + MC_PREP_OP(param, 0, 0, 32, uint16_t, cfg->adv.options); \ + MC_PREP_OP(param, 0, 32, 8, uint16_t, cfg->adv.num_queues); \ + MC_PREP_OP(param, 0, 40, 8, uint16_t, cfg->adv.num_tcs); \ + MC_PREP_OP(param, 0, 48, 8, uint16_t, cfg->adv.mac_entries); \ + MC_PREP_OP(param, 1, 0, 8, uint16_t, cfg->adv.vlan_entries); \ + MC_PREP_OP(param, 1, 16, 8, uint16_t, cfg->adv.qos_entries); \ + MC_PREP_OP(param, 1, 32, 16, uint16_t, cfg->adv.fs_entries); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_EXT_CFG(param, cfg) \ +do { \ + MC_EXT_OP(param, 0, 0, 32, uint16_t, cfg->adv.options); \ + MC_EXT_OP(param, 0, 32, 8, uint16_t, cfg->adv.num_queues); \ + MC_EXT_OP(param, 0, 40, 8, uint16_t, cfg->adv.num_tcs); \ + MC_EXT_OP(param, 0, 48, 8, uint16_t, cfg->adv.mac_entries); \ + MC_EXT_OP(param, 1, 0, 8, uint16_t, cfg->adv.vlan_entries); \ + MC_EXT_OP(param, 1, 16, 8, uint16_t, cfg->adv.qos_entries); \ + MC_EXT_OP(param, 1, 32, 16, uint16_t, cfg->adv.fs_entries); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_CREATE(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->adv.options); \ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->adv.num_queues); \ + MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->adv.num_tcs); \ + MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->adv.mac_entries); \ + MC_CMD_OP(cmd, 1, 0, 8, uint8_t, cfg->adv.vlan_entries); \ + MC_CMD_OP(cmd, 1, 16, 8, uint8_t, cfg->adv.qos_entries); \ + MC_CMD_OP(cmd, 1, 32, 16, uint8_t, cfg->adv.fs_entries); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_POOLS(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_dpbp); \ + MC_CMD_OP(cmd, 0, 8, 1, int, cfg->pools[0].backup_pool); \ + MC_CMD_OP(cmd, 0, 9, 1, int, cfg->pools[1].backup_pool); \ + MC_CMD_OP(cmd, 0, 10, 1, int, cfg->pools[2].backup_pool); \ + MC_CMD_OP(cmd, 0, 11, 1, int, cfg->pools[3].backup_pool); \ + MC_CMD_OP(cmd, 0, 12, 1, int, cfg->pools[4].backup_pool); \ + MC_CMD_OP(cmd, 0, 13, 1, int, cfg->pools[5].backup_pool); \ + MC_CMD_OP(cmd, 0, 14, 1, int, cfg->pools[6].backup_pool); \ + MC_CMD_OP(cmd, 0, 15, 1, int, cfg->pools[7].backup_pool); \ + MC_CMD_OP(cmd, 0, 32, 32, int, cfg->pools[0].dpbp_id); \ + MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\ + MC_CMD_OP(cmd, 1, 0, 32, int, cfg->pools[1].dpbp_id); \ + MC_CMD_OP(cmd, 4, 48, 16, uint16_t, cfg->pools[1].buffer_size);\ + MC_CMD_OP(cmd, 1, 32, 32, int, cfg->pools[2].dpbp_id); \ + MC_CMD_OP(cmd, 5, 0, 16, uint16_t, cfg->pools[2].buffer_size);\ + MC_CMD_OP(cmd, 2, 0, 32, int, cfg->pools[3].dpbp_id); \ + MC_CMD_OP(cmd, 5, 16, 16, uint16_t, cfg->pools[3].buffer_size);\ + MC_CMD_OP(cmd, 2, 32, 32, int, cfg->pools[4].dpbp_id); \ + MC_CMD_OP(cmd, 5, 32, 16, uint16_t, cfg->pools[4].buffer_size);\ + MC_CMD_OP(cmd, 3, 0, 32, int, cfg->pools[5].dpbp_id); \ + MC_CMD_OP(cmd, 5, 48, 16, uint16_t, cfg->pools[5].buffer_size);\ + MC_CMD_OP(cmd, 3, 32, 32, int, cfg->pools[6].dpbp_id); \ + MC_CMD_OP(cmd, 6, 0, 16, uint16_t, cfg->pools[6].buffer_size);\ + MC_CMD_OP(cmd, 4, 0, 32, int, cfg->pools[7].dpbp_id); \ + MC_CMD_OP(cmd, 6, 16, 16, uint16_t, cfg->pools[7].buffer_size);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_ATTR(cmd, attr) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 32, int, attr->options);\ + MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->max_num_queues); \ + MC_RSP_OP(cmd, 0, 40, 8, uint8_t, attr->max_num_tcs); \ + MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->max_mac_entries); \ + MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->max_vlan_entries); \ + MC_RSP_OP(cmd, 1, 16, 8, uint8_t, attr->max_qos_entries); \ + MC_RSP_OP(cmd, 1, 32, 16, uint16_t, attr->max_fs_entries); \ + MC_RSP_OP(cmd, 2, 0, 8, uint8_t, attr->max_qos_key_size); \ + MC_RSP_OP(cmd, 2, 8, 8, uint8_t, attr->max_fs_key_size); \ + MC_RSP_OP(cmd, 2, 16, 16, uint16_t, attr->wriop_version); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->errors); \ + MC_CMD_OP(cmd, 0, 32, 4, enum dpni_error_action, cfg->error_action); \ + MC_CMD_OP(cmd, 0, 36, 1, int, cfg->set_frame_annotation); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_BUFFER_LAYOUT(cmd, layout, queue) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, queue); \ + MC_CMD_OP(cmd, 1, 0, 16, uint16_t, layout->private_data_size); \ + MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_align); \ + MC_CMD_OP(cmd, 0, 32, 16, uint16_t, layout->options); \ + MC_CMD_OP(cmd, 0, 48, 1, int, layout->pass_timestamp); \ + MC_CMD_OP(cmd, 0, 49, 1, int, layout->pass_parser_result); \ + MC_CMD_OP(cmd, 0, 50, 1, int, layout->pass_frame_status); \ + MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_head_room); \ + MC_CMD_OP(cmd, 1, 48, 16, uint16_t, layout->data_tail_room); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_QDID(cmd, qdid) \ + MC_RSP_OP(cmd, 0, 0, 16, uint16_t, qdid) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_TX_DATA_OFFSET(cmd, data_offset) \ + MC_RSP_OP(cmd, 0, 0, 16, uint16_t, data_offset) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_LINK_CFG(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate);\ + MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_LINK_STATE(cmd, state) \ +do { \ + MC_RSP_OP(cmd, 0, 32, 1, int, state->up);\ + MC_RSP_OP(cmd, 1, 0, 32, uint32_t, state->rate);\ + MC_RSP_OP(cmd, 2, 0, 64, uint64_t, state->options);\ +} while (0) + + + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr) \ +do { \ + MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ + MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ + MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ + MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ + MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr) \ +do { \ + MC_RSP_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ + MC_RSP_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ + MC_RSP_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ + MC_RSP_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ + MC_RSP_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ + MC_RSP_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr) \ +do { \ + MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ + MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ + MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ + MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ + MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr) \ +do { \ + MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ + MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ + MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ + MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ + MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ +} while (0) + +#define DPNI_CMD_GET_QUEUE(cmd, type, tc, index) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, type); \ + MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc); \ + MC_CMD_OP(cmd, 0, 16, 8, uint8_t, index); \ +} while (0) + +#define DPNI_RSP_GET_QUEUE(cmd, queue) \ +do { \ + MC_RSP_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \ + MC_RSP_OP(cmd, 1, 56, 4, enum dpni_dest, (queue)->destination.type); \ + MC_RSP_OP(cmd, 1, 62, 1, char, (queue)->destination.stash_ctrl); \ + MC_RSP_OP(cmd, 1, 63, 1, char, (queue)->destination.hold_active); \ + MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (queue)->flc); \ + MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (queue)->user_context); \ + MC_RSP_OP(cmd, 4, 0, 32, uint32_t, (queue)->fqid); \ + MC_RSP_OP(cmd, 4, 32, 16, uint16_t, (queue)->qdbin); \ +} while (0) + +#define DPNI_CMD_SET_QUEUE(cmd, type, tc, index, queue) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, type); \ + MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc); \ + MC_CMD_OP(cmd, 0, 16, 8, uint8_t, index); \ + MC_CMD_OP(cmd, 0, 24, 8, uint8_t, (queue)->options); \ + MC_CMD_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \ + MC_CMD_OP(cmd, 1, 56, 4, enum dpni_dest, (queue)->destination.type); \ + MC_CMD_OP(cmd, 1, 62, 1, char, (queue)->destination.stash_ctrl); \ + MC_CMD_OP(cmd, 1, 63, 1, char, (queue)->destination.hold_active); \ + MC_CMD_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \ + MC_CMD_OP(cmd, 2, 0, 64, uint64_t, (queue)->flc); \ + MC_CMD_OP(cmd, 3, 0, 64, uint64_t, (queue)->user_context); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_GET_STATISTICS(cmd, page) \ + MC_CMD_OP(cmd, 0, 0, 8, uint8_t, page) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_STATISTICS(cmd, stat) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 64, uint64_t, (stat)->counter0); \ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, (stat)->counter1); \ + MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (stat)->counter2); \ + MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (stat)->counter3); \ + MC_RSP_OP(cmd, 4, 0, 64, uint64_t, (stat)->counter4); \ + MC_RSP_OP(cmd, 5, 0, 64, uint64_t, (stat)->counter5); \ + MC_RSP_OP(cmd, 6, 0, 64, uint64_t, (stat)->counter6); \ +} while (0) + +enum net_prot { + NET_PROT_NONE = 0, + NET_PROT_PAYLOAD, + NET_PROT_ETH, + NET_PROT_VLAN, + NET_PROT_IPV4, + NET_PROT_IPV6, + NET_PROT_IP, + NET_PROT_TCP, + NET_PROT_UDP, + NET_PROT_UDP_LITE, + NET_PROT_IPHC, + NET_PROT_SCTP, + NET_PROT_SCTP_CHUNK_DATA, + NET_PROT_PPPOE, + NET_PROT_PPP, + NET_PROT_PPPMUX, + NET_PROT_PPPMUX_SUBFRM, + NET_PROT_L2TPV2, + NET_PROT_L2TPV3_CTRL, + NET_PROT_L2TPV3_SESS, + NET_PROT_LLC, + NET_PROT_LLC_SNAP, + NET_PROT_NLPID, + NET_PROT_SNAP, + NET_PROT_MPLS, + NET_PROT_IPSEC_AH, + NET_PROT_IPSEC_ESP, + NET_PROT_UDP_ENC_ESP, /* RFC 3948 */ + NET_PROT_MACSEC, + NET_PROT_GRE, + NET_PROT_MINENCAP, + NET_PROT_DCCP, + NET_PROT_ICMP, + NET_PROT_IGMP, + NET_PROT_ARP, + NET_PROT_CAPWAP_DATA, + NET_PROT_CAPWAP_CTRL, + NET_PROT_RFC2684, + NET_PROT_ICMPV6, + NET_PROT_FCOE, + NET_PROT_FIP, + NET_PROT_ISCSI, + NET_PROT_GTP, + NET_PROT_USER_DEFINED_L2, + NET_PROT_USER_DEFINED_L3, + NET_PROT_USER_DEFINED_L4, + NET_PROT_USER_DEFINED_L5, + NET_PROT_USER_DEFINED_SHIM1, + NET_PROT_USER_DEFINED_SHIM2, + + NET_PROT_DUMMY_LAST +}; + +/** + * Data Path Network Interface API + * Contains initialization APIs and runtime control APIs for DPNI + */ + +struct fsl_mc_io; + +/* General DPNI macros */ + +/* Maximum number of traffic classes */ +#define DPNI_MAX_TC 8 +/* Maximum number of buffer pools per DPNI */ +#define DPNI_MAX_DPBP 8 + +/* All traffic classes considered; see dpni_set_rx_flow() */ +#define DPNI_ALL_TCS (uint8_t)(-1) +/* All flows within traffic class considered; see dpni_set_rx_flow() */ +#define DPNI_ALL_TC_FLOWS (uint16_t)(-1) +/* Generate new flow ID; see dpni_set_tx_flow() */ +#define DPNI_NEW_FLOW_ID (uint16_t)(-1) +/* use for common tx-conf queue; see dpni_set_tx_conf_() */ +#define DPNI_COMMON_TX_CONF (uint16_t)(-1) + +/** + * dpni_open() - Open a control session for the specified object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpni_id: DPNI unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpni_create() function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_open(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + int dpni_id, + uint16_t *token); + +/** + * dpni_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_close(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/* DPNI configuration options */ + +/** + * Allow different distribution key profiles for different traffic classes; + * if not set, a single key profile is assumed + */ +#define DPNI_OPT_ALLOW_DIST_KEY_PER_TC 0x00000001 + +/** + * Disable all non-error transmit confirmation; error frames are reported + * back to a common Tx error queue + */ +#define DPNI_OPT_TX_CONF_DISABLED 0x00000002 + +/* Disable per-sender private Tx confirmation/error queue */ +#define DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED 0x00000004 + +/** + * Support distribution based on hashed key; + * allows statistical distribution over receive queues in a traffic class + */ +#define DPNI_OPT_DIST_HASH 0x00000010 + +/** + * Support distribution based on flow steering; + * allows explicit control of distribution over receive queues in a traffic + * class + */ +#define DPNI_OPT_DIST_FS 0x00000020 + +/* Unicast filtering support */ +#define DPNI_OPT_UNICAST_FILTER 0x00000080 +/* Multicast filtering support */ +#define DPNI_OPT_MULTICAST_FILTER 0x00000100 +/* VLAN filtering support */ +#define DPNI_OPT_VLAN_FILTER 0x00000200 +/* Support IP reassembly on received packets */ +#define DPNI_OPT_IPR 0x00000800 +/* Support IP fragmentation on transmitted packets */ +#define DPNI_OPT_IPF 0x00001000 +/* VLAN manipulation support */ +#define DPNI_OPT_VLAN_MANIPULATION 0x00010000 +/* Support masking of QoS lookup keys */ +#define DPNI_OPT_QOS_MASK_SUPPORT 0x00020000 +/* Support masking of Flow Steering lookup keys */ +#define DPNI_OPT_FS_MASK_SUPPORT 0x00040000 + +/** + * enum dpni_queue_type - Identifies a type of queue targeted by the command + * @DPNI_QUEUE_RX: Rx queue + * @DPNI_QUEUE_TX: Tx queue + * @DPNI_QUEUE_TX_CONFIRM: Tx confirmation queue + * @DPNI_QUEUE_RX_ERR: Rx error queue + */ +enum dpni_queue_type { + DPNI_QUEUE_RX, + DPNI_QUEUE_TX, + DPNI_QUEUE_TX_CONFIRM, + DPNI_QUEUE_RX_ERR, +}; + +struct dpni_cfg { + uint8_t mac_addr[6]; + struct { + uint32_t options; + uint16_t fs_entries; + uint8_t num_queues; + uint8_t num_tcs; + uint8_t mac_entries; + uint8_t vlan_entries; + uint8_t qos_entries; + } adv; +}; + +/** + * struct dpni_extended_cfg - Structure representing extended DPNI configuration + * @tc_cfg: TCs configuration + * @ipr_cfg: IP reassembly configuration + */ +struct dpni_extended_cfg { + /** + * struct tc_cfg - TC configuration + * @max_dist: Maximum distribution size for Rx traffic class; + * supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96, + * 112,128,192,224,256,384,448,512,768,896,1024; + * value '0' will be treated as '1'. + * other unsupported values will be round down to the nearest + * supported value. + * @max_fs_entries: Maximum FS entries for Rx traffic class; + * '0' means no support for this TC; + */ + struct { + uint16_t max_dist; + uint16_t max_fs_entries; + } tc_cfg[DPNI_MAX_TC]; + /** + * struct ipr_cfg - Structure representing IP reassembly configuration + * @max_reass_frm_size: Maximum size of the reassembled frame + * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments + * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments + * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly + * process + * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly + * process + */ + struct { + uint16_t max_reass_frm_size; + uint16_t min_frag_size_ipv4; + uint16_t min_frag_size_ipv6; + uint16_t max_open_frames_ipv4; + uint16_t max_open_frames_ipv6; + } ipr_cfg; +}; + +/** + * dpni_prepare_cfg() - function prepare parameters + * @cfg: cfg structure + * @cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA + * + * This function has to be called before dpni_create() + */ +int dpni_prepare_cfg(const struct dpni_cfg *cfg, + uint8_t *cfg_buf); +/** + * dpni_create() - Create the DPNI object + * @mc_io: Pointer to MC portal's I/O object + * @token: Authentication token. + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @obj_id: Returned obj_id; use in subsequent API calls + * + * Create the DPNI object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpni_open() function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_create(struct fsl_mc_io *mc_io, + uint16_t token, + uint32_t cmd_flags, + const struct dpni_cfg *cfg, + uint32_t *obj_id); + +/** + * dpni_destroy() - Destroy the DPNI object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @token: Authentication token. + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @obj_id: Returned obj_id; use in subsequent API calls + * + * Return: '0' on Success; error code otherwise. + */ +int dpni_destroy(struct fsl_mc_io *mc_io, + uint16_t token, + uint32_t cmd_flags, + uint32_t obj_id); + +/** + * struct dpni_pools_cfg - Structure representing buffer pools configuration + * @num_dpbp: Number of DPBPs + * @pools: Array of buffer pools parameters; The number of valid entries + * must match 'num_dpbp' value + */ +struct dpni_pools_cfg { + uint8_t num_dpbp; + /** + * struct pools - Buffer pools parameters + * @dpbp_id: DPBP object ID + * @buffer_size: Buffer size + * @backup_pool: Backup pool + */ + struct { + int dpbp_id; + uint16_t buffer_size; + int backup_pool; + } pools[DPNI_MAX_DPBP]; +}; + +/** + * dpni_set_pools() - Set buffer pools configuration + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @cfg: Buffer pools configuration + * + * mandatory for DPNI operation + * warning:Allowed only when DPNI is disabled + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_pools(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dpni_pools_cfg *cfg); + +/** + * dpni_enable() - Enable the DPNI, allow sending and receiving frames. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_enable(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** + * dpni_disable() - Disable the DPNI, stop sending and receiving frames. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_disable(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + + +/** + * dpni_reset() - Reset the DPNI, returns the object to initial state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_reset(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** + * struct dpni_attr - Structure representing DPNI attributes + * @options: Mask of available options; reflects the value as was given in + * object's creation + * @max_num_queues: Number of queues available (for both Tx and Rx) + * @max_num_tcs: Maximum number of traffic classes (for both Tx and Rx) + * @max_mac_entries: Maximum number of traffic classes (for both Tx and Rx) + * @max_unicast_filters: Maximum number of unicast filters + * @max_multicast_filters: Maximum number of multicast filters + * @max_vlan_entries: Maximum number of VLAN filters + * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in QoS table + * @max_fs_entries: declares the maximum entries in flow steering table + * @max_qos_key_size: Maximum key size for the QoS look-up + * @max_fs_key_size: Maximum key size for the flow steering + * @wriop_version: Indicates revision of WRIOP hardware block + */ +struct dpni_attr { + uint32_t id; + uint32_t options; + uint8_t max_num_queues; + uint8_t max_num_tcs; + uint8_t max_mac_entries; + uint8_t max_vlan_entries; + uint8_t max_qos_entries; + uint16_t max_fs_entries; + uint8_t max_qos_key_size; + uint8_t max_fs_key_size; + uint16_t wriop_version; +}; + +/** + * dpni_get_attributes() - Retrieve DPNI attributes. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @attr: Object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_attributes(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_attr *attr); + +/** + * dpni_extract_cfg() - extract the parameters + * @cfg: cfg structure + * @cfg_buf: 256 bytes of DMA-able memory + * + * This function has to be called after dpni_get_attributes() + */ +int dpni_extract_cfg(struct dpni_cfg *cfg, + const uint8_t *cfg_buf); + +/** + * DPNI errors + */ + +/** + * Extract out of frame header error + */ +#define DPNI_ERROR_EOFHE 0x00020000 +/** + * Frame length error + */ +#define DPNI_ERROR_FLE 0x00002000 +/** + * Frame physical error + */ +#define DPNI_ERROR_FPE 0x00001000 +/** + * Parsing header error + */ +#define DPNI_ERROR_PHE 0x00000020 +/** + * Parser L3 checksum error + */ +#define DPNI_ERROR_L3CE 0x00000004 +/** + * Parser L3 checksum error + */ +#define DPNI_ERROR_L4CE 0x00000001 + +/** + * enum dpni_error_action - Defines DPNI behavior for errors + * @DPNI_ERROR_ACTION_DISCARD: Discard the frame + * @DPNI_ERROR_ACTION_CONTINUE: Continue with the normal flow + * @DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE: Send the frame to the error queue + */ +enum dpni_error_action { + DPNI_ERROR_ACTION_DISCARD = 0, + DPNI_ERROR_ACTION_CONTINUE = 1, + DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE = 2 +}; + +/** + * struct dpni_error_cfg - Structure representing DPNI errors treatment + * @errors: Errors mask; use 'DPNI_ERROR__ + * @error_action: The desired action for the errors mask + * @set_frame_annotation: Set to '1' to mark the errors in frame annotation + * status (FAS); relevant only for the non-discard action + */ +struct dpni_error_cfg { + uint32_t errors; + enum dpni_error_action error_action; + int set_frame_annotation; +}; + +/** + * dpni_set_errors_behavior() - Set errors behavior + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @cfg: Errors configuration + * + * this function may be called numerous times with different + * error masks + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_error_cfg *cfg); + +/* DPNI buffer layout modification options */ + +/* Select to modify the time-stamp setting */ +#define DPNI_BUF_LAYOUT_OPT_TIMESTAMP 0x00000001 +/* Select to modify the parser-result setting; not applicable for Tx */ +#define DPNI_BUF_LAYOUT_OPT_PARSER_RESULT 0x00000002 +/* Select to modify the frame-status setting */ +#define DPNI_BUF_LAYOUT_OPT_FRAME_STATUS 0x00000004 +/* Select to modify the private-data-size setting */ +#define DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE 0x00000008 +/* Select to modify the data-alignment setting */ +#define DPNI_BUF_LAYOUT_OPT_DATA_ALIGN 0x00000010 +/* Select to modify the data-head-room setting */ +#define DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM 0x00000020 +/*!< Select to modify the data-tail-room setting */ +#define DPNI_BUF_LAYOUT_OPT_DATA_TAIL_ROOM 0x00000040 + +/** + * struct dpni_buffer_layout - Structure representing DPNI buffer layout + * @options: Flags representing the suggested modifications to the buffer + * layout; Use any combination of 'DPNI_BUF_LAYOUT_OPT_' flags + * @pass_timestamp: Pass timestamp value + * @pass_parser_result: Pass parser results + * @pass_frame_status: Pass frame status + * @private_data_size: Size kept for private data (in bytes) + * @data_align: Data alignment + * @data_head_room: Data head room + * @data_tail_room: Data tail room + */ +struct dpni_buffer_layout { + uint16_t options; + int pass_timestamp; + int pass_parser_result; + int pass_frame_status; + uint16_t private_data_size; + uint16_t data_align; + uint16_t data_head_room; + uint16_t data_tail_room; +}; + +/** + * dpni_get_buffer_layout() - Retrieve buffer layout attributes. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @layout: Returns buffer layout attributes + * @type: DPNI queue type + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_buffer_layout(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dpni_buffer_layout *layout, + enum dpni_queue_type type); + +/** + * dpni_set_buffer_layout() - Set buffer layout configuration. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @layout: Buffer layout configuration + * @type: DPNI queue type + * + * Return: '0' on Success; Error code otherwise. + * + * @warning Allowed only when DPNI is disabled + */ +int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dpni_buffer_layout *layout, + enum dpni_queue_type type); + +/** + * dpni_get_qdid() - Get the Queuing Destination ID (QDID) that should be used + * for enqueue operations + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @qdid: Returned virtual QDID value that should be used as an argument + * in all enqueue operations + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_qdid(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint16_t *qdid); + +/** + * dpni_get_tx_data_offset() - Get the Tx data offset (from start of buffer) + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @data_offset: Tx data offset (from start of buffer) + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint16_t *data_offset); + +/* Enable auto-negotiation */ +#define DPNI_LINK_OPT_AUTONEG 0x0000000000000001ULL +/* Enable half-duplex mode */ +#define DPNI_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL +/* Enable pause frames */ +#define DPNI_LINK_OPT_PAUSE 0x0000000000000004ULL +/* Enable a-symmetric pause frames */ +#define DPNI_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL + +/** + * struct - Structure representing DPNI link configuration + * @rate: Rate + * @options: Mask of available options; use 'DPNI_LINK_OPT_' values + */ +struct dpni_link_cfg { + uint32_t rate; + uint64_t options; +}; + +/** + * dpni_set_link_cfg() - set the link configuration. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @cfg: Link configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_link_cfg(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dpni_link_cfg *cfg); + +/** + * struct dpni_link_state - Structure representing DPNI link state + * @rate: Rate + * @options: Mask of available options; use 'DPNI_LINK_OPT_' values + * @up: Link state; '0' for down, '1' for up + */ +struct dpni_link_state { + uint32_t rate; + uint64_t options; + int up; +}; + +/** + * dpni_get_link_state() - Return the link state (either up or down) + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @state: Returned link state; + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_link_state(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_link_state *state); + +/** + * dpni_set_primary_mac_addr() - Set the primary MAC address + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @mac_addr: MAC address to set as primary address + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const uint8_t mac_addr[6]); + +/** + * dpni_get_primary_mac_addr() - Get the primary MAC address + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @mac_addr: Returned MAC address + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t mac_addr[6]); + +/** + * dpni_add_mac_addr() - Add MAC address filter + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @mac_addr: MAC address to add + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_add_mac_addr(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const uint8_t mac_addr[6]); + +/** + * dpni_remove_mac_addr() - Remove MAC address filter + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @mac_addr: MAC address to remove + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_remove_mac_addr(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const uint8_t mac_addr[6]); + +/** + * enum dpni_dest - DPNI destination types + * @DPNI_DEST_NONE: Unassigned destination; The queue is set in parked mode and + * does not generate FQDAN notifications; user is expected to + * dequeue from the queue based on polling or other user-defined + * method + * @DPNI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN + * notifications to the specified DPIO; user is expected to dequeue + * from the queue only after notification is received + * @DPNI_DEST_DPCON: The queue is set in schedule mode and does not generate + * FQDAN notifications, but is connected to the specified DPCON + * object; user is expected to dequeue from the DPCON channel + */ +enum dpni_dest { + DPNI_DEST_NONE = 0, + DPNI_DEST_DPIO = 1, + DPNI_DEST_DPCON = 2 +}; + +/** + * struct dpni_dest_cfg - Structure representing DPNI destination parameters + * @dest_type: Destination type + * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type + * @priority: Priority selection within the DPIO or DPCON channel; valid values + * are 0-1 or 0-7, depending on the number of priorities in that + * channel; not relevant for 'DPNI_DEST_NONE' option + */ +struct dpni_dest_cfg { + enum dpni_dest dest_type; + int dest_id; + uint8_t priority; +}; + +/** + * enum dpni_flc_type - DPNI FLC types + * @DPNI_FLC_USER_DEFINED: select the FLC to be used for user defined value + * @DPNI_FLC_STASH: select the FLC to be used for stash control + */ +enum dpni_flc_type { + DPNI_FLC_USER_DEFINED = 0, + DPNI_FLC_STASH = 1, +}; + +/** + * enum dpni_stash_size - DPNI FLC stashing size + * @DPNI_STASH_SIZE_0B: no stash + * @DPNI_STASH_SIZE_64B: stashes 64 bytes + * @DPNI_STASH_SIZE_128B: stashes 128 bytes + * @DPNI_STASH_SIZE_192B: stashes 192 bytes + */ +enum dpni_stash_size { + DPNI_STASH_SIZE_0B = 0, + DPNI_STASH_SIZE_64B = 1, + DPNI_STASH_SIZE_128B = 2, + DPNI_STASH_SIZE_192B = 3, +}; + +/* DPNI FLC stash options */ + +/* stashes the whole annotation area (up to 192 bytes) */ +#define DPNI_FLC_STASH_FRAME_ANNOTATION 0x00000001 + +/** + * struct dpni_flc_cfg - Structure representing DPNI FLC configuration + * @flc_type: FLC type + * @options: Mask of available options; + * use 'DPNI_FLC_STASH_' values + * @frame_data_size: Size of frame data to be stashed + * @flow_context_size: Size of flow context to be stashed + * @flow_context: 1. In case flc_type is 'DPNI_FLC_USER_DEFINED': + * this value will be provided in the frame descriptor + * (FD[FLC]) + * 2. In case flc_type is 'DPNI_FLC_STASH': + * this value will be I/O virtual address of the + * flow-context; + * Must be cacheline-aligned and DMA-able memory + */ +struct dpni_flc_cfg { + enum dpni_flc_type flc_type; + uint32_t options; + enum dpni_stash_size frame_data_size; + enum dpni_stash_size flow_context_size; + uint64_t flow_context; +}; + +/* DPNI queue modification options */ + +/* Select to modify the user's context associated with the queue */ +#define DPNI_QUEUE_OPT_USER_CTX 0x00000001 +/* Select to modify the queue's destination */ +#define DPNI_QUEUE_OPT_DEST 0x00000002 +/** Select to modify the flow-context parameters; + * not applicable for Tx-conf/Err queues as the FD comes from the user + */ +#define DPNI_QUEUE_OPT_FLC 0x00000004 +/* Select to modify the queue's order preservation */ +#define DPNI_QUEUE_OPT_ORDER_PRESERVATION 0x00000008 +/* Select to modify the queue's tail-drop threshold */ +#define DPNI_QUEUE_OPT_TAILDROP_THRESHOLD 0x00000010 + +/** + * struct dpni_queue_cfg - Structure representing queue configuration + * @options: Flags representing the suggested modifications to the queue; + * Use any combination of 'DPNI_QUEUE_OPT_' flags + * @user_ctx: User context value provided in the frame descriptor of each + * dequeued frame; valid only if 'DPNI_QUEUE_OPT_USER_CTX' + * is contained in 'options' + * @dest_cfg: Queue destination parameters; + * valid only if 'DPNI_QUEUE_OPT_DEST' is contained in 'options' + * @flc_cfg: Flow context configuration; in case the TC's distribution + * is either NONE or HASH the FLC's settings of flow#0 are used. + * in the case of FS (flow-steering) the flow's FLC settings + * are used. + * valid only if 'DPNI_QUEUE_OPT_FLC' is contained in 'options' + * @order_preservation_en: enable/disable order preservation; + * valid only if 'DPNI_QUEUE_OPT_ORDER_PRESERVATION' is contained + * in 'options' + * @tail_drop_threshold: set the queue's tail drop threshold in bytes; + * '0' value disable the threshold; maximum value is 0xE000000; + * valid only if 'DPNI_QUEUE_OPT_TAILDROP_THRESHOLD' is contained + * in 'options' + */ +struct dpni_queue_cfg { + uint32_t options; + uint64_t user_ctx; + struct dpni_dest_cfg dest_cfg; + struct dpni_flc_cfg flc_cfg; + int order_preservation_en; + uint32_t tail_drop_threshold; +}; + +/** + * struct dpni_queue_attr - Structure representing queue attributes + * @user_ctx: User context value provided in the frame descriptor of each + * dequeued frame + * @dest_cfg: Queue destination configuration + * @flc_cfg: Flow context configuration + * @order_preservation_en: enable/disable order preservation + * @tail_drop_threshold: queue's tail drop threshold in bytes; + * @fqid: Virtual fqid value to be used for dequeue operations + */ +struct dpni_queue_attr { + uint64_t user_ctx; + struct dpni_dest_cfg dest_cfg; + struct dpni_flc_cfg flc_cfg; + int order_preservation_en; + uint32_t tail_drop_threshold; + uint32_t fqid; +}; + +/* DPNI Tx flow modification options */ + +/* Select to modify the settings for dedicate Tx confirmation/error */ +#define DPNI_TX_FLOW_OPT_TX_CONF_ERROR 0x00000001 +/*!< Select to modify the L3 checksum generation setting */ +#define DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN 0x00000010 +/*!< Select to modify the L4 checksum generation setting */ +#define DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN 0x00000020 + +/** + * dpni_get_api_version - Retrieve DPNI Major and Minor version info. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: DPNI major version + * @minor_ver: DPNI minor version + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_api_version(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 *major_ver, + u16 *minor_ver); + +/** + * enum dpni_confirmation_mode - Defines DPNI options supported for Tx + * confirmation + * @DPNI_CONF_AFFINE: For each Tx queue set associated with a sender there is + * an affine Tx Confirmation queue + * @DPNI_CONF_SINGLE: All Tx queues are associated with a single Tx + * confirmation queue + * @DPNI_CONF_DISABLE: Tx frames are not confirmed. This must be associated + * with proper FD set-up to have buffers release to a Buffer Pool, otherwise + * buffers will be leaked. + */ +enum dpni_confirmation_mode { + DPNI_CONF_AFFINE, + DPNI_CONF_SINGLE, + DPNI_CONF_DISABLE, +}; + +struct dpni_tx_confirmation_mode { + uint32_t pad; + uint8_t confirmation_mode; +}; + +/** + * struct dpni_queue - Queue structure + * @fqid: FQID used for enqueueing to and/or configuration of this specific FQ + * @qdbin: Queueing bin, used to enqueue using QDID, DQBIN, QPRI. Only relevant + * for Tx queues. + * @flc: FLC value for traffic dequeued from this queue. + * @user_context: User data, presented to the user along with any frames + * from this queue. Not relevant for Tx queues. + */ +struct dpni_queue { + /** + * struct destination - Destination structure + * @id: ID of the destination, only relevant if DEST_TYPE is > 0. + * Identifies either a DPIO or a DPCON object. Not relevant for Tx + * queues. + * @type: May be one of the following: + * 0 - No destination, queue can be manually queried, but won't + * push traffic or notifications to a DPIO; + * 1 - The destination is DPIO. When traffic becomes available in + * the queue a FQDAN (FQ data available notification) will be + * generated to selected DPIO; + * 2 - The destination is a DPCON. The queue is associated with a + * DPCON object for purpose of scheduling between multiple + * queues. The DPCON may be independently configured to + * generate notifications. Not relevant for Tx queues. + * @hold_active: Hold active + */ + struct { + uint32_t id; + enum dpni_dest type; + char hold_active; + char stash_ctrl; + } destination; + uint8_t options; + uint32_t fqid; + uint16_t qdbin; + uint64_t flc; + uint64_t user_context; +}; + +/** + * dpni_set_queue() - Set queue parameters + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @type: Type of queue + * @tc: Traffic class, in range 0 to NUM_TCS - 1 + * @index: Selects the specific queue out of the set allocated for the same + * TC. Value must be in range 0 to NUM_QUEUES - 1 + * @queue: Queue structure + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_queue(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + enum dpni_queue_type type, + uint8_t tc, + uint8_t index, + const struct dpni_queue *queue); + +/** + * dpni_get_queue() - Get queue parameters + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @type: Type of queue + * @tc: Traffic class, in range 0 to NUM_TCS - 1 + * @index: Selects the specific queue out of the set allocated for the same + * TC. Value must be in range 0 to NUM_QUEUES - 1 + * @queue: Queue structure + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_queue(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + enum dpni_queue_type type, + uint8_t tc, + uint8_t index, + struct dpni_queue *queue); + +/** + * dpni_set_tx_confirmation_mode() - Set TX conf mode + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @mode: DPNI confirmation mode type + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + enum dpni_confirmation_mode mode); +struct dpni_statistics { + /** + * Page_0 statistics structure + * @ingress_all_frames: Ingress frame count + * @ingress_all_bytes: Ingress byte count + * @ingress_multicast_frames: Ingress multicast frame count + * @ingress_multicast_bytes: Ingress multicast byte count + * @ingress_broadcast_frames: Ingress broadcast frame count + * @ingress_broadcast_bytes: Ingress broadcast byte count + * + * Page_1 statistics structure + * @egress_all_frames: Egress frame count + * @egress_all_bytes: Egress byte count + * @egress_multicast_frames: Egress multicast frame count + * @egress_multicast_bytes: Egress multicast byte count + * @egress_broadcast_frames: Egress broadcast frame count + * @egress_broadcast_bytes: Egress broadcast byte count + * + * Page_2 statistics structure + * @ingress_filtered_frames: Ingress filtered frame count + * @ingress_discarded_frames: Ingress discarded frame count + * @ingress_nobuffer_discards: Ingress discarded frame count due to + * lack of buffers. + * @egress_discarded_frames: Egress discarded frame count + * @egress_confirmed_frames: Egress confirmed frame count + */ + + uint64_t counter0; + uint64_t counter1; + uint64_t counter2; + uint64_t counter3; + uint64_t counter4; + uint64_t counter5; + uint64_t counter6; +}; + +/** + * dpni_get_statistics() - Get DPNI statistics + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @page: Selects the statistics page to retrieve, see DPNI_GET_STATISTICS + * output. Pages are numbered 0 to 2. + * @stat: Structure containing the statistics + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_statistics(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t page, + struct dpni_statistics *stat); + +/** + * dpni_reset_statistics() - Clears DPNI statistics + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_reset_statistics(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); +#endif /* _FSL_DPNI_H */ diff --git a/roms/u-boot/include/fsl-mc/fsl_dprc.h b/roms/u-boot/include/fsl-mc/fsl_dprc.h new file mode 100644 index 000000000..950ecb075 --- /dev/null +++ b/roms/u-boot/include/fsl-mc/fsl_dprc.h @@ -0,0 +1,957 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale Layerscape MC I/O wrapper + * + * Copyright 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ +#ifndef _FSL_DPRC_H +#define _FSL_DPRC_H + +/* DPRC Version */ +#define DPRC_VER_MAJOR 6 +#define DPRC_VER_MINOR 1 + +/* Command IDs */ +#define DPRC_CMDID_CLOSE 0x8001 +#define DPRC_CMDID_OPEN 0x8051 +#define DPRC_CMDID_CREATE 0x9051 + +#define DPRC_CMDID_GET_ATTR 0x0041 +#define DPRC_CMDID_RESET_CONT 0x0051 +#define DPRC_CMDID_GET_API_VERSION 0xa051 + +#define DPRC_CMDID_CREATE_CONT 0x1511 +#define DPRC_CMDID_DESTROY_CONT 0x1521 +#define DPRC_CMDID_GET_CONT_ID 0x8301 +#define DPRC_CMDID_GET_OBJ_COUNT 0x1591 +#define DPRC_CMDID_GET_OBJ 0x15A1 +#define DPRC_CMDID_GET_RES_COUNT 0x15B1 +#define DPRC_CMDID_GET_RES_IDS 0x15C1 +#define DPRC_CMDID_GET_OBJ_REG 0x15E1 + +#define DPRC_CMDID_CONNECT 0x1671 +#define DPRC_CMDID_DISCONNECT 0x1681 +#define DPRC_CMDID_GET_CONNECTION 0x16C1 + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_CONTAINER_ID(cmd, container_id) \ + MC_RSP_OP(cmd, 0, 0, 32, int, container_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_OPEN(cmd, container_id) \ + MC_CMD_OP(cmd, 0, 0, 32, int, container_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_CREATE_CONTAINER(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->icid); \ + MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->options); \ + MC_CMD_OP(cmd, 1, 32, 32, int, cfg->portal_id); \ + MC_CMD_OP(cmd, 2, 0, 8, char, cfg->label[0]);\ + MC_CMD_OP(cmd, 2, 8, 8, char, cfg->label[1]);\ + MC_CMD_OP(cmd, 2, 16, 8, char, cfg->label[2]);\ + MC_CMD_OP(cmd, 2, 24, 8, char, cfg->label[3]);\ + MC_CMD_OP(cmd, 2, 32, 8, char, cfg->label[4]);\ + MC_CMD_OP(cmd, 2, 40, 8, char, cfg->label[5]);\ + MC_CMD_OP(cmd, 2, 48, 8, char, cfg->label[6]);\ + MC_CMD_OP(cmd, 2, 56, 8, char, cfg->label[7]);\ + MC_CMD_OP(cmd, 3, 0, 8, char, cfg->label[8]);\ + MC_CMD_OP(cmd, 3, 8, 8, char, cfg->label[9]);\ + MC_CMD_OP(cmd, 3, 16, 8, char, cfg->label[10]);\ + MC_CMD_OP(cmd, 3, 24, 8, char, cfg->label[11]);\ + MC_CMD_OP(cmd, 3, 32, 8, char, cfg->label[12]);\ + MC_CMD_OP(cmd, 3, 40, 8, char, cfg->label[13]);\ + MC_CMD_OP(cmd, 3, 48, 8, char, cfg->label[14]);\ + MC_CMD_OP(cmd, 3, 56, 8, char, cfg->label[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_CREATE_CONTAINER(cmd, child_container_id, child_portal_offset)\ +do { \ + MC_RSP_OP(cmd, 1, 0, 32, int, child_container_id); \ + MC_RSP_OP(cmd, 2, 0, 64, uint64_t, child_portal_offset);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id) \ + MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_RESET_CONTAINER(cmd, child_container_id) \ + MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_ATTRIBUTES(cmd, attr) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 32, int, attr->container_id); \ + MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->icid); \ + MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->options);\ + MC_RSP_OP(cmd, 1, 32, 32, int, attr->portal_id); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_OBJ_COUNT(cmd, obj_count) \ + MC_RSP_OP(cmd, 0, 32, 32, int, obj_count) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_GET_OBJ(cmd, obj_index) \ + MC_CMD_OP(cmd, 0, 0, 32, int, obj_index) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_OBJ(cmd, obj_desc) \ +do { \ + MC_RSP_OP(cmd, 0, 32, 32, int, obj_desc->id); \ + MC_RSP_OP(cmd, 1, 0, 16, uint16_t, obj_desc->vendor); \ + MC_RSP_OP(cmd, 1, 16, 8, uint8_t, obj_desc->irq_count); \ + MC_RSP_OP(cmd, 1, 24, 8, uint8_t, obj_desc->region_count); \ + MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\ + MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\ + MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\ + MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \ + MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\ + MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\ + MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\ + MC_RSP_OP(cmd, 3, 24, 8, char, obj_desc->type[3]);\ + MC_RSP_OP(cmd, 3, 32, 8, char, obj_desc->type[4]);\ + MC_RSP_OP(cmd, 3, 40, 8, char, obj_desc->type[5]);\ + MC_RSP_OP(cmd, 3, 48, 8, char, obj_desc->type[6]);\ + MC_RSP_OP(cmd, 3, 56, 8, char, obj_desc->type[7]);\ + MC_RSP_OP(cmd, 4, 0, 8, char, obj_desc->type[8]);\ + MC_RSP_OP(cmd, 4, 8, 8, char, obj_desc->type[9]);\ + MC_RSP_OP(cmd, 4, 16, 8, char, obj_desc->type[10]);\ + MC_RSP_OP(cmd, 4, 24, 8, char, obj_desc->type[11]);\ + MC_RSP_OP(cmd, 4, 32, 8, char, obj_desc->type[12]);\ + MC_RSP_OP(cmd, 4, 40, 8, char, obj_desc->type[13]);\ + MC_RSP_OP(cmd, 4, 48, 8, char, obj_desc->type[14]);\ + MC_RSP_OP(cmd, 4, 56, 8, char, obj_desc->type[15]);\ + MC_RSP_OP(cmd, 5, 0, 8, char, obj_desc->label[0]);\ + MC_RSP_OP(cmd, 5, 8, 8, char, obj_desc->label[1]);\ + MC_RSP_OP(cmd, 5, 16, 8, char, obj_desc->label[2]);\ + MC_RSP_OP(cmd, 5, 24, 8, char, obj_desc->label[3]);\ + MC_RSP_OP(cmd, 5, 32, 8, char, obj_desc->label[4]);\ + MC_RSP_OP(cmd, 5, 40, 8, char, obj_desc->label[5]);\ + MC_RSP_OP(cmd, 5, 48, 8, char, obj_desc->label[6]);\ + MC_RSP_OP(cmd, 5, 56, 8, char, obj_desc->label[7]);\ + MC_RSP_OP(cmd, 6, 0, 8, char, obj_desc->label[8]);\ + MC_RSP_OP(cmd, 6, 8, 8, char, obj_desc->label[9]);\ + MC_RSP_OP(cmd, 6, 16, 8, char, obj_desc->label[10]);\ + MC_RSP_OP(cmd, 6, 24, 8, char, obj_desc->label[11]);\ + MC_RSP_OP(cmd, 6, 32, 8, char, obj_desc->label[12]);\ + MC_RSP_OP(cmd, 6, 40, 8, char, obj_desc->label[13]);\ + MC_RSP_OP(cmd, 6, 48, 8, char, obj_desc->label[14]);\ + MC_RSP_OP(cmd, 6, 56, 8, char, obj_desc->label[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_GET_OBJ_DESC(cmd, obj_type, obj_id) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, obj_id);\ + MC_CMD_OP(cmd, 1, 0, 8, char, obj_type[0]);\ + MC_CMD_OP(cmd, 1, 8, 8, char, obj_type[1]);\ + MC_CMD_OP(cmd, 1, 16, 8, char, obj_type[2]);\ + MC_CMD_OP(cmd, 1, 24, 8, char, obj_type[3]);\ + MC_CMD_OP(cmd, 1, 32, 8, char, obj_type[4]);\ + MC_CMD_OP(cmd, 1, 40, 8, char, obj_type[5]);\ + MC_CMD_OP(cmd, 1, 48, 8, char, obj_type[6]);\ + MC_CMD_OP(cmd, 1, 56, 8, char, obj_type[7]);\ + MC_CMD_OP(cmd, 2, 0, 8, char, obj_type[8]);\ + MC_CMD_OP(cmd, 2, 8, 8, char, obj_type[9]);\ + MC_CMD_OP(cmd, 2, 16, 8, char, obj_type[10]);\ + MC_CMD_OP(cmd, 2, 24, 8, char, obj_type[11]);\ + MC_CMD_OP(cmd, 2, 32, 8, char, obj_type[12]);\ + MC_CMD_OP(cmd, 2, 40, 8, char, obj_type[13]);\ + MC_CMD_OP(cmd, 2, 48, 8, char, obj_type[14]);\ + MC_CMD_OP(cmd, 2, 56, 8, char, obj_type[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_OBJ_DESC(cmd, obj_desc) \ +do { \ + MC_RSP_OP(cmd, 0, 32, 32, int, obj_desc->id); \ + MC_RSP_OP(cmd, 1, 0, 16, uint16_t, obj_desc->vendor); \ + MC_RSP_OP(cmd, 1, 16, 8, uint8_t, obj_desc->irq_count); \ + MC_RSP_OP(cmd, 1, 24, 8, uint8_t, obj_desc->region_count); \ + MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\ + MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\ + MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\ + MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \ + MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\ + MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\ + MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\ + MC_RSP_OP(cmd, 3, 24, 8, char, obj_desc->type[3]);\ + MC_RSP_OP(cmd, 3, 32, 8, char, obj_desc->type[4]);\ + MC_RSP_OP(cmd, 3, 40, 8, char, obj_desc->type[5]);\ + MC_RSP_OP(cmd, 3, 48, 8, char, obj_desc->type[6]);\ + MC_RSP_OP(cmd, 3, 56, 8, char, obj_desc->type[7]);\ + MC_RSP_OP(cmd, 4, 0, 8, char, obj_desc->type[8]);\ + MC_RSP_OP(cmd, 4, 8, 8, char, obj_desc->type[9]);\ + MC_RSP_OP(cmd, 4, 16, 8, char, obj_desc->type[10]);\ + MC_RSP_OP(cmd, 4, 24, 8, char, obj_desc->type[11]);\ + MC_RSP_OP(cmd, 4, 32, 8, char, obj_desc->type[12]);\ + MC_RSP_OP(cmd, 4, 40, 8, char, obj_desc->type[13]);\ + MC_RSP_OP(cmd, 4, 48, 8, char, obj_desc->type[14]);\ + MC_RSP_OP(cmd, 4, 56, 8, char, obj_desc->type[15]);\ + MC_RSP_OP(cmd, 5, 0, 8, char, obj_desc->label[0]);\ + MC_RSP_OP(cmd, 5, 8, 8, char, obj_desc->label[1]);\ + MC_RSP_OP(cmd, 5, 16, 8, char, obj_desc->label[2]);\ + MC_RSP_OP(cmd, 5, 24, 8, char, obj_desc->label[3]);\ + MC_RSP_OP(cmd, 5, 32, 8, char, obj_desc->label[4]);\ + MC_RSP_OP(cmd, 5, 40, 8, char, obj_desc->label[5]);\ + MC_RSP_OP(cmd, 5, 48, 8, char, obj_desc->label[6]);\ + MC_RSP_OP(cmd, 5, 56, 8, char, obj_desc->label[7]);\ + MC_RSP_OP(cmd, 6, 0, 8, char, obj_desc->label[8]);\ + MC_RSP_OP(cmd, 6, 8, 8, char, obj_desc->label[9]);\ + MC_RSP_OP(cmd, 6, 16, 8, char, obj_desc->label[10]);\ + MC_RSP_OP(cmd, 6, 24, 8, char, obj_desc->label[11]);\ + MC_RSP_OP(cmd, 6, 32, 8, char, obj_desc->label[12]);\ + MC_RSP_OP(cmd, 6, 40, 8, char, obj_desc->label[13]);\ + MC_RSP_OP(cmd, 6, 48, 8, char, obj_desc->label[14]);\ + MC_RSP_OP(cmd, 6, 56, 8, char, obj_desc->label[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_GET_RES_COUNT(cmd, type) \ +do { \ + MC_CMD_OP(cmd, 1, 0, 8, char, type[0]);\ + MC_CMD_OP(cmd, 1, 8, 8, char, type[1]);\ + MC_CMD_OP(cmd, 1, 16, 8, char, type[2]);\ + MC_CMD_OP(cmd, 1, 24, 8, char, type[3]);\ + MC_CMD_OP(cmd, 1, 32, 8, char, type[4]);\ + MC_CMD_OP(cmd, 1, 40, 8, char, type[5]);\ + MC_CMD_OP(cmd, 1, 48, 8, char, type[6]);\ + MC_CMD_OP(cmd, 1, 56, 8, char, type[7]);\ + MC_CMD_OP(cmd, 2, 0, 8, char, type[8]);\ + MC_CMD_OP(cmd, 2, 8, 8, char, type[9]);\ + MC_CMD_OP(cmd, 2, 16, 8, char, type[10]);\ + MC_CMD_OP(cmd, 2, 24, 8, char, type[11]);\ + MC_CMD_OP(cmd, 2, 32, 8, char, type[12]);\ + MC_CMD_OP(cmd, 2, 40, 8, char, type[13]);\ + MC_CMD_OP(cmd, 2, 48, 8, char, type[14]);\ + MC_CMD_OP(cmd, 2, 56, 8, char, type[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_RES_COUNT(cmd, res_count) \ + MC_RSP_OP(cmd, 0, 0, 32, int, res_count) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_GET_RES_IDS(cmd, range_desc, type) \ +do { \ + MC_CMD_OP(cmd, 0, 42, 7, enum dprc_iter_status, \ + range_desc->iter_status); \ + MC_CMD_OP(cmd, 1, 0, 32, int, range_desc->base_id); \ + MC_CMD_OP(cmd, 1, 32, 32, int, range_desc->last_id);\ + MC_CMD_OP(cmd, 2, 0, 8, char, type[0]);\ + MC_CMD_OP(cmd, 2, 8, 8, char, type[1]);\ + MC_CMD_OP(cmd, 2, 16, 8, char, type[2]);\ + MC_CMD_OP(cmd, 2, 24, 8, char, type[3]);\ + MC_CMD_OP(cmd, 2, 32, 8, char, type[4]);\ + MC_CMD_OP(cmd, 2, 40, 8, char, type[5]);\ + MC_CMD_OP(cmd, 2, 48, 8, char, type[6]);\ + MC_CMD_OP(cmd, 2, 56, 8, char, type[7]);\ + MC_CMD_OP(cmd, 3, 0, 8, char, type[8]);\ + MC_CMD_OP(cmd, 3, 8, 8, char, type[9]);\ + MC_CMD_OP(cmd, 3, 16, 8, char, type[10]);\ + MC_CMD_OP(cmd, 3, 24, 8, char, type[11]);\ + MC_CMD_OP(cmd, 3, 32, 8, char, type[12]);\ + MC_CMD_OP(cmd, 3, 40, 8, char, type[13]);\ + MC_CMD_OP(cmd, 3, 48, 8, char, type[14]);\ + MC_CMD_OP(cmd, 3, 56, 8, char, type[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_RES_IDS(cmd, range_desc) \ +do { \ + MC_RSP_OP(cmd, 0, 42, 7, enum dprc_iter_status, \ + range_desc->iter_status);\ + MC_RSP_OP(cmd, 1, 0, 32, int, range_desc->base_id); \ + MC_RSP_OP(cmd, 1, 32, 32, int, range_desc->last_id);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_GET_OBJ_REGION(cmd, obj_type, obj_id, region_index) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, obj_id); \ + MC_CMD_OP(cmd, 0, 48, 8, uint8_t, region_index);\ + MC_CMD_OP(cmd, 3, 0, 8, char, obj_type[0]);\ + MC_CMD_OP(cmd, 3, 8, 8, char, obj_type[1]);\ + MC_CMD_OP(cmd, 3, 16, 8, char, obj_type[2]);\ + MC_CMD_OP(cmd, 3, 24, 8, char, obj_type[3]);\ + MC_CMD_OP(cmd, 3, 32, 8, char, obj_type[4]);\ + MC_CMD_OP(cmd, 3, 40, 8, char, obj_type[5]);\ + MC_CMD_OP(cmd, 3, 48, 8, char, obj_type[6]);\ + MC_CMD_OP(cmd, 3, 56, 8, char, obj_type[7]);\ + MC_CMD_OP(cmd, 4, 0, 8, char, obj_type[8]);\ + MC_CMD_OP(cmd, 4, 8, 8, char, obj_type[9]);\ + MC_CMD_OP(cmd, 4, 16, 8, char, obj_type[10]);\ + MC_CMD_OP(cmd, 4, 24, 8, char, obj_type[11]);\ + MC_CMD_OP(cmd, 4, 32, 8, char, obj_type[12]);\ + MC_CMD_OP(cmd, 4, 40, 8, char, obj_type[13]);\ + MC_CMD_OP(cmd, 4, 48, 8, char, obj_type[14]);\ + MC_CMD_OP(cmd, 4, 56, 8, char, obj_type[15]);\ +} while (0) + +/* param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_OBJ_REGION(cmd, region_desc) \ +do { \ + MC_RSP_OP(cmd, 1, 0, 32, uint32_t, region_desc->base_offset);\ + MC_RSP_OP(cmd, 2, 0, 32, uint32_t, region_desc->size); \ + MC_RSP_OP(cmd, 2, 32, 4, enum dprc_region_type, region_desc->type);\ + MC_RSP_OP(cmd, 3, 0, 32, uint32_t, region_desc->flags);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_SET_OBJ_LABEL(cmd, obj_type, obj_id, label) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, obj_id); \ + MC_CMD_OP(cmd, 1, 0, 8, char, label[0]);\ + MC_CMD_OP(cmd, 1, 8, 8, char, label[1]);\ + MC_CMD_OP(cmd, 1, 16, 8, char, label[2]);\ + MC_CMD_OP(cmd, 1, 24, 8, char, label[3]);\ + MC_CMD_OP(cmd, 1, 32, 8, char, label[4]);\ + MC_CMD_OP(cmd, 1, 40, 8, char, label[5]);\ + MC_CMD_OP(cmd, 1, 48, 8, char, label[6]);\ + MC_CMD_OP(cmd, 1, 56, 8, char, label[7]);\ + MC_CMD_OP(cmd, 2, 0, 8, char, label[8]);\ + MC_CMD_OP(cmd, 2, 8, 8, char, label[9]);\ + MC_CMD_OP(cmd, 2, 16, 8, char, label[10]);\ + MC_CMD_OP(cmd, 2, 24, 8, char, label[11]);\ + MC_CMD_OP(cmd, 2, 32, 8, char, label[12]);\ + MC_CMD_OP(cmd, 2, 40, 8, char, label[13]);\ + MC_CMD_OP(cmd, 2, 48, 8, char, label[14]);\ + MC_CMD_OP(cmd, 2, 56, 8, char, label[15]);\ + MC_CMD_OP(cmd, 3, 0, 8, char, obj_type[0]);\ + MC_CMD_OP(cmd, 3, 8, 8, char, obj_type[1]);\ + MC_CMD_OP(cmd, 3, 16, 8, char, obj_type[2]);\ + MC_CMD_OP(cmd, 3, 24, 8, char, obj_type[3]);\ + MC_CMD_OP(cmd, 3, 32, 8, char, obj_type[4]);\ + MC_CMD_OP(cmd, 3, 40, 8, char, obj_type[5]);\ + MC_CMD_OP(cmd, 3, 48, 8, char, obj_type[6]);\ + MC_CMD_OP(cmd, 3, 56, 8, char, obj_type[7]);\ + MC_CMD_OP(cmd, 4, 0, 8, char, obj_type[8]);\ + MC_CMD_OP(cmd, 4, 8, 8, char, obj_type[9]);\ + MC_CMD_OP(cmd, 4, 16, 8, char, obj_type[10]);\ + MC_CMD_OP(cmd, 4, 24, 8, char, obj_type[11]);\ + MC_CMD_OP(cmd, 4, 32, 8, char, obj_type[12]);\ + MC_CMD_OP(cmd, 4, 40, 8, char, obj_type[13]);\ + MC_CMD_OP(cmd, 4, 48, 8, char, obj_type[14]);\ + MC_CMD_OP(cmd, 4, 56, 8, char, obj_type[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \ + MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \ + MC_CMD_OP(cmd, 1, 0, 32, int, endpoint2->id); \ + MC_CMD_OP(cmd, 1, 32, 32, int, endpoint2->if_id); \ + MC_CMD_OP(cmd, 2, 0, 8, char, endpoint1->type[0]); \ + MC_CMD_OP(cmd, 2, 8, 8, char, endpoint1->type[1]); \ + MC_CMD_OP(cmd, 2, 16, 8, char, endpoint1->type[2]); \ + MC_CMD_OP(cmd, 2, 24, 8, char, endpoint1->type[3]); \ + MC_CMD_OP(cmd, 2, 32, 8, char, endpoint1->type[4]); \ + MC_CMD_OP(cmd, 2, 40, 8, char, endpoint1->type[5]); \ + MC_CMD_OP(cmd, 2, 48, 8, char, endpoint1->type[6]); \ + MC_CMD_OP(cmd, 2, 56, 8, char, endpoint1->type[7]); \ + MC_CMD_OP(cmd, 3, 0, 8, char, endpoint1->type[8]); \ + MC_CMD_OP(cmd, 3, 8, 8, char, endpoint1->type[9]); \ + MC_CMD_OP(cmd, 3, 16, 8, char, endpoint1->type[10]); \ + MC_CMD_OP(cmd, 3, 24, 8, char, endpoint1->type[11]); \ + MC_CMD_OP(cmd, 3, 32, 8, char, endpoint1->type[12]); \ + MC_CMD_OP(cmd, 3, 40, 8, char, endpoint1->type[13]); \ + MC_CMD_OP(cmd, 3, 48, 8, char, endpoint1->type[14]); \ + MC_CMD_OP(cmd, 3, 56, 8, char, endpoint1->type[15]); \ + MC_CMD_OP(cmd, 4, 0, 32, uint32_t, cfg->max_rate); \ + MC_CMD_OP(cmd, 4, 32, 32, uint32_t, cfg->committed_rate); \ + MC_CMD_OP(cmd, 5, 0, 8, char, endpoint2->type[0]); \ + MC_CMD_OP(cmd, 5, 8, 8, char, endpoint2->type[1]); \ + MC_CMD_OP(cmd, 5, 16, 8, char, endpoint2->type[2]); \ + MC_CMD_OP(cmd, 5, 24, 8, char, endpoint2->type[3]); \ + MC_CMD_OP(cmd, 5, 32, 8, char, endpoint2->type[4]); \ + MC_CMD_OP(cmd, 5, 40, 8, char, endpoint2->type[5]); \ + MC_CMD_OP(cmd, 5, 48, 8, char, endpoint2->type[6]); \ + MC_CMD_OP(cmd, 5, 56, 8, char, endpoint2->type[7]); \ + MC_CMD_OP(cmd, 6, 0, 8, char, endpoint2->type[8]); \ + MC_CMD_OP(cmd, 6, 8, 8, char, endpoint2->type[9]); \ + MC_CMD_OP(cmd, 6, 16, 8, char, endpoint2->type[10]); \ + MC_CMD_OP(cmd, 6, 24, 8, char, endpoint2->type[11]); \ + MC_CMD_OP(cmd, 6, 32, 8, char, endpoint2->type[12]); \ + MC_CMD_OP(cmd, 6, 40, 8, char, endpoint2->type[13]); \ + MC_CMD_OP(cmd, 6, 48, 8, char, endpoint2->type[14]); \ + MC_CMD_OP(cmd, 6, 56, 8, char, endpoint2->type[15]); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_DISCONNECT(cmd, endpoint) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, endpoint->id); \ + MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint->if_id); \ + MC_CMD_OP(cmd, 1, 0, 8, char, endpoint->type[0]); \ + MC_CMD_OP(cmd, 1, 8, 8, char, endpoint->type[1]); \ + MC_CMD_OP(cmd, 1, 16, 8, char, endpoint->type[2]); \ + MC_CMD_OP(cmd, 1, 24, 8, char, endpoint->type[3]); \ + MC_CMD_OP(cmd, 1, 32, 8, char, endpoint->type[4]); \ + MC_CMD_OP(cmd, 1, 40, 8, char, endpoint->type[5]); \ + MC_CMD_OP(cmd, 1, 48, 8, char, endpoint->type[6]); \ + MC_CMD_OP(cmd, 1, 56, 8, char, endpoint->type[7]); \ + MC_CMD_OP(cmd, 2, 0, 8, char, endpoint->type[8]); \ + MC_CMD_OP(cmd, 2, 8, 8, char, endpoint->type[9]); \ + MC_CMD_OP(cmd, 2, 16, 8, char, endpoint->type[10]); \ + MC_CMD_OP(cmd, 2, 24, 8, char, endpoint->type[11]); \ + MC_CMD_OP(cmd, 2, 32, 8, char, endpoint->type[12]); \ + MC_CMD_OP(cmd, 2, 40, 8, char, endpoint->type[13]); \ + MC_CMD_OP(cmd, 2, 48, 8, char, endpoint->type[14]); \ + MC_CMD_OP(cmd, 2, 56, 8, char, endpoint->type[15]); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_GET_CONNECTION(cmd, endpoint1) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \ + MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \ + MC_CMD_OP(cmd, 1, 0, 8, char, endpoint1->type[0]); \ + MC_CMD_OP(cmd, 1, 8, 8, char, endpoint1->type[1]); \ + MC_CMD_OP(cmd, 1, 16, 8, char, endpoint1->type[2]); \ + MC_CMD_OP(cmd, 1, 24, 8, char, endpoint1->type[3]); \ + MC_CMD_OP(cmd, 1, 32, 8, char, endpoint1->type[4]); \ + MC_CMD_OP(cmd, 1, 40, 8, char, endpoint1->type[5]); \ + MC_CMD_OP(cmd, 1, 48, 8, char, endpoint1->type[6]); \ + MC_CMD_OP(cmd, 1, 56, 8, char, endpoint1->type[7]); \ + MC_CMD_OP(cmd, 2, 0, 8, char, endpoint1->type[8]); \ + MC_CMD_OP(cmd, 2, 8, 8, char, endpoint1->type[9]); \ + MC_CMD_OP(cmd, 2, 16, 8, char, endpoint1->type[10]); \ + MC_CMD_OP(cmd, 2, 24, 8, char, endpoint1->type[11]); \ + MC_CMD_OP(cmd, 2, 32, 8, char, endpoint1->type[12]); \ + MC_CMD_OP(cmd, 2, 40, 8, char, endpoint1->type[13]); \ + MC_CMD_OP(cmd, 2, 48, 8, char, endpoint1->type[14]); \ + MC_CMD_OP(cmd, 2, 56, 8, char, endpoint1->type[15]); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_CONNECTION(cmd, endpoint2, state) \ +do { \ + MC_RSP_OP(cmd, 3, 0, 32, int, endpoint2->id); \ + MC_RSP_OP(cmd, 3, 32, 16, uint16_t, endpoint2->if_id); \ + MC_RSP_OP(cmd, 4, 0, 8, char, endpoint2->type[0]); \ + MC_RSP_OP(cmd, 4, 8, 8, char, endpoint2->type[1]); \ + MC_RSP_OP(cmd, 4, 16, 8, char, endpoint2->type[2]); \ + MC_RSP_OP(cmd, 4, 24, 8, char, endpoint2->type[3]); \ + MC_RSP_OP(cmd, 4, 32, 8, char, endpoint2->type[4]); \ + MC_RSP_OP(cmd, 4, 40, 8, char, endpoint2->type[5]); \ + MC_RSP_OP(cmd, 4, 48, 8, char, endpoint2->type[6]); \ + MC_RSP_OP(cmd, 4, 56, 8, char, endpoint2->type[7]); \ + MC_RSP_OP(cmd, 5, 0, 8, char, endpoint2->type[8]); \ + MC_RSP_OP(cmd, 5, 8, 8, char, endpoint2->type[9]); \ + MC_RSP_OP(cmd, 5, 16, 8, char, endpoint2->type[10]); \ + MC_RSP_OP(cmd, 5, 24, 8, char, endpoint2->type[11]); \ + MC_RSP_OP(cmd, 5, 32, 8, char, endpoint2->type[12]); \ + MC_RSP_OP(cmd, 5, 40, 8, char, endpoint2->type[13]); \ + MC_RSP_OP(cmd, 5, 48, 8, char, endpoint2->type[14]); \ + MC_RSP_OP(cmd, 5, 56, 8, char, endpoint2->type[15]); \ + MC_RSP_OP(cmd, 6, 0, 32, int, state); \ +} while (0) + +/* Data Path Resource Container API + * Contains DPRC API for managing and querying DPAA resources + */ + +struct fsl_mc_io; + +/** + * Set this value as the icid value in dprc_cfg structure when creating a + * container, in case the ICID is not selected by the user and should be + * allocated by the DPRC from the pool of ICIDs. + */ +#define DPRC_GET_ICID_FROM_POOL (uint16_t)(~(0)) + +/** + * Set this value as the portal_id value in dprc_cfg structure when creating a + * container, in case the portal ID is not specifically selected by the + * user and should be allocated by the DPRC from the pool of portal ids. + */ +#define DPRC_GET_PORTAL_ID_FROM_POOL (int)(~(0)) + +/** + * dprc_get_container_id() - Get container ID associated with a given portal. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @container_id: Requested container ID + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_container_id(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + int *container_id); + +/** + * dprc_open() - Open DPRC object for use + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @container_id: Container ID to open + * @token: Returned token of DPRC object + * + * Return: '0' on Success; Error code otherwise. + * + * @warning Required before any operation on the object. + */ +int dprc_open(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + int container_id, + uint16_t *token); + +/** + * dprc_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_close(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** + * Container general options + * + * These options may be selected at container creation by the container creator + * and can be retrieved using dprc_get_attributes() + */ + +/* Spawn Policy Option allowed - Indicates that the new container is allowed + * to spawn and have its own child containers. + */ +#define DPRC_CFG_OPT_SPAWN_ALLOWED 0x00000001 + +/* General Container allocation policy - Indicates that the new container is + * allowed to allocate requested resources from its parent container; if not + * set, the container is only allowed to use resources in its own pools; Note + * that this is a container's global policy, but the parent container may + * override it and set specific quota per resource type. + */ +#define DPRC_CFG_OPT_ALLOC_ALLOWED 0x00000002 + +/* Object initialization allowed - software context associated with this + * container is allowed to invoke object initialization operations. + */ +#define DPRC_CFG_OPT_OBJ_CREATE_ALLOWED 0x00000004 + +/* Topology change allowed - software context associated with this + * container is allowed to invoke topology operations, such as attach/detach + * of network objects. + */ +#define DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED 0x00000008 + + +/* AIOP - Indicates that container belongs to AIOP. */ +#define DPRC_CFG_OPT_AIOP 0x00000020 + +/* IRQ Config - Indicates that the container allowed to configure its IRQs.*/ +#define DPRC_CFG_OPT_IRQ_CFG_ALLOWED 0x00000040 + +/** + * struct dprc_cfg - Container configuration options + * @icid: Container's ICID; if set to 'DPRC_GET_ICID_FROM_POOL', a free + * ICID value is allocated by the DPRC + * @portal_id: Portal ID; if set to 'DPRC_GET_PORTAL_ID_FROM_POOL', a free + * portal ID is allocated by the DPRC + * @options: Combination of 'DPRC_CFG_OPT_' options + * @label: Object's label + */ +struct dprc_cfg { + uint16_t icid; + int portal_id; + uint64_t options; + char label[16]; +}; + +/** + * dprc_create_container() - Create child container + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @cfg: Child container configuration + * @child_container_id: Returned child container ID + * @child_portal_offset: Returned child portal offset from MC portal base + * + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_create_container(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dprc_cfg *cfg, + int *child_container_id, + uint64_t *child_portal_offset); + +/** + * dprc_destroy_container() - Destroy child container. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @child_container_id: ID of the container to destroy + * + * This function terminates the child container, so following this call the + * child container ID becomes invalid. + * + * Notes: + * - All resources and objects of the destroyed container are returned to the + * parent container or destroyed if were created be the destroyed container. + * - This function destroy all the child containers of the specified + * container prior to destroying the container itself. + * + * warning: Only the parent container is allowed to destroy a child policy + * Container 0 can't be destroyed + * + * Return: '0' on Success; Error code otherwise. + * + */ +int dprc_destroy_container(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + int child_container_id); + +/** + * dprc_reset_container - Reset child container. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @child_container_id: ID of the container to reset + * + * In case a software context crashes or becomes non-responsive, the parent + * may wish to reset its resources container before the software context is + * restarted. + * + * This routine informs all objects assigned to the child container that the + * container is being reset, so they may perform any cleanup operations that are + * needed. All objects handles that were owned by the child container shall be + * closed. + * + * Note that such request may be submitted even if the child software context + * has not crashed, but the resulting object cleanup operations will not be + * aware of that. + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_reset_container(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + int child_container_id); + +/** + * struct dprc_attributes - Container attributes + * @container_id: Container's ID + * @icid: Container's ICID + * @portal_id: Container's portal ID + * @options: Container's options as set at container's creation + * @version: DPRC version + */ +struct dprc_attributes { + int container_id; + uint16_t icid; + int portal_id; + uint64_t options; +}; + +/** + * dprc_get_attributes() - Obtains container attributes + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @attributes: Returned container attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_attributes(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dprc_attributes *attributes); + +/** + * dprc_get_obj_count() - Obtains the number of objects in the DPRC + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @obj_count: Number of objects assigned to the DPRC + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_obj_count(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + int *obj_count); + +/* Objects Attributes Flags */ + +/* Opened state - Indicates that an object is open by at least one owner */ +#define DPRC_OBJ_STATE_OPEN 0x00000001 +/* Plugged state - Indicates that the object is plugged */ +#define DPRC_OBJ_STATE_PLUGGED 0x00000002 + +/** + * Shareability flag - Object flag indicating no memory shareability. + * the object generates memory accesses that are non coherent with other + * masters; + * user is responsible for proper memory handling through IOMMU configuration. + */ +#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001 + +/** + * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj() + * @type: Type of object: NULL terminated string + * @id: ID of logical object resource + * @vendor: Object vendor identifier + * @ver_major: Major version number + * @ver_minor: Minor version number + * @irq_count: Number of interrupts supported by the object + * @region_count: Number of mappable regions supported by the object + * @state: Object state: combination of DPRC_OBJ_STATE_ states + * @label: Object label + * @flags: Object's flags + */ +struct dprc_obj_desc { + char type[16]; + int id; + uint16_t vendor; + uint16_t ver_major; + uint16_t ver_minor; + uint8_t irq_count; + uint8_t region_count; + uint32_t state; + char label[16]; + uint16_t flags; +}; + +/** + * dprc_get_obj() - Get general information on an object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @obj_index: Index of the object to be queried (< obj_count) + * @obj_desc: Returns the requested object descriptor + * + * The object descriptors are retrieved one by one by incrementing + * obj_index up to (not including) the value of obj_count returned + * from dprc_get_obj_count(). dprc_get_obj_count() must + * be called prior to dprc_get_obj(). + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_obj(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + int obj_index, + struct dprc_obj_desc *obj_desc); + +/** + * dprc_get_res_count() - Obtains the number of free resources that are + * assigned to this container, by pool type + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @type: pool type + * @res_count: Returned number of free resources of the given + * resource type that are assigned to this DPRC + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_res_count(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + char *type, + int *res_count); + +/** + * enum dprc_iter_status - Iteration status + * @DPRC_ITER_STATUS_FIRST: Perform first iteration + * @DPRC_ITER_STATUS_MORE: Indicates more/next iteration is needed + * @DPRC_ITER_STATUS_LAST: Indicates last iteration + */ +enum dprc_iter_status { + DPRC_ITER_STATUS_FIRST = 0, + DPRC_ITER_STATUS_MORE = 1, + DPRC_ITER_STATUS_LAST = 2 +}; + +/** + * struct dprc_res_ids_range_desc - Resource ID range descriptor + * @base_id: Base resource ID of this range + * @last_id: Last resource ID of this range + * @iter_status: Iteration status - should be set to DPRC_ITER_STATUS_FIRST at + * first iteration; while the returned marker is DPRC_ITER_STATUS_MORE, + * additional iterations are needed, until the returned marker is + * DPRC_ITER_STATUS_LAST + */ +struct dprc_res_ids_range_desc { + int base_id; + int last_id; + enum dprc_iter_status iter_status; +}; + +/** + * dprc_get_res_ids() - Obtains IDs of free resources in the container + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @type: pool type + * @range_desc: range descriptor + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_res_ids(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + char *type, + struct dprc_res_ids_range_desc *range_desc); + +/* Region flags */ +/* Cacheable - Indicates that region should be mapped as cacheable */ +#define DPRC_REGION_CACHEABLE 0x00000001 + +/** + * enum dprc_region_type - Region type + * @DPRC_REGION_TYPE_MC_PORTAL: MC portal region + * @DPRC_REGION_TYPE_QBMAN_PORTAL: Qbman portal region + */ +enum dprc_region_type { + DPRC_REGION_TYPE_MC_PORTAL, + DPRC_REGION_TYPE_QBMAN_PORTAL +}; + +/** + * struct dprc_region_desc - Mappable region descriptor + * @base_offset: Region offset from region's base address. + * For DPMCP and DPRC objects, region base is offset from SoC MC portals + * base address; For DPIO, region base is offset from SoC QMan portals + * base address + * @size: Region size (in bytes) + * @flags: Region attributes + * @type: Portal region type + */ +struct dprc_region_desc { + uint32_t base_offset; + uint32_t size; + uint32_t flags; + enum dprc_region_type type; +}; + +/** + * dprc_get_obj_region() - Get region information for a specified object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @obj_type: Object type as returned in dprc_get_obj() + * @obj_id: Unique object instance as returned in dprc_get_obj() + * @region_index: The specific region to query + * @region_desc: Returns the requested region descriptor + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_obj_region(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + char *obj_type, + int obj_id, + uint8_t region_index, + struct dprc_region_desc *region_desc); +/** + * struct dprc_endpoint - Endpoint description for link connect/disconnect + * operations + * @type: Endpoint object type: NULL terminated string + * @id: Endpoint object ID + * @if_id: Interface ID; should be set for endpoints with multiple + * interfaces ("dpsw", "dpdmux"); for others, always set to 0 + */ +struct dprc_endpoint { + char type[16]; + int id; + uint16_t if_id; +}; + +/** + * struct dprc_connection_cfg - Connection configuration. + * Used for virtual connections only + * @committed_rate: Committed rate (Mbits/s) + * @max_rate: Maximum rate (Mbits/s) + */ +struct dprc_connection_cfg { + uint32_t committed_rate; + uint32_t max_rate; +}; + +/** + * dprc_connect() - Connect two endpoints to create a network link between them + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @endpoint1: Endpoint 1 configuration parameters + * @endpoint2: Endpoint 2 configuration parameters + * @cfg: Connection configuration. The connection configuration is ignored for + * connections made to DPMAC objects, where rate is retrieved from the + * MAC configuration. + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_connect(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dprc_endpoint *endpoint1, + const struct dprc_endpoint *endpoint2, + const struct dprc_connection_cfg *cfg); + +/** + * dprc_disconnect() - Disconnect one endpoint to remove its network connection + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @endpoint: Endpoint configuration parameters + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_disconnect(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dprc_endpoint *endpoint); + +/** +* dprc_get_connection() - Get connected endpoint and link status if connection +* exists. +* @mc_io: Pointer to MC portal's I/O object +* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' +* @token: Token of DPRC object +* @endpoint1: Endpoint 1 configuration parameters +* @endpoint2: Returned endpoint 2 configuration parameters +* @state: Returned link state: +* 1 - link is up; +* 0 - link is down; +* -1 - no connection (endpoint2 information is irrelevant) +* +* Return: '0' on Success; -ENAVAIL if connection does not exist. +*/ +int dprc_get_connection(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dprc_endpoint *endpoint1, + struct dprc_endpoint *endpoint2, + int *state); + +/** + * dprc_get_api_version - Retrieve DPRC Major and Minor version info. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: DPRC major version + * @minor_ver: DPRC minor version + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_api_version(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 *major_ver, + u16 *minor_ver); + +#endif /* _FSL_DPRC_H */ diff --git a/roms/u-boot/include/fsl-mc/fsl_dpsparser.h b/roms/u-boot/include/fsl-mc/fsl_dpsparser.h new file mode 100644 index 000000000..48fb49505 --- /dev/null +++ b/roms/u-boot/include/fsl-mc/fsl_dpsparser.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Data Path Soft Parser API + * + * Copyright 2018 NXP + */ +#ifndef _FSL_DPSPARSER_H +#define _FSL_DPSPARSER_H + +/* DPSPARSER last supported API version */ +#define DPSPARSER_VER_MAJOR 1 +#define DPSPARSER_VER_MINOR 0 + +/* Command IDs */ +#define DPSPARSER_CMDID_CLOSE 0x8001 +#define DPSPARSER_CMDID_OPEN 0x8111 +#define DPSPARSER_CMDID_CREATE 0x9111 +#define DPSPARSER_CMDID_DESTROY 0x9911 +#define DPSPARSER_CMDID_GET_API_VERSION 0xa111 + +#define DPSPARSER_CMDID_APPLY_SPB 0x1181 + +/* cmd, param, offset, width, type, arg_name */ +#define DPSPARSER_CMD_BLOB_SET_ADDR(cmd, addr) \ + MC_CMD_OP(cmd, 0, 0, 64, u64, addr) + +/* cmd, param, offset, width, type, arg_name */ +#define DPSPARSER_CMD_BLOB_REPORT_ERROR(cmd, err) \ + MC_RSP_OP(cmd, 0, 0, 16, u16, err) + +/* Data Path Soft Parser API + * Contains initialization APIs and runtime control APIs for DPSPARSER + */ + +struct fsl_mc_io; + +/* MC Unknown error: */ +#define MC_ERROR_MSG_SPB_UNKNOWN "Unknown MC error\n" + +/* MC Error messages (in order for each error code defined above): */ +#define MC_ERROR_MSG_APPLY_SPB \ +{ \ + "OK\n", \ + "BLOB : Magic number does not match\n", \ + "BLOB : Version does not match MC API version\n", \ + "BLOB : IP revision does not match HW revision\n", \ + "BLOB : Blob length is not a multiple of 4\n", \ + "BLOB : Invalid length detected\n", \ + "BLOB : Name length < 0 in 'blob-name'\n", \ + "BLOB : Name length not a 4 multiple in 'blob-name'\n", \ + "BLOB : No target HW parser selected\n", \ + "BLOB : SP size is negative\n", \ + "BLOB : Size is zero\n", \ + "BLOB : Number of protocols is negative\n", \ + "BLOB : Zero protocols\n", \ + "BLOB : Protocol name is null\n", \ + "BLOB : SP 'seq-start' is not in [0x40, 0xffc0) range\n", \ + "BLOB : Invalid base protocol\n", \ + "BLOB : Invalid parameters section\n", \ + "BLOB : Invalid parameter\n", \ + "BLOB : Invalid parameter configuration\n", \ + "BLOB : Not aligned value\n", \ + "BLOB : Invalid section TAG detected\n", \ + "BLOB : Section size is zero\n", \ + "BLOB : Section size not a 4 multiple\n", \ + "BLOB : Section size is too big\n", \ + "BLOB : No 'bytecode' section before\n", \ + "BLOB : No 'sp-protocols' section before\n", \ + "BLOB : No 'bytecode' section defined\n", \ + "BLOB : No 'sp-protocols' section defined\n", \ + "BLOB : Soft Parser BLOB parsing : Error detected\n", \ + "apply spb : Soft Parser BLOB is already applied\n", \ + "apply spb : BLOB address is not set\n", \ + "BLOB : SP parameter offset is not a 4 multiple\n", \ + "BLOB : SP parameter offset can't be less than 0x40\n", \ + "BLOB : Bytecode size is not a 4 multiple\n", \ + "BLOB : Bytecode size cannot be zero\n", \ + "BLOB : Bytecode can't overwrite the 0xFFE address\n", \ + "BLOB : No hardware parser selected as target\n", \ + "BLOB : Bytecode overlap detected\n", \ + "BLOB : No parser support\n", \ + "BLOB : Too many bytecode sections on WRIOP ingress\n", \ + "BLOB : Too many bytecode sections on WRIOP egress\n", \ + "BLOB : Too many bytecode sections on AIOP\n", \ + "BLOB : Duplicated protocol is already registered\n", \ + "BLOB : Maximum number of allowed protocols was exceeded\n", \ + "BLOB : Protocols limit exceeded\n", \ + "BLOB : Protocol is linked twice\n", \ + "BLOB : Soft parser is linked twice\n", \ + "BLOB : Parameter offset exceeds the maximum parameters limit\n", \ + "BLOB : Parameter size can't be 0 or greater than 64\n", \ + "BLOB : Parameter offset plus size exceeds the maximum limit\n", \ + "BLOB : Parameters number exceeds the maximum limit\n", \ + "BLOB : Duplicated parameter name\n", \ + "BLOB : Parameters overlapped detected\n", \ + "apply spb : No dpsparser handle.\n", \ + \ + MC_ERROR_MSG_SPB_UNKNOWN, \ + NULL, \ +} + +/** + * dpsparser_open() - Open a control session for the specified object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpsparser_create function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpsparser_open(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 *token); + +/** + * dpsparser_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSPARSER object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpsparser_close(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token); + +/** + * dpsparser_create() - Create the DPSPARSER object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Returned token; use in subsequent API calls + * + * Create the DPSPARSER object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpsparser_open function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpsparser_create(struct fsl_mc_io *mc_io, + u16 token, + u32 cmd_flags, + u32 *obj_id); + +/** + * dpsparser_destroy() - Destroy the DPSPARSER object and release all its + * resources. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSPARSER object + * + * Return: '0' on Success; error code otherwise. + */ +int dpsparser_destroy(struct fsl_mc_io *mc_io, + u16 token, + u32 cmd_flags, + u32 obj_id); + +/** + * dpsparser_apply_spb() - Applies the Soft Parser Blob loaded at specified + * address. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSPARSER object + * @blob_addr: Blob loading address + * @error: Error reported by MC related to SP Blob parsing and apply + * + * Return: '0' on Success; error code otherwise. + */ +int dpsparser_apply_spb(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u64 blob_addr, + u16 *error); + +/** + * dpsparser_get_api_version - Retrieve DPSPARSER Major and Minor version info. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: DPSPARSER major version + * @minor_ver: DPSPARSER minor version + * + * Return: '0' on Success; Error code otherwise. + */ +int dpsparser_get_api_version(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 *major_ver, + u16 *minor_ver); + +#endif /* _FSL_DPSPARSER_H */ diff --git a/roms/u-boot/include/fsl-mc/fsl_mc.h b/roms/u-boot/include/fsl-mc/fsl_mc.h new file mode 100644 index 000000000..a8b072ad7 --- /dev/null +++ b/roms/u-boot/include/fsl-mc/fsl_mc.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Freescale Semiconductor + */ + +#ifndef __FSL_MC_H__ +#define __FSL_MC_H__ + +#include +#include + +#define MC_CCSR_BASE_ADDR \ + ((struct mc_ccsr_registers __iomem *)0x8340000) + +#define GCR1_P1_STOP BIT(31) +#define GCR1_P2_STOP BIT(30) +#define GCR1_P1_DE_RST BIT(23) +#define GCR1_P2_DE_RST BIT(22) +#define GCR1_M1_DE_RST BIT(15) +#define GCR1_M2_DE_RST BIT(14) +#define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST) +#define GSR_FS_MASK 0x3fffffff + +#define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000) +#define SOC_QBMAN_PORTALS_BASE_ADDR ((void __iomem *)0x000818000000) +#define SOC_MC_PORTAL_STRIDE 0x10000 + +#define SOC_MC_PORTAL_ADDR(_portal_id) \ + ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \ + (_portal_id) * SOC_MC_PORTAL_STRIDE)) + +#define MC_PORTAL_OFFSET_TO_PORTAL_ID(_portal_offset) \ + ((_portal_offset) / SOC_MC_PORTAL_STRIDE) + +struct mc_ccsr_registers { + u32 reg_gcr1; + u32 reserved1; + u32 reg_gsr; + u32 reserved2; + u32 reg_sicbalr; + u32 reg_sicbahr; + u32 reg_sicapr; + u32 reserved3; + u32 reg_mcfbalr; + u32 reg_mcfbahr; + u32 reg_mcfapr; + u32 reserved4[0x2f1]; + u32 reg_psr; + u32 reserved5; + u32 reg_brr[2]; + u32 reserved6[0x80]; + u32 reg_error[]; +}; + +void fdt_fsl_mc_fixup_iommu_map_entry(void *blob); +int get_mc_boot_status(void); +int get_dpl_apply_status(void); +int is_lazy_dpl_addr_valid(void); +void fdt_fixup_mc_ddr(u64 *base, u64 *size); +#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +int get_aiop_apply_status(void); +#endif +u64 mc_get_dram_addr(void); +unsigned long mc_get_dram_block_size(void); +int fsl_mc_ldpaa_init(struct bd_info *bis); +int fsl_mc_ldpaa_exit(struct bd_info *bd); +void mc_env_boot(void); +#endif diff --git a/roms/u-boot/include/fsl-mc/fsl_mc_cmd.h b/roms/u-boot/include/fsl-mc/fsl_mc_cmd.h new file mode 100644 index 000000000..591cda968 --- /dev/null +++ b/roms/u-boot/include/fsl-mc/fsl_mc_cmd.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ +#ifndef __FSL_MC_CMD_H +#define __FSL_MC_CMD_H + +#define MC_CMD_NUM_OF_PARAMS 7 + +#define MAKE_UMASK64(_width) \ + ((uint64_t)((_width) < 64 ? ((uint64_t)1 << (_width)) - 1 : -1)) + +static inline uint64_t mc_enc(int lsoffset, int width, uint64_t val) +{ + return (uint64_t)(((uint64_t)val & MAKE_UMASK64(width)) << lsoffset); +} +static inline uint64_t mc_dec(uint64_t val, int lsoffset, int width) +{ + return (uint64_t)((val >> lsoffset) & MAKE_UMASK64(width)); +} + +struct mc_command { + uint64_t header; + uint64_t params[MC_CMD_NUM_OF_PARAMS]; +}; + +struct mc_rsp_create { + __le32 object_id; +}; + +struct mc_rsp_api_ver { + __le16 major_ver; + __le16 minor_ver; +}; + +enum mc_cmd_status { + MC_CMD_STATUS_OK = 0x0, /*!< Completed successfully */ + MC_CMD_STATUS_READY = 0x1, /*!< Ready to be processed */ + MC_CMD_STATUS_AUTH_ERR = 0x3, /*!< Authentication error */ + MC_CMD_STATUS_NO_PRIVILEGE = 0x4, /*!< No privilege */ + MC_CMD_STATUS_DMA_ERR = 0x5, /*!< DMA or I/O error */ + MC_CMD_STATUS_CONFIG_ERR = 0x6, /*!< Configuration error */ + MC_CMD_STATUS_TIMEOUT = 0x7, /*!< Operation timed out */ + MC_CMD_STATUS_NO_RESOURCE = 0x8, /*!< No resources */ + MC_CMD_STATUS_NO_MEMORY = 0x9, /*!< No memory available */ + MC_CMD_STATUS_BUSY = 0xA, /*!< Device is busy */ + MC_CMD_STATUS_UNSUPPORTED_OP = 0xB, /*!< Unsupported operation */ + MC_CMD_STATUS_INVALID_STATE = 0xC /*!< Invalid state */ +}; + +/* + * MC command flags + */ + +/* High priority flag */ +#define MC_CMD_FLAG_PRI 0x00008000 +/* No flags */ +#define MC_CMD_NO_FLAGS 0x00000000 +/* Command completion flag */ +#define MC_CMD_FLAG_INTR_DIS 0x01000000 + + +#define MC_CMD_HDR_CMDID_O 48 /* Command ID field offset */ +#define MC_CMD_HDR_CMDID_S 16 /* Command ID field size */ +#define MC_CMD_HDR_STATUS_O 16 /* Status field offset */ +#define MC_CMD_HDR_TOKEN_O 32 /* Token field offset */ +#define MC_CMD_HDR_TOKEN_S 16 /* Token field size */ +#define MC_CMD_HDR_STATUS_S 8 /* Status field size*/ +#define MC_CMD_HDR_FLAGS_O 0 /* Flags field offset */ +#define MC_CMD_HDR_FLAGS_S 32 /* Flags field size*/ +#define MC_CMD_HDR_FLAGS_MASK 0x0000FFFF /* Command flags mask */ + +#define MC_CMD_HDR_READ_STATUS(_hdr) \ + ((enum mc_cmd_status)mc_dec((_hdr), \ + MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S)) + +#define MC_CMD_HDR_READ_TOKEN(_hdr) \ + ((uint16_t)mc_dec((_hdr), MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S)) + +#define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \ + ((_ext)[_param] |= cpu_to_le64(mc_enc((_offset), (_width), _arg))) + +#define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \ + (_arg = (_type)mc_dec(cpu_to_le64(_ext[_param]), (_offset), (_width))) + +#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ + ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg)) + +#define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \ + (_arg = (_type)mc_dec(_cmd.params[_param], (_offset), (_width))) + +/* cmd, param, offset, width, type, arg_name */ +#define MC_CMD_READ_OBJ_ID(cmd, obj_id) \ + MC_RSP_OP(cmd, 0, 0, 32, uint32_t, obj_id) + +/* cmd, param, offset, width, type, arg_name */ +#define CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, object_id) \ + MC_CMD_OP(cmd, 0, 0, 32, uint32_t, object_id) + +static inline uint64_t mc_encode_cmd_header(uint16_t cmd_id, + uint32_t cmd_flags, + uint16_t token) +{ + uint64_t hdr = 0; + + hdr = mc_enc(MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S, cmd_id); + hdr |= mc_enc(MC_CMD_HDR_FLAGS_O, MC_CMD_HDR_FLAGS_S, + (cmd_flags & MC_CMD_HDR_FLAGS_MASK)); + hdr |= mc_enc(MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S, token); + hdr |= mc_enc(MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S, + MC_CMD_STATUS_READY); + + return hdr; +} + +/** + * mc_write_command - writes a command to a Management Complex (MC) portal + * + * @portal: pointer to an MC portal + * @cmd: pointer to a filled command + */ +static inline void mc_write_command(struct mc_command __iomem *portal, + struct mc_command *cmd) +{ + int i; + + /* copy command parameters into the portal */ + for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++) + writeq(cmd->params[i], &portal->params[i]); + + /* submit the command by writing the header */ + writeq(cmd->header, &portal->header); +} + +/** + * mc_read_response - reads the response for the last MC command from a + * Management Complex (MC) portal + * + * @portal: pointer to an MC portal + * @resp: pointer to command response buffer + * + * Returns MC_CMD_STATUS_OK on Success; Error code otherwise. + */ +static inline enum mc_cmd_status mc_read_response( + struct mc_command __iomem *portal, + struct mc_command *resp) +{ + int i; + enum mc_cmd_status status; + + /* Copy command response header from MC portal: */ + resp->header = readq(&portal->header); + status = MC_CMD_HDR_READ_STATUS(resp->header); + if (status != MC_CMD_STATUS_OK) + return status; + + /* Copy command response data from MC portal: */ + for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++) + resp->params[i] = readq(&portal->params[i]); + + return status; +} + +/** + * mc_read_version - read version of the given cmd + * + * @cmd: pointer to a filled command + * @major_version: major version value for the given cmd + * @minor_version: minor version value for the given cmd + */ +static inline void mc_cmd_read_api_version(struct mc_command *cmd, + u16 *major_ver, + u16 *minor_ver) +{ + struct mc_rsp_api_ver *rsp_params; + + rsp_params = (struct mc_rsp_api_ver *)cmd->params; + *major_ver = le16_to_cpu(rsp_params->major_ver); + *minor_ver = le16_to_cpu(rsp_params->minor_ver); +} + +#endif /* __FSL_MC_CMD_H */ diff --git a/roms/u-boot/include/fsl-mc/fsl_mc_private.h b/roms/u-boot/include/fsl-mc/fsl_mc_private.h new file mode 100644 index 000000000..28b6d4502 --- /dev/null +++ b/roms/u-boot/include/fsl-mc/fsl_mc_private.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +#ifndef _FSL_MC_PRIVATE_H_ +#define _FSL_MC_PRIVATE_H_ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +extern struct fsl_mc_io *dflt_mc_io; + +/** + * struct dpbp_node - DPBP strucuture + * @uint16_t handle: DPBP object handle + * @struct dpbp_attr: DPBP attribute + */ +struct fsl_dpbp_obj { + uint32_t dpbp_id; + uint16_t dpbp_handle; + struct dpbp_attr dpbp_attr; +}; + +extern struct fsl_dpbp_obj *dflt_dpbp; + +/** + * struct fsl_dpio_obj - DPIO strucuture + * @int dpio_id: DPIO id + * @struct qbman_swp *sw_portal: SW portal object + */ +struct fsl_dpio_obj { + uint32_t dpio_id; + uint16_t dpio_handle; + struct qbman_swp *sw_portal; /** SW portal object */ +}; + +extern struct fsl_dpio_obj *dflt_dpio; + +/** + * struct dpni_node - DPNI strucuture + * @int dpni_id: DPNI id + * @uint16_t handle: DPNI object handle + * @struct dpni_attr: DPNI attributes + * @struct dpni_buffer_layout: DPNI buffer layout + */ +struct fsl_dpni_obj { + uint32_t dpni_id; + uint16_t dpni_handle; + struct dpni_attr dpni_attrs; + struct dpni_buffer_layout buf_layout; +}; + +extern struct fsl_dpni_obj *dflt_dpni; + +/** + * struct sp_blob_header - SP Blob header structure + * @magic: SP Blob magic number + * @blob_ver: SP Blob version + * @ip_rev: SP IP revision + * @length: Length of the SP Blob + */ +struct sp_blob_header { + u32 magic; + u32 blob_ver; + u32 ip_rev; + u32 length; +}; + +int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr); +int ldpaa_eth_init(int dpmac_id, phy_interface_t enet_if); +int mc_apply_dpl(u64 mc_dpl_addr); +int mc_apply_spb(u64 mc_spb_addr); +#endif /* _FSL_MC_PRIVATE_H_ */ diff --git a/roms/u-boot/include/fsl-mc/fsl_mc_sys.h b/roms/u-boot/include/fsl-mc/fsl_mc_sys.h new file mode 100644 index 000000000..9fb8164f5 --- /dev/null +++ b/roms/u-boot/include/fsl-mc/fsl_mc_sys.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale Layerscape Management Complex (MC) Environment-specific code + * + * Copyright (C) 2014 Freescale Semiconductor, Inc. + */ + +#ifndef _FSL_MC_SYS_H +#define _FSL_MC_SYS_H + +#include + +struct mc_command; + +/* + * struct mc_portal_wrapper - MC command portal wrapper object + */ +struct fsl_mc_io { + struct mc_command __iomem *mmio_regs; +}; + +int mc_send_command(struct fsl_mc_io *mc_io, + struct mc_command *cmd); + +#endif /* _FSL_MC_SYS_H */ diff --git a/roms/u-boot/include/fsl-mc/fsl_qbman_base.h b/roms/u-boot/include/fsl-mc/fsl_qbman_base.h new file mode 100644 index 000000000..7818fc28e --- /dev/null +++ b/roms/u-boot/include/fsl-mc/fsl_qbman_base.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Freescale Semiconductor + */ + +#ifndef _FSL_QBMAN_BASE_H +#define _FSL_QBMAN_BASE_H + +/* Descriptor for a QBMan instance on the SoC. On partitions/targets that do not + * control this QBMan instance, these values may simply be place-holders. The + * idea is simply that we be able to distinguish between them, eg. so that SWP + * descriptors can identify which QBMan instance they belong to. */ +struct qbman_block_desc { + void *ccsr_reg_bar; /* CCSR register map */ + int irq_rerr; /* Recoverable error interrupt line */ + int irq_nrerr; /* Non-recoverable error interrupt line */ +}; + +/* Descriptor for a QBMan software portal, expressed in terms that make sense to + * the user context. Ie. on MC, this information is likely to be true-physical, + * and instantiated statically at compile-time. On GPP, this information is + * likely to be obtained via "discovery" over a partition's "layerscape bus" + * (ie. in response to a MC portal command), and would take into account any + * virtualisation of the GPP user's address space and/or interrupt numbering. */ +struct qbman_swp_desc { + const struct qbman_block_desc *block; /* The QBMan instance */ + void *cena_bar; /* Cache-enabled portal register map */ + void *cinh_bar; /* Cache-inhibited portal register map */ +}; + +/* Driver object for managing a QBMan portal */ +struct qbman_swp; + +/* Place-holder for FDs, we represent it via the simplest form that we need for + * now. Different overlays may be needed to support different options, etc. (It + * is impractical to define One True Struct, because the resulting encoding + * routines (lots of read-modify-writes) would be worst-case performance whether + * or not circumstances required them.) + * + * Note, as with all data-structures exchanged between software and hardware (be + * they located in the portal register map or DMA'd to and from main-memory), + * the driver ensures that the caller of the driver API sees the data-structures + * in host-endianness. "struct qbman_fd" is no exception. The 32-bit words + * contained within this structure are represented in host-endianness, even if + * hardware always treats them as little-endian. As such, if any of these fields + * are interpreted in a binary (rather than numerical) fashion by hardware + * blocks (eg. accelerators), then the user should be careful. We illustrate + * with an example; + * + * Suppose the desired behaviour of an accelerator is controlled by the "frc" + * field of the FDs that are sent to it. Suppose also that the behaviour desired + * by the user corresponds to an "frc" value which is expressed as the literal + * sequence of bytes 0xfe, 0xed, 0xab, and 0xba. So "frc" should be the 32-bit + * value in which 0xfe is the first byte and 0xba is the last byte, and as + * hardware is little-endian, this amounts to a 32-bit "value" of 0xbaabedfe. If + * the software is little-endian also, this can simply be achieved by setting + * frc=0xbaabedfe. On the other hand, if software is big-endian, it should set + * frc=0xfeedabba! The best away of avoiding trouble with this sort of thing is + * to treat the 32-bit words as numerical values, in which the offset of a field + * from the beginning of the first byte (as required or generated by hardware) + * is numerically encoded by a left-shift (ie. by raising the field to a + * corresponding power of 2). Ie. in the current example, software could set + * "frc" in the following way, and it would work correctly on both little-endian + * and big-endian operation; + * fd.frc = (0xfe << 0) | (0xed << 8) | (0xab << 16) | (0xba << 24); + */ +struct qbman_fd { + union { + uint32_t words[8]; + struct qbman_fd_simple { + uint32_t addr_lo; + uint32_t addr_hi; + uint32_t len; + /* offset in the MS 16 bits, BPID in the LS 16 bits */ + uint32_t bpid_offset; + uint32_t frc; /* frame context */ + /* "err", "va", "cbmt", "asal", [...] */ + uint32_t ctrl; + /* flow context */ + uint32_t flc_lo; + uint32_t flc_hi; + } simple; + }; +}; + +#endif /* !_FSL_QBMAN_BASE_H */ diff --git a/roms/u-boot/include/fsl-mc/fsl_qbman_portal.h b/roms/u-boot/include/fsl-mc/fsl_qbman_portal.h new file mode 100644 index 000000000..ee0e4aa50 --- /dev/null +++ b/roms/u-boot/include/fsl-mc/fsl_qbman_portal.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Freescale Semiconductor + */ + +#ifndef _FSL_QBMAN_PORTAL_H +#define _FSL_QBMAN_PORTAL_H + +#include + +/* Create and destroy a functional object representing the given QBMan portal + * descriptor. */ +struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *); + + /************/ + /* Dequeues */ + /************/ + +/* See the QBMan driver API documentation for details on the enqueue + * mechanisms. NB: the use of a 'ldpaa_' prefix for this type is because it is + * primarily used by the "DPIO" layer that sits above (and hides) the QBMan + * driver. The structure is defined in the DPIO interface, but to avoid circular + * dependencies we just pre/re-declare it here opaquely. */ +struct ldpaa_dq; + + +/* ------------------- */ +/* Pull-mode dequeuing */ +/* ------------------- */ + +struct qbman_pull_desc { + uint32_t dont_manipulate_directly[6]; +}; + +/* Clear the contents of a descriptor to default/starting state. */ +void qbman_pull_desc_clear(struct qbman_pull_desc *); +/* If not called, or if called with 'storage' as NULL, the result pull dequeues + * will produce results to DQRR. If 'storage' is non-NULL, then results are + * produced to the given memory location (using the physical/DMA address which + * the caller provides in 'storage_phys'), and 'stash' controls whether or not + * those writes to main-memory express a cache-warming attribute. */ +void qbman_pull_desc_set_storage(struct qbman_pull_desc *, + struct ldpaa_dq *storage, + dma_addr_t storage_phys, + int stash); +/* numframes must be between 1 and 16, inclusive */ +void qbman_pull_desc_set_numframes(struct qbman_pull_desc *, uint8_t numframes); +/* token is the value that shows up in the dequeue results that can be used to + * detect when the results have been published, and is not really used when + * dequeue results go to DQRR. The easiest technique is to zero result "storage" + * before issuing a pull dequeue, and use any non-zero 'token' value. */ +void qbman_pull_desc_set_token(struct qbman_pull_desc *, uint8_t token); +/* Exactly one of the following descriptor "actions" should be set. (Calling any + * one of these will replace the effect of any prior call to one of these.) + * - pull dequeue from the given frame queue (FQ) + * - pull dequeue from any FQ in the given work queue (WQ) + * - pull dequeue from any FQ in any WQ in the given channel + */ +void qbman_pull_desc_set_fq(struct qbman_pull_desc *, uint32_t fqid); + +/* Issue the pull dequeue command */ +int qbman_swp_pull(struct qbman_swp *, struct qbman_pull_desc *); + +/* -------------------------------- */ +/* Polling DQRR for dequeue results */ +/* -------------------------------- */ + +/* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry + * only once, so repeated calls can return a sequence of DQRR entries, without + * requiring they be consumed immediately or in any particular order. */ +const struct ldpaa_dq *qbman_swp_dqrr_next(struct qbman_swp *); +/* Consume DQRR entries previously returned from qbman_swp_dqrr_next(). */ +void qbman_swp_dqrr_consume(struct qbman_swp *, const struct ldpaa_dq *); + +/* ------------------------------------------------- */ +/* Polling user-provided storage for dequeue results */ +/* ------------------------------------------------- */ + +/* Only used for user-provided storage of dequeue results, not DQRR. Prior to + * being used, the storage must set "oldtoken", so that the driver notices when + * hardware has filled it in with results using a "newtoken". NB, for efficiency + * purposes, the driver will perform any required endianness conversion to + * ensure that the user's dequeue result storage is in host-endian format + * (whether or not that is the same as the little-endian format that hardware + * DMA'd to the user's storage). As such, once the user has called + * qbman_dq_entry_has_newtoken() and been returned a valid dequeue result, they + * should not call it again on the same memory location (except of course if + * another dequeue command has been executed to produce a new result to that + * location). + */ +void qbman_dq_entry_set_oldtoken(struct ldpaa_dq *, + unsigned int num_entries, + uint8_t oldtoken); +int qbman_dq_entry_has_newtoken(struct qbman_swp *, + const struct ldpaa_dq *, + uint8_t newtoken); + +/* -------------------------------------------------------- */ +/* Parsing dequeue entries (DQRR and user-provided storage) */ +/* -------------------------------------------------------- */ + +/* DQRR entries may contain non-dequeue results, ie. notifications */ +int qbman_dq_entry_is_DQ(const struct ldpaa_dq *); + + /************/ + /* Enqueues */ + /************/ + +struct qbman_eq_desc { + uint32_t dont_manipulate_directly[8]; +}; + + +/* Clear the contents of a descriptor to default/starting state. */ +void qbman_eq_desc_clear(struct qbman_eq_desc *); +/* Exactly one of the following descriptor "actions" should be set. (Calling + * any one of these will replace the effect of any prior call to one of these.) + * - enqueue without order-restoration + * - enqueue with order-restoration + * - fill a hole in the order-restoration sequence, without any enqueue + * - advance NESN (Next Expected Sequence Number), without any enqueue + * 'respond_success' indicates whether an enqueue response should be DMA'd + * after success (otherwise a response is DMA'd only after failure). + * 'incomplete' indicates that other fragments of the same 'seqnum' are yet to + * be enqueued. + */ +void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *, int respond_success); +void qbman_eq_desc_set_response(struct qbman_eq_desc *, + dma_addr_t storage_phys, + int stash); +/* token is the value that shows up in an enqueue response that can be used to + * detect when the results have been published. The easiest technique is to zero + * result "storage" before issuing an enqueue, and use any non-zero 'token' + * value. */ +void qbman_eq_desc_set_token(struct qbman_eq_desc *, uint8_t token); +/* Exactly one of the following descriptor "targets" should be set. (Calling any + * one of these will replace the effect of any prior call to one of these.) + * - enqueue to a frame queue + * - enqueue to a queuing destination + * Note, that none of these will have any affect if the "action" type has been + * set to "orp_hole" or "orp_nesn". + */ +void qbman_eq_desc_set_fq(struct qbman_eq_desc *, uint32_t fqid); +void qbman_eq_desc_set_qd(struct qbman_eq_desc *, uint32_t qdid, + uint32_t qd_bin, uint32_t qd_prio); + +/* Issue an enqueue command. ('fd' should only be NULL if the "action" of the + * descriptor is "orp_hole" or "orp_nesn".) */ +int qbman_swp_enqueue(struct qbman_swp *, const struct qbman_eq_desc *, + const struct qbman_fd *fd); + + /*******************/ + /* Buffer releases */ + /*******************/ + +struct qbman_release_desc { + uint32_t dont_manipulate_directly[1]; +}; + +/* Clear the contents of a descriptor to default/starting state. */ +void qbman_release_desc_clear(struct qbman_release_desc *); +/* Set the ID of the buffer pool to release to */ +void qbman_release_desc_set_bpid(struct qbman_release_desc *, uint32_t bpid); +/* Issue a release command. 'num_buffers' must be less than 8. */ +int qbman_swp_release(struct qbman_swp *, const struct qbman_release_desc *, + const uint64_t *buffers, unsigned int num_buffers); + + /*******************/ + /* Buffer acquires */ + /*******************/ + +int qbman_swp_acquire(struct qbman_swp *, uint32_t bpid, uint64_t *buffers, + unsigned int num_buffers); +#endif /* !_FSL_QBMAN_PORTAL_H */ diff --git a/roms/u-boot/include/fsl-mc/ldpaa_wriop.h b/roms/u-boot/include/fsl-mc/ldpaa_wriop.h new file mode 100644 index 000000000..b55c39cbb --- /dev/null +++ b/roms/u-boot/include/fsl-mc/ldpaa_wriop.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor + */ + +#ifndef __LDPAA_WRIOP_H +#define __LDPAA_WRIOP_H + +#include + +#define DEFAULT_WRIOP_MDIO1_NAME "FSL_MDIO0" +#define DEFAULT_WRIOP_MDIO2_NAME "FSL_MDIO1" +#define WRIOP_MAX_PHY_NUM 2 + +enum wriop_port { + WRIOP1_DPMAC1 = 1, + WRIOP1_DPMAC2, + WRIOP1_DPMAC3, + WRIOP1_DPMAC4, + WRIOP1_DPMAC5, + WRIOP1_DPMAC6, + WRIOP1_DPMAC7, + WRIOP1_DPMAC8, + WRIOP1_DPMAC9, + WRIOP1_DPMAC10, + WRIOP1_DPMAC11, + WRIOP1_DPMAC12, + WRIOP1_DPMAC13, + WRIOP1_DPMAC14, + WRIOP1_DPMAC15, + WRIOP1_DPMAC16, + WRIOP1_DPMAC17, + WRIOP1_DPMAC18, + WRIOP1_DPMAC19, + WRIOP1_DPMAC20, + WRIOP1_DPMAC21, + WRIOP1_DPMAC22, + WRIOP1_DPMAC23, + WRIOP1_DPMAC24, + NUM_WRIOP_PORTS, +}; + +struct wriop_dpmac_info { + u8 enabled; + u8 id; + u8 board_mux; + int phy_addr[WRIOP_MAX_PHY_NUM]; + phy_interface_t enet_if; + struct phy_device *phydev[WRIOP_MAX_PHY_NUM]; + struct mii_dev *bus; +}; + +extern struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS]; + +void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl); +void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if); +int wriop_disable_dpmac(int dpmac_id); +int wriop_enable_dpmac(int dpmac_id); +int wriop_is_enabled_dpmac(int dpmac_id); +int wriop_set_mdio(int dpmac_id, struct mii_dev *bus); +struct mii_dev *wriop_get_mdio(int dpmac_id); +int wriop_set_phy_address(int dpmac_id, int phy_num, int address); +int wriop_get_phy_address(int dpmac_id, int phy_num); +int wriop_set_phy_dev(int dpmac_id, int phy_num, struct phy_device *phydev); +struct phy_device *wriop_get_phy_dev(int dpmac_id, int phy_num); +phy_interface_t wriop_get_enet_if(int dpmac_id); + +void wriop_dpmac_disable(int dpmac_id); +void wriop_dpmac_enable(int dpmac_id); +phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl); +void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl); +void wriop_init_rgmii(void); +#endif /* __LDPAA_WRIOP_H */ diff --git a/roms/u-boot/include/fsl_csu.h b/roms/u-boot/include/fsl_csu.h new file mode 100644 index 000000000..0e59ac3c3 --- /dev/null +++ b/roms/u-boot/include/fsl_csu.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor + * + */ + +#ifndef __FSL_CSU_H__ +#define __FSL_CSU_H__ + +enum csu_cslx_access { + CSU_NS_SUP_R = 0x08, + CSU_NS_SUP_W = 0x80, + CSU_NS_SUP_RW = 0x88, + CSU_NS_USER_R = 0x04, + CSU_NS_USER_W = 0x40, + CSU_NS_USER_RW = 0x44, + CSU_S_SUP_R = 0x02, + CSU_S_SUP_W = 0x20, + CSU_S_SUP_RW = 0x22, + CSU_S_USER_R = 0x01, + CSU_S_USER_W = 0x10, + CSU_S_USER_RW = 0x11, + CSU_ALL_RW = 0xff, +}; + +struct csu_ns_dev { + unsigned long ind; + uint32_t val; +}; + +void enable_layerscape_ns_access(void); +void set_devices_ns_access(unsigned long, u16 val); +void set_pcie_ns_access(int pcie, u16 val); + +#endif diff --git a/roms/u-boot/include/fsl_dcu_fb.h b/roms/u-boot/include/fsl_dcu_fb.h new file mode 100644 index 000000000..7a5347a92 --- /dev/null +++ b/roms/u-boot/include/fsl_dcu_fb.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * FSL DCU Framebuffer driver + */ +#include + +int fsl_dcu_init(struct fb_info *fbinfo, + unsigned int xres, + unsigned int yres, + unsigned int pixel_format); + +int fsl_dcu_fixedfb_setup(void *blob); + +/* Prototypes for external board-specific functions */ +int platform_dcu_init(struct fb_info *fbinfo, + unsigned int xres, + unsigned int yres, + const char *port, + struct fb_videomode *dcu_fb_videomode); +unsigned int dcu_set_pixel_clock(unsigned int pixclock); diff --git a/roms/u-boot/include/fsl_ddr.h b/roms/u-boot/include/fsl_ddr.h new file mode 100644 index 000000000..025d7a1e7 --- /dev/null +++ b/roms/u-boot/include/fsl_ddr.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + */ + +#ifndef FSL_DDR_MAIN_H +#define FSL_DDR_MAIN_H + +#include +#include +#include + +#include + +struct cmd_tbl; + +#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS +/* All controllers are for main memory */ +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_NUM_DDR_CTLRS +#endif + +#ifdef CONFIG_SYS_FSL_DDR_LE +#define ddr_in32(a) in_le32(a) +#define ddr_out32(a, v) out_le32(a, v) +#define ddr_setbits32(a, v) setbits_le32(a, v) +#define ddr_clrbits32(a, v) clrbits_le32(a, v) +#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set) +#else +#define ddr_in32(a) in_be32(a) +#define ddr_out32(a, v) out_be32(a, v) +#define ddr_setbits32(a, v) setbits_be32(a, v) +#define ddr_clrbits32(a, v) clrbits_be32(a, v) +#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) +#endif + +u32 fsl_ddr_get_version(unsigned int ctrl_num); + +#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) +/* + * Bind the main DDR setup driver's generic names + * to this specific DDR technology. + */ +static __inline__ int +compute_dimm_parameters(const unsigned int ctrl_num, + const generic_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) +{ + return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number); +} +#endif + +/* + * Data Structures + * + * All data structures have to be on the stack + */ +#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR + +typedef struct { + generic_spd_eeprom_t + spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; + struct dimm_params_s + dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; + memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; + common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; + fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; + unsigned int first_ctrl; + unsigned int num_ctrls; + unsigned long long mem_base; + unsigned int dimm_slots_per_ctrl; + int (*board_need_mem_reset)(void); + void (*board_mem_reset)(void); + void (*board_mem_de_reset)(void); +} fsl_ddr_info_t; + +/* Compute steps */ +#define STEP_GET_SPD (1 << 0) +#define STEP_COMPUTE_DIMM_PARMS (1 << 1) +#define STEP_COMPUTE_COMMON_PARMS (1 << 2) +#define STEP_GATHER_OPTS (1 << 3) +#define STEP_ASSIGN_ADDRESSES (1 << 4) +#define STEP_COMPUTE_REGS (1 << 5) +#define STEP_PROGRAM_REGS (1 << 6) +#define STEP_ALL 0xFFF + +unsigned long long +fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, + unsigned int size_only); +const char *step_to_string(unsigned int step); + +unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num, + const memctl_options_t *popts, + fsl_ddr_cfg_regs_t *ddr, + const common_timing_params_t *common_dimm, + const dimm_params_t *dimm_parameters, + unsigned int dbw_capacity_adjust, + unsigned int size_only); +unsigned int compute_lowest_common_dimm_parameters( + const unsigned int ctrl_num, + const dimm_params_t *dimm_params, + common_timing_params_t *outpdimm, + unsigned int number_of_dimms); +unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, + memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num); +void check_interleaving_options(fsl_ddr_info_t *pinfo); + +unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk); +unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num); +unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos); +void fsl_ddr_set_lawbar( + const common_timing_params_t *memctl_common_params, + unsigned int memctl_interleaved, + unsigned int ctrl_num); +void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, + unsigned int last_ctrl); + +int fsl_ddr_interactive_env_var_exists(void); +unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl); + +int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); +void board_add_ram_info(int use_default); + +/* processor specific function */ +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step); +void remove_unused_controllers(fsl_ddr_info_t *info); + +/* board specific function */ +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number); +void update_spd_address(unsigned int ctrl_num, + unsigned int slot, + unsigned int *addr); + +void erratum_a009942_check_cpo(void); +#endif diff --git a/roms/u-boot/include/fsl_ddr_dimm_params.h b/roms/u-boot/include/fsl_ddr_dimm_params.h new file mode 100644 index 000000000..58b42b875 --- /dev/null +++ b/roms/u-boot/include/fsl_ddr_dimm_params.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2008-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP Semiconductor + */ + +#ifndef DDR2_DIMM_PARAMS_H +#define DDR2_DIMM_PARAMS_H + +#define EDC_DATA_PARITY 1 +#define EDC_ECC 2 +#define EDC_AC_PARITY 4 + +/* Parameters for a DDR dimm computed from the SPD */ +typedef struct dimm_params_s { + + /* DIMM organization parameters */ + char mpart[19]; /* guaranteed null terminated */ + + unsigned int n_ranks; + unsigned int die_density; + unsigned long long rank_density; + unsigned long long capacity; + unsigned int data_width; + unsigned int primary_sdram_width; + unsigned int ec_sdram_width; + unsigned int registered_dimm; + unsigned int package_3ds; /* number of dies in 3DS DIMM */ + unsigned int device_width; /* x4, x8, x16 components */ + + /* SDRAM device parameters */ + unsigned int n_row_addr; + unsigned int n_col_addr; + unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ +#ifdef CONFIG_SYS_FSL_DDR4 + unsigned int bank_addr_bits; + unsigned int bank_group_bits; +#else + unsigned int n_banks_per_sdram_device; +#endif + unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ + + /* used in computing base address of DIMMs */ + unsigned long long base_address; + /* mirrored DIMMs */ + unsigned int mirrored_dimm; /* only for ddr3 */ + + /* DIMM timing parameters */ + + int mtb_ps; /* medium timebase ps */ + int ftb_10th_ps; /* fine timebase, in 1/10 ps */ + int taa_ps; /* minimum CAS latency time */ + int tfaw_ps; /* four active window delay */ + + /* + * SDRAM clock periods + * The range for these are 1000-10000 so a short should be sufficient + */ + int tckmin_x_ps; + int tckmin_x_minus_1_ps; + int tckmin_x_minus_2_ps; + int tckmax_ps; + + /* SPD-defined CAS latencies */ + unsigned int caslat_x; + unsigned int caslat_x_minus_1; + unsigned int caslat_x_minus_2; + + unsigned int caslat_lowest_derated; /* Derated CAS latency */ + + /* basic timing parameters */ + int trcd_ps; + int trp_ps; + int tras_ps; + +#ifdef CONFIG_SYS_FSL_DDR4 + int trfc1_ps; + int trfc2_ps; + int trfc4_ps; + int trrds_ps; + int trrdl_ps; + int tccdl_ps; + int trfc_slr_ps; +#else + int twr_ps; /* maximum = 63750 ps */ + int trfc_ps; /* max = 255 ns + 256 ns + .75 ns + = 511750 ps */ + int trrd_ps; /* maximum = 63750 ps */ + int twtr_ps; /* maximum = 63750 ps */ + int trtp_ps; /* byte 38, spd->trtp */ +#endif + + int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ + + int refresh_rate_ps; + int extended_op_srt; + +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) + int tis_ps; /* byte 32, spd->ca_setup */ + int tih_ps; /* byte 33, spd->ca_hold */ + int tds_ps; /* byte 34, spd->data_setup */ + int tdh_ps; /* byte 35, spd->data_hold */ + int tdqsq_max_ps; /* byte 44, spd->tdqsq */ + int tqhs_ps; /* byte 45, spd->tqhs */ +#endif + + /* DDR3 & DDR4 RDIMM */ + unsigned char rcw[16]; /* Register Control Word 0-15 */ +#ifdef CONFIG_SYS_FSL_DDR4 + unsigned int dq_mapping[18]; + unsigned int dq_mapping_ors; +#endif +} dimm_params_t; + +unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, + const generic_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number); + +#endif diff --git a/roms/u-boot/include/fsl_ddr_sdram.h b/roms/u-boot/include/fsl_ddr_sdram.h new file mode 100644 index 000000000..56c9db259 --- /dev/null +++ b/roms/u-boot/include/fsl_ddr_sdram.h @@ -0,0 +1,490 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2008-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP Semiconductor + */ + +#ifndef FSL_DDR_MEMCTL_H +#define FSL_DDR_MEMCTL_H + +/* + * Pick a basic DDR Technology. + */ +#include +#include + +#define SDRAM_TYPE_DDR1 2 +#define SDRAM_TYPE_DDR2 3 +#define SDRAM_TYPE_LPDDR1 6 +#define SDRAM_TYPE_DDR3 7 +#define SDRAM_TYPE_DDR4 5 + +#define DDR_BL4 4 /* burst length 4 */ +#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ +#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ +#define DDR_BL8 8 /* burst length 8 */ + +#define DDR3_RTT_OFF 0 +#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ +#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ +#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ +#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ +#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ + +#define DDR4_RTT_OFF 0 +#define DDR4_RTT_60_OHM 1 /* RZQ/4 */ +#define DDR4_RTT_120_OHM 2 /* RZQ/2 */ +#define DDR4_RTT_40_OHM 3 /* RZQ/6 */ +#define DDR4_RTT_240_OHM 4 /* RZQ/1 */ +#define DDR4_RTT_48_OHM 5 /* RZQ/5 */ +#define DDR4_RTT_80_OHM 6 /* RZQ/3 */ +#define DDR4_RTT_34_OHM 7 /* RZQ/7 */ + +#define DDR2_RTT_OFF 0 +#define DDR2_RTT_75_OHM 1 +#define DDR2_RTT_150_OHM 2 +#define DDR2_RTT_50_OHM 3 + +#if defined(CONFIG_SYS_FSL_DDR1) +#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) +typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1 +#endif +#elif defined(CONFIG_SYS_FSL_DDR2) +#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) +typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 +#endif +#elif defined(CONFIG_SYS_FSL_DDR3) +typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 +#endif +#elif defined(CONFIG_SYS_FSL_DDR4) +#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ +typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4 +#endif +#endif /* #if defined(CONFIG_SYS_FSL_DDR1) */ + +#define FSL_DDR_ODT_NEVER 0x0 +#define FSL_DDR_ODT_CS 0x1 +#define FSL_DDR_ODT_ALL_OTHER_CS 0x2 +#define FSL_DDR_ODT_OTHER_DIMM 0x3 +#define FSL_DDR_ODT_ALL 0x4 +#define FSL_DDR_ODT_SAME_DIMM 0x5 +#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6 +#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 + +/* define bank(chip select) interleaving mode */ +#define FSL_DDR_CS0_CS1 0x40 +#define FSL_DDR_CS2_CS3 0x20 +#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) +#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) + +/* define memory controller interleaving mode */ +#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 +#define FSL_DDR_PAGE_INTERLEAVING 0x1 +#define FSL_DDR_BANK_INTERLEAVING 0x2 +#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 +#define FSL_DDR_256B_INTERLEAVING 0x8 +#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA +#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC +#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD +/* placeholder for 4-way interleaving */ +#define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A +#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C +#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D + +#define SDRAM_CS_CONFIG_EN 0x80000000 + +/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration + */ +#define SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG_SREN 0x40000000 +#define SDRAM_CFG_ECC_EN 0x20000000 +#define SDRAM_CFG_RD_EN 0x10000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 +#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 +#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 +#define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_DBW_MASK 0x00180000 +#define SDRAM_CFG_DBW_SHIFT 19 +#define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_16_BE 0x00100000 +#define SDRAM_CFG_8_BE 0x00040000 +#define SDRAM_CFG_NCAP 0x00020000 +#define SDRAM_CFG_2T_EN 0x00008000 +#define SDRAM_CFG_BI 0x00000001 + +#define SDRAM_CFG2_FRC_SR 0x80000000 +#define SDRAM_CFG2_D_INIT 0x00000010 +#define SDRAM_CFG2_AP_EN 0x00000020 +#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 +#define SDRAM_CFG2_ODT_NEVER 0 +#define SDRAM_CFG2_ODT_ONLY_WRITE 1 +#define SDRAM_CFG2_ODT_ONLY_READ 2 +#define SDRAM_CFG2_ODT_ALWAYS 3 + +#define SDRAM_INTERVAL_BSTOPRE 0x3FFF +#define TIMING_CFG_2_CPO_MASK 0x0F800000 + +#if defined(CONFIG_SYS_FSL_DDR_VER) && \ + (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4) +#define RD_TO_PRE_MASK 0xf +#define RD_TO_PRE_SHIFT 13 +#define WR_DATA_DELAY_MASK 0xf +#define WR_DATA_DELAY_SHIFT 9 +#else +#define RD_TO_PRE_MASK 0x7 +#define RD_TO_PRE_SHIFT 13 +#define WR_DATA_DELAY_MASK 0x7 +#define WR_DATA_DELAY_SHIFT 10 +#endif + +/* DDR_EOR register */ +#define DDR_EOR_RD_REOD_DIS 0x07000000 +#define DDR_EOR_WD_REOD_DIS 0x00100000 + +/* DDR_MD_CNTL */ +#define MD_CNTL_MD_EN 0x80000000 +#define MD_CNTL_CS_SEL_CS0 0x00000000 +#define MD_CNTL_CS_SEL_CS1 0x10000000 +#define MD_CNTL_CS_SEL_CS2 0x20000000 +#define MD_CNTL_CS_SEL_CS3 0x30000000 +#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000 +#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000 +#define MD_CNTL_MD_SEL_MR 0x00000000 +#define MD_CNTL_MD_SEL_EMR 0x01000000 +#define MD_CNTL_MD_SEL_EMR2 0x02000000 +#define MD_CNTL_MD_SEL_EMR3 0x03000000 +#define MD_CNTL_SET_REF 0x00800000 +#define MD_CNTL_SET_PRE 0x00400000 +#define MD_CNTL_CKE_CNTL_LOW 0x00100000 +#define MD_CNTL_CKE_CNTL_HIGH 0x00200000 +#define MD_CNTL_WRCW 0x00080000 +#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) +#define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28) +#define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24) + +/* DDR_CDR1 */ +#define DDR_CDR1_DHC_EN 0x80000000 +#define DDR_CDR1_V0PT9_EN 0x40000000 +#define DDR_CDR1_ODT_SHIFT 17 +#define DDR_CDR1_ODT_MASK 0x6 +#define DDR_CDR2_ODT_MASK 0x1 +#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) +#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) +#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8)) +#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 +#define DDR_CDR2_VREF_RANGE_2 0x00000040 + +/* DDR ERR_DISABLE */ +#define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */ + +/* Mode Registers */ +#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ +#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ + +/* DEBUG_26 register */ +#define DDR_CAS_TO_PRE_SUB_MASK 0x0000f000 /* CAS to preamble subtract value */ +#define DDR_CAS_TO_PRE_SUB_SHIFT 12 + +/* DEBUG_29 register */ +#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */ + + +#if (defined(CONFIG_SYS_FSL_DDR_VER) && \ + (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) +#ifdef CONFIG_SYS_FSL_DDR3L +#define DDR_CDR_ODT_OFF 0x0 +#define DDR_CDR_ODT_120ohm 0x1 +#define DDR_CDR_ODT_200ohm 0x2 +#define DDR_CDR_ODT_75ohm 0x3 +#define DDR_CDR_ODT_60ohm 0x5 +#define DDR_CDR_ODT_46ohm 0x7 +#elif defined(CONFIG_SYS_FSL_DDR4) +#define DDR_CDR_ODT_OFF 0x0 +#define DDR_CDR_ODT_100ohm 0x1 +#define DDR_CDR_ODT_120OHM 0x2 +#define DDR_CDR_ODT_80ohm 0x3 +#define DDR_CDR_ODT_60ohm 0x4 +#define DDR_CDR_ODT_40ohm 0x5 +#define DDR_CDR_ODT_50ohm 0x6 +#define DDR_CDR_ODT_30ohm 0x7 +#else +#define DDR_CDR_ODT_OFF 0x0 +#define DDR_CDR_ODT_120ohm 0x1 +#define DDR_CDR_ODT_180ohm 0x2 +#define DDR_CDR_ODT_75ohm 0x3 +#define DDR_CDR_ODT_110ohm 0x4 +#define DDR_CDR_ODT_60hm 0x5 +#define DDR_CDR_ODT_70ohm 0x6 +#define DDR_CDR_ODT_47ohm 0x7 +#endif /* DDR3L */ +#else +#define DDR_CDR_ODT_75ohm 0x0 +#define DDR_CDR_ODT_55ohm 0x1 +#define DDR_CDR_ODT_60ohm 0x2 +#define DDR_CDR_ODT_50ohm 0x3 +#define DDR_CDR_ODT_150ohm 0x4 +#define DDR_CDR_ODT_43ohm 0x5 +#define DDR_CDR_ODT_120ohm 0x6 +#endif + +#define DDR_INIT_ADDR_EXT_UIA (1 << 31) + +/* Record of register values computed */ +typedef struct fsl_ddr_cfg_regs_s { + struct { + unsigned int bnds; + unsigned int config; + unsigned int config_2; + } cs[CONFIG_CHIP_SELECTS_PER_CTRL]; + unsigned int timing_cfg_3; + unsigned int timing_cfg_0; + unsigned int timing_cfg_1; + unsigned int timing_cfg_2; + unsigned int ddr_sdram_cfg; + unsigned int ddr_sdram_cfg_2; + unsigned int ddr_sdram_cfg_3; + unsigned int ddr_sdram_mode; + unsigned int ddr_sdram_mode_2; + unsigned int ddr_sdram_mode_3; + unsigned int ddr_sdram_mode_4; + unsigned int ddr_sdram_mode_5; + unsigned int ddr_sdram_mode_6; + unsigned int ddr_sdram_mode_7; + unsigned int ddr_sdram_mode_8; + unsigned int ddr_sdram_mode_9; + unsigned int ddr_sdram_mode_10; + unsigned int ddr_sdram_mode_11; + unsigned int ddr_sdram_mode_12; + unsigned int ddr_sdram_mode_13; + unsigned int ddr_sdram_mode_14; + unsigned int ddr_sdram_mode_15; + unsigned int ddr_sdram_mode_16; + unsigned int ddr_sdram_md_cntl; + unsigned int ddr_sdram_interval; + unsigned int ddr_data_init; + unsigned int ddr_sdram_clk_cntl; + unsigned int ddr_init_addr; + unsigned int ddr_init_ext_addr; + unsigned int timing_cfg_4; + unsigned int timing_cfg_5; + unsigned int timing_cfg_6; + unsigned int timing_cfg_7; + unsigned int timing_cfg_8; + unsigned int timing_cfg_9; + unsigned int ddr_zq_cntl; + unsigned int ddr_wrlvl_cntl; + unsigned int ddr_wrlvl_cntl_2; + unsigned int ddr_wrlvl_cntl_3; + unsigned int ddr_sr_cntr; + unsigned int ddr_sdram_rcw_1; + unsigned int ddr_sdram_rcw_2; + unsigned int ddr_sdram_rcw_3; + unsigned int ddr_sdram_rcw_4; + unsigned int ddr_sdram_rcw_5; + unsigned int ddr_sdram_rcw_6; + unsigned int dq_map_0; + unsigned int dq_map_1; + unsigned int dq_map_2; + unsigned int dq_map_3; + unsigned int ddr_eor; + unsigned int ddr_cdr1; + unsigned int ddr_cdr2; + unsigned int err_disable; + unsigned int err_int_en; + unsigned int debug[64]; +} fsl_ddr_cfg_regs_t; + +typedef struct memctl_options_partial_s { + unsigned int all_dimms_ecc_capable; + unsigned int all_dimms_tckmax_ps; + unsigned int all_dimms_burst_lengths_bitmask; + unsigned int all_dimms_registered; + unsigned int all_dimms_unbuffered; + /* unsigned int lowest_common_spd_caslat; */ + unsigned int all_dimms_minimum_trcd_ps; +} memctl_options_partial_t; + +#define DDR_DATA_BUS_WIDTH_64 0 +#define DDR_DATA_BUS_WIDTH_32 1 +#define DDR_DATA_BUS_WIDTH_16 2 +#define DDR_CSWL_CS0 0x04000001 +/* + * Generalized parameters for memory controller configuration, + * might be a little specific to the FSL memory controller + */ +typedef struct memctl_options_s { + /* + * Memory organization parameters + * + * if DIMM is present in the system + * where DIMMs are with respect to chip select + * where chip selects are with respect to memory boundaries + */ + unsigned int registered_dimm_en; /* use registered DIMM support */ + + /* Options local to a Chip Select */ + struct cs_local_opts_s { + unsigned int auto_precharge; + unsigned int odt_rd_cfg; + unsigned int odt_wr_cfg; + unsigned int odt_rtt_norm; + unsigned int odt_rtt_wr; + } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; + + /* Special configurations for chip select */ + unsigned int memctl_interleaving; + unsigned int memctl_interleaving_mode; + unsigned int ba_intlv_ctl; + unsigned int addr_hash; + + /* Operational mode parameters */ + unsigned int ecc_mode; /* Use ECC? */ + /* Initialize ECC using memory controller? */ + unsigned int ecc_init_using_memctl; + unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ + /* SREN - self-refresh during sleep */ + unsigned int self_refresh_in_sleep; + /* SR_IE - Self-refresh interrupt enable */ + unsigned int self_refresh_interrupt_en; + unsigned int dynamic_power; /* DYN_PWR */ + /* memory data width to use (16-bit, 32-bit, 64-bit) */ + unsigned int data_bus_width; + unsigned int burst_length; /* BL4, OTF and BL8 */ + /* On-The-Fly Burst Chop enable */ + unsigned int otf_burst_chop_en; + /* mirrior DIMMs for DDR3 */ + unsigned int mirrored_dimm; + unsigned int quad_rank_present; + unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */ + unsigned int x4_en; /* enable x4 devices */ + unsigned int package_3ds; + + /* Global Timing Parameters */ + unsigned int cas_latency_override; + unsigned int cas_latency_override_value; + unsigned int use_derated_caslat; + unsigned int additive_latency_override; + unsigned int additive_latency_override_value; + + unsigned int clk_adjust; /* */ + unsigned int cpo_override; /* override timing_cfg_2[CPO]*/ + unsigned int cpo_sample; /* optimize debug_29[24:31] */ + unsigned int write_data_delay; /* DQS adjust */ + + unsigned int cswl_override; + unsigned int wrlvl_override; + unsigned int wrlvl_sample; /* Write leveling */ + unsigned int wrlvl_start; + unsigned int wrlvl_ctl_2; + unsigned int wrlvl_ctl_3; + + unsigned int half_strength_driver_enable; + unsigned int twot_en; + unsigned int threet_en; + unsigned int bstopre; + unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */ + + /* Rtt impedance */ + unsigned int rtt_override; /* rtt_override enable */ + unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ + unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ + + /* Automatic self refresh */ + unsigned int auto_self_refresh_en; + unsigned int sr_it; + /* ZQ calibration */ + unsigned int zq_en; + /* Write leveling */ + unsigned int wrlvl_en; + /* RCW override for RDIMM */ + unsigned int rcw_override; + unsigned int rcw_1; + unsigned int rcw_2; + unsigned int rcw_3; + /* control register 1 */ + unsigned int ddr_cdr1; + unsigned int ddr_cdr2; + + unsigned int trwt_override; + unsigned int trwt; /* read-to-write turnaround */ +} memctl_options_t; + +phys_size_t fsl_ddr_sdram(void); +phys_size_t fsl_ddr_sdram_size(void); +phys_size_t fsl_other_ddr_sdram(unsigned long long base, + unsigned int first_ctrl, + unsigned int num_ctrls, + unsigned int dimm_slots_per_ctrl, + int (*board_need_reset)(void), + void (*board_reset)(void), + void (*board_de_reset)(void)); +extern int fsl_use_spd(void); +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step); +u32 fsl_ddr_get_intl3r(void); +void print_ddr_info(unsigned int start_ctrl); + +static void __board_assert_mem_reset(void) +{ +} + +static void __board_deassert_mem_reset(void) +{ +} + +void board_assert_mem_reset(void) + __attribute__((weak, alias("__board_assert_mem_reset"))); + +void board_deassert_mem_reset(void) + __attribute__((weak, alias("__board_deassert_mem_reset"))); + +static int __board_need_mem_reset(void) +{ + return 0; +} + +int board_need_mem_reset(void) + __attribute__((weak, alias("__board_need_mem_reset"))); + +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void); +bool is_warm_boot(void); +int fsl_dp_resume(void); +#endif + +/* + * The 85xx boards have a common prototype for fixed_sdram so put the + * declaration here. + */ +#ifdef CONFIG_MPC85xx +extern phys_size_t fixed_sdram(void); +#endif + +#if defined(CONFIG_DDR_ECC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + + +typedef struct fixed_ddr_parm{ + int min_freq; + int max_freq; + fsl_ddr_cfg_regs_t *ddr_settings; +} fixed_ddr_parm_t; + +/** + * fsl_initdram() - Set up the SDRAM + * + * @return 0 if OK, -ve on error + */ +int fsl_initdram(void); + +#endif diff --git a/roms/u-boot/include/fsl_ddrc_version.h b/roms/u-boot/include/fsl_ddrc_version.h new file mode 100644 index 000000000..7c1d0419d --- /dev/null +++ b/roms/u-boot/include/fsl_ddrc_version.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __FSL_DDRC_VER_H +#define __FSL_DDRC_VER_H + +/* + * Only the versions with distinct features or registers are listed here. + */ +#define FSL_DDR_VER_4_4 44 +#define FSL_DDR_VER_4_6 46 +#define FSL_DDR_VER_4_7 47 +#define FSL_DDR_VER_5_0 50 + +#endif /* __FSL_DDRC_VER_H */ diff --git a/roms/u-boot/include/fsl_devdis.h b/roms/u-boot/include/fsl_devdis.h new file mode 100644 index 000000000..1f1b03331 --- /dev/null +++ b/roms/u-boot/include/fsl_devdis.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __FSL_DEVDIS_H_ +#define __FSL_DEVDIS_H_ + +struct devdis_table { + char name[32]; + u32 offset; + u32 mask; +}; + +void device_disable(const struct devdis_table *tbl, uint32_t num); + +#endif diff --git a/roms/u-boot/include/fsl_diu_fb.h b/roms/u-boot/include/fsl_diu_fb.h new file mode 100644 index 000000000..139851ba1 --- /dev/null +++ b/roms/u-boot/include/fsl_diu_fb.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2007, 2011 Freescale Semiconductor, Inc. + * Authors: York Sun + * Timur Tabi + * + * FSL DIU Framebuffer driver + */ + +int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix); + +/* Prototypes for external board-specific functions */ +int platform_diu_init(unsigned int xres, unsigned int yres, const char *port); +void diu_set_pixel_clock(unsigned int pixclock); diff --git a/roms/u-boot/include/fsl_dspi.h b/roms/u-boot/include/fsl_dspi.h new file mode 100644 index 000000000..4fec83549 --- /dev/null +++ b/roms/u-boot/include/fsl_dspi.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale DSPI Module Defines + * + * Copyright (C) 2004-2007, 2015 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * Chao Fu (B44548@freesacle.com) + * Haikun Wang (B53464@freescale.com) + */ + +#ifndef _FSL_DSPI_H_ +#define _FSL_DSPI_H_ + +/* DMA Serial Peripheral Interface (DSPI) */ +struct dspi { + u32 mcr; /* 0x00 */ + u32 resv0; /* 0x04 */ + u32 tcr; /* 0x08 */ + u32 ctar[8]; /* 0x0C - 0x28 */ + u32 sr; /* 0x2C */ + u32 irsr; /* 0x30 */ + u32 tfr; /* 0x34 - PUSHR */ + u32 rfr; /* 0x38 - POPR */ +#ifdef CONFIG_MCF547x_8x + u32 tfdr[4]; /* 0x3C */ + u8 resv2[0x30]; /* 0x40 */ + u32 rfdr[4]; /* 0x7C */ +#else + u32 tfdr[16]; /* 0x3C */ + u32 rfdr[16]; /* 0x7C */ +#endif +}; + +/* Module configuration */ +#define DSPI_MCR_MSTR 0x80000000 +#define DSPI_MCR_CSCK 0x40000000 +#define DSPI_MCR_DCONF(x) (((x) & 0x03) << 28) +#define DSPI_MCR_FRZ 0x08000000 +#define DSPI_MCR_MTFE 0x04000000 +#define DSPI_MCR_PCSSE 0x02000000 +#define DSPI_MCR_ROOE 0x01000000 +#define DSPI_MCR_PCSIS(x) (1 << (16 + (x))) +#define DSPI_MCR_PCSIS_MASK (0xff << 16) +#define DSPI_MCR_CSIS7 0x00800000 +#define DSPI_MCR_CSIS6 0x00400000 +#define DSPI_MCR_CSIS5 0x00200000 +#define DSPI_MCR_CSIS4 0x00100000 +#define DSPI_MCR_CSIS3 0x00080000 +#define DSPI_MCR_CSIS2 0x00040000 +#define DSPI_MCR_CSIS1 0x00020000 +#define DSPI_MCR_CSIS0 0x00010000 +#define DSPI_MCR_DOZE 0x00008000 +#define DSPI_MCR_MDIS 0x00004000 +#define DSPI_MCR_DTXF 0x00002000 +#define DSPI_MCR_DRXF 0x00001000 +#define DSPI_MCR_CTXF 0x00000800 +#define DSPI_MCR_CRXF 0x00000400 +#define DSPI_MCR_SMPL_PT(x) (((x) & 0x03) << 8) +#define DSPI_MCR_FCPCS 0x00000001 +#define DSPI_MCR_PES 0x00000001 +#define DSPI_MCR_HALT 0x00000001 + +/* Transfer count */ +#define DSPI_TCR_SPI_TCNT(x) (((x) & 0x0000FFFF) << 16) + +/* Clock and transfer attributes */ +#define DSPI_CTAR(x) (0x0c + (x * 4)) +#define DSPI_CTAR_DBR 0x80000000 +#define DSPI_CTAR_TRSZ(x) (((x) & 0x0F) << 27) +#define DSPI_CTAR_CPOL 0x04000000 +#define DSPI_CTAR_CPHA 0x02000000 +#define DSPI_CTAR_LSBFE 0x01000000 +#define DSPI_CTAR_PCSSCK(x) (((x) & 0x03) << 22) +#define DSPI_CTAR_PCSSCK_7CLK 0x00A00000 +#define DSPI_CTAR_PCSSCK_5CLK 0x00800000 +#define DSPI_CTAR_PCSSCK_3CLK 0x00400000 +#define DSPI_CTAR_PCSSCK_1CLK 0x00000000 +#define DSPI_CTAR_PASC(x) (((x) & 0x03) << 20) +#define DSPI_CTAR_PASC_7CLK 0x00300000 +#define DSPI_CTAR_PASC_5CLK 0x00200000 +#define DSPI_CTAR_PASC_3CLK 0x00100000 +#define DSPI_CTAR_PASC_1CLK 0x00000000 +#define DSPI_CTAR_PDT(x) (((x) & 0x03) << 18) +#define DSPI_CTAR_PDT_7CLK 0x000A0000 +#define DSPI_CTAR_PDT_5CLK 0x00080000 +#define DSPI_CTAR_PDT_3CLK 0x00040000 +#define DSPI_CTAR_PDT_1CLK 0x00000000 +#define DSPI_CTAR_PBR(x) (((x) & 0x03) << 16) +#define DSPI_CTAR_PBR_7CLK 0x00030000 +#define DSPI_CTAR_PBR_5CLK 0x00020000 +#define DSPI_CTAR_PBR_3CLK 0x00010000 +#define DSPI_CTAR_PBR_1CLK 0x00000000 +#define DSPI_CTAR_CSSCK(x) (((x) & 0x0F) << 12) +#define DSPI_CTAR_ASC(x) (((x) & 0x0F) << 8) +#define DSPI_CTAR_DT(x) (((x) & 0x0F) << 4) +#define DSPI_CTAR_BR(x) ((x) & 0x0F) +#define DSPI_CTAR_SCALE_BITS 0xf + +/* Status */ +#define DSPI_SR_TCF 0x80000000 +#define DSPI_SR_TXRXS 0x40000000 +#define DSPI_SR_EOQF 0x10000000 +#define DSPI_SR_TFUF 0x08000000 +#define DSPI_SR_TFFF 0x02000000 +#define DSPI_SR_RFOF 0x00080000 +#define DSPI_SR_RFDF 0x00020000 +#define DSPI_SR_TXCTR(x) (((x) & 0x0000F000) >> 12) +#define DSPI_SR_TXPTR(x) (((x) & 0x00000F00) >> 8) +#define DSPI_SR_RXCTR(x) (((x) & 0x000000F0) >> 4) +#define DSPI_SR_RXPTR(x) ((x) & 0x0000000F) + +/* DMA/interrupt request selct and enable */ +#define DSPI_IRSR_TCFE 0x80000000 +#define DSPI_IRSR_EOQFE 0x10000000 +#define DSPI_IRSR_TFUFE 0x08000000 +#define DSPI_IRSR_TFFFE 0x02000000 +#define DSPI_IRSR_TFFFS 0x01000000 +#define DSPI_IRSR_RFOFE 0x00080000 +#define DSPI_IRSR_RFDFE 0x00020000 +#define DSPI_IRSR_RFDFS 0x00010000 + +/* Transfer control - 32-bit access */ +#define DSPI_TFR_PCS(x) (((1 << x) & 0x0000003f) << 16) +#define DSPI_TFR_CONT 0x80000000 +#define DSPI_TFR_CTAS(x) (((x) & 0x07) << 28) +#define DSPI_TFR_EOQ 0x08000000 +#define DSPI_TFR_CTCNT 0x04000000 +#define DSPI_TFR_CS7 0x00800000 +#define DSPI_TFR_CS6 0x00400000 +#define DSPI_TFR_CS5 0x00200000 +#define DSPI_TFR_CS4 0x00100000 +#define DSPI_TFR_CS3 0x00080000 +#define DSPI_TFR_CS2 0x00040000 +#define DSPI_TFR_CS1 0x00020000 +#define DSPI_TFR_CS0 0x00010000 + +/* Transfer Fifo */ +#define DSPI_TFR_TXDATA(x) ((x) & 0x0000FFFF) + +/* Bit definitions and macros for DRFR */ +#define DSPI_RFR_RXDATA(x) ((x) & 0x0000FFFF) + +/* Bit definitions and macros for DTFDR group */ +#define DSPI_TFDR_TXDATA(x) ((x) & 0x0000FFFF) +#define DSPI_TFDR_TXCMD(x) (((x) & 0x0000FFFF) << 16) + +/* Bit definitions and macros for DRFDR group */ +#define DSPI_RFDR_RXDATA(x) ((x) & 0x0000FFFF) + +#endif /* _FSL_DSPI_H_ */ diff --git a/roms/u-boot/include/fsl_dtsec.h b/roms/u-boot/include/fsl_dtsec.h new file mode 100644 index 000000000..ccd6572ae --- /dev/null +++ b/roms/u-boot/include/fsl_dtsec.h @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + */ + +#ifndef __DTSEC_H__ +#define __DTSEC_H__ + +#include + +struct dtsec { + u32 tsec_id; /* controller ID and version */ + u32 tsec_id2; /* controller ID and configuration */ + u32 ievent; /* interrupt event */ + u32 imask; /* interrupt mask */ + u32 res0; + u32 ecntrl; /* ethernet control and configuration */ + u32 ptv; /* pause time value */ + u32 tbipa; /* TBI PHY address */ + u32 res1[8]; + u32 tctrl; /* Transmit control register */ + u32 res2[3]; + u32 rctrl; /* Receive control register */ + u32 res3[11]; + u32 igaddr[8]; /* Individual group address */ + u32 gaddr[8]; /* group address */ + u32 res4[16]; + u32 maccfg1; /* MAC configuration register 1 */ + u32 maccfg2; /* MAC configuration register 2 */ + u32 ipgifg; /* inter-packet/inter-frame gap */ + u32 hafdup; /* half-duplex control */ + u32 maxfrm; /* Maximum frame size */ + u32 res5[3]; + u32 miimcfg; /* MII management configuration */ + u32 miimcom; /* MII management command */ + u32 miimadd; /* MII management address */ + u32 miimcon; /* MII management control */ + u32 miimstat; /* MII management status */ + u32 miimind; /* MII management indicator */ + u32 res6; + u32 ifstat; /* Interface status */ + u32 macstnaddr1; /* MAC station address 1 */ + u32 macstnaddr2; /* MAC station address 2 */ + u32 res7[46]; + /* transmit and receive counter */ + u32 tr64; /* Tx and Rx 64 bytes frame */ + u32 tr127; /* Tx and Rx 65 to 127 bytes frame */ + u32 tr255; /* Tx and Rx 128 to 255 bytes frame */ + u32 tr511; /* Tx and Rx 256 to 511 bytes frame */ + u32 tr1k; /* Tx and Rx 512 to 1023 bytes frame */ + u32 trmax; /* Tx and Rx 1024 to 1518 bytes frame */ + u32 trmgv; /* Tx and Rx 1519 to 1522 good VLAN frame */ + /* receive counters */ + u32 rbyt; /* Receive byte counter */ + u32 rpkt; /* Receive packet counter */ + u32 rfcs; /* Receive FCS error */ + u32 rmca; /* Receive multicast packet */ + u32 rbca; /* Receive broadcast packet */ + u32 rxcf; /* Receive control frame */ + u32 rxpf; /* Receive pause frame */ + u32 rxuo; /* Receive unknown OP code */ + u32 raln; /* Receive alignment error */ + u32 rflr; /* Receive frame length error */ + u32 rcde; /* Receive code error */ + u32 rcse; /* Receive carrier sense error */ + u32 rund; /* Receive undersize packet */ + u32 rovr; /* Receive oversize packet */ + u32 rfrg; /* Receive fragments counter */ + u32 rjbr; /* Receive jabber counter */ + u32 rdrp; /* Receive drop counter */ + /* transmit counters */ + u32 tbyt; /* Transmit byte counter */ + u32 tpkt; /* Transmit packet */ + u32 tmca; /* Transmit multicast packet */ + u32 tbca; /* Transmit broadcast packet */ + u32 txpf; /* Transmit pause control frame */ + u32 tdfr; /* Transmit deferral packet */ + u32 tedf; /* Transmit excessive deferral pkt */ + u32 tscl; /* Transmit single collision pkt */ + u32 tmcl; /* Transmit multiple collision pkt */ + u32 tlcl; /* Transmit late collision pkt */ + u32 txcl; /* Transmit excessive collision */ + u32 tncl; /* Transmit total collision */ + u32 res8; + u32 tdrp; /* Transmit drop frame */ + u32 tjbr; /* Transmit jabber frame */ + u32 tfcs; /* Transmit FCS error */ + u32 txcf; /* Transmit control frame */ + u32 tovr; /* Transmit oversize frame */ + u32 tund; /* Transmit undersize frame */ + u32 tfrg; /* Transmit fragments frame */ + /* counter controls */ + u32 car1; /* carry register 1 */ + u32 car2; /* carry register 2 */ + u32 cam1; /* carry register 1 mask */ + u32 cam2; /* carry register 2 mask */ + u32 res9[80]; +}; + + +/* TBI register addresses */ +#define TBI_CR 0x00 +#define TBI_SR 0x01 +#define TBI_ANA 0x04 +#define TBI_ANLPBPA 0x05 +#define TBI_ANEX 0x06 +#define TBI_TBICON 0x11 + +/* TBI MDIO register bit fields*/ +#define TBICON_CLK_SELECT 0x0020 +#define TBIANA_ASYMMETRIC_PAUSE 0x0100 +#define TBIANA_SYMMETRIC_PAUSE 0x0080 +#define TBIANA_HALF_DUPLEX 0x0040 +#define TBIANA_FULL_DUPLEX 0x0020 +#define TBICR_PHY_RESET 0x8000 +#define TBICR_ANEG_ENABLE 0x1000 +#define TBICR_RESTART_ANEG 0x0200 +#define TBICR_FULL_DUPLEX 0x0100 +#define TBICR_SPEED1_SET 0x0040 + +/* IEVENT - interrupt events register */ +#define IEVENT_BABR 0x80000000 /* Babbling receive error */ +#define IEVENT_RXC 0x40000000 /* pause control frame received */ +#define IEVENT_MSRO 0x04000000 /* MIB counter overflow */ +#define IEVENT_GTSC 0x02000000 /* Graceful transmit stop complete */ +#define IEVENT_BABT 0x01000000 /* Babbling transmit error */ +#define IEVENT_TXC 0x00800000 /* control frame transmitted */ +#define IEVENT_TXE 0x00400000 /* Transmit channel error */ +#define IEVENT_LC 0x00040000 /* Late collision occurred */ +#define IEVENT_CRL 0x00020000 /* Collision retry exceed limit */ +#define IEVENT_XFUN 0x00010000 /* Transmit FIFO underrun */ +#define IEVENT_ABRT 0x00008000 /* Transmit packet abort */ +#define IEVENT_MMRD 0x00000400 /* MII management read complete */ +#define IEVENT_MMWR 0x00000200 /* MII management write complete */ +#define IEVENT_GRSC 0x00000100 /* Graceful stop complete */ +#define IEVENT_TDPE 0x00000002 /* Internal data parity error on Tx */ +#define IEVENT_RDPE 0x00000001 /* Internal data parity error on Rx */ + +#define IEVENT_CLEAR_ALL 0xffffffff + +/* IMASK - interrupt mask register */ +#define IMASK_BREN 0x80000000 /* Babbling receive enable */ +#define IMASK_RXCEN 0x40000000 /* receive control enable */ +#define IMASK_MSROEN 0x04000000 /* MIB counter overflow enable */ +#define IMASK_GTSCEN 0x02000000 /* Graceful Tx stop complete enable */ +#define IMASK_BTEN 0x01000000 /* Babbling transmit error enable */ +#define IMASK_TXCEN 0x00800000 /* control frame transmitted enable */ +#define IMASK_TXEEN 0x00400000 /* Transmit channel error enable */ +#define IMASK_LCEN 0x00040000 /* Late collision interrupt enable */ +#define IMASK_CRLEN 0x00020000 /* Collision retry exceed limit */ +#define IMASK_XFUNEN 0x00010000 /* Transmit FIFO underrun enable */ +#define IMASK_ABRTEN 0x00008000 /* Transmit packet abort enable */ +#define IMASK_MMRDEN 0x00000400 /* MII management read complete enable */ +#define IMASK_MMWREN 0x00000200 /* MII management write complete enable */ +#define IMASK_GRSCEN 0x00000100 /* Graceful stop complete interrupt enable */ +#define IMASK_TDPEEN 0x00000002 /* Internal data parity error on Tx enable */ +#define IMASK_RDPEEN 0x00000001 /* Internal data parity error on Rx enable */ + +#define IMASK_MASK_ALL 0x00000000 + +/* ECNTRL - ethernet control register */ +#define ECNTRL_CFG_RO 0x80000000 /* GMIIM, RPM, R100M, SGMIIM bits are RO */ +#define ECNTRL_CLRCNT 0x00004000 /* clear all statistics */ +#define ECNTRL_AUTOZ 0x00002000 /* auto zero MIB counter */ +#define ECNTRL_STEN 0x00001000 /* enable internal counters to update */ +#define ECNTRL_GMIIM 0x00000040 /* 1- GMII or RGMII interface mode */ +#define ECNTRL_TBIM 0x00000020 /* 1- Ten-bit interface mode */ +#define ECNTRL_RPM 0x00000010 /* 1- RGMII reduced-pin mode */ +#define ECNTRL_R100M 0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps + 0- RGMII 10 Mbps, SGMII 10 Mbps */ +#define ECNTRL_SGMIIM 0x00000002 /* 1- SGMII interface mode */ +#define ECNTRL_TBIM 0x00000020 /* 1- TBI Interface mode (for SGMII) */ + +#define ECNTRL_DEFAULT (ECNTRL_TBIM | ECNTRL_R100M | ECNTRL_SGMIIM) + +/* TCTRL - Transmit control register */ +#define TCTRL_THDF 0x00000800 /* Transmit half-duplex flow control */ +#define TCTRL_TTSE 0x00000040 /* Transmit time-stamp enable */ +#define TCTRL_GTS 0x00000020 /* Graceful transmit stop */ +#define TCTRL_RFC_PAUSE 0x00000010 /* Receive flow control pause frame */ + +/* RCTRL - Receive control register */ +#define RCTRL_PAL_MASK 0x001f0000 /* packet alignment padding length */ +#define RCTRL_PAL_SHIFT 16 +#define RCTRL_CFA 0x00008000 /* control frame accept enable */ +#define RCTRL_GHTX 0x00000800 /* group address hash table extend */ +#define RCTRL_RTSE 0x00000040 /* receive 1588 time-stamp enable */ +#define RCTRL_GRS 0x00000020 /* graceful receive stop */ +#define RCTRL_BC_REJ 0x00000010 /* broadcast frame reject */ +#define RCTRL_BC_MPROM 0x00000008 /* all multicast/broadcast frames received */ +#define RCTRL_RSF 0x00000004 /* receive short frame(17~63 bytes) enable */ +#define RCTRL_EMEN 0x00000002 /* Exact match MAC address enable */ +#define RCTRL_UPROM 0x00000001 /* all unicast frame received */ + +/* MACCFG1 - MAC configuration 1 register */ +#define MACCFG1_SOFT_RST 0x80000000 /* place the MAC in reset */ +#define MACCFG1_RST_RXMAC 0x00080000 /* reset receive MAC control block */ +#define MACCFG1_RST_TXMAC 0x00040000 /* reet transmit MAC control block */ +#define MACCFG1_RST_RXFUN 0x00020000 /* reset receive function block */ +#define MACCFG1_RST_TXFUN 0x00010000 /* reset transmit function block */ +#define MACCFG1_LOOPBACK 0x00000100 /* MAC loopback */ +#define MACCFG1_RX_FLOW 0x00000020 /* Receive flow */ +#define MACCFG1_TX_FLOW 0x00000010 /* Transmit flow */ +#define MACCFG1_SYNC_RXEN 0x00000008 /* Frame reception enabled */ +#define MACCFG1_RX_EN 0x00000004 /* Rx enable */ +#define MACCFG1_SYNC_TXEN 0x00000002 /* Frame transmission is enabled */ +#define MACCFG1_TX_EN 0x00000001 /* Tx enable */ +#define MACCFG1_RXTX_EN (MACCFG1_RX_EN | MACCFG1_TX_EN) + +/* MACCFG2 - MAC configuration 2 register */ +#define MACCFG2_PRE_LEN_MASK 0x0000f000 /* preamble length */ +#define MACCFG2_PRE_LEN(x) ((x << 12) & MACCFG2_PRE_LEN_MASK) +#define MACCFG2_IF_MODE_MASK 0x00000300 +#define MACCFG2_IF_MODE_NIBBLE 0x00000100 /* MII, 10/100 Mbps MII/RMII */ +#define MACCFG2_IF_MODE_BYTE 0x00000200 /* GMII/TBI, 1000 GMII/TBI */ +#define MACCFG2_PRE_RX_EN 0x00000080 /* receive preamble enable */ +#define MACCFG2_PRE_TX_EN 0x00000040 /* tx preable enable */ +#define MACCFG2_HUGE_FRAME 0x00000020 /* >= max frame len enable */ +#define MACCFG2_LEN_CHECK 0x00000010 /* MAC check frame's length Rx */ +#define MACCFG2_MAG_EN 0x00000008 /* magic packet enable */ +#define MACCFG2_PAD_CRC 0x00000004 /* pad and append CRC */ +#define MACCFG2_CRC_EN 0x00000002 /* MAC appends a CRC on all frames */ +#define MACCFG2_FULL_DUPLEX 0x00000001 /* Full deplex mode */ + +struct fsl_enet_mac; + +void init_dtsec(struct fsl_enet_mac *mac, void *base, void *phyregs, + int max_rx_len); + +#endif diff --git a/roms/u-boot/include/fsl_errata.h b/roms/u-boot/include/fsl_errata.h new file mode 100644 index 000000000..88f426865 --- /dev/null +++ b/roms/u-boot/include/fsl_errata.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 - 2015 Freescale Semiconductor, Inc. + */ + +#ifndef _FSL_ERRATA_H +#define _FSL_ERRATA_H + +#include +#if defined(CONFIG_PPC) +#include +#elif defined(CONFIG_ARCH_LS1021A) +#include +#elif defined(CONFIG_FSL_LAYERSCAPE) +#include +#endif + + +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 +static inline bool has_erratum_a006379(void) +{ + u32 svr = get_svr(); + if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) || + ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) || + ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1)) + return true; + + return false; +} +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007186 +static inline bool has_erratum_a007186(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_T4240: + return IS_SVR_REV(svr, 2, 0); + case SVR_T4160: + return IS_SVR_REV(svr, 2, 0); + case SVR_B4860: + return IS_SVR_REV(svr, 2, 0); + case SVR_B4420: + return IS_SVR_REV(svr, 2, 0); + case SVR_T2081: + case SVR_T2080: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); + } + + return false; +} +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008378 +static inline bool has_erratum_a008378(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + + switch (soc) { +#ifdef CONFIG_ARCH_LS1021A + case SOC_VER_LS1020: + case SOC_VER_LS1021: + case SOC_VER_LS1022: + case SOC_VER_SLS1020: + return IS_SVR_REV(svr, 1, 0); +#endif +#ifdef CONFIG_PPC + case SVR_T1023: + case SVR_T1024: + return IS_SVR_REV(svr, 1, 0); + case SVR_T1020: + case SVR_T1022: + case SVR_T1040: + case SVR_T1042: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); +#endif + default: + return false; + } +} +#endif + +#endif /* _FSL_ERRATA_H */ diff --git a/roms/u-boot/include/fsl_esdhc.h b/roms/u-boot/include/fsl_esdhc.h new file mode 100644 index 000000000..f86afe5da --- /dev/null +++ b/roms/u-boot/include/fsl_esdhc.h @@ -0,0 +1,259 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * FSL SD/MMC Defines + *------------------------------------------------------------------- + * + * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc + * Copyright 2020 NXP + */ + +#ifndef __FSL_ESDHC_H__ +#define __FSL_ESDHC_H__ + +#include +#include + +/* needed for the mmc_cfg definition */ +#include + +/* FSL eSDHC-specific constants */ +#define SYSCTL 0x0002e02c +#define SYSCTL_INITA 0x08000000 +#define SYSCTL_TIMEOUT_MASK 0x000f0000 +#define SYSCTL_CLOCK_MASK 0x0000fff0 +#define SYSCTL_CKEN 0x00000008 +#define SYSCTL_PEREN 0x00000004 +#define SYSCTL_HCKEN 0x00000002 +#define SYSCTL_IPGEN 0x00000001 +#define SYSCTL_RSTA 0x01000000 +#define SYSCTL_RSTC 0x02000000 +#define SYSCTL_RSTD 0x04000000 + +#define IRQSTAT 0x0002e030 +#define IRQSTAT_DMAE (0x10000000) +#define IRQSTAT_AC12E (0x01000000) +#define IRQSTAT_DEBE (0x00400000) +#define IRQSTAT_DCE (0x00200000) +#define IRQSTAT_DTOE (0x00100000) +#define IRQSTAT_CIE (0x00080000) +#define IRQSTAT_CEBE (0x00040000) +#define IRQSTAT_CCE (0x00020000) +#define IRQSTAT_CTOE (0x00010000) +#define IRQSTAT_CINT (0x00000100) +#define IRQSTAT_CRM (0x00000080) +#define IRQSTAT_CINS (0x00000040) +#define IRQSTAT_BRR (0x00000020) +#define IRQSTAT_BWR (0x00000010) +#define IRQSTAT_DINT (0x00000008) +#define IRQSTAT_BGE (0x00000004) +#define IRQSTAT_TC (0x00000002) +#define IRQSTAT_CC (0x00000001) + +#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE) +#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \ + IRQSTAT_DMAE) +#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT) + +#define IRQSTATEN 0x0002e034 +#define IRQSTATEN_DMAE (0x10000000) +#define IRQSTATEN_AC12E (0x01000000) +#define IRQSTATEN_DEBE (0x00400000) +#define IRQSTATEN_DCE (0x00200000) +#define IRQSTATEN_DTOE (0x00100000) +#define IRQSTATEN_CIE (0x00080000) +#define IRQSTATEN_CEBE (0x00040000) +#define IRQSTATEN_CCE (0x00020000) +#define IRQSTATEN_CTOE (0x00010000) +#define IRQSTATEN_CINT (0x00000100) +#define IRQSTATEN_CRM (0x00000080) +#define IRQSTATEN_CINS (0x00000040) +#define IRQSTATEN_BRR (0x00000020) +#define IRQSTATEN_BWR (0x00000010) +#define IRQSTATEN_DINT (0x00000008) +#define IRQSTATEN_BGE (0x00000004) +#define IRQSTATEN_TC (0x00000002) +#define IRQSTATEN_CC (0x00000001) + +/* eSDHC control register */ +#define ESDHCCTL 0x0002e40c +#define ESDHCCTL_PCS (0x00080000) +#define ESDHCCTL_FAF (0x00040000) + +#define PRSSTAT 0x0002e024 +#define PRSSTAT_DAT0 (0x01000000) +#define PRSSTAT_CLSL (0x00800000) +#define PRSSTAT_WPSPL (0x00080000) +#define PRSSTAT_CDPL (0x00040000) +#define PRSSTAT_CINS (0x00010000) +#define PRSSTAT_BREN (0x00000800) +#define PRSSTAT_BWEN (0x00000400) +#define PRSSTAT_SDSTB (0X00000008) +#define PRSSTAT_DLA (0x00000004) +#define PRSSTAT_CICHB (0x00000002) +#define PRSSTAT_CIDHB (0x00000001) + +#define PROCTL 0x0002e028 +#define PROCTL_INIT 0x00000020 +#define PROCTL_DTW_4 0x00000002 +#define PROCTL_DTW_8 0x00000004 +#define PROCTL_D3CD 0x00000008 +#define PROCTL_DMAS_MASK 0x00000300 +#define PROCTL_DMAS_SDMA 0x00000000 +#define PROCTL_DMAS_ADMA1 0x00000100 +#define PROCTL_DMAS_ADMA2 0x00000300 +#define PROCTL_VOLT_SEL 0x00000400 + +#define CMDARG 0x0002e008 + +#define XFERTYP 0x0002e00c +#define XFERTYP_CMD(x) ((x & 0x3f) << 24) +#define XFERTYP_CMDTYP_NORMAL 0x0 +#define XFERTYP_CMDTYP_SUSPEND 0x00400000 +#define XFERTYP_CMDTYP_RESUME 0x00800000 +#define XFERTYP_CMDTYP_ABORT 0x00c00000 +#define XFERTYP_DPSEL 0x00200000 +#define XFERTYP_CICEN 0x00100000 +#define XFERTYP_CCCEN 0x00080000 +#define XFERTYP_RSPTYP_NONE 0 +#define XFERTYP_RSPTYP_136 0x00010000 +#define XFERTYP_RSPTYP_48 0x00020000 +#define XFERTYP_RSPTYP_48_BUSY 0x00030000 +#define XFERTYP_MSBSEL 0x00000020 +#define XFERTYP_DTDSEL 0x00000010 +#define XFERTYP_DDREN 0x00000008 +#define XFERTYP_AC12EN 0x00000004 +#define XFERTYP_BCEN 0x00000002 +#define XFERTYP_DMAEN 0x00000001 + +#define CINS_TIMEOUT 1000 +#define PIO_TIMEOUT 500 + +#define DSADDR 0x2e004 + +#define CMDRSP0 0x2e010 +#define CMDRSP1 0x2e014 +#define CMDRSP2 0x2e018 +#define CMDRSP3 0x2e01c + +#define DATPORT 0x2e020 + +#define WML 0x2e044 +#define WML_WRITE 0x00010000 +#ifdef CONFIG_FSL_SDHC_V2_3 +#define WML_RD_WML_MAX 0x80 +#define WML_WR_WML_MAX 0x80 +#define WML_RD_WML_MAX_VAL 0x0 +#define WML_WR_WML_MAX_VAL 0x0 +#define WML_RD_WML_MASK 0x7f +#define WML_WR_WML_MASK 0x7f0000 +#else +#define WML_RD_WML_MAX 0x10 +#define WML_WR_WML_MAX 0x80 +#define WML_RD_WML_MAX_VAL 0x10 +#define WML_WR_WML_MAX_VAL 0x80 +#define WML_RD_WML_MASK 0xff +#define WML_WR_WML_MASK 0xff0000 +#endif + +#define BLKATTR 0x2e004 +#define BLKATTR_CNT(x) ((x & 0xffff) << 16) +#define BLKATTR_SIZE(x) (x & 0x1fff) +#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */ + +/* Auto CMD error status register / system control 2 register */ +#define EXECUTE_TUNING 0x00400000 +#define SMPCLKSEL 0x00800000 +#define UHSM_MASK 0x00070000 +#define UHSM_SDR104_HS200 0x00030000 + +/* Host controller capabilities register */ +#define HOSTCAPBLT_VS18 0x04000000 +#define HOSTCAPBLT_VS30 0x02000000 +#define HOSTCAPBLT_VS33 0x01000000 +#define HOSTCAPBLT_SRS 0x00800000 +#define HOSTCAPBLT_DMAS 0x00400000 +#define HOSTCAPBLT_HSS 0x00200000 + +/* Tuning block control register */ +#define TBCTL_TB_EN 0x00000004 +#define HS400_MODE 0x00000010 +#define HS400_WNDW_ADJUST 0x00000040 + +/* SD clock control register */ +#define CMD_CLK_CTL 0x00008000 + +/* SD timing control register */ +#define FLW_CTL_BG 0x00008000 + +/* DLL config 0 register */ +#define DLL_ENABLE 0x80000000 +#define DLL_RESET 0x40000000 +#define DLL_FREQ_SEL 0x08000000 + +/* DLL config 1 register */ +#define DLL_PD_PULSE_STRETCH_SEL 0x80000000 + +/* DLL status 0 register */ +#define DLL_STS_SLV_LOCK 0x08000000 + +#define MAX_TUNING_LOOP 40 + +#define HOSTVER_VENDOR(x) (((x) >> 8) & 0xff) +#define VENDOR_V_10 0x00 +#define VENDOR_V_20 0x10 +#define VENDOR_V_21 0x11 +#define VENDOR_V_22 0x12 +#define VENDOR_V_23 0x13 +#define VENDOR_V_30 0x20 +#define VENDOR_V_31 0x21 +#define VENDOR_V_32 0x22 + +struct fsl_esdhc_cfg { + phys_addr_t esdhc_base; + u32 sdhc_clk; + u8 max_bus_width; + int vs18_enable; /* Use 1.8V if set to 1 */ + struct mmc_config cfg; +}; + +/* Select the correct accessors depending on endianess */ +#if defined CONFIG_SYS_FSL_ESDHC_LE +#define esdhc_read32 in_le32 +#define esdhc_write32 out_le32 +#define esdhc_clrsetbits32 clrsetbits_le32 +#define esdhc_clrbits32 clrbits_le32 +#define esdhc_setbits32 setbits_le32 +#elif defined(CONFIG_SYS_FSL_ESDHC_BE) +#define esdhc_read32 in_be32 +#define esdhc_write32 out_be32 +#define esdhc_clrsetbits32 clrsetbits_be32 +#define esdhc_clrbits32 clrbits_be32 +#define esdhc_setbits32 setbits_be32 +#elif __BYTE_ORDER == __LITTLE_ENDIAN +#define esdhc_read32 in_le32 +#define esdhc_write32 out_le32 +#define esdhc_clrsetbits32 clrsetbits_le32 +#define esdhc_clrbits32 clrbits_le32 +#define esdhc_setbits32 setbits_le32 +#elif __BYTE_ORDER == __BIG_ENDIAN +#define esdhc_read32 in_be32 +#define esdhc_write32 out_be32 +#define esdhc_clrsetbits32 clrsetbits_be32 +#define esdhc_clrbits32 clrbits_be32 +#define esdhc_setbits32 setbits_be32 +#else +#error "Endianess is not defined: please fix to continue" +#endif + +#ifdef CONFIG_FSL_ESDHC +int fsl_esdhc_mmc_init(struct bd_info *bis); +int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg); +void fdt_fixup_esdhc(void *blob, struct bd_info *bd); +#else +static inline int fsl_esdhc_mmc_init(struct bd_info *bis) { return -ENOSYS; } +static inline void fdt_fixup_esdhc(void *blob, struct bd_info *bd) {} +#endif /* CONFIG_FSL_ESDHC */ +void __noreturn mmc_boot(void); +void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst); + +#endif /* __FSL_ESDHC_H__ */ diff --git a/roms/u-boot/include/fsl_esdhc_imx.h b/roms/u-boot/include/fsl_esdhc_imx.h new file mode 100644 index 000000000..45ed635a7 --- /dev/null +++ b/roms/u-boot/include/fsl_esdhc_imx.h @@ -0,0 +1,272 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * FSL SD/MMC Defines + *------------------------------------------------------------------- + * + * Copyright 2019 NXP + * Yangbo Lu + * + * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc + */ + +#ifndef __FSL_ESDHC_IMX_H__ +#define __FSL_ESDHC_IMX_H__ + +#include +#include +#include + +/* needed for the mmc_cfg definition */ +#include + +/* FSL eSDHC-specific constants */ +#define SYSCTL 0x0002e02c +#define SYSCTL_INITA 0x08000000 +#define SYSCTL_TIMEOUT_MASK 0x000f0000 +#define SYSCTL_CLOCK_MASK 0x0000fff0 +#if !defined(CONFIG_FSL_USDHC) +#define SYSCTL_CKEN 0x00000008 +#define SYSCTL_PEREN 0x00000004 +#define SYSCTL_HCKEN 0x00000002 +#define SYSCTL_IPGEN 0x00000001 +#endif +#define SYSCTL_RSTA 0x01000000 +#define SYSCTL_RSTC 0x02000000 +#define SYSCTL_RSTD 0x04000000 + +#define VENDORSPEC_CKEN 0x00004000 +#define VENDORSPEC_PEREN 0x00002000 +#define VENDORSPEC_HCKEN 0x00001000 +#define VENDORSPEC_IPGEN 0x00000800 +#define VENDORSPEC_INIT 0x20007809 + +#define IRQSTAT 0x0002e030 +#define IRQSTAT_DMAE (0x10000000) +#define IRQSTAT_AC12E (0x01000000) +#define IRQSTAT_DEBE (0x00400000) +#define IRQSTAT_DCE (0x00200000) +#define IRQSTAT_DTOE (0x00100000) +#define IRQSTAT_CIE (0x00080000) +#define IRQSTAT_CEBE (0x00040000) +#define IRQSTAT_CCE (0x00020000) +#define IRQSTAT_CTOE (0x00010000) +#define IRQSTAT_CINT (0x00000100) +#define IRQSTAT_CRM (0x00000080) +#define IRQSTAT_CINS (0x00000040) +#define IRQSTAT_BRR (0x00000020) +#define IRQSTAT_BWR (0x00000010) +#define IRQSTAT_DINT (0x00000008) +#define IRQSTAT_BGE (0x00000004) +#define IRQSTAT_TC (0x00000002) +#define IRQSTAT_CC (0x00000001) + +#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE) +#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \ + IRQSTAT_DMAE) +#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT) + +#define IRQSTATEN 0x0002e034 +#define IRQSTATEN_DMAE (0x10000000) +#define IRQSTATEN_AC12E (0x01000000) +#define IRQSTATEN_DEBE (0x00400000) +#define IRQSTATEN_DCE (0x00200000) +#define IRQSTATEN_DTOE (0x00100000) +#define IRQSTATEN_CIE (0x00080000) +#define IRQSTATEN_CEBE (0x00040000) +#define IRQSTATEN_CCE (0x00020000) +#define IRQSTATEN_CTOE (0x00010000) +#define IRQSTATEN_CINT (0x00000100) +#define IRQSTATEN_CRM (0x00000080) +#define IRQSTATEN_CINS (0x00000040) +#define IRQSTATEN_BRR (0x00000020) +#define IRQSTATEN_BWR (0x00000010) +#define IRQSTATEN_DINT (0x00000008) +#define IRQSTATEN_BGE (0x00000004) +#define IRQSTATEN_TC (0x00000002) +#define IRQSTATEN_CC (0x00000001) + +#define ESDHCCTL 0x0002e40c +#define ESDHCCTL_PCS (0x00080000) + +#define PRSSTAT 0x0002e024 +#define PRSSTAT_DAT0 (0x01000000) +#define PRSSTAT_CLSL (0x00800000) +#define PRSSTAT_WPSPL (0x00080000) +#define PRSSTAT_CDPL (0x00040000) +#define PRSSTAT_CINS (0x00010000) +#define PRSSTAT_BREN (0x00000800) +#define PRSSTAT_BWEN (0x00000400) +#define PRSSTAT_SDSTB (0X00000008) +#define PRSSTAT_DLA (0x00000004) +#define PRSSTAT_CICHB (0x00000002) +#define PRSSTAT_CIDHB (0x00000001) + +#define PROCTL 0x0002e028 +#define PROCTL_INIT 0x00000020 +#define PROCTL_DTW_4 0x00000002 +#define PROCTL_DTW_8 0x00000004 +#define PROCTL_D3CD 0x00000008 + +#define CMDARG 0x0002e008 + +#define XFERTYP 0x0002e00c +#define XFERTYP_CMD(x) ((x & 0x3f) << 24) +#define XFERTYP_CMDTYP_NORMAL 0x0 +#define XFERTYP_CMDTYP_SUSPEND 0x00400000 +#define XFERTYP_CMDTYP_RESUME 0x00800000 +#define XFERTYP_CMDTYP_ABORT 0x00c00000 +#define XFERTYP_DPSEL 0x00200000 +#define XFERTYP_CICEN 0x00100000 +#define XFERTYP_CCCEN 0x00080000 +#define XFERTYP_RSPTYP_NONE 0 +#define XFERTYP_RSPTYP_136 0x00010000 +#define XFERTYP_RSPTYP_48 0x00020000 +#define XFERTYP_RSPTYP_48_BUSY 0x00030000 +#define XFERTYP_MSBSEL 0x00000020 +#define XFERTYP_DTDSEL 0x00000010 +#define XFERTYP_DDREN 0x00000008 +#define XFERTYP_AC12EN 0x00000004 +#define XFERTYP_BCEN 0x00000002 +#define XFERTYP_DMAEN 0x00000001 + +#define CINS_TIMEOUT 1000 +#define PIO_TIMEOUT 500 + +#define DSADDR 0x2e004 + +#define CMDRSP0 0x2e010 +#define CMDRSP1 0x2e014 +#define CMDRSP2 0x2e018 +#define CMDRSP3 0x2e01c + +#define DATPORT 0x2e020 + +#define WML 0x2e044 +#define WML_WRITE 0x00010000 +#ifdef CONFIG_FSL_SDHC_V2_3 +#define WML_RD_WML_MAX 0x80 +#define WML_WR_WML_MAX 0x80 +#define WML_RD_WML_MAX_VAL 0x0 +#define WML_WR_WML_MAX_VAL 0x0 +#define WML_RD_WML_MASK 0x7f +#define WML_WR_WML_MASK 0x7f0000 +#else +#define WML_RD_WML_MAX 0x10 +#define WML_WR_WML_MAX 0x80 +#define WML_RD_WML_MAX_VAL 0x10 +#define WML_WR_WML_MAX_VAL 0x80 +#define WML_RD_WML_MASK 0xff +#define WML_WR_WML_MASK 0xff0000 +#endif + +#define BLKATTR 0x2e004 +#define BLKATTR_CNT(x) ((x & 0xffff) << 16) +#define BLKATTR_SIZE(x) (x & 0x1fff) +#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */ + +#define ESDHC_HOSTCAPBLT_VS18 0x04000000 +#define ESDHC_HOSTCAPBLT_VS30 0x02000000 +#define ESDHC_HOSTCAPBLT_VS33 0x01000000 +#define ESDHC_HOSTCAPBLT_SRS 0x00800000 +#define ESDHC_HOSTCAPBLT_DMAS 0x00400000 +#define ESDHC_HOSTCAPBLT_HSS 0x00200000 + +#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */ + +/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */ +#define MIX_CTRL_DDREN BIT(3) +#define MIX_CTRL_DTDSEL_READ BIT(4) +#define MIX_CTRL_AC23EN BIT(7) +#define MIX_CTRL_EXE_TUNE BIT(22) +#define MIX_CTRL_SMPCLK_SEL BIT(23) +#define MIX_CTRL_AUTO_TUNE_EN BIT(24) +#define MIX_CTRL_FBCLK_SEL BIT(25) +#define MIX_CTRL_HS400_EN BIT(26) +#define MIX_CTRL_HS400_ES BIT(27) +/* Bits 3 and 6 are not SDHCI standard definitions */ +#define MIX_CTRL_SDHCI_MASK 0xb7 +/* Tuning bits */ +#define MIX_CTRL_TUNING_MASK 0x03c00000 + +/* strobe dll register */ +#define ESDHC_STROBE_DLL_CTRL 0x70 +#define ESDHC_STROBE_DLL_CTRL_ENABLE BIT(0) +#define ESDHC_STROBE_DLL_CTRL_RESET BIT(1) +#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7 +#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 + +#define ESDHC_STROBE_DLL_STATUS 0x74 +#define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1) +#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 +#define ESDHC_STROBE_DLL_CLK_FREQ 100000000 + +#define ESDHC_STD_TUNING_EN BIT(24) +/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ +#define ESDHC_TUNING_START_TAP_DEFAULT 0x1 +#define ESDHC_TUNING_START_TAP_MASK 0x7f +#define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE BIT(7) +#define ESDHC_TUNING_STEP_MASK 0x00070000 +#define ESDHC_TUNING_STEP_SHIFT 16 + +#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) +#define ESDHC_FLAG_ENGCM07207 BIT(2) +#define ESDHC_FLAG_USDHC BIT(3) +#define ESDHC_FLAG_MAN_TUNING BIT(4) +#define ESDHC_FLAG_STD_TUNING BIT(5) +#define ESDHC_FLAG_HAVE_CAP1 BIT(6) +#define ESDHC_FLAG_ERR004536 BIT(7) +#define ESDHC_FLAG_HS200 BIT(8) +#define ESDHC_FLAG_HS400 BIT(9) +#define ESDHC_FLAG_ERR010450 BIT(10) +#define ESDHC_FLAG_HS400_ES BIT(11) + +struct fsl_esdhc_cfg { + phys_addr_t esdhc_base; + u32 sdhc_clk; + u8 max_bus_width; + int wp_enable; + int vs18_enable; /* Use 1.8V if set to 1 */ + struct mmc_config cfg; +}; + +/* Select the correct accessors depending on endianess */ +#if defined CONFIG_SYS_FSL_ESDHC_LE +#define esdhc_read32 in_le32 +#define esdhc_write32 out_le32 +#define esdhc_clrsetbits32 clrsetbits_le32 +#define esdhc_clrbits32 clrbits_le32 +#define esdhc_setbits32 setbits_le32 +#elif defined(CONFIG_SYS_FSL_ESDHC_BE) +#define esdhc_read32 in_be32 +#define esdhc_write32 out_be32 +#define esdhc_clrsetbits32 clrsetbits_be32 +#define esdhc_clrbits32 clrbits_be32 +#define esdhc_setbits32 setbits_be32 +#elif __BYTE_ORDER == __LITTLE_ENDIAN +#define esdhc_read32 in_le32 +#define esdhc_write32 out_le32 +#define esdhc_clrsetbits32 clrsetbits_le32 +#define esdhc_clrbits32 clrbits_le32 +#define esdhc_setbits32 setbits_le32 +#elif __BYTE_ORDER == __BIG_ENDIAN +#define esdhc_read32 in_be32 +#define esdhc_write32 out_be32 +#define esdhc_clrsetbits32 clrsetbits_be32 +#define esdhc_clrbits32 clrbits_be32 +#define esdhc_setbits32 setbits_be32 +#else +#error "Endianess is not defined: please fix to continue" +#endif + +#ifdef CONFIG_FSL_ESDHC_IMX +int fsl_esdhc_mmc_init(struct bd_info *bis); +int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg); +void fdt_fixup_esdhc(void *blob, struct bd_info *bd); +#else +static inline int fsl_esdhc_mmc_init(struct bd_info *bis) { return -ENOSYS; } +static inline void fdt_fixup_esdhc(void *blob, struct bd_info *bd) {} +#endif /* CONFIG_FSL_ESDHC_IMX */ +void __noreturn mmc_boot(void); +void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst); + +#endif /* __FSL_ESDHC_IMX_H__ */ diff --git a/roms/u-boot/include/fsl_fman.h b/roms/u-boot/include/fsl_fman.h new file mode 100644 index 000000000..74acdb256 --- /dev/null +++ b/roms/u-boot/include/fsl_fman.h @@ -0,0 +1,463 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * MPC85xx Internal Memory Map + * + * Copyright 2010-2011 Freescale Semiconductor, Inc. + */ + +#ifndef __FSL_FMAN_H__ +#define __FSL_FMAN_H__ + +#include + +typedef struct fm_bmi_common { + u32 fmbm_init; /* BMI initialization */ + u32 fmbm_cfg1; /* BMI configuration1 */ + u32 fmbm_cfg2; /* BMI configuration2 */ + u32 res0[0x5]; + u32 fmbm_ievr; /* interrupt event register */ + u32 fmbm_ier; /* interrupt enable register */ + u32 fmbm_ifr; /* interrupt force register */ + u32 res1[0x5]; + u32 fmbm_arb[0x8]; /* BMI arbitration */ + u32 res2[0x28]; + u32 fmbm_gde; /* global debug enable */ + u32 fmbm_pp[0x3f]; /* BMI port parameters */ + u32 res3; + u32 fmbm_pfs[0x3f]; /* BMI port FIFO size */ + u32 res4; + u32 fmbm_ppid[0x3f];/* port partition ID */ +} fm_bmi_common_t; + +typedef struct fm_qmi_common { + u32 fmqm_gc; /* general configuration register */ + u32 res0; + u32 fmqm_eie; /* error interrupt event register */ + u32 fmqm_eien; /* error interrupt enable register */ + u32 fmqm_eif; /* error interrupt force register */ + u32 fmqm_ie; /* interrupt event register */ + u32 fmqm_ien; /* interrupt enable register */ + u32 fmqm_if; /* interrupt force register */ + u32 fmqm_gs; /* global status register */ + u32 fmqm_ts; /* task status register */ + u32 fmqm_etfc; /* enqueue total frame counter */ + u32 fmqm_dtfc; /* dequeue total frame counter */ + u32 fmqm_dc0; /* dequeue counter 0 */ + u32 fmqm_dc1; /* dequeue counter 1 */ + u32 fmqm_dc2; /* dequeue counter 2 */ + u32 fmqm_dc3; /* dequeue counter 3 */ + u32 fmqm_dfnoc; /* dequeue FQID not override counter */ + u32 fmqm_dfcc; /* dequeue FQID from context counter */ + u32 fmqm_dffc; /* dequeue FQID from FD counter */ + u32 fmqm_dcc; /* dequeue confirm counter */ + u32 res1[0xc]; + u32 fmqm_dtrc; /* debug trap configuration register */ + u32 fmqm_efddd; /* enqueue frame descriptor dynamic debug */ + u32 res3[0x2]; + u32 res4[0xdc]; /* missing debug regs */ +} fm_qmi_common_t; + +typedef struct fm_bmi { + u8 res[1024]; +} fm_bmi_t; + +typedef struct fm_qmi { + u8 res[1024]; +} fm_qmi_t; + +struct fm_bmi_rx_port { + u32 fmbm_rcfg; /* Rx configuration */ + u32 fmbm_rst; /* Rx status */ + u32 fmbm_rda; /* Rx DMA attributes */ + u32 fmbm_rfp; /* Rx FIFO parameters */ + u32 fmbm_rfed; /* Rx frame end data */ + u32 fmbm_ricp; /* Rx internal context parameters */ + u32 fmbm_rim; /* Rx internal margins */ + u32 fmbm_rebm; /* Rx external buffer margins */ + u32 fmbm_rfne; /* Rx frame next engine */ + u32 fmbm_rfca; /* Rx frame command attributes */ + u32 fmbm_rfpne; /* Rx frame parser next engine */ + u32 fmbm_rpso; /* Rx parse start offset */ + u32 fmbm_rpp; /* Rx policer profile */ + u32 fmbm_rccb; /* Rx coarse classification base */ + u32 res1[0x2]; + u32 fmbm_rprai[0x8]; /* Rx parse results array Initialization */ + u32 fmbm_rfqid; /* Rx frame queue ID */ + u32 fmbm_refqid; /* Rx error frame queue ID */ + u32 fmbm_rfsdm; /* Rx frame status discard mask */ + u32 fmbm_rfsem; /* Rx frame status error mask */ + u32 fmbm_rfene; /* Rx frame enqueue next engine */ + u32 res2[0x23]; + u32 fmbm_ebmpi[0x8]; /* buffer manager pool information */ + u32 fmbm_acnt[0x8]; /* allocate counter */ + u32 res3[0x8]; + u32 fmbm_cgm[0x8]; /* congestion group map */ + u32 fmbm_mpd; /* BMan pool depletion */ + u32 res4[0x1F]; + u32 fmbm_rstc; /* Rx statistics counters */ + u32 fmbm_rfrc; /* Rx frame counters */ + u32 fmbm_rfbc; /* Rx bad frames counter */ + u32 fmbm_rlfc; /* Rx large frames counter */ + u32 fmbm_rffc; /* Rx filter frames counter */ + u32 fmbm_rfdc; /* Rx frame discard counter */ + u32 fmbm_rfldec; /* Rx frames list DMA error counter */ + u32 fmbm_rodc; /* Rx out of buffers discard counter */ + u32 fmbm_rbdc; /* Rx buffers deallocate counter */ + u32 res5[0x17]; + u32 fmbm_rpc; /* Rx performance counters */ + u32 fmbm_rpcp; /* Rx performance count parameters */ + u32 fmbm_rccn; /* Rx cycle counter */ + u32 fmbm_rtuc; /* Rx tasks utilization counter */ + u32 fmbm_rrquc; /* Rx receive queue utilization counter */ + u32 fmbm_rduc; /* Rx DMA utilization counter */ + u32 fmbm_rfuc; /* Rx FIFO utilization counter */ + u32 fmbm_rpac; /* Rx pause activation counter */ + u32 res6[0x18]; + u32 fmbm_rdbg; /* Rx debug configuration */ +}; + +/* FMBM_RCFG - Rx configuration */ +#define FMBM_RCFG_EN 0x80000000 /* port is enabled to receive data */ +#define FMBM_RCFG_FDOVR 0x02000000 /* frame discard override */ +#define FMBM_RCFG_IM 0x01000000 /* independent mode */ + +/* FMBM_RST - Rx status */ +#define FMBM_RST_BSY 0x80000000 /* Rx port is busy */ + +/* FMBM_RFCA - Rx frame command attributes */ +#define FMBM_RFCA_ORDER 0x80000000 +#define FMBM_RFCA_MR_MASK 0x003f0000 +#define FMBM_RFCA_MR(x) ((x << 16) & FMBM_RFCA_MR_MASK) + +/* FMBM_RSTC - Rx statistics */ +#define FMBM_RSTC_EN 0x80000000 /* statistics counters enable */ + +struct fm_bmi_tx_port { + u32 fmbm_tcfg; /* Tx configuration */ + u32 fmbm_tst; /* Tx status */ + u32 fmbm_tda; /* Tx DMA attributes */ + u32 fmbm_tfp; /* Tx FIFO parameters */ + u32 fmbm_tfed; /* Tx frame end data */ + u32 fmbm_ticp; /* Tx internal context parameters */ + u32 fmbm_tfne; /* Tx frame next engine */ + u32 fmbm_tfca; /* Tx frame command attributes */ + u32 fmbm_tcfqid;/* Tx confirmation frame queue ID */ + u32 fmbm_tfeqid;/* Tx error frame queue ID */ + u32 fmbm_tfene; /* Tx frame enqueue next engine */ + u32 fmbm_trlmts;/* Tx rate limiter scale */ + u32 fmbm_trlmt; /* Tx rate limiter */ + u32 res0[0x73]; + u32 fmbm_tstc; /* Tx statistics counters */ + u32 fmbm_tfrc; /* Tx frame counter */ + u32 fmbm_tfdc; /* Tx frames discard counter */ + u32 fmbm_tfledc;/* Tx frame length error discard counter */ + u32 fmbm_tfufdc;/* Tx frame unsupported format discard counter */ + u32 fmbm_tbdc; /* Tx buffers deallocate counter */ + u32 res1[0x1a]; + u32 fmbm_tpc; /* Tx performance counters */ + u32 fmbm_tpcp; /* Tx performance count parameters */ + u32 fmbm_tccn; /* Tx cycle counter */ + u32 fmbm_ttuc; /* Tx tasks utilization counter */ + u32 fmbm_ttcquc;/* Tx transmit confirm queue utilization counter */ + u32 fmbm_tduc; /* Tx DMA utilization counter */ + u32 fmbm_tfuc; /* Tx FIFO utilization counter */ + u32 res2[0x19]; + u32 fmbm_tdcfg; /* Tx debug configuration */ +}; + +/* FMBM_TCFG - Tx configuration */ +#define FMBM_TCFG_EN 0x80000000 /* port is enabled to transmit data */ +#define FMBM_TCFG_IM 0x01000000 /* independent mode enable */ + +/* FMBM_TST - Tx status */ +#define FMBM_TST_BSY 0x80000000 /* Tx port is busy */ + +/* FMBM_TFCA - Tx frame command attributes */ +#define FMBM_TFCA_ORDER 0x80000000 +#define FMBM_TFCA_MR_MASK 0x003f0000 +#define FMBM_TFCA_MR(x) ((x << 16) & FMBM_TFCA_MR_MASK) + +/* FMBM_TSTC - Tx statistics counters */ +#define FMBM_TSTC_EN 0x80000000 + +/* FMBM_INIT - BMI initialization register */ +#define FMBM_INIT_START 0x80000000 /* init internal buffers */ + +/* FMBM_CFG1 - BMI configuration 1 */ +#define FMBM_CFG1_FBPS_MASK 0x03ff0000 /* Free buffer pool size */ +#define FMBM_CFG1_FBPS_SHIFT 16 +#define FMBM_CFG1_FBPO_MASK 0x000003ff /* Free buffer pool offset */ + +/* FMBM_IEVR - interrupt event */ +#define FMBM_IEVR_PEC 0x80000000 /* pipeline table ECC err detected */ +#define FMBM_IEVR_LEC 0x40000000 /* linked list RAM ECC error */ +#define FMBM_IEVR_SEC 0x20000000 /* statistics count RAM ECC error */ +#define FMBM_IEVR_CLEAR_ALL (FMBM_IEVR_PEC | FMBM_IEVR_LEC | FMBM_IEVR_SEC) + +/* FMBM_IER - interrupt enable */ +#define FMBM_IER_PECE 0x80000000 /* PEC interrupt enable */ +#define FMBM_IER_LECE 0x40000000 /* LEC interrupt enable */ +#define FMBM_IER_SECE 0x20000000 /* SEC interrupt enable */ + +#define FMBM_IER_DISABLE_ALL 0x00000000 + +/* FMBM_PP - BMI Port Parameters */ +#define FMBM_PP_MXT_MASK 0x3f000000 /* Max # tasks */ +#define FMBM_PP_MXT(x) (((x-1) << 24) & FMBM_PP_MXT_MASK) +#define FMBM_PP_MXD_MASK 0x00000f00 /* Max DMA */ +#define FMBM_PP_MXD(x) (((x-1) << 8) & FMBM_PP_MXD_MASK) + +/* FMBM_PFS - BMI Port FIFO Size */ +#define FMBM_PFS_IFSZ_MASK 0x000003ff /* Internal Fifo Size */ +#define FMBM_PFS_IFSZ(x) (x & FMBM_PFS_IFSZ_MASK) + +/* FMQM_GC - global configuration */ +#define FMQM_GC_ENQ_EN 0x80000000 /* enqueue enable */ +#define FMQM_GC_DEQ_EN 0x40000000 /* dequeue enable */ +#define FMQM_GC_STEN 0x10000000 /* enable global stat counters */ +#define FMQM_GC_ENQ_THR_MASK 0x00003f00 /* max number of enqueue Tnum */ +#define FMQM_GC_ENQ(x) ((x << 8) & FMQM_GC_ENQ_THR_MAS) +#define FMQM_GC_DEQ_THR_MASK 0x0000003f /* max number of dequeue Tnum */ +#define FMQM_GC_DEQ(x) (x & FMQM_GC_DEQ_THR_MASK) + +/* FMQM_EIE - error interrupt event register */ +#define FMQM_EIE_DEE 0x80000000 /* double-bit ECC error */ +#define FMQM_EIE_DFUPE 0x40000000 /* dequeue from unknown PortID */ +#define FMQM_EIE_CLEAR_ALL (FMQM_EIE_DEE | FMQM_EIE_DFUPE) + +/* FMQM_EIEN - error interrupt enable register */ +#define FMQM_EIEN_DEEN 0x80000000 /* double-bit ECC error */ +#define FMQM_EIEN_DFUPEN 0x40000000 /* dequeue from unknown PortID */ +#define FMQM_EIEN_DISABLE_ALL 0x00000000 + +/* FMQM_IE - interrupt event register */ +#define FMQM_IE_SEE 0x80000000 /* single-bit ECC error detected */ +#define FMQM_IE_CLEAR_ALL FMQM_IE_SEE + +/* FMQM_IEN - interrupt enable register */ +#define FMQM_IEN_SEE 0x80000000 /* single-bit ECC err IRQ enable */ +#define FMQM_IEN_DISABLE_ALL 0x00000000 + +/* NIA - next invoked action */ +#define NIA_ENG_RISC 0x00000000 +#define NIA_ENG_MASK 0x007c0000 + +/* action code */ +#define NIA_RISC_AC_CC 0x00000006 +#define NIA_RISC_AC_IM_TX 0x00000008 /* independent mode Tx */ +#define NIA_RISC_AC_IM_RX 0x0000000a /* independent mode Rx */ +#define NIA_RISC_AC_HC 0x0000000c + +typedef struct fm_parser { + u8 res[1024]; +} fm_parser_t; + +typedef struct fm_policer { + u8 res[4*1024]; +} fm_policer_t; + +typedef struct fm_keygen { + u8 res[4*1024]; +} fm_keygen_t; + +typedef struct fm_dma { + u32 fmdmsr; /* status register */ + u32 fmdmmr; /* mode register */ + u32 fmdmtr; /* bus threshold register */ + u32 fmdmhy; /* bus hysteresis register */ + u32 fmdmsetr; /* SOS emergency threshold register */ + u32 fmdmtah; /* transfer bus address high register */ + u32 fmdmtal; /* transfer bus address low register */ + u32 fmdmtcid; /* transfer bus communication ID register */ + u32 fmdmra; /* DMA bus internal ram address register */ + u32 fmdmrd; /* DMA bus internal ram data register */ + u32 res0[0xb]; + u32 fmdmdcr; /* debug counter */ + u32 fmdmemsr; /* emrgency smoother register */ + u32 res1; + u32 fmdmplr[32]; /* FM DMA PID-LIODN # register */ + u32 res[0x3c8]; +} fm_dma_t; + +/* FMDMSR - Fman DMA status register */ +#define FMDMSR_CMDQNE 0x10000000 /* command queue not empty */ +#define FMDMSR_BER 0x08000000 /* bus err event occurred on bus */ +#define FMDMSR_RDB_ECC 0x04000000 /* read buffer ECC error */ +#define FMDMSR_WRB_SECC 0x02000000 /* write buf ECC err sys side */ +#define FMDMSR_WRB_FECC 0x01000000 /* write buf ECC err Fman side */ +#define FMDMSR_DPEXT_SECC 0x00800000 /* DP external ECC err sys side */ +#define FMDMSR_DPEXT_FECC 0x00400000 /* DP external ECC err Fman side */ +#define FMDMSR_DPDAT_SECC 0x00200000 /* DP data ECC err on sys side */ +#define FMDMSR_DPDAT_FECC 0x00100000 /* DP data ECC err on Fman side */ +#define FMDMSR_SPDAT_FECC 0x00080000 /* SP data ECC error Fman side */ + +#define FMDMSR_CLEAR_ALL (FMDMSR_BER | FMDMSR_RDB_ECC \ + | FMDMSR_WRB_SECC | FMDMSR_WRB_FECC \ + | FMDMSR_DPEXT_SECC | FMDMSR_DPEXT_FECC \ + | FMDMSR_DPDAT_SECC | FMDMSR_DPDAT_FECC \ + | FMDMSR_SPDAT_FECC) + +/* FMDMMR - FMan DMA mode register */ +#define FMDMMR_SBER 0x10000000 /* stop the DMA if a bus error */ + +typedef struct fm_fpm { + u32 fpmtnc; /* TNUM control */ + u32 fpmprc; /* Port_ID control */ + u32 res0; + u32 fpmflc; /* flush control */ + u32 fpmdis1; /* dispatch thresholds1 */ + u32 fpmdis2; /* dispatch thresholds2 */ + u32 fmepi; /* error pending interrupts */ + u32 fmrie; /* rams interrupt enable */ + u32 fpmfcevent[0x4];/* FMan controller event 0-3 */ + u32 res1[0x4]; + u32 fpmfcmask[0x4]; /* FMan controller mask 0-3 */ + u32 res2[0x4]; + u32 fpmtsc1; /* timestamp control1 */ + u32 fpmtsc2; /* timestamp control2 */ + u32 fpmtsp; /* time stamp */ + u32 fpmtsf; /* time stamp fraction */ + u32 fpmrcr; /* rams control and event */ + u32 res3[0x3]; + u32 fpmdrd[0x4]; /* data_ram data 0-3 */ + u32 res4[0xc]; + u32 fpmdra; /* data ram access */ + u32 fm_ip_rev_1; /* IP block revision 1 */ + u32 fm_ip_rev_2; /* IP block revision 2 */ + u32 fmrstc; /* reset command */ + u32 fmcld; /* classifier debug control */ + u32 fmnpi; /* normal pending interrupts */ + u32 res5; + u32 fmfpee; /* event and enable */ + u32 fpmcev[0x4]; /* CPU event 0-3 */ + u32 res6[0x4]; + u32 fmfp_ps[0x40]; /* port status */ + u32 res7[0x260]; + u32 fpmts[0x80]; /* task status */ + u32 res8[0xa0]; +} fm_fpm_t; + +/* FMFP_PRC - FPM Port_ID Control Register */ +#define FMFPPRC_PORTID_MASK 0x3f000000 +#define FMFPPRC_PORTID_SHIFT 24 +#define FMFPPRC_ORA_SHIFT 16 +#define FMFPPRC_RISC1 0x00000001 +#define FMFPPRC_RISC2 0x00000002 +#define FMFPPRC_RISC_ALL (FMFPPRC_RISC1 | FMFPPRC_RSIC2) + +/* FPM Flush Control Register */ +#define FMFP_FLC_DISP_LIM_NONE 0x00000000 /* no dispatch limitation */ + +/* FMFP_EE - FPM event and enable register */ +#define FMFPEE_DECC 0x80000000 /* double ECC err on FPM ram */ +#define FMFPEE_STL 0x40000000 /* stall of task ... */ +#define FMFPEE_SECC 0x20000000 /* single ECC error */ +#define FMFPEE_RFM 0x00010000 /* release FMan */ +#define FMFPEE_DECC_EN 0x00008000 /* double ECC interrupt enable */ +#define FMFPEE_STL_EN 0x00004000 /* stall of task interrupt enable */ +#define FMFPEE_SECC_EN 0x00002000 /* single ECC err interrupt enable */ +#define FMFPEE_EHM 0x00000008 /* external halt enable */ +#define FMFPEE_UEC 0x00000004 /* FMan is not halted */ +#define FMFPEE_CER 0x00000002 /* only errornous task stalled */ +#define FMFPEE_DER 0x00000001 /* DMA error is just reported */ + +#define FMFPEE_CLEAR_EVENT (FMFPEE_DECC | FMFPEE_STL | FMFPEE_SECC | \ + FMFPEE_EHM | FMFPEE_UEC | FMFPEE_CER | \ + FMFPEE_DER | FMFPEE_RFM) + +/* FMFP_RCR - FMan Rams Control and Event */ +#define FMFP_RCR_MDEC 0x00008000 /* double ECC error in muram */ +#define FMFP_RCR_IDEC 0x00004000 /* double ECC error in iram */ + +typedef struct fm_imem { + u32 iadd; /* instruction address register */ + u32 idata; /* instruction data register */ + u32 itcfg; /* timing config register */ + u32 iready; /* ready register */ + u8 res[0xff0]; +} fm_imem_t; +#define IRAM_IADD_AIE 0x80000000 /* address auto increase enable */ +#define IRAM_READY 0x80000000 /* ready to use */ + +typedef struct fm_soft_parser { + u8 res[4*1024]; +} fm_soft_parser_t; + +typedef struct fm_dtesc { + u8 res[4*1024]; +} fm_dtsec_t; + +typedef struct fm_mdio { + u8 res0[0x120]; + u32 miimcfg; /* MII management configuration reg */ + u32 miimcom; /* MII management command reg */ + u32 miimadd; /* MII management address reg */ + u32 miimcon; /* MII management control reg */ + u32 miimstat; /* MII management status reg */ + u32 miimind; /* MII management indication reg */ + u8 res1[0x1000 - 0x138]; +} fm_mdio_t; + +typedef struct fm_10gec { + u8 res[4*1024]; +} fm_10gec_t; + +typedef struct fm_10gec_mdio { + u8 res[4*1024]; +} fm_10gec_mdio_t; + +typedef struct fm_memac { + u8 res[4*1024]; +} fm_memac_t; + +typedef struct fm_memac_mdio { + u8 res[4*1024]; +} fm_memac_mdio_t; + +typedef struct fm_1588 { + u8 res[4*1024]; +} fm_1588_t; + +typedef struct ccsr_fman { + u8 muram[0x80000]; + fm_bmi_common_t fm_bmi_common; + fm_qmi_common_t fm_qmi_common; + u8 res0[2048]; + struct { + fm_bmi_t fm_bmi; + fm_qmi_t fm_qmi; + fm_parser_t fm_parser; + u8 res[1024]; + } port[63]; + fm_policer_t fm_policer; + fm_keygen_t fm_keygen; + fm_dma_t fm_dma; + fm_fpm_t fm_fpm; + fm_imem_t fm_imem; + u8 res1[8*1024]; + fm_soft_parser_t fm_soft_parser; + u8 res2[96*1024]; +#ifdef CONFIG_SYS_FMAN_V3 + struct { + fm_memac_t fm_memac; + fm_memac_mdio_t fm_memac_mdio; + } memac[10]; + u8 res4[32*1024]; + fm_memac_mdio_t fm_dedicated_mdio[2]; +#else + struct { + fm_dtsec_t fm_dtesc; + fm_mdio_t fm_mdio; + } mac_1g[8]; /* support up to 8 1g controllers */ + struct { + fm_10gec_t fm_10gec; + fm_10gec_mdio_t fm_10gec_mdio; + } mac_10g[1]; + u8 res4[48*1024]; +#endif + fm_1588_t fm_1588; + u8 res5[4*1024]; +} ccsr_fman_t; + +void fdt_fixup_fman_firmware(void *blob); +#endif /*__FSL_FMAN_H__*/ diff --git a/roms/u-boot/include/fsl_ifc.h b/roms/u-boot/include/fsl_ifc.h new file mode 100644 index 000000000..9f243cd94 --- /dev/null +++ b/roms/u-boot/include/fsl_ifc.h @@ -0,0 +1,1061 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Dipen Dudhat + */ + +#ifndef __FSL_IFC_H +#define __FSL_IFC_H + +#ifdef CONFIG_FSL_IFC +#include +#include +#include +#ifdef CONFIG_ARM +#include +#endif + +#define FSL_IFC_V1_1_0 0x01010000 +#define FSL_IFC_V2_0_0 0x02000000 + +#ifdef CONFIG_SYS_FSL_IFC_LE +#define ifc_in32(a) in_le32(a) +#define ifc_out32(a, v) out_le32(a, v) +#define ifc_in16(a) in_le16(a) +#define ifc_out16(a, v) out_le16(a, v) +#elif defined(CONFIG_SYS_FSL_IFC_BE) +#define ifc_in32(a) in_be32(a) +#define ifc_out32(a, v) out_be32(a, v) +#define ifc_in16(a) in_be16(a) +#define ifc_out16(a, v) out_be16(a, v) +#else +#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined +#endif + + +/* + * CSPR - Chip Select Property Register + */ +#define CSPR_BA 0xFFFF0000 +#define CSPR_BA_SHIFT 16 +#define CSPR_PORT_SIZE 0x00000180 +#define CSPR_PORT_SIZE_SHIFT 7 +/* Port Size 8 bit */ +#define CSPR_PORT_SIZE_8 0x00000080 +/* Port Size 16 bit */ +#define CSPR_PORT_SIZE_16 0x00000100 +/* Port Size 32 bit */ +#define CSPR_PORT_SIZE_32 0x00000180 +/* Write Protect */ +#define CSPR_WP 0x00000040 +#define CSPR_WP_SHIFT 6 +/* Machine Select */ +#define CSPR_MSEL 0x00000006 +#define CSPR_MSEL_SHIFT 1 +/* External Transceiver Enable */ +#define CSPR_TE 0x00000010 +/* NOR */ +#define CSPR_MSEL_NOR 0x00000000 +/* NAND */ +#define CSPR_MSEL_NAND 0x00000002 +/* GPCM */ +#define CSPR_MSEL_GPCM 0x00000004 +/* Bank Valid */ +#define CSPR_V 0x00000001 +#define CSPR_V_SHIFT 0 + +/* Convert an address into the right format for the CSPR Registers */ +#define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000) + +/* + * Address Mask Register + */ +#define IFC_AMASK_MASK 0xFFFF0000 +#define IFC_AMASK_SHIFT 16 +#define IFC_AMASK(n) (IFC_AMASK_MASK << \ + (LOG2(n) - IFC_AMASK_SHIFT)) + +/* + * Chip Select Option Register IFC_NAND Machine + */ +/* Enable ECC Encoder */ +#define CSOR_NAND_ECC_ENC_EN 0x80000000 +#define CSOR_NAND_ECC_MODE_MASK 0x30000000 +/* 4 bit correction per 520 Byte sector */ +#define CSOR_NAND_ECC_MODE_4 0x00000000 +/* 8 bit correction per 528 Byte sector */ +#define CSOR_NAND_ECC_MODE_8 0x10000000 +/* Enable ECC Decoder */ +#define CSOR_NAND_ECC_DEC_EN 0x04000000 +/* Row Address Length */ +#define CSOR_NAND_RAL_MASK 0x01800000 +#define CSOR_NAND_RAL_SHIFT 20 +#define CSOR_NAND_RAL_1 0x00000000 +#define CSOR_NAND_RAL_2 0x00800000 +#define CSOR_NAND_RAL_3 0x01000000 +#define CSOR_NAND_RAL_4 0x01800000 +/* Page Size 512b, 2k, 4k */ +#define CSOR_NAND_PGS_MASK 0x00180000 +#define CSOR_NAND_PGS_SHIFT 16 +#define CSOR_NAND_PGS_512 0x00000000 +#define CSOR_NAND_PGS_2K 0x00080000 +#define CSOR_NAND_PGS_4K 0x00100000 +#define CSOR_NAND_PGS_8K 0x00180000 +/* Spare region Size */ +#define CSOR_NAND_SPRZ_MASK 0x0000E000 +#define CSOR_NAND_SPRZ_SHIFT 13 +#define CSOR_NAND_SPRZ_16 0x00000000 +#define CSOR_NAND_SPRZ_64 0x00002000 +#define CSOR_NAND_SPRZ_128 0x00004000 +#define CSOR_NAND_SPRZ_210 0x00006000 +#define CSOR_NAND_SPRZ_218 0x00008000 +#define CSOR_NAND_SPRZ_224 0x0000A000 +#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 +/* Pages Per Block */ +#define CSOR_NAND_PB_MASK 0x00000700 +#define CSOR_NAND_PB_SHIFT 8 +#define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT) +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_NAND_TRHZ_MASK 0x0000001C +#define CSOR_NAND_TRHZ_SHIFT 2 +#define CSOR_NAND_TRHZ_20 0x00000000 +#define CSOR_NAND_TRHZ_40 0x00000004 +#define CSOR_NAND_TRHZ_60 0x00000008 +#define CSOR_NAND_TRHZ_80 0x0000000C +#define CSOR_NAND_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_NAND_BCTLD 0x00000001 + +/* + * Chip Select Option Register - NOR Flash Mode + */ +/* Enable Address shift Mode */ +#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 +/* Page Read Enable from NOR device */ +#define CSOR_NOR_PGRD_EN 0x10000000 +/* AVD Toggle Enable during Burst Program */ +#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 +/* Address Data Multiplexing Shift */ +#define CSOR_NOR_ADM_MASK 0x0003E000 +#define CSOR_NOR_ADM_SHIFT_SHIFT 13 +#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) +/* Type of the NOR device hooked */ +#define CSOR_NOR_NOR_MODE_ASYNC_NOR 0x00000000 +#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_NOR_TRHZ_MASK 0x0000001C +#define CSOR_NOR_TRHZ_SHIFT 2 +#define CSOR_NOR_TRHZ_20 0x00000000 +#define CSOR_NOR_TRHZ_40 0x00000004 +#define CSOR_NOR_TRHZ_60 0x00000008 +#define CSOR_NOR_TRHZ_80 0x0000000C +#define CSOR_NOR_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_NOR_BCTLD 0x00000001 + +/* + * Chip Select Option Register - GPCM Mode + */ +/* GPCM Mode - Normal */ +#define CSOR_GPCM_GPMODE_NORMAL 0x00000000 +/* GPCM Mode - GenericASIC */ +#define CSOR_GPCM_GPMODE_ASIC 0x80000000 +/* Parity Mode odd/even */ +#define CSOR_GPCM_PARITY_EVEN 0x40000000 +/* Parity Checking enable/disable */ +#define CSOR_GPCM_PAR_EN 0x20000000 +/* GPCM Timeout Count */ +#define CSOR_GPCM_GPTO_MASK 0x0F000000 +#define CSOR_GPCM_GPTO_SHIFT 24 +#define CSOR_GPCM_GPTO(n) ((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) +/* GPCM External Access Termination mode for read access */ +#define CSOR_GPCM_RGETA_EXT 0x00080000 +/* GPCM External Access Termination mode for write access */ +#define CSOR_GPCM_WGETA_EXT 0x00040000 +/* Address Data Multiplexing Shift */ +#define CSOR_GPCM_ADM_MASK 0x0003E000 +#define CSOR_GPCM_ADM_SHIFT_SHIFT 13 +#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) +/* Generic ASIC Parity error indication delay */ +#define CSOR_GPCM_GAPERRD_MASK 0x00000180 +#define CSOR_GPCM_GAPERRD_SHIFT 7 +#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_GPCM_TRHZ_MASK 0x0000001C +#define CSOR_GPCM_TRHZ_20 0x00000000 +#define CSOR_GPCM_TRHZ_40 0x00000004 +#define CSOR_GPCM_TRHZ_60 0x00000008 +#define CSOR_GPCM_TRHZ_80 0x0000000C +#define CSOR_GPCM_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_GPCM_BCTLD 0x00000001 + +/* + * Flash Timing Registers (FTIM0 - FTIM2_CSn) + */ +/* + * FTIM0 - NAND Flash Mode + */ +#define FTIM0_NAND 0x7EFF3F3F +#define FTIM0_NAND_TCCST_SHIFT 25 +#define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) +#define FTIM0_NAND_TWP_SHIFT 16 +#define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) +#define FTIM0_NAND_TWCHT_SHIFT 8 +#define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) +#define FTIM0_NAND_TWH_SHIFT 0 +#define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) +/* + * FTIM1 - NAND Flash Mode + */ +#define FTIM1_NAND 0xFFFF3FFF +#define FTIM1_NAND_TADLE_SHIFT 24 +#define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT) +#define FTIM1_NAND_TWBE_SHIFT 16 +#define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT) +#define FTIM1_NAND_TRR_SHIFT 8 +#define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) +#define FTIM1_NAND_TRP_SHIFT 0 +#define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) +/* + * FTIM2 - NAND Flash Mode + */ +#define FTIM2_NAND 0x1FE1F8FF +#define FTIM2_NAND_TRAD_SHIFT 21 +#define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT) +#define FTIM2_NAND_TREH_SHIFT 11 +#define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT) +#define FTIM2_NAND_TWHRE_SHIFT 0 +#define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT) +/* + * FTIM3 - NAND Flash Mode + */ +#define FTIM3_NAND 0xFF000000 +#define FTIM3_NAND_TWW_SHIFT 24 +#define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) + +/* + * FTIM0 - NOR Flash Mode + */ +#define FTIM0_NOR 0xF03F3F3F +#define FTIM0_NOR_TACSE_SHIFT 28 +#define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) +#define FTIM0_NOR_TEADC_SHIFT 16 +#define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) +#define FTIM0_NOR_TAVDS_SHIFT 8 +#define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) +#define FTIM0_NOR_TEAHC_SHIFT 0 +#define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) +/* + * FTIM1 - NOR Flash Mode + */ +#define FTIM1_NOR 0xFF003F3F +#define FTIM1_NOR_TACO_SHIFT 24 +#define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) +#define FTIM1_NOR_TRAD_NOR_SHIFT 8 +#define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) +#define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 +#define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) +/* + * FTIM2 - NOR Flash Mode + */ +#define FTIM2_NOR 0x0F3CFCFF +#define FTIM2_NOR_TCS_SHIFT 24 +#define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) +#define FTIM2_NOR_TCH_SHIFT 18 +#define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) +#define FTIM2_NOR_TWPH_SHIFT 10 +#define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) +#define FTIM2_NOR_TWP_SHIFT 0 +#define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) + +/* + * FTIM0 - Normal GPCM Mode + */ +#define FTIM0_GPCM 0xF03F3F3F +#define FTIM0_GPCM_TACSE_SHIFT 28 +#define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) +#define FTIM0_GPCM_TEADC_SHIFT 16 +#define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) +#define FTIM0_GPCM_TAVDS_SHIFT 8 +#define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) +#define FTIM0_GPCM_TEAHC_SHIFT 0 +#define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) +/* + * FTIM1 - Normal GPCM Mode + */ +#define FTIM1_GPCM 0xFF003F00 +#define FTIM1_GPCM_TACO_SHIFT 24 +#define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) +#define FTIM1_GPCM_TRAD_SHIFT 8 +#define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) +/* + * FTIM2 - Normal GPCM Mode + */ +#define FTIM2_GPCM 0x0F3C00FF +#define FTIM2_GPCM_TCS_SHIFT 24 +#define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) +#define FTIM2_GPCM_TCH_SHIFT 18 +#define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) +#define FTIM2_GPCM_TWP_SHIFT 0 +#define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) + +/* + * Ready Busy Status Register (RB_STAT) + */ +/* CSn is READY */ +#define IFC_RB_STAT_READY_CS0 0x80000000 +#define IFC_RB_STAT_READY_CS1 0x40000000 +#define IFC_RB_STAT_READY_CS2 0x20000000 +#define IFC_RB_STAT_READY_CS3 0x10000000 + +/* + * General Control Register (GCR) + */ +#define IFC_GCR_MASK 0x8000F800 +/* reset all IFC hardware */ +#define IFC_GCR_SOFT_RST_ALL 0x80000000 +/* Turnaroud Time of external buffer */ +#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 +#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 + +/* + * Common Event and Error Status Register (CM_EVTER_STAT) + */ +/* Chip select error */ +#define IFC_CM_EVTER_STAT_CSER 0x80000000 + +/* + * Common Event and Error Enable Register (CM_EVTER_EN) + */ +/* Chip select error checking enable */ +#define IFC_CM_EVTER_EN_CSEREN 0x80000000 + +/* + * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) + */ +/* Chip select error interrupt enable */ +#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 + +/* + * Common Transfer Error Attribute Register-0 (CM_ERATTR0) + */ +/* transaction type of error Read/Write */ +#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 +#define IFC_CM_ERATTR0_ERAID 0x0FF00000 +#define IFC_CM_ERATTR0_ESRCID 0x0000FF00 + +/* + * Clock Control Register (CCR) + */ +#define IFC_CCR_MASK 0x0F0F8800 +/* Clock division ratio */ +#define IFC_CCR_CLK_DIV_MASK 0x0F000000 +#define IFC_CCR_CLK_DIV_SHIFT 24 +#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) +/* IFC Clock Delay */ +#define IFC_CCR_CLK_DLY_MASK 0x000F0000 +#define IFC_CCR_CLK_DLY_SHIFT 16 +#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) +/* Invert IFC clock before sending out */ +#define IFC_CCR_INV_CLK_EN 0x00008000 +/* Fedback IFC Clock */ +#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 + +/* + * Clock Status Register (CSR) + */ +/* Clk is stable */ +#define IFC_CSR_CLK_STAT_STABLE 0x80000000 + +/* + * IFC_NAND Machine Specific Registers + */ +/* + * NAND Configuration Register (NCFGR) + */ +/* Auto Boot Mode */ +#define IFC_NAND_NCFGR_BOOT 0x80000000 +/* SRAM INIT EN */ +#define IFC_NAND_SRAM_INIT_EN 0x20000000 +/* Addressing Mode-ROW0+n/COL0 */ +#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 +/* Addressing Mode-ROW0+n/COL0+n */ +#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 +/* Number of loop iterations of FIR sequences for multi page operations */ +#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 +#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 +#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) +/* Number of wait cycles */ +#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF +#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 + +/* + * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) + */ +/* General purpose FCM flash command bytes CMD0-CMD7 */ +#define IFC_NAND_FCR0_CMD0 0xFF000000 +#define IFC_NAND_FCR0_CMD0_SHIFT 24 +#define IFC_NAND_FCR0_CMD1 0x00FF0000 +#define IFC_NAND_FCR0_CMD1_SHIFT 16 +#define IFC_NAND_FCR0_CMD2 0x0000FF00 +#define IFC_NAND_FCR0_CMD2_SHIFT 8 +#define IFC_NAND_FCR0_CMD3 0x000000FF +#define IFC_NAND_FCR0_CMD3_SHIFT 0 +#define IFC_NAND_FCR1_CMD4 0xFF000000 +#define IFC_NAND_FCR1_CMD4_SHIFT 24 +#define IFC_NAND_FCR1_CMD5 0x00FF0000 +#define IFC_NAND_FCR1_CMD5_SHIFT 16 +#define IFC_NAND_FCR1_CMD6 0x0000FF00 +#define IFC_NAND_FCR1_CMD6_SHIFT 8 +#define IFC_NAND_FCR1_CMD7 0x000000FF +#define IFC_NAND_FCR1_CMD7_SHIFT 0 + +/* + * Flash ROW and COL Address Register (ROWn, COLn) + */ +/* Main/spare region locator */ +#define IFC_NAND_COL_MS 0x80000000 +/* Column Address */ +#define IFC_NAND_COL_CA_MASK 0x00000FFF + +/* + * NAND Flash Byte Count Register (NAND_BC) + */ +/* Byte Count for read/Write */ +#define IFC_NAND_BC 0x000001FF + +/* + * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) + */ +/* NAND Machine specific opcodes OP0-OP14*/ +#define IFC_NAND_FIR0_OP0 0xFC000000 +#define IFC_NAND_FIR0_OP0_SHIFT 26 +#define IFC_NAND_FIR0_OP1 0x03F00000 +#define IFC_NAND_FIR0_OP1_SHIFT 20 +#define IFC_NAND_FIR0_OP2 0x000FC000 +#define IFC_NAND_FIR0_OP2_SHIFT 14 +#define IFC_NAND_FIR0_OP3 0x00003F00 +#define IFC_NAND_FIR0_OP3_SHIFT 8 +#define IFC_NAND_FIR0_OP4 0x000000FC +#define IFC_NAND_FIR0_OP4_SHIFT 2 +#define IFC_NAND_FIR1_OP5 0xFC000000 +#define IFC_NAND_FIR1_OP5_SHIFT 26 +#define IFC_NAND_FIR1_OP6 0x03F00000 +#define IFC_NAND_FIR1_OP6_SHIFT 20 +#define IFC_NAND_FIR1_OP7 0x000FC000 +#define IFC_NAND_FIR1_OP7_SHIFT 14 +#define IFC_NAND_FIR1_OP8 0x00003F00 +#define IFC_NAND_FIR1_OP8_SHIFT 8 +#define IFC_NAND_FIR1_OP9 0x000000FC +#define IFC_NAND_FIR1_OP9_SHIFT 2 +#define IFC_NAND_FIR2_OP10 0xFC000000 +#define IFC_NAND_FIR2_OP10_SHIFT 26 +#define IFC_NAND_FIR2_OP11 0x03F00000 +#define IFC_NAND_FIR2_OP11_SHIFT 20 +#define IFC_NAND_FIR2_OP12 0x000FC000 +#define IFC_NAND_FIR2_OP12_SHIFT 14 +#define IFC_NAND_FIR2_OP13 0x00003F00 +#define IFC_NAND_FIR2_OP13_SHIFT 8 +#define IFC_NAND_FIR2_OP14 0x000000FC +#define IFC_NAND_FIR2_OP14_SHIFT 2 + +/* + * Instruction opcodes to be programmed + * in FIR registers- 6bits + */ +enum ifc_nand_fir_opcodes { + IFC_FIR_OP_NOP, + IFC_FIR_OP_CA0, + IFC_FIR_OP_CA1, + IFC_FIR_OP_CA2, + IFC_FIR_OP_CA3, + IFC_FIR_OP_RA0, + IFC_FIR_OP_RA1, + IFC_FIR_OP_RA2, + IFC_FIR_OP_RA3, + IFC_FIR_OP_CMD0, + IFC_FIR_OP_CMD1, + IFC_FIR_OP_CMD2, + IFC_FIR_OP_CMD3, + IFC_FIR_OP_CMD4, + IFC_FIR_OP_CMD5, + IFC_FIR_OP_CMD6, + IFC_FIR_OP_CMD7, + IFC_FIR_OP_CW0, + IFC_FIR_OP_CW1, + IFC_FIR_OP_CW2, + IFC_FIR_OP_CW3, + IFC_FIR_OP_CW4, + IFC_FIR_OP_CW5, + IFC_FIR_OP_CW6, + IFC_FIR_OP_CW7, + IFC_FIR_OP_WBCD, + IFC_FIR_OP_RBCD, + IFC_FIR_OP_BTRD, + IFC_FIR_OP_RDSTAT, + IFC_FIR_OP_NWAIT, + IFC_FIR_OP_WFR, + IFC_FIR_OP_SBRD, + IFC_FIR_OP_UA, + IFC_FIR_OP_RB, +}; + +/* + * NAND Chip Select Register (NAND_CSEL) + */ +#define IFC_NAND_CSEL 0x0C000000 +#define IFC_NAND_CSEL_SHIFT 26 +#define IFC_NAND_CSEL_CS0 0x00000000 +#define IFC_NAND_CSEL_CS1 0x04000000 +#define IFC_NAND_CSEL_CS2 0x08000000 +#define IFC_NAND_CSEL_CS3 0x0C000000 + +/* + * NAND Operation Sequence Start (NANDSEQ_STRT) + */ +/* NAND Flash Operation Start */ +#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 +/* Automatic Erase */ +#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 +/* Automatic Program */ +#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 +/* Automatic Copyback */ +#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 +/* Automatic Read Operation */ +#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 +/* Automatic Status Read */ +#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 + +/* + * NAND Event and Error Status Register (NAND_EVTER_STAT) + */ +/* Operation Complete */ +#define IFC_NAND_EVTER_STAT_OPC 0x80000000 +/* Flash Timeout Error */ +#define IFC_NAND_EVTER_STAT_FTOER 0x08000000 +/* Write Protect Error */ +#define IFC_NAND_EVTER_STAT_WPER 0x04000000 +/* ECC Error */ +#define IFC_NAND_EVTER_STAT_ECCER 0x02000000 +/* RCW Load Done */ +#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 +/* Boot Loadr Done */ +#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 +/* Bad Block Indicator search select */ +#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 + +/* + * NAND Flash Page Read Completion Event Status Register + * (PGRDCMPL_EVT_STAT) + */ +#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 +/* Small Page 0-15 Done */ +#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) +/* Large Page(2K) 0-3 Done */ +#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) +/* Large Page(4K) 0-1 Done */ +#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) + +/* + * NAND Event and Error Enable Register (NAND_EVTER_EN) + */ +/* Operation complete event enable */ +#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 +/* Page read complete event enable */ +#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 +/* Flash Timeout error enable */ +#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 +/* Write Protect error enable */ +#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 +/* ECC error logging enable */ +#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 + +/* + * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) + */ +/* Enable interrupt for operation complete */ +#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 +/* Enable interrupt for Page read complete */ +#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 +/* Enable interrupt for Flash timeout error */ +#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 +/* Enable interrupt for Write protect error */ +#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 +/* Enable interrupt for ECC error*/ +#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 + +/* + * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) + */ +#define IFC_NAND_ERATTR0_MASK 0x0C080000 +/* Error on CS0-3 for NAND */ +#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 +#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 +#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 +/* Transaction type of error Read/Write */ +#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 + +/* + * NAND Flash Status Register (NAND_FSR) + */ +/* First byte of data read from read status op */ +#define IFC_NAND_NFSR_RS0 0xFF000000 +/* Second byte of data read from read status op */ +#define IFC_NAND_NFSR_RS1 0x00FF0000 + +/* + * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) + */ +/* Number of ECC errors on sector n (n = 0-15) */ +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 + +/* + * NAND Control Register (NANDCR) + */ +#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 +#define IFC_NAND_NCR_FTOCNT_SHIFT 25 +#define IFC_NAND_NCR_FTOCNT(n) ((LOG2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) + +/* + * NAND_AUTOBOOT_TRGR + */ +/* Trigger RCW load */ +#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 +/* Trigget Auto Boot */ +#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 + +/* + * NAND_MDR + */ +/* 1st read data byte when opcode SBRD */ +#define IFC_NAND_MDR_RDATA0 0xFF000000 +/* 2nd read data byte when opcode SBRD */ +#define IFC_NAND_MDR_RDATA1 0x00FF0000 + +/* + * NOR Machine Specific Registers + */ +/* + * NOR Event and Error Status Register (NOR_EVTER_STAT) + */ +/* NOR Command Sequence Operation Complete */ +#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 +/* Write Protect Error */ +#define IFC_NOR_EVTER_STAT_WPER 0x04000000 +/* Command Sequence Timeout Error */ +#define IFC_NOR_EVTER_STAT_STOER 0x01000000 + +/* + * NOR Event and Error Enable Register (NOR_EVTER_EN) + */ +/* NOR Command Seq complete event enable */ +#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 +/* Write Protect Error Checking Enable */ +#define IFC_NOR_EVTER_EN_WPEREN 0x04000000 +/* Timeout Error Enable */ +#define IFC_NOR_EVTER_EN_STOEREN 0x01000000 + +/* + * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) + */ +/* Enable interrupt for OPC complete */ +#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 +/* Enable interrupt for write protect error */ +#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 +/* Enable interrupt for timeout error */ +#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 + +/* + * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) + */ +/* Source ID for error transaction */ +#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 +/* AXI ID for error transation */ +#define IFC_NOR_ERATTR0_ERAID 0x000FF000 +/* Chip select corresponds to NOR error */ +#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 +#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 +#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 +/* Type of transaction read/write */ +#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 + +/* + * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) + */ +#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 +#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 + +/* + * NOR Control Register (NORCR) + */ +#define IFC_NORCR_MASK 0x0F0F0000 +/* No. of Address/Data Phase */ +#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 +#define IFC_NORCR_NUM_PHASE_SHIFT 24 +#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) +/* Sequence Timeout Count */ +#define IFC_NORCR_STOCNT_MASK 0x000F0000 +#define IFC_NORCR_STOCNT_SHIFT 16 +#define IFC_NORCR_STOCNT(n) ((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) + +/* + * GPCM Machine specific registers + */ +/* + * GPCM Event and Error Status Register (GPCM_EVTER_STAT) + */ +/* Timeout error */ +#define IFC_GPCM_EVTER_STAT_TOER 0x04000000 +/* Parity error */ +#define IFC_GPCM_EVTER_STAT_PER 0x01000000 + +/* + * GPCM Event and Error Enable Register (GPCM_EVTER_EN) + */ +/* Timeout error enable */ +#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 +/* Parity error enable */ +#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 + +/* + * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) + */ +/* Enable Interrupt for timeout error */ +#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 +/* Enable Interrupt for Parity error */ +#define IFC_GPCM_EEIER_PERIR_EN 0x01000000 + +/* + * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) + */ +/* Source ID for error transaction */ +#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 +/* AXI ID for error transaction */ +#define IFC_GPCM_ERATTR0_ERAID 0x000FF000 +/* Chip select corresponds to GPCM error */ +#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 +#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 +#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 +/* Type of transaction read/Write */ +#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 + +/* + * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) + */ +/* On which beat of address/data parity error is observed */ +#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 +/* Parity Error on byte */ +#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 +/* Parity Error reported in addr or data phase */ +#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 + +/* + * GPCM Status Register (GPCM_STAT) + */ +#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ + + +#ifndef __ASSEMBLY__ +#include + +extern void print_ifc_regs(void); +extern void init_early_memctl_regs(void); +void init_final_memctl_regs(void); + +#define IFC_RREGS_4KOFFSET (4*1024) +#define IFC_RREGS_64KOFFSET (64*1024) + +#define IFC_FCM_BASE_ADDR \ + ((struct fsl_ifc_fcm *)CONFIG_SYS_IFC_ADDR) + +#define get_ifc_cspr_ext(i) \ + (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext)) +#define get_ifc_cspr(i) \ + (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr)) +#define get_ifc_csor_ext(i) \ + (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext)) +#define get_ifc_csor(i) \ + (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor)) +#define get_ifc_amask(i) \ + (ifc_in32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask)) +#define get_ifc_ftim(i, j) \ + (ifc_in32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j])) +#define set_ifc_cspr_ext(i, v) \ + (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) +#define set_ifc_cspr(i, v) \ + (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr, v)) +#define set_ifc_csor_ext(i, v) \ + (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext, v)) +#define set_ifc_csor(i, v) \ + (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor, v)) +#define set_ifc_amask(i, v) \ + (ifc_out32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask, v)) +#define set_ifc_ftim(i, j, v) \ + (ifc_out32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j], v)) + +enum ifc_chip_sel { + IFC_CS0, + IFC_CS1, + IFC_CS2, + IFC_CS3, + IFC_CS4, + IFC_CS5, + IFC_CS6, + IFC_CS7, +}; + +enum ifc_ftims { + IFC_FTIM0, + IFC_FTIM1, + IFC_FTIM2, + IFC_FTIM3, +}; + +/* + * IFC Controller NAND Machine registers + */ +struct fsl_ifc_nand { + u32 ncfgr; + u32 res1[0x4]; + u32 nand_fcr0; + u32 nand_fcr1; + u32 res2[0x8]; + u32 row0; + u32 res3; + u32 col0; + u32 res4; + u32 row1; + u32 res5; + u32 col1; + u32 res6; + u32 row2; + u32 res7; + u32 col2; + u32 res8; + u32 row3; + u32 res9; + u32 col3; + u32 res10[0x24]; + u32 nand_fbcr; + u32 res11; + u32 nand_fir0; + u32 nand_fir1; + u32 nand_fir2; + u32 res12[0x10]; + u32 nand_csel; + u32 res13; + u32 nandseq_strt; + u32 res14; + u32 nand_evter_stat; + u32 res15; + u32 pgrdcmpl_evt_stat; + u32 res16[0x2]; + u32 nand_evter_en; + u32 res17[0x2]; + u32 nand_evter_intr_en; + u32 nand_vol_addr_stat; + u32 res18; + u32 nand_erattr0; + u32 nand_erattr1; + u32 res19[0x10]; + u32 nand_fsr; + u32 res20[0x1]; + u32 nand_eccstat[8]; + u32 res21[0x1c]; + u32 nanndcr; + u32 res22[0x2]; + u32 nand_autoboot_trgr; + u32 res23; + u32 nand_mdr; + u32 res24[0x1c]; + u32 nand_dll_lowcfg0; + u32 nand_dll_lowcfg1; + u32 res25; + u32 nand_dll_lowstat; + u32 res26[0x3C]; +}; + +/* + * IFC controller NOR Machine registers + */ +struct fsl_ifc_nor { + u32 nor_evter_stat; + u32 res1[0x2]; + u32 nor_evter_en; + u32 res2[0x2]; + u32 nor_evter_intr_en; + u32 res3[0x2]; + u32 nor_erattr0; + u32 nor_erattr1; + u32 nor_erattr2; + u32 res4[0x4]; + u32 norcr; + u32 res5[0xEF]; +}; + +/* + * IFC controller GPCM Machine registers + */ +struct fsl_ifc_gpcm { + u32 gpcm_evter_stat; + u32 res1[0x2]; + u32 gpcm_evter_en; + u32 res2[0x2]; + u32 gpcm_evter_intr_en; + u32 res3[0x2]; + u32 gpcm_erattr0; + u32 gpcm_erattr1; + u32 gpcm_erattr2; + u32 gpcm_stat; +}; + +#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT +#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8) +#define IFC_CSPR_REG_LEN 148 +#define IFC_AMASK_REG_LEN 144 +#define IFC_CSOR_REG_LEN 144 +#define IFC_FTIM_REG_LEN 576 + +#define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \ + CONFIG_SYS_FSL_IFC_BANK_COUNT +#define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \ + CONFIG_SYS_FSL_IFC_BANK_COUNT +#define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \ + CONFIG_SYS_FSL_IFC_BANK_COUNT +#define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \ + CONFIG_SYS_FSL_IFC_BANK_COUNT +#else +#error IFC BANK count not vaild +#endif +#else +#error IFC BANK count not defined +#endif + +struct fsl_ifc_cspr { + u32 cspr_ext; + u32 cspr; + u32 res; +}; + +struct fsl_ifc_amask { + u32 amask; + u32 res[0x2]; +}; + +struct fsl_ifc_csor { + u32 csor; + u32 csor_ext; + u32 res; +}; + +struct fsl_ifc_ftim { + u32 ftim[4]; + u32 res[0x8]; +}; + +/* + * IFC Controller Global Registers + * FCM - Flash control machine + */ + +struct fsl_ifc_fcm { + u32 ifc_rev; + u32 res1[0x2]; + struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; + u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN]; + struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; + u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN]; + struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; + u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN]; + struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; + u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN]; + u32 rb_stat; + u32 rb_map; + u32 wp_map; + u32 ifc_gcr; + u32 res7[0x2]; + u32 cm_evter_stat; + u32 res8[0x2]; + u32 cm_evter_en; + u32 res9[0x2]; + u32 cm_evter_intr_en; + u32 res10[0x2]; + u32 cm_erattr0; + u32 cm_erattr1; + u32 res11[0x2]; + u32 ifc_ccr; + u32 ifc_csr; + u32 ddr_ccr_low; +}; + +struct fsl_ifc_runtime { + struct fsl_ifc_nand ifc_nand; + struct fsl_ifc_nor ifc_nor; + struct fsl_ifc_gpcm ifc_gpcm; +}; + +struct fsl_ifc { + struct fsl_ifc_fcm *gregs; + struct fsl_ifc_runtime *rregs; +}; + +struct ifc_regs { + const char *name; + u32 pr; + u32 pr_ext; + u32 amask; + u32 or; + u32 ftim[4]; + u32 or_ext; + u32 pr_final; + u32 amask_final; +}; + +struct ifc_regs_info { + struct ifc_regs *regs; + u32 cs_size; +}; + +#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 +#undef CSPR_MSEL_NOR +#define CSPR_MSEL_NOR CSPR_MSEL_GPCM +#endif +#endif /* CONFIG_FSL_IFC */ + +#endif /* __ASSEMBLY__ */ +#endif /* __FSL_IFC_H */ diff --git a/roms/u-boot/include/fsl_immap.h b/roms/u-boot/include/fsl_immap.h new file mode 100644 index 000000000..5297c0b3f --- /dev/null +++ b/roms/u-boot/include/fsl_immap.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Common internal memory map for some Freescale SoCs + * + * Copyright 2013-2014 Freescale Semiconductor, Inc. + */ + +#ifndef __FSL_IMMAP_H +#define __FSL_IMMAP_H +/* + * DDR memory controller registers + * This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx. + */ +struct ccsr_ddr { + u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ + u8 res_04[4]; + u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ + u8 res_0c[4]; + u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ + u8 res_14[4]; + u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ + u8 res_1c[100]; + u32 cs0_config; /* Chip Select Configuration */ + u32 cs1_config; /* Chip Select Configuration */ + u32 cs2_config; /* Chip Select Configuration */ + u32 cs3_config; /* Chip Select Configuration */ + u8 res_90[48]; + u32 cs0_config_2; /* Chip Select Configuration 2 */ + u32 cs1_config_2; /* Chip Select Configuration 2 */ + u32 cs2_config_2; /* Chip Select Configuration 2 */ + u32 cs3_config_2; /* Chip Select Configuration 2 */ + u8 res_d0[48]; + u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ + u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ + u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ + u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ + u32 sdram_cfg; /* SDRAM Control Configuration */ + u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ + u32 sdram_mode; /* SDRAM Mode Configuration */ + u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ + u32 sdram_md_cntl; /* SDRAM Mode Control */ + u32 sdram_interval; /* SDRAM Interval Configuration */ + u32 sdram_data_init; /* SDRAM Data initialization */ + u8 res_12c[4]; + u32 sdram_clk_cntl; /* SDRAM Clock Control */ + u8 res_134[20]; + u32 init_addr; /* training init addr */ + u32 init_ext_addr; /* training init extended addr */ + u8 res_150[16]; + u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ + u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ + u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */ + u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */ + u32 ddr_zq_cntl; /* ZQ calibration control*/ + u32 ddr_wrlvl_cntl; /* write leveling control*/ + u8 reg_178[4]; + u32 ddr_sr_cntr; /* self refresh counter */ + u32 ddr_sdram_rcw_1; /* Control Words 1 */ + u32 ddr_sdram_rcw_2; /* Control Words 2 */ + u8 reg_188[8]; + u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ + u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ + u8 res_198[0x1a0-0x198]; + u32 ddr_sdram_rcw_3; + u32 ddr_sdram_rcw_4; + u32 ddr_sdram_rcw_5; + u32 ddr_sdram_rcw_6; + u8 res_1b0[0x200-0x1b0]; + u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ + u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ + u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ + u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ + u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ + u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ + u8 res_218[0x220-0x218]; + u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */ + u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */ + u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */ + u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */ + u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */ + u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */ + u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */ + u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */ + u8 res_240[0x250-0x240]; + u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */ + u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */ + u8 res_258[0x260-0x258]; + u32 sdram_cfg_3; + u8 res_264[0x400-0x264]; + u32 dq_map_0; + u32 dq_map_1; + u32 dq_map_2; + u32 dq_map_3; + u8 res_410[0xb20-0x410]; + u32 ddr_dsr1; /* Debug Status 1 */ + u32 ddr_dsr2; /* Debug Status 2 */ + u32 ddr_cdr1; /* Control Driver 1 */ + u32 ddr_cdr2; /* Control Driver 2 */ + u8 res_b30[200]; + u32 ip_rev1; /* IP Block Revision 1 */ + u32 ip_rev2; /* IP Block Revision 2 */ + u32 eor; /* Enhanced Optimization Register */ + u8 res_c04[252]; + u32 mtcr; /* Memory Test Control Register */ + u8 res_d04[28]; + u32 mtp1; /* Memory Test Pattern 1 */ + u32 mtp2; /* Memory Test Pattern 2 */ + u32 mtp3; /* Memory Test Pattern 3 */ + u32 mtp4; /* Memory Test Pattern 4 */ + u32 mtp5; /* Memory Test Pattern 5 */ + u32 mtp6; /* Memory Test Pattern 6 */ + u32 mtp7; /* Memory Test Pattern 7 */ + u32 mtp8; /* Memory Test Pattern 8 */ + u32 mtp9; /* Memory Test Pattern 9 */ + u32 mtp10; /* Memory Test Pattern 10 */ + u8 res_d48[184]; + u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ + u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ + u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ + u8 res_e0c[20]; + u32 capture_data_hi; /* Data Path Read Capture High */ + u32 capture_data_lo; /* Data Path Read Capture Low */ + u32 capture_ecc; /* Data Path Read Capture ECC */ + u8 res_e2c[20]; + u32 err_detect; /* Error Detect */ + u32 err_disable; /* Error Disable */ + u32 err_int_en; + u32 capture_attributes; /* Error Attrs Capture */ + u32 capture_address; /* Error Addr Capture */ + u32 capture_ext_address; /* Error Extended Addr Capture */ + u32 err_sbe; /* Single-Bit ECC Error Management */ + u8 res_e5c[164]; + u32 debug[64]; /* debug_1 to debug_64 */ +}; + +#ifdef CONFIG_SYS_FSL_HAS_CCI400 +#define CCI400_CTRLORD_TERM_BARRIER 0x00000008 +#define CCI400_CTRLORD_EN_BARRIER 0 +#define CCI400_SHAORD_NON_SHAREABLE 0x00000002 +#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 +#define CCI400_SNOOP_REQ_EN 0x00000001 + +/* CCI-400 registers */ +struct ccsr_cci400 { + u32 ctrl_ord; /* Control Override */ + u32 spec_ctrl; /* Speculation Control */ + u32 secure_access; /* Secure Access */ + u32 status; /* Status */ + u32 impr_err; /* Imprecise Error */ + u8 res_14[0x100 - 0x14]; + u32 pmcr; /* Performance Monitor Control */ + u8 res_104[0xfd0 - 0x104]; + u32 pid[8]; /* Peripheral ID */ + u32 cid[4]; /* Component ID */ + struct { + u32 snoop_ctrl; /* Snoop Control */ + u32 sha_ord; /* Shareable Override */ + u8 res_1008[0x1100 - 0x1008]; + u32 rc_qos_ord; /* read channel QoS Value Override */ + u32 wc_qos_ord; /* read channel QoS Value Override */ + u8 res_1108[0x110c - 0x1108]; + u32 qos_ctrl; /* QoS Control */ + u32 max_ot; /* Max OT */ + u8 res_1114[0x1130 - 0x1114]; + u32 target_lat; /* Target Latency */ + u32 latency_regu; /* Latency Regulation */ + u32 qos_range; /* QoS Range */ + u8 res_113c[0x2000 - 0x113c]; + } slave[5]; /* Slave Interface */ + u8 res_6000[0x9004 - 0x6000]; + u32 cycle_counter; /* Cycle counter */ + u32 count_ctrl; /* Count Control */ + u32 overflow_status; /* Overflow Flag Status */ + u8 res_9010[0xa000 - 0x9010]; + struct { + u32 event_select; /* Event Select */ + u32 event_count; /* Event Count */ + u32 counter_ctrl; /* Counter Control */ + u32 overflow_status; /* Overflow Flag Status */ + u8 res_a010[0xb000 - 0xa010]; + } pcounter[4]; /* Performance Counter */ + u8 res_e004[0x10000 - 0xe004]; +}; +#endif + +#endif /* __FSL_IMMAP_H */ diff --git a/roms/u-boot/include/fsl_lpuart.h b/roms/u-boot/include/fsl_lpuart.h new file mode 100644 index 000000000..511fb8436 --- /dev/null +++ b/roms/u-boot/include/fsl_lpuart.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + */ + +#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \ + defined(CONFIG_ARCH_IMXRT) +struct lpuart_fsl_reg32 { + u32 verid; + u32 param; + u32 global; + u32 pincfg; + u32 baud; + u32 stat; + u32 ctrl; + u32 data; + u32 match; + u32 modir; + u32 fifo; + u32 water; +}; +#else +struct lpuart_fsl_reg32 { + u32 baud; + u32 stat; + u32 ctrl; + u32 data; + u32 match; + u32 modir; + u32 fifo; + u32 water; +}; +#endif + +struct lpuart_fsl { + u8 ubdh; + u8 ubdl; + u8 uc1; + u8 uc2; + u8 us1; + u8 us2; + u8 uc3; + u8 ud; + u8 uma1; + u8 uma2; + u8 uc4; + u8 uc5; + u8 ued; + u8 umodem; + u8 uir; + u8 reserved; + u8 upfifo; + u8 ucfifo; + u8 usfifo; + u8 utwfifo; + u8 utcfifo; + u8 urwfifo; + u8 urcfifo; + u8 rsvd[28]; +}; + +/* Used on i.MX7ULP */ +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000) +#define LPUART_BAUD_OSR_MASK (0x1F000000) +#define LPUART_BAUD_OSR_SHIFT (24) +#define LPUART_BAUD_OSR(x) ((((uint32_t)(x)) << 24) & 0x1F000000) +#define LPUART_BAUD_SBR_MASK (0x1FFF) +#define LPUART_BAUD_SBR_SHIFT (0U) +#define LPUART_BAUD_SBR(x) (((uint32_t)(x)) & 0x1FFF) +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_SBNS_MASK (0x2000U) diff --git a/roms/u-boot/include/fsl_mdio.h b/roms/u-boot/include/fsl_mdio.h new file mode 100644 index 000000000..b6c02cf34 --- /dev/null +++ b/roms/u-boot/include/fsl_mdio.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2009-2012, 2013 Freescale Semiconductor, Inc. + * Jun-jie Zhang + * Mingkai Hu + */ + +#ifndef __FSL_PHY_H__ +#define __FSL_PHY_H__ + +#include +#include + +struct tsec_mii_mng { + u32 miimcfg; /* MII management configuration reg */ + u32 miimcom; /* MII management command reg */ + u32 miimadd; /* MII management address reg */ + u32 miimcon; /* MII management control reg */ + u32 miimstat; /* MII management status reg */ + u32 miimind; /* MII management indication reg */ + u32 ifstat; /* Interface Status Register */ +}; + +int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc); + +/* PHY register offsets */ +#define PHY_EXT_PAGE_ACCESS 0x1f + +/* MII Management Configuration Register */ +#define MIIMCFG_RESET_MGMT 0x80000000 +#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007 +#define MIIMCFG_INIT_VALUE 0x00000003 + +/* MII Management Command Register */ +#define MIIMCOM_READ_CYCLE 0x00000001 +#define MIIMCOM_SCAN_CYCLE 0x00000002 + +/* MII Management Address Register */ +#define MIIMADD_PHY_ADDR_SHIFT 8 + +/* MII Management Indicator Register */ +#define MIIMIND_BUSY 0x00000001 +#define MIIMIND_NOTVALID 0x00000004 + +void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr, + int dev_addr, int reg, int value); +int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr, + int dev_addr, int regnum); +int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum); +int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum, + u16 value); +int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, + int regnum, u16 value); +int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, + int regnum); +int memac_mdio_reset(struct mii_dev *bus); + +struct fsl_pq_mdio_data { + u32 mdio_regs_off; +}; + +struct fsl_pq_mdio_info { + struct tsec_mii_mng __iomem *regs; + char *name; +}; +int fsl_pq_mdio_init(struct bd_info *bis, struct fsl_pq_mdio_info *info); + +#endif /* __FSL_PHY_H__ */ diff --git a/roms/u-boot/include/fsl_memac.h b/roms/u-boot/include/fsl_memac.h new file mode 100644 index 000000000..d067f1511 --- /dev/null +++ b/roms/u-boot/include/fsl_memac.h @@ -0,0 +1,264 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Roy Zang + */ + +#ifndef __MEMAC_H__ +#define __MEMAC_H__ + +#include + +struct memac { + /* memac general control and status registers */ + u32 res_0[2]; + u32 command_config; /* Control and configuration register */ + u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */ + u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */ + u32 maxfrm; /* Maximum frame length register */ + u32 res_18[5]; + u32 hashtable_ctrl; /* Hash table control register */ + u32 res_30[4]; + u32 ievent; /* Interrupt event register */ + u32 tx_ipg_length; /* Transmitter inter-packet-gap register */ + u32 res_48; + u32 imask; /* interrupt mask register */ + u32 res_50; + u32 cl_pause_quanta[4]; /* CL01-CL67 pause quanta register */ + u32 cl_pause_thresh[4]; /* CL01-CL67 pause thresh register */ + u32 rx_pause_status; /* Receive pause status register */ + u32 res_78[2]; + u32 mac_addr[14]; /* MAC address */ + u32 lpwake_timer; /* EEE low power wakeup timer register */ + u32 sleep_timer; /* Transmit EEE Low Power Timer register */ + u32 res_c0[8]; + u32 statn_config; /* Statistics configuration register */ + u32 res_e4[7]; + + /* memac statistics counter registers */ + u32 rx_eoct_l; /* Rx ethernet octests lower */ + u32 rx_eoct_u; /* Rx ethernet octests upper */ + u32 rx_oct_l; /* Rx octests lower */ + u32 rx_oct_u; /* Rx octests upper */ + u32 rx_align_err_l; /* Rx alignment error lower */ + u32 rx_align_err_u; /* Rx alignment error upper */ + u32 rx_pause_frame_l; /* Rx valid pause frame upper */ + u32 rx_pause_frame_u; /* Rx valid pause frame upper */ + u32 rx_frame_l; /* Rx frame counter lower */ + u32 rx_frame_u; /* Rx frame counter upper */ + u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */ + u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */ + u32 rx_vlan_l; /* Rx VLAN frame lower */ + u32 rx_vlan_u; /* Rx VLAN frame upper */ + u32 rx_err_l; /* Rx frame error lower */ + u32 rx_err_u; /* Rx frame error upper */ + u32 rx_uni_l; /* Rx unicast frame lower */ + u32 rx_uni_u; /* Rx unicast frame upper */ + u32 rx_multi_l; /* Rx multicast frame lower */ + u32 rx_multi_u; /* Rx multicast frame upper */ + u32 rx_brd_l; /* Rx broadcast frame lower */ + u32 rx_brd_u; /* Rx broadcast frame upper */ + u32 rx_drop_l; /* Rx dropped packets lower */ + u32 rx_drop_u; /* Rx dropped packets upper */ + u32 rx_pkt_l; /* Rx packets lower */ + u32 rx_pkt_u; /* Rx packets upper */ + u32 rx_undsz_l; /* Rx undersized packet lower */ + u32 rx_undsz_u; /* Rx undersized packet upper */ + u32 rx_64_l; /* Rx 64 oct packet lower */ + u32 rx_64_u; /* Rx 64 oct packet upper */ + u32 rx_127_l; /* Rx 65 to 127 oct packet lower */ + u32 rx_127_u; /* Rx 65 to 127 oct packet upper */ + u32 rx_255_l; /* Rx 128 to 255 oct packet lower */ + u32 rx_255_u; /* Rx 128 to 255 oct packet upper */ + u32 rx_511_l; /* Rx 256 to 511 oct packet lower */ + u32 rx_511_u; /* Rx 256 to 511 oct packet upper */ + u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */ + u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */ + u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */ + u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */ + u32 rx_1519_l; /* Rx 1519 to max oct packet lower */ + u32 rx_1519_u; /* Rx 1519 to max oct packet upper */ + u32 rx_oversz_l; /* Rx oversized packet lower */ + u32 rx_oversz_u; /* Rx oversized packet upper */ + u32 rx_jabber_l; /* Rx Jabber packet lower */ + u32 rx_jabber_u; /* Rx Jabber packet upper */ + u32 rx_frag_l; /* Rx Fragment packet lower */ + u32 rx_frag_u; /* Rx Fragment packet upper */ + u32 rx_cnp_l; /* Rx control packet lower */ + u32 rx_cnp_u; /* Rx control packet upper */ + u32 rx_drntp_l; /* Rx dripped not truncated packet lower */ + u32 rx_drntp_u; /* Rx dripped not truncated packet upper */ + u32 res_1d0[0xc]; + + u32 tx_eoct_l; /* Tx ethernet octests lower */ + u32 tx_eoct_u; /* Tx ethernet octests upper */ + u32 tx_oct_l; /* Tx octests lower */ + u32 tx_oct_u; /* Tx octests upper */ + u32 res_210[0x2]; + u32 tx_pause_frame_l; /* Tx valid pause frame lower */ + u32 tx_pause_frame_u; /* Tx valid pause frame upper */ + u32 tx_frame_l; /* Tx frame counter lower */ + u32 tx_frame_u; /* Tx frame counter upper */ + u32 tx_frame_crc_err_l; /* Tx frame check sequence error lower */ + u32 tx_frame_crc_err_u; /* Tx frame check sequence error upper */ + u32 tx_vlan_l; /* Tx VLAN frame lower */ + u32 tx_vlan_u; /* Tx VLAN frame upper */ + u32 tx_frame_err_l; /* Tx frame error lower */ + u32 tx_frame_err_u; /* Tx frame error upper */ + u32 tx_uni_l; /* Tx unicast frame lower */ + u32 tx_uni_u; /* Tx unicast frame upper */ + u32 tx_multi_l; /* Tx multicast frame lower */ + u32 tx_multi_u; /* Tx multicast frame upper */ + u32 tx_brd_l; /* Tx broadcast frame lower */ + u32 tx_brd_u; /* Tx broadcast frame upper */ + u32 res_258[0x2]; + u32 tx_pkt_l; /* Tx packets lower */ + u32 tx_pkt_u; /* Tx packets upper */ + u32 tx_undsz_l; /* Tx undersized packet lower */ + u32 tx_undsz_u; /* Tx undersized packet upper */ + u32 tx_64_l; /* Tx 64 oct packet lower */ + u32 tx_64_u; /* Tx 64 oct packet upper */ + u32 tx_127_l; /* Tx 65 to 127 oct packet lower */ + u32 tx_127_u; /* Tx 65 to 127 oct packet upper */ + u32 tx_255_l; /* Tx 128 to 255 oct packet lower */ + u32 tx_255_u; /* Tx 128 to 255 oct packet upper */ + u32 tx_511_l; /* Tx 256 to 511 oct packet lower */ + u32 tx_511_u; /* Tx 256 to 511 oct packet upper */ + u32 tx_1023_l; /* Tx 512 to 1023 oct packet lower */ + u32 tx_1023_u; /* Tx 512 to 1023 oct packet upper */ + u32 tx_1518_l; /* Tx 1024 to 1518 oct packet lower */ + u32 tx_1518_u; /* Tx 1024 to 1518 oct packet upper */ + u32 tx_1519_l; /* Tx 1519 to max oct packet lower */ + u32 tx_1519_u; /* Tx 1519 to max oct packet upper */ + u32 res_2a8[0x6]; + u32 tx_cnp_l; /* Tx control packet lower */ + u32 tx_cnp_u; /* Tx control packet upper */ + u32 res_2c8[0xe]; + + /* Line interface control register */ + u32 if_mode; /* interface mode control */ + u32 if_status; /* interface status */ + u32 res_308[0xe]; + + /* HiGig/2 Register */ + u32 hg_config; /* HiGig2 control and configuration */ + u32 res_344[0x3]; + u32 hg_pause_quanta; /* HiGig2 pause quanta */ + u32 res_354[0x3]; + u32 hg_pause_thresh; /* HiGig2 pause quanta threshold */ + u32 res_364[0x3]; + u32 hgrx_pause_status; /* HiGig2 rx pause quanta status */ + u32 hg_fifos_status; /* HiGig2 fifos status */ + u32 rhm; /* Rx HiGig2 message counter register */ + u32 thm;/* Tx HiGig2 message counter register */ + u32 res_380[0x320]; +}; + +/* COMMAND_CONFIG - command and configuration register */ +#define MEMAC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */ +#define MEMAC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */ +#define MEMAC_CMD_CFG_RXTX_EN (MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN) +#define MEMAC_CMD_CFG_NO_LEN_CHK 0x20000 /* Payload length check disable */ + +/* HASHTABLE_CTRL - Hashtable control register */ +#define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */ +#define HASHTABLE_CTRL_ADDR_MASK 0x000001ff + +/* TX_IPG_LENGTH - Transmit inter-packet gap length register */ +#define TX_IPG_LENGTH_IPG_LEN_MASK 0x000003ff + +/* IMASK - interrupt mask register */ +#define IMASK_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event mask */ +#define IMASK_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion mask */ +#define IMASK_REM_FAULT 0x00004000 /* remote fault mask */ +#define IMASK_LOC_FAULT 0x00002000 /* local fault mask */ +#define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */ +#define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */ +#define IMASK_TX_ER 0x00000200 /* Tx frame error mask */ +#define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */ +#define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */ +#define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */ +#define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */ +#define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */ +#define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */ +#define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */ +#define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */ +#define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */ + +#define IMASK_MASK_ALL 0x00000000 + +/* IEVENT - interrupt event register */ +#define IEVENT_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event */ +#define IEVENT_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion */ +#define IEVENT_REM_FAULT 0x00004000 /* remote fault */ +#define IEVENT_LOC_FAULT 0x00002000 /* local fault */ +#define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */ +#define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */ +#define IEVENT_TX_ER 0x00000200 /* Tx frame error */ +#define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */ +#define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */ +#define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */ +#define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */ +#define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */ +#define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */ +#define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */ +#define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */ +#define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */ + +#define IEVENT_CLEAR_ALL 0xffffffff + +/* IF_MODE - Interface Mode Register */ +#define IF_MODE_EN_AUTO 0x00008000 /* 1 - Enable automatic speed selection */ +#define IF_MODE_SETSP_100M 0x00000000 /* 00 - 100Mbps RGMII */ +#define IF_MODE_SETSP_10M 0x00002000 /* 01 - 10Mbps RGMII */ +#define IF_MODE_SETSP_1000M 0x00004000 /* 10 - 1000Mbps RGMII */ +#define IF_MODE_SETSP_MASK 0x00006000 /* setsp mask bits */ +#define IF_MODE_XGMII 0x00000000 /* 00- XGMII(10) interface mode */ +#define IF_MODE_GMII 0x00000002 /* 10- GMII interface mode */ +#define IF_MODE_MASK 0x00000003 /* mask for mode interface mode */ +#define IF_MODE_RG 0x00000004 /* 1- RGMII */ +#define IF_MODE_RM 0x00000008 /* 1- RGMII */ + +#define IF_DEFAULT (IF_GMII) + +/* Internal PHY Registers - SGMII */ +#define PHY_SGMII_CR_PHY_RESET 0x8000 +#define PHY_SGMII_CR_RESET_AN 0x0200 +#define PHY_SGMII_CR_DEF_VAL 0x1140 +#define PHY_SGMII_IF_SPEED_GIGABIT 0x0008 +#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001 +#define PHY_SGMII_IF_MODE_AN 0x0002 +#define PHY_SGMII_IF_MODE_SGMII 0x0001 + +struct memac_mdio_controller { + u32 res0[0xc]; + u32 mdio_stat; /* MDIO configuration and status */ + u32 mdio_ctl; /* MDIO control */ + u32 mdio_data; /* MDIO data */ + u32 mdio_addr; /* MDIO address */ +}; + +#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8) +#define MDIO_STAT_BSY (1 << 0) +#define MDIO_STAT_RD_ER (1 << 1) +#define MDIO_STAT_PRE (1 << 5) +#define MDIO_STAT_ENC (1 << 6) +#define MDIO_STAT_HOLD_15_CLK (7 << 2) +#define MDIO_STAT_NEG (1 << 23) + +#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f) +#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5) +#define MDIO_CTL_PRE_DIS (1 << 10) +#define MDIO_CTL_SCAN_EN (1 << 11) +#define MDIO_CTL_POST_INC (1 << 14) +#define MDIO_CTL_READ (1 << 15) + +#define MDIO_DATA(x) (x & 0xffff) +#define MDIO_DATA_BSY (1 << 31) + +struct fsl_enet_mac; + +void init_memac(struct fsl_enet_mac *mac, void *base, void *phyregs, + int max_rx_len); + +#endif diff --git a/roms/u-boot/include/fsl_mmdc.h b/roms/u-boot/include/fsl_mmdc.h new file mode 100644 index 000000000..05fb41f40 --- /dev/null +++ b/roms/u-boot/include/fsl_mmdc.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +#ifndef FSL_MMDC_H +#define FSL_MMDC_H + +/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */ +#define MPWLGCR_HW_WL_EN (1 << 0) + +/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */ +#define MPPDCMPR2_MPR_COMPARE_EN (1 << 0) + + +/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */ +#define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28) + +/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */ +#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4) + +/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */ +#define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067 + +/* MMDC Core Refresh Control Register (MMDC_MDREF) */ +#define MDREF_START_REFRESH (1 << 0) + +/* MMDC Core Special Command Register (MDSCR) */ +#define CMD_ADDR_MSB_MR_OP(x) (x << 24) +#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16) +#define MDSCR_DISABLE_CFG_REQ (0 << 15) +#define MDSCR_ENABLE_CON_REQ (1 << 15) +#define MDSCR_CON_ACK (1 << 14) +#define MDSCR_WL_EN (1 << 9) +#define CMD_NORMAL (0 << 4) +#define CMD_PRECHARGE (1 << 4) +#define CMD_AUTO_REFRESH (2 << 4) +#define CMD_LOAD_MODE_REG (3 << 4) +#define CMD_ZQ_CALIBRATION (4 << 4) +#define CMD_PRECHARGE_BANK_OPEN (5 << 4) +#define CMD_MRR (6 << 4) +#define CMD_BANK_ADDR_0 0x0 +#define CMD_BANK_ADDR_1 0x1 +#define CMD_BANK_ADDR_2 0x2 +#define CMD_BANK_ADDR_3 0x3 +#define CMD_BANK_ADDR_4 0x4 +#define CMD_BANK_ADDR_5 0x5 +#define CMD_BANK_ADDR_6 0x6 +#define CMD_BANK_ADDR_7 0x7 + +/* MMDC Core Control Register (MDCTL) */ +#define MDCTL_SDE0 (1 << 31) +#define MDCTL_SDE1 (1 << 30) + +/* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */ +#define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16) + +/* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */ +#define MMDC_MPMUR0_FRC_MSR (1 << 11) + +/* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */ +/* default 64 for a quarter cycle delay */ +#define MMDC_MPRDDLCTL_DEFAULT_DELAY 0x40404040 + +/* MMDC Registers */ +struct mmdc_regs { + u32 mdctl; + u32 mdpdc; + u32 mdotc; + u32 mdcfg0; + u32 mdcfg1; + u32 mdcfg2; + u32 mdmisc; + u32 mdscr; + u32 mdref; + u32 res1[2]; + u32 mdrwd; + u32 mdor; + u32 mdmrr; + u32 mdcfg3lp; + u32 mdmr4; + u32 mdasp; + u32 res2[239]; + u32 maarcr; + u32 mapsr; + u32 maexidr0; + u32 maexidr1; + u32 madpcr0; + u32 madpcr1; + u32 madpsr0; + u32 madpsr1; + u32 madpsr2; + u32 madpsr3; + u32 madpsr4; + u32 madpsr5; + u32 masbs0; + u32 masbs1; + u32 res3[2]; + u32 magenp; + u32 res4[239]; + u32 mpzqhwctrl; + u32 mpzqswctrl; + u32 mpwlgcr; + u32 mpwldectrl0; + u32 mpwldectrl1; + u32 mpwldlst; + u32 mpodtctrl; + u32 mprddqby0dl; + u32 mprddqby1dl; + u32 mprddqby2dl; + u32 mprddqby3dl; + u32 mpwrdqby0dl; + u32 mpwrdqby1dl; + u32 mpwrdqby2dl; + u32 mpwrdqby3dl; + u32 mpdgctrl0; + u32 mpdgctrl1; + u32 mpdgdlst0; + u32 mprddlctl; + u32 mprddlst; + u32 mpwrdlctl; + u32 mpwrdlst; + u32 mpsdctrl; + u32 mpzqlp2ctl; + u32 mprddlhwctl; + u32 mpwrdlhwctl; + u32 mprddlhwst0; + u32 mprddlhwst1; + u32 mpwrdlhwst0; + u32 mpwrdlhwst1; + u32 mpwlhwerr; + u32 mpdghwst0; + u32 mpdghwst1; + u32 mpdghwst2; + u32 mpdghwst3; + u32 mppdcmpr1; + u32 mppdcmpr2; + u32 mpswdar0; + u32 mpswdrdr0; + u32 mpswdrdr1; + u32 mpswdrdr2; + u32 mpswdrdr3; + u32 mpswdrdr4; + u32 mpswdrdr5; + u32 mpswdrdr6; + u32 mpswdrdr7; + u32 mpmur0; + u32 mpwrcadl; + u32 mpdccr; +}; + +struct fsl_mmdc_info { + u32 mdctl; + u32 mdpdc; + u32 mdotc; + u32 mdcfg0; + u32 mdcfg1; + u32 mdcfg2; + u32 mdmisc; + u32 mdref; + u32 mdrwd; + u32 mdor; + u32 mdasp; + u32 mpodtctrl; + u32 mpzqhwctrl; + u32 mprddlctl; +}; + +void mmdc_init(const struct fsl_mmdc_info *); + +#endif /* FSL_MMDC_H */ diff --git a/roms/u-boot/include/fsl_pmic.h b/roms/u-boot/include/fsl_pmic.h new file mode 100644 index 000000000..132db8175 --- /dev/null +++ b/roms/u-boot/include/fsl_pmic.h @@ -0,0 +1,160 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + */ + +#ifndef __FSL_PMIC_H__ +#define __FSL_PMIC_H__ + +/* + * The registers of different PMIC has the same meaning + * but the bit positions of the fields can differ or + * some fields has a meaning only on some devices. + * You have to check with the internal SPI bitmap + * (see Freescale Documentation) to set the registers + * for the device you are using + */ +enum { + REG_INT_STATUS0 = 0, + REG_INT_MASK0, + REG_INT_SENSE0, + REG_INT_STATUS1, + REG_INT_MASK1, + REG_INT_SENSE1, + REG_PU_MODE_S, + REG_IDENTIFICATION, + REG_UNUSED0, + REG_ACC0, + REG_ACC1, /*10 */ + REG_UNUSED1, + REG_UNUSED2, + REG_POWER_CTL0, + REG_POWER_CTL1, + REG_POWER_CTL2, + REG_REGEN_ASSIGN, + REG_UNUSED3, + REG_MEM_A, + REG_MEM_B, + REG_RTC_TIME, /*20 */ + REG_RTC_ALARM, + REG_RTC_DAY, + REG_RTC_DAY_ALARM, + REG_SW_0, + REG_SW_1, + REG_SW_2, + REG_SW_3, + REG_SW_4, + REG_SW_5, + REG_SETTING_0, /*30 */ + REG_SETTING_1, + REG_MODE_0, + REG_MODE_1, + REG_POWER_MISC, + REG_UNUSED4, + REG_UNUSED5, + REG_UNUSED6, + REG_UNUSED7, + REG_UNUSED8, + REG_UNUSED9, /*40 */ + REG_UNUSED10, + REG_UNUSED11, + REG_ADC0, + REG_ADC1, + REG_ADC2, + REG_ADC3, + REG_ADC4, + REG_CHARGE, + REG_USB0, + REG_USB1, /*50 */ + REG_LED_CTL0, + REG_LED_CTL1, + REG_LED_CTL2, + REG_LED_CTL3, + REG_UNUSED12, + REG_UNUSED13, + REG_TRIM0, + REG_TRIM1, + REG_TEST0, + REG_TEST1, /*60 */ + REG_TEST2, + REG_TEST3, + REG_TEST4, + PMIC_NUM_OF_REGS, +}; + +/* REG_POWER_MISC */ +#define GPO1EN (1 << 6) +#define GPO1STBY (1 << 7) +#define GPO2EN (1 << 8) +#define GPO2STBY (1 << 9) +#define GPO3EN (1 << 10) +#define GPO3STBY (1 << 11) +#define GPO4EN (1 << 12) +#define GPO4STBY (1 << 13) +#define PWGT1SPIEN (1 << 15) +#define PWGT2SPIEN (1 << 16) +#define PWUP (1 << 21) + +/* Power Control 0 */ +#define COINCHEN (1 << 23) +#define BATTDETEN (1 << 19) + +/* Interrupt status 1 */ +#define RTCRSTI (1 << 7) + +/* MC34708 Definitions */ +#define SWx_VOLT_MASK_MC34708 0x3F +#define SWx_1_110V_MC34708 0x24 +#define SWx_1_250V_MC34708 0x30 +#define SWx_1_300V_MC34708 0x34 +#define TIMER_MASK_MC34708 0x300 +#define TIMER_4S_MC34708 0x100 +#define VUSBSEL_MC34708 (1 << 2) +#define VUSBEN_MC34708 (1 << 3) +#define SWBST_CTRL 31 +#define SWBST_AUTO 0x8 + +#define MC34708_REG_SW12_OPMODE 28 + +#define MC34708_SW1AMODE_MASK 0x00000f +#define MC34708_SW1AMHMODE 0x000010 +#define MC34708_SW1AUOMODE 0x000020 +#define MC34708_SW1DVSSPEED 0x0000c0 +#define MC34708_SW2MODE_MASK 0x03c000 +#define MC34708_SW2MHMODE 0x040000 +#define MC34708_SW2UOMODE 0x080000 +#define MC34708_SW2DVSSPEED 0x300000 +#define MC34708_PLLEN 0x400000 +#define MC34708_PLLX 0x800000 + +#define MC34708_REG_SW345_OPMODE 29 + +#define MC34708_SW3MODE_MASK 0x00000f +#define MC34708_SW3MHMODE 0x000010 +#define MC34708_SW3UOMODE 0x000020 +#define MC34708_SW4AMODE_MASK 0x0003c0 +#define MC34708_SW4AMHMODE 0x000400 +#define MC34708_SW4AUOMODE 0x000800 +#define MC34708_SW4BMODE_MASK 0x00f000 +#define MC34708_SW4BMHMODE 0x010000 +#define MC34708_SW4BUOMODE 0x020000 +#define MC34708_SW5MODE_MASK 0x3c0000 +#define MC34708_SW5MHMODE 0x400000 +#define MC34708_SW5UOMODE 0x800000 + +#define SW_MODE_OFFOFF 0x00 +#define SW_MODE_PWMOFF 0x01 +#define SW_MODE_PFMOFF 0x03 +#define SW_MODE_APSOFF 0x04 +#define SW_MODE_PWMPWM 0x05 +#define SW_MODE_PWMAPS 0x06 +#define SW_MODE_APSAPS 0x08 +#define SW_MODE_APSPFM 0x0c +#define SW_MODE_PWMPFM 0x0d +#define SW_MODE_PFMPFM 0x0f + +#define MC34708_TRANSFER_SIZE 3 +#endif diff --git a/roms/u-boot/include/fsl_qbman.h b/roms/u-boot/include/fsl_qbman.h new file mode 100644 index 000000000..4687eb9bb --- /dev/null +++ b/roms/u-boot/include/fsl_qbman.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + */ + +#ifndef __FSL_QBMAN_H__ +#define __FSL_QBMAN_H__ +void fdt_fixup_qportals(void *blob); +void fdt_fixup_bportals(void *blob); +void inhibit_portals(void __iomem *addr, int max_portals, + int arch_max_portals, int portal_cinh_size); +void setup_qbman_portals(void); + +struct ccsr_qman { +#ifdef CONFIG_SYS_FSL_QMAN_V3 + u8 res0[0x200]; +#else + struct { + u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ + u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ + u32 res; + u32 qcsp_dd_cfg; /* 0xc - SW Portal Dynamic Debug cfg */ + } qcsp[32]; +#endif + /* Not actually reserved, but irrelevant to u-boot */ + u8 res[0xbf8 - 0x200]; + u32 ip_rev_1; + u32 ip_rev_2; + u32 fqd_bare; /* FQD Extended Base Addr Register */ + u32 fqd_bar; /* FQD Base Addr Register */ + u8 res1[0x8]; + u32 fqd_ar; /* FQD Attributes Register */ + u8 res2[0xc]; + u32 pfdr_bare; /* PFDR Extended Base Addr Register */ + u32 pfdr_bar; /* PFDR Base Addr Register */ + u8 res3[0x8]; + u32 pfdr_ar; /* PFDR Attributes Register */ + u8 res4[0x4c]; + u32 qcsp_bare; /* QCSP Extended Base Addr Register */ + u32 qcsp_bar; /* QCSP Base Addr Register */ + u8 res5[0x78]; + u32 ci_sched_cfg; /* Initiator Scheduling Configuration */ + u32 srcidr; /* Source ID Register */ + u32 liodnr; /* LIODN Register */ + u8 res6[4]; + u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */ + u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */ + u8 res7[0x2e8]; +#ifdef CONFIG_SYS_FSL_QMAN_V3 + struct { + u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ + u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ + u32 res; + u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/ + } qcsp[50]; +#endif +}; + +struct ccsr_bman { + /* Not actually reserved, but irrelevant to u-boot */ + u8 res[0xbf8]; + u32 ip_rev_1; + u32 ip_rev_2; + u32 fbpr_bare; /* FBPR Extended Base Addr Register */ + u32 fbpr_bar; /* FBPR Base Addr Register */ + u8 res1[0x8]; + u32 fbpr_ar; /* FBPR Attributes Register */ + u8 res2[0xf0]; + u32 srcidr; /* Source ID Register */ + u32 liodnr; /* LIODN Register */ + u8 res7[0x2f4]; +}; + +#endif /* __FSL_QBMAN_H__ */ diff --git a/roms/u-boot/include/fsl_qe.h b/roms/u-boot/include/fsl_qe.h new file mode 100644 index 000000000..cd8fca95b --- /dev/null +++ b/roms/u-boot/include/fsl_qe.h @@ -0,0 +1,304 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. + * + * Dave Liu + * based on source code of Shlomi Gridish + */ + +#ifndef __QE_H__ +#define __QE_H__ + +#include "common.h" +#ifdef CONFIG_U_QE +#include +#endif + +#define QE_NUM_OF_BRGS 16 +#define UCC_MAX_NUM 8 + +#define QE_DATAONLY_BASE 0 +#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE) + +struct udevice; + +/* QE threads SNUM +*/ +typedef enum qe_snum_state { + QE_SNUM_STATE_USED, /* used */ + QE_SNUM_STATE_FREE /* free */ +} qe_snum_state_e; + +typedef struct qe_snum { + u8 num; /* snum */ + qe_snum_state_e state; /* state */ +} qe_snum_t; + +/* QE RISC allocation +*/ +#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ +#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ +#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ +#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ +#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ + QE_RISC_ALLOCATION_RISC2) +#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ + QE_RISC_ALLOCATION_RISC2 | \ + QE_RISC_ALLOCATION_RISC3 | \ + QE_RISC_ALLOCATION_RISC4) + +/* QE CECR commands for UCC fast. +*/ +#define QE_CR_FLG 0x00010000 +#define QE_RESET 0x80000000 +#define QE_INIT_TX_RX 0x00000000 +#define QE_INIT_RX 0x00000001 +#define QE_INIT_TX 0x00000002 +#define QE_ENTER_HUNT_MODE 0x00000003 +#define QE_STOP_TX 0x00000004 +#define QE_GRACEFUL_STOP_TX 0x00000005 +#define QE_RESTART_TX 0x00000006 +#define QE_SWITCH_COMMAND 0x00000007 +#define QE_SET_GROUP_ADDRESS 0x00000008 +#define QE_INSERT_CELL 0x00000009 +#define QE_ATM_TRANSMIT 0x0000000a +#define QE_CELL_POOL_GET 0x0000000b +#define QE_CELL_POOL_PUT 0x0000000c +#define QE_IMA_HOST_CMD 0x0000000d +#define QE_ATM_MULTI_THREAD_INIT 0x00000011 +#define QE_ASSIGN_PAGE 0x00000012 +#define QE_START_FLOW_CONTROL 0x00000014 +#define QE_STOP_FLOW_CONTROL 0x00000015 +#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 +#define QE_GRACEFUL_STOP_RX 0x0000001a +#define QE_RESTART_RX 0x0000001b + +/* QE CECR Sub Block Code - sub block code of QE command. +*/ +#define QE_CR_SUBBLOCK_INVALID 0x00000000 +#define QE_CR_SUBBLOCK_USB 0x03200000 +#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 +#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 +#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 +#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 +#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 +#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 +#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 +#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 +#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 +#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 +#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 +#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 +#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 +#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 +#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 +#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 +#define QE_CR_SUBBLOCK_MCC1 0x03800000 +#define QE_CR_SUBBLOCK_MCC2 0x03a00000 +#define QE_CR_SUBBLOCK_MCC3 0x03000000 +#define QE_CR_SUBBLOCK_IDMA1 0x02800000 +#define QE_CR_SUBBLOCK_IDMA2 0x02a00000 +#define QE_CR_SUBBLOCK_IDMA3 0x02c00000 +#define QE_CR_SUBBLOCK_IDMA4 0x02e00000 +#define QE_CR_SUBBLOCK_HPAC 0x01e00000 +#define QE_CR_SUBBLOCK_SPI1 0x01400000 +#define QE_CR_SUBBLOCK_SPI2 0x01600000 +#define QE_CR_SUBBLOCK_RAND 0x01c00000 +#define QE_CR_SUBBLOCK_TIMER 0x01e00000 +#define QE_CR_SUBBLOCK_GENERAL 0x03c00000 + +/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command. +*/ +#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ +#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 +#define QE_CR_PROTOCOL_ATM_POS 0x0A +#define QE_CR_PROTOCOL_ETHERNET 0x0C +#define QE_CR_PROTOCOL_L2_SWITCH 0x0D +#define QE_CR_PROTOCOL_SHIFT 6 + +/* QE ASSIGN PAGE command +*/ +#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17 + +/* Communication Direction. +*/ +typedef enum comm_dir { + COMM_DIR_NONE = 0, + COMM_DIR_RX = 1, + COMM_DIR_TX = 2, + COMM_DIR_RX_AND_TX = 3 +} comm_dir_e; + +/* Clocks and BRG's +*/ +typedef enum qe_clock { + QE_CLK_NONE = 0, + QE_BRG1, /* Baud Rate Generator 1 */ + QE_BRG2, /* Baud Rate Generator 2 */ + QE_BRG3, /* Baud Rate Generator 3 */ + QE_BRG4, /* Baud Rate Generator 4 */ + QE_BRG5, /* Baud Rate Generator 5 */ + QE_BRG6, /* Baud Rate Generator 6 */ + QE_BRG7, /* Baud Rate Generator 7 */ + QE_BRG8, /* Baud Rate Generator 8 */ + QE_BRG9, /* Baud Rate Generator 9 */ + QE_BRG10, /* Baud Rate Generator 10 */ + QE_BRG11, /* Baud Rate Generator 11 */ + QE_BRG12, /* Baud Rate Generator 12 */ + QE_BRG13, /* Baud Rate Generator 13 */ + QE_BRG14, /* Baud Rate Generator 14 */ + QE_BRG15, /* Baud Rate Generator 15 */ + QE_BRG16, /* Baud Rate Generator 16 */ + QE_CLK1, /* Clock 1 */ + QE_CLK2, /* Clock 2 */ + QE_CLK3, /* Clock 3 */ + QE_CLK4, /* Clock 4 */ + QE_CLK5, /* Clock 5 */ + QE_CLK6, /* Clock 6 */ + QE_CLK7, /* Clock 7 */ + QE_CLK8, /* Clock 8 */ + QE_CLK9, /* Clock 9 */ + QE_CLK10, /* Clock 10 */ + QE_CLK11, /* Clock 11 */ + QE_CLK12, /* Clock 12 */ + QE_CLK13, /* Clock 13 */ + QE_CLK14, /* Clock 14 */ + QE_CLK15, /* Clock 15 */ + QE_CLK16, /* Clock 16 */ + QE_CLK17, /* Clock 17 */ + QE_CLK18, /* Clock 18 */ + QE_CLK19, /* Clock 19 */ + QE_CLK20, /* Clock 20 */ + QE_CLK21, /* Clock 21 */ + QE_CLK22, /* Clock 22 */ + QE_CLK23, /* Clock 23 */ + QE_CLK24, /* Clock 24 */ + QE_CLK_DUMMY +} qe_clock_e; + +/* QE CMXGCR register +*/ +#define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000 +#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 + +/* QE CMXUCR registers + */ +#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F + +/* QE BRG configuration register +*/ +#define QE_BRGC_ENABLE 0x00010000 +#define QE_BRGC_DIVISOR_SHIFT 1 +#define QE_BRGC_DIVISOR_MAX 0xFFF +#define QE_BRGC_DIV16 1 + +/* QE SDMA registers +*/ +#define QE_SDSR_BER1 0x02000000 +#define QE_SDSR_BER2 0x01000000 + +#define QE_SDMR_GLB_1_MSK 0x80000000 +#define QE_SDMR_ADR_SEL 0x20000000 +#define QE_SDMR_BER1_MSK 0x02000000 +#define QE_SDMR_BER2_MSK 0x01000000 +#define QE_SDMR_EB1_MSK 0x00800000 +#define QE_SDMR_ER1_MSK 0x00080000 +#define QE_SDMR_ER2_MSK 0x00040000 +#define QE_SDMR_CEN_MASK 0x0000E000 +#define QE_SDMR_SBER_1 0x00000200 +#define QE_SDMR_SBER_2 0x00000200 +#define QE_SDMR_EB1_PR_MASK 0x000000C0 +#define QE_SDMR_ER1_PR 0x00000008 + +#define QE_SDMR_CEN_SHIFT 13 +#define QE_SDMR_EB1_PR_SHIFT 6 + +#define QE_SDTM_MSNUM_SHIFT 24 + +#define QE_SDEBCR_BA_MASK 0x01FFFFFF + +/* Communication Processor */ +#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ +#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ +#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ + +/* I-RAM */ +#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ +#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ +#define QE_IRAM_READY 0x80000000 + +/* Structure that defines QE firmware binary files. + * + * See Documentation/powerpc/qe_firmware.rst in the Linux kernel tree for + * a description of these fields. + */ +struct qe_firmware { + struct qe_header { + u32 length; /* Length of the entire structure, in bytes */ + u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ + u8 version; /* Version of this layout. First ver is '1' */ + } header; + u8 id[62]; /* Null-terminated identifier string */ + u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ + u8 count; /* Number of microcode[] structures */ + struct { + u16 model; /* The SOC model */ + u8 major; /* The SOC revision major */ + u8 minor; /* The SOC revision minor */ + } __attribute__ ((packed)) soc; + u8 padding[4]; /* Reserved, for alignment */ + u64 extended_modes; /* Extended modes */ + u32 vtraps[8]; /* Virtual trap addresses */ + u8 reserved[4]; /* Reserved, for future expansion */ + struct qe_microcode { + u8 id[32]; /* Null-terminated identifier */ + u32 traps[16]; /* Trap addresses, 0 == ignore */ + u32 eccr; /* The value for the ECCR register */ + u32 iram_offset;/* Offset into I-RAM for the code */ + u32 count; /* Number of 32-bit words of the code */ + u32 code_offset;/* Offset of the actual microcode */ + u8 major; /* The microcode version major */ + u8 minor; /* The microcode version minor */ + u8 revision; /* The microcode version revision */ + u8 padding; /* Reserved, for alignment */ + u8 reserved[4]; /* Reserved, for future expansion */ + } __attribute__ ((packed)) microcode[1]; + /* All microcode binaries should be located here */ + /* CRC32 should be located here, after the microcode binaries */ +} __attribute__ ((packed)); + +struct qe_firmware_info { + char id[64]; /* Firmware name */ + u32 vtraps[8]; /* Virtual trap addresses */ + u64 extended_modes; /* Extended modes */ +}; + +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); +void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data); +uint qe_muram_alloc(uint size, uint align); +void *qe_muram_addr(uint offset); +int qe_get_snum(void); +void qe_put_snum(u8 snum); +void qe_init(uint qe_base); +void qe_reset(void); +void qe_assign_page(uint snum, uint para_ram_base); +int qe_set_brg(uint brg, uint rate); +int qe_set_mii_clk_src(int ucc_num); +int qe_upload_firmware(const struct qe_firmware *firmware); +struct qe_firmware_info *qe_get_firmware_info(void); +void ft_qe_setup(void *blob); +void qe_init(uint qe_base); +void qe_reset(void); + +#ifdef CONFIG_U_QE +void u_qe_init(void); +int u_qe_upload_firmware(const struct qe_firmware *firmware); +void u_qe_resume(void); +int u_qe_firmware_resume(const struct qe_firmware *firmware, + qe_map_t *qe_immrr); +#endif + +#if defined(CONFIG_PINCTRL) +int par_io_of_config(struct udevice *dev); +#endif +#endif /* __QE_H__ */ diff --git a/roms/u-boot/include/fsl_sec.h b/roms/u-boot/include/fsl_sec.h new file mode 100644 index 000000000..c4121696f --- /dev/null +++ b/roms/u-boot/include/fsl_sec.h @@ -0,0 +1,384 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Common internal memory map for some Freescale SoCs + * + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + */ + +#ifndef __FSL_SEC_H +#define __FSL_SEC_H + +#include +#include + +#ifdef CONFIG_SYS_FSL_SEC_LE +#define sec_in32(a) in_le32((ulong *)(ulong)a) +#define sec_out32(a, v) out_le32((ulong *)(ulong)a, v) +#define sec_in16(a) in_le16(a) +#define sec_clrbits32 clrbits_le32 +#define sec_setbits32 setbits_le32 +#elif defined(CONFIG_SYS_FSL_SEC_BE) +#define sec_in32(a) in_be32(a) +#define sec_out32(a, v) out_be32(a, v) +#define sec_in16(a) in_be16(a) +#define sec_clrbits32 clrbits_be32 +#define sec_setbits32 setbits_be32 +#elif defined(CONFIG_SYS_FSL_HAS_SEC) +#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined +#endif + +#define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */ + +/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ +#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 +/* RNG4 TRNG test registers */ +struct rng4tst { +#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ +#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in + both entropy shifter and + statistical checker */ +#define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both + entropy shifter and + statistical checker */ +#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in + entropy shifter, raw data + in statistical checker */ +#define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */ + u32 rtmctl; /* misc. control register */ + u32 rtscmisc; /* statistical check misc. register */ + u32 rtpkrrng; /* poker range register */ +#define RTSDCTL_ENT_DLY_MIN 3200 +#define RTSDCTL_ENT_DLY_MAX 12800 + union { + u32 rtpkrmax; /* PRGM=1: poker max. limit register */ + u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ + }; +#define RTSDCTL_ENT_DLY_SHIFT 16 +#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) + u32 rtsdctl; /* seed control register */ + union { + u32 rtsblim; /* PRGM=1: sparse bit limit register */ + u32 rttotsam; /* PRGM=0: total samples register */ + }; + u32 rtfreqmin; /* frequency count min. limit register */ +#define RTFRQMAX_DISABLE (1 << 20) + union { + u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */ + u32 rtfreqcnt; /* PRGM=0: freq. count register */ + }; + u32 rsvd1[40]; +#define RDSTA_IF(idx) (0x00000001 << (idx)) +#define RDSTA_PR(idx) (0x00000010 << (idx)) +#define RDSTA_MASK (RDSTA_PR(1) | RDSTA_PR(0) | RDSTA_IF(1) | RDSTA_IF(0)) +#define RDSTA_SKVN 0x40000000 + u32 rdsta; /*RNG DRNG Status Register*/ + u32 rsvd2[15]; +}; + +/* Version registers (Era 10+) */ +struct version_regs { + u32 crca; /* CRCA_VERSION */ + u32 afha; /* AFHA_VERSION */ + u32 kfha; /* KFHA_VERSION */ + u32 pkha; /* PKHA_VERSION */ + u32 aesa; /* AESA_VERSION */ + u32 mdha; /* MDHA_VERSION */ + u32 desa; /* DESA_VERSION */ + u32 snw8a; /* SNW8A_VERSION */ + u32 snw9a; /* SNW9A_VERSION */ + u32 zuce; /* ZUCE_VERSION */ + u32 zuca; /* ZUCA_VERSION */ + u32 ccha; /* CCHA_VERSION */ + u32 ptha; /* PTHA_VERSION */ + u32 rng; /* RNG_VERSION */ + u32 trng; /* TRNG_VERSION */ + u32 aaha; /* AAHA_VERSION */ + u32 rsvd[10]; + u32 sr; /* SR_VERSION */ + u32 dma; /* DMA_VERSION */ + u32 ai; /* AI_VERSION */ + u32 qi; /* QI_VERSION */ + u32 jr; /* JR_VERSION */ + u32 deco; /* DECO_VERSION */ +}; + +#define CHA_VER_NUM_MASK 0x000000ff +#define CHA_VER_MISC_SHIFT 8 +#define CHA_VER_MISC_MASK 0x0000ff00 +#define CHA_VER_REV_SHIFT 16 +#define CHA_VER_REV_MASK 0x00ff0000 +#define CHA_VER_VID_SHIFT 24 +#define CHA_VER_VID_MASK 0xff000000 + +typedef struct ccsr_sec { + u32 res0; + u32 mcfgr; /* Master CFG Register */ + u8 res1[0x4]; + u32 scfgr; + struct { + u32 ms; /* Job Ring LIODN Register, MS */ + u32 ls; /* Job Ring LIODN Register, LS */ + } jrliodnr[4]; + u8 res2[0x2c]; + u32 jrstartr; /* Job Ring Start Register */ + struct { + u32 ms; /* RTIC LIODN Register, MS */ + u32 ls; /* RTIC LIODN Register, LS */ + } rticliodnr[4]; + u8 res3[0x1c]; + u32 decorr; /* DECO Request Register */ + struct { + u32 ms; /* DECO LIODN Register, MS */ + u32 ls; /* DECO LIODN Register, LS */ + } decoliodnr[16]; + u32 dar; /* DECO Avail Register */ + u32 drr; /* DECO Reset Register */ + u8 res5[0x4d8]; + struct rng4tst rng; /* RNG Registers */ + u8 res6[0x780]; + struct version_regs vreg; /* version registers since era 10 */ + u8 res7[0xa0]; + u32 crnr_ms; /* CHA Revision Number Register, MS */ + u32 crnr_ls; /* CHA Revision Number Register, LS */ + u32 ctpr_ms; /* Compile Time Parameters Register, MS */ + u32 ctpr_ls; /* Compile Time Parameters Register, LS */ + u8 res8[0x10]; + u32 far_ms; /* Fault Address Register, MS */ + u32 far_ls; /* Fault Address Register, LS */ + u32 falr; /* Fault Address LIODN Register */ + u32 fadr; /* Fault Address Detail Register */ + u8 res9[0x4]; + u32 csta; /* CAAM Status Register */ + u32 smpart; /* Secure Memory Partition Parameters */ + u32 smvid; /* Secure Memory Version ID */ + u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ + u32 ccbvid; /* CHA Cluster Block Version ID Register */ + u32 chavid_ms; /* CHA Version ID Register, MS */ + u32 chavid_ls; /* CHA Version ID Register, LS */ + u32 chanum_ms; /* CHA Number Register, MS */ + u32 chanum_ls; /* CHA Number Register, LS */ + u32 secvid_ms; /* SEC Version ID Register, MS */ + u32 secvid_ls; /* SEC Version ID Register, LS */ +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) + u8 res10[0x6f020]; +#else + u8 res10[0x6020]; +#endif + u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ + u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) + u8 res11[0x8ffd8]; +#else + u8 res11[0x8fd8]; +#endif +} ccsr_sec_t; + +#define SEC_CTPR_MS_AXI_LIODN 0x08000000 +#define SEC_CTPR_MS_QI 0x02000000 +#define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001 +#define SEC_CTPR_MS_VIRT_EN_POR 0x00000002 +#define SEC_RVID_MA 0x0f000000 +#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 +#define SEC_CHANUM_MS_JRNUM_SHIFT 28 +#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 +#define SEC_CHANUM_MS_DECONUM_SHIFT 24 +#define SEC_SECVID_MS_IPID_MASK 0xffff0000 +#define SEC_SECVID_MS_IPID_SHIFT 16 +#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00 +#define SEC_SECVID_MS_MAJ_REV_SHIFT 8 +#define SEC_CCBVID_ERA_MASK 0xff000000 +#define SEC_CCBVID_ERA_SHIFT 24 +#define SEC_SCFGR_RDBENABLE 0x00000400 +#define SEC_SCFGR_VIRT_EN 0x00008000 +#define SEC_CHAVID_LS_RNG_SHIFT 16 +#define SEC_CHAVID_RNG_LS_MASK 0x000f0000 + +#define CONFIG_JRSTARTR_JR0 0x00000001 + +struct jr_regs { +#if defined(CONFIG_SYS_FSL_SEC_LE) && \ + !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) + u32 irba_l; + u32 irba_h; +#else + u32 irba_h; + u32 irba_l; +#endif + u32 rsvd1; + u32 irs; + u32 rsvd2; + u32 irsa; + u32 rsvd3; + u32 irja; +#if defined(CONFIG_SYS_FSL_SEC_LE) && \ + !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) + u32 orba_l; + u32 orba_h; +#else + u32 orba_h; + u32 orba_l; +#endif + u32 rsvd4; + u32 ors; + u32 rsvd5; + u32 orjr; + u32 rsvd6; + u32 orsf; + u32 rsvd7; + u32 jrsta; + u32 rsvd8; + u32 jrint; + u32 jrcfg0; + u32 jrcfg1; + u32 rsvd9; + u32 irri; + u32 rsvd10; + u32 orwi; + u32 rsvd11; + u32 jrcr; +}; + +/* + * Scatter Gather Entry - Specifies the the Scatter Gather Format + * related information + */ +struct sg_entry { +#if defined(CONFIG_SYS_FSL_SEC_LE) && \ + !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) + uint32_t addr_lo; /* Memory Address - lo */ + uint32_t addr_hi; /* Memory Address of start of buffer - hi */ +#else + uint32_t addr_hi; /* Memory Address of start of buffer - hi */ + uint32_t addr_lo; /* Memory Address - lo */ +#endif + + uint32_t len_flag; /* Length of the data in the frame */ +#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF +#define SG_ENTRY_EXTENSION_BIT 0x80000000 +#define SG_ENTRY_FINAL_BIT 0x40000000 + uint32_t bpid_offset; +#define SG_ENTRY_BPID_MASK 0x00FF0000 +#define SG_ENTRY_BPID_SHIFT 16 +#define SG_ENTRY_OFFSET_MASK 0x00001FFF +#define SG_ENTRY_OFFSET_SHIFT 0 +}; + +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) +/* Job Ring Base Address */ +#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1)) +/* Secure Memory Offset varies accross versions */ +#define SM_V1_OFFSET 0x0f4 +#define SM_V2_OFFSET 0xa00 +/*Secure Memory Versioning */ +#define SMVID_V2 0x20105 +#define SM_VERSION(x) ({typeof(x) _x = x; \ + _x < SMVID_V2 ? 1 : (_x < 0x20300 ? 2 : 3); }) +#define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET) +/* CAAM Job Ring 0 Registers */ +/* Secure Memory Partition Owner register */ +#define SMCSJR_PO (3 << 6) +/* JR Allocation Error */ +#define SMCSJR_AERR (3 << 12) +/* Secure memory partition 0 page 0 owner register */ +#define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC) +/* Secure memory command register */ +#define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v)) +/* Secure memory command status register */ +#define CAAM_SMCSJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v)) +/* Secure memory access permissions register */ +#define CAAM_SMAPJR(v, jr, y) \ + (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16) +/* Secure memory access group 2 register */ +#define CAAM_SMAG2JR(v, jr, y) \ + (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16) +/* Secure memory access group 1 register */ +#define CAAM_SMAG1JR(v, jr, y) \ + (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16) + +/* Commands and macros for secure memory */ +#define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4) +#define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC) +#define SM_PERM(v) (v == 1 ? 0x10 : 0x4) +#define SM_GROUP2(v) ({typeof(v) _v = v; \ + _v == 1 ? 0x14 : (_v == 2 ? 0x8 : 0xC); }) +#define SM_GROUP1(v) ({typeof(v) _v = v; \ + _v == 1 ? 0x18 : (_v == 2 ? 0xC : 0x8); }) +#define CMD_PAGE_ALLOC 0x1 +#define CMD_PAGE_DEALLOC 0x2 +#define CMD_PART_DEALLOC 0x3 +#define CMD_INQUIRY 0x5 +#define CMD_COMPLETE (3 << 14) +#define PAGE_AVAILABLE 0 +#define PAGE_OWNED (3 << 6) +#define PAGE(x) (x << 16) +#define PARTITION(x) (x << 8) +#define PARTITION_OWNER(x) (0x3 << (x*2)) + +/* Address of secure 4kbyte pages */ +#define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR +#define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000) +#define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000) +#define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000) + +#ifdef CONFIG_IMX8M +#define JR_MID (1) /* Matches ATF configuration */ +#define KS_G1 (0x10000 << JR_MID) /* CAAM only */ +#define PERM (0xB080) /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */ +#else +#define JR_MID (2) /* Matches ROM configuration */ +#define KS_G1 BIT(JR_MID) /* CAAM only */ +#define PERM (0xB008) /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */ +#endif /* CONFIG_IMX8M */ + +/* HAB WRAPPED KEY header */ +#define WRP_HDR_SIZE 0x08 +#define HDR_TAG 0x81 +#define HDR_PAR 0x41 +/* HAB WRAPPED KEY Data */ +#define HAB_MOD 0x66 +#define HAB_ALG 0x55 +#define HAB_FLG 0x00 + +/* Partition and Page IDs */ +#define PARTITION_1 1 +#define PAGE_1 1 + +#define ERROR_IN_PAGE_ALLOC 1 +#define ECONSTRJDESC -1 + +#endif + +#define FSL_CAAM_MP_PUBK_BYTES 64 +#define FSL_CAAM_MP_PRVK_BYTES 32 +#define FSL_CAAM_MP_MES_DGST_BYTES 32 + +#define FSL_CAAM_ORSR_JRa_OFFSET 0x102c +#define FSL_CAAM_MAX_JR_SIZE 4 + +/* blob_dek: + * Encapsulates the src in a secure blob and stores it dst + * @src: reference to the plaintext + * @dst: reference to the output adrress + * @len: size in bytes of src + * @return: 0 on success, error otherwise + */ +int blob_dek(const u8 *src, u8 *dst, u8 len); + +int gen_mppubk(u8 *dst); + +int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d); + +#if defined(CONFIG_ARCH_C29X) +int sec_init_idx(uint8_t); +#endif +int sec_init(void); + +u8 caam_get_era(void); +#endif + +#endif /* __FSL_SEC_H */ diff --git a/roms/u-boot/include/fsl_sec_mon.h b/roms/u-boot/include/fsl_sec_mon.h new file mode 100644 index 000000000..fb838db0b --- /dev/null +++ b/roms/u-boot/include/fsl_sec_mon.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Common internal memory map for some Freescale SoCs + * + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __FSL_SEC_MON_H +#define __FSL_SEC_MON_H + +#include +#include + +#ifdef CONFIG_SYS_FSL_SEC_MON_LE +#define sec_mon_in32(a) in_le32(a) +#define sec_mon_out32(a, v) out_le32(a, v) +#define sec_mon_in16(a) in_le16(a) +#define sec_mon_clrbits32 clrbits_le32 +#define sec_mon_setbits32 setbits_le32 +#elif defined(CONFIG_SYS_FSL_SEC_MON_BE) +#define sec_mon_in32(a) in_be32(a) +#define sec_mon_out32(a, v) out_be32(a, v) +#define sec_mon_in16(a) in_be16(a) +#define sec_mon_clrbits32 clrbits_be32 +#define sec_mon_setbits32 setbits_be32 +#else +#error Neither CONFIG_SYS_FSL_SEC_MON_LE nor CONFIG_SYS_FSL_SEC_MON_BE defined +#endif + +struct ccsr_sec_mon_regs { + u8 reserved0[0x04]; + u32 hp_com; /* 0x04 SEC_MON_HP Command Register */ + u8 reserved2[0x0c]; + u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */ +}; + +#define HPCOMR_SW_SV 0x100 /* Security Violation bit */ +#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */ +#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */ +#define HPCOMR_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */ +#define HPCOMR_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */ +#define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */ +#define HPSR_SSM_ST_NON_SECURE 0xb00 /* SEC_MON is in non secure state */ +#define HPSR_SSM_ST_TRUST 0xd00 /* SEC_MON is in trusted state */ +#define HPSR_SSM_ST_SOFT_FAIL 0x300 /* SEC_MON is in soft fail state */ +#define HPSR_SSM_ST_SECURE 0xf00 /* SEC_MON is in secure state */ +#define HPSR_SSM_ST_MASK 0xf00 /* Mask for SSM_ST field */ + +/* + * SEC_MON read. This specifies the possible reads + * from the SEC_MON + */ +enum { + SEC_MON_SSM_ST, + SEC_MON_SW_FSV, + SEC_MON_SW_SV, +}; + +/* Transition SEC_MON state */ +int set_sec_mon_state(u32 state); + +#endif /* __FSL_SEC_MON_H */ diff --git a/roms/u-boot/include/fsl_secboot_err.h b/roms/u-boot/include/fsl_secboot_err.h new file mode 100644 index 000000000..bc9dab230 --- /dev/null +++ b/roms/u-boot/include/fsl_secboot_err.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef _FSL_SECBOOT_ERR_H +#define _FSL_SECBOOT_ERR_H + +#define ERROR_ESBC_PAMU_INIT 0x100000 +#define ERROR_ESBC_SEC_RESET 0x200000 +#define ERROR_ESBC_SEC_INIT 0x400000 +#define ERROR_ESBC_SEC_DEQ 0x800000 +#define ERROR_ESBC_SEC_DEQ_TO 0x1000000 +#define ERROR_ESBC_SEC_ENQ 0x2000000 +#define ERROR_ESBC_SEC_JOBQ_STATUS 0x4000000 +#define ERROR_ESBC_CLIENT_CPUID_NO_MATCH 0x1 +#define ERROR_ESBC_CLIENT_HDR_LOC 0x2 +#define ERROR_ESBC_CLIENT_HEADER_BARKER 0x4 +#define ERROR_ESBC_CLIENT_HEADER_KEY_LEN 0x8 +#define ERROR_ESBC_CLIENT_HEADER_SIG_LEN 0x10 +#define ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED 0x11 +#define ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY 0x12 +#define ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM 0x13 +#define ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN 0x14 +#define ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED 0x15 +#define ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY 0x16 +#define ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM 0x17 +#define ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN 0x18 +#define ERROR_IE_TABLE_NOT_FOUND 0x19 +#define ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN 0x20 +#define ERROR_KEY_TABLE_NOT_FOUND 0x21 +#define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1 0x40 +#define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2 0x80 +#define ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD 0x100 +#define ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP 0x200 +#define ERROR_ESBC_CLIENT_HASH_COMPARE_KEY 0x400 +#define ERROR_ESBC_CLIENT_HASH_COMPARE_EM 0x800 +#define ERROR_ESBC_CLIENT_SSM_TRUSTSTS 0x1000 +#define ERROR_ESBC_CLIENT_BAD_ADDRESS 0x2000 +#define ERROR_ESBC_CLIENT_MISC 0x4000 +#define ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD 0x8000 +#define ERROR_ESBC_CLIENT_HEADER_SG 0x10000 +#define ERROR_ESBC_CLIENT_HEADER_IMG_SIZE 0x20000 +#define ERROR_ESBC_WRONG_CMD 0x40000 +#define ERROR_ESBC_MISSING_BOOTM 0x80000 +#define ERROR_ESBC_CLIENT_MAX 0x0 + +struct fsl_secboot_errcode { + int errcode; + const char *name; +}; + +static const struct fsl_secboot_errcode fsl_secboot_errcodes[] = { + { ERROR_ESBC_PAMU_INIT, + "Error in initializing PAMU"}, + { ERROR_ESBC_SEC_RESET, + "Error in resetting Job ring of SEC"}, + { ERROR_ESBC_SEC_INIT, + "Error in initializing SEC"}, + { ERROR_ESBC_SEC_ENQ, + "Error in enqueue operation by SEC"}, + { ERROR_ESBC_SEC_DEQ_TO, + "Dequeue operation by SEC is timed out"}, + { ERROR_ESBC_SEC_DEQ, + "Error in dequeue operation by SEC"}, + { ERROR_ESBC_SEC_JOBQ_STATUS, + "Error in status of the job submitted to SEC"}, + { ERROR_ESBC_CLIENT_CPUID_NO_MATCH, + "Current core is not boot core i.e core0" }, + { ERROR_ESBC_CLIENT_HDR_LOC, + "Header address not in allowed memory range" }, + { ERROR_ESBC_CLIENT_HEADER_BARKER, + "Wrong barker code in header" }, + { ERROR_ESBC_CLIENT_HEADER_KEY_LEN, + "Wrong public key length in header" }, + { ERROR_ESBC_CLIENT_HEADER_SIG_LEN, + "Wrong signature length in header" }, + { ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN, + "Public key length not twice of signature length" }, + { ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1, + "Public key Modulus most significant bit not set" }, + { ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2, + "Public key Modulus in header not odd" }, + { ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD, + "Signature not less than modulus" }, + { ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP, + "Entry point not in allowed space or one of the SG entries" }, + { ERROR_ESBC_CLIENT_HASH_COMPARE_KEY, + "Public key hash comparison failed" }, + { ERROR_ESBC_CLIENT_HASH_COMPARE_EM, + "RSA verification failed" }, + { ERROR_ESBC_CLIENT_SSM_TRUSTSTS, + "SNVS not in TRUSTED state" }, + { ERROR_ESBC_CLIENT_BAD_ADDRESS, + "Bad address error" }, + { ERROR_ESBC_CLIENT_MISC, + "Miscallaneous error" }, + { ERROR_ESBC_CLIENT_HEADER_SG, + "No SG support" }, + { ERROR_ESBC_CLIENT_HEADER_IMG_SIZE, + "Invalid Image size" }, + { ERROR_ESBC_WRONG_CMD, + "Unknown cmd/Wrong arguments. Core in infinite loop"}, + { ERROR_ESBC_MISSING_BOOTM, + "Bootm command missing from bootscript" }, + { ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED, + "Selected key is revoked" }, + { ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY, + "Wrong key entry" }, + { ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM, + "Wrong key is selected" }, + { ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN, + "Wrong srk public key len in header" }, + { ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED, + "Selected IE key is revoked" }, + { ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY, + "Wrong key entry in IE Table" }, + { ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM, + "Wrong IE key is selected" }, + { ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN, + "Wrong IE public key len in header" }, + { ERROR_IE_TABLE_NOT_FOUND, + "Information about IE Table missing" }, + { ERROR_KEY_TABLE_NOT_FOUND, + "No Key/ Key Table Found in header"}, + { ERROR_ESBC_CLIENT_MAX, "NULL" } +}; + +void fsl_secboot_handle_error(int error); +#endif diff --git a/roms/u-boot/include/fsl_sfp.h b/roms/u-boot/include/fsl_sfp.h new file mode 100644 index 000000000..613814d90 --- /dev/null +++ b/roms/u-boot/include/fsl_sfp.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef _FSL_SFP_SNVS_ +#define _FSL_SFP_SNVS_ + +#include +#include +#include + +#ifdef CONFIG_SYS_FSL_SRK_LE +#define srk_in32(a) in_le32(a) +#else +#define srk_in32(a) in_be32(a) +#endif + +#ifdef CONFIG_SYS_FSL_SFP_LE +#define sfp_in32(a) in_le32(a) +#define sfp_out32(a, v) out_le32(a, v) +#define sfp_in16(a) in_le16(a) +#elif defined(CONFIG_SYS_FSL_SFP_BE) +#define sfp_in32(a) in_be32(a) +#define sfp_out32(a, v) out_be32(a, v) +#define sfp_in16(a) in_be16(a) +#else +#error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined +#endif + +/* Number of SRKH registers */ +#define NUM_SRKH_REGS 8 + +#if defined(CONFIG_SYS_FSL_SFP_VER_3_2) || \ + defined(CONFIG_SYS_FSL_SFP_VER_3_4) +struct ccsr_sfp_regs { + u32 ospr; /* 0x200 */ + u32 ospr1; /* 0x204 */ + u32 reserved1[4]; + u32 fswpr; /* 0x218 FSL Section Write Protect */ + u32 fsl_uid; /* 0x21c FSL UID 0 */ + u32 fsl_uid_1; /* 0x220 FSL UID 0 */ + u32 reserved2[12]; + u32 srk_hash[8]; /* 0x254 Super Root Key Hash */ + u32 oem_uid; /* 0x274 OEM UID 0*/ + u32 oem_uid_1; /* 0x278 OEM UID 1*/ + u32 oem_uid_2; /* 0x27c OEM UID 2*/ + u32 oem_uid_3; /* 0x280 OEM UID 3*/ + u32 oem_uid_4; /* 0x284 OEM UID 4*/ + u32 reserved3[8]; +}; +#elif defined(CONFIG_SYS_FSL_SFP_VER_3_0) +struct ccsr_sfp_regs { + u32 ospr; /* 0x200 */ + u32 reserved0[14]; + u32 srk_hash[NUM_SRKH_REGS]; /* 0x23c Super Root Key Hash */ + u32 oem_uid; /* 0x9c OEM Unique ID */ + u8 reserved2[0x04]; + u32 ovpr; /* 0xA4 Intent To Secure */ + u8 reserved4[0x08]; + u32 fsl_uid; /* 0xB0 FSL Unique ID */ + u8 reserved5[0x04]; + u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */ + u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */ + +}; +#else +struct ccsr_sfp_regs { + u8 reserved0[0x40]; + u32 ospr; /* 0x40 OEM Security Policy Register */ + u8 reserved2[0x38]; + u32 srk_hash[8]; /* 0x7c Super Root Key Hash */ + u32 oem_uid; /* 0x9c OEM Unique ID */ + u8 reserved4[0x4]; + u32 ovpr; /* 0xA4 OEM Validation Policy Register */ + u8 reserved8[0x8]; + u32 fsl_uid; /* 0xB0 FSL Unique ID */ +}; +#endif + +#define ITS_MASK 0x00000004 +#define ITS_BIT 2 + +#if defined(CONFIG_SYS_FSL_SFP_VER_3_4) +#define OSPR_KEY_REVOC_SHIFT 9 +#define OSPR_KEY_REVOC_MASK 0x0000fe00 +#else +#define OSPR_KEY_REVOC_SHIFT 13 +#define OSPR_KEY_REVOC_MASK 0x0000e000 +#endif /* CONFIG_SYS_FSL_SFP_VER_3_4 */ + +#endif diff --git a/roms/u-boot/include/fsl_tgec.h b/roms/u-boot/include/fsl_tgec.h new file mode 100644 index 000000000..59cd856ba --- /dev/null +++ b/roms/u-boot/include/fsl_tgec.h @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Dave Liu + */ + +#ifndef __TGEC_H__ +#define __TGEC_H__ + +#include + +struct tgec { + /* 10GEC general control and status registers */ + u32 tgec_id; /* Controller ID register */ + u32 res0; + u32 command_config; /* Control and configuration register */ + u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */ + u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */ + u32 maxfrm; /* Maximum frame length register */ + u32 pause_quant; /* Pause quanta register */ + u32 res1[4]; + u32 hashtable_ctrl; /* Hash table control register */ + u32 res2[4]; + u32 status; /* MAC status register */ + u32 tx_ipg_length; /* Transmitter inter-packet-gap register */ + u32 mac_addr_2; /* Lower 32 bits of the 2nd 48-bit MAC addr */ + u32 mac_addr_3; /* Upper 16 bits of the 2nd 48-bit MAC addr */ + u32 res3[4]; + u32 imask; /* Interrupt mask register */ + u32 ievent; /* Interrupt event register */ + u32 res4[6]; + /* 10GEC statistics counter registers */ + u32 tx_frame_u; /* Tx frame counter upper */ + u32 tx_frame_l; /* Tx frame counter lower */ + u32 rx_frame_u; /* Rx frame counter upper */ + u32 rx_frame_l; /* Rx frame counter lower */ + u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */ + u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */ + u32 rx_align_err_u; /* Rx alignment error upper */ + u32 rx_align_err_l; /* Rx alignment error lower */ + u32 tx_pause_frame_u; /* Tx valid pause frame upper */ + u32 tx_pause_frame_l; /* Tx valid pause frame lower */ + u32 rx_pause_frame_u; /* Rx valid pause frame upper */ + u32 rx_pause_frame_l; /* Rx valid pause frame upper */ + u32 rx_long_err_u; /* Rx too long frame error upper */ + u32 rx_long_err_l; /* Rx too long frame error lower */ + u32 rx_frame_err_u; /* Rx frame length error upper */ + u32 rx_frame_err_l; /* Rx frame length error lower */ + u32 tx_vlan_u; /* Tx VLAN frame upper */ + u32 tx_vlan_l; /* Tx VLAN frame lower */ + u32 rx_vlan_u; /* Rx VLAN frame upper */ + u32 rx_vlan_l; /* Rx VLAN frame lower */ + u32 tx_oct_u; /* Tx octets upper */ + u32 tx_oct_l; /* Tx octets lower */ + u32 rx_oct_u; /* Rx octets upper */ + u32 rx_oct_l; /* Rx octets lower */ + u32 rx_uni_u; /* Rx unicast frame upper */ + u32 rx_uni_l; /* Rx unicast frame lower */ + u32 rx_multi_u; /* Rx multicast frame upper */ + u32 rx_multi_l; /* Rx multicast frame lower */ + u32 rx_brd_u; /* Rx broadcast frame upper */ + u32 rx_brd_l; /* Rx broadcast frame lower */ + u32 tx_frame_err_u; /* Tx frame error upper */ + u32 tx_frame_err_l; /* Tx frame error lower */ + u32 tx_uni_u; /* Tx unicast frame upper */ + u32 tx_uni_l; /* Tx unicast frame lower */ + u32 tx_multi_u; /* Tx multicast frame upper */ + u32 tx_multi_l; /* Tx multicast frame lower */ + u32 tx_brd_u; /* Tx broadcast frame upper */ + u32 tx_brd_l; /* Tx broadcast frame lower */ + u32 rx_drop_u; /* Rx dropped packets upper */ + u32 rx_drop_l; /* Rx dropped packets lower */ + u32 rx_eoct_u; /* Rx ethernet octets upper */ + u32 rx_eoct_l; /* Rx ethernet octets lower */ + u32 rx_pkt_u; /* Rx packets upper */ + u32 rx_pkt_l; /* Rx packets lower */ + u32 tx_undsz_u; /* Undersized packet upper */ + u32 tx_undsz_l; /* Undersized packet lower */ + u32 rx_64_u; /* Rx 64 oct packet upper */ + u32 rx_64_l; /* Rx 64 oct packet lower */ + u32 rx_127_u; /* Rx 65 to 127 oct packet upper */ + u32 rx_127_l; /* Rx 65 to 127 oct packet lower */ + u32 rx_255_u; /* Rx 128 to 255 oct packet upper */ + u32 rx_255_l; /* Rx 128 to 255 oct packet lower */ + u32 rx_511_u; /* Rx 256 to 511 oct packet upper */ + u32 rx_511_l; /* Rx 256 to 511 oct packet lower */ + u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */ + u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */ + u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */ + u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */ + u32 rx_1519_u; /* Rx 1519 to max oct packet upper */ + u32 rx_1519_l; /* Rx 1519 to max oct packet lower */ + u32 tx_oversz_u; /* oversized packet upper */ + u32 tx_oversz_l; /* oversized packet lower */ + u32 tx_jabber_u; /* Jabber packet upper */ + u32 tx_jabber_l; /* Jabber packet lower */ + u32 tx_frag_u; /* Fragment packet upper */ + u32 tx_frag_l; /* Fragment packet lower */ + u32 rx_err_u; /* Rx frame error upper */ + u32 rx_err_l; /* Rx frame error lower */ + u32 res5[0x39a]; +}; + +/* EC10G_ID - 10-gigabit ethernet MAC controller ID */ +#define EC10G_ID_VER_MASK 0x0000ff00 +#define EC10G_ID_VER_SHIFT 8 +#define EC10G_ID_REV_MASK 0x000000ff + +/* COMMAND_CONFIG - command and configuration register */ +#define TGEC_CMD_CFG_EN_TIMESTAMP 0x00100000 /* enable IEEE1588 */ +#define TGEC_CMD_CFG_TX_ADDR_INS_SEL 0x00080000 /* Tx mac addr w/ second */ +#define TGEC_CMD_CFG_NO_LEN_CHK 0x00020000 /* payload len chk disable */ +#define TGEC_CMD_CFG_SEND_IDLE 0x00010000 /* send XGMII idle seqs */ +#define TGEC_CMD_CFG_RX_ER_DISC 0x00004000 /* Rx err frm discard enb */ +#define TGEC_CMD_CFG_CMD_FRM_EN 0x00002000 /* CMD frame RX enable */ +#define TGEC_CMD_CFG_STAT_CLR 0x00001000 /* clear stats */ +#define TGEC_CMD_CFG_TX_ADDR_INS 0x00000200 /* overwrite src MAC addr */ +#define TGEC_CMD_CFG_PAUSE_IGNORE 0x00000100 /* ignore pause frames */ +#define TGEC_CMD_CFG_PAUSE_FWD 0x00000080 /* fwd pause frames */ +#define TGEC_CMD_CFG_CRC_FWD 0x00000040 /* fwd Rx CRC frames */ +#define TGEC_CMD_CFG_PAD_EN 0x00000020 /* MAC remove Rx padding */ +#define TGEC_CMD_CFG_PROM_EN 0x00000010 /* promiscuous mode enable */ +#define TGEC_CMD_CFG_WAN_MODE 0x00000008 /* WAN mode enable */ +#define TGEC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */ +#define TGEC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */ +#define TGEC_CMD_CFG_RXTX_EN (TGEC_CMD_CFG_RX_EN | TGEC_CMD_CFG_TX_EN) + +/* HASHTABLE_CTRL - Hashtable control register */ +#define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */ +#define HASHTABLE_CTRL_ADDR_MASK 0x000001ff + +/* TX_IPG_LENGTH - Transmit inter-packet gap length register */ +#define TX_IPG_LENGTH_IPG_LEN_MASK 0x000003ff + +/* IMASK - interrupt mask register */ +#define IMASK_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event mask */ +#define IMASK_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion mask */ +#define IMASK_REM_FAULT 0x00004000 /* remote fault mask */ +#define IMASK_LOC_FAULT 0x00002000 /* local fault mask */ +#define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */ +#define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */ +#define IMASK_TX_ER 0x00000200 /* Tx frame error mask */ +#define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */ +#define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */ +#define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */ +#define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */ +#define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */ +#define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */ +#define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */ +#define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */ +#define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */ + +#define IMASK_MASK_ALL 0x00000000 + +/* IEVENT - interrupt event register */ +#define IEVENT_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event */ +#define IEVENT_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion */ +#define IEVENT_REM_FAULT 0x00004000 /* remote fault */ +#define IEVENT_LOC_FAULT 0x00002000 /* local fault */ +#define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */ +#define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */ +#define IEVENT_TX_ER 0x00000200 /* Tx frame error */ +#define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */ +#define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */ +#define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */ +#define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */ +#define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */ +#define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */ +#define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */ +#define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */ +#define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */ + +#define IEVENT_CLEAR_ALL 0xffffffff + +struct tgec_mdio_controller { + u32 res0[0xc]; + u32 mdio_stat; /* MDIO configuration and status */ + u32 mdio_ctl; /* MDIO control */ + u32 mdio_data; /* MDIO data */ + u32 mdio_addr; /* MDIO address */ +}; + +#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8) +#define MDIO_STAT_BSY (1 << 0) +#define MDIO_STAT_RD_ER (1 << 1) +#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f) +#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5) +#define MDIO_CTL_PRE_DIS (1 << 10) +#define MDIO_CTL_SCAN_EN (1 << 11) +#define MDIO_CTL_POST_INC (1 << 14) +#define MDIO_CTL_READ (1 << 15) + +#define MDIO_DATA(x) (x & 0xffff) +#define MDIO_DATA_BSY (1 << 31) + +struct fsl_enet_mac; + +void init_tgec(struct fsl_enet_mac *mac, void *base, void *phyregs, + int max_rx_len); + +#endif diff --git a/roms/u-boot/include/fsl_usb.h b/roms/u-boot/include/fsl_usb.h new file mode 100644 index 000000000..c0f076b06 --- /dev/null +++ b/roms/u-boot/include/fsl_usb.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Freescale USB Controller + * + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#ifndef _ASM_FSL_USB_H_ +#define _ASM_FSL_USB_H_ + +#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE +struct ccsr_usb_port_ctrl { + u32 ctrl; + u32 drvvbuscfg; + u32 pwrfltcfg; + u32 sts; + u8 res_14[0xc]; + u32 bistcfg; + u32 biststs; + u32 abistcfg; + u32 abiststs; + u8 res_30[0x10]; + u32 xcvrprg; + u32 anaprg; + u32 anadrv; + u32 anasts; +}; + +struct ccsr_usb_phy { + u32 id; + struct ccsr_usb_port_ctrl port1; + u8 res_50[0xc]; + u32 tvr; + u32 pllprg[4]; + u8 res_70[0x4]; + u32 anaccfg; + u32 dbg; + u8 res_7c[0x4]; + struct ccsr_usb_port_ctrl port2; + u8 res_dc[0x334]; +}; + +#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0) +#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1) +#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1) +#define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0) +#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0) +#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1) +#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13) +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK +#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4) +#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16) +#define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20) +#endif +#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4) +#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16) +#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21) +#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0) +#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7) +#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4) + +#define INC_DCNT_THRESHOLD_25MV (0 << 4) +#define INC_DCNT_THRESHOLD_50MV (1 << 4) +#define DEC_DCNT_THRESHOLD_25MV (2 << 4) +#define DEC_DCNT_THRESHOLD_50MV (3 << 4) +#else +struct ccsr_usb_phy { + u32 config1; + u32 config2; + u32 config3; + u32 config4; + u32 config5; + u32 status1; + u32 usb_enable_override; + u8 res[0xe4]; +}; +#define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22) +#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20) +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3 +#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07 +#endif + +/* USB Erratum Checking code */ +#if defined(CONFIG_PPC) || defined(CONFIG_ARM) +bool has_dual_phy(void); +bool has_erratum_a005275(void); +bool has_erratum_a006261(void); +bool has_erratum_a007075(void); +bool has_erratum_a007798(void); +bool has_erratum_a007792(void); +bool has_erratum_a005697(void); +bool has_erratum_a004477(void); +bool has_erratum_a008751(void); +bool has_erratum_a010151(void); +#endif +#endif /*_ASM_FSL_USB_H_ */ diff --git a/roms/u-boot/include/fsl_validate.h b/roms/u-boot/include/fsl_validate.h new file mode 100644 index 000000000..252d499e7 --- /dev/null +++ b/roms/u-boot/include/fsl_validate.h @@ -0,0 +1,283 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef _FSL_VALIDATE_H_ +#define _FSL_VALIDATE_H_ + +#include +#include +#include + +struct cmd_tbl; + +#define WORD_SIZE 4 + +/* Minimum and maximum size of RSA signature length in bits */ +#define KEY_SIZE 4096 +#define KEY_SIZE_BYTES (KEY_SIZE/8) +#define KEY_SIZE_WORDS (KEY_SIZE_BYTES/(WORD_SIZE)) + +extern struct jobring jr; + +/* Barker code size in bytes */ +#define ESBC_BARKER_LEN 4 /* barker code length in ESBC uboot client */ + /* header */ + +/* No-error return values */ +#define ESBC_VALID_HDR 0 /* header is valid */ + +/* Maximum number of SG entries allowed */ +#define MAX_SG_ENTRIES 8 + +/* Different Header Struct for LS-CH3 */ +#ifdef CONFIG_ESBC_HDR_LS +struct fsl_secboot_img_hdr { + u8 barker[ESBC_BARKER_LEN]; /* barker code */ + u32 srk_tbl_off; + struct { + u8 num_srk; + u8 srk_sel; + u8 reserve; + } len_kr; + u8 ie_flag; + + u32 uid_flag; + + u32 psign; /* signature offset */ + u32 sign_len; /* length of the signature in bytes */ + + u64 pimg64; /* 64 bit pointer to ESBC Image */ + u32 img_size; /* ESBC client image size in bytes */ + u32 ie_key_sel; + + u32 fsl_uid_0; + u32 fsl_uid_1; + u32 oem_uid_0; + u32 oem_uid_1; + u32 oem_uid_2; + u32 oem_uid_3; + u32 oem_uid_4; + u32 reserved1[3]; +}; + +#ifdef CONFIG_KEY_REVOCATION +/* Srk table and key revocation check */ +#define UNREVOCABLE_KEY 8 +#define ALIGN_REVOC_KEY 7 +#define MAX_KEY_ENTRIES 8 +#endif + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#define IE_FLAG_MASK 0x1 +#define SCRATCH_IE_LOW_ADR 13 +#define SCRATCH_IE_HIGH_ADR 14 +#endif + +#else /* CONFIG_ESBC_HDR_LS */ + +/* + * ESBC uboot client header structure. + * The struct contain the following fields + * barker code + * public key offset + * pub key length + * signature offset + * length of the signature + * ptr to SG table + * no of entries in SG table + * esbc ptr + * size of esbc + * esbc entry point + * Scatter gather flag + * UID flag + * FSL UID + * OEM UID + * Here, pub key is modulus concatenated with exponent + * of equal length + */ +struct fsl_secboot_img_hdr { + u8 barker[ESBC_BARKER_LEN]; /* barker code */ + union { + u32 pkey; /* public key offset */ +#ifdef CONFIG_KEY_REVOCATION + u32 srk_tbl_off; +#endif + }; + + union { + u32 key_len; /* pub key length in bytes */ +#ifdef CONFIG_KEY_REVOCATION + struct { + u32 srk_table_flag:8; + u32 srk_sel:8; + u32 num_srk:16; + } len_kr; +#endif + }; + + u32 psign; /* signature offset */ + u32 sign_len; /* length of the signature in bytes */ + union { + u32 psgtable; /* ptr to SG table */ +#ifndef CONFIG_ESBC_ADDR_64BIT + u32 pimg; /* ptr to ESBC client image */ +#endif + }; + union { + u32 sg_entries; /* no of entries in SG table */ + u32 img_size; /* ESBC client image size in bytes */ + }; + u32 img_start; /* ESBC client entry point */ + u32 sg_flag; /* Scatter gather flag */ + u32 uid_flag; + u32 fsl_uid_0; + u32 oem_uid_0; + u32 reserved1[2]; + u32 fsl_uid_1; + u32 oem_uid_1; + union { + u32 reserved2[2]; +#ifdef CONFIG_ESBC_ADDR_64BIT + u64 pimg64; /* 64 bit pointer to ESBC Image */ +#endif + }; + u32 ie_flag; + u32 ie_key_sel; +}; + +#ifdef CONFIG_KEY_REVOCATION +/* Srk table and key revocation check */ +#define SRK_FLAG 0x01 +#define UNREVOCABLE_KEY 4 +#define ALIGN_REVOC_KEY 3 +#define MAX_KEY_ENTRIES 4 +#endif + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#define IE_FLAG_MASK 0xFFFFFFFF +#endif + +#endif /* CONFIG_ESBC_HDR_LS */ + + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +struct ie_key_table { + u32 key_len; + u8 pkey[2 * KEY_SIZE_BYTES]; +}; + +struct ie_key_info { + uint32_t key_revok; + uint32_t num_keys; + struct ie_key_table ie_key_tbl[32]; +}; +#endif + +#ifdef CONFIG_KEY_REVOCATION +struct srk_table { + u32 key_len; + u8 pkey[2 * KEY_SIZE_BYTES]; +}; +#endif + +/* + * SG table. + */ +#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET) +/* + * This struct contains the following fields + * length of the segment + * source address + */ +struct fsl_secboot_sg_table { + u32 len; /* length of the segment in bytes */ + u32 src_addr; /* ptr to the data segment */ +}; +#else +/* + * This struct contains the following fields + * length of the segment + * Destination Target ID + * source address + * destination address + */ +struct fsl_secboot_sg_table { + u32 len; + u32 trgt_id; + u32 src_addr; + u32 dst_addr; +}; +#endif + +/* ESBC global structure. + * Data to be used across verification of different images. + * Stores following Data: + * IE Table + */ +struct fsl_secboot_glb { +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + uintptr_t ie_addr; + struct ie_key_info ie_tbl; +#endif +}; +/* + * ESBC private structure. + * Private structure used by ESBC to store following fields + * ESBC client key + * ESBC client key hash + * ESBC client Signature + * Encoded hash recovered from signature + * Encoded hash of ESBC client header plus ESBC client image + */ +struct fsl_secboot_img_priv { + uint32_t hdr_location; + uintptr_t ie_addr; + u32 key_len; + struct fsl_secboot_img_hdr hdr; + + u8 img_key[2 * KEY_SIZE_BYTES]; /* ESBC client key */ + u8 img_key_hash[32]; /* ESBC client key hash */ + +#ifdef CONFIG_KEY_REVOCATION + struct srk_table srk_tbl[MAX_KEY_ENTRIES]; +#endif + u8 img_sign[KEY_SIZE_BYTES]; /* ESBC client signature */ + + u8 img_encoded_hash[KEY_SIZE_BYTES]; /* EM wrt RSA PKCSv1.5 */ + /* Includes hash recovered after + * signature verification + */ + + u8 img_encoded_hash_second[KEY_SIZE_BYTES];/* EM' wrt RSA PKCSv1.5 */ + /* Includes hash of + * ESBC client header plus + * ESBC client image + */ + + struct fsl_secboot_sg_table sgtbl[MAX_SG_ENTRIES]; /* SG table */ + uintptr_t ehdrloc; /* ESBC Header location */ + uintptr_t *img_addr_ptr; /* ESBC Image Location */ + uint32_t img_size; /* ESBC Image Size */ +}; + +int do_esbc_halt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); + +int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, + uintptr_t *img_addr_ptr); +int fsl_secboot_blob_encap(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); +int fsl_secboot_blob_decap(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); + +int fsl_check_boot_mode_secure(void); +int fsl_setenv_chain_of_trust(void); + +/* + * This function is used to validate the main U-boot binary from + * SPL just before passing control to it using QorIQ Trust + * Architecture header (appended to U-boot image). + */ +void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr); +#endif diff --git a/roms/u-boot/include/fsl_wdog.h b/roms/u-boot/include/fsl_wdog.h new file mode 100644 index 000000000..655f22ed9 --- /dev/null +++ b/roms/u-boot/include/fsl_wdog.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Freescale Semiconductor, Inc. + */ + +struct watchdog_regs { + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ +}; + +#define WCR_WDZST 0x01 +#define WCR_WDBG 0x02 +#define WCR_WDE 0x04 +#define WCR_WDT 0x08 +#define WCR_SRS 0x10 +#define WCR_WDA 0x20 +#define SET_WCR_WT(x) (x << 8) +#define WCR_WT_MSK SET_WCR_WT(0xFF) diff --git a/roms/u-boot/include/fuse.h b/roms/u-boot/include/fuse.h new file mode 100644 index 000000000..d48dcdfa6 --- /dev/null +++ b/roms/u-boot/include/fuse.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009-2013 ADVANSEE + * Benoît Thébaudeau + * + * Based on the mpc512x iim code: + * Copyright 2008 Silicon Turnkey Express, Inc. + * Martha Marx + */ + +#ifndef _FUSE_H_ +#define _FUSE_H_ + +/* + * Read/Sense/Program/Override interface: + * bank: Fuse bank + * word: Fuse word within the bank + * val: Value to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int fuse_read(u32 bank, u32 word, u32 *val); +int fuse_sense(u32 bank, u32 word, u32 *val); +int fuse_prog(u32 bank, u32 word, u32 val); +int fuse_override(u32 bank, u32 word, u32 val); + +#endif /* _FUSE_H_ */ diff --git a/roms/u-boot/include/g_dnl.h b/roms/u-boot/include/g_dnl.h new file mode 100644 index 000000000..836ee602c --- /dev/null +++ b/roms/u-boot/include/g_dnl.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Samsung Electronics + * Lukasz Majewski + */ + +#ifndef __G_DOWNLOAD_H_ +#define __G_DOWNLOAD_H_ + +#include +#include +#include +#include + +/* + * @usb_fname: unescaped USB function name + * @callback_ptr: bind callback, one per function name + */ +#define DECLARE_GADGET_BIND_CALLBACK(usb_fname, callback_ptr) \ + ll_entry_declare(struct g_dnl_bind_callback, \ + __usb_function_name_##usb_fname, \ + g_dnl_bind_callbacks) = { \ + .usb_function_name = #usb_fname, \ + .fptr = callback_ptr \ + } + +typedef int (*g_dnl_bind_callback_f)(struct usb_configuration *); + +/* used in Gadget downloader callback linker list */ +struct g_dnl_bind_callback { + const char *usb_function_name; + g_dnl_bind_callback_f fptr; +}; + +int g_dnl_bind_fixup(struct usb_device_descriptor *, const char *); +int g_dnl_get_board_bcd_device_number(int gcnum); +int g_dnl_board_usb_cable_connected(void); +int g_dnl_register(const char *s); +void g_dnl_unregister(void); +void g_dnl_set_serialnumber(char *); +void g_dnl_set_product(const char *s); + +bool g_dnl_detach(void); +void g_dnl_trigger_detach(void); +void g_dnl_clear_detach(void); +int run_usb_dnl_gadget(int usbctrl_index, char *usb_dnl_gadget); + +#endif /* __G_DOWNLOAD_H_ */ diff --git a/roms/u-boot/include/gdsys_fpga.h b/roms/u-boot/include/gdsys_fpga.h new file mode 100644 index 000000000..aa9b9f58b --- /dev/null +++ b/roms/u-boot/include/gdsys_fpga.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + */ + +#ifndef __GDSYS_FPGA_H +#define __GDSYS_FPGA_H + +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS +int init_func_fpga(void); + +enum { + FPGA_STATE_DONE_FAILED = 1 << 0, + FPGA_STATE_REFLECTION_FAILED = 1 << 1, + FPGA_STATE_PLATFORM = 1 << 2, +}; + +int get_fpga_state(unsigned dev); + +int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data); +int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data); + +extern struct ihs_fpga *fpga_ptr[]; + +#define FPGA_SET_REG(ix, fld, val) \ + fpga_set_reg((ix), \ + &fpga_ptr[ix]->fld, \ + offsetof(struct ihs_fpga, fld), \ + val) + +#define FPGA_GET_REG(ix, fld, val) \ + fpga_get_reg((ix), \ + &fpga_ptr[ix]->fld, \ + offsetof(struct ihs_fpga, fld), \ + val) +#endif + +struct ihs_gpio { + u16 read; + u16 clear; + u16 set; +}; + +struct ihs_i2c { + u16 interrupt_status; + u16 interrupt_enable; + u16 write_mailbox_ext; + u16 write_mailbox; + u16 read_mailbox_ext; + u16 read_mailbox; +}; + +struct ihs_osd { + u16 version; + u16 features; + u16 control; + u16 xy_size; + u16 xy_scale; + u16 x_pos; + u16 y_pos; +}; + +struct ihs_mdio { + u16 control; + u16 address_data; + u16 rx_data; +}; + +struct ihs_io_ep { + u16 transmit_data; + u16 rx_tx_control; + u16 receive_data; + u16 rx_tx_status; + u16 reserved; + u16 device_address; + u16 target_address; +}; + +#ifdef CONFIG_NEO +struct ihs_fpga { + u16 reflection_low; /* 0x0000 */ + u16 versions; /* 0x0002 */ + u16 fpga_features; /* 0x0004 */ + u16 fpga_version; /* 0x0006 */ + u16 reserved_0[8187]; /* 0x0008 */ + u16 reflection_high; /* 0x3ffe */ +}; +#endif + +#endif diff --git a/roms/u-boot/include/generic-phy.h b/roms/u-boot/include/generic-phy.h new file mode 100644 index 000000000..a17d900e4 --- /dev/null +++ b/roms/u-boot/include/generic-phy.h @@ -0,0 +1,423 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Written by Jean-Jacques Hiblot + */ + +#ifndef __GENERIC_PHY_H +#define __GENERIC_PHY_H + +#include + +struct ofnode_phandle_args; + +/** + * struct phy - A handle to (allowing control of) a single phy port. + * + * Clients provide storage for phy handles. The content of the structure is + * managed solely by the PHY API and PHY drivers. A phy struct is + * initialized by "get"ing the phy struct. The phy struct is passed to all + * other phy APIs to identify which PHY port to operate upon. + * + * @dev: The device which implements the PHY port. + * @id: The PHY ID within the provider. + * + */ +struct phy { + struct udevice *dev; + unsigned long id; +}; + +/* + * struct udevice_ops - set of function pointers for phy operations + * @init: operation to be performed for initializing phy (optional) + * @exit: operation to be performed while exiting (optional) + * @reset: reset the phy (optional). + * @power_on: powering on the phy (optional) + * @power_off: powering off the phy (optional) + */ +struct phy_ops { + /** + * of_xlate - Translate a client's device-tree (OF) phy specifier. + * + * The PHY core calls this function as the first step in implementing + * a client's generic_phy_get_by_*() call. + * + * If this function pointer is set to NULL, the PHY core will use a + * default implementation, which assumes #phy-cells = <0> or + * #phy-cells = <1>, and in the later case that the DT cell + * contains a simple integer PHY port ID. + * + * @phy: The phy struct to hold the translation result. + * @args: The phy specifier values from device tree. + * @return 0 if OK, or a negative error code. + */ + int (*of_xlate)(struct phy *phy, struct ofnode_phandle_args *args); + + /** + * init - initialize the hardware. + * + * Hardware intialization should not be done in during probe() but + * should be implemented in this init() function. It could be starting + * PLL, taking a controller out of reset, routing, etc. This function + * is typically called only once per PHY port. + * If power_on() is not implemented, it must power up the phy. + * + * @phy: the PHY port to initialize + * @return 0 if OK, or a negative error code. + */ + int (*init)(struct phy *phy); + + /** + * exit - de-initialize the PHY device + * + * Hardware de-intialization should be done here. Every step done in + * init() should be undone here. + * This could be used to suspend the phy to reduce power consumption or + * to put the phy in a known condition before booting the OS (though it + * is NOT called automatically before booting the OS) + * If power_off() is not implemented, it must power down the phy. + * + * @phy: PHY port to be de-initialized + * @return 0 if OK, or a negative error code + */ + int (*exit)(struct phy *phy); + + /** + * reset - resets a PHY device without shutting down + * + * @phy: PHY port to be reset + * + * During runtime, the PHY may need to be reset in order to + * re-establish connection etc without being shut down or exit. + * + * @return 0 if OK, or a negative error code + */ + int (*reset)(struct phy *phy); + + /** + * power_on - power on a PHY device + * + * @phy: PHY port to be powered on + * + * During runtime, the PHY may need to be powered on or off several + * times. This function is used to power on the PHY. It relies on the + * setup done in init(). If init() is not implemented, it must take care + * of setting up the context (PLLs, ...) + * + * @return 0 if OK, or a negative error code + */ + int (*power_on)(struct phy *phy); + + /** + * power_off - power off a PHY device + * + * @phy: PHY port to be powered off + * + * During runtime, the PHY may need to be powered on or off several + * times. This function is used to power off the PHY. Except if + * init()/deinit() are not implemented, it must not de-initialize + * everything. + * + * @return 0 if OK, or a negative error code + */ + int (*power_off)(struct phy *phy); + + /** + * configure - configure a PHY device + * + * @phy: PHY port to be configured + * @params: PHY Parameters, underlying data is specific to the PHY function + * + * During runtime, the PHY may need to be configured for it's main function. + * This function configures the PHY for it's main function following + * power_on/off() after beeing initialized. + * + * @return 0 if OK, or a negative error code + */ + int (*configure)(struct phy *phy, void *params); +}; + +/** + * struct phy_bulk - A handle to (allowing control of) a bulk of phys. + * + * Consumers provide storage for the phy bulk. The content of the structure is + * managed solely by the phy API. A phy bulk struct is initialized + * by "get"ing the phy bulk struct. + * The phy bulk struct is passed to all other bulk phy APIs to apply + * the API to all the phy in the bulk struct. + * + * @phys: An array of phy handles. + * @count: The number of phy handles in the phys array. + */ +struct phy_bulk { + struct phy *phys; + unsigned int count; +}; + +#ifdef CONFIG_PHY + +/** + * generic_phy_init() - initialize the PHY port + * + * @phy: the PHY port to initialize + * @return 0 if OK, or a negative error code + */ +int generic_phy_init(struct phy *phy); + +/** + * generic_phy_init() - de-initialize the PHY device + * + * @phy: PHY port to be de-initialized + * @return 0 if OK, or a negative error code + */ +int generic_phy_exit(struct phy *phy); + +/** + * generic_phy_reset() - resets a PHY device without shutting down + * + * @phy: PHY port to be reset + *@return 0 if OK, or a negative error code + */ +int generic_phy_reset(struct phy *phy); + +/** + * generic_phy_power_on() - power on a PHY device + * + * @phy: PHY port to be powered on + * @return 0 if OK, or a negative error code + */ +int generic_phy_power_on(struct phy *phy); + +/** + * generic_phy_power_off() - power off a PHY device + * + * @phy: PHY port to be powered off + * @return 0 if OK, or a negative error code + */ +int generic_phy_power_off(struct phy *phy); + +/** + * generic_phy_configure() - configure a PHY device + * + * @phy: PHY port to be configured + * @params: PHY Parameters, underlying data is specific to the PHY function + * @return 0 if OK, or a negative error code + */ +int generic_phy_configure(struct phy *phy, void *params); + + +/** + * generic_phy_get_by_index() - Get a PHY device by integer index. + * + * @user: the client device + * @index: The index in the list of available PHYs + * @phy: A pointer to the PHY port + * + * This looks up a PHY device for a client device based on its position in the + * list of the possible PHYs. + * + * example: + * usb1: usb_otg_ss@xxx { + * compatible = "xxx"; + * reg = ; + * . + * . + * phys = <&usb2_phy>, <&usb3_phy>; + * . + * . + * }; + * the USB2 phy can be accessed by passing index '0' and the USB3 phy can + * be accessed by passing index '1' + * + * @return 0 if OK, or a negative error code + */ +int generic_phy_get_by_index(struct udevice *user, int index, + struct phy *phy); + +/** + * generic_phy_get_by_index_nodev() - Get a PHY device by integer index + * without a device + * + * @node: The client ofnode. + * @index: The index in the list of available PHYs + * @phy: A pointer to the PHY port + * + * This is a version of generic_phy_get_by_index() that does not use a device. + * + * This looks up a PHY device for a client device based on its ofnode and on + * its position in the list of the possible PHYs. + * + * example: + * usb1: usb_otg_ss@xxx { + * compatible = "xxx"; + * reg = ; + * . + * . + * phys = <&usb2_phy>, <&usb3_phy>; + * . + * . + * }; + * the USB2 phy can be accessed by passing index '0' and the USB3 phy can + * be accessed by passing index '1' + * + * @return 0 if OK, or a negative error code + */ +int generic_phy_get_by_index_nodev(ofnode node, int index, struct phy *phy); + +/** + * generic_phy_get_by_name() - Get a PHY device by its name. + * + * @user: the client device + * @phy_name: The name of the PHY in the list of possible PHYs + * @phy: A pointer to the PHY port + * + * This looks up a PHY device for a client device in the + * list of the possible PHYs based on its name. + * + * example: + * usb1: usb_otg_ss@xxx { + * compatible = "xxx"; + * reg = ; + * . + * . + * phys = <&usb2_phy>, <&usb3_phy>; + * phy-names = "usb2phy", "usb3phy"; + * . + * . + * }; + * the USB3 phy can be accessed using "usb3phy", and USB2 by using "usb2phy" + * + * @return 0 if OK, or a negative error code + */ +int generic_phy_get_by_name(struct udevice *user, const char *phy_name, + struct phy *phy); + +/** + * generic_phy_get_bulk - Get all phys of a device. + * + * This looks up and gets all phys of the consumer device; each device is + * assumed to have n phys associated with it somehow, and this function finds + * and gets all of them in a separate structure. + * + * @dev: The consumer device. + * @bulk A pointer to a phy bulk struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int generic_phy_get_bulk(struct udevice *dev, struct phy_bulk *bulk); + +/** + * generic_phy_init_bulk() - Initialize all phys in a phy bulk struct. + * + * @bulk: A phy bulk struct that was previously successfully requested + * by generic_phy_get_bulk(). + * @return 0 if OK, or negative error code. + */ +int generic_phy_init_bulk(struct phy_bulk *bulk); + +/** + * generic_phy_exit_bulk() - de-initialize all phys in a phy bulk struct. + * + * @bulk: A phy bulk struct that was previously successfully requested + * by generic_phy_get_bulk(). + * @return 0 if OK, or negative error code. + */ +int generic_phy_exit_bulk(struct phy_bulk *bulk); + +/** + * generic_phy_power_on_bulk() - Power on all phys in a phy bulk struct. + * + * @bulk: A phy bulk struct that was previously successfully requested + * by generic_phy_get_bulk(). + * @return 0 if OK, or negative error code. + */ +int generic_phy_power_on_bulk(struct phy_bulk *bulk); + +/** + * generic_phy_power_off_bulk() - Power off all phys in a phy bulk struct. + * + * @bulk: A phy bulk struct that was previously successfully requested + * by generic_phy_get_bulk(). + * @return 0 if OK, or negative error code. + */ +int generic_phy_power_off_bulk(struct phy_bulk *bulk); + +#else /* CONFIG_PHY */ + +static inline int generic_phy_init(struct phy *phy) +{ + return 0; +} + +static inline int generic_phy_exit(struct phy *phy) +{ + return 0; +} + +static inline int generic_phy_reset(struct phy *phy) +{ + return 0; +} + +static inline int generic_phy_power_on(struct phy *phy) +{ + return 0; +} + +static inline int generic_phy_power_off(struct phy *phy) +{ + return 0; +} + +static inline int generic_phy_get_by_index(struct udevice *user, int index, + struct phy *phy) +{ + return 0; +} + +static inline int generic_phy_get_by_name(struct udevice *user, const char *phy_name, + struct phy *phy) +{ + return 0; +} + +static inline int +generic_phy_get_bulk(struct udevice *dev, struct phy_bulk *bulk) +{ + return 0; +} + +static inline int generic_phy_init_bulk(struct phy_bulk *bulk) +{ + return 0; +} + +static inline int generic_phy_exit_bulk(struct phy_bulk *bulk) +{ + return 0; +} + +static inline int generic_phy_power_on_bulk(struct phy_bulk *bulk) +{ + return 0; +} + +static inline int generic_phy_power_off_bulk(struct phy_bulk *bulk) +{ + return 0; +} + +#endif /* CONFIG_PHY */ + +/** + * generic_phy_valid() - check if PHY port is valid + * + * @phy: the PHY port to check + * @return TRUE if valid, or FALSE + */ +static inline bool generic_phy_valid(struct phy *phy) +{ + return phy && phy->dev; +} + +#endif /*__GENERIC_PHY_H */ diff --git a/roms/u-boot/include/getopt.h b/roms/u-boot/include/getopt.h new file mode 100644 index 000000000..6f5811e64 --- /dev/null +++ b/roms/u-boot/include/getopt.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * getopt.h - a simple getopt(3) implementation. + * + * Copyright (C) 2020 Sean Anderson + * Copyright (c) 2007 Sascha Hauer , Pengutronix + */ + +#ifndef __GETOPT_H +#define __GETOPT_H + +/** + * struct getopt_state - Saved state across getopt() calls + */ +struct getopt_state { + /** + * @index: Index of the next unparsed argument of @argv. If getopt() has + * parsed all of @argv, then @index will equal @argc. + */ + int index; + /* private: */ + /** @arg_index: Index within the current argument */ + int arg_index; + union { + /* public: */ + /** + * @opt: Option being parsed when an error occurs. @opt is only + * valid when getopt() returns ``?`` or ``:``. + */ + int opt; + /** + * @arg: The argument to an option, NULL if there is none. @arg + * is only valid when getopt() returns an option character. + */ + char *arg; + /* private: */ + }; +}; + +/** + * getopt_init_state() - Initialize a &struct getopt_state + * @gs: The state to initialize + * + * This must be called before using @gs with getopt(). + */ +void getopt_init_state(struct getopt_state *gs); + +int __getopt(struct getopt_state *gs, int argc, char *const argv[], + const char *optstring, bool silent); + +/** + * getopt() - Parse short command-line options + * @gs: Internal state and out-of-band return arguments. This must be + * initialized with getopt_init_context() beforehand. + * @argc: Number of arguments, not including the %NULL terminator + * @argv: Argument list, terminated by %NULL + * @optstring: Option specification, as described below + * + * getopt() parses short options. Short options are single characters. They may + * be followed by a required argument or an optional argument. Arguments to + * options may occur in the same argument as an option (like ``-larg``), or + * in the following argument (like ``-l arg``). An argument containing + * options begins with a ``-``. If an option expects no arguments, then it may + * be immediately followed by another option (like ``ls -alR``). + * + * @optstring is a list of accepted options. If an option is followed by ``:`` + * in @optstring, then it expects a mandatory argument. If an option is followed + * by ``::`` in @optstring, it expects an optional argument. @gs.arg points + * to the argument, if one is parsed. + * + * getopt() stops parsing options when it encounters the first non-option + * argument, when it encounters the argument ``--``, or when it runs out of + * arguments. For example, in ``ls -l foo -R``, option parsing will stop when + * getopt() encounters ``foo``, if ``l`` does not expect an argument. However, + * the whole list of arguments would be parsed if ``l`` expects an argument. + * + * An example invocation of getopt() might look like:: + * + * char *argv[] = { "program", "-cbx", "-a", "foo", "bar", 0 }; + * int opt, argc = ARRAY_SIZE(argv) - 1; + * struct getopt_state gs; + * + * getopt_init_state(&gs); + * while ((opt = getopt(&gs, argc, argv, "a::b:c")) != -1) + * printf("opt = %c, index = %d, arg = \"%s\"\n", opt, gs.index, gs.arg); + * printf("%d argument(s) left\n", argc - gs.index); + * + * and would produce an output of:: + * + * opt = c, index = 1, arg = "" + * opt = b, index = 2, arg = "x" + * opt = a, index = 4, arg = "foo" + * 1 argument(s) left + * + * For further information, refer to the getopt(3) man page. + * + * Return: + * * An option character if an option is found. @gs.arg is set to the + * argument if there is one, otherwise it is set to ``NULL``. + * * ``-1`` if there are no more options, if a non-option argument is + * encountered, or if an ``--`` argument is encountered. + * * ``'?'`` if we encounter an option not in @optstring. @gs.opt is set to + * the unknown option. + * * ``':'`` if an argument is required, but no argument follows the + * option. @gs.opt is set to the option missing its argument. + * + * @gs.index is always set to the index of the next unparsed argument in @argv. + */ +static inline int getopt(struct getopt_state *gs, int argc, + char *const argv[], const char *optstring) +{ + return __getopt(gs, argc, argv, optstring, false); +} + +/** + * getopt_silent() - Parse short command-line options silently + * @gs: State + * @argc: Argument count + * @argv: Argument list + * @optstring: Option specification + * + * Same as getopt(), except no error messages are printed. + */ +static inline int getopt_silent(struct getopt_state *gs, int argc, + char *const argv[], const char *optstring) +{ + return __getopt(gs, argc, argv, optstring, true); +} + +#endif /* __GETOPT_H */ diff --git a/roms/u-boot/include/gt64120.h b/roms/u-boot/include/gt64120.h new file mode 100644 index 000000000..0b577f3f4 --- /dev/null +++ b/roms/u-boot/include/gt64120.h @@ -0,0 +1,538 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef _ASM_GT64120_H +#define _ASM_GT64120_H + +#define MSK(n) ((1 << (n)) - 1) + +/* + * Register offset addresses + */ +/* CPU Configuration. */ +#define GT_CPU_OFS 0x000 + +#define GT_MULTI_OFS 0x120 + +/* CPU Address Decode. */ +#define GT_SCS10LD_OFS 0x008 +#define GT_SCS10HD_OFS 0x010 +#define GT_SCS32LD_OFS 0x018 +#define GT_SCS32HD_OFS 0x020 +#define GT_CS20LD_OFS 0x028 +#define GT_CS20HD_OFS 0x030 +#define GT_CS3BOOTLD_OFS 0x038 +#define GT_CS3BOOTHD_OFS 0x040 +#define GT_PCI0IOLD_OFS 0x048 +#define GT_PCI0IOHD_OFS 0x050 +#define GT_PCI0M0LD_OFS 0x058 +#define GT_PCI0M0HD_OFS 0x060 +#define GT_ISD_OFS 0x068 + +#define GT_PCI0M1LD_OFS 0x080 +#define GT_PCI0M1HD_OFS 0x088 +#define GT_PCI1IOLD_OFS 0x090 +#define GT_PCI1IOHD_OFS 0x098 +#define GT_PCI1M0LD_OFS 0x0a0 +#define GT_PCI1M0HD_OFS 0x0a8 +#define GT_PCI1M1LD_OFS 0x0b0 +#define GT_PCI1M1HD_OFS 0x0b8 +#define GT_PCI1M1LD_OFS 0x0b0 +#define GT_PCI1M1HD_OFS 0x0b8 + +#define GT_SCS10AR_OFS 0x0d0 +#define GT_SCS32AR_OFS 0x0d8 +#define GT_CS20R_OFS 0x0e0 +#define GT_CS3BOOTR_OFS 0x0e8 + +#define GT_PCI0IOREMAP_OFS 0x0f0 +#define GT_PCI0M0REMAP_OFS 0x0f8 +#define GT_PCI0M1REMAP_OFS 0x100 +#define GT_PCI1IOREMAP_OFS 0x108 +#define GT_PCI1M0REMAP_OFS 0x110 +#define GT_PCI1M1REMAP_OFS 0x118 + +/* CPU Error Report. */ +#define GT_CPUERR_ADDRLO_OFS 0x070 +#define GT_CPUERR_ADDRHI_OFS 0x078 + +#define GT_CPUERR_DATALO_OFS 0x128 /* GT-64120A only */ +#define GT_CPUERR_DATAHI_OFS 0x130 /* GT-64120A only */ +#define GT_CPUERR_PARITY_OFS 0x138 /* GT-64120A only */ + +/* CPU Sync Barrier. */ +#define GT_PCI0SYNC_OFS 0x0c0 +#define GT_PCI1SYNC_OFS 0x0c8 + +/* SDRAM and Device Address Decode. */ +#define GT_SCS0LD_OFS 0x400 +#define GT_SCS0HD_OFS 0x404 +#define GT_SCS1LD_OFS 0x408 +#define GT_SCS1HD_OFS 0x40c +#define GT_SCS2LD_OFS 0x410 +#define GT_SCS2HD_OFS 0x414 +#define GT_SCS3LD_OFS 0x418 +#define GT_SCS3HD_OFS 0x41c +#define GT_CS0LD_OFS 0x420 +#define GT_CS0HD_OFS 0x424 +#define GT_CS1LD_OFS 0x428 +#define GT_CS1HD_OFS 0x42c +#define GT_CS2LD_OFS 0x430 +#define GT_CS2HD_OFS 0x434 +#define GT_CS3LD_OFS 0x438 +#define GT_CS3HD_OFS 0x43c +#define GT_BOOTLD_OFS 0x440 +#define GT_BOOTHD_OFS 0x444 + +#define GT_ADERR_OFS 0x470 + +/* SDRAM Configuration. */ +#define GT_SDRAM_CFG_OFS 0x448 + +#define GT_SDRAM_OPMODE_OFS 0x474 +#define GT_SDRAM_BM_OFS 0x478 +#define GT_SDRAM_ADDRDECODE_OFS 0x47c + +/* SDRAM Parameters. */ +#define GT_SDRAM_B0_OFS 0x44c +#define GT_SDRAM_B1_OFS 0x450 +#define GT_SDRAM_B2_OFS 0x454 +#define GT_SDRAM_B3_OFS 0x458 + +/* Device Parameters. */ +#define GT_DEV_B0_OFS 0x45c +#define GT_DEV_B1_OFS 0x460 +#define GT_DEV_B2_OFS 0x464 +#define GT_DEV_B3_OFS 0x468 +#define GT_DEV_BOOT_OFS 0x46c + +/* ECC. */ +#define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */ +#define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */ +#define GT_ECC_MEM 0x488 /* GT-64120A only */ +#define GT_ECC_CALC 0x48c /* GT-64120A only */ +#define GT_ECC_ERRADDR 0x490 /* GT-64120A only */ + +/* DMA Record. */ +#define GT_DMA0_CNT_OFS 0x800 +#define GT_DMA1_CNT_OFS 0x804 +#define GT_DMA2_CNT_OFS 0x808 +#define GT_DMA3_CNT_OFS 0x80c +#define GT_DMA0_SA_OFS 0x810 +#define GT_DMA1_SA_OFS 0x814 +#define GT_DMA2_SA_OFS 0x818 +#define GT_DMA3_SA_OFS 0x81c +#define GT_DMA0_DA_OFS 0x820 +#define GT_DMA1_DA_OFS 0x824 +#define GT_DMA2_DA_OFS 0x828 +#define GT_DMA3_DA_OFS 0x82c +#define GT_DMA0_NEXT_OFS 0x830 +#define GT_DMA1_NEXT_OFS 0x834 +#define GT_DMA2_NEXT_OFS 0x838 +#define GT_DMA3_NEXT_OFS 0x83c + +#define GT_DMA0_CUR_OFS 0x870 +#define GT_DMA1_CUR_OFS 0x874 +#define GT_DMA2_CUR_OFS 0x878 +#define GT_DMA3_CUR_OFS 0x87c + +/* DMA Channel Control. */ +#define GT_DMA0_CTRL_OFS 0x840 +#define GT_DMA1_CTRL_OFS 0x844 +#define GT_DMA2_CTRL_OFS 0x848 +#define GT_DMA3_CTRL_OFS 0x84c + +/* DMA Arbiter. */ +#define GT_DMA_ARB_OFS 0x860 + +/* Timer/Counter. */ +#define GT_TC0_OFS 0x850 +#define GT_TC1_OFS 0x854 +#define GT_TC2_OFS 0x858 +#define GT_TC3_OFS 0x85c + +#define GT_TC_CONTROL_OFS 0x864 + +/* PCI Internal. */ +#define GT_PCI0_CMD_OFS 0xc00 +#define GT_PCI0_TOR_OFS 0xc04 +#define GT_PCI0_BS_SCS10_OFS 0xc08 +#define GT_PCI0_BS_SCS32_OFS 0xc0c +#define GT_PCI0_BS_CS20_OFS 0xc10 +#define GT_PCI0_BS_CS3BT_OFS 0xc14 + +#define GT_PCI1_IACK_OFS 0xc30 +#define GT_PCI0_IACK_OFS 0xc34 + +#define GT_PCI0_BARE_OFS 0xc3c +#define GT_PCI0_PREFMBR_OFS 0xc40 + +#define GT_PCI0_SCS10_BAR_OFS 0xc48 +#define GT_PCI0_SCS32_BAR_OFS 0xc4c +#define GT_PCI0_CS20_BAR_OFS 0xc50 +#define GT_PCI0_CS3BT_BAR_OFS 0xc54 +#define GT_PCI0_SSCS10_BAR_OFS 0xc58 +#define GT_PCI0_SSCS32_BAR_OFS 0xc5c + +#define GT_PCI0_SCS3BT_BAR_OFS 0xc64 + +#define GT_PCI1_CMD_OFS 0xc80 +#define GT_PCI1_TOR_OFS 0xc84 +#define GT_PCI1_BS_SCS10_OFS 0xc88 +#define GT_PCI1_BS_SCS32_OFS 0xc8c +#define GT_PCI1_BS_CS20_OFS 0xc90 +#define GT_PCI1_BS_CS3BT_OFS 0xc94 + +#define GT_PCI1_BARE_OFS 0xcbc +#define GT_PCI1_PREFMBR_OFS 0xcc0 + +#define GT_PCI1_SCS10_BAR_OFS 0xcc8 +#define GT_PCI1_SCS32_BAR_OFS 0xccc +#define GT_PCI1_CS20_BAR_OFS 0xcd0 +#define GT_PCI1_CS3BT_BAR_OFS 0xcd4 +#define GT_PCI1_SSCS10_BAR_OFS 0xcd8 +#define GT_PCI1_SSCS32_BAR_OFS 0xcdc + +#define GT_PCI1_SCS3BT_BAR_OFS 0xce4 + +#define GT_PCI1_CFGADDR_OFS 0xcf0 +#define GT_PCI1_CFGDATA_OFS 0xcf4 +#define GT_PCI0_CFGADDR_OFS 0xcf8 +#define GT_PCI0_CFGDATA_OFS 0xcfc + +/* Interrupts. */ +#define GT_INTRCAUSE_OFS 0xc18 +#define GT_INTRMASK_OFS 0xc1c + +#define GT_PCI0_ICMASK_OFS 0xc24 +#define GT_PCI0_SERR0MASK_OFS 0xc28 + +#define GT_CPU_INTSEL_OFS 0xc70 +#define GT_PCI0_INTSEL_OFS 0xc74 + +#define GT_HINTRCAUSE_OFS 0xc98 +#define GT_HINTRMASK_OFS 0xc9c + +#define GT_PCI0_HICMASK_OFS 0xca4 +#define GT_PCI1_SERR1MASK_OFS 0xca8 + + +/* + * I2O Support Registers + */ +#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 +#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 +#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 +#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c +#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 +#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 +#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 +#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c +#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 +#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 +#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 +#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 +#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 +#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 +#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 +#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 +#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 +#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c +#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 +#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 +#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 +#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c + +#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10 +#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14 +#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18 +#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c +#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20 +#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24 +#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28 +#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c +#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30 +#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34 +#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40 +#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44 +#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50 +#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54 +#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60 +#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64 +#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68 +#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c +#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70 +#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74 +#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78 +#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c + +/* + * Register encodings + */ +#define GT_CPU_ENDIAN_SHF 12 +#define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF) +#define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK +#define GT_CPU_WR_SHF 16 +#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) +#define GT_CPU_WR_BIT GT_CPU_WR_MSK +#define GT_CPU_WR_DXDXDXDX 0 +#define GT_CPU_WR_DDDD 1 + + +#define GT_PCI_DCRM_SHF 21 +#define GT_PCI_LD_SHF 0 +#define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF) +#define GT_PCI_HD_SHF 0 +#define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF) +#define GT_PCI_REMAP_SHF 0 +#define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF) + + +#define GT_CFGADDR_CFGEN_SHF 31 +#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) +#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK + +#define GT_CFGADDR_BUSNUM_SHF 16 +#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) + +#define GT_CFGADDR_DEVNUM_SHF 11 +#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) + +#define GT_CFGADDR_FUNCNUM_SHF 8 +#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) + +#define GT_CFGADDR_REGNUM_SHF 2 +#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) + + +#define GT_SDRAM_BM_ORDER_SHF 2 +#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) +#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK +#define GT_SDRAM_BM_ORDER_SUB 1 +#define GT_SDRAM_BM_ORDER_LIN 0 + +#define GT_SDRAM_BM_RSVD_ALL1 0xffb + + +#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 +#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) +#define GT_SDRAM_ADDRDECODE_ADDR_0 0 +#define GT_SDRAM_ADDRDECODE_ADDR_1 1 +#define GT_SDRAM_ADDRDECODE_ADDR_2 2 +#define GT_SDRAM_ADDRDECODE_ADDR_3 3 +#define GT_SDRAM_ADDRDECODE_ADDR_4 4 +#define GT_SDRAM_ADDRDECODE_ADDR_5 5 +#define GT_SDRAM_ADDRDECODE_ADDR_6 6 +#define GT_SDRAM_ADDRDECODE_ADDR_7 7 + + +#define GT_SDRAM_B0_CASLAT_SHF 0 +#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) +#define GT_SDRAM_B0_CASLAT_2 1 +#define GT_SDRAM_B0_CASLAT_3 2 + +#define GT_SDRAM_B0_FTDIS_SHF 2 +#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) +#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK + +#define GT_SDRAM_B0_SRASPRCHG_SHF 3 +#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) +#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK +#define GT_SDRAM_B0_SRASPRCHG_2 0 +#define GT_SDRAM_B0_SRASPRCHG_3 1 + +#define GT_SDRAM_B0_B0COMPAB_SHF 4 +#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) +#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK + +#define GT_SDRAM_B0_64BITINT_SHF 5 +#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) +#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK +#define GT_SDRAM_B0_64BITINT_2 0 +#define GT_SDRAM_B0_64BITINT_4 1 + +#define GT_SDRAM_B0_BW_SHF 6 +#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) +#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK +#define GT_SDRAM_B0_BW_32 0 +#define GT_SDRAM_B0_BW_64 1 + +#define GT_SDRAM_B0_BLODD_SHF 7 +#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) +#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK + +#define GT_SDRAM_B0_PAR_SHF 8 +#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) +#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK + +#define GT_SDRAM_B0_BYPASS_SHF 9 +#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) +#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK + +#define GT_SDRAM_B0_SRAS2SCAS_SHF 10 +#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) +#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK +#define GT_SDRAM_B0_SRAS2SCAS_2 0 +#define GT_SDRAM_B0_SRAS2SCAS_3 1 + +#define GT_SDRAM_B0_SIZE_SHF 11 +#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) +#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK +#define GT_SDRAM_B0_SIZE_16M 0 +#define GT_SDRAM_B0_SIZE_64M 1 + +#define GT_SDRAM_B0_EXTPAR_SHF 12 +#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) +#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK + +#define GT_SDRAM_B0_BLEN_SHF 13 +#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) +#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK +#define GT_SDRAM_B0_BLEN_8 0 +#define GT_SDRAM_B0_BLEN_4 1 + + +#define GT_SDRAM_CFG_REFINT_SHF 0 +#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) + +#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 +#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) +#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK + +#define GT_SDRAM_CFG_RMW_SHF 15 +#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) +#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK + +#define GT_SDRAM_CFG_NONSTAGREF_SHF 16 +#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) +#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK + +#define GT_SDRAM_CFG_DUPCNTL_SHF 19 +#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) +#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK + +#define GT_SDRAM_CFG_DUPBA_SHF 20 +#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) +#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK + +#define GT_SDRAM_CFG_DUPEOT0_SHF 21 +#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) +#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK + +#define GT_SDRAM_CFG_DUPEOT1_SHF 22 +#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) +#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK + +#define GT_SDRAM_OPMODE_OP_SHF 0 +#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) +#define GT_SDRAM_OPMODE_OP_NORMAL 0 +#define GT_SDRAM_OPMODE_OP_NOP 1 +#define GT_SDRAM_OPMODE_OP_PRCHG 2 +#define GT_SDRAM_OPMODE_OP_MODE 3 +#define GT_SDRAM_OPMODE_OP_CBR 4 + +#define GT_TC_CONTROL_ENTC0_SHF 0 +#define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF) +#define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK +#define GT_TC_CONTROL_SELTC0_SHF 1 +#define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF) +#define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK + + +#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 +#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK \ + (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) +#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK + +#define GT_PCI0_BARE_SWSCS32DIS_SHF 1 +#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) +#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK + +#define GT_PCI0_BARE_SWSCS10DIS_SHF 2 +#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) +#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK + +#define GT_PCI0_BARE_INTIODIS_SHF 3 +#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) +#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK + +#define GT_PCI0_BARE_INTMEMDIS_SHF 4 +#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) +#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK + +#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 +#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) +#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK + +#define GT_PCI0_BARE_CS20DIS_SHF 6 +#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) +#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK + +#define GT_PCI0_BARE_SCS32DIS_SHF 7 +#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) +#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK + +#define GT_PCI0_BARE_SCS10DIS_SHF 8 +#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) +#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK + + +#define GT_INTRCAUSE_MASABORT0_SHF 18 +#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) +#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK + +#define GT_INTRCAUSE_TARABORT0_SHF 19 +#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) +#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK + + +#define GT_PCI0_CFGADDR_REGNUM_SHF 2 +#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) +#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 +#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) +#define GT_PCI0_CFGADDR_DEVNUM_SHF 11 +#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) +#define GT_PCI0_CFGADDR_BUSNUM_SHF 16 +#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) +#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 +#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) +#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK + +#define GT_PCI0_CMD_MBYTESWAP_SHF 0 +#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) +#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK +#define GT_PCI0_CMD_MWORDSWAP_SHF 10 +#define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF) +#define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK +#define GT_PCI0_CMD_SBYTESWAP_SHF 16 +#define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF) +#define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK +#define GT_PCI0_CMD_SWORDSWAP_SHF 11 +#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) +#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK + +#define GT_INTR_T0EXP_SHF 8 +#define GT_INTR_T0EXP_MSK (MSK(1) << GT_INTR_T0EXP_SHF) +#define GT_INTR_T0EXP_BIT GT_INTR_T0EXP_MSK +#define GT_INTR_RETRYCTR0_SHF 20 +#define GT_INTR_RETRYCTR0_MSK (MSK(1) << GT_INTR_RETRYCTR0_SHF) +#define GT_INTR_RETRYCTR0_BIT GT_INTR_RETRYCTR0_MSK + +/* + * Misc + */ +#define GT_DEF_PCI0_IO_BASE 0x10000000 +#define GT_DEF_PCI0_IO_SIZE 0x02000000 +#define GT_DEF_PCI0_MEM0_BASE 0x12000000 +#define GT_DEF_PCI0_MEM0_SIZE 0x02000000 +#define GT_DEF_BASE 0x14000000 + +#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ +#define GT_LATTIM_MIN 6 /* Minimum lat */ + +#endif /* _ASM_GT64120_H */ diff --git a/roms/u-boot/include/gzip.h b/roms/u-boot/include/gzip.h new file mode 100644 index 000000000..783acbb60 --- /dev/null +++ b/roms/u-boot/include/gzip.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef __GZIP_H +#define __GZIP_H + +struct blk_desc; + +/** + * gzip_parse_header() - Parse a header from a gzip file + * + * This returns the length of the header. + * + * @src: Pointer to gzip file + * @len: Length of data + * @return length of header in bytes, or -1 if not enough data + */ +int gzip_parse_header(const unsigned char *src, unsigned long len); + +/** + * gunzip() - Decompress gzipped data + * + * @dst: Destination for uncompressed data + * @dstlen: Size of destination buffer + * @src: Source data to decompress + * @lenp: Returns length of uncompressed data + * @return 0 if OK, -1 on error + */ +int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp); + +/** + * zunzip() - Uncompress blocks compressed with zlib without headers + * + * @dst: Destination for uncompressed data + * @dstlen: Size of destination buffer + * @src: Source data to decompress + * @lenp: On entry, length data at @src. On exit, number of bytes used from @src + * @stoponerr: 0 to continue when a decode error is found, 1 to stop + * @offset: start offset within the src buffer + * @return 0 if OK, -1 on error + */ +int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp, + int stoponerr, int offset); + +/** + * gzwrite progress indicators: defined weak to allow board-specific + * overrides: + * + * gzwrite_progress_init called on startup + * gzwrite_progress called during decompress/write loop + * gzwrite_progress_finish called at end of loop to + * indicate success (retcode=0) or failure + */ +void gzwrite_progress_init(u64 expected_size); + +void gzwrite_progress(int iteration, u64 bytes_written, u64 total_bytes); + +void gzwrite_progress_finish(int retcode, u64 totalwritten, u64 totalsize, + u32 expected_crc, u32 calculated_crc); + +/** + * gzwrite() - decompress and write gzipped image from memory to block device + * + * @src: compressed image address + * @len: compressed image length in bytes + * @dev: block device descriptor + * @szwritebuf: bytes per write (pad to erase size) + * @startoffs: offset in bytes of first write + * @szexpected: expected uncompressed length, may be zero to use gzip trailer + * for files under 4GiB + * @return 0 if OK, -1 on error + */ +int gzwrite(unsigned char *src, int len, struct blk_desc *dev, ulong szwritebuf, + u64 startoffs, u64 szexpected); + +/** + * gzip()- Compress data into a buffer using the gzip algorithm + * + * @dst: Destination buffer for compressed data + * @lenp: On entry, space available in destination buffer (in bytes). On exit, + * number of bytes used in the buffer + * @src: Source data to compress + * @srclen: Size of source data + * @return 0 if OK, -1 on error + */ +int gzip(void *dst, unsigned long *lenp, unsigned char *src, ulong srclen); + +/** + * zzip() - Compress blocks with zlib + * + * @dst: Destination for compressed data + * @lenp: On entry, length data at @dst. On exit, number of bytes written to + * @dst + * @src: Source data to compress + * @srclen: Size of source data + * @stoponerr: 0 to continue when a decode error is found, 1 to stop + * @func: Some sort of function that is called to do something. !ADD DOCS HERE! + */ +int zzip(void *dst, ulong *lenp, unsigned char *src, ulong srclen, + int stoponerr, int (*func)(ulong, ulong)); + +#endif diff --git a/roms/u-boot/include/handoff.h b/roms/u-boot/include/handoff.h new file mode 100644 index 000000000..070a79c1b --- /dev/null +++ b/roms/u-boot/include/handoff.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Passing basic information from SPL to U-Boot proper + * + * Copyright 2018 Google, Inc + */ + +#ifndef __HANDOFF_H +#define __HANDOFF_H + +#if CONFIG_IS_ENABLED(HANDOFF) + +#include + +/** + * struct spl_handoff - information passed from SPL to U-Boot proper + * + * @ram_size: Value to use for gd->ram_size + */ +struct spl_handoff { + struct arch_spl_handoff arch; + u64 ram_size; + struct { + u64 start; + u64 size; + } ram_bank[CONFIG_NR_DRAM_BANKS]; +}; + +void handoff_save_dram(struct spl_handoff *ho); +void handoff_load_dram_size(struct spl_handoff *ho); +void handoff_load_dram_banks(struct spl_handoff *ho); + +/** + * handoff_arch_save() - Save arch-specific info into the handoff area + * + * This is defined to an empty function by default, but arch-specific code can + * define it to write to spi_handoff->arch. It is called from + * write_spl_handoff(). + * + * @ho: Handoff area to fill in + * @return 0 if OK, -ve on error + */ +int handoff_arch_save(struct spl_handoff *ho); + +#endif + +#endif diff --git a/roms/u-boot/include/hang.h b/roms/u-boot/include/hang.h new file mode 100644 index 000000000..27cda4935 --- /dev/null +++ b/roms/u-boot/include/hang.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef __HANG_H +#define __HANG_H + +#ifndef __ASSEMBLY__ +/** + * hang() - Print a message and stop execution + * + * This shows a 'hang' message where possible and then goes into an infinite + * loop. This is called by panic() if CONFIG_PANIC_HANG is enabled. + * + * This function does not return. + */ +void hang(void) __attribute__ ((noreturn)); +#endif + +#endif diff --git a/roms/u-boot/include/hash.h b/roms/u-boot/include/hash.h new file mode 100644 index 000000000..97bb3ed5d --- /dev/null +++ b/roms/u-boot/include/hash.h @@ -0,0 +1,162 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2012 The Chromium OS Authors. + */ + +#ifndef _HASH_H +#define _HASH_H + +struct cmd_tbl; + +/* + * Maximum digest size for all algorithms we support. Having this value + * avoids a malloc() or C99 local declaration in common/cmd_hash.c. + */ +#if defined(CONFIG_SHA384) || defined(CONFIG_SHA512) +#define HASH_MAX_DIGEST_SIZE 64 +#else +#define HASH_MAX_DIGEST_SIZE 32 +#endif + +enum { + HASH_FLAG_VERIFY = 1 << 0, /* Enable verify mode */ + HASH_FLAG_ENV = 1 << 1, /* Allow env vars */ +}; + +struct hash_algo { + const char *name; /* Name of algorithm */ + int digest_size; /* Length of digest */ + /** + * hash_func_ws: Generic hashing function + * + * This is the generic prototype for a hashing function. We only + * have the watchdog version at present. + * + * @input: Input buffer + * @ilen: Input buffer length + * @output: Checksum result (length depends on algorithm) + * @chunk_sz: Trigger watchdog after processing this many bytes + */ + void (*hash_func_ws)(const unsigned char *input, unsigned int ilen, + unsigned char *output, unsigned int chunk_sz); + int chunk_size; /* Watchdog chunk size */ + /* + * hash_init: Create the context for progressive hashing + * + * @algo: Pointer to the hash_algo struct + * @ctxp: Pointer to the pointer of the context for hashing + * @return 0 if ok, -1 on error + */ + int (*hash_init)(struct hash_algo *algo, void **ctxp); + /* + * hash_update: Perform hashing on the given buffer + * + * The context is freed by this function if an error occurs. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @buf: Pointer to the buffer being hashed + * @size: Size of the buffer being hashed + * @is_last: 1 if this is the last update; 0 otherwise + * @return 0 if ok, -1 on error + */ + int (*hash_update)(struct hash_algo *algo, void *ctx, const void *buf, + unsigned int size, int is_last); + /* + * hash_finish: Write the hash result to the given buffer + * + * The context is freed by this function. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @dest_buf: Pointer to the buffer for the result + * @size: Size of the buffer for the result + * @return 0 if ok, -ENOSPC if size of the result buffer is too small + * or -1 on other errors + */ + int (*hash_finish)(struct hash_algo *algo, void *ctx, void *dest_buf, + int size); +}; + +#ifndef USE_HOSTCC +/** + * hash_command: Process a hash command for a particular algorithm + * + * This common function is used to implement specific hash commands. + * + * @algo_name: Hash algorithm being used (lower case!) + * @flags: Flags value (HASH_FLAG_...) + * @cmdtp: Pointer to command table entry + * @flag: Some flags normally 0 (see CMD_FLAG_.. above) + * @argc: Number of arguments (arg 0 must be the command text) + * @argv: Arguments + */ +int hash_command(const char *algo_name, int flags, struct cmd_tbl *cmdtp, + int flag, int argc, char *const argv[]); + +/** + * hash_block() - Hash a block according to the requested algorithm + * + * The caller probably knows the hash length for the chosen algorithm, but + * in order to provide a general interface, and output_size parameter is + * provided. + * + * @algo_name: Hash algorithm to use + * @data: Data to hash + * @len: Lengh of data to hash in bytes + * @output: Place to put hash value + * @output_size: On entry, pointer to the number of bytes available in + * output. On exit, pointer to the number of bytes used. + * If NULL, then it is assumed that the caller has + * allocated enough space for the hash. This is possible + * since the caller is selecting the algorithm. + * @return 0 if ok, -ve on error: -EPROTONOSUPPORT for an unknown algorithm, + * -ENOSPC if the output buffer is not large enough. + */ +int hash_block(const char *algo_name, const void *data, unsigned int len, + uint8_t *output, int *output_size); + +#endif /* !USE_HOSTCC */ + +/** + * hash_lookup_algo() - Look up the hash_algo struct for an algorithm + * + * The function returns the pointer to the struct or -EPROTONOSUPPORT if the + * algorithm is not available. + * + * @algo_name: Hash algorithm to look up + * @algop: Pointer to the hash_algo struct if found + * + * @return 0 if ok, -EPROTONOSUPPORT for an unknown algorithm. + */ +int hash_lookup_algo(const char *algo_name, struct hash_algo **algop); + +/** + * hash_progressive_lookup_algo() - Look up hash_algo for prog. hash support + * + * The function returns the pointer to the struct or -EPROTONOSUPPORT if the + * algorithm is not available with progressive hash support. + * + * @algo_name: Hash algorithm to look up + * @algop: Pointer to the hash_algo struct if found + * + * @return 0 if ok, -EPROTONOSUPPORT for an unknown algorithm. + */ +int hash_progressive_lookup_algo(const char *algo_name, + struct hash_algo **algop); + +/** + * hash_parse_string() - Parse hash string into a binary array + * + * The function parses a hash string into a binary array that + * can for example easily be used to compare to hash values. + * + * @algo_name: Hash algorithm to look up + * @str: Hash string to get parsed + * @result: Binary array of the parsed hash string + * + * @return 0 if ok, -EPROTONOSUPPORT for an unknown algorithm. + */ +int hash_parse_string(const char *algo_name, const char *str, uint8_t *result); + +#endif diff --git a/roms/u-boot/include/hda_codec.h b/roms/u-boot/include/hda_codec.h new file mode 100644 index 000000000..56de571f0 --- /dev/null +++ b/roms/u-boot/include/hda_codec.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel High-Definition Audio codec + * + * Copyright 2018 Google LLC + * + * Taken from coreboot file of the same name + */ + +#ifndef __HDA_CODEC_H_ +#define __HDA_CODEC_H_ + +struct hda_regs; + +/** + * struct hda_codec_priv - Private data required by the HDA codec + * + * @regs: HDA registers + * @beep_nid: Node ID of beep node (>0) + */ +struct hda_codec_priv { + struct hda_regs *regs; + uint beep_nid; +}; + +/** + * hda_wait_for_ready() - Wait for the codec to indicate it is ready + * + * @regs: HDA registers + * @return 0 if OK -ETIMEDOUT if codec did not respond in time + */ +int hda_wait_for_ready(struct hda_regs *regs); + +/** + * hda_wait_for_valid() - Wait for the codec to accept the last command + * + * @regs: HDA registers + * @return 0 if OK -ETIMEDOUT if codec did not respond in time + */ +int hda_wait_for_valid(struct hda_regs *regs); + +/** + * hda_codec_detect() - Detect which codecs are present + * + * @regs: HDA registers + * @return bit mask of active codecs (0 if none) + * @return 0 if OK, -ve on error + */ +int hda_codec_detect(struct hda_regs *regs); + +/** + * hda_codecs_init() - Init all codecs + * + * @dev: Sound device + * @regs: HDA registers + * @codec_mask: Mask of codecs to init (bits 3:0) + * @return 0 if OK, -ve on error + */ +int hda_codecs_init(struct udevice *dev, struct hda_regs *regs, u32 codec_mask); + +/** + * hda_codec_start_beep() - Start beeping + * + * This tells the sound hardware to start a beep. It will continue until stopped + * by sound_stop_beep(). + * + * @dev: Sound device + * @frequency_hz: Beep frequency in hertz + * @return if OK, -ve on error + */ +int hda_codec_start_beep(struct udevice *dev, int frequency_hz); + +/** + * hda_codec_stop_beep() - Stop beeping + * + * This tells the sound hardware to stop a previously started beep. + * + * @dev: Sound device + * @return if OK, -ve on error + */ +int hda_codec_stop_beep(struct udevice *dev); + +/** + * hda_codec_init() - Set up the HDA codec base address + * + * This should be called at the start of the probe() method. + * + * @dev: Sound device + * @return 0 if OK, -ve on error + */ +int hda_codec_init(struct udevice *dev); + +/** + * hda_codec_finish_init() - Finish setting up the HDA codec base address + * + * This should be called at the end of the probe() method. + * + * @dev: Sound device + * @return 0 if OK, -ve on error + */ +int hda_codec_finish_init(struct udevice *dev); + +#endif /* __HDA_CODEC_H_ */ diff --git a/roms/u-boot/include/hexdump.h b/roms/u-boot/include/hexdump.h new file mode 100644 index 000000000..f7b76ff71 --- /dev/null +++ b/roms/u-boot/include/hexdump.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Synopsys, Inc. All rights reserved. + * + */ + +#ifndef HEXDUMP_H +#define HEXDUMP_H + +#include +#include + +enum { + DUMP_PREFIX_NONE, + DUMP_PREFIX_ADDRESS, + DUMP_PREFIX_OFFSET +}; + +extern const char hex_asc[]; +#define hex_asc_lo(x) hex_asc[((x) & 0x0f)] +#define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4] + +static inline char *hex_byte_pack(char *buf, u8 byte) +{ + *buf++ = hex_asc_hi(byte); + *buf++ = hex_asc_lo(byte); + return buf; +} + +/** + * hex_to_bin - convert a hex digit to its real value + * @ch: ascii character represents hex digit + * + * hex_to_bin() converts one hex digit to its actual value or -1 in case of bad + * input. + */ +static inline int hex_to_bin(char ch) +{ + if ((ch >= '0') && (ch <= '9')) + return ch - '0'; + ch = tolower(ch); + if ((ch >= 'a') && (ch <= 'f')) + return ch - 'a' + 10; + return -1; +} + +/** + * hex2bin - convert an ascii hexadecimal string to its binary representation + * @dst: binary result + * @src: ascii hexadecimal string + * @count: result length + * + * Return 0 on success, -1 in case of bad input. + */ +static inline int hex2bin(u8 *dst, const char *src, size_t count) +{ + while (count--) { + int hi = hex_to_bin(*src++); + int lo = hex_to_bin(*src++); + + if ((hi < 0) || (lo < 0)) + return -1; + + *dst++ = (hi << 4) | lo; + } + return 0; +} + +/** + * bin2hex - convert binary data to an ascii hexadecimal string + * @dst: ascii hexadecimal result + * @src: binary data + * @count: binary data length + */ +static inline char *bin2hex(char *dst, const void *src, size_t count) +{ + const unsigned char *_src = src; + + while (count--) + dst = hex_byte_pack(dst, *_src++); + return dst; +} + +int hex_dump_to_buffer(const void *buf, size_t len, int rowsize, int groupsize, + char *linebuf, size_t linebuflen, bool ascii); +void print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, + int groupsize, const void *buf, size_t len, bool ascii); +void print_hex_dump_bytes(const char *prefix_str, int prefix_type, + const void *buf, size_t len); + +#endif /* HEXDUMP_H */ diff --git a/roms/u-boot/include/host_arch.h b/roms/u-boot/include/host_arch.h new file mode 100644 index 000000000..169d49451 --- /dev/null +++ b/roms/u-boot/include/host_arch.h @@ -0,0 +1,24 @@ +#if 0 +# SPDX SPDX-License-Identifier: GPL-2.0+ +# +# Constants defining the host architecture in assembler, C, and make files. +# The values are arbitrary. +# +# Copyright 2019 Heinrich Schuchardt +#endif + +#if 0 +export HOST_ARCH_AARCH64=0xaa64 +export HOST_ARCH_ARM=0x00a7 +export HOST_ARCH_RISCV32=0x5032 +export HOST_ARCH_RISCV64=0x5064 +export HOST_ARCH_X86=0x0386 +export HOST_ARCH_X86_64=0x8664 +#endif + +#define HOST_ARCH_AARCH64 0xaa64 +#define HOST_ARCH_ARM 0x00a7 +#define HOST_ARCH_RISCV32 0x5032 +#define HOST_ARCH_RISCV64 0x5064 +#define HOST_ARCH_X86 0x0386 +#define HOST_ARCH_X86_64 0x8664 diff --git a/roms/u-boot/include/hw_sha.h b/roms/u-boot/include/hw_sha.h new file mode 100644 index 000000000..d4f3471c4 --- /dev/null +++ b/roms/u-boot/include/hw_sha.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Header file for SHA hardware acceleration + * + * Copyright (c) 2012 Samsung Electronics + */ +#ifndef __HW_SHA_H +#define __HW_SHA_H +#include + +/** + * Computes hash value of input pbuf using h/w acceleration + * + * @param in_addr A pointer to the input buffer + * @param bufleni Byte length of input buffer + * @param out_addr A pointer to the output buffer. When complete + * 64 bytes are copied to pout[0]...pout[63]. Thus, a user + * should allocate at least 64 bytes at pOut in advance. + * @param chunk_size chunk size for sha512 + */ +void hw_sha512(const uchar *in_addr, uint buflen, uchar *out_addr, + uint chunk_size); + +/** + * Computes hash value of input pbuf using h/w acceleration + * + * @param in_addr A pointer to the input buffer + * @param bufleni Byte length of input buffer + * @param out_addr A pointer to the output buffer. When complete + * 48 bytes are copied to pout[0]...pout[47]. Thus, a user + * should allocate at least 48 bytes at pOut in advance. + * @param chunk_size chunk size for sha384 + */ +void hw_sha384(const uchar *in_addr, uint buflen, uchar *out_addr, + uint chunk_size); + +/** + * Computes hash value of input pbuf using h/w acceleration + * + * @param in_addr A pointer to the input buffer + * @param bufleni Byte length of input buffer + * @param out_addr A pointer to the output buffer. When complete + * 32 bytes are copied to pout[0]...pout[31]. Thus, a user + * should allocate at least 32 bytes at pOut in advance. + * @param chunk_size chunk size for sha256 + */ +void hw_sha256(const uchar *in_addr, uint buflen, uchar *out_addr, + uint chunk_size); + +/** + * Computes hash value of input pbuf using h/w acceleration + * + * @param in_addr A pointer to the input buffer + * @param bufleni Byte length of input buffer + * @param out_addr A pointer to the output buffer. When complete + * 32 bytes are copied to pout[0]...pout[31]. Thus, a user + * should allocate at least 32 bytes at pOut in advance. + * @param chunk_size chunk_size for sha1 + */ +void hw_sha1(const uchar *in_addr, uint buflen, uchar *out_addr, + uint chunk_size); + +/* + * Create the context for sha progressive hashing using h/w acceleration + * + * @algo: Pointer to the hash_algo struct + * @ctxp: Pointer to the pointer of the context for hashing + * @return 0 if ok, -ve on error + */ +int hw_sha_init(struct hash_algo *algo, void **ctxp); + +/* + * Update buffer for sha progressive hashing using h/w acceleration + * + * The context is freed by this function if an error occurs. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @buf: Pointer to the buffer being hashed + * @size: Size of the buffer being hashed + * @is_last: 1 if this is the last update; 0 otherwise + * @return 0 if ok, -ve on error + */ +int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf, + unsigned int size, int is_last); + +/* + * Copy sha hash result at destination location + * + * The context is freed after completion of hash operation or after an error. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @dest_buf: Pointer to the destination buffer where hash is to be copied + * @size: Size of the buffer being hashed + * @return 0 if ok, -ve on error + */ +int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, + int size); + +#endif diff --git a/roms/u-boot/include/hwconfig.h b/roms/u-boot/include/hwconfig.h new file mode 100644 index 000000000..cf4721075 --- /dev/null +++ b/roms/u-boot/include/hwconfig.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * An inteface for configuring a hardware via u-boot environment. + * + * Copyright (c) 2009 MontaVista Software, Inc. + * Copyright 2011 Freescale Semiconductor, Inc. + * + * Author: Anton Vorontsov + */ + +#ifndef _HWCONFIG_H +#define _HWCONFIG_H + +#include +#include + +#ifdef CONFIG_HWCONFIG + +extern int hwconfig_f(const char *opt, char *buf); +extern const char *hwconfig_arg_f(const char *opt, size_t *arglen, char *buf); +extern int hwconfig_arg_cmp_f(const char *opt, const char *arg, char *buf); +extern int hwconfig_sub_f(const char *opt, const char *subopt, char *buf); +extern const char *hwconfig_subarg_f(const char *opt, const char *subopt, + size_t *subarglen, char *buf); +extern int hwconfig_subarg_cmp_f(const char *opt, const char *subopt, + const char *subarg, char *buf); +#else + +static inline int hwconfig_f(const char *opt, char *buf) +{ + return -ENOSYS; +} + +static inline const char *hwconfig_arg_f(const char *opt, size_t *arglen, + char *buf) +{ + *arglen = 0; + return ""; +} + +static inline int hwconfig_arg_cmp_f(const char *opt, const char *arg, + char *buf) +{ + return -ENOSYS; +} + +static inline int hwconfig_sub_f(const char *opt, const char *subopt, char *buf) +{ + return -ENOSYS; +} + +static inline const char *hwconfig_subarg_f(const char *opt, const char *subopt, + size_t *subarglen, char *buf) +{ + *subarglen = 0; + return ""; +} + +static inline int hwconfig_subarg_cmp_f(const char *opt, const char *subopt, + const char *subarg, char *buf) +{ + return -ENOSYS; +} + +#endif /* CONFIG_HWCONFIG */ + +static inline int hwconfig(const char *opt) +{ + return hwconfig_f(opt, NULL); +} + +static inline const char *hwconfig_arg(const char *opt, size_t *arglen) +{ + return hwconfig_arg_f(opt, arglen, NULL); +} + +static inline int hwconfig_arg_cmp(const char *opt, const char *arg) +{ + return hwconfig_arg_cmp_f(opt, arg, NULL); +} + +static inline int hwconfig_sub(const char *opt, const char *subopt) +{ + return hwconfig_sub_f(opt, subopt, NULL); +} + +static inline const char *hwconfig_subarg(const char *opt, const char *subopt, + size_t *subarglen) +{ + return hwconfig_subarg_f(opt, subopt, subarglen, NULL); +} + +static inline int hwconfig_subarg_cmp(const char *opt, const char *subopt, + const char *subarg) +{ + return hwconfig_subarg_cmp_f(opt, subopt, subarg, NULL); +} + +#endif /* _HWCONFIG_H */ diff --git a/roms/u-boot/include/hwspinlock.h b/roms/u-boot/include/hwspinlock.h new file mode 100644 index 000000000..99389c13c --- /dev/null +++ b/roms/u-boot/include/hwspinlock.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#ifndef _HWSPINLOCK_H_ +#define _HWSPINLOCK_H_ + +/** + * Implement a hwspinlock uclass. + * Hardware spinlocks are used to perform hardware protection of + * critical sections and synchronisation between multiprocessors. + */ + +struct udevice; + +/** + * struct hwspinlock - A handle to (allowing control of) a single hardware + * spinlock. + * + * @dev: The device which implements the hardware spinlock. + * @id: The hardware spinlock ID within the provider. + */ +struct hwspinlock { + struct udevice *dev; + unsigned long id; +}; + +#if CONFIG_IS_ENABLED(DM_HWSPINLOCK) + +/** + * hwspinlock_get_by_index - Get a hardware spinlock by integer index + * + * This looks up and request a hardware spinlock. The index is relative to the + * client device; each device is assumed to have n hardware spinlock associated + * with it somehow, and this function finds and requests one of them. + * + * @dev: The client device. + * @index: The index of the hardware spinlock to request, within the + * client's list of hardware spinlock. + * @hws: A pointer to a hardware spinlock struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int hwspinlock_get_by_index(struct udevice *dev, + int index, struct hwspinlock *hws); + +/** + * Lock the hardware spinlock + * + * @hws: A hardware spinlock struct that previously requested by + * hwspinlock_get_by_index + * @timeout: Timeout value in msecs + * @return: 0 if OK, -ETIMEDOUT if timeout, -ve on other errors + */ +int hwspinlock_lock_timeout(struct hwspinlock *hws, unsigned int timeout); + +/** + * Unlock the hardware spinlock + * + * @hws: A hardware spinlock struct that previously requested by + * hwspinlock_get_by_index + * @return: 0 if OK, -ve on error + */ +int hwspinlock_unlock(struct hwspinlock *hws); + +#else + +static inline int hwspinlock_get_by_index(struct udevice *dev, + int index, + struct hwspinlock *hws) +{ + return -ENOSYS; +} + +static inline int hwspinlock_lock_timeout(struct hwspinlock *hws, + int timeout) +{ + return -ENOSYS; +} + +static inline int hwspinlock_unlock(struct hwspinlock *hws) +{ + return -ENOSYS; +} + +#endif /* CONFIG_DM_HWSPINLOCK */ + +struct ofnode_phandle_args; + +/** + * struct hwspinlock_ops - Driver model hwspinlock operations + * + * The uclass interface is implemented by all hwspinlock devices which use + * driver model. + */ +struct hwspinlock_ops { + /** + * of_xlate - Translate a client's device-tree (OF) hardware specifier. + * + * The hardware core calls this function as the first step in + * implementing a client's hwspinlock_get_by_*() call. + * + * @hws: The hardware spinlock struct to hold the translation + * result. + * @args: The hardware spinlock specifier values from device tree. + * @return 0 if OK, or a negative error code. + */ + int (*of_xlate)(struct hwspinlock *hws, + struct ofnode_phandle_args *args); + + /** + * Lock the hardware spinlock + * + * @dev: hwspinlock Device + * @index: index of the lock to be used + * @return 0 if OK, -ve on error + */ + int (*lock)(struct udevice *dev, int index); + + /** + * Unlock the hardware spinlock + * + * @dev: hwspinlock Device + * @index: index of the lock to be unlocked + * @return 0 if OK, -ve on error + */ + int (*unlock)(struct udevice *dev, int index); + + /** + * Relax - optional + * Platform-specific relax method, called by hwspinlock core + * while spinning on a lock, between two successive call to + * lock + * + * @dev: hwspinlock Device + */ + void (*relax)(struct udevice *dev); +}; + +#endif /* _HWSPINLOCK_H_ */ diff --git a/roms/u-boot/include/i2c.h b/roms/u-boot/include/i2c.h new file mode 100644 index 000000000..c0fe94c1f --- /dev/null +++ b/roms/u-boot/include/i2c.h @@ -0,0 +1,989 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2009 Sergey Kubushyn + * Copyright (C) 2009 - 2013 Heiko Schocher + * Changes for multibus/multiadapter I2C support. + * + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. + * + * The original I2C interface was + * (C) 2000 by Paolo Scaffardi (arsenio@tin.it) + * AIRVENT SAM s.p.a - RIMINI(ITALY) + * but has been changed substantially. + */ + +#ifndef _I2C_H_ +#define _I2C_H_ + +#include + +/* + * For now there are essentially two parts to this file - driver model + * here at the top, and the older code below (with CONFIG_SYS_I2C being + * most recent). The plan is to migrate everything to driver model. + * The driver model structures and API are separate as they are different + * enough as to be incompatible for compilation purposes. + */ + +enum dm_i2c_chip_flags { + DM_I2C_CHIP_10BIT = 1 << 0, /* Use 10-bit addressing */ + DM_I2C_CHIP_RD_ADDRESS = 1 << 1, /* Send address for each read byte */ + DM_I2C_CHIP_WR_ADDRESS = 1 << 2, /* Send address for each write byte */ +}; + +/** enum i2c_speed_mode - standard I2C speed modes */ +enum i2c_speed_mode { + IC_SPEED_MODE_STANDARD, + IC_SPEED_MODE_FAST, + IC_SPEED_MODE_FAST_PLUS, + IC_SPEED_MODE_HIGH, + IC_SPEED_MODE_FAST_ULTRA, + + IC_SPEED_MODE_COUNT, +}; + +/** enum i2c_speed_rate - standard I2C speeds in Hz */ +enum i2c_speed_rate { + I2C_SPEED_STANDARD_RATE = 100000, + I2C_SPEED_FAST_RATE = 400000, + I2C_SPEED_FAST_PLUS_RATE = 1000000, + I2C_SPEED_HIGH_RATE = 3400000, + I2C_SPEED_FAST_ULTRA_RATE = 5000000, +}; + +/** enum i2c_address_mode - available address modes */ +enum i2c_address_mode { + I2C_MODE_7_BIT, + I2C_MODE_10_BIT +}; + +/** enum i2c_device_t - Types of I2C devices, used for compatible strings */ +enum i2c_device_t { + I2C_DEVICE_GENERIC, + I2C_DEVICE_HID_OVER_I2C, +}; + +struct udevice; +/** + * struct dm_i2c_chip - information about an i2c chip + * + * An I2C chip is a device on the I2C bus. It sits at a particular address + * and normally supports 7-bit or 10-bit addressing. + * + * To obtain this structure, use dev_get_parent_plat(dev) where dev is + * the chip to examine. + * + * @chip_addr: Chip address on bus + * @offset_len: Length of offset in bytes. A single byte offset can + * represent up to 256 bytes. A value larger than 1 may be + * needed for larger devices. + * @flags: Flags for this chip (dm_i2c_chip_flags) + * @chip_addr_offset_mask: Mask of offset bits within chip_addr. Used for + * devices which steal addresses as part of offset. + * If offset_len is zero, then the offset is encoded + * completely within the chip address itself. + * e.g. a devce with chip address of 0x2c with 512 + * registers might use the bottom bit of the address + * to indicate which half of the address space is being + * accessed while still only using 1 byte offset. + * This means it will respond to chip address 0x2c and + * 0x2d. + * A real world example is the Atmel AT24C04. It's + * datasheet explains it's usage of this addressing + * mode. + * @emul: Emulator for this chip address (only used for emulation) + * @emul_idx: Emulator index, used for of-platdata and set by each i2c chip's + * bind() method. This allows i2c_emul_find() to work with of-platdata. + */ +struct dm_i2c_chip { + uint chip_addr; + uint offset_len; + uint flags; + uint chip_addr_offset_mask; +#ifdef CONFIG_SANDBOX + struct udevice *emul; + bool test_mode; + int emul_idx; +#endif +}; + +/** + * struct dm_i2c_bus- information about an i2c bus + * + * An I2C bus contains 0 or more chips on it, each at its own address. The + * bus can operate at different speeds (measured in Hz, typically 100KHz + * or 400KHz). + * + * To obtain this structure, use dev_get_uclass_priv(bus) where bus is the + * I2C bus udevice. + * + * @speed_hz: Bus speed in hertz (typically 100000) + * @max_transaction_bytes: Maximal size of single I2C transfer + */ +struct dm_i2c_bus { + int speed_hz; + int max_transaction_bytes; +}; + +/* + * Not all of these flags are implemented in the U-Boot API + */ +enum dm_i2c_msg_flags { + I2C_M_TEN = 0x0010, /* ten-bit chip address */ + I2C_M_RD = 0x0001, /* read data, from slave to master */ + I2C_M_STOP = 0x8000, /* send stop after this message */ + I2C_M_NOSTART = 0x4000, /* no start before this message */ + I2C_M_REV_DIR_ADDR = 0x2000, /* invert polarity of R/W bit */ + I2C_M_IGNORE_NAK = 0x1000, /* continue after NAK */ + I2C_M_NO_RD_ACK = 0x0800, /* skip the Ack bit on reads */ + I2C_M_RECV_LEN = 0x0400, /* length is first received byte */ +}; + +/** + * struct i2c_msg - an I2C message + * + * @addr: Slave address + * @flags: Flags (see enum dm_i2c_msg_flags) + * @len: Length of buffer in bytes, may be 0 for a probe + * @buf: Buffer to send/receive, or NULL if no data + */ +struct i2c_msg { + uint addr; + uint flags; + uint len; + u8 *buf; +}; + +/** + * struct i2c_msg_list - a list of I2C messages + * + * This is called i2c_rdwr_ioctl_data in Linux but the name does not seem + * appropriate in U-Boot. + * + * @msg: Pointer to i2c_msg array + * @nmsgs: Number of elements in the array + */ +struct i2c_msg_list { + struct i2c_msg *msgs; + uint nmsgs; +}; + +/** + * dm_i2c_read() - read bytes from an I2C chip + * + * To obtain an I2C device (called a 'chip') given the I2C bus address you + * can use i2c_get_chip(). To obtain a bus by bus number use + * uclass_get_device_by_seq(UCLASS_I2C, ). + * + * To set the address length of a devce use i2c_set_addr_len(). It + * defaults to 1. + * + * @dev: Chip to read from + * @offset: Offset within chip to start reading + * @buffer: Place to put data + * @len: Number of bytes to read + * + * @return 0 on success, -ve on failure + */ +int dm_i2c_read(struct udevice *dev, uint offset, uint8_t *buffer, int len); + +/** + * dm_i2c_write() - write bytes to an I2C chip + * + * See notes for dm_i2c_read() above. + * + * @dev: Chip to write to + * @offset: Offset within chip to start writing + * @buffer: Buffer containing data to write + * @len: Number of bytes to write + * + * @return 0 on success, -ve on failure + */ +int dm_i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer, + int len); + +/** + * dm_i2c_probe() - probe a particular chip address + * + * This can be useful to check for the existence of a chip on the bus. + * It is typically implemented by writing the chip address to the bus + * and checking that the chip replies with an ACK. + * + * @bus: Bus to probe + * @chip_addr: 7-bit address to probe (10-bit and others are not supported) + * @chip_flags: Flags for the probe (see enum dm_i2c_chip_flags) + * @devp: Returns the device found, or NULL if none + * @return 0 if a chip was found at that address, -ve if not + */ +int dm_i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags, + struct udevice **devp); + +/** + * dm_i2c_reg_read() - Read a value from an I2C register + * + * This reads a single value from the given address in an I2C chip + * + * @dev: Device to use for transfer + * @addr: Address to read from + * @return value read, or -ve on error + */ +int dm_i2c_reg_read(struct udevice *dev, uint offset); + +/** + * dm_i2c_reg_write() - Write a value to an I2C register + * + * This writes a single value to the given address in an I2C chip + * + * @dev: Device to use for transfer + * @addr: Address to write to + * @val: Value to write (normally a byte) + * @return 0 on success, -ve on error + */ +int dm_i2c_reg_write(struct udevice *dev, uint offset, unsigned int val); + +/** + * dm_i2c_xfer() - Transfer messages over I2C + * + * This transfers a raw message. It is best to use dm_i2c_reg_read/write() + * instead. + * + * @dev: Device to use for transfer + * @msg: List of messages to transfer + * @nmsgs: Number of messages to transfer + * @return 0 on success, -ve on error + */ +int dm_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs); + +/** + * dm_i2c_set_bus_speed() - set the speed of a bus + * + * @bus: Bus to adjust + * @speed: Requested speed in Hz + * @return 0 if OK, -EINVAL for invalid values + */ +int dm_i2c_set_bus_speed(struct udevice *bus, unsigned int speed); + +/** + * dm_i2c_get_bus_speed() - get the speed of a bus + * + * @bus: Bus to check + * @return speed of selected I2C bus in Hz, -ve on error + */ +int dm_i2c_get_bus_speed(struct udevice *bus); + +/** + * i2c_set_chip_flags() - set flags for a chip + * + * Typically addresses are 7 bits, but for 10-bit addresses you should set + * flags to DM_I2C_CHIP_10BIT. All accesses will then use 10-bit addressing. + * + * @dev: Chip to adjust + * @flags: New flags + * @return 0 if OK, -EINVAL if value is unsupported, other -ve value on error + */ +int i2c_set_chip_flags(struct udevice *dev, uint flags); + +/** + * i2c_get_chip_flags() - get flags for a chip + * + * @dev: Chip to check + * @flagsp: Place to put flags + * @return 0 if OK, other -ve value on error + */ +int i2c_get_chip_flags(struct udevice *dev, uint *flagsp); + +/** + * i2c_set_offset_len() - set the offset length for a chip + * + * The offset used to access a chip may be up to 4 bytes long. Typically it + * is only 1 byte, which is enough for chips with 256 bytes of memory or + * registers. The default value is 1, but you can call this function to + * change it. + * + * @offset_len: New offset length value (typically 1 or 2) + */ +int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len); + +/** + * i2c_get_offset_len() - get the offset length for a chip + * + * @return: Current offset length value (typically 1 or 2) + */ +int i2c_get_chip_offset_len(struct udevice *dev); + +/** + * i2c_set_chip_addr_offset_mask() - set mask of address bits usable by offset + * + * Some devices listen on multiple chip addresses to achieve larger offsets + * than their single or multiple byte offsets would allow for. You can use this + * function to set the bits that are valid to be used for offset overflow. + * + * @mask: The mask to be used for high offset bits within address + * @return 0 if OK, other -ve value on error + */ +int i2c_set_chip_addr_offset_mask(struct udevice *dev, uint mask); + +/* + * i2c_get_chip_addr_offset_mask() - get mask of address bits usable by offset + * + * @return current chip addr offset mask + */ +uint i2c_get_chip_addr_offset_mask(struct udevice *dev); + +/** + * i2c_deblock() - recover a bus that is in an unknown state + * + * See the deblock() method in 'struct dm_i2c_ops' for full information + * + * @bus: Bus to recover + * @return 0 if OK, -ve on error + */ +int i2c_deblock(struct udevice *bus); + +/** + * i2c_deblock_gpio_loop() - recover a bus from an unknown state by toggling SDA/SCL + * + * This is the inner logic used for toggling I2C SDA/SCL lines as GPIOs + * for deblocking the I2C bus. + * + * @sda_pin: SDA GPIO + * @scl_pin: SCL GPIO + * @scl_count: Number of SCL clock cycles generated to deblock SDA + * @start_count:Number of I2C start conditions sent after deblocking SDA + * @delay: Delay between SCL clock line changes + * @return 0 if OK, -ve on error + */ +struct gpio_desc; +int i2c_deblock_gpio_loop(struct gpio_desc *sda_pin, struct gpio_desc *scl_pin, + unsigned int scl_count, unsigned int start_count, + unsigned int delay); + +/** + * struct dm_i2c_ops - driver operations for I2C uclass + * + * Drivers should support these operations unless otherwise noted. These + * operations are intended to be used by uclass code, not directly from + * other code. + */ +struct dm_i2c_ops { + /** + * xfer() - transfer a list of I2C messages + * + * @bus: Bus to read from + * @msg: List of messages to transfer + * @nmsgs: Number of messages in the list + * @return 0 if OK, -EREMOTEIO if the slave did not ACK a byte, + * -ECOMM if the speed cannot be supported, -EPROTO if the chip + * flags cannot be supported, other -ve value on some other error + */ + int (*xfer)(struct udevice *bus, struct i2c_msg *msg, int nmsgs); + + /** + * probe_chip() - probe for the presense of a chip address + * + * This function is optional. If omitted, the uclass will send a zero + * length message instead. + * + * @bus: Bus to probe + * @chip_addr: Chip address to probe + * @chip_flags: Probe flags (enum dm_i2c_chip_flags) + * @return 0 if chip was found, -EREMOTEIO if not, -ENOSYS to fall back + * to default probem other -ve value on error + */ + int (*probe_chip)(struct udevice *bus, uint chip_addr, uint chip_flags); + + /** + * set_bus_speed() - set the speed of a bus (optional) + * + * The bus speed value will be updated by the uclass if this function + * does not return an error. This method is optional - if it is not + * provided then the driver can read the speed from + * dev_get_uclass_priv(bus)->speed_hz + * + * @bus: Bus to adjust + * @speed: Requested speed in Hz + * @return 0 if OK, -EINVAL for invalid values + */ + int (*set_bus_speed)(struct udevice *bus, unsigned int speed); + + /** + * get_bus_speed() - get the speed of a bus (optional) + * + * Normally this can be provided by the uclass, but if you want your + * driver to check the bus speed by looking at the hardware, you can + * implement that here. This method is optional. This method would + * normally be expected to return dev_get_uclass_priv(bus)->speed_hz. + * + * @bus: Bus to check + * @return speed of selected I2C bus in Hz, -ve on error + */ + int (*get_bus_speed)(struct udevice *bus); + + /** + * set_flags() - set the flags for a chip (optional) + * + * This is generally implemented by the uclass, but drivers can + * check the value to ensure that unsupported options are not used. + * This method is optional. If provided, this method will always be + * called when the flags change. + * + * @dev: Chip to adjust + * @flags: New flags value + * @return 0 if OK, -EINVAL if value is unsupported + */ + int (*set_flags)(struct udevice *dev, uint flags); + + /** + * deblock() - recover a bus that is in an unknown state + * + * I2C is a synchronous protocol and resets of the processor in the + * middle of an access can block the I2C Bus until a powerdown of + * the full unit is done. This is because slaves can be stuck + * waiting for addition bus transitions for a transaction that will + * never complete. Resetting the I2C master does not help. The only + * way is to force the bus through a series of transitions to make + * sure that all slaves are done with the transaction. This method + * performs this 'deblocking' if support by the driver. + * + * This method is optional. + */ + int (*deblock)(struct udevice *bus); +}; + +#define i2c_get_ops(dev) ((struct dm_i2c_ops *)(dev)->driver->ops) + +/** + * struct i2c_mux_ops - operations for an I2C mux + * + * The current mux state is expected to be stored in the mux itself since + * it is the only thing that knows how to make things work. The mux can + * record the current state and then avoid switching unless it is necessary. + * So select() can be skipped if the mux is already in the correct state. + * Also deselect() can be made a nop if required. + */ +struct i2c_mux_ops { + /** + * select() - select one of of I2C buses attached to a mux + * + * This will be called when there is no bus currently selected by the + * mux. This method does not need to deselect the old bus since + * deselect() will be already have been called if necessary. + * + * @mux: Mux device + * @bus: I2C bus to select + * @channel: Channel number correponding to the bus to select + * @return 0 if OK, -ve on error + */ + int (*select)(struct udevice *mux, struct udevice *bus, uint channel); + + /** + * deselect() - select one of of I2C buses attached to a mux + * + * This is used to deselect the currently selected I2C bus. + * + * @mux: Mux device + * @bus: I2C bus to deselect + * @channel: Channel number correponding to the bus to deselect + * @return 0 if OK, -ve on error + */ + int (*deselect)(struct udevice *mux, struct udevice *bus, uint channel); +}; + +#define i2c_mux_get_ops(dev) ((struct i2c_mux_ops *)(dev)->driver->ops) + +/** + * i2c_get_chip() - get a device to use to access a chip on a bus + * + * This returns the device for the given chip address. The device can then + * be used with calls to i2c_read(), i2c_write(), i2c_probe(), etc. + * + * @bus: Bus to examine + * @chip_addr: Chip address for the new device + * @offset_len: Length of a register offset in bytes (normally 1) + * @devp: Returns pointer to new device if found or -ENODEV if not + * found + */ +int i2c_get_chip(struct udevice *bus, uint chip_addr, uint offset_len, + struct udevice **devp); + +/** + * i2c_get_chip_for_busnum() - get a device to use to access a chip on + * a bus number + * + * This returns the device for the given chip address on a particular bus + * number. + * + * @busnum: Bus number to examine + * @chip_addr: Chip address for the new device + * @offset_len: Length of a register offset in bytes (normally 1) + * @devp: Returns pointer to new device if found or -ENODEV if not + * found + */ +int i2c_get_chip_for_busnum(int busnum, int chip_addr, uint offset_len, + struct udevice **devp); + +/** + * i2c_chip_of_to_plat() - Decode standard I2C platform data + * + * This decodes the chip address from a device tree node and puts it into + * its dm_i2c_chip structure. This should be called in your driver's + * of_to_plat() method. + * + * @blob: Device tree blob + * @node: Node offset to read from + * @spi: Place to put the decoded information + */ +int i2c_chip_of_to_plat(struct udevice *dev, struct dm_i2c_chip *chip); + +/** + * i2c_dump_msgs() - Dump a list of I2C messages + * + * This may be useful for debugging. + * + * @msg: Message list to dump + * @nmsgs: Number of messages + */ +void i2c_dump_msgs(struct i2c_msg *msg, int nmsgs); + +/** + * i2c_emul_find() - Find an emulator for an i2c sandbox device + * + * This looks at the device's 'emul' phandle + * + * @dev: Device to find an emulator for + * @emulp: Returns the associated emulator, if found * + * @return 0 if OK, -ENOENT or -ENODEV if not found + */ +int i2c_emul_find(struct udevice *dev, struct udevice **emulp); + +/** + * i2c_emul_set_idx() - Set the emulator index for an i2c sandbox device + * + * With of-platdata we cannot find the emulator using the device tree, so rely + * on the bind() method of each i2c driver calling this function to tell us + * the of-platdata idx of the emulator + * + * @dev: i2c device to set the emulator for + * @emul_idx: of-platdata index for that emulator + */ +void i2c_emul_set_idx(struct udevice *dev, int emul_idx); + +/** + * i2c_emul_get_device() - Find the device being emulated + * + * Given an emulator this returns the associated device + * + * @emul: Emulator for the device + * @return device that @emul is emulating + */ +struct udevice *i2c_emul_get_device(struct udevice *emul); + +/* ACPI operations for generic I2C devices */ +extern struct acpi_ops i2c_acpi_ops; + +/** + * acpi_i2c_of_to_plat() - Read properties intended for ACPI + * + * This reads the generic I2C properties from the device tree, so that these + * can be used to create ACPI information for the device. + * + * See the i2c/generic-acpi.txt binding file for information about the + * properties. + * + * @dev: I2C device to process + * @return 0 if OK, -EINVAL if acpi,hid is not present + */ +int acpi_i2c_of_to_plat(struct udevice *dev); + +#if !CONFIG_IS_ENABLED(DM_I2C) + +/* + * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING + * + * The implementation MUST NOT use static or global variables if the + * I2C routines are used to read SDRAM configuration information + * because this is done before the memories are initialized. Limited + * use of stack-based variables are OK (the initial stack size is + * limited). + * + * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING + */ + +/* + * Configuration items. + */ +#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ + +#if !defined(CONFIG_SYS_I2C_MAX_HOPS) +/* no muxes used bus = i2c adapters */ +#define CONFIG_SYS_I2C_DIRECT_BUS 1 +#define CONFIG_SYS_I2C_MAX_HOPS 0 +#define CONFIG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) +#else +/* we use i2c muxes */ +#undef CONFIG_SYS_I2C_DIRECT_BUS +#endif + +/* define the I2C bus number for RTC and DTT if not already done */ +#if !defined(CONFIG_SYS_RTC_BUS_NUM) +#define CONFIG_SYS_RTC_BUS_NUM 0 +#endif +#if !defined(CONFIG_SYS_SPD_BUS_NUM) +#define CONFIG_SYS_SPD_BUS_NUM 0 +#endif + +struct i2c_adapter { + void (*init)(struct i2c_adapter *adap, int speed, + int slaveaddr); + int (*probe)(struct i2c_adapter *adap, uint8_t chip); + int (*read)(struct i2c_adapter *adap, uint8_t chip, + uint addr, int alen, uint8_t *buffer, + int len); + int (*write)(struct i2c_adapter *adap, uint8_t chip, + uint addr, int alen, uint8_t *buffer, + int len); + uint (*set_bus_speed)(struct i2c_adapter *adap, + uint speed); + int speed; + int waitdelay; + int slaveaddr; + int init_done; + int hwadapnr; + char *name; +}; + +#define U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \ + _set_speed, _speed, _slaveaddr, _hwadapnr, _name) \ + { \ + .init = _init, \ + .probe = _probe, \ + .read = _read, \ + .write = _write, \ + .set_bus_speed = _set_speed, \ + .speed = _speed, \ + .slaveaddr = _slaveaddr, \ + .init_done = 0, \ + .hwadapnr = _hwadapnr, \ + .name = #_name \ +}; + +#define U_BOOT_I2C_ADAP_COMPLETE(_name, _init, _probe, _read, _write, \ + _set_speed, _speed, _slaveaddr, _hwadapnr) \ + ll_entry_declare(struct i2c_adapter, _name, i2c) = \ + U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \ + _set_speed, _speed, _slaveaddr, _hwadapnr, _name); + +struct i2c_adapter *i2c_get_adapter(int index); + +#ifndef CONFIG_SYS_I2C_DIRECT_BUS +struct i2c_mux { + int id; + char name[16]; +}; + +struct i2c_next_hop { + struct i2c_mux mux; + uint8_t chip; + uint8_t channel; +}; + +struct i2c_bus_hose { + int adapter; + struct i2c_next_hop next_hop[CONFIG_SYS_I2C_MAX_HOPS]; +}; +#define I2C_NULL_HOP {{-1, ""}, 0, 0} +extern struct i2c_bus_hose i2c_bus[]; + +#define I2C_ADAPTER(bus) i2c_bus[bus].adapter +#else +#define I2C_ADAPTER(bus) bus +#endif +#define I2C_BUS gd->cur_i2c_bus + +#define I2C_ADAP_NR(bus) i2c_get_adapter(I2C_ADAPTER(bus)) +#define I2C_ADAP I2C_ADAP_NR(gd->cur_i2c_bus) +#define I2C_ADAP_HWNR (I2C_ADAP->hwadapnr) + +#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#define I2C_MUX_PCA9540_ID 1 +#define I2C_MUX_PCA9540 {I2C_MUX_PCA9540_ID, "PCA9540B"} +#define I2C_MUX_PCA9542_ID 2 +#define I2C_MUX_PCA9542 {I2C_MUX_PCA9542_ID, "PCA9542A"} +#define I2C_MUX_PCA9544_ID 3 +#define I2C_MUX_PCA9544 {I2C_MUX_PCA9544_ID, "PCA9544A"} +#define I2C_MUX_PCA9547_ID 4 +#define I2C_MUX_PCA9547 {I2C_MUX_PCA9547_ID, "PCA9547A"} +#define I2C_MUX_PCA9548_ID 5 +#define I2C_MUX_PCA9548 {I2C_MUX_PCA9548_ID, "PCA9548"} +#endif + +#ifndef I2C_SOFT_DECLARATIONS +# if (defined(CONFIG_AT91RM9200) || \ + defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ + defined(CONFIG_AT91SAM9263)) +# define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; +# else +# define I2C_SOFT_DECLARATIONS +# endif +#endif + +/* + * Many boards/controllers/drivers don't support an I2C slave interface so + * provide a default slave address for them for use in common code. A real + * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does + * support a slave interface. + */ +#ifndef CONFIG_SYS_I2C_SLAVE +#define CONFIG_SYS_I2C_SLAVE 0xfe +#endif + +/* + * Initialization, must be called once on start up, may be called + * repeatedly to change the speed and slave addresses. + */ +#ifdef CONFIG_SYS_I2C_EARLY_INIT +void i2c_early_init_f(void); +#endif +void i2c_init(int speed, int slaveaddr); +void i2c_init_board(void); + +#ifdef CONFIG_SYS_I2C +/* + * i2c_get_bus_num: + * + * Returns index of currently active I2C bus. Zero-based. + */ +unsigned int i2c_get_bus_num(void); + +/* + * i2c_set_bus_num: + * + * Change the active I2C bus. Subsequent read/write calls will + * go to this one. + * + * bus - bus index, zero based + * + * Returns: 0 on success, not 0 on failure + * + */ +int i2c_set_bus_num(unsigned int bus); + +/* + * i2c_init_all(): + * + * Initializes all I2C adapters in the system. All i2c_adap structures must + * be initialized beforehead with function pointers and data, including + * speed and slaveaddr. Returns 0 on success, non-0 on failure. + */ +void i2c_init_all(void); + +/* + * Probe the given I2C chip address. Returns 0 if a chip responded, + * not 0 on failure. + */ +int i2c_probe(uint8_t chip); + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int i2c_read(uint8_t chip, unsigned int addr, int alen, + uint8_t *buffer, int len); + +int i2c_write(uint8_t chip, unsigned int addr, int alen, + uint8_t *buffer, int len); + +/* + * Utility routines to read/write registers. + */ +uint8_t i2c_reg_read(uint8_t addr, uint8_t reg); + +void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val); + +/* + * i2c_set_bus_speed: + * + * Change the speed of the active I2C bus + * + * speed - bus speed in Hz + * + * Returns: new bus speed + * + */ +unsigned int i2c_set_bus_speed(unsigned int speed); + +/* + * i2c_get_bus_speed: + * + * Returns speed of currently active I2C bus in Hz + */ + +unsigned int i2c_get_bus_speed(void); + +#else + +/* + * Probe the given I2C chip address. Returns 0 if a chip responded, + * not 0 on failure. + */ +int i2c_probe(uchar chip); + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); + +/* + * Utility routines to read/write registers. + */ +static inline u8 i2c_reg_read(u8 addr, u8 reg) +{ + u8 buf; + +#ifdef DEBUG + printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg); +#endif + + i2c_read(addr, reg, 1, &buf, 1); + + return buf; +} + +static inline void i2c_reg_write(u8 addr, u8 reg, u8 val) +{ +#ifdef DEBUG + printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n", + __func__, addr, reg, val); +#endif + + i2c_write(addr, reg, 1, &val, 1); +} + +/* + * Functions for setting the current I2C bus and its speed + */ + +/* + * i2c_set_bus_num: + * + * Change the active I2C bus. Subsequent read/write calls will + * go to this one. + * + * bus - bus index, zero based + * + * Returns: 0 on success, not 0 on failure + * + */ +int i2c_set_bus_num(unsigned int bus); + +/* + * i2c_get_bus_num: + * + * Returns index of currently active I2C bus. Zero-based. + */ + +unsigned int i2c_get_bus_num(void); + +/* + * i2c_set_bus_speed: + * + * Change the speed of the active I2C bus + * + * speed - bus speed in Hz + * + * Returns: 0 on success, not 0 on failure + * + */ +int i2c_set_bus_speed(unsigned int); + +/* + * i2c_get_bus_speed: + * + * Returns speed of currently active I2C bus in Hz + */ + +unsigned int i2c_get_bus_speed(void); +#endif /* CONFIG_SYS_I2C */ + +/* + * only for backwardcompatibility, should go away if we switched + * completely to new multibus support. + */ +#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS) +# if !defined(CONFIG_SYS_MAX_I2C_BUS) +# define CONFIG_SYS_MAX_I2C_BUS 2 +# endif +# define I2C_MULTI_BUS 1 +#else +# define CONFIG_SYS_MAX_I2C_BUS 1 +# define I2C_MULTI_BUS 0 +#endif + +/* NOTE: These two functions MUST be always_inline to avoid code growth! */ +static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline)); +static inline unsigned int I2C_GET_BUS(void) +{ + return I2C_MULTI_BUS ? i2c_get_bus_num() : 0; +} + +static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline)); +static inline void I2C_SET_BUS(unsigned int bus) +{ + if (I2C_MULTI_BUS) + i2c_set_bus_num(bus); +} + +/* Multi I2C definitions */ +enum { + I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7, + I2C_8, I2C_9, I2C_10, +}; + +/** + * Get FDT values for i2c bus. + * + * @param blob Device tree blbo + * @return the number of I2C bus + */ +void board_i2c_init(const void *blob); + +/** + * Find the I2C bus number by given a FDT I2C node. + * + * @param blob Device tree blbo + * @param node FDT I2C node to find + * @return the number of I2C bus (zero based), or -1 on error + */ +int i2c_get_bus_num_fdt(int node); + +/** + * Reset the I2C bus represented by the given a FDT I2C node. + * + * @param blob Device tree blbo + * @param node FDT I2C node to find + * @return 0 if port was reset, -1 if not found + */ +int i2c_reset_port_fdt(const void *blob, int node); + +#endif /* !CONFIG_DM_I2C */ + +#endif /* _I2C_H_ */ diff --git a/roms/u-boot/include/i2c_eeprom.h b/roms/u-boot/include/i2c_eeprom.h new file mode 100644 index 000000000..cd620d519 --- /dev/null +++ b/roms/u-boot/include/i2c_eeprom.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2014 Google, Inc + */ + +#ifndef __I2C_EEPROM +#define __I2C_EEPROM + +struct i2c_eeprom_ops { + int (*read)(struct udevice *dev, int offset, uint8_t *buf, int size); + int (*write)(struct udevice *dev, int offset, const uint8_t *buf, + int size); + int (*size)(struct udevice *dev); +}; + +struct i2c_eeprom { + /* The EEPROM's page size in byte */ + unsigned long pagesize; + /* The EEPROM's capacity in bytes */ + unsigned long size; +}; + +/* + * i2c_eeprom_read() - read bytes from an I2C EEPROM chip + * + * @dev: Chip to read from + * @offset: Offset within chip to start reading + * @buf: Place to put data + * @size: Number of bytes to read + * + * @return 0 on success, -ve on failure + */ +int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf, int size); + +/* + * i2c_eeprom_write() - write bytes to an I2C EEPROM chip + * + * @dev: Chip to write to + * @offset: Offset within chip to start writing + * @buf: Buffer containing data to write + * @size: Number of bytes to write + * + * @return 0 on success, -ve on failure + */ +int i2c_eeprom_write(struct udevice *dev, int offset, uint8_t *buf, int size); + +/* + * i2c_eeprom_size() - get size of I2C EEPROM chip + * + * @dev: Chip to query + * + * @return +ve size in bytes on success, -ve on failure + */ +int i2c_eeprom_size(struct udevice *dev); + +#endif diff --git a/roms/u-boot/include/i2s.h b/roms/u-boot/include/i2s.h new file mode 100644 index 000000000..7760aab7c --- /dev/null +++ b/roms/u-boot/include/i2s.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Samsung Electronics + * R. Chandrasekar + */ + +#ifndef __I2S_H__ +#define __I2S_H__ + +/* + * DAI hardware audio formats. + * + * Describes the physical PCM data formating and clocking. Add new formats + * to the end. + */ +#define SND_SOC_DAIFMT_I2S 1 /* I2S mode */ +#define SND_SOC_DAIFMT_RIGHT_J 2 /* Right Justified mode */ +#define SND_SOC_DAIFMT_LEFT_J 3 /* Left Justified mode */ +#define SND_SOC_DAIFMT_DSP_A 4 /* L data MSB after FRM LRC */ +#define SND_SOC_DAIFMT_DSP_B 5 /* L data MSB during FRM LRC */ +#define SND_SOC_DAIFMT_AC97 6 /* AC97 */ +#define SND_SOC_DAIFMT_PDM 7 /* Pulse density modulation */ + +/* left and right justified also known as MSB and LSB respectively */ +#define SND_SOC_DAIFMT_MSB SND_SOC_DAIFMT_LEFT_J +#define SND_SOC_DAIFMT_LSB SND_SOC_DAIFMT_RIGHT_J + +/* + * DAI hardware signal inversions. + * + * Specifies whether the DAI can also support inverted clocks for the specified + * format. + */ +#define SND_SOC_DAIFMT_NB_NF (1 << 8) /* normal bit clock + frame */ +#define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */ +#define SND_SOC_DAIFMT_IB_NF (3 << 8) /* invert BCLK + nor FRM */ +#define SND_SOC_DAIFMT_IB_IF (4 << 8) /* invert BCLK + FRM */ + +/* + * DAI hardware clock masters. + * + * This is wrt the codec, the inverse is true for the interface + * i.e. if the codec is clk and FRM master then the interface is + * clk and frame slave. + */ +#define SND_SOC_DAIFMT_CBM_CFM (1 << 12) /* codec clk & FRM master */ +#define SND_SOC_DAIFMT_CBS_CFM (2 << 12) /* codec clk slave & FRM master */ +#define SND_SOC_DAIFMT_CBM_CFS (3 << 12) /* codec clk master & frame slave */ +#define SND_SOC_DAIFMT_CBS_CFS (4 << 12) /* codec clk & FRM slave */ + +#define SND_SOC_DAIFMT_FORMAT_MASK 0x000f +#define SND_SOC_DAIFMT_CLOCK_MASK 0x00f0 +#define SND_SOC_DAIFMT_INV_MASK 0x0f00 +#define SND_SOC_DAIFMT_MASTER_MASK 0xf000 + +/* + * Master Clock Directions + */ +#define SND_SOC_CLOCK_IN 0 +#define SND_SOC_CLOCK_OUT 1 + +/* I2S Tx Control */ +#define I2S_TX_ON 1 +#define I2S_TX_OFF 0 + +#define FIFO_LENGTH 64 + +/* I2s Registers */ +struct i2s_reg { + unsigned int con; /* base + 0 , Control register */ + unsigned int mod; /* Mode register */ + unsigned int fic; /* FIFO control register */ + unsigned int psr; /* Reserved */ + unsigned int txd; /* Transmit data register */ + unsigned int rxd; /* Receive Data Register */ +}; + +/* This structure stores the i2s related information */ +struct i2s_uc_priv { + unsigned int rfs; /* LR clock frame size */ + unsigned int bfs; /* Bit clock frame size */ + unsigned int audio_pll_clk; /* Audio pll frequency in Hz */ + unsigned int samplingrate; /* sampling rate */ + unsigned int bitspersample; /* bits per sample */ + unsigned int channels; /* audio channels */ + unsigned int base_address; /* I2S Register Base */ + unsigned int id; /* I2S controller id */ +}; + +/* Operations for i2s devices */ +struct i2s_ops { + /** + * tx_data() - Transmit audio data + * + * @dev: I2C device + * @data: Data buffer to play + * @data_size: Size of data buffer in bytes + * @return 0 if OK, -ve on error + */ + int (*tx_data)(struct udevice *dev, void *data, uint data_size); +}; + +#define i2s_get_ops(dev) ((struct i2s_ops *)(dev)->driver->ops) + +/** + * i2s_tx_data() - Transmit audio data + * + * @dev: I2C device + * @data: Data buffer to play + * @data_size: Size of data buffer in bytes + * @return 0 if OK, -ve on error + */ +int i2s_tx_data(struct udevice *dev, void *data, uint data_size); + +/* + * Sends the given data through i2s tx + * + * @param pi2s_tx pointer of i2s transmitter parameter structure. + * @param data address of the data buffer + * @param data_size size of the data (in bytes) + * @return int value 0 for success, -1 in case of error + */ +int i2s_transfer_tx_data(struct i2s_uc_priv *pi2s_tx, void *data, + uint data_size); + +#endif /* __I2S_H__ */ diff --git a/roms/u-boot/include/i8042.h b/roms/u-boot/include/i8042.h new file mode 100644 index 000000000..8d69fa13b --- /dev/null +++ b/roms/u-boot/include/i8042.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + */ + +/* i8042.h - Intel 8042 keyboard driver header */ + +#ifndef _I8042_H_ +#define _I8042_H_ + +/* defines */ + +#define I8042_DATA_REG 0x60 /* keyboard i/o buffer */ +#define I8042_STS_REG 0x64 /* keyboard status read */ +#define I8042_CMD_REG 0x64 /* keyboard ctrl write */ + +/* Status register bit defines */ +#define STATUS_OBF (1 << 0) +#define STATUS_IBF (1 << 1) + +/* Configuration byte bit defines */ +#define CONFIG_KIRQ_EN (1 << 0) +#define CONFIG_MIRQ_EN (1 << 1) +#define CONFIG_SET_BIST (1 << 2) +#define CONFIG_KCLK_DIS (1 << 4) +#define CONFIG_MCLK_DIS (1 << 5) +#define CONFIG_AT_TRANS (1 << 6) + +/* i8042 commands */ +#define CMD_RD_CONFIG 0x20 /* read configuration byte */ +#define CMD_WR_CONFIG 0x60 /* write configuration byte */ +#define CMD_SELF_TEST 0xaa /* controller self-test */ +#define CMD_KBD_DIS 0xad /* keyboard disable */ +#define CMD_KBD_EN 0xae /* keyboard enable */ +#define CMD_SET_KBD_LED 0xed /* set keyboard led */ +#define CMD_DRAIN_OUTPUT 0xf4 /* drain output buffer */ +#define CMD_RESET_KBD 0xff /* reset keyboard */ + +/* i8042 command result */ +#define KBC_TEST_OK 0x55 +#define KBD_ACK 0xfa +#define KBD_POR 0xaa + +/* keyboard scan codes */ + +#define KBD_US 0 /* default US layout */ +#define KBD_GER 1 /* german layout */ + +#define KBD_TIMEOUT 1000 /* 1 sec */ +#define KBD_RESET_TRIES 3 + +#define AS 0 /* normal character index */ +#define SH 1 /* shift index */ +#define CN 2 /* control index */ +#define NM 3 /* numeric lock index */ +#define AK 4 /* right alt key */ +#define CP 5 /* capslock index */ +#define ST 6 /* stop output index */ +#define EX 7 /* extended code index */ +#define ES 8 /* escape and extended code index */ + +#define NORMAL 0x0000 /* normal key */ +#define STP 0x0001 /* scroll lock stop output*/ +#define NUM 0x0002 /* numeric lock */ +#define CAPS 0x0004 /* capslock */ +#define SHIFT 0x0008 /* shift */ +#define CTRL 0x0010 /* control*/ +#define EXT 0x0020 /* extended scan code 0xe0 */ +#define ESC 0x0040 /* escape key press */ +#define E1 0x0080 /* extended scan code 0xe1 */ +#define BRK 0x0100 /* make break flag for keyboard */ +#define ALT 0x0200 /* right alt */ + +#endif /* _I8042_H_ */ diff --git a/roms/u-boot/include/ide.h b/roms/u-boot/include/ide.h new file mode 100644 index 000000000..1b37d6799 --- /dev/null +++ b/roms/u-boot/include/ide.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef _IDE_H +#define _IDE_H + +#include + +#define IDE_BUS(dev) (dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS)) + +#define ATA_CURR_BASE(dev) (CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)]) +extern ulong ide_bus_offset[]; + +/* + * Function Prototypes + */ + +void ide_init(void); +struct blk_desc; +struct udevice; +#ifdef CONFIG_BLK +ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, + void *buffer); +ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, + const void *buffer); +#else +ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt, + void *buffer); +ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt, + const void *buffer); +#endif + +#ifdef CONFIG_IDE_PREINIT +int ide_preinit(void); +#endif + +#if defined(CONFIG_OF_IDE_FIXUP) +int ide_device_present(int dev); +#endif + +#if defined(CONFIG_IDE_AHB) +unsigned char ide_read_register(int dev, unsigned int port); +void ide_write_register(int dev, unsigned int port, unsigned char val); +void ide_read_data(int dev, ulong *sect_buf, int words); +void ide_write_data(int dev, const ulong *sect_buf, int words); +#endif + +/* + * I/O function overrides + */ +unsigned char ide_inb(int dev, int port); +void ide_outb(int dev, int port, unsigned char val); +void ide_input_swap_data(int dev, ulong *sect_buf, int words); +void ide_input_data(int dev, ulong *sect_buf, int words); +void ide_output_data(int dev, const ulong *sect_buf, int words); +void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts); +void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts); + +void ide_led(uchar led, uchar status); + +/** + * board_start_ide() - Start up the board IDE interfac + * + * @return 0 if ok + */ +int board_start_ide(void); + +#endif /* _IDE_H */ diff --git a/roms/u-boot/include/image-android-dt.h b/roms/u-boot/include/image-android-dt.h new file mode 100644 index 000000000..9a3aa8fa3 --- /dev/null +++ b/roms/u-boot/include/image-android-dt.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 Linaro Ltd. + * Sam Protsenko + */ + +#ifndef IMAGE_ANDROID_DT_H +#define IMAGE_ANDROID_DT_H + +#include + +bool android_dt_check_header(ulong hdr_addr); +bool android_dt_get_fdt_by_index(ulong hdr_addr, u32 index, ulong *addr, + u32 *size); + +#if !defined(CONFIG_SPL_BUILD) +void android_dt_print_contents(ulong hdr_addr); +#endif + +#endif /* IMAGE_ANDROID_DT_H */ diff --git a/roms/u-boot/include/image-sparse.h b/roms/u-boot/include/image-sparse.h new file mode 100644 index 000000000..0572dbd0a --- /dev/null +++ b/roms/u-boot/include/image-sparse.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Broadcom Corporation. + */ + +#include +#include +#include + +#define ROUNDUP(x, y) (((x) + ((y) - 1)) & ~((y) - 1)) + +struct sparse_storage { + lbaint_t blksz; + lbaint_t start; + lbaint_t size; + void *priv; + + lbaint_t (*write)(struct sparse_storage *info, + lbaint_t blk, + lbaint_t blkcnt, + const void *buffer); + + lbaint_t (*reserve)(struct sparse_storage *info, + lbaint_t blk, + lbaint_t blkcnt); + + void (*mssg)(const char *str, char *response); +}; + +static inline int is_sparse_image(void *buf) +{ + sparse_header_t *s_header = (sparse_header_t *)buf; + + if ((le32_to_cpu(s_header->magic) == SPARSE_HEADER_MAGIC) && + (le16_to_cpu(s_header->major_version) == 1)) + return 1; + + return 0; +} + +int write_sparse_image(struct sparse_storage *info, const char *part_name, + void *data, char *response); diff --git a/roms/u-boot/include/image.h b/roms/u-boot/include/image.h new file mode 100644 index 000000000..459685d4d --- /dev/null +++ b/roms/u-boot/include/image.h @@ -0,0 +1,1650 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2008 Semihalf + * + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef __IMAGE_H__ +#define __IMAGE_H__ + +#include "compiler.h" +#include +#include + +/* Define this to avoid #ifdefs later on */ +struct lmb; +struct fdt_region; + +#ifdef USE_HOSTCC +#include + +/* new uImage format support enabled on host */ +#define IMAGE_ENABLE_FIT 1 +#define IMAGE_ENABLE_OF_LIBFDT 1 +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ +#define CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT 1 +#define CONFIG_FIT_ENABLE_SHA256_SUPPORT +#define CONFIG_FIT_ENABLE_SHA384_SUPPORT +#define CONFIG_FIT_ENABLE_SHA512_SUPPORT +#define CONFIG_SHA1 +#define CONFIG_SHA256 +#define CONFIG_SHA384 +#define CONFIG_SHA512 + +#define IMAGE_ENABLE_IGNORE 0 +#define IMAGE_INDENT_STRING "" + +#else + +#include +#include +#include + +/* Take notice of the 'ignore' property for hashes */ +#define IMAGE_ENABLE_IGNORE 1 +#define IMAGE_INDENT_STRING " " + +#define IMAGE_ENABLE_FIT CONFIG_IS_ENABLED(FIT) +#define IMAGE_ENABLE_OF_LIBFDT CONFIG_IS_ENABLED(OF_LIBFDT) + +#endif /* USE_HOSTCC */ + +#if IMAGE_ENABLE_FIT +#include +#include +#include +# ifdef CONFIG_SPL_BUILD +# ifdef CONFIG_SPL_CRC32_SUPPORT +# define IMAGE_ENABLE_CRC32 1 +# endif +# ifdef CONFIG_SPL_MD5_SUPPORT +# define IMAGE_ENABLE_MD5 1 +# endif +# ifdef CONFIG_SPL_SHA1_SUPPORT +# define IMAGE_ENABLE_SHA1 1 +# endif +# else +# define IMAGE_ENABLE_CRC32 1 +# define IMAGE_ENABLE_MD5 1 +# define IMAGE_ENABLE_SHA1 1 +# endif + +#ifndef IMAGE_ENABLE_CRC32 +#define IMAGE_ENABLE_CRC32 0 +#endif + +#ifndef IMAGE_ENABLE_MD5 +#define IMAGE_ENABLE_MD5 0 +#endif + +#ifndef IMAGE_ENABLE_SHA1 +#define IMAGE_ENABLE_SHA1 0 +#endif + +#if defined(CONFIG_FIT_ENABLE_SHA256_SUPPORT) || \ + defined(CONFIG_SPL_SHA256_SUPPORT) +#define IMAGE_ENABLE_SHA256 1 +#else +#define IMAGE_ENABLE_SHA256 0 +#endif + +#if defined(CONFIG_FIT_ENABLE_SHA384_SUPPORT) || \ + defined(CONFIG_SPL_SHA384_SUPPORT) +#define IMAGE_ENABLE_SHA384 1 +#else +#define IMAGE_ENABLE_SHA384 0 +#endif + +#if defined(CONFIG_FIT_ENABLE_SHA512_SUPPORT) || \ + defined(CONFIG_SPL_SHA512_SUPPORT) +#define IMAGE_ENABLE_SHA512 1 +#else +#define IMAGE_ENABLE_SHA512 0 +#endif + +#endif /* IMAGE_ENABLE_FIT */ + +#ifdef CONFIG_SYS_BOOT_GET_CMDLINE +# define IMAGE_BOOT_GET_CMDLINE 1 +#else +# define IMAGE_BOOT_GET_CMDLINE 0 +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +# define IMAGE_OF_BOARD_SETUP 1 +#else +# define IMAGE_OF_BOARD_SETUP 0 +#endif + +#ifdef CONFIG_OF_SYSTEM_SETUP +# define IMAGE_OF_SYSTEM_SETUP 1 +#else +# define IMAGE_OF_SYSTEM_SETUP 0 +#endif + +extern ulong image_load_addr; /* Default Load Address */ +extern ulong image_save_addr; /* Default Save Address */ +extern ulong image_save_size; /* Default Save Size */ + +/* An invalid size, meaning that the image size is not known */ +#define IMAGE_SIZE_INVAL (-1UL) + +enum ih_category { + IH_ARCH, + IH_COMP, + IH_OS, + IH_TYPE, + + IH_COUNT, +}; + +/* + * Operating System Codes + * + * The following are exposed to uImage header. + * New IDs *MUST* be appended at the end of the list and *NEVER* + * inserted for backward compatibility. + */ +enum { + IH_OS_INVALID = 0, /* Invalid OS */ + IH_OS_OPENBSD, /* OpenBSD */ + IH_OS_NETBSD, /* NetBSD */ + IH_OS_FREEBSD, /* FreeBSD */ + IH_OS_4_4BSD, /* 4.4BSD */ + IH_OS_LINUX, /* Linux */ + IH_OS_SVR4, /* SVR4 */ + IH_OS_ESIX, /* Esix */ + IH_OS_SOLARIS, /* Solaris */ + IH_OS_IRIX, /* Irix */ + IH_OS_SCO, /* SCO */ + IH_OS_DELL, /* Dell */ + IH_OS_NCR, /* NCR */ + IH_OS_LYNXOS, /* LynxOS */ + IH_OS_VXWORKS, /* VxWorks */ + IH_OS_PSOS, /* pSOS */ + IH_OS_QNX, /* QNX */ + IH_OS_U_BOOT, /* Firmware */ + IH_OS_RTEMS, /* RTEMS */ + IH_OS_ARTOS, /* ARTOS */ + IH_OS_UNITY, /* Unity OS */ + IH_OS_INTEGRITY, /* INTEGRITY */ + IH_OS_OSE, /* OSE */ + IH_OS_PLAN9, /* Plan 9 */ + IH_OS_OPENRTOS, /* OpenRTOS */ + IH_OS_ARM_TRUSTED_FIRMWARE, /* ARM Trusted Firmware */ + IH_OS_TEE, /* Trusted Execution Environment */ + IH_OS_OPENSBI, /* RISC-V OpenSBI */ + IH_OS_EFI, /* EFI Firmware (e.g. GRUB2) */ + + IH_OS_COUNT, +}; + +/* + * CPU Architecture Codes (supported by Linux) + * + * The following are exposed to uImage header. + * New IDs *MUST* be appended at the end of the list and *NEVER* + * inserted for backward compatibility. + */ +enum { + IH_ARCH_INVALID = 0, /* Invalid CPU */ + IH_ARCH_ALPHA, /* Alpha */ + IH_ARCH_ARM, /* ARM */ + IH_ARCH_I386, /* Intel x86 */ + IH_ARCH_IA64, /* IA64 */ + IH_ARCH_MIPS, /* MIPS */ + IH_ARCH_MIPS64, /* MIPS 64 Bit */ + IH_ARCH_PPC, /* PowerPC */ + IH_ARCH_S390, /* IBM S390 */ + IH_ARCH_SH, /* SuperH */ + IH_ARCH_SPARC, /* Sparc */ + IH_ARCH_SPARC64, /* Sparc 64 Bit */ + IH_ARCH_M68K, /* M68K */ + IH_ARCH_NIOS, /* Nios-32 */ + IH_ARCH_MICROBLAZE, /* MicroBlaze */ + IH_ARCH_NIOS2, /* Nios-II */ + IH_ARCH_BLACKFIN, /* Blackfin */ + IH_ARCH_AVR32, /* AVR32 */ + IH_ARCH_ST200, /* STMicroelectronics ST200 */ + IH_ARCH_SANDBOX, /* Sandbox architecture (test only) */ + IH_ARCH_NDS32, /* ANDES Technology - NDS32 */ + IH_ARCH_OPENRISC, /* OpenRISC 1000 */ + IH_ARCH_ARM64, /* ARM64 */ + IH_ARCH_ARC, /* Synopsys DesignWare ARC */ + IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */ + IH_ARCH_XTENSA, /* Xtensa */ + IH_ARCH_RISCV, /* RISC-V */ + + IH_ARCH_COUNT, +}; + +/* + * Image Types + * + * "Standalone Programs" are directly runnable in the environment + * provided by U-Boot; it is expected that (if they behave + * well) you can continue to work in U-Boot after return from + * the Standalone Program. + * "OS Kernel Images" are usually images of some Embedded OS which + * will take over control completely. Usually these programs + * will install their own set of exception handlers, device + * drivers, set up the MMU, etc. - this means, that you cannot + * expect to re-enter U-Boot except by resetting the CPU. + * "RAMDisk Images" are more or less just data blocks, and their + * parameters (address, size) are passed to an OS kernel that is + * being started. + * "Multi-File Images" contain several images, typically an OS + * (Linux) kernel image and one or more data images like + * RAMDisks. This construct is useful for instance when you want + * to boot over the network using BOOTP etc., where the boot + * server provides just a single image file, but you want to get + * for instance an OS kernel and a RAMDisk image. + * + * "Multi-File Images" start with a list of image sizes, each + * image size (in bytes) specified by an "uint32_t" in network + * byte order. This list is terminated by an "(uint32_t)0". + * Immediately after the terminating 0 follow the images, one by + * one, all aligned on "uint32_t" boundaries (size rounded up to + * a multiple of 4 bytes - except for the last file). + * + * "Firmware Images" are binary images containing firmware (like + * U-Boot or FPGA images) which usually will be programmed to + * flash memory. + * + * "Script files" are command sequences that will be executed by + * U-Boot's command interpreter; this feature is especially + * useful when you configure U-Boot to use a real shell (hush) + * as command interpreter (=> Shell Scripts). + * + * The following are exposed to uImage header. + * New IDs *MUST* be appended at the end of the list and *NEVER* + * inserted for backward compatibility. + */ + +enum { + IH_TYPE_INVALID = 0, /* Invalid Image */ + IH_TYPE_STANDALONE, /* Standalone Program */ + IH_TYPE_KERNEL, /* OS Kernel Image */ + IH_TYPE_RAMDISK, /* RAMDisk Image */ + IH_TYPE_MULTI, /* Multi-File Image */ + IH_TYPE_FIRMWARE, /* Firmware Image */ + IH_TYPE_SCRIPT, /* Script file */ + IH_TYPE_FILESYSTEM, /* Filesystem Image (any type) */ + IH_TYPE_FLATDT, /* Binary Flat Device Tree Blob */ + IH_TYPE_KWBIMAGE, /* Kirkwood Boot Image */ + IH_TYPE_IMXIMAGE, /* Freescale IMXBoot Image */ + IH_TYPE_UBLIMAGE, /* Davinci UBL Image */ + IH_TYPE_OMAPIMAGE, /* TI OMAP Config Header Image */ + IH_TYPE_AISIMAGE, /* TI Davinci AIS Image */ + /* OS Kernel Image, can run from any load address */ + IH_TYPE_KERNEL_NOLOAD, + IH_TYPE_PBLIMAGE, /* Freescale PBL Boot Image */ + IH_TYPE_MXSIMAGE, /* Freescale MXSBoot Image */ + IH_TYPE_GPIMAGE, /* TI Keystone GPHeader Image */ + IH_TYPE_ATMELIMAGE, /* ATMEL ROM bootable Image */ + IH_TYPE_SOCFPGAIMAGE, /* Altera SOCFPGA CV/AV Preloader */ + IH_TYPE_X86_SETUP, /* x86 setup.bin Image */ + IH_TYPE_LPC32XXIMAGE, /* x86 setup.bin Image */ + IH_TYPE_LOADABLE, /* A list of typeless images */ + IH_TYPE_RKIMAGE, /* Rockchip Boot Image */ + IH_TYPE_RKSD, /* Rockchip SD card */ + IH_TYPE_RKSPI, /* Rockchip SPI image */ + IH_TYPE_ZYNQIMAGE, /* Xilinx Zynq Boot Image */ + IH_TYPE_ZYNQMPIMAGE, /* Xilinx ZynqMP Boot Image */ + IH_TYPE_ZYNQMPBIF, /* Xilinx ZynqMP Boot Image (bif) */ + IH_TYPE_FPGA, /* FPGA Image */ + IH_TYPE_VYBRIDIMAGE, /* VYBRID .vyb Image */ + IH_TYPE_TEE, /* Trusted Execution Environment OS Image */ + IH_TYPE_FIRMWARE_IVT, /* Firmware Image with HABv4 IVT */ + IH_TYPE_PMMC, /* TI Power Management Micro-Controller Firmware */ + IH_TYPE_STM32IMAGE, /* STMicroelectronics STM32 Image */ + IH_TYPE_SOCFPGAIMAGE_V1, /* Altera SOCFPGA A10 Preloader */ + IH_TYPE_MTKIMAGE, /* MediaTek BootROM loadable Image */ + IH_TYPE_IMX8MIMAGE, /* Freescale IMX8MBoot Image */ + IH_TYPE_IMX8IMAGE, /* Freescale IMX8Boot Image */ + IH_TYPE_COPRO, /* Coprocessor Image for remoteproc*/ + IH_TYPE_SUNXI_EGON, /* Allwinner eGON Boot Image */ + + IH_TYPE_COUNT, /* Number of image types */ +}; + +/* + * Compression Types + * + * The following are exposed to uImage header. + * New IDs *MUST* be appended at the end of the list and *NEVER* + * inserted for backward compatibility. + */ +enum { + IH_COMP_NONE = 0, /* No Compression Used */ + IH_COMP_GZIP, /* gzip Compression Used */ + IH_COMP_BZIP2, /* bzip2 Compression Used */ + IH_COMP_LZMA, /* lzma Compression Used */ + IH_COMP_LZO, /* lzo Compression Used */ + IH_COMP_LZ4, /* lz4 Compression Used */ + IH_COMP_ZSTD, /* zstd Compression Used */ + + IH_COMP_COUNT, +}; + +#define LZ4F_MAGIC 0x184D2204 /* LZ4 Magic Number */ +#define IH_MAGIC 0x27051956 /* Image Magic Number */ +#define IH_NMLEN 32 /* Image Name Length */ + +/* Reused from common.h */ +#define ROUND(a, b) (((a) + (b) - 1) & ~((b) - 1)) + +/* + * Legacy format image header, + * all data in network byte order (aka natural aka bigendian). + */ +typedef struct image_header { + uint32_t ih_magic; /* Image Header Magic Number */ + uint32_t ih_hcrc; /* Image Header CRC Checksum */ + uint32_t ih_time; /* Image Creation Timestamp */ + uint32_t ih_size; /* Image Data Size */ + uint32_t ih_load; /* Data Load Address */ + uint32_t ih_ep; /* Entry Point Address */ + uint32_t ih_dcrc; /* Image Data CRC Checksum */ + uint8_t ih_os; /* Operating System */ + uint8_t ih_arch; /* CPU architecture */ + uint8_t ih_type; /* Image Type */ + uint8_t ih_comp; /* Compression Type */ + uint8_t ih_name[IH_NMLEN]; /* Image Name */ +} image_header_t; + +typedef struct image_info { + ulong start, end; /* start/end of blob */ + ulong image_start, image_len; /* start of image within blob, len of image */ + ulong load; /* load addr for the image */ + uint8_t comp, type, os; /* compression, type of image, os type */ + uint8_t arch; /* CPU architecture */ +} image_info_t; + +/* + * Legacy and FIT format headers used by do_bootm() and do_bootm_() + * routines. + */ +typedef struct bootm_headers { + /* + * Legacy os image header, if it is a multi component image + * then boot_get_ramdisk() and get_fdt() will attempt to get + * data from second and third component accordingly. + */ + image_header_t *legacy_hdr_os; /* image header pointer */ + image_header_t legacy_hdr_os_copy; /* header copy */ + ulong legacy_hdr_valid; + +#if IMAGE_ENABLE_FIT + const char *fit_uname_cfg; /* configuration node unit name */ + + void *fit_hdr_os; /* os FIT image header */ + const char *fit_uname_os; /* os subimage node unit name */ + int fit_noffset_os; /* os subimage node offset */ + + void *fit_hdr_rd; /* init ramdisk FIT image header */ + const char *fit_uname_rd; /* init ramdisk subimage node unit name */ + int fit_noffset_rd; /* init ramdisk subimage node offset */ + + void *fit_hdr_fdt; /* FDT blob FIT image header */ + const char *fit_uname_fdt; /* FDT blob subimage node unit name */ + int fit_noffset_fdt;/* FDT blob subimage node offset */ + + void *fit_hdr_setup; /* x86 setup FIT image header */ + const char *fit_uname_setup; /* x86 setup subimage node name */ + int fit_noffset_setup;/* x86 setup subimage node offset */ +#endif + +#ifndef USE_HOSTCC + image_info_t os; /* os image info */ + ulong ep; /* entry point of OS */ + + ulong rd_start, rd_end;/* ramdisk start/end */ + + char *ft_addr; /* flat dev tree address */ + ulong ft_len; /* length of flat device tree */ + + ulong initrd_start; + ulong initrd_end; + ulong cmdline_start; + ulong cmdline_end; + struct bd_info *kbd; +#endif + + int verify; /* env_get("verify")[0] != 'n' */ + +#define BOOTM_STATE_START (0x00000001) +#define BOOTM_STATE_FINDOS (0x00000002) +#define BOOTM_STATE_FINDOTHER (0x00000004) +#define BOOTM_STATE_LOADOS (0x00000008) +#define BOOTM_STATE_RAMDISK (0x00000010) +#define BOOTM_STATE_FDT (0x00000020) +#define BOOTM_STATE_OS_CMDLINE (0x00000040) +#define BOOTM_STATE_OS_BD_T (0x00000080) +#define BOOTM_STATE_OS_PREP (0x00000100) +#define BOOTM_STATE_OS_FAKE_GO (0x00000200) /* 'Almost' run the OS */ +#define BOOTM_STATE_OS_GO (0x00000400) + int state; + +#if defined(CONFIG_LMB) && !defined(USE_HOSTCC) + struct lmb lmb; /* for memory mgmt */ +#endif +} bootm_headers_t; + +extern bootm_headers_t images; + +/* + * Some systems (for example LWMON) have very short watchdog periods; + * we must make sure to split long operations like memmove() or + * checksum calculations into reasonable chunks. + */ +#ifndef CHUNKSZ +#define CHUNKSZ (64 * 1024) +#endif + +#ifndef CHUNKSZ_CRC32 +#define CHUNKSZ_CRC32 (64 * 1024) +#endif + +#ifndef CHUNKSZ_MD5 +#define CHUNKSZ_MD5 (64 * 1024) +#endif + +#ifndef CHUNKSZ_SHA1 +#define CHUNKSZ_SHA1 (64 * 1024) +#endif + +#define uimage_to_cpu(x) be32_to_cpu(x) +#define cpu_to_uimage(x) cpu_to_be32(x) + +/* + * Translation table for entries of a specific type; used by + * get_table_entry_id() and get_table_entry_name(). + */ +typedef struct table_entry { + int id; + char *sname; /* short (input) name to find table entry */ + char *lname; /* long (output) name to print for messages */ +} table_entry_t; + +/* + * Compression type and magic number mapping table. + */ +struct comp_magic_map { + int comp_id; + const char *name; + unsigned char magic[2]; +}; + +/* + * get_table_entry_id() scans the translation table trying to find an + * entry that matches the given short name. If a matching entry is + * found, it's id is returned to the caller. + */ +int get_table_entry_id(const table_entry_t *table, + const char *table_name, const char *name); +/* + * get_table_entry_name() scans the translation table trying to find + * an entry that matches the given id. If a matching entry is found, + * its long name is returned to the caller. + */ +char *get_table_entry_name(const table_entry_t *table, char *msg, int id); + +const char *genimg_get_os_name(uint8_t os); + +/** + * genimg_get_os_short_name() - get the short name for an OS + * + * @param os OS (IH_OS_...) + * @return OS short name, or "unknown" if unknown + */ +const char *genimg_get_os_short_name(uint8_t comp); + +const char *genimg_get_arch_name(uint8_t arch); + +/** + * genimg_get_arch_short_name() - get the short name for an architecture + * + * @param arch Architecture type (IH_ARCH_...) + * @return architecture short name, or "unknown" if unknown + */ +const char *genimg_get_arch_short_name(uint8_t arch); + +const char *genimg_get_type_name(uint8_t type); + +/** + * genimg_get_type_short_name() - get the short name for an image type + * + * @param type Image type (IH_TYPE_...) + * @return image short name, or "unknown" if unknown + */ +const char *genimg_get_type_short_name(uint8_t type); + +const char *genimg_get_comp_name(uint8_t comp); + +/** + * genimg_get_comp_short_name() - get the short name for a compression method + * + * @param comp compression method (IH_COMP_...) + * @return compression method short name, or "unknown" if unknown + */ +const char *genimg_get_comp_short_name(uint8_t comp); + +/** + * genimg_get_cat_name() - Get the name of an item in a category + * + * @category: Category of item + * @id: Item ID + * @return name of item, or "Unknown ..." if unknown + */ +const char *genimg_get_cat_name(enum ih_category category, uint id); + +/** + * genimg_get_cat_short_name() - Get the short name of an item in a category + * + * @category: Category of item + * @id: Item ID + * @return short name of item, or "Unknown ..." if unknown + */ +const char *genimg_get_cat_short_name(enum ih_category category, uint id); + +/** + * genimg_get_cat_count() - Get the number of items in a category + * + * @category: Category to check + * @return the number of items in the category (IH_xxx_COUNT) + */ +int genimg_get_cat_count(enum ih_category category); + +/** + * genimg_get_cat_desc() - Get the description of a category + * + * @category: Category to check + * @return the description of a category, e.g. "architecture". This + * effectively converts the enum to a string. + */ +const char *genimg_get_cat_desc(enum ih_category category); + +/** + * genimg_cat_has_id() - Check whether a category has an item + * + * @category: Category to check + * @id: Item ID + * @return true or false as to whether a category has an item + */ +bool genimg_cat_has_id(enum ih_category category, uint id); + +int genimg_get_os_id(const char *name); +int genimg_get_arch_id(const char *name); +int genimg_get_type_id(const char *name); +int genimg_get_comp_id(const char *name); +void genimg_print_size(uint32_t size); + +#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || \ + defined(USE_HOSTCC) +#define IMAGE_ENABLE_TIMESTAMP 1 +#else +#define IMAGE_ENABLE_TIMESTAMP 0 +#endif +void genimg_print_time(time_t timestamp); + +/* What to do with a image load address ('load = <> 'in the FIT) */ +enum fit_load_op { + FIT_LOAD_IGNORED, /* Ignore load address */ + FIT_LOAD_OPTIONAL, /* Can be provided, but optional */ + FIT_LOAD_OPTIONAL_NON_ZERO, /* Optional, a value of 0 is ignored */ + FIT_LOAD_REQUIRED, /* Must be provided */ +}; + +int boot_get_setup(bootm_headers_t *images, uint8_t arch, ulong *setup_start, + ulong *setup_len); + +#ifndef USE_HOSTCC +/* Image format types, returned by _get_format() routine */ +#define IMAGE_FORMAT_INVALID 0x00 +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) +#define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */ +#endif +#define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */ +#define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */ + +ulong genimg_get_kernel_addr_fit(char * const img_addr, + const char **fit_uname_config, + const char **fit_uname_kernel); +ulong genimg_get_kernel_addr(char * const img_addr); +int genimg_get_format(const void *img_addr); +int genimg_has_config(bootm_headers_t *images); + +int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images, + uint8_t arch, const ulong *ld_start, ulong * const ld_len); +int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, + uint8_t arch, ulong *rd_start, ulong *rd_end); + +/** + * boot_get_loadable - routine to load a list of binaries to memory + * @argc: Ignored Argument + * @argv: Ignored Argument + * @images: pointer to the bootm images structure + * @arch: expected architecture for the image + * @ld_start: Ignored Argument + * @ld_len: Ignored Argument + * + * boot_get_loadable() will take the given FIT configuration, and look + * for a field named "loadables". Loadables, is a list of elements in + * the FIT given as strings. exe: + * loadables = "linux_kernel", "fdt-2"; + * this function will attempt to parse each string, and load the + * corresponding element from the FIT into memory. Once placed, + * no aditional actions are taken. + * + * @return: + * 0, if only valid images or no images are found + * error code, if an error occurs during fit_image_load + */ +int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images, + uint8_t arch, const ulong *ld_start, ulong *const ld_len); +#endif /* !USE_HOSTCC */ + +int boot_get_setup_fit(bootm_headers_t *images, uint8_t arch, + ulong *setup_start, ulong *setup_len); + +/** + * boot_get_fdt_fit() - load a DTB from a FIT file (applying overlays) + * + * This deals with all aspects of loading an DTB from a FIT. + * The correct base image based on configuration will be selected, and + * then any overlays specified will be applied (as present in fit_uname_configp). + * + * @param images Boot images structure + * @param addr Address of FIT in memory + * @param fit_unamep On entry this is the requested image name + * (e.g. "kernel") or NULL to use the default. On exit + * points to the selected image name + * @param fit_uname_configp On entry this is the requested configuration + * name (e.g. "conf-1") or NULL to use the default. On + * exit points to the selected configuration name. + * @param arch Expected architecture (IH_ARCH_...) + * @param datap Returns address of loaded image + * @param lenp Returns length of loaded image + * + * @return node offset of base image, or -ve error code on error + */ +int boot_get_fdt_fit(bootm_headers_t *images, ulong addr, + const char **fit_unamep, const char **fit_uname_configp, + int arch, ulong *datap, ulong *lenp); + +/** + * fit_image_load() - load an image from a FIT + * + * This deals with all aspects of loading an image from a FIT, including + * selecting the right image based on configuration, verifying it, printing + * out progress messages, checking the type/arch/os and optionally copying it + * to the right load address. + * + * The property to look up is defined by image_type. + * + * @param images Boot images structure + * @param addr Address of FIT in memory + * @param fit_unamep On entry this is the requested image name + * (e.g. "kernel") or NULL to use the default. On exit + * points to the selected image name + * @param fit_uname_configp On entry this is the requested configuration + * name (e.g. "conf-1") or NULL to use the default. On + * exit points to the selected configuration name. + * @param arch Expected architecture (IH_ARCH_...) + * @param image_type Required image type (IH_TYPE_...). If this is + * IH_TYPE_KERNEL then we allow IH_TYPE_KERNEL_NOLOAD + * also. + * @param bootstage_id ID of starting bootstage to use for progress updates. + * This will be added to the BOOTSTAGE_SUB values when + * calling bootstage_mark() + * @param load_op Decribes what to do with the load address + * @param datap Returns address of loaded image + * @param lenp Returns length of loaded image + * @return node offset of image, or -ve error code on error + */ +int fit_image_load(bootm_headers_t *images, ulong addr, + const char **fit_unamep, const char **fit_uname_configp, + int arch, int image_type, int bootstage_id, + enum fit_load_op load_op, ulong *datap, ulong *lenp); + +/** + * image_source_script() - Execute a script + * + * Executes a U-Boot script at a particular address in memory. The script should + * have a header (FIT or legacy) with the script type (IH_TYPE_SCRIPT). + * + * @addr: Address of script + * @fit_uname: FIT subimage name + * @return result code (enum command_ret_t) + */ +int image_source_script(ulong addr, const char *fit_uname); + +#ifndef USE_HOSTCC +/** + * fit_get_node_from_config() - Look up an image a FIT by type + * + * This looks in the selected conf- node (images->fit_uname_cfg) for a + * particular image type (e.g. "kernel") and then finds the image that is + * referred to. + * + * For example, for something like: + * + * images { + * kernel { + * ... + * }; + * }; + * configurations { + * conf-1 { + * kernel = "kernel"; + * }; + * }; + * + * the function will return the node offset of the kernel@1 node, assuming + * that conf-1 is the chosen configuration. + * + * @param images Boot images structure + * @param prop_name Property name to look up (FIT_..._PROP) + * @param addr Address of FIT in memory + */ +int fit_get_node_from_config(bootm_headers_t *images, const char *prop_name, + ulong addr); + +int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch, + bootm_headers_t *images, + char **of_flat_tree, ulong *of_size); +void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob); +int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size); + +int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, + ulong *initrd_start, ulong *initrd_end); +int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end); +#ifdef CONFIG_SYS_BOOT_GET_KBD +int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd); +#endif /* CONFIG_SYS_BOOT_GET_KBD */ +#endif /* !USE_HOSTCC */ + +/*******************************************************************/ +/* Legacy format specific code (prefixed with image_) */ +/*******************************************************************/ +static inline uint32_t image_get_header_size(void) +{ + return (sizeof(image_header_t)); +} + +#define image_get_hdr_l(f) \ + static inline uint32_t image_get_##f(const image_header_t *hdr) \ + { \ + return uimage_to_cpu(hdr->ih_##f); \ + } +image_get_hdr_l(magic) /* image_get_magic */ +image_get_hdr_l(hcrc) /* image_get_hcrc */ +image_get_hdr_l(time) /* image_get_time */ +image_get_hdr_l(size) /* image_get_size */ +image_get_hdr_l(load) /* image_get_load */ +image_get_hdr_l(ep) /* image_get_ep */ +image_get_hdr_l(dcrc) /* image_get_dcrc */ + +#define image_get_hdr_b(f) \ + static inline uint8_t image_get_##f(const image_header_t *hdr) \ + { \ + return hdr->ih_##f; \ + } +image_get_hdr_b(os) /* image_get_os */ +image_get_hdr_b(arch) /* image_get_arch */ +image_get_hdr_b(type) /* image_get_type */ +image_get_hdr_b(comp) /* image_get_comp */ + +static inline char *image_get_name(const image_header_t *hdr) +{ + return (char *)hdr->ih_name; +} + +static inline uint32_t image_get_data_size(const image_header_t *hdr) +{ + return image_get_size(hdr); +} + +/** + * image_get_data - get image payload start address + * @hdr: image header + * + * image_get_data() returns address of the image payload. For single + * component images it is image data start. For multi component + * images it points to the null terminated table of sub-images sizes. + * + * returns: + * image payload data start address + */ +static inline ulong image_get_data(const image_header_t *hdr) +{ + return ((ulong)hdr + image_get_header_size()); +} + +static inline uint32_t image_get_image_size(const image_header_t *hdr) +{ + return (image_get_size(hdr) + image_get_header_size()); +} +static inline ulong image_get_image_end(const image_header_t *hdr) +{ + return ((ulong)hdr + image_get_image_size(hdr)); +} + +#define image_set_hdr_l(f) \ + static inline void image_set_##f(image_header_t *hdr, uint32_t val) \ + { \ + hdr->ih_##f = cpu_to_uimage(val); \ + } +image_set_hdr_l(magic) /* image_set_magic */ +image_set_hdr_l(hcrc) /* image_set_hcrc */ +image_set_hdr_l(time) /* image_set_time */ +image_set_hdr_l(size) /* image_set_size */ +image_set_hdr_l(load) /* image_set_load */ +image_set_hdr_l(ep) /* image_set_ep */ +image_set_hdr_l(dcrc) /* image_set_dcrc */ + +#define image_set_hdr_b(f) \ + static inline void image_set_##f(image_header_t *hdr, uint8_t val) \ + { \ + hdr->ih_##f = val; \ + } +image_set_hdr_b(os) /* image_set_os */ +image_set_hdr_b(arch) /* image_set_arch */ +image_set_hdr_b(type) /* image_set_type */ +image_set_hdr_b(comp) /* image_set_comp */ + +static inline void image_set_name(image_header_t *hdr, const char *name) +{ + strncpy(image_get_name(hdr), name, IH_NMLEN); +} + +int image_check_hcrc(const image_header_t *hdr); +int image_check_dcrc(const image_header_t *hdr); +#ifndef USE_HOSTCC +ulong env_get_bootm_low(void); +phys_size_t env_get_bootm_size(void); +phys_size_t env_get_bootm_mapsize(void); +#endif +void memmove_wd(void *to, void *from, size_t len, ulong chunksz); + +static inline int image_check_magic(const image_header_t *hdr) +{ + return (image_get_magic(hdr) == IH_MAGIC); +} +static inline int image_check_type(const image_header_t *hdr, uint8_t type) +{ + return (image_get_type(hdr) == type); +} +static inline int image_check_arch(const image_header_t *hdr, uint8_t arch) +{ +#ifndef USE_HOSTCC + /* Let's assume that sandbox can load any architecture */ + if (IS_ENABLED(CONFIG_SANDBOX)) + return true; +#endif + return (image_get_arch(hdr) == arch) || + (image_get_arch(hdr) == IH_ARCH_ARM && arch == IH_ARCH_ARM64); +} +static inline int image_check_os(const image_header_t *hdr, uint8_t os) +{ + return (image_get_os(hdr) == os); +} + +ulong image_multi_count(const image_header_t *hdr); +void image_multi_getimg(const image_header_t *hdr, ulong idx, + ulong *data, ulong *len); + +void image_print_contents(const void *hdr); + +#ifndef USE_HOSTCC +static inline int image_check_target_arch(const image_header_t *hdr) +{ +#ifndef IH_ARCH_DEFAULT +# error "please define IH_ARCH_DEFAULT in your arch asm/u-boot.h" +#endif + return image_check_arch(hdr, IH_ARCH_DEFAULT); +} +#endif /* USE_HOSTCC */ + +/** + * image_decomp_type() - Find out compression type of an image + * + * @buf: Address in U-Boot memory where image is loaded. + * @len: Length of the compressed image. + * @return compression type or IH_COMP_NONE if not compressed. + * + * Note: Only following compression types are supported now. + * lzo, lzma, gzip, bzip2 + */ +int image_decomp_type(const unsigned char *buf, ulong len); + +/** + * image_decomp() - decompress an image + * + * @comp: Compression algorithm that is used (IH_COMP_...) + * @load: Destination load address in U-Boot memory + * @image_start Image start address (where we are decompressing from) + * @type: OS type (IH_OS_...) + * @load_bug: Place to decompress to + * @image_buf: Address to decompress from + * @image_len: Number of bytes in @image_buf to decompress + * @unc_len: Available space for decompression + * @return 0 if OK, -ve on error (BOOTM_ERR_...) + */ +int image_decomp(int comp, ulong load, ulong image_start, int type, + void *load_buf, void *image_buf, ulong image_len, + uint unc_len, ulong *load_end); + +/** + * Set up properties in the FDT + * + * This sets up properties in the FDT that is to be passed to linux. + * + * @images: Images information + * @blob: FDT to update + * @of_size: Size of the FDT + * @lmb: Points to logical memory block structure + * @return 0 if ok, <0 on failure + */ +int image_setup_libfdt(bootm_headers_t *images, void *blob, + int of_size, struct lmb *lmb); + +/** + * Set up the FDT to use for booting a kernel + * + * This performs ramdisk setup, sets up the FDT if required, and adds + * paramters to the FDT if libfdt is available. + * + * @param images Images information + * @return 0 if ok, <0 on failure + */ +int image_setup_linux(bootm_headers_t *images); + +/** + * bootz_setup() - Extract stat and size of a Linux xImage + * + * @image: Address of image + * @start: Returns start address of image + * @end : Returns end address of image + * @return 0 if OK, 1 if the image was not recognised + */ +int bootz_setup(ulong image, ulong *start, ulong *end); + +/** + * Return the correct start address and size of a Linux aarch64 Image. + * + * @image: Address of image + * @start: Returns start address of image + * @size : Returns size image + * @force_reloc: Ignore image->ep field, always place image to RAM start + * @return 0 if OK, 1 if the image was not recognised + */ +int booti_setup(ulong image, ulong *relocated_addr, ulong *size, + bool force_reloc); + +/*******************************************************************/ +/* New uImage format specific code (prefixed with fit_) */ +/*******************************************************************/ + +#define FIT_IMAGES_PATH "/images" +#define FIT_CONFS_PATH "/configurations" + +/* hash/signature/key node */ +#define FIT_HASH_NODENAME "hash" +#define FIT_ALGO_PROP "algo" +#define FIT_VALUE_PROP "value" +#define FIT_IGNORE_PROP "uboot-ignore" +#define FIT_SIG_NODENAME "signature" +#define FIT_KEY_REQUIRED "required" +#define FIT_KEY_HINT "key-name-hint" + +/* cipher node */ +#define FIT_CIPHER_NODENAME "cipher" +#define FIT_ALGO_PROP "algo" + +/* image node */ +#define FIT_DATA_PROP "data" +#define FIT_DATA_POSITION_PROP "data-position" +#define FIT_DATA_OFFSET_PROP "data-offset" +#define FIT_DATA_SIZE_PROP "data-size" +#define FIT_TIMESTAMP_PROP "timestamp" +#define FIT_DESC_PROP "description" +#define FIT_ARCH_PROP "arch" +#define FIT_TYPE_PROP "type" +#define FIT_OS_PROP "os" +#define FIT_COMP_PROP "compression" +#define FIT_ENTRY_PROP "entry" +#define FIT_LOAD_PROP "load" + +/* configuration node */ +#define FIT_KERNEL_PROP "kernel" +#define FIT_RAMDISK_PROP "ramdisk" +#define FIT_FDT_PROP "fdt" +#define FIT_LOADABLE_PROP "loadables" +#define FIT_DEFAULT_PROP "default" +#define FIT_SETUP_PROP "setup" +#define FIT_FPGA_PROP "fpga" +#define FIT_FIRMWARE_PROP "firmware" +#define FIT_STANDALONE_PROP "standalone" + +#define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE + +#if IMAGE_ENABLE_FIT +/* cmdline argument format parsing */ +int fit_parse_conf(const char *spec, ulong addr_curr, + ulong *addr, const char **conf_name); +int fit_parse_subimage(const char *spec, ulong addr_curr, + ulong *addr, const char **image_name); + +int fit_get_subimage_count(const void *fit, int images_noffset); +void fit_print_contents(const void *fit); +void fit_image_print(const void *fit, int noffset, const char *p); + +/** + * fit_get_end - get FIT image size + * @fit: pointer to the FIT format image header + * + * returns: + * size of the FIT image (blob) in memory + */ +static inline ulong fit_get_size(const void *fit) +{ + return fdt_totalsize(fit); +} + +/** + * fit_get_end - get FIT image end + * @fit: pointer to the FIT format image header + * + * returns: + * end address of the FIT image (blob) in memory + */ +ulong fit_get_end(const void *fit); + +/** + * fit_get_name - get FIT node name + * @fit: pointer to the FIT format image header + * + * returns: + * NULL, on error + * pointer to node name, on success + */ +static inline const char *fit_get_name(const void *fit_hdr, + int noffset, int *len) +{ + return fdt_get_name(fit_hdr, noffset, len); +} + +int fit_get_desc(const void *fit, int noffset, char **desc); +int fit_get_timestamp(const void *fit, int noffset, time_t *timestamp); + +int fit_image_get_node(const void *fit, const char *image_uname); +int fit_image_get_os(const void *fit, int noffset, uint8_t *os); +int fit_image_get_arch(const void *fit, int noffset, uint8_t *arch); +int fit_image_get_type(const void *fit, int noffset, uint8_t *type); +int fit_image_get_comp(const void *fit, int noffset, uint8_t *comp); +int fit_image_get_load(const void *fit, int noffset, ulong *load); +int fit_image_get_entry(const void *fit, int noffset, ulong *entry); +int fit_image_get_data(const void *fit, int noffset, + const void **data, size_t *size); +int fit_image_get_data_offset(const void *fit, int noffset, int *data_offset); +int fit_image_get_data_position(const void *fit, int noffset, + int *data_position); +int fit_image_get_data_size(const void *fit, int noffset, int *data_size); +int fit_image_get_data_size_unciphered(const void *fit, int noffset, + size_t *data_size); +int fit_image_get_data_and_size(const void *fit, int noffset, + const void **data, size_t *size); + +int fit_image_hash_get_algo(const void *fit, int noffset, char **algo); +int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value, + int *value_len); + +int fit_set_timestamp(void *fit, int noffset, time_t timestamp); + +int fit_cipher_data(const char *keydir, void *keydest, void *fit, + const char *comment, int require_keys, + const char *engine_id, const char *cmdname); + +/** + * fit_add_verification_data() - add verification data to FIT image nodes + * + * @keydir: Directory containing keys + * @kwydest: FDT blob to write public key information to + * @fit: Pointer to the FIT format image header + * @comment: Comment to add to signature nodes + * @require_keys: Mark all keys as 'required' + * @engine_id: Engine to use for signing + * @cmdname: Command name used when reporting errors + * + * Adds hash values for all component images in the FIT blob. + * Hashes are calculated for all component images which have hash subnodes + * with algorithm property set to one of the supported hash algorithms. + * + * Also add signatures if signature nodes are present. + * + * returns + * 0, on success + * libfdt error code, on failure + */ +int fit_add_verification_data(const char *keydir, const char *keyfile, + void *keydest, void *fit, const char *comment, + int require_keys, const char *engine_id, + const char *cmdname); + +int fit_image_verify_with_data(const void *fit, int image_noffset, + const void *data, size_t size); +int fit_image_verify(const void *fit, int noffset); +int fit_config_verify(const void *fit, int conf_noffset); +int fit_all_image_verify(const void *fit); +int fit_config_decrypt(const void *fit, int conf_noffset); +int fit_image_check_os(const void *fit, int noffset, uint8_t os); +int fit_image_check_arch(const void *fit, int noffset, uint8_t arch); +int fit_image_check_type(const void *fit, int noffset, uint8_t type); +int fit_image_check_comp(const void *fit, int noffset, uint8_t comp); + +/** + * fit_check_format() - Check that the FIT is valid + * + * This performs various checks on the FIT to make sure it is suitable for + * use, looking for mandatory properties, nodes, etc. + * + * If FIT_FULL_CHECK is enabled, it also runs it through libfdt to make + * sure that there are no strange tags or broken nodes in the FIT. + * + * @fit: pointer to the FIT format image header + * @return 0 if OK, -ENOEXEC if not an FDT file, -EINVAL if the full FDT check + * failed (e.g. due to bad structure), -ENOMSG if the description is + * missing, -EBADMSG if the timestamp is missing, -ENOENT if the /images + * path is missing + */ +int fit_check_format(const void *fit, ulong size); + +int fit_conf_find_compat(const void *fit, const void *fdt); + +/** + * fit_conf_get_node - get node offset for configuration of a given unit name + * @fit: pointer to the FIT format image header + * @conf_uname: configuration node unit name (NULL to use default) + * + * fit_conf_get_node() finds a configuration (within the '/configurations' + * parent node) of a provided unit name. If configuration is found its node + * offset is returned to the caller. + * + * When NULL is provided in second argument fit_conf_get_node() will search + * for a default configuration node instead. Default configuration node unit + * name is retrieved from FIT_DEFAULT_PROP property of the '/configurations' + * node. + * + * returns: + * configuration node offset when found (>=0) + * negative number on failure (FDT_ERR_* code) + */ +int fit_conf_get_node(const void *fit, const char *conf_uname); + +int fit_conf_get_prop_node_count(const void *fit, int noffset, + const char *prop_name); +int fit_conf_get_prop_node_index(const void *fit, int noffset, + const char *prop_name, int index); + +/** + * fit_conf_get_prop_node() - Get node refered to by a configuration + * @fit: FIT to check + * @noffset: Offset of conf@xxx node to check + * @prop_name: Property to read from the conf node + * + * The conf- nodes contain references to other nodes, using properties + * like 'kernel = "kernel"'. Given such a property name (e.g. "kernel"), + * return the offset of the node referred to (e.g. offset of node + * "/images/kernel". + */ +int fit_conf_get_prop_node(const void *fit, int noffset, + const char *prop_name); + +int fit_check_ramdisk(const void *fit, int os_noffset, + uint8_t arch, int verify); +#endif /* IMAGE_ENABLE_FIT */ + +int calculate_hash(const void *data, int data_len, const char *algo, + uint8_t *value, int *value_len); + +/* + * At present we only support signing on the host, and verification on the + * device + */ +#if defined(USE_HOSTCC) +# if defined(CONFIG_FIT_SIGNATURE) +# define IMAGE_ENABLE_SIGN 1 +# define IMAGE_ENABLE_VERIFY 1 +# define IMAGE_ENABLE_VERIFY_ECDSA 1 +# define FIT_IMAGE_ENABLE_VERIFY 1 +# include +# else +# define IMAGE_ENABLE_SIGN 0 +# define IMAGE_ENABLE_VERIFY 0 +# define IMAGE_ENABLE_VERIFY_ECDSA 0 +# define FIT_IMAGE_ENABLE_VERIFY 0 +# endif +#else +# define IMAGE_ENABLE_SIGN 0 +# define IMAGE_ENABLE_VERIFY CONFIG_IS_ENABLED(RSA_VERIFY) +# define IMAGE_ENABLE_VERIFY_ECDSA 0 +# define FIT_IMAGE_ENABLE_VERIFY CONFIG_IS_ENABLED(FIT_SIGNATURE) +#endif + +#if IMAGE_ENABLE_FIT +#ifdef USE_HOSTCC +void *image_get_host_blob(void); +void image_set_host_blob(void *host_blob); +# define gd_fdt_blob() image_get_host_blob() +#else +# define gd_fdt_blob() (gd->fdt_blob) +#endif + +#ifdef CONFIG_FIT_BEST_MATCH +#define IMAGE_ENABLE_BEST_MATCH 1 +#else +#define IMAGE_ENABLE_BEST_MATCH 0 +#endif +#endif /* IMAGE_ENABLE_FIT */ + +/* + * Information passed to the signing routines + * + * Either 'keydir', 'keyname', or 'keyfile' can be NULL. However, either + * 'keyfile', or both 'keydir' and 'keyname' should have valid values. If + * neither are valid, some operations might fail with EINVAL. + */ +struct image_sign_info { + const char *keydir; /* Directory conaining keys */ + const char *keyname; /* Name of key to use */ + const char *keyfile; /* Filename of private or public key */ + void *fit; /* Pointer to FIT blob */ + int node_offset; /* Offset of signature node */ + const char *name; /* Algorithm name */ + struct checksum_algo *checksum; /* Checksum algorithm information */ + struct padding_algo *padding; /* Padding algorithm information */ + struct crypto_algo *crypto; /* Crypto algorithm information */ + const void *fdt_blob; /* FDT containing public keys */ + int required_keynode; /* Node offset of key to use: -1=any */ + const char *require_keys; /* Value for 'required' property */ + const char *engine_id; /* Engine to use for signing */ + /* + * Note: the following two fields are always valid even w/o + * RSA_VERIFY_WITH_PKEY in order to make sure this structure is + * the same on target and host. Otherwise, vboot test may fail. + */ + const void *key; /* Pointer to public key in DER */ + int keylen; /* Length of public key */ +}; + +/* A part of an image, used for hashing */ +struct image_region { + const void *data; + int size; +}; + +#if IMAGE_ENABLE_VERIFY +# include +#endif +struct checksum_algo { + const char *name; + const int checksum_len; + const int der_len; + const uint8_t *der_prefix; +#if IMAGE_ENABLE_SIGN + const EVP_MD *(*calculate_sign)(void); +#endif + int (*calculate)(const char *name, + const struct image_region region[], + int region_count, uint8_t *checksum); +}; + +struct crypto_algo { + const char *name; /* Name of algorithm */ + const int key_len; + + /** + * sign() - calculate and return signature for given input data + * + * @info: Specifies key and FIT information + * @data: Pointer to the input data + * @data_len: Data length + * @sigp: Set to an allocated buffer holding the signature + * @sig_len: Set to length of the calculated hash + * + * This computes input data signature according to selected algorithm. + * Resulting signature value is placed in an allocated buffer, the + * pointer is returned as *sigp. The length of the calculated + * signature is returned via the sig_len pointer argument. The caller + * should free *sigp. + * + * @return: 0, on success, -ve on error + */ + int (*sign)(struct image_sign_info *info, + const struct image_region region[], + int region_count, uint8_t **sigp, uint *sig_len); + + /** + * add_verify_data() - Add verification information to FDT + * + * Add public key information to the FDT node, suitable for + * verification at run-time. The information added depends on the + * algorithm being used. + * + * @info: Specifies key and FIT information + * @keydest: Destination FDT blob for public key data + * @return: 0, on success, -ve on error + */ + int (*add_verify_data)(struct image_sign_info *info, void *keydest); + + /** + * verify() - Verify a signature against some data + * + * @info: Specifies key and FIT information + * @data: Pointer to the input data + * @data_len: Data length + * @sig: Signature + * @sig_len: Number of bytes in signature + * @return 0 if verified, -ve on error + */ + int (*verify)(struct image_sign_info *info, + const struct image_region region[], int region_count, + uint8_t *sig, uint sig_len); +}; + +struct padding_algo { + const char *name; + int (*verify)(struct image_sign_info *info, + uint8_t *pad, int pad_len, + const uint8_t *hash, int hash_len); +}; + +/** + * image_get_checksum_algo() - Look up a checksum algorithm + * + * @param full_name Name of algorithm in the form "checksum,crypto" + * @return pointer to algorithm information, or NULL if not found + */ +struct checksum_algo *image_get_checksum_algo(const char *full_name); + +/** + * image_get_crypto_algo() - Look up a cryptosystem algorithm + * + * @param full_name Name of algorithm in the form "checksum,crypto" + * @return pointer to algorithm information, or NULL if not found + */ +struct crypto_algo *image_get_crypto_algo(const char *full_name); + +/** + * image_get_padding_algo() - Look up a padding algorithm + * + * @param name Name of padding algorithm + * @return pointer to algorithm information, or NULL if not found + */ +struct padding_algo *image_get_padding_algo(const char *name); + +#if IMAGE_ENABLE_FIT + +/** + * fit_image_verify_required_sigs() - Verify signatures marked as 'required' + * + * @fit: FIT to check + * @image_noffset: Offset of image node to check + * @data: Image data to check + * @size: Size of image data + * @sig_blob: FDT containing public keys + * @no_sigsp: Returns 1 if no signatures were required, and + * therefore nothing was checked. The caller may wish + * to fall back to other mechanisms, or refuse to + * boot. + * @return 0 if all verified ok, <0 on error + */ +int fit_image_verify_required_sigs(const void *fit, int image_noffset, + const char *data, size_t size, const void *sig_blob, + int *no_sigsp); + +/** + * fit_image_check_sig() - Check a single image signature node + * + * @fit: FIT to check + * @noffset: Offset of signature node to check + * @data: Image data to check + * @size: Size of image data + * @required_keynode: Offset in the control FDT of the required key node, + * if any. If this is given, then the image wil not + * pass verification unless that key is used. If this is + * -1 then any signature will do. + * @err_msgp: In the event of an error, this will be pointed to a + * help error string to display to the user. + * @return 0 if all verified ok, <0 on error + */ +int fit_image_check_sig(const void *fit, int noffset, const void *data, + size_t size, int required_keynode, char **err_msgp); + +int fit_image_decrypt_data(const void *fit, + int image_noffset, int cipher_noffset, + const void *data, size_t size, + void **data_unciphered, size_t *size_unciphered); + +/** + * fit_region_make_list() - Make a list of regions to hash + * + * Given a list of FIT regions (offset, size) provided by libfdt, create + * a list of regions (void *, size) for use by the signature creationg + * and verification code. + * + * @fit: FIT image to process + * @fdt_regions: Regions as returned by libfdt + * @count: Number of regions returned by libfdt + * @region: Place to put list of regions (NULL to allocate it) + * @return pointer to list of regions, or NULL if out of memory + */ +struct image_region *fit_region_make_list(const void *fit, + struct fdt_region *fdt_regions, int count, + struct image_region *region); + +static inline int fit_image_check_target_arch(const void *fdt, int node) +{ +#ifndef USE_HOSTCC + return fit_image_check_arch(fdt, node, IH_ARCH_DEFAULT); +#else + return 0; +#endif +} + +/* + * At present we only support ciphering on the host, and unciphering on the + * device + */ +#if defined(USE_HOSTCC) +# if defined(CONFIG_FIT_CIPHER) +# define IMAGE_ENABLE_ENCRYPT 1 +# define IMAGE_ENABLE_DECRYPT 1 +# include +# else +# define IMAGE_ENABLE_ENCRYPT 0 +# define IMAGE_ENABLE_DECRYPT 0 +# endif +#else +# define IMAGE_ENABLE_ENCRYPT 0 +# define IMAGE_ENABLE_DECRYPT CONFIG_IS_ENABLED(FIT_CIPHER) +#endif + +/* Information passed to the ciphering routines */ +struct image_cipher_info { + const char *keydir; /* Directory containing keys */ + const char *keyname; /* Name of key to use */ + const char *ivname; /* Name of IV to use */ + const void *fit; /* Pointer to FIT blob */ + int node_noffset; /* Offset of the cipher node */ + const char *name; /* Algorithm name */ + struct cipher_algo *cipher; /* Cipher algorithm information */ + const void *fdt_blob; /* FDT containing key and IV */ + const void *key; /* Value of the key */ + const void *iv; /* Value of the IV */ + size_t size_unciphered; /* Size of the unciphered data */ +}; + +struct cipher_algo { + const char *name; /* Name of algorithm */ + int key_len; /* Length of the key */ + int iv_len; /* Length of the IV */ + +#if IMAGE_ENABLE_ENCRYPT + const EVP_CIPHER * (*calculate_type)(void); +#endif + + int (*encrypt)(struct image_cipher_info *info, + const unsigned char *data, int data_len, + unsigned char **cipher, int *cipher_len); + + int (*add_cipher_data)(struct image_cipher_info *info, + void *keydest, void *fit, int node_noffset); + + int (*decrypt)(struct image_cipher_info *info, + const void *cipher, size_t cipher_len, + void **data, size_t *data_len); +}; + +int fit_image_cipher_get_algo(const void *fit, int noffset, char **algo); + +struct cipher_algo *image_get_cipher_algo(const char *full_name); + +#ifdef CONFIG_FIT_VERBOSE +#define fit_unsupported(msg) printf("! %s:%d " \ + "FIT images not supported for '%s'\n", \ + __FILE__, __LINE__, (msg)) + +#define fit_unsupported_reset(msg) printf("! %s:%d " \ + "FIT images not supported for '%s' " \ + "- must reset board to recover!\n", \ + __FILE__, __LINE__, (msg)) +#else +#define fit_unsupported(msg) +#define fit_unsupported_reset(msg) +#endif /* CONFIG_FIT_VERBOSE */ +#endif /* CONFIG_FIT */ + +#if !defined(USE_HOSTCC) +#if defined(CONFIG_ANDROID_BOOT_IMAGE) +struct andr_img_hdr; +int android_image_check_header(const struct andr_img_hdr *hdr); +int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, + ulong *os_data, ulong *os_len); +int android_image_get_ramdisk(const struct andr_img_hdr *hdr, + ulong *rd_data, ulong *rd_len); +int android_image_get_second(const struct andr_img_hdr *hdr, + ulong *second_data, ulong *second_len); +bool android_image_get_dtbo(ulong hdr_addr, ulong *addr, u32 *size); +bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr, + u32 *size); +ulong android_image_get_end(const struct andr_img_hdr *hdr); +ulong android_image_get_kload(const struct andr_img_hdr *hdr); +ulong android_image_get_kcomp(const struct andr_img_hdr *hdr); +void android_print_contents(const struct andr_img_hdr *hdr); +#if !defined(CONFIG_SPL_BUILD) +bool android_image_print_dtb_contents(ulong hdr_addr); +#endif + +#endif /* CONFIG_ANDROID_BOOT_IMAGE */ +#endif /* !USE_HOSTCC */ + +/** + * board_fit_config_name_match() - Check for a matching board name + * + * This is used when SPL loads a FIT containing multiple device tree files + * and wants to work out which one to use. The description of each one is + * passed to this function. The description comes from the 'description' field + * in each (FDT) image node. + * + * @name: Device tree description + * @return 0 if this device tree should be used, non-zero to try the next + */ +int board_fit_config_name_match(const char *name); + +/** + * board_fit_image_post_process() - Do any post-process on FIT binary data + * + * This is used to do any sort of image manipulation, verification, decryption + * etc. in a platform or board specific way. Obviously, anything done here would + * need to be comprehended in how the images were prepared before being injected + * into the FIT creation (i.e. the binary blobs would have been pre-processed + * before being added to the FIT image). + * + * @image: pointer to the image start pointer + * @size: pointer to the image size + * @return no return value (failure should be handled internally) + */ +void board_fit_image_post_process(void **p_image, size_t *p_size); + +#define FDT_ERROR ((ulong)(-1)) + +ulong fdt_getprop_u32(const void *fdt, int node, const char *prop); + +/** + * fit_find_config_node() - Find the node for the best DTB in a FIT image + * + * A FIT image contains one or more DTBs. This function parses the + * configurations described in the FIT images and returns the node of + * the first matching DTB. To check if a DTB matches a board, this function + * calls board_fit_config_name_match(). If no matching DTB is found, it returns + * the node described by the default configuration if it exists. + * + * @fdt: pointer to flat device tree + * @return the node if found, -ve otherwise + */ +int fit_find_config_node(const void *fdt); + +/** + * Mapping of image types to function handlers to be invoked on the associated + * loaded images + * + * @type: Type of image, I.E. IH_TYPE_* + * @handler: Function to call on loaded image + */ +struct fit_loadable_tbl { + int type; + /** + * handler() - Process a loaded image + * + * @data: Pointer to start of loaded image data + * @size: Size of loaded image data + */ + void (*handler)(ulong data, size_t size); +}; + +/* + * Define a FIT loadable image type handler + * + * _type is a valid uimage_type ID as defined in the "Image Type" enum above + * _handler is the handler function to call after this image type is loaded + */ +#define U_BOOT_FIT_LOADABLE_HANDLER(_type, _handler) \ + ll_entry_declare(struct fit_loadable_tbl, _function, fit_loadable) = { \ + .type = _type, \ + .handler = _handler, \ + } + +/** + * fit_update - update storage with FIT image + * @fit: Pointer to FIT image + * + * Update firmware on storage using FIT image as input. + * The storage area to be update will be identified by the name + * in FIT and matching it to "dfu_alt_info" variable. + * + * Return: 0 on success, non-zero otherwise + */ +int fit_update(const void *fit); + +#endif /* __IMAGE_H__ */ diff --git a/roms/u-boot/include/imx8image.h b/roms/u-boot/include/imx8image.h new file mode 100644 index 000000000..00c614ab6 --- /dev/null +++ b/roms/u-boot/include/imx8image.h @@ -0,0 +1,272 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + * + * Peng Fan + */ + +#ifndef _IMX8IMAGE_H_ +#define _IMX8IMAGE_H_ + +#include +#include +#include "imagetool.h" + +#define __packed __attribute__((packed)) + +#define IV_MAX_LEN 32 +#define HASH_MAX_LEN 64 +#define MAX_NUM_IMGS 6 +#define MAX_NUM_SRK_RECORDS 4 + +#define IVT_HEADER_TAG_B0 0x87 +#define IVT_VERSION_B0 0x00 + +#define IMG_FLAG_HASH_SHA256 0x000 +#define IMG_FLAG_HASH_SHA384 0x100 +#define IMG_FLAG_HASH_SHA512 0x200 + +#define IMG_FLAG_ENCRYPTED_MASK 0x400 +#define IMG_FLAG_ENCRYPTED_SHIFT 0x0A + +#define IMG_FLAG_BOOTFLAGS_MASK 0xFFFF0000 +#define IMG_FLAG_BOOTFLAGS_SHIFT 0x10 + +#define IMG_ARRAY_ENTRY_SIZE 128 +#define HEADER_IMG_ARRAY_OFFSET 0x10 + +#define HASH_TYPE_SHA_256 256 +#define HASH_TYPE_SHA_384 384 +#define HASH_TYPE_SHA_512 512 + +#define IMAGE_HASH_ALGO_DEFAULT 384 +#define IMAGE_PADDING_DEFAULT 0x1000 + +#define DCD_ENTRY_ADDR_IN_SCFW 0x240 + +#define CONTAINER_ALIGNMENT 0x400 +#define CONTAINER_FLAGS_DEFAULT 0x10 +#define CONTAINER_FUSE_DEFAULT 0x0 + +#define SIGNATURE_BLOCK_HEADER_LENGTH 0x10 + +#define MAX_NUM_OF_CONTAINER 2 + +#define FIRST_CONTAINER_HEADER_LENGTH 0x400 + +#define BOOT_IMG_META_MU_RID_SHIFT 10 +#define BOOT_IMG_META_PART_ID_SHIFT 20 + +#define IMAGE_A35_DEFAULT_META(PART) (((PART == 0) ? \ + PARTITION_ID_AP : PART) << \ + BOOT_IMG_META_PART_ID_SHIFT | \ + SC_R_MU_0A << \ + BOOT_IMG_META_MU_RID_SHIFT | \ + SC_R_A35_0) + +#define IMAGE_A53_DEFAULT_META(PART) (((PART == 0) ? \ + PARTITION_ID_AP : PART) << \ + BOOT_IMG_META_PART_ID_SHIFT | \ + SC_R_MU_0A << \ + BOOT_IMG_META_MU_RID_SHIFT | \ + SC_R_A53_0) + +#define IMAGE_A72_DEFAULT_META(PART) (((PART == 0) ? \ + PARTITION_ID_AP : PART) << \ + BOOT_IMG_META_PART_ID_SHIFT | \ + SC_R_MU_0A << \ + BOOT_IMG_META_MU_RID_SHIFT | \ + SC_R_A72_0) + +#define IMAGE_M4_0_DEFAULT_META(PART) (((PART == 0) ? \ + PARTITION_ID_M4 : PART) << \ + BOOT_IMG_META_PART_ID_SHIFT | \ + SC_R_M4_0_MU_1A << \ + BOOT_IMG_META_MU_RID_SHIFT | \ + SC_R_M4_0_PID0) + +#define IMAGE_M4_1_DEFAULT_META(PART) (((PART == 0) ? \ + PARTITION_ID_M4 : PART) << \ + BOOT_IMG_META_PART_ID_SHIFT | \ + SC_R_M4_1_MU_1A << \ + BOOT_IMG_META_MU_RID_SHIFT | \ + SC_R_M4_1_PID0) + +#define CONTAINER_IMAGE_ARRAY_START_OFFSET 0x2000 + +typedef struct { + uint8_t version; + uint16_t length; + uint8_t tag; + uint16_t srk_table_offset; + uint16_t cert_offset; + uint16_t blob_offset; + uint16_t signature_offset; + uint32_t reserved; +} __packed sig_blk_hdr_t; + +typedef struct { + uint32_t offset; + uint32_t size; + uint64_t dst; + uint64_t entry; + uint32_t hab_flags; + uint32_t meta; + uint8_t hash[HASH_MAX_LEN]; + uint8_t iv[IV_MAX_LEN]; +} __packed boot_img_t; + +typedef struct { + uint8_t version; + uint16_t length; + uint8_t tag; + uint32_t flags; + uint16_t sw_version; + uint8_t fuse_version; + uint8_t num_images; + uint16_t sig_blk_offset; + uint16_t reserved; + boot_img_t img[MAX_NUM_IMGS]; + sig_blk_hdr_t sig_blk_hdr; + uint32_t sigblk_size; + uint32_t padding; +} __packed flash_header_v3_t; + +typedef struct { + flash_header_v3_t fhdr[MAX_NUM_OF_CONTAINER]; +} __packed imx_header_v3_t; + +struct image_array { + char *name; + unsigned int core_type; + unsigned int core_id; + unsigned int load_addr; +}; + +enum imx8image_cmd { + CMD_INVALID, + CMD_BOOT_FROM, + CMD_FUSE_VERSION, + CMD_SW_VERSION, + CMD_MSG_BLOCK, + CMD_FILEOFF, + CMD_FLAG, + CMD_APPEND, + CMD_PARTITION, + CMD_SOC_TYPE, + CMD_CONTAINER, + CMD_IMAGE, + CMD_DATA +}; + +enum imx8image_core_type { + CFG_CORE_INVALID, + CFG_SCU, + CFG_M40, + CFG_M41, + CFG_A35, + CFG_A53, + CFG_A72 +}; + +enum imx8image_fld_types { + CFG_INVALID = -1, + CFG_COMMAND, + CFG_CORE_TYPE, + CFG_IMAGE_NAME, + CFG_LOAD_ADDR +}; + +typedef enum SOC_TYPE { + NONE = 0, + QX, + QM +} soc_type_t; + +typedef enum option_type { + NO_IMG = 0, + DCD, + SCFW, + SECO, + M40, + M41, + AP, + OUTPUT, + SCD, + CSF, + FLAG, + DEVICE, + NEW_CONTAINER, + APPEND, + DATA, + PARTITION, + FILEOFF, + MSG_BLOCK +} option_type_t; + +typedef struct { + option_type_t option; + char *filename; + uint64_t src; + uint64_t dst; + uint64_t entry; + uint64_t ext; +} image_t; + +#define CORE_SC 1 +#define CORE_CM4_0 2 +#define CORE_CM4_1 3 +#define CORE_CA53 4 +#define CORE_CA35 4 +#define CORE_CA72 5 +#define CORE_SECO 6 + +#define SC_R_OTP 357U +#define SC_R_DEBUG 354U +#define SC_R_ROM_0 236U + +#define MSG_DEBUG_EN SC_R_DEBUG +#define MSG_FUSE SC_R_OTP +#define MSG_FIELD SC_R_ROM_0 + +#define IMG_TYPE_CSF 0x01 /* CSF image type */ +#define IMG_TYPE_SCD 0x02 /* SCD image type */ +#define IMG_TYPE_EXEC 0x03 /* Executable image type */ +#define IMG_TYPE_DATA 0x04 /* Data image type */ +#define IMG_TYPE_DCD_DDR 0x05 /* DCD/DDR image type */ +#define IMG_TYPE_SECO 0x06 /* SECO image type */ +#define IMG_TYPE_PROV 0x07 /* Provisioning image type */ +#define IMG_TYPE_DEK 0x08 /* DEK validation type */ + +#define IMG_TYPE_SHIFT 0 +#define IMG_TYPE_MASK 0x1f +#define IMG_TYPE(x) (((x) & IMG_TYPE_MASK) >> IMG_TYPE_SHIFT) + +#define BOOT_IMG_FLAGS_CORE_MASK 0xF +#define BOOT_IMG_FLAGS_CORE_SHIFT 0x04 +#define BOOT_IMG_FLAGS_CPU_RID_MASK 0x3FF0 +#define BOOT_IMG_FLAGS_CPU_RID_SHIFT 4 +#define BOOT_IMG_FLAGS_MU_RID_MASK 0xFFC000 +#define BOOT_IMG_FLAGS_MU_RID_SHIFT 14 +#define BOOT_IMG_FLAGS_PARTITION_ID_MASK 0x1F000000 +#define BOOT_IMG_FLAGS_PARTITION_ID_SHIFT 24 + +/* Resource id used in scfw */ +#define SC_R_A35_0 508 +#define SC_R_A53_0 1 +#define SC_R_A72_0 6 +#define SC_R_MU_0A 213 +#define SC_R_M4_0_PID0 278 +#define SC_R_M4_0_MU_1A 297 +#define SC_R_M4_1_PID0 298 +#define SC_R_M4_1_MU_1A 317 +#define PARTITION_ID_M4 0 +#define PARTITION_ID_AP 1 + +#define IMG_STACK_SIZE 32 + +#define append(p, s, l) do { \ + memcpy((p), (uint8_t *)(s), (l)); (p) += (l); \ + } while (0) + +#endif diff --git a/roms/u-boot/include/imx_lpi2c.h b/roms/u-boot/include/imx_lpi2c.h new file mode 100644 index 000000000..3ce9edaf1 --- /dev/null +++ b/roms/u-boot/include/imx_lpi2c.h @@ -0,0 +1,523 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Freescale Semiconductors, Inc. + * + * I2CLP driver for i.MX + * + */ +#ifndef __IMX_LPI2C_H__ +#define __IMX_LPI2C_H__ + +#include + +struct imx_lpi2c_bus { + int index; + ulong base; + ulong driver_data; + int speed; + struct i2c_pads_info *pads_info; + struct udevice *bus; + struct clk per_clk; + struct clk ipg_clk; +}; + +struct imx_lpi2c_reg { + u32 verid; + u32 param; + u8 reserved_0[8]; + u32 mcr; + u32 msr; + u32 mier; + u32 mder; + u32 mcfgr0; + u32 mcfgr1; + u32 mcfgr2; + u32 mcfgr3; + u8 reserved_1[16]; + u32 mdmr; + u8 reserved_2[4]; + u32 mccr0; + u8 reserved_3[4]; + u32 mccr1; + u8 reserved_4[4]; + u32 mfcr; + u32 mfsr; + u32 mtdr; + u8 reserved_5[12]; + u32 mrdr; + u8 reserved_6[156]; + u32 scr; + u32 ssr; + u32 sier; + u32 sder; + u8 reserved_7[4]; + u32 scfgr1; + u32 scfgr2; + u8 reserved_8[20]; + u32 samr; + u8 reserved_9[12]; + u32 sasr; + u32 star; + u8 reserved_10[8]; + u32 stdr; + u8 reserved_11[12]; + u32 srdr; +}; + +typedef enum lpi2c_status { + LPI2C_SUCESS = 0, + LPI2C_END_PACKET_ERR, + LPI2C_STOP_ERR, + LPI2C_NAK_ERR, + LPI2C_ARB_LOST_ERR, + LPI2C_FIFO_ERR, + LPI2C_PIN_LOW_TIMEOUT_ERR, + LPI2C_DATA_MATCH_ERR, + LPI2C_BUSY, + LPI2C_IDLE, + LPI2C_BIT_ERR, + LPI2C_NO_TRANS_PROG, + LPI2C_DMA_REQ_FAIL, +} lpi2c_status_t; + +/* ---------------------------------------------------------------------------- + -- LPI2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Register_Masks LPI2C Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) +#define LPI2C_VERID_FEATURE_SHIFT (0U) +#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) +#define LPI2C_VERID_MINOR_MASK (0xFF0000U) +#define LPI2C_VERID_MINOR_SHIFT (16U) +#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) +#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) +#define LPI2C_VERID_MAJOR_SHIFT (24U) +#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) + +/*! @name PARAM - Parameter Register */ +#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) +#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) +#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) +#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) +#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) +#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) + +/*! @name MCR - Master Control Register */ +#define LPI2C_MCR_MEN_MASK (0x1U) +#define LPI2C_MCR_MEN_SHIFT (0U) +#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) +#define LPI2C_MCR_RST_MASK (0x2U) +#define LPI2C_MCR_RST_SHIFT (1U) +#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) +#define LPI2C_MCR_DOZEN_MASK (0x4U) +#define LPI2C_MCR_DOZEN_SHIFT (2U) +#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) +#define LPI2C_MCR_DBGEN_MASK (0x8U) +#define LPI2C_MCR_DBGEN_SHIFT (3U) +#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) +#define LPI2C_MCR_RTF_MASK (0x100U) +#define LPI2C_MCR_RTF_SHIFT (8U) +#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) +#define LPI2C_MCR_RRF_MASK (0x200U) +#define LPI2C_MCR_RRF_SHIFT (9U) +#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) + +/*! @name MSR - Master Status Register */ +#define LPI2C_MSR_TDF_MASK (0x1U) +#define LPI2C_MSR_TDF_SHIFT (0U) +#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) +#define LPI2C_MSR_RDF_MASK (0x2U) +#define LPI2C_MSR_RDF_SHIFT (1U) +#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) +#define LPI2C_MSR_EPF_MASK (0x100U) +#define LPI2C_MSR_EPF_SHIFT (8U) +#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) +#define LPI2C_MSR_SDF_MASK (0x200U) +#define LPI2C_MSR_SDF_SHIFT (9U) +#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) +#define LPI2C_MSR_NDF_MASK (0x400U) +#define LPI2C_MSR_NDF_SHIFT (10U) +#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) +#define LPI2C_MSR_ALF_MASK (0x800U) +#define LPI2C_MSR_ALF_SHIFT (11U) +#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) +#define LPI2C_MSR_FEF_MASK (0x1000U) +#define LPI2C_MSR_FEF_SHIFT (12U) +#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) +#define LPI2C_MSR_PLTF_MASK (0x2000U) +#define LPI2C_MSR_PLTF_SHIFT (13U) +#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) +#define LPI2C_MSR_DMF_MASK (0x4000U) +#define LPI2C_MSR_DMF_SHIFT (14U) +#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) +#define LPI2C_MSR_MBF_MASK (0x1000000U) +#define LPI2C_MSR_MBF_SHIFT (24U) +#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) +#define LPI2C_MSR_BBF_MASK (0x2000000U) +#define LPI2C_MSR_BBF_SHIFT (25U) +#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) + +/*! @name MIER - Master Interrupt Enable Register */ +#define LPI2C_MIER_TDIE_MASK (0x1U) +#define LPI2C_MIER_TDIE_SHIFT (0U) +#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) +#define LPI2C_MIER_RDIE_MASK (0x2U) +#define LPI2C_MIER_RDIE_SHIFT (1U) +#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) +#define LPI2C_MIER_EPIE_MASK (0x100U) +#define LPI2C_MIER_EPIE_SHIFT (8U) +#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) +#define LPI2C_MIER_SDIE_MASK (0x200U) +#define LPI2C_MIER_SDIE_SHIFT (9U) +#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) +#define LPI2C_MIER_NDIE_MASK (0x400U) +#define LPI2C_MIER_NDIE_SHIFT (10U) +#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) +#define LPI2C_MIER_ALIE_MASK (0x800U) +#define LPI2C_MIER_ALIE_SHIFT (11U) +#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) +#define LPI2C_MIER_FEIE_MASK (0x1000U) +#define LPI2C_MIER_FEIE_SHIFT (12U) +#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) +#define LPI2C_MIER_PLTIE_MASK (0x2000U) +#define LPI2C_MIER_PLTIE_SHIFT (13U) +#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) +#define LPI2C_MIER_DMIE_MASK (0x4000U) +#define LPI2C_MIER_DMIE_SHIFT (14U) +#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) + +/*! @name MDER - Master DMA Enable Register */ +#define LPI2C_MDER_TDDE_MASK (0x1U) +#define LPI2C_MDER_TDDE_SHIFT (0U) +#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) +#define LPI2C_MDER_RDDE_MASK (0x2U) +#define LPI2C_MDER_RDDE_SHIFT (1U) +#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) + +/*! @name MCFGR0 - Master Configuration Register 0 */ +#define LPI2C_MCFGR0_HREN_MASK (0x1U) +#define LPI2C_MCFGR0_HREN_SHIFT (0U) +#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) +#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) +#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) +#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) +#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) +#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) +#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) +#define LPI2C_MCFGR0_RDMO_MASK (0x200U) +#define LPI2C_MCFGR0_RDMO_SHIFT (9U) +#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) + +/*! @name MCFGR1 - Master Configuration Register 1 */ +#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) +#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) +#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) +#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) +#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) +#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) +#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) +#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) +#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) +#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) +#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) +#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) + +/*! @name MCFGR2 - Master Configuration Register 2 */ +#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) +#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) +#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) +#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) +#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) +#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) +#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) + +/*! @name MCFGR3 - Master Configuration Register 3 */ +#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) +#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) +#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) + +/*! @name MDMR - Master Data Match Register */ +#define LPI2C_MDMR_MATCH0_MASK (0xFFU) +#define LPI2C_MDMR_MATCH0_SHIFT (0U) +#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) +#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) +#define LPI2C_MDMR_MATCH1_SHIFT (16U) +#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) + +/*! @name MCCR0 - Master Clock Configuration Register 0 */ +#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR0_CLKLO_SHIFT (0U) +#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) +#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR0_CLKHI_SHIFT (8U) +#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) +#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) +#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) +#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR0_DATAVD_SHIFT (24U) +#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) + +/*! @name MCCR1 - Master Clock Configuration Register 1 */ +#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR1_CLKLO_SHIFT (0U) +#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) +#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR1_CLKHI_SHIFT (8U) +#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) +#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) +#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) +#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR1_DATAVD_SHIFT (24U) +#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) + +/*! @name MFCR - Master FIFO Control Register */ +#define LPI2C_MFCR_TXWATER_MASK (0xFFU) +#define LPI2C_MFCR_TXWATER_SHIFT (0U) +#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) +#define LPI2C_MFCR_RXWATER_MASK (0xFF0000U) +#define LPI2C_MFCR_RXWATER_SHIFT (16U) +#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) + +/*! @name MFSR - Master FIFO Status Register */ +#define LPI2C_MFSR_TXCOUNT_MASK (0xFFU) +#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) +#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) +#define LPI2C_MFSR_RXCOUNT_MASK (0xFF0000U) +#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) +#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) + +/*! @name MTDR - Master Transmit Data Register */ +#define LPI2C_MTDR_DATA_MASK (0xFFU) +#define LPI2C_MTDR_DATA_SHIFT (0U) +#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) +#define LPI2C_MTDR_CMD_MASK (0x700U) +#define LPI2C_MTDR_CMD_SHIFT (8U) +#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) + +/*! @name MRDR - Master Receive Data Register */ +#define LPI2C_MRDR_DATA_MASK (0xFFU) +#define LPI2C_MRDR_DATA_SHIFT (0U) +#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) +#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) + +/*! @name SCR - Slave Control Register */ +#define LPI2C_SCR_SEN_MASK (0x1U) +#define LPI2C_SCR_SEN_SHIFT (0U) +#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) +#define LPI2C_SCR_RST_MASK (0x2U) +#define LPI2C_SCR_RST_SHIFT (1U) +#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) +#define LPI2C_SCR_FILTEN_MASK (0x10U) +#define LPI2C_SCR_FILTEN_SHIFT (4U) +#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) +#define LPI2C_SCR_FILTDZ_MASK (0x20U) +#define LPI2C_SCR_FILTDZ_SHIFT (5U) +#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) +#define LPI2C_SCR_RTF_MASK (0x100U) +#define LPI2C_SCR_RTF_SHIFT (8U) +#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) +#define LPI2C_SCR_RRF_MASK (0x200U) +#define LPI2C_SCR_RRF_SHIFT (9U) +#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) + +/*! @name SSR - Slave Status Register */ +#define LPI2C_SSR_TDF_MASK (0x1U) +#define LPI2C_SSR_TDF_SHIFT (0U) +#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) +#define LPI2C_SSR_RDF_MASK (0x2U) +#define LPI2C_SSR_RDF_SHIFT (1U) +#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) +#define LPI2C_SSR_AVF_MASK (0x4U) +#define LPI2C_SSR_AVF_SHIFT (2U) +#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) +#define LPI2C_SSR_TAF_MASK (0x8U) +#define LPI2C_SSR_TAF_SHIFT (3U) +#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) +#define LPI2C_SSR_RSF_MASK (0x100U) +#define LPI2C_SSR_RSF_SHIFT (8U) +#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) +#define LPI2C_SSR_SDF_MASK (0x200U) +#define LPI2C_SSR_SDF_SHIFT (9U) +#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) +#define LPI2C_SSR_BEF_MASK (0x400U) +#define LPI2C_SSR_BEF_SHIFT (10U) +#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) +#define LPI2C_SSR_FEF_MASK (0x800U) +#define LPI2C_SSR_FEF_SHIFT (11U) +#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) +#define LPI2C_SSR_AM0F_MASK (0x1000U) +#define LPI2C_SSR_AM0F_SHIFT (12U) +#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) +#define LPI2C_SSR_AM1F_MASK (0x2000U) +#define LPI2C_SSR_AM1F_SHIFT (13U) +#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) +#define LPI2C_SSR_GCF_MASK (0x4000U) +#define LPI2C_SSR_GCF_SHIFT (14U) +#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) +#define LPI2C_SSR_SARF_MASK (0x8000U) +#define LPI2C_SSR_SARF_SHIFT (15U) +#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) +#define LPI2C_SSR_SBF_MASK (0x1000000U) +#define LPI2C_SSR_SBF_SHIFT (24U) +#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) +#define LPI2C_SSR_BBF_MASK (0x2000000U) +#define LPI2C_SSR_BBF_SHIFT (25U) +#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) + +/*! @name SIER - Slave Interrupt Enable Register */ +#define LPI2C_SIER_TDIE_MASK (0x1U) +#define LPI2C_SIER_TDIE_SHIFT (0U) +#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) +#define LPI2C_SIER_RDIE_MASK (0x2U) +#define LPI2C_SIER_RDIE_SHIFT (1U) +#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) +#define LPI2C_SIER_AVIE_MASK (0x4U) +#define LPI2C_SIER_AVIE_SHIFT (2U) +#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) +#define LPI2C_SIER_TAIE_MASK (0x8U) +#define LPI2C_SIER_TAIE_SHIFT (3U) +#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) +#define LPI2C_SIER_RSIE_MASK (0x100U) +#define LPI2C_SIER_RSIE_SHIFT (8U) +#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) +#define LPI2C_SIER_SDIE_MASK (0x200U) +#define LPI2C_SIER_SDIE_SHIFT (9U) +#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) +#define LPI2C_SIER_BEIE_MASK (0x400U) +#define LPI2C_SIER_BEIE_SHIFT (10U) +#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) +#define LPI2C_SIER_FEIE_MASK (0x800U) +#define LPI2C_SIER_FEIE_SHIFT (11U) +#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) +#define LPI2C_SIER_AM0IE_MASK (0x1000U) +#define LPI2C_SIER_AM0IE_SHIFT (12U) +#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) +#define LPI2C_SIER_AM1F_MASK (0x2000U) +#define LPI2C_SIER_AM1F_SHIFT (13U) +#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) +#define LPI2C_SIER_GCIE_MASK (0x4000U) +#define LPI2C_SIER_GCIE_SHIFT (14U) +#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) +#define LPI2C_SIER_SARIE_MASK (0x8000U) +#define LPI2C_SIER_SARIE_SHIFT (15U) +#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) + +/*! @name SDER - Slave DMA Enable Register */ +#define LPI2C_SDER_TDDE_MASK (0x1U) +#define LPI2C_SDER_TDDE_SHIFT (0U) +#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) +#define LPI2C_SDER_RDDE_MASK (0x2U) +#define LPI2C_SDER_RDDE_SHIFT (1U) +#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) +#define LPI2C_SDER_AVDE_MASK (0x4U) +#define LPI2C_SDER_AVDE_SHIFT (2U) +#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) + +/*! @name SCFGR1 - Slave Configuration Register 1 */ +#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) +#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) +#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) +#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) +#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) +#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) +#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) +#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) +#define LPI2C_SCFGR1_GCEN_MASK (0x100U) +#define LPI2C_SCFGR1_GCEN_SHIFT (8U) +#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) +#define LPI2C_SCFGR1_SAEN_MASK (0x200U) +#define LPI2C_SCFGR1_SAEN_SHIFT (9U) +#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) +#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) +#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) +#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) +#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) +#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) +#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) +#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) +#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) +#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) +#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) + +/*! @name SCFGR2 - Slave Configuration Register 2 */ +#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) +#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) +#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) +#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) +#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) +#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) +#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) +#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) +#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) +#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) + +/*! @name SAMR - Slave Address Match Register */ +#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) +#define LPI2C_SAMR_ADDR0_SHIFT (1U) +#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) +#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) +#define LPI2C_SAMR_ADDR1_SHIFT (17U) +#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) + +/*! @name SASR - Slave Address Status Register */ +#define LPI2C_SASR_RADDR_MASK (0x7FFU) +#define LPI2C_SASR_RADDR_SHIFT (0U) +#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) +#define LPI2C_SASR_ANV_MASK (0x4000U) +#define LPI2C_SASR_ANV_SHIFT (14U) +#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) + +/*! @name STAR - Slave Transmit ACK Register */ +#define LPI2C_STAR_TXNACK_MASK (0x1U) +#define LPI2C_STAR_TXNACK_SHIFT (0U) +#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) + +/*! @name STDR - Slave Transmit Data Register */ +#define LPI2C_STDR_DATA_MASK (0xFFU) +#define LPI2C_STDR_DATA_SHIFT (0U) +#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) + +/*! @name SRDR - Slave Receive Data Register */ +#define LPI2C_SRDR_DATA_MASK (0xFFU) +#define LPI2C_SRDR_DATA_SHIFT (0U) +#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) +#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) +#define LPI2C_SRDR_SOF_MASK (0x8000U) +#define LPI2C_SRDR_SOF_SHIFT (15U) +#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) + +#endif /* __ASM_ARCH_IMX_I2C_H__ */ diff --git a/roms/u-boot/include/imx_sip.h b/roms/u-boot/include/imx_sip.h new file mode 100644 index 000000000..26dbe0421 --- /dev/null +++ b/roms/u-boot/include/imx_sip.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + */ + +#ifndef _IMX_SIP_H__ +#define _IMX_SIP_H_ + +#define IMX_SIP_GPC 0xC2000000 +#define IMX_SIP_GPC_PM_DOMAIN 0x03 + +#define IMX_SIP_BUILDINFO 0xC2000003 +#define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00 + +#define IMX_SIP_SRC 0xC2000005 +#define IMX_SIP_SRC_M4_START 0x00 +#define IMX_SIP_SRC_M4_STARTED 0x01 + +#endif diff --git a/roms/u-boot/include/imx_thermal.h b/roms/u-boot/include/imx_thermal.h new file mode 100644 index 000000000..6f32cb50b --- /dev/null +++ b/roms/u-boot/include/imx_thermal.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * + * (C) Copyright 2014 Freescale Semiconductor, Inc + */ + +#ifndef _IMX_THERMAL_H_ +#define _IMX_THERMAL_H_ + +/* CPU Temperature Grades */ +#define TEMP_COMMERCIAL 0 +#define TEMP_EXTCOMMERCIAL 1 +#define TEMP_INDUSTRIAL 2 +#define TEMP_AUTOMOTIVE 3 + +struct imx_thermal_plat { + void *regs; + int fuse_bank; + int fuse_word; +}; + +#endif /* _IMX_THERMAL_H_ */ diff --git a/roms/u-boot/include/imximage.h b/roms/u-boot/include/imximage.h new file mode 100644 index 000000000..1ed3284f1 --- /dev/null +++ b/roms/u-boot/include/imximage.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + */ + +#ifndef _IMXIMAGE_H_ +#define _IMXIMAGE_H_ + +#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */ +#define MAX_PLUGIN_CODE_SIZE (64 * 1024) +#define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */ +#define APP_CODE_BARKER 0xB1 +#define DCD_BARKER 0xB17219E9 + +/* Specify the offset of the IVT in the IMX header as expected by BootROM */ +#define BOOTROM_IVT_HDR_OFFSET 0xC00 + +/* + * NOTE: This file must be kept in sync with arch/arm/include/asm/\ + * mach-imx/imximage.cfg because tools/imximage.c can not + * cross-include headers from arch/arm/ and vice-versa. + */ +#define CMD_DATA_STR "DATA" + +/* Initial Vector Table Offset */ +#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF +#define FLASH_OFFSET_STANDARD 0x400 +#define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD +#define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD +#define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD +#define FLASH_OFFSET_ONENAND 0x100 +#define FLASH_OFFSET_NOR 0x1000 +#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD +#define FLASH_OFFSET_QSPI 0x1000 +#define FLASH_OFFSET_FLEXSPI 0x1000 + +/* Initial Load Region Size */ +#define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF +#define FLASH_LOADSIZE_STANDARD 0x1000 +#define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD +#define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD +#define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD +#define FLASH_LOADSIZE_ONENAND 0x400 +#define FLASH_LOADSIZE_NOR 0x0 /* entire image */ +#define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD +#define FLASH_LOADSIZE_QSPI 0x0 /* entire image */ + +/* Command tags and parameters */ +#define IVT_HEADER_TAG 0xD1 +#define IVT_VERSION 0x40 +#define IVT_VERSION_V3 0x41 +#define DCD_HEADER_TAG 0xD2 +#define DCD_VERSION 0x40 +#define DCD_WRITE_DATA_COMMAND_TAG 0xCC +#define DCD_WRITE_DATA_PARAM 0x4 +#define DCD_WRITE_CLR_BIT_PARAM 0xC +#define DCD_WRITE_SET_BIT_PARAM 0x1C +#define DCD_CHECK_DATA_COMMAND_TAG 0xCF +#define DCD_CHECK_BITS_SET_PARAM 0x14 +#define DCD_CHECK_BITS_CLR_PARAM 0x04 + +#ifndef __ASSEMBLY__ +enum imximage_cmd { + CMD_INVALID, + CMD_IMAGE_VERSION, + CMD_BOOT_FROM, + CMD_BOOT_OFFSET, + CMD_WRITE_DATA, + CMD_WRITE_CLR_BIT, + CMD_WRITE_SET_BIT, + CMD_CHECK_BITS_SET, + CMD_CHECK_BITS_CLR, + CMD_CSF, + CMD_PLUGIN, + /* Following on i.MX8MQ/MM */ + CMD_FIT, + CMD_SIGNED_HDMI, + CMD_LOADER, + CMD_SECOND_LOADER, + CMD_DDR_FW, + CMD_ROM_VERSION, +}; + +enum imximage_fld_types { + CFG_INVALID = -1, + CFG_COMMAND, + CFG_REG_SIZE, + CFG_REG_ADDRESS, + CFG_REG_VALUE +}; + +enum imximage_version { + IMXIMAGE_VER_INVALID = -1, + IMXIMAGE_V1 = 1, + IMXIMAGE_V2, + IMXIMAGE_V3 +}; + +typedef struct { + uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */ + uint32_t addr; /* Address to write to */ + uint32_t value; /* Data to write */ +} dcd_type_addr_data_t; + +typedef struct { + uint32_t barker; /* Barker for sanity check */ + uint32_t length; /* Device configuration length (without preamble) */ +} dcd_preamble_t; + +typedef struct { + dcd_preamble_t preamble; + dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1]; +} dcd_v1_t; + +typedef struct { + uint32_t app_code_jump_vector; + uint32_t app_code_barker; + uint32_t app_code_csf; + uint32_t dcd_ptr_ptr; + uint32_t super_root_key; + uint32_t dcd_ptr; + uint32_t app_dest_ptr; +} flash_header_v1_t; + +typedef struct { + uint32_t length; /* Length of data to be read from flash */ +} flash_cfg_parms_t; + +typedef struct { + flash_header_v1_t fhdr; + dcd_v1_t dcd_table; + flash_cfg_parms_t ext_header; +} imx_header_v1_t; + +typedef struct { + uint32_t addr; + uint32_t value; +} dcd_addr_data_t; + +typedef struct { + uint8_t tag; + uint16_t length; + uint8_t version; +} __attribute__((packed)) ivt_header_t; + +typedef struct { + uint8_t tag; + uint16_t length; + uint8_t param; +} __attribute__((packed)) write_dcd_command_t; + +struct dcd_v2_cmd { + write_dcd_command_t write_dcd_command; + dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2]; +}; + +typedef struct { + ivt_header_t header; + struct dcd_v2_cmd dcd_cmd; + uint32_t padding[1]; /* end up on an 8-byte boundary */ +} dcd_v2_t; + +typedef struct { + uint32_t start; + uint32_t size; + uint32_t plugin; +} boot_data_t; + +typedef struct { + ivt_header_t header; + uint32_t entry; + uint32_t reserved1; + uint32_t dcd_ptr; + uint32_t boot_data_ptr; + uint32_t self; + uint32_t csf; + uint32_t reserved2; +} flash_header_v2_t; + +typedef struct { + flash_header_v2_t fhdr; + boot_data_t boot_data; + union { + dcd_v2_t dcd_table; + char plugin_code[MAX_PLUGIN_CODE_SIZE]; + } data; +} imx_header_v2_t; + +typedef struct { + flash_header_v2_t fhdr; + boot_data_t boot_data; + uint32_t padding[5]; +} imx_header_v3_t; + +/* The header must be aligned to 4k on MX53 for NAND boot */ +struct imx_header { + union { + imx_header_v1_t hdr_v1; + imx_header_v2_t hdr_v2; + } header; +}; + +typedef void (*set_dcd_val_t)(struct imx_header *imxhdr, + char *name, int lineno, + int fld, uint32_t value, + uint32_t off); + +typedef void (*set_dcd_param_t)(struct imx_header *imxhdr, uint32_t dcd_len, + int32_t cmd); + +typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr, + uint32_t dcd_len, + char *name, int lineno); + +typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len, + uint32_t entry_point, uint32_t flash_offset); + +#endif /* __ASSEMBLY__ */ +#endif /* _IMXIMAGE_H_ */ diff --git a/roms/u-boot/include/init.h b/roms/u-boot/include/init.h new file mode 100644 index 000000000..fd51d7f96 --- /dev/null +++ b/roms/u-boot/include/init.h @@ -0,0 +1,341 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copy the startup prototype, previously defined in common.h + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#ifndef __INIT_H_ +#define __INIT_H_ 1 + +#ifndef __ASSEMBLY__ /* put C only stuff in this section */ + +#include + +/* Avoid using CONFIG_EFI_STUB directly as we may boot from other loaders */ +#ifdef CONFIG_EFI_STUB +#define ll_boot_init() false +#else +#include + +#define ll_boot_init() (!(gd->flags & GD_FLG_SKIP_LL_INIT)) +#endif + +/* + * Function Prototypes + */ + +/* common/board_f.c */ +void board_init_f(ulong dummy); + +/** + * arch_cpu_init() - basic cpu-dependent setup for an architecture + * + * This is called after early malloc is available. It should handle any + * CPU- or SoC- specific init needed to continue the init sequence. See + * board_f.c for where it is called. If this is not provided, a default + * version (which does nothing) will be used. + * + * Return: 0 on success, otherwise error + */ +int arch_cpu_init(void); + +/** + * arch_cpu_init_dm() - init CPU after driver model is available + * + * This is called immediately after driver model is available before + * relocation. This is similar to arch_cpu_init() but is able to reference + * devices + * + * Return: 0 if OK, -ve on error + */ +int arch_cpu_init_dm(void); + +/** + * mach_cpu_init() - SoC/machine dependent CPU setup + * + * This is called after arch_cpu_init(). It should handle any + * SoC or machine specific init needed to continue the init sequence. See + * board_f.c for where it is called. If this is not provided, a default + * version (which does nothing) will be used. + * + * Return: 0 on success, otherwise error + */ +int mach_cpu_init(void); + +/** + * arch_fsp_init() - perform firmware support package init + * + * Where U-Boot relies on binary blobs to handle part of the system init, this + * function can be used to set up the blobs. This is used on some Intel + * platforms. + * + * Return: 0 + */ +int arch_fsp_init(void); + +/** + * arch_fsp_init() - perform post-relocation firmware support package init + * + * Where U-Boot relies on binary blobs to handle part of the system init, this + * function can be used to set up the blobs. This is used on some Intel + * platforms. + * + * Return: 0 + */ +int arch_fsp_init_r(void); + +int dram_init(void); + +/** + * dram_init_banksize() - Set up DRAM bank sizes + * + * This can be implemented by boards to set up the DRAM bank information in + * gd->bd->bi_dram(). It is called just before relocation, after dram_init() + * is called. + * + * If this is not provided, a default implementation will try to set up a + * single bank. It will do this if CONFIG_NR_DRAM_BANKS and + * CONFIG_SYS_SDRAM_BASE are set. The bank will have a start address of + * CONFIG_SYS_SDRAM_BASE and the size will be determined by a call to + * get_effective_memsize(). + * + * Return: 0 if OK, -ve on error + */ +int dram_init_banksize(void); + +long get_ram_size(long *base, long size); +phys_size_t get_effective_memsize(void); + +int testdram(void); + +/** + * arch_reserve_stacks() - Reserve all necessary stacks + * + * This is used in generic board init sequence in common/board_f.c. Each + * architecture could provide this function to tailor the required stacks. + * + * On entry gd->start_addr_sp is pointing to the suggested top of the stack. + * The callee ensures gd->start_add_sp is 16-byte aligned, so architectures + * require only this can leave it untouched. + * + * On exit gd->start_addr_sp and gd->irq_sp should be set to the respective + * positions of the stack. The stack pointer(s) will be set to this later. + * gd->irq_sp is only required, if the architecture needs it. + * + * Return: 0 if no error + */ +int arch_reserve_stacks(void); + +/** + * arch_reserve_mmu() - Reserve memory for MMU TLB table + * + * Architecture-specific routine for reserving memory for the MMU TLB table. + * This is used in generic board init sequence in common/board_f.c. + * + * If an implementation is not provided, it will just be a nop stub. + * + * Return: 0 if OK + */ +int arch_reserve_mmu(void); + +/** + * arch_setup_bdinfo() - Architecture dependent boardinfo setup + * + * Architecture-specific routine for populating various boardinfo fields of + * gd->bd. It is called during the generic board init sequence. + * + * If an implementation is not provided, it will just be a nop stub. + * + * Return: 0 if OK + */ +int arch_setup_bdinfo(void); + +/** + * setup_bdinfo() - Generic boardinfo setup + * + * Routine for populating various generic boardinfo fields of + * gd->bd. It is called during the generic board init sequence. + * + * Return: 0 if OK + */ +int setup_bdinfo(void); + +/** + * cpu_secondary_init_r() - CPU-specific secondary initialization + * + * After non-volatile devices, environment and cpu code are setup, have + * another round to deal with any initialization that might require + * full access to the environment or loading of some image (firmware) + * from a non-volatile device. + * + * It is called during the generic post-relocation init sequence. + * + * Return: 0 if OK + */ +int cpu_secondary_init_r(void); + +/** + * pci_ep_init() - Initialize pci endpoint devices + * + * It is called during the generic post-relocation init sequence. + * + * Return: 0 if OK + */ +int pci_ep_init(void); + +/** + * pci_init() - Enumerate pci devices + * + * It is called during the generic post-relocation init sequence to enumerate + * pci buses. This is needed, for instance, in the case of DM PCI-based + * Ethernet devices, which will not be detected without having the enumeration + * performed earlier. + * + * Return: 0 if OK + */ +int pci_init(void); + +/** + * init_cache_f_r() - Turn on the cache in preparation for relocation + * + * Return: 0 if OK, -ve on error + */ +int init_cache_f_r(void); + +#if !CONFIG_IS_ENABLED(CPU) +/** + * print_cpuinfo() - Display information about the CPU + * + * Return: 0 if OK, -ve on error + */ +int print_cpuinfo(void); +#endif +int timer_init(void); +int misc_init_f(void); + +#if defined(CONFIG_DTB_RESELECT) +int embedded_dtb_select(void); +#endif + +/* common/init/board_init.c */ +extern ulong monitor_flash_len; + +/** + * ulong board_init_f_alloc_reserve - allocate reserved area + * @top: top of the reserve area, growing down. + * + * This function is called by each architecture very early in the start-up + * code to allow the C runtime to reserve space on the stack for writable + * 'globals' such as GD and the malloc arena. + * + * Return: bottom of reserved area + */ +ulong board_init_f_alloc_reserve(ulong top); + +/** + * board_init_f_init_reserve - initialize the reserved area(s) + * @base: top from which reservation was done + * + * This function is called once the C runtime has allocated the reserved + * area on the stack. It must initialize the GD at the base of that area. + */ +void board_init_f_init_reserve(ulong base); + +struct global_data; + +/** + * arch_setup_gd() - Set up the global_data pointer + * @gd_ptr: Pointer to global data + * + * This pointer is special in some architectures and cannot easily be assigned + * to. For example on x86 it is implemented by adding a specific record to its + * Global Descriptor Table! So we we provide a function to carry out this task. + * For most architectures this can simply be: + * + * gd = gd_ptr; + */ +void arch_setup_gd(struct global_data *gd_ptr); + +/* common/board_r.c */ +void board_init_r(struct global_data *id, ulong dest_addr) + __attribute__ ((noreturn)); + +int cpu_init_r(void); +int last_stage_init(void); +int mac_read_from_eeprom(void); +int set_cpu_clk_info(void); +int update_flash_size(int flash_size); +int arch_early_init_r(void); +int misc_init_r(void); +#if defined(CONFIG_VID) +int init_func_vid(void); +#endif + +/* common/board_info.c */ +int checkboard(void); +int show_board_info(void); + +/** + * Get the uppermost pointer that is valid to access + * + * Some systems may not map all of their address space. This function allows + * boards to indicate what their highest support pointer value is for DRAM + * access. + * + * @param total_size Size of U-Boot (unused?) + */ +ulong board_get_usable_ram_top(ulong total_size); + +int board_early_init_f(void); + +/* manipulate the U-Boot fdt before its relocation */ +int board_fix_fdt(void *rw_fdt_blob); +int board_late_init(void); +int board_postclk_init(void); /* after clocks/timebase, before env/serial */ +int board_early_init_r(void); + +/* TODO(sjg@chromium.org): Drop this when DM_PCI migration is completed */ +void pci_init_board(void); + +/** + * arch_initr_trap() - Init traps + * + * Arch specific routine for initializing traps. It is called during the + * generic board init sequence, after relocation. + * + * Return: 0 if OK + */ +int arch_initr_trap(void); + +/** + * main_loop() - Enter the main loop of U-Boot + * + * This normally runs the command line. + */ +void main_loop(void); + +#if defined(CONFIG_ARM) +void relocate_code(ulong addr_moni); +#else +void relocate_code(ulong start_addr_sp, struct global_data *new_gd, + ulong relocaddr) + __attribute__ ((noreturn)); +#endif + +/* Print a numeric value (for use in arch_print_bdinfo()) */ +void bdinfo_print_num_l(const char *name, ulong value); +void bdinfo_print_num_ll(const char *name, unsigned long long value); + +/* Print a clock speed in MHz */ +void bdinfo_print_mhz(const char *name, unsigned long hz); + +/* Show arch-specific information for the 'bd' command */ +void arch_print_bdinfo(void); + +#endif /* __ASSEMBLY__ */ +/* Put only stuff here that the assembler can digest */ + +#endif /* __INIT_H_ */ diff --git a/roms/u-boot/include/initcall.h b/roms/u-boot/include/initcall.h new file mode 100644 index 000000000..69ce26807 --- /dev/null +++ b/roms/u-boot/include/initcall.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#ifndef __INITCALL_H +#define __INITCALL_H + +typedef int (*init_fnc_t)(void); + +#include +#ifdef CONFIG_EFI_APP +#include +#endif +#include + +/* + * To enable debugging. add #define DEBUG at the top of the including file. + * + * To find a symbol, use grep on u-boot.map + */ +static inline int initcall_run_list(const init_fnc_t init_sequence[]) +{ + const init_fnc_t *init_fnc_ptr; + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + unsigned long reloc_ofs = 0; + int ret; + + /* + * Sandbox is relocated by the OS, so symbols always appear at + * the relocated address. + */ + if (IS_ENABLED(CONFIG_SANDBOX) || (gd->flags & GD_FLG_RELOC)) + reloc_ofs = gd->reloc_off; +#ifdef CONFIG_EFI_APP + reloc_ofs = (unsigned long)image_base; +#endif + if (reloc_ofs) + debug("initcall: %p (relocated to %p)\n", + (char *)*init_fnc_ptr - reloc_ofs, + (char *)*init_fnc_ptr); + else + debug("initcall: %p\n", (char *)*init_fnc_ptr - reloc_ofs); + + ret = (*init_fnc_ptr)(); + if (ret) { + printf("initcall sequence %p failed at call %p (err=%d)\n", + init_sequence, + (char *)*init_fnc_ptr - reloc_ofs, ret); + return -1; + } + } + return 0; +} + +#endif diff --git a/roms/u-boot/include/input.h b/roms/u-boot/include/input.h new file mode 100644 index 000000000..3285a3ffa --- /dev/null +++ b/roms/u-boot/include/input.h @@ -0,0 +1,202 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Keyboard input helper functions (too small to be called a layer) + * + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#ifndef _INPUT_H +#define _INPUT_H + +enum { + INPUT_MAX_MODIFIERS = 4, + INPUT_BUFFER_LEN = 16, +}; + +enum { + /* Keyboard LEDs */ + INPUT_LED_SCROLL = 1 << 0, + INPUT_LED_NUM = 1 << 1, + INPUT_LED_CAPS = 1 << 2, +}; + +/* + * This table translates key codes to ASCII. Most of the entries are ASCII + * codes, but entries after KEY_FIRST_MOD indicate that this key is a + * modifier key, like shift, ctrl. KEY_FIRST_MOD + MOD_SHIFT is the shift + * key, for example. + */ +struct input_key_xlate { + /* keycode of the modifiers which select this table, -1 if none */ + int left_keycode; + int right_keycode; + const uchar *xlate; /* keycode to ASCII table */ + int num_entries; /* number of entries in this table */ +}; + +struct input_config { + struct udevice *dev; + uchar fifo[INPUT_BUFFER_LEN]; + int fifo_in, fifo_out; + + /* Which modifiers are active (1 bit for each MOD_... value) */ + uchar modifiers; + uchar flags; /* active state keys (FLAGS_...) */ + uchar leds; /* active LEDs (INPUT_LED_...) */ + uchar leds_changed; /* LEDs that just changed */ + uchar num_tables; /* number of modifier tables */ + int prev_keycodes[INPUT_BUFFER_LEN]; /* keys held last time */ + int num_prev_keycodes; /* number of prev keys */ + struct input_key_xlate table[INPUT_MAX_MODIFIERS]; + + /** + * Function the input helper calls to scan the keyboard + * + * @param config Input state + * @return 0 if no keys read, otherwise number of keys read, or 1 if + * unknown + */ + int (*read_keys)(struct input_config *config); + bool allow_repeats; /* Don't filter out repeats */ + unsigned int next_repeat_ms; /* Next time we repeat a key */ + unsigned int repeat_delay_ms; /* Time before autorepeat starts */ + unsigned int repeat_rate_ms; /* Autorepeat rate in ms */ +}; + +struct stdio_dev; + +/** + * Convert a list of key codes into ASCII and send them + * + * @param config Input state + * @param keycode List of key codes to examine + * @param num_keycodes Number of key codes + * @return number of ascii characters sent, or 0 if none, or -1 for an + * internal error + */ +int input_send_keycodes(struct input_config *config, int keycode[], int count); + +/** + * Add a new keycode to an existing list of keycodes + * + * This can be used to handle keyboards which do their own scanning. An + * internal list of depressed keys is maintained by the input library. Then + * this function is called to add a new key to the list (when a 'make code' is + * received), or remove a key (when a 'break code' is received). + * + * This function looks after maintenance of the list of active keys, and calls + * input_send_keycodes() with its updated list. + * + * @param config Input state + * @param new_keycode New keycode to add/remove + * @param release true if this key was released, false if depressed + * @return number of ascii characters sent, or 0 if none, or -1 for an + * internal error + */ +int input_add_keycode(struct input_config *config, int new_keycode, + bool release); + +/** + * Add a new key translation table to the input + * + * @param config Input state + * @param left_keycode Key to hold to get into this table + * @param right_keycode Another key to hold to get into this table + * @param xlate Conversion table from key codes to ASCII + * @param num_entries Number of entries in xlate table + */ +int input_add_table(struct input_config *config, int left_keycode, + int right_keycode, const uchar *xlate, int num_entries); + +/** + * Test if keys are available to be read + * + * @param config Input state + * @return 0 if no keys available, 1 if keys are available + */ +int input_tstc(struct input_config *config); + +/** + * Read a key + * + * TODO: U-Boot wants 0 for no key, but Ctrl-@ is a valid key... + * + * @param config Input state + * @return key, or 0 if no key, or -1 if error + */ +int input_getc(struct input_config *config); + +/** + * Register a new device with stdio and switch to it if wanted + * + * @param dev Pointer to device + * @return 0 if ok, -1 on error + */ +int input_stdio_register(struct stdio_dev *dev); + +/** + * Set up the keyboard autorepeat delays + * + * @param repeat_delay_ms Delay before key auto-repeat starts (in ms) + * @param repeat_rate_ms Delay between successive key repeats (in ms) + */ +void input_set_delays(struct input_config *config, int repeat_delay_ms, + int repeat_rate_ms); + +/** + * Tell the input layer whether to allow the caller to determine repeats + * + * Generally the input library handles processing of a list of scanned keys. + * Repeated keys need to be generated based on a timer in this case, since all + * that is provided is a list of keys current depressed. + * + * Keyboards which do their own scanning will resend codes when they want to + * inject a repeating key. This function can be called at start-up to select + * this behaviour. + * + * @param config Input state + * @param allow_repeats true to repeat depressed keys every time + * input_send_keycodes() is called, false to do normal + * keyboard repeat processing with a timer. + */ +void input_allow_repeats(struct input_config *config, bool allow_repeats); + +/** + * Check if keyboard LEDs need to be updated + * + * This can be called after input_tstc() to see if keyboard LEDs need + * updating. + * + * @param config Input state + * @return -1 if no LEDs need updating, other value if they do + */ +int input_leds_changed(struct input_config *config); + +/** + * Set up the key map tables + * + * This must be called after input_init() or keycode decoding will not work. + * + * @param config Input state + * @param german true to use German keyboard layout, false for US + * @return 0 if ok, -1 on error + */ +int input_add_tables(struct input_config *config, bool german); + +/** + * Set up the input handler with basic key maps. + * + * @param config Input state + * @param leds Initial LED value (INPUT_LED_ mask), 0 suggested + * @return 0 if ok, -1 on error + */ +int input_init(struct input_config *config, int leds); + +#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +extern int overwrite_console(void); +#define OVERWRITE_CONSOLE overwrite_console() +#else +#define OVERWRITE_CONSOLE 0 +#endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */ + +#endif diff --git a/roms/u-boot/include/inttypes.h b/roms/u-boot/include/inttypes.h new file mode 100644 index 000000000..dcb678522 --- /dev/null +++ b/roms/u-boot/include/inttypes.h @@ -0,0 +1,271 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 1997-2001, 2004, 2007 Free Software Foundation, Inc. + * + * This file is taken from the GNU C Library v2.15, with the unimplemented + * functions removed and a few style fixes. + */ + +/* + * ISO C99: 7.8 Format conversion of integer types + */ + +#ifndef _INTTYPES_H +#define _INTTYPES_H 1 + +#include + +/* Get a definition for wchar_t. But we must not define wchar_t itself. */ +#ifndef ____gwchar_t_defined +# ifdef __cplusplus +# define __gwchar_t wchar_t +# elif defined __WCHAR_TYPE__ +typedef __WCHAR_TYPE__ __gwchar_t; +# else +# define __need_wchar_t +# include +typedef wchar_t __gwchar_t; +# endif +# define ____gwchar_t_defined 1 +#endif + +/* + * The ISO C99 standard specifies that these macros must only be defined if + * explicitly requested + */ +#if !defined __cplusplus || defined __STDC_FORMAT_MACROS + +/* linux/types.h always uses long long for 64-bit and long for uintptr_t */ +# define __PRI64_PREFIX "ll" +# define __PRIPTR_PREFIX "l" + +/* Macros for printing format specifiers. */ + +/* Decimal notation. */ +# define PRId8 "d" +# define PRId16 "d" +# define PRId32 "d" +# define PRId64 __PRI64_PREFIX "d" + +# define PRIdLEAST8 "d" +# define PRIdLEAST16 "d" +# define PRIdLEAST32 "d" +# define PRIdLEAST64 __PRI64_PREFIX "d" + +# define PRIdFAST8 "d" +# define PRIdFAST16 __PRIPTR_PREFIX "d" +# define PRIdFAST32 __PRIPTR_PREFIX "d" +# define PRIdFAST64 __PRI64_PREFIX "d" + +# define PRIi8 "i" +# define PRIi16 "i" +# define PRIi32 "i" +# define PRIi64 __PRI64_PREFIX "i" + +# define PRIiLEAST8 "i" +# define PRIiLEAST16 "i" +# define PRIiLEAST32 "i" +# define PRIiLEAST64 __PRI64_PREFIX "i" + +# define PRIiFAST8 "i" +# define PRIiFAST16 __PRIPTR_PREFIX "i" +# define PRIiFAST32 __PRIPTR_PREFIX "i" +# define PRIiFAST64 __PRI64_PREFIX "i" + +/* Octal notation. */ +# define PRIo8 "o" +# define PRIo16 "o" +# define PRIo32 "o" +# define PRIo64 __PRI64_PREFIX "o" + +# define PRIoLEAST8 "o" +# define PRIoLEAST16 "o" +# define PRIoLEAST32 "o" +# define PRIoLEAST64 __PRI64_PREFIX "o" + +# define PRIoFAST8 "o" +# define PRIoFAST16 __PRIPTR_PREFIX "o" +# define PRIoFAST32 __PRIPTR_PREFIX "o" +# define PRIoFAST64 __PRI64_PREFIX "o" + +/* Unsigned integers. */ +# define PRIu8 "u" +# define PRIu16 "u" +# define PRIu32 "u" +# define PRIu64 __PRI64_PREFIX "u" + +# define PRIuLEAST8 "u" +# define PRIuLEAST16 "u" +# define PRIuLEAST32 "u" +# define PRIuLEAST64 __PRI64_PREFIX "u" + +# define PRIuFAST8 "u" +# define PRIuFAST16 __PRIPTR_PREFIX "u" +# define PRIuFAST32 __PRIPTR_PREFIX "u" +# define PRIuFAST64 __PRI64_PREFIX "u" + +/* lowercase hexadecimal notation. */ +# define PRIx8 "x" +# define PRIx16 "x" +# define PRIx32 "x" +# define PRIx64 __PRI64_PREFIX "x" + +# define PRIxLEAST8 "x" +# define PRIxLEAST16 "x" +# define PRIxLEAST32 "x" +# define PRIxLEAST64 __PRI64_PREFIX "x" + +# define PRIxFAST8 "x" +# define PRIxFAST16 __PRIPTR_PREFIX "x" +# define PRIxFAST32 __PRIPTR_PREFIX "x" +# define PRIxFAST64 __PRI64_PREFIX "x" + +/* UPPERCASE hexadecimal notation. */ +# define PRIX8 "X" +# define PRIX16 "X" +# define PRIX32 "X" +# define PRIX64 __PRI64_PREFIX "X" + +# define PRIXLEAST8 "X" +# define PRIXLEAST16 "X" +# define PRIXLEAST32 "X" +# define PRIXLEAST64 __PRI64_PREFIX "X" + +# define PRIXFAST8 "X" +# define PRIXFAST16 __PRIPTR_PREFIX "X" +# define PRIXFAST32 __PRIPTR_PREFIX "X" +# define PRIXFAST64 __PRI64_PREFIX "X" + +/* Macros for printing `intmax_t' and `uintmax_t'. */ +# define PRIdMAX __PRI64_PREFIX "d" +# define PRIiMAX __PRI64_PREFIX "i" +# define PRIoMAX __PRI64_PREFIX "o" +# define PRIuMAX __PRI64_PREFIX "u" +# define PRIxMAX __PRI64_PREFIX "x" +# define PRIXMAX __PRI64_PREFIX "X" + +/* Macros for printing `intptr_t' and `uintptr_t'. */ +# define PRIdPTR __PRIPTR_PREFIX "d" +# define PRIiPTR __PRIPTR_PREFIX "i" +# define PRIoPTR __PRIPTR_PREFIX "o" +# define PRIuPTR __PRIPTR_PREFIX "u" +# define PRIxPTR __PRIPTR_PREFIX "x" +# define PRIXPTR __PRIPTR_PREFIX "X" + +/* Macros for scanning format specifiers. */ + +/* Signed decimal notation. */ +# define SCNd8 "hhd" +# define SCNd16 "hd" +# define SCNd32 "d" +# define SCNd64 __PRI64_PREFIX "d" + +# define SCNdLEAST8 "hhd" +# define SCNdLEAST16 "hd" +# define SCNdLEAST32 "d" +# define SCNdLEAST64 __PRI64_PREFIX "d" + +# define SCNdFAST8 "hhd" +# define SCNdFAST16 __PRIPTR_PREFIX "d" +# define SCNdFAST32 __PRIPTR_PREFIX "d" +# define SCNdFAST64 __PRI64_PREFIX "d" + +/* Signed decimal notation. */ +# define SCNi8 "hhi" +# define SCNi16 "hi" +# define SCNi32 "i" +# define SCNi64 __PRI64_PREFIX "i" + +# define SCNiLEAST8 "hhi" +# define SCNiLEAST16 "hi" +# define SCNiLEAST32 "i" +# define SCNiLEAST64 __PRI64_PREFIX "i" + +# define SCNiFAST8 "hhi" +# define SCNiFAST16 __PRIPTR_PREFIX "i" +# define SCNiFAST32 __PRIPTR_PREFIX "i" +# define SCNiFAST64 __PRI64_PREFIX "i" + +/* Unsigned decimal notation. */ +# define SCNu8 "hhu" +# define SCNu16 "hu" +# define SCNu32 "u" +# define SCNu64 __PRI64_PREFIX "u" + +# define SCNuLEAST8 "hhu" +# define SCNuLEAST16 "hu" +# define SCNuLEAST32 "u" +# define SCNuLEAST64 __PRI64_PREFIX "u" + +# define SCNuFAST8 "hhu" +# define SCNuFAST16 __PRIPTR_PREFIX "u" +# define SCNuFAST32 __PRIPTR_PREFIX "u" +# define SCNuFAST64 __PRI64_PREFIX "u" + +/* Octal notation. */ +# define SCNo8 "hho" +# define SCNo16 "ho" +# define SCNo32 "o" +# define SCNo64 __PRI64_PREFIX "o" + +# define SCNoLEAST8 "hho" +# define SCNoLEAST16 "ho" +# define SCNoLEAST32 "o" +# define SCNoLEAST64 __PRI64_PREFIX "o" + +# define SCNoFAST8 "hho" +# define SCNoFAST16 __PRIPTR_PREFIX "o" +# define SCNoFAST32 __PRIPTR_PREFIX "o" +# define SCNoFAST64 __PRI64_PREFIX "o" + +/* Hexadecimal notation. */ +# define SCNx8 "hhx" +# define SCNx16 "hx" +# define SCNx32 "x" +# define SCNx64 __PRI64_PREFIX "x" + +# define SCNxLEAST8 "hhx" +# define SCNxLEAST16 "hx" +# define SCNxLEAST32 "x" +# define SCNxLEAST64 __PRI64_PREFIX "x" + +# define SCNxFAST8 "hhx" +# define SCNxFAST16 __PRIPTR_PREFIX "x" +# define SCNxFAST32 __PRIPTR_PREFIX "x" +# define SCNxFAST64 __PRI64_PREFIX "x" + +/* Macros for scanning `intmax_t' and `uintmax_t'. */ +# define SCNdMAX __PRI64_PREFIX "d" +# define SCNiMAX __PRI64_PREFIX "i" +# define SCNoMAX __PRI64_PREFIX "o" +# define SCNuMAX __PRI64_PREFIX "u" +# define SCNxMAX __PRI64_PREFIX "x" + +/* Macros for scanning `intptr_t' and `uintptr_t'. */ +# define SCNdPTR __PRIPTR_PREFIX "d" +# define SCNiPTR __PRIPTR_PREFIX "i" +# define SCNoPTR __PRIPTR_PREFIX "o" +# define SCNuPTR __PRIPTR_PREFIX "u" +# define SCNxPTR __PRIPTR_PREFIX "x" + +#endif /* C++ && format macros */ + +#if __WORDSIZE == 64 + +/* We have to define the `uintmax_t' type using `ldiv_t'. */ +typedef struct { + long int quot; /* Quotient. */ + long int rem; /* Remainder. */ +} imaxdiv_t; + +#else + +/* We have to define the `uintmax_t' type using `lldiv_t'. */ +typedef struct { + long long int quot; /* Quotient. */ + long long int rem; /* Remainder. */ +} imaxdiv_t; + +#endif + +#endif /* inttypes.h */ diff --git a/roms/u-boot/include/iomux.h b/roms/u-boot/include/iomux.h new file mode 100644 index 000000000..37f5f6dee --- /dev/null +++ b/roms/u-boot/include/iomux.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2008 + * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. + */ + +#ifndef _IO_MUX_H +#define _IO_MUX_H + +#include + +/* + * Stuff required to support console multiplexing. + */ + +/* + * Pointers to devices used for each file type. Defined in console.c + * but storage is allocated in iomux.c. + */ +extern struct stdio_dev **console_devices[MAX_FILES]; +/* + * The count of devices assigned to each FILE. Defined in console.c + * and populated in iomux.c. + */ +extern int cd_count[MAX_FILES]; + +#define for_each_console_dev(i, file, dev) \ + for (i = 0, dev = console_devices[file][i]; \ + i < cd_count[file]; \ + i++, dev = console_devices[file][i]) + +int iomux_match_device(struct stdio_dev **, const int, struct stdio_dev *); +int iomux_doenv(const int, const char *); +int iomux_replace_device(const int, const char *, const char *); +void iomux_printdevs(const int); + +#endif /* _IO_MUX_H */ diff --git a/roms/u-boot/include/ioports.h b/roms/u-boot/include/ioports.h new file mode 100644 index 000000000..1cd3ceb37 --- /dev/null +++ b/roms/u-boot/include/ioports.h @@ -0,0 +1,62 @@ +/* + * definitions for MPC8xxx I/O Ports + * + * Murray.Jensen@cmst.csiro.au, 20-Oct-00 + */ + +/* + * this structure mirrors the layout of the five port registers in + * the internal memory map + */ +typedef struct { + unsigned int pdir; /* Port Data Direction Register (35-3) */ + unsigned int ppar; /* Port Pin Assignment Register (35-4) */ + unsigned int psor; /* Port Special Options Register (35-5) */ + unsigned int podr; /* Port Open Drain Register (35-2) */ + unsigned int pdat; /* Port Data Register (35-3) */ +} ioport_t; + +/* + * this macro calculates the address within the internal + * memory map (im) of the set of registers for a port (idx) + * + * the internal memory map aligns the above structure on + * a 0x20 byte boundary + */ +#ifdef CONFIG_MPC85xx +#define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20)) +#else +#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20)) +#endif + +/* + * this structure provides configuration + * information for one port pin + */ +typedef struct { + unsigned char conf:1; /* if 1, configure this port */ + unsigned char ppar:1; /* Port Pin Assignment Register (35-4) */ + unsigned char psor:1; /* Port Special Options Register (35-2) */ + unsigned char pdir:1; /* Port Data Direction Register (35-3) */ + unsigned char podr:1; /* Port Open Drain Register (35-2) */ + unsigned char pdat:1; /* Port Data Register (35-2) */ +} iop_conf_t; + +/* + * a table that contains configuration information for all 32 pins + * + * NOTE: in the second dimension of this table, index 0 refers to pin 31 + * and index 31 refers to pin 0. this made the code in the table look more + * like the table in the 8260UM (and in the hymod manuals). + */ +extern const iop_conf_t iop_conf_tab[4][32]; + +typedef struct { + unsigned char port; + unsigned char pin; + int dir; + int open_drain; + int assign; +} qe_iop_conf_t; + +#define QE_IOP_TAB_END (-1) diff --git a/roms/u-boot/include/iotrace.h b/roms/u-boot/include/iotrace.h new file mode 100644 index 000000000..380da1fbc --- /dev/null +++ b/roms/u-boot/include/iotrace.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2014 Google, Inc. + */ + +#ifndef __IOTRACE_H +#define __IOTRACE_H + +//#include +#include + +/* Support up to the machine word length for now */ +typedef ulong iovalue_t; + +enum iotrace_flags { + IOT_8 = 0, + IOT_16, + IOT_32, + + IOT_READ = 0 << 3, + IOT_WRITE = 1 << 3, +}; + +/** + * struct iotrace_record - Holds a single I/O trace record + * + * @flags: I/O access type + * @timestamp: Timestamp of access + * @addr: Address of access + * @value: Value written or read + */ +struct iotrace_record { + enum iotrace_flags flags; + u64 timestamp; + phys_addr_t addr; + iovalue_t value; +}; + +/* + * This file is designed to be included in arch//include/asm/io.h. + * It redirects all IO access through a tracing/checksumming feature for + * testing purposes. + */ + +#if defined(CONFIG_IO_TRACE) && !defined(IOTRACE_IMPL) && \ + !defined(CONFIG_SPL_BUILD) + +#undef readl +#define readl(addr) iotrace_readl((const void *)(addr)) + +#undef writel +#define writel(val, addr) iotrace_writel(val, (void *)(addr)) + +#undef readw +#define readw(addr) iotrace_readw((const void *)(addr)) + +#undef writew +#define writew(val, addr) iotrace_writew(val, (void *)(addr)) + +#undef readb +#define readb(addr) iotrace_readb((const void *)(uintptr_t)addr) + +#undef writeb +#define writeb(val, addr) iotrace_writeb(val, (void *)(uintptr_t)addr) + +#endif + +/* Tracing functions which mirror their io.h counterparts */ +u32 iotrace_readl(const void *ptr); +void iotrace_writel(ulong value, void *ptr); +u16 iotrace_readw(const void *ptr); +void iotrace_writew(ulong value, void *ptr); +u8 iotrace_readb(const void *ptr); +void iotrace_writeb(ulong value, void *ptr); + +/** + * iotrace_reset_checksum() - Reset the iotrace checksum + */ +void iotrace_reset_checksum(void); + +/** + * iotrace_get_checksum() - Get the current checksum value + * + * @return currect checksum value + */ +u32 iotrace_get_checksum(void); + +/** + * iotrace_set_region() - Set whether iotrace is limited to a specific + * io region. + * + * Defines the address and size of the limited region. + * + * @start: address of the beginning of the region + * @size: size of the region in bytes. + */ +void iotrace_set_region(ulong start, ulong size); + +/** + * iotrace_reset_region() - Reset the region limit + */ +void iotrace_reset_region(void); + +/** + * iotrace_get_region() - Get region information + * + * @start: Returns start address of region + * @size: Returns size of region in bytes + */ +void iotrace_get_region(ulong *start, ulong *size); + +/** + * iotrace_set_enabled() - Set whether iotracing is enabled or not + * + * This controls whether the checksum is updated and a trace record added + * for each I/O access. + * + * @enable: true to enable iotracing, false to disable + */ +void iotrace_set_enabled(int enable); + +/** + * iotrace_get_enabled() - Get whether iotracing is enabled or not + * + * @return true if enabled, false if disabled + */ +int iotrace_get_enabled(void); + +/** + * iotrace_set_buffer() - Set position and size of iotrace buffer + * + * Defines where the iotrace buffer goes, and resets the output pointer to + * the start of the buffer. + * + * The buffer can be 0 size in which case the checksum is updated but no + * trace records are writen. If the buffer is exhausted, the offset will + * continue to increase but not new data will be written. + * + * @start: Start address of buffer + * @size: Size of buffer in bytes + */ +void iotrace_set_buffer(ulong start, ulong size); + +/** + * iotrace_get_buffer() - Get buffer information + * + * @start: Returns start address of buffer + * @size: Returns actual size of buffer in bytes + * @needed_size: Returns needed size of buffer in bytes + * @offset: Returns the byte offset where the next output trace record will + * @count: Returns the number of trace records recorded + * be written (or would be if the buffer was large enough) + */ +void iotrace_get_buffer(ulong *start, ulong *size, ulong *needed_size, ulong *offset, ulong *count); + +#endif /* __IOTRACE_H */ diff --git a/roms/u-boot/include/ipu_pixfmt.h b/roms/u-boot/include/ipu_pixfmt.h new file mode 100644 index 000000000..866ead0ec --- /dev/null +++ b/roms/u-boot/include/ipu_pixfmt.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de + * + * Based on Linux IPU driver for MX51 (ipu.h): + * + * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. + */ + +#ifndef __IPU_PIXFMT_H__ +#define __IPU_PIXFMT_H__ + +#include +#include + +/* IPU Pixel format definitions */ +#define fourcc(a, b, c, d)\ + (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24)) + +/* + * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are + * the same used by V4L2 API. + */ + +#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0') +#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1') +#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6') +#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8') + +#define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*< 8 RGB-3-3-2 */ +#define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*< 16 RGB-5-5-5 */ +#define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*< 1 6 RGB-5-6-5 */ +#define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*< 18 RGB-6-6-6 */ +#define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*< 18 BGR-6-6-6 */ +#define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*< 24 BGR-8-8-8 */ +#define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*< 24 RGB-8-8-8 */ +#define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*< 32 BGR-8-8-8-8 */ +#define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*< 32 BGR-8-8-8-8 */ +#define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*< 32 RGB-8-8-8-8 */ +#define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*< 32 RGB-8-8-8-8 */ +#define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*< 32 ABGR-8-8-8-8 */ + +/* YUV Interleaved Formats */ +#define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*< 16 YUV 4:2:2 */ +#define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*< 16 YUV 4:2:2 */ +#define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*< 12 YUV 4:1:1 */ +#define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*< 24 YUV 4:4:4 */ + +/* two planes -- one Y, one Cb + Cr interleaved */ +#define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ + +#define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*< 8 Greyscale */ +#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*< 9 YVU 4:1:0 */ +#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*< 9 YUV 4:1:0 */ +#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*< 12 YVU 4:2:0 */ +#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*< 12 YUV 4:2:0 */ +#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*< 12 YUV 4:2:0 */ +#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*< 16 YVU 4:2:2 */ +#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */ + +int ipuv3_fb_init(struct fb_videomode const *mode, + uint8_t disp, + uint32_t pixfmt); +void ipuv3_fb_shutdown(void); + +#endif diff --git a/roms/u-boot/include/irq.h b/roms/u-boot/include/irq.h new file mode 100644 index 000000000..8527e4dd7 --- /dev/null +++ b/roms/u-boot/include/irq.h @@ -0,0 +1,269 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * IRQ is a type of interrupt controller used on recent Intel SoC. + * + * Copyright 2019 Google LLC + */ + +#ifndef __irq_H +#define __irq_H + +struct acpi_irq; +struct ofnode_phandle_args; + +/* + * Interrupt controller types available. You can find a particular one with + * irq_first_device_type() + */ +enum irq_dev_t { + X86_IRQT_BASE, /* Base controller */ + X86_IRQT_ITSS, /* ITSS controller, e.g. on APL */ + X86_IRQT_ACPI_GPE, /* ACPI General-Purpose Events controller */ + SANDBOX_IRQT_BASE, /* Sandbox testing */ +}; + +/** + * struct irq - A single irq line handled by an interrupt controller + * + * @dev: IRQ device that handles this irq + * @id: ID to identify this irq with the device + * @flags: Flags associated with this interrupt (IRQ_TYPE_...) + */ +struct irq { + struct udevice *dev; + ulong id; + ulong flags; +}; + +/** + * struct irq_ops - Operations for the IRQ + * + * Each IRQ device can handle mulitple IRQ lines + */ +struct irq_ops { + /** + * route_pmc_gpio_gpe() - Get the GPIO for an event + * + * @dev: IRQ device + * @pmc_gpe_num: Event number to check + * @returns GPIO for the event, or -ENOENT if none + */ + int (*route_pmc_gpio_gpe)(struct udevice *dev, uint pmc_gpe_num); + + /** + * set_polarity() - Set the IRQ polarity + * + * @dev: IRQ device + * @irq: Interrupt number to set + * @active_low: true if active low, false for active high + * @return 0 if OK, -EINVAL if @irq is invalid + */ + int (*set_polarity)(struct udevice *dev, uint irq, bool active_low); + + /** + * snapshot_polarities() - record IRQ polarities for later restore + * + * @dev: IRQ device + * @return 0 + */ + int (*snapshot_polarities)(struct udevice *dev); + + /** + * restore_polarities() - restore IRQ polarities + * + * @dev: IRQ device + * @return 0 + */ + int (*restore_polarities)(struct udevice *dev); + + /** + * read_and_clear() - get the value of an interrupt and clear it + * + * Clears the interrupt if pending + * + * @irq: IRQ line + * @return 0 if interrupt is not pending, 1 if it was (and so has been + * cleared), -ve on error + */ + int (*read_and_clear)(struct irq *irq); + /** + * of_xlate - Translate a client's device-tree (OF) irq specifier. + * + * The irq core calls this function as the first step in implementing + * a client's irq_get_by_*() call. + * + * If this function pointer is set to NULL, the irq core will use a + * default implementation, which assumes #interrupt-cells = <1>, and + * that the DT cell contains a simple integer irq ID. + * + * @irq: The irq struct to hold the translation result. + * @args: The irq specifier values from device tree. + * @return 0 if OK, or a negative error code. + */ + int (*of_xlate)(struct irq *irq, struct ofnode_phandle_args *args); + /** + * request - Request a translated irq. + * + * The irq core calls this function as the second step in + * implementing a client's irq_get_by_*() call, following a successful + * xxx_xlate() call, or as the only step in implementing a client's + * irq_request() call. + * + * @irq: The irq struct to request; this has been fille in by + * a previoux xxx_xlate() function call, or by the caller + * of irq_request(). + * @return 0 if OK, or a negative error code. + */ + int (*request)(struct irq *irq); + /** + * free - Free a previously requested irq. + * + * This is the implementation of the client irq_free() API. + * + * @irq: The irq to free. + * @return 0 if OK, or a negative error code. + */ + int (*free)(struct irq *irq); + +#if CONFIG_IS_ENABLED(ACPIGEN) + /** + * get_acpi() - Get the ACPI info for an irq + * + * This converts a irq to an ACPI structure for adding to the ACPI + * tables. + * + * @irq: irq to convert + * @acpi_irq: Output ACPI interrupt information + * @return ACPI pin number or -ve on error + */ + int (*get_acpi)(const struct irq *irq, struct acpi_irq *acpi_irq); +#endif +}; + +#define irq_get_ops(dev) ((struct irq_ops *)(dev)->driver->ops) + +/** + * irq_is_valid() - Check if an IRQ is valid + * + * @irq: IRQ description containing device and ID, e.g. previously + * returned by irq_get_by_index() + * @return true if valid, false if not + */ +static inline bool irq_is_valid(const struct irq *irq) +{ + return irq->dev != NULL; +} + +/** + * irq_route_pmc_gpio_gpe() - Get the GPIO for an event + * + * @dev: IRQ device + * @pmc_gpe_num: Event number to check + * @returns GPIO for the event, or -ENOENT if none + */ +int irq_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num); + +/** + * irq_set_polarity() - Set the IRQ polarity + * + * @dev: IRQ device + * @irq: Interrupt number to set + * @active_low: true if active low, false for active high + * @return 0 if OK, -EINVAL if @irq is invalid + */ +int irq_set_polarity(struct udevice *dev, uint irq, bool active_low); + +/** + * irq_snapshot_polarities() - record IRQ polarities for later restore + * + * @dev: IRQ device + * @return 0 + */ +int irq_snapshot_polarities(struct udevice *dev); + +/** + * irq_restore_polarities() - restore IRQ polarities + * + * @dev: IRQ device + * @return 0 + */ +int irq_restore_polarities(struct udevice *dev); + +/** + * read_and_clear() - get the value of an interrupt and clear it + * + * Clears the interrupt if pending + * + * @dev: IRQ device + * @return 0 if interrupt is not pending, 1 if it was (and so has been + * cleared), -ve on error + */ +int irq_read_and_clear(struct irq *irq); + +/** + * irq_get_by_index - Get/request an irq by integer index. + * + * This looks up and requests an irq. The index is relative to the client + * device; each device is assumed to have n irqs associated with it somehow, + * and this function finds and requests one of them. The mapping of client + * device irq indices to provider irqs may be via device-tree + * properties, board-provided mapping tables, or some other mechanism. + * + * @dev: The client device. + * @index: The index of the irq to request, within the client's list of + * irqs. + * @irq: A pointer to a irq struct to initialise. + * @return 0 if OK, or a negative error code. + */ +int irq_get_by_index(struct udevice *dev, int index, struct irq *irq); + +/** + * irq_request - Request a irq by provider-specific ID. + * + * This requests a irq using a provider-specific ID. Generally, this function + * should not be used, since irq_get_by_index/name() provide an interface that + * better separates clients from intimate knowledge of irq providers. + * However, this function may be useful in core SoC-specific code. + * + * @dev: The irq provider device. + * @irq: A pointer to a irq struct to initialise. The caller must + * have already initialised any field in this struct which the + * irq provider uses to identify the irq. + * @return 0 if OK, or a negative error code. + */ +int irq_request(struct udevice *dev, struct irq *irq); + +/** + * irq_free - Free a previously requested irq. + * + * @irq: A irq struct that was previously successfully requested by + * irq_request/get_by_*(). + * @return 0 if OK, or a negative error code. + */ +int irq_free(struct irq *irq); + +/** + * irq_first_device_type() - Get a particular interrupt controller + * + * On success this returns an activated interrupt device. + * + * @type: Type to find + * @devp: Returns the device, if found + * @return 0 if OK, -ENODEV if not found, other -ve error if uclass failed to + * probe + */ +int irq_first_device_type(enum irq_dev_t type, struct udevice **devp); + +/** + * irq_get_acpi() - Get the ACPI info for an irq + * + * This converts a irq to an ACPI structure for adding to the ACPI + * tables. + * + * @irq: irq to convert + * @acpi_irq: Output ACPI interrupt information + * @return ACPI pin number or -ve on error + */ +int irq_get_acpi(const struct irq *irq, struct acpi_irq *acpi_irq); + +#endif diff --git a/roms/u-boot/include/irq_func.h b/roms/u-boot/include/irq_func.h new file mode 100644 index 000000000..c7c4babbf --- /dev/null +++ b/roms/u-boot/include/irq_func.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Header file for interrupt functions + * + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef __IRQ_FUNC_H +#define __IRQ_FUNC_H + +struct pt_regs; + +typedef void (interrupt_handler_t)(void *arg); + +int interrupt_init(void); +void timer_interrupt(struct pt_regs *regs); +void external_interrupt(struct pt_regs *regs); +void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg); +void irq_free_handler(int vec); +void reset_timer(void); + +void enable_interrupts(void); +int disable_interrupts(void); + +#endif diff --git a/roms/u-boot/include/jffs2/compr_rubin.h b/roms/u-boot/include/jffs2/compr_rubin.h new file mode 100644 index 000000000..f26f476da --- /dev/null +++ b/roms/u-boot/include/jffs2/compr_rubin.h @@ -0,0 +1,11 @@ +/* Rubin encoder/decoder header */ +/* work started at : aug 3, 1994 */ +/* last modification : aug 15, 1994 */ +/* $Id: compr_rubin.h,v 1.1 2002/01/16 23:34:32 nyet Exp $ */ + +#define RUBIN_REG_SIZE 16 +#define UPPER_BIT_RUBIN (((long) 1)<<(RUBIN_REG_SIZE-1)) +#define LOWER_BITS_RUBIN ((((long) 1)<<(RUBIN_REG_SIZE-1))-1) + +void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, + unsigned long sourcelen, unsigned long dstlen); diff --git a/roms/u-boot/include/jffs2/jffs2.h b/roms/u-boot/include/jffs2/jffs2.h new file mode 100644 index 000000000..651f94cf3 --- /dev/null +++ b/roms/u-boot/include/jffs2/jffs2.h @@ -0,0 +1,234 @@ +/* + * JFFS2 -- Journalling Flash File System, Version 2. + * + * Copyright (C) 2001 Red Hat, Inc. + * + * Created by David Woodhouse + * + * The original JFFS, from which the design for JFFS2 was derived, + * was designed and implemented by Axis Communications AB. + * + * The contents of this file are subject to the Red Hat eCos Public + * License Version 1.1 (the "Licence"); you may not use this file + * except in compliance with the Licence. You may obtain a copy of + * the Licence at http://www.redhat.com/ + * + * Software distributed under the Licence is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. + * See the Licence for the specific language governing rights and + * limitations under the Licence. + * + * The Original Code is JFFS2 - Journalling Flash File System, version 2 + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use your + * version of this file under the RHEPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the RHEPL or the GPL. + * + * $Id: jffs2.h,v 1.2 2002/01/17 00:53:20 nyet Exp $ + * + */ + +#ifndef __LINUX_JFFS2_H__ +#define __LINUX_JFFS2_H__ + +#include +#include + +#define JFFS2_SUPER_MAGIC 0x72b6 + +/* Values we may expect to find in the 'magic' field */ +#define JFFS2_OLD_MAGIC_BITMASK 0x1984 +#define JFFS2_MAGIC_BITMASK 0x1985 +#define KSAMTIB_CIGAM_2SFFJ 0x5981 /* For detecting wrong-endian fs */ +#define JFFS2_EMPTY_BITMASK 0xffff +#define JFFS2_DIRTY_BITMASK 0x0000 + +/* Summary node MAGIC marker */ +#define JFFS2_SUM_MAGIC 0x02851885 + +/* We only allow a single char for length, and 0xFF is empty flash so + we don't want it confused with a real length. Hence max 254. +*/ +#define JFFS2_MAX_NAME_LEN 254 + +/* How small can we sensibly write nodes? */ +#define JFFS2_MIN_DATA_LEN 128 + +#define JFFS2_COMPR_NONE 0x00 +#define JFFS2_COMPR_ZERO 0x01 +#define JFFS2_COMPR_RTIME 0x02 +#define JFFS2_COMPR_RUBINMIPS 0x03 +#define JFFS2_COMPR_COPY 0x04 +#define JFFS2_COMPR_DYNRUBIN 0x05 +#define JFFS2_COMPR_ZLIB 0x06 +#if defined(CONFIG_JFFS2_LZO) +#define JFFS2_COMPR_LZO 0x07 +#define JFFS2_NUM_COMPR 8 +#else +#define JFFS2_NUM_COMPR 7 +#endif + +/* Compatibility flags. */ +#define JFFS2_COMPAT_MASK 0xc000 /* What do to if an unknown nodetype is found */ +#define JFFS2_NODE_ACCURATE 0x2000 +/* INCOMPAT: Fail to mount the filesystem */ +#define JFFS2_FEATURE_INCOMPAT 0xc000 +/* ROCOMPAT: Mount read-only */ +#define JFFS2_FEATURE_ROCOMPAT 0x8000 +/* RWCOMPAT_COPY: Mount read/write, and copy the node when it's GC'd */ +#define JFFS2_FEATURE_RWCOMPAT_COPY 0x4000 +/* RWCOMPAT_DELETE: Mount read/write, and delete the node when it's GC'd */ +#define JFFS2_FEATURE_RWCOMPAT_DELETE 0x0000 + +#define JFFS2_NODETYPE_DIRENT (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 1) +#define JFFS2_NODETYPE_INODE (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 2) +#define JFFS2_NODETYPE_CLEANMARKER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) +#define JFFS2_NODETYPE_PADDING (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 4) +#define JFFS2_NODETYPE_SUMMARY (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 6) + +/* Maybe later... */ +/*#define JFFS2_NODETYPE_CHECKPOINT (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) */ +/*#define JFFS2_NODETYPE_OPTIONS (JFFS2_FEATURE_RWCOMPAT_COPY | JFFS2_NODE_ACCURATE | 4) */ + +/* Same as the non_ECC versions, but with extra space for real + * ECC instead of just the checksum. For use on NAND flash + */ +/*#define JFFS2_NODETYPE_DIRENT_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 5) */ +/*#define JFFS2_NODETYPE_INODE_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 6) */ + +#define JFFS2_INO_FLAG_PREREAD 1 /* Do read_inode() for this one at + mount time, don't wait for it to + happen later */ +#define JFFS2_INO_FLAG_USERCOMPR 2 /* User has requested a specific + compression type */ + + +struct jffs2_unknown_node +{ + /* All start like this */ + __u16 magic; + __u16 nodetype; + __u32 totlen; /* So we can skip over nodes we don't grok */ + __u32 hdr_crc; +} __attribute__((packed)); + +struct jffs2_raw_dirent +{ + __u16 magic; + __u16 nodetype; /* == JFFS_NODETYPE_DIRENT */ + __u32 totlen; + __u32 hdr_crc; + __u32 pino; + __u32 version; + __u32 ino; /* == zero for unlink */ + __u32 mctime; + __u8 nsize; + __u8 type; + __u8 unused[2]; + __u32 node_crc; + __u32 name_crc; + __u8 name[0]; +} __attribute__((packed)); + +/* The JFFS2 raw inode structure: Used for storage on physical media. */ +/* The uid, gid, atime, mtime and ctime members could be longer, but + are left like this for space efficiency. If and when people decide + they really need them extended, it's simple enough to add support for + a new type of raw node. +*/ +struct jffs2_raw_inode +{ + __u16 magic; /* A constant magic number. */ + __u16 nodetype; /* == JFFS_NODETYPE_INODE */ + __u32 totlen; /* Total length of this node (inc data, etc.) */ + __u32 hdr_crc; + __u32 ino; /* Inode number. */ + __u32 version; /* Version number. */ + __u32 mode; /* The file's type or mode. */ + __u16 uid; /* The file's owner. */ + __u16 gid; /* The file's group. */ + __u32 isize; /* Total resultant size of this inode (used for truncations) */ + __u32 atime; /* Last access time. */ + __u32 mtime; /* Last modification time. */ + __u32 ctime; /* Change time. */ + __u32 offset; /* Where to begin to write. */ + __u32 csize; /* (Compressed) data size */ + __u32 dsize; /* Size of the node's data. (after decompression) */ + __u8 compr; /* Compression algorithm used */ + __u8 usercompr; /* Compression algorithm requested by the user */ + __u16 flags; /* See JFFS2_INO_FLAG_* */ + __u32 data_crc; /* CRC for the (compressed) data. */ + __u32 node_crc; /* CRC for the raw inode (excluding data) */ +/* __u8 data[dsize]; */ +} __attribute__((packed)); + +struct jffs2_raw_summary +{ + __u16 magic; + __u16 nodetype; /* = JFFS2_NODETYPE_SUMMARY */ + __u32 totlen; + __u32 hdr_crc; + __u32 sum_num; /* number of sum entries*/ + __u32 cln_mkr; /* clean marker size, 0 = no cleanmarker */ + __u32 padded; /* sum of the size of padding nodes */ + __u32 sum_crc; /* summary information crc */ + __u32 node_crc; /* node crc */ + __u32 sum[0]; /* inode summary info */ +}; + +union jffs2_node_union { + struct jffs2_raw_inode i; + struct jffs2_raw_dirent d; + struct jffs2_raw_summary s; + struct jffs2_unknown_node u; +} __attribute__((packed)); + +enum + { + DT_UNKNOWN = 0, +# define DT_UNKNOWN DT_UNKNOWN + DT_FIFO = 1, +# define DT_FIFO DT_FIFO + DT_CHR = 2, +# define DT_CHR DT_CHR + DT_DIR = 4, +# define DT_DIR DT_DIR + DT_BLK = 6, +# define DT_BLK DT_BLK + DT_REG = 8, +# define DT_REG DT_REG + DT_LNK = 10, +# define DT_LNK DT_LNK + DT_SOCK = 12, +# define DT_SOCK DT_SOCK + DT_WHT = 14 +# define DT_WHT DT_WHT + }; + + +u32 jffs2_1pass_ls(struct part_info *part,const char *fname); +u32 jffs2_1pass_load(char *dest, struct part_info *part,const char *fname); +u32 jffs2_1pass_info(struct part_info *part); + +void rtime_decompress(unsigned char *data_in, unsigned char *cpage_out, + u32 srclen, u32 destlen); +void rubin_do_decompress(unsigned char *bits, unsigned char *in, + unsigned char *page_out, __u32 destlen); +void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, + unsigned long sourcelen, unsigned long dstlen); +long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out, + __u32 srclen, __u32 destlen); +#if defined(CONFIG_JFFS2_LZO) +int lzo_decompress(unsigned char *data_in, unsigned char *cpage_out, + u32 srclen, u32 destlen); +#endif + +char *mkmodestr(unsigned long mode, char *str); +#endif /* __LINUX_JFFS2_H__ */ diff --git a/roms/u-boot/include/jffs2/jffs2_1pass.h b/roms/u-boot/include/jffs2/jffs2_1pass.h new file mode 100644 index 000000000..5bc3e66cd --- /dev/null +++ b/roms/u-boot/include/jffs2/jffs2_1pass.h @@ -0,0 +1,3 @@ +u32 jffs2_1pass_ls(struct part_info *part,const char *fname); +u32 jffs2_1pass_load(char *dest, struct part_info *part,const char *fname); +u32 jffs2_1pass_info(struct part_info *part); diff --git a/roms/u-boot/include/jffs2/load_kernel.h b/roms/u-boot/include/jffs2/load_kernel.h new file mode 100644 index 000000000..9346d7ee9 --- /dev/null +++ b/roms/u-boot/include/jffs2/load_kernel.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef load_kernel_h +#define load_kernel_h +/*------------------------------------------------------------------------- + * Filename: load_kernel.h + * Version: $Id: load_kernel.h,v 1.3 2002/01/25 01:34:11 nyet Exp $ + * Copyright: Copyright (C) 2001, Russ Dill + * Author: Russ Dill + * Description: header for load kernel modules + *-----------------------------------------------------------------------*/ + +#include + +/* mtd device types */ +#define MTD_DEV_TYPE_NOR 0x0001 +#define MTD_DEV_TYPE_NAND 0x0002 +#define MTD_DEV_TYPE_ONENAND 0x0004 +#define MTD_DEV_TYPE_SPINAND 0x0008 + +#define MTD_DEV_TYPE(type) (type == MTD_DEV_TYPE_NAND ? "nand" : \ + (type == MTD_DEV_TYPE_NOR ? "nor" : \ + (type == MTD_DEV_TYPE_ONENAND ? "onenand" : \ + "spi-nand"))) \ + +struct mtd_device { + struct list_head link; + struct mtdids *id; /* parent mtd id entry */ + u16 num_parts; /* number of partitions on this device */ + struct list_head parts; /* partitions */ +}; + +struct part_info { + struct list_head link; + char *name; /* partition name */ + u8 auto_name; /* set to 1 for generated name */ + u64 size; /* total size of the partition */ + u64 offset; /* offset within device */ + void *jffs2_priv; /* used internaly by jffs2 */ + u32 mask_flags; /* kernel MTD mask flags */ + u32 sector_size; /* size of sector */ + struct mtd_device *dev; /* parent device */ +}; + +struct mtdids { + struct list_head link; + u8 type; /* device type */ + u8 num; /* device number */ + u64 size; /* device size */ + char *mtd_id; /* linux kernel device id */ +}; + +#define ldr_strlen strlen +#define ldr_strncmp strncmp +#define ldr_memcpy memcpy +#define putstr(x) printf("%s", x) +#define mmalloc malloc +#define UDEBUG printf + +#define putnstr(str, size) printf("%*.*s", size, size, str) +#define ldr_output_string(x) puts(x) +#define putLabeledWord(x, y) printf("%s %08x\n", x, (unsigned int)y) +#define led_blink(x, y, z, a) + +/* common/cmd_jffs2.c */ +extern int mtdparts_init(void); +extern int find_dev_and_part(const char *id, struct mtd_device **dev, + u8 *part_num, struct part_info **part); +extern struct mtd_device *device_find(u8 type, u8 num); + +#endif /* load_kernel_h */ diff --git a/roms/u-boot/include/jffs2/mini_inflate.h b/roms/u-boot/include/jffs2/mini_inflate.h new file mode 100644 index 000000000..52eb30b4e --- /dev/null +++ b/roms/u-boot/include/jffs2/mini_inflate.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*------------------------------------------------------------------------- + * Filename: mini_inflate.h + * Version: $Id: mini_inflate.h,v 1.2 2002/01/17 00:53:20 nyet Exp $ + * Copyright: Copyright (C) 2001, Russ Dill + * Author: Russ Dill + * Description: Mini deflate implementation + *-----------------------------------------------------------------------*/ + +typedef __SIZE_TYPE__ size; + +#define NO_ERROR 0 +#define COMP_UNKNOWN 1 /* The specififed bytype is invalid */ +#define CODE_NOT_FOUND 2 /* a huffman code in the stream could not be decoded */ +#define TOO_MANY_BITS 3 /* pull_bits was passed an argument that is too + * large */ + +/* This struct represents an entire huffman code set. It has various lookup + * tables to speed decoding */ +struct huffman_set { + int bits; /* maximum bit length */ + int num_symbols; /* Number of symbols this code can represent */ + int *lengths; /* The bit length of symbols */ + int *symbols; /* All of the symbols, sorted by the huffman code */ + int *count; /* the number of codes of this bit length */ + int *first; /* the first code of this bit length */ + int *pos; /* the symbol that first represents (in the symbols + * array) */ +}; + +struct bitstream { + unsigned char *data; /* increments as we move from byte to byte */ + unsigned char bit; /* 0 to 7 */ + void *(*memcpy)(void *, const void *, size); + unsigned long decoded; /* The number of bytes decoded */ + int error; + + int distance_count[16]; + int distance_first[16]; + int distance_pos[16]; + int distance_lengths[32]; + int distance_symbols[32]; + + int code_count[8]; + int code_first[8]; + int code_pos[8]; + int code_lengths[19]; + int code_symbols[19]; + + int length_count[16]; + int length_first[16]; + int length_pos[16]; + int length_lengths[288]; + int length_symbols[288]; + + struct huffman_set codes; + struct huffman_set lengths; + struct huffman_set distance; +}; + +#define NO_COMP 0 +#define FIXED_COMP 1 +#define DYNAMIC_COMP 2 + +long decompress_block(unsigned char *dest, unsigned char *source, + void *(*inflate_memcpy)(void *dest, const void *src, size n)); diff --git a/roms/u-boot/include/k3-avs.h b/roms/u-boot/include/k3-avs.h new file mode 100644 index 000000000..e3c3cafbb --- /dev/null +++ b/roms/u-boot/include/k3-avs.h @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments' K3 Adaptive Voltage Scaling driver + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Tero Kristo + * + */ + +#ifndef _K3_AVS0_ +#define _K3_AVS0_ + +#define AM6_VDD_WKUP 0 +#define AM6_VDD_MCU 1 +#define AM6_VDD_CORE 2 +#define AM6_VDD_MPU0 3 +#define AM6_VDD_MPU1 4 + +#define J721E_VDD_MPU 2 + +#define NUM_OPPS 4 + +#define AM6_OPP_NOM 1 +#define AM6_OPP_OD 2 +#define AM6_OPP_TURBO 3 + +int k3_avs_set_opp(struct udevice *dev, int vdd_id, int opp_id); +int k3_avs_notify_freq(int dev_id, int clk_id, u32 freq); + +#endif diff --git a/roms/u-boot/include/kendryte/bypass.h b/roms/u-boot/include/kendryte/bypass.h new file mode 100644 index 000000000..ab85bbcbf --- /dev/null +++ b/roms/u-boot/include/kendryte/bypass.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Sean Anderson + */ +#ifndef K210_BYPASS_H +#define K210_BYPASS_H + +struct clk; + +struct k210_bypass { + struct clk clk; + struct clk **children; /* Clocks to reparent */ + struct clk **saved_parents; /* Parents saved over en-/dis-able */ + struct clk *bypassee; /* Clock to bypass */ + const struct clk_ops *bypassee_ops; /* Ops of the bypass clock */ + struct clk *alt; /* Clock to set children to when bypassing */ + size_t child_count; +}; + +#define to_k210_bypass(_clk) container_of(_clk, struct k210_bypass, clk) + +int k210_bypass_set_children(struct clk *clk, struct clk **children, + size_t child_count); +struct clk *k210_register_bypass_struct(const char *name, + const char *parent_name, + struct k210_bypass *bypass); +struct clk *k210_register_bypass(const char *name, const char *parent_name, + struct clk *bypassee, + const struct clk_ops *bypassee_ops, + struct clk *alt); +#endif /* K210_BYPASS_H */ diff --git a/roms/u-boot/include/kendryte/clk.h b/roms/u-boot/include/kendryte/clk.h new file mode 100644 index 000000000..9c6245d46 --- /dev/null +++ b/roms/u-boot/include/kendryte/clk.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-20 Sean Anderson + */ + +#ifndef K210_CLK_H +#define K210_CLK_H + +#define LOG_CATEGORY UCLASS_CLK +#include +#include + +static inline struct clk *k210_clk_gate(const char *name, + const char *parent_name, + void __iomem *reg, u8 bit_idx) +{ + return clk_register_gate(NULL, name, parent_name, 0, reg, bit_idx, 0, + NULL); +} + +static inline struct clk *k210_clk_half(const char *name, + const char *parent_name) +{ + return clk_register_fixed_factor(NULL, name, parent_name, 0, 1, 2); +} + +static inline struct clk *k210_clk_div(const char *name, + const char *parent_name, + void __iomem *reg, u8 shift, u8 width) +{ + return clk_register_divider(NULL, name, parent_name, 0, reg, shift, + width, 0); +} + +#endif /* K210_CLK_H */ diff --git a/roms/u-boot/include/kendryte/pll.h b/roms/u-boot/include/kendryte/pll.h new file mode 100644 index 000000000..95b8494f4 --- /dev/null +++ b/roms/u-boot/include/kendryte/pll.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-20 Sean Anderson + */ +#ifndef K210_PLL_H +#define K210_PLL_H + +#include +#include +#include + +#define K210_PLL_CLKR GENMASK(3, 0) +#define K210_PLL_CLKF GENMASK(9, 4) +#define K210_PLL_CLKOD GENMASK(13, 10) /* Output Divider */ +#define K210_PLL_BWADJ GENMASK(19, 14) /* BandWidth Adjust */ +#define K210_PLL_RESET BIT(20) +#define K210_PLL_PWRD BIT(21) /* PoWeReD */ +#define K210_PLL_INTFB BIT(22) /* Internal FeedBack */ +#define K210_PLL_BYPASS BIT(23) +#define K210_PLL_TEST BIT(24) +#define K210_PLL_EN BIT(25) +#define K210_PLL_TEST_EN BIT(26) + +#define K210_PLL_LOCK 0 +#define K210_PLL_CLEAR_SLIP 2 +#define K210_PLL_TEST_OUT 3 + +struct k210_pll { + struct clk clk; + void __iomem *reg; /* Base PLL register */ + void __iomem *lock; /* Common PLL lock register */ + u8 shift; /* Offset of bits in lock register */ + u8 width; /* Width of lock bits to test against */ +}; + +#define to_k210_pll(_clk) container_of(_clk, struct k210_pll, clk) + +struct k210_pll_config { + u8 r; + u8 f; + u8 od; +}; + +#ifdef CONFIG_UNIT_TEST +TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in, + struct k210_pll_config *best); + +#ifndef nop +#define nop() +#endif + +#endif + +extern const struct clk_ops k210_pll_ops; + +struct clk *k210_register_pll_struct(const char *name, const char *parent_name, + struct k210_pll *pll); +#endif /* K210_PLL_H */ diff --git a/roms/u-boot/include/key_matrix.h b/roms/u-boot/include/key_matrix.h new file mode 100644 index 000000000..519722f2d --- /dev/null +++ b/roms/u-boot/include/key_matrix.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Keyboard matrix helper functions + * + * Copyright (c) 2012 The Chromium OS Authors. + */ + +#ifndef _KEY_MATRIX_H +#define _KEY_MATRIX_H + +#include + +/* Information about a matrix keyboard */ +struct key_matrix { + /* Dimensions of the keyboard matrix, in rows and columns */ + int num_rows; + int num_cols; + int key_count; /* number of keys in the matrix (= rows * cols) */ + + /* + * Information about keycode mappings. The plain_keycode array must + * exist but fn may be NULL in which case it is not decoded. + */ + const u8 *plain_keycode; /* key code for each row / column */ + const u8 *fn_keycode; /* ...when Fn held down */ + int fn_pos; /* position of Fn key in key (or -1) */ + int ghost_filter; /* non-zero to enable ghost filter */ +}; + +/* Information about a particular key (row, column pair) in the matrix */ +struct key_matrix_key { + uint8_t row; /* row number (0 = first) */ + uint8_t col; /* column number (0 = first) */ + uint8_t valid; /* 1 if valid, 0 to ignore this */ +}; + +/** + * Decode a set of pressed keys into key codes + * + * Given a list of keys that are pressed, this converts this list into + * a list of key codes. Each of the keys has a valid flag, which can be + * used to mark a particular key as invalid (so that it is ignored). + * + * The plain keymap is used, unless the Fn key is detected along the way, + * at which point we switch to the Fn key map. + * + * If key ghosting is detected, we simply ignore the keys and return 0. + * + * @param config Keyboard matrix config + * @param keys List of keys to process (each is row, col) + * @param num_keys Number of keys to process + * @param keycode Returns a list of key codes, decoded from input + * @param max_keycodes Size of key codes array (suggest 8) + * + */ +int key_matrix_decode(struct key_matrix *config, struct key_matrix_key *keys, + int num_keys, int keycode[], int max_keycodes); + +/** + * Read the keyboard configuration out of the fdt. + * + * Decode properties of named "linux,keymap" where is either + * empty, or "fn-". Then set up the plain key map (and the FN keymap if + * present). + * + * @param config Keyboard matrix config + * @param blob FDT blob + * @param node Node containing compatible data + * @return 0 if ok, -1 on error + */ +int key_matrix_decode_fdt(struct udevice *dev, struct key_matrix *config); + +/** + * Set up a new key matrix. + * + * @param config Keyboard matrix config + * @param rows Number of rows in key matrix + * @param cols Number of columns in key matrix + * @param ghost_filter Non-zero to enable ghost filtering + * @return 0 if ok, -1 on error + */ +int key_matrix_init(struct key_matrix *config, int rows, int cols, + int ghost_filter); + +#endif diff --git a/roms/u-boot/include/keyboard.h b/roms/u-boot/include/keyboard.h new file mode 100644 index 000000000..7561954f7 --- /dev/null +++ b/roms/u-boot/include/keyboard.h @@ -0,0 +1,79 @@ +#ifndef __KEYBOARD_H +#define __KEYBOARD_H + +#include +#include + +/** + * struct keyboard_priv - information about a keyboard, for the uclass + * + * @sdev: stdio device + * @input: input configuration (the driver may use this if desired) + */ +struct keyboard_priv { + struct stdio_dev sdev; + + /* + * This is set up by the uclass but will only be used if the driver + * sets input.dev to its device pointer (it is initially NULL). + */ + struct input_config input; +}; + +/** + * struct keyboard_ops - keyboard device operations + */ +struct keyboard_ops { + /** + * start() - enable the keyboard ready for use + * + * @dev: Device to enable + * @return 0 if OK, -ve on error + */ + int (*start)(struct udevice *dev); + + /** + * stop() - disable the keyboard when no-longer needed + * + * @dev: Device to disable + * @return 0 if OK, -ve on error + */ + int (*stop)(struct udevice *dev); + + /** + * tstc() - check if a key is available + * + * @dev: Device to check + * @return 0 if no key is available, 1 if a key is available, -ve on + * error + */ + int (*tstc)(struct udevice *dev); + + /** + * getc() - get a key + * + * TODO(sjg@chromium.org): At present this method may wait if it calls + * input_getc(). + * + * @dev: Device to read from + * @return -EAGAIN if no key is available, otherwise key value read + * (as ASCII). + */ + int (*getc)(struct udevice *dev); + + /** + * update_leds() - update keyboard LEDs + * + * This is called when the LEDs have changed and need to be updated. + * For example, if 'caps lock' is pressed then this method will be + * called with the new LED value. + * + * @dev: Device to update + * @leds: New LED mask (see INPUT_LED_... in input.h) + */ + int (*update_leds)(struct udevice *dev, int leds); +}; + +#define keyboard_get_ops(dev) ((struct keyboard_ops *)(dev)->driver->ops) + +#endif /* __KEYBOARD_H */ diff --git a/roms/u-boot/include/keys/asymmetric-type.h b/roms/u-boot/include/keys/asymmetric-type.h new file mode 100644 index 000000000..47d83917d --- /dev/null +++ b/roms/u-boot/include/keys/asymmetric-type.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Asymmetric Public-key cryptography key type interface + * + * See Documentation/crypto/asymmetric-keys.txt + * + * Copyright (C) 2012 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + */ + +#ifndef _KEYS_ASYMMETRIC_TYPE_H +#define _KEYS_ASYMMETRIC_TYPE_H + +#ifndef __UBOOT__ +#include +#include + +extern struct key_type key_type_asymmetric; + +/* + * The key payload is four words. The asymmetric-type key uses them as + * follows: + */ +enum asymmetric_payload_bits { + asym_crypto, /* The data representing the key */ + asym_subtype, /* Pointer to an asymmetric_key_subtype struct */ + asym_key_ids, /* Pointer to an asymmetric_key_ids struct */ + asym_auth /* The key's authorisation (signature, parent key ID) */ +}; +#endif /* !__UBOOT__ */ + +/* + * Identifiers for an asymmetric key ID. We have three ways of looking up a + * key derived from an X.509 certificate: + * + * (1) Serial Number & Issuer. Non-optional. This is the only valid way to + * map a PKCS#7 signature to an X.509 certificate. + * + * (2) Issuer & Subject Unique IDs. Optional. These were the original way to + * match X.509 certificates, but have fallen into disuse in favour of (3). + * + * (3) Auth & Subject Key Identifiers. Optional. SKIDs are only provided on + * CA keys that are intended to sign other keys, so don't appear in end + * user certificates unless forced. + * + * We could also support an PGP key identifier, which is just a SHA1 sum of the + * public key and certain parameters, but since we don't support PGP keys at + * the moment, we shall ignore those. + * + * What we actually do is provide a place where binary identifiers can be + * stashed and then compare against them when checking for an id match. + */ +struct asymmetric_key_id { + unsigned short len; + unsigned char data[]; +}; + +struct asymmetric_key_ids { + void *id[2]; +}; + +extern bool asymmetric_key_id_same(const struct asymmetric_key_id *kid1, + const struct asymmetric_key_id *kid2); + +extern bool asymmetric_key_id_partial(const struct asymmetric_key_id *kid1, + const struct asymmetric_key_id *kid2); + +extern struct asymmetric_key_id *asymmetric_key_generate_id(const void *val_1, + size_t len_1, + const void *val_2, + size_t len_2); +#ifndef __UBOOT__ +static inline +const struct asymmetric_key_ids *asymmetric_key_ids(const struct key *key) +{ + return key->payload.data[asym_key_ids]; +} + +extern struct key *find_asymmetric_key(struct key *keyring, + const struct asymmetric_key_id *id_0, + const struct asymmetric_key_id *id_1, + bool partial); +#endif + +/* + * The payload is at the discretion of the subtype. + */ + +#endif /* _KEYS_ASYMMETRIC_TYPE_H */ diff --git a/roms/u-boot/include/kgdb.h b/roms/u-boot/include/kgdb.h new file mode 100644 index 000000000..616ce4451 --- /dev/null +++ b/roms/u-boot/include/kgdb.h @@ -0,0 +1,70 @@ +#ifndef __KGDB_H__ +#define __KGDB_H__ + +#include + +#define KGDBERR_BADPARAMS 1 +#define KGDBERR_NOTHEXDIG 2 +#define KGDBERR_MEMFAULT 3 +#define KGDBERR_NOSPACE 4 +#define KGDBERR_ALIGNFAULT 5 + +#define KGDBDATA_MAXREGS 8 +#define KGDBDATA_MAXPRIV 8 + +#define KGDBEXIT_TYPEMASK 0xff + +#define KGDBEXIT_KILL 0 +#define KGDBEXIT_CONTINUE 1 +#define KGDBEXIT_SINGLE 2 + +#define KGDBEXIT_WITHADDR 0x100 + +typedef + struct { + int num; + unsigned long val; + } +kgdb_reg; + +typedef + struct { + int sigval; + int extype; + unsigned long exaddr; + int nregs; + kgdb_reg regs[KGDBDATA_MAXREGS]; + unsigned long private[KGDBDATA_MAXPRIV]; + } +kgdb_data; + +/* these functions are provided by the generic kgdb support */ +extern void kgdb_init(void); +extern void kgdb_error(int); +extern int kgdb_output_string(const char *, unsigned int); +extern void breakpoint(void); + +/* these functions are provided by the platform specific kgdb support */ +extern void kgdb_flush_cache_range(void *, void *); +extern void kgdb_flush_cache_all(void); +extern int kgdb_setjmp(long *); +extern void kgdb_longjmp(long *, int); +extern void kgdb_enter(struct pt_regs *, kgdb_data *); +extern void kgdb_exit(struct pt_regs *, kgdb_data *); +extern int kgdb_getregs(struct pt_regs *, char *, int); +extern void kgdb_putreg(struct pt_regs *, int, char *, int); +extern void kgdb_putregs(struct pt_regs *, char *, int); +extern int kgdb_trap(struct pt_regs *); +void kgdb_breakpoint(int argc, char *const argv[]); + +/* these functions are provided by the platform serial driver */ +extern void kgdb_serial_init(void); +extern int getDebugChar(void); +extern void putDebugChar(int); +extern void putDebugStr(const char *); +extern void kgdb_interruptible(int); + +/* this is referenced in the trap handler for the platform */ +extern int (*debugger_exception_handler)(struct pt_regs *); + +#endif /* __KGDB_H__ */ diff --git a/roms/u-boot/include/lattice.h b/roms/u-boot/include/lattice.h new file mode 100644 index 000000000..80fafc00d --- /dev/null +++ b/roms/u-boot/include/lattice.h @@ -0,0 +1,298 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Porting to U-Boot: + * + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Lattice's ispVME Embedded Tool to load Lattice's FPGA: + * + * Lattice Semiconductor Corp. Copyright 2009 + */ + +#ifndef _VME_OPCODE_H +#define _VME_OPCODE_H + +#define VME_VERSION_NUMBER "12.1" + +/* Maximum declarations. */ + +#define VMEHEXMAX 60000L /* The hex file is split 60K per file. */ +#define SCANMAX 64000L /* The maximum SDR/SIR burst. */ + +/* + * + * Supported JTAG state transitions. + * + */ + +#define RESET 0x00 +#define IDLE 0x01 +#define IRPAUSE 0x02 +#define DRPAUSE 0x03 +#define SHIFTIR 0x04 +#define SHIFTDR 0x05 +/* 11/15/05 Nguyen changed to support DRCAPTURE*/ +#define DRCAPTURE 0x06 + +/* + * Flow control register bit definitions. A set bit indicates + * that the register currently exhibits the corresponding mode. + */ + +#define INTEL_PRGM 0x0001 /* Intelligent programming is in effect. */ +#define CASCADE 0x0002 /* Currently splitting large SDR. */ +#define REPEATLOOP 0x0008 /* Currently executing a repeat loop. */ +#define SHIFTRIGHT 0x0080 /* The next data stream needs a right shift. */ +#define SHIFTLEFT 0x0100 /* The next data stream needs a left shift. */ +#define VERIFYUES 0x0200 /* Continue if fail is in effect. */ + +/* + * DataType register bit definitions. A set bit indicates + * that the register currently holds the corresponding type of data. + */ + +#define EXPRESS 0x0001 /* Simultaneous program and verify. */ +#define SIR_DATA 0x0002 /* SIR is the active SVF command. */ +#define SDR_DATA 0x0004 /* SDR is the active SVF command. */ +#define COMPRESS 0x0008 /* Data is compressed. */ +#define TDI_DATA 0x0010 /* TDI data is present. */ +#define TDO_DATA 0x0020 /* TDO data is present. */ +#define MASK_DATA 0x0040 /* MASK data is present. */ +#define HEAP_IN 0x0080 /* Data is from the heap. */ +#define LHEAP_IN 0x0200 /* Data is from intel data buffer. */ +#define VARIABLE 0x0400 /* Data is from a declared variable. */ +#define CRC_DATA 0x0800 /* CRC data is pressent. */ +#define CMASK_DATA 0x1000 /* CMASK data is pressent. */ +#define RMASK_DATA 0x2000 /* RMASK data is pressent. */ +#define READ_DATA 0x4000 /* READ data is pressent. */ +#define DMASK_DATA 0x8000 /* DMASK data is pressent. */ + +/* + * + * Pin opcodes. + * + */ + +#define signalENABLE 0x1C /* ispENABLE pin. */ +#define signalTMS 0x1D /* TMS pin. */ +#define signalTCK 0x1E /* TCK pin. */ +#define signalTDI 0x1F /* TDI pin. */ +#define signalTRST 0x20 /* TRST pin. */ + +/* + * + * Supported vendors. + * + */ + +#define VENDOR 0x56 +#define LATTICE 0x01 +#define ALTERA 0x02 +#define XILINX 0x03 + +/* + * Opcode definitions. + * + * Note: opcodes must be unique. + */ + +#define ENDDATA 0x00 /* The end of the current SDR data stream. */ +#define RUNTEST 0x01 /* The duration to stay at the stable state. */ +#define ENDDR 0x02 /* The stable state after SDR. */ +#define ENDIR 0x03 /* The stable state after SIR. */ +#define ENDSTATE 0x04 /* The stable state after RUNTEST. */ +#define TRST 0x05 /* Assert the TRST pin. */ +#define HIR 0x06 /* + * The sum of the IR bits of the + * leading devices. + */ +#define TIR 0x07 /* + * The sum of the IR bits of the trailing + * devices. + */ +#define HDR 0x08 /* The number of leading devices. */ +#define TDR 0x09 /* The number of trailing devices. */ +#define ispEN 0x0A /* Assert the ispEN pin. */ +#define FREQUENCY 0x0B /* + * The maximum clock rate to run the JTAG state + * machine. + */ +#define STATE 0x10 /* Move to the next stable state. */ +#define SIR 0x11 /* The instruction stream follows. */ +#define SDR 0x12 /* The data stream follows. */ +#define TDI 0x13 /* The following data stream feeds into + the device. */ +#define TDO 0x14 /* + * The following data stream is compared against + * the device. + */ +#define MASK 0x15 /* The following data stream is used as mask. */ +#define XSDR 0x16 /* + * The following data stream is for simultaneous + * program and verify. + */ +#define XTDI 0x17 /* The following data stream is for shift in + * only. It must be stored for the next + * XSDR. + */ +#define XTDO 0x18 /* + * There is not data stream. The data stream + * was stored from the previous XTDI. + */ +#define MEM 0x19 /* + * The maximum memory needed to allocate in + * order hold one row of data. + */ +#define WAIT 0x1A /* The duration of delay to observe. */ +#define TCK 0x1B /* The number of TCK pulses. */ +#define SHR 0x23 /* + * Set the flow control register for + * right shift + */ +#define SHL 0x24 /* + * Set the flow control register for left shift. + */ +#define HEAP 0x32 /* The memory size needed to hold one loop. */ +#define REPEAT 0x33 /* The beginning of the loop. */ +#define LEFTPAREN 0x35 /* The beginning of data following the loop. */ +#define VAR 0x55 /* Plac holder for loop data. */ +#define SEC 0x1C /* + * The delay time in seconds that must be + * observed. + */ +#define SMASK 0x1D /* The mask for TDI data. */ +#define MAX_WAIT 0x1E /* The absolute maximum wait time. */ +#define ON 0x1F /* Assert the targeted pin. */ +#define OFF 0x20 /* Dis-assert the targeted pin. */ +#define SETFLOW 0x30 /* Change the flow control register. */ +#define RESETFLOW 0x31 /* Clear the flow control register. */ + +#define CRC 0x47 /* + * The following data stream is used for CRC + * calculation. + */ +#define CMASK 0x48 /* + * The following data stream is used as mask + * for CRC calculation. + */ +#define RMASK 0x49 /* + * The following data stream is used as mask + * for read and save. + */ +#define READ 0x50 /* + * The following data stream is used for read + * and save. + */ +#define ENDLOOP 0x59 /* The end of the repeat loop. */ +#define SECUREHEAP 0x60 /* Used to secure the HEAP opcode. */ +#define VUES 0x61 /* Support continue if fail. */ +#define DMASK 0x62 /* + * The following data stream is used for dynamic + * I/O. + */ +#define COMMENT 0x63 /* Support SVF comments in the VME file. */ +#define HEADER 0x64 /* Support header in VME file. */ +#define FILE_CRC 0x65 /* Support crc-protected VME file. */ +#define LCOUNT 0x66 /* Support intelligent programming. */ +#define LDELAY 0x67 /* Support intelligent programming. */ +#define LSDR 0x68 /* Support intelligent programming. */ +#define LHEAP 0x69 /* + * Memory needed to hold intelligent data + * buffer + */ +#define CONTINUE 0x70 /* Allow continuation. */ +#define LVDS 0x71 /* Support LVDS. */ +#define ENDVME 0x7F /* End of the VME file. */ +#define ENDFILE 0xFF /* End of file. */ + +/* + * + * ispVM Embedded Return Codes. + * + */ + +#define VME_VERIFICATION_FAILURE -1 +#define VME_FILE_READ_FAILURE -2 +#define VME_VERSION_FAILURE -3 +#define VME_INVALID_FILE -4 +#define VME_ARGUMENT_FAILURE -5 +#define VME_CRC_FAILURE -6 + +#define g_ucPinTDI 0x01 +#define g_ucPinTCK 0x02 +#define g_ucPinTMS 0x04 +#define g_ucPinENABLE 0x08 +#define g_ucPinTRST 0x10 + +/* + * + * Type definitions. + * + */ + +/* Support LVDS */ +typedef struct { + unsigned short usPositiveIndex; + unsigned short usNegativeIndex; + unsigned char ucUpdate; +} LVDSPair; + +typedef enum { + min_lattice_iface_type, /* insert all new types after this */ + lattice_jtag_mode, /* jtag/tap */ + max_lattice_iface_type /* insert all new types before this */ +} Lattice_iface; + +typedef enum { + min_lattice_type, + Lattice_XP2, /* Lattice XP2 Family */ + max_lattice_type /* insert all new types before this */ +} Lattice_Family; + +typedef struct { + Lattice_Family family; /* part type */ + Lattice_iface iface; /* interface type */ + size_t size; /* bytes of data part can accept */ + void *iface_fns; /* interface function table */ + void *base; /* base interface address */ + int cookie; /* implementation specific cookie */ + char *desc; /* description string */ +} Lattice_desc; /* end, typedef Altera_desc */ + +/* Board specific implementation specific function types */ +typedef void (*Lattice_jtag_init)(void); +typedef void (*Lattice_jtag_set_tdi)(int v); +typedef void (*Lattice_jtag_set_tms)(int v); +typedef void (*Lattice_jtag_set_tck)(int v); +typedef int (*Lattice_jtag_get_tdo)(void); + +typedef struct { + Lattice_jtag_init jtag_init; + Lattice_jtag_set_tdi jtag_set_tdi; + Lattice_jtag_set_tms jtag_set_tms; + Lattice_jtag_set_tck jtag_set_tck; + Lattice_jtag_get_tdo jtag_get_tdo; +} lattice_board_specific_func; + +void writePort(unsigned char pins, unsigned char value); +unsigned char readPort(void); +void sclock(void); +void ispVMDelay(unsigned short int a_usMicroSecondDelay); +void calibration(void); + +int lattice_load(Lattice_desc *desc, const void *buf, size_t bsize); +int lattice_dump(Lattice_desc *desc, const void *buf, size_t bsize); +int lattice_info(Lattice_desc *desc); + +void ispVMStart(void); +void ispVMEnd(void); +extern void ispVMFreeMem(void); +signed char ispVMCode(void); +void ispVMDelay(unsigned short int a_usMicroSecondDelay); +void ispVMCalculateCRC32(unsigned char a_ucData); +unsigned char GetByte(void); +void writePort(unsigned char pins, unsigned char value); +unsigned char readPort(void); +void sclock(void); +#endif diff --git a/roms/u-boot/include/lcd.h b/roms/u-boot/include/lcd.h new file mode 100644 index 000000000..9a4c0da5b --- /dev/null +++ b/roms/u-boot/include/lcd.h @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * MPC823 and PXA LCD Controller + * + * Modeled after video interface by Paolo Scaffardi + * + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef _LCD_H_ +#define _LCD_H_ +#include +#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) +#include +#include +#endif + +int bmp_display(ulong addr, int x, int y); +struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp, + void **alloc_addr); + +#ifndef CONFIG_DM_VIDEO + +extern char lcd_is_enabled; +extern int lcd_line_length; +extern struct vidinfo panel_info; + +void lcd_ctrl_init(void *lcdbase); +void lcd_enable(void); +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue); +ulong lcd_setmem(ulong addr); + +/** + * Set whether we need to flush the dcache when changing the LCD image. This + * defaults to off. + * + * @param flush non-zero to flush cache after update, 0 to skip + */ +void lcd_set_flush_dcache(int flush); + +#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ + defined CONFIG_CPU_MONAHANS +#include +#elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD) +#include +#elif defined(CONFIG_EXYNOS_FB) +#include +#else +typedef struct vidinfo { + ushort vl_col; /* Number of columns (i.e. 160) */ + ushort vl_row; /* Number of rows (i.e. 100) */ + ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ + u_char vl_bpix; /* Bits per pixel, 0 = 1 */ + ushort *cmap; /* Pointer to the colormap */ + void *priv; /* Pointer to driver-specific data */ +} vidinfo_t; + +static __maybe_unused ushort *configuration_get_cmap(void) +{ + return panel_info.cmap; +} +#endif + +ushort *configuration_get_cmap(void); + +extern vidinfo_t panel_info; + +void lcd_putc(const char c); +void lcd_puts(const char *s); +void lcd_printf(const char *fmt, ...); +void lcd_clear(void); +int lcd_display_bitmap(ulong bmp_image, int x, int y); + +/** + * Get the width of the LCD in pixels + * + * @return width of LCD in pixels + */ +int lcd_get_pixel_width(void); + +/** + * Get the height of the LCD in pixels + * + * @return height of LCD in pixels + */ +int lcd_get_pixel_height(void); + +/** + * Get the number of text lines/rows on the LCD + * + * @return number of rows + */ +int lcd_get_screen_rows(void); + +/** + * Get the number of text columns on the LCD + * + * @return number of columns + */ +int lcd_get_screen_columns(void); + +/** + * Get the background color of the LCD + * + * @return background color value + */ +int lcd_getbgcolor(void); + +/** + * Get the foreground color of the LCD + * + * @return foreground color value + */ +int lcd_getfgcolor(void); + +/** + * Set the position of the text cursor + * + * @param col Column to place cursor (0 = left side) + * @param row Row to place cursor (0 = top line) + */ +void lcd_position_cursor(unsigned col, unsigned row); + +/* Allow boards to customize the information displayed */ +void lcd_show_board_info(void); + +/* Return the size of the LCD frame buffer, and the line length */ +int lcd_get_size(int *line_length); + +/* Update the LCD / flush the cache */ +void lcd_sync(void); + +/* + * Information about displays we are using. This is for configuring + * the LCD controller and memory allocation. Someone has to know what + * is connected, as we can't autodetect anything. + */ +#define CONFIG_SYS_HIGH 0 /* Pins are active high */ +#define CONFIG_SYS_LOW 1 /* Pins are active low */ + +#define LCD_MONOCHROME 0 +#define LCD_COLOR2 1 +#define LCD_COLOR4 2 +#define LCD_COLOR8 3 +#define LCD_COLOR16 4 +#define LCD_COLOR32 5 + +#if defined(CONFIG_LCD_INFO_BELOW_LOGO) +#define LCD_INFO_X 0 +#define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT) +#elif defined(CONFIG_LCD_LOGO) +#define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH) +#define LCD_INFO_Y VIDEO_FONT_HEIGHT +#else +#define LCD_INFO_X VIDEO_FONT_WIDTH +#define LCD_INFO_Y VIDEO_FONT_HEIGHT +#endif + +/* Default to 8bpp if bit depth not specified */ +#ifndef LCD_BPP +#define LCD_BPP LCD_COLOR8 +#endif + +#ifndef LCD_DF +#define LCD_DF 1 +#endif + +/* Calculate nr. of bits per pixel and nr. of colors */ +#define NBITS(bit_code) (1 << (bit_code)) +#define NCOLORS(bit_code) (1 << NBITS(bit_code)) + +#if LCD_BPP == LCD_COLOR8 +# define CONSOLE_COLOR_BLACK 0 +# define CONSOLE_COLOR_RED 1 +# define CONSOLE_COLOR_GREEN 2 +# define CONSOLE_COLOR_YELLOW 3 +# define CONSOLE_COLOR_BLUE 4 +# define CONSOLE_COLOR_MAGENTA 5 +# define CONSOLE_COLOR_CYAN 6 +# define CONSOLE_COLOR_GREY 14 +# define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ +#elif LCD_BPP == LCD_COLOR32 +#define CONSOLE_COLOR_RED 0x00ff0000 +#define CONSOLE_COLOR_GREEN 0x0000ff00 +#define CONSOLE_COLOR_YELLOW 0x00ffff00 +#define CONSOLE_COLOR_BLUE 0x000000ff +#define CONSOLE_COLOR_MAGENTA 0x00ff00ff +#define CONSOLE_COLOR_CYAN 0x0000ffff +#define CONSOLE_COLOR_GREY 0x00aaaaaa +#define CONSOLE_COLOR_BLACK 0x00000000 +#define CONSOLE_COLOR_WHITE 0x00ffffff /* Must remain last / highest */ +#define NBYTES(bit_code) (NBITS(bit_code) >> 3) +#else /* 16bpp color definitions */ +# define CONSOLE_COLOR_BLACK 0x0000 +# define CONSOLE_COLOR_RED 0xF800 +# define CONSOLE_COLOR_GREEN 0x07E0 +# define CONSOLE_COLOR_YELLOW 0xFFE0 +# define CONSOLE_COLOR_BLUE 0x001F +# define CONSOLE_COLOR_MAGENTA 0xF81F +# define CONSOLE_COLOR_CYAN 0x07FF +# define CONSOLE_COLOR_GREY 0xC618 +# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ +#endif /* color definitions */ + +#if LCD_BPP == LCD_COLOR16 +#define fbptr_t ushort +#elif LCD_BPP == LCD_COLOR32 +#define fbptr_t u32 +#else +#define fbptr_t uchar +#endif + +#ifndef PAGE_SIZE +#define PAGE_SIZE 4096 +#endif + +#endif /* !CONFIG_DM_VIDEO */ + +#endif /* _LCD_H_ */ diff --git a/roms/u-boot/include/lcd_console.h b/roms/u-boot/include/lcd_console.h new file mode 100644 index 000000000..061a6a41b --- /dev/null +++ b/roms/u-boot/include/lcd_console.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + */ + +/* By default we scroll by a single line */ + +struct console_t { + short curr_col, curr_row; + short cols, rows; + void *fbbase; + u32 lcdsizex, lcdsizey, lcdrot; + void (*fp_putc_xy)(struct console_t *pcons, ushort x, ushort y, char c); + void (*fp_console_moverow)(struct console_t *pcons, + u32 rowdst, u32 rowsrc); + void (*fp_console_setrow)(struct console_t *pcons, u32 row, int clr); +}; + +/** + * console_calc_rowcol() - calculate available rows / columns wihtin a given + * screen-size based on used VIDEO_FONT. + * + * @pcons: Pointer to struct console_t + * @sizex: size X of the screen in pixel + * @sizey: size Y of the screen in pixel + */ +void console_calc_rowcol(struct console_t *pcons, u32 sizex, u32 sizey); +/** + * lcd_init_console() - Initialize lcd console parameters + * + * Setup the address of console base, and the number of rows and columns the + * console has. + * + * @address: Console base address + * @vl_rows: Number of rows in the console + * @vl_cols: Number of columns in the console + * @vl_rot: Rotation of display in degree (0 - 90 - 180 - 270) counterlockwise + */ +void lcd_init_console(void *address, int vl_cols, int vl_rows, int vl_rot); +/** + * lcd_set_col() - Set the number of the current lcd console column + * + * Set the number of the console column where the cursor is. + * + * @col: Column number + */ +void lcd_set_col(short col); + +/** + * lcd_set_row() - Set the number of the current lcd console row + * + * Set the number of the console row where the cursor is. + * + * @row: Row number + */ +void lcd_set_row(short row); + +/** + * lcd_position_cursor() - Position the cursor on the screen + * + * Position the cursor at the given coordinates on the screen. + * + * @col: Column number + * @row: Row number + */ +void lcd_position_cursor(unsigned col, unsigned row); + +/** + * lcd_get_screen_rows() - Get the total number of screen rows + * + * @return: Number of screen rows + */ +int lcd_get_screen_rows(void); + +/** + * lcd_get_screen_columns() - Get the total number of screen columns + * + * @return: Number of screen columns + */ +int lcd_get_screen_columns(void); + +/** + * lcd_putc() - Print to screen a single character at the location of the cursor + * + * @c: The character to print + */ +void lcd_putc(const char c); + +/** + * lcd_puts() - Print to screen a string at the location of the cursor + * + * @s: The string to print + */ +void lcd_puts(const char *s); + +/** + * lcd_printf() - Print to screen a formatted string at location of the cursor + * + * @fmt: The formatted string to print + * @...: The arguments for the formatted string + */ +void lcd_printf(const char *fmt, ...); diff --git a/roms/u-boot/include/lcdvideo.h b/roms/u-boot/include/lcdvideo.h new file mode 100644 index 000000000..f0640a538 --- /dev/null +++ b/roms/u-boot/include/lcdvideo.h @@ -0,0 +1,69 @@ +/* + * MPC823 LCD and Video Controller + * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) + */ +#ifndef __LCDVIDEO_H__ +#define __LCDVIDEO_H__ + + +/* LCD Controller Configuration Register. +*/ +#define LCCR_BNUM ((uint)0xfffe0000) +#define LCCR_EIEN ((uint)0x00010000) +#define LCCR_IEN ((uint)0x00008000) +#define LCCR_IRQL ((uint)0x00007000) +#define LCCR_CLKP ((uint)0x00000800) +#define LCCR_OEP ((uint)0x00000400) +#define LCCR_HSP ((uint)0x00000200) +#define LCCR_VSP ((uint)0x00000100) +#define LCCR_DP ((uint)0x00000080) +#define LCCR_BPIX ((uint)0x00000060) +#define LCCR_LBW ((uint)0x00000010) +#define LCCR_SPLT ((uint)0x00000008) +#define LCCR_CLOR ((uint)0x00000004) +#define LCCR_TFT ((uint)0x00000002) +#define LCCR_PON ((uint)0x00000001) + +/* Define the bit shifts to load values into the register. +*/ +#define LCDBIT(BIT, VAL) ((VAL) << (31 - BIT)) + +#define LCCR_BNUM_BIT ((uint)14) +#define LCCR_EIEN_BIT ((uint)15) +#define LCCR_IEN_BIT ((uint)16) +#define LCCR_IROL_BIT ((uint)19) +#define LCCR_CLKP_BIT ((uint)20) +#define LCCR_OEP_BIT ((uint)21) +#define LCCR_HSP_BIT ((uint)22) +#define LCCR_VSP_BIT ((uint)23) +#define LCCR_DP_BIT ((uint)24) +#define LCCR_BPIX_BIT ((uint)26) +#define LCCR_LBW_BIT ((uint)27) +#define LCCR_SPLT_BIT ((uint)28) +#define LCCR_CLOR_BIT ((uint)29) +#define LCCR_TFT_BIT ((uint)30) +#define LCCR_PON_BIT ((uint)31) + +/* LCD Horizontal control register. +*/ +#define LCHCR_BO ((uint)0x01000000) +#define LCHCR_AT ((uint)0x00e00000) +#define LCHCR_HPC ((uint)0x001ffc00) +#define LCHCR_WBL ((uint)0x000003ff) + +#define LCHCR_AT_BIT ((uint)10) +#define LCHCR_HPC_BIT ((uint)21) +#define LCHCR_WBL_BIT ((uint)31) + +/* LCD Vertical control register. +*/ +#define LCVCR_VPW ((uint)0xf0000000) +#define LCVCR_LCD_AC ((uint)0x01e00000) +#define LCVCR_VPC ((uint)0x001ff800) +#define LCVCR_WBF ((uint)0x000003ff) + +#define LCVCR_VPW_BIT ((uint)3) +#define LCVCR_LCD_AC_BIT ((uint)10) +#define LCVCR_VPC_BIT ((uint)20) + +#endif /* __LCDVIDEO_H__ */ diff --git a/roms/u-boot/include/ld9040.h b/roms/u-boot/include/ld9040.h new file mode 100644 index 000000000..58413d0a3 --- /dev/null +++ b/roms/u-boot/include/ld9040.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * ld9040 AMOLED LCD panel driver. + * + * Copyright (C) 2012 Samsung Electronics + * Donghwa Lee + */ + +#ifndef __LD9040_H_ +#define __LD9040_H_ + +void ld9040_cfg_ldo(void); +void ld9040_enable_ldo(unsigned int onoff); + +#endif /* __LD9040_H_ */ diff --git a/roms/u-boot/include/led.h b/roms/u-boot/include/led.h new file mode 100644 index 000000000..02766fa56 --- /dev/null +++ b/roms/u-boot/include/led.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass + */ + +#ifndef __LED_H +#define __LED_H + +struct udevice; + +/** + * struct led_uc_plat - Platform data the uclass stores about each device + * + * @label: LED label + */ +struct led_uc_plat { + const char *label; +}; + +/** + * struct led_uc_priv - Private data the uclass stores about each device + * + * @period_ms: Flash period in milliseconds + */ +struct led_uc_priv { + int period_ms; +}; + +enum led_state_t { + LEDST_OFF = 0, + LEDST_ON = 1, + LEDST_TOGGLE, +#ifdef CONFIG_LED_BLINK + LEDST_BLINK, +#endif + + LEDST_COUNT, +}; + +struct led_ops { + /** + * set_state() - set the state of an LED + * + * @dev: LED device to change + * @state: LED state to set + * @return 0 if OK, -ve on error + */ + int (*set_state)(struct udevice *dev, enum led_state_t state); + + /** + * led_get_state() - get the state of an LED + * + * @dev: LED device to change + * @return LED state led_state_t, or -ve on error + */ + enum led_state_t (*get_state)(struct udevice *dev); + +#ifdef CONFIG_LED_BLINK + /** + * led_set_period() - set the blink period of an LED + * + * Thie records the period if supported, or returns -ENOSYS if not. + * To start the LED blinking, use set_state(). + * + * @dev: LED device to change + * @period_ms: LED blink period in milliseconds + * @return 0 if OK, -ve on error + */ + int (*set_period)(struct udevice *dev, int period_ms); +#endif +}; + +#define led_get_ops(dev) ((struct led_ops *)(dev)->driver->ops) + +/** + * led_get_by_label() - Find an LED device by label + * + * @label: LED label to look up + * @devp: Returns the associated device, if found + * @return 0 if found, -ENODEV if not found, other -ve on error + */ +int led_get_by_label(const char *label, struct udevice **devp); + +/** + * led_set_state() - set the state of an LED + * + * @dev: LED device to change + * @state: LED state to set + * @return 0 if OK, -ve on error + */ +int led_set_state(struct udevice *dev, enum led_state_t state); + +/** + * led_get_state() - get the state of an LED + * + * @dev: LED device to change + * @return LED state led_state_t, or -ve on error + */ +enum led_state_t led_get_state(struct udevice *dev); + +/** + * led_set_period() - set the blink period of an LED + * + * @dev: LED device to change + * @period_ms: LED blink period in milliseconds + * @return 0 if OK, -ve on error + */ +int led_set_period(struct udevice *dev, int period_ms); + +/** + * led_default_state() - set the default state for all the LED + * + * This enables all leds which have default state. + * see Documentation/devicetree/bindings/leds/common.txt + * + */ +int led_default_state(void); + +#endif diff --git a/roms/u-boot/include/libata.h b/roms/u-boot/include/libata.h new file mode 100644 index 000000000..b03b29960 --- /dev/null +++ b/roms/u-boot/include/libata.h @@ -0,0 +1,654 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2003-2004 Red Hat, Inc. All rights reserved. + * Copyright 2003-2004 Jeff Garzik + * Copyright (C) 2008 Freescale Semiconductor, Inc. + * Dave Liu + * port from libata of linux kernel + */ + +#ifndef __LIBATA_H__ +#define __LIBATA_H__ + +#include + +enum { + /* various global constants */ + ATA_MAX_DEVICES = 2, /* per bus/port */ + ATA_MAX_PRD = 256, /* we could make these 256/256 */ + ATA_SECT_SIZE = 512, + ATA_MAX_SECTORS_128 = 128, + ATA_MAX_SECTORS = 256, + ATA_MAX_SECTORS_LBA48 = 65535, + ATA_MAX_SECTORS_TAPE = 65535, + + ATA_ID_WORDS = 256, + ATA_ID_SERNO = 10, + ATA_ID_FW_REV = 23, + ATA_ID_PROD = 27, + ATA_ID_OLD_PIO_MODES = 51, + ATA_ID_FIELD_VALID = 53, + ATA_ID_LBA_SECTORS = 60, + ATA_ID_MWDMA_MODES = 63, + ATA_ID_PIO_MODES = 64, + ATA_ID_EIDE_DMA_MIN = 65, + ATA_ID_EIDE_PIO = 67, + ATA_ID_EIDE_PIO_IORDY = 68, + ATA_ID_PIO4 = (1 << 1), + ATA_ID_QUEUE_DEPTH = 75, + ATA_ID_SATA_CAP = 76, + ATA_ID_SATA_FEATURES = 78, + ATA_ID_SATA_FEATURES_EN = 79, + ATA_ID_MAJOR_VER = 80, + ATA_ID_MINOR_VER = 81, + ATA_ID_UDMA_MODES = 88, + ATA_ID_LBA48_SECTORS = 100, + + ATA_ID_SERNO_LEN = 20, + ATA_ID_FW_REV_LEN = 8, + ATA_ID_PROD_LEN = 40, + + ATA_PCI_CTL_OFS = 2, + + ATA_PIO0 = (1 << 0), + ATA_PIO1 = ATA_PIO0 | (1 << 1), + ATA_PIO2 = ATA_PIO1 | (1 << 2), + ATA_PIO3 = ATA_PIO2 | (1 << 3), + ATA_PIO4 = ATA_PIO3 | (1 << 4), + ATA_PIO5 = ATA_PIO4 | (1 << 5), + ATA_PIO6 = ATA_PIO5 | (1 << 6), + + ATA_SWDMA0 = (1 << 0), + ATA_SWDMA1 = ATA_SWDMA0 | (1 << 1), + ATA_SWDMA2 = ATA_SWDMA1 | (1 << 2), + + ATA_SWDMA2_ONLY = (1 << 2), + + ATA_MWDMA0 = (1 << 0), + ATA_MWDMA1 = ATA_MWDMA0 | (1 << 1), + ATA_MWDMA2 = ATA_MWDMA1 | (1 << 2), + + ATA_MWDMA12_ONLY = (1 << 1) | (1 << 2), + ATA_MWDMA2_ONLY = (1 << 2), + + ATA_UDMA0 = (1 << 0), + ATA_UDMA1 = ATA_UDMA0 | (1 << 1), + ATA_UDMA2 = ATA_UDMA1 | (1 << 2), + ATA_UDMA3 = ATA_UDMA2 | (1 << 3), + ATA_UDMA4 = ATA_UDMA3 | (1 << 4), + ATA_UDMA5 = ATA_UDMA4 | (1 << 5), + ATA_UDMA6 = ATA_UDMA5 | (1 << 6), + ATA_UDMA7 = ATA_UDMA6 | (1 << 7), + /* ATA_UDMA7 is just for completeness... doesn't exist (yet?). */ + + ATA_UDMA_MASK_40C = ATA_UDMA2, /* udma0-2 */ + + /* DMA-related */ + ATA_PRD_SZ = 8, + ATA_PRD_TBL_SZ = (ATA_MAX_PRD * ATA_PRD_SZ), + ATA_PRD_EOT = (1 << 31), /* end-of-table flag */ + + ATA_DMA_TABLE_OFS = 4, + ATA_DMA_STATUS = 2, + ATA_DMA_CMD = 0, + ATA_DMA_WR = (1 << 3), + ATA_DMA_START = (1 << 0), + ATA_DMA_INTR = (1 << 2), + ATA_DMA_ERR = (1 << 1), + ATA_DMA_ACTIVE = (1 << 0), + + /* bits in ATA command block registers */ + ATA_HOB = (1 << 7), /* LBA48 selector */ + ATA_NIEN = (1 << 1), /* disable-irq flag */ + ATA_LBA = (1 << 6), /* LBA28 selector */ + ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */ + ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */ + ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */ + ATA_BUSY = (1 << 7), /* BSY status bit */ + ATA_DRDY = (1 << 6), /* device ready */ + ATA_DF = (1 << 5), /* device fault */ + ATA_DRQ = (1 << 3), /* data request i/o */ + ATA_ERR = (1 << 0), /* have an error */ + ATA_SRST = (1 << 2), /* software reset */ + ATA_ICRC = (1 << 7), /* interface CRC error */ + ATA_UNC = (1 << 6), /* uncorrectable media error */ + ATA_IDNF = (1 << 4), /* ID not found */ + ATA_ABORTED = (1 << 2), /* command aborted */ + + /* ATA command block registers */ + ATA_REG_DATA = 0x00, + ATA_REG_ERR = 0x01, + ATA_REG_NSECT = 0x02, + ATA_REG_LBAL = 0x03, + ATA_REG_LBAM = 0x04, + ATA_REG_LBAH = 0x05, + ATA_REG_DEVICE = 0x06, + ATA_REG_STATUS = 0x07, + + ATA_REG_FEATURE = ATA_REG_ERR, /* and their aliases */ + ATA_REG_CMD = ATA_REG_STATUS, + ATA_REG_BYTEL = ATA_REG_LBAM, + ATA_REG_BYTEH = ATA_REG_LBAH, + ATA_REG_DEVSEL = ATA_REG_DEVICE, + ATA_REG_IRQ = ATA_REG_NSECT, + + /* ATA device commands */ + ATA_CMD_DEV_RESET = 0x08, /* ATAPI device reset */ + ATA_CMD_PIO_READ = 0x20, /* Read sectors with retry */ + ATA_CMD_PIO_READ_EXT = 0x24, + ATA_CMD_READ_EXT = 0x25, + ATA_CMD_READ_NATIVE_MAX_EXT = 0x27, + ATA_CMD_READ_MULTI_EXT = 0x29, + ATA_CMD_READ_LOG_EXT = 0x2f, + ATA_CMD_PIO_WRITE = 0x30, /* write sectors with retry */ + ATA_CMD_PIO_WRITE_EXT = 0x34, + ATA_CMD_WRITE_EXT = 0x35, + ATA_CMD_SET_MAX_EXT = 0x37, + ATA_CMD_WRITE_MULTI_EXT = 0x39, + ATA_CMD_WRITE_FUA_EXT = 0x3D, + ATA_CMD_VERIFY = 0x40, /* read verify sectors with retry */ + ATA_CMD_VERIFY_EXT = 0x42, + ATA_CMD_FPDMA_READ = 0x60, + ATA_CMD_FPDMA_WRITE = 0x61, + ATA_CMD_EDD = 0x90, /* execute device diagnostic */ + ATA_CMD_INIT_DEV_PARAMS = 0x91, /* initialize device parameters */ + ATA_CMD_PACKET = 0xA0, /* ATAPI packet */ + ATA_CMD_ID_ATAPI = 0xA1, /* ATAPI identify device */ + ATA_CMD_CONF_OVERLAY = 0xB1, + ATA_CMD_READ_MULTI = 0xC4, /* read multiple */ + ATA_CMD_WRITE_MULTI = 0xC5, /* write multiple */ + ATA_CMD_SET_MULTI = 0xC6, /* set multiple mode */ + ATA_CMD_READ = 0xC8, /* read DMA with retry */ + ATA_CMD_WRITE = 0xCA, /* write DMA with retry */ + ATA_CMD_WRITE_MULTI_FUA_EXT = 0xCE, + ATA_CMD_STANDBYNOW1 = 0xE0, /* standby immediate */ + ATA_CMD_IDLEIMMEDIATE = 0xE1, /* idle immediate */ + ATA_CMD_STANDBY = 0xE2, /* place in standby power mode */ + ATA_CMD_IDLE = 0xE3, /* place in idle power mode */ + ATA_CMD_PMP_READ = 0xE4, /* read buffer */ + ATA_CMD_CHK_POWER = 0xE5, /* check power mode */ + ATA_CMD_SLEEP = 0xE6, /* sleep */ + ATA_CMD_FLUSH = 0xE7, + ATA_CMD_PMP_WRITE = 0xE8, /* write buffer */ + ATA_CMD_FLUSH_EXT = 0xEA, + ATA_CMD_ID_ATA = 0xEC, /* identify device */ + ATA_CMD_SET_FEATURES = 0xEF, /* set features */ + ATA_CMD_SEC_FREEZE_LOCK = 0xF5, /* security freeze */ + ATA_CMD_READ_NATIVE_MAX = 0xF8, + ATA_CMD_SET_MAX = 0xF9, + + /* READ_LOG_EXT pages */ + ATA_LOG_SATA_NCQ = 0x10, + + /* READ/WRITE LONG (obsolete) */ + ATA_CMD_READ_LONG = 0x22, + ATA_CMD_READ_LONG_ONCE = 0x23, + ATA_CMD_WRITE_LONG = 0x32, + ATA_CMD_WRITE_LONG_ONCE = 0x33, + + /* SETFEATURES stuff */ + SETFEATURES_XFER = 0x03, + XFER_UDMA_7 = 0x47, + XFER_UDMA_6 = 0x46, + XFER_UDMA_5 = 0x45, + XFER_UDMA_4 = 0x44, + XFER_UDMA_3 = 0x43, + XFER_UDMA_2 = 0x42, + XFER_UDMA_1 = 0x41, + XFER_UDMA_0 = 0x40, + XFER_MW_DMA_4 = 0x24, /* CFA only */ + XFER_MW_DMA_3 = 0x23, /* CFA only */ + XFER_MW_DMA_2 = 0x22, + XFER_MW_DMA_1 = 0x21, + XFER_MW_DMA_0 = 0x20, + XFER_SW_DMA_2 = 0x12, + XFER_SW_DMA_1 = 0x11, + XFER_SW_DMA_0 = 0x10, + XFER_PIO_6 = 0x0E, /* CFA only */ + XFER_PIO_5 = 0x0D, /* CFA only */ + XFER_PIO_4 = 0x0C, + XFER_PIO_3 = 0x0B, + XFER_PIO_2 = 0x0A, + XFER_PIO_1 = 0x09, + XFER_PIO_0 = 0x08, + XFER_PIO_SLOW = 0x00, + + SETFEATURES_WC_ON = 0x02, /* Enable write cache */ + SETFEATURES_WC_OFF = 0x82, /* Disable write cache */ + + SETFEATURES_SPINUP = 0x07, /* Spin-up drive */ + + SETFEATURES_SATA_ENABLE = 0x10, /* Enable use of SATA feature */ + SETFEATURES_SATA_DISABLE = 0x90, /* Disable use of SATA feature */ + + /* SETFEATURE Sector counts for SATA features */ + SATA_AN = 0x05, /* Asynchronous Notification */ + SATA_DIPM = 0x03, /* Device Initiated Power Management */ + + /* feature values for SET_MAX */ + ATA_SET_MAX_ADDR = 0x00, + ATA_SET_MAX_PASSWD = 0x01, + ATA_SET_MAX_LOCK = 0x02, + ATA_SET_MAX_UNLOCK = 0x03, + ATA_SET_MAX_FREEZE_LOCK = 0x04, + + /* feature values for DEVICE CONFIGURATION OVERLAY */ + ATA_DCO_RESTORE = 0xC0, + ATA_DCO_FREEZE_LOCK = 0xC1, + ATA_DCO_IDENTIFY = 0xC2, + ATA_DCO_SET = 0xC3, + + /* ATAPI stuff */ + ATAPI_PKT_DMA = (1 << 0), + ATAPI_DMADIR = (1 << 2), /* ATAPI data dir: + 0=to device, 1=to host */ + ATAPI_CDB_LEN = 16, + + /* PMP stuff */ + SATA_PMP_MAX_PORTS = 15, + SATA_PMP_CTRL_PORT = 15, + + SATA_PMP_GSCR_DWORDS = 128, + SATA_PMP_GSCR_PROD_ID = 0, + SATA_PMP_GSCR_REV = 1, + SATA_PMP_GSCR_PORT_INFO = 2, + SATA_PMP_GSCR_ERROR = 32, + SATA_PMP_GSCR_ERROR_EN = 33, + SATA_PMP_GSCR_FEAT = 64, + SATA_PMP_GSCR_FEAT_EN = 96, + + SATA_PMP_PSCR_STATUS = 0, + SATA_PMP_PSCR_ERROR = 1, + SATA_PMP_PSCR_CONTROL = 2, + + SATA_PMP_FEAT_BIST = (1 << 0), + SATA_PMP_FEAT_PMREQ = (1 << 1), + SATA_PMP_FEAT_DYNSSC = (1 << 2), + SATA_PMP_FEAT_NOTIFY = (1 << 3), + + /* cable types */ + ATA_CBL_NONE = 0, + ATA_CBL_PATA40 = 1, + ATA_CBL_PATA80 = 2, + ATA_CBL_PATA40_SHORT = 3, /* 40 wire cable to high UDMA spec */ + ATA_CBL_PATA_UNK = 4, /* don't know, maybe 80c? */ + ATA_CBL_PATA_IGN = 5, /* don't know, ignore cable handling */ + ATA_CBL_SATA = 6, + + /* SATA Status and Control Registers */ + SCR_STATUS = 0, + SCR_ERROR = 1, + SCR_CONTROL = 2, + SCR_ACTIVE = 3, + SCR_NOTIFICATION = 4, + + /* SError bits */ + SERR_DATA_RECOVERED = (1 << 0), /* recovered data error */ + SERR_COMM_RECOVERED = (1 << 1), /* recovered comm failure */ + SERR_DATA = (1 << 8), /* unrecovered data error */ + SERR_PERSISTENT = (1 << 9), /* persistent data/comm error */ + SERR_PROTOCOL = (1 << 10), /* protocol violation */ + SERR_INTERNAL = (1 << 11), /* host internal error */ + SERR_PHYRDY_CHG = (1 << 16), /* PHY RDY changed */ + SERR_PHY_INT_ERR = (1 << 17), /* PHY internal error */ + SERR_COMM_WAKE = (1 << 18), /* Comm wake */ + SERR_10B_8B_ERR = (1 << 19), /* 10b to 8b decode error */ + SERR_DISPARITY = (1 << 20), /* Disparity */ + SERR_CRC = (1 << 21), /* CRC error */ + SERR_HANDSHAKE = (1 << 22), /* Handshake error */ + SERR_LINK_SEQ_ERR = (1 << 23), /* Link sequence error */ + SERR_TRANS_ST_ERROR = (1 << 24), /* Transport state trans. error */ + SERR_UNRECOG_FIS = (1 << 25), /* Unrecognized FIS */ + SERR_DEV_XCHG = (1 << 26), /* device exchanged */ + + /* struct ata_taskfile flags */ + ATA_TFLAG_LBA48 = (1 << 0), /* enable 48-bit LBA and "HOB" */ + ATA_TFLAG_ISADDR = (1 << 1), /* enable r/w to nsect/lba regs */ + ATA_TFLAG_DEVICE = (1 << 2), /* enable r/w to device reg */ + ATA_TFLAG_WRITE = (1 << 3), /* data dir: host->dev==1 (write) */ + ATA_TFLAG_LBA = (1 << 4), /* enable LBA */ + ATA_TFLAG_FUA = (1 << 5), /* enable FUA */ + ATA_TFLAG_POLLING = (1 << 6), /* set nIEN to 1 and use polling */ + + /* protocol flags */ + ATA_PROT_FLAG_PIO = (1 << 0), /* is PIO */ + ATA_PROT_FLAG_DMA = (1 << 1), /* is DMA */ + ATA_PROT_FLAG_DATA = ATA_PROT_FLAG_PIO | ATA_PROT_FLAG_DMA, + ATA_PROT_FLAG_NCQ = (1 << 2), /* is NCQ */ + ATA_PROT_FLAG_ATAPI = (1 << 3), /* is ATAPI */ +}; + +enum ata_tf_protocols { + /* ATA taskfile protocols */ + ATA_PROT_UNKNOWN, /* unknown/invalid */ + ATA_PROT_NODATA, /* no data */ + ATA_PROT_PIO, /* PIO data xfer */ + ATA_PROT_DMA, /* DMA */ + ATA_PROT_NCQ, /* NCQ */ + ATAPI_PROT_NODATA, /* packet command, no data */ + ATAPI_PROT_PIO, /* packet command, PIO data xfer*/ + ATAPI_PROT_DMA, /* packet command with special DMA sauce */ +}; + +enum ata_ioctls { + ATA_IOC_GET_IO32 = 0x309, + ATA_IOC_SET_IO32 = 0x324, +}; + +enum ata_dev_typed { + ATA_DEV_ATA, /* ATA device */ + ATA_DEV_ATAPI, /* ATAPI device */ + ATA_DEV_PMP, /* Port Multiplier Port */ + ATA_DEV_UNKNOWN, /* unknown */ +}; + +struct ata_taskfile { + unsigned long flags; /* ATA_TFLAG_xxx */ + u8 protocol; /* ATA_PROT_xxx */ + + u8 ctl; /* control reg */ + + u8 hob_feature; /* additional data */ + u8 hob_nsect; /* to support LBA48 */ + u8 hob_lbal; + u8 hob_lbam; + u8 hob_lbah; + + u8 feature; + u8 nsect; + u8 lbal; + u8 lbam; + u8 lbah; + + u8 device; + + u8 command; /* IO operation */ +}; + +/* + * protocol tests + */ +static inline unsigned int ata_prot_flags(u8 prot) +{ + switch (prot) { + case ATA_PROT_NODATA: + return 0; + case ATA_PROT_PIO: + return ATA_PROT_FLAG_PIO; + case ATA_PROT_DMA: + return ATA_PROT_FLAG_DMA; + case ATA_PROT_NCQ: + return ATA_PROT_FLAG_DMA | ATA_PROT_FLAG_NCQ; + case ATAPI_PROT_NODATA: + return ATA_PROT_FLAG_ATAPI; + case ATAPI_PROT_PIO: + return ATA_PROT_FLAG_ATAPI | ATA_PROT_FLAG_PIO; + case ATAPI_PROT_DMA: + return ATA_PROT_FLAG_ATAPI | ATA_PROT_FLAG_DMA; + } + return 0; +} + +static inline int ata_is_atapi(u8 prot) +{ + return ata_prot_flags(prot) & ATA_PROT_FLAG_ATAPI; +} + +static inline int ata_is_nodata(u8 prot) +{ + return !(ata_prot_flags(prot) & ATA_PROT_FLAG_DATA); +} + +static inline int ata_is_pio(u8 prot) +{ + return ata_prot_flags(prot) & ATA_PROT_FLAG_PIO; +} + +static inline int ata_is_dma(u8 prot) +{ + return ata_prot_flags(prot) & ATA_PROT_FLAG_DMA; +} + +static inline int ata_is_ncq(u8 prot) +{ + return ata_prot_flags(prot) & ATA_PROT_FLAG_NCQ; +} + +static inline int ata_is_data(u8 prot) +{ + return ata_prot_flags(prot) & ATA_PROT_FLAG_DATA; +} + +/* + * id tests + */ +#define ata_id_is_ata(id) (((id)[0] & (1 << 15)) == 0) +#define ata_id_has_lba(id) ((id)[49] & (1 << 9)) +#define ata_id_has_dma(id) ((id)[49] & (1 << 8)) +#define ata_id_has_ncq(id) ((id)[76] & (1 << 8)) +#define ata_id_queue_depth(id) (((id)[75] & 0x1f) + 1) +#define ata_id_removeable(id) ((id)[0] & (1 << 7)) +#define ata_id_iordy_disable(id) ((id)[49] & (1 << 10)) +#define ata_id_has_iordy(id) ((id)[49] & (1 << 11)) + +#define ata_id_u32(id,n) \ + (((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)])) +#define ata_id_u64(id,n) \ + ( ((u64) (id)[(n) + 3] << 48) | \ + ((u64) (id)[(n) + 2] << 32) | \ + ((u64) (id)[(n) + 1] << 16) | \ + ((u64) (id)[(n) + 0]) ) + +#define ata_id_cdb_intr(id) (((id)[0] & 0x60) == 0x20) + +static inline int ata_id_has_fua(const u16 *id) +{ + if ((id[84] & 0xC000) != 0x4000) + return 0; + return id[84] & (1 << 6); +} + +static inline int ata_id_has_flush(const u16 *id) +{ + if ((id[83] & 0xC000) != 0x4000) + return 0; + return id[83] & (1 << 12); +} + +static inline int ata_id_has_flush_ext(const u16 *id) +{ + if ((id[83] & 0xC000) != 0x4000) + return 0; + return id[83] & (1 << 13); +} + +static inline int ata_id_has_lba48(const u16 *id) +{ + if ((id[83] & 0xC000) != 0x4000) + return 0; + if (!ata_id_u64(id, 100)) + return 0; + return id[83] & (1 << 10); +} + +static inline int ata_id_hpa_enabled(const u16 *id) +{ + /* Yes children, word 83 valid bits cover word 82 data */ + if ((id[83] & 0xC000) != 0x4000) + return 0; + /* And 87 covers 85-87 */ + if ((id[87] & 0xC000) != 0x4000) + return 0; + /* Check command sets enabled as well as supported */ + if ((id[85] & ( 1 << 10)) == 0) + return 0; + return id[82] & (1 << 10); +} + +static inline int ata_id_has_wcache(const u16 *id) +{ + /* Yes children, word 83 valid bits cover word 82 data */ + if ((id[83] & 0xC000) != 0x4000) + return 0; + return id[82] & (1 << 5); +} + +static inline int ata_id_has_pm(const u16 *id) +{ + if ((id[83] & 0xC000) != 0x4000) + return 0; + return id[82] & (1 << 3); +} + +static inline int ata_id_rahead_enabled(const u16 *id) +{ + if ((id[87] & 0xC000) != 0x4000) + return 0; + return id[85] & (1 << 6); +} + +static inline int ata_id_wcache_enabled(const u16 *id) +{ + if ((id[87] & 0xC000) != 0x4000) + return 0; + return id[85] & (1 << 5); +} + +static inline unsigned int ata_id_major_version(const u16 *id) +{ + unsigned int mver; + + if (id[ATA_ID_MAJOR_VER] == 0xFFFF) + return 0; + + for (mver = 14; mver >= 1; mver--) + if (id[ATA_ID_MAJOR_VER] & (1 << mver)) + break; + return mver; +} + +static inline int ata_id_is_sata(const u16 *id) +{ + return ata_id_major_version(id) >= 5 && id[93] == 0; +} + +static inline int ata_id_has_tpm(const u16 *id) +{ + /* The TPM bits are only valid on ATA8 */ + if (ata_id_major_version(id) < 8) + return 0; + if ((id[48] & 0xC000) != 0x4000) + return 0; + return id[48] & (1 << 0); +} + +static inline int ata_id_has_dword_io(const u16 *id) +{ + /* ATA 8 reuses this flag for "trusted" computing */ + if (ata_id_major_version(id) > 7) + return 0; + if (id[48] & (1 << 0)) + return 1; + return 0; +} + +static inline int ata_id_current_chs_valid(const u16 *id) +{ + /* For ATA-1 devices, if the INITIALIZE DEVICE PARAMETERS command + has not been issued to the device then the values of + id[54] to id[56] are vendor specific. */ + return (id[53] & 0x01) && /* Current translation valid */ + id[54] && /* cylinders in current translation */ + id[55] && /* heads in current translation */ + id[55] <= 16 && + id[56]; /* sectors in current translation */ +} + +static inline int ata_id_is_cfa(const u16 *id) +{ + u16 v = id[0]; + if (v == 0x848A) /* Standard CF */ + return 1; + /* Could be CF hiding as standard ATA */ + if (ata_id_major_version(id) >= 3 && id[82] != 0xFFFF && + (id[82] & ( 1 << 2))) + return 1; + return 0; +} + +static inline int ata_drive_40wire(const u16 *dev_id) +{ + if (ata_id_is_sata(dev_id)) + return 0; /* SATA */ + if ((dev_id[93] & 0xE000) == 0x6000) + return 0; /* 80 wire */ + return 1; +} + +static inline int ata_drive_40wire_relaxed(const u16 *dev_id) +{ + if ((dev_id[93] & 0x2000) == 0x2000) + return 0; /* 80 wire */ + return 1; +} + +static inline int atapi_cdb_len(const u16 *dev_id) +{ + u16 tmp = dev_id[0] & 0x3; + switch (tmp) { + case 0: return 12; + case 1: return 16; + default: return -1; + } +} + +static inline int atapi_command_packet_set(const u16 *dev_id) +{ + return (dev_id[0] >> 8) & 0x1f; +} + +static inline int atapi_id_dmadir(const u16 *dev_id) +{ + return ata_id_major_version(dev_id) >= 7 && (dev_id[62] & 0x8000); +} + +static inline int is_multi_taskfile(struct ata_taskfile *tf) +{ + return (tf->command == ATA_CMD_READ_MULTI) || + (tf->command == ATA_CMD_WRITE_MULTI) || + (tf->command == ATA_CMD_READ_MULTI_EXT) || + (tf->command == ATA_CMD_WRITE_MULTI_EXT) || + (tf->command == ATA_CMD_WRITE_MULTI_FUA_EXT); +} + +static inline int ata_ok(u8 status) +{ + return ((status & (ATA_BUSY | ATA_DRDY | ATA_DF | ATA_DRQ | ATA_ERR)) + == ATA_DRDY); +} + +static inline int lba_28_ok(u64 block, u32 n_block) +{ + /* check the ending block number */ + return ((block + n_block - 1) < ((u64)1 << 28)) && (n_block <= 256); +} + +static inline int lba_48_ok(u64 block, u32 n_block) +{ + /* check the ending block number */ + return ((block + n_block - 1) < ((u64)1 << 48)) && (n_block <= 65536); +} + +#define sata_pmp_gscr_vendor(gscr) ((gscr)[SATA_PMP_GSCR_PROD_ID] & 0xffff) +#define sata_pmp_gscr_devid(gscr) ((gscr)[SATA_PMP_GSCR_PROD_ID] >> 16) +#define sata_pmp_gscr_rev(gscr) (((gscr)[SATA_PMP_GSCR_REV] >> 8) & 0xff) +#define sata_pmp_gscr_ports(gscr) ((gscr)[SATA_PMP_GSCR_PORT_INFO] & 0xf) + +u64 ata_id_n_sectors(u16 *id); +u32 ata_dev_classify(u32 sig); +void ata_id_c_string(const u16 *id, unsigned char *s, + unsigned int ofs, unsigned int len); +void ata_dump_id(u16 *id); +void ata_swap_buf_le16(u16 *buf, unsigned int buf_words); + +#endif /* __LIBATA_H__ */ diff --git a/roms/u-boot/include/libtizen.h b/roms/u-boot/include/libtizen.h new file mode 100644 index 000000000..655d4cb28 --- /dev/null +++ b/roms/u-boot/include/libtizen.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 Samsung Electronics + * Donghwa Lee + */ + +#ifndef _LIBTIZEN_H_ +#define _LIBTIZEN_H_ + +#define HD_RESOLUTION 0 + +#ifdef CONFIG_LCD +void get_tizen_logo_info(vidinfo_t *vid); +#endif + +#endif /* _LIBTIZEN_H_ */ diff --git a/roms/u-boot/include/linker_lists.h b/roms/u-boot/include/linker_lists.h new file mode 100644 index 000000000..0575164ce --- /dev/null +++ b/roms/u-boot/include/linker_lists.h @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/linker_lists.h + * + * Implementation of linker-generated arrays + * + * Copyright (C) 2012 Marek Vasut + */ + +#ifndef __LINKER_LISTS_H__ +#define __LINKER_LISTS_H__ + +#include + +/* + * There is no use in including this from ASM files. + * So just don't define anything when included from ASM. + */ + +#if !defined(__ASSEMBLY__) + +/** + * llsym() - Access a linker-generated array entry + * @_type: Data type of the entry + * @_name: Name of the entry + * @_list: name of the list. Should contain only characters allowed + * in a C variable name! + */ +#define llsym(_type, _name, _list) \ + ((_type *)&_u_boot_list_2_##_list##_2_##_name) + +/** + * ll_entry_declare() - Declare linker-generated array entry + * @_type: Data type of the entry + * @_name: Name of the entry + * @_list: name of the list. Should contain only characters allowed + * in a C variable name! + * + * This macro declares a variable that is placed into a linker-generated + * array. This is a basic building block for more advanced use of linker- + * generated arrays. The user is expected to build their own macro wrapper + * around this one. + * + * A variable declared using this macro must be compile-time initialized. + * + * Special precaution must be made when using this macro: + * + * 1) The _type must not contain the "static" keyword, otherwise the + * entry is generated and can be iterated but is listed in the map + * file and cannot be retrieved by name. + * + * 2) In case a section is declared that contains some array elements AND + * a subsection of this section is declared and contains some elements, + * it is imperative that the elements are of the same type. + * + * 3) In case an outer section is declared that contains some array elements + * AND an inner subsection of this section is declared and contains some + * elements, then when traversing the outer section, even the elements of + * the inner sections are present in the array. + * + * Example: + * + * :: + * + * ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub) = { + * .x = 3, + * .y = 4, + * }; + */ +#define ll_entry_declare(_type, _name, _list) \ + _type _u_boot_list_2_##_list##_2_##_name __aligned(4) \ + __attribute__((unused)) \ + __section(".u_boot_list_2_"#_list"_2_"#_name) + +/** + * ll_entry_declare_list() - Declare a list of link-generated array entries + * @_type: Data type of each entry + * @_name: Name of the entry + * @_list: name of the list. Should contain only characters allowed + * in a C variable name! + * + * This is like ll_entry_declare() but creates multiple entries. It should + * be assigned to an array. + * + * :: + * + * ll_entry_declare_list(struct my_sub_cmd, my_sub_cmd, cmd_sub) = { + * { .x = 3, .y = 4 }, + * { .x = 8, .y = 2 }, + * { .x = 1, .y = 7 } + * }; + */ +#define ll_entry_declare_list(_type, _name, _list) \ + _type _u_boot_list_2_##_list##_2_##_name[] __aligned(4) \ + __attribute__((unused)) \ + __section(".u_boot_list_2_"#_list"_2_"#_name) + +/* + * We need a 0-byte-size type for iterator symbols, and the compiler + * does not allow defining objects of C type 'void'. Using an empty + * struct is allowed by the compiler, but causes gcc versions 4.4 and + * below to complain about aliasing. Therefore we use the next best + * thing: zero-sized arrays, which are both 0-byte-size and exempt from + * aliasing warnings. + */ + +/** + * ll_entry_start() - Point to first entry of linker-generated array + * @_type: Data type of the entry + * @_list: Name of the list in which this entry is placed + * + * This function returns ``(_type *)`` pointer to the very first entry of a + * linker-generated array placed into subsection of .u_boot_list section + * specified by _list argument. + * + * Since this macro defines an array start symbol, its leftmost index + * must be 2 and its rightmost index must be 1. + * + * Example: + * + * :: + * + * struct my_sub_cmd *msc = ll_entry_start(struct my_sub_cmd, cmd_sub); + */ +#define ll_entry_start(_type, _list) \ +({ \ + static char start[0] __aligned(CONFIG_LINKER_LIST_ALIGN) \ + __attribute__((unused)) \ + __section(".u_boot_list_2_"#_list"_1"); \ + (_type *)&start; \ +}) + +/** + * ll_entry_end() - Point after last entry of linker-generated array + * @_type: Data type of the entry + * @_list: Name of the list in which this entry is placed + * (with underscores instead of dots) + * + * This function returns ``(_type *)`` pointer after the very last entry of + * a linker-generated array placed into subsection of .u_boot_list + * section specified by _list argument. + * + * Since this macro defines an array end symbol, its leftmost index + * must be 2 and its rightmost index must be 3. + * + * Example: + * + * :: + * + * struct my_sub_cmd *msc = ll_entry_end(struct my_sub_cmd, cmd_sub); + */ +#define ll_entry_end(_type, _list) \ +({ \ + static char end[0] __aligned(4) __attribute__((unused)) \ + __section(".u_boot_list_2_"#_list"_3"); \ + (_type *)&end; \ +}) +/** + * ll_entry_count() - Return the number of elements in linker-generated array + * @_type: Data type of the entry + * @_list: Name of the list of which the number of elements is computed + * + * This function returns the number of elements of a linker-generated array + * placed into subsection of .u_boot_list section specified by _list + * argument. The result is of an unsigned int type. + * + * Example: + * + * :: + * + * int i; + * const unsigned int count = ll_entry_count(struct my_sub_cmd, cmd_sub); + * struct my_sub_cmd *msc = ll_entry_start(struct my_sub_cmd, cmd_sub); + * for (i = 0; i < count; i++, msc++) + * printf("Entry %i, x=%i y=%i\n", i, msc->x, msc->y); + */ +#define ll_entry_count(_type, _list) \ + ({ \ + _type *start = ll_entry_start(_type, _list); \ + _type *end = ll_entry_end(_type, _list); \ + unsigned int _ll_result = end - start; \ + _ll_result; \ + }) + +/** + * ll_entry_get() - Retrieve entry from linker-generated array by name + * @_type: Data type of the entry + * @_name: Name of the entry + * @_list: Name of the list in which this entry is placed + * + * This function returns a pointer to a particular entry in linker-generated + * array identified by the subsection of u_boot_list where the entry resides + * and it's name. + * + * Example: + * + * :: + * + * ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub) = { + * .x = 3, + * .y = 4, + * }; + * ... + * struct my_sub_cmd *c = ll_entry_get(struct my_sub_cmd, my_sub_cmd, cmd_sub); + */ +#define ll_entry_get(_type, _name, _list) \ + ({ \ + extern _type _u_boot_list_2_##_list##_2_##_name; \ + _type *_ll_result = \ + &_u_boot_list_2_##_list##_2_##_name; \ + _ll_result; \ + }) + +/** + * ll_entry_ref() - Get a reference to a linker-generated array entry + * + * Once an extern ll_entry_declare() has been used to declare the reference, + * this macro allows the entry to be accessed. + * + * This is like ll_entry_get(), but without the extra code, so it is suitable + * for putting into data structures. + * + * @_type: C type of the list entry, e.g. 'struct foo' + * @_name: name of the entry + * @_list: name of the list + */ +#define ll_entry_ref(_type, _name, _list) \ + ((_type *)&_u_boot_list_2_##_list##_2_##_name) + +/** + * ll_start() - Point to first entry of first linker-generated array + * @_type: Data type of the entry + * + * This function returns ``(_type *)`` pointer to the very first entry of + * the very first linker-generated array. + * + * Since this macro defines the start of the linker-generated arrays, + * its leftmost index must be 1. + * + * Example: + * + * :: + * + * struct my_sub_cmd *msc = ll_start(struct my_sub_cmd); + */ +#define ll_start(_type) \ +({ \ + static char start[0] __aligned(4) __attribute__((unused)) \ + __section(".u_boot_list_1"); \ + (_type *)&start; \ +}) + +/** + * ll_end() - Point after last entry of last linker-generated array + * @_type: Data type of the entry + * + * This function returns ``(_type *)`` pointer after the very last entry of + * the very last linker-generated array. + * + * Since this macro defines the end of the linker-generated arrays, + * its leftmost index must be 3. + * + * Example: + * + * :: + * + * struct my_sub_cmd *msc = ll_end(struct my_sub_cmd); + */ +#define ll_end(_type) \ +({ \ + static char end[0] __aligned(4) __attribute__((unused)) \ + __section(".u_boot_list_3"); \ + (_type *)&end; \ +}) + +#endif /* __ASSEMBLY__ */ + +#endif /* __LINKER_LISTS_H__ */ diff --git a/roms/u-boot/include/linux/apm_bios.h b/roms/u-boot/include/linux/apm_bios.h new file mode 100644 index 000000000..3dabc3f77 --- /dev/null +++ b/roms/u-boot/include/linux/apm_bios.h @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _LINUX_APM_H +#define _LINUX_APM_H + +/* + * Include file for the interface to an APM BIOS + * Copyright 1994-2001 Stephen Rothwell (sfr@canb.auug.org.au) + */ + +#include + +typedef unsigned short apm_event_t; +typedef unsigned short apm_eventinfo_t; + +struct apm_bios_info { + __u16 version; + __u16 cseg; + __u32 offset; + __u16 cseg_16; + __u16 dseg; + __u16 flags; + __u16 cseg_len; + __u16 cseg_16_len; + __u16 dseg_len; +}; + +#ifdef __KERNEL__ + +#define APM_CS (GDT_ENTRY_APMBIOS_BASE * 8) +#define APM_CS_16 (APM_CS + 8) +#define APM_DS (APM_CS_16 + 8) + +/* Results of APM Installation Check */ +#define APM_16_BIT_SUPPORT 0x0001 +#define APM_32_BIT_SUPPORT 0x0002 +#define APM_IDLE_SLOWS_CLOCK 0x0004 +#define APM_BIOS_DISABLED 0x0008 +#define APM_BIOS_DISENGAGED 0x0010 + +/* + * Data for APM that is persistent across module unload/load + */ +struct apm_info { + struct apm_bios_info bios; + unsigned short connection_version; + int get_power_status_broken; + int get_power_status_swabinminutes; + int allow_ints; + int forbid_idle; + int realmode_power_off; + int disabled; +}; + +/* + * The APM function codes + */ +#define APM_FUNC_INST_CHECK 0x5300 +#define APM_FUNC_REAL_CONN 0x5301 +#define APM_FUNC_16BIT_CONN 0x5302 +#define APM_FUNC_32BIT_CONN 0x5303 +#define APM_FUNC_DISCONN 0x5304 +#define APM_FUNC_IDLE 0x5305 +#define APM_FUNC_BUSY 0x5306 +#define APM_FUNC_SET_STATE 0x5307 +#define APM_FUNC_ENABLE_PM 0x5308 +#define APM_FUNC_RESTORE_BIOS 0x5309 +#define APM_FUNC_GET_STATUS 0x530a +#define APM_FUNC_GET_EVENT 0x530b +#define APM_FUNC_GET_STATE 0x530c +#define APM_FUNC_ENABLE_DEV_PM 0x530d +#define APM_FUNC_VERSION 0x530e +#define APM_FUNC_ENGAGE_PM 0x530f +#define APM_FUNC_GET_CAP 0x5310 +#define APM_FUNC_RESUME_TIMER 0x5311 +#define APM_FUNC_RESUME_ON_RING 0x5312 +#define APM_FUNC_TIMER 0x5313 + +/* + * Function code for APM_FUNC_RESUME_TIMER + */ +#define APM_FUNC_DISABLE_TIMER 0 +#define APM_FUNC_GET_TIMER 1 +#define APM_FUNC_SET_TIMER 2 + +/* + * Function code for APM_FUNC_RESUME_ON_RING + */ +#define APM_FUNC_DISABLE_RING 0 +#define APM_FUNC_ENABLE_RING 1 +#define APM_FUNC_GET_RING 2 + +/* + * Function code for APM_FUNC_TIMER_STATUS + */ +#define APM_FUNC_TIMER_DISABLE 0 +#define APM_FUNC_TIMER_ENABLE 1 +#define APM_FUNC_TIMER_GET 2 + +/* + * in arch/i386/kernel/setup.c + */ +extern struct apm_info apm_info; + +#endif /* __KERNEL__ */ + +/* + * Power states + */ +#define APM_STATE_READY 0x0000 +#define APM_STATE_STANDBY 0x0001 +#define APM_STATE_SUSPEND 0x0002 +#define APM_STATE_OFF 0x0003 +#define APM_STATE_BUSY 0x0004 +#define APM_STATE_REJECT 0x0005 +#define APM_STATE_OEM_SYS 0x0020 +#define APM_STATE_OEM_DEV 0x0040 + +#define APM_STATE_DISABLE 0x0000 +#define APM_STATE_ENABLE 0x0001 + +#define APM_STATE_DISENGAGE 0x0000 +#define APM_STATE_ENGAGE 0x0001 + +/* + * Events (results of Get PM Event) + */ +#define APM_SYS_STANDBY 0x0001 +#define APM_SYS_SUSPEND 0x0002 +#define APM_NORMAL_RESUME 0x0003 +#define APM_CRITICAL_RESUME 0x0004 +#define APM_LOW_BATTERY 0x0005 +#define APM_POWER_STATUS_CHANGE 0x0006 +#define APM_UPDATE_TIME 0x0007 +#define APM_CRITICAL_SUSPEND 0x0008 +#define APM_USER_STANDBY 0x0009 +#define APM_USER_SUSPEND 0x000a +#define APM_STANDBY_RESUME 0x000b +#define APM_CAPABILITY_CHANGE 0x000c + +/* + * Error codes + */ +#define APM_SUCCESS 0x00 +#define APM_DISABLED 0x01 +#define APM_CONNECTED 0x02 +#define APM_NOT_CONNECTED 0x03 +#define APM_16_CONNECTED 0x05 +#define APM_16_UNSUPPORTED 0x06 +#define APM_32_CONNECTED 0x07 +#define APM_32_UNSUPPORTED 0x08 +#define APM_BAD_DEVICE 0x09 +#define APM_BAD_PARAM 0x0a +#define APM_NOT_ENGAGED 0x0b +#define APM_BAD_FUNCTION 0x0c +#define APM_RESUME_DISABLED 0x0d +#define APM_NO_ERROR 0x53 +#define APM_BAD_STATE 0x60 +#define APM_NO_EVENTS 0x80 +#define APM_NOT_PRESENT 0x86 + +/* + * APM Device IDs + */ +#define APM_DEVICE_BIOS 0x0000 +#define APM_DEVICE_ALL 0x0001 +#define APM_DEVICE_DISPLAY 0x0100 +#define APM_DEVICE_STORAGE 0x0200 +#define APM_DEVICE_PARALLEL 0x0300 +#define APM_DEVICE_SERIAL 0x0400 +#define APM_DEVICE_NETWORK 0x0500 +#define APM_DEVICE_PCMCIA 0x0600 +#define APM_DEVICE_BATTERY 0x8000 +#define APM_DEVICE_OEM 0xe000 +#define APM_DEVICE_OLD_ALL 0xffff +#define APM_DEVICE_CLASS 0x00ff +#define APM_DEVICE_MASK 0xff00 + +#ifdef __KERNEL__ +/* + * This is the "All Devices" ID communicated to the BIOS + */ +#define APM_DEVICE_BALL ((apm_info.connection_version > 0x0100) ? \ + APM_DEVICE_ALL : APM_DEVICE_OLD_ALL) +#endif + +/* + * Battery status + */ +#define APM_MAX_BATTERIES 2 + +/* + * APM defined capability bit flags + */ +#define APM_CAP_GLOBAL_STANDBY 0x0001 +#define APM_CAP_GLOBAL_SUSPEND 0x0002 +#define APM_CAP_RESUME_STANDBY_TIMER 0x0004 /* Timer resume from standby */ +#define APM_CAP_RESUME_SUSPEND_TIMER 0x0008 /* Timer resume from suspend */ +#define APM_CAP_RESUME_STANDBY_RING 0x0010 /* Resume on Ring fr standby */ +#define APM_CAP_RESUME_SUSPEND_RING 0x0020 /* Resume on Ring fr suspend */ +#define APM_CAP_RESUME_STANDBY_PCMCIA 0x0040 /* Resume on PCMCIA Ring */ +#define APM_CAP_RESUME_SUSPEND_PCMCIA 0x0080 /* Resume on PCMCIA Ring */ + +/* + * ioctl operations + */ +#include + +#define APM_IOC_STANDBY _IO('A', 1) +#define APM_IOC_SUSPEND _IO('A', 2) + +#endif /* LINUX_APM_H */ diff --git a/roms/u-boot/include/linux/arm-smccc.h b/roms/u-boot/include/linux/arm-smccc.h new file mode 100644 index 000000000..7f2be2339 --- /dev/null +++ b/roms/u-boot/include/linux/arm-smccc.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2015, Linaro Limited + */ +#ifndef __LINUX_ARM_SMCCC_H +#define __LINUX_ARM_SMCCC_H + +/* + * This file provides common defines for ARM SMC Calling Convention as + * specified in + * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html + */ + +#define ARM_SMCCC_STD_CALL 0UL +#define ARM_SMCCC_FAST_CALL 1UL +#define ARM_SMCCC_TYPE_SHIFT 31 + +#define ARM_SMCCC_SMC_32 0 +#define ARM_SMCCC_SMC_64 1 +#define ARM_SMCCC_CALL_CONV_SHIFT 30 + +#define ARM_SMCCC_OWNER_MASK 0x3F +#define ARM_SMCCC_OWNER_SHIFT 24 + +#define ARM_SMCCC_FUNC_MASK 0xFFFF + +#define ARM_SMCCC_IS_FAST_CALL(smc_val) \ + ((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT)) +#define ARM_SMCCC_IS_64(smc_val) \ + ((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT)) +#define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val) & ARM_SMCCC_FUNC_MASK) +#define ARM_SMCCC_OWNER_NUM(smc_val) \ + (((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK) + +#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \ + (((type) << ARM_SMCCC_TYPE_SHIFT) | \ + ((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \ + (((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \ + ((func_num) & ARM_SMCCC_FUNC_MASK)) + +#define ARM_SMCCC_OWNER_ARCH 0 +#define ARM_SMCCC_OWNER_CPU 1 +#define ARM_SMCCC_OWNER_SIP 2 +#define ARM_SMCCC_OWNER_OEM 3 +#define ARM_SMCCC_OWNER_STANDARD 4 +#define ARM_SMCCC_OWNER_TRUSTED_APP 48 +#define ARM_SMCCC_OWNER_TRUSTED_APP_END 49 +#define ARM_SMCCC_OWNER_TRUSTED_OS 50 +#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 + +#define ARM_SMCCC_QUIRK_NONE 0 +#define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ + +#ifndef __ASSEMBLY__ + +#include +#include +/** + * struct arm_smccc_res - Result from SMC/HVC call + * @a0-a3 result values from registers 0 to 3 + */ +struct arm_smccc_res { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; + +/** + * struct arm_smccc_quirk - Contains quirk information + * @id: quirk identification + * @state: quirk specific information + * @a6: Qualcomm quirk entry for returning post-smc call contents of a6 + */ +struct arm_smccc_quirk { + int id; + union { + unsigned long a6; + } state; +}; + +/** + * __arm_smccc_smc() - make SMC calls + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required. + * + * This function is used to make SMC calls following SMC Calling Convention. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction. An optional + * quirk structure provides vendor specific behavior. + */ +asmlinkage void __arm_smccc_smc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, unsigned long a4, + unsigned long a5, unsigned long a6, unsigned long a7, + struct arm_smccc_res *res, struct arm_smccc_quirk *quirk); + +/** + * __arm_smccc_hvc() - make HVC calls + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required. + * + * This function is used to make HVC calls following SMC Calling + * Convention. The content of the supplied param are copied to registers 0 + * to 7 prior to the HVC instruction. The return values are updated with + * the content from register 0 to 3 on return from the HVC instruction. An + * optional quirk structure provides vendor specific behavior. + */ +asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, unsigned long a4, + unsigned long a5, unsigned long a6, unsigned long a7, + struct arm_smccc_res *res, struct arm_smccc_quirk *quirk); + +#define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__, NULL) + +#define arm_smccc_smc_quirk(...) __arm_smccc_smc(__VA_ARGS__) + +#define arm_smccc_hvc(...) __arm_smccc_hvc(__VA_ARGS__, NULL) + +#define arm_smccc_hvc_quirk(...) __arm_smccc_hvc(__VA_ARGS__) + +#endif /*__ASSEMBLY__*/ +#endif /*__LINUX_ARM_SMCCC_H*/ diff --git a/roms/u-boot/include/linux/asn1.h b/roms/u-boot/include/linux/asn1.h new file mode 100644 index 000000000..a4d0bdd10 --- /dev/null +++ b/roms/u-boot/include/linux/asn1.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* ASN.1 BER/DER/CER encoding definitions + * + * Copyright (C) 2012 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + */ + +#ifndef _LINUX_ASN1_H +#define _LINUX_ASN1_H + +/* Class */ +enum asn1_class { + ASN1_UNIV = 0, /* Universal */ + ASN1_APPL = 1, /* Application */ + ASN1_CONT = 2, /* Context */ + ASN1_PRIV = 3 /* Private */ +}; +#define ASN1_CLASS_BITS 0xc0 + + +enum asn1_method { + ASN1_PRIM = 0, /* Primitive */ + ASN1_CONS = 1 /* Constructed */ +}; +#define ASN1_CONS_BIT 0x20 + +/* Tag */ +enum asn1_tag { + ASN1_EOC = 0, /* End Of Contents or N/A */ + ASN1_BOOL = 1, /* Boolean */ + ASN1_INT = 2, /* Integer */ + ASN1_BTS = 3, /* Bit String */ + ASN1_OTS = 4, /* Octet String */ + ASN1_NULL = 5, /* Null */ + ASN1_OID = 6, /* Object Identifier */ + ASN1_ODE = 7, /* Object Description */ + ASN1_EXT = 8, /* External */ + ASN1_REAL = 9, /* Real float */ + ASN1_ENUM = 10, /* Enumerated */ + ASN1_EPDV = 11, /* Embedded PDV */ + ASN1_UTF8STR = 12, /* UTF8 String */ + ASN1_RELOID = 13, /* Relative OID */ + /* 14 - Reserved */ + /* 15 - Reserved */ + ASN1_SEQ = 16, /* Sequence and Sequence of */ + ASN1_SET = 17, /* Set and Set of */ + ASN1_NUMSTR = 18, /* Numerical String */ + ASN1_PRNSTR = 19, /* Printable String */ + ASN1_TEXSTR = 20, /* T61 String / Teletext String */ + ASN1_VIDSTR = 21, /* Videotex String */ + ASN1_IA5STR = 22, /* IA5 String */ + ASN1_UNITIM = 23, /* Universal Time */ + ASN1_GENTIM = 24, /* General Time */ + ASN1_GRASTR = 25, /* Graphic String */ + ASN1_VISSTR = 26, /* Visible String */ + ASN1_GENSTR = 27, /* General String */ + ASN1_UNISTR = 28, /* Universal String */ + ASN1_CHRSTR = 29, /* Character String */ + ASN1_BMPSTR = 30, /* BMP String */ + ASN1_LONG_TAG = 31 /* Long form tag */ +}; + +#define ASN1_INDEFINITE_LENGTH 0x80 + +#endif /* _LINUX_ASN1_H */ diff --git a/roms/u-boot/include/linux/asn1_ber_bytecode.h b/roms/u-boot/include/linux/asn1_ber_bytecode.h new file mode 100644 index 000000000..b38361953 --- /dev/null +++ b/roms/u-boot/include/linux/asn1_ber_bytecode.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* ASN.1 BER/DER/CER parsing state machine internal definitions + * + * Copyright (C) 2012 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + */ + +#ifndef _LINUX_ASN1_BER_BYTECODE_H +#define _LINUX_ASN1_BER_BYTECODE_H + +#ifdef __KERNEL__ +#include +#endif +#include + +typedef int (*asn1_action_t)(void *context, + size_t hdrlen, /* In case of ANY type */ + unsigned char tag, /* In case of ANY type */ + const void *value, size_t vlen); + +struct asn1_decoder { + const unsigned char *machine; + size_t machlen; + const asn1_action_t *actions; +}; + +enum asn1_opcode { + /* The tag-matching ops come first and the odd-numbered slots + * are for OR_SKIP ops. + */ +#define ASN1_OP_MATCH__SKIP 0x01 +#define ASN1_OP_MATCH__ACT 0x02 +#define ASN1_OP_MATCH__JUMP 0x04 +#define ASN1_OP_MATCH__ANY 0x08 +#define ASN1_OP_MATCH__COND 0x10 + + ASN1_OP_MATCH = 0x00, + ASN1_OP_MATCH_OR_SKIP = 0x01, + ASN1_OP_MATCH_ACT = 0x02, + ASN1_OP_MATCH_ACT_OR_SKIP = 0x03, + ASN1_OP_MATCH_JUMP = 0x04, + ASN1_OP_MATCH_JUMP_OR_SKIP = 0x05, + ASN1_OP_MATCH_ANY = 0x08, + ASN1_OP_MATCH_ANY_OR_SKIP = 0x09, + ASN1_OP_MATCH_ANY_ACT = 0x0a, + ASN1_OP_MATCH_ANY_ACT_OR_SKIP = 0x0b, + /* Everything before here matches unconditionally */ + + ASN1_OP_COND_MATCH_OR_SKIP = 0x11, + ASN1_OP_COND_MATCH_ACT_OR_SKIP = 0x13, + ASN1_OP_COND_MATCH_JUMP_OR_SKIP = 0x15, + ASN1_OP_COND_MATCH_ANY = 0x18, + ASN1_OP_COND_MATCH_ANY_OR_SKIP = 0x19, + ASN1_OP_COND_MATCH_ANY_ACT = 0x1a, + ASN1_OP_COND_MATCH_ANY_ACT_OR_SKIP = 0x1b, + + /* Everything before here will want a tag from the data */ +#define ASN1_OP__MATCHES_TAG ASN1_OP_COND_MATCH_ANY_ACT_OR_SKIP + + /* These are here to help fill up space */ + ASN1_OP_COND_FAIL = 0x1c, + ASN1_OP_COMPLETE = 0x1d, + ASN1_OP_ACT = 0x1e, + ASN1_OP_MAYBE_ACT = 0x1f, + + /* The following eight have bit 0 -> SET, 1 -> OF, 2 -> ACT */ + ASN1_OP_END_SEQ = 0x20, + ASN1_OP_END_SET = 0x21, + ASN1_OP_END_SEQ_OF = 0x22, + ASN1_OP_END_SET_OF = 0x23, + ASN1_OP_END_SEQ_ACT = 0x24, + ASN1_OP_END_SET_ACT = 0x25, + ASN1_OP_END_SEQ_OF_ACT = 0x26, + ASN1_OP_END_SET_OF_ACT = 0x27, +#define ASN1_OP_END__SET 0x01 +#define ASN1_OP_END__OF 0x02 +#define ASN1_OP_END__ACT 0x04 + + ASN1_OP_RETURN = 0x28, + + ASN1_OP__NR +}; + +#define _tag(CLASS, CP, TAG) ((ASN1_##CLASS << 6) | (ASN1_##CP << 5) | ASN1_##TAG) +#define _tagn(CLASS, CP, TAG) ((ASN1_##CLASS << 6) | (ASN1_##CP << 5) | TAG) +#define _jump_target(N) (N) +#define _action(N) (N) + +#endif /* _LINUX_ASN1_BER_BYTECODE_H */ diff --git a/roms/u-boot/include/linux/asn1_decoder.h b/roms/u-boot/include/linux/asn1_decoder.h new file mode 100644 index 000000000..83f9c6e1e --- /dev/null +++ b/roms/u-boot/include/linux/asn1_decoder.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* ASN.1 decoder + * + * Copyright (C) 2012 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + */ + +#ifndef _LINUX_ASN1_DECODER_H +#define _LINUX_ASN1_DECODER_H + +#include + +struct asn1_decoder; + +extern int asn1_ber_decoder(const struct asn1_decoder *decoder, + void *context, + const unsigned char *data, + size_t datalen); + +#endif /* _LINUX_ASN1_DECODER_H */ diff --git a/roms/u-boot/include/linux/bch.h b/roms/u-boot/include/linux/bch.h new file mode 100644 index 000000000..1305d2ca1 --- /dev/null +++ b/roms/u-boot/include/linux/bch.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Generic binary BCH encoding/decoding library + * + * Copyright © 2011 Parrot S.A. + * + * Author: Ivan Djelic + * + * Description: + * + * This library provides runtime configurable encoding/decoding of binary + * Bose-Chaudhuri-Hocquenghem (BCH) codes. +*/ +#ifndef _BCH_H +#define _BCH_H + +#include + +/** + * struct bch_control - BCH control structure + * @m: Galois field order + * @n: maximum codeword size in bits (= 2^m-1) + * @t: error correction capability in bits + * @ecc_bits: ecc exact size in bits, i.e. generator polynomial degree (<=m*t) + * @ecc_bytes: ecc max size (m*t bits) in bytes + * @a_pow_tab: Galois field GF(2^m) exponentiation lookup table + * @a_log_tab: Galois field GF(2^m) log lookup table + * @mod8_tab: remainder generator polynomial lookup tables + * @ecc_buf: ecc parity words buffer + * @ecc_buf2: ecc parity words buffer + * @xi_tab: GF(2^m) base for solving degree 2 polynomial roots + * @syn: syndrome buffer + * @cache: log-based polynomial representation buffer + * @elp: error locator polynomial + * @poly_2t: temporary polynomials of degree 2t + */ +struct bch_control { + unsigned int m; + unsigned int n; + unsigned int t; + unsigned int ecc_bits; + unsigned int ecc_bytes; +/* private: */ + uint16_t *a_pow_tab; + uint16_t *a_log_tab; + uint32_t *mod8_tab; + uint32_t *ecc_buf; + uint32_t *ecc_buf2; + unsigned int *xi_tab; + unsigned int *syn; + int *cache; + struct gf_poly *elp; + struct gf_poly *poly_2t[4]; +}; + +struct bch_control *init_bch(int m, int t, unsigned int prim_poly); + +void free_bch(struct bch_control *bch); + +void encode_bch(struct bch_control *bch, const uint8_t *data, + unsigned int len, uint8_t *ecc); + +int decode_bch(struct bch_control *bch, const uint8_t *data, unsigned int len, + const uint8_t *recv_ecc, const uint8_t *calc_ecc, + const unsigned int *syn, unsigned int *errloc); + +#endif /* _BCH_H */ diff --git a/roms/u-boot/include/linux/bitfield.h b/roms/u-boot/include/linux/bitfield.h new file mode 100644 index 000000000..7ad02f8cb --- /dev/null +++ b/roms/u-boot/include/linux/bitfield.h @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2014 Felix Fietkau + * Copyright (C) 2004 - 2009 Ivo van Doorn + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _LINUX_BITFIELD_H +#define _LINUX_BITFIELD_H + +#include +#include + +/* + * Bitfield access macros + * + * FIELD_{GET,PREP} macros take as first parameter shifted mask + * from which they extract the base mask and shift amount. + * Mask must be a compilation time constant. + * + * Example: + * + * #define REG_FIELD_A GENMASK(6, 0) + * #define REG_FIELD_B BIT(7) + * #define REG_FIELD_C GENMASK(15, 8) + * #define REG_FIELD_D GENMASK(31, 16) + * + * Get: + * a = FIELD_GET(REG_FIELD_A, reg); + * b = FIELD_GET(REG_FIELD_B, reg); + * + * Set: + * reg = FIELD_PREP(REG_FIELD_A, 1) | + * FIELD_PREP(REG_FIELD_B, 0) | + * FIELD_PREP(REG_FIELD_C, c) | + * FIELD_PREP(REG_FIELD_D, 0x40); + * + * Modify: + * reg &= ~REG_FIELD_C; + * reg |= FIELD_PREP(REG_FIELD_C, c); + */ + +#define __bf_shf(x) (__builtin_ffsll(x) - 1) + +#define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx) \ + ({ \ + BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \ + _pfx "mask is not constant"); \ + BUILD_BUG_ON_MSG(!(_mask), _pfx "mask is zero"); \ + BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \ + ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \ + _pfx "value too large for the field"); \ + BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull, \ + _pfx "type of reg too small for mask"); \ + __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \ + (1ULL << __bf_shf(_mask))); \ + }) + +/** + * FIELD_FIT() - check if value fits in the field + * @_mask: shifted mask defining the field's length and position + * @_val: value to test against the field + * + * Return: true if @_val can fit inside @_mask, false if @_val is too big. + */ +#define FIELD_FIT(_mask, _val) \ + ({ \ + __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_FIT: "); \ + !((((typeof(_mask))_val) << __bf_shf(_mask)) & ~(_mask)); \ + }) + +/** + * FIELD_PREP() - prepare a bitfield element + * @_mask: shifted mask defining the field's length and position + * @_val: value to put in the field + * + * FIELD_PREP() masks and shifts up the value. The result should + * be combined with other fields of the bitfield using logical OR. + */ +#define FIELD_PREP(_mask, _val) \ + ({ \ + __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ + ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ + }) + +/** + * FIELD_GET() - extract a bitfield element + * @_mask: shifted mask defining the field's length and position + * @_reg: 32bit value of entire bitfield + * + * FIELD_GET() extracts the field specified by @_mask from the + * bitfield passed in as @_reg by masking and shifting it down. + */ +#define FIELD_GET(_mask, _reg) \ + ({ \ + __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \ + (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ + }) + +extern void __compiletime_error("value doesn't fit into mask") +__field_overflow(void); +extern void __compiletime_error("bad bitfield mask") +__bad_mask(void); + +static __always_inline u64 field_multiplier(u64 field) +{ + if ((field | (field - 1)) & ((field | (field - 1)) + 1)) + __bad_mask(); + return field & -field; +} + +static __always_inline u64 field_mask(u64 field) +{ + return field / field_multiplier(field); +} + +#define ____MAKE_OP(type, base, to, from) \ +static __always_inline __##type type##_encode_bits(base v, base field) \ +{ \ + if (__builtin_constant_p(v) && (v & ~field_mask(field))) \ + __field_overflow(); \ + return to((v & field_mask(field)) * field_multiplier(field)); \ +} \ +static __always_inline __##type type##_replace_bits(__##type old, \ + base val, base field) \ +{ \ + return (old & ~to(field)) | type##_encode_bits(val, field); \ +} \ +static __always_inline void type##p_replace_bits(__##type * p, \ + base val, base field) \ +{ \ + *p = (*p & ~to(field)) | type##_encode_bits(val, field); \ +} \ +static __always_inline base type##_get_bits(__##type v, base field) \ +{ \ + return (from(v) & field) / field_multiplier(field); \ +} + +#define __MAKE_OP(size) \ + ____MAKE_OP(le##size, u##size, cpu_to_le##size, le##size##_to_cpu) \ + ____MAKE_OP(be##size, u##size, cpu_to_be##size, be##size##_to_cpu) \ + ____MAKE_OP(u##size, u##size, ,) + +____MAKE_OP(u8, u8, ,) +__MAKE_OP(16) +__MAKE_OP(32) +__MAKE_OP(64) + +#undef __MAKE_OP +#undef ____MAKE_OP + +#endif diff --git a/roms/u-boot/include/linux/bitmap.h b/roms/u-boot/include/linux/bitmap.h new file mode 100644 index 000000000..dae4225be --- /dev/null +++ b/roms/u-boot/include/linux/bitmap.h @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0+ +#ifndef __LINUX_BITMAP_H +#define __LINUX_BITMAP_H + +#include +#include +#include +#include + +#ifdef __LITTLE_ENDIAN +#define BITMAP_MEM_ALIGNMENT 8 +#else +#define BITMAP_MEM_ALIGNMENT (8 * sizeof(unsigned long)) +#endif +#define BITMAP_MEM_MASK (BITMAP_MEM_ALIGNMENT - 1) + +#define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1))) +#define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1))) +#define small_const_nbits(nbits) \ + (__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG) + +static inline void +__bitmap_or(unsigned long *dst, const unsigned long *bitmap1, + const unsigned long *bitmap2, unsigned int bits) +{ + unsigned int k; + unsigned int nr = BITS_TO_LONGS(bits); + + for (k = 0; k < nr; k++) + dst[k] = bitmap1[k] | bitmap2[k]; +} + +static inline int +__bitmap_weight(const unsigned long *bitmap, unsigned int bits) +{ + unsigned int k, lim = bits / BITS_PER_LONG; + int w = 0; + + for (k = 0; k < lim; k++) + w += hweight_long(bitmap[k]); + + if (bits % BITS_PER_LONG) + w += hweight_long(bitmap[k] & BITMAP_LAST_WORD_MASK(bits)); + + return w; +} + +static inline void +__bitmap_set(unsigned long *map, unsigned int start, int len) +{ + unsigned long *p = map + BIT_WORD(start); + const unsigned int size = start + len; + int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG); + unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start); + + while (len - bits_to_set >= 0) { + *p |= mask_to_set; + len -= bits_to_set; + bits_to_set = BITS_PER_LONG; + mask_to_set = ~0UL; + p++; + } + if (len) { + mask_to_set &= BITMAP_LAST_WORD_MASK(size); + *p |= mask_to_set; + } +} + +static inline void +__bitmap_clear(unsigned long *map, unsigned int start, int len) +{ + unsigned long *p = map + BIT_WORD(start); + const unsigned int size = start + len; + int bits_to_clear = BITS_PER_LONG - (start % BITS_PER_LONG); + unsigned long mask_to_clear = BITMAP_FIRST_WORD_MASK(start); + + while (len - bits_to_clear >= 0) { + *p &= ~mask_to_clear; + len -= bits_to_clear; + bits_to_clear = BITS_PER_LONG; + mask_to_clear = ~0UL; + p++; + } + if (len) { + mask_to_clear &= BITMAP_LAST_WORD_MASK(size); + *p &= ~mask_to_clear; + } +} + +static inline void bitmap_zero(unsigned long *dst, int nbits) +{ + if (small_const_nbits(nbits)) { + *dst = 0UL; + } else { + int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long); + + memset(dst, 0, len); + } +} + +static inline unsigned long +find_next_bit(const unsigned long *addr, unsigned long size, + unsigned long offset) +{ + const unsigned long *p = addr + BIT_WORD(offset); + unsigned long result = offset & ~(BITS_PER_LONG - 1); + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset %= BITS_PER_LONG; + if (offset) { + tmp = *(p++); + tmp &= (~0UL << offset); + if (size < BITS_PER_LONG) + goto found_first; + if (tmp) + goto found_middle; + size -= BITS_PER_LONG; + result += BITS_PER_LONG; + } + while (size & ~(BITS_PER_LONG - 1)) { + tmp = *(p++); + if ((tmp)) + goto found_middle; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp &= (~0UL >> (BITS_PER_LONG - size)); + if (tmp == 0UL) /* Are any bits set? */ + return result + size; /* Nope. */ +found_middle: + return result + __ffs(tmp); +} + +/* + * Find the first set bit in a memory region. + */ +static inline unsigned long find_first_bit(const unsigned long *addr, unsigned long size) +{ + unsigned long idx; + + for (idx = 0; idx * BITS_PER_LONG < size; idx++) { + if (addr[idx]) + return min(idx * BITS_PER_LONG + __ffs(addr[idx]), size); + } + + return size; +} + +#define for_each_set_bit(bit, addr, size) \ + for ((bit) = find_first_bit((addr), (size)); \ + (bit) < (size); \ + (bit) = find_next_bit((addr), (size), (bit) + 1)) + +static inline void bitmap_fill(unsigned long *dst, unsigned int nbits) +{ + if (small_const_nbits(nbits)) { + *dst = ~0UL; + } else { + unsigned int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long); + + memset(dst, 0xff, len); + } +} + +static inline void bitmap_or(unsigned long *dst, const unsigned long *src1, + const unsigned long *src2, unsigned int nbits) +{ + if (small_const_nbits(nbits)) + *dst = *src1 | *src2; + else + __bitmap_or(dst, src1, src2, nbits); +} + +static inline int bitmap_weight(const unsigned long *src, unsigned int nbits) +{ + if (small_const_nbits(nbits)) + return hweight_long(*src & BITMAP_LAST_WORD_MASK(nbits)); + return __bitmap_weight(src, nbits); +} + +static inline void bitmap_set(unsigned long *map, unsigned int start, + unsigned int nbits) +{ + if (__builtin_constant_p(nbits) && nbits == 1) + __set_bit(start, map); + else if (__builtin_constant_p(start & BITMAP_MEM_MASK) && + IS_ALIGNED(start, BITMAP_MEM_ALIGNMENT) && + __builtin_constant_p(nbits & BITMAP_MEM_MASK) && + IS_ALIGNED(nbits, BITMAP_MEM_ALIGNMENT)) + memset((char *)map + start / 8, 0xff, nbits / 8); + else + __bitmap_set(map, start, nbits); +} + +static inline void bitmap_clear(unsigned long *map, unsigned int start, + unsigned int nbits) +{ + if (__builtin_constant_p(nbits) && nbits == 1) + __clear_bit(start, map); + else if (__builtin_constant_p(start & BITMAP_MEM_MASK) && + IS_ALIGNED(start, BITMAP_MEM_ALIGNMENT) && + __builtin_constant_p(nbits & BITMAP_MEM_MASK) && + IS_ALIGNED(nbits, BITMAP_MEM_ALIGNMENT)) + memset((char *)map + start / 8, 0, nbits / 8); + else + __bitmap_clear(map, start, nbits); +} + +#endif /* __LINUX_BITMAP_H */ diff --git a/roms/u-boot/include/linux/bitops.h b/roms/u-boot/include/linux/bitops.h new file mode 100644 index 000000000..d2e5ca026 --- /dev/null +++ b/roms/u-boot/include/linux/bitops.h @@ -0,0 +1,225 @@ +#ifndef _LINUX_BITOPS_H +#define _LINUX_BITOPS_H + +#if !defined(USE_HOSTCC) && !defined(__ASSEMBLY__) + +#include +#include +#include + +#ifdef __KERNEL__ +#define BIT(nr) (1UL << (nr)) +#define BIT_ULL(nr) (1ULL << (nr)) +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) +#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) +#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) +#define BITS_PER_BYTE 8 +#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) +#endif + +/* kernel.h includes log.h which include bitops.h */ +#include + +/* + * Create a contiguous bitmask starting at bit position @l and ending at + * position @h. For example + * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. + */ +#ifdef CONFIG_SANDBOX +#define GENMASK(h, l) \ + (((~0UL) << (l)) & (~0UL >> (CONFIG_SANDBOX_BITS_PER_LONG - 1 - (h)))) +#else +#define GENMASK(h, l) \ + (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) +#endif + +#define GENMASK_ULL(h, l) \ + (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +static inline int generic_ffs(int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} + +/** + * fls - find last (most-significant) bit set + * @x: the word to search + * + * This is defined the same way as ffs. + * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. + */ +static inline int generic_fls(int x) +{ + int r = 32; + + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; +} + + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +static inline unsigned int generic_hweight32(unsigned int w) +{ + unsigned int res = (w & 0x55555555) + ((w >> 1) & 0x55555555); + res = (res & 0x33333333) + ((res >> 2) & 0x33333333); + res = (res & 0x0F0F0F0F) + ((res >> 4) & 0x0F0F0F0F); + res = (res & 0x00FF00FF) + ((res >> 8) & 0x00FF00FF); + return (res & 0x0000FFFF) + ((res >> 16) & 0x0000FFFF); +} + +static inline unsigned int generic_hweight16(unsigned int w) +{ + unsigned int res = (w & 0x5555) + ((w >> 1) & 0x5555); + res = (res & 0x3333) + ((res >> 2) & 0x3333); + res = (res & 0x0F0F) + ((res >> 4) & 0x0F0F); + return (res & 0x00FF) + ((res >> 8) & 0x00FF); +} + +static inline unsigned int generic_hweight8(unsigned int w) +{ + unsigned int res = (w & 0x55) + ((w >> 1) & 0x55); + res = (res & 0x33) + ((res >> 2) & 0x33); + return (res & 0x0F) + ((res >> 4) & 0x0F); +} + +static inline unsigned long generic_hweight64(__u64 w) +{ + return generic_hweight32((unsigned int)(w >> 32)) + + generic_hweight32((unsigned int)w); +} + +static inline unsigned long hweight_long(unsigned long w) +{ + return sizeof(w) == 4 ? generic_hweight32(w) : generic_hweight64(w); +} + +#include + +/* linux/include/asm-generic/bitops/non-atomic.h */ + +#ifndef PLATFORM__SET_BIT +# define __set_bit generic_set_bit +#endif + +#ifndef PLATFORM__CLEAR_BIT +# define __clear_bit generic_clear_bit +#endif + +#ifndef PLATFORM_FFS +# define ffs generic_ffs +#endif + +#ifndef PLATFORM_FLS +# define fls generic_fls +#endif + +static inline unsigned fls_long(unsigned long l) +{ + if (sizeof(l) == 4) + return fls(l); + return fls64(l); +} + +/** + * __ffs64 - find first set bit in a 64 bit word + * @word: The 64 bit word + * + * On 64 bit arches this is a synomyn for __ffs + * The result is not defined if no bits are set, so check that @word + * is non-zero before calling this. + */ +static inline unsigned long __ffs64(u64 word) +{ +#if BITS_PER_LONG == 32 + if (((u32)word) == 0UL) + return __ffs((u32)(word >> 32)) + 32; +#elif BITS_PER_LONG != 64 +#error BITS_PER_LONG not 32 or 64 +#endif + return __ffs((unsigned long)word); +} + +/** + * __set_bit - Set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void generic_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p |= mask; +} + +static inline void generic_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p &= ~mask; +} + +#endif /* !USE_HOSTCC && !__ASSEMBLY__ */ + +#endif diff --git a/roms/u-boot/include/linux/bitrev.h b/roms/u-boot/include/linux/bitrev.h new file mode 100644 index 000000000..8ec9411aa --- /dev/null +++ b/roms/u-boot/include/linux/bitrev.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_BITREV_H +#define _LINUX_BITREV_H + +#include + +#ifdef CONFIG_HAVE_ARCH_BITREVERSE +#include + +#define __bitrev32 __arch_bitrev32 +#define __bitrev16 __arch_bitrev16 +#define __bitrev8 __arch_bitrev8 + +#else +extern u8 const byte_rev_table[256]; +static inline u8 __bitrev8(u8 byte) +{ + return byte_rev_table[byte]; +} + +static inline u16 __bitrev16(u16 x) +{ + return (__bitrev8(x & 0xff) << 8) | __bitrev8(x >> 8); +} + +static inline u32 __bitrev32(u32 x) +{ + return (__bitrev16(x & 0xffff) << 16) | __bitrev16(x >> 16); +} + +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ + +#define __bitrev8x4(x) (__bitrev32(swab32(x))) + +#define __constant_bitrev32(x) \ +({ \ + u32 __x = x; \ + __x = (__x >> 16) | (__x << 16);\ + __x = ((__x & (u32)0xFF00FF00UL) >> 8) | ((__x & (u32)0x00FF00FFUL) << 8); \ + __x = ((__x & (u32)0xF0F0F0F0UL) >> 4) | ((__x & (u32)0x0F0F0F0FUL) << 4); \ + __x = ((__x & (u32)0xCCCCCCCCUL) >> 2) | ((__x & (u32)0x33333333UL) << 2); \ + __x = ((__x & (u32)0xAAAAAAAAUL) >> 1) | ((__x & (u32)0x55555555UL) << 1); \ + __x; \ +}) + +#define __constant_bitrev16(x) \ +({ \ + u16 __x = x; \ + __x = (__x >> 8) | (__x << 8); \ + __x = ((__x & (u16)0xF0F0U) >> 4) | ((__x & (u16)0x0F0FU) << 4); \ + __x = ((__x & (u16)0xCCCCU) >> 2) | ((__x & (u16)0x3333U) << 2); \ + __x = ((__x & (u16)0xAAAAU) >> 1) | ((__x & (u16)0x5555U) << 1); \ + __x; \ +}) + +#define __constant_bitrev8x4(x) \ +({ \ + u32 __x = x; \ + __x = ((__x & (u32)0xF0F0F0F0UL) >> 4) | ((__x & (u32)0x0F0F0F0FUL) << 4); \ + __x = ((__x & (u32)0xCCCCCCCCUL) >> 2) | ((__x & (u32)0x33333333UL) << 2); \ + __x = ((__x & (u32)0xAAAAAAAAUL) >> 1) | ((__x & (u32)0x55555555UL) << 1); \ + __x; \ +}) + +#define __constant_bitrev8(x) \ +({ \ + u8 __x = x; \ + __x = (__x >> 4) | (__x << 4); \ + __x = ((__x & (u8)0xCCU) >> 2) | ((__x & (u8)0x33U) << 2); \ + __x = ((__x & (u8)0xAAU) >> 1) | ((__x & (u8)0x55U) << 1); \ + __x; \ +}) + +#define bitrev32(x) \ +({ \ + u32 __x = x; \ + __builtin_constant_p(__x) ? \ + __constant_bitrev32(__x) : \ + __bitrev32(__x); \ +}) + +#define bitrev16(x) \ +({ \ + u16 __x = x; \ + __builtin_constant_p(__x) ? \ + __constant_bitrev16(__x) : \ + __bitrev16(__x); \ +}) + +#define bitrev8x4(x) \ +({ \ + u32 __x = x; \ + __builtin_constant_p(__x) ? \ + __constant_bitrev8x4(__x) : \ + __bitrev8x4(__x); \ +}) + +#define bitrev8(x) \ +({ \ + u8 __x = x; \ + __builtin_constant_p(__x) ? \ + __constant_bitrev8(__x) : \ + __bitrev8(__x) ; \ +}) +#endif /* _LINUX_BITREV_H */ diff --git a/roms/u-boot/include/linux/bug.h b/roms/u-boot/include/linux/bug.h new file mode 100644 index 000000000..29f84168a --- /dev/null +++ b/roms/u-boot/include/linux/bug.h @@ -0,0 +1,52 @@ +#ifndef _LINUX_BUG_H +#define _LINUX_BUG_H + +#include /* for panic() */ +#include +#include +#include + +#define BUG() do { \ + printk("BUG at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \ + panic("BUG!"); \ +} while (0) + +#define BUG_ON(condition) do { if (unlikely(condition)) BUG(); } while (0) + +#define WARN_ON(condition) ({ \ + int __ret_warn_on = !!(condition); \ + if (unlikely(__ret_warn_on)) \ + printk("WARNING at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \ + unlikely(__ret_warn_on); \ +}) + +#define WARN(condition, format...) ({ \ + int __ret_warn_on = !!(condition); \ + if (unlikely(__ret_warn_on)) \ + printf(format); \ + unlikely(__ret_warn_on); \ +}) + +#define WARN_ON_ONCE(condition) ({ \ + static bool __warned; \ + int __ret_warn_once = !!(condition); \ + \ + if (unlikely(__ret_warn_once && !__warned)) { \ + __warned = true; \ + WARN_ON(1); \ + } \ + unlikely(__ret_warn_once); \ +}) + +#define WARN_ONCE(condition, format...) ({ \ + static bool __warned; \ + int __ret_warn_once = !!(condition); \ + \ + if (unlikely(__ret_warn_once && !__warned)) { \ + __warned = true; \ + WARN(1, format); \ + } \ + unlikely(__ret_warn_once); \ +}) + +#endif /* _LINUX_BUG_H */ diff --git a/roms/u-boot/include/linux/build_bug.h b/roms/u-boot/include/linux/build_bug.h new file mode 100644 index 000000000..b7d22d600 --- /dev/null +++ b/roms/u-boot/include/linux/build_bug.h @@ -0,0 +1,84 @@ +#ifndef _LINUX_BUILD_BUG_H +#define _LINUX_BUILD_BUG_H + +#include + +#ifdef __CHECKER__ +#define __BUILD_BUG_ON_NOT_POWER_OF_2(n) (0) +#define BUILD_BUG_ON_NOT_POWER_OF_2(n) (0) +#define BUILD_BUG_ON_ZERO(e) (0) +#define BUILD_BUG_ON_NULL(e) ((void *)0) +#define BUILD_BUG_ON_INVALID(e) (0) +#define BUILD_BUG_ON_MSG(cond, msg) (0) +#define BUILD_BUG_ON(condition) (0) +#define BUILD_BUG() (0) +#else /* __CHECKER__ */ + +/* Force a compilation error if a constant expression is not a power of 2 */ +#define __BUILD_BUG_ON_NOT_POWER_OF_2(n) \ + BUILD_BUG_ON(((n) & ((n) - 1)) != 0) +#define BUILD_BUG_ON_NOT_POWER_OF_2(n) \ + BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0)) + +/* + * Force a compilation error if condition is true, but also produce a + * result (of value 0 and type size_t), so the expression can be used + * e.g. in a structure initializer (or where-ever else comma expressions + * aren't permitted). + */ +#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:(-!!(e)); })) +#define BUILD_BUG_ON_NULL(e) ((void *)sizeof(struct { int:(-!!(e)); })) + +/* + * BUILD_BUG_ON_INVALID() permits the compiler to check the validity of the + * expression but avoids the generation of any code, even if that expression + * has side-effects. + */ +#define BUILD_BUG_ON_INVALID(e) ((void)(sizeof((__force long)(e)))) + +/** + * BUILD_BUG_ON_MSG - break compile if a condition is true & emit supplied + * error message. + * @condition: the condition which the compiler should know is false. + * + * See BUILD_BUG_ON for description. + */ +#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) + +/** + * BUILD_BUG_ON - break compile if a condition is true. + * @condition: the condition which the compiler should know is false. + * + * If you have some code which relies on certain constants being equal, or + * some other compile-time-evaluated condition, you should use BUILD_BUG_ON to + * detect if someone changes it. + * + * The implementation uses gcc's reluctance to create a negative array, but gcc + * (as of 4.4) only emits that error for obvious cases (e.g. not arguments to + * inline functions). Luckily, in 4.3 they added the "error" function + * attribute just for this type of case. Thus, we use a negative sized array + * (should always create an error on gcc versions older than 4.4) and then call + * an undefined function with the error attribute (should always create an + * error on gcc 4.3 and later). If for some reason, neither creates a + * compile-time error, we'll still have a link-time error, which is harder to + * track down. + */ +#ifndef __OPTIMIZE__ +#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)])) +#else +#define BUILD_BUG_ON(condition) \ + BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition) +#endif + +/** + * BUILD_BUG - break compile if used. + * + * If you have some code that you expect the compiler to eliminate at + * build time, you should use BUILD_BUG to detect if it is + * unexpectedly used. + */ +#define BUILD_BUG() BUILD_BUG_ON_MSG(1, "BUILD_BUG failed") + +#endif /* __CHECKER__ */ + +#endif /* _LINUX_BUILD_BUG_H */ diff --git a/roms/u-boot/include/linux/byteorder/big_endian.h b/roms/u-boot/include/linux/byteorder/big_endian.h new file mode 100644 index 000000000..aaf77577c --- /dev/null +++ b/roms/u-boot/include/linux/byteorder/big_endian.h @@ -0,0 +1,110 @@ +#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H +#define _LINUX_BYTEORDER_BIG_ENDIAN_H + +#ifndef __BIG_ENDIAN +#define __BIG_ENDIAN 4321 +#endif +#ifndef __BIG_ENDIAN_BITFIELD +#define __BIG_ENDIAN_BITFIELD +#endif +#define __BYTE_ORDER __BIG_ENDIAN + +#include +#include +#include + +#define __constant_htonl(x) ((__force __be32)(__u32)(x)) +#define __constant_ntohl(x) ((__force __u32)(__be32)(x)) +#define __constant_htons(x) ((__force __be16)(__u16)(x)) +#define __constant_ntohs(x) ((__force __u16)(__be16)(x)) +#define __constant_cpu_to_le64(x) ((__force __le64)___constant_swab64((x))) +#define __constant_le64_to_cpu(x) ___constant_swab64((__force __u64)(__le64)(x)) +#define __constant_cpu_to_le32(x) ((__force __le32)___constant_swab32((x))) +#define __constant_le32_to_cpu(x) ___constant_swab32((__force __u32)(__le32)(x)) +#define __constant_cpu_to_le16(x) ((__force __le16)___constant_swab16((x))) +#define __constant_le16_to_cpu(x) ___constant_swab16((__force __u16)(__le16)(x)) +#define __constant_cpu_to_be64(x) ((__force __be64)(__u64)(x)) +#define __constant_be64_to_cpu(x) ((__force __u64)(__be64)(x)) +#define __constant_cpu_to_be32(x) ((__force __be32)(__u32)(x)) +#define __constant_be32_to_cpu(x) ((__force __u32)(__be32)(x)) +#define __constant_cpu_to_be16(x) ((__force __be16)(__u16)(x)) +#define __constant_be16_to_cpu(x) ((__force __u16)(__be16)(x)) +#define __cpu_to_le64(x) ((__force __le64)__swab64((x))) +#define __le64_to_cpu(x) __swab64((__force __u64)(__le64)(x)) +#define __cpu_to_le32(x) ((__force __le32)__swab32((x))) +#define __le32_to_cpu(x) __swab32((__force __u32)(__le32)(x)) +#define __cpu_to_le16(x) ((__force __le16)__swab16((x))) +#define __le16_to_cpu(x) __swab16((__force __u16)(__le16)(x)) +#define __cpu_to_be64(x) ((__force __be64)(__u64)(x)) +#define __be64_to_cpu(x) ((__force __u64)(__be64)(x)) +#define __cpu_to_be32(x) ((__force __be32)(__u32)(x)) +#define __be32_to_cpu(x) ((__force __u32)(__be32)(x)) +#define __cpu_to_be16(x) ((__force __be16)(__u16)(x)) +#define __be16_to_cpu(x) ((__force __u16)(__be16)(x)) + +static inline __le64 __cpu_to_le64p(const __u64 *p) +{ + return (__force __le64)__swab64p(p); +} +static inline __u64 __le64_to_cpup(const __le64 *p) +{ + return __swab64p((__u64 *)p); +} +static inline __le32 __cpu_to_le32p(const __u32 *p) +{ + return (__force __le32)__swab32p(p); +} +static inline __u32 __le32_to_cpup(const __le32 *p) +{ + return __swab32p((__u32 *)p); +} +static inline __le16 __cpu_to_le16p(const __u16 *p) +{ + return (__force __le16)__swab16p(p); +} +static inline __u16 __le16_to_cpup(const __le16 *p) +{ + return __swab16p((__u16 *)p); +} +static inline __be64 __cpu_to_be64p(const __u64 *p) +{ + return (__force __be64)*p; +} +static inline __u64 __be64_to_cpup(const __be64 *p) +{ + return (__force __u64)*p; +} +static inline __be32 __cpu_to_be32p(const __u32 *p) +{ + return (__force __be32)*p; +} +static inline __u32 __be32_to_cpup(const __be32 *p) +{ + return (__force __u32)*p; +} +static inline __be16 __cpu_to_be16p(const __u16 *p) +{ + return (__force __be16)*p; +} +static inline __u16 __be16_to_cpup(const __be16 *p) +{ + return (__force __u16)*p; +} +#define __cpu_to_le64s(x) __swab64s((x)) +#define __le64_to_cpus(x) __swab64s((x)) +#define __cpu_to_le32s(x) __swab32s((x)) +#define __le32_to_cpus(x) __swab32s((x)) +#define __cpu_to_le16s(x) __swab16s((x)) +#define __le16_to_cpus(x) __swab16s((x)) +#define __cpu_to_be64s(x) do { (void)(x); } while (0) +#define __be64_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_be32s(x) do { (void)(x); } while (0) +#define __be32_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_be16s(x) do { (void)(x); } while (0) +#define __be16_to_cpus(x) do { (void)(x); } while (0) + +#ifdef __KERNEL__ +#include +#endif + +#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */ diff --git a/roms/u-boot/include/linux/byteorder/generic.h b/roms/u-boot/include/linux/byteorder/generic.h new file mode 100644 index 000000000..8fae186d1 --- /dev/null +++ b/roms/u-boot/include/linux/byteorder/generic.h @@ -0,0 +1,207 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_BYTEORDER_GENERIC_H +#define _LINUX_BYTEORDER_GENERIC_H + +/* + * linux/byteorder/generic.h + * Generic Byte-reordering support + * + * The "... p" macros, like le64_to_cpup, can be used with pointers + * to unaligned data, but there will be a performance penalty on + * some architectures. Use get_unaligned for unaligned data. + * + * Francois-Rene Rideau 19970707 + * gathered all the good ideas from all asm-foo/byteorder.h into one file, + * cleaned them up. + * I hope it is compliant with non-GCC compilers. + * I decided to put __BYTEORDER_HAS_U64__ in byteorder.h, + * because I wasn't sure it would be ok to put it in types.h + * Upgraded it to 2.1.43 + * Francois-Rene Rideau 19971012 + * Upgraded it to 2.1.57 + * to please Linus T., replaced huge #ifdef's between little/big endian + * by nestedly #include'd files. + * Francois-Rene Rideau 19971205 + * Made it to 2.1.71; now a facelift: + * Put files under include/linux/byteorder/ + * Split swab from generic support. + * + * TODO: + * = Regular kernel maintainers could also replace all these manual + * byteswap macros that remain, disseminated among drivers, + * after some grep or the sources... + * = Linus might want to rename all these macros and files to fit his taste, + * to fit his personal naming scheme. + * = it seems that a few drivers would also appreciate + * nybble swapping support... + * = every architecture could add their byteswap macro in asm/byteorder.h + * see how some architectures already do (i386, alpha, ppc, etc) + * = cpu_to_beXX and beXX_to_cpu might some day need to be well + * distinguished throughout the kernel. This is not the case currently, + * since little endian, big endian, and pdp endian machines needn't it. + * But this might be the case for, say, a port of Linux to 20/21 bit + * architectures (and F21 Linux addict around?). + */ + +/* + * The following macros are to be defined by : + * + * Conversion of long and short int between network and host format + * ntohl(__u32 x) + * ntohs(__u16 x) + * htonl(__u32 x) + * htons(__u16 x) + * It seems that some programs (which? where? or perhaps a standard? POSIX?) + * might like the above to be functions, not macros (why?). + * if that's true, then detect them, and take measures. + * Anyway, the measure is: define only ___ntohl as a macro instead, + * and in a separate file, have + * unsigned long inline ntohl(x){return ___ntohl(x);} + * + * The same for constant arguments + * __constant_ntohl(__u32 x) + * __constant_ntohs(__u16 x) + * __constant_htonl(__u32 x) + * __constant_htons(__u16 x) + * + * Conversion of XX-bit integers (16- 32- or 64-) + * between native CPU format and little/big endian format + * 64-bit stuff only defined for proper architectures + * cpu_to_[bl]eXX(__uXX x) + * [bl]eXX_to_cpu(__uXX x) + * + * The same, but takes a pointer to the value to convert + * cpu_to_[bl]eXXp(__uXX x) + * [bl]eXX_to_cpup(__uXX x) + * + * The same, but change in situ + * cpu_to_[bl]eXXs(__uXX x) + * [bl]eXX_to_cpus(__uXX x) + * + * See asm-foo/byteorder.h for examples of how to provide + * architecture-optimized versions + * + */ + +#define cpu_to_le64 __cpu_to_le64 +#define le64_to_cpu __le64_to_cpu +#define cpu_to_le32 __cpu_to_le32 +#define le32_to_cpu __le32_to_cpu +#define cpu_to_le16 __cpu_to_le16 +#define le16_to_cpu __le16_to_cpu +#define cpu_to_be64 __cpu_to_be64 +#define be64_to_cpu __be64_to_cpu +#define cpu_to_be32 __cpu_to_be32 +#define be32_to_cpu __be32_to_cpu +#define cpu_to_be16 __cpu_to_be16 +#define be16_to_cpu __be16_to_cpu +#define cpu_to_le64p __cpu_to_le64p +#define le64_to_cpup __le64_to_cpup +#define cpu_to_le32p __cpu_to_le32p +#define le32_to_cpup __le32_to_cpup +#define cpu_to_le16p __cpu_to_le16p +#define le16_to_cpup __le16_to_cpup +#define cpu_to_be64p __cpu_to_be64p +#define be64_to_cpup __be64_to_cpup +#define cpu_to_be32p __cpu_to_be32p +#define be32_to_cpup __be32_to_cpup +#define cpu_to_be16p __cpu_to_be16p +#define be16_to_cpup __be16_to_cpup +#define cpu_to_le64s __cpu_to_le64s +#define le64_to_cpus __le64_to_cpus +#define cpu_to_le32s __cpu_to_le32s +#define le32_to_cpus __le32_to_cpus +#define cpu_to_le16s __cpu_to_le16s +#define le16_to_cpus __le16_to_cpus +#define cpu_to_be64s __cpu_to_be64s +#define be64_to_cpus __be64_to_cpus +#define cpu_to_be32s __cpu_to_be32s +#define be32_to_cpus __be32_to_cpus +#define cpu_to_be16s __cpu_to_be16s +#define be16_to_cpus __be16_to_cpus + +/* + * They have to be macros in order to do the constant folding + * correctly - if the argument passed into a inline function + * it is no longer constant according to gcc.. + */ + +#undef ntohl +#undef ntohs +#undef htonl +#undef htons + +#define ___htonl(x) __cpu_to_be32(x) +#define ___htons(x) __cpu_to_be16(x) +#define ___ntohl(x) __be32_to_cpu(x) +#define ___ntohs(x) __be16_to_cpu(x) + +#define htonl(x) ___htonl(x) +#define ntohl(x) ___ntohl(x) +#define htons(x) ___htons(x) +#define ntohs(x) ___ntohs(x) + +static inline void le16_add_cpu(__le16 *var, u16 val) +{ + *var = cpu_to_le16(le16_to_cpu(*var) + val); +} + +static inline void le32_add_cpu(__le32 *var, u32 val) +{ + *var = cpu_to_le32(le32_to_cpu(*var) + val); +} + +static inline void le64_add_cpu(__le64 *var, u64 val) +{ + *var = cpu_to_le64(le64_to_cpu(*var) + val); +} + +/* XXX: this stuff can be optimized */ +static inline void le32_to_cpu_array(u32 *buf, unsigned int words) +{ + while (words--) { + __le32_to_cpus(buf); + buf++; + } +} + +static inline void cpu_to_le32_array(u32 *buf, unsigned int words) +{ + while (words--) { + __cpu_to_le32s(buf); + buf++; + } +} + +static inline void be16_add_cpu(__be16 *var, u16 val) +{ + *var = cpu_to_be16(be16_to_cpu(*var) + val); +} + +static inline void be32_add_cpu(__be32 *var, u32 val) +{ + *var = cpu_to_be32(be32_to_cpu(*var) + val); +} + +static inline void be64_add_cpu(__be64 *var, u64 val) +{ + *var = cpu_to_be64(be64_to_cpu(*var) + val); +} + +static inline void cpu_to_be32_array(__be32 *dst, const u32 *src, size_t len) +{ + int i; + + for (i = 0; i < len; i++) + dst[i] = cpu_to_be32(src[i]); +} + +static inline void be32_to_cpu_array(u32 *dst, const __be32 *src, size_t len) +{ + int i; + + for (i = 0; i < len; i++) + dst[i] = be32_to_cpu(src[i]); +} + +#endif /* _LINUX_BYTEORDER_GENERIC_H */ diff --git a/roms/u-boot/include/linux/byteorder/little_endian.h b/roms/u-boot/include/linux/byteorder/little_endian.h new file mode 100644 index 000000000..a4cb3bfde --- /dev/null +++ b/roms/u-boot/include/linux/byteorder/little_endian.h @@ -0,0 +1,110 @@ +#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H +#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H + +#ifndef __LITTLE_ENDIAN +#define __LITTLE_ENDIAN 1234 +#endif +#ifndef __LITTLE_ENDIAN_BITFIELD +#define __LITTLE_ENDIAN_BITFIELD +#endif +#define __BYTE_ORDER __LITTLE_ENDIAN + +#include +#include +#include + +#define __constant_htonl(x) ((__force __be32)___constant_swab32((x))) +#define __constant_ntohl(x) ___constant_swab32((__force __be32)(x)) +#define __constant_htons(x) ((__force __be16)___constant_swab16((x))) +#define __constant_ntohs(x) ___constant_swab16((__force __be16)(x)) +#define __constant_cpu_to_le64(x) ((__force __le64)(__u64)(x)) +#define __constant_le64_to_cpu(x) ((__force __u64)(__le64)(x)) +#define __constant_cpu_to_le32(x) ((__force __le32)(__u32)(x)) +#define __constant_le32_to_cpu(x) ((__force __u32)(__le32)(x)) +#define __constant_cpu_to_le16(x) ((__force __le16)(__u16)(x)) +#define __constant_le16_to_cpu(x) ((__force __u16)(__le16)(x)) +#define __constant_cpu_to_be64(x) ((__force __be64)___constant_swab64((x))) +#define __constant_be64_to_cpu(x) ___constant_swab64((__force __u64)(__be64)(x)) +#define __constant_cpu_to_be32(x) ((__force __be32)___constant_swab32((x))) +#define __constant_be32_to_cpu(x) ___constant_swab32((__force __u32)(__be32)(x)) +#define __constant_cpu_to_be16(x) ((__force __be16)___constant_swab16((x))) +#define __constant_be16_to_cpu(x) ___constant_swab16((__force __u16)(__be16)(x)) +#define __cpu_to_le64(x) ((__force __le64)(__u64)(x)) +#define __le64_to_cpu(x) ((__force __u64)(__le64)(x)) +#define __cpu_to_le32(x) ((__force __le32)(__u32)(x)) +#define __le32_to_cpu(x) ((__force __u32)(__le32)(x)) +#define __cpu_to_le16(x) ((__force __le16)(__u16)(x)) +#define __le16_to_cpu(x) ((__force __u16)(__le16)(x)) +#define __cpu_to_be64(x) ((__force __be64)__swab64((x))) +#define __be64_to_cpu(x) __swab64((__force __u64)(__be64)(x)) +#define __cpu_to_be32(x) ((__force __be32)__swab32((x))) +#define __be32_to_cpu(x) __swab32((__force __u32)(__be32)(x)) +#define __cpu_to_be16(x) ((__force __be16)__swab16((x))) +#define __be16_to_cpu(x) __swab16((__force __u16)(__be16)(x)) + +static inline __le64 __cpu_to_le64p(const __u64 *p) +{ + return (__force __le64)*p; +} +static inline __u64 __le64_to_cpup(const __le64 *p) +{ + return (__force __u64)*p; +} +static inline __le32 __cpu_to_le32p(const __u32 *p) +{ + return (__force __le32)*p; +} +static inline __u32 __le32_to_cpup(const __le32 *p) +{ + return (__force __u32)*p; +} +static inline __le16 __cpu_to_le16p(const __u16 *p) +{ + return (__force __le16)*p; +} +static inline __u16 __le16_to_cpup(const __le16 *p) +{ + return (__force __u16)*p; +} +static inline __be64 __cpu_to_be64p(const __u64 *p) +{ + return (__force __be64)__swab64p(p); +} +static inline __u64 __be64_to_cpup(const __be64 *p) +{ + return __swab64p((__u64 *)p); +} +static inline __be32 __cpu_to_be32p(const __u32 *p) +{ + return (__force __be32)__swab32p(p); +} +static inline __u32 __be32_to_cpup(const __be32 *p) +{ + return __swab32p((__u32 *)p); +} +static inline __be16 __cpu_to_be16p(const __u16 *p) +{ + return (__force __be16)__swab16p(p); +} +static inline __u16 __be16_to_cpup(const __be16 *p) +{ + return __swab16p((__u16 *)p); +} +#define __cpu_to_le64s(x) do { (void)(x); } while (0) +#define __le64_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_le32s(x) do { (void)(x); } while (0) +#define __le32_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_le16s(x) do { (void)(x); } while (0) +#define __le16_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_be64s(x) __swab64s((x)) +#define __be64_to_cpus(x) __swab64s((x)) +#define __cpu_to_be32s(x) __swab32s((x)) +#define __be32_to_cpus(x) __swab32s((x)) +#define __cpu_to_be16s(x) __swab16s((x)) +#define __be16_to_cpus(x) __swab16s((x)) + +#ifdef __KERNEL__ +#include +#endif + +#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */ diff --git a/roms/u-boot/include/linux/byteorder/swab.h b/roms/u-boot/include/linux/byteorder/swab.h new file mode 100644 index 000000000..4334fa77e --- /dev/null +++ b/roms/u-boot/include/linux/byteorder/swab.h @@ -0,0 +1,156 @@ +#ifndef _LINUX_BYTEORDER_SWAB_H +#define _LINUX_BYTEORDER_SWAB_H + +/* + * linux/byteorder/swab.h + * Byte-swapping, independently from CPU endianness + * swabXX[ps]?(foo) + * + * Francois-Rene Rideau 19971205 + * separated swab functions from cpu_to_XX, + * to clean up support for bizarre-endian architectures. + * + * See asm-i386/byteorder.h and suches for examples of how to provide + * architecture-dependent optimized versions + * + */ + +/* casts are necessary for constants, because we never know how for sure + * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. + */ +#define ___swab16(x) \ + ((__u16)( \ + (((__u16)(x) & (__u16)0x00ffU) << 8) | \ + (((__u16)(x) & (__u16)0xff00U) >> 8) )) +#define ___swab32(x) \ + ((__u32)( \ + (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ + (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x) & (__u32)0xff000000UL) >> 24) )) +#define ___swab64(x) \ + ((__u64)( \ + (__u64)(((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \ + (__u64)(((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \ + (__u64)(((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \ + (__u64)(((__u64)(x) & (__u64)0x00000000ff000000ULL) << 8) | \ + (__u64)(((__u64)(x) & (__u64)0x000000ff00000000ULL) >> 8) | \ + (__u64)(((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \ + (__u64)(((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \ + (__u64)(((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56) )) + +/* + * provide defaults when no architecture-specific optimization is detected + */ +#ifndef __arch__swab16 +# define __arch__swab16(x) ___swab16(x) +#endif +#ifndef __arch__swab32 +# define __arch__swab32(x) ___swab32(x) +#endif +#ifndef __arch__swab64 +# define __arch__swab64(x) ___swab64(x) +#endif + +#ifndef __arch__swab16p +# define __arch__swab16p(x) __swab16(*(x)) +#endif +#ifndef __arch__swab32p +# define __arch__swab32p(x) __swab32(*(x)) +#endif +#ifndef __arch__swab64p +# define __arch__swab64p(x) __swab64(*(x)) +#endif + +#ifndef __arch__swab16s +# define __arch__swab16s(x) do { *(x) = __swab16p((x)); } while (0) +#endif +#ifndef __arch__swab32s +# define __arch__swab32s(x) do { *(x) = __swab32p((x)); } while (0) +#endif +#ifndef __arch__swab64s +# define __arch__swab64s(x) do { *(x) = __swab64p((x)); } while (0) +#endif + + +/* + * Allow constant folding + */ +#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) +# define __swab16(x) \ +(__builtin_constant_p((__u16)(x)) ? \ + ___swab16((x)) : \ + __fswab16((x))) +# define __swab32(x) \ +(__builtin_constant_p((__u32)(x)) ? \ + ___swab32((x)) : \ + __fswab32((x))) +# define __swab64(x) \ +(__builtin_constant_p((__u64)(x)) ? \ + ___swab64((x)) : \ + __fswab64((x))) +#else +# define __swab16(x) __fswab16(x) +# define __swab32(x) __fswab32(x) +# define __swab64(x) __fswab64(x) +#endif /* OPTIMIZE */ + + +static __inline__ __attribute__((const)) __u16 __fswab16(__u16 x) +{ + return __arch__swab16(x); +} +static __inline__ __u16 __swab16p(const __u16 *x) +{ + return __arch__swab16p(x); +} +static __inline__ void __swab16s(__u16 *addr) +{ + __arch__swab16s(addr); +} + +static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x) +{ + return __arch__swab32(x); +} +static __inline__ __u32 __swab32p(const __u32 *x) +{ + return __arch__swab32p(x); +} +static __inline__ void __swab32s(__u32 *addr) +{ + __arch__swab32s(addr); +} + +static __inline__ __attribute__((const)) __u64 __fswab64(__u64 x) +{ +# ifdef __SWAB_64_THRU_32__ + __u32 h = x >> 32; + __u32 l = x & ((1ULL<<32)-1); + return (((__u64)__swab32(l)) << 32) | ((__u64)(__swab32(h))); +# else + return __arch__swab64(x); +# endif +} +static __inline__ __u64 __swab64p(const __u64 *x) +{ + return __arch__swab64p(x); +} +static __inline__ void __swab64s(__u64 *addr) +{ + __arch__swab64s(addr); +} + +#if defined(__KERNEL__) +#define swab16 __swab16 +#define swab32 __swab32 +#define swab64 __swab64 +#define swab16p __swab16p +#define swab32p __swab32p +#define swab64p __swab64p +#define swab16s __swab16s +#define swab32s __swab32s +#define swab64s __swab64s +#endif + +#endif /* _LINUX_BYTEORDER_SWAB_H */ diff --git a/roms/u-boot/include/linux/clk-provider.h b/roms/u-boot/include/linux/clk-provider.h new file mode 100644 index 000000000..6fda14f5f --- /dev/null +++ b/roms/u-boot/include/linux/clk-provider.h @@ -0,0 +1,254 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * Copyright (c) 2010-2011 Jeremy Kerr + * Copyright (C) 2011-2012 Linaro Ltd + */ +#ifndef __LINUX_CLK_PROVIDER_H +#define __LINUX_CLK_PROVIDER_H + +#include +#include +#include + +struct udevice; + +static inline void clk_dm(ulong id, struct clk *clk) +{ + if (!IS_ERR(clk)) + clk->id = id; +} + +/* + * flags used across common struct clk. these flags should only affect the + * top-level framework. custom flags for dealing with hardware specifics + * belong in struct clk_foo + * + * Please update clk_flags[] in drivers/clk/clk.c when making changes here! + */ +#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ +#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ +#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ +#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ + /* unused */ +#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ +#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ +#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ +#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ +#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ +#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ +#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ +/* parents need enable during gate/ungate, set rate and re-parent */ +#define CLK_OPS_PARENT_ENABLE BIT(12) +/* duty cycle call may be forwarded to the parent clock */ +#define CLK_DUTY_CYCLE_PARENT BIT(13) + +#define CLK_MUX_INDEX_ONE BIT(0) +#define CLK_MUX_INDEX_BIT BIT(1) +#define CLK_MUX_HIWORD_MASK BIT(2) +#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ +#define CLK_MUX_ROUND_CLOSEST BIT(4) + +struct clk_mux { + struct clk clk; + void __iomem *reg; + u32 *table; + u32 mask; + u8 shift; + u8 flags; + + /* + * Fields from struct clk_init_data - this struct has been + * omitted to avoid too deep level of CCF for bootloader + */ + const char * const *parent_names; + u8 num_parents; +#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) + u32 io_mux_val; +#endif + +}; + +#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk) +extern const struct clk_ops clk_mux_ops; +u8 clk_mux_get_parent(struct clk *clk); + +/** + * clk_mux_index_to_val() - Convert the parent index to the register value + * + * It returns the value to write in the hardware register to output the selected + * input clock parent. + * + * @table: array of register values corresponding to the parent index (optional) + * @flags: hardware-specific flags + * @index: parent clock index + * @return the register value + */ +unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index); + +struct clk_gate { + struct clk clk; + void __iomem *reg; + u8 bit_idx; + u8 flags; +#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) + u32 io_gate_val; +#endif +}; + +#define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk) + +#define CLK_GATE_SET_TO_DISABLE BIT(0) +#define CLK_GATE_HIWORD_MASK BIT(1) + +extern const struct clk_ops clk_gate_ops; +struct clk *clk_register_gate(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); + +struct clk_div_table { + unsigned int val; + unsigned int div; +}; + +struct clk_divider { + struct clk clk; + void __iomem *reg; + u8 shift; + u8 width; + u8 flags; + const struct clk_div_table *table; +#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) + u32 io_divider_val; +#endif +}; + +#define clk_div_mask(width) ((1 << (width)) - 1) +#define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk) + +#define CLK_DIVIDER_ONE_BASED BIT(0) +#define CLK_DIVIDER_POWER_OF_TWO BIT(1) +#define CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define CLK_DIVIDER_HIWORD_MASK BIT(3) +#define CLK_DIVIDER_ROUND_CLOSEST BIT(4) +#define CLK_DIVIDER_READ_ONLY BIT(5) +#define CLK_DIVIDER_MAX_AT_ZERO BIT(6) +extern const struct clk_ops clk_divider_ops; + +/** + * clk_divider_get_table_div() - convert the register value to the divider + * + * @table: array of register values corresponding to valid dividers + * @val: value to convert + * @return the divider + */ +unsigned int clk_divider_get_table_div(const struct clk_div_table *table, + unsigned int val); + +/** + * clk_divider_get_table_val() - convert the divider to the register value + * + * It returns the value to write in the hardware register to divide the input + * clock rate by @div. + * + * @table: array of register values corresponding to valid dividers + * @div: requested divider + * @return the register value + */ +unsigned int clk_divider_get_table_val(const struct clk_div_table *table, + unsigned int div); + +/** + * clk_divider_is_valid_div() - check if the divider is valid + * + * @table: array of valid dividers (optional) + * @div: divider to check + * @flags: hardware-specific flags + * @return true if the divider is valid, false otherwise + */ +bool clk_divider_is_valid_div(const struct clk_div_table *table, + unsigned int div, unsigned long flags); + +/** + * clk_divider_is_valid_table_div - check if the divider is in the @table array + * + * @table: array of valid dividers + * @div: divider to check + * @return true if the divider is found in the @table array, false otherwise + */ +bool clk_divider_is_valid_table_div(const struct clk_div_table *table, + unsigned int div); +unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate, + unsigned int val, + const struct clk_div_table *table, + unsigned long flags, unsigned long width); + +struct clk_fixed_factor { + struct clk clk; + unsigned int mult; + unsigned int div; +}; + +extern const struct clk_ops clk_fixed_rate_ops; + +#define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\ + clk) + +struct clk_fixed_rate { + struct clk clk; + unsigned long fixed_rate; +}; + +#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_plat(dev)) + +void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev, + struct clk_fixed_rate *plat); + +struct clk_composite { + struct clk clk; + struct clk_ops ops; + + struct clk *mux; + struct clk *rate; + struct clk *gate; + + const struct clk_ops *mux_ops; + const struct clk_ops *rate_ops; + const struct clk_ops *gate_ops; +}; + +#define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk) + +struct clk *clk_register_composite(struct device *dev, const char *name, + const char * const *parent_names, int num_parents, + struct clk *mux_clk, const struct clk_ops *mux_ops, + struct clk *rate_clk, const struct clk_ops *rate_ops, + struct clk *gate_clk, const struct clk_ops *gate_ops, + unsigned long flags); + +int clk_register(struct clk *clk, const char *drv_name, const char *name, + const char *parent_name); + +struct clk *clk_register_fixed_factor(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + unsigned int mult, unsigned int div); + +struct clk *clk_register_divider(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags); + +struct clk *clk_register_mux(struct device *dev, const char *name, + const char * const *parent_names, u8 num_parents, + unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_mux_flags); + +const char *clk_hw_get_name(const struct clk *hw); +ulong clk_generic_get_rate(struct clk *clk); + +struct clk *dev_get_clk_ptr(struct udevice *dev); +#endif /* __LINUX_CLK_PROVIDER_H */ diff --git a/roms/u-boot/include/linux/clk/analogbits-wrpll-cln28hpc.h b/roms/u-boot/include/linux/clk/analogbits-wrpll-cln28hpc.h new file mode 100644 index 000000000..03279097e --- /dev/null +++ b/roms/u-boot/include/linux/clk/analogbits-wrpll-cln28hpc.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018-2019 SiFive, Inc. + * Wesley Terpstra + * Paul Walmsley + */ + +#ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H +#define __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H + +#include + +/* DIVQ_VALUES: number of valid DIVQ values */ +#define DIVQ_VALUES 6 + +/* + * Bit definitions for struct wrpll_cfg.flags + * + * WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be + * programmed to enter bypass + * WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset + * WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal + * feedback mode + * WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external + * feedback mode (not yet supported by this driver) + */ +#define WRPLL_FLAGS_BYPASS_SHIFT 0 +#define WRPLL_FLAGS_BYPASS_MASK BIT(WRPLL_FLAGS_BYPASS_SHIFT) +#define WRPLL_FLAGS_RESET_SHIFT 1 +#define WRPLL_FLAGS_RESET_MASK BIT(WRPLL_FLAGS_RESET_SHIFT) +#define WRPLL_FLAGS_INT_FEEDBACK_SHIFT 2 +#define WRPLL_FLAGS_INT_FEEDBACK_MASK BIT(WRPLL_FLAGS_INT_FEEDBACK_SHIFT) +#define WRPLL_FLAGS_EXT_FEEDBACK_SHIFT 3 +#define WRPLL_FLAGS_EXT_FEEDBACK_MASK BIT(WRPLL_FLAGS_EXT_FEEDBACK_SHIFT) + +/** + * struct wrpll_cfg - WRPLL configuration values + * @divr: reference divider value (6 bits), as presented to the PLL signals + * @divf: feedback divider value (9 bits), as presented to the PLL signals + * @divq: output divider value (3 bits), as presented to the PLL signals + * @flags: PLL configuration flags. See above for more information + * @range: PLL loop filter range. See below for more information + * @output_rate_cache: cached output rates, swept across DIVQ + * @parent_rate: PLL refclk rate for which values are valid + * @max_r: maximum possible R divider value, given @parent_rate + * @init_r: initial R divider value to start the search from + * + * @divr, @divq, @divq, @range represent what the PLL expects to see + * on its input signals. Thus @divr and @divf are the actual divisors + * minus one. @divq is a power-of-two divider; for example, 1 = + * divide-by-2 and 6 = divide-by-64. 0 is an invalid @divq value. + * + * When initially passing a struct wrpll_cfg record, the + * record should be zero-initialized with the exception of the @flags + * field. The only flag bits that need to be set are either + * WRPLL_FLAGS_INT_FEEDBACK or WRPLL_FLAGS_EXT_FEEDBACK. + */ +struct wrpll_cfg { + u8 divr; + u8 divq; + u8 range; + u8 flags; + u16 divf; +/* private: */ + u32 output_rate_cache[DIVQ_VALUES]; + unsigned long parent_rate; + u8 max_r; + u8 init_r; +}; + +int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate, + unsigned long parent_rate); + +unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c); + +unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c, + unsigned long parent_rate); + +#endif /* __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H */ diff --git a/roms/u-boot/include/linux/clk/at91_pmc.h b/roms/u-boot/include/linux/clk/at91_pmc.h new file mode 100644 index 000000000..ee39e72e2 --- /dev/null +++ b/roms/u-boot/include/linux/clk/at91_pmc.h @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Power Management Controller (PMC) - System peripherals registers. + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Based on AT91RM9200 datasheet revision E. + * Based on include/linux/clk/at91_pmc.h on Linux. + */ + +#ifndef AT91_PMC_H_ +#define AT91_PMC_H_ + +#define AT91_PMC_V1 (1) /* PMC version 1 */ +#define AT91_PMC_V2 (2) /* PMC version 2 [SAM9X60] */ + +#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ +#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */ + +#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */ +#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ +#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ +#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ +#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ +#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ +#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ +#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ +#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ +#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ +#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ +#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ + +#define AT91_PMC_PLL_CTRL0 0x0C /* PLL Control Register 0 [for SAM9X60] */ +#define AT91_PMC_PLL_CTRL0_ENPLL (1 << 28) /* Enable PLL */ +#define AT91_PMC_PLL_CTRL0_ENPLLCK (1 << 29) /* Enable PLL clock for PMC */ +#define AT91_PMC_PLL_CTRL0_ENLOCK (1 << 31) /* Enable PLL lock */ + +#define AT91_PMC_PLL_CTRL1 0x10 /* PLL Control Register 1 [for SAM9X60] */ + +#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */ +#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ +#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */ + +#define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */ +#define AT91_PMC_PLL_ACR_DEFAULT_UPLL 0x12020010UL /* Default PLL ACR value for UPLL */ +#define AT91_PMC_PLL_ACR_DEFAULT_PLLA 0x00020010UL /* Default PLL ACR value for PLLA */ +#define AT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage regulator Control */ +#define AT91_PMC_PLL_ACR_UTMIBG (1 << 13) /* UPLL Bandgap Control */ + +#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */ +#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ +#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ +#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ +#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ + +#define AT91_PMC_PLL_UPDT 0x1C /* PMC PLL update register [for SAM9X60] */ +#define AT91_PMC_PLL_UPDT_ID_MSK (0xf) +#define AT91_PMC_PLL_UPDT_UPDATE (1 << 8) /* Update PLL settings */ +#define AT91_PMC_PLL_UPDT_ID (1 << 0) /* PLL ID */ +#define AT91_PMC_PLL_UPDT_STUPTIM(n) ((n) << 16) /* Startup time */ +#define AT91_PMC_PMM_UPDT_STUPTIM_MSK (0xff << 16) + +#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ +#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ +#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ +#define AT91_PMC_WAITMODE (1 << 2) /* Wait Mode Command */ +#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ +#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ +#define AT91_PMC_KEY_MASK (0xff << 16) +#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ +#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ +#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ + +#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */ +#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ +#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ + +#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ +#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ +#define AT91_PMC_DIV (0xff << 0) /* Divider */ +#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ +#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ +#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ +#define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff) +#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */ +#define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f) +#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ +#define AT91_PMC_USBDIV_1 (0 << 28) +#define AT91_PMC_USBDIV_2 (1 << 28) +#define AT91_PMC_USBDIV_4 (2 << 28) +#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ + +#define AT91_PMC_CPU_CKR 0x28 /* CPU Clock Register */ + +#define AT91_PMC_MCKR 0x30 /* Master Clock Register */ +#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ +#define AT91_PMC_CSS_SLOW (0 << 0) +#define AT91_PMC_CSS_MAIN (1 << 0) +#define AT91_PMC_CSS_PLLA (2 << 0) +#define AT91_PMC_CSS_PLLB (3 << 0) +#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ +#define PMC_PRES_OFFSET 2 +#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */ +#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET) +#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET) +#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET) +#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET) +#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET) +#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET) +#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET) +#define PMC_ALT_PRES_OFFSET 4 +#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */ +#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET) +#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET) +#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET) +#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET) +#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET) +#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET) +#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET) +#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ +#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ +#define AT91RM9200_PMC_MDIV_2 (1 << 8) +#define AT91RM9200_PMC_MDIV_3 (2 << 8) +#define AT91RM9200_PMC_MDIV_4 (3 << 8) +#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */ +#define AT91SAM9_PMC_MDIV_2 (1 << 8) +#define AT91SAM9_PMC_MDIV_4 (2 << 8) +#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ +#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ +#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ +#define AT91_PMC_PDIV_1 (0 << 12) +#define AT91_PMC_PDIV_2 (1 << 12) +#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ +#define AT91_PMC_PLLADIV2_OFF (0 << 12) +#define AT91_PMC_PLLADIV2_ON (1 << 12) +#define AT91_PMC_H32MXDIV BIT(24) + +#define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */ + +#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ +#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ +#define AT91_PMC_USBS_PLLA (0 << 0) +#define AT91_PMC_USBS_UPLL (1 << 0) +#define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */ +#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ +#define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8) +#define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8) + +#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */ +#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ +#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */ +#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) + +#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ +#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */ +#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */ +#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ +#define AT91_PMC_CSSMCK_CSS (0 << 8) +#define AT91_PMC_CSSMCK_MCK (1 << 8) + +#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */ +#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */ +#define AT91_PMC_SR 0x68 /* Status Register */ +#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ +#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ +#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ +#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ +#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */ +#define AT91_PMC_OSCSEL (1 << 7) /* Slow Oscillator Selection [some SAM9] */ +#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ +#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ +#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ +#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ +#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ +#define AT91_PMC_GCKRDY (1 << 24) /* Generated Clocks */ +#define AT91_PMC_MCKXRDY (1 << 26) /* Master Clock x [x=1..4] Ready Status */ +#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ + +#define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */ +#define AT91_PMC_FSTT(n) BIT(n) +#define AT91_PMC_RTTAL BIT(16) +#define AT91_PMC_RTCAL BIT(17) /* RTC Alarm Enable */ +#define AT91_PMC_USBAL BIT(18) /* USB Resume Enable */ +#define AT91_PMC_SDMMC_CD BIT(19) /* SDMMC Card Detect Enable */ +#define AT91_PMC_LPM BIT(20) /* Low-power Mode */ +#define AT91_PMC_RXLP_MCE BIT(24) /* Backup UART Receive Enable */ +#define AT91_PMC_ACC_CE BIT(25) /* ACC Enable */ + +#define AT91_PMC_FSPR 0x74 /* Fast Startup Polarity Reg */ + +#define AT91_PMC_FS_INPUT_MASK 0x7ff + +#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ + +#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ +#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ +#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ +#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */ + +#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */ +#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ +#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ + +#define AT91_PMC_PLL_ISR0 0xEC /* PLL Interrupt Status Register 0 [SAM9X60 only] */ + +#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ +#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ +#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ + +#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ +#define AT91_PMC_PCR_PID_MASK 0x3f +#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ +#define AT91_PMC_PCR_GCKDIV_MASK GENMASK(27, 20) +#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ +#define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */ + +#define AT91_PMC_AUDIO_PLL0 0x14c +#define AT91_PMC_AUDIO_PLL_PLLEN (1 << 0) +#define AT91_PMC_AUDIO_PLL_PADEN (1 << 1) +#define AT91_PMC_AUDIO_PLL_PMCEN (1 << 2) +#define AT91_PMC_AUDIO_PLL_RESETN (1 << 3) +#define AT91_PMC_AUDIO_PLL_ND_OFFSET 8 +#define AT91_PMC_AUDIO_PLL_ND_MASK (0x7f << AT91_PMC_AUDIO_PLL_ND_OFFSET) +#define AT91_PMC_AUDIO_PLL_ND(n) ((n) << AT91_PMC_AUDIO_PLL_ND_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPMC_OFFSET 16 +#define AT91_PMC_AUDIO_PLL_QDPMC_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPMC(n) ((n) << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) + +#define AT91_PMC_AUDIO_PLL1 0x150 +#define AT91_PMC_AUDIO_PLL_FRACR_MASK 0x3fffff +#define AT91_PMC_AUDIO_PLL_QDPAD_OFFSET 24 +#define AT91_PMC_AUDIO_PLL_QDPAD_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET AT91_PMC_AUDIO_PLL_QDPAD_OFFSET +#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK (0x3 << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_DIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET 26 +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX 0x1f +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK (AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET) + +#endif diff --git a/roms/u-boot/include/linux/compat.h b/roms/u-boot/include/linux/compat.h new file mode 100644 index 000000000..3d0acbd58 --- /dev/null +++ b/roms/u-boot/include/linux/compat.h @@ -0,0 +1,389 @@ +#ifndef _LINUX_COMPAT_H_ +#define _LINUX_COMPAT_H_ + +#include +#include +#include + +#include + +#include +#include +#include + +#ifdef CONFIG_XEN +#include +#endif + +struct unused {}; +typedef struct unused unused_t; + +struct p_current{ + int pid; +}; + +extern struct p_current *current; + +#define GFP_ATOMIC ((gfp_t) 0) +#define GFP_KERNEL ((gfp_t) 0) +#define GFP_NOFS ((gfp_t) 0) +#define GFP_USER ((gfp_t) 0) +#define __GFP_NOWARN ((gfp_t) 0) +#define __GFP_ZERO ((__force gfp_t)0x8000u) /* Return zeroed page on success */ + +void *kmalloc(size_t size, int flags); + +static inline void *kzalloc(size_t size, gfp_t flags) +{ + return kmalloc(size, flags | __GFP_ZERO); +} + +static inline void *kmalloc_array(size_t n, size_t size, gfp_t flags) +{ + if (size != 0 && n > SIZE_MAX / size) + return NULL; + return kmalloc(n * size, flags | __GFP_ZERO); +} + +static inline void *kcalloc(size_t n, size_t size, gfp_t flags) +{ + return kmalloc_array(n, size, flags | __GFP_ZERO); +} + +#define vmalloc(size) kmalloc(size, 0) +#define __vmalloc(size, flags, pgsz) kmalloc(size, flags) +static inline void *vzalloc(unsigned long size) +{ + return kzalloc(size, 0); +} +static inline void kfree(const void *block) +{ + free((void *)block); +} +static inline void vfree(const void *addr) +{ + free((void *)addr); +} + +struct kmem_cache { int sz; }; + +struct kmem_cache *get_mem(int element_sz); +#define kmem_cache_create(a, sz, c, d, e) get_mem(sz) +void *kmem_cache_alloc(struct kmem_cache *obj, int flag); +static inline void kmem_cache_free(struct kmem_cache *cachep, void *obj) +{ + free(obj); +} +static inline void kmem_cache_destroy(struct kmem_cache *cachep) +{ + free(cachep); +} + +#define DECLARE_WAITQUEUE(...) do { } while (0) +#define add_wait_queue(...) do { } while (0) +#define remove_wait_queue(...) do { } while (0) + +#ifndef CONFIG_XEN +#define eventchn_poll() +#endif + +#define __wait_event_timeout(condition, timeout, ret) \ +({ \ + ulong __ret = ret; /* explicit shadow */ \ + ulong start = get_timer(0); \ + for (;;) { \ + eventchn_poll(); \ + if (condition) { \ + __ret = 1; \ + break; \ + } \ + if ((get_timer(start) > timeout) || ctrlc()) { \ + __ret = 0; \ + break; \ + } \ + cpu_relax(); \ + } \ + __ret; \ +}) + +/** + * wait_event_timeout() - Wait until the event occurs before the timeout. + * @wr_head: The wait queue to wait on. + * @condition: Expression for the event to wait for. + * @timeout: Maximum waiting time. + * + * We wait until the @condition evaluates to %true (succeed) or + * %false (@timeout elapsed). + * + * Return: + * 0 - if the @condition evaluated to %false after the @timeout elapsed + * 1 - if the @condition evaluated to %true + */ +#define wait_event_timeout(wq_head, condition, timeout) \ +({ \ + ulong __ret; \ + if (condition) \ + __ret = 1; \ + else \ + __ret = __wait_event_timeout(condition, timeout, __ret);\ + __ret; \ +}) + +#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) + +/* This is also defined in ARMv8's mmu.h */ +#ifndef PAGE_SIZE +#define PAGE_SIZE 4096 +#endif + +/* drivers/char/random.c */ +#define get_random_bytes(...) + +/* include/linux/leds.h */ +struct led_trigger {}; + +#define DEFINE_LED_TRIGGER(x) static struct led_trigger *x; +enum led_brightness { + LED_OFF = 0, + LED_HALF = 127, + LED_FULL = 255, +}; + +static inline void led_trigger_register_simple(const char *name, + struct led_trigger **trigger) {} +static inline void led_trigger_unregister_simple(struct led_trigger *trigger) {} +static inline void led_trigger_event(struct led_trigger *trigger, + enum led_brightness event) {} + +/* uapi/linux/limits.h */ +#define XATTR_LIST_MAX 65536 /* size of extended attribute namelist (64k) */ + +/** + * The type used for indexing onto a disc or disc partition. + * + * Linux always considers sectors to be 512 bytes long independently + * of the devices real block size. + * + * blkcnt_t is the type of the inode's block count. + */ +#ifdef CONFIG_LBDAF +typedef u64 sector_t; +typedef u64 blkcnt_t; +#else +typedef unsigned long sector_t; +typedef unsigned long blkcnt_t; +#endif + +/* module */ +#define THIS_MODULE 0 +#define try_module_get(...) 1 +#define module_put(...) do { } while (0) +#define module_init(...) +#define module_exit(...) +#define EXPORT_SYMBOL(...) +#define EXPORT_SYMBOL_GPL(...) +#define module_param(...) +#define module_param_call(...) +#define MODULE_PARM_DESC(...) +#define MODULE_VERSION(...) +#define MODULE_DESCRIPTION(...) +#define MODULE_AUTHOR(...) +#define MODULE_LICENSE(...) +#define MODULE_ALIAS(...) +#define __module_get(...) + +/* character device */ +#define MKDEV(...) 0 +#define MAJOR(dev) 0 +#define MINOR(dev) 0 + +#define alloc_chrdev_region(...) 0 +#define unregister_chrdev_region(...) + +#define class_create(...) __builtin_return_address(0) +#define class_create_file(...) 0 +#define class_register(...) 0 +#define class_unregister(...) +#define class_remove_file(...) +#define class_destroy(...) +#define misc_register(...) 0 +#define misc_deregister(...) + +#define blocking_notifier_call_chain(...) 0 + +#define __initdata +#define late_initcall(...) + +#define dev_set_name(...) do { } while (0) +#define device_register(...) 0 +#define device_unregister(...) +#define volume_sysfs_init(...) 0 +#define volume_sysfs_close(...) do { } while (0) + +#define init_waitqueue_head(...) do { } while (0) +#define wait_event_interruptible(...) 0 +#define wake_up_interruptible(...) do { } while (0) +#define dump_stack(...) do { } while (0) + +#define task_pid_nr(x) 0 +#define set_freezable(...) do { } while (0) +#define try_to_freeze(...) 0 +#define set_current_state(...) do { } while (0) +#define kthread_should_stop(...) 0 +#define schedule() do { } while (0) + +#define setup_timer(timer, func, data) do {} while (0) +#define del_timer_sync(timer) do {} while (0) +#define schedule_work(work) do {} while (0) +#define INIT_WORK(work, fun) do {} while (0) + +struct work_struct {}; + +unsigned long copy_from_user(void *dest, const void *src, + unsigned long count); + +typedef unused_t spinlock_t; +typedef int wait_queue_head_t; + +#define spin_lock_init(lock) do {} while (0) +#define spin_lock(lock) do {} while (0) +#define spin_unlock(lock) do {} while (0) +#define spin_lock_irqsave(lock, flags) do {} while (0) +#define spin_unlock_irqrestore(lock, flags) do { flags = 0; } while (0) + +#define DEFINE_MUTEX(...) +#define mutex_init(...) +#define mutex_lock(...) +#define mutex_unlock(...) + +#define init_rwsem(...) do { } while (0) +#define down_read(...) do { } while (0) +#define down_write(...) do { } while (0) +#define down_write_trylock(...) 1 +#define up_read(...) do { } while (0) +#define up_write(...) do { } while (0) + +#define cond_resched() do { } while (0) +#define yield() do { } while (0) + +#define __init +#define __exit +#define __devinit +#define __devinitdata +#define __devinitconst + +#define kthread_create(...) __builtin_return_address(0) +#define kthread_stop(...) do { } while (0) +#define wake_up_process(...) do { } while (0) + +struct rw_semaphore { int i; }; +#define down_write(...) do { } while (0) +#define up_write(...) do { } while (0) +#define down_read(...) do { } while (0) +#define up_read(...) do { } while (0) +struct device { + struct device *parent; + struct class *class; + dev_t devt; /* dev_t, creates the sysfs "dev" */ + void (*release)(struct device *dev); + /* This is used from drivers/usb/musb-new subsystem only */ + void *driver_data; /* data private to the driver */ + void *device_data; /* data private to the device */ +}; +struct mutex { int i; }; +struct kernel_param { int i; }; + +struct cdev { + int owner; + dev_t dev; +}; +#define cdev_init(...) do { } while (0) +#define cdev_add(...) 0 +#define cdev_del(...) do { } while (0) + +#define prandom_u32(...) 0 + +typedef struct { + uid_t val; +} kuid_t; + +typedef struct { + gid_t val; +} kgid_t; + +/* from include/linux/types.h */ + +/** + * struct callback_head - callback structure for use with RCU and task_work + * @next: next update requests in a list + * @func: actual update function to call after the grace period. + */ +struct callback_head { + struct callback_head *next; + void (*func)(struct callback_head *head); +}; +#define rcu_head callback_head +enum writeback_sync_modes { + WB_SYNC_NONE, /* Don't wait on anything */ + WB_SYNC_ALL, /* Wait on every mapping */ +}; + +/* from include/linux/writeback.h */ +/* + * A control structure which tells the writeback code what to do. These are + * always on the stack, and hence need no locking. They are always initialised + * in a manner such that unspecified fields are set to zero. + */ +struct writeback_control { + long nr_to_write; /* Write this many pages, and decrement + this for each page written */ + long pages_skipped; /* Pages which were not written */ + + /* + * For a_ops->writepages(): if start or end are non-zero then this is + * a hint that the filesystem need only write out the pages inside that + * byterange. The byte at `end' is included in the writeout request. + */ + loff_t range_start; + loff_t range_end; + + enum writeback_sync_modes sync_mode; + + unsigned for_kupdate:1; /* A kupdate writeback */ + unsigned for_background:1; /* A background writeback */ + unsigned tagged_writepages:1; /* tag-and-write to avoid livelock */ + unsigned for_reclaim:1; /* Invoked from the page allocator */ + unsigned range_cyclic:1; /* range_start is cyclic */ + unsigned for_sync:1; /* sync(2) WB_SYNC_ALL writeback */ +}; + +void *kmemdup(const void *src, size_t len, gfp_t gfp); + +typedef int irqreturn_t; + +struct timer_list {}; +struct notifier_block {}; + +typedef unsigned long dmaaddr_t; + +#define pm_runtime_get_sync(dev) do {} while (0) +#define pm_runtime_put(dev) do {} while (0) +#define pm_runtime_put_sync(dev) do {} while (0) +#define pm_runtime_use_autosuspend(dev) do {} while (0) +#define pm_runtime_set_autosuspend_delay(dev, delay) do {} while (0) +#define pm_runtime_enable(dev) do {} while (0) + +#define IRQ_NONE 0 +#define IRQ_HANDLED 1 +#define IRQ_WAKE_THREAD 2 + +#define dev_set_drvdata(dev, data) do {} while (0) + +#define enable_irq(...) +#define disable_irq(...) +#define disable_irq_wake(irq) do {} while (0) +#define enable_irq_wake(irq) -EINVAL +#define free_irq(irq, data) do {} while (0) +#define request_irq(nr, f, flags, nm, data) 0 + +#endif diff --git a/roms/u-boot/include/linux/compiler-clang.h b/roms/u-boot/include/linux/compiler-clang.h new file mode 100644 index 000000000..333a6695a --- /dev/null +++ b/roms/u-boot/include/linux/compiler-clang.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_COMPILER_TYPES_H +#error "Please don't include directly, include instead." +#endif + +/* Compiler specific definitions for Clang compiler */ + +#define uninitialized_var(x) x = *(&(x)) + +/* same as gcc, this was present in clang-2.6 so we can assume it works + * with any version that can compile the kernel + */ +#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) + +/* all clang versions usable with the kernel support KASAN ABI version 5 */ +#define KASAN_ABI_VERSION 5 + +#if __has_feature(address_sanitizer) || __has_feature(hwaddress_sanitizer) +/* emulate gcc's __SANITIZE_ADDRESS__ flag */ +#define __SANITIZE_ADDRESS__ +#define __no_sanitize_address \ + __attribute__((no_sanitize("address", "hwaddress"))) +#else +#define __no_sanitize_address +#endif + +/* + * Not all versions of clang implement the the type-generic versions + * of the builtin overflow checkers. Fortunately, clang implements + * __has_builtin allowing us to avoid awkward version + * checks. Unfortunately, we don't know which version of gcc clang + * pretends to be, so the macro may or may not be defined. + */ +#if __has_builtin(__builtin_mul_overflow) && \ + __has_builtin(__builtin_add_overflow) && \ + __has_builtin(__builtin_sub_overflow) +#define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1 +#endif + +/* The following are for compatibility with GCC, from compiler-gcc.h, + * and may be redefined here because they should not be shared with other + * compilers, like ICC. + */ +#define barrier() __asm__ __volatile__("" : : : "memory") diff --git a/roms/u-boot/include/linux/compiler-gcc.h b/roms/u-boot/include/linux/compiler-gcc.h new file mode 100644 index 000000000..d7ee4c6ba --- /dev/null +++ b/roms/u-boot/include/linux/compiler-gcc.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_COMPILER_TYPES_H +#error "Please don't include directly, include instead." +#endif + +/* + * Common definitions for all gcc versions go here. + */ +#define GCC_VERSION (__GNUC__ * 10000 \ + + __GNUC_MINOR__ * 100 \ + + __GNUC_PATCHLEVEL__) + +#if GCC_VERSION < 40600 +# error Sorry, your compiler is too old - please upgrade it. +#endif + +/* Optimization barrier */ + +/* The "volatile" is due to gcc bugs */ +#define barrier() __asm__ __volatile__("": : :"memory") +/* + * This version is i.e. to prevent dead stores elimination on @ptr + * where gcc and llvm may behave differently when otherwise using + * normal barrier(): while gcc behavior gets along with a normal + * barrier(), llvm needs an explicit input variable to be assumed + * clobbered. The issue is as follows: while the inline asm might + * access any memory it wants, the compiler could have fit all of + * @ptr into memory registers instead, and since @ptr never escaped + * from that, it proved that the inline asm wasn't touching any of + * it. This version works well with both compilers, i.e. we're telling + * the compiler that the inline asm absolutely may see the contents + * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495 + */ +#define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory") + +/* + * This macro obfuscates arithmetic on a variable address so that gcc + * shouldn't recognize the original var, and make assumptions about it. + * + * This is needed because the C standard makes it undefined to do + * pointer arithmetic on "objects" outside their boundaries and the + * gcc optimizers assume this is the case. In particular they + * assume such arithmetic does not wrap. + * + * A miscompilation has been observed because of this on PPC. + * To work around it we hide the relationship of the pointer and the object + * using this macro. + * + * Versions of the ppc64 compiler before 4.1 had a bug where use of + * RELOC_HIDE could trash r30. The bug can be worked around by changing + * the inline assembly constraint from =g to =r, in this particular + * case either is valid. + */ +#define RELOC_HIDE(ptr, off) \ +({ \ + unsigned long __ptr; \ + __asm__ ("" : "=r"(__ptr) : "0"(ptr)); \ + (typeof(ptr)) (__ptr + (off)); \ +}) + +/* + * A trick to suppress uninitialized variable warning without generating any + * code + */ +#define uninitialized_var(x) x = x + +#ifdef CONFIG_RETPOLINE +#define __noretpoline __attribute__((__indirect_branch__("keep"))) +#endif + +#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) + +#define __compiletime_object_size(obj) __builtin_object_size(obj, 0) + +#define __compiletime_warning(message) __attribute__((__warning__(message))) +#define __compiletime_error(message) __attribute__((__error__(message))) + +#if defined(LATENT_ENTROPY_PLUGIN) && !defined(__CHECKER__) +#define __latent_entropy __attribute__((latent_entropy)) +#endif + +/* + * calling noreturn functions, __builtin_unreachable() and __builtin_trap() + * confuse the stack allocation in gcc, leading to overly large stack + * frames, see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82365 + * + * Adding an empty inline assembly before it works around the problem + */ +#define barrier_before_unreachable() asm volatile("") + +/* + * Mark a position in code as unreachable. This can be used to + * suppress control flow warnings after asm blocks that transfer + * control elsewhere. + */ +#define unreachable() \ + do { \ + annotate_unreachable(); \ + barrier_before_unreachable(); \ + __builtin_unreachable(); \ + } while (0) + +#if defined(RANDSTRUCT_PLUGIN) && !defined(__CHECKER__) +#define __randomize_layout __attribute__((randomize_layout)) +#define __no_randomize_layout __attribute__((no_randomize_layout)) +/* This anon struct can add padding, so only enable it under randstruct. */ +#define randomized_struct_fields_start struct { +#define randomized_struct_fields_end } __randomize_layout; +#endif + +/* + * GCC 'asm goto' miscompiles certain code sequences: + * + * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670 + * + * Work it around via a compiler barrier quirk suggested by Jakub Jelinek. + * + * (asm goto is automatically volatile - the naming reflects this.) + */ +#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0) + +/* + * sparse (__CHECKER__) pretends to be gcc, but can't do constant + * folding in __builtin_bswap*() (yet), so don't set these for it. + */ +#if defined(CONFIG_ARCH_USE_BUILTIN_BSWAP) && !defined(__CHECKER__) +#define __HAVE_BUILTIN_BSWAP32__ +#define __HAVE_BUILTIN_BSWAP64__ +#if GCC_VERSION >= 40800 +#define __HAVE_BUILTIN_BSWAP16__ +#endif +#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP && !__CHECKER__ */ + +#if GCC_VERSION >= 70000 +#define KASAN_ABI_VERSION 5 +#elif GCC_VERSION >= 50000 +#define KASAN_ABI_VERSION 4 +#elif GCC_VERSION >= 40902 +#define KASAN_ABI_VERSION 3 +#endif + +#if __has_attribute(__no_sanitize_address__) +#define __no_sanitize_address __attribute__((no_sanitize_address)) +#else +#define __no_sanitize_address +#endif + +#if GCC_VERSION >= 50100 +#define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1 +#endif + +/* + * Turn individual warnings and errors on and off locally, depending + * on version. + */ +#define __diag_GCC(version, severity, s) \ + __diag_GCC_ ## version(__diag_GCC_ ## severity s) + +/* Severity used in pragma directives */ +#define __diag_GCC_ignore ignored +#define __diag_GCC_warn warning +#define __diag_GCC_error error + +#define __diag_str1(s) #s +#define __diag_str(s) __diag_str1(s) +#define __diag(s) _Pragma(__diag_str(GCC diagnostic s)) + +#if GCC_VERSION >= 80000 +#define __diag_GCC_8(s) __diag(s) +#else +#define __diag_GCC_8(s) +#endif + +#define __no_fgcse __attribute__((optimize("-fno-gcse"))) diff --git a/roms/u-boot/include/linux/compiler-intel.h b/roms/u-boot/include/linux/compiler-intel.h new file mode 100644 index 000000000..b17f3cd18 --- /dev/null +++ b/roms/u-boot/include/linux/compiler-intel.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_COMPILER_TYPES_H +#error "Please don't include directly, include instead." +#endif + +#ifdef __ECC + +/* Compiler specific definitions for Intel ECC compiler */ + +#include + +/* Intel ECC compiler doesn't support gcc specific asm stmts. + * It uses intrinsics to do the equivalent things. + */ + +#define barrier() __memory_barrier() +#define barrier_data(ptr) barrier() + +#define RELOC_HIDE(ptr, off) \ + ({ unsigned long __ptr; \ + __ptr = (unsigned long) (ptr); \ + (typeof(ptr)) (__ptr + (off)); }) + +/* This should act as an optimization barrier on var. + * Given that this compiler does not have inline assembly, a compiler barrier + * is the best we can do. + */ +#define OPTIMIZER_HIDE_VAR(var) barrier() + +#endif + +/* icc has this, but it's called _bswap16 */ +#define __HAVE_BUILTIN_BSWAP16__ +#define __builtin_bswap16 _bswap16 diff --git a/roms/u-boot/include/linux/compiler.h b/roms/u-boot/include/linux/compiler.h new file mode 100644 index 000000000..98dd3fc4c --- /dev/null +++ b/roms/u-boot/include/linux/compiler.h @@ -0,0 +1,355 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_COMPILER_H +#define __LINUX_COMPILER_H + +#include + +#ifndef __ASSEMBLY__ + +#ifdef __KERNEL__ + +/* + * Note: DISABLE_BRANCH_PROFILING can be used by special lowlevel code + * to disable branch tracing on a per file basis. + */ +#if defined(CONFIG_TRACE_BRANCH_PROFILING) \ + && !defined(DISABLE_BRANCH_PROFILING) && !defined(__CHECKER__) +void ftrace_likely_update(struct ftrace_likely_data *f, int val, + int expect, int is_constant); + +#define likely_notrace(x) __builtin_expect(!!(x), 1) +#define unlikely_notrace(x) __builtin_expect(!!(x), 0) + +#define __branch_check__(x, expect, is_constant) ({ \ + long ______r; \ + static struct ftrace_likely_data \ + __aligned(4) \ + __section("_ftrace_annotated_branch") \ + ______f = { \ + .data.func = __func__, \ + .data.file = __FILE__, \ + .data.line = __LINE__, \ + }; \ + ______r = __builtin_expect(!!(x), expect); \ + ftrace_likely_update(&______f, ______r, \ + expect, is_constant); \ + ______r; \ + }) + +/* + * Using __builtin_constant_p(x) to ignore cases where the return + * value is always the same. This idea is taken from a similar patch + * written by Daniel Walker. + */ +# ifndef likely +# define likely(x) (__branch_check__(x, 1, __builtin_constant_p(x))) +# endif +# ifndef unlikely +# define unlikely(x) (__branch_check__(x, 0, __builtin_constant_p(x))) +# endif + +#ifdef CONFIG_PROFILE_ALL_BRANCHES +/* + * "Define 'is'", Bill Clinton + * "Define 'if'", Steven Rostedt + */ +#define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) ) + +#define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond)) + +#define __trace_if_value(cond) ({ \ + static struct ftrace_branch_data \ + __aligned(4) \ + __section("_ftrace_branch") \ + __if_trace = { \ + .func = __func__, \ + .file = __FILE__, \ + .line = __LINE__, \ + }; \ + (cond) ? \ + (__if_trace.miss_hit[1]++,1) : \ + (__if_trace.miss_hit[0]++,0); \ +}) + +#endif /* CONFIG_PROFILE_ALL_BRANCHES */ + +#else +# define likely(x) __builtin_expect(!!(x), 1) +# define unlikely(x) __builtin_expect(!!(x), 0) +#endif + +/* Optimization barrier */ +#ifndef barrier +# define barrier() __memory_barrier() +#endif + +#ifndef barrier_data +# define barrier_data(ptr) barrier() +#endif + +/* workaround for GCC PR82365 if needed */ +#ifndef barrier_before_unreachable +# define barrier_before_unreachable() do { } while (0) +#endif + +/* Unreachable code */ +#ifdef CONFIG_STACK_VALIDATION +/* + * These macros help objtool understand GCC code flow for unreachable code. + * The __COUNTER__ based labels are a hack to make each instance of the macros + * unique, to convince GCC not to merge duplicate inline asm statements. + */ +#define annotate_reachable() ({ \ + asm volatile("%c0:\n\t" \ + ".pushsection .discard.reachable\n\t" \ + ".long %c0b - .\n\t" \ + ".popsection\n\t" : : "i" (__COUNTER__)); \ +}) +#define annotate_unreachable() ({ \ + asm volatile("%c0:\n\t" \ + ".pushsection .discard.unreachable\n\t" \ + ".long %c0b - .\n\t" \ + ".popsection\n\t" : : "i" (__COUNTER__)); \ +}) +#define ASM_UNREACHABLE \ + "999:\n\t" \ + ".pushsection .discard.unreachable\n\t" \ + ".long 999b - .\n\t" \ + ".popsection\n\t" + +/* Annotate a C jump table to allow objtool to follow the code flow */ +#define __annotate_jump_table __section(".rodata..c_jump_table") + +#else +#define annotate_reachable() +#define annotate_unreachable() +#define __annotate_jump_table +#endif + +#ifndef ASM_UNREACHABLE +# define ASM_UNREACHABLE +#endif +#ifndef unreachable +# define unreachable() do { \ + annotate_unreachable(); \ + __builtin_unreachable(); \ +} while (0) +#endif + +/* + * KENTRY - kernel entry point + * This can be used to annotate symbols (functions or data) that are used + * without their linker symbol being referenced explicitly. For example, + * interrupt vector handlers, or functions in the kernel image that are found + * programatically. + * + * Not required for symbols exported with EXPORT_SYMBOL, or initcalls. Those + * are handled in their own way (with KEEP() in linker scripts). + * + * KENTRY can be avoided if the symbols in question are marked as KEEP() in the + * linker script. For example an architecture could KEEP() its entire + * boot/exception vector code rather than annotate each function and data. + */ +#ifndef KENTRY +# define KENTRY(sym) \ + extern typeof(sym) sym; \ + static const unsigned long __kentry_##sym \ + __used \ + __section("___kentry" "+" #sym ) \ + = (unsigned long)&sym; +#endif + +#ifndef RELOC_HIDE +# define RELOC_HIDE(ptr, off) \ + ({ unsigned long __ptr; \ + __ptr = (unsigned long) (ptr); \ + (typeof(ptr)) (__ptr + (off)); }) +#endif + +#ifndef OPTIMIZER_HIDE_VAR +/* Make the optimizer believe the variable can be manipulated arbitrarily. */ +#define OPTIMIZER_HIDE_VAR(var) \ + __asm__ ("" : "=r" (var) : "0" (var)) +#endif + +/* Not-quite-unique ID. */ +#ifndef __UNIQUE_ID +# define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __LINE__) +#endif + +#include + +#define __READ_ONCE_SIZE \ +({ \ + switch (size) { \ + case 1: *(__u8 *)res = *(volatile __u8 *)p; break; \ + case 2: *(__u16 *)res = *(volatile __u16 *)p; break; \ + case 4: *(__u32 *)res = *(volatile __u32 *)p; break; \ + case 8: *(__u64 *)res = *(volatile __u64 *)p; break; \ + default: \ + barrier(); \ + __builtin_memcpy((void *)res, (const void *)p, size); \ + barrier(); \ + } \ +}) + +static __always_inline +void __read_once_size(const volatile void *p, void *res, int size) +{ + __READ_ONCE_SIZE; +} + +#ifdef CONFIG_KASAN +/* + * We can't declare function 'inline' because __no_sanitize_address confilcts + * with inlining. Attempt to inline it may cause a build failure. + * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368 + * '__maybe_unused' allows us to avoid defined-but-not-used warnings. + */ +# define __no_kasan_or_inline __no_sanitize_address notrace __maybe_unused +#else +# define __no_kasan_or_inline __always_inline +#endif + +static __no_kasan_or_inline +void __read_once_size_nocheck(const volatile void *p, void *res, int size) +{ + __READ_ONCE_SIZE; +} + +static __always_inline void __write_once_size(volatile void *p, void *res, int size) +{ + switch (size) { + case 1: *(volatile __u8 *)p = *(__u8 *)res; break; + case 2: *(volatile __u16 *)p = *(__u16 *)res; break; + case 4: *(volatile __u32 *)p = *(__u32 *)res; break; + case 8: *(volatile __u64 *)p = *(__u64 *)res; break; + default: + barrier(); + __builtin_memcpy((void *)p, (const void *)res, size); + barrier(); + } +} + +/* + * Prevent the compiler from merging or refetching reads or writes. The + * compiler is also forbidden from reordering successive instances of + * READ_ONCE and WRITE_ONCE, but only when the compiler is aware of some + * particular ordering. One way to make the compiler aware of ordering is to + * put the two invocations of READ_ONCE or WRITE_ONCE in different C + * statements. + * + * These two macros will also work on aggregate data types like structs or + * unions. If the size of the accessed data type exceeds the word size of + * the machine (e.g., 32 bits or 64 bits) READ_ONCE() and WRITE_ONCE() will + * fall back to memcpy(). There's at least two memcpy()s: one for the + * __builtin_memcpy() and then one for the macro doing the copy of variable + * - '__u' allocated on the stack. + * + * Their two major use cases are: (1) Mediating communication between + * process-level code and irq/NMI handlers, all running on the same CPU, + * and (2) Ensuring that the compiler does not fold, spindle, or otherwise + * mutilate accesses that either do not require ordering or that interact + * with an explicit memory barrier or atomic instruction that provides the + * required ordering. + */ + +#define __READ_ONCE(x, check) \ +({ \ + union { typeof(x) __val; char __c[1]; } __u; \ + if (check) \ + __read_once_size(&(x), __u.__c, sizeof(x)); \ + else \ + __read_once_size_nocheck(&(x), __u.__c, sizeof(x)); \ + __u.__val; \ +}) +#define READ_ONCE(x) __READ_ONCE(x, 1) + +/* + * Use READ_ONCE_NOCHECK() instead of READ_ONCE() if you need + * to hide memory access from KASAN. + */ +#define READ_ONCE_NOCHECK(x) __READ_ONCE(x, 0) + +static __no_kasan_or_inline +unsigned long read_word_at_a_time(const void *addr) +{ + return *(unsigned long *)addr; +} + +#define WRITE_ONCE(x, val) \ +({ \ + union { typeof(x) __val; char __c[1]; } __u = \ + { .__val = (__force typeof(x)) (val) }; \ + __write_once_size(&(x), __u.__c, sizeof(x)); \ + __u.__val; \ +}) + +#endif /* __KERNEL__ */ + +/* + * Force the compiler to emit 'sym' as a symbol, so that we can reference + * it from inline assembler. Necessary in case 'sym' could be inlined + * otherwise, or eliminated entirely due to lack of references that are + * visible to the compiler. + */ +#define __ADDRESSABLE(sym) \ + static void * __section(".discard.addressable") __used \ + __UNIQUE_ID(__PASTE(__addressable_,sym)) = (void *)&sym; + +/** + * offset_to_ptr - convert a relative memory offset to an absolute pointer + * @off: the address of the 32-bit offset value + */ +static inline void *offset_to_ptr(const int *off) +{ + return (void *)((unsigned long)off + *off); +} + +#endif /* __ASSEMBLY__ */ + +/* Compile time object size, -1 for unknown */ +#ifndef __compiletime_object_size +# define __compiletime_object_size(obj) -1 +#endif +#ifndef __compiletime_warning +# define __compiletime_warning(message) +#endif +#ifndef __compiletime_error +# define __compiletime_error(message) +#endif + +#ifdef __OPTIMIZE__ +# define __compiletime_assert(condition, msg, prefix, suffix) \ + do { \ + extern void prefix ## suffix(void) __compiletime_error(msg); \ + if (!(condition)) \ + prefix ## suffix(); \ + } while (0) +#else +# define __compiletime_assert(condition, msg, prefix, suffix) do { } while (0) +#endif + +#define _compiletime_assert(condition, msg, prefix, suffix) \ + __compiletime_assert(condition, msg, prefix, suffix) + +/** + * compiletime_assert - break build and emit msg if condition is false + * @condition: a compile-time constant condition to check + * @msg: a message to emit if condition is false + * + * In tradition of POSIX assert, this macro will break the build if the + * supplied condition is *false*, emitting the supplied error message if the + * compiler has support to do so. + */ +#define compiletime_assert(condition, msg) \ + _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) + +#define compiletime_assert_atomic_type(t) \ + compiletime_assert(__native_word(t), \ + "Need native word sized stores/loads for atomicity.") + +/* &a[0] degrades to a pointer: a different type from an array */ +#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0])) + +#endif /* __LINUX_COMPILER_H */ diff --git a/roms/u-boot/include/linux/compiler_attributes.h b/roms/u-boot/include/linux/compiler_attributes.h new file mode 100644 index 000000000..44c9a08d7 --- /dev/null +++ b/roms/u-boot/include/linux/compiler_attributes.h @@ -0,0 +1,273 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_COMPILER_ATTRIBUTES_H +#define __LINUX_COMPILER_ATTRIBUTES_H + +/* + * The attributes in this file are unconditionally defined and they directly + * map to compiler attribute(s), unless one of the compilers does not support + * the attribute. In that case, __has_attribute is used to check for support + * and the reason is stated in its comment ("Optional: ..."). + * + * Any other "attributes" (i.e. those that depend on a configuration option, + * on a compiler, on an architecture, on plugins, on other attributes...) + * should be defined elsewhere (e.g. compiler_types.h or compiler-*.h). + * The intention is to keep this file as simple as possible, as well as + * compiler- and version-agnostic (e.g. avoiding GCC_VERSION checks). + * + * This file is meant to be sorted (by actual attribute name, + * not by #define identifier). Use the __attribute__((__name__)) syntax + * (i.e. with underscores) to avoid future collisions with other macros. + * Provide links to the documentation of each supported compiler, if it exists. + */ + +/* + * __has_attribute is supported on gcc >= 5, clang >= 2.9 and icc >= 17. + * In the meantime, to support 4.6 <= gcc < 5, we implement __has_attribute + * by hand. + * + * sparse does not support __has_attribute (yet) and defines __GNUC_MINOR__ + * depending on the compiler used to build it; however, these attributes have + * no semantic effects for sparse, so it does not matter. Also note that, + * in order to avoid sparse's warnings, even the unsupported ones must be + * defined to 0. + */ +#ifndef __has_attribute +# define __has_attribute(x) __GCC4_has_attribute_##x +# define __GCC4_has_attribute___assume_aligned__ (__GNUC_MINOR__ >= 9) +# define __GCC4_has_attribute___copy__ 0 +# define __GCC4_has_attribute___designated_init__ 0 +# define __GCC4_has_attribute___externally_visible__ 1 +# define __GCC4_has_attribute___noclone__ 1 +# define __GCC4_has_attribute___nonstring__ 0 +# define __GCC4_has_attribute___no_sanitize_address__ (__GNUC_MINOR__ >= 8) +# define __GCC4_has_attribute___fallthrough__ 0 +#endif + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-alias-function-attribute + */ +#define __alias(symbol) __attribute__((__alias__(#symbol))) + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-aligned-function-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-aligned-type-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-aligned-variable-attribute + */ +#define __aligned(x) __attribute__((__aligned__(x))) +#define __aligned_largest __attribute__((__aligned__)) + +/* + * Note: users of __always_inline currently do not write "inline" themselves, + * which seems to be required by gcc to apply the attribute according + * to its docs (and also "warning: always_inline function might not be + * inlinable [-Wattributes]" is emitted). + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-always_005finline-function-attribute + * clang: mentioned + */ +#define __always_inline inline __attribute__((__always_inline__)) + +/* + * The second argument is optional (default 0), so we use a variadic macro + * to make the shorthand. + * + * Beware: Do not apply this to functions which may return + * ERR_PTRs. Also, it is probably unwise to apply it to functions + * returning extra information in the low bits (but in that case the + * compiler should see some alignment anyway, when the return value is + * massaged by 'flags = ptr & 3; ptr &= ~3;'). + * + * Optional: only supported since gcc >= 4.9 + * Optional: not supported by icc + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-assume_005faligned-function-attribute + * clang: https://clang.llvm.org/docs/AttributeReference.html#assume-aligned + */ +#if __has_attribute(__assume_aligned__) +# define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__))) +#else +# define __assume_aligned(a, ...) +#endif + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-cold-function-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Label-Attributes.html#index-cold-label-attribute + */ +#define __cold __attribute__((__cold__)) + +/* + * Note the long name. + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-const-function-attribute + */ +#define __attribute_const__ __attribute__((__const__)) + +/* + * Optional: only supported since gcc >= 9 + * Optional: not supported by clang + * Optional: not supported by icc + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-copy-function-attribute + */ +#if __has_attribute(__copy__) +# define __copy(symbol) __attribute__((__copy__(symbol))) +#else +# define __copy(symbol) +#endif + +/* + * Don't. Just don't. See commit 771c035372a0 ("deprecate the '__deprecated' + * attribute warnings entirely and for good") for more information. + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-deprecated-function-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-deprecated-type-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-deprecated-variable-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Enumerator-Attributes.html#index-deprecated-enumerator-attribute + * clang: https://clang.llvm.org/docs/AttributeReference.html#deprecated + */ +#define __deprecated + +/* + * Optional: only supported since gcc >= 5.1 + * Optional: not supported by clang + * Optional: not supported by icc + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-designated_005finit-type-attribute + */ +#if __has_attribute(__designated_init__) +# define __designated_init __attribute__((__designated_init__)) +#else +# define __designated_init +#endif + +/* + * Optional: not supported by clang + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-externally_005fvisible-function-attribute + */ +#if __has_attribute(__externally_visible__) +# define __visible __attribute__((__externally_visible__)) +#else +# define __visible +#endif + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-format-function-attribute + * clang: https://clang.llvm.org/docs/AttributeReference.html#format + */ +#define __printf(a, b) __attribute__((__format__(printf, a, b))) +#define __scanf(a, b) __attribute__((__format__(scanf, a, b))) + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-gnu_005finline-function-attribute + * clang: https://clang.llvm.org/docs/AttributeReference.html#gnu-inline + */ +#define __gnu_inline __attribute__((__gnu_inline__)) + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-malloc-function-attribute + */ +#define __malloc __attribute__((__malloc__)) + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-mode-type-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-mode-variable-attribute + */ +#define __mode(x) __attribute__((__mode__(x))) + +/* + * Optional: not supported by clang + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-noclone-function-attribute + */ +#if __has_attribute(__noclone__) +# define __noclone __attribute__((__noclone__)) +#else +# define __noclone +#endif + +/* + * Add the pseudo keyword 'fallthrough' so case statement blocks + * must end with any of these keywords: + * break; + * fallthrough; + * goto