From 1c7d6584a7811b7785ae5c1e378f14b5ba0971cf Mon Sep 17 00:00:00 2001 From: takeshi_hoshina Date: Mon, 2 Nov 2020 11:07:33 +0900 Subject: basesystem-jj recipes --- ...rm64-dts-renesas-add-V3H-GMSL2-Videoboxes.patch | 1445 ++++++++++++++++++++ 1 file changed, 1445 insertions(+) create mode 100644 bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0500-arm64-dts-renesas-add-V3H-GMSL2-Videoboxes.patch (limited to 'bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0500-arm64-dts-renesas-add-V3H-GMSL2-Videoboxes.patch') diff --git a/bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0500-arm64-dts-renesas-add-V3H-GMSL2-Videoboxes.patch b/bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0500-arm64-dts-renesas-add-V3H-GMSL2-Videoboxes.patch new file mode 100644 index 00000000..4e58b2d8 --- /dev/null +++ b/bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0500-arm64-dts-renesas-add-V3H-GMSL2-Videoboxes.patch @@ -0,0 +1,1445 @@ +From bcba64742b957d8a6f7303abf05c4e586522c89b Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov +Date: Mon, 27 Apr 2020 18:53:42 +0300 +Subject: [PATCH] arm64: dts: renesas: add V3H GMSL2 Videoboxes + +This adds Quad and Dual GMSL Videoboxes on V3H + +Signed-off-by: Andrey Gusakov +Signed-off-by: Vladimir Barinov +--- + arch/arm64/boot/dts/renesas/Makefile | 2 + + .../dts/renesas/r8a77980-v3hsk-vb-gmsl2-2x2.dts | 717 +++++++++++++++++++++ + .../boot/dts/renesas/r8a77980-v3hsk-vb-gmsl2-4.dts | 683 ++++++++++++++++++++ + 3 files changed, 1402 insertions(+) + create mode 100644 arch/arm64/boot/dts/renesas/r8a77980-v3hsk-vb-gmsl2-2x2.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a77980-v3hsk-vb-gmsl2-4.dts + +diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile +index 89da50c..a1373ba 100644 +--- a/arch/arm64/boot/dts/renesas/Makefile ++++ b/arch/arm64/boot/dts/renesas/Makefile +@@ -43,6 +43,8 @@ dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk-vbm-v3.dtb + dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk-vbm-v2.dtb + dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk-vbm-v3.dtb + dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk-vb-8ch.dtb r8a77980-v3hsk-vb-4ch.dtb ++dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk-vb-gmsl2-2x2.dtb ++dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk-vb-gmsl2-4.dtb + dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk-vb-gmsl-8ch.dtb + dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk-vb-4ch-hdmi.dtb r8a77980-v3hsk-vb-8ch-hdmi.dtb + +diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk-vb-gmsl2-2x2.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk-vb-gmsl2-2x2.dts +new file mode 100644 +index 0000000..155b73f +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk-vb-gmsl2-2x2.dts +@@ -0,0 +1,717 @@ ++/* ++ * Device Tree Source for the V3HSK Videobox Mini board on r8a7798 ++ * ++ * Copyright (C) 2018 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a77980-v3hsk.dts" ++#include ++/* FDPLink output */ ++//#include "vb-fdplink-output.dtsi" ++ ++#define COMPATIBLE_CAMERAS \ ++"onsemi,ar0140", \ ++"onsemi,ar0143", \ ++"onsemi,ar0147", \ ++"onsemi,ar0231", \ ++"onsemi,ar0233", \ ++"onsemi,ap0101", \ ++"onsemi,ap0201", \ ++"ovti,ov10635", \ ++"ovti,ov10640", \ ++"ovti,ov2311", \ ++"ovti,ov2775", \ ++"ovti,ov490", \ ++"ovti,ov495", \ ++"ovti,ox01d10", \ ++"ovti,ox03a", \ ++"sony,imx390", \ ++"sony,isx016", \ ++"sony,isx019", \ ++"dummy,camera" ++ ++/ { ++ model = "Renesas V3HSK 2x2ch GMSL2 Videobox board based on r8a7798"; ++ ++ aliases { ++ serial1 = &scif3; ++ ethernet1 = &avb; ++ }; ++ ++ cs2300_ref_clk: cs2300_ref_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <25000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led0 { ++ label = "board:status"; ++ gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "none"; ++ }; ++ }; ++ ++ mpcie_1v8: regulator2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "mPCIe 1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ mpcie_3v3: regulator3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "mPCIe 3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ common_3v3: regulator4 { ++ compatible = "regulator-fixed"; ++ regulator-name = "main 3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ regulator_poc_0: regulator-poc-0 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "POC 0"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ startup-delay-us = <50>; ++ ++ gpio = <&gpio_exp_ch0 10 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ regulator_poc_1: regulator-poc-1 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "POC 1"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ startup-delay-us = <50>; ++ ++ gpio = <&gpio_exp_ch0 11 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ regulator_poc_2: regulator-poc-2 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "POC 2"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ startup-delay-us = <50>; ++ ++ gpio = <&gpio_exp_ch0 14 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ regulator_poc_3: regulator-poc-3 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "POC 3"; ++ regulator-min-microvolt = <9000000>; ++ regulator-max-microvolt = <9000000>; ++ startup-delay-us = <50>; ++ ++ gpio = <&gpio_exp_ch0 15 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++}; ++ ++&canfd { ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ channel0 { ++ status = "okay"; ++ }; ++ ++ channel1 { ++ status = "okay"; ++ }; ++}; ++ ++&avb { ++ pinctrl-0 = <&avb_pins>; ++ pinctrl-names = "default"; ++ renesas,no-ether-link; ++ phy-handle = <&avb_phy0>; ++ status = "okay"; ++ phy-int-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; ++ ++ avb_phy0: eavb-phy@0 { ++ rxc-skew-ps = <1500>; ++ rxdv-skew-ps = <420>; /* default */ ++ rxd0-skew-ps = <420>; /* default */ ++ rxd1-skew-ps = <420>; /* default */ ++ rxd2-skew-ps = <420>; /* default */ ++ rxd3-skew-ps = <420>; /* default */ ++ txc-skew-ps = <900>; /* default */ ++ txen-skew-ps = <420>; /* default */ ++ txd0-skew-ps = <420>; /* default */ ++ txd1-skew-ps = <420>; /* default */ ++ txd2-skew-ps = <420>; /* default */ ++ txd3-skew-ps = <420>; /* default */ ++ reg = <3>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <17 IRQ_TYPE_LEVEL_LOW>; ++ max-speed = <1000>; ++ }; ++}; ++ ++&csi40 { ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <1200>; ++ }; ++ }; ++}; ++ ++&csi41 { ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi41_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <1200>; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ pinctrl-0 = <&i2c1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ clock-frequency = <400000>; ++ ++ i2cswitch1: i2c-switch@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; ++ ++ /* CCTRL_SDA and CCTRL_SCL */ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ gpio_exp_ch0: gpio_ch0@76 { ++ compatible = "nxp,pca9539"; ++ reg = <0x76>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ cmr_pwr_en { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CmrPEn"; ++ }; ++ }; ++ ++ /* CS2300 node @0x4e */ ++ cs2300: clk_multiplier@4e { ++ #clock-cells = <0>; ++ compatible = "cirrus,cs2300-cp"; ++ reg = <0x4e>; ++ clocks = <&cs2300_ref_clk>; ++ clock-names = "clk_in"; ++ ++ assigned-clocks = <&cs2300>; ++ assigned-clock-rates = <25000000>; ++ }; ++ ++ dac_vcam: dac_vcam@60 { ++ compatible = "microchip,mcp4725"; ++ reg = <0x60>; ++ vdd-supply = <&common_3v3>; ++ }; ++ }; ++ ++ /* DS0_SDA and DS0_SCL */ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ ++ max9296@48 { ++ compatible = "maxim,max9296"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x48>; ++ clocks = <&cs2300>; ++ clock-names = "ref_clk"; ++ shutdown-gpios = <&gpio_exp_ch0 1 GPIO_ACTIVE_LOW>; ++ ++ maxim,link-mipi-map = <1 1>; ++ ++ poc0-supply = <®ulator_poc_0>; ++ poc1-supply = <®ulator_poc_1>; ++ ++ port@0 { ++ max9296_des0ep0: endpoint@0 { ++ ser-addr = <0x0c>; ++ remote-endpoint = <&camera_in0>; ++ }; ++ max9296_des0ep1: endpoint@1 { ++ ser-addr = <0x0d>; ++ remote-endpoint = <&camera_in1>; ++ }; ++ }; ++ ++ port@1 { ++ max9296_des0mipi1: endpoint { ++ csi-rate = <1200>; ++ remote-endpoint = <&csi40_ep>; ++ }; ++ }; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ camera@60 { ++ compatible = COMPATIBLE_CAMERAS; ++ reg = <0x60 0x0c>; ++ ++ port@0 { ++ camera_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ camera_max9296_des0ep0: endpoint@1 { ++ remote-endpoint = <&max9296_des0ep0>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ ++ camera@61 { ++ compatible = COMPATIBLE_CAMERAS; ++ reg = <0x61 0x0d>; ++ ++ port@0 { ++ camera_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ camera_max9296_des0ep1: endpoint@1 { ++ remote-endpoint = <&max9296_des0ep1>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ /* DS1_SDA and DS1_SCL */ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ ++ max9296@48 { ++ compatible = "maxim,max9296"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x48>; ++ clocks = <&cs2300>; ++ clock-names = "ref_clk"; ++ shutdown-gpios = <&gpio_exp_ch0 0 GPIO_ACTIVE_LOW>; ++ ++ maxim,link-mipi-map = <1 1>; ++ ++ poc0-supply = <®ulator_poc_2>; ++ poc1-supply = <®ulator_poc_3>; ++ ++ port@0 { ++ max9296_des1ep0: endpoint@0 { ++ ser-addr = <0x0c>; ++ remote-endpoint = <&camera_in2>; ++ }; ++ max9296_des1ep1: endpoint@1 { ++ ser-addr = <0x51>; ++ remote-endpoint = <&camera_in3>; ++ }; ++ }; ++ ++ port@1 { ++ max9296_des1mipi1: endpoint { ++ csi-rate = <1200>; ++ remote-endpoint = <&csi41_ep>; ++ }; ++ }; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ camera@60 { ++ compatible = COMPATIBLE_CAMERAS; ++ reg = <0x60 0x0c>; ++ ++ port@0 { ++ camera_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ camera_max9296_des1ep0: endpoint@1 { ++ remote-endpoint = <&max9296_des1ep0>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ ++ camera@61 { ++ compatible = COMPATIBLE_CAMERAS; ++ reg = <0x61 0x0c>; ++ ++ port@0 { ++ camera_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ port@1 { ++ camera_max9296_des1ep1: endpoint@1 { ++ remote-endpoint = <&max9296_des1ep1>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ /* Disp_SDA and Disp_SCL */ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ ++ /* fan node - lm96063 */ ++ fan_ctrl: lm96063@4c { ++ compatible = "lm96163"; ++ reg = <0x4c>; ++ }; ++ }; ++ ++ /* ESDA and ESCL */ ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ ++ /* ext connector nodes here */ ++ }; ++ }; ++}; ++ ++&gpio0 { ++ fpdl_shdn { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "FPDL_SHDN"; ++ }; ++ ++ cam_pwr_en { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "VIPWR_En"; ++ }; ++ ++ wake_pin_8 { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "WAKE INPUT PIN 8"; ++ }; ++}; ++ ++&gpio1 { ++ md_buf_en { ++ gpio-hog; ++ gpios = <19 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CPLD_If_En"; ++ }; ++}; ++ ++&gpio2 { ++ m2_rst { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M.2 RST#"; ++ }; ++ ++ cctrl_rstn { ++ gpio-hog; ++ gpios = <16 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CCTRL_RSTn"; ++ }; ++ ++ can0_stby { ++ gpio-hog; ++ gpios = <27 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CAN0STBY"; ++ }; ++ ++ can1_load { ++ gpio-hog; ++ gpios = <29 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CAN1Loff"; ++ }; ++ ++ can1_stby { ++ gpio-hog; ++ gpios = <22 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CAN1STBY"; ++ }; ++ ++ wake_pin_7 { ++ gpio-hog; ++ gpios = <19 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "WAKE INPUT PIN 7"; ++ }; ++ ++ vi1_gpioext_rst { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "VIP1_RST"; ++ }; ++}; ++ ++&gpio3 { ++ vi0_gpioext_rst { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "VIP0_RST"; ++ }; ++}; ++ ++&pcie_bus_clk { ++ clock-frequency = <100000000>; ++ status = "okay"; ++}; ++ ++&pciec { ++ pcie3v3-supply = <&mpcie_3v3>; ++ pcie1v8-supply = <&mpcie_1v8>; ++ status = "okay"; ++}; ++ ++&pcie_phy { ++ status = "okay"; ++}; ++ ++&pfc { ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; ++ ++ canfd1_pins: canfd1 { ++ groups = "canfd1_data"; ++ function = "canfd1"; ++ }; ++ ++ avb_pins: avb { ++ groups = "avb_mdio", "avb_rgmii"; ++ function = "avb"; ++ }; ++ ++ i2c1_pins: i2c1 { ++ groups = "i2c1"; ++ function = "i2c1"; ++ }; ++ ++ scif3_pins: scif3 { ++ groups = "scif3_data"; ++ function = "scif3"; ++ }; ++}; ++ ++&scif3 { ++ pinctrl-0 = <&scif3_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&tpu { ++ status = "disabled"; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&camera_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9296_des0ep0: endpoint@1 { ++ remote-endpoint = <&max9296_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&camera_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9296_des0ep1: endpoint@1 { ++ remote-endpoint = <&max9296_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin4 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&camera_in2>; ++ }; ++ }; ++ port@1 { ++ csi1ep0: endpoint { ++ remote-endpoint = <&csi41_ep>; ++ }; ++ }; ++ port@2 { ++ vin4_max9296_des1ep0: endpoint@1 { ++ remote-endpoint = <&max9296_des1ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin5 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&camera_in3>; ++ }; ++ }; ++ port@1 { ++ csi1ep1: endpoint { ++ remote-endpoint = <&csi41_ep>; ++ }; ++ }; ++ port@2 { ++ vin5_max9296_des1ep1: endpoint@1 { ++ remote-endpoint = <&max9296_des1ep1>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk-vb-gmsl2-4.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk-vb-gmsl2-4.dts +new file mode 100644 +index 0000000..310061f +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk-vb-gmsl2-4.dts +@@ -0,0 +1,683 @@ ++/* ++ * Device Tree Source for the V3HSK GMSL2 Quad Videobox Mini board on r8a7798 ++ * ++ * Copyright (C) 2019 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a77980-v3hsk.dts" ++#include ++/* FDPLink output */ ++//#include "vb-fdplink-output.dtsi" ++ ++#define COMPATIBLE_CAMERAS \ ++"onsemi,ar0140", \ ++"onsemi,ar0143", \ ++"onsemi,ar0147", \ ++"onsemi,ar0231", \ ++"onsemi,ar0233", \ ++"onsemi,ap0101", \ ++"onsemi,ap0201", \ ++"ovti,ov10635", \ ++"ovti,ov10640", \ ++"ovti,ov2311", \ ++"ovti,ov2775", \ ++"ovti,ov490", \ ++"ovti,ov495", \ ++"ovti,ox01d10", \ ++"ovti,ox03a", \ ++"sony,imx390", \ ++"sony,isx016", \ ++"sony,isx019", \ ++"dummy,camera" ++ ++/ { ++ model = "Renesas V3HSK 4ch GMSL2 Videobox board based on r8a77980"; ++ ++ aliases { ++ serial1 = &scif3; ++ ethernet1 = &avb; ++ }; ++ ++ cs2300_ref_clk: cs2300_ref_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <25000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led0 { ++ label = "board:status"; ++ gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "none"; ++ }; ++ }; ++ ++ mpcie_1v8: regulator2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "mPCIe 1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ mpcie_3v3: regulator3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "mPCIe 3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ common_3v3: regulator4 { ++ compatible = "regulator-fixed"; ++ regulator-name = "main 3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ iio_hwmon: hwmon@1 { ++ compatible = "iio-hwmon"; ++ io-channels = ++ /* current */ ++ <&max2008x 0>, ++ <&max2008x 2>, ++ /* voltage */ ++ <&max2008x 4>, ++ <&max2008x 6>, ++ /* misc voltages */ ++ <&max2008x 8>, ++ <&max2008x 9>; ++ io-channel-names = ++ "camera-0-Iout", ++ "camera-1-Iout", ++ "camera-0-Vout", ++ "camera-1-Vout", ++ "cameras-Vregulator", ++ "cameras-3v3"; ++ }; ++}; ++ ++&canfd { ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ channel0 { ++ status = "okay"; ++ }; ++ ++ channel1 { ++ status = "okay"; ++ }; ++}; ++ ++&avb { ++ pinctrl-0 = <&avb_pins>; ++ pinctrl-names = "default"; ++ renesas,no-ether-link; ++ phy-handle = <&avb_phy0>; ++ status = "okay"; ++ phy-int-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; ++ ++ avb_phy0: eavb-phy@0 { ++ rxc-skew-ps = <1500>; ++ rxdv-skew-ps = <420>; /* default */ ++ rxd0-skew-ps = <420>; /* default */ ++ rxd1-skew-ps = <420>; /* default */ ++ rxd2-skew-ps = <420>; /* default */ ++ rxd3-skew-ps = <420>; /* default */ ++ txc-skew-ps = <900>; /* default */ ++ txen-skew-ps = <420>; /* default */ ++ txd0-skew-ps = <420>; /* default */ ++ txd1-skew-ps = <420>; /* default */ ++ txd2-skew-ps = <420>; /* default */ ++ txd3-skew-ps = <420>; /* default */ ++ reg = <3>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <17 IRQ_TYPE_LEVEL_LOW>; ++ max-speed = <1000>; ++ }; ++}; ++ ++&csi40 { ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <1200>; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ pinctrl-0 = <&i2c1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ clock-frequency = <400000>; ++ ++ i2cswitch1: i2c-switch@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; ++ ++ /* CCTRL_SDA and CCTRL_SCL */ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ gpio_exp_ch0: gpio_ch0@76 { ++ compatible = "nxp,pca9539"; ++ reg = <0x76>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ cmr_pwr_en { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CmrPEn"; ++ }; ++ }; ++ ++ cs2300: clk_multiplier@4e { ++ #clock-cells = <0>; ++ compatible = "cirrus,cs2300-cp"; ++ reg = <0x4e>; ++ clocks = <&cs2300_ref_clk>; ++ clock-names = "clk_in"; ++ ++ assigned-clocks = <&cs2300>; ++ assigned-clock-rates = <25000000>; ++ }; ++ ++ dac_vcam: dac_vcam@60 { ++ compatible = "microchip,mcp4725"; ++ reg = <0x60>; ++ vdd-supply = <&common_3v3>; ++ }; ++ ++ max2008x: vcam_switch@28 { ++ compatible = "maxim,max2008x"; ++ reg = <0x28>; ++ #io-channel-cells = <1>; ++ enable-gpios = <&gpio_exp_ch0 5 GPIO_ACTIVE_HIGH>; ++ ++ regulators { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ vdd_cam0: SW0 { ++ reg = <0>; ++ regulator-name = "Camera-0"; ++ }; ++ vdd_cam1: SW1 { ++ reg = <1>; ++ regulator-name = "Camera-1"; ++ }; ++ vdd_cam2: SW2 { ++ reg = <2>; ++ regulator-name = "Camera-2"; ++ }; ++ vdd_cam3: SW3 { ++ reg = <3>; ++ regulator-name = "Camera-3"; ++ }; ++ }; ++ }; ++ }; ++ ++ /* DS0_SDA and DS0_SCL */ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ ++ max96712@29 { ++ compatible = "maxim,max96712"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x29>; ++ clocks = <&cs2300>; ++ clock-names = "ref_clk"; ++ shutdown-gpios = <&gpio_exp_ch0 1 GPIO_ACTIVE_LOW>; ++ ++ maxim,links-mipi-map = <2 2 2 2>; ++ ++ poc0-supply = <&vdd_cam3>; ++ poc1-supply = <&vdd_cam1>; ++ poc2-supply = <&vdd_cam0>; ++ poc3-supply = <&vdd_cam2>; ++ ++ port@0 { ++ max96712_des0ep0: endpoint@0 { ++ ser-addr = <0x0c>; ++ remote-endpoint = <&camera_in0>; ++ }; ++ max96712_des0ep1: endpoint@1 { ++ ser-addr = <0x0d>; ++ remote-endpoint = <&camera_in1>; ++ }; ++ max96712_des0ep2: endpoint@2 { ++ ser-addr = <0x0e>; ++ remote-endpoint = <&camera_in2>; ++ }; ++ max96712_des0ep3: endpoint@3 { ++ ser-addr = <0x0f>; ++ remote-endpoint = <&camera_in3>; ++ }; ++ }; ++ ++ port@1 { ++ max96712_mipi2: endpoint { ++ csi-rate = <1200>; ++ remote-endpoint = <&csi40_ep>; ++ }; ++ }; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ camera@60 { ++ compatible = COMPATIBLE_CAMERAS; ++ reg = <0x60 0x0c>; ++ ++ port@0 { ++ camera_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ camera_max96712_des0ep0: endpoint@1 { ++ remote-endpoint = <&max96712_des0ep0>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ ++ camera@61 { ++ compatible = COMPATIBLE_CAMERAS; ++ reg = <0x61 0x0d>; ++ ++ port@0 { ++ camera_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ camera_max96712_des0ep1: endpoint@1 { ++ remote-endpoint = <&max96712_des0ep1>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ ++ camera@62 { ++ compatible = COMPATIBLE_CAMERAS; ++ reg = <0x62 0x0e>; ++ ++ port@0 { ++ camera_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ camera_max96712_des0ep2: endpoint@1 { ++ remote-endpoint = <&max96712_des0ep2>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ ++ camera@63 { ++ compatible = COMPATIBLE_CAMERAS; ++ reg = <0x63 0x0f>; ++ ++ port@0 { ++ camera_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ camera_max96712_des0ep3: endpoint@1 { ++ remote-endpoint = <&max96712_des0ep3>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ /* CTL0_SDA and CTL0_SCL */ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ }; ++ ++ /* Disp_SDA and Disp_SCL */ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ ++ /* fan node - lm96063 */ ++ fan_ctrl: lm96063@4c { ++ compatible = "lm96163"; ++ reg = <0x4c>; ++ }; ++ }; ++ ++ /* ESDA and ESCL */ ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ ++ rtc: mcp79411@6f { ++ compatible = "microchip,mcp7941x"; ++ reg = <0x6f>; ++ }; ++ }; ++ }; ++}; ++ ++&gpio0 { ++ fpdl_shdn { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "FPDL_SHDN"; ++ }; ++ ++ cam_pwr_en { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "VIPWR_En"; ++ }; ++ ++ wake_pin_8 { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "WAKE INPUT PIN 8"; ++ }; ++}; ++ ++&gpio1 { ++ md_buf_en { ++ gpio-hog; ++ gpios = <19 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CPLD_If_En"; ++ }; ++}; ++ ++&gpio2 { ++ m2_rst { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M.2 RST#"; ++ }; ++ ++ cctrl_rstn { ++ gpio-hog; ++ gpios = <16 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CCTRL_RSTn"; ++ }; ++ ++ can0_stby { ++ gpio-hog; ++ gpios = <27 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CAN0STBY"; ++ }; ++ ++ can1_load { ++ gpio-hog; ++ gpios = <29 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CAN1Loff"; ++ }; ++ ++ can1_stby { ++ gpio-hog; ++ gpios = <22 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "CAN1STBY"; ++ }; ++ ++ wake_pin_7 { ++ gpio-hog; ++ gpios = <19 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "WAKE INPUT PIN 7"; ++ }; ++ ++ vi1_gpioext_rst { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "VIP1_RST"; ++ }; ++}; ++ ++&gpio3 { ++ vi0_gpioext_rst { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "VIP0_RST"; ++ }; ++}; ++ ++&pcie_bus_clk { ++ clock-frequency = <100000000>; ++ status = "okay"; ++}; ++ ++&pciec { ++ pcie3v3-supply = <&mpcie_3v3>; ++ pcie1v8-supply = <&mpcie_1v8>; ++ status = "okay"; ++}; ++ ++&pcie_phy { ++ status = "okay"; ++}; ++ ++&pfc { ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; ++ ++ canfd1_pins: canfd1 { ++ groups = "canfd1_data"; ++ function = "canfd1"; ++ }; ++ ++ avb_pins: avb { ++ groups = "avb_mdio", "avb_rgmii"; ++ function = "avb"; ++ }; ++ ++ i2c1_pins: i2c1 { ++ groups = "i2c1"; ++ function = "i2c1"; ++ }; ++ ++ scif3_pins: scif3 { ++ groups = "scif3_data"; ++ function = "scif3"; ++ }; ++}; ++ ++&scif3 { ++ pinctrl-0 = <&scif3_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&tpu { ++ status = "disabled"; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&camera_in0>; ++ }; ++ }; ++ port@1 { ++ csi1ep0: endpoint { ++ remote-endpoint = <&csi40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max96712_des0ep0: endpoint@1 { ++ remote-endpoint = <&max96712_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&camera_in1>; ++ }; ++ }; ++ port@1 { ++ csi1ep1: endpoint { ++ remote-endpoint = <&csi40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max96712_des0ep1: endpoint@1 { ++ remote-endpoint = <&max96712_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&camera_in2>; ++ }; ++ }; ++ port@1 { ++ csi1ep2: endpoint { ++ remote-endpoint = <&csi40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max96712_des0ep2: endpoint@1 { ++ remote-endpoint = <&max96712_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&camera_in3>; ++ }; ++ }; ++ port@1 { ++ csi1ep3: endpoint { ++ remote-endpoint = <&csi40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max96712_des0ep3: endpoint@1 { ++ remote-endpoint = <&max96712_des0ep3>; ++ }; ++ }; ++ }; ++}; +-- +2.7.4 + -- cgit 1.2.3-korg