From 1c7d6584a7811b7785ae5c1e378f14b5ba0971cf Mon Sep 17 00:00:00 2001 From: takeshi_hoshina Date: Mon, 2 Nov 2020 11:07:33 +0900 Subject: basesystem-jj recipes --- .../webrtc-audio-processing/riscv_support.patch | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 external/meta-openembedded/meta-multimedia/recipes-multimedia/webrtc-audio-processing/webrtc-audio-processing/riscv_support.patch (limited to 'external/meta-openembedded/meta-multimedia/recipes-multimedia/webrtc-audio-processing/webrtc-audio-processing/riscv_support.patch') diff --git a/external/meta-openembedded/meta-multimedia/recipes-multimedia/webrtc-audio-processing/webrtc-audio-processing/riscv_support.patch b/external/meta-openembedded/meta-multimedia/recipes-multimedia/webrtc-audio-processing/webrtc-audio-processing/riscv_support.patch new file mode 100644 index 00000000..576b9860 --- /dev/null +++ b/external/meta-openembedded/meta-multimedia/recipes-multimedia/webrtc-audio-processing/webrtc-audio-processing/riscv_support.patch @@ -0,0 +1,33 @@ +Add support for RISC-V + +Upstream-Status: Pending +Signed-off-by: Khem Raj +--- a/webrtc/base/basictypes.h ++++ b/webrtc/base/basictypes.h +@@ -29,6 +29,10 @@ + #define CPU_ARM 1 + #endif + ++#if defined(__riscv) || defined(_M_RISCV) ++#define CPU_RISCV 1 ++#endif ++ + #if defined(CPU_X86) && defined(CPU_ARM) + #error CPU_X86 and CPU_ARM both defined. + #endif +--- a/webrtc/typedefs.h ++++ b/webrtc/typedefs.h +@@ -56,6 +56,13 @@ + #elif defined(__powerpc__) + #define WEBRTC_ARCH_32_BITS + #define WEBRTC_ARCH_BIG_ENDIAN ++#elif defined(__riscv) ++#if __riscv_xlen == 64 ++# define WEBRTC_ARCH_64_BITS ++#else ++# define WEBRTC_ARCH_32_BITS ++#endif ++#define WEBRTC_ARCH_LITTLE_ENDIAN + #elif defined(__pnacl__) + #define WEBRTC_ARCH_32_BITS + #define WEBRTC_ARCH_LITTLE_ENDIAN -- cgit 1.2.3-korg