From 1c7d6584a7811b7785ae5c1e378f14b5ba0971cf Mon Sep 17 00:00:00 2001 From: takeshi_hoshina Date: Mon, 2 Nov 2020 11:07:33 +0900 Subject: basesystem-jj recipes --- .../python/python3-grpcio/riscv64_support.patch | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 external/meta-openembedded/meta-python/recipes-devtools/python/python3-grpcio/riscv64_support.patch (limited to 'external/meta-openembedded/meta-python/recipes-devtools/python/python3-grpcio/riscv64_support.patch') diff --git a/external/meta-openembedded/meta-python/recipes-devtools/python/python3-grpcio/riscv64_support.patch b/external/meta-openembedded/meta-python/recipes-devtools/python/python3-grpcio/riscv64_support.patch new file mode 100644 index 00000000..8c9ffa21 --- /dev/null +++ b/external/meta-openembedded/meta-python/recipes-devtools/python/python3-grpcio/riscv64_support.patch @@ -0,0 +1,21 @@ +Add RISC-V 64bit support + +Upstream-Status: Pending +Signed-off-by: Khem Raj +--- a/third_party/boringssl/include/openssl/base.h ++++ b/third_party/boringssl/include/openssl/base.h +@@ -108,6 +108,14 @@ extern "C" { + #elif defined(__mips__) && defined(__LP64__) + #define OPENSSL_64_BIT + #define OPENSSL_MIPS64 ++#elif defined(__riscv) ++# if (__riscv_xlen == 64) ++# define OPENSSL_64_BIT ++# define OPENSSL_RISCV64 ++# elif(__riscv_xlen == 32) ++# define OPENSSL_32_BIT ++# define OPENSSL_RISCV32 ++# endif + #elif defined(__pnacl__) + #define OPENSSL_32_BIT + #define OPENSSL_PNACL -- cgit 1.2.3-korg