From 5eed9c28ff8ef9a54bdebef89925f198e9caf846 Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Tue, 23 Apr 2019 23:16:15 +0300 Subject: [PATCH 16/23] ARM: rmobile: Add R8A77970 V3MSK board support This adds V3MSK board support based on the Eagle board. Signed-off-by: Valentine Barshak --- arch/arm/dts/Makefile | 1 + arch/arm/dts/r8a77970-v3msk-u-boot.dts | 54 ++++++++ arch/arm/dts/r8a77970-v3msk.dts | 228 +++++++++++++++++++++++++++++++++ arch/arm/mach-rmobile/Kconfig.64 | 6 + board/renesas/v3msk/Kconfig | 15 +++ board/renesas/v3msk/MAINTAINERS | 6 + board/renesas/v3msk/Makefile | 10 ++ board/renesas/v3msk/v3msk.c | 107 ++++++++++++++++ configs/r8a77970_v3msk_defconfig | 77 +++++++++++ doc/README.rmobile | 1 + include/configs/v3msk.h | 32 +++++ 11 files changed, 537 insertions(+) create mode 100644 arch/arm/dts/r8a77970-v3msk-u-boot.dts create mode 100644 arch/arm/dts/r8a77970-v3msk.dts create mode 100644 board/renesas/v3msk/Kconfig create mode 100644 board/renesas/v3msk/MAINTAINERS create mode 100644 board/renesas/v3msk/Makefile create mode 100644 board/renesas/v3msk/v3msk.c create mode 100644 configs/r8a77970_v3msk_defconfig create mode 100644 include/configs/v3msk.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0b422ca..c6e1908 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -466,6 +466,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \ r8a77965-salvator-xs-u-boot.dtb \ r8a77965-m3nulcb-u-boot.dtb \ r8a77970-eagle-u-boot.dtb \ + r8a77970-v3msk-u-boot.dtb \ r8a77990-ebisu-u-boot.dtb \ r8a77990-ebisu-4d-u-boot.dtb \ r8a77995-draak-u-boot.dtb diff --git a/arch/arm/dts/r8a77970-v3msk-u-boot.dts b/arch/arm/dts/r8a77970-v3msk-u-boot.dts new file mode 100644 index 0000000..65a3061 --- /dev/null +++ b/arch/arm/dts/r8a77970-v3msk-u-boot.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the V3MSK board + * + * Copyright (C) 2019 Cogent Embedded, Inc. + */ + +#include "r8a77970-v3msk.dts" +#include "r8a77970-u-boot.dtsi" +#include + +/ { + aliases { + spi0 = &rpc; + }; +}; + +&avb { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + +}; + +&phy0 { + reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +}; + +&pfc { + avb0_pins: avb { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; + function = "avb0"; + }; + }; +}; + +&rpc { + num-cs = <1>; + status = "okay"; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + + flash0: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fs512s", "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + reg = <0>; + status = "okay"; + }; +}; diff --git a/arch/arm/dts/r8a77970-v3msk.dts b/arch/arm/dts/r8a77970-v3msk.dts new file mode 100644 index 0000000..72ddc82 --- /dev/null +++ b/arch/arm/dts/r8a77970-v3msk.dts @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the V3M Starter Kit board + * + * Copyright (C) 2019 Renesas Electronics Corp. + * Copyright (C) 2019 Cogent Embedded, Inc. + */ + +/dts-v1/; +#include "r8a77970.dtsi" + +/ { + model = "Renesas V3M Starter Kit board"; + compatible = "renesas,v3msk", "renesas,r8a77970"; + + aliases { + serial0 = &scif0; + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + osc5_clk: osc5-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + vcc_d1_8v: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VCC_D1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_d3_3v: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VCC_D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_vddq_vin0: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "VCC_VDDQ_VIN0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + lvds-decoder { + compatible = "thine,thc63lvd1024"; + vcc-supply = <&vcc_d3_3v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + thc63lvd1024_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@2 { + reg = <2>; + thc63lvd1024_out: endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + renesas,no-ether-link; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + }; +}; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&osc5_clk>; + clock-names = "du.0", "dclkin.0"; + status = "okay"; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&pfc { + avb_pins: avb0 { + groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; + function = "avb0"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + mmc_pins: mmc_3_3v { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <3300>; + }; + + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + hdmi@39{ + compatible = "adi,adv7511w"; + #sound-dai-cells = <0>; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + avdd-supply = <&vcc_d1_8v>; + dvdd-supply = <&vcc_d1_8v>; + pvdd-supply = <&vcc_d1_8v>; + bgvdd-supply = <&vcc_d1_8v>; + dvdd-3v-supply = <&vcc_d3_3v>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&thc63lvd1024_out>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&thc63lvd1024_in>; + }; + }; + }; +}; + +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_d3_3v>; + vqmmc-supply = <&vcc_vddq_vin0>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index cb9f569..08239a6 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -34,6 +34,11 @@ config TARGET_EAGLE help Support for Renesas R-Car Gen3 Eagle platform +config TARGET_V3MSK + bool "V3MSK board" + help + Support for Renesas R-Car Gen3 V3MSK platform + config TARGET_EBISU bool "Ebisu board" help @@ -56,6 +61,7 @@ config SYS_SOC source "board/renesas/draak/Kconfig" source "board/renesas/eagle/Kconfig" +source "board/renesas/v3msk/Kconfig" source "board/renesas/ebisu/Kconfig" source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig" diff --git a/board/renesas/v3msk/Kconfig b/board/renesas/v3msk/Kconfig new file mode 100644 index 0000000..ecfc9b9 --- /dev/null +++ b/board/renesas/v3msk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_V3MSK + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "v3msk" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "v3msk" + +endif diff --git a/board/renesas/v3msk/MAINTAINERS b/board/renesas/v3msk/MAINTAINERS new file mode 100644 index 0000000..12822a4 --- /dev/null +++ b/board/renesas/v3msk/MAINTAINERS @@ -0,0 +1,6 @@ +V3MSK BOARD +M: Cogent Embedded, Inc. +S: Maintained +F: board/renesas/v3msk/ +F: include/configs/v3msk.h +F: configs/r8a77970_v3msk_defconfig diff --git a/board/renesas/v3msk/Makefile b/board/renesas/v3msk/Makefile new file mode 100644 index 0000000..f1ce184 --- /dev/null +++ b/board/renesas/v3msk/Makefile @@ -0,0 +1,10 @@ +# +# board/renesas/v3msk/Makefile +# +# Copyright (C) 2019 Renesas Electronics Corporation +# Copyright (C) 2019 Cogent Embedded, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := v3msk.o diff --git a/board/renesas/v3msk/v3msk.c b/board/renesas/v3msk/v3msk.c new file mode 100644 index 0000000..4a1c546 --- /dev/null +++ b/board/renesas/v3msk/v3msk.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * board/renesas/v3msk/v3msk.c + * This file is V3MSK board support. + * + * Based on Eagle board support. + * + * Copyright (C) 2019 Cogent Embedded, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define CPGWPR 0xE6150900 +#define CPGWPCR 0xE6150904 + +/* PLL */ +#define PLL0CR 0xE61500D8 +#define PLL0_STC_MASK 0x7F000000 +#define PLL0_STC_OFFSET 24 + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + u32 stc; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* CPU frequency setting. Set to 0.8GHz */ + stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET; + clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); +} + +int board_early_init_f(void) +{ + /* Unlock CPG access */ + writel(0xA5A5FFFF, CPGWPR); + writel(0x5A5A0000, CPGWPCR); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; + + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + return -EINVAL; + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +#define RST_BASE 0xE6160000 +#define RST_CA57RESCNT (RST_BASE + 0x40) +#define RST_CA53RESCNT (RST_BASE + 0x44) +#define RST_RSTOUTCR (RST_BASE + 0x58) +#define RST_CA57_CODE 0xA5A5000F +#define RST_CA53_CODE 0x5A5A000F + +void reset_cpu(ulong addr) +{ + unsigned long midr, cputype; + + asm volatile("mrs %0, midr_el1" : "=r" (midr)); + cputype = (midr >> 4) & 0xfff; + + if (cputype == 0xd03) + writel(RST_CA53_CODE, RST_CA53RESCNT); + else if (cputype == 0xd07) + writel(RST_CA57_CODE, RST_CA57RESCNT); + else + hang(); +} diff --git a/configs/r8a77970_v3msk_defconfig b/configs/r8a77970_v3msk_defconfig new file mode 100644 index 0000000..7de8af5 --- /dev/null +++ b/configs/r8a77970_v3msk_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_RMOBILE=y +CONFIG_SYS_TEXT_BASE=0x50000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_RCAR_GEN3=y +CONFIG_R8A77970=y +CONFIG_TARGET_V3MSK=y +CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_DEFAULT_FDT_FILE="r8a77970-v3msk.dtb" +CONFIG_VERSION_VARIABLE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="r8a77970-v3msk-u-boot" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_DM_GPIO=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_RENESAS_RAVB=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_PFC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SCIF_CONSOLE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SMBIOS_MANUFACTURER="" diff --git a/doc/README.rmobile b/doc/README.rmobile index f1bca54..c4bde66 100644 --- a/doc/README.rmobile +++ b/doc/README.rmobile @@ -34,6 +34,7 @@ Currently the following boards are supported: | R8A77965 M3-N | Renesas Electronics Salvator-XS | r8a77965_salvator-x_defconfig |---------------+----------------------------------------+------------------- | R8A77970 V3M | Renesas Electronics Eagle | r8a77970_eagle_defconfig +| R8A77970 V3M | Renesas Electronics V3MSK | r8a77970_v3msk_defconfig |---------------+----------------------------------------+------------------- | R8A77995 D3 | Renesas Electronics Draak | r8a77995_draak_defconfig '===============+========================================+=================== diff --git a/include/configs/v3msk.h b/include/configs/v3msk.h new file mode 100644 index 0000000..290e4a2 --- /dev/null +++ b/include/configs/v3msk.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/v3msk.h + * This file is V3MSK board configuration. + * + * Copyright (C) 2019 Renesas Electronics Corporation + * Copyright (C) 2019 Cogent Embedded, Inc. + */ + +#ifndef __V3MSK_H +#define __V3MSK_H + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* Environment compatibility */ +#undef CONFIG_ENV_SIZE_REDUND +#undef CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SECT_SIZE (256 * 1024) +#define CONFIG_ENV_OFFSET 0x700000 + +/* Board Clock */ +/* XTAL_CLK : 33.33MHz */ +#define CONFIG_SYS_CLK_FREQ 33333333u + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +#endif /* __V3MSK_H */ -- 2.7.4