From 084e65dfa693df84189b907ab06ec0bac92abc92 Mon Sep 17 00:00:00 2001 From: Yusuke Goda Date: Fri, 26 Oct 2018 15:42:38 +0900 Subject: [PATCH 027/122] Add MOST support for r8a77965 This adds MOST support to R-Car M3N. Signed-off-by: Yusuke Goda Signed-off-by: Valentine Barshak --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 13 +++++++++++++ drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 + drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 14 ++++++++++++++ 3 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index e682d10..b5926ff 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1188,6 +1188,19 @@ status = "disabled"; }; + mlp: mlp@ec520000 { + compatible = "rcar,medialb-dim2"; + reg = <0 0xec520000 0 0x800>; + interrupts = , + , + , + , + ; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + status = "disabled"; + }; + msiof0: spi@e6e90000 { compatible = "renesas,msiof-r8a77965", "renesas,rcar-gen3-msiof"; diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index b3b637f..3d4fe53 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -190,6 +190,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { DEF_MOD("lvds", 727, R8A77965_CLK_S2D1), DEF_MOD("hdmi0", 729, R8A77965_CLK_HDMI), + DEF_MOD("mlp", 802, R8A77965_CLK_S2D1), DEF_MOD("vin7", 804, R8A77965_CLK_S0D2), DEF_MOD("vin6", 805, R8A77965_CLK_S0D2), DEF_MOD("vin5", 806, R8A77965_CLK_S0D2), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c index 8f4b73c..91aa6c0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c @@ -2627,6 +2627,14 @@ static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), +}; +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, +}; + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -4562,6 +4570,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), + SH_PFC_PIN_GROUP(mlb_3pin), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -4982,6 +4991,10 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq5", }; +static const char * const mlb_3pin_groups[] = { + "mlb_3pin", +}; + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -5325,6 +5338,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), SH_PFC_FUNCTION(intc_ex), + SH_PFC_FUNCTION(mlb_3pin), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), -- 2.7.4