meta-agl-demo - meta-agl-demo layer (demo/staging/"one-shot")

Age	Commit message (Expand)	Author	Files	Lines
2019-11-06	Update LIN demo to use lin-config	Scott Murray	4	-6/+24
2018-11-30	Disable sllin driver(using HVAC apps) debug logguppy_6.99.2 guppy/6.99.2 6.99.2	Yuichi Kusakabe	2	-0/+28
2018-11-29	We need to use multi-user.target	Jan-Simon Möller	1	-1/+1
2018-11-13	Finalize and automate sllin setup for LIN on demo unit	Jan-Simon Möller	3	-1/+82
2018-10-31	Add package for sllin driver to image	Jan-Simon Möller	4	-0/+287
2018-06-08	meta-agl-demo: remove Mocca application	Christian Gromm	1	-22/+0
2018-06-05	3rd part of the layer/profile rework [2/2]	Jan-Simon Möller	1	-0/+22
2018-04-28	2nd part of the layer/profile rework [2/2]	Jan-Simon Möller	11	-1299/+0
2018-03-13	recipes-kernel: most: add patch set for DT support	Christian Gromm	5	-0/+707
2018-02-13	Fix most for kernel 4.14	ronan	2	-34/+0
2017-12-19	Convert most.bb to use KERNEL_MODULE_AUTOLOAD framework	Jan-Simon Möller	1	-17/+1
2017-11-09	recipes-kernel: most: use AGL_BRANCH variable	Christian Gromm	1	-1/+1
2017-11-09	recipes-kernel: most: update recipes	Christian Gromm	8	-279/+512
2017-11-05	Allow SRCREV handling through poky-agl.confeel_4.99.2 eel/4.99.2 4.99.2	Jan-Simon Möller	2	-3/+3
2017-09-29	most.bbappend: Fix for Renesas Porter board	Leon Anavi	1	-0/+3
2017-09-26	recipes-kernel: most: add most.bbappend file	Christian Gromm	6	-0/+278
2017-06-12	fix MOST driver dependency issues	Christian Gromm	11	-199/+38
2017-05-29	Unpin after Daring Dab RC1	Jan-Simon Moeller	8	-8/+0
2017-05-25	Add a bbappend with pinnning for all packages with AUTOREVdab_3.99.1 dab/3.99.1 3.99.1	Jan-Simon Möller	8	-0/+8
2017-02-14	kernel: most: add mostcore module dependencies	Matt Ranostay	7	-0/+7
2017-01-27	meta-agl-demo: recipes-kernel: update MOST driver recipes	Christian Gromm	11	-68/+93
2016-12-22	Add packages to agl-demo-platform for CES2017 Demo	Tadao Tanikawa	13	-790/+27
2016-12-22	Support systemd services of MOST for CES2017 Demo	Tadao Tanikawa	9	-0/+72
2016-12-17	recipes-demo-hmi: fix file permissions	Christian Gromm	1	-0/+0
2016-08-02	recipes-kernel: update driver recipes	Christian Gromm	45	-11596/+504
2015-12-21	recipes-kernel: add MOST driver kernel modules	Christian Gromm	41	-0/+12040

From 2259b001b23c4328ec197604a2d430dcf3c3f78a Mon Sep 17 00:00:00 2001 From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Date: Sat, 10 Feb 2018 00:52:28 +0300 Subject: [PATCH] plat: renesas: rcar: V3H support This adds R-Car V3H support. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> --- plat/renesas/rcar/bl2_cpg_init.c | 68 ++ plat/renesas/rcar/bl2_rcar_setup.c | 11 +- plat/renesas/rcar/ddr/boot_init_dram.c | 7 + plat/renesas/rcar/drivers/rom/rom_api.c | 17 +- plat/renesas/rcar/drivers/scif/scif.S | 2 +- plat/renesas/rcar/include/bl2_dma_register.h | 2 +- plat/renesas/rcar/include/platform_def.h | 4 + plat/renesas/rcar/pfc/V3H/pfc_init_v3h.c | 1196 ++++++++++++++++++++++++++ plat/renesas/rcar/pfc/V3H/pfc_init_v3h.h | 37 + plat/renesas/rcar/pfc/pfc.mk | 7 + plat/renesas/rcar/pfc/pfc_init.c | 21 + plat/renesas/rcar/platform.mk | 18 + plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.c | 651 ++++++++++++++ plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.h | 37 + plat/renesas/rcar/qos/qos.mk | 7 + plat/renesas/rcar/qos/qos_init.c | 26 + plat/renesas/rcar/rcar_def.h | 3 +- tools/dummy_create/makefile | 5 + 18 files changed, 2113 insertions(+), 6 deletions(-) create mode 100644 plat/renesas/rcar/pfc/V3H/pfc_init_v3h.c create mode 100644 plat/renesas/rcar/pfc/V3H/pfc_init_v3h.h create mode 100644 plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.c create mode 100644 plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.h diff --git a/plat/renesas/rcar/bl2_cpg_init.c b/plat/renesas/rcar/bl2_cpg_init.c index 3b424e0..9e945a0 100644 --- a/plat/renesas/rcar/bl2_cpg_init.c +++ b/plat/renesas/rcar/bl2_cpg_init.c @@ -52,6 +52,10 @@ static void bl2_system_cpg_init_m3n(void); static void bl2_realtime_cpg_init_v3m(void); static void bl2_system_cpg_init_v3m(void); #endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M) */ +#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3H) +static void bl2_realtime_cpg_init_v3h(void); +static void bl2_system_cpg_init_v3h(void); +#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3H) */ typedef struct { uintptr_t adr; @@ -367,6 +371,60 @@ static void bl2_system_cpg_init_v3m(void) } #endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M) */ +#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3H) +static void bl2_realtime_cpg_init_v3h(void) +{ + /* CPG (REALTIME) registers */ + + /* Realtime Module Stop Control Register 0 */ + cpg_write(RMSTPCR0, 0x00230000U); + /* Realtime Module Stop Control Register 1 */ + cpg_write(RMSTPCR1, 0xFFFFFFFFU); + /* Realtime Module Stop Control Register 2 */ + cpg_write(RMSTPCR2, 0x14062FD8U); + /* Realtime Module Stop Control Register 3 */ + cpg_write(RMSTPCR3, 0xFFFFFFDFU); + /* Realtime Module Stop Control Register 4 */ + cpg_write(RMSTPCR4, 0x80000184U); + /* Realtime Module Stop Control Register 5 */ + cpg_write(RMSTPCR5, 0x83FFFFFFU); + /* Realtime Module Stop Control Register 6 */ + cpg_write(RMSTPCR6, 0xFFFFFFFFU); + /* Realtime Module Stop Control Register 7 */ + cpg_write(RMSTPCR7, 0xFFFFFFFFU); + /* Realtime Module Stop Control Register 8 */ + cpg_write(RMSTPCR8, 0x7FF3FFF4U); + /* Realtime Module Stop Control Register 9 */ + cpg_write(RMSTPCR9, 0xFFFFFFFEU); +} + +static void bl2_system_cpg_init_v3h(void) +{ + /* CPG (SYSTEM) registers */ + + /* System Module Stop Control Register 0 */ + cpg_write(SMSTPCR0, 0x00210000U); + /* System Module Stop Control Register 1 */ + cpg_write(SMSTPCR1, 0xFFFFFFFFU); + /* System Module Stop Control Register 2 */ + cpg_write(SMSTPCR2, 0x340E2FDCU); + /* System Module Stop Control Register 3 */ + cpg_write(SMSTPCR3, 0xFFFFFBDFU); + /* System Module Stop Control Register 4 */ + cpg_write(SMSTPCR4, 0x80000004U); + /* System Module Stop Control Register 5 */ + cpg_write(SMSTPCR5, 0xC3FFFFFFU); + /* System Module Stop Control Register 6 */ + cpg_write(SMSTPCR6, 0xFFFFFFFFU); + /* System Module Stop Control Register 7 */ + cpg_write(SMSTPCR7, 0xFFFFFFFFU); + /* System Module Stop Control Register 8 */ + cpg_write(SMSTPCR8, 0x01F1FFF5U); + /* System Module Stop Control Register 9 */ + cpg_write(SMSTPCR9, 0xFFFFFFFEU); +} +#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3H) */ + void bl2_cpg_init(void) { uint32_t modemr; @@ -398,6 +456,9 @@ void bl2_cpg_init(void) case RCAR_PRODUCT_v3m: bl2_realtime_cpg_init_v3m(); break; + case RCAR_PRODUCT_v3h: + bl2_realtime_cpg_init_v3h(); + break; default: panic(); break; @@ -410,6 +471,8 @@ void bl2_cpg_init(void) bl2_realtime_cpg_init_m3n(); #elif RCAR_LSI == RCAR_V3M bl2_realtime_cpg_init_v3m(); +#elif RCAR_LSI == RCAR_V3H + bl2_realtime_cpg_init_v3h(); #else /* RCAR_LSI == RCAR_XX */ #error "Don't have CPG initialize routine(unknown)." #endif /* RCAR_LSI == RCAR_XX */ @@ -435,6 +498,9 @@ void bl2_system_cpg_init(void) case RCAR_PRODUCT_V3M: bl2_system_cpg_init_v3m(); break; + case RCAR_PRODUCT_V3H: + bl2_system_cpg_init_v3h(); + break; default: panic(); break; @@ -447,6 +513,8 @@ void bl2_system_cpg_init(void) bl2_system_cpg_init_m3n(); #elif RCAR_LSI == RCAR_V3M bl2_system_cpg_init_v3m(); +#elif RCAR_LSI == RCAR_V3H + bl2_system_cpg_init_v3h(); #else /* RCAR_LSI == RCAR_XX */ #error "Don't have CPG initialize routine(unknown)." #endif /* RCAR_LSI == RCAR_XX */ diff --git a/plat/renesas/rcar/bl2_rcar_setup.c b/plat/renesas/rcar/bl2_rcar_setup.c index 19f887c..ffa5e3c 100755 --- a/plat/renesas/rcar/bl2_rcar_setup.c +++ b/plat/renesas/rcar/bl2_rcar_setup.c @@ -141,6 +141,9 @@ #elif RCAR_LSI == RCAR_V3M #define TARGET_PRODUCT RCAR_PRODUCT_V3M #define TARGET_NAME "R-Car V3M" +#elif RCAR_LSI == RCAR_V3H +#define TARGET_PRODUCT RCAR_PRODUCT_V3H +#define TARGET_NAME "R-Car V3H" #endif /* for SuspendToRAM */ @@ -392,6 +395,7 @@ void bl2_early_platform_setup(meminfo_t *mem_layout) const char *product_m3 = "M3"; const char *product_m3n = "M3N"; const char *product_v3m = "V3M"; + const char *product_v3h = "V3H"; const char *lcs_cm = "CM"; const char *lcs_dm = "DM"; const char *lcs_sd = "SD"; @@ -469,6 +473,9 @@ void bl2_early_platform_setup(meminfo_t *mem_layout) case RCAR_PRODUCT_V3M: str = product_v3m; break; + case RCAR_PRODUCT_V3H: + str = product_v3h; + break; default: str = unknown; break; @@ -513,7 +520,7 @@ void bl2_early_platform_setup(meminfo_t *mem_layout) } #endif /* RCAR_LSI != RCAR_AUTO */ -#if RCAR_LSI != RCAR_V3M +#if (RCAR_LSI != RCAR_V3M) && (RCAR_LSI != RCAR_V3H) /* Initialize AVS Settings */ bl2_avs_init(); @@ -547,7 +554,7 @@ void bl2_early_platform_setup(meminfo_t *mem_layout) (void)sprintf(msg, "BL2: Boot device is %s\n", str); NOTICE("%s", msg); -#if RCAR_LSI != RCAR_V3M +#if (RCAR_LSI != RCAR_V3M) && (RCAR_LSI != RCAR_V3H) /* Proceed with separated AVS processing */ bl2_avs_setting(); #endif diff --git a/plat/renesas/rcar/ddr/boot_init_dram.c b/plat/renesas/rcar/ddr/boot_init_dram.c index 87360a6..28b0a9f 100644 --- a/plat/renesas/rcar/ddr/boot_init_dram.c +++ b/plat/renesas/rcar/ddr/boot_init_dram.c @@ -3594,6 +3594,13 @@ int32_t InitDram(void) } #endif +#if RCAR_LSI == RCAR_V3H + if (Prr_Product == PRR_PRODUCT_V3H) { + /* dram initialized by CR7 */ + return INITDRAM_OK; + } +#endif + if (Prr_Product == PRR_PRODUCT_H3) { if(PRR_PRODUCT_11>=Prr_Cut){ pDDR_REGDEF_TBL = (uint32_t *)&DDR_REGDEF_TBL[0][0]; diff --git a/plat/renesas/rcar/drivers/rom/rom_api.c b/plat/renesas/rcar/drivers/rom/rom_api.c index 186660d..812f6a9 100644 --- a/plat/renesas/rcar/drivers/rom/rom_api.c +++ b/plat/renesas/rcar/drivers/rom/rom_api.c @@ -54,7 +54,8 @@ static uint32_t get_table_index(void); #define OLD_API_TABLE3 (2U) /* M3 WS1.0/1.05 */ #define NEW_API_TABLE (3U) /* M3 WS1.06 or later, M3N, E3, V3M WS2.0 */ #define NEW_API_TABLE2 (4U) /* V3M WS1.0 */ -#define API_TABLE_MAX (5U) /* table max */ +#define NEW_API_TABLE3 (5U) /* V3H WS1.0 */ +#define API_TABLE_MAX (6U) /* table max */ @@ -69,6 +70,7 @@ uint32_t ROM_SecureBootAPI( uint32_t *pKeyCert, 0xEB1102FCU, /* M3 WS1.0/1.05 */ 0xEB100180U, /* M3 WS1.06 or later, M3N, E3, V3M WS2.0 */ 0xEB110128U, /* V3M WS1.0 */ + 0xEB101960U, /* V3H WS1.0 */ }; ROM_SECURE_BOOT_API func; @@ -83,6 +85,10 @@ uint32_t ROM_SecureBootAPI( uint32_t *pKeyCert, uint32_t ROM_GetLcs(uint32_t *pLcs) { +#if RCAR_LSI == RCAR_V3H + *pLcs = 0xff; + return 0; +#else /* Get LCS stete API address table */ static const uintptr_t ROM_GetLcs_table[API_TABLE_MAX] = { 0xEB10DFE0U, /* H3 WS1.0/WS1.1 */ @@ -90,6 +96,7 @@ uint32_t ROM_GetLcs(uint32_t *pLcs) 0xEB110578U, /* M3 WS1.0/1.05 */ 0xEB10018CU, /* M3 WS1.06 or later, M3N, E3, V3M WS2.0 */ 0xEB1103A4U, /* V3M WS1.0 */ + 0xEB101940U, /* V3H WS1.0 */ }; ROM_GETLCS_API func; @@ -99,6 +106,7 @@ uint32_t ROM_GetLcs(uint32_t *pLcs) func = (ROM_GETLCS_API)ROM_GetLcs_table[index]; return func(pLcs); +#endif } @@ -145,6 +153,13 @@ static uint32_t get_table_index(void) index = NEW_API_TABLE; /* V3M WS2.0 or later */ } break; + case RCAR_PRODUCT_V3H: + if (cut_ver == RCAR_CUT_ES10) { + index = NEW_API_TABLE3; /* V3H WS1.0 */ + } else { + index = NEW_API_TABLE3; /* */ + } + break; default: index = NEW_API_TABLE; /* assume that M3N and E3 */ break; diff --git a/plat/renesas/rcar/drivers/scif/scif.S b/plat/renesas/rcar/drivers/scif/scif.S index bb9bfef..5349478 100644 --- a/plat/renesas/rcar/drivers/scif/scif.S +++ b/plat/renesas/rcar/drivers/scif/scif.S @@ -50,7 +50,7 @@ #define SCIF0_BASE (0xE6E60000) /* SCIF-0 base address */ #define SCIF2_BASE (0xE6E88000) /* SCIF-2 base address */ -#if RCAR_LSI == RCAR_V3M /* V3M */ +#if (RCAR_LSI == RCAR_V3M) || (RCAR_LSI == RCAR_V3H) /* V3M/V3H */ #define SCIF_BASE SCIF0_BASE #define CPG_SMSTPCR CPG_SMSTPCR2 #define MSTP MSTP207 diff --git a/plat/renesas/rcar/include/bl2_dma_register.h b/plat/renesas/rcar/include/bl2_dma_register.h index 4bc9341..195515a 100644 --- a/plat/renesas/rcar/include/bl2_dma_register.h +++ b/plat/renesas/rcar/include/bl2_dma_register.h @@ -32,7 +32,7 @@ #ifndef BL2_DMA_REGISTER_H__ #define BL2_DMA_REGISTER_H__ -#if RCAR_LSI == RCAR_V3M /* V3M */ +#if (RCAR_LSI == RCAR_V3M) || (RCAR_LSI == RCAR_V3H) /* V3M/V3H */ #define DMACH 16 /* DMA CH setting (0/16/32) */ #else #define DMACH 0 /* DMA CH setting (0/16/32) */ diff --git a/plat/renesas/rcar/include/platform_def.h b/plat/renesas/rcar/include/platform_def.h index 59685c1..edaa59f 100644 --- a/plat/renesas/rcar/include/platform_def.h +++ b/plat/renesas/rcar/include/platform_def.h @@ -153,6 +153,10 @@ #define RCAR_SECRAM_BASE (0xE6300000) #define BL2_BASE (0xE6344000) #define BL2_LIMIT (0xE636E800) +#elif RCAR_LSI == RCAR_V3H +#define RCAR_SECRAM_BASE (0xEB200000) +#define BL2_BASE (0xEB244000) +#define BL2_LIMIT (0xEB26E800) #else #define RCAR_SECRAM_BASE (0xE6300000) #define BL2_BASE (0xE6304000) diff --git a/plat/renesas/rcar/pfc/V3H/pfc_init_v3h.c b/plat/renesas/rcar/pfc/V3H/pfc_init_v3h.c new file mode 100644 index 0000000..351747a --- /dev/null +++ b/plat/renesas/rcar/pfc/V3H/pfc_init_v3h.c @@ -0,0 +1,1196 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <stdint.h> /* for uint32_t */ +#include <mmio.h> +#include "pfc_init_v3h.h" + + +/* GPIO base address */ +#define GPIO_BASE (0xE6050000U) + +/* GPIO registers */ +#define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U) +#define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U) +#define GPIO_OUTDT0 (GPIO_BASE + 0x0008U) +#define GPIO_INDT0 (GPIO_BASE + 0x000CU) +#define GPIO_INTDT0 (GPIO_BASE + 0x0010U) +#define GPIO_INTCLR0 (GPIO_BASE + 0x0014U) +#define GPIO_INTMSK0 (GPIO_BASE + 0x0018U) +#define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU) +#define GPIO_POSNEG0 (GPIO_BASE + 0x0020U) +#define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U) +#define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U) +#define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U) +#define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU) +#define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U) +#define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U) +#define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U) +#define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU) +#define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U) +#define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U) +#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U) +#define GPIO_INDT1 (GPIO_BASE + 0x100CU) +#define GPIO_INTDT1 (GPIO_BASE + 0x1010U) +#define GPIO_INTCLR1 (GPIO_BASE + 0x1014U) +#define GPIO_INTMSK1 (GPIO_BASE + 0x1018U) +#define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU) +#define GPIO_POSNEG1 (GPIO_BASE + 0x1020U) +#define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U) +#define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U) +#define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U) +#define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU) +#define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U) +#define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U) +#define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U) +#define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU) +#define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U) +#define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U) +#define GPIO_OUTDT2 (GPIO_BASE + 0x2008U) +#define GPIO_INDT2 (GPIO_BASE + 0x200CU) +#define GPIO_INTDT2 (GPIO_BASE + 0x2010U) +#define GPIO_INTCLR2 (GPIO_BASE + 0x2014U) +#define GPIO_INTMSK2 (GPIO_BASE + 0x2018U) +#define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU) +#define GPIO_POSNEG2 (GPIO_BASE + 0x2020U) +#define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U) +#define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U) +#define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U) +#define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU) +#define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U) +#define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U) +#define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U) +#define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU) +#define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U) +#define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U) +#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U) +#define GPIO_INDT3 (GPIO_BASE + 0x300CU) +#define GPIO_INTDT3 (GPIO_BASE + 0x3010U) +#define GPIO_INTCLR3 (GPIO_BASE + 0x3014U) +#define GPIO_INTMSK3 (GPIO_BASE + 0x3018U) +#define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU) +#define GPIO_POSNEG3 (GPIO_BASE + 0x3020U) +#define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U) +#define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U) +#define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U) +#define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU) +#define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U) +#define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U) +#define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U) +#define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU) +#define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U) +#define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U) +#define GPIO_OUTDT4 (GPIO_BASE + 0x4008U) +#define GPIO_INDT4 (GPIO_BASE + 0x400CU) +#define GPIO_INTDT4 (GPIO_BASE + 0x4010U) +#define GPIO_INTCLR4 (GPIO_BASE + 0x4014U) +#define GPIO_INTMSK4 (GPIO_BASE + 0x4018U) +#define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU) +#define GPIO_POSNEG4 (GPIO_BASE + 0x4020U) +#define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U) +#define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U) +#define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U) +#define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU) +#define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U) +#define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U) +#define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U) +#define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU) +#define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U) +#define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U) +#define GPIO_OUTDT5 (GPIO_BASE + 0x5008U) +#define GPIO_INDT5 (GPIO_BASE + 0x500CU) +#define GPIO_INTDT5 (GPIO_BASE + 0x5010U) +#define GPIO_INTCLR5 (GPIO_BASE + 0x5014U) +#define GPIO_INTMSK5 (GPIO_BASE + 0x5018U) +#define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU) +#define GPIO_POSNEG5 (GPIO_BASE + 0x5020U) +#define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U) +#define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U) +#define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U) +#define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU) +#define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U) +#define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U) +#define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U) +#define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU) + +/* Pin functon base address */ +#define PFC_BASE (0xE6060000U) + +/* Pin functon registers */ +#define PFC_PMMR (PFC_BASE + 0x0000U) +#define PFC_GPSR0 (PFC_BASE + 0x0100U) +#define PFC_GPSR1 (PFC_BASE + 0x0104U) +#define PFC_GPSR2 (PFC_BASE + 0x0108U) +#define PFC_GPSR3 (PFC_BASE + 0x010CU) +#define PFC_GPSR4 (PFC_BASE + 0x0110U) +#define PFC_GPSR5 (PFC_BASE + 0x0114U) +#define PFC_IPSR0 (PFC_BASE + 0x0200U) +#define PFC_IPSR1 (PFC_BASE + 0x0204U) +#define PFC_IPSR2 (PFC_BASE + 0x0208U) +#define PFC_IPSR3 (PFC_BASE + 0x020CU) +#define PFC_IPSR4 (PFC_BASE + 0x0210U) +#define PFC_IPSR5 (PFC_BASE + 0x0214U) +#define PFC_IPSR6 (PFC_BASE + 0x0218U) +#define PFC_IPSR7 (PFC_BASE + 0x021CU) +#define PFC_IPSR8 (PFC_BASE + 0x0220U) +#define PFC_IPSR9 (PFC_BASE + 0x0224U) +#define PFC_IPSR10 (PFC_BASE + 0x0228U) +#define PFC_IOCTRL0 (PFC_BASE + 0x0300U) +#define PFC_IOCTRL1 (PFC_BASE + 0x0304U) +#define PFC_IOCTRL2 (PFC_BASE + 0x0308U) +#define PFC_IOCTRL3 (PFC_BASE + 0x030CU) +#define PFC_IOCTRL4 (PFC_BASE + 0x0310U) +#define PFC_IOCTRL5 (PFC_BASE + 0x0314U) +#define PFC_IOCTRL6 (PFC_BASE + 0x0318U) +#define PFC_IOCTRL7 (PFC_BASE + 0x031CU) +#define PFC_IOCTRL8 (PFC_BASE + 0x0320U) +#define PFC_IOCTRL9 (PFC_BASE + 0x0324U) +#define PFC_IOCTRL10 (PFC_BASE + 0x0328U) +#define PFC_IOCTRL11 (PFC_BASE + 0x032CU) +#define PFC_IOCTRL12 (PFC_BASE + 0x0330U) +#define PFC_IOCTRL13 (PFC_BASE + 0x0334U) +#define PFC_IOCTRL14 (PFC_BASE + 0x0338U) +#define PFC_IOCTRL15 (PFC_BASE + 0x033CU) +#define PFC_IOCTRL16 (PFC_BASE + 0x0340U) +#define PFC_IOCTRL17 (PFC_BASE + 0x0344U) +#define PFC_IOCTRL18 (PFC_BASE + 0x0348U) +#define PFC_IOCTRL19 (PFC_BASE + 0x034CU) +#define PFC_IOCTRL30 (PFC_BASE + 0x0380U) +#define PFC_IOCTRL31 (PFC_BASE + 0x0384U) +#define PFC_IOCTRL32 (PFC_BASE + 0x0388U) +#define PFC_IOCTRL33 (PFC_BASE + 0x038CU) +#define PFC_IOCTRL40 (PFC_BASE + 0x03C0U) +#define PFC_TSREG (PFC_BASE + 0x03E4U) +#define PFC_PUEN0 (PFC_BASE + 0x0400U) +#define PFC_PUEN1 (PFC_BASE + 0x0404U) +#define PFC_PUEN2 (PFC_BASE + 0x0408U) +#define PFC_PUEN3 (PFC_BASE + 0x040CU) +#define PFC_PUEN4 (PFC_BASE + 0x0410U) +#define PFC_PUD0 (PFC_BASE + 0x0440U) +#define PFC_PUD1 (PFC_BASE + 0x0444U) +#define PFC_PUD2 (PFC_BASE + 0x0448U) +#define PFC_PUD3 (PFC_BASE + 0x044CU) +#define PFC_PUD4 (PFC_BASE + 0x0450U) +#define PFC_MOD_SEL0 (PFC_BASE + 0x0500U) + +#define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) +#define GPSR0_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) +#define GPSR0_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) +#define GPSR0_DU_EXHSYNC_DU_HSYNC_A ((uint32_t)0U << 19U) +#define GPSR0_DU_DOTCLKOUT ((uint32_t)1U << 18U) +#define GPSR0_DU_DB7 ((uint32_t)1U << 17U) +#define GPSR0_DU_DB6 ((uint32_t)1U << 16U) +#define GPSR0_DU_DB5 ((uint32_t)1U << 15U) +#define GPSR0_DU_DB4 ((uint32_t)1U << 14U) +#define GPSR0_DU_DB3 ((uint32_t)1U << 13U) +#define GPSR0_DU_DB2 ((uint32_t)1U << 12U) +#define GPSR0_DU_DG7 ((uint32_t)1U << 11U) +#define GPSR0_DU_DG6 ((uint32_t)1U << 10U) +#define GPSR0_DU_DG5 ((uint32_t)1U << 9U) +#define GPSR0_DU_DG4 ((uint32_t)1U << 8U) +#define GPSR0_DU_DG3 ((uint32_t)1U << 7U) +#define GPSR0_DU_DG2 ((uint32_t)1U << 6U) +#define GPSR0_DU_DR7 ((uint32_t)1U << 5U) +#define GPSR0_DU_DR6 ((uint32_t)1U << 4U) +#define GPSR0_DU_DR5 ((uint32_t)1U << 3U) +#define GPSR0_DU_DR4 ((uint32_t)1U << 2U) +#define GPSR0_DU_DR3 ((uint32_t)1U << 1U) +#define GPSR0_DU_DR2 ((uint32_t)1U << 0U) +#define GPSR1_DIGRF_CLKOUT ((uint32_t)1U << 27U) +#define GPSR1_DIGRF_CLKIN ((uint32_t)1U << 26U) +#define GPSR1_CANFD_CLK_A ((uint32_t)1U << 25U) +#define GPSR1_CANFD1_RX ((uint32_t)1U << 24U) +#define GPSR1_CANFD1_TX ((uint32_t)1U << 23U) +#define GPSR1_CANFD0_RX_A ((uint32_t)1U << 22U) +#define GPSR1_CANFD0_TX_A ((uint32_t)1U << 21U) +#define GPSR1_AVB_AVTP_CAPTURE ((uint32_t)1U << 20U) +#define GPSR1_AVB_AVTP_MATCH ((uint32_t)1U << 19U) +#define GPSR1_AVB_LINK ((uint32_t)1U << 18U) +#define GPSR1_AVB_PHY_INT ((uint32_t)1U << 17U) +#define GPSR1_AVB_MAGIC ((uint32_t)1U << 16U) +#define GPSR1_AVB_MDC ((uint32_t)1U << 15U) +#define GPSR1_AVB_MDIO ((uint32_t)1U << 14U) +#define GPSR1_AVB_TXCREFCLK ((uint32_t)1U << 13U) +#define GPSR1_AVB_TD3 ((uint32_t)1U << 12U) +#define GPSR1_AVB_TD2 ((uint32_t)1U << 11U) +#define GPSR1_AVB_TD1 ((uint32_t)1U << 10U) +#define GPSR1_AVB_TD0 ((uint32_t)1U << 9U) +#define GPSR1_AVB_TXC ((uint32_t)1U << 8U) +#define GPSR1_AVB_TX_CTL ((uint32_t)1U << 7U) +#define GPSR1_AVB_RD3 ((uint32_t)1U << 6U) +#define GPSR1_AVB_RD2 ((uint32_t)1U << 5U) +#define GPSR1_AVB_RD1 ((uint32_t)1U << 4U) +#define GPSR1_AVB_RD0 ((uint32_t)1U << 3U) +#define GPSR1_AVB_RXC ((uint32_t)1U << 2U) +#define GPSR1_AVB_RX_CTL ((uint32_t)1U << 1U) +#define GPSR1_IRQ0 ((uint32_t)1U << 0U) +#define GPSR2_FSO_TOE ((uint32_t)1U << 29U) +#define GPSR2_FSO_CFE_1 ((uint32_t)1U << 28U) +#define GPSR2_FSO_CFE_0 ((uint32_t)1U << 27U) +#define GPSR2_SDA3 ((uint32_t)1U << 26U) +#define GPSR2_SCL3 ((uint32_t)1U << 25U) +#define GPSR2_MSIOF0_SS2 ((uint32_t)1U << 24U) +#define GPSR2_MSIOF0_SS1 ((uint32_t)1U << 23U) +#define GPSR2_MSIOF0_SYNC ((uint32_t)1U << 22U) +#define GPSR2_MSIOF0_SCK ((uint32_t)1U << 21U) +#define GPSR2_MSIOF0_TXD ((uint32_t)1U << 20U) +#define GPSR2_MSIOF0_RXD ((uint32_t)1U << 19U) +#define GPSR2_IRQ5 ((uint32_t)1U << 18U) +#define GPSR2_IRQ4 ((uint32_t)1U << 17U) +#define GPSR2_VI0_FIELD ((uint32_t)1U << 16U) +#define GPSR2_VI0_DATA11 ((uint32_t)1U << 15U) +#define GPSR2_VI0_DATA10 ((uint32_t)1U << 14U) +#define GPSR2_VI0_DATA9 ((uint32_t)1U << 13U) +#define GPSR2_VI0_DATA8 ((uint32_t)1U << 12U) +#define GPSR2_VI0_DATA7 ((uint32_t)1U << 11U) +#define GPSR2_VI0_DATA6 ((uint32_t)1U << 10U) +#define GPSR2_VI0_DATA5 ((uint32_t)1U << 9U) +#define GPSR2_VI0_DATA4 ((uint32_t)1U << 8U) +#define GPSR2_VI0_DATA3 ((uint32_t)1U << 7U) +#define GPSR2_VI0_DATA2 ((uint32_t)1U << 6U) +#define GPSR2_VI0_DATA1 ((uint32_t)1U << 5U) +#define GPSR2_VI0_DATA0 ((uint32_t)1U << 4U) +#define GPSR2_VI0_VSYNC ((uint32_t)1U << 3U) +#define GPSR2_VI0_HSYNC ((uint32_t)1U << 2U) +#define GPSR2_VI0_CLKENB ((uint32_t)1U << 1U) +#define GPSR2_VI0_CLK ((uint32_t)1U << 0U) +#define GPSR3_VI1_FIELD ((uint32_t)1U << 16U) +#define GPSR3_VI1_DATA11 ((uint32_t)1U << 15U) +#define GPSR3_VI1_DATA10 ((uint32_t)1U << 14U) +#define GPSR3_VI1_DATA9 ((uint32_t)1U << 13U) +#define GPSR3_VI1_DATA8 ((uint32_t)1U << 12U) +#define GPSR3_VI1_DATA7 ((uint32_t)1U << 11U) +#define GPSR3_VI1_DATA6 ((uint32_t)1U << 10U) +#define GPSR3_VI1_DATA5 ((uint32_t)1U << 9U) +#define GPSR3_VI1_DATA4 ((uint32_t)1U << 8U) +#define GPSR3_VI1_DATA3 ((uint32_t)1U << 7U) +#define GPSR3_VI1_DATA2 ((uint32_t)1U << 6U) +#define GPSR3_VI1_DATA1 ((uint32_t)1U << 5U) +#define GPSR3_VI1_DATA0 ((uint32_t)1U << 4U) +#define GPSR3_VI1_VSYNC ((uint32_t)1U << 3U) +#define GPSR3_VI1_HSYNC ((uint32_t)1U << 2U) +#define GPSR3_VI1_CLKENB ((uint32_t)1U << 1U) +#define GPSR3_VI1_CLK ((uint32_t)1U << 0U) +#define GPSR4_GETHER_LINK_A ((uint32_t)1U << 24U) +#define GPSR4_GETHER_PHY_INT_A ((uint32_t)1U << 23U) +#define GPSR4_GETHER_MAGIC ((uint32_t)1U << 22U) +#define GPSR4_GETHER_MDC_A ((uint32_t)1U << 21U) +#define GPSR4_GETHER_MDIO_A ((uint32_t)1U << 20U) +#define GPSR4_GETHER_TXCREFCLK_MEGA ((uint32_t)1U << 19U) +#define GPSR4_GETHER_TXCREFCLK ((uint32_t)1U << 18U) +#define GPSR4_GETHER_TD3 ((uint32_t)1U << 17U) +#define GPSR4_GETHER_TD2 ((uint32_t)1U << 16U) +#define GPSR4_GETHER_TD1 ((uint32_t)1U << 15U) +#define GPSR4_GETHER_TD0 ((uint32_t)1U << 14U) +#define GPSR4_GETHER_TXC ((uint32_t)1U << 13U) +#define GPSR4_GETHER_TX_CTL ((uint32_t)1U << 12U) +#define GPSR4_GETHER_RD3 ((uint32_t)1U << 11U) +#define GPSR4_GETHER_RD2 ((uint32_t)1U << 10U) +#define GPSR4_GETHER_RD1 ((uint32_t)1U << 9U) +#define GPSR4_GETHER_RD0 ((uint32_t)1U << 8U) +#define GPSR4_GETHER_RXC ((uint32_t)1U << 7U) +#define GPSR4_GETHER_RX_CTL ((uint32_t)1U << 6U) +#define GPSR4_SDA2 ((uint32_t)1U << 5U) +#define GPSR4_SCL2 ((uint32_t)1U << 4U) +#define GPSR4_SDA1 ((uint32_t)1U << 3U) +#define GPSR4_SCL1 ((uint32_t)1U << 2U) +#define GPSR4_SDA0 ((uint32_t)1U << 1U) +#define GPSR4_SCL0 ((uint32_t)1U << 0U) +#define GPSR5_RPC_INT ((uint32_t)1U << 14U) +#define GPSR5_RPC_WP ((uint32_t)1U << 13U) +#define GPSR5_RPC_RESET ((uint32_t)1U << 12U) +#define GPSR5_QSPI1_SSL ((uint32_t)1U << 11U) +#define GPSR5_QSPI1_IO3 ((uint32_t)1U << 10U) +#define GPSR5_QSPI1_IO2 ((uint32_t)1U << 9U) +#define GPSR5_QSPI1_MISO_IO1 ((uint32_t)1U << 8U) +#define GPSR5_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U) +#define GPSR5_QSPI1_SPCLK ((uint32_t)1U << 6U) +#define GPSR5_QSPI0_SSL ((uint32_t)1U << 5U) +#define GPSR5_QSPI0_IO3 ((uint32_t)1U << 4U) +#define GPSR5_QSPI0_IO2 ((uint32_t)1U << 3U) +#define GPSR5_QSPI0_MISO_IO1 ((uint32_t)1U << 2U) +#define GPSR5_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U) +#define GPSR5_QSPI0_SPCLK ((uint32_t)1U << 0U) + +#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) +#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) +#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) +#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) +#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) +#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) +#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) +#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) + +#define IOCTRL0_MASK (0x00000000U) +#define IOCTRL1_MASK (0x00000000U) +#define IOCTRL2_MASK (0x00000000U) +#define IOCTRL3_MASK (0x00000000U) +#define IOCTRL4_MASK (0x00000000U) +#define IOCTRL5_MASK (0x00000000U) +#define IOCTRL6_MASK (0x00000000U) +#define IOCTRL7_MASK (0x00000000U) +#define IOCTRL8_MASK (0x00000000U) +#define IOCTRL9_MASK (0x00000000U) +#define IOCTRL10_MASK (0x00000000U) +#define IOCTRL11_MASK (0x00000000U) +#define IOCTRL12_MASK (0x00000000U) +#define IOCTRL13_MASK (0x00000000U) +#define IOCTRL14_MASK (0x00000000U) +#define IOCTRL15_MASK (0x00000000U) +#define IOCTRL16_MASK (0x00000000U) +#define IOCTRL17_MASK (0x00000000U) +#define IOCTRL18_MASK (0x00000000U) +#define IOCTRL19_MASK (0x00000000U) + +#define IOCTRL0_DRV3_GETHER_DR2 ((uint32_t)1U << 30U) +#define IOCTRL0_DRV2_GETHER_DR2 ((uint32_t)1U << 29U) +#define IOCTRL0_DRV1_GETHER_DR2 ((uint32_t)1U << 28U) +#define IOCTRL0_DRV3_GETHER_DR3 ((uint32_t)1U << 26U) +#define IOCTRL0_DRV2_GETHER_DR3 ((uint32_t)1U << 25U) +#define IOCTRL0_DRV1_GETHER_DR3 ((uint32_t)1U << 24U) +#define IOCTRL0_DRV3_GETHER_DR4 ((uint32_t)1U << 22U) +#define IOCTRL0_DRV2_GETHER_DR4 ((uint32_t)1U << 21U) +#define IOCTRL0_DRV1_GETHER_DR4 ((uint32_t)1U << 20U) +#define IOCTRL0_DRV3_GETHER_DR5 ((uint32_t)1U << 18U) +#define IOCTRL0_DRV2_GETHER_DR5 ((uint32_t)1U << 17U) +#define IOCTRL0_DRV1_GETHER_DR5 ((uint32_t)1U << 16U) +#define IOCTRL0_DRV3_GETHER_DR6 ((uint32_t)1U << 14U) +#define IOCTRL0_DRV2_GETHER_DR6 ((uint32_t)1U << 13U) +#define IOCTRL0_DRV1_GETHER_DR6 ((uint32_t)1U << 12U) +#define IOCTRL0_DRV3_GETHER_DR7 ((uint32_t)1U << 10U) +#define IOCTRL0_DRV2_GETHER_DR7 ((uint32_t)1U << 9U) +#define IOCTRL0_DRV1_GETHER_DR7 ((uint32_t)1U << 8U) +#define IOCTRL0_DRV3_GETHER_DG2 ((uint32_t)1U << 6U) +#define IOCTRL0_DRV2_GETHER_DG2 ((uint32_t)1U << 5U) +#define IOCTRL0_DRV1_GETHER_DG2 ((uint32_t)1U << 4U) +#define IOCTRL0_DRV3_GETHER_DG3 ((uint32_t)1U << 2U) +#define IOCTRL0_DRV2_GETHER_DG3 ((uint32_t)1U << 1U) +#define IOCTRL0_DRV1_GETHER_DG3 ((uint32_t)1U << 0U) +#define IOCTRL1_DRV3_GETHER_DG4 ((uint32_t)1U << 30U) +#define IOCTRL1_DRV2_GETHER_DG4 ((uint32_t)1U << 29U) +#define IOCTRL1_DRV1_GETHER_DG4 ((uint32_t)1U << 28U) +#define IOCTRL1_DRV3_GETHER_DG5 ((uint32_t)1U << 26U) +#define IOCTRL1_DRV2_GETHER_DG5 ((uint32_t)1U << 25U) +#define IOCTRL1_DRV1_GETHER_DG5 ((uint32_t)1U << 24U) +#define IOCTRL1_DRV3_GETHER_DG6 ((uint32_t)1U << 22U) +#define IOCTRL1_DRV2_GETHER_DG6 ((uint32_t)1U << 21U) +#define IOCTRL1_DRV1_GETHER_DG6 ((uint32_t)1U << 20U) +#define IOCTRL1_DRV3_GETHER_DG7 ((uint32_t)1U << 18U) +#define IOCTRL1_DRV2_GETHER_DG7 ((uint32_t)1U << 17U) +#define IOCTRL1_DRV1_GETHER_DG7 ((uint32_t)1U << 16U) +#define IOCTRL1_DRV3_GETHER_DB2 ((uint32_t)1U << 14U) +#define IOCTRL1_DRV2_GETHER_DB2 ((uint32_t)1U << 13U) +#define IOCTRL1_DRV1_GETHER_DB2 ((uint32_t)1U << 12U) +#define IOCTRL1_DRV3_GETHER_DB3 ((uint32_t)1U << 10U) +#define IOCTRL1_DRV2_GETHER_DB3 ((uint32_t)1U << 9U) +#define IOCTRL1_DRV1_GETHER_DB3 ((uint32_t)1U << 8U) +#define IOCTRL1_DRV3_GETHER_DB4 ((uint32_t)1U << 6U) +#define IOCTRL1_DRV2_GETHER_DB4 ((uint32_t)1U << 5U) +#define IOCTRL1_DRV1_GETHER_DB4 ((uint32_t)1U << 4U) +#define IOCTRL1_DRV3_GETHER_DB5 ((uint32_t)1U << 2U) +#define IOCTRL1_DRV2_GETHER_DB5 ((uint32_t)1U << 1U) +#define IOCTRL1_DRV1_GETHER_DB5 ((uint32_t)1U << 0U) +#define IOCTRL2_DRV3_GETHER_DB6 ((uint32_t)1U << 30U) +#define IOCTRL2_DRV2_GETHER_DB6 ((uint32_t)1U << 29U) +#define IOCTRL2_DRV1_GETHER_DB6 ((uint32_t)1U << 28U) +#define IOCTRL2_DRV3_GETHER_DB7 ((uint32_t)1U << 26U) +#define IOCTRL2_DRV2_GETHER_DB7 ((uint32_t)1U << 25U) +#define IOCTRL2_DRV1_GETHER_DB7 ((uint32_t)1U << 24U) +#define IOCTRL2_DRV3_DU_DOTCLKOUT ((uint32_t)1U << 22U) +#define IOCTRL2_DRV2_DU_DOTCLKOUT ((uint32_t)1U << 21U) +#define IOCTRL2_DRV1_DU_DOTCLKOUT ((uint32_t)1U << 20U) +#define IOCTRL2_DRV3_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 18U) +#define IOCTRL2_DRV2_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 17U) +#define IOCTRL2_DRV1_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 16U) +#define IOCTRL2_DRV3_DU_EXHSYNC_DU_VSYNC ((uint32_t)1U << 14U) +#define IOCTRL2_DRV2_DU_EXHSYNC_DU_VSYNC ((uint32_t)1U << 13U) +#define IOCTRL2_DRV1_DU_EXHSYNC_DU_VSYNC ((uint32_t)1U << 12U) +#define IOCTRL2_DRV3_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 10U) +#define IOCTRL2_DRV2_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 9U) +#define IOCTRL2_DRV1_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 8U) +#define IOCTRL3_DRV2_DU_DOTCLKIN ((uint32_t)1U << 29U) +#define IOCTRL3_DRV1_DU_DOTCLKIN ((uint32_t)1U << 28U) +#define IOCTRL3_DRV3_PRESETOUT ((uint32_t)1U << 22U) +#define IOCTRL3_DRV2_PRESETOUT ((uint32_t)1U << 21U) +#define IOCTRL3_DRV1_PRESETOUT ((uint32_t)1U << 20U) +#define IOCTRL3_DRV2_FSCLKST ((uint32_t)1U << 1U) +#define IOCTRL3_DRV1_FSCLKST ((uint32_t)1U << 0U) +#define IOCTRL4_DRV2_FSCLKST2 ((uint32_t)1U << 29U) +#define IOCTRL4_DRV1_FSCLKST2 ((uint32_t)1U << 28U) +#define IOCTRL4_DRV3_IRQ0 ((uint32_t)1U << 22U) +#define IOCTRL4_DRV2_IRQ0 ((uint32_t)1U << 21U) +#define IOCTRL4_DRV1_IRQ0 ((uint32_t)1U << 20U) +#define IOCTRL4_DRV2_DCUTMS ((uint32_t)1U << 9U) +#define IOCTRL4_DRV1_DCUTMS ((uint32_t)1U << 8U) +#define IOCTRL4_DRV2_DCUTDO_LPDO ((uint32_t)1U << 1U) +#define IOCTRL4_DRV1_DCUTDO_LPDO ((uint32_t)1U << 0U) +#define IOCTRL5_DRV2_DCURDY_LPDCLKOUT ((uint32_t)1U << 29U) +#define IOCTRL5_DRV1_DCURDY_LPDCLKOUT ((uint32_t)1U << 28U) +#define IOCTRL5_DRV3_VI0_CLK ((uint32_t)1U << 26U) +#define IOCTRL5_DRV2_VI0_CLK ((uint32_t)1U << 25U) +#define IOCTRL5_DRV1_VI0_CLK ((uint32_t)1U << 24U) +#define IOCTRL5_DRV3_VI0_CLKENB ((uint32_t)1U << 22U) +#define IOCTRL5_DRV2_VI0_CLKENB ((uint32_t)1U << 21U) +#define IOCTRL5_DRV1_VI0_CLKENB ((uint32_t)1U << 20U) +#define IOCTRL5_DRV3_VI0_HSYNC ((uint32_t)1U << 18U) +#define IOCTRL5_DRV2_VI0_HSYNC ((uint32_t)1U << 17U) +#define IOCTRL5_DRV1_VI0_HSYNC ((uint32_t)1U << 16U) +#define IOCTRL5_DRV3_VI0_VSYNC ((uint32_t)1U << 14U) +#define IOCTRL5_DRV2_VI0_VSYNC ((uint32_t)1U << 13U) +#define IOCTRL5_DRV1_VI0_VSYNC ((uint32_t)1U << 12U) +#define IOCTRL5_DRV3_VI0_DATA0 ((uint32_t)1U << 10U) +#define IOCTRL5_DRV2_VI0_DATA0 ((uint32_t)1U << 9U) +#define IOCTRL5_DRV1_VI0_DATA0 ((uint32_t)1U << 8U) +#define IOCTRL5_DRV3_VI0_DATA1 ((uint32_t)1U << 6U) +#define IOCTRL5_DRV2_VI0_DATA1 ((uint32_t)1U << 5U) +#define IOCTRL5_DRV1_VI0_DATA1 ((uint32_t)1U << 4U) +#define IOCTRL5_DRV3_VI0_DATA2 ((uint32_t)1U << 2U) +#define IOCTRL5_DRV2_VI0_DATA2 ((uint32_t)1U << 1U) +#define IOCTRL5_DRV1_VI0_DATA2 ((uint32_t)1U << 0U) +#define IOCTRL6_DRV3_VI0_DATA3 ((uint32_t)1U << 30U) +#define IOCTRL6_DRV2_VI0_DATA3 ((uint32_t)1U << 29U) +#define IOCTRL6_DRV1_VI0_DATA3 ((uint32_t)1U << 28U) +#define IOCTRL6_DRV3_VI0_DATA4 ((uint32_t)1U << 26U) +#define IOCTRL6_DRV2_VI0_DATA4 ((uint32_t)1U << 25U) +#define IOCTRL6_DRV1_VI0_DATA4 ((uint32_t)1U << 24U) +#define IOCTRL6_DRV3_VI0_DATA5 ((uint32_t)1U << 22U) +#define IOCTRL6_DRV2_VI0_DATA5 ((uint32_t)1U << 21U) +#define IOCTRL6_DRV1_VI0_DATA5 ((uint32_t)1U << 20U) +#define IOCTRL6_DRV3_VI0_DATA6 ((uint32_t)1U << 18U) +#define IOCTRL6_DRV2_VI0_DATA6 ((uint32_t)1U << 17U) +#define IOCTRL6_DRV1_VI0_DATA6 ((uint32_t)1U << 16U) +#define IOCTRL6_DRV3_VI0_DATA7 ((uint32_t)1U << 14U) +#define IOCTRL6_DRV2_VI0_DATA7 ((uint32_t)1U << 13U) +#define IOCTRL6_DRV1_VI0_DATA7 ((uint32_t)1U << 12U) +#define IOCTRL6_DRV3_VI0_DATA8 ((uint32_t)1U << 10U) +#define IOCTRL6_DRV2_VI0_DATA8 ((uint32_t)1U << 9U) +#define IOCTRL6_DRV1_VI0_DATA8 ((uint32_t)1U << 8U) +#define IOCTRL6_DRV3_VI0_DATA9 ((uint32_t)1U << 6U) +#define IOCTRL6_DRV2_VI0_DATA9 ((uint32_t)1U << 5U) +#define IOCTRL6_DRV1_VI0_DATA9 ((uint32_t)1U << 4U) +#define IOCTRL6_DRV3_VI0_DATA10 ((uint32_t)1U << 2U) +#define IOCTRL6_DRV2_VI0_DATA10 ((uint32_t)1U << 1U) +#define IOCTRL6_DRV1_VI0_DATA10 ((uint32_t)1U << 0U) +#define IOCTRL7_DRV3_VI0_DATA11 ((uint32_t)1U << 30U) +#define IOCTRL7_DRV2_VI0_DATA11 ((uint32_t)1U << 29U) +#define IOCTRL7_DRV1_VI0_DATA11 ((uint32_t)1U << 28U) +#define IOCTRL7_DRV3_VI0_FIELD ((uint32_t)1U << 26U) +#define IOCTRL7_DRV2_VI0_FIELD ((uint32_t)1U << 25U) +#define IOCTRL7_DRV1_VI0_FIELD ((uint32_t)1U << 24U) +#define IOCTRL7_DRV3_VI1_CLK ((uint32_t)1U << 22U) +#define IOCTRL7_DRV2_VI1_CLK ((uint32_t)1U << 21U) +#define IOCTRL7_DRV1_VI1_CLK ((uint32_t)1U << 20U) +#define IOCTRL7_DRV3_VI1_CLKENB ((uint32_t)1U << 18U) +#define IOCTRL7_DRV2_VI1_CLKENB ((uint32_t)1U << 17U) +#define IOCTRL7_DRV1_VI1_CLKENB ((uint32_t)1U << 16U) +#define IOCTRL7_DRV3_VI1_HSYNC ((uint32_t)1U << 14U) +#define IOCTRL7_DRV2_VI1_HSYNC ((uint32_t)1U << 13U) +#define IOCTRL7_DRV1_VI1_HSYNC ((uint32_t)1U << 12U) +#define IOCTRL7_DRV3_VI1_VSYNC ((uint32_t)1U << 10U) +#define IOCTRL7_DRV2_VI1_VSYNC ((uint32_t)1U << 9U) +#define IOCTRL7_DRV1_VI1_VSYNC ((uint32_t)1U << 8U) +#define IOCTRL7_DRV3_VI1_DATA0 ((uint32_t)1U << 6U) +#define IOCTRL7_DRV2_VI1_DATA0 ((uint32_t)1U << 5U) +#define IOCTRL7_DRV1_VI1_DATA0 ((uint32_t)1U << 4U) +#define IOCTRL7_DRV3_VI1_DATA1 ((uint32_t)1U << 2U) +#define IOCTRL7_DRV2_VI1_DATA1 ((uint32_t)1U << 1U) +#define IOCTRL7_DRV1_VI1_DATA1 ((uint32_t)1U << 0U) +#define IOCTRL8_DRV3_VI1_DATA2 ((uint32_t)1U << 30U) +#define IOCTRL8_DRV2_VI1_DATA2 ((uint32_t)1U << 29U) +#define IOCTRL8_DRV1_VI1_DATA2 ((uint32_t)1U << 28U) +#define IOCTRL8_DRV3_VI1_DATA3 ((uint32_t)1U << 26U) +#define IOCTRL8_DRV2_VI1_DATA3 ((uint32_t)1U << 25U) +#define IOCTRL8_DRV1_VI1_DATA3 ((uint32_t)1U << 24U) +#define IOCTRL8_DRV3_VI1_DATA4 ((uint32_t)1U << 22U) +#define IOCTRL8_DRV2_VI1_DATA4 ((uint32_t)1U << 21U) +#define IOCTRL8_DRV1_VI1_DATA4 ((uint32_t)1U << 20U) +#define IOCTRL8_DRV3_VI1_DATA5 ((uint32_t)1U << 18U) +#define IOCTRL8_DRV2_VI1_DATA5 ((uint32_t)1U << 17U) +#define IOCTRL8_DRV1_VI1_DATA5 ((uint32_t)1U << 16U) +#define IOCTRL8_DRV3_VI1_DATA6 ((uint32_t)1U << 14U) +#define IOCTRL8_DRV2_VI1_DATA6 ((uint32_t)1U << 13U) +#define IOCTRL8_DRV1_VI1_DATA6 ((uint32_t)1U << 12U) +#define IOCTRL8_DRV3_VI1_DATA7 ((uint32_t)1U << 10U) +#define IOCTRL8_DRV2_VI1_DATA7 ((uint32_t)1U << 9U) +#define IOCTRL8_DRV1_VI1_DATA7 ((uint32_t)1U << 8U) +#define IOCTRL8_DRV3_VI1_DATA8 ((uint32_t)1U << 6U) +#define IOCTRL8_DRV2_VI1_DATA8 ((uint32_t)1U << 5U) +#define IOCTRL8_DRV1_VI1_DATA8 ((uint32_t)1U << 4U) +#define IOCTRL8_DRV3_VI1_DATA9 ((uint32_t)1U << 2U) +#define IOCTRL8_DRV2_VI1_DATA9 ((uint32_t)1U << 1U) +#define IOCTRL8_DRV1_VI1_DATA9 ((uint32_t)1U << 0U) +#define IOCTRL9_DRV3_VI1_DATA10 ((uint32_t)1U << 30U) +#define IOCTRL9_DRV2_VI1_DATA10 ((uint32_t)1U << 29U) +#define IOCTRL9_DRV1_VI1_DATA10 ((uint32_t)1U << 28U) +#define IOCTRL9_DRV3_VI1_DATA11 ((uint32_t)1U << 26U) +#define IOCTRL9_DRV2_VI1_DATA11 ((uint32_t)1U << 25U) +#define IOCTRL9_DRV1_VI1_DATA11 ((uint32_t)1U << 24U) +#define IOCTRL9_DRV3_VI1_FIELD ((uint32_t)1U << 22U) +#define IOCTRL9_DRV2_VI1_FIELD ((uint32_t)1U << 21U) +#define IOCTRL9_DRV1_VI1_FIELD ((uint32_t)1U << 20U) +#define IOCTRL9_DRV3_VI1_SCL0 ((uint32_t)1U << 18U) +#define IOCTRL9_DRV2_VI1_SCL0 ((uint32_t)1U << 17U) +#define IOCTRL9_DRV1_VI1_SCL0 ((uint32_t)1U << 16U) +#define IOCTRL9_DRV3_VI1_SDA0 ((uint32_t)1U << 14U) +#define IOCTRL9_DRV2_VI1_SDA0 ((uint32_t)1U << 13U) +#define IOCTRL9_DRV1_VI1_SDA0 ((uint32_t)1U << 12U) +#define IOCTRL9_DRV3_VI1_SCL1 ((uint32_t)1U << 10U) +#define IOCTRL9_DRV2_VI1_SCL1 ((uint32_t)1U << 9U) +#define IOCTRL9_DRV1_VI1_SCL1 ((uint32_t)1U << 8U) +#define IOCTRL9_DRV3_VI1_SDA1 ((uint32_t)1U << 6U) +#define IOCTRL9_DRV2_VI1_SDA1 ((uint32_t)1U << 5U) +#define IOCTRL9_DRV1_VI1_SDA1 ((uint32_t)1U << 4U) +#define IOCTRL9_DRV3_VI1_SCL2 ((uint32_t)1U << 2U) +#define IOCTRL9_DRV2_VI1_SCL2 ((uint32_t)1U << 1U) +#define IOCTRL9_DRV1_VI1_SCL2 ((uint32_t)1U << 0U) +#define IOCTRL10_DRV3_VI1_SDA2 ((uint32_t)1U << 30U) +#define IOCTRL10_DRV2_VI1_SDA2 ((uint32_t)1U << 29U) +#define IOCTRL10_DRV1_VI1_SDA2 ((uint32_t)1U << 28U) +#define IOCTRL10_DRV3_AVB_RX_CTL ((uint32_t)1U << 26U) +#define IOCTRL10_DRV2_AVB_RX_CTL ((uint32_t)1U << 25U) +#define IOCTRL10_DRV1_AVB_RX_CTL ((uint32_t)1U << 24U) +#define IOCTRL10_DRV3_AVB_RX_RXC ((uint32_t)1U << 22U) +#define IOCTRL10_DRV2_AVB_RX_RXC ((uint32_t)1U << 21U) +#define IOCTRL10_DRV1_AVB_RX_RXC ((uint32_t)1U << 20U) +#define IOCTRL10_DRV3_AVB_RX_RD0 ((uint32_t)1U << 18U) +#define IOCTRL10_DRV2_AVB_RX_RD0 ((uint32_t)1U << 17U) +#define IOCTRL10_DRV1_AVB_RX_RD0 ((uint32_t)1U << 16U) +#define IOCTRL10_DRV3_AVB_RX_RD1 ((uint32_t)1U << 14U) +#define IOCTRL10_DRV2_AVB_RX_RD1 ((uint32_t)1U << 13U) +#define IOCTRL10_DRV1_AVB_RX_RD1 ((uint32_t)1U << 12U) +#define IOCTRL10_DRV3_AVB_RX_RD2 ((uint32_t)1U << 10U) +#define IOCTRL10_DRV2_AVB_RX_RD2 ((uint32_t)1U << 9U) +#define IOCTRL10_DRV1_AVB_RX_RD2 ((uint32_t)1U << 8U) +#define IOCTRL10_DRV3_AVB_RX_RD3 ((uint32_t)1U << 6U) +#define IOCTRL10_DRV2_AVB_RX_RD3 ((uint32_t)1U << 5U) +#define IOCTRL10_DRV1_AVB_RX_RD3 ((uint32_t)1U << 4U) +#define IOCTRL10_DRV3_AVB_TX_CTL ((uint32_t)1U << 2U) +#define IOCTRL10_DRV2_AVB_TX_CTL ((uint32_t)1U << 1U) +#define IOCTRL10_DRV1_AVB_TX_CTL ((uint32_t)1U << 0U) +#define IOCTRL11_DRV3_AVB_TXC ((uint32_t)1U << 30U) +#define IOCTRL11_DRV2_AVB_TXC ((uint32_t)1U << 29U) +#define IOCTRL11_DRV1_AVB_TXC ((uint32_t)1U << 28U) +#define IOCTRL11_DRV3_AVB_TD0 ((uint32_t)1U << 26U) +#define IOCTRL11_DRV2_AVB_TD0 ((uint32_t)1U << 25U) +#define IOCTRL11_DRV1_AVB_TD0 ((uint32_t)1U << 24U) +#define IOCTRL11_DRV3_AVB_TD1 ((uint32_t)1U << 22U) +#define IOCTRL11_DRV2_AVB_TD1 ((uint32_t)1U << 21U) +#define IOCTRL11_DRV1_AVB_TD1 ((uint32_t)1U << 20U) +#define IOCTRL11_DRV3_AVB_TD2 ((uint32_t)1U << 18U) +#define IOCTRL11_DRV2_AVB_TD2 ((uint32_t)1U << 17U) +#define IOCTRL11_DRV1_AVB_TD2 ((uint32_t)1U << 16U) +#define IOCTRL11_DRV3_AVB_TD3 ((uint32_t)1U << 14U) +#define IOCTRL11_DRV2_AVB_TD3 ((uint32_t)1U << 13U) +#define IOCTRL11_DRV1_AVB_TD3 ((uint32_t)1U << 12U) +#define IOCTRL11_DRV3_AVB_TXCREFCLK ((uint32_t)1U << 10U) +#define IOCTRL11_DRV2_AVB_TXCREFCLK ((uint32_t)1U << 9U) +#define IOCTRL11_DRV1_AVB_TXCREFCLK ((uint32_t)1U << 8U) +#define IOCTRL11_DRV3_AVB_MDIO ((uint32_t)1U << 6U) +#define IOCTRL11_DRV2_AVB_MDIO ((uint32_t)1U << 5U) +#define IOCTRL11_DRV1_AVB_MDIO ((uint32_t)1U << 4U) +#define IOCTRL11_DRV3_AVB_MDC ((uint32_t)1U << 2U) +#define IOCTRL11_DRV2_AVB_MDC ((uint32_t)1U << 1U) +#define IOCTRL11_DRV1_AVB_MDC ((uint32_t)1U << 0U) +#define IOCTRL12_DRV3_AVB_MAGIC ((uint32_t)1U << 30U) +#define IOCTRL12_DRV2_AVB_MAGIC ((uint32_t)1U << 29U) +#define IOCTRL12_DRV1_AVB_MAGIC ((uint32_t)1U << 28U) +#define IOCTRL12_DRV3_AVB_PHY_INT ((uint32_t)1U << 26U) +#define IOCTRL12_DRV2_AVB_PHY_INT ((uint32_t)1U << 25U) +#define IOCTRL12_DRV1_AVB_PHY_INT ((uint32_t)1U << 24U) +#define IOCTRL12_DRV3_AVB_LINK ((uint32_t)1U << 22U) +#define IOCTRL12_DRV2_AVB_LINK ((uint32_t)1U << 21U) +#define IOCTRL12_DRV1_AVB_LINK ((uint32_t)1U << 20U) +#define IOCTRL12_DRV3_AVB_AVTP_MATCH ((uint32_t)1U << 18U) +#define IOCTRL12_DRV2_AVB_AVTP_MATCH ((uint32_t)1U << 17U) +#define IOCTRL12_DRV1_AVB_AVTP_MATCH ((uint32_t)1U << 16U) +#define IOCTRL12_DRV3_AVB_AVTP_CAPTURE ((uint32_t)1U << 14U) +#define IOCTRL12_DRV2_AVB_AVTP_CAPTURE ((uint32_t)1U << 13U) +#define IOCTRL12_DRV1_AVB_AVTP_CAPTURE ((uint32_t)1U << 12U) +#define IOCTRL12_DRV3_GETHER_RX_CTL ((uint32_t)1U << 10U) +#define IOCTRL12_DRV2_GETHER_RX_CTL ((uint32_t)1U << 9U) +#define IOCTRL12_DRV1_GETHER_RX_CTL ((uint32_t)1U << 8U) +#define IOCTRL12_DRV3_GETHER_RXC ((uint32_t)1U << 6U) +#define IOCTRL12_DRV2_GETHER_RXC ((uint32_t)1U << 5U) +#define IOCTRL12_DRV1_GETHER_RXC ((uint32_t)1U << 4U) +#define IOCTRL12_DRV3_GETHER_RD0 ((uint32_t)1U << 2U) +#define IOCTRL12_DRV2_GETHER_RD0 ((uint32_t)1U << 1U) +#define IOCTRL12_DRV1_GETHER_RD0 ((uint32_t)1U << 0U) +#define IOCTRL13_DRV3_GETHER_RD1 ((uint32_t)1U << 30U) +#define IOCTRL13_DRV2_GETHER_RD1 ((uint32_t)1U << 29U) +#define IOCTRL13_DRV1_GETHER_RD1 ((uint32_t)1U << 28U) +#define IOCTRL13_DRV3_GETHER_RD2 ((uint32_t)1U << 26U) +#define IOCTRL13_DRV2_GETHER_RD2 ((uint32_t)1U << 25U) +#define IOCTRL13_DRV1_GETHER_RD2 ((uint32_t)1U << 24U) +#define IOCTRL13_DRV3_GETHER_RD3 ((uint32_t)1U << 22U) +#define IOCTRL13_DRV2_GETHER_RD3 ((uint32_t)1U << 21U) +#define IOCTRL13_DRV1_GETHER_RD3 ((uint32_t)1U << 20U) +#define IOCTRL13_DRV3_GETHER_TX_CTL ((uint32_t)1U << 18U) +#define IOCTRL13_DRV2_GETHER_TX_CTL ((uint32_t)1U << 17U) +#define IOCTRL13_DRV1_GETHER_TX_CTL ((uint32_t)1U << 16U) +#define IOCTRL13_DRV3_GETHER_TXC ((uint32_t)1U << 14U) +#define IOCTRL13_DRV2_GETHER_TXC ((uint32_t)1U << 13U) +#define IOCTRL13_DRV1_GETHER_TXC ((uint32_t)1U << 12U) +#define IOCTRL13_DRV3_GETHER_TD0 ((uint32_t)1U << 10U) +#define IOCTRL13_DRV2_GETHER_TD0 ((uint32_t)1U << 9U) +#define IOCTRL13_DRV1_GETHER_TD0 ((uint32_t)1U << 8U) +#define IOCTRL13_DRV3_GETHER_TD1 ((uint32_t)1U << 6U) +#define IOCTRL13_DRV2_GETHER_TD1 ((uint32_t)1U << 5U) +#define IOCTRL13_DRV1_GETHER_TD1 ((uint32_t)1U << 4U) +#define IOCTRL13_DRV3_GETHER_TD2 ((uint32_t)1U << 2U) +#define IOCTRL13_DRV2_GETHER_TD2 ((uint32_t)1U << 1U) +#define IOCTRL13_DRV1_GETHER_TD2 ((uint32_t)1U << 0U) +#define IOCTRL13_DRV3_GETHER_TD3 ((uint32_t)1U << 30U) +#define IOCTRL13_DRV2_GETHER_TD3 ((uint32_t)1U << 29U) +#define IOCTRL13_DRV1_GETHER_TD3 ((uint32_t)1U << 28U) +#define IOCTRL14_DRV3_GETHER_TXCREFCLK ((uint32_t)1U << 26U) +#define IOCTRL14_DRV2_GETHER_TXCREFCLK ((uint32_t)1U << 25U) +#define IOCTRL14_DRV1_GETHER_TXCREFCLK ((uint32_t)1U << 24U) +#define IOCTRL14_DRV3_GETHER_TXCREFCLK_MEGA ((uint32_t)1U << 22U) +#define IOCTRL14_DRV2_GETHER_TXCREFCLK_MEGA ((uint32_t)1U << 21U) +#define IOCTRL14_DRV1_GETHER_TXCREFCLK_MEGA ((uint32_t)1U << 20U) +#define IOCTRL14_DRV3_GETHER_MDIO ((uint32_t)1U << 18U) +#define IOCTRL14_DRV2_GETHER_MDIO ((uint32_t)1U << 17U) +#define IOCTRL14_DRV1_GETHER_MDIO ((uint32_t)1U << 16U) +#define IOCTRL14_DRV3_GETHER_MDC ((uint32_t)1U << 14U) +#define IOCTRL14_DRV2_GETHER_MDC ((uint32_t)1U << 13U) +#define IOCTRL14_DRV1_GETHER_MDC ((uint32_t)1U << 12U) +#define IOCTRL14_DRV3_GETHER_MAGIC ((uint32_t)1U << 10U) +#define IOCTRL14_DRV2_GETHER_MAGIC ((uint32_t)1U << 9U) +#define IOCTRL14_DRV1_GETHER_MAGIC ((uint32_t)1U << 8U) +#define IOCTRL14_DRV3_GETHER_PHY_INT ((uint32_t)1U << 6U) +#define IOCTRL14_DRV2_GETHER_PHY_INT ((uint32_t)1U << 5U) +#define IOCTRL14_DRV1_GETHER_PHY_INT ((uint32_t)1U << 4U) +#define IOCTRL14_DRV3_GETHER_LINK ((uint32_t)1U << 2U) +#define IOCTRL14_DRV2_GETHER_LINK ((uint32_t)1U << 1U) +#define IOCTRL14_DRV1_GETHER_LINK ((uint32_t)1U << 0U) +#define IOCTRL15_DRV3_CANFD0_TX ((uint32_t)1U << 30U) +#define IOCTRL15_DRV2_CANFD0_TX ((uint32_t)1U << 29U) +#define IOCTRL15_DRV1_CANFD0_TX ((uint32_t)1U << 28U) +#define IOCTRL15_DRV3_CANFD0_RX ((uint32_t)1U << 26U) +#define IOCTRL15_DRV2_CANFD0_RX ((uint32_t)1U << 25U) +#define IOCTRL15_DRV1_CANFD0_RX ((uint32_t)1U << 24U) +#define IOCTRL15_DRV3_CANFD1_TX ((uint32_t)1U << 22U) +#define IOCTRL15_DRV2_CANFD1_TX ((uint32_t)1U << 21U) +#define IOCTRL15_DRV1_CANFD1_TX ((uint32_t)1U << 20U) +#define IOCTRL15_DRV3_CANFD1_RX ((uint32_t)1U << 18U) +#define IOCTRL15_DRV2_CANFD1_RX ((uint32_t)1U << 17U) +#define IOCTRL15_DRV1_CANFD1_RX ((uint32_t)1U << 16U) +#define IOCTRL15_DRV3_CAN_CLK ((uint32_t)1U << 14U) +#define IOCTRL15_DRV2_CAN_CLK ((uint32_t)1U << 13U) +#define IOCTRL15_DRV1_CAN_CLK ((uint32_t)1U << 12U) +#define IOCTRL15_DRV2_QSPI0_SPCLK ((uint32_t)1U << 9U) +#define IOCTRL15_DRV1_QSPI0_SPCLK ((uint32_t)1U << 8U) +#define IOCTRL15_DRV2_QSPI0_MOSI_IO0 ((uint32_t)1U << 5U) +#define IOCTRL15_DRV1_QSPI0_MOSI_IO0 ((uint32_t)1U << 4U) +#define IOCTRL15_DRV2_QSPI0_MOSI_IO1 ((uint32_t)1U << 1U) +#define IOCTRL15_DRV1_QSPI0_MOSI_IO1 ((uint32_t)1U << 0U) +#define IOCTRL16_DRV2_QSPI0_MOSI_IO2 ((uint32_t)1U << 29U) +#define IOCTRL16_DRV1_QSPI0_MOSI_IO2 ((uint32_t)1U << 28U) +#define IOCTRL16_DRV2_QSPI0_MOSI_IO3 ((uint32_t)1U << 25U) +#define IOCTRL16_DRV1_QSPI0_MOSI_IO3 ((uint32_t)1U << 24U) +#define IOCTRL16_DRV2_QSPI0_SSL ((uint32_t)1U << 21U) +#define IOCTRL16_DRV1_QSPI0_SSL ((uint32_t)1U << 20U) +#define IOCTRL16_DRV2_QSPI1_SPCLK ((uint32_t)1U << 17U) +#define IOCTRL16_DRV1_QSPI1_SPCLK ((uint32_t)1U << 16U) +#define IOCTRL16_DRV2_QSPI1_MOSI_IO0 ((uint32_t)1U << 13U) +#define IOCTRL16_DRV1_QSPI1_MOSI_IO0 ((uint32_t)1U << 12U) +#define IOCTRL16_DRV2_QSPI1_MOSI_IO1 ((uint32_t)1U << 9U) +#define IOCTRL16_DRV1_QSPI1_MOSI_IO1 ((uint32_t)1U << 8U) +#define IOCTRL16_DRV2_QSPI1_IO2 ((uint32_t)1U << 5U) +#define IOCTRL16_DRV1_QSPI1_IO2 ((uint32_t)1U << 4U) +#define IOCTRL16_DRV2_QSPI1_IO3 ((uint32_t)1U << 1U) +#define IOCTRL16_DRV1_QSPI1_IO3 ((uint32_t)1U << 0U) +#define IOCTRL17_DRV2_QSPI1_SSL ((uint32_t)1U << 29U) +#define IOCTRL17_DRV1_QSPI1_SSL ((uint32_t)1U << 28U) +#define IOCTRL17_DRV2_QSPI1_RPC_RESET ((uint32_t)1U << 25U) +#define IOCTRL17_DRV1_QSPI1_RPC_RESET ((uint32_t)1U << 24U) +#define IOCTRL17_DRV2_RPC_WP ((uint32_t)1U << 21U) +#define IOCTRL17_DRV1_RPC_WP ((uint32_t)1U << 20U) +#define IOCTRL17_DRV2_RPC_INT ((uint32_t)1U << 17U) +#define IOCTRL17_DRV1_RPC_INT ((uint32_t)1U << 16U) +#define IOCTRL17_DRV2_DIGRF_CLKIN ((uint32_t)1U << 13U) +#define IOCTRL17_DRV1_DIGRF_CLKIN ((uint32_t)1U << 12U) +#define IOCTRL17_DRV2_DIGRF_CLKOUT ((uint32_t)1U << 9U) +#define IOCTRL17_DRV1_DIGRF_CLKOUT ((uint32_t)1U << 8U) +#define IOCTRL17_DRV2_RPC_IRQ4 ((uint32_t)1U << 5U) +#define IOCTRL17_DRV1_RPC_IRQ4 ((uint32_t)1U << 4U) +#define IOCTRL17_DRV2_RPC_IRQ5 ((uint32_t)1U << 1U) +#define IOCTRL17_DRV1_RPC_IRQ5 ((uint32_t)1U << 0U) +#define IOCTRL18_DRV3_SCL3 ((uint32_t)1U << 30U) +#define IOCTRL18_DRV2_SCL3 ((uint32_t)1U << 29U) +#define IOCTRL18_DRV1_SCL3 ((uint32_t)1U << 28U) +#define IOCTRL18_DRV3_SDA3 ((uint32_t)1U << 26U) +#define IOCTRL18_DRV2_SDA3 ((uint32_t)1U << 25U) +#define IOCTRL18_DRV1_SDA3 ((uint32_t)1U << 24U) +#define IOCTRL18_DRV3_MSIOF0_RXD ((uint32_t)1U << 22U) +#define IOCTRL18_DRV2_MSIOF0_RXD ((uint32_t)1U << 21U) +#define IOCTRL18_DRV1_MSIOF0_RXD ((uint32_t)1U << 20U) +#define IOCTRL18_DRV3_MSIOF0_TXD ((uint32_t)1U << 18U) +#define IOCTRL18_DRV2_MSIOF0_TXD ((uint32_t)1U << 17U) +#define IOCTRL18_DRV1_MSIOF0_TXD ((uint32_t)1U << 16U) +#define IOCTRL18_DRV3_MSIOF0_SCK ((uint32_t)1U << 14U) +#define IOCTRL18_DRV2_MSIOF0_SCK ((uint32_t)1U << 13U) +#define IOCTRL18_DRV1_MSIOF0_SCK ((uint32_t)1U << 12U) +#define IOCTRL18_DRV3_MSIOF0_SYNC ((uint32_t)1U << 10U) +#define IOCTRL18_DRV2_MSIOF0_SYNC ((uint32_t)1U << 9U) +#define IOCTRL18_DRV1_MSIOF0_SYNC ((uint32_t)1U << 8U) +#define IOCTRL18_DRV3_MSIOF0_SS1 ((uint32_t)1U << 6U) +#define IOCTRL18_DRV2_MSIOF0_SS1 ((uint32_t)1U << 5U) +#define IOCTRL18_DRV1_MSIOF0_SS1 ((uint32_t)1U << 4U) +#define IOCTRL18_DRV3_MSIOF0_SS2 ((uint32_t)1U << 2U) +#define IOCTRL18_DRV2_MSIOF0_SS2 ((uint32_t)1U << 1U) +#define IOCTRL18_DRV1_MSIOF0_SS2 ((uint32_t)1U << 0U) +#define IOCTRL19_DRV3_FSO_CFE_0 ((uint32_t)1U << 30U) +#define IOCTRL19_DRV2_FSO_CFE_0 ((uint32_t)1U << 29U) +#define IOCTRL19_DRV1_FSO_CFE_0 ((uint32_t)1U << 28U) +#define IOCTRL19_DRV3_FSO_CFE_1 ((uint32_t)1U << 26U) +#define IOCTRL19_DRV2_FSO_CFE_1 ((uint32_t)1U << 25U) +#define IOCTRL19_DRV1_FSO_CFE_1 ((uint32_t)1U << 24U) +#define IOCTRL19_DRV3_FSO_TOE ((uint32_t)1U << 22U) +#define IOCTRL19_DRV2_FSO_TOE ((uint32_t)1U << 21U) +#define IOCTRL19_DRV1_FSO_TOE ((uint32_t)1U << 20U) + +#define IOCTRL30_POC_VI0_DATA5 ((uint32_t)1U << 31U) +#define IOCTRL30_POC_VI0_DATA4 ((uint32_t)1U << 30U) +#define IOCTRL30_POC_VI0_DATA3 ((uint32_t)1U << 29U) +#define IOCTRL30_POC_VI0_DATA2 ((uint32_t)1U << 28U) +#define IOCTRL30_POC_VI0_DATA1 ((uint32_t)1U << 27U) +#define IOCTRL30_POC_VI0_DATA0 ((uint32_t)1U << 26U) +#define IOCTRL30_POC_VI0_VSYNC_N ((uint32_t)1U << 25U) +#define IOCTRL30_POC_VI0_HSYNC_N ((uint32_t)1U << 24U) +#define IOCTRL30_POC_VI0_CLKENB ((uint32_t)1U << 23U) +#define IOCTRL30_POC_VI0_CLK ((uint32_t)1U << 22U) +#define IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) +#define IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) +#define IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) +#define IOCTRL30_POC_DU_DOTCLKOUT ((uint32_t)1U << 18U) +#define IOCTRL30_POC_DU_DB7 ((uint32_t)1U << 17U) +#define IOCTRL30_POC_DU_DB6 ((uint32_t)1U << 16U) +#define IOCTRL30_POC_DU_DB5 ((uint32_t)1U << 15U) +#define IOCTRL30_POC_DU_DB4 ((uint32_t)1U << 14U) +#define IOCTRL30_POC_DU_DB3 ((uint32_t)1U << 13U) +#define IOCTRL30_POC_DU_DB2 ((uint32_t)1U << 12U) +#define IOCTRL30_POC_DU_DG7 ((uint32_t)1U << 11U) +#define IOCTRL30_POC_DU_DG6 ((uint32_t)1U << 10U) +#define IOCTRL30_POC_DU_DG5 ((uint32_t)1U << 9U) +#define IOCTRL30_POC_DU_DG4 ((uint32_t)1U << 8U) +#define IOCTRL30_POC_DU_DG3 ((uint32_t)1U << 7U) +#define IOCTRL30_POC_DU_DG2 ((uint32_t)1U << 6U) +#define IOCTRL30_POC_DU_DR7 ((uint32_t)1U << 5U) +#define IOCTRL30_POC_DU_DR6 ((uint32_t)1U << 4U) +#define IOCTRL30_POC_DU_DR5 ((uint32_t)1U << 3U) +#define IOCTRL30_POC_DU_DR4 ((uint32_t)1U << 2U) +#define IOCTRL30_POC_DU_DR3 ((uint32_t)1U << 1U) +#define IOCTRL30_POC_DU_DR2 ((uint32_t)1U << 0U) + +#define IOCTRL31_POC_MSIOF0_SS2 ((uint32_t)1U << 31U) +#define IOCTRL31_POC_MSIOF0_SS1 ((uint32_t)1U << 30U) +#define IOCTRL31_POC_MSIOF0_SYNC ((uint32_t)1U << 29U) +#define IOCTRL31_POC_MSIOF0_SCK ((uint32_t)1U << 28U) +#define IOCTRL31_POC_MSIOF0_TXD ((uint32_t)1U << 27U) +#define IOCTRL31_POC_MSIOF0_RXD ((uint32_t)1U << 26U) +#define IOCTRL31_POC_MSIOF0_IRQ5 ((uint32_t)1U << 25U) +#define IOCTRL31_POC_MSIOF0_IRQ4 ((uint32_t)1U << 24U) +#define IOCTRL31_POC_VI1_FIELD ((uint32_t)1U << 23U) +#define IOCTRL31_POC_VI1_DATA11 ((uint32_t)1U << 22U) +#define IOCTRL31_POC_VI1_DATA10 ((uint32_t)1U << 21U) +#define IOCTRL31_POC_VI1_DATA9 ((uint32_t)1U << 20U) +#define IOCTRL31_POC_VI1_DATA8 ((uint32_t)1U << 19U) +#define IOCTRL31_POC_VI1_DATA7 ((uint32_t)1U << 18U) +#define IOCTRL31_POC_VI1_DATA6 ((uint32_t)1U << 17U) +#define IOCTRL31_POC_VI1_DATA5 ((uint32_t)1U << 16U) +#define IOCTRL31_POC_VI1_DATA4 ((uint32_t)1U << 15U) +#define IOCTRL31_POC_VI1_DATA3 ((uint32_t)1U << 14U) +#define IOCTRL31_POC_VI1_DATA2 ((uint32_t)1U << 13U) +#define IOCTRL31_POC_VI1_DATA1 ((uint32_t)1U << 12U) +#define IOCTRL31_POC_VI1_DATA0 ((uint32_t)1U << 11U) +#define IOCTRL31_POC_VI1_VSYNC ((uint32_t)1U << 10U) +#define IOCTRL31_POC_VI1_HSYNC ((uint32_t)1U << 9U) +#define IOCTRL31_POC_VI1_CLKENB ((uint32_t)1U << 8U) +#define IOCTRL31_POC_VI1_CLK ((uint32_t)1U << 7U) +#define IOCTRL31_POC_VI0_FIELD ((uint32_t)1U << 6U) +#define IOCTRL31_POC_VI0_DATA11 ((uint32_t)1U << 5U) +#define IOCTRL31_POC_VI0_DATA10 ((uint32_t)1U << 4U) +#define IOCTRL31_POC_VI0_DATA9 ((uint32_t)1U << 3U) +#define IOCTRL31_POC_VI0_DATA8 ((uint32_t)1U << 2U) +#define IOCTRL31_POC_VI0_DATA7 ((uint32_t)1U << 1U) +#define IOCTRL31_POC_VI0_DATA6 ((uint32_t)1U << 0U) +#define IOCTRL32_POC_FSO_TOE ((uint32_t)1U << 4U) +#define IOCTRL32_POC_FSO_CFE_1 ((uint32_t)1U << 3U) +#define IOCTRL32_POC_FSO_CFE_0 ((uint32_t)1U << 2U) +#define IOCTRL32_POC_SDA3 ((uint32_t)1U << 1U) +#define IOCTRL32_POC_SCL3 ((uint32_t)1U << 0U) +#define IOCTRL40_SD0TDSEL1 ((uint32_t)1U << 1U) +#define IOCTRL40_SD0TDSEL0 ((uint32_t)1U << 0U) + +#define MOD_sel_canfd0_A ((uint32_t)0U << 11U) +#define MOD_sel_canfd0_B ((uint32_t)1U << 11U) +#define MOD_sel_gether_A ((uint32_t)0U << 10U) +#define MOD_sel_gether_B ((uint32_t)1U << 10U) +#define MOD_sel_hscif0_A ((uint32_t)0U << 9U) +#define MOD_sel_hscif0_B ((uint32_t)1U << 9U) +#define MOD_sel_pwm0_A ((uint32_t)0U << 8U) +#define MOD_sel_pwm0_B ((uint32_t)1U << 8U) +#define MOD_sel_pwm1_A ((uint32_t)0U << 7U) +#define MOD_sel_pwm1_B ((uint32_t)1U << 7U) +#define MOD_sel_pwm2_A ((uint32_t)0U << 6U) +#define MOD_sel_pwm2_B ((uint32_t)1U << 6U) +#define MOD_sel_pwm3_A ((uint32_t)0U << 5U) +#define MOD_sel_pwm3_B ((uint32_t)1U << 5U) +#define MOD_sel_pwm4_A ((uint32_t)0U << 4U) +#define MOD_sel_pwm4_B ((uint32_t)1U << 4U) +#define MOD_sel_rsp_A ((uint32_t)0U << 2U) +#define MOD_sel_rsp_B ((uint32_t)1U << 2U) +#define MOD_sel_scif1_A ((uint32_t)0U << 1U) +#define MOD_sel_scif1_B ((uint32_t)1U << 1U) +#define MOD_sel_tmu_A ((uint32_t)0U << 0U) +#define MOD_sel_tmu_B ((uint32_t)1U << 0U) + + +static void pfc_reg_write(uint32_t addr, uint32_t data); + +static void pfc_reg_write(uint32_t addr, uint32_t data) +{ + mmio_write_32(PFC_PMMR, ~data); + mmio_write_32((uintptr_t)addr, data); +} + + +void pfc_init_v3h(void) +{ + + /* initialize module select */ + pfc_reg_write(PFC_MOD_SEL0, MOD_sel_canfd0_A + | MOD_sel_gether_A + | MOD_sel_hscif0_B + | MOD_sel_pwm0_A + | MOD_sel_pwm1_A + | MOD_sel_pwm2_A + | MOD_sel_pwm3_A + | MOD_sel_pwm4_A + | MOD_sel_rsp_A + | MOD_sel_scif1_A + | MOD_sel_tmu_A); + + /* initialize peripheral function select */ + pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(4) + | IPSR_24_FUNC(4) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(4) + | IPSR_24_FUNC(4) + | IPSR_20_FUNC(4) + | IPSR_16_FUNC(4) + | IPSR_12_FUNC(4) + | IPSR_8_FUNC(4) + | IPSR_4_FUNC(4) + | IPSR_0_FUNC(4)); + pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) + | IPSR_24_FUNC(4) + | IPSR_20_FUNC(4) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(4)); + pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(4) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + + /* initialize GPIO/perihperal function select */ + pfc_reg_write(PFC_GPSR0, 0x00000000); + + pfc_reg_write(PFC_GPSR1, GPSR1_DIGRF_CLKOUT + | GPSR1_DIGRF_CLKIN + | GPSR1_CANFD_CLK_A + | GPSR1_CANFD0_RX_A + | GPSR1_CANFD0_TX_A + | GPSR1_AVB_LINK + | GPSR1_AVB_PHY_INT + | GPSR1_AVB_MDC + | GPSR1_AVB_MDIO + | GPSR1_AVB_TXCREFCLK + | GPSR1_AVB_TD3 + | GPSR1_AVB_TD2 + | GPSR1_AVB_TD1 + | GPSR1_AVB_TD0 + | GPSR1_AVB_TXC + | GPSR1_AVB_TX_CTL + | GPSR1_AVB_RD3 + | GPSR1_AVB_RD2 + | GPSR1_AVB_RD1 + | GPSR1_AVB_RD0 + | GPSR1_AVB_RXC + | GPSR1_AVB_RX_CTL + | GPSR1_IRQ0); + + pfc_reg_write(PFC_GPSR2, 0x00000000); + + pfc_reg_write(PFC_GPSR3, GPSR3_VI1_FIELD + | GPSR3_VI1_DATA11 + | GPSR3_VI1_DATA10 + | GPSR3_VI1_DATA9 + | GPSR3_VI1_DATA8 + | GPSR3_VI1_DATA7 + | GPSR3_VI1_DATA6 + | GPSR3_VI1_DATA5 + | GPSR3_VI1_DATA4 + | GPSR3_VI1_DATA3 + | GPSR3_VI1_DATA2); + + pfc_reg_write(PFC_GPSR4, GPSR4_GETHER_LINK_A + | GPSR4_GETHER_PHY_INT_A + | GPSR4_GETHER_MDC_A + | GPSR4_GETHER_MDIO_A + | GPSR4_GETHER_TXCREFCLK_MEGA + | GPSR4_GETHER_TXCREFCLK + | GPSR4_GETHER_TD3 + | GPSR4_GETHER_TD2 + | GPSR4_GETHER_TD1 + | GPSR4_GETHER_TD0 + | GPSR4_GETHER_TXC + | GPSR4_GETHER_TX_CTL + | GPSR4_GETHER_RD3 + | GPSR4_GETHER_RD2 + | GPSR4_GETHER_RD1 + | GPSR4_GETHER_RD0 + | GPSR4_GETHER_RXC + | GPSR4_GETHER_RX_CTL + | GPSR4_SDA2 + | GPSR4_SCL2 + | GPSR4_SDA1 + | GPSR4_SCL1 + | GPSR4_SDA0 + | GPSR4_SCL0); + + pfc_reg_write(PFC_GPSR5, GPSR5_QSPI1_SSL + | GPSR5_QSPI1_IO3 + | GPSR5_QSPI1_IO2 + | GPSR5_QSPI1_MISO_IO1 + | GPSR5_QSPI1_MOSI_IO0 + | GPSR5_QSPI1_SPCLK + | GPSR5_QSPI0_SSL + | GPSR5_QSPI0_IO3 + | GPSR5_QSPI0_IO2 + | GPSR5_QSPI0_MISO_IO1 + | GPSR5_QSPI0_MOSI_IO0 + | GPSR5_QSPI0_SPCLK); + + + + /* initialize POC Control */ + + pfc_reg_write(PFC_IOCTRL30, IOCTRL30_POC_VI0_DATA5 + | IOCTRL30_POC_VI0_DATA4 + | IOCTRL30_POC_VI0_DATA3 + | IOCTRL30_POC_VI0_DATA2 + | IOCTRL30_POC_VI0_DATA1 + | IOCTRL30_POC_VI0_DATA0 + | IOCTRL30_POC_VI0_VSYNC_N + | IOCTRL30_POC_VI0_HSYNC_N + | IOCTRL30_POC_VI0_CLKENB + | IOCTRL30_POC_VI0_CLK + | IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE + | IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC + | IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC + | IOCTRL30_POC_DU_DOTCLKOUT + | IOCTRL30_POC_DU_DB7 + | IOCTRL30_POC_DU_DB6 + | IOCTRL30_POC_DU_DB5 + | IOCTRL30_POC_DU_DB4 + | IOCTRL30_POC_DU_DB3 + | IOCTRL30_POC_DU_DB2 + | IOCTRL30_POC_DU_DG7 + | IOCTRL30_POC_DU_DG6 + | IOCTRL30_POC_DU_DG5 + | IOCTRL30_POC_DU_DG4 + | IOCTRL30_POC_DU_DG3 + | IOCTRL30_POC_DU_DG2 + | IOCTRL30_POC_DU_DR7 + | IOCTRL30_POC_DU_DR6 + | IOCTRL30_POC_DU_DR5 + | IOCTRL30_POC_DU_DR4 + | IOCTRL30_POC_DU_DR3 + | IOCTRL30_POC_DU_DR2); + + pfc_reg_write(PFC_IOCTRL31, IOCTRL31_POC_MSIOF0_SS2 + | IOCTRL31_POC_MSIOF0_SS1 + | IOCTRL31_POC_MSIOF0_SYNC + | IOCTRL31_POC_MSIOF0_SCK + | IOCTRL31_POC_MSIOF0_TXD + | IOCTRL31_POC_MSIOF0_RXD + | IOCTRL31_POC_MSIOF0_IRQ5 + | IOCTRL31_POC_MSIOF0_IRQ4 + | IOCTRL31_POC_VI1_FIELD + | IOCTRL31_POC_VI1_DATA11 + | IOCTRL31_POC_VI1_DATA10 + | IOCTRL31_POC_VI1_DATA9 + | IOCTRL31_POC_VI1_DATA8 + | IOCTRL31_POC_VI1_DATA7 + | IOCTRL31_POC_VI1_DATA6 + | IOCTRL31_POC_VI1_DATA5 + | IOCTRL31_POC_VI1_DATA4 + | IOCTRL31_POC_VI1_DATA3 + | IOCTRL31_POC_VI1_DATA2 + | IOCTRL31_POC_VI1_DATA1 + | IOCTRL31_POC_VI1_DATA0 + | IOCTRL31_POC_VI1_VSYNC + | IOCTRL31_POC_VI1_HSYNC + | IOCTRL31_POC_VI1_CLKENB + | IOCTRL31_POC_VI1_CLK + | IOCTRL31_POC_VI0_FIELD + | IOCTRL31_POC_VI0_DATA11 + | IOCTRL31_POC_VI0_DATA10 + | IOCTRL31_POC_VI0_DATA9 + | IOCTRL31_POC_VI0_DATA8 + | IOCTRL31_POC_VI0_DATA7 + | IOCTRL31_POC_VI0_DATA6 + | IOCTRL31_POC_VI0_DATA6); + + pfc_reg_write(PFC_IOCTRL32, IOCTRL32_POC_FSO_TOE + | IOCTRL32_POC_FSO_CFE_1 + | IOCTRL32_POC_FSO_CFE_0 + | IOCTRL32_POC_SDA3 + | IOCTRL32_POC_SCL3); + + pfc_reg_write(PFC_IOCTRL33,0x00000000); + + pfc_reg_write(PFC_IOCTRL40,0x00000000); + + + /* initialize LSI pin pull-up/down control */ + pfc_reg_write(PFC_PUD0,0x80000000U); + pfc_reg_write(PFC_PUD1,0x1B01C77CU); + pfc_reg_write(PFC_PUD2,0x00000000U); + pfc_reg_write(PFC_PUD3,0x0F800008U); + pfc_reg_write(PFC_PUD4,0x03807C00U); + + /* initialize LSI pin pull-enable register */ + pfc_reg_write(PFC_PUEN0,0x0035F721U); + pfc_reg_write(PFC_PUEN1,0x7E01C700U); + pfc_reg_write(PFC_PUEN2,0x003F0000U); + pfc_reg_write(PFC_PUEN3,0x07000000U); + pfc_reg_write(PFC_PUEN4,0x0381E800U); + + /* initialize positive/negative logic select */ + mmio_write_32(GPIO_POSNEG0, 0x00000000U); + mmio_write_32(GPIO_POSNEG1, 0x00000000U); + mmio_write_32(GPIO_POSNEG2, 0x00000000U); + mmio_write_32(GPIO_POSNEG3, 0x00000000U); + mmio_write_32(GPIO_POSNEG4, 0x00000000U); + mmio_write_32(GPIO_POSNEG5, 0x00000000U); + + /* initialize general IO/interrupt switching */ + mmio_write_32(GPIO_IOINTSEL0, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL1, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL2, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL3, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL4, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL5, 0x00000000U); + + /* initialize general output register */ + mmio_write_32(GPIO_OUTDT1, 0x00010000U); + mmio_write_32(GPIO_OUTDT4, 0x00400000U); + mmio_write_32(GPIO_OUTDT5, 0x00007000U); + + /* initialize general input/output switching */ + mmio_write_32(GPIO_INOUTSEL0, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL1, 0x00010000U); + mmio_write_32(GPIO_INOUTSEL2, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL3, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL4, 0x00400000U); + mmio_write_32(GPIO_INOUTSEL5, 0x00007000U); +} diff --git a/plat/renesas/rcar/pfc/V3H/pfc_init_v3h.h b/plat/renesas/rcar/pfc/V3H/pfc_init_v3h.h new file mode 100644 index 0000000..6ecedb5 --- /dev/null +++ b/plat/renesas/rcar/pfc/V3H/pfc_init_v3h.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef PFC_INIT_V3H_H__ +#define PFC_INIT_V3H_H__ + +void pfc_init_v3h(void); + +#endif /* PFC_INIT_V3H_H__ */ diff --git a/plat/renesas/rcar/pfc/pfc.mk b/plat/renesas/rcar/pfc/pfc.mk index 0ccbe3c..33c76ba 100644 --- a/plat/renesas/rcar/pfc/pfc.mk +++ b/plat/renesas/rcar/pfc/pfc.mk @@ -35,6 +35,7 @@ ifeq (${RCAR_LSI},${RCAR_AUTO}) BL2_SOURCES += plat/renesas/rcar/pfc/M3/pfc_init_m3.c BL2_SOURCES += plat/renesas/rcar/pfc/M3N/pfc_init_m3n.c BL2_SOURCES += plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c + BL2_SOURCES += plat/renesas/rcar/pfc/V3H/pfc_init_v3h.c else ifdef RCAR_LSI_CUT_COMPAT ifeq (${RCAR_LSI},${RCAR_H3}) @@ -50,6 +51,9 @@ else ifdef RCAR_LSI_CUT_COMPAT ifeq (${RCAR_LSI},${RCAR_V3M}) BL2_SOURCES += plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c endif + ifeq (${RCAR_LSI},${RCAR_V3H}) + BL2_SOURCES += plat/renesas/rcar/pfc/V3H/pfc_init_v3h.c + endif else ifeq (${RCAR_LSI},${RCAR_H3}) ifeq (${LSI_CUT},10) @@ -71,6 +75,9 @@ else ifeq (${RCAR_LSI},${RCAR_V3M}) BL2_SOURCES += plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c endif + ifeq (${RCAR_LSI},${RCAR_V3H}) + BL2_SOURCES += plat/renesas/rcar/pfc/V3H/pfc_init_v3h.c + endif endif BL2_SOURCES += plat/renesas/rcar/pfc/pfc_init.c diff --git a/plat/renesas/rcar/pfc/pfc_init.c b/plat/renesas/rcar/pfc/pfc_init.c index c270851..94675b1 100644 --- a/plat/renesas/rcar/pfc/pfc_init.c +++ b/plat/renesas/rcar/pfc/pfc_init.c @@ -40,6 +40,7 @@ #include "M3/pfc_init_m3.h" #include "M3N/pfc_init_m3n.h" #include "V3M/pfc_init_v3m.h" + #include "V3H/pfc_init_v3h.h" #endif #if RCAR_LSI == RCAR_H3 /* H3 */ #include "H3/pfc_init_h3_v1.h" @@ -50,10 +51,14 @@ #endif #if RCAR_LSI == RCAR_M3N /* M3N */ #include "M3N/pfc_init_m3n.h" + #include "V3H/pfc_init_v3h.h" #endif #if RCAR_LSI == RCAR_V3M /* V3M */ #include "V3M/pfc_init_v3m.h" #endif +#if RCAR_LSI == RCAR_V3H /* V3H */ + #include "V3H/pfc_init_v3h.h" +#endif /* Product Register */ #define PRR (0xFFF00044U) @@ -63,6 +68,7 @@ #define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ #define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */ #define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */ +#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */ #define PRR_PRODUCT_10 (0x00U) #define PRR_PRODUCT_11 (0x01U) #define PRR_PRODUCT_20 (0x10U) @@ -111,6 +117,9 @@ void pfc_init(void) case RCAR_PRODUCT_V3M: pfc_init_v3m(); break; + case RCAR_PRODUCT_V3H: + pfc_init_v3h(); + break; default: PRR_PRODUCT_ERR(reg); break; @@ -159,6 +168,13 @@ void pfc_init(void) pfc_init_v3m(); #endif break; + case PRR_PRODUCT_V3H: +#if RCAR_LSI != RCAR_V3H + PRR_PRODUCT_ERR(reg); +#else + pfc_init_v3h(); +#endif + break; default: PRR_PRODUCT_ERR(reg); break; @@ -205,6 +221,11 @@ void pfc_init(void) PRR_PRODUCT_ERR(reg); } pfc_init_v3m(); + #elif RCAR_LSI == RCAR_V3H /* V3H */ + if ((PRR_PRODUCT_V3H) != (reg & PRR_PRODUCT_MASK)) { + PRR_PRODUCT_ERR(reg); + } + pfc_init_v3h(); #else #error "Don't have PFC initialize routine(unknown)." #endif diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk index 550d829..a19d246 100644 --- a/plat/renesas/rcar/platform.mk +++ b/plat/renesas/rcar/platform.mk @@ -113,11 +113,13 @@ RCAR_H3:=0 RCAR_M3:=1 RCAR_M3N:=2 RCAR_V3M:=3 +RCAR_V3H:=4 RCAR_AUTO:=99 $(eval $(call add_define,RCAR_H3)) $(eval $(call add_define,RCAR_M3)) $(eval $(call add_define,RCAR_M3N)) $(eval $(call add_define,RCAR_V3M)) +$(eval $(call add_define,RCAR_V3H)) $(eval $(call add_define,RCAR_AUTO)) RCAR_CUT_10:=0 RCAR_CUT_11:=1 @@ -195,6 +197,22 @@ else endif $(eval $(call add_define,RCAR_LSI_CUT)) endif + else ifeq (${LSI},V3H) + RCAR_LSI:=${RCAR_V3H} + ifndef LSI_CUT + # enable compatible function. + RCAR_LSI_CUT_COMPAT := 1 + $(eval $(call add_define,RCAR_LSI_CUT_COMPAT)) + else + # disable compatible function. + ifeq (${LSI_CUT},10) + RCAR_LSI_CUT:=0 + endif + ifeq (${LSI_CUT},20) + RCAR_LSI_CUT:=10 + endif + $(eval $(call add_define,RCAR_LSI_CUT)) + endif else $(error "Error: ${LSI} is not supported.") endif diff --git a/plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.c b/plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.c new file mode 100644 index 0000000..af56e33 --- /dev/null +++ b/plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.c @@ -0,0 +1,651 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <stdint.h> +#include <debug.h> +#include "qos_init_v3h_v10.h" + + +#define RCAR_QOS_VERSION "rev.0.14" + +#define RCAR_QOS_NONE (3U) +#define RCAR_QOS_TYPE_DEFAULT (0U) + +#define RCAR_DRAM_SPLIT_LINEAR (0U) +#define RCAR_DRAM_SPLIT_4CH (1U) +#define RCAR_DRAM_SPLIT_2CH (2U) +#define RCAR_DRAM_SPLIT_AUTO (3U) + +#define RST_BASE (0xE6160000U) +#define RST_MODEMR (RST_BASE + 0x0060U) + +#define DBSC_BASE (0xE6790000U) +#define DBSC_DBDFIPMSTRCNF (DBSC_BASE + 0x0520U) +#define DBSC_AXARB (DBSC_BASE + 0x0800U) +#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U) +#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) +#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) +#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) +#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU) +#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) +#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U) +#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) +#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) +#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U) +#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U) +#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U) +#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U) +#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU) +#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U) +#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U) +#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U) +#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU) +#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U) +#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U) +#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U) +#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU) +#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U) +#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U) +#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U) +#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU) +#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U) +#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U) +#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U) +#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU) +#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U) +#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U) +#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U) +#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU) +#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U) +#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U) +#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U) +#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU) +#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U) +#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U) +#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U) +#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU) +#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U) +#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U) +#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U) +#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU) +#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U) +#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U) +#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U) +#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU) +#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U) +#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U) +#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U) +#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU) +#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U) +#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U) +#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U) +#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU) +#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U) +#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U) +#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U) +#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU) +#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U) +#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U) +#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U) +#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU) +#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U) +#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U) +#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U) +#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU) +#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U) +#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U) +#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U) +#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU) +#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) + +#define AXI_BASE (0xE6784000U) +#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U) +#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU) +#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U) +#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U) +#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U) +#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U) +#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U) +#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U) +#define ADSPLCR0_SWP (0x0CU) + +#define MSTAT_BASE (0xE67E0000U) +#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U) +#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U) +#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U) +#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U) +#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U) +#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U) +#define MSTAT_STATQC (MSTAT_BASE + 0x8008U) + +#define RALLOC_BASE (0xE67F0000U) +#define RALLOC_RAS (RALLOC_BASE + 0x0000U) +#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U) +#define RALLOC_RAEN (RALLOC_BASE + 0x0018U) +#define RALLOC_REGGD (RALLOC_BASE + 0x0020U) +#define RALLOC_DANN (RALLOC_BASE + 0x0030U) +#define RALLOC_DANT (RALLOC_BASE + 0x0038U) +#define RALLOC_EC (RALLOC_BASE + 0x003CU) +#define RALLOC_EMS (RALLOC_BASE + 0x0040U) +#define RALLOC_FSS (RALLOC_BASE + 0x0048U) +#define RALLOC_INSFC (RALLOC_BASE + 0x0050U) +#define RALLOC_BERR (RALLOC_BASE + 0x0054U) +#define RALLOC_EARLYR (RALLOC_BASE + 0x0060U) +#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U) +#define RALLOC_STATGEN0 (RALLOC_BASE + 0x0088U) + +#define ACTIVE_OR (0xFD812030U) + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +static inline void io_write_32(uintptr_t addr, uint32_t value) +{ + *(volatile uint32_t*)addr = value; +} + +static inline void io_write_64(uintptr_t addr, uint64_t value) +{ + *(volatile uint64_t*)addr = value; +} + +typedef struct { + uintptr_t addr; + uint64_t value; +} mstat_slot_t; + + +#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT +static const mstat_slot_t mstat_fix[] = { + {0x0000U, 0x0000000000000000U}, + {0x0008U, 0x0000000000000000U}, + {0x0010U, 0x0000000000000000U}, + {0x0018U, 0x0000000000000000U}, + {0x0020U, 0x0000000000000000U}, + {0x0028U, 0x0000000000000000U}, + {0x0030U, 0x001004030000FFFFU}, + {0x0038U, 0x001008060000FFFFU}, + {0x0040U, 0x001424120000FFFFU}, + {0x0048U, 0x0000000000000000U}, + {0x0050U, 0x001404010000FFFFU}, + {0x0058U, 0x0014100F0000FFFFU}, + {0x0060U, 0x00140C0C0000FFFFU}, + {0x0068U, 0x0000000000000000U}, + {0x0070U, 0x001404010000FFFFU}, + {0x0078U, 0x001008060000FFFFU}, + {0x0080U, 0x0000000000000000U}, + {0x0088U, 0x001424120000FFFFU}, + {0x0090U, 0x00140C0C0000FFFFU}, + {0x0098U, 0x0000000000000000U}, + {0x00A0U, 0x000C04020000FFFFU}, + {0x00A8U, 0x000C04010000FFFFU}, + {0x00B0U, 0x000C04010000FFFFU}, + {0x00B8U, 0x0000000000000000U}, + {0x00C0U, 0x000C04020000FFFFU}, + {0x00C8U, 0x000C04010000FFFFU}, + {0x00D0U, 0x000C04010000FFFFU}, + {0x00D8U, 0x001020080000FFFFU}, + {0x00E0U, 0x001008080000FFFFU}, + {0x00E8U, 0x0000000000000000U}, + {0x00F0U, 0x001020080000FFFFU}, + {0x00F8U, 0x000C08060000FFFFU}, + {0x0100U, 0x0000000000000000U}, + {0x0108U, 0x0000000000000000U}, + {0x0110U, 0x001008080000FFFFU}, + {0x0118U, 0x000C100F0000FFFFU}, + {0x0120U, 0x000C100F0000FFFFU}, + {0x0128U, 0x0000000000000000U}, + {0x0130U, 0x0000000000000000U}, + {0x0138U, 0x00100C0A0000FFFFU}, + {0x0140U, 0x00100C0A0000FFFFU}, + {0x0148U, 0x0000000000000000U}, + {0x0150U, 0x00100C0C0000FFFFU}, + {0x0158U, 0x00100C0C0000FFFFU}, + {0x0160U, 0x00100C0A0000FFFFU}, + {0x0168U, 0x00100C0A0000FFFFU}, + {0x0170U, 0x0000000000000000U}, + {0x0178U, 0x001008050000FFFFU}, + {0x0180U, 0x001008050000FFFFU}, + {0x0188U, 0x0000000000000000U}, + {0x0190U, 0x00102C2A0000FFFFU}, + {0x0198U, 0x00102C2A0000FFFFU}, + {0x01A0U, 0x00100C0A0000FFFFU}, + {0x01A8U, 0x00100C0A0000FFFFU}, + {0x01B0U, 0x0000000000000000U}, + {0x01B8U, 0x0000000000000000U}, + {0x01C0U, 0x0000000000000000U}, + {0x01C8U, 0x0000000000000000U}, + {0x01D0U, 0x0000000000000000U}, + {0x01D8U, 0x0000000000000000U}, + {0x01E0U, 0x0000000000000000U}, + {0x01E8U, 0x0000000000000000U}, + {0x01F0U, 0x0000000000000000U}, + {0x01F8U, 0x0000000000000000U}, + {0x0200U, 0x0000000000000000U}, + {0x0208U, 0x0000000000000000U}, + {0x0210U, 0x0000000000000000U}, + {0x0218U, 0x0000000000000000U}, + {0x0220U, 0x0000000000000000U}, + {0x0228U, 0x0000000000000000U}, + {0x0230U, 0x0000000000000000U}, + {0x0238U, 0x0000000000000000U}, + {0x0240U, 0x0000000000000000U}, + {0x0248U, 0x0000000000000000U}, + {0x0250U, 0x0000000000000000U}, + {0x0258U, 0x0000000000000000U}, + {0x0260U, 0x0000000000000000U}, + {0x0268U, 0x001408010000FFFFU}, + {0x0270U, 0x001404010000FFFFU}, + {0x0278U, 0x0000000000000000U}, + {0x0280U, 0x0000000000000000U}, + {0x0288U, 0x0000000000000000U}, + {0x0290U, 0x001408010000FFFFU}, + {0x0298U, 0x001404010000FFFFU}, + {0x02A0U, 0x000C04010000FFFFU}, + {0x02A8U, 0x000C04010000FFFFU}, + {0x02B0U, 0x001404010000FFFFU}, + {0x02B8U, 0x0000000000000000U}, + {0x02C0U, 0x0000000000000000U}, + {0x02C8U, 0x0000000000000000U}, + {0x02D0U, 0x000C04010000FFFFU}, + {0x02D8U, 0x000C04010000FFFFU}, + {0x02E0U, 0x001404010000FFFFU}, + {0x02E8U, 0x0000000000000000U}, + {0x02F0U, 0x0000000000000000U}, + {0x02F8U, 0x0000000000000000U}, + {0x0300U, 0x0000000000000000U}, + {0x0308U, 0x0000000000000000U}, + {0x0310U, 0x0000000000000000U}, + {0x0318U, 0x0000000000000000U}, + {0x0320U, 0x0000000000000000U}, + {0x0328U, 0x0000000000000000U}, + {0x0330U, 0x0000000000000000U}, + {0x0338U, 0x0000000000000000U}, + {0x0340U, 0x0000000000000000U}, + {0x0348U, 0x0000000000000000U}, + {0x0350U, 0x0000000000000000U}, + {0x0358U, 0x0000000000000000U}, + {0x0360U, 0x0000000000000000U}, + {0x0368U, 0x0000000000000000U}, +}; + +static const mstat_slot_t mstat_be[] = { + {0x0000U, 0x001200100C89C401U}, + {0x0008U, 0x001200100C89C401U}, + {0x0010U, 0x001200100C89C401U}, + {0x0018U, 0x001200100C89C401U}, + {0x0020U, 0x0000000000000000U}, + {0x0028U, 0x001200100C80FC01U}, + {0x0030U, 0x0000000000000000U}, + {0x0038U, 0x0000000000000000U}, + {0x0040U, 0x0000000000000000U}, + {0x0048U, 0x0000000000000000U}, + {0x0050U, 0x0000000000000000U}, + {0x0058U, 0x0000000000000000U}, + {0x0060U, 0x0000000000000000U}, + {0x0068U, 0x0000000000000000U}, + {0x0070U, 0x0000000000000000U}, + {0x0078U, 0x0000000000000000U}, + {0x0080U, 0x0000000000000000U}, + {0x0088U, 0x0000000000000000U}, + {0x0090U, 0x0000000000000000U}, + {0x0098U, 0x0000000000000000U}, + {0x00A0U, 0x0000000000000000U}, + {0x00A8U, 0x0000000000000000U}, + {0x00B0U, 0x0000000000000000U}, + {0x00B8U, 0x0000000000000000U}, + {0x00C0U, 0x0000000000000000U}, + {0x00C8U, 0x0000000000000000U}, + {0x00D0U, 0x0000000000000000U}, + {0x00D8U, 0x0000000000000000U}, + {0x00E0U, 0x0000000000000000U}, + {0x00E8U, 0x0000000000000000U}, + {0x00F0U, 0x0000000000000000U}, + {0x00F8U, 0x0000000000000000U}, + {0x0100U, 0x0000000000000000U}, + {0x0108U, 0x0000000000000000U}, + {0x0110U, 0x0000000000000000U}, + {0x0118U, 0x0000000000000000U}, + {0x0120U, 0x0000000000000000U}, + {0x0128U, 0x0000000000000000U}, + {0x0130U, 0x0000000000000000U}, + {0x0138U, 0x0000000000000000U}, + {0x0140U, 0x0000000000000000U}, + {0x0148U, 0x0000000000000000U}, + {0x0150U, 0x0000000000000000U}, + {0x0158U, 0x0000000000000000U}, + {0x0160U, 0x0000000000000000U}, + {0x0168U, 0x0000000000000000U}, + {0x0170U, 0x0000000000000000U}, + {0x0178U, 0x0000000000000000U}, + {0x0180U, 0x0000000000000000U}, + {0x0188U, 0x0000000000000000U}, + {0x0190U, 0x0000000000000000U}, + {0x0198U, 0x0000000000000000U}, + {0x01A0U, 0x0000000000000000U}, + {0x01A8U, 0x0000000000000000U}, + {0x01B0U, 0x0000000000000000U}, + {0x01B8U, 0x0000000000000000U}, + {0x01C0U, 0x001100800C8FFC01U}, + {0x01C8U, 0x001100800C8FFC01U}, + {0x01D0U, 0x001100800C8FFC01U}, + {0x01D8U, 0x001100800C8FFC01U}, + {0x01E0U, 0x0000000000000000U}, + {0x01E8U, 0x001200100C80FC01U}, + {0x01F0U, 0x001100100C80FC01U}, + {0x01F8U, 0x0000000000000000U}, + {0x0200U, 0x0000000000000000U}, + {0x0208U, 0x001200100C80FC01U}, + {0x0210U, 0x001100100C80FC01U}, + {0x0218U, 0x001100100C825801U}, + {0x0220U, 0x001100100C825801U}, + {0x0228U, 0x0000000000000000U}, + {0x0230U, 0x001100100C825801U}, + {0x0238U, 0x001100100C825801U}, + {0x0240U, 0x001200100C8BB801U}, + {0x0248U, 0x001100200C8FFC01U}, + {0x0250U, 0x001200100C8BB801U}, + {0x0258U, 0x001100200C8FFC01U}, + {0x0260U, 0x001100100C84E401U}, + {0x0268U, 0x0000000000000000U}, + {0x0270U, 0x0000000000000000U}, + {0x0278U, 0x001100100C81F401U}, + {0x0280U, 0x0000000000000000U}, + {0x0288U, 0x0000000000000000U}, + {0x0290U, 0x0000000000000000U}, + {0x0298U, 0x0000000000000000U}, + {0x02A0U, 0x0000000000000000U}, + {0x02A8U, 0x0000000000000000U}, + {0x02B0U, 0x0000000000000000U}, + {0x02B8U, 0x001100100C803401U}, + {0x02C0U, 0x0000000000000000U}, + {0x02C8U, 0x0000000000000000U}, + {0x02D0U, 0x0000000000000000U}, + {0x02D8U, 0x0000000000000000U}, + {0x02E0U, 0x0000000000000000U}, + {0x02E8U, 0x001100100C803401U}, + {0x02F0U, 0x001100300C8FFC01U}, + {0x02F8U, 0x001100500C8FFC01U}, + {0x0300U, 0x0000000000000000U}, + {0x0308U, 0x001100300C8FFC01U}, + {0x0310U, 0x001100500C8FFC01U}, + {0x0318U, 0x001200100C803401U}, + {0x0320U, 0x001100300C8FFC01U}, + {0x0328U, 0x001100500C8FFC01U}, + {0x0330U, 0x001100300C8FFC01U}, + {0x0338U, 0x001100500C8FFC01U}, + {0x0340U, 0x0000000000000000U}, + {0x0348U, 0x0000000000000000U}, + {0x0350U, 0x0000000000000000U}, + {0x0358U, 0x0000000000000000U}, + {0x0360U, 0x0000000000000000U}, + {0x0368U, 0x0000000000000000U}, +}; +#endif + +static void dbsc_setting(void) +{ + uint32_t md=0; + + /* BUFCAM settings */ + //DBSC_DBCAM0CNF0 not set + io_write_32(DBSC_DBCAM0CNF1, 0x00043218U); //dbcam0cnf1 + io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U); //dbcam0cnf2 + io_write_32(DBSC_DBCAM0CNF3, 0x00000000U); //dbcam0cnf3 + io_write_32(DBSC_DBSCHCNT0, 0x000F0037U); //dbschcnt0 + //DBSC_DBSCHCNT1 not set + io_write_32(DBSC_DBSCHSZ0, 0x00000001U); //dbschsz0 + io_write_32(DBSC_DBSCHRW0, 0x22421111U); //dbschrw0 + io_write_32(DBSC_DBSCHRW1, 0x00000034U); //dbschrw1 + + md = (*((volatile uint32_t*)RST_MODEMR) & 0x000A0000) >> 17; + + switch (md) { + case 0x0: + /* DDR3200 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123U); + break; + case 0x1: //MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) + /* DDR2800 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123U); + break; + case 0x4: //MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) + /* DDR2400 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123U); + break; + default: //MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) + /* DDR1600 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123U); + break; + } + + /* QoS Settings */ + io_write_32(DBSC_DBSCHQOS_0_0, 0x00000F00U); + io_write_32(DBSC_DBSCHQOS_0_1, 0x00000B00U); + io_write_32(DBSC_DBSCHQOS_0_2, 0x00000000U); + io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000U); + //DBSC_DBSCHQOS_1_0 not set + //DBSC_DBSCHQOS_1_1 not set + //DBSC_DBSCHQOS_1_2 not set + //DBSC_DBSCHQOS_1_3 not set + //DBSC_DBSCHQOS_2_0 not set + //DBSC_DBSCHQOS_2_1 not set + //DBSC_DBSCHQOS_2_2 not set + //DBSC_DBSCHQOS_2_3 not set + //DBSC_DBSCHQOS_3_0 not set + //DBSC_DBSCHQOS_3_1 not set + //DBSC_DBSCHQOS_3_2 not set + //DBSC_DBSCHQOS_3_3 not set + io_write_32(DBSC_DBSCHQOS_4_0, 0x00000300U); + io_write_32(DBSC_DBSCHQOS_4_1, 0x000002F0U); + io_write_32(DBSC_DBSCHQOS_4_2, 0x00000200U); + io_write_32(DBSC_DBSCHQOS_4_3, 0x00000100U); + //DBSC_DBSCHQOS_5_0 not set + //DBSC_DBSCHQOS_5_1 not set + //DBSC_DBSCHQOS_5_2 not set + //DBSC_DBSCHQOS_5_3 not set + //DBSC_DBSCHQOS_6_0 not set + //DBSC_DBSCHQOS_6_1 not set + //DBSC_DBSCHQOS_6_2 not set + //DBSC_DBSCHQOS_6_3 not set + //DBSC_DBSCHQOS_7_0 not set + //DBSC_DBSCHQOS_7_1 not set + //DBSC_DBSCHQOS_7_2 not set + //DBSC_DBSCHQOS_7_3 not set + //DBSC_DBSCHQOS_8_0 not set + //DBSC_DBSCHQOS_8_1 not set + //DBSC_DBSCHQOS_8_2 not set + //DBSC_DBSCHQOS_8_3 not set + io_write_32(DBSC_DBSCHQOS_9_0, 0x00000300U); + io_write_32(DBSC_DBSCHQOS_9_1, 0x000002F0U); + io_write_32(DBSC_DBSCHQOS_9_2, 0x00000200U); + io_write_32(DBSC_DBSCHQOS_9_3, 0x00000100U); + //DBSC_DBSCHQOS_10_0 not set + //DBSC_DBSCHQOS_10_1 not set + //DBSC_DBSCHQOS_10_2 not set + //DBSC_DBSCHQOS_10_3 not set + //DBSC_DBSCHQOS_11_0 not set + //DBSC_DBSCHQOS_11_1 not set + //DBSC_DBSCHQOS_11_2 not set + //DBSC_DBSCHQOS_11_3 not set + io_write_32(DBSC_DBSCHQOS_12_0, 0x00000040U); + io_write_32(DBSC_DBSCHQOS_12_1, 0x00000030U); + io_write_32(DBSC_DBSCHQOS_12_2, 0x00000020U); + io_write_32(DBSC_DBSCHQOS_12_3, 0x00000010U); + io_write_32(DBSC_DBSCHQOS_13_0, 0x00000100U); + io_write_32(DBSC_DBSCHQOS_13_1, 0x000000F0U); + io_write_32(DBSC_DBSCHQOS_13_2, 0x000000A0U); + io_write_32(DBSC_DBSCHQOS_13_3, 0x00000040U); + io_write_32(DBSC_DBSCHQOS_14_0, 0x000000C0U); + io_write_32(DBSC_DBSCHQOS_14_1, 0x000000B0U); + io_write_32(DBSC_DBSCHQOS_14_2, 0x00000080U); + io_write_32(DBSC_DBSCHQOS_14_3, 0x00000040U); + io_write_32(DBSC_DBSCHQOS_15_0, 0x00000040U); + io_write_32(DBSC_DBSCHQOS_15_1, 0x00000030U); + io_write_32(DBSC_DBSCHQOS_15_2, 0x00000020U); + io_write_32(DBSC_DBSCHQOS_15_3, 0x00000010U); +} + +void qos_init_v3h_v10(void) +{ + /* this setting value is H3 * + * Respond by updating in the future */ + dbsc_setting(); + + /* DRAM Split Address mapping */ +#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \ + (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO) + NOTICE("BL2: DRAM Split is 4ch\n"); + io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT + | ADSPLCR0_SPLITSEL(0xFFU) + | ADSPLCR0_AREA(0x1BU) + | ADSPLCR0_SWP); + io_write_32(AXI_ADSPLCR1, 0x00000000U); + io_write_32(AXI_ADSPLCR2, 0xA8A90000U); + io_write_32(AXI_ADSPLCR3, 0x00000000U); +#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH + NOTICE("BL2: DRAM Split is 2ch\n"); + io_write_32(AXI_ADSPLCR0, 0x00000000U); + io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT + | ADSPLCR0_SPLITSEL(0xFFU) + | ADSPLCR0_AREA(0x1BU) + | ADSPLCR0_SWP); + io_write_32(AXI_ADSPLCR2, 0x00000000U); + io_write_32(AXI_ADSPLCR3, 0x00000000U); +#else + NOTICE("BL2: DRAM Split is OFF\n"); +#endif + +#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) +#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT + NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); +#endif + + /* Resource Alloc setting */ + io_write_32(RALLOC_RAS, 0x00000044U); + io_write_32(RALLOC_FIXTH, 0x000F0005U); + io_write_32(RALLOC_REGGD, 0x00000000U); + io_write_64(RALLOC_DANN, 0x0404010002020201U); + io_write_32(RALLOC_DANT, 0x0020100AU); + io_write_32(RALLOC_EC, 0x00000000U); + io_write_64(RALLOC_EMS, 0x0000000000000000U); + io_write_32(RALLOC_FSS, 0x000003e8U); + io_write_32(RALLOC_INSFC, 0xC7840001U); + io_write_32(RALLOC_BERR, 0x00000000U); + io_write_32(RALLOC_EARLYR, 0x00000000U); + io_write_32(RALLOC_RACNT0, 0x00010003U); + + /* GPU Boost Mode */ + io_write_32(RALLOC_STATGEN0, 0x00000001U); + io_write_32(ACTIVE_OR, 0x00000000U); /* 0:enable, 1:disable */ + + /* MSTAT setting */ + io_write_32(MSTAT_SL_INIT, 0x0305007DU); + io_write_32(MSTAT_REF_ARS, 0x00330000U); + + /* MSTAT SRAM setting */ + { + uint32_t i; + + for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { + io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr, + mstat_fix[i].value); + io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr, + mstat_fix[i].value); + } + for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { + io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr, + mstat_be[i].value); + io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr, + mstat_be[i].value); + } + } + + /* AXI-IF arbitration setting */ + io_write_32(DBSC_AXARB, 0x00000000U); + + /* 3DG bus Leaf setting */ + io_write_32(0xFD820800U, 0x00000000U); + io_write_32(0xFD821800U, 0x00000000U); + io_write_32(0xFD822800U, 0x00000000U); + io_write_32(0xFD823800U, 0x00000000U); + io_write_32(0xFD824800U, 0x00000000U); + io_write_32(0xFD825800U, 0x00000000U); + io_write_32(0xFD826800U, 0x00000000U); + io_write_32(0xFD827800U, 0x00000000U); + + /* VIO bus Leaf setting */ + io_write_32(0xFEB89800, 0x00000000U); + io_write_32(0xFEB8A800, 0x00000000U); + io_write_32(0xFEB8B800, 0x00000000U); + io_write_32(0xFEB8C800, 0x00000000U); + + /* HSC bus Leaf setting */ + io_write_32(0xE6430800, 0x00000000U); + io_write_32(0xE6431800, 0x00000000U); + io_write_32(0xE6432800, 0x00000000U); + io_write_32(0xE6433800, 0x00000000U); + + /* MP bus Leaf setting */ + io_write_32(0xEC620800, 0x00000000U); + io_write_32(0xEC621800, 0x00000000U); + + /* PERIE bus Leaf setting */ + io_write_32(0xE7760800, 0x00000000U); + io_write_32(0xE7768800, 0x00000000U); + + /* PERIW bus Leaf setting */ + io_write_32(0xE6760800, 0x00000000U); + io_write_32(0xE6768800, 0x00000000U); + + /* RT bus Leaf setting */ + io_write_32(0xFFC50800U, 0x00000000U); + io_write_32(0xFFC51800U, 0x00000000U); + + /* CCI bus Leaf setting */ + io_write_32(0xF1300800, 0x00000003U); + io_write_32(0xF1340800, 0x00000003U); + io_write_32(0xF1380800, 0x00000003U); + io_write_32(0xF13C0800, 0x00000003U); + + /* Resource Alloc start */ + io_write_32(RALLOC_RAEN, 0x00000001U); + + /* MSTAT start */ + io_write_32(MSTAT_STATQC, 0x00000001U); +#else + NOTICE("BL2: QoS is None\n"); + + /* Resource Alloc setting */ + io_write_32(RALLOC_EC, 0x00000000U); + /* Resource Alloc start */ + io_write_32(RALLOC_RAEN, 0x00000001U); +#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ +} diff --git a/plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.h b/plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.h new file mode 100644 index 0000000..893d46f --- /dev/null +++ b/plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef QOS_INIT_H_H3_V20__ +#define QOS_INIT_H_H3_V20__ + +void qos_init_v3h_v10(void); + +#endif /* QOS_INIT_H_H3_V20__ */ diff --git a/plat/renesas/rcar/qos/qos.mk b/plat/renesas/rcar/qos/qos.mk index 161ab74..39c9c49 100644 --- a/plat/renesas/rcar/qos/qos.mk +++ b/plat/renesas/rcar/qos/qos.mk @@ -37,6 +37,7 @@ ifeq (${RCAR_LSI},${RCAR_AUTO}) BL2_SOURCES += plat/renesas/rcar/qos/M3/qos_init_m3_v11.c BL2_SOURCES += plat/renesas/rcar/qos/M3N/qos_init_m3n_v10.c BL2_SOURCES += plat/renesas/rcar/qos/V3M/qos_init_v3m.c + BL2_SOURCES += plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.c else ifdef RCAR_LSI_CUT_COMPAT ifeq (${RCAR_LSI},${RCAR_H3}) BL2_SOURCES += plat/renesas/rcar/qos/H3/qos_init_h3_v10.c @@ -53,6 +54,9 @@ else ifdef RCAR_LSI_CUT_COMPAT ifeq (${RCAR_LSI},${RCAR_V3M}) BL2_SOURCES += plat/renesas/rcar/qos/V3M/qos_init_v3m.c endif + ifeq (${RCAR_LSI},${RCAR_V3H}) + BL2_SOURCES += plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.c + endif else ifeq (${RCAR_LSI},${RCAR_H3}) ifeq (${LSI_CUT},10) @@ -87,6 +91,9 @@ else ifeq (${RCAR_LSI},${RCAR_V3M}) BL2_SOURCES += plat/renesas/rcar/qos/V3M/qos_init_v3m.c endif + ifeq (${RCAR_LSI},${RCAR_V3H}) + BL2_SOURCES += plat/renesas/rcar/qos/V3M/qos_init_v3h_v10.c + endif endif BL2_SOURCES += plat/renesas/rcar/qos/qos_init.c diff --git a/plat/renesas/rcar/qos/qos_init.c b/plat/renesas/rcar/qos/qos_init.c index 86ee492..07aaac2 100644 --- a/plat/renesas/rcar/qos/qos_init.c +++ b/plat/renesas/rcar/qos/qos_init.c @@ -42,6 +42,7 @@ #include "M3/qos_init_m3_v11.h" #include "M3N/qos_init_m3n_v10.h" #include "V3M/qos_init_v3m.h" + #include "V3H/qos_init_v3h_v10.h" #endif #if RCAR_LSI == RCAR_H3 /* H3 */ #include "H3/qos_init_h3_v10.h" @@ -54,10 +55,14 @@ #endif #if RCAR_LSI == RCAR_M3N /* M3N */ #include "M3N/qos_init_m3n_v10.h" + #include "V3H/qos_init_v3h.h" #endif #if RCAR_LSI == RCAR_V3M /* V3M */ #include "V3M/qos_init_v3m.h" #endif +#if RCAR_LSI == RCAR_V3H /* V3H */ + #include "V3H/qos_init_v3h_v10.h" +#endif /* Product Register */ #define PRR (0xFFF00044U) @@ -67,6 +72,7 @@ #define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ #define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */ #define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */ +#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */ #define PRR_PRODUCT_10 (0x00U) #define PRR_PRODUCT_11 (0x01U) #define PRR_PRODUCT_20 (0x10U) @@ -147,6 +153,19 @@ void qos_init(void) PRR_PRODUCT_ERR(reg); #endif break; + case PRR_PRODUCT_V3H: + #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3H) + switch (reg & PRR_CUT_MASK) { + case PRR_PRODUCT_10: + case PRR_PRODUCT_20: + default: + qos_init_v3h_v10(); + break; + } + #else + PRR_PRODUCT_ERR(reg); + #endif + break; default: PRR_PRODUCT_ERR(reg); break; @@ -205,6 +224,13 @@ void qos_init(void) PRR_PRODUCT_ERR(reg); } qos_init_v3m(); + #elif RCAR_LSI == RCAR_V3H /* V3H */ + /* V3H Cut 10 or later */ + if ((PRR_PRODUCT_V3H) + != (reg & (PRR_PRODUCT_MASK))) { + PRR_PRODUCT_ERR(reg); + } + qos_init_v3h_v10(); #else #error "Don't have QoS initialize routine(Unknown chip)." #endif diff --git a/plat/renesas/rcar/rcar_def.h b/plat/renesas/rcar/rcar_def.h index ddbca3b..d8fd976 100644 --- a/plat/renesas/rcar/rcar_def.h +++ b/plat/renesas/rcar/rcar_def.h @@ -79,7 +79,7 @@ #define DEVICE_RCAR_BASE 0xE6000000U #define DEVICE_RCAR_SIZE 0x00300000U -#if RCAR_LSI == RCAR_V3M +#if RCAR_LSI == RCAR_V3M || RCAR_LSI == RCAR_V3H #define DEVICE_RCAR_BASE2 MAKE_U(0xE6370000) #else #define DEVICE_RCAR_BASE2 MAKE_U(0xE6360000) @@ -261,6 +261,7 @@ #define RCAR_PRODUCT_M3 (0x00005200U) #define RCAR_PRODUCT_V3M (0x00005400U) #define RCAR_PRODUCT_M3N (0x00005500U) +#define RCAR_PRODUCT_V3H (0x00005600U) #define RCAR_CUT_ES10 (0x00000000U) #define RCAR_CUT_ES11 (0x00000001U) #define RCAR_CUT_ES20 (0x00000010U) diff --git a/tools/dummy_create/makefile b/tools/dummy_create/makefile index f73dc30..eb83556 100644 --- a/tools/dummy_create/makefile +++ b/tools/dummy_create/makefile @@ -110,8 +110,13 @@ $(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6) -o $(OUTPUT_FILE_SA6) \ -Map $(FILE_NAME_SA6).map \ +ifeq (${LSI},V3H) + $(objcopy) -O srec --adjust-vma=0xEB220000 --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec + $(objcopy) -O binary --adjust-vma=0xEB220000 --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin +else $(objcopy) -O srec --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec $(objcopy) -O binary --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin +endif ################################################### # Compile -- 1.9.1