diff options
Diffstat (limited to 'meta-eas/recipes-kernel/linux/linux-renesas/0030-arm64-dts-add-Juno-r2-cpu-capacity-dmips-mhz-informa.patch')
| -rw-r--r-- | meta-eas/recipes-kernel/linux/linux-renesas/0030-arm64-dts-add-Juno-r2-cpu-capacity-dmips-mhz-informa.patch | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/meta-eas/recipes-kernel/linux/linux-renesas/0030-arm64-dts-add-Juno-r2-cpu-capacity-dmips-mhz-informa.patch b/meta-eas/recipes-kernel/linux/linux-renesas/0030-arm64-dts-add-Juno-r2-cpu-capacity-dmips-mhz-informa.patch new file mode 100644 index 0000000..79bd1a6 --- /dev/null +++ b/meta-eas/recipes-kernel/linux/linux-renesas/0030-arm64-dts-add-Juno-r2-cpu-capacity-dmips-mhz-informa.patch @@ -0,0 +1,83 @@ +From 893313890fb7c18ba7e63626924f32deea273bec Mon Sep 17 00:00:00 2001 +From: Juri Lelli <juri.lelli@arm.com> +Date: Tue, 22 Mar 2016 15:45:16 +0000 +Subject: [PATCH 30/92] arm64, dts: add Juno r2 cpu capacity-dmips-mhz + information + +Add Juno r2 cpu capacity-dmips-mhz information. + +Cc: Rob Herring <robh+dt@kernel.org> +Cc: Pawel Moll <pawel.moll@arm.com> +Cc: Mark Rutland <mark.rutland@arm.com> +Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> +Cc: Kumar Gala <galak@codeaurora.org> +Cc: Catalin Marinas <catalin.marinas@arm.com> +Cc: Will Deacon <will.deacon@arm.com> +Cc: Liviu Dudau <Liviu.Dudau@arm.com> +Cc: Sudeep Holla <sudeep.holla@arm.com> +Cc: Arnd Bergmann <arnd@arndb.de> +Cc: Jon Medhurst <tixy@linaro.org> +Cc: Olof Johansson <olof@lixom.net> +Cc: Robin Murphy <robin.murphy@arm.com> +Cc: devicetree@vger.kernel.org +Acked-by: Sudeep Holla <sudeep.holla@arm.com> +Signed-off-by: Juri Lelli <juri.lelli@arm.com> +--- + arch/arm64/boot/dts/arm/juno-r2.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts +index 26aaa6a..28f40ec 100644 +--- a/arch/arm64/boot/dts/arm/juno-r2.dts ++++ b/arch/arm64/boot/dts/arm/juno-r2.dts +@@ -90,6 +90,7 @@ + next-level-cache = <&A72_L2>; + clocks = <&scpi_dvfs 0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; ++ capacity-dmips-mhz = <1024>; + }; + + A72_1: cpu@1 { +@@ -100,6 +101,7 @@ + next-level-cache = <&A72_L2>; + clocks = <&scpi_dvfs 0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; ++ capacity-dmips-mhz = <1024>; + }; + + A53_0: cpu@100 { +@@ -110,6 +112,7 @@ + next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; ++ capacity-dmips-mhz = <485>; + }; + + A53_1: cpu@101 { +@@ -120,6 +123,7 @@ + next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; ++ capacity-dmips-mhz = <485>; + }; + + A53_2: cpu@102 { +@@ -130,6 +134,7 @@ + next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; ++ capacity-dmips-mhz = <485>; + }; + + A53_3: cpu@103 { +@@ -140,6 +145,7 @@ + next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; ++ capacity-dmips-mhz = <485>; + }; + + A72_L2: l2-cache0 { +-- +1.9.1 + |