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From 4461e893a07445bcbb54a6bbf4919955c1d22e5e Mon Sep 17 00:00:00 2001
From: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Date: Fri, 24 Mar 2017 19:59:17 +0900
Subject: [PATCH 89/92] arm64: dts: r8a7795-es1: Add cpu capacity-dmips-mhz
Set the capacity-dmips-mhz for R-CAR H3(ES1.x).
This value is based on the result of the evaluation.
Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
index 172007a..c2b5b8d 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -110,6 +110,7 @@
<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
<&cluster0_opp_tb7>;
+ capacity-dmips-mhz = <1024>;
};
a57_1: cpu@1 {
@@ -125,6 +126,7 @@
<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
<&cluster0_opp_tb7>;
+ capacity-dmips-mhz = <1024>;
};
a57_2: cpu@2 {
@@ -140,6 +142,7 @@
<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
<&cluster0_opp_tb7>;
+ capacity-dmips-mhz = <1024>;
};
a57_3: cpu@3 {
@@ -155,6 +158,7 @@
<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
<&cluster0_opp_tb7>;
+ capacity-dmips-mhz = <1024>;
};
a53_0: cpu@100 {
@@ -166,6 +170,7 @@
dynamic-power-coefficient = <277>;
clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp_tb0>;
+ capacity-dmips-mhz = <379>;
};
a53_1: cpu@101 {
@@ -175,6 +180,7 @@
next-level-cache = <&L2_CA53>;
enable-method = "psci";
operating-points-v2 = <&cluster1_opp_tb0>;
+ capacity-dmips-mhz = <379>;
};
a53_2: cpu@102 {
@@ -184,6 +190,7 @@
next-level-cache = <&L2_CA53>;
enable-method = "psci";
operating-points-v2 = <&cluster1_opp_tb0>;
+ capacity-dmips-mhz = <379>;
};
a53_3: cpu@103 {
@@ -193,6 +200,7 @@
next-level-cache = <&L2_CA53>;
enable-method = "psci";
operating-points-v2 = <&cluster1_opp_tb0>;
+ capacity-dmips-mhz = <379>;
};
L2_CA57: cache-controller@0 {
--
1.9.1
|
