diff options
| author |   Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> | 2018-01-19 20:43:09 +0900 |
|---|---|---|
| committer | Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> | 2018-01-19 20:43:09 +0900 |
| commit | 2e1a7e39e012ea4436c819f46cfcac05fb161184 (patch) | |
| tree | 094a98fe4f8a2970fdd7a86e1562125f096db049 | |
| parent | 89ae3df5fc1ec66b573f724c0e462bde0eabe783 (diff) | |
| parent | 87b938882b4c672c775c7a0908f4a8b711a16c95 (diff) | |
Merge remote-tracking branch 'cogent/v2.23.1' into test
Change-Id: I2615a0e01b209fb359245a56996185e046cdb94a
Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
17 files changed, 6578 insertions, 384 deletions
diff --git a/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bbappend b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bbappend index aefd88a..d2ac495 100644 --- a/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bbappend +++ b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bbappend @@ -1,11 +1,17 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/files:" +COMPATIBLE_MACHINE_eagle = "eagle" +COMPATIBLE_MACHINE_v3msk = "v3msk" +ATFW_OPT_r8a7797 = "LSI=V3M RCAR_DRAM_SPLIT=0 RCAR_LOSSY_ENABLE=0 PMIC_ROHM_BD9571=0 RCAR_SYSTEM_SUSPEND=0 SPD=none" + ATFW_OPT_append = " ${@base_conditional("CA57CA53BOOT", "1", " PSCI_DISABLE_BIGLITTLE_IN_CA57BOOT=0", "", d)}" ATFW_OPT_append += " ${@base_conditional("DISABLE_RPC_ACCESS", "1", " RCAR_DISABLE_NONSECURE_RPC_ACCESS=1", "", d)}" +ATFW_OPT_append += " LIFEC_DBSC_PROTECT_ENABLE=0" SRC_URI_append = " \ file://0001-plat-renesas-rcar-Make-RPC-secure-settings-optional.patch \ file://0002-plat-renesas-rcar-kingfisher-reboot-fix-power-off-on-reset.diff \ + file://0003-plat-renesas-rcar-V3M-support.patch \ " do_deploy_append() { diff --git a/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0003-plat-renesas-rcar-V3M-support.patch b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0003-plat-renesas-rcar-V3M-support.patch new file mode 100644 index 0000000..822895a --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0003-plat-renesas-rcar-V3M-support.patch @@ -0,0 +1,3005 @@ +From fa455ba3a98d9e49c1aa576ab962a8c9e00a267e Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Thu, 4 Jan 2018 17:50:38 +0300 +Subject: [PATCH] plat: renesas: rcar: V3M support + +This adds R-Car V3M support. + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +--- + plat/renesas/rcar/aarch64/rcar_helpers.S | 4 + + plat/renesas/rcar/bl2_cpg_init.c | 68 ++ + plat/renesas/rcar/bl2_rcar_setup.c | 11 + + .../rcar/ddr/V3M/boot_init_dram_regdef_v3m.h | 320 ++++++ + plat/renesas/rcar/ddr/V3M/boot_init_dram_v3m.h | 37 + + plat/renesas/rcar/ddr/V3M/ddr_init_v3m.c | 356 +++++++ + plat/renesas/rcar/ddr/boot_init_dram.c | 11 + + plat/renesas/rcar/ddr/boot_init_dram_regdef.h | 1 + + plat/renesas/rcar/ddr/ddr.mk | 3 + + plat/renesas/rcar/drivers/board/board.c | 2 +- + plat/renesas/rcar/drivers/rom/rom_api.c | 18 +- + plat/renesas/rcar/drivers/scif/scif.S | 29 +- + plat/renesas/rcar/include/bl2_dma_register.h | 4 + + plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c | 1076 ++++++++++++++++++++ + plat/renesas/rcar/pfc/V3M/pfc_init_v3m.h | 37 + + plat/renesas/rcar/pfc/pfc.mk | 7 + + plat/renesas/rcar/pfc/pfc_init.c | 20 + + plat/renesas/rcar/platform.mk | 18 + + plat/renesas/rcar/qos/V3M/qos_init_v3m.c | 411 ++++++++ + plat/renesas/rcar/qos/V3M/qos_init_v3m.h | 37 + + plat/renesas/rcar/qos/qos.mk | 7 + + plat/renesas/rcar/qos/qos_init.c | 25 + + plat/renesas/rcar/rcar_def.h | 1 + + 23 files changed, 2490 insertions(+), 13 deletions(-) + mode change 100644 => 100755 plat/renesas/rcar/bl2_rcar_setup.c + create mode 100644 plat/renesas/rcar/ddr/V3M/boot_init_dram_regdef_v3m.h + create mode 100644 plat/renesas/rcar/ddr/V3M/boot_init_dram_v3m.h + create mode 100644 plat/renesas/rcar/ddr/V3M/ddr_init_v3m.c + create mode 100644 plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c + create mode 100644 plat/renesas/rcar/pfc/V3M/pfc_init_v3m.h + create mode 100644 plat/renesas/rcar/qos/V3M/qos_init_v3m.c + create mode 100644 plat/renesas/rcar/qos/V3M/qos_init_v3m.h + +diff --git a/plat/renesas/rcar/aarch64/rcar_helpers.S b/plat/renesas/rcar/aarch64/rcar_helpers.S +index edf7eeb..eae80fd 100644 +--- a/plat/renesas/rcar/aarch64/rcar_helpers.S ++++ b/plat/renesas/rcar/aarch64/rcar_helpers.S +@@ -295,7 +295,11 @@ checkCA57: + * This CPU is secondary + */ + platform_is_secondary: ++#if RCAR_LSI == RCAR_V3M ++ mov x0, #1 /* This cpu is primary */ ++#else + mov x0, #0 /* This cpu is secondary */ ++#endif + b primary_check_exit /* return */ + primary_check: + and x0, x0, # MPIDR_CPU_MASK /* Get the bit7-0 of MPIDR_EL1 -> x0 */ +diff --git a/plat/renesas/rcar/bl2_cpg_init.c b/plat/renesas/rcar/bl2_cpg_init.c +index 0c1abe7..3b424e0 100644 +--- a/plat/renesas/rcar/bl2_cpg_init.c ++++ b/plat/renesas/rcar/bl2_cpg_init.c +@@ -48,6 +48,10 @@ static void bl2_system_cpg_init_m3(void); + static void bl2_realtime_cpg_init_m3n(void); + static void bl2_system_cpg_init_m3n(void); + #endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) */ ++#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M) ++static void bl2_realtime_cpg_init_v3m(void); ++static void bl2_system_cpg_init_v3m(void); ++#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M) */ + + typedef struct { + uintptr_t adr; +@@ -309,6 +313,60 @@ static void bl2_system_cpg_init_m3n(void) + } + #endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) */ + ++#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M) ++static void bl2_realtime_cpg_init_v3m(void) ++{ ++ /* CPG (REALTIME) registers */ ++ ++ /* Realtime Module Stop Control Register 0 */ ++ cpg_write(RMSTPCR0, 0x00230000U); ++ /* Realtime Module Stop Control Register 1 */ ++ cpg_write(RMSTPCR1, 0xFFFFFFFFU); ++ /* Realtime Module Stop Control Register 2 */ ++ cpg_write(RMSTPCR2, 0x14062FD8U); ++ /* Realtime Module Stop Control Register 3 */ ++ cpg_write(RMSTPCR3, 0xFFFFFFDFU); ++ /* Realtime Module Stop Control Register 4 */ ++ cpg_write(RMSTPCR4, 0x80000184U); ++ /* Realtime Module Stop Control Register 5 */ ++ cpg_write(RMSTPCR5, 0x83FFFFFFU); ++ /* Realtime Module Stop Control Register 6 */ ++ cpg_write(RMSTPCR6, 0xFFFFFFFFU); ++ /* Realtime Module Stop Control Register 7 */ ++ cpg_write(RMSTPCR7, 0xFFFFFFFFU); ++ /* Realtime Module Stop Control Register 8 */ ++ cpg_write(RMSTPCR8, 0x7FF3FFF4U); ++ /* Realtime Module Stop Control Register 9 */ ++ cpg_write(RMSTPCR9, 0xFFFFFFFEU); ++} ++ ++static void bl2_system_cpg_init_v3m(void) ++{ ++ /* CPG (SYSTEM) registers */ ++ ++ /* System Module Stop Control Register 0 */ ++ cpg_write(SMSTPCR0, 0x00210000U); ++ /* System Module Stop Control Register 1 */ ++ cpg_write(SMSTPCR1, 0xFFFFFFFFU); ++ /* System Module Stop Control Register 2 */ ++ cpg_write(SMSTPCR2, 0x340E2FDCU); ++ /* System Module Stop Control Register 3 */ ++ cpg_write(SMSTPCR3, 0xFFFFFBDFU); ++ /* System Module Stop Control Register 4 */ ++ cpg_write(SMSTPCR4, 0x80000004U); ++ /* System Module Stop Control Register 5 */ ++ cpg_write(SMSTPCR5, 0xC3FFFFFFU); ++ /* System Module Stop Control Register 6 */ ++ cpg_write(SMSTPCR6, 0xFFFFFFFFU); ++ /* System Module Stop Control Register 7 */ ++ cpg_write(SMSTPCR7, 0xFFFFFFFFU); ++ /* System Module Stop Control Register 8 */ ++ cpg_write(SMSTPCR8, 0x01F1FFF5U); ++ /* System Module Stop Control Register 9 */ ++ cpg_write(SMSTPCR9, 0xFFFFFFFEU); ++} ++#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M) */ ++ + void bl2_cpg_init(void) + { + uint32_t modemr; +@@ -337,6 +395,9 @@ void bl2_cpg_init(void) + case RCAR_PRODUCT_M3N: + bl2_realtime_cpg_init_m3n(); + break; ++ case RCAR_PRODUCT_v3m: ++ bl2_realtime_cpg_init_v3m(); ++ break; + default: + panic(); + break; +@@ -347,6 +408,8 @@ void bl2_cpg_init(void) + bl2_realtime_cpg_init_m3(); + #elif RCAR_LSI == RCAR_M3N + bl2_realtime_cpg_init_m3n(); ++#elif RCAR_LSI == RCAR_V3M ++ bl2_realtime_cpg_init_v3m(); + #else /* RCAR_LSI == RCAR_XX */ + #error "Don't have CPG initialize routine(unknown)." + #endif /* RCAR_LSI == RCAR_XX */ +@@ -369,6 +432,9 @@ void bl2_system_cpg_init(void) + case RCAR_PRODUCT_M3N: + bl2_system_cpg_init_m3n(); + break; ++ case RCAR_PRODUCT_V3M: ++ bl2_system_cpg_init_v3m(); ++ break; + default: + panic(); + break; +@@ -379,6 +445,8 @@ void bl2_system_cpg_init(void) + bl2_system_cpg_init_m3(); + #elif RCAR_LSI == RCAR_M3N + bl2_system_cpg_init_m3n(); ++#elif RCAR_LSI == RCAR_V3M ++ bl2_system_cpg_init_v3m(); + #else /* RCAR_LSI == RCAR_XX */ + #error "Don't have CPG initialize routine(unknown)." + #endif /* RCAR_LSI == RCAR_XX */ +diff --git a/plat/renesas/rcar/bl2_rcar_setup.c b/plat/renesas/rcar/bl2_rcar_setup.c +old mode 100644 +new mode 100755 +index b3a88e3..19f887c +--- a/plat/renesas/rcar/bl2_rcar_setup.c ++++ b/plat/renesas/rcar/bl2_rcar_setup.c +@@ -138,6 +138,9 @@ + #elif RCAR_LSI == RCAR_M3N + #define TARGET_PRODUCT RCAR_PRODUCT_M3N + #define TARGET_NAME "R-Car M3N" ++#elif RCAR_LSI == RCAR_V3M ++#define TARGET_PRODUCT RCAR_PRODUCT_V3M ++#define TARGET_NAME "R-Car V3M" + #endif + + /* for SuspendToRAM */ +@@ -388,6 +391,7 @@ void bl2_early_platform_setup(meminfo_t *mem_layout) + const char *product_h3 = "H3"; + const char *product_m3 = "M3"; + const char *product_m3n = "M3N"; ++ const char *product_v3m = "V3M"; + const char *lcs_cm = "CM"; + const char *lcs_dm = "DM"; + const char *lcs_sd = "SD"; +@@ -462,6 +466,9 @@ void bl2_early_platform_setup(meminfo_t *mem_layout) + case RCAR_PRODUCT_M3N: + str = product_m3n; + break; ++ case RCAR_PRODUCT_V3M: ++ str = product_v3m; ++ break; + default: + str = unknown; + break; +@@ -506,11 +513,13 @@ void bl2_early_platform_setup(meminfo_t *mem_layout) + } + #endif /* RCAR_LSI != RCAR_AUTO */ + ++#if RCAR_LSI != RCAR_V3M + /* Initialize AVS Settings */ + bl2_avs_init(); + + /* Proceed with separated AVS processing */ + bl2_avs_setting(); ++#endif + + switch (modemr_boot_dev) { + case MODEMR_BOOT_DEV_HYPERFLASH160: +@@ -538,8 +547,10 @@ void bl2_early_platform_setup(meminfo_t *mem_layout) + (void)sprintf(msg, "BL2: Boot device is %s\n", str); + NOTICE("%s", msg); + ++#if RCAR_LSI != RCAR_V3M + /* Proceed with separated AVS processing */ + bl2_avs_setting(); ++#endif + + reg = ROM_GetLcs(&lcs); + if (reg == 0U) { +diff --git a/plat/renesas/rcar/ddr/V3M/boot_init_dram_regdef_v3m.h b/plat/renesas/rcar/ddr/V3M/boot_init_dram_regdef_v3m.h +new file mode 100644 +index 0000000..40383ad +--- /dev/null ++++ b/plat/renesas/rcar/ddr/V3M/boot_init_dram_regdef_v3m.h +@@ -0,0 +1,320 @@ ++/* ++ * Copyright (c) 2015-2016, Renesas Electronics Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * - Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * - Neither the name of Renesas nor the names of its contributors may be ++ * used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef BOOT_INIT_DRAM_REGDEF_V3M_H_ ++#define BOOT_INIT_DRAM_REGDEF_V3M_H_ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#define BIT0 0x00000001U ++#define BIT30 0x40000000U ++ ++/* DBSC registers */ ++ ++// modified , last 2016.12.08 ++ ++#define DBSC_V3M_DBSYSCONF0 0xE6790000U ++#define DBSC_V3M_DBSYSCONF1 0xE6790004U ++#define DBSC_V3M_DBPHYCONF0 0xE6790010U ++#define DBSC_V3M_DBKIND 0xE6790020U ++#define DBSC_V3M_DBMEMCONF00 0xE6790030U ++#define DBSC_V3M_DBMEMCONF01 0xE6790034U ++#define DBSC_V3M_DBMEMCONF02 0xE6790038U ++#define DBSC_V3M_DBMEMCONF03 0xE679003CU ++#define DBSC_V3M_DBMEMCONF10 0xE6790040U ++#define DBSC_V3M_DBMEMCONF11 0xE6790044U ++#define DBSC_V3M_DBMEMCONF12 0xE6790048U ++#define DBSC_V3M_DBMEMCONF13 0xE679004CU ++#define DBSC_V3M_DBMEMCONF20 0xE6790050U ++#define DBSC_V3M_DBMEMCONF21 0xE6790054U ++#define DBSC_V3M_DBMEMCONF22 0xE6790058U ++#define DBSC_V3M_DBMEMCONF23 0xE679005CU ++#define DBSC_V3M_DBMEMCONF30 0xE6790060U ++#define DBSC_V3M_DBMEMCONF31 0xE6790064U ++#define DBSC_V3M_DBMEMCONF32 0xE6790068U ++#define DBSC_V3M_DBMEMCONF33 0xE679006CU ++#define DBSC_V3M_DBSYSCNT0 0xE6790100U ++#define DBSC_V3M_DBSVCR1 0xE6790104U ++#define DBSC_V3M_DBSTATE0 0xE6790108U ++#define DBSC_V3M_DBSTATE1 0xE679010CU ++#define DBSC_V3M_DBINTEN 0xE6790180U ++#define DBSC_V3M_DBINTSTAT0 0xE6790184U ++#define DBSC_V3M_DBACEN 0xE6790200U ++#define DBSC_V3M_DBRFEN 0xE6790204U ++#define DBSC_V3M_DBCMD 0xE6790208U ++#define DBSC_V3M_DBWAIT 0xE6790210U ++#define DBSC_V3M_DBSYSCTRL0 0xE6790280U ++#define DBSC_V3M_DBTR0 0xE6790300U ++#define DBSC_V3M_DBTR1 0xE6790304U ++#define DBSC_V3M_DBTR2 0xE6790308U ++#define DBSC_V3M_DBTR3 0xE679030CU ++#define DBSC_V3M_DBTR4 0xE6790310U ++#define DBSC_V3M_DBTR5 0xE6790314U ++#define DBSC_V3M_DBTR6 0xE6790318U ++#define DBSC_V3M_DBTR7 0xE679031CU ++#define DBSC_V3M_DBTR8 0xE6790320U ++#define DBSC_V3M_DBTR9 0xE6790324U ++#define DBSC_V3M_DBTR10 0xE6790328U ++#define DBSC_V3M_DBTR11 0xE679032CU ++#define DBSC_V3M_DBTR12 0xE6790330U ++#define DBSC_V3M_DBTR13 0xE6790334U ++#define DBSC_V3M_DBTR14 0xE6790338U ++#define DBSC_V3M_DBTR15 0xE679033CU ++#define DBSC_V3M_DBTR16 0xE6790340U ++#define DBSC_V3M_DBTR17 0xE6790344U ++#define DBSC_V3M_DBTR18 0xE6790348U ++#define DBSC_V3M_DBTR19 0xE679034CU ++#define DBSC_V3M_DBTR20 0xE6790350U ++#define DBSC_V3M_DBTR21 0xE6790354U ++#define DBSC_V3M_DBTR22 0xE6790358U ++#define DBSC_V3M_DBTR23 0xE679035CU ++#define DBSC_V3M_DBTR24 0xE6790360U ++#define DBSC_V3M_DBTR25 0xE6790364U ++#define DBSC_V3M_DBBL 0xE6790400U ++#define DBSC_V3M_DBRFCNF1 0xE6790414U ++#define DBSC_V3M_DBRFCNF2 0xE6790418U ++#define DBSC_V3M_DBTSPCNF 0xE6790420U ++#define DBSC_V3M_DBCALCNF 0xE6790424U ++#define DBSC_V3M_DBRNK2 0xE6790438U ++#define DBSC_V3M_DBRNK3 0xE679043CU ++#define DBSC_V3M_DBRNK4 0xE6790440U ++#define DBSC_V3M_DBRNK5 0xE6790444U ++#define DBSC_V3M_DBPDNCNF 0xE6790450U ++#define DBSC_V3M_DBODT0 0xE6790460U ++#define DBSC_V3M_DBODT1 0xE6790464U ++#define DBSC_V3M_DBODT2 0xE6790468U ++#define DBSC_V3M_DBODT3 0xE679046CU ++#define DBSC_V3M_DBODT4 0xE6790470U ++#define DBSC_V3M_DBODT5 0xE6790474U ++#define DBSC_V3M_DBODT6 0xE6790478U ++#define DBSC_V3M_DBODT7 0xE679047CU ++#define DBSC_V3M_DBADJ0 0xE6790500U ++#define DBSC_V3M_DBDBICNT 0xE6790518U ++#define DBSC_V3M_DBDFIPMSTRCNF 0xE6790520U ++#define DBSC_V3M_DBDFIPMSTRSTAT 0xE6790524U ++#define DBSC_V3M_DBDFILPCNF 0xE6790528U ++#define DBSC_V3M_DBDFICUPDCNF 0xE679052CU ++#define DBSC_V3M_DBDFISTAT0 0xE6790600U ++#define DBSC_V3M_DBDFICNT0 0xE6790604U ++#define DBSC_V3M_DBPDCNT00 0xE6790610U ++#define DBSC_V3M_DBPDCNT01 0xE6790614U ++#define DBSC_V3M_DBPDCNT02 0xE6790618U ++#define DBSC_V3M_DBPDCNT03 0xE679061CU ++#define DBSC_V3M_DBPDLK0 0xE6790620U ++#define DBSC_V3M_DBPDRGA0 0xE6790624U ++#define DBSC_V3M_DBPDRGD0 0xE6790628U ++#define DBSC_V3M_DBPDSTAT00 0xE6790630U ++#define DBSC_V3M_DBDFISTAT1 0xE6790640U ++#define DBSC_V3M_DBDFICNT1 0xE6790644U ++#define DBSC_V3M_DBPDCNT10 0xE6790650U ++#define DBSC_V3M_DBPDCNT11 0xE6790654U ++#define DBSC_V3M_DBPDCNT12 0xE6790658U ++#define DBSC_V3M_DBPDCNT13 0xE679065CU ++#define DBSC_V3M_DBPDLK1 0xE6790660U ++#define DBSC_V3M_DBPDRGA1 0xE6790664U ++#define DBSC_V3M_DBPDRGD1 0xE6790668U ++#define DBSC_V3M_DBPDSTAT10 0xE6790670U ++#define DBSC_V3M_DBDFISTAT2 0xE6790680U ++#define DBSC_V3M_DBDFICNT2 0xE6790684U ++#define DBSC_V3M_DBPDCNT20 0xE6790690U ++#define DBSC_V3M_DBPDCNT21 0xE6790694U ++#define DBSC_V3M_DBPDCNT22 0xE6790698U ++#define DBSC_V3M_DBPDCNT23 0xE679069CU ++#define DBSC_V3M_DBPDLK2 0xE67906A0U ++#define DBSC_V3M_DBPDRGA2 0xE67906A4U ++#define DBSC_V3M_DBPDRGD2 0xE67906A8U ++#define DBSC_V3M_DBPDSTAT20 0xE67906B0U ++#define DBSC_V3M_DBDFISTAT3 0xE67906C0U ++#define DBSC_V3M_DBDFICNT3 0xE67906C4U ++#define DBSC_V3M_DBPDCNT30 0xE67906D0U ++#define DBSC_V3M_DBPDCNT31 0xE67906D4U ++#define DBSC_V3M_DBPDCNT32 0xE67906D8U ++#define DBSC_V3M_DBPDCNT33 0xE67906DCU ++#define DBSC_V3M_DBPDLK3 0xE67906E0U ++#define DBSC_V3M_DBPDRGA3 0xE67906E4U ++#define DBSC_V3M_DBPDRGD3 0xE67906E8U ++#define DBSC_V3M_DBPDSTAT30 0xE67906F0U ++#define DBSC_V3M_DBBUS0CNF0 0xE6790800U ++#define DBSC_V3M_DBBUS0CNF1 0xE6790804U ++#define DBSC_V3M_DBCAM0CNF1 0xE6790904U ++#define DBSC_V3M_DBCAM0CNF2 0xE6790908U ++#define DBSC_V3M_DBCAM0CNF3 0xE679090CU ++#define DBSC_V3M_DBCAM0CTRL0 0xE6790940U ++#define DBSC_V3M_DBCAM0STAT0 0xE6790980U ++#define DBSC_V3M_DBCAM1STAT0 0xE6790990U ++#define DBSC_V3M_DBBCAMSWAP 0xE67909F0U ++#define DBSC_V3M_DBBCAMDIS 0xE67909FCU ++#define DBSC_V3M_DBSCHCNT0 0xE6791000U ++#define DBSC_V3M_DBSCHCNT1 0xE6791004U ++#define DBSC_V3M_DBSCHSZ0 0xE6791010U ++#define DBSC_V3M_DBSCHRW0 0xE6791020U ++#define DBSC_V3M_DBSCHRW1 0xE6791024U ++#define DBSC_V3M_DBSCHQOS00 0xE6791030U ++#define DBSC_V3M_DBSCHQOS01 0xE6791034U ++#define DBSC_V3M_DBSCHQOS02 0xE6791038U ++#define DBSC_V3M_DBSCHQOS03 0xE679103CU ++#define DBSC_V3M_DBSCHQOS10 0xE6791040U ++#define DBSC_V3M_DBSCHQOS11 0xE6791044U ++#define DBSC_V3M_DBSCHQOS12 0xE6791048U ++#define DBSC_V3M_DBSCHQOS13 0xE679104CU ++#define DBSC_V3M_DBSCHQOS20 0xE6791050U ++#define DBSC_V3M_DBSCHQOS21 0xE6791054U ++#define DBSC_V3M_DBSCHQOS22 0xE6791058U ++#define DBSC_V3M_DBSCHQOS23 0xE679105CU ++#define DBSC_V3M_DBSCHQOS30 0xE6791060U ++#define DBSC_V3M_DBSCHQOS31 0xE6791064U ++#define DBSC_V3M_DBSCHQOS32 0xE6791068U ++#define DBSC_V3M_DBSCHQOS33 0xE679106CU ++#define DBSC_V3M_DBSCHQOS40 0xE6791070U ++#define DBSC_V3M_DBSCHQOS41 0xE6791074U ++#define DBSC_V3M_DBSCHQOS42 0xE6791078U ++#define DBSC_V3M_DBSCHQOS43 0xE679107CU ++#define DBSC_V3M_DBSCHQOS50 0xE6791080U ++#define DBSC_V3M_DBSCHQOS51 0xE6791084U ++#define DBSC_V3M_DBSCHQOS52 0xE6791088U ++#define DBSC_V3M_DBSCHQOS53 0xE679108CU ++#define DBSC_V3M_DBSCHQOS60 0xE6791090U ++#define DBSC_V3M_DBSCHQOS61 0xE6791094U ++#define DBSC_V3M_DBSCHQOS62 0xE6791098U ++#define DBSC_V3M_DBSCHQOS63 0xE679109CU ++#define DBSC_V3M_DBSCHQOS70 0xE67910A0U ++#define DBSC_V3M_DBSCHQOS71 0xE67910A4U ++#define DBSC_V3M_DBSCHQOS72 0xE67910A8U ++#define DBSC_V3M_DBSCHQOS73 0xE67910ACU ++#define DBSC_V3M_DBSCHQOS80 0xE67910B0U ++#define DBSC_V3M_DBSCHQOS81 0xE67910B4U ++#define DBSC_V3M_DBSCHQOS82 0xE67910B8U ++#define DBSC_V3M_DBSCHQOS83 0xE67910BCU ++#define DBSC_V3M_DBSCHQOS90 0xE67910C0U ++#define DBSC_V3M_DBSCHQOS91 0xE67910C4U ++#define DBSC_V3M_DBSCHQOS92 0xE67910C8U ++#define DBSC_V3M_DBSCHQOS93 0xE67910CCU ++#define DBSC_V3M_DBSCHQOS100 0xE67910D0U ++#define DBSC_V3M_DBSCHQOS101 0xE67910D4U ++#define DBSC_V3M_DBSCHQOS102 0xE67910D8U ++#define DBSC_V3M_DBSCHQOS103 0xE67910DCU ++#define DBSC_V3M_DBSCHQOS110 0xE67910E0U ++#define DBSC_V3M_DBSCHQOS111 0xE67910E4U ++#define DBSC_V3M_DBSCHQOS112 0xE67910E8U ++#define DBSC_V3M_DBSCHQOS113 0xE67910ECU ++#define DBSC_V3M_DBSCHQOS120 0xE67910F0U ++#define DBSC_V3M_DBSCHQOS121 0xE67910F4U ++#define DBSC_V3M_DBSCHQOS122 0xE67910F8U ++#define DBSC_V3M_DBSCHQOS123 0xE67910FCU ++#define DBSC_V3M_DBSCHQOS130 0xE6791100U ++#define DBSC_V3M_DBSCHQOS131 0xE6791104U ++#define DBSC_V3M_DBSCHQOS132 0xE6791108U ++#define DBSC_V3M_DBSCHQOS133 0xE679110CU ++#define DBSC_V3M_DBSCHQOS140 0xE6791110U ++#define DBSC_V3M_DBSCHQOS141 0xE6791114U ++#define DBSC_V3M_DBSCHQOS142 0xE6791118U ++#define DBSC_V3M_DBSCHQOS143 0xE679111CU ++#define DBSC_V3M_DBSCHQOS150 0xE6791120U ++#define DBSC_V3M_DBSCHQOS151 0xE6791124U ++#define DBSC_V3M_DBSCHQOS152 0xE6791128U ++#define DBSC_V3M_DBSCHQOS153 0xE679112CU ++#define DBSC_V3M_SCFCTST0 0xE6791700U ++#define DBSC_V3M_SCFCTST1 0xE6791708U ++#define DBSC_V3M_SCFCTST2 0xE679170CU ++#define DBSC_V3M_DBMRRDR0 0xE6791800U ++#define DBSC_V3M_DBMRRDR1 0xE6791804U ++#define DBSC_V3M_DBMRRDR2 0xE6791808U ++#define DBSC_V3M_DBMRRDR3 0xE679180CU ++#define DBSC_V3M_DBMRRDR4 0xE6791810U ++#define DBSC_V3M_DBMRRDR5 0xE6791814U ++#define DBSC_V3M_DBMRRDR6 0xE6791818U ++#define DBSC_V3M_DBMRRDR7 0xE679181CU ++#define DBSC_V3M_DBDTMP0 0xE6791820U ++#define DBSC_V3M_DBDTMP1 0xE6791824U ++#define DBSC_V3M_DBDTMP2 0xE6791828U ++#define DBSC_V3M_DBDTMP3 0xE679182CU ++#define DBSC_V3M_DBDTMP4 0xE6791830U ++#define DBSC_V3M_DBDTMP5 0xE6791834U ++#define DBSC_V3M_DBDTMP6 0xE6791838U ++#define DBSC_V3M_DBDTMP7 0xE679183CU ++#define DBSC_V3M_DBDQSOSC00 0xE6791840U ++#define DBSC_V3M_DBDQSOSC01 0xE6791844U ++#define DBSC_V3M_DBDQSOSC10 0xE6791848U ++#define DBSC_V3M_DBDQSOSC11 0xE679184CU ++#define DBSC_V3M_DBDQSOSC20 0xE6791850U ++#define DBSC_V3M_DBDQSOSC21 0xE6791854U ++#define DBSC_V3M_DBDQSOSC30 0xE6791858U ++#define DBSC_V3M_DBDQSOSC31 0xE679185CU ++#define DBSC_V3M_DBDQSOSC40 0xE6791860U ++#define DBSC_V3M_DBDQSOSC41 0xE6791864U ++#define DBSC_V3M_DBDQSOSC50 0xE6791868U ++#define DBSC_V3M_DBDQSOSC51 0xE679186CU ++#define DBSC_V3M_DBDQSOSC60 0xE6791870U ++#define DBSC_V3M_DBDQSOSC61 0xE6791874U ++#define DBSC_V3M_DBDQSOSC70 0xE6791878U ++#define DBSC_V3M_DBDQSOSC71 0xE679187CU ++#define DBSC_V3M_DBOSCTHH00 0xE6791880U ++#define DBSC_V3M_DBOSCTHH01 0xE6791884U ++#define DBSC_V3M_DBOSCTHH10 0xE6791888U ++#define DBSC_V3M_DBOSCTHH11 0xE679188CU ++#define DBSC_V3M_DBOSCTHH20 0xE6791890U ++#define DBSC_V3M_DBOSCTHH21 0xE6791894U ++#define DBSC_V3M_DBOSCTHH30 0xE6791898U ++#define DBSC_V3M_DBOSCTHH31 0xE679189CU ++#define DBSC_V3M_DBOSCTHH40 0xE67918A0U ++#define DBSC_V3M_DBOSCTHH41 0xE67918A4U ++#define DBSC_V3M_DBOSCTHH50 0xE67918A8U ++#define DBSC_V3M_DBOSCTHH51 0xE67918ACU ++#define DBSC_V3M_DBOSCTHH60 0xE67918B0U ++#define DBSC_V3M_DBOSCTHH61 0xE67918B4U ++#define DBSC_V3M_DBOSCTHH70 0xE67918B8U ++#define DBSC_V3M_DBOSCTHH71 0xE67918BCU ++#define DBSC_V3M_DBOSCTHL00 0xE67918C0U ++#define DBSC_V3M_DBOSCTHL01 0xE67918C4U ++#define DBSC_V3M_DBOSCTHL10 0xE67918C8U ++#define DBSC_V3M_DBOSCTHL11 0xE67918CCU ++#define DBSC_V3M_DBOSCTHL20 0xE67918D0U ++#define DBSC_V3M_DBOSCTHL21 0xE67918D4U ++#define DBSC_V3M_DBOSCTHL30 0xE67918D8U ++#define DBSC_V3M_DBOSCTHL31 0xE67918DCU ++#define DBSC_V3M_DBOSCTHL40 0xE67918E0U ++#define DBSC_V3M_DBOSCTHL41 0xE67918E4U ++#define DBSC_V3M_DBOSCTHL50 0xE67918E8U ++#define DBSC_V3M_DBOSCTHL51 0xE67918ECU ++#define DBSC_V3M_DBOSCTHL60 0xE67918F0U ++#define DBSC_V3M_DBOSCTHL61 0xE67918F4U ++#define DBSC_V3M_DBOSCTHL70 0xE67918F8U ++#define DBSC_V3M_DBOSCTHL71 0xE67918FCU ++#define DBSC_V3M_DBMEMSWAPCONF0 0xE6792000U ++ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* BOOT_INIT_DRAM_REGDEF_V3M_H_*/ +\ No newline at end of file +diff --git a/plat/renesas/rcar/ddr/V3M/boot_init_dram_v3m.h b/plat/renesas/rcar/ddr/V3M/boot_init_dram_v3m.h +new file mode 100644 +index 0000000..3b0cf12 +--- /dev/null ++++ b/plat/renesas/rcar/ddr/V3M/boot_init_dram_v3m.h +@@ -0,0 +1,37 @@ ++/* ++ * Copyright (c) 2015-2016, Renesas Electronics Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * - Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * - Neither the name of Renesas nor the names of its contributors may be ++ * used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef BOOT_INIT_DRAM_V3M__ ++#define BOOT_INIT_DRAM_V3M__ ++ ++extern void init_ddr_v3m1600(void); ++ ++#endif /* BOOT_INIT_DRAM_V3M__ */ +diff --git a/plat/renesas/rcar/ddr/V3M/ddr_init_v3m.c b/plat/renesas/rcar/ddr/V3M/ddr_init_v3m.c +new file mode 100644 +index 0000000..4083226 +--- /dev/null ++++ b/plat/renesas/rcar/ddr/V3M/ddr_init_v3m.c +@@ -0,0 +1,356 @@ ++/* ++ * Copyright (c) 2015-2016, Renesas Electronics Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * - Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * - Neither the name of Renesas nor the names of its contributors may be ++ * used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include <stdint.h> ++#include "boot_init_dram_regdef_v3m.h" ++ ++void WriteReg_32(uintptr_t a, uint32_t v) ++{ ++ *(volatile uint32_t*)a = v; ++} ++ ++uint32_t ReadReg_32(uintptr_t a) ++{ ++ uint32_t w = *(volatile uint32_t*)a; ++ return w; ++} ++ ++uint32_t init_ddr_v3m1600(void) ++{ ++ // last modified 2016.12.16 ++ ++ uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12; ++ ++ WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); ++ WriteReg_32(DBSC_V3M_DBKIND,0x00000007); ++// WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02); // 1GB: Eagle ++ WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02); // 2GB: V3MSK ++ WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001); ++ WriteReg_32(DBSC_V3M_DBTR0,0x0000000B); ++ WriteReg_32(DBSC_V3M_DBTR1,0x00000008); ++ WriteReg_32(DBSC_V3M_DBTR3,0x0000000B); ++ WriteReg_32(DBSC_V3M_DBTR4,0x000B000B); ++ WriteReg_32(DBSC_V3M_DBTR5,0x00000027); ++ WriteReg_32(DBSC_V3M_DBTR6,0x0000001C); ++ WriteReg_32(DBSC_V3M_DBTR7,0x00060006); ++ WriteReg_32(DBSC_V3M_DBTR8,0x00000020); ++ WriteReg_32(DBSC_V3M_DBTR9,0x00000006); ++ WriteReg_32(DBSC_V3M_DBTR10,0x0000000C); ++ WriteReg_32(DBSC_V3M_DBTR11,0x0000000B); ++ WriteReg_32(DBSC_V3M_DBTR12,0x00120012); ++ WriteReg_32(DBSC_V3M_DBTR13,0x01180118); ++ WriteReg_32(DBSC_V3M_DBTR14,0x00140005); ++ WriteReg_32(DBSC_V3M_DBTR15,0x00050004); ++ WriteReg_32(DBSC_V3M_DBTR16,0x071D0305); ++ WriteReg_32(DBSC_V3M_DBTR17,0x040C0010); ++ WriteReg_32(DBSC_V3M_DBTR18,0x00000200); ++ WriteReg_32(DBSC_V3M_DBTR19,0x01000040); ++ WriteReg_32(DBSC_V3M_DBTR20,0x02000120); ++ WriteReg_32(DBSC_V3M_DBTR21,0x00040004); ++ WriteReg_32(DBSC_V3M_DBBL,0x00000000); ++ WriteReg_32(DBSC_V3M_DBODT0,0x00000001); ++ WriteReg_32(DBSC_V3M_DBADJ0,0x00000001); ++ WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00082010); ++ WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x00002000); ++ WriteReg_32(DBSC_V3M_DBSCHCNT0,0x080f003f); ++ WriteReg_32(DBSC_V3M_DBSCHCNT1,0x00001010); ++ WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001); ++ WriteReg_32(DBSC_V3M_DBSCHRW0,0x00000200); ++ WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000040); ++ WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000600); ++ WriteReg_32(DBSC_V3M_DBSCHQOS41,0x00000480); ++ WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000300); ++ WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000180); ++ WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000400); ++ WriteReg_32(DBSC_V3M_DBSCHQOS91,0x00000300); ++ WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200); ++ WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100); ++ WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000300); ++ WriteReg_32(DBSC_V3M_DBSCHQOS131,0x00000240); ++ WriteReg_32(DBSC_V3M_DBSCHQOS132,0x00000180); ++ WriteReg_32(DBSC_V3M_DBSCHQOS133,0x000000c0); ++ WriteReg_32(DBSC_V3M_DBSCHQOS140,0x00000200); ++ WriteReg_32(DBSC_V3M_DBSCHQOS141,0x00000180); ++ WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000100); ++ WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000080); ++ WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000100); ++ WriteReg_32(DBSC_V3M_DBSCHQOS151,0x000000c0); ++ WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000080); ++ WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000040); ++ WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002); ++ WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00040C04); ++ WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000001c4); ++ WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000003); ++ WriteReg_32(DBSC_V3M_DBSCHRW1,0x001a0080); ++ WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010); ++ ++ WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A); ++ WriteReg_32(DBSC_V3M_DBCMD,0x01000001); ++ WriteReg_32(DBSC_V3M_DBCMD,0x08000000); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); ++ while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); ++ ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); ++ while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); ++ ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); ++ while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); ++ ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C700); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); ++ while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); ++ ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X08C0C170); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X2D9C0B66); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X2A88C400); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X30005200); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A9C9); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000D70); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000018); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X13C03C10); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); ++ while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); ++ ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181); ++ WriteReg_32(DBSC_V3M_DBCMD,0x08000001); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); ++ while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); ++ ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); ++ while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); ++ ++ for (uint32_t i = 0; i<4; i++) ++ { ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20); ++ RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8; ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20); ++ RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ; ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20); ++ RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ; ++ if ( RegVal_R6 > 0 ) ++ { ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); ++ RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; ++ ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); ++ RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6); ++ } else ++ { ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); ++ RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7); ++ ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); ++ RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2); ++ } ++ } ++ ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00A0); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); ++ while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); ++ ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00B8); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); ++ while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); ++ ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); ++ while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); ++ ++ for (uint32_t i = 0; i < 4; i++) ++ { ++ WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B1 + i * 0x20); ++ RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8; ++ WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B4 + i * 0x20); ++ RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF); ++ ++ WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B3 + i * 0x20); ++ RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007); ++ RegVal_R12 = (RegVal_R5 >> 2); ++ if (RegVal_R6 - RegVal_R12 > 0) ++ { ++ WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); ++ RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8); ++ ++ WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); ++ WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R7 + 1) & 0X00000007) | RegVal_R2); ++ WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); ++ RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00); ++ ++ WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); ++ WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2); ++ } ++ else ++ { ++ WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); ++ RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8); ++ WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); ++ WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal_R7 & 0X00000007) | RegVal_R2); ++ WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); ++ RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00); ++ WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); ++ WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 + RegVal_R5 + (RegVal_R5 >> 1) + RegVal_R12) & 0X000000FF) | RegVal_R2); ++ } ++ } ++ ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); ++ while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); ++ ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C700); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); ++ while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 ); ++ WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); ++ WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E); ++ ++ WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000); ++ WriteReg_32(DBSC_V3M_DBBUS0CNF0,0x00010001); ++ WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200E); ++ WriteReg_32(DBSC_V3M_DBRFCNF1,0x00081860); ++ WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000); ++ WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001); ++ WriteReg_32(DBSC_V3M_DBRFEN,0x00000001); ++ WriteReg_32(DBSC_V3M_DBACEN,0x00000001); ++ WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000); ++ WriteReg_32(0xE67F0024, 0x00000001); ++ WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); ++ ++ return 1; ++} ++ +diff --git a/plat/renesas/rcar/ddr/boot_init_dram.c b/plat/renesas/rcar/ddr/boot_init_dram.c +index 7c55a04..87360a6 100644 +--- a/plat/renesas/rcar/ddr/boot_init_dram.c ++++ b/plat/renesas/rcar/ddr/boot_init_dram.c +@@ -43,6 +43,10 @@ + #include "dram_sub_func.h" + #include "micro_wait.h" + ++#if RCAR_LSI == RCAR_V3M /* V3M */ ++ #include "V3M/boot_init_dram_v3m.h" ++#endif ++ + #define DDR_BACKUPMODE + #define FATAL_MSG(x) NOTICE(x) + /******************************************************************************* +@@ -3583,6 +3587,13 @@ int32_t InitDram(void) + Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; + ++#if RCAR_LSI == RCAR_V3M ++ if (Prr_Product == PRR_PRODUCT_V3M) { ++ init_ddr_v3m1600(); ++ return INITDRAM_OK; ++ } ++#endif ++ + if (Prr_Product == PRR_PRODUCT_H3) { + if(PRR_PRODUCT_11>=Prr_Cut){ + pDDR_REGDEF_TBL = (uint32_t *)&DDR_REGDEF_TBL[0][0]; +diff --git a/plat/renesas/rcar/ddr/boot_init_dram_regdef.h b/plat/renesas/rcar/ddr/boot_init_dram_regdef.h +index 5ae7c3f..c5ebf8e 100644 +--- a/plat/renesas/rcar/ddr/boot_init_dram_regdef.h ++++ b/plat/renesas/rcar/ddr/boot_init_dram_regdef.h +@@ -75,6 +75,7 @@ + #define PRR_CUT_MASK (0x000000FFU) + #define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */ + #define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ ++#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */ + #define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */ + #define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */ + #define PRR_PRODUCT_10 (0x00U) /* ver 1.0 */ +diff --git a/plat/renesas/rcar/ddr/ddr.mk b/plat/renesas/rcar/ddr/ddr.mk +index e0b58ed..5bcd49f 100644 +--- a/plat/renesas/rcar/ddr/ddr.mk ++++ b/plat/renesas/rcar/ddr/ddr.mk +@@ -31,3 +31,6 @@ + + BL2_SOURCES += plat/renesas/rcar/ddr/boot_init_dram.c + BL2_SOURCES += plat/renesas/rcar/ddr/dram_sub_func.c ++ifeq (${RCAR_LSI},${RCAR_V3M}) ++ BL2_SOURCES += plat/renesas/rcar/ddr/V3M/ddr_init_v3m.c ++endif +diff --git a/plat/renesas/rcar/drivers/board/board.c b/plat/renesas/rcar/drivers/board/board.c +index d38cf36..87c5faf 100644 +--- a/plat/renesas/rcar/drivers/board/board.c ++++ b/plat/renesas/rcar/drivers/board/board.c +@@ -37,7 +37,7 @@ + * Defines + ************************************************************************/ + #ifndef BOARD_DEFAULT +-#define BOARD_DEFAULT (BOARD_SALVATOR_X << BOARD_CODE_SHIFT) ++#define BOARD_DEFAULT (BOARD_UNKNOWN << BOARD_CODE_SHIFT) + #endif + + #define SLAVE_ADDR_EEPROM (0x50U) +diff --git a/plat/renesas/rcar/drivers/rom/rom_api.c b/plat/renesas/rcar/drivers/rom/rom_api.c +index b54ed20..186660d 100644 +--- a/plat/renesas/rcar/drivers/rom/rom_api.c ++++ b/plat/renesas/rcar/drivers/rom/rom_api.c +@@ -52,8 +52,9 @@ static uint32_t get_table_index(void); + #define OLD_API_TABLE1 (0U) /* H3 WS1.0/WS1.1 */ + #define OLD_API_TABLE2 (1U) /* H3 WS2.0 */ + #define OLD_API_TABLE3 (2U) /* M3 WS1.0/1.05 */ +-#define NEW_API_TABLE (3U) /* M3 WS1.06 or later, M3N, E3 */ +-#define API_TABLE_MAX (4U) /* table max */ ++#define NEW_API_TABLE (3U) /* M3 WS1.06 or later, M3N, E3, V3M WS2.0 */ ++#define NEW_API_TABLE2 (4U) /* V3M WS1.0 */ ++#define API_TABLE_MAX (5U) /* table max */ + + + +@@ -66,7 +67,8 @@ uint32_t ROM_SecureBootAPI( uint32_t *pKeyCert, + 0xEB10DD64U, /* H3 WS1.0/WS1.1 */ + 0xEB116ED4U, /* H3 WS2.0 */ + 0xEB1102FCU, /* M3 WS1.0/1.05 */ +- 0xEB100180U /* M3 WS1.06 or later, M3N, E3 */ ++ 0xEB100180U, /* M3 WS1.06 or later, M3N, E3, V3M WS2.0 */ ++ 0xEB110128U, /* V3M WS1.0 */ + }; + + ROM_SECURE_BOOT_API func; +@@ -86,7 +88,8 @@ uint32_t ROM_GetLcs(uint32_t *pLcs) + 0xEB10DFE0U, /* H3 WS1.0/WS1.1 */ + 0xEB117150U, /* H3 WS2.0 */ + 0xEB110578U, /* M3 WS1.0/1.05 */ +- 0xEB10018CU /* M3 WS1.06 or later, M3N, E3 */ ++ 0xEB10018CU, /* M3 WS1.06 or later, M3N, E3, V3M WS2.0 */ ++ 0xEB1103A4U, /* V3M WS1.0 */ + }; + + ROM_GETLCS_API func; +@@ -135,6 +138,13 @@ static uint32_t get_table_index(void) + index = NEW_API_TABLE; /* M3 WS1.1 or later */ + } + break; ++ case RCAR_PRODUCT_V3M: ++ if (cut_ver == RCAR_CUT_ES10) { ++ index = NEW_API_TABLE2; /* V3M WS1.0 */ ++ } else { ++ index = NEW_API_TABLE; /* V3M WS2.0 or later */ ++ } ++ break; + default: + index = NEW_API_TABLE; /* assume that M3N and E3 */ + break; +diff --git a/plat/renesas/rcar/drivers/scif/scif.S b/plat/renesas/rcar/drivers/scif/scif.S +index 3fc5814..bb9bfef 100644 +--- a/plat/renesas/rcar/drivers/scif/scif.S ++++ b/plat/renesas/rcar/drivers/scif/scif.S +@@ -40,13 +40,26 @@ + + /* module stop */ + #define CPG_BASE (0xE6150000) ++#define CPG_SMSTPCR2 (0x0118) + #define CPG_SMSTPCR3 (0x013C) ++#define MSTP207 (1 << 7) + #define MSTP310 (1 << 10) + #define CPG_CPGWPR (0x0900) + +-/* SCIF2 */ ++/* SCIF */ ++#define SCIF0_BASE (0xE6E60000) /* SCIF-0 base address */ + #define SCIF2_BASE (0xE6E88000) /* SCIF-2 base address */ + ++#if RCAR_LSI == RCAR_V3M /* V3M */ ++#define SCIF_BASE SCIF0_BASE ++#define CPG_SMSTPCR CPG_SMSTPCR2 ++#define MSTP MSTP207 ++#else ++#define SCIF_BASE SCIF2_BASE ++#define CPG_SMSTPCR CPG_SMSTPCR3 ++#define MSTP MSTP310 ++#endif ++ + #define SCIF_SCSMR (0x00) /* Serial mode register */ + #define SCIF_SCBRR (0x04) /* Bit rate register */ + #define SCIF_SCSCR (0x08) /* Serial control register */ +@@ -163,13 +176,13 @@ endfunc console_init + */ + func console_core_init + ldr x0, =CPG_BASE +- ldr w1, [x0, #CPG_SMSTPCR3] +- and w1, w1, #~MSTP310 /* MSTP310=0 */ ++ ldr w1, [x0, #CPG_SMSTPCR] ++ and w1, w1, #~MSTP + mvn w2, w1 + str w2, [x0, #CPG_CPGWPR] +- str w1, [x0, #CPG_SMSTPCR3] ++ str w1, [x0, #CPG_SMSTPCR] + +- ldr x0, =SCIF2_BASE ++ ldr x0, =SCIF_BASE + /* Clear bits TE and RE in SCSCR to 0 */ + mov w1, #(SCSCR_TE_DIS + SCSCR_RE_DIS) /* TE=0,RE=0 */ + strh w1, [x0, #SCIF_SCSCR] +@@ -253,7 +266,7 @@ endfunc console_putc + * -------------------------------------------------------- + */ + func console_core_putc +- ldr x1, =SCIF2_BASE ++ ldr x1, =SCIF_BASE + cmp w0, #0xA + /* Prepend '\r' to '\n' */ + bne 2f +@@ -294,7 +307,7 @@ endfunc console_getc + * ----------------------------------------------- + */ + func console_finalize +- ldr x0, =SCIF2_BASE ++ ldr x0, =SCIF_BASE + 1: + ldrh w1, [x0, #SCIF_SCFDR] + ubfx w1, w1, #8, #5 +@@ -306,7 +319,7 @@ func console_finalize + bl micro_wait + mov x30, x3 + +- ldr x0, =SCIF2_BASE ++ ldr x0, =SCIF_BASE + ldrh w1, [x0, #SCIF_SCSCR] + and w1, w1, #~(SCSCR_TE_EN + SCSCR_RE_EN) /* TE=0,RE=0 */ + strh w1, [x0, #SCIF_SCSCR] +diff --git a/plat/renesas/rcar/include/bl2_dma_register.h b/plat/renesas/rcar/include/bl2_dma_register.h +index 7c7e7a8..4bc9341 100644 +--- a/plat/renesas/rcar/include/bl2_dma_register.h ++++ b/plat/renesas/rcar/include/bl2_dma_register.h +@@ -32,7 +32,11 @@ + #ifndef BL2_DMA_REGISTER_H__ + #define BL2_DMA_REGISTER_H__ + ++#if RCAR_LSI == RCAR_V3M /* V3M */ ++#define DMACH 16 /* DMA CH setting (0/16/32) */ ++#else + #define DMACH 0 /* DMA CH setting (0/16/32) */ ++#endif + + #if (DMACH==0) /* SYS-DMAC0 (CH0) */ + #define SYS_DMAC_BIT ((uint32_t)1U << 19U) +diff --git a/plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c b/plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c +new file mode 100644 +index 0000000..0344189 +--- /dev/null ++++ b/plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c +@@ -0,0 +1,1076 @@ ++/* ++ * Copyright (c) 2015-2017, Renesas Electronics Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * - Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * - Neither the name of Renesas nor the names of its contributors may be ++ * used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include <stdint.h> /* for uint32_t */ ++#include <mmio.h> ++#include "bl2_cpg_init.h" ++#include "pfc_init_v3m.h" ++#include "rcar_def.h" ++ ++#define RST_MODEMR 0xE6160060 // Mode Monitor Register ++ ++/* GPIO base address */ ++#define GPIO_BASE (0xE6050000U) ++ ++/* GPIO registers */ ++#define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U) ++#define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U) ++#define GPIO_OUTDT0 (GPIO_BASE + 0x0008U) ++#define GPIO_INDT0 (GPIO_BASE + 0x000CU) ++#define GPIO_INTDT0 (GPIO_BASE + 0x0010U) ++#define GPIO_INTCLR0 (GPIO_BASE + 0x0014U) ++#define GPIO_INTMSK0 (GPIO_BASE + 0x0018U) ++#define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU) ++#define GPIO_POSNEG0 (GPIO_BASE + 0x0020U) ++#define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U) ++#define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U) ++#define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U) ++#define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU) ++#define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U) ++#define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U) ++#define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U) ++#define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU) ++#define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U) ++#define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U) ++#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U) ++#define GPIO_INDT1 (GPIO_BASE + 0x100CU) ++#define GPIO_INTDT1 (GPIO_BASE + 0x1010U) ++#define GPIO_INTCLR1 (GPIO_BASE + 0x1014U) ++#define GPIO_INTMSK1 (GPIO_BASE + 0x1018U) ++#define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU) ++#define GPIO_POSNEG1 (GPIO_BASE + 0x1020U) ++#define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U) ++#define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U) ++#define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U) ++#define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU) ++#define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U) ++#define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U) ++#define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U) ++#define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU) ++#define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U) ++#define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U) ++#define GPIO_OUTDT2 (GPIO_BASE + 0x2008U) ++#define GPIO_INDT2 (GPIO_BASE + 0x200CU) ++#define GPIO_INTDT2 (GPIO_BASE + 0x2010U) ++#define GPIO_INTCLR2 (GPIO_BASE + 0x2014U) ++#define GPIO_INTMSK2 (GPIO_BASE + 0x2018U) ++#define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU) ++#define GPIO_POSNEG2 (GPIO_BASE + 0x2020U) ++#define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U) ++#define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U) ++#define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U) ++#define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU) ++#define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U) ++#define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U) ++#define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U) ++#define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU) ++#define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U) ++#define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U) ++#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U) ++#define GPIO_INDT3 (GPIO_BASE + 0x300CU) ++#define GPIO_INTDT3 (GPIO_BASE + 0x3010U) ++#define GPIO_INTCLR3 (GPIO_BASE + 0x3014U) ++#define GPIO_INTMSK3 (GPIO_BASE + 0x3018U) ++#define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU) ++#define GPIO_POSNEG3 (GPIO_BASE + 0x3020U) ++#define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U) ++#define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U) ++#define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U) ++#define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU) ++#define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U) ++#define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U) ++#define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U) ++#define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU) ++#define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U) ++#define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U) ++#define GPIO_OUTDT4 (GPIO_BASE + 0x4008U) ++#define GPIO_INDT4 (GPIO_BASE + 0x400CU) ++#define GPIO_INTDT4 (GPIO_BASE + 0x4010U) ++#define GPIO_INTCLR4 (GPIO_BASE + 0x4014U) ++#define GPIO_INTMSK4 (GPIO_BASE + 0x4018U) ++#define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU) ++#define GPIO_POSNEG4 (GPIO_BASE + 0x4020U) ++#define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U) ++#define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U) ++#define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U) ++#define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU) ++#define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U) ++#define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U) ++#define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U) ++#define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU) ++#define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U) ++#define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U) ++#define GPIO_OUTDT5 (GPIO_BASE + 0x5008U) ++#define GPIO_INDT5 (GPIO_BASE + 0x500CU) ++#define GPIO_INTDT5 (GPIO_BASE + 0x5010U) ++#define GPIO_INTCLR5 (GPIO_BASE + 0x5014U) ++#define GPIO_INTMSK5 (GPIO_BASE + 0x5018U) ++#define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU) ++#define GPIO_POSNEG5 (GPIO_BASE + 0x5020U) ++#define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U) ++#define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U) ++#define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U) ++#define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU) ++#define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U) ++#define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U) ++#define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U) ++#define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU) ++ ++/* Pin functon base address */ ++#define PFC_BASE (0xE6060000U) ++ ++/* Pin functon registers */ ++#define PFC_PMMR (PFC_BASE + 0x0000U) ++#define PFC_GPSR0 (PFC_BASE + 0x0100U) ++#define PFC_GPSR1 (PFC_BASE + 0x0104U) ++#define PFC_GPSR2 (PFC_BASE + 0x0108U) ++#define PFC_GPSR3 (PFC_BASE + 0x010CU) ++#define PFC_GPSR4 (PFC_BASE + 0x0110U) ++#define PFC_GPSR5 (PFC_BASE + 0x0114U) ++#define PFC_IPSR0 (PFC_BASE + 0x0200U) ++#define PFC_IPSR1 (PFC_BASE + 0x0204U) ++#define PFC_IPSR2 (PFC_BASE + 0x0208U) ++#define PFC_IPSR3 (PFC_BASE + 0x020CU) ++#define PFC_IPSR4 (PFC_BASE + 0x0210U) ++#define PFC_IPSR5 (PFC_BASE + 0x0214U) ++#define PFC_IPSR6 (PFC_BASE + 0x0218U) ++#define PFC_IPSR7 (PFC_BASE + 0x021CU) ++#define PFC_IPSR8 (PFC_BASE + 0x0220U) ++#define PFC_IOCTRL30 (PFC_BASE + 0x0380U) ++#define PFC_IOCTRL31 (PFC_BASE + 0x0384U) ++#define PFC_IOCTRL32 (PFC_BASE + 0x0388U) ++#define PFC_IOCTRL40 (PFC_BASE + 0x03C0U) ++#define PFC_PUEN0 (PFC_BASE + 0x0400U) ++#define PFC_PUEN1 (PFC_BASE + 0x0404U) ++#define PFC_PUEN2 (PFC_BASE + 0x0408U) ++#define PFC_PUEN3 (PFC_BASE + 0x040CU) ++#define PFC_PUD0 (PFC_BASE + 0x0440U) ++#define PFC_PUD1 (PFC_BASE + 0x0444U) ++#define PFC_PUD2 (PFC_BASE + 0x0448U) ++#define PFC_PUD3 (PFC_BASE + 0x044CU) ++#define PFC_MOD_SEL0 (PFC_BASE + 0x0500U) ++ ++/* Pin functon bit */ ++#define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) ++#define GPSR0_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) ++#define GPSR0_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) ++#define GPSR0_DU_DOTCLKOUT ((uint32_t)1U << 18U) ++#define GPSR0_DU_DB7 ((uint32_t)1U << 17U) ++#define GPSR0_DU_DB6 ((uint32_t)1U << 16U) ++#define GPSR0_DU_DB5 ((uint32_t)1U << 15U) ++#define GPSR0_DU_DB4 ((uint32_t)1U << 14U) ++#define GPSR0_DU_DB3 ((uint32_t)1U << 13U) ++#define GPSR0_DU_DB2 ((uint32_t)1U << 12U) ++#define GPSR0_DU_DG7 ((uint32_t)1U << 11U) ++#define GPSR0_DU_DG6 ((uint32_t)1U << 10U) ++#define GPSR0_DU_DG5 ((uint32_t)1U << 9U) ++#define GPSR0_DU_DG4 ((uint32_t)1U << 8U) ++#define GPSR0_DU_DG3 ((uint32_t)1U << 7U) ++#define GPSR0_DU_DG2 ((uint32_t)1U << 6U) ++#define GPSR0_DU_DR7 ((uint32_t)1U << 5U) ++#define GPSR0_DU_DR6 ((uint32_t)1U << 4U) ++#define GPSR0_DU_DR5 ((uint32_t)1U << 3U) ++#define GPSR0_DU_DR4 ((uint32_t)1U << 2U) ++#define GPSR0_DU_DR3 ((uint32_t)1U << 1U) ++#define GPSR0_DU_DR2 ((uint32_t)1U << 0U) ++ ++#define GPSR1_DIGRF_CLKOUT ((uint32_t)1U << 27U) ++#define GPSR1_DIGRF_CLKIN ((uint32_t)1U << 26U) ++#define GPSR1_CANFD_CLK ((uint32_t)1U << 25U) ++#define GPSR1_CANFD1_RX ((uint32_t)1U << 24U) ++#define GPSR1_CANFD1_TX ((uint32_t)1U << 23U) ++#define GPSR1_CANFD0_RX ((uint32_t)1U << 22U) ++#define GPSR1_CANFD0_TX ((uint32_t)1U << 21U) ++#define GPSR1_AVB0_AVTP_CAPTURE ((uint32_t)1U << 20U) ++#define GPSR1_AVB0_AVTP_MATCH ((uint32_t)1U << 19U) ++#define GPSR1_AVB0_LINK ((uint32_t)1U << 18U) ++#define GPSR1_AVB0_PHY_INT ((uint32_t)1U << 17U) ++#define GPSR1_AVB0_MAGIC ((uint32_t)1U << 16U) ++#define GPSR1_AVB0_MDC ((uint32_t)1U << 15U) ++#define GPSR1_AVB0_MDIO ((uint32_t)1U << 14U) ++#define GPSR1_AVB0_TXCREFCLK ((uint32_t)1U << 13U) ++#define GPSR1_AVB0_TD3 ((uint32_t)1U << 12U) ++#define GPSR1_AVB0_TD2 ((uint32_t)1U << 11U) ++#define GPSR1_AVB0_TD1 ((uint32_t)1U << 10U) ++#define GPSR1_AVB0_TD0 ((uint32_t)1U << 9U) ++#define GPSR1_AVB0_TXC ((uint32_t)1U << 8U) ++#define GPSR1_AVB0_TX_CTL ((uint32_t)1U << 7U) ++#define GPSR1_AVB0_RD3 ((uint32_t)1U << 6U) ++#define GPSR1_AVB0_RD2 ((uint32_t)1U << 5U) ++#define GPSR1_AVB0_RD1 ((uint32_t)1U << 4U) ++#define GPSR1_AVB0_RD0 ((uint32_t)1U << 3U) ++#define GPSR1_AVB0_RXC ((uint32_t)1U << 2U) ++#define GPSR1_AVB0_RX_CTL ((uint32_t)1U << 1U) ++#define GPSR1_IRQ0 ((uint32_t)1U << 0U) ++ ++#define GPSR2_VI0_FIELD ((uint32_t)1U << 16U) ++#define GPSR2_VI0_DATA11 ((uint32_t)1U << 15U) ++#define GPSR2_VI0_DATA10 ((uint32_t)1U << 14U) ++#define GPSR2_VI0_DATA9 ((uint32_t)1U << 13U) ++#define GPSR2_VI0_DATA8 ((uint32_t)1U << 12U) ++#define GPSR2_VI0_DATA7 ((uint32_t)1U << 11U) ++#define GPSR2_VI0_DATA6 ((uint32_t)1U << 10U) ++#define GPSR2_VI0_DATA5 ((uint32_t)1U << 9U) ++#define GPSR2_VI0_DATA4 ((uint32_t)1U << 8U) ++#define GPSR2_VI0_DATA3 ((uint32_t)1U << 7U) ++#define GPSR2_VI0_DATA2 ((uint32_t)1U << 6U) ++#define GPSR2_VI0_DATA1 ((uint32_t)1U << 5U) ++#define GPSR2_VI0_DATA0 ((uint32_t)1U << 4U) ++#define GPSR2_VI0_VSYNC_N ((uint32_t)1U << 3U) ++#define GPSR2_VI0_HSYNC_N ((uint32_t)1U << 2U) ++#define GPSR2_VI0_CLKENB ((uint32_t)1U << 1U) ++#define GPSR2_VI0_CLK ((uint32_t)1U << 0U) ++ ++#define GPSR3_VI1_FIELD ((uint32_t)1U << 16U) ++#define GPSR3_VI1_DATA11 ((uint32_t)1U << 15U) ++#define GPSR3_VI1_DATA10 ((uint32_t)1U << 14U) ++#define GPSR3_VI1_DATA9 ((uint32_t)1U << 13U) ++#define GPSR3_VI1_DATA8 ((uint32_t)1U << 12U) ++#define GPSR3_VI1_DATA7 ((uint32_t)1U << 11U) ++#define GPSR3_VI1_DATA6 ((uint32_t)1U << 10U) ++#define GPSR3_VI1_DATA5 ((uint32_t)1U << 9U) ++#define GPSR3_VI1_DATA4 ((uint32_t)1U << 8U) ++#define GPSR3_VI1_DATA3 ((uint32_t)1U << 7U) ++#define GPSR3_VI1_DATA2 ((uint32_t)1U << 6U) ++#define GPSR3_VI1_DATA1 ((uint32_t)1U << 5U) ++#define GPSR3_VI1_DATA0 ((uint32_t)1U << 4U) ++#define GPSR3_VI1_VSYNC_N ((uint32_t)1U << 3U) ++#define GPSR3_VI1_HSYNC_N ((uint32_t)1U << 2U) ++#define GPSR3_VI1_CLKENB ((uint32_t)1U << 1U) ++#define GPSR3_VI1_CLK ((uint32_t)1U << 0U) ++ ++#define GPSR4_SDA2 ((uint32_t)1U << 5U) ++#define GPSR4_SCL2 ((uint32_t)1U << 4U) ++#define GPSR4_SDA1 ((uint32_t)1U << 3U) ++#define GPSR4_SCL1 ((uint32_t)1U << 2U) ++#define GPSR4_SDA0 ((uint32_t)1U << 1U) ++#define GPSR4_SCL0 ((uint32_t)1U << 0U) ++ ++#define GPSR5_RPC_INT_N ((uint32_t)1U << 14U) ++#define GPSR5_RPC_WP_N ((uint32_t)1U << 13U) ++#define GPSR5_RPC_RESET_N ((uint32_t)1U << 12U) ++#define GPSR5_QSPI1_SSL ((uint32_t)1U << 11U) ++#define GPSR5_QSPI1_IO3 ((uint32_t)1U << 10U) ++#define GPSR5_QSPI1_IO2 ((uint32_t)1U << 9U) ++#define GPSR5_QSPI1_MISO_IO1 ((uint32_t)1U << 8U) ++#define GPSR5_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U) ++#define GPSR5_QSPI1_SPCLK ((uint32_t)1U << 6U) ++#define GPSR5_QSPI0_SSL ((uint32_t)1U << 5U) ++#define GPSR5_QSPI0_IO3 ((uint32_t)1U << 4U) ++#define GPSR5_QSPI0_IO2 ((uint32_t)1U << 3U) ++#define GPSR5_QSPI0_MISO_IO1 ((uint32_t)1U << 2U) ++#define GPSR5_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U) ++#define GPSR5_QSPI0_SPCLK ((uint32_t)1U << 0U) ++ ++#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) ++#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) ++#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) ++#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) ++#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) ++#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) ++#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) ++#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) ++ ++#define IOCTRL30_POC_VI0_DATA5 ((uint32_t)1U << 31U) ++#define IOCTRL30_POC_VI0_DATA4 ((uint32_t)1U << 30U) ++#define IOCTRL30_POC_VI0_DATA3 ((uint32_t)1U << 29U) ++#define IOCTRL30_POC_VI0_DATA2 ((uint32_t)1U << 28U) ++#define IOCTRL30_POC_VI0_DATA1 ((uint32_t)1U << 27U) ++#define IOCTRL30_POC_VI0_DATA0 ((uint32_t)1U << 26U) ++#define IOCTRL30_POC_VI0_VSYNC_N ((uint32_t)1U << 25U) ++#define IOCTRL30_POC_VI0_HSYNC_N ((uint32_t)1U << 24U) ++#define IOCTRL30_POC_VI0_CLKENB ((uint32_t)1U << 23U) ++#define IOCTRL30_POC_VI0_CLK ((uint32_t)1U << 22U) ++#define IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) ++#define IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) ++#define IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) ++#define IOCTRL30_POC_DU_DOTCLKOUT ((uint32_t)1U << 18U) ++#define IOCTRL30_POC_DU_DB7 ((uint32_t)1U << 17U) ++#define IOCTRL30_POC_DU_DB6 ((uint32_t)1U << 16U) ++#define IOCTRL30_POC_DU_DB5 ((uint32_t)1U << 15U) ++#define IOCTRL30_POC_DU_DB4 ((uint32_t)1U << 14U) ++#define IOCTRL30_POC_DU_DB3 ((uint32_t)1U << 13U) ++#define IOCTRL30_POC_DU_DB2 ((uint32_t)1U << 12U) ++#define IOCTRL30_POC_DU_DG7 ((uint32_t)1U << 11U) ++#define IOCTRL30_POC_DU_DG6 ((uint32_t)1U << 10U) ++#define IOCTRL30_POC_DU_DG5 ((uint32_t)1U << 9U) ++#define IOCTRL30_POC_DU_DG4 ((uint32_t)1U << 8U) ++#define IOCTRL30_POC_DU_DG3 ((uint32_t)1U << 7U) ++#define IOCTRL30_POC_DU_DG2 ((uint32_t)1U << 6U) ++#define IOCTRL30_POC_DU_DR7 ((uint32_t)1U << 5U) ++#define IOCTRL30_POC_DU_DR6 ((uint32_t)1U << 4U) ++#define IOCTRL30_POC_DU_DR5 ((uint32_t)1U << 3U) ++#define IOCTRL30_POC_DU_DR4 ((uint32_t)1U << 2U) ++#define IOCTRL30_POC_DU_DR3 ((uint32_t)1U << 1U) ++#define IOCTRL30_POC_DU_DR2 ((uint32_t)1U << 0U) ++ ++#define IOCTRL31_POC_DUMMY_31 ((uint32_t)1U << 31U) ++#define IOCTRL31_POC_DUMMY_30 ((uint32_t)1U << 30U) ++#define IOCTRL31_POC_DUMMY_29 ((uint32_t)1U << 29U) ++#define IOCTRL31_POC_DUMMY_28 ((uint32_t)1U << 28U) ++#define IOCTRL31_POC_DUMMY_27 ((uint32_t)1U << 27U) ++#define IOCTRL31_POC_DUMMY_26 ((uint32_t)1U << 26U) ++#define IOCTRL31_POC_DUMMY_25 ((uint32_t)1U << 25U) ++#define IOCTRL31_POC_DUMMY_24 ((uint32_t)1U << 24U) ++#define IOCTRL31_POC_VI1_FIELD ((uint32_t)1U << 23U) ++#define IOCTRL31_POC_VI1_DATA11 ((uint32_t)1U << 22U) ++#define IOCTRL31_POC_VI1_DATA10 ((uint32_t)1U << 21U) ++#define IOCTRL31_POC_VI1_DATA9 ((uint32_t)1U << 20U) ++#define IOCTRL31_POC_VI1_DATA8 ((uint32_t)1U << 19U) ++#define IOCTRL31_POC_VI1_DATA7 ((uint32_t)1U << 18U) ++#define IOCTRL31_POC_VI1_DATA6 ((uint32_t)1U << 17U) ++#define IOCTRL31_POC_VI1_DATA5 ((uint32_t)1U << 16U) ++#define IOCTRL31_POC_VI1_DATA4 ((uint32_t)1U << 15U) ++#define IOCTRL31_POC_VI1_DATA3 ((uint32_t)1U << 14U) ++#define IOCTRL31_POC_VI1_DATA2 ((uint32_t)1U << 13U) ++#define IOCTRL31_POC_VI1_DATA1 ((uint32_t)1U << 12U) ++#define IOCTRL31_POC_VI1_DATA0 ((uint32_t)1U << 11U) ++#define IOCTRL31_POC_VI1_VSYNC_N ((uint32_t)1U << 10U) ++#define IOCTRL31_POC_VI1_HSYNC_N ((uint32_t)1U << 9U) ++#define IOCTRL31_POC_VI1_CLKENB ((uint32_t)1U << 8U) ++#define IOCTRL31_POC_VI1_CLK ((uint32_t)1U << 7U) ++#define IOCTRL31_POC_VI0_FIELD ((uint32_t)1U << 6U) ++#define IOCTRL31_POC_VI0_DATA11 ((uint32_t)1U << 5U) ++#define IOCTRL31_POC_VI0_DATA10 ((uint32_t)1U << 4U) ++#define IOCTRL31_POC_VI0_DATA9 ((uint32_t)1U << 3U) ++#define IOCTRL31_POC_VI0_DATA8 ((uint32_t)1U << 2U) ++#define IOCTRL31_POC_VI0_DATA7 ((uint32_t)1U << 1U) ++#define IOCTRL31_POC_VI0_DATA6 ((uint32_t)1U << 0U) ++#define IOCTRL32_POC2_VREF ((uint32_t)1U << 0U) ++#define IOCTRL40_SD0TDSEL1 ((uint32_t)1U << 1U) ++#define IOCTRL40_SD0TDSEL0 ((uint32_t)1U << 0U) ++ ++#define PUEN0_PUEN_VI0_CLK ((uint32_t)1U << 31U) ++#define PUEN0_PUEN_TDI ((uint32_t)1U << 30U) ++#define PUEN0_PUEN_TMS ((uint32_t)1U << 29U) ++#define PUEN0_PUEN_TCK ((uint32_t)1U << 28U) ++#define PUEN0_PUEN_TRST_N ((uint32_t)1U << 27U) ++#define PUEN0_PUEN_IRQ0 ((uint32_t)1U << 26U) ++#define PUEN0_PUEN_FSCLKST_N ((uint32_t)1U << 25U) ++#define PUEN0_PUEN_EXTALR ((uint32_t)1U << 24U) ++#define PUEN0_PUEN_PRESETOUT_N ((uint32_t)1U << 23U) ++#define PUEN0_PUEN_DU_DOTCLKIN ((uint32_t)1U << 22U) ++#define PUEN0_PUEN_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) ++#define PUEN0_PUEN_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) ++#define PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) ++#define PUEN0_PUEN_DU_DOTCLKOUT ((uint32_t)1U << 18U) ++#define PUEN0_PUEN_DU_DB7 ((uint32_t)1U << 17U) ++#define PUEN0_PUEN_DU_DB6 ((uint32_t)1U << 16U) ++#define PUEN0_PUEN_DU_DB5 ((uint32_t)1U << 15U) ++#define PUEN0_PUEN_DU_DB4 ((uint32_t)1U << 14U) ++#define PUEN0_PUEN_DU_DB3 ((uint32_t)1U << 13U) ++#define PUEN0_PUEN_DU_DB2 ((uint32_t)1U << 12U) ++#define PUEN0_PUEN_DU_DG7 ((uint32_t)1U << 11U) ++#define PUEN0_PUEN_DU_DG6 ((uint32_t)1U << 10U) ++#define PUEN0_PUEN_DU_DG5 ((uint32_t)1U << 9U) ++#define PUEN0_PUEN_DU_DG4 ((uint32_t)1U << 8U) ++#define PUEN0_PUEN_DU_DG3 ((uint32_t)1U << 7U) ++#define PUEN0_PUEN_DU_DG2 ((uint32_t)1U << 6U) ++#define PUEN0_PUEN_DU_DR7 ((uint32_t)1U << 5U) ++#define PUEN0_PUEN_DU_DR6 ((uint32_t)1U << 4U) ++#define PUEN0_PUEN_DU_DR5 ((uint32_t)1U << 3U) ++#define PUEN0_PUEN_DU_DR4 ((uint32_t)1U << 2U) ++#define PUEN0_PUEN_DU_DR3 ((uint32_t)1U << 1U) ++#define PUEN0_PUEN_DU_DR2 ((uint32_t)1U << 0U) ++ ++#define PUEN1_PUEN_VI1_DATA11 ((uint32_t)1U << 31U) ++#define PUEN1_PUEN_VI1_DATA10 ((uint32_t)1U << 30U) ++#define PUEN1_PUEN_VI1_DATA9 ((uint32_t)1U << 29U) ++#define PUEN1_PUEN_VI1_DATA8 ((uint32_t)1U << 28U) ++#define PUEN1_PUEN_VI1_DATA7 ((uint32_t)1U << 27U) ++#define PUEN1_PUEN_VI1_DATA6 ((uint32_t)1U << 26U) ++#define PUEN1_PUEN_VI1_DATA5 ((uint32_t)1U << 25U) ++#define PUEN1_PUEN_VI1_DATA4 ((uint32_t)1U << 24U) ++#define PUEN1_PUEN_VI1_DATA3 ((uint32_t)1U << 23U) ++#define PUEN1_PUEN_VI1_DATA2 ((uint32_t)1U << 22U) ++#define PUEN1_PUEN_VI1_DATA1 ((uint32_t)1U << 21U) ++#define PUEN1_PUEN_VI1_DATA0 ((uint32_t)1U << 20U) ++#define PUEN1_PUEN_VI1_VSYNC_N ((uint32_t)1U << 19U) ++#define PUEN1_PUEN_VI1_HSYNC_N ((uint32_t)1U << 18U) ++#define PUEN1_PUEN_VI1_CLKENB ((uint32_t)1U << 17U) ++#define PUEN1_PUEN_VI1_CLK ((uint32_t)1U << 16U) ++#define PUEN1_PUEN_VI0_FIELD ((uint32_t)1U << 15U) ++#define PUEN1_PUEN_VI0_DATA11 ((uint32_t)1U << 14U) ++#define PUEN1_PUEN_VI0_DATA10 ((uint32_t)1U << 13U) ++#define PUEN1_PUEN_VI0_DATA9 ((uint32_t)1U << 12U) ++#define PUEN1_PUEN_VI0_DATA8 ((uint32_t)1U << 11U) ++#define PUEN1_PUEN_VI0_DATA7 ((uint32_t)1U << 10U) ++#define PUEN1_PUEN_VI0_DATA6 ((uint32_t)1U << 9U) ++#define PUEN1_PUEN_VI0_DATA5 ((uint32_t)1U << 8U) ++#define PUEN1_PUEN_VI0_DATA4 ((uint32_t)1U << 7U) ++#define PUEN1_PUEN_VI0_DATA3 ((uint32_t)1U << 6U) ++#define PUEN1_PUEN_VI0_DATA2 ((uint32_t)1U << 5U) ++#define PUEN1_PUEN_VI0_DATA1 ((uint32_t)1U << 4U) ++#define PUEN1_PUEN_VI0_DATA0 ((uint32_t)1U << 3U) ++#define PUEN1_PUEN_VI0_VSYNC_N ((uint32_t)1U << 2U) ++#define PUEN1_PUEN_VI0_HSYNC_N ((uint32_t)1U << 1U) ++#define PUEN1_PUEN_VI0_CLKENB ((uint32_t)1U << 0U) ++ ++#define PUEN2_PUEN_CANFD_CLK ((uint32_t)1U << 31U) ++#define PUEN2_PUEN_CANFD1_RX ((uint32_t)1U << 30U) ++#define PUEN2_PUEN_CANFD1_TX ((uint32_t)1U << 29U) ++#define PUEN2_PUEN_CANFD0_RX ((uint32_t)1U << 28U) ++#define PUEN2_PUEN_CANFD0_TX ((uint32_t)1U << 27U) ++#define PUEN2_PUEN_AVB0_AVTP_CAPTURE ((uint32_t)1U << 26U) ++#define PUEN2_PUEN_AVB0_AVTP_MATCH ((uint32_t)1U << 25U) ++#define PUEN2_PUEN_AVB0_LINK ((uint32_t)1U << 24U) ++#define PUEN2_PUEN_AVB0_PHY_INT ((uint32_t)1U << 23U) ++#define PUEN2_PUEN_AVB0_MAGIC ((uint32_t)1U << 22U) ++#define PUEN2_PUEN_AVB0_MDC ((uint32_t)1U << 21U) ++#define PUEN2_PUEN_AVB0_MDIO ((uint32_t)1U << 20U) ++#define PUEN2_PUEN_AVB0_TXCREFCLK ((uint32_t)1U << 19U) ++#define PUEN2_PUEN_AVB0_TD3 ((uint32_t)1U << 18U) ++#define PUEN2_PUEN_AVB0_TD2 ((uint32_t)1U << 17U) ++#define PUEN2_PUEN_AVB0_TD1 ((uint32_t)1U << 16U) ++#define PUEN2_PUEN_AVB0_TD0 ((uint32_t)1U << 15U) ++#define PUEN2_PUEN_AVB0_TXC ((uint32_t)1U << 14U) ++#define PUEN2_PUEN_AVB0_TX_CTL ((uint32_t)1U << 13U) ++#define PUEN2_PUEN_AVB0_RD3 ((uint32_t)1U << 12U) ++#define PUEN2_PUEN_AVB0_RD2 ((uint32_t)1U << 11U) ++#define PUEN2_PUEN_AVB0_RD1 ((uint32_t)1U << 10U) ++#define PUEN2_PUEN_AVB0_RD0 ((uint32_t)1U << 9U) ++#define PUEN2_PUEN_AVB0_RXC ((uint32_t)1U << 8U) ++#define PUEN2_PUEN_AVB0_RX_CTL ((uint32_t)1U << 7U) ++#define PUEN2_PUEN_SDA2 ((uint32_t)1U << 6U) ++#define PUEN2_PUEN_SCL2 ((uint32_t)1U << 5U) ++#define PUEN2_PUEN_SDA1 ((uint32_t)1U << 4U) ++#define PUEN2_PUEN_SCL1 ((uint32_t)1U << 3U) ++#define PUEN2_PUEN_SDA0 ((uint32_t)1U << 2U) ++#define PUEN2_PUEN_SCL0 ((uint32_t)1U << 1U) ++#define PUEN2_PUEN_VI1_FIELD ((uint32_t)1U << 0U) ++ ++#define PUEN3_PUEN_DIGRF_CLKOUT ((uint32_t)1U << 16U) ++#define PUEN3_PUEN_DIGRF_CLKIN ((uint32_t)1U << 15U) ++#define PUEN3_PUEN_RPC_INT_N ((uint32_t)1U << 14U) ++#define PUEN3_PUEN_RPC_WP_N ((uint32_t)1U << 13U) ++#define PUEN3_PUEN_RPC_RESET_N ((uint32_t)1U << 12U) ++#define PUEN3_PUEN_QSPI1_SSL ((uint32_t)1U << 11U) ++#define PUEN3_PUEN_QSPI1_IO3 ((uint32_t)1U << 10U) ++#define PUEN3_PUEN_QSPI1_IO2 ((uint32_t)1U << 9U) ++#define PUEN3_PUEN_QSPI1_MISO_IO1 ((uint32_t)1U << 8U) ++#define PUEN3_PUEN_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U) ++#define PUEN3_PUEN_QSPI1_SPCLK ((uint32_t)1U << 6U) ++#define PUEN3_PUEN_QSPI0_SSL ((uint32_t)1U << 5U) ++#define PUEN3_PUEN_QSPI0_IO3 ((uint32_t)1U << 4U) ++#define PUEN3_PUEN_QSPI0_IO2 ((uint32_t)1U << 3U) ++#define PUEN3_PUEN_QSPI0_MISO_IO1 ((uint32_t)1U << 2U) ++#define PUEN3_PUEN_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U) ++#define PUEN3_PUEN_QSPI0_SPCLK ((uint32_t)1U << 0U) ++ ++#define PUD0_PUD_VI0_CLK ((uint32_t)1U << 31U) ++#define PUD0_PUD_IRQ0 ((uint32_t)1U << 26U) ++#define PUD0_PUD_FSCLKST_N ((uint32_t)1U << 25U) ++#define PUD0_PUD_PRESETOUT_N ((uint32_t)1U << 23U) ++#define PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) ++#define PUD0_PUD_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) ++#define PUD0_PUD_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) ++#define PUD0_PUD_DU_DOTCLKOUT ((uint32_t)1U << 18U) ++#define PUD0_PUD_DU_DB7 ((uint32_t)1U << 17U) ++#define PUD0_PUD_DU_DB6 ((uint32_t)1U << 16U) ++#define PUD0_PUD_DU_DB5 ((uint32_t)1U << 15U) ++#define PUD0_PUD_DU_DB4 ((uint32_t)1U << 14U) ++#define PUD0_PUD_DU_DB3 ((uint32_t)1U << 13U) ++#define PUD0_PUD_DU_DB2 ((uint32_t)1U << 12U) ++#define PUD0_PUD_DU_DG7 ((uint32_t)1U << 11U) ++#define PUD0_PUD_DU_DG6 ((uint32_t)1U << 10U) ++#define PUD0_PUD_DU_DG5 ((uint32_t)1U << 9U) ++#define PUD0_PUD_DU_DG4 ((uint32_t)1U << 8U) ++#define PUD0_PUD_DU_DG3 ((uint32_t)1U << 7U) ++#define PUD0_PUD_DU_DG2 ((uint32_t)1U << 6U) ++#define PUD0_PUD_DU_DR7 ((uint32_t)1U << 5U) ++#define PUD0_PUD_DU_DR6 ((uint32_t)1U << 4U) ++#define PUD0_PUD_DU_DR5 ((uint32_t)1U << 3U) ++#define PUD0_PUD_DU_DR4 ((uint32_t)1U << 2U) ++#define PUD0_PUD_DU_DR3 ((uint32_t)1U << 1U) ++#define PUD0_PUD_DU_DR2 ((uint32_t)1U << 0U) ++ ++#define PUD1_PUD_VI1_DATA11 ((uint32_t)1U << 31U) ++#define PUD1_PUD_VI1_DATA10 ((uint32_t)1U << 30U) ++#define PUD1_PUD_VI1_DATA9 ((uint32_t)1U << 29U) ++#define PUD1_PUD_VI1_DATA8 ((uint32_t)1U << 28U) ++#define PUD1_PUD_VI1_DATA7 ((uint32_t)1U << 27U) ++#define PUD1_PUD_VI1_DATA6 ((uint32_t)1U << 26U) ++#define PUD1_PUD_VI1_DATA5 ((uint32_t)1U << 25U) ++#define PUD1_PUD_VI1_DATA4 ((uint32_t)1U << 24U) ++#define PUD1_PUD_VI1_DATA3 ((uint32_t)1U << 23U) ++#define PUD1_PUD_VI1_DATA2 ((uint32_t)1U << 22U) ++#define PUD1_PUD_VI1_DATA1 ((uint32_t)1U << 21U) ++#define PUD1_PUD_VI1_DATA0 ((uint32_t)1U << 20U) ++#define PUD1_PUD_VI1_VSYNC_N ((uint32_t)1U << 19U) ++#define PUD1_PUD_VI1_HSYNC_N ((uint32_t)1U << 18U) ++#define PUD1_PUD_VI1_CLKENB ((uint32_t)1U << 17U) ++#define PUD1_PUD_VI1_CLK ((uint32_t)1U << 16U) ++#define PUD1_PUD_VI0_FIELD ((uint32_t)1U << 15U) ++#define PUD1_PUD_VI0_DATA11 ((uint32_t)1U << 14U) ++#define PUD1_PUD_VI0_DATA10 ((uint32_t)1U << 13U) ++#define PUD1_PUD_VI0_DATA9 ((uint32_t)1U << 12U) ++#define PUD1_PUD_VI0_DATA8 ((uint32_t)1U << 11U) ++#define PUD1_PUD_VI0_DATA7 ((uint32_t)1U << 10U) ++#define PUD1_PUD_VI0_DATA6 ((uint32_t)1U << 9U) ++#define PUD1_PUD_VI0_DATA5 ((uint32_t)1U << 8U) ++#define PUD1_PUD_VI0_DATA4 ((uint32_t)1U << 7U) ++#define PUD1_PUD_VI0_DATA3 ((uint32_t)1U << 6U) ++#define PUD1_PUD_VI0_DATA2 ((uint32_t)1U << 5U) ++#define PUD1_PUD_VI0_DATA1 ((uint32_t)1U << 4U) ++#define PUD1_PUD_VI0_DATA0 ((uint32_t)1U << 3U) ++#define PUD1_PUD_VI0_VSYNC_N ((uint32_t)1U << 2U) ++#define PUD1_PUD_VI0_HSYNC_N ((uint32_t)1U << 1U) ++#define PUD1_PUD_VI0_CLKENB ((uint32_t)1U << 0U) ++ ++#define PUD2_PUD_CANFD_CLK ((uint32_t)1U << 31U) ++#define PUD2_PUD_CANFD1_RX ((uint32_t)1U << 30U) ++#define PUD2_PUD_CANFD1_TX ((uint32_t)1U << 29U) ++#define PUD2_PUD_CANFD0_RX ((uint32_t)1U << 28U) ++#define PUD2_PUD_CANFD0_TX ((uint32_t)1U << 27U) ++#define PUD2_PUD_AVB0_AVTP_CAPTURE ((uint32_t)1U << 26U) ++#define PUD2_PUD_AVB0_AVTP_MATCH ((uint32_t)1U << 25U) ++#define PUD2_PUD_AVB0_LINK ((uint32_t)1U << 24U) ++#define PUD2_PUD_AVB0_PHY_INT ((uint32_t)1U << 23U) ++#define PUD2_PUD_AVB0_MAGIC ((uint32_t)1U << 22U) ++#define PUD2_PUD_AVB0_MDC ((uint32_t)1U << 21U) ++#define PUD2_PUD_AVB0_MDIO ((uint32_t)1U << 20U) ++#define PUD2_PUD_AVB0_TXCREFCLK ((uint32_t)1U << 19U) ++#define PUD2_PUD_AVB0_TD3 ((uint32_t)1U << 18U) ++#define PUD2_PUD_AVB0_TD2 ((uint32_t)1U << 17U) ++#define PUD2_PUD_AVB0_TD1 ((uint32_t)1U << 16U) ++#define PUD2_PUD_AVB0_TD0 ((uint32_t)1U << 15U) ++#define PUD2_PUD_AVB0_TXC ((uint32_t)1U << 14U) ++#define PUD2_PUD_AVB0_TX_CTL ((uint32_t)1U << 13U) ++#define PUD2_PUD_AVB0_RD3 ((uint32_t)1U << 12U) ++#define PUD2_PUD_AVB0_RD2 ((uint32_t)1U << 11U) ++#define PUD2_PUD_AVB0_RD1 ((uint32_t)1U << 10U) ++#define PUD2_PUD_AVB0_RD0 ((uint32_t)1U << 9U) ++#define PUD2_PUD_AVB0_RXC ((uint32_t)1U << 8U) ++#define PUD2_PUD_AVB0_RX_CTL ((uint32_t)1U << 7U) ++#define PUD2_PUD_SDA2 ((uint32_t)1U << 6U) ++#define PUD2_PUD_SCL2 ((uint32_t)1U << 5U) ++#define PUD2_PUD_SDA1 ((uint32_t)1U << 4U) ++#define PUD2_PUD_SCL1 ((uint32_t)1U << 3U) ++#define PUD2_PUD_SDA0 ((uint32_t)1U << 2U) ++#define PUD2_PUD_SCL0 ((uint32_t)1U << 1U) ++#define PUD2_PUD_VI1_FIELD ((uint32_t)1U << 0U) ++ ++#define PUD3_PUD_DIGRF_CLKOUT ((uint32_t)1U << 16U) ++#define PUD3_PUD_DIGRF_CLKIN ((uint32_t)1U << 15U) ++#define PUD3_PUD_RPC_INT_N ((uint32_t)1U << 14U) ++#define PUD3_PUD_RPC_WP_N ((uint32_t)1U << 13U) ++#define PUD3_PUD_RPC_RESET_N ((uint32_t)1U << 12U) ++#define PUD3_PUD_QSPI1_SSL ((uint32_t)1U << 11U) ++#define PUD3_PUD_QSPI1_IO3 ((uint32_t)1U << 10U) ++#define PUD3_PUD_QSPI1_IO2 ((uint32_t)1U << 9U) ++#define PUD3_PUD_QSPI1_MISO_IO1 ((uint32_t)1U << 8U) ++#define PUD3_PUD_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U) ++#define PUD3_PUD_QSPI1_SPCLK ((uint32_t)1U << 6U) ++#define PUD3_PUD_QSPI0_SSL ((uint32_t)1U << 5U) ++#define PUD3_PUD_QSPI0_IO3 ((uint32_t)1U << 4U) ++#define PUD3_PUD_QSPI0_IO2 ((uint32_t)1U << 3U) ++#define PUD3_PUD_QSPI0_MISO_IO1 ((uint32_t)1U << 2U) ++#define PUD3_PUD_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U) ++#define PUD3_PUD_QSPI0_SPCLK ((uint32_t)1U << 0U) ++ ++#define MOD_SEL0_sel_hscif0 ((uint32_t)1U << 10U) ++#define MOD_SEL0_sel_scif1 ((uint32_t)1U << 9U) ++#define MOD_SEL0_sel_canfd0 ((uint32_t)1U << 8U) ++#define MOD_SEL0_sel_pwm4 ((uint32_t)1U << 7U) ++#define MOD_SEL0_sel_pwm3 ((uint32_t)1U << 6U) ++#define MOD_SEL0_sel_pwm2 ((uint32_t)1U << 5U) ++#define MOD_SEL0_sel_pwm1 ((uint32_t)1U << 4U) ++#define MOD_SEL0_sel_pwm0 ((uint32_t)1U << 3U) ++#define MOD_SEL0_sel_rfso ((uint32_t)1U << 2U) ++#define MOD_SEL0_sel_rsp ((uint32_t)1U << 1U) ++#define MOD_SEL0_sel_tmu ((uint32_t)1U << 0U) ++ ++/* SCIF3 Registers for Dummy write */ ++#define SCIF3_BASE (0xE6C50000U) ++#define SCIF3_SCFCR (SCIF3_BASE + 0x0018U) ++#define SCIF3_SCFDR (SCIF3_BASE + 0x001CU) ++#define SCFCR_DATA (0x0000U) ++ ++/* Realtime module stop control */ ++#define CPG_BASE (0xE6150000U) ++#define CPG_MSTPSR0 (CPG_BASE + 0x0030U) ++#define CPG_RMSTPCR0 (CPG_BASE + 0x0110U) ++#define RMSTPCR0_RTDMAC (0x00200000U) ++ ++/* RT-DMAC Registers */ ++#define RTDMAC_CH (0U) /* choose 0 to 15 */ ++ ++#define RTDMAC_BASE (0xFFC10000U) ++#define RTDMAC_RDMOR (RTDMAC_BASE + 0x0060U) ++#define RTDMAC_RDMCHCLR (RTDMAC_BASE + 0x0080U) ++#define RTDMAC_RDMSAR(x) (RTDMAC_BASE + 0x8000U + (0x80U * (x))) ++#define RTDMAC_RDMDAR(x) (RTDMAC_BASE + 0x8004U + (0x80U * (x))) ++#define RTDMAC_RDMTCR(x) (RTDMAC_BASE + 0x8008U + (0x80U * (x))) ++#define RTDMAC_RDMCHCR(x) (RTDMAC_BASE + 0x800CU + (0x80U * (x))) ++#define RTDMAC_RDMCHCRB(x) (RTDMAC_BASE + 0x801CU + (0x80U * (x))) ++#define RTDMAC_RDMDPBASE(x) (RTDMAC_BASE + 0x8050U + (0x80U * (x))) ++#define RTDMAC_DESC_BASE (RTDMAC_BASE + 0xA000U) ++#define RTDMAC_DESC_RDMSAR (RTDMAC_DESC_BASE + 0x0000U) ++#define RTDMAC_DESC_RDMDAR (RTDMAC_DESC_BASE + 0x0004U) ++#define RTDMAC_DESC_RDMTCR (RTDMAC_DESC_BASE + 0x0008U) ++ ++#define RDMOR_DME (0x0001U) /* DMA Master Enable */ ++#define RDMCHCR_DPM_INFINITE (0x30000000U) /* Infinite repeat mode */ ++#define RDMCHCR_RPT_TCR (0x02000000U) /* enable to update TCR */ ++#define RDMCHCR_TS_2 (0x00000008U) /* Word(2byte) units transfer */ ++#define RDMCHCR_RS_AUTO (0x00000400U) /* Auto request */ ++#define RDMCHCR_DE (0x00000001U) /* DMA Enable */ ++#define RDMCHCRB_DRST (0x00008000U) /* Descriptor reset */ ++#define RDMCHCRB_SLM_256 (0x00000080U) /* once in 256 clock cycle */ ++#define RDMDPBASE_SEL_EXT (0x00000001U) /* External memory use */ ++ ++static void pfc_reg_write(uint32_t addr, uint32_t data); ++static void StartRtDma0_Descriptor(void); ++ ++static void pfc_reg_write(uint32_t addr, uint32_t data) ++{ ++ mmio_write_32(PFC_PMMR, ~data); ++ mmio_write_32((uintptr_t)addr, data); ++} ++ ++static void StartRtDma0_Descriptor(void) ++{ ++ uint32_t reg; ++ ++ /* Module stop clear */ ++ while((mmio_read_32(CPG_MSTPSR0) & RMSTPCR0_RTDMAC) != 0U) { ++ reg = mmio_read_32(CPG_RMSTPCR0); ++ reg &= ~RMSTPCR0_RTDMAC; ++ cpg_write(CPG_RMSTPCR0, reg); ++ } ++ ++ /* Initialize ch0, Reset Descriptor */ ++ mmio_write_32(RTDMAC_RDMCHCLR, ((uint32_t)1U << RTDMAC_CH)); ++ mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_DRST); ++ ++ /* Enable DMA */ ++ mmio_write_16(RTDMAC_RDMOR, RDMOR_DME); ++ ++ /* Set first transfer */ ++ mmio_write_32(RTDMAC_RDMSAR(RTDMAC_CH), RCAR_PRR); ++ mmio_write_32(RTDMAC_RDMDAR(RTDMAC_CH), SCIF3_SCFDR); ++ mmio_write_32(RTDMAC_RDMTCR(RTDMAC_CH), 0x00000001U); ++ ++ /* Set descriptor */ ++ mmio_write_32(RTDMAC_DESC_RDMSAR, 0x00000000U); ++ mmio_write_32(RTDMAC_DESC_RDMDAR, 0x00000000U); ++ mmio_write_32(RTDMAC_DESC_RDMTCR, 0x00200000U); ++ mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_SLM_256); ++ mmio_write_32(RTDMAC_RDMDPBASE(RTDMAC_CH), RTDMAC_DESC_BASE ++ | RDMDPBASE_SEL_EXT); ++ ++ /* Set transfer parameter, Start transfer */ ++ mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE ++ | RDMCHCR_RPT_TCR ++ | RDMCHCR_TS_2 ++ | RDMCHCR_RS_AUTO ++ | RDMCHCR_DE); ++} ++ ++void pfc_init_v3m(void) ++{ ++ /* Work around for PFC eratta */ ++ StartRtDma0_Descriptor(); ++ ++ // pin function ++ // md[4:1]!=0000 ++ /* initialize GPIO/perihperal function select */ ++ ++ pfc_reg_write(PFC_GPSR0, 0x00000000); ++ ++ pfc_reg_write(PFC_GPSR1, GPSR1_CANFD_CLK); ++ ++ pfc_reg_write(PFC_GPSR2, 0x00000000); ++ ++ pfc_reg_write(PFC_GPSR3, 0x00000000); ++ ++ pfc_reg_write(PFC_GPSR4, GPSR4_SDA2 ++ | GPSR4_SCL2); ++ ++ pfc_reg_write(PFC_GPSR5, GPSR5_QSPI1_SSL ++ | GPSR5_QSPI1_IO3 ++ | GPSR5_QSPI1_IO2 ++ | GPSR5_QSPI1_MISO_IO1 ++ | GPSR5_QSPI1_MOSI_IO0 ++ | GPSR5_QSPI1_SPCLK ++ | GPSR5_QSPI0_SSL ++ | GPSR5_QSPI0_IO3 ++ | GPSR5_QSPI0_IO2 ++ | GPSR5_QSPI0_MISO_IO1 ++ | GPSR5_QSPI0_MOSI_IO0 ++ | GPSR5_QSPI0_SPCLK); ++ ++ ++ /* initialize peripheral function select */ ++ pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) ++ | IPSR_24_FUNC(0) ++ | IPSR_20_FUNC(0) ++ | IPSR_16_FUNC(0) ++ | IPSR_12_FUNC(0) ++ | IPSR_8_FUNC(0) ++ | IPSR_4_FUNC(0) ++ | IPSR_0_FUNC(0)); ++ ++ pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0) ++ | IPSR_24_FUNC(0) ++ | IPSR_20_FUNC(0) ++ | IPSR_16_FUNC(0) ++ | IPSR_12_FUNC(0) ++ | IPSR_8_FUNC(0) ++ | IPSR_4_FUNC(0) ++ | IPSR_0_FUNC(0)); ++ ++ pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0) ++ | IPSR_24_FUNC(0) ++ | IPSR_20_FUNC(0) ++ | IPSR_16_FUNC(0) ++ | IPSR_12_FUNC(0) ++ | IPSR_8_FUNC(0) ++ | IPSR_4_FUNC(0) ++ | IPSR_0_FUNC(0)); ++ ++ pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(0) ++ | IPSR_24_FUNC(0) ++ | IPSR_20_FUNC(0) ++ | IPSR_16_FUNC(0) ++ | IPSR_12_FUNC(0) ++ | IPSR_8_FUNC(0) ++ | IPSR_4_FUNC(0) ++ | IPSR_0_FUNC(0)); ++ ++ pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0) ++ | IPSR_24_FUNC(0) ++ | IPSR_20_FUNC(0) ++ | IPSR_16_FUNC(0) ++ | IPSR_12_FUNC(0) ++ | IPSR_8_FUNC(0) ++ | IPSR_4_FUNC(0) ++ | IPSR_0_FUNC(0)); ++ ++ pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0) ++ | IPSR_24_FUNC(0) ++ | IPSR_20_FUNC(0) ++ | IPSR_16_FUNC(0) ++ | IPSR_12_FUNC(0) ++ | IPSR_8_FUNC(0) ++ | IPSR_4_FUNC(0) ++ | IPSR_0_FUNC(0)); ++ ++ pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(0) ++ | IPSR_24_FUNC(0) ++ | IPSR_20_FUNC(0) ++ | IPSR_16_FUNC(0) ++ | IPSR_12_FUNC(0) ++ | IPSR_8_FUNC(0) ++ | IPSR_4_FUNC(0) ++ | IPSR_0_FUNC(0)); ++ ++ pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) ++ | IPSR_24_FUNC(4) ++ | IPSR_20_FUNC(4) ++ | IPSR_16_FUNC(4) ++ | IPSR_12_FUNC(4) ++ | IPSR_8_FUNC(0) ++ | IPSR_4_FUNC(0) ++ | IPSR_0_FUNC(0)); ++ ++ pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0) ++ | IPSR_24_FUNC(0) ++ | IPSR_20_FUNC(0) ++ | IPSR_16_FUNC(4) ++ | IPSR_12_FUNC(0) ++ | IPSR_8_FUNC(0) ++ | IPSR_4_FUNC(0) ++ | IPSR_0_FUNC(0)); ++ ++ /* initialize POC Control */ ++ ++ pfc_reg_write(PFC_IOCTRL30, IOCTRL30_POC_VI0_DATA5 ++ | IOCTRL30_POC_VI0_DATA4 ++ | IOCTRL30_POC_VI0_DATA3 ++ | IOCTRL30_POC_VI0_DATA2 ++ | IOCTRL30_POC_VI0_DATA1 ++ | IOCTRL30_POC_VI0_DATA0 ++ | IOCTRL30_POC_VI0_VSYNC_N ++ | IOCTRL30_POC_VI0_HSYNC_N ++ | IOCTRL30_POC_VI0_CLKENB ++ | IOCTRL30_POC_VI0_CLK ++ | IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE ++ | IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC ++ | IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC ++ | IOCTRL30_POC_DU_DOTCLKOUT ++ | IOCTRL30_POC_DU_DB7 ++ | IOCTRL30_POC_DU_DB6 ++ | IOCTRL30_POC_DU_DB5 ++ | IOCTRL30_POC_DU_DB4 ++ | IOCTRL30_POC_DU_DB3 ++ | IOCTRL30_POC_DU_DB2 ++ | IOCTRL30_POC_DU_DG7 ++ | IOCTRL30_POC_DU_DG6 ++ | IOCTRL30_POC_DU_DG5 ++ | IOCTRL30_POC_DU_DG4 ++ | IOCTRL30_POC_DU_DG3 ++ | IOCTRL30_POC_DU_DG2 ++ | IOCTRL30_POC_DU_DR7 ++ | IOCTRL30_POC_DU_DR6 ++ | IOCTRL30_POC_DU_DR5 ++ | IOCTRL30_POC_DU_DR4 ++ | IOCTRL30_POC_DU_DR3 ++ | IOCTRL30_POC_DU_DR2); ++ ++ pfc_reg_write(PFC_IOCTRL31, IOCTRL31_POC_DUMMY_31 ++ | IOCTRL31_POC_DUMMY_30 ++ | IOCTRL31_POC_DUMMY_29 ++ | IOCTRL31_POC_DUMMY_28 ++ | IOCTRL31_POC_DUMMY_27 ++ | IOCTRL31_POC_DUMMY_26 ++ | IOCTRL31_POC_DUMMY_25 ++ | IOCTRL31_POC_DUMMY_24 ++ | IOCTRL31_POC_VI1_FIELD ++ | IOCTRL31_POC_VI1_DATA11 ++ | IOCTRL31_POC_VI1_DATA10 ++ | IOCTRL31_POC_VI1_DATA9 ++ | IOCTRL31_POC_VI1_DATA8 ++ | IOCTRL31_POC_VI1_DATA7 ++ | IOCTRL31_POC_VI1_DATA6 ++ | IOCTRL31_POC_VI1_DATA5 ++ | IOCTRL31_POC_VI1_DATA4 ++ | IOCTRL31_POC_VI1_DATA3 ++ | IOCTRL31_POC_VI1_DATA2 ++ | IOCTRL31_POC_VI1_DATA1 ++ | IOCTRL31_POC_VI1_DATA0 ++ | IOCTRL31_POC_VI1_VSYNC_N ++ | IOCTRL31_POC_VI1_HSYNC_N ++ | IOCTRL31_POC_VI1_CLKENB ++ | IOCTRL31_POC_VI1_CLK ++ | IOCTRL31_POC_VI0_FIELD ++ | IOCTRL31_POC_VI0_DATA11 ++ | IOCTRL31_POC_VI0_DATA10 ++ | IOCTRL31_POC_VI0_DATA9 ++ | IOCTRL31_POC_VI0_DATA8 ++ | IOCTRL31_POC_VI0_DATA7 ++ | IOCTRL31_POC_VI0_DATA6); ++ ++ pfc_reg_write(PFC_IOCTRL32,0x00000000); ++ ++ pfc_reg_write(PFC_IOCTRL40,0x00000000); ++ ++ /* initialize Pull enable */ ++ pfc_reg_write(PFC_PUEN0,PUEN0_PUEN_VI0_CLK ++ | PUEN0_PUEN_TDI ++ | PUEN0_PUEN_TMS ++ | PUEN0_PUEN_TCK ++ | PUEN0_PUEN_TRST_N ++ | PUEN0_PUEN_IRQ0 ++ | PUEN0_PUEN_FSCLKST_N ++ | PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC ++ | PUEN0_PUEN_DU_DOTCLKOUT ++ | PUEN0_PUEN_DU_DB7 ++ | PUEN0_PUEN_DU_DB6 ++ | PUEN0_PUEN_DU_DB5 ++ | PUEN0_PUEN_DU_DB4 ++ | PUEN0_PUEN_DU_DB3 ++ | PUEN0_PUEN_DU_DB2 ++ | PUEN0_PUEN_DU_DG7 ++ | PUEN0_PUEN_DU_DG6 ++ | PUEN0_PUEN_DU_DG5 ++ | PUEN0_PUEN_DU_DG4 ++ | PUEN0_PUEN_DU_DG3 ++ | PUEN0_PUEN_DU_DG2 ++ | PUEN0_PUEN_DU_DR7 ++ | PUEN0_PUEN_DU_DR6 ++ | PUEN0_PUEN_DU_DR5 ++ | PUEN0_PUEN_DU_DR4 ++ | PUEN0_PUEN_DU_DR3 ++ | PUEN0_PUEN_DU_DR2); ++ ++ pfc_reg_write(PFC_PUEN1,PUEN1_PUEN_VI1_DATA11 ++ | PUEN1_PUEN_VI1_DATA10 ++ | PUEN1_PUEN_VI1_DATA9 ++ | PUEN1_PUEN_VI1_DATA8 ++ | PUEN1_PUEN_VI1_DATA7 ++ | PUEN1_PUEN_VI1_DATA6 ++ | PUEN1_PUEN_VI1_DATA5 ++ | PUEN1_PUEN_VI1_DATA4 ++ | PUEN1_PUEN_VI1_DATA3 ++ | PUEN1_PUEN_VI1_DATA2 ++ | PUEN1_PUEN_VI1_DATA1 ++ | PUEN1_PUEN_VI1_DATA0 ++ | PUEN1_PUEN_VI1_VSYNC_N ++ | PUEN1_PUEN_VI1_HSYNC_N ++ | PUEN1_PUEN_VI1_CLKENB ++ | PUEN1_PUEN_VI1_CLK ++ | PUEN1_PUEN_VI0_DATA11 ++ | PUEN1_PUEN_VI0_DATA10 ++ | PUEN1_PUEN_VI0_DATA9 ++ | PUEN1_PUEN_VI0_DATA8 ++ | PUEN1_PUEN_VI0_DATA7 ++ | PUEN1_PUEN_VI0_DATA6 ++ | PUEN1_PUEN_VI0_DATA5 ++ | PUEN1_PUEN_VI0_DATA4 ++ | PUEN1_PUEN_VI0_DATA3 ++ | PUEN1_PUEN_VI0_DATA2 ++ | PUEN1_PUEN_VI0_DATA1); ++ ++ pfc_reg_write(PFC_PUEN2,PUEN2_PUEN_CANFD_CLK ++ | PUEN2_PUEN_CANFD1_RX ++ | PUEN2_PUEN_CANFD1_TX ++ | PUEN2_PUEN_CANFD0_RX ++ | PUEN2_PUEN_CANFD0_TX ++ | PUEN2_PUEN_AVB0_AVTP_CAPTURE ++ | PUEN2_PUEN_AVB0_AVTP_MATCH ++ | PUEN2_PUEN_AVB0_LINK ++ | PUEN2_PUEN_AVB0_PHY_INT ++ | PUEN2_PUEN_AVB0_MAGIC ++ | PUEN2_PUEN_AVB0_TXCREFCLK ++ | PUEN2_PUEN_AVB0_TD3 ++ | PUEN2_PUEN_AVB0_TD2 ++ | PUEN2_PUEN_AVB0_TD1 ++ | PUEN2_PUEN_AVB0_TD0 ++ | PUEN2_PUEN_AVB0_TXC ++ | PUEN2_PUEN_AVB0_TX_CTL ++ | PUEN2_PUEN_AVB0_RD3 ++ | PUEN2_PUEN_AVB0_RD2 ++ | PUEN2_PUEN_AVB0_RD1 ++ | PUEN2_PUEN_AVB0_RD0 ++ | PUEN2_PUEN_AVB0_RXC ++ | PUEN2_PUEN_AVB0_RX_CTL ++ | PUEN2_PUEN_VI1_FIELD); ++ ++ pfc_reg_write(PFC_PUEN3,PUEN3_PUEN_DIGRF_CLKOUT ++ | PUEN3_PUEN_DIGRF_CLKIN); ++ ++ /* initialize PUD Control */ ++ pfc_reg_write(PFC_PUD0,PUD0_PUD_VI0_CLK ++ | PUD0_PUD_IRQ0 ++ | PUD0_PUD_FSCLKST_N ++ | PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE ++ | PUD0_PUD_DU_EXVSYNC_DU_VSYNC ++ | PUD0_PUD_DU_EXHSYNC_DU_HSYNC ++ | PUD0_PUD_DU_DOTCLKOUT ++ | PUD0_PUD_DU_DB7 ++ | PUD0_PUD_DU_DB6 ++ | PUD0_PUD_DU_DB5 ++ | PUD0_PUD_DU_DB4 ++ | PUD0_PUD_DU_DB3 ++ | PUD0_PUD_DU_DB2 ++ | PUD0_PUD_DU_DG7 ++ | PUD0_PUD_DU_DG6 ++ | PUD0_PUD_DU_DG5 ++ | PUD0_PUD_DU_DG4 ++ | PUD0_PUD_DU_DG3 ++ | PUD0_PUD_DU_DG2 ++ | PUD0_PUD_DU_DR7 ++ | PUD0_PUD_DU_DR6 ++ | PUD0_PUD_DU_DR5 ++ | PUD0_PUD_DU_DR4 ++ | PUD0_PUD_DU_DR3 ++ | PUD0_PUD_DU_DR2); ++ ++ pfc_reg_write(PFC_PUD1,PUD1_PUD_VI1_DATA11 ++ | PUD1_PUD_VI1_DATA10 ++ | PUD1_PUD_VI1_DATA9 ++ | PUD1_PUD_VI1_DATA8 ++ | PUD1_PUD_VI1_DATA7 ++ | PUD1_PUD_VI1_DATA6 ++ | PUD1_PUD_VI1_DATA5 ++ | PUD1_PUD_VI1_DATA4 ++ | PUD1_PUD_VI1_DATA3 ++ | PUD1_PUD_VI1_DATA2 ++ | PUD1_PUD_VI1_DATA1 ++ | PUD1_PUD_VI1_DATA0 ++ | PUD1_PUD_VI1_VSYNC_N ++ | PUD1_PUD_VI1_HSYNC_N ++ | PUD1_PUD_VI1_CLKENB ++ | PUD1_PUD_VI1_CLK ++ | PUD1_PUD_VI0_DATA11 ++ | PUD1_PUD_VI0_DATA10 ++ | PUD1_PUD_VI0_DATA9 ++ | PUD1_PUD_VI0_DATA8 ++ | PUD1_PUD_VI0_DATA7 ++ | PUD1_PUD_VI0_DATA6 ++ | PUD1_PUD_VI0_DATA5 ++ | PUD1_PUD_VI0_DATA4 ++ | PUD1_PUD_VI0_DATA3 ++ | PUD1_PUD_VI0_DATA2 ++ | PUD1_PUD_VI0_DATA1 ++ | PUD1_PUD_VI0_DATA0 ++ | PUD1_PUD_VI0_VSYNC_N ++ | PUD1_PUD_VI0_HSYNC_N ++ | PUD1_PUD_VI0_CLKENB); ++ ++ pfc_reg_write(PFC_PUD2,PUD2_PUD_CANFD_CLK ++ | PUD2_PUD_CANFD1_RX ++ | PUD2_PUD_CANFD1_TX ++ | PUD2_PUD_CANFD0_RX ++ | PUD2_PUD_CANFD0_TX ++ | PUD2_PUD_AVB0_AVTP_CAPTURE ++ | PUD2_PUD_VI1_FIELD); ++ ++ pfc_reg_write(PFC_PUD3,PUD3_PUD_DIGRF_CLKOUT ++ | PUD3_PUD_DIGRF_CLKIN); ++ ++ /* initialize Module Select */ ++ pfc_reg_write(PFC_MOD_SEL0,0x00000000); ++ ++ // gpio ++ /* initialize positive/negative logic select */ ++ mmio_write_32(GPIO_POSNEG0, 0x00000000U); ++ mmio_write_32(GPIO_POSNEG1, 0x00000000U); ++ mmio_write_32(GPIO_POSNEG2, 0x00000000U); ++ mmio_write_32(GPIO_POSNEG3, 0x00000000U); ++ mmio_write_32(GPIO_POSNEG4, 0x00000000U); ++ mmio_write_32(GPIO_POSNEG5, 0x00000000U); ++ ++ /* initialize general IO/interrupt switching */ ++ mmio_write_32(GPIO_IOINTSEL0, 0x00000000U); ++ mmio_write_32(GPIO_IOINTSEL1, 0x00000000U); ++ mmio_write_32(GPIO_IOINTSEL2, 0x00000000U); ++ mmio_write_32(GPIO_IOINTSEL3, 0x00000000U); ++ mmio_write_32(GPIO_IOINTSEL4, 0x00000000U); ++ mmio_write_32(GPIO_IOINTSEL5, 0x00000000U); ++ ++ /* initialize general output register */ ++ mmio_write_32(GPIO_OUTDT0, 0x00000000U); ++ mmio_write_32(GPIO_OUTDT1, 0x00000000U); ++ mmio_write_32(GPIO_OUTDT2, 0x00000000U); ++ mmio_write_32(GPIO_OUTDT3, 0x00000000U); ++ mmio_write_32(GPIO_OUTDT4, 0x00000000U); ++ mmio_write_32(GPIO_OUTDT5, 0x00000000U); ++ ++ /* initialize general input/output switching */ ++ mmio_write_32(GPIO_INOUTSEL0, 0x00000000U); ++ mmio_write_32(GPIO_INOUTSEL1, 0x00000000U); ++ mmio_write_32(GPIO_INOUTSEL2, 0x00000000U); ++ mmio_write_32(GPIO_INOUTSEL3, 0x00000000U); ++ mmio_write_32(GPIO_INOUTSEL4, 0x00000000U); ++ mmio_write_32(GPIO_INOUTSEL5, 0x00000000U); ++} +diff --git a/plat/renesas/rcar/pfc/V3M/pfc_init_v3m.h b/plat/renesas/rcar/pfc/V3M/pfc_init_v3m.h +new file mode 100644 +index 0000000..bfc0253 +--- /dev/null ++++ b/plat/renesas/rcar/pfc/V3M/pfc_init_v3m.h +@@ -0,0 +1,37 @@ ++/* ++ * Copyright (c) 2015-2017, Renesas Electronics Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * - Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * - Neither the name of Renesas nor the names of its contributors may be ++ * used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef PFC_INIT_V3M_H__ ++#define PFC_INIT_V3M_H__ ++ ++void pfc_init_v3m(void); ++ ++#endif /* PFC_INIT_V3M_H__ */ +diff --git a/plat/renesas/rcar/pfc/pfc.mk b/plat/renesas/rcar/pfc/pfc.mk +index 9668522..0ccbe3c 100644 +--- a/plat/renesas/rcar/pfc/pfc.mk ++++ b/plat/renesas/rcar/pfc/pfc.mk +@@ -34,6 +34,7 @@ ifeq (${RCAR_LSI},${RCAR_AUTO}) + BL2_SOURCES += plat/renesas/rcar/pfc/H3/pfc_init_h3_v2.c + BL2_SOURCES += plat/renesas/rcar/pfc/M3/pfc_init_m3.c + BL2_SOURCES += plat/renesas/rcar/pfc/M3N/pfc_init_m3n.c ++ BL2_SOURCES += plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c + + else ifdef RCAR_LSI_CUT_COMPAT + ifeq (${RCAR_LSI},${RCAR_H3}) +@@ -46,6 +47,9 @@ else ifdef RCAR_LSI_CUT_COMPAT + ifeq (${RCAR_LSI},${RCAR_M3N}) + BL2_SOURCES += plat/renesas/rcar/pfc/M3N/pfc_init_m3n.c + endif ++ ifeq (${RCAR_LSI},${RCAR_V3M}) ++ BL2_SOURCES += plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c ++ endif + else + ifeq (${RCAR_LSI},${RCAR_H3}) + ifeq (${LSI_CUT},10) +@@ -64,6 +68,9 @@ else + ifeq (${RCAR_LSI},${RCAR_M3N}) + BL2_SOURCES += plat/renesas/rcar/pfc/M3N/pfc_init_m3n.c + endif ++ ifeq (${RCAR_LSI},${RCAR_V3M}) ++ BL2_SOURCES += plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c ++ endif + endif + + BL2_SOURCES += plat/renesas/rcar/pfc/pfc_init.c +diff --git a/plat/renesas/rcar/pfc/pfc_init.c b/plat/renesas/rcar/pfc/pfc_init.c +index 267ee9d..c270851 100644 +--- a/plat/renesas/rcar/pfc/pfc_init.c ++++ b/plat/renesas/rcar/pfc/pfc_init.c +@@ -39,6 +39,7 @@ + #include "H3/pfc_init_h3_v2.h" + #include "M3/pfc_init_m3.h" + #include "M3N/pfc_init_m3n.h" ++ #include "V3M/pfc_init_v3m.h" + #endif + #if RCAR_LSI == RCAR_H3 /* H3 */ + #include "H3/pfc_init_h3_v1.h" +@@ -50,6 +51,9 @@ + #if RCAR_LSI == RCAR_M3N /* M3N */ + #include "M3N/pfc_init_m3n.h" + #endif ++#if RCAR_LSI == RCAR_V3M /* V3M */ ++ #include "V3M/pfc_init_v3m.h" ++#endif + + /* Product Register */ + #define PRR (0xFFF00044U) +@@ -57,6 +61,7 @@ + #define PRR_CUT_MASK (0x000000FFU) + #define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */ + #define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ ++#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */ + #define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */ + #define PRR_PRODUCT_10 (0x00U) + #define PRR_PRODUCT_11 (0x01U) +@@ -103,6 +108,9 @@ void pfc_init(void) + case RCAR_PRODUCT_M3N: + pfc_init_m3n(); + break; ++ case RCAR_PRODUCT_V3M: ++ pfc_init_v3m(); ++ break; + default: + PRR_PRODUCT_ERR(reg); + break; +@@ -144,6 +152,13 @@ void pfc_init(void) + pfc_init_m3n(); + #endif + break; ++ case PRR_PRODUCT_V3M: ++#if RCAR_LSI != RCAR_V3M ++ PRR_PRODUCT_ERR(reg); ++#else ++ pfc_init_v3m(); ++#endif ++ break; + default: + PRR_PRODUCT_ERR(reg); + break; +@@ -185,6 +200,11 @@ void pfc_init(void) + PRR_PRODUCT_ERR(reg); + } + pfc_init_m3n(); ++ #elif RCAR_LSI == RCAR_V3M /* V3M */ ++ if ((PRR_PRODUCT_V3M) != (reg & PRR_PRODUCT_MASK)) { ++ PRR_PRODUCT_ERR(reg); ++ } ++ pfc_init_v3m(); + #else + #error "Don't have PFC initialize routine(unknown)." + #endif +diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk +index 01164d2..550d829 100644 +--- a/plat/renesas/rcar/platform.mk ++++ b/plat/renesas/rcar/platform.mk +@@ -112,10 +112,12 @@ endif + RCAR_H3:=0 + RCAR_M3:=1 + RCAR_M3N:=2 ++RCAR_V3M:=3 + RCAR_AUTO:=99 + $(eval $(call add_define,RCAR_H3)) + $(eval $(call add_define,RCAR_M3)) + $(eval $(call add_define,RCAR_M3N)) ++$(eval $(call add_define,RCAR_V3M)) + $(eval $(call add_define,RCAR_AUTO)) + RCAR_CUT_10:=0 + RCAR_CUT_11:=1 +@@ -177,6 +179,22 @@ else + endif + $(eval $(call add_define,RCAR_LSI_CUT)) + endif ++ else ifeq (${LSI},V3M) ++ RCAR_LSI:=${RCAR_V3M} ++ ifndef LSI_CUT ++ # enable compatible function. ++ RCAR_LSI_CUT_COMPAT := 1 ++ $(eval $(call add_define,RCAR_LSI_CUT_COMPAT)) ++ else ++ # disable compatible function. ++ ifeq (${LSI_CUT},10) ++ RCAR_LSI_CUT:=0 ++ endif ++ ifeq (${LSI_CUT},20) ++ RCAR_LSI_CUT:=10 ++ endif ++ $(eval $(call add_define,RCAR_LSI_CUT)) ++ endif + else + $(error "Error: ${LSI} is not supported.") + endif +diff --git a/plat/renesas/rcar/qos/V3M/qos_init_v3m.c b/plat/renesas/rcar/qos/V3M/qos_init_v3m.c +new file mode 100644 +index 0000000..9e6afa2 +--- /dev/null ++++ b/plat/renesas/rcar/qos/V3M/qos_init_v3m.c +@@ -0,0 +1,411 @@ ++/* ++ * Copyright (c) 2015-2017, Renesas Electronics Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * - Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * - Neither the name of Renesas nor the names of its contributors may be ++ * used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include <stdint.h> ++#include <debug.h> ++#include "qos_init_v3m.h" ++ ++#define RCAR_QOS_VERSION "rev.0.01" ++ ++#define RCAR_QOS_NONE (3U) ++#define RCAR_QOS_TYPE_DEFAULT (0U) ++ ++#define RCAR_DRAM_SPLIT_LINEAR (0U) ++#define RCAR_DRAM_SPLIT_4CH (1U) ++#define RCAR_DRAM_SPLIT_2CH (2U) ++ ++#define DBSC_BASE (0xE6790000U) ++#define DBSC_AXARB (DBSC_BASE + 0x0800U) ++ ++#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U) ++#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) ++#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) ++#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) ++#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU) ++#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) ++#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U) ++#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) ++#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) ++#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U) ++#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U) ++#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U) ++#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U) ++#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU) ++#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U) ++#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U) ++#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U) ++#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU) ++#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U) ++#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U) ++#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U) ++#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU) ++#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U) ++#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U) ++#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U) ++#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU) ++#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U) ++#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U) ++#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U) ++#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU) ++#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U) ++#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U) ++#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U) ++#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU) ++#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U) ++#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U) ++#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U) ++#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU) ++#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U) ++#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U) ++#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U) ++#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU) ++#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U) ++#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U) ++#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U) ++#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU) ++#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U) ++#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U) ++#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U) ++#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU) ++#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U) ++#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U) ++#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U) ++#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU) ++#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U) ++#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U) ++#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U) ++#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU) ++#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U) ++#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U) ++#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U) ++#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU) ++#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U) ++#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U) ++#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U) ++#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU) ++#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U) ++#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U) ++#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U) ++#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU) ++#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U) ++#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U) ++#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U) ++#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU) ++#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U) ++#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U) ++#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) ++ ++#define AXI_BASE (0xE6784000U) ++#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U) ++#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU) ++#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U) ++#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U) ++#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U) ++#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U) ++#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U) ++#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U) ++#define ADSPLCR0_SWP (0x0CU) ++ ++#define MSTAT_BASE (0xE67E0000U) ++#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U) ++#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U) ++#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U) ++#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U) ++#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U) ++#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U) ++#define MSTAT_STATQC (MSTAT_BASE + 0x8008U) ++ ++#define RALLOC_BASE (0xE67F0000U) ++#define RALLOC_RAS (RALLOC_BASE + 0x0000U) ++#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U) ++#define RALLOC_RAEN (RALLOC_BASE + 0x0018U) ++#define RALLOC_REGGD (RALLOC_BASE + 0x0020U) ++#define RALLOC_DANN (RALLOC_BASE + 0x0030U) ++#define RALLOC_DANT (RALLOC_BASE + 0x0038U) ++#define RALLOC_EC (RALLOC_BASE + 0x003CU) ++#define RALLOC_EMS (RALLOC_BASE + 0x0040U) ++#define RALLOC_INSFC (RALLOC_BASE + 0x0050U) ++#define RALLOC_BERR (RALLOC_BASE + 0x0054U) ++#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U) ++ ++#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) ++ ++ ++static inline void io_write_32(uintptr_t addr, uint32_t value) ++{ ++ *(volatile uint32_t*)addr = value; ++} ++ ++static inline void io_write_64(uintptr_t addr, uint64_t value) ++{ ++ *(volatile uint64_t*)addr = value; ++} ++ ++ ++typedef struct { ++ uintptr_t addr; ++ uint64_t value; ++} mstat_slot_t; ++ ++#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT ++static const mstat_slot_t mstat_fix[] = { ++ {0x0000U, 0x000000000000FFFFU}, ++ {0x0008U, 0x000000000000FFFFU}, ++ {0x0010U, 0x000000000000FFFFU}, ++ {0x0018U, 0x000000000000FFFFU}, ++ {0x0020U, 0x001414090000FFFFU}, ++ {0x0028U, 0x000C00000000FFFFU}, ++ {0x0030U, 0x001008040000FFFFU}, ++ {0x0038U, 0x001004040000FFFFU}, ++ {0x0040U, 0x001004040000FFFFU}, ++ {0x0048U, 0x000000000000FFFFU}, ++ {0x0050U, 0x001004040000FFFFU}, ++ {0x0058U, 0x001004040000FFFFU}, ++ {0x0060U, 0x000000000000FFFFU}, ++ {0x0068U, 0x001404040000FFFFU}, ++ {0x0070U, 0x001008030000FFFFU}, ++ {0x0078U, 0x001004030000FFFFU}, ++ {0x0080U, 0x001004030000FFFFU}, ++ {0x0088U, 0x000000000000FFFFU}, ++ {0x0090U, 0x001004040000FFFFU}, ++ {0x0098U, 0x001004040000FFFFU}, ++ {0x00A0U, 0x000000000000FFFFU}, ++ {0x00A8U, 0x000000000000FFFFU}, ++ {0x00B0U, 0x000000000000FFFFU}, ++ {0x00B8U, 0x000000000000FFFFU}, ++ {0x00C0U, 0x000000000000FFFFU}, ++ {0x00C8U, 0x000000000000FFFFU}, ++ {0x00D0U, 0x000000000000FFFFU}, ++ {0x00D8U, 0x000000000000FFFFU}, ++ {0x00E0U, 0x001404020000FFFFU}, ++ {0x00E8U, 0x000000000000FFFFU}, ++ {0x00F0U, 0x000000000000FFFFU}, ++ {0x00F8U, 0x000000000000FFFFU}, ++ {0x0100U, 0x000000000000FFFFU}, ++ {0x0108U, 0x000C04020000FFFFU}, ++ {0x0110U, 0x000000000000FFFFU}, ++ {0x0118U, 0x001404020000FFFFU}, ++ {0x0120U, 0x000000000000FFFFU}, ++ {0x0128U, 0x000000000000FFFFU}, ++ {0x0130U, 0x000000000000FFFFU}, ++ {0x0138U, 0x000000000000FFFFU}, ++ {0x0140U, 0x000000000000FFFFU}, ++ {0x0148U, 0x000000000000FFFFU}, ++}; ++ ++static const mstat_slot_t mstat_be[] = { ++ {0x0000U, 0x00100020447FFC01U}, ++ {0x0008U, 0x00100020447FFC01U}, ++ {0x0010U, 0x00100040447FFC01U}, ++ {0x0018U, 0x00100040447FFC01U}, ++ {0x0020U, 0x0000000000000000U}, ++ {0x0028U, 0x0000000000000000U}, ++ {0x0030U, 0x0000000000000000U}, ++ {0x0038U, 0x0000000000000000U}, ++ {0x0040U, 0x0000000000000000U}, ++ {0x0048U, 0x0000000000000000U}, ++ {0x0050U, 0x0000000000000000U}, ++ {0x0058U, 0x0000000000000000U}, ++ {0x0060U, 0x0000000000000000U}, ++ {0x0068U, 0x0000000000000000U}, ++ {0x0070U, 0x0000000000000000U}, ++ {0x0078U, 0x0000000000000000U}, ++ {0x0080U, 0x0000000000000000U}, ++ {0x0088U, 0x0000000000000000U}, ++ {0x0090U, 0x0000000000000000U}, ++ {0x0098U, 0x0000000000000000U}, ++ {0x00A0U, 0x00100010447FFC01U}, ++ {0x00A8U, 0x00100010447FFC01U}, ++ {0x00B0U, 0x00100010447FFC01U}, ++ {0x00B8U, 0x00100010447FFC01U}, ++ {0x00C0U, 0x00100010447FFC01U}, ++ {0x00C8U, 0x00100010447FFC01U}, ++ {0x00D0U, 0x0000000000000000U}, ++ {0x00D8U, 0x00100010447FFC01U}, ++ {0x00E0U, 0x0000000000000000U}, ++ {0x00E8U, 0x00100010447FFC01U}, ++ {0x00F0U, 0x00100010447FFC01U}, ++ {0x00F8U, 0x00100010447FFC01U}, ++ {0x0100U, 0x00100010447FFC01U}, ++ {0x0108U, 0x0000000000000000U}, ++ {0x0110U, 0x00100010447FFC01U}, ++ {0x0118U, 0x0000000000000000U}, ++ {0x0120U, 0x00100010447FFC01U}, ++ {0x0128U, 0x00100010447FFC01U}, ++ {0x0130U, 0x00100010447FFC01U}, ++ {0x0138U, 0x00100010447FFC01U}, ++ {0x0140U, 0x00100020447FFC01U}, ++ {0x0148U, 0x00100020447FFC01U}, ++}; ++#endif ++ ++static void dbsc_setting(void) ++{ ++ ++ /* BUFCAM settings */ ++ //DBSC_DBCAM0CNF0 not set ++ io_write_32(DBSC_DBCAM0CNF1, 0x00044218); //dbcam0cnf1 ++ io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2 ++ //io_write_32(DBSC_DBCAM0CNF3, 0x00000007); //dbcam0cnf3 ++ io_write_32(DBSC_DBSCHCNT0, 0x080F003F); //dbschcnt0 ++ io_write_32(DBSC_DBSCHCNT1, 0x00001010); //dbschcnt0 ++ ++ io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0 ++ io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0 ++ io_write_32(DBSC_DBSCHRW1, 0x00180034); //dbschrw1 ++ io_write_32(DBSC_SCFCTST0,0x180B1708); ++ io_write_32(DBSC_SCFCTST1,0x0808070C); ++ io_write_32(DBSC_SCFCTST2,0x012F1123); ++ ++ /* QoS Settings */ ++ io_write_32(DBSC_DBSCHQOS_0_0, 0x0000F000); ++ io_write_32(DBSC_DBSCHQOS_0_1, 0x0000E000); ++ io_write_32(DBSC_DBSCHQOS_0_2, 0x00007000); ++ io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000); ++ //DBSC_DBSCHQOS_1_0 not set ++ //DBSC_DBSCHQOS_1_1 not set ++ //DBSC_DBSCHQOS_1_2 not set ++ //DBSC_DBSCHQOS_1_3 not set ++ //DBSC_DBSCHQOS_2_0 not set ++ //DBSC_DBSCHQOS_2_1 not set ++ //DBSC_DBSCHQOS_2_2 not set ++ //DBSC_DBSCHQOS_2_3 not set ++ //DBSC_DBSCHQOS_3_0 not set ++ //DBSC_DBSCHQOS_3_1 not set ++ //DBSC_DBSCHQOS_3_2 not set ++ //DBSC_DBSCHQOS_3_3 not set ++ io_write_32(DBSC_DBSCHQOS_4_0, 0x0000F000); ++ io_write_32(DBSC_DBSCHQOS_4_1, 0x0000EFFF); ++ io_write_32(DBSC_DBSCHQOS_4_2, 0x0000B000); ++ io_write_32(DBSC_DBSCHQOS_4_3, 0x00000000); ++ //DBSC_DBSCHQOS_5_0 not set ++ //DBSC_DBSCHQOS_5_1 not set ++ //DBSC_DBSCHQOS_5_2 not set ++ //DBSC_DBSCHQOS_5_3 not set ++ //DBSC_DBSCHQOS_6_0 not set ++ //DBSC_DBSCHQOS_6_1 not set ++ //DBSC_DBSCHQOS_6_2 not set ++ //DBSC_DBSCHQOS_6_3 not set ++ //DBSC_DBSCHQOS_7_0 not set ++ //DBSC_DBSCHQOS_7_1 not set ++ //DBSC_DBSCHQOS_7_2 not set ++ //DBSC_DBSCHQOS_7_3 not set ++ //DBSC_DBSCHQOS_8_0 not set ++ //DBSC_DBSCHQOS_8_1 not set ++ //DBSC_DBSCHQOS_8_2 not set ++ //DBSC_DBSCHQOS_8_3 not set ++ io_write_32(DBSC_DBSCHQOS_9_0, 0x0000F000); ++ io_write_32(DBSC_DBSCHQOS_9_1, 0x0000EFFF); ++ io_write_32(DBSC_DBSCHQOS_9_2, 0x0000D000); ++ io_write_32(DBSC_DBSCHQOS_9_3, 0x00000000); ++ //DBSC_DBSCHQOS_10_0 not set ++ //DBSC_DBSCHQOS_10_1 not set ++ //DBSC_DBSCHQOS_10_2 not set ++ //DBSC_DBSCHQOS_10_3 not set ++ //DBSC_DBSCHQOS_11_0 not set ++ //DBSC_DBSCHQOS_11_1 not set ++ //DBSC_DBSCHQOS_11_2 not set ++ //DBSC_DBSCHQOS_11_3 not set ++ //DBSC_DBSCHQOS_12_0 not set ++ //DBSC_DBSCHQOS_12_1 not set ++ //DBSC_DBSCHQOS_12_2 not set ++ //DBSC_DBSCHQOS_12_3 not set ++ io_write_32(DBSC_DBSCHQOS_13_0, 0x0000F000); ++ io_write_32(DBSC_DBSCHQOS_13_1, 0x0000EFFF); ++ io_write_32(DBSC_DBSCHQOS_13_2, 0x0000E800); ++ io_write_32(DBSC_DBSCHQOS_13_3, 0x00007000); ++ io_write_32(DBSC_DBSCHQOS_14_0, 0x0000F000); ++ io_write_32(DBSC_DBSCHQOS_14_1, 0x0000EFFF); ++ io_write_32(DBSC_DBSCHQOS_14_2, 0x0000E800); ++ io_write_32(DBSC_DBSCHQOS_14_3, 0x0000B000); ++ io_write_32(DBSC_DBSCHQOS_15_0, 0x000007D0); ++ io_write_32(DBSC_DBSCHQOS_15_1, 0x000007CF); ++ io_write_32(DBSC_DBSCHQOS_15_2, 0x000005D0); ++ io_write_32(DBSC_DBSCHQOS_15_3, 0x000003D0); ++} ++ ++void qos_init_v3m(void) ++{ ++return; ++ ++ dbsc_setting(); ++ ++#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) ++#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT ++ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); ++#endif ++ ++ /* Resource Alloc setting */ ++ io_write_32(RALLOC_RAS, 0x00000020U); ++ io_write_32(RALLOC_FIXTH, 0x000F0005U); ++ io_write_32(RALLOC_REGGD, 0x00000004U); ++ io_write_64(RALLOC_DANN, 0x0202020104040200U); ++ io_write_32(RALLOC_DANT, 0x00201008U); ++ io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 ES1 */ ++ io_write_64(RALLOC_EMS, 0x0000000000000000U); ++ io_write_32(RALLOC_INSFC, 0x63C20001U); ++ io_write_32(RALLOC_BERR, 0x00000000U); ++ ++ /* MSTAT setting */ ++ io_write_32(MSTAT_SL_INIT, 0x0305007DU); ++ io_write_32(MSTAT_REF_ARS, 0x00330000U); ++ ++ /* MSTAT SRAM setting */ ++ { ++ uint32_t i; ++ ++ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { ++ io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr, ++ mstat_fix[i].value); ++ io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr, ++ mstat_fix[i].value); ++ } ++ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { ++ io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr, ++ mstat_be[i].value); ++ io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr, ++ mstat_be[i].value); ++ } ++ } ++ ++ /* AXI-IF arbitration setting */ ++ io_write_32(DBSC_AXARB, 0x18010000U); ++ ++ /* Resource Alloc start */ ++ io_write_32(RALLOC_RAEN, 0x00000001U); ++ ++ /* MSTAT start */ ++ io_write_32(MSTAT_STATQC, 0x00000001U); ++ ++#else ++ NOTICE("BL2: QoS is None\n"); ++#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ ++} +diff --git a/plat/renesas/rcar/qos/V3M/qos_init_v3m.h b/plat/renesas/rcar/qos/V3M/qos_init_v3m.h +new file mode 100644 +index 0000000..43a2d5b +--- /dev/null ++++ b/plat/renesas/rcar/qos/V3M/qos_init_v3m.h +@@ -0,0 +1,37 @@ ++/* ++ * Copyright (c) 2015-2017, Renesas Electronics Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * - Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * - Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * - Neither the name of Renesas nor the names of its contributors may be ++ * used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef QOS_INIT_H_V3M__ ++#define QOS_INIT_H_V3M__ ++ ++void qos_init_v3m(void); ++ ++#endif /* QOS_INIT_H_V3M__ */ +diff --git a/plat/renesas/rcar/qos/qos.mk b/plat/renesas/rcar/qos/qos.mk +index e29df09..161ab74 100644 +--- a/plat/renesas/rcar/qos/qos.mk ++++ b/plat/renesas/rcar/qos/qos.mk +@@ -36,6 +36,7 @@ ifeq (${RCAR_LSI},${RCAR_AUTO}) + BL2_SOURCES += plat/renesas/rcar/qos/M3/qos_init_m3_v10.c + BL2_SOURCES += plat/renesas/rcar/qos/M3/qos_init_m3_v11.c + BL2_SOURCES += plat/renesas/rcar/qos/M3N/qos_init_m3n_v10.c ++ BL2_SOURCES += plat/renesas/rcar/qos/V3M/qos_init_v3m.c + else ifdef RCAR_LSI_CUT_COMPAT + ifeq (${RCAR_LSI},${RCAR_H3}) + BL2_SOURCES += plat/renesas/rcar/qos/H3/qos_init_h3_v10.c +@@ -49,6 +50,9 @@ else ifdef RCAR_LSI_CUT_COMPAT + ifeq (${RCAR_LSI},${RCAR_M3N}) + BL2_SOURCES += plat/renesas/rcar/qos/M3N/qos_init_m3n_v10.c + endif ++ ifeq (${RCAR_LSI},${RCAR_V3M}) ++ BL2_SOURCES += plat/renesas/rcar/qos/V3M/qos_init_v3m.c ++ endif + else + ifeq (${RCAR_LSI},${RCAR_H3}) + ifeq (${LSI_CUT},10) +@@ -80,6 +84,9 @@ else + BL2_SOURCES += plat/renesas/rcar/qos/M3N/qos_init_m3n_v10.c + endif + endif ++ ifeq (${RCAR_LSI},${RCAR_V3M}) ++ BL2_SOURCES += plat/renesas/rcar/qos/V3M/qos_init_v3m.c ++ endif + endif + + BL2_SOURCES += plat/renesas/rcar/qos/qos_init.c +diff --git a/plat/renesas/rcar/qos/qos_init.c b/plat/renesas/rcar/qos/qos_init.c +index ca0f311..86ee492 100644 +--- a/plat/renesas/rcar/qos/qos_init.c ++++ b/plat/renesas/rcar/qos/qos_init.c +@@ -41,6 +41,7 @@ + #include "M3/qos_init_m3_v10.h" + #include "M3/qos_init_m3_v11.h" + #include "M3N/qos_init_m3n_v10.h" ++ #include "V3M/qos_init_v3m.h" + #endif + #if RCAR_LSI == RCAR_H3 /* H3 */ + #include "H3/qos_init_h3_v10.h" +@@ -54,6 +55,9 @@ + #if RCAR_LSI == RCAR_M3N /* M3N */ + #include "M3N/qos_init_m3n_v10.h" + #endif ++#if RCAR_LSI == RCAR_V3M /* V3M */ ++ #include "V3M/qos_init_v3m.h" ++#endif + + /* Product Register */ + #define PRR (0xFFF00044U) +@@ -61,6 +65,7 @@ + #define PRR_CUT_MASK (0x000000FFU) + #define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */ + #define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ ++#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */ + #define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */ + #define PRR_PRODUCT_10 (0x00U) + #define PRR_PRODUCT_11 (0x01U) +@@ -129,6 +134,19 @@ void qos_init(void) + PRR_PRODUCT_ERR(reg); + #endif + break; ++ case PRR_PRODUCT_V3M: ++ #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M) ++ switch (reg & PRR_CUT_MASK) { ++ case PRR_PRODUCT_10: ++ case PRR_PRODUCT_20: ++ default: ++ qos_init_v3m(); ++ break; ++ } ++ #else ++ PRR_PRODUCT_ERR(reg); ++ #endif ++ break; + default: + PRR_PRODUCT_ERR(reg); + break; +@@ -180,6 +198,13 @@ void qos_init(void) + PRR_PRODUCT_ERR(reg); + } + qos_init_m3n_v10(); ++ #elif RCAR_LSI == RCAR_V3M /* V3M */ ++ /* V3M Cut 10 or later */ ++ if ((PRR_PRODUCT_V3M) ++ != (reg & (PRR_PRODUCT_MASK))) { ++ PRR_PRODUCT_ERR(reg); ++ } ++ qos_init_v3m(); + #else + #error "Don't have QoS initialize routine(Unknown chip)." + #endif +diff --git a/plat/renesas/rcar/rcar_def.h b/plat/renesas/rcar/rcar_def.h +index 03e0f14..103f754 100644 +--- a/plat/renesas/rcar/rcar_def.h ++++ b/plat/renesas/rcar/rcar_def.h +@@ -255,6 +255,7 @@ + #define RCAR_CUT_MASK (0x000000FFU) + #define RCAR_PRODUCT_H3 (0x00004F00U) + #define RCAR_PRODUCT_M3 (0x00005200U) ++#define RCAR_PRODUCT_V3M (0x00005400U) + #define RCAR_PRODUCT_M3N (0x00005500U) + #define RCAR_CUT_ES10 (0x00000000U) + #define RCAR_CUT_ES11 (0x00000001U) +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch index 8545634..050d98f 100644 --- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch @@ -3510,19 +3510,7 @@ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-comm index 0a959f7..ec20aba 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h -@@ -93,7 +93,11 @@ - #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 } - - /* MEMORY */ -+#if defined(CONFIG_R8A7797) -+#define CONFIG_SYS_TEXT_BASE 0x58280000 -+#else - #define CONFIG_SYS_TEXT_BASE 0x50000000 -+#endif - #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7fff0) - - -@@ -124,6 +128,14 @@ +@@ -124,6 +128,17 @@ #define PHYS_SDRAM_1_SIZE ((unsigned long)(0x80000000 - DRAM_RSV_SIZE)) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE @@ -3530,8 +3518,11 @@ index 0a959f7..ec20aba 100644 +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE) /* legacy */ +#define PHYS_SDRAM_1_SIZE ((unsigned long)(0x40000000 - DRAM_RSV_SIZE)) -+#define PHYS_SDRAM_2 0x0600000000 /* ext */ -+#define PHYS_SDRAM_2_SIZE ((unsigned long)0x80000000) ++ #if defined(CONFIG_TARGET_V3MSK) ++ #define PHYS_SDRAM_1_SIZE ((unsigned long)(0x80000000 - DRAM_RSV_SIZE)) ++ #else ++ #define PHYS_SDRAM_1_SIZE ((unsigned long)(0x40000000 - DRAM_RSV_SIZE)) ++ #endif +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE #else diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch index 479f23f..ecbbfea 100644 --- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch @@ -8,8 +8,9 @@ This is only for H3ULCB.HAD Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> --- - include/configs/h3ulcb.h | 4 ++-- - 1 file changed, 1 insertions(+), 1 deletions(-) + include/configs/h3ulcb.h | 4 ++-- + board/renesas/ulcb/ulcb.c | 3 +++ + 2 file changed, 4 insertions(+), 1 deletions(-) diff --git a/include/configs/h3ulcb.h b/include/configs/h3ulcb.h index b9be845..3da2e5a 100644 @@ -23,6 +24,27 @@ index b9be845..3da2e5a 100644 +#define CONFIG_CONS_SCIF1 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ +diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c +index 0d8752f..1be01cf 100644 +--- a/board/renesas/ulcb/ulcb.c ++++ b/board/renesas/ulcb/ulcb.c +@@ -29,6 +29,7 @@ + + DECLARE_GLOBAL_DATA_PTR; + ++#define SCIF1_MSTP206 (1 << 6) + #define SCIF2_MSTP310 (1 << 10) + #define ETHERAVB_MSTP812 (1 << 12) + #define DVFS_MSTP926 (1 << 26) +@@ -49,6 +50,8 @@ int board_early_init_f(void) + + rcar_prr_init(); + ++ /* SCIF1 */ ++ mstp_clrbits_le32(SMSTPCR2, SMSTPCR2, SCIF1_MSTP206); + /* SCIF2 */ + mstp_clrbits_le32(SMSTPCR3, SMSTPCR3, SCIF2_MSTP310); + /* EHTERAVB */ -- 1.9.1 diff --git a/meta-rcar-gen3-adas/recipes-bsp/utest-apps/files/utest-cam-imr-drm.tar.gz b/meta-rcar-gen3-adas/recipes-bsp/utest-apps/files/utest-cam-imr-drm.tar.gz Binary files differindex 7502d90..a5319a4 100644 --- a/meta-rcar-gen3-adas/recipes-bsp/utest-apps/files/utest-cam-imr-drm.tar.gz +++ b/meta-rcar-gen3-adas/recipes-bsp/utest-apps/files/utest-cam-imr-drm.tar.gz diff --git a/meta-rcar-gen3-adas/recipes-core/images/core-image-weston.bbappend b/meta-rcar-gen3-adas/recipes-core/images/core-image-weston.bbappend index 945d9b0..85a94f0 100644 --- a/meta-rcar-gen3-adas/recipes-core/images/core-image-weston.bbappend +++ b/meta-rcar-gen3-adas/recipes-core/images/core-image-weston.bbappend @@ -1,6 +1,7 @@ IMAGE_INSTALL_append = " \ packagegroup-opencv-sdk \ packagegroup-surroundview \ + utest-cam-imr-drm \ " CONFLICT_DISTRO_FEATURES = "x11"
\ No newline at end of file diff --git a/meta-rcar-gen3-adas/recipes-kernel/kernel-module-uio-imp/files/uio_imp.c b/meta-rcar-gen3-adas/recipes-kernel/kernel-module-uio-imp/files/uio_imp.c index ca90d2c..ff06016 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/kernel-module-uio-imp/files/uio_imp.c +++ b/meta-rcar-gen3-adas/recipes-kernel/kernel-module-uio-imp/files/uio_imp.c @@ -77,14 +77,18 @@ #define DRIVER_NAME "uio_imp" #define DRIVER_VER "0.0" -#define LUIO_DEVICE_IMP 0 -#define LUIO_DEVICE_IMPSC 1 -#define LUIO_DEVICE_IMPDES 2 -#define LUIO_DEVICE_IMRLSX 3 -#define LUIO_DEVICE_IMRX 4 -#define LUIO_DEVICE_MEM 5 -#define LUIO_DEVICE_VSP 6 -#define LUIO_DEVICE_IMPDMAC 7 +enum { + LUIO_DEVICE_IMP, + LUIO_DEVICE_IMPSC, + LUIO_DEVICE_IMPDES, + LUIO_DEVICE_IMRLSX, + LUIO_DEVICE_IMRX, + LUIO_DEVICE_MEM, + LUIO_DEVICE_VSP, + LUIO_DEVICE_IMPDMAC, + LUIO_DEVICE_IMPPSC, + LUIO_DEVICE_IMPCNN, +}; #define IMP_INTERNAL_REG_SIZE 0x1000 #define IMP_NUM_DIST_HWIRQ 32 @@ -137,7 +141,8 @@ static irqreturn_t imp_handler(int irq, struct uio_info *dev_info) if (stat != 0) { /* mask all interrupts */ - WriteReg(dev_info, 0x14, ReadReg(dev_info, 0x14) & 0x0fffffff); + u32 mask = ReadReg(dev_info, 0x14); + WriteReg(dev_info, 0x14, mask & 0x0fffffff); return IRQ_HANDLED; } else { @@ -190,6 +195,68 @@ static void impsc_sreset(struct uio_info *info) WriteReg(info, 0x20, 0xffffffff); } +static irqreturn_t impdmac_handler(int irq, struct uio_info *dev_info) +{ + u32 stat = ReadReg(dev_info, 0x08); + + if (clear_int && (stat & 0x00000040)) { + /* clear INT state */ + WriteReg(dev_info, 0x0c, 0x00000040); + return IRQ_NONE; + } + + if (stat != 0) { + /* mask all interrupts */ + WriteReg(dev_info, 0x14, 0xffffffff); + + return IRQ_HANDLED; + } else { + return IRQ_NONE; + } +} + +static void impdmac_sreset(struct uio_info *info) +{ + /* software reset */ + WriteReg(info, 0x04, 0x80000000); + WriteReg(info, 0x04, 0x00000000); + ReadReg(info, 0x04); + + /* mask all interrupts */ + WriteReg(info, 0x14, 0xffffffff); +} + +static irqreturn_t impcnn_handler(int irq, struct uio_info *dev_info) +{ + u32 stat = ReadReg(dev_info, 0x10); + + if (clear_int && (stat & 0x00000004)) { + /* clear INT state */ + WriteReg(dev_info, 0x18, 0x00000004); + return IRQ_NONE; + } + + if (stat != 0) { + /* mask all interrupts */ + WriteReg(dev_info, 0x1c, 0xffffffff); + + return IRQ_HANDLED; + } else { + return IRQ_NONE; + } +} + +static void impcnn_sreset(struct uio_info *info) +{ + /* software reset */ + WriteReg(info, 0x08, 0x00000001); + WriteReg(info, 0x08, 0x00000000); + ReadReg(info, 0x08); + + /* mask all interrupts */ + WriteReg(info, 0x1c, 0xffffffff); +} + static irqreturn_t impdist_handler(int irq, struct uio_info *dev_info) { unsigned int bit; @@ -216,6 +283,32 @@ static irqreturn_t impdist_handler(int irq, struct uio_info *dev_info) return IRQ_HANDLED; } +static irqreturn_t impdist2_handler(int irq, struct uio_info *dev_info) +{ + unsigned int bit; + unsigned long stat; + struct uio_imp_platdata *priv = dev_info->priv; + + stat = ReadReg(dev_info, 0x100); /* sr */ + stat &= ~ReadReg(dev_info, 0x10c); /* imr */ + + if (stat & 0x20000000) + stat |= ReadReg(dev_info, 0x110); /* g0intsel */ + if (stat & 0x40000000) + stat |= ReadReg(dev_info, 0x114); /* g1intsel */ + if (stat & 0x80000000) + stat |= ReadReg(dev_info, 0x118); /* g2intsel */ + stat &= ~0xe0000000; + + if (!stat) + return IRQ_NONE; + + for_each_set_bit(bit, &stat, IMP_NUM_DIST_HWIRQ) + generic_handle_irq(priv->domain_irq[bit]); + + return IRQ_HANDLED; +} + static void impdist_irq_enable(struct irq_data *d) { struct uio_imp_platdata *priv = irq_data_get_irq_chip_data(d); @@ -257,37 +350,6 @@ static void impdist_sreset(struct uio_info *info) WriteReg(info, 0x500, 0); } -static irqreturn_t impdmac_handler(int irq, struct uio_info *dev_info) -{ - u32 stat = ReadReg(dev_info, 0x08); - - if (clear_int && (stat & 0x00000040)) { - /* clear INT state */ - WriteReg(dev_info, 0x0c, 0x00000040); - return IRQ_NONE; - } - - if (stat != 0) { - /* mask all interrupts */ - WriteReg(dev_info, 0x14, 0xffffffff); - - return IRQ_HANDLED; - } else { - return IRQ_NONE; - } -} - -static void impdmac_sreset(struct uio_info *info) -{ - /* software reset */ - WriteReg(info, 0x04, 0x80000000); - WriteReg(info, 0x04, 0x00000000); - ReadReg(info, 0x04); - - /* mask all interrupts */ - WriteReg(info, 0x14, 0xffffffff); -} - static const struct imp_dev_data imp_dev_data_legacy = { .dtype = LUIO_DEVICE_IMP, .handler = imp_handler, @@ -311,13 +373,30 @@ static const struct imp_dev_data imp_dev_data_dmac = { .handler = impdmac_handler, .sreset = impdmac_sreset, }; +static const struct imp_dev_data imp_dev_data_distributer2 = { + .dtype = LUIO_DEVICE_IMPDES, + .handler = impdist2_handler, +}; +static const struct imp_dev_data imp_dev_data_psc = { + .dtype = LUIO_DEVICE_IMPPSC, + .handler = impdmac_handler, /* same as dmac */ + .sreset = impdmac_sreset, /* same as dmac */ +}; +static const struct imp_dev_data imp_dev_data_cnn = { + .dtype = LUIO_DEVICE_IMPCNN, + .handler = impcnn_handler, + .sreset = impcnn_sreset, +}; static const struct of_device_id of_imp_match[] = { - { .compatible = "renesas,impx4-legacy", .data = &imp_dev_data_legacy }, - { .compatible = "renesas,impx4-shader", .data = &imp_dev_data_shader }, - { .compatible = "renesas,impx4-distributer", .data = &imp_dev_data_distributer }, - { .compatible = "renesas,impx4-memory", .data = &imp_dev_data_memory }, - { .compatible = "renesas,impx5-dmac", .data = &imp_dev_data_dmac }, + { .compatible = "renesas,impx4-legacy", .data = &imp_dev_data_legacy }, + { .compatible = "renesas,impx4-shader", .data = &imp_dev_data_shader }, + { .compatible = "renesas,impx4-distributer", .data = &imp_dev_data_distributer }, + { .compatible = "renesas,impx4-memory", .data = &imp_dev_data_memory }, + { .compatible = "renesas,impx5-dmac", .data = &imp_dev_data_dmac }, + { .compatible = "renesas,impx5+-distributer", .data = &imp_dev_data_distributer2 }, + { .compatible = "renesas,impx5+-psc", .data = &imp_dev_data_psc }, + { .compatible = "renesas,impx5+-cnn", .data = &imp_dev_data_cnn }, { /* Terminator */ }, }; MODULE_DEVICE_TABLE(of, of_imp_match); diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch index d6726a3..ffe7684 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch @@ -8,10 +8,10 @@ This adds Renesas R8A7797 SoC support Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> --- arch/arm64/Kconfig.platforms | 6 + - arch/arm64/boot/dts/renesas/r8a7797.dtsi | 1002 ++++++++++ + arch/arm64/boot/dts/renesas/r8a7797.dtsi | 1156 +++++++++++ drivers/clk/renesas/Kconfig | 1 + drivers/clk/renesas/Makefile | 1 + - drivers/clk/renesas/r8a7797-cpg-mssr.c | 222 +++ + drivers/clk/renesas/r8a7797-cpg-mssr.c | 231 +++ drivers/clk/renesas/rcar-gen3-cpg.c | 41 +- drivers/clk/renesas/rcar-gen3-cpg.h | 6 + drivers/clk/renesas/renesas-cpg-mssr.c | 6 + @@ -34,7 +34,7 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> drivers/pinctrl/sh-pfc/Kconfig | 5 + drivers/pinctrl/sh-pfc/Makefile | 1 + drivers/pinctrl/sh-pfc/core.c | 7 + - drivers/pinctrl/sh-pfc/pfc-r8a7797.c | 2586 +++++++++++++++++++++++++ + drivers/pinctrl/sh-pfc/pfc-r8a7797.c | 2628 +++++++++++++++++++++++++ drivers/pinctrl/sh-pfc/sh_pfc.h | 12 + drivers/soc/renesas/Makefile | 4 + drivers/soc/renesas/r8a7797-sysc.c | 39 + @@ -47,7 +47,7 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> drivers/thermal/rcar_gen3_thermal.c | 29 + include/dt-bindings/clock/r8a7797-cpg-mssr.h | 48 + include/dt-bindings/power/r8a7797-sysc.h | 32 + - 40 files changed, 4281 insertions(+), 29 deletions(-) + 40 files changed, 4486 insertions(+), 29 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/r8a7797.dtsi create mode 100644 drivers/clk/renesas/r8a7797-cpg-mssr.c create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7797.c @@ -74,10 +74,10 @@ index ebe0a37..d3b6771 100644 help diff --git a/arch/arm64/boot/dts/renesas/r8a7797.dtsi b/arch/arm64/boot/dts/renesas/r8a7797.dtsi new file mode 100644 -index 0000000..6eaa5ba +index 0000000..0dd374f --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797.dtsi -@@ -0,0 +1,1002 @@ +@@ -0,0 +1,1156 @@ +/* + * Device Tree Source for the r8a7797 SoC + * @@ -577,6 +577,158 @@ index 0000000..6eaa5ba + }; + }; + ++ cmt0: timer@ffca0000 { ++ compatible = "renesas,cmt-48-r8a7797", "renesas,cmt-48-gen2"; ++ reg = <0 0xffca0000 0 0x1004>; ++ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 303>; ++ clock-names = "fck"; ++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; ++ ++ renesas,channels-mask = <0x60>; ++ ++ status = "disabled"; ++ }; ++ ++ cmt1: timer@e6130000 { ++ compatible = "renesas,cmt-48-r8a7797", "renesas,cmt-48-gen2"; ++ reg = <0 0xe6130000 0 0x1004>; ++ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 302>; ++ clock-names = "fck"; ++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; ++ ++ renesas,channels-mask = <0xff>; ++ ++ status = "disabled"; ++ }; ++ ++ cmt2: timer@e6140000 { ++ compatible = "renesas,cmt-48-r8a7797", "renesas,cmt-48-gen2"; ++ reg = <0 0xe6140000 0 0x1004>; ++ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 301>; ++ clock-names = "fck"; ++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; ++ ++ renesas,channels-mask = <0xff>; ++ ++ status = "disabled"; ++ }; ++ ++ cmt3: timer@e6148000 { ++ compatible = "renesas,cmt-48-r8a7797", "renesas,cmt-48-gen2"; ++ reg = <0 0xe6148000 0 0x1004>; ++ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 300>; ++ clock-names = "fck"; ++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; ++ ++ renesas,channels-mask = <0xff>; ++ ++ status = "disabled"; ++ }; ++ ++ tpu: pwm@e6e80000 { ++ compatible = "renesas,tpu-r8a7797", "renesas,tpu"; ++ reg = <0 0xe6e80000 0 0x100>; ++ clocks = <&cpg CPG_MOD 304>; ++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; ++ status = "disabled"; ++ #pwm-cells = <4>; ++ }; ++ ++ tmu0: timer@e61e0000 { ++ compatible = "renesas,tmu-r8a7797", "renesas,tmu"; ++ reg = <0 0xe61e0000 0 0x30>; ++ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 125>; ++ clock-names = "fck"; ++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; ++ #renesas,channels = <3>; ++ status = "disabled"; ++ }; ++ ++ tmu1: timer@e6fc0000 { ++ compatible = "renesas,tmu-r8a7797", "renesas,tmu"; ++ reg = <0 0xe6fc0000 0 0x30>; ++ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 124>; ++ clock-names = "fck"; ++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; ++ #renesas,channels = <3>; ++ status = "disabled"; ++ }; ++ ++ tmu2: timer@e6fd0000 { ++ compatible = "renesas,tmu-r8a7797", "renesas,tmu"; ++ reg = <0 0xe6fd0000 0 0x30>; ++ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 123>; ++ clock-names = "fck"; ++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; ++ #renesas,channels = <3>; ++ status = "disabled"; ++ }; ++ ++ tmu3: timer@e6fe0000 { ++ compatible = "renesas,tmu-r8a7797", "renesas,tmu"; ++ reg = <0 0xe6fe0000 0 0x30>; ++ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 122>; ++ clock-names = "fck"; ++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; ++ #renesas,channels = <3>; ++ status = "disabled"; ++ }; ++ ++ tmu4: timer@ffc00000 { ++ compatible = "renesas,tmu-r8a7797", "renesas,tmu"; ++ reg = <0 0xffc00000 0 0x30>; ++ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 121>; ++ clock-names = "fck"; ++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>; ++ #renesas,channels = <3>; ++ status = "disabled"; ++ }; ++ + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7797", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x10>; @@ -970,8 +1122,10 @@ index 0000000..6eaa5ba + }; + + tsc1: thermal@0xe6190000 { -+ compatible = "renesas,thermal-r8a7797"; -+ reg = <0 0xe6190000 0 0x5c>; ++ compatible = "renesas,rcar-thermal"; ++ reg = <0 0xe6190000 0 0x14 ++ 0 0xe6190100 0 0x38>; ++ + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; /* SPI67~69:Thermal Sensor.ch0~2 */ @@ -1106,10 +1260,10 @@ index 2c224e9..c2ef11e 100644 obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o clk-div6.o diff --git a/drivers/clk/renesas/r8a7797-cpg-mssr.c b/drivers/clk/renesas/r8a7797-cpg-mssr.c new file mode 100644 -index 0000000..29dfe4a +index 0000000..6f481a4 --- /dev/null +++ b/drivers/clk/renesas/r8a7797-cpg-mssr.c -@@ -0,0 +1,222 @@ +@@ -0,0 +1,231 @@ +/* + * r8a7797 Clock Pulse Generator / Module Standby and Software Reset + * @@ -1204,6 +1358,10 @@ index 0000000..29dfe4a +}; + +static const struct mssr_mod_clk r8a7797_mod_clks[] __initconst = { ++ DEF_MOD("tmu4", 121, R8A7797_CLK_S2D2), ++ DEF_MOD("tmu3", 122, R8A7797_CLK_S2D2), ++ DEF_MOD("tmu2", 123, R8A7797_CLK_S2D2), ++ DEF_MOD("tmu1", 124, R8A7797_CLK_S2D2), + DEF_MOD("ivcp1e", 127, R8A7797_CLK_S2D1), + DEF_MOD("scif4", 203, R8A7797_CLK_S2D4), /* @@ H3=S3D4 */ + DEF_MOD("scif3", 204, R8A7797_CLK_S2D4), /* @@ H3=S3D4 */ @@ -1216,6 +1374,11 @@ index 0000000..29dfe4a + DEF_MOD("mfis", 213, R8A7797_CLK_S2D2), /* @@ H3=S3D2 */ + DEF_MOD("sys-dmac2", 217, R8A7797_CLK_S2D1), /* @@ H3=S3D1 */ + DEF_MOD("sys-dmac1", 218, R8A7797_CLK_S2D1), /* @@ H3=S3D1 */ ++ DEF_MOD("cmt3", 300, R8A7797_CLK_R), ++ DEF_MOD("cmt2", 301, R8A7797_CLK_R), ++ DEF_MOD("cmt1", 302, R8A7797_CLK_R), ++ DEF_MOD("cmt0", 303, R8A7797_CLK_R), ++ DEF_MOD("tpu", 304, R8A7797_CLK_S2D4), + DEF_MOD("sdif", 314, R8A7797_CLK_SD0), + DEF_MOD("rwdt0", 402, R8A7797_CLK_R), + DEF_MOD("intc-ex", 407, R8A7797_CLK_CP), @@ -2166,10 +2329,10 @@ index a6a8f65..9aba933 100644 .compatible = "renesas,pfc-sh73a0", diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7797.c b/drivers/pinctrl/sh-pfc/pfc-r8a7797.c new file mode 100644 -index 0000000..9b6127f +index 0000000..6b83f44 --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7797.c -@@ -0,0 +1,2586 @@ +@@ -0,0 +1,2628 @@ +/* + * R8A7797 processor support - PFC hardware block. + * @@ -3572,6 +3735,36 @@ index 0000000..9b6127f + MSIOF3_RXD_MARK, +}; + ++/* - TPU ------------------------------------------------------------------- */ ++static const unsigned int tpu_to0_pins[] = { ++ /* TPU0TO0 */ ++ RCAR_GP_PIN(4, 0), ++}; ++static const unsigned int tpu_to0_mux[] = { ++ TPU0TO0_MARK, ++}; ++static const unsigned int tpu_to1_pins[] = { ++ /* TPU0TO1 */ ++ RCAR_GP_PIN(4, 1), ++}; ++static const unsigned int tpu_to1_mux[] = { ++ TPU0TO1_MARK, ++}; ++static const unsigned int tpu_to2_pins[] = { ++ /* TPU0TO2 */ ++ RCAR_GP_PIN(4, 2), ++}; ++static const unsigned int tpu_to2_mux[] = { ++ TPU0TO2_MARK, ++}; ++static const unsigned int tpu_to3_pins[] = { ++ /* TPU0TO3 */ ++ RCAR_GP_PIN(4, 3), ++}; ++static const unsigned int tpu_to3_mux[] = { ++ TPU0TO3_MARK, ++}; ++ +/* - PWM0 ------------------------------------------------------------------- */ +static const unsigned int pwm0_a_pins[] = { + /* PWM0 */ @@ -4062,6 +4255,10 @@ index 0000000..9b6127f + SH_PFC_PIN_GROUP(msiof3_ss2), + SH_PFC_PIN_GROUP(msiof3_txd), + SH_PFC_PIN_GROUP(msiof3_rxd), ++ SH_PFC_PIN_GROUP(tpu_to0), ++ SH_PFC_PIN_GROUP(tpu_to1), ++ SH_PFC_PIN_GROUP(tpu_to2), ++ SH_PFC_PIN_GROUP(tpu_to3), + SH_PFC_PIN_GROUP(pwm0_a), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm1_a), @@ -4246,6 +4443,13 @@ index 0000000..9b6127f + "msiof3_rxd", +}; + ++static const char * const tpu_groups[] = { ++ "tpu_to0", ++ "tpu_to1", ++ "tpu_to2", ++ "tpu_to3", ++}; ++ +static const char * const pwm0_groups[] = { + "pwm0_a", + "pwm0_b", @@ -4361,6 +4565,7 @@ index 0000000..9b6127f + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), ++ SH_PFC_FUNCTION(tpu), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0030-Gen3-LVDS-cameras.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0030-Gen3-LVDS-cameras.patch index 75b3fb9..00928d1 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0030-Gen3-LVDS-cameras.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0030-Gen3-LVDS-cameras.patch @@ -5,38 +5,42 @@ Subject: [PATCH] Gen3: LVDS cameras This add Gen3 LVDS cameras support: - deserializers: MAX9286, TI964, TI954, TI960 -- cameras: ov10635, ov490+ov10640, ov495+OV2775, ar0132 +- cameras: ov10635, ov490+ov10640, ov495+OV2775, ar0132, ap0101+ar014x Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> --- drivers/media/i2c/soc_camera/Kconfig | 47 + drivers/media/i2c/soc_camera/Makefile | 7 + + drivers/media/i2c/soc_camera/ap0101_ar014x.c | 536 ++++++++++ + drivers/media/i2c/soc_camera/ap0101_ar014x.h | 28 + drivers/media/i2c/soc_camera/ar0132.c | 581 +++++++++++ drivers/media/i2c/soc_camera/ar0132.h | 213 ++++ - drivers/media/i2c/soc_camera/max9286_max9271.c | 607 ++++++++++++ - drivers/media/i2c/soc_camera/max9286_max9271.h | 244 +++++ + drivers/media/i2c/soc_camera/max9286.c | 672 +++++++++++++ + drivers/media/i2c/soc_camera/max9286.h | 244 +++++ drivers/media/i2c/soc_camera/ov10635.c | 758 ++++++++++++++ - drivers/media/i2c/soc_camera/ov10635.h | 1139 ++++++++++++++++++++++ + drivers/media/i2c/soc_camera/ov10635.h | 1139 +++++++++++++++++++++ drivers/media/i2c/soc_camera/ov10635_debug.h | 54 + - drivers/media/i2c/soc_camera/ov106xx.c | 106 ++ - drivers/media/i2c/soc_camera/ov490_ov10640.c | 1092 +++++++++++++++++++++ - drivers/media/i2c/soc_camera/ov490_ov10640.h | 93 ++ - drivers/media/i2c/soc_camera/ov495_ov2775.c | 658 +++++++++++++ + drivers/media/i2c/soc_camera/ov106xx.c | 117 +++ + drivers/media/i2c/soc_camera/ov490_ov10640.c | 1156 ++++++++++++++++++++++ + drivers/media/i2c/soc_camera/ov490_ov10640.h | 102 ++ + drivers/media/i2c/soc_camera/ov495_ov2775.c | 658 ++++++++++++ drivers/media/i2c/soc_camera/ov495_ov2775.h | 23 + drivers/media/i2c/soc_camera/ti954_ti9x3.c | 431 ++++++++ - drivers/media/i2c/soc_camera/ti964_ti9x3.c | 399 ++++++++ + drivers/media/i2c/soc_camera/ti964_ti9x3.c | 400 ++++++++ drivers/media/i2c/soc_camera/ti9x4_ti9x3.h | 153 +++ drivers/media/platform/soc_camera/rcar_csi2.c | 297 ++++-- - drivers/media/platform/soc_camera/rcar_vin.c | 174 +++- + drivers/media/platform/soc_camera/rcar_vin.c | 211 +++- drivers/media/platform/soc_camera/soc_camera.c | 17 +- drivers/media/platform/soc_camera/soc_mediabus.c | 16 + include/media/drv-intf/soc_mediabus.h | 3 + include/media/soc_camera.h | 1 + - 23 files changed, 7004 insertions(+), 109 deletions(-) + 25 files changed, 7755 insertions(+), 109 deletions(-) + create mode 100644 drivers/media/i2c/soc_camera/ap0101_ar014x.c + create mode 100644 drivers/media/i2c/soc_camera/ap0101_ar014x.h create mode 100644 drivers/media/i2c/soc_camera/ar0132.c create mode 100644 drivers/media/i2c/soc_camera/ar0132.h - create mode 100644 drivers/media/i2c/soc_camera/max9286_max9271.c - create mode 100644 drivers/media/i2c/soc_camera/max9286_max9271.h + create mode 100644 drivers/media/i2c/soc_camera/max9286.c + create mode 100644 drivers/media/i2c/soc_camera/max9286.h create mode 100644 drivers/media/i2c/soc_camera/ov10635.c create mode 100644 drivers/media/i2c/soc_camera/ov10635.h create mode 100644 drivers/media/i2c/soc_camera/ov10635_debug.h @@ -108,12 +112,12 @@ index 7704bcf..82da59f 100644 tristate "mt9m001 support" depends on SOC_CAMERA && I2C diff --git a/drivers/media/i2c/soc_camera/Makefile b/drivers/media/i2c/soc_camera/Makefile -index 6f994f9..7d4c1ab 100644 +index 6f994f9..e88f6a9 100644 --- a/drivers/media/i2c/soc_camera/Makefile +++ b/drivers/media/i2c/soc_camera/Makefile @@ -1,8 +1,15 @@ obj-$(CONFIG_SOC_CAMERA_IMX074) += imx074.o -+obj-$(CONFIG_SOC_CAMERA_MAX9286_MAX9271) += max9286_max9271.o ++obj-$(CONFIG_SOC_CAMERA_MAX9286_MAX9271) += max9286.o +obj-$(CONFIG_SOC_CAMERA_TI964_TI9X3) += ti964_ti9x3.o +obj-$(CONFIG_SOC_CAMERA_TI954_TI9X3) += ti954_ti9x3.o obj-$(CONFIG_SOC_CAMERA_MT9M001) += mt9m001.o @@ -127,14 +131,590 @@ index 6f994f9..7d4c1ab 100644 obj-$(CONFIG_SOC_CAMERA_OV2640) += ov2640.o obj-$(CONFIG_SOC_CAMERA_OV5642) += ov5642.o obj-$(CONFIG_SOC_CAMERA_OV6650) += ov6650.o +diff --git a/drivers/media/i2c/soc_camera/ap0101_ar014x.c b/drivers/media/i2c/soc_camera/ap0101_ar014x.c +new file mode 100644 +index 0000000..4757657 +--- /dev/null ++++ b/drivers/media/i2c/soc_camera/ap0101_ar014x.c +@@ -0,0 +1,536 @@ ++/* ++ * ON Semiconductor AP0101-AR014X sensor camera driver ++ * ++ * Copyright (C) 2018 Cogent Embedded, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/delay.h> ++#include <linux/init.h> ++#include <linux/i2c.h> ++#include <linux/module.h> ++#include <linux/videodev2.h> ++ ++#include <media/soc_camera.h> ++#include <media/v4l2-common.h> ++#include <media/v4l2-ctrls.h> ++#include <media/v4l2-of.h> ++ ++#include "ap0101_ar014x.h" ++ ++#define AP0101_I2C_ADDR 0x5d ++ ++#define AP0101_PID 0x0000 ++#define AP0101_VERSION_REG 0x0160 ++ ++#define AP0101_MEDIA_BUS_FMT MEDIA_BUS_FMT_YUYV8_2X8 ++ ++struct ap0101_priv { ++ struct v4l2_subdev sd; ++ struct v4l2_ctrl_handler hdl; ++ struct media_pad pad; ++ struct v4l2_rect rect; ++ int init_complete; ++ u8 id[6]; ++ int exposure; ++ int gain; ++ int autogain; ++ /* serializers */ ++ int max9286_addr; ++ int max9271_addr; ++ int port; ++ int gpio_resetb; ++ int gpio_fsin; ++ ++}; ++ ++static inline struct ap0101_priv *to_ap0101(const struct i2c_client *client) ++{ ++ return container_of(i2c_get_clientdata(client), struct ap0101_priv, sd); ++} ++ ++static void ap0101_s_port(struct i2c_client *client, int fwd_en) ++{ ++ struct ap0101_priv *priv = to_ap0101(client); ++ int tmp_addr; ++ ++ if (priv->max9286_addr) { ++ tmp_addr = client->addr; ++ client->addr = priv->max9286_addr; /* Deserializer I2C address */ ++ reg8_write(client, 0x0a, fwd_en ? 0x11 << priv->port : 0); /* Enable/disable reverse/forward control for this port */ ++ client->addr = tmp_addr; ++ }; ++} ++ ++static int ap0101_set_regs(struct i2c_client *client, ++ const struct ap0101_reg *regs, int nr_regs) ++{ ++ int i; ++ ++ for (i = 0; i < nr_regs; i++) { ++ if (regs[i].reg == AP0101_DELAY) { ++ mdelay(regs[i].val); ++ continue; ++ } ++ ++ reg16_write16(client, regs[i].reg, regs[i].val); ++ } ++ ++ return 0; ++} ++ ++static int ap0101_s_stream(struct v4l2_subdev *sd, int enable) ++{ ++ return 0; ++} ++ ++static int ap0101_get_fmt(struct v4l2_subdev *sd, ++ struct v4l2_subdev_pad_config *cfg, ++ struct v4l2_subdev_format *format) ++{ ++ struct v4l2_mbus_framefmt *mf = &format->format; ++ struct i2c_client *client = v4l2_get_subdevdata(sd); ++ struct ap0101_priv *priv = to_ap0101(client); ++ ++ if (format->pad) ++ return -EINVAL; ++ ++ mf->width = priv->rect.width; ++ mf->height = priv->rect.height; ++ mf->code = AP0101_MEDIA_BUS_FMT; ++ mf->colorspace = V4L2_COLORSPACE_SMPTE170M; ++ mf->field = V4L2_FIELD_NONE; ++ ++ return 0; ++} ++ ++static int ap0101_set_fmt(struct v4l2_subdev *sd, ++ struct v4l2_subdev_pad_config *cfg, ++ struct v4l2_subdev_format *format) ++{ ++ struct v4l2_mbus_framefmt *mf = &format->format; ++ ++ mf->code = AP0101_MEDIA_BUS_FMT; ++ mf->colorspace = V4L2_COLORSPACE_SMPTE170M; ++ mf->field = V4L2_FIELD_NONE; ++ ++ if (format->which == V4L2_SUBDEV_FORMAT_TRY) ++ cfg->try_fmt = *mf; ++ ++ return 0; ++} ++ ++static int ap0101_enum_mbus_code(struct v4l2_subdev *sd, ++ struct v4l2_subdev_pad_config *cfg, ++ struct v4l2_subdev_mbus_code_enum *code) ++{ ++ if (code->pad || code->index > 0) ++ return -EINVAL; ++ ++ code->code = AP0101_MEDIA_BUS_FMT; ++ ++ return 0; ++} ++ ++static int ap0101_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) ++{ ++ struct i2c_client *client = v4l2_get_subdevdata(sd); ++ struct ap0101_priv *priv = to_ap0101(client); ++ ++ memcpy(edid->edid, priv->id, 6); ++ ++ edid->edid[6] = 0xff; ++ edid->edid[7] = client->addr; ++ edid->edid[8] = AP0101_VERSION_REG >> 8; ++ edid->edid[9] = AP0101_VERSION_REG & 0xff; ++ ++ return 0; ++} ++ ++static int ap0101_set_selection(struct v4l2_subdev *sd, ++ struct v4l2_subdev_pad_config *cfg, ++ struct v4l2_subdev_selection *sel) ++{ ++ struct v4l2_rect *rect = &sel->r; ++ struct i2c_client *client = v4l2_get_subdevdata(sd); ++ struct ap0101_priv *priv = to_ap0101(client); ++ ++ if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE || ++ sel->target != V4L2_SEL_TGT_CROP) ++ return -EINVAL; ++ ++ rect->left = ALIGN(rect->left, 2); ++ rect->top = ALIGN(rect->top, 2); ++ rect->width = ALIGN(rect->width, 2); ++ rect->height = ALIGN(rect->height, 2); ++ ++ if ((rect->left + rect->width > AP0101_MAX_WIDTH) || ++ (rect->top + rect->height > AP0101_MAX_HEIGHT)) ++ *rect = priv->rect; ++ ++ priv->rect.left = rect->left; ++ priv->rect.top = rect->top; ++ priv->rect.width = rect->width; ++ priv->rect.height = rect->height; ++ ++ return 0; ++} ++ ++static int ap0101_get_selection(struct v4l2_subdev *sd, ++ struct v4l2_subdev_pad_config *cfg, ++ struct v4l2_subdev_selection *sel) ++{ ++ struct i2c_client *client = v4l2_get_subdevdata(sd); ++ struct ap0101_priv *priv = to_ap0101(client); ++ ++ if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) ++ return -EINVAL; ++ ++ switch (sel->target) { ++ case V4L2_SEL_TGT_CROP_BOUNDS: ++ sel->r.left = 0; ++ sel->r.top = 0; ++ sel->r.width = AP0101_MAX_WIDTH; ++ sel->r.height = AP0101_MAX_HEIGHT; ++ return 0; ++ case V4L2_SEL_TGT_CROP_DEFAULT: ++ sel->r.left = 0; ++ sel->r.top = 0; ++ sel->r.width = AP0101_MAX_WIDTH; ++ sel->r.height = AP0101_MAX_HEIGHT; ++ return 0; ++ case V4L2_SEL_TGT_CROP: ++ sel->r = priv->rect; ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static int ap0101_g_mbus_config(struct v4l2_subdev *sd, ++ struct v4l2_mbus_config *cfg) ++{ ++ cfg->flags = V4L2_MBUS_CSI2_1_LANE | V4L2_MBUS_CSI2_CHANNEL_0 | ++ V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; ++ cfg->type = V4L2_MBUS_CSI2; ++ ++ return 0; ++} ++ ++#ifdef CONFIG_VIDEO_ADV_DEBUG ++static int ap0101_g_register(struct v4l2_subdev *sd, ++ struct v4l2_dbg_register *reg) ++{ ++ struct i2c_client *client = v4l2_get_subdevdata(sd); ++ int ret; ++ u16 val = 0; ++ ++ ret = reg16_read16(client, (u16)reg->reg, &val); ++ if (ret < 0) ++ return ret; ++ ++ reg->val = val; ++ reg->size = sizeof(u16); ++ ++ return 0; ++} ++ ++static int ap0101_s_register(struct v4l2_subdev *sd, ++ const struct v4l2_dbg_register *reg) ++{ ++ struct i2c_client *client = v4l2_get_subdevdata(sd); ++ ++ return reg16_write16(client, (u16)reg->reg, (u16)reg->val); ++} ++#endif ++ ++static struct v4l2_subdev_core_ops ap0101_core_ops = { ++#ifdef CONFIG_VIDEO_ADV_DEBUG ++ .g_register = ap0101_g_register, ++ .s_register = ap0101_s_register, ++#endif ++}; ++ ++static int ap0101_s_ctrl(struct v4l2_ctrl *ctrl) ++{ ++ struct v4l2_subdev *sd = to_sd(ctrl); ++ struct i2c_client *client = v4l2_get_subdevdata(sd); ++ struct ap0101_priv *priv = to_ap0101(client); ++ int ret = -EINVAL; ++ ++ if (!priv->init_complete) ++ return 0; ++ ++ switch (ctrl->id) { ++ case V4L2_CID_BRIGHTNESS: ++ case V4L2_CID_CONTRAST: ++ case V4L2_CID_SATURATION: ++ case V4L2_CID_HUE: ++ case V4L2_CID_GAMMA: ++ case V4L2_CID_SHARPNESS: ++ case V4L2_CID_AUTOGAIN: ++ case V4L2_CID_GAIN: ++ case V4L2_CID_EXPOSURE: ++ case V4L2_CID_HFLIP: ++ case V4L2_CID_VFLIP: ++ break; ++ } ++ ++ return ret; ++} ++ ++static const struct v4l2_ctrl_ops ap0101_ctrl_ops = { ++ .s_ctrl = ap0101_s_ctrl, ++}; ++ ++static struct v4l2_subdev_video_ops ap0101_video_ops = { ++ .s_stream = ap0101_s_stream, ++ .g_mbus_config = ap0101_g_mbus_config, ++}; ++ ++static const struct v4l2_subdev_pad_ops ap0101_subdev_pad_ops = { ++ .get_edid = ap0101_get_edid, ++ .enum_mbus_code = ap0101_enum_mbus_code, ++ .get_selection = ap0101_get_selection, ++ .set_selection = ap0101_set_selection, ++ .get_fmt = ap0101_get_fmt, ++ .set_fmt = ap0101_set_fmt, ++}; ++ ++static struct v4l2_subdev_ops ap0101_subdev_ops = { ++ .core = &ap0101_core_ops, ++ .video = &ap0101_video_ops, ++ .pad = &ap0101_subdev_pad_ops, ++}; ++ ++static void ap0101_otp_id_read(struct i2c_client *client) ++{ ++} ++ ++static ssize_t ap0101_otp_id_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ struct v4l2_subdev *sd = i2c_get_clientdata(to_i2c_client(dev)); ++ struct i2c_client *client = v4l2_get_subdevdata(sd); ++ struct ap0101_priv *priv = to_ap0101(client); ++ ++ return snprintf(buf, 32, "%02x:%02x:%02x:%02x:%02x:%02x\n", ++ priv->id[0], priv->id[1], priv->id[2], priv->id[3], priv->id[4], priv->id[5]); ++} ++ ++static DEVICE_ATTR(otp_id_ap0101, S_IRUGO, ap0101_otp_id_show, NULL); ++ ++static int ap0101_initialize(struct i2c_client *client) ++{ ++ struct ap0101_priv *priv = to_ap0101(client); ++ u16 pid = 0; ++ int ret = 0; ++ ++ ap0101_s_port(client, 1); ++ ++ /* check and show model ID */ ++ reg16_read16(client, AP0101_PID, &pid); ++ ++ if (pid != AP0101_VERSION_REG) { ++ dev_dbg(&client->dev, "Product ID error %x\n", pid); ++ ret = -ENODEV; ++ goto err; ++ } ++ ++ /* Program wizard registers */ ++ ap0101_set_regs(client, ap0101_regs_wizard, ARRAY_SIZE(ap0101_regs_wizard)); ++ ++ /* Read OTP IDs */ ++ ap0101_otp_id_read(client); ++ ++ dev_info(&client->dev, "ap0101 PID %x, res %dx%d, OTP_ID %02x:%02x:%02x:%02x:%02x:%02x\n", ++ pid, AP0101_MAX_WIDTH, AP0101_MAX_HEIGHT, priv->id[0], priv->id[1], priv->id[2], priv->id[3], priv->id[4], priv->id[5]); ++err: ++ ap0101_s_port(client, 0); ++ ++ return ret; ++} ++ ++static int ap0101_parse_dt(struct device_node *np, struct ap0101_priv *priv) ++{ ++ struct i2c_client *client = v4l2_get_subdevdata(&priv->sd); ++ int i; ++ struct device_node *endpoint = NULL, *rendpoint = NULL; ++ int tmp_addr = 0; ++ ++ for (i = 0; ; i++) { ++ endpoint = of_graph_get_next_endpoint(np, endpoint); ++ if (!endpoint) ++ break; ++ ++ of_node_put(endpoint); ++ ++ rendpoint = of_parse_phandle(endpoint, "remote-endpoint", 0); ++ if (!rendpoint) ++ continue; ++ ++ if (!of_property_read_u32(rendpoint, "max9271-addr", &priv->max9271_addr) && ++ !of_property_read_u32(rendpoint->parent->parent, "reg", &priv->max9286_addr) && ++ !kstrtouint(strrchr(rendpoint->full_name, '@') + 1, 0, &priv->port)) ++ break; ++ } ++ ++ if (!priv->max9286_addr) { ++ dev_err(&client->dev, "deserializer does not present for AP0101\n"); ++ return -EINVAL; ++ } ++ ++ ap0101_s_port(client, 1); ++ ++ /* setup I2C translator address */ ++ tmp_addr = client->addr; ++ if (priv->max9286_addr) { ++ client->addr = priv->max9271_addr; /* Serializer I2C address */ ++ ++ reg8_write(client, 0x09, tmp_addr << 1); /* Sensor translated I2C address */ ++ reg8_write(client, 0x0A, AP0101_I2C_ADDR << 1); /* Sensor native I2C address */ ++ usleep_range(2000, 2500); /* wait 2ms */ ++ }; ++ client->addr = tmp_addr; ++ ++ mdelay(10); ++ ++ return 0; ++} ++ ++static int ap0101_probe(struct i2c_client *client, ++ const struct i2c_device_id *did) ++{ ++ struct ap0101_priv *priv; ++ int ret; ++ ++ priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ v4l2_i2c_subdev_init(&priv->sd, client, &ap0101_subdev_ops); ++ priv->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE; ++ ++ priv->exposure = 0x100; ++ priv->gain = 0x100; ++ priv->autogain = 1; ++ v4l2_ctrl_handler_init(&priv->hdl, 4); ++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops, ++ V4L2_CID_BRIGHTNESS, 0, 16, 1, 7); ++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops, ++ V4L2_CID_CONTRAST, 0, 16, 1, 7); ++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops, ++ V4L2_CID_SATURATION, 0, 7, 1, 2); ++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops, ++ V4L2_CID_HUE, 0, 23, 1, 12); ++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops, ++ V4L2_CID_GAMMA, -128, 128, 1, 0); ++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops, ++ V4L2_CID_SHARPNESS, 0, 10, 1, 3); ++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops, ++ V4L2_CID_AUTOGAIN, 0, 1, 1, priv->autogain); ++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops, ++ V4L2_CID_GAIN, 0, 0xffff, 1, priv->gain); ++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops, ++ V4L2_CID_EXPOSURE, 0, 0xffff, 1, priv->exposure); ++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops, ++ V4L2_CID_HFLIP, 0, 1, 1, 1); ++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops, ++ V4L2_CID_VFLIP, 0, 1, 1, 0); ++ priv->sd.ctrl_handler = &priv->hdl; ++ ++ ret = priv->hdl.error; ++ if (ret) ++ goto cleanup; ++ ++ v4l2_ctrl_handler_setup(&priv->hdl); ++ ++ priv->pad.flags = MEDIA_PAD_FL_SOURCE; ++ priv->sd.entity.flags |= MEDIA_ENT_F_CAM_SENSOR; ++ ret = media_entity_pads_init(&priv->sd.entity, 1, &priv->pad); ++ if (ret < 0) ++ goto cleanup; ++ ++ ret = ap0101_parse_dt(client->dev.of_node, priv); ++ if (ret) ++ goto cleanup; ++ ++ ret = ap0101_initialize(client); ++ if (ret < 0) ++ goto cleanup; ++ ++ priv->rect.left = 0; ++ priv->rect.top = 0; ++ priv->rect.width = AP0101_MAX_WIDTH; ++ priv->rect.height = AP0101_MAX_HEIGHT; ++ ++ ret = v4l2_async_register_subdev(&priv->sd); ++ if (ret) ++ goto cleanup; ++ ++ if (device_create_file(&client->dev, &dev_attr_otp_id_ap0101) != 0) { ++ dev_err(&client->dev, "sysfs otp_id entry creation failed\n"); ++ goto cleanup; ++ } ++ ++ priv->init_complete = 1; ++ ++ return 0; ++ ++cleanup: ++ media_entity_cleanup(&priv->sd.entity); ++ v4l2_ctrl_handler_free(&priv->hdl); ++ v4l2_device_unregister_subdev(&priv->sd); ++#ifdef CONFIG_SOC_CAMERA_AP0101 ++ v4l_err(client, "failed to probe @ 0x%02x (%s)\n", ++ client->addr, client->adapter->name); ++#endif ++ return ret; ++} ++ ++static int ap0101_remove(struct i2c_client *client) ++{ ++ struct ap0101_priv *priv = i2c_get_clientdata(client); ++ ++ device_remove_file(&client->dev, &dev_attr_otp_id_ap0101); ++ v4l2_async_unregister_subdev(&priv->sd); ++ media_entity_cleanup(&priv->sd.entity); ++ v4l2_ctrl_handler_free(&priv->hdl); ++ v4l2_device_unregister_subdev(&priv->sd); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_SOC_CAMERA_AP0101 ++static const struct i2c_device_id ap0101_id[] = { ++ { "ap0101", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, ap0101_id); ++ ++static const struct of_device_id ap0101_of_ids[] = { ++ { .compatible = "aptina,ap0101", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, ap0101_of_ids); ++ ++static struct i2c_driver ap0101_i2c_driver = { ++ .driver = { ++ .name = "ap0101", ++ .of_match_table = ap0101_of_ids, ++ }, ++ .probe = ap0101_probe, ++ .remove = ap0101_remove, ++ .id_table = ap0101_id, ++}; ++ ++module_i2c_driver(ap0101_i2c_driver); ++ ++MODULE_DESCRIPTION("SoC Camera driver for AP0101"); ++MODULE_AUTHOR("Vladimir Barinov"); ++MODULE_LICENSE("GPL"); ++#endif +diff --git a/drivers/media/i2c/soc_camera/ap0101_ar014x.h b/drivers/media/i2c/soc_camera/ap0101_ar014x.h +new file mode 100644 +index 0000000..16599a1 +--- /dev/null ++++ b/drivers/media/i2c/soc_camera/ap0101_ar014x.h +@@ -0,0 +1,28 @@ ++/* ++ * ON Semiconductor ap0101-ar014x sensor camera wizard 1280x720@30/UYVY/BT601/8bit ++ * ++ * Copyright (C) 2018 Cogent Embedded, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#define AP0101_MAX_WIDTH 1280 ++#define AP0101_MAX_HEIGHT 720 ++ ++#define AP0101_DELAY 0xffff ++ ++struct ap0101_reg { ++ u16 reg; ++ u16 val; ++}; ++ ++static const struct ap0101_reg ap0101_regs_wizard[] = { ++/* enable FSIN */ ++{0xc88c, 0x0303}, ++{0xfc00, 0x2800}, ++{0x0040, 0x8100}, ++{AP0101_DELAY, 100}, ++}; diff --git a/drivers/media/i2c/soc_camera/ar0132.c b/drivers/media/i2c/soc_camera/ar0132.c new file mode 100644 -index 0000000..decbf5f +index 0000000..bbaeeaae --- /dev/null +++ b/drivers/media/i2c/soc_camera/ar0132.c @@ -0,0 +1,581 @@ +/* -+ * Aptina AR0132 sensor camera driver ++ * ON Semiconductor AR0132 sensor camera driver + * + * Copyright (C) 2017 Cogent Embedded, Inc. + * @@ -716,12 +1296,12 @@ index 0000000..decbf5f +#endif diff --git a/drivers/media/i2c/soc_camera/ar0132.h b/drivers/media/i2c/soc_camera/ar0132.h new file mode 100644 -index 0000000..055841d +index 0000000..bcee0e5 --- /dev/null +++ b/drivers/media/i2c/soc_camera/ar0132.h @@ -0,0 +1,213 @@ +/* -+ * OmniVision ar0132 sensor camera wizard 1110x620@30/BGGR/BT601/12bit ++ * ON Semiconductor ar0132 sensor camera wizard 1110x620@30/BGGR/BT601/12bit + * + * Copyright (C) 2017 Cogent Embedded, Inc. + * @@ -933,16 +1513,16 @@ index 0000000..055841d +{0x31D0, 0x0001}, +{0x30B0, 0x2002}, +}; -diff --git a/drivers/media/i2c/soc_camera/max9286_max9271.c b/drivers/media/i2c/soc_camera/max9286_max9271.c +diff --git a/drivers/media/i2c/soc_camera/max9286.c b/drivers/media/i2c/soc_camera/max9286.c new file mode 100644 -index 0000000..91223a0 +index 0000000..20ef2de --- /dev/null -+++ b/drivers/media/i2c/soc_camera/max9286_max9271.c -@@ -0,0 +1,607 @@ ++++ b/drivers/media/i2c/soc_camera/max9286.c +@@ -0,0 +1,672 @@ +/* -+ * MAXIM max9286-max9271 GMSL driver ++ * MAXIM max9286 GMSL driver + * -+ * Copyright (C) 2015-2017 Cogent Embedded, Inc. ++ * Copyright (C) 2015-2018 Cogent Embedded, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the @@ -963,7 +1543,7 @@ index 0000000..91223a0 +#include <media/v4l2-of.h> +#include <media/v4l2-subdev.h> + -+#include "max9286_max9271.h" ++#include "max9286.h" + +#define MAXIM_I2C_I2C_SPEED_837KHZ (0x7 << 2) /* 837kbps */ +#define MAXIM_I2C_I2C_SPEED_533KHZ (0x6 << 2) /* 533kbps */ @@ -974,7 +1554,7 @@ index 0000000..91223a0 +#define MAXIM_I2C_I2C_SPEED_028KHZ (0x1 << 2) /* 28.3 kbps */ +#define MAXIM_I2C_I2C_SPEED MAXIM_I2C_I2C_SPEED_339KHZ + -+struct max9286_max9271_priv { ++struct max9286_priv { + struct v4l2_subdev sd[4]; + struct device_node *sd_of_node[4]; + int des_addr; @@ -988,47 +1568,68 @@ index 0000000..91223a0 + char pclk_rising_edge; + int gpio_resetb; + int active_low_resetb; ++ int him; ++ int hsync; ++ int vsync; + int timeout; + atomic_t use_count; + u32 csi2_outord; + struct i2c_client *client; + int max9271_addr_map[4]; ++ int ser_id; + struct regulator *poc_supply[4]; /* PoC power supply */ +}; + -+static int force_conf_link; -+static int force_poc_trig; -+#ifndef MODULE -+static __init int max9286_max9271_force_conf_link(char *str) -+{ -+ /* force configuration link */ -+ /* used only if robust firmware flashing required (f.e. recovery) */ -+ force_conf_link = 1; -+ return 0; -+} -+early_param("force_conf_link", max9286_max9271_force_conf_link); ++static int conf_link; ++module_param(conf_link, int, 0644); ++MODULE_PARM_DESC(conf_link, " Force configuration link. Used only if robust firmware flashing required (f.e. recovery)"); ++ ++static int poc_trig; ++module_param(poc_trig, int, 0644); ++MODULE_PARM_DESC(poc_trig, " Use PoC triggering during reverse channel setup. Useful on systems with dedicated PoC and unstable ser-des lock */"); ++ ++static int him; ++module_param(him, int, 0644); ++MODULE_PARM_DESC(him, " Use High-Immunity mode (default: leagacy mode) */"); ++ ++static int fsync_period; ++module_param(fsync_period, int, 0644); ++MODULE_PARM_DESC(fsync_period, " Frame sync period (default: 3.2MHz) */"); ++ ++static int hsync; ++module_param(hsync, int, 0644); ++MODULE_PARM_DESC(hsync, " HSYNC invertion (default: 0 - not inverted) */"); + -+static __init int max9286_max9271_force_poc_trig(char *str) ++static int vsync = 1; ++module_param(vsync, int, 0644); ++MODULE_PARM_DESC(vsync, " VSYNC invertion (default: 1 - inverted) */"); ++ ++static char* ser_name(int id) +{ -+ /* force PoC triggering during reverse channel setup */ -+ /* to be used on systems with dedicated PoC and unstable ser-des lock */ -+ force_poc_trig = 1; -+ return 0; ++ switch (id) { ++ case MAX9271_ID: ++ return "MAX9271"; ++ case MAX96705_ID: ++ return "MAX96705"; ++ default: ++ return "unknown"; ++ } +} -+early_param("force_poc_trig", max9286_max9271_force_poc_trig); -+#endif + -+static void max9286_max9271_preinit(struct i2c_client *client, int addr) ++static void max9286_preinit(struct i2c_client *client, int addr) +{ ++ struct max9286_priv *priv = i2c_get_clientdata(client); ++ + client->addr = addr; /* MAX9286-CAMx I2C */ + reg8_write(client, 0x0a, 0x00); /* disable reverse control for all cams */ + reg8_write(client, 0x00, 0x00); /* disable all GMSL links [0:3] */ + usleep_range(2000, 2500); /* wait 2ms after any change of reverse channel settings */ ++ reg8_write(client, 0x1c, priv->him ? 0xf4 : 0x04); /* high-immunity or legacy mode */ +} + -+static void max9286_max9271_sensor_reset(struct i2c_client *client, int addr, int reset_on) ++static void max9286_sensor_reset(struct i2c_client *client, int addr, int reset_on) +{ -+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client); ++ struct max9286_priv *priv = i2c_get_clientdata(client); + + if (priv->gpio_resetb < 1 || priv->gpio_resetb > 5) + return; @@ -1040,9 +1641,9 @@ index 0000000..91223a0 + reg8_write(client, 0x0e, 0x42 | BIT(priv->gpio_resetb)); /* set GPIOn direction output */ +} + -+static void max9286_max9271_postinit(struct i2c_client *client, int addr) ++static void max9286_postinit(struct i2c_client *client, int addr) +{ -+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client); ++ struct max9286_priv *priv = i2c_get_clientdata(client); + int idx; + + for (idx = 0; idx < priv->links; idx++) { @@ -1050,7 +1651,7 @@ index 0000000..91223a0 + reg8_write(client, 0x0a, 0x11 << idx); /* enable reverse/forward control for CAMx */ + + client->addr = priv->max9271_addr_map[idx]; /* MAX9271-CAMx I2C */ -+ max9286_max9271_sensor_reset(client, client->addr, 0); /* sensor unreset */ ++ max9286_sensor_reset(client, client->addr, 0); /* sensor unreset */ + } + + client->addr = addr; /* MAX9286 I2C */ @@ -1062,9 +1663,9 @@ index 0000000..91223a0 + usleep_range(5000, 5500); /* wait 2ms after any change of reverse channel settings */ +} + -+static int max9286_max9271_reverse_channel_setup(struct i2c_client *client, int idx) ++static int max9286_reverse_channel_setup(struct i2c_client *client, int idx) +{ -+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client); ++ struct max9286_priv *priv = i2c_get_clientdata(client); + u8 val = 0; + int timeout = priv->timeout; + char timeout_str[10]; @@ -1087,8 +1688,8 @@ index 0000000..91223a0 + client->addr = 0x40; /* MAX9271-CAMx I2C */ + reg8_write(client, 0x04, 0x43); /* wake-up, enable reverse_control/conf_link */ + usleep_range(2000, 2500); /* wait 2ms after any change of reverse channel settings */ -+ reg8_write(client, 0x08, 0x1); /* reverse channel receiver high threshold enable */ -+ reg8_write(client, 0x97, 0x5f); /* enable reverse control channel programming (MAX96705-MAX96711 only) */ ++ reg8_write(client, 0x08, 0x01); /* reverse channel receiver high threshold enable */ ++ reg8_write(client, 0x97, priv->him ? 0xaf : 0x5f); /* enable reverse control channel programming (MAX96705-MAX96711 only) */ + usleep_range(2000, 2500); /* wait 2ms after any change of reverse channel settings */ + + client->addr = priv->des_addr; /* MAX9286-CAMx I2C */ @@ -1097,20 +1698,23 @@ index 0000000..91223a0 + + client->addr = 0x40; /* MAX9271-CAMx I2C */ + reg8_read(client, 0x1e, &val); /* read max9271 ID */ -+ if (val == MAX9271_ID || val == MAX96705_ID || --timeout == 0) ++ if (val == MAX9271_ID || val == MAX96705_ID || --timeout == 0) { ++ priv->ser_id = val; + break; ++ } + + /* Check if already initialized (after reboot/reset ?) */ + client->addr = priv->max9271_addr_map[idx]; /* MAX9271-CAMx I2C */ + reg8_read(client, 0x1e, &val); /* read max9271 ID */ + if (val == MAX9271_ID || val == MAX96705_ID) { ++ priv->ser_id = val; + reg8_write(client, 0x04, 0x43); /* enable reverse_control/conf_link */ + usleep_range(2000, 2500); /* wait 2ms after any change of reverse channel settings */ + ret = -EADDRINUSE; + break; + } + -+ if (timeout == priv->timeout / 2 && force_poc_trig) { ++ if (timeout == priv->timeout / 2 && poc_trig) { + if (!IS_ERR(priv->poc_supply[idx])) { + if (regulator_disable(priv->poc_supply[idx])) + dev_err(&client->dev, "fail to disable POC%d regulator\n", idx); @@ -1121,7 +1725,7 @@ index 0000000..91223a0 + } + } + -+ max9286_max9271_sensor_reset(client, client->addr, 1); /* sensor reset */ ++ max9286_sensor_reset(client, client->addr, 1); /* sensor reset */ + + if (!timeout) { + ret = -ETIMEDOUT; @@ -1134,7 +1738,7 @@ index 0000000..91223a0 + +out: + sprintf(timeout_str, "retries=%d", priv->timeout - timeout); -+ dev_info(&client->dev, "link%d MAX9271 %sat 0x%x %s %s\n", idx, ++ dev_info(&client->dev, "link%d %s %sat 0x%x %s %s\n", idx, ser_name(priv->ser_id), + ret == -EADDRINUSE ? "already " : "", priv->max9271_addr_map[idx], + ret == -ETIMEDOUT ? "not found: timeout GMSL link establish" : "", + priv->timeout - timeout? timeout_str : ""); @@ -1142,9 +1746,9 @@ index 0000000..91223a0 + return ret; +} + -+static void max9286_max9271_initial_setup(struct i2c_client *client) ++static void max9286_initial_setup(struct i2c_client *client) +{ -+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client); ++ struct max9286_priv *priv = i2c_get_clientdata(client); + + /* Initial setup */ + client->addr = priv->des_addr; /* MAX9286-CAMx I2C */ @@ -1167,10 +1771,11 @@ index 0000000..91223a0 + dev_err(&client->dev, "CSI2 lanes number is invalid (%d)\n", priv->lanes); + } + ++ reg8_write(client, 0x06, priv->fsync_period & 0xff); ++ reg8_write(client, 0x07, (priv->fsync_period >> 8) & 0xff); ++ reg8_write(client, 0x08, priv->fsync_period >> 16); ++ + if (strcmp(priv->fsync_mode, "manual") == 0) { -+ reg8_write(client, 0x06, priv->fsync_period & 0xff); -+ reg8_write(client, 0x07, (priv->fsync_period >> 8) & 0xff); -+ reg8_write(client, 0x08, priv->fsync_period >> 16); + reg8_write(client, 0x01, 0x00); /* manual: FRAMESYNC set manually via [0x06:0x08] regs */ + } else if (strcmp(priv->fsync_mode, "automatic") == 0) { + reg8_write(client, 0x01, 0x02); /* automatic: FRAMESYNC taken from the slowest Link */ @@ -1182,12 +1787,13 @@ index 0000000..91223a0 + + reg8_write(client, 0x63, 0); /* disable overlap window */ + reg8_write(client, 0x64, 0); -+ reg8_write(client, 0x0c, 0x89); /* enable HS/VS encoding, use D14/15 for HS/VS, invert VS */ ++ reg8_write(client, 0x0c, 0x91 | (priv->vsync ? BIT(3) : 0) | (priv->hsync ? BIT(2) : 0)); /* enable HS/VS encoding, use D14/15 for HS/VS, invert HS/VS */ ++ reg8_write(client, 0x19, 0x0c); /* Drive HSTRAIL state for 120ns after the last payload bit */ +} + -+static void max9286_max9271_gmsl_link_setup(struct i2c_client *client, int idx) ++static void max9286_gmsl_link_setup(struct i2c_client *client, int idx) +{ -+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client); ++ struct max9286_priv *priv = i2c_get_clientdata(client); + + /* GMSL setup */ + client->addr = 0x40; /* MAX9271-CAMx I2C */ @@ -1197,6 +1803,27 @@ index 0000000..91223a0 + reg8_write(client, 0x02, 0xff); /* spread spectrum +-4%, pclk range automatic, Gbps automatic */ + usleep_range(2000, 2500); /* wait 2ms */ + ++ if (priv->ser_id == MAX96705_ID) { ++ /* setup crossbar in DBL mode: reverse DVP bus */ ++ reg8_write(client, 0x20, 0x07); ++ reg8_write(client, 0x21, 0x06); ++ reg8_write(client, 0x22, 0x05); ++ reg8_write(client, 0x23, 0x04); ++ reg8_write(client, 0x24, 0x03); ++ reg8_write(client, 0x25, 0x02); ++ reg8_write(client, 0x26, 0x01); ++ reg8_write(client, 0x27, 0x00); ++ ++ reg8_write(client, 0x30, 0x17); ++ reg8_write(client, 0x31, 0x16); ++ reg8_write(client, 0x32, 0x15); ++ reg8_write(client, 0x33, 0x14); ++ reg8_write(client, 0x34, 0x13); ++ reg8_write(client, 0x35, 0x12); ++ reg8_write(client, 0x36, 0x11); ++ reg8_write(client, 0x37, 0x10); ++ } ++ + client->addr = priv->des_addr; /* MAX9286-CAMx I2C */ + reg8_write(client, 0x34, 0x22 | MAXIM_I2C_I2C_SPEED); /* disable artificial ACK, I2C speed set */ + usleep_range(2000, 2500); /* wait 2ms */ @@ -1223,9 +1850,9 @@ index 0000000..91223a0 +#endif +} + -+static int max9286_max9271_initialize(struct i2c_client *client) ++static int max9286_initialize(struct i2c_client *client) +{ -+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client); ++ struct max9286_priv *priv = i2c_get_clientdata(client); + int idx, ret; + + dev_info(&client->dev, "LINKs=%d, LANES=%d, FSYNC mode=%s, FSYNC period=%d, PCLK edge=%s\n", @@ -1233,10 +1860,10 @@ index 0000000..91223a0 + priv->pclk_rising_edge ? "rising" : "falling"); + + if (priv->des_quirk_addr) -+ max9286_max9271_preinit(client, priv->des_quirk_addr); ++ max9286_preinit(client, priv->des_quirk_addr); + -+ max9286_max9271_preinit(client, priv->des_addr); -+ max9286_max9271_initial_setup(client); ++ max9286_preinit(client, priv->des_addr); ++ max9286_initial_setup(client); + + for (idx = 0; idx < priv->links; idx++) { + if (!IS_ERR(priv->poc_supply[idx])) { @@ -1244,13 +1871,13 @@ index 0000000..91223a0 + dev_err(&client->dev, "fail to enable POC%d regulator\n", idx); + } + -+ ret = max9286_max9271_reverse_channel_setup(client, idx); ++ ret = max9286_reverse_channel_setup(client, idx); + if (ret) + continue; -+ max9286_max9271_gmsl_link_setup(client, idx); ++ max9286_gmsl_link_setup(client, idx); + } + -+ max9286_max9271_postinit(client, priv->des_addr); ++ max9286_postinit(client, priv->des_addr); + + client->addr = priv->des_addr; + @@ -1258,10 +1885,10 @@ index 0000000..91223a0 +} + +#ifdef CONFIG_VIDEO_ADV_DEBUG -+static int max9286_max9271_g_register(struct v4l2_subdev *sd, ++static int max9286_g_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) +{ -+ struct max9286_max9271_priv *priv = v4l2_get_subdevdata(sd); ++ struct max9286_priv *priv = v4l2_get_subdevdata(sd); + struct i2c_client *client = priv->client; + int ret; + u8 val = 0; @@ -1276,19 +1903,19 @@ index 0000000..91223a0 + return 0; +} + -+static int max9286_max9271_s_register(struct v4l2_subdev *sd, ++static int max9286_s_register(struct v4l2_subdev *sd, + const struct v4l2_dbg_register *reg) +{ -+ struct max9286_max9271_priv *priv = v4l2_get_subdevdata(sd); ++ struct max9286_priv *priv = v4l2_get_subdevdata(sd); + struct i2c_client *client = priv->client; + + return reg8_write(client, (u8)reg->reg, (u8)reg->val); +} +#endif + -+static int max9286_max9271_s_power(struct v4l2_subdev *sd, int on) ++static int max9286_s_power(struct v4l2_subdev *sd, int on) +{ -+ struct max9286_max9271_priv *priv = v4l2_get_subdevdata(sd); ++ struct max9286_priv *priv = v4l2_get_subdevdata(sd); + struct i2c_client *client = priv->client; + + if (on) { @@ -1302,9 +1929,9 @@ index 0000000..91223a0 + return 0; +} + -+static int max9286_max9271_registered_async(struct v4l2_subdev *sd) ++static int max9286_registered_async(struct v4l2_subdev *sd) +{ -+ struct max9286_max9271_priv *priv = v4l2_get_subdevdata(sd); ++ struct max9286_priv *priv = v4l2_get_subdevdata(sd); + struct i2c_client *client = priv->client; + int idx, tmp_addr; + @@ -1316,7 +1943,7 @@ index 0000000..91223a0 + reg8_write(client, 0x0a, 0x11 << idx); /* enable reverse/forward control for CAMx */ + + client->addr = priv->max9271_addr_map[idx]; /* MAX9271-CAMx */ -+ reg8_write(client, 0x04, force_conf_link ? 0x43 : 0x83); /* enable reverse_control/serial_link */ ++ reg8_write(client, 0x04, conf_link ? 0x43 : 0x83); /* enable serial_link */ + usleep_range(2000, 2500); /* wait 2ms after changing reverse_control */ + + client->addr = priv->des_addr; /* MAX9286 I2C */ @@ -1327,22 +1954,22 @@ index 0000000..91223a0 + return 0; +} + -+static struct v4l2_subdev_core_ops max9286_max9271_subdev_core_ops = { ++static struct v4l2_subdev_core_ops max9286_subdev_core_ops = { +#ifdef CONFIG_VIDEO_ADV_DEBUG -+ .g_register = max9286_max9271_g_register, -+ .s_register = max9286_max9271_s_register, ++ .g_register = max9286_g_register, ++ .s_register = max9286_s_register, +#endif -+ .s_power = max9286_max9271_s_power, -+ .registered_async = max9286_max9271_registered_async, ++ .s_power = max9286_s_power, ++ .registered_async = max9286_registered_async, +}; + -+static struct v4l2_subdev_ops max9286_max9271_subdev_ops = { -+ .core = &max9286_max9271_subdev_core_ops, ++static struct v4l2_subdev_ops max9286_subdev_ops = { ++ .core = &max9286_subdev_core_ops, +}; + -+static int max9286_max9271_parse_dt(struct i2c_client *client) ++static int max9286_parse_dt(struct i2c_client *client) +{ -+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client); ++ struct max9286_priv *priv = i2c_get_clientdata(client); + struct device_node *np = client->dev.of_node; + struct device_node *endpoint = NULL; + struct property *prop; @@ -1402,6 +2029,24 @@ index 0000000..91223a0 + priv->timeout = 100; + if (of_property_read_u32(np, "maxim,i2c-quirk", &priv->des_quirk_addr)) + priv->des_quirk_addr = 0; ++ if (of_property_read_u32(np, "maxim,him", &priv->him)) ++ priv->him = 0; ++ if (of_property_read_u32(np, "maxim,hsync", &priv->hsync)) ++ priv->hsync = 0; ++ if (of_property_read_u32(np, "maxim,vsync", &priv->vsync)) ++ priv->vsync = 1; ++ ++ /* module params override dts */ ++ if (him) ++ priv->him = him; ++ if (fsync_period) { ++ priv->fsync_period = fsync_period; ++ priv->fsync_mode = fsync_mode_default; ++ } ++ if (hsync) ++ priv->hsync = hsync; ++ if (!vsync) ++ priv->vsync = vsync; + + for (i = 0; i < priv->links; i++) { + endpoint = of_graph_get_next_endpoint(np, endpoint); @@ -1421,9 +2066,9 @@ index 0000000..91223a0 + return 0; +} + -+static void max9286_max9271_setup_remote_endpoint(struct i2c_client *client) ++static void max9286_setup_remote_endpoint(struct i2c_client *client) +{ -+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client); ++ struct max9286_priv *priv = i2c_get_clientdata(client); + struct device_node *np = client->dev.of_node; + struct device_node *endpoint = NULL, *rendpoint = NULL; + int i; @@ -1454,10 +2099,10 @@ index 0000000..91223a0 + } +} + -+static int max9286_max9271_probe(struct i2c_client *client, ++static int max9286_probe(struct i2c_client *client, + const struct i2c_device_id *did) +{ -+ struct max9286_max9271_priv *priv; ++ struct max9286_priv *priv; + int err, i; + char supply_name[10]; + @@ -1471,7 +2116,7 @@ index 0000000..91223a0 + atomic_set(&priv->use_count, 0); + priv->csi2_outord = 0xff; + -+ err = max9286_max9271_parse_dt(client); ++ err = max9286_parse_dt(client); + if (err) + goto out; + @@ -1480,14 +2125,14 @@ index 0000000..91223a0 + priv->poc_supply[i] = devm_regulator_get_optional(&client->dev, supply_name); + } + -+ err = max9286_max9271_initialize(client); ++ err = max9286_initialize(client); + if (err < 0) + goto out; + -+ max9286_max9271_setup_remote_endpoint(client); ++ max9286_setup_remote_endpoint(client); + + for (i = 0; i < 4; i++) { -+ v4l2_subdev_init(&priv->sd[i], &max9286_max9271_subdev_ops); ++ v4l2_subdev_init(&priv->sd[i], &max9286_subdev_ops); + priv->sd[i].owner = client->dev.driver->owner; + priv->sd[i].dev = &client->dev; + priv->sd[i].grp_id = i; @@ -1506,9 +2151,9 @@ index 0000000..91223a0 + return err; +} + -+static int max9286_max9271_remove(struct i2c_client *client) ++static int max9286_remove(struct i2c_client *client) +{ -+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client); ++ struct max9286_priv *priv = i2c_get_clientdata(client); + int i; + + for (i = 0; i < 4; i++) { @@ -1519,38 +2164,38 @@ index 0000000..91223a0 + return 0; +} + -+static const struct of_device_id max9286_max9271_dt_ids[] = { -+ { .compatible = "maxim,max9286-max9271" }, ++static const struct of_device_id max9286_dt_ids[] = { ++ { .compatible = "maxim,max9286" }, + {}, +}; -+MODULE_DEVICE_TABLE(of, max9286_max9271_dt_ids); ++MODULE_DEVICE_TABLE(of, max9286_dt_ids); + -+static const struct i2c_device_id max9286_max9271_id[] = { -+ { "max9286_max9271", 0 }, ++static const struct i2c_device_id max9286_id[] = { ++ { "max9286", 0 }, + { } +}; -+MODULE_DEVICE_TABLE(i2c, max9286_max9271_id); ++MODULE_DEVICE_TABLE(i2c, max9286_id); + -+static struct i2c_driver max9286_max9271_i2c_driver = { ++static struct i2c_driver max9286_i2c_driver = { + .driver = { -+ .name = "max9286_max9271", -+ .of_match_table = of_match_ptr(max9286_max9271_dt_ids), ++ .name = "max9286", ++ .of_match_table = of_match_ptr(max9286_dt_ids), + }, -+ .probe = max9286_max9271_probe, -+ .remove = max9286_max9271_remove, -+ .id_table = max9286_max9271_id, ++ .probe = max9286_probe, ++ .remove = max9286_remove, ++ .id_table = max9286_id, +}; + -+module_i2c_driver(max9286_max9271_i2c_driver); ++module_i2c_driver(max9286_i2c_driver); + -+MODULE_DESCRIPTION("GMSL driver for MAX9286-MAX9271"); ++MODULE_DESCRIPTION("GMSL driver for MAX9286"); +MODULE_AUTHOR("Vladimir Barinov"); +MODULE_LICENSE("GPL"); -diff --git a/drivers/media/i2c/soc_camera/max9286_max9271.h b/drivers/media/i2c/soc_camera/max9286_max9271.h +diff --git a/drivers/media/i2c/soc_camera/max9286.h b/drivers/media/i2c/soc_camera/max9286.h new file mode 100644 index 0000000..6c2a9e0 --- /dev/null -+++ b/drivers/media/i2c/soc_camera/max9286_max9271.h ++++ b/drivers/media/i2c/soc_camera/max9286.h @@ -0,0 +1,244 @@ +/* + * MAXIM max9286-max9271 GMSL driver include file @@ -1798,7 +2443,7 @@ index 0000000..6c2a9e0 +#endif /* _MAX9286_MAX9271_H */ diff --git a/drivers/media/i2c/soc_camera/ov10635.c b/drivers/media/i2c/soc_camera/ov10635.c new file mode 100644 -index 0000000..6296647 +index 0000000..c8da1f4 --- /dev/null +++ b/drivers/media/i2c/soc_camera/ov10635.c @@ -0,0 +1,758 @@ @@ -1824,7 +2469,7 @@ index 0000000..6296647 +#include <media/v4l2-ctrls.h> +#include <media/v4l2-of.h> + -+#include "max9286_max9271.h" ++#include "max9286.h" +#include "ov10635.h" + +#define OV10635_I2C_ADDR 0x30 @@ -3767,10 +4412,10 @@ index 0000000..4c3515a +#endif diff --git a/drivers/media/i2c/soc_camera/ov106xx.c b/drivers/media/i2c/soc_camera/ov106xx.c new file mode 100644 -index 0000000..f2bb706 +index 0000000..4c797f9 --- /dev/null +++ b/drivers/media/i2c/soc_camera/ov106xx.c -@@ -0,0 +1,106 @@ +@@ -0,0 +1,117 @@ +/* + * OmniVision ov10635/ov490-ov10640/ov495-ov2775 sensor camera driver + * @@ -3786,12 +4431,14 @@ index 0000000..f2bb706 +#include "ov490_ov10640.c" +#include "ov495_ov2775.c" +#include "ar0132.c" ++#include "ap0101_ar014x.c" + +static enum { + ID_OV10635, + ID_OV490_OV10640, + ID_OV495_OV2775, + ID_AR0132, ++ ID_AP0101_AR014X, +} chip_id; + +static int ov106xx_probe(struct i2c_client *client, @@ -3824,6 +4471,12 @@ index 0000000..f2bb706 + goto out; + } + ++ ret = ap0101_probe(client, did); ++ if (!ret) { ++ chip_id = ID_AP0101_AR014X; ++ goto out; ++ } ++ + v4l_err(client, "failed to probe @ 0x%02x (%s)\n", + client->addr, client->adapter->name); +out: @@ -3845,6 +4498,9 @@ index 0000000..f2bb706 + case ID_AR0132: + ar0132_remove(client); + break; ++ case ID_AP0101_AR014X: ++ ap0101_remove(client); ++ break; + }; + + return 0; @@ -3874,15 +4530,15 @@ index 0000000..f2bb706 + +module_i2c_driver(ov106xx_i2c_driver); + -+MODULE_DESCRIPTION("SoC Camera driver for OV10635 or OV490/OV10640 or OV495/OV2775 or AR0132"); ++MODULE_DESCRIPTION("SoC Camera driver for OV10635 or OV490/OV10640 or OV495/OV2775 or AR0132 or AP0101/AR014X"); +MODULE_AUTHOR("Vladimir Barinov"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/i2c/soc_camera/ov490_ov10640.c b/drivers/media/i2c/soc_camera/ov490_ov10640.c new file mode 100644 -index 0000000..813c08e +index 0000000..be7098e --- /dev/null +++ b/drivers/media/i2c/soc_camera/ov490_ov10640.c -@@ -0,0 +1,1092 @@ +@@ -0,0 +1,1156 @@ +/* + * OmniVision ov490-ov10640 sensor camera driver + * @@ -3905,7 +4561,7 @@ index 0000000..813c08e +#include <media/v4l2-ctrls.h> +#include <media/v4l2-of.h> + -+#include "max9286_max9271.h" ++#include "max9286.h" +#include "ov490_ov10640.h" + +#define OV490_I2C_ADDR 0x24 @@ -3933,6 +4589,11 @@ index 0000000..813c08e + int exposure; + int gain; + int autogain; ++ int red; ++ int green_r; ++ int green_b; ++ int blue; ++ int awb; + int dvp_order; + /* serializers */ + int max9286_addr; @@ -4369,6 +5030,54 @@ index 0000000..813c08e + usleep_range(100, 150); /* wait 100 us */ + ret |= reg16_write(client, 0x00C0, 0xea); + break; ++ case V4L2_CID_AUTO_WHITE_BALANCE: ++ case V4L2_CID_RED_BALANCE: ++ case V4L2_CID_BLUE_BALANCE: ++ if (ctrl->id == V4L2_CID_AUTO_WHITE_BALANCE) ++ priv->awb = ctrl->val; ++ if (ctrl->id == V4L2_CID_RED_BALANCE) { ++ priv->red = ctrl->val; ++ priv->red <<= 8; ++ priv->green_r = priv->red / 2; ++ } ++ if (ctrl->id == V4L2_CID_BLUE_BALANCE) { ++ priv->blue = ctrl->val; ++ priv->blue <<= 8; ++ priv->green_b = priv->blue / 2; ++ } ++ ++ ret = reg16_write(client, 0xFFFD, 0x80); ++ ret |= reg16_write(client, 0xFFFE, 0x19); ++ usleep_range(100, 150); /* wait 100 us */ ++ ret |= reg16_write(client, 0x5000, !priv->awb); ++ ret |= reg16_write(client, 0x5001, priv->red >> 8); ++ ret |= reg16_write(client, 0x5002, priv->red & 0xff); ++ ret |= reg16_write(client, 0x5003, priv->green_r >> 8); ++ ret |= reg16_write(client, 0x5004, priv->green_r & 0xff); ++ ret |= reg16_write(client, 0x5005, priv->green_b >> 8); ++ ret |= reg16_write(client, 0x5006, priv->green_b & 0xff); ++ ret |= reg16_write(client, 0x5007, priv->blue >> 8); ++ ret |= reg16_write(client, 0x5008, priv->blue & 0xff); ++ ret |= reg16_write(client, 0x5009, priv->red >> 8); ++ ret |= reg16_write(client, 0x500a, priv->red & 0xff); ++ ret |= reg16_write(client, 0x500b, priv->green_r >> 8); ++ ret |= reg16_write(client, 0x500c, priv->green_r & 0xff); ++ ret |= reg16_write(client, 0x500d, priv->green_b >> 8); ++ ret |= reg16_write(client, 0x500e, priv->green_b & 0xff); ++ ret |= reg16_write(client, 0x500f, priv->blue >> 8); ++ ret |= reg16_write(client, 0x5010, priv->blue & 0xff); ++ ret |= reg16_write(client, 0x5011, priv->red >> 8); ++ ret |= reg16_write(client, 0x5012, priv->red & 0xff); ++ ret |= reg16_write(client, 0x5013, priv->green_r >> 8); ++ ret |= reg16_write(client, 0x5014, priv->green_r & 0xff); ++ ret |= reg16_write(client, 0x5015, priv->green_b >> 8); ++ ret |= reg16_write(client, 0x5016, priv->green_b & 0xff); ++ ret |= reg16_write(client, 0x5017, priv->blue >> 8); ++ ret |= reg16_write(client, 0x5018, priv->blue & 0xff); ++ ret |= reg16_write(client, 0xFFFE, 0x80); ++ usleep_range(100, 150); /* wait 100 us */ ++ ret |= reg16_write(client, 0x00C0, 0xeb); ++ break; + case V4L2_CID_HFLIP: +#if 1 + ret = reg16_write(client, 0xFFFD, 0x80); @@ -4855,6 +5564,11 @@ index 0000000..813c08e + priv->exposure = 0x100; + priv->gain = 0x100; + priv->autogain = 1; ++ priv->red = 0x400; ++ priv->blue = 0x400; ++ priv->green_r = priv->red / 2; ++ priv->green_b = priv->blue / 2; ++ priv->awb = 1; + v4l2_ctrl_handler_init(&priv->hdl, 4); + v4l2_ctrl_new_std(&priv->hdl, &ov490_ctrl_ops, + V4L2_CID_BRIGHTNESS, 0, 16, 1, 7); @@ -4875,6 +5589,12 @@ index 0000000..813c08e + v4l2_ctrl_new_std(&priv->hdl, &ov490_ctrl_ops, + V4L2_CID_EXPOSURE, 0, 0xffff, 1, priv->exposure); + v4l2_ctrl_new_std(&priv->hdl, &ov490_ctrl_ops, ++ V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, priv->autogain); ++ v4l2_ctrl_new_std(&priv->hdl, &ov490_ctrl_ops, ++ V4L2_CID_RED_BALANCE, 2, 0xf, 1, priv->red >> 8); ++ v4l2_ctrl_new_std(&priv->hdl, &ov490_ctrl_ops, ++ V4L2_CID_BLUE_BALANCE, 2, 0xf, 1, priv->blue >> 8); ++ v4l2_ctrl_new_std(&priv->hdl, &ov490_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 1); + v4l2_ctrl_new_std(&priv->hdl, &ov490_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); @@ -4977,10 +5697,10 @@ index 0000000..813c08e +#endif diff --git a/drivers/media/i2c/soc_camera/ov490_ov10640.h b/drivers/media/i2c/soc_camera/ov490_ov10640.h new file mode 100644 -index 0000000..8c9ecf1 +index 0000000..b22e93e --- /dev/null +++ b/drivers/media/i2c/soc_camera/ov490_ov10640.h -@@ -0,0 +1,93 @@ +@@ -0,0 +1,102 @@ +/* + * OmniVision ov490-ov10640 sensor camera wizard 1280x1080@30/UYVY/BT601/8bit + * @@ -4992,6 +5712,8 @@ index 0000000..8c9ecf1 + * option) any later version. + */ + ++//#define OV490_DISPLAY_PATTERN ++ +struct ov490_reg { + u16 reg; + u8 val; @@ -5073,6 +5795,13 @@ index 0000000..8c9ecf1 +{0x5001, 0x00}, +{0xfffe, 0x80}, +{0x00c0, 0xdc}, ++#ifdef OV490_DISPLAY_PATTERN ++{0xfffd, 0x80}, ++{0xfffe, 0x19}, ++{0x5000, 0x02}, ++{0xfffe, 0x80}, ++{0x00c0, 0xd6}, ++#endif +}; diff --git a/drivers/media/i2c/soc_camera/ov495_ov2775.c b/drivers/media/i2c/soc_camera/ov495_ov2775.c new file mode 100644 @@ -6206,10 +6935,10 @@ index 0000000..1672173 +MODULE_LICENSE("GPL"); diff --git a/drivers/media/i2c/soc_camera/ti964_ti9x3.c b/drivers/media/i2c/soc_camera/ti964_ti9x3.c new file mode 100644 -index 0000000..770d306 +index 0000000..bffd7c2 --- /dev/null +++ b/drivers/media/i2c/soc_camera/ti964_ti9x3.c -@@ -0,0 +1,399 @@ +@@ -0,0 +1,400 @@ +/* + * TI (ti964/ti960)-(ti913/ti953) FPDLinkIII driver + * @@ -6281,7 +7010,8 @@ index 0000000..770d306 + reg8_write(client, 0x1f, 0x00); /* CSI rate 1.5/1.6Gbps */ + break; + case 800: /* REFCLK = 25MHZ */ -+ reg8_write(client, 0x1f, 0x02); /* CSI rate 800Mbps */ ++ case 700: /* REFCLK = 22.5MHZ */ ++ reg8_write(client, 0x1f, 0x02); /* CSI rate 700/800Mbps */ + break; + case 400: /* REFCLK = 25MHZ */ + reg8_write(client, 0x1f, 0x03); /* CSI rate 400Mbps */ @@ -7255,10 +7985,24 @@ index 4d95da6..2ef27e8 100644 return 0; diff --git a/drivers/media/platform/soc_camera/rcar_vin.c b/drivers/media/platform/soc_camera/rcar_vin.c -index 74fb005..496a8bd 100644 +index 74fb005..ac75af6 100644 --- a/drivers/media/platform/soc_camera/rcar_vin.c +++ b/drivers/media/platform/soc_camera/rcar_vin.c -@@ -106,6 +106,7 @@ +@@ -95,17 +95,21 @@ + #define VNC8A_REG 0xF0 /* Video n Coefficient Set C8A Register */ + #define VNC8B_REG 0xF4 /* Video n Coefficient Set C8B Register */ + #define VNC8C_REG 0xF8 /* Video n Coefficient Set C8C Register */ ++#define VNLUTP_REG 0x100 /* Video n Lookup table pointer */ ++#define VNLUTD_REG 0x104 /* Video n Lookup table data register */ + + /* Register bit fields for R-Car VIN */ + /* Video n Main Control Register bits */ + #define VNMC_DPINE (1 << 27) + #define VNMC_SCLE (1 << 26) + #define VNMC_FOC (1 << 21) ++#define VNMC_LUTE (1 << 20) + #define VNMC_YCAL (1 << 19) + #define VNMC_INF_YUV8_BT656 (0 << 16) #define VNMC_INF_YUV8_BT601 (1 << 16) #define VNMC_INF_YUV10_BT656 (2 << 16) #define VNMC_INF_YUV10_BT601 (3 << 16) @@ -7266,7 +8010,7 @@ index 74fb005..496a8bd 100644 #define VNMC_INF_YUV16 (5 << 16) #define VNMC_INF_RGB888 (6 << 16) #define VNMC_INF_MASK (7 << 16) -@@ -138,6 +139,7 @@ +@@ -138,6 +142,7 @@ #define VNINTS_FOS (1 << 0) /* Video n Data Mode Register bits */ @@ -7274,7 +8018,18 @@ index 74fb005..496a8bd 100644 #define VNDMR_EXRGB (1 << 8) #define VNDMR_BPSM (1 << 4) #define VNDMR_DTMD_YCSEP (1 << 1) -@@ -408,6 +410,7 @@ enum csi2_fmt { +@@ -178,6 +183,10 @@ + #define RCAR_VIN_BT656 (1 << 3) + #define RCAR_VIN_CSI2 (1 << 4) + ++static int lut_reverse; ++module_param(lut_reverse, int, 0644); ++MODULE_PARM_DESC(lut_reverse, " Use LUT for data order reverse (only 8-bit data allowed)*/"); ++ + static int ifmd0_reg_match[VNCSI_IFMD_SEL_NUMBER]; + static int ifmd4_reg_match[VNCSI_IFMD_SEL_NUMBER]; + static int ifmd0_init = true; +@@ -408,6 +417,7 @@ enum csi2_fmt { RCAR_CSI_FMT_NONE = -1, RCAR_CSI_RGB888, RCAR_CSI_YCBCR422, @@ -7282,11 +8037,12 @@ index 74fb005..496a8bd 100644 }; struct vin_coeff { -@@ -773,10 +776,13 @@ struct rcar_vin_priv { +@@ -773,10 +783,14 @@ struct rcar_vin_priv { enum csi2_fmt csi_fmt; enum virtual_ch vc; bool csi_sync; + bool deser_sync; ++ int lut_updated; struct rcar_vin_async_client *async_client; /* Asynchronous CSI2 linking */ @@ -7296,7 +8052,16 @@ index 74fb005..496a8bd 100644 /* Synchronous probing compatibility */ struct platform_device *csi2_pdev; -@@ -989,6 +995,10 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv) +@@ -939,6 +953,8 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv) + struct rcar_vin_cam *cam = icd->host_priv; + u32 vnmc, dmr, interrupts; + bool progressive = false, output_is_yuv = false, input_is_yuv = false; ++ int i; ++ u32 lutd; + + switch (priv->field) { + case V4L2_FIELD_TOP: +@@ -989,6 +1005,10 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv) VNMC_INF_YUV10_BT656 : VNMC_INF_YUV10_BT601; input_is_yuv = true; break; @@ -7307,7 +8072,7 @@ index 74fb005..496a8bd 100644 default: break; } -@@ -1021,6 +1031,10 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv) +@@ -1021,6 +1041,10 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv) dmr = 0; output_is_yuv = true; break; @@ -7318,7 +8083,7 @@ index 74fb005..496a8bd 100644 case V4L2_PIX_FMT_ARGB555: dmr = VNDMR_DTMD_ARGB; break; -@@ -1043,6 +1057,10 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv) +@@ -1043,6 +1067,10 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv) dmr = VNDMR_EXRGB | VNDMR_DTMD_ARGB; break; @@ -7329,7 +8094,7 @@ index 74fb005..496a8bd 100644 default: goto e_format; } -@@ -1061,7 +1079,9 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv) +@@ -1061,7 +1089,9 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv) else vnmc |= VNMC_DPINE; @@ -7340,7 +8105,41 @@ index 74fb005..496a8bd 100644 && is_scaling(cam)) vnmc |= VNMC_SCLE; } -@@ -1211,6 +1231,10 @@ static void rcar_vin_videobuf_queue(struct vb2_buffer *vb) +@@ -1073,6 +1103,33 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv) + if (vin_debug) + interrupts |= VNIE_FOE; + ++ if (lut_reverse && !priv->lut_updated) { ++ iowrite32(0, priv->base + VNLUTP_REG); ++ ++ for (i = 0; i < 1024; i++) { ++ /* reverse MSB 8bits image at 10bit LUT address */ ++ lutd = ((i >> 2) & BIT(0) ? BIT(7) : 0); ++ lutd |= ((i >> 2) & BIT(1) ? BIT(6) : 0); ++ lutd |= ((i >> 2) & BIT(2) ? BIT(5) : 0); ++ lutd |= ((i >> 2) & BIT(3) ? BIT(4) : 0); ++ lutd |= ((i >> 2) & BIT(4) ? BIT(3) : 0); ++ lutd |= ((i >> 2) & BIT(5) ? BIT(2) : 0); ++ lutd |= ((i >> 2) & BIT(6) ? BIT(1) : 0); ++ lutd |= ((i >> 2) & BIT(7) ? BIT(0) : 0); ++#if 0 ++ /* strait (no any density convertion, used for testing) */ ++ lutd = i >> 2; ++#endif ++ lutd = (lutd << 16) | (lutd << 8) | lutd; ++ iowrite32(lutd, priv->base + VNLUTD_REG); ++ } ++ /* update LUT table once */ ++ priv->lut_updated = 1; ++ } ++ ++ if (lut_reverse) ++ vnmc |= VNMC_LUTE; ++ + /* ack interrupts */ + iowrite32(interrupts, priv->base + VNINTS_REG); + /* enable interrupts */ +@@ -1211,6 +1268,10 @@ static void rcar_vin_videobuf_queue(struct vb2_buffer *vb) */ static void rcar_vin_wait_stop_streaming(struct rcar_vin_priv *priv) { @@ -7351,14 +8150,14 @@ index 74fb005..496a8bd 100644 while (priv->state != STOPPED) { /* issue stop if running */ if (priv->state == RUNNING) -@@ -1361,6 +1385,31 @@ static struct v4l2_subdev *find_csi2(struct rcar_vin_priv *pcdev) +@@ -1361,6 +1422,31 @@ static struct v4l2_subdev *find_csi2(struct rcar_vin_priv *pcdev) return NULL; } +static struct v4l2_subdev *find_deser(struct rcar_vin_priv *pcdev) +{ + struct v4l2_subdev *sd; -+ char name[] = "max9286_max9271"; ++ char name[] = "max9286"; + char name2[] = "ti964_ti9x3"; + char name3[] = "ti954_ti9x3"; + @@ -7383,7 +8182,7 @@ index 74fb005..496a8bd 100644 static int rcar_vin_add_device(struct soc_camera_device *icd) { struct soc_camera_host *ici = to_soc_camera_host(icd->parent); -@@ -1375,7 +1424,8 @@ static int rcar_vin_add_device(struct soc_camera_device *icd) +@@ -1375,7 +1461,8 @@ static int rcar_vin_add_device(struct soc_camera_device *icd) if (priv->chip == RCAR_H3 || priv->chip == RCAR_M3 || priv->chip == RCAR_V3M) { struct v4l2_subdev *csi2_sd = find_csi2(priv); @@ -7393,7 +8192,7 @@ index 74fb005..496a8bd 100644 if (csi2_sd) { csi2_sd->grp_id = soc_camera_grp_id(icd); -@@ -1390,6 +1440,18 @@ static int rcar_vin_add_device(struct soc_camera_device *icd) +@@ -1390,6 +1477,18 @@ static int rcar_vin_add_device(struct soc_camera_device *icd) if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV) return ret; } @@ -7412,7 +8211,7 @@ index 74fb005..496a8bd 100644 /* * -ENODEV is special: * either csi2_sd == NULL or the CSI-2 driver -@@ -1417,6 +1479,7 @@ static void rcar_vin_remove_device(struct soc_camera_device *icd) +@@ -1417,6 +1516,7 @@ static void rcar_vin_remove_device(struct soc_camera_device *icd) struct rcar_vin_priv *priv = ici->priv; struct vb2_v4l2_buffer *vbuf; struct v4l2_subdev *csi2_sd = find_csi2(priv); @@ -7420,7 +8219,7 @@ index 74fb005..496a8bd 100644 int i; /* disable capture, disable interrupts */ -@@ -1443,6 +1506,8 @@ static void rcar_vin_remove_device(struct soc_camera_device *icd) +@@ -1443,6 +1543,8 @@ static void rcar_vin_remove_device(struct soc_camera_device *icd) if ((csi2_sd) && (priv->csi_sync)) v4l2_subdev_call(csi2_sd, core, s_power, 0); @@ -7429,7 +8228,7 @@ index 74fb005..496a8bd 100644 dev_dbg(icd->parent, "R-Car VIN driver detached from camera %d\n", icd->devnum); -@@ -1621,13 +1686,19 @@ static int rcar_vin_set_rect(struct soc_camera_device *icd) +@@ -1621,13 +1723,19 @@ static int rcar_vin_set_rect(struct soc_camera_device *icd) if (priv->chip == RCAR_H3 || priv->chip == RCAR_M3 || priv->chip == RCAR_V3M) { @@ -7451,7 +8250,7 @@ index 74fb005..496a8bd 100644 (icd->current_fmt->host_fmt->fourcc == V4L2_PIX_FMT_NV16) || (icd->current_fmt->host_fmt->fourcc == V4L2_PIX_FMT_NV12)) iowrite32(ALIGN(cam->out_width, 0x20), -@@ -1868,6 +1939,14 @@ static bool rcar_vin_packing_supported(const struct soc_mbus_pixelfmt *fmt) +@@ -1868,6 +1976,14 @@ static bool rcar_vin_packing_supported(const struct soc_mbus_pixelfmt *fmt) .layout = SOC_MBUS_LAYOUT_PACKED, }, { @@ -7466,7 +8265,7 @@ index 74fb005..496a8bd 100644 .fourcc = V4L2_PIX_FMT_RGB565, .name = "RGB565", .bits_per_sample = 16, -@@ -1899,6 +1978,22 @@ static bool rcar_vin_packing_supported(const struct soc_mbus_pixelfmt *fmt) +@@ -1899,6 +2015,22 @@ static bool rcar_vin_packing_supported(const struct soc_mbus_pixelfmt *fmt) .order = SOC_MBUS_ORDER_LE, .layout = SOC_MBUS_LAYOUT_PACKED, }, @@ -7489,7 +8288,7 @@ index 74fb005..496a8bd 100644 }; static int rcar_vin_get_formats(struct soc_camera_device *icd, unsigned int idx, -@@ -2012,6 +2107,8 @@ static int rcar_vin_get_formats(struct soc_camera_device *icd, unsigned int idx, +@@ -2012,6 +2144,8 @@ static int rcar_vin_get_formats(struct soc_camera_device *icd, unsigned int idx, case MEDIA_BUS_FMT_YUYV8_2X8: case MEDIA_BUS_FMT_YUYV10_2X10: case MEDIA_BUS_FMT_RGB888_1X24: @@ -7498,7 +8297,7 @@ index 74fb005..496a8bd 100644 if (cam->extra_fmt) break; -@@ -2218,12 +2315,15 @@ static int rcar_vin_set_fmt(struct soc_camera_device *icd, +@@ -2218,12 +2352,15 @@ static int rcar_vin_set_fmt(struct soc_camera_device *icd, case V4L2_PIX_FMT_ABGR32: case V4L2_PIX_FMT_UYVY: case V4L2_PIX_FMT_YUYV: @@ -7514,7 +8313,7 @@ index 74fb005..496a8bd 100644 default: can_scale = false; break; -@@ -2316,7 +2416,8 @@ static int rcar_vin_try_fmt(struct soc_camera_device *icd, +@@ -2316,7 +2453,8 @@ static int rcar_vin_try_fmt(struct soc_camera_device *icd, /* odd number clipping by pixel post clip processing, */ /* it is outputted to a memory per even pixels. */ if ((pixfmt == V4L2_PIX_FMT_NV16) || (pixfmt == V4L2_PIX_FMT_NV12) || @@ -7524,7 +8323,7 @@ index 74fb005..496a8bd 100644 v4l_bound_align_image(&pix->width, 5, priv->max_width, 1, &pix->height, 2, priv->max_height, 0, 0); else -@@ -2486,6 +2587,19 @@ static int rcar_vin_cropcap(struct soc_camera_device *icd, +@@ -2486,6 +2624,19 @@ static int rcar_vin_cropcap(struct soc_camera_device *icd, } #endif @@ -7544,7 +8343,7 @@ index 74fb005..496a8bd 100644 static struct soc_camera_host_ops rcar_vin_host_ops = { .owner = THIS_MODULE, .add = rcar_vin_add_device, -@@ -2504,6 +2618,7 @@ static int rcar_vin_cropcap(struct soc_camera_device *icd, +@@ -2504,6 +2655,7 @@ static int rcar_vin_cropcap(struct soc_camera_device *icd, .get_selection = rcar_vin_get_selection, .cropcap = rcar_vin_cropcap, #endif @@ -7552,7 +8351,7 @@ index 74fb005..496a8bd 100644 }; #ifdef CONFIG_OF -@@ -2524,7 +2639,7 @@ static int rcar_vin_cropcap(struct soc_camera_device *icd, +@@ -2524,7 +2676,7 @@ static int rcar_vin_cropcap(struct soc_camera_device *icd, MODULE_DEVICE_TABLE(of, rcar_vin_of_table); #endif @@ -7561,7 +8360,7 @@ index 74fb005..496a8bd 100644 static DECLARE_BITMAP(device_map, MAP_MAX_NUM); static DEFINE_MUTEX(list_lock); -@@ -2714,7 +2829,11 @@ static int rcar_vin_probe(struct platform_device *pdev) +@@ -2714,7 +2866,11 @@ static int rcar_vin_probe(struct platform_device *pdev) const char *str; unsigned int i; struct device_node *epn = NULL, *ren = NULL; @@ -7573,7 +8372,7 @@ index 74fb005..496a8bd 100644 match = of_match_device(of_match_ptr(rcar_vin_of_table), &pdev->dev); -@@ -2741,13 +2860,27 @@ static int rcar_vin_probe(struct platform_device *pdev) +@@ -2741,13 +2897,27 @@ static int rcar_vin_probe(struct platform_device *pdev) dev_dbg(&pdev->dev, "node name:%s\n", of_node_full_name(ren->parent)); @@ -7584,7 +8383,7 @@ index 74fb005..496a8bd 100644 + } - of_node_put(ren); -+ if (strcmp(ren->parent->name, "max9286-max9271") == 0) { ++ if (strcmp(ren->parent->name, "max9286") == 0) { + max9286_ren = of_parse_phandle(epn, "remote-endpoint", 0); + max9286_use = true; + } @@ -7605,7 +8404,7 @@ index 74fb005..496a8bd 100644 } ret = v4l2_of_parse_endpoint(np, &ep); -@@ -2799,6 +2932,7 @@ static int rcar_vin_probe(struct platform_device *pdev) +@@ -2799,6 +2969,7 @@ static int rcar_vin_probe(struct platform_device *pdev) priv->ici.drv_name = dev_name(&pdev->dev); priv->ici.ops = &rcar_vin_host_ops; priv->csi_sync = false; @@ -7613,7 +8412,7 @@ index 74fb005..496a8bd 100644 priv->pdata_flags = pdata_flags; if (!match) { -@@ -2983,7 +3117,25 @@ static int rcar_vin_probe(struct platform_device *pdev) +@@ -2983,7 +3154,25 @@ static int rcar_vin_probe(struct platform_device *pdev) goto cleanup; if (csi_use) { diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch index 9db9056..5387ae8 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch @@ -18,45 +18,51 @@ Kingfisher board on R8A7797 SoC Videobox board on R8A7795 ES1.x SoC Videobox board on R8A7795 SoC Eagle board on R8A7797 SoC +Eagle Function board on R8A7797 SoC V3MSK board on R8A7797 SoC V3MSK.View board on R8A7797 SoC Videobox Mini board on R8A7795 ES1.x SoC Videobox Mini board on R8A7795 SoC Videobox Mini board on R8A7797 SoC +Videobox2 board on R8A7795 ES1.x SoC +Videobox2 board on R8A7795 SoC Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> --- - arch/arm64/boot/dts/renesas/Makefile | 19 + + arch/arm64/boot/dts/renesas/Makefile | 20 + arch/arm64/boot/dts/renesas/legacy/Makefile | 8 + .../renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts | 1710 +++++++++++++++++++ .../renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts | 441 +++++ .../dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts | 1724 +++++++++++++++++++ - .../dts/renesas/legacy/r8a7795-h3ulcb-kf-v1.dts | 465 ++++++ - .../dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts | 1214 ++++++++++++++ - .../dts/renesas/legacy/r8a7796-m3ulcb-kf-v1.dts | 465 ++++++ + .../dts/renesas/legacy/r8a7795-h3ulcb-kf-v1.dts | 465 +++++ + .../dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts | 1214 +++++++++++++ + .../dts/renesas/legacy/r8a7796-m3ulcb-kf-v1.dts | 465 +++++ .../dts/renesas/legacy/r8a7797-v3msk-kf-v0.dts | 82 + .../boot/dts/renesas/legacy/ulcb-kf-cmos.dtsi | 75 + .../arm64/boot/dts/renesas/legacy/ulcb-kf-rpi.dtsi | 77 + .../dts/renesas/r8a7795-es1-h3ulcb-had-alfa.dts | 22 + .../dts/renesas/r8a7795-es1-h3ulcb-had-beta.dts | 23 + - .../boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi | 225 +++ + .../boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi | 221 +++ .../boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts | 39 + .../boot/dts/renesas/r8a7795-es1-h3ulcb-vb.dts | 69 + + .../boot/dts/renesas/r8a7795-es1-h3ulcb-vb2.dts | 77 + .../boot/dts/renesas/r8a7795-es1-h3ulcb-vbm.dts | 26 + - .../boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts | 546 +++++++ - .../dts/renesas/r8a7795-es1-salvator-x-view.dts | 552 +++++++ + .../boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts | 546 ++++++ + .../dts/renesas/r8a7795-es1-salvator-x-view.dts | 552 ++++++ .../boot/dts/renesas/r8a7795-h3ulcb-had-alfa.dts | 22 + .../boot/dts/renesas/r8a7795-h3ulcb-had-beta.dts | 23 + - .../arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi | 219 +++ + .../arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi | 215 +++ arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts | 39 + arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts | 68 + + arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb2.dts | 68 + arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vbm.dts | 26 + - .../arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts | 546 +++++++ - .../boot/dts/renesas/r8a7795-salvator-x-view.dts | 552 +++++++ + .../arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts | 546 ++++++ + .../boot/dts/renesas/r8a7795-salvator-x-view.dts | 552 ++++++ arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts | 40 + .../arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts | 287 ++++ .../boot/dts/renesas/r8a7796-salvator-x-view.dts | 318 ++++ - arch/arm64/boot/dts/renesas/r8a7797-eagle.dts | 560 +++++++ + .../boot/dts/renesas/r8a7797-eagle-function.dts | 62 + + arch/arm64/boot/dts/renesas/r8a7797-eagle.dts | 575 +++++++ arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts | 578 +++++++ arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts | 518 ++++++ arch/arm64/boot/dts/renesas/r8a7797-v3msk-view.dts | 298 ++++ @@ -64,11 +70,12 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi | 545 ++++++ arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi | 30 + arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi | 46 + - arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 1541 +++++++++++++++++ + arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 1542 +++++++++++++++++ arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi | 515 ++++++ - arch/arm64/boot/dts/renesas/ulcb-vb.dtsi | 1726 ++++++++++++++++++++ + arch/arm64/boot/dts/renesas/ulcb-vb.dtsi | 1726 +++++++++++++++++++ + arch/arm64/boot/dts/renesas/ulcb-vb2.dtsi | 1792 ++++++++++++++++++++ arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi | 578 +++++++ - 42 files changed, 17171 insertions(+) + 46 files changed, 19179 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/legacy/Makefile create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts @@ -84,6 +91,7 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb2.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vbm.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts @@ -92,12 +100,14 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb2.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vbm.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts + create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-eagle-function.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-eagle.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts @@ -109,13 +119,14 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vb.dtsi + create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vb2.dtsi create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile -index f9c71df..af88350 100644 +index f9c71df..1c63893 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile -@@ -6,5 +6,24 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb +@@ -6,5 +6,25 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs.dtb @@ -128,8 +139,9 @@ index f9c71df..af88350 100644 +dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-had-alfa.dtb r8a7795-h3ulcb-had-beta.dtb r8a7795-es1-h3ulcb-had-alfa.dtb r8a7795-es1-h3ulcb-had-beta.dtb +dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb r8a7795-es1-h3ulcb-kf.dtb +dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-vb.dtb r8a7795-es1-h3ulcb-vb.dtb ++dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-vb2.dtb r8a7795-es1-h3ulcb-vb2.dtb +dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-vbm.dtb r8a7795-es1-h3ulcb-vbm.dtb -+dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-eagle.dtb ++dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-eagle.dtb r8a7797-eagle-function.dtb +dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk.dtb +dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-view.dtb +dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-kf.dtb @@ -156,7 +168,7 @@ index 0000000..7f25079 +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts new file mode 100644 -index 0000000..2fee788 +index 0000000..fe07e22 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts @@ -0,0 +1,1710 @@ @@ -895,8 +907,8 @@ index 0000000..2fee788 + }; + + /* MAX9286 @ 0x2c */ -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@0 { ++ compatible = "maxim,max9286"; + reg = <0x2c>; + maxim,sensor_delay = <350>; + maxim,links = <4>; @@ -1104,8 +1116,8 @@ index 0000000..2fee788 + }; + + /* MAX9286 @ 0x2c */ -+ max9286-max9271@1 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@1 { ++ compatible = "maxim,max9286"; + reg = <0x2c>; + maxim,sensor_delay = <350>; + maxim,links = <4>; @@ -2319,7 +2331,7 @@ index 0000000..ac6a12b +}; diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts new file mode 100644 -index 0000000..78c766b +index 0000000..c19bc58 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts @@ -0,0 +1,1724 @@ @@ -3058,8 +3070,8 @@ index 0000000..78c766b + }; + + /* MAX9286 @ 0x2c */ -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@0 { ++ compatible = "maxim,max9286"; + reg = <0x2c>; + maxim,sensor_delay = <350>; + maxim,links = <4>; @@ -3267,8 +3279,8 @@ index 0000000..78c766b + }; + + /* MAX9286 @ 0x2c */ -+ max9286-max9271@1 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@1 { ++ compatible = "maxim,max9286"; + reg = <0x2c>; + maxim,sensor_delay = <350>; + maxim,links = <4>; @@ -4520,7 +4532,7 @@ index 0000000..14b6f52 +}; diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts new file mode 100644 -index 0000000..ffa1879 +index 0000000..8e7de0f --- /dev/null +++ b/arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts @@ -0,0 +1,1214 @@ @@ -5259,8 +5271,8 @@ index 0000000..ffa1879 + }; + + /* MAX9286 @ 0x2c */ -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@0 { ++ compatible = "maxim,max9286"; + reg = <0x2c>; + maxim,sensor_delay = <350>; + maxim,links = <4>; @@ -6520,10 +6532,10 @@ index 0000000..2f8b274 +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi new file mode 100644 -index 0000000..d50ff7a +index 0000000..dd399f4 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi -@@ -0,0 +1,225 @@ +@@ -0,0 +1,221 @@ +/* + * Device Tree Source for the H3ULCB.HAD board on r8a7795 ES1.x + * @@ -6546,15 +6558,11 @@ index 0000000..d50ff7a + model = "Renesas H3ULCB.HAD board based on r8a7795"; + + aliases { -+ serial1 = &scif1; ++ serial0 = &scif1; + spi1 = &spi0_gpio; + spi2 = &spi1_gpio; + }; + -+ chosen { -+ stdout-path = "serial1:115200n8"; -+ }; -+ + spi0_gpio: spi_gpio@0 { + compatible = "spi-gpio"; + num-chipselects = <1>; @@ -6869,6 +6877,89 @@ index 0000000..549a717 +&hsusb { + status = "okay"; +}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb2.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb2.dts +new file mode 100644 +index 0000000..1a8db57 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb2.dts +@@ -0,0 +1,77 @@ ++/* ++ * Device Tree Source for the H3ULCB Videobox board V2 on r8a7795 ++ * ++ * Copyright (C) 2018 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-es1-h3ulcb.dts" ++#include "ulcb-vb2.dtsi" ++ ++/ { ++ model = "Renesas H3ULCB Videobox board based on r8a7795"; ++ ++ hdmi1-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con: endpoint { ++ remote-endpoint = <&rcar_dw_hdmi1_out>; ++ }; ++ }; ++ }; ++}; ++ ++&pfc { ++ usb31_pins: usb31 { ++ groups = "usb31"; ++ function = "usb31"; ++ }; ++}; ++ ++&du { ++ ports { ++ port@2 { ++ endpoint { ++ remote-endpoint = <&rcar_dw_hdmi1_in>; ++ }; ++ }; ++ port@3 { ++ endpoint { ++ remote-endpoint = <&lvds_enc_in>; ++ }; ++ }; ++ }; ++}; ++ ++&hdmi1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ rcar_dw_hdmi1_in: endpoint { ++ remote-endpoint = <&du_out_hdmi1>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ rcar_dw_hdmi1_out: endpoint { ++ remote-endpoint = <&hdmi1_con>; ++ }; ++ }; ++ }; ++}; ++ ++&xhci1 { ++ status = "okay"; ++ pinctrl-0 = <&usb31_pins>; ++ pinctrl-names = "default"; ++}; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vbm.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vbm.dts new file mode 100644 index 0000000..323722c @@ -6903,7 +6994,7 @@ index 0000000..323722c +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts new file mode 100644 -index 0000000..de56fa4 +index 0000000..6eb7cac --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts @@ -0,0 +1,546 @@ @@ -7069,8 +7160,8 @@ index 0000000..de56fa4 + }; + }; + -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@0 { ++ compatible = "maxim,max9286"; + reg = <0x4c>; + gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + maxim,sensor_delay = <0>; @@ -7111,8 +7202,8 @@ index 0000000..de56fa4 + }; + }; + -+ max9286-max9271@1 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@1 { ++ compatible = "maxim,max9286"; + reg = <0x6c>; + gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; + maxim,sensor_delay = <0>; @@ -7455,7 +7546,7 @@ index 0000000..de56fa4 +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts new file mode 100644 -index 0000000..3f3d66a +index 0000000..d4caf46 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts @@ -0,0 +1,552 @@ @@ -7636,8 +7727,8 @@ index 0000000..3f3d66a + }; + }; + -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@0 { ++ compatible = "maxim,max9286"; + reg = <0x4c>; + gpios = <&gpio6 30 GPIO_ACTIVE_LOW>; + maxim,sensor_delay = <0>; @@ -7678,8 +7769,8 @@ index 0000000..3f3d66a + }; + }; + -+ max9286-max9271@1 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@1 { ++ compatible = "maxim,max9286"; + reg = <0x6c>; + maxim,sensor_delay = <0>; + maxim,links = <4>; @@ -8070,10 +8161,10 @@ index 0000000..805067e +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi new file mode 100644 -index 0000000..4a00426 +index 0000000..d1bbea4 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi -@@ -0,0 +1,219 @@ +@@ -0,0 +1,215 @@ +/* + * Device Tree Source for the H3ULCB.HAD board on r8a7795 + * @@ -8096,15 +8187,11 @@ index 0000000..4a00426 + model = "Renesas H3ULCB.HAD board based on r8a7795"; + + aliases { -+ serial1 = &scif1; ++ serial0 = &scif1; + spi1 = &spi0_gpio; + spi2 = &spi1_gpio; + }; + -+ chosen { -+ stdout-path = "serial1:115200n8"; -+ }; -+ + spi0_gpio: spi_gpio@0 { + compatible = "spi-gpio"; + num-chipselects = <1>; @@ -8412,6 +8499,80 @@ index 0000000..330bba2 +&hsusb0 { + status = "okay"; +}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb2.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb2.dts +new file mode 100644 +index 0000000..e862d3e +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb2.dts +@@ -0,0 +1,68 @@ ++/* ++ * Device Tree Source for the H3ULCB Videobox board V2 on r8a7795 ++ * ++ * Copyright (C) 2018 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7795-h3ulcb.dts" ++#include "ulcb-vb2.dtsi" ++ ++/ { ++ model = "Renesas H3ULCB Videobox board based on r8a7795"; ++ ++ hdmi1-out { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con: endpoint { ++ remote-endpoint = <&rcar_dw_hdmi1_out>; ++ }; ++ }; ++ }; ++}; ++ ++&du { ++ ports { ++ port@2 { ++ endpoint { ++ remote-endpoint = <&rcar_dw_hdmi1_in>; ++ }; ++ }; ++ port@3 { ++ endpoint { ++ remote-endpoint = <&lvds_enc_in>; ++ }; ++ }; ++ }; ++}; ++ ++&hdmi1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ rcar_dw_hdmi1_in: endpoint { ++ remote-endpoint = <&du_out_hdmi1>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ rcar_dw_hdmi1_out: endpoint { ++ remote-endpoint = <&hdmi1_con>; ++ }; ++ }; ++ }; ++}; ++ ++&hsusb0 { ++ status = "okay"; ++}; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vbm.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vbm.dts new file mode 100644 index 0000000..87f1889 @@ -8446,7 +8607,7 @@ index 0000000..87f1889 +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts new file mode 100644 -index 0000000..2c24b85 +index 0000000..8541518 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts @@ -0,0 +1,546 @@ @@ -8612,8 +8773,8 @@ index 0000000..2c24b85 + }; + }; + -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@0 { ++ compatible = "maxim,max9286"; + reg = <0x4c>; + gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + maxim,sensor_delay = <0>; @@ -8654,8 +8815,8 @@ index 0000000..2c24b85 + }; + }; + -+ max9286-max9271@1 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@1 { ++ compatible = "maxim,max9286"; + reg = <0x6c>; + gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; + maxim,sensor_delay = <0>; @@ -8998,7 +9159,7 @@ index 0000000..2c24b85 +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts new file mode 100644 -index 0000000..fb12a39f3 +index 0000000..14539ea --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts @@ -0,0 +1,552 @@ @@ -9179,8 +9340,8 @@ index 0000000..fb12a39f3 + }; + }; + -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@0 { ++ compatible = "maxim,max9286"; + reg = <0x4c>; + gpios = <&gpio6 30 GPIO_ACTIVE_LOW>; + maxim,sensor_delay = <0>; @@ -9221,8 +9382,8 @@ index 0000000..fb12a39f3 + }; + }; + -+ max9286-max9271@1 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@1 { ++ compatible = "maxim,max9286"; + reg = <0x6c>; + maxim,sensor_delay = <0>; + maxim,links = <4>; @@ -9602,7 +9763,7 @@ index 0000000..a409402 +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts new file mode 100644 -index 0000000..1ac0041 +index 0000000..ea7f378 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts @@ -0,0 +1,287 @@ @@ -9696,8 +9857,8 @@ index 0000000..1ac0041 + }; + }; + -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@0 { ++ compatible = "maxim,max9286"; + reg = <0x4c>; + gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + maxim,sensor_delay = <0>; @@ -9895,7 +10056,7 @@ index 0000000..1ac0041 +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts new file mode 100644 -index 0000000..cc6866c +index 0000000..319120f --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts @@ -0,0 +1,318 @@ @@ -10004,8 +10165,8 @@ index 0000000..cc6866c + }; + }; + -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@0 { ++ compatible = "maxim,max9286"; + reg = <0x4c>; + gpios = <&gpio6 30 GPIO_ACTIVE_LOW>; + maxim,sensor_delay = <0>; @@ -10217,12 +10378,80 @@ index 0000000..cc6866c + pinctrl-names = "default"; + status = "okay"; +}; +diff --git a/arch/arm64/boot/dts/renesas/r8a7797-eagle-function.dts b/arch/arm64/boot/dts/renesas/r8a7797-eagle-function.dts +new file mode 100644 +index 0000000..82d6513 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/r8a7797-eagle-function.dts +@@ -0,0 +1,62 @@ ++/* ++ * Device Tree Source for the Eagle Function board on r8a7797 ++ * ++ * Copyright (C) 2017 Renesas Electronics Corp. ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include "r8a7797-eagle.dts" ++ ++/ { ++ model = "Renesas Eagle Function board based on r8a7797"; ++ ++ vcc_3v3: regulator0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-VCC3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ vcc_vddq_vin0: regulator1 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC-VDDQ-VIN0"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++&pfc { ++ sdhi2_pins_1v8: sdhi2_1v8 { ++ groups = "mmc_data8", "mmc_ctrl"; ++ function = "mmc"; ++ power-source = <1800>; ++ }; ++ ++ sdhi2_pins_3v3: sdhi2_3v3 { ++ groups = "mmc_data8", "mmc_ctrl"; ++ function = "mmc"; ++ power-source = <3300>; ++ }; ++}; ++ ++&sdhi2 { ++ /* used for on-board eMMC */ ++ pinctrl-0 = <&sdhi2_pins_3v3>; ++ pinctrl-1 = <&sdhi2_pins_1v8>; ++ pinctrl-names = "default", "state_uhs"; ++ ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_vddq_vin0>; ++ mmc-hs200-1_8v; ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; diff --git a/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts b/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts new file mode 100644 -index 0000000..3fb3bf1 +index 0000000..ce7a88e --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts -@@ -0,0 +1,560 @@ +@@ -0,0 +1,575 @@ +/* + * Device Tree Source for the Eagle board + * @@ -10394,6 +10623,11 @@ index 0000000..3fb3bf1 + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; ++ + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; @@ -10563,8 +10797,8 @@ index 0000000..3fb3bf1 + }; + }; + -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@0 { ++ compatible = "maxim,max9286"; + reg = <0x48>; + gpios = <&gpio_ext 0 GPIO_ACTIVE_LOW>; /* CSI0 DE_PDn */ + maxim,gpio0 = <0>; @@ -10750,6 +10984,16 @@ index 0000000..3fb3bf1 + }; +}; + ++&canfd { ++ pinctrl-0 = <&canfd0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ channel0 { ++ status = "okay"; ++ }; ++}; ++ +&csi2_40 { + status = "okay"; + @@ -10785,7 +11029,7 @@ index 0000000..3fb3bf1 +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts new file mode 100644 -index 0000000..979cebe +index 0000000..b92fe83 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts @@ -0,0 +1,578 @@ @@ -11041,8 +11285,8 @@ index 0000000..979cebe + }; + + /* MAX9286 @ 0x2c */ -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@0 { ++ compatible = "maxim,max9286"; + reg = <0x2c>; + maxim,sensor_delay = <350>; + maxim,links = <4>; @@ -11369,7 +11613,7 @@ index 0000000..979cebe +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts new file mode 100644 -index 0000000..4292b7b +index 0000000..26f8c70 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts @@ -0,0 +1,518 @@ @@ -11580,8 +11824,8 @@ index 0000000..4292b7b + }; + }; + -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@0 { ++ compatible = "maxim,max9286"; + reg = <0x2c>; + maxim,sensor_delay = <350>; + maxim,links = <4>; @@ -11661,7 +11905,7 @@ index 0000000..4292b7b + }; + port@1 { + ti964_csi0ep0: endpoint { -+ csi-rate = <1450>; ++ csi-rate = <700>; + remote-endpoint = <&csi2_40_ep>; + }; + }; @@ -11893,7 +12137,7 @@ index 0000000..4292b7b +}; diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-view.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-view.dts new file mode 100644 -index 0000000..573e2bc +index 0000000..6f82385 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-view.dts @@ -0,0 +1,298 @@ @@ -12026,8 +12270,8 @@ index 0000000..573e2bc + }; + }; + -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@0 { ++ compatible = "maxim,max9286"; + reg = <0x6c>; + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + maxim,sensor_delay = <0>; @@ -12517,7 +12761,7 @@ index 0000000..91d10c5 +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi new file mode 100644 -index 0000000..589a774 +index 0000000..b469ca6 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi @@ -0,0 +1,545 @@ @@ -12747,8 +12991,8 @@ index 0000000..589a774 + }; + + /* MAX9286 @ 0x2c */ -+ max9286-max9271@1 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@1 { ++ compatible = "maxim,max9286"; + reg = <0x2c>; + maxim,sensor_delay = <350>; + maxim,links = <4>; @@ -12756,10 +13000,10 @@ index 0000000..589a774 + maxim,resetb-gpio = <1>; + maxim,fsync-mode = "automatic"; + maxim,timeout = <100>; -+ POC0-supply = <&pwr0B>; -+ POC1-supply = <&pwr1B>; -+ POC2-supply = <&pwr2B>; -+ POC3-supply = <&pwr3B>; ++ POC0-supply = <&pwr1B>; ++ POC1-supply = <&pwr0B>; ++ POC2-supply = <&pwr3B>; ++ POC3-supply = <&pwr2B>; + + port@0 { + max9286_des1ep0: endpoint@0 { @@ -13156,10 +13400,10 @@ index 0000000..b854216 +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi new file mode 100644 -index 0000000..5958450 +index 0000000..d7ffd79 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi -@@ -0,0 +1,1541 @@ +@@ -0,0 +1,1542 @@ +/* + * Device Tree Source for the ULCB Kingfisher board + * @@ -14130,19 +14374,20 @@ index 0000000..5958450 + }; + + /* MAX9286 @ 0x2c */ -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@0 { ++ compatible = "maxim,max9286"; + reg = <0x2c>; + maxim,sensor_delay = <350>; + maxim,links = <4>; + maxim,lanes = <4>; + maxim,resetb-gpio = <1>; + maxim,fsync-mode = "automatic"; ++ + maxim,timeout = <100>; -+ POC0-supply = <&pwr0A>; -+ POC1-supply = <&pwr1A>; -+ POC2-supply = <&pwr2A>; -+ POC3-supply = <&pwr3A>; ++ POC0-supply = <&pwr1A>; ++ POC1-supply = <&pwr0A>; ++ POC2-supply = <&pwr3A>; ++ POC3-supply = <&pwr2A>; + + port@0 { + max9286_des0ep0: endpoint@0 { @@ -14703,7 +14948,7 @@ index 0000000..5958450 + diff --git a/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi new file mode 100644 -index 0000000..92ed4a4 +index 0000000..d5c4f46 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi @@ -0,0 +1,515 @@ @@ -14888,8 +15133,8 @@ index 0000000..92ed4a4 + }; + + /* MAX9286 @ 0x2c */ -+ max9286-max9271@2 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@2 { ++ compatible = "maxim,max9286"; + reg = <0x2c>; + maxim,sensor_delay = <350>; + maxim,links = <4>; @@ -15224,7 +15469,7 @@ index 0000000..92ed4a4 +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-vb.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vb.dtsi new file mode 100644 -index 0000000..193153e +index 0000000..4fcb320 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-vb.dtsi @@ -0,0 +1,1726 @@ @@ -15831,8 +16076,8 @@ index 0000000..193153e + }; + + /* MAX9286 @ 0x2c */ -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@0 { ++ compatible = "maxim,max9286"; + reg = <0x2c>; + maxim,sensor_delay = <350>; + maxim,links = <4>; @@ -16040,8 +16285,8 @@ index 0000000..193153e + }; + + /* MAX9286 @ 0x2c */ -+ max9286-max9271@1 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@1 { ++ compatible = "maxim,max9286"; + reg = <0x2c>; + maxim,sensor_delay = <350>; + maxim,links = <4>; @@ -16954,9 +17199,1807 @@ index 0000000..193153e + +/* uncomment to enable CN12 on VIN4-7 */ +//#include "ulcb-vb-cn12.dtsi" +diff --git a/arch/arm64/boot/dts/renesas/ulcb-vb2.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vb2.dtsi +new file mode 100644 +index 0000000..67b6085 +--- /dev/null ++++ b/arch/arm64/boot/dts/renesas/ulcb-vb2.dtsi +@@ -0,0 +1,1792 @@ ++/* ++ * Device Tree Source for the ULCB Videobox V2 board ++ * ++ * Copyright (C) 2018 Cogent Embedded, Inc. ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++/ { ++ leds { ++ compatible = "gpio-leds"; ++ ++ led5 { ++ gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; ++ }; ++ led6 { ++ gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; ++ }; ++ /* D13 - status 0 */ ++ led_ext00 { ++ gpios = <&gpio_ext_led 0 GPIO_ACTIVE_LOW>; ++ /* linux,default-trigger = "heartbeat"; */ ++ }; ++ /* D14 - status 1 */ ++ led_ext01 { ++ gpios = <&gpio_ext_led 1 GPIO_ACTIVE_LOW>; ++ /* linux,default-trigger = "mmc1"; */ ++ }; ++ /* D16 - HDMI0 */ ++ led_ext02 { ++ gpios = <&gpio_ext_led 2 GPIO_ACTIVE_LOW>; ++ }; ++ /* D18 - HDMI1 */ ++ led_ext03 { ++ gpios = <&gpio_ext_led 3 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ snd_clk: snd_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24576000>; ++ clock-output-names = "scki"; ++ }; ++ ++ vcc_sdhi3: regulator-vcc-sdhi3 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "SDHI3 Vcc"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ vccq_sdhi3: regulator-vccq-sdhi3 { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "SDHI3 VccQ"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ fpdlink_switch: regulator@8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "fpdlink_on"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio1 20 0>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ hub_reset: regulator@9 { ++ compatible = "regulator-fixed"; ++ regulator-name = "hub_reset"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio5 5 0>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ hub_power: regulator@10 { ++ compatible = "regulator-fixed"; ++ regulator-name = "hub_power"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio6 28 0>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ /delete-node/sound; ++ ++ rsnd_ak4613: sound@0 { ++ pinctrl-0 = <&sound_0_pins>; ++ pinctrl-names = "default"; ++ compatible = "simple-audio-card"; ++ ++ simple-audio-card,format = "left_j"; ++ simple-audio-card,name = "ak4613"; ++ ++ simple-audio-card,bitclock-master = <&sndcpu>; ++ simple-audio-card,frame-master = <&sndcpu>; ++ ++ sndcpu: simple-audio-card,cpu@1 { ++ sound-dai = <&rcar_sound>; ++ }; ++ ++ sndcodec: simple-audio-card,codec@1 { ++ sound-dai = <&ak4613>; ++ }; ++ }; ++ ++ lvds-encoder { ++ compatible = "thine,thc63lvdm83d"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ lvds_enc_in: endpoint { ++ remote-endpoint = <&du_out_lvds0>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ lvds_enc_out: endpoint { ++ remote-endpoint = <&lvds_in>; ++ }; ++ }; ++ }; ++ }; ++ ++ lvds { ++ compatible = "lvds-connector"; ++ ++ width-mm = <210>; ++ height-mm = <158>; ++ ++ panel-timing { ++ /* 1280x800 @60Hz */ ++ clock-frequency = <65000000>; ++ hactive = <1280>; ++ vactive = <800>; ++ hsync-len = <40>; ++ hfront-porch = <80>; ++ hback-porch = <40>; ++ vfront-porch = <14>; ++ vback-porch = <14>; ++ vsync-len = <4>; ++ }; ++ ++ port { ++ lvds_in: endpoint { ++ remote-endpoint = <&lvds_enc_out>; ++ }; ++ }; ++ }; ++ ++ excan_ref_clk: excan-ref-clock { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <16000000>; ++ }; ++ ++ spi_gpio_sw { ++ compatible = "spi-gpio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ gpio-sck = <&gpio0 8 GPIO_ACTIVE_HIGH>; ++ gpio-miso = <&gpio0 10 GPIO_ACTIVE_HIGH>; ++ gpio-mosi = <&gpio0 11 GPIO_ACTIVE_HIGH>; ++ cs-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; ++ num-chipselects = <1>; ++ ++ spidev: spidev@0 { ++ compatible = "spidev", "spi-gpio"; ++ reg = <0>; ++ spi-max-frequency = <25000000>; ++ spi-cpha; ++ spi-cpol; ++ }; ++ }; ++ ++ spi_gpio_can { ++ compatible = "spi-gpio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ gpio-sck = <&gpio1 2 GPIO_ACTIVE_HIGH>; ++ gpio-miso = <&gpio1 3 GPIO_ACTIVE_HIGH>; ++ gpio-mosi = <&gpio1 1 GPIO_ACTIVE_HIGH>; ++ cs-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH ++ &gpio1 4 GPIO_ACTIVE_HIGH>; ++ num-chipselects = <2>; ++ ++ spican0: spidev@0 { ++ compatible = "microchip,mcp2515"; ++ reg = <0>; ++ clocks = <&excan_ref_clk>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <15 GPIO_ACTIVE_LOW>; ++ spi-max-frequency = <10000000>; ++ }; ++ spican1: spidev@1 { ++ compatible = "microchip,mcp2515"; ++ reg = <1>; ++ clocks = <&excan_ref_clk>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <5 GPIO_ACTIVE_LOW>; ++ spi-max-frequency = <10000000>; ++ }; ++ }; ++}; ++ ++&pfc { ++ hscif4_pins: hscif4 { ++ groups = "hscif4_data_a", "hscif4_ctrl"; ++ function = "hscif4"; ++ }; ++ ++ /delete-node/sound; ++ ++ sound_0_pins: sound1 { ++ groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; ++ function = "ssi"; ++ }; ++ ++ usb0_pins: usb0 { ++ groups = "usb0"; ++ function = "usb0"; ++ }; ++ ++ usb2_pins: usb2 { ++ groups = "usb2"; ++ function = "usb2"; ++ }; ++ ++ can0_pins: can0 { ++ groups = "can0_data_a"; ++ function = "can0"; ++ }; ++ ++ can1_pins: can1 { ++ groups = "can1_data"; ++ function = "can1"; ++ }; ++ ++ canfd0_pins: canfd0 { ++ groups = "canfd0_data_a"; ++ function = "canfd0"; ++ }; ++ ++ canfd1_pins: canfd1 { ++ groups = "canfd1_data"; ++ function = "canfd1"; ++ }; ++ ++ sdhi3_pins: sd3 { ++ groups = "sdhi3_data4", "sdhi3_ctrl"; ++ function = "sdhi3"; ++ power-source = <3300>; ++ }; ++ ++ sdhi3_pins_uhs: sd3_uhs { ++ groups = "sdhi3_data4", "sdhi3_ctrl"; ++ function = "sdhi3"; ++ power-source = <1800>; ++ }; ++}; ++ ++&gpio0 { ++ video_a_irq { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A irq"; ++ }; ++ ++ video_b_irq { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B irq"; ++ }; ++ ++ video_c_irq { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-C irq"; ++ }; ++}; ++ ++&gpio1 { ++ gpioext_4_22_irq { ++ gpio-hog; ++ gpios = <25 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "0x22@i2c4 irq"; ++ }; ++ m2_0_sleep { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M2 0 SLEEP#"; ++ }; ++ m2_1_sleep { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M2 1 SLEEP#"; ++ }; ++ m2_0_pcie_det { ++ gpio-hog; ++ gpios = <18 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 0 PCIe/SATA"; ++ }; ++ m2_1_pcie_det { ++ gpio-hog; ++ gpios = <19 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 1 PCIe/SATA"; ++ }; ++ m2_1_rst { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M.2 1 RST#"; ++ }; ++ switch_ext_phy_reset { ++ gpio-hog; ++ gpios = <16 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BR ext phy reset"; ++ }; ++ switch_sw_reset { ++ gpio-hog; ++ gpios = <17 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BR switch reset"; ++ }; ++ switch_1v2_en { ++ gpio-hog; ++ gpios = <27 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BR 1.2V en"; ++ }; ++}; ++ ++&gpio2 { ++ m2_0_wake { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 0 WAKE#"; ++ }; ++ m2_0_clkreq { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 0 CLKREQ#"; ++ }; ++ switch_3v3_en { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BR 3.3V en"; ++ }; ++}; ++ ++&gpio3 { ++ switch_int_phy_reset { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BR int phy reset"; ++ }; ++}; ++ ++&gpio5 { ++ switch_2v5_en { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BR 2.5V en"; ++ }; ++ switch_25mhz_en { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "BR 25MHz clk en"; ++ }; ++}; ++ ++&gpio6 { ++ m2_1_wake { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 1 WAKE#"; ++ }; ++ m2_1_clkreq { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "M.2 1 CLKREQ#"; ++ }; ++ ++ m2_0_rst { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "M.2 0 RST#"; ++ }; ++}; ++ ++&i2c2 { ++ clock-frequency = <400000>; ++ ++ i2cswitch2: pca9548@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ /* USB3.0 HUB node(s) */ ++ /* addr of TUSB8041 is 100.0100 = 0x44 */ ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ /* Slot A (CN10) */ ++ ++ ov106xx@0 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x60>; ++ ++ port@0 { ++ ov106xx_in0: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin0ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ ov106xx_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ ov106xx_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@1 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x61>; ++ ++ port@0 { ++ ov106xx_in1: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin1ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ ov106xx_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ ov106xx_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@2 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x62>; ++ ++ port@0 { ++ ov106xx_in2: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin2ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ ov106xx_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@3 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x63>; ++ ++ port@0 { ++ ov106xx_in3: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin3ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ ov106xx_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@0 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "stp"; ++ ++ port@0 { ++ ti964_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti964_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ ti964_des0ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ ti964_des0ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ ti964_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@0 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_a_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "stp"; ++ ++ port@0 { ++ ti954_des0ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ ti954_des0ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ ti954_csi0ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ ++ /* MAX9286 @ 0x2c */ ++ max9286@0 { ++ compatible = "maxim,max9286"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des0ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ max9286_des0ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ max9286_des0ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ max9286_des0ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ max9286_csi0ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* Slot B (CN11) */ ++ ++ ov106xx@4 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x64>; ++ ++ port@0 { ++ ov106xx_in4: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin4ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ ov106xx_ti964_des1ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep0>; ++ }; ++ ov106xx_ti954_des1ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep0>; ++ }; ++ }; ++ }; ++ ++ ov106xx@5 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x65>; ++ ++ port@0 { ++ ov106xx_in5: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin5ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ ov106xx_ti964_des1ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep1>; ++ }; ++ ov106xx_ti954_des1ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep1>; ++ }; ++ }; ++ }; ++ ++ ov106xx@6 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x66>; ++ ++ port@0 { ++ ov106xx_in6: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin6ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ ov106xx_ti964_des1ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep2>; ++ }; ++ }; ++ }; ++ ++ ov106xx@7 { ++ compatible = "ovti,ov106xx"; ++ reg = <0x67>; ++ ++ port@0 { ++ ov106xx_in7: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&vin7ep0>; ++ }; ++ }; ++ port@1 { ++ ov106xx_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ ov106xx_ti964_des1ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep3>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB964 @ 0x3a */ ++ ti964-ti9x3@1 { ++ compatible = "ti,ti964-ti9x3"; ++ reg = <0x3a>; ++ ti,sensor_delay = <350>; ++ ti,links = <4>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "stp"; ++ ++ port@0 { ++ ti964_des1ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ ti964_des1ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ ti964_des1ep2: endpoint@2 { ++ ti9x3-addr = <0x0e>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ ti964_des1ep3: endpoint@3 { ++ ti9x3-addr = <0x0f>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ ti964_csi2ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ ++ /* DS90UB954 @ 0x38 */ ++ ti954-ti9x3@1 { ++ compatible = "ti,ti954-ti9x3"; ++ reg = <0x38>; ++ /* gpios = <&video_b_ext1 10 GPIO_ACTIVE_HIGH>; */ ++ ti,sensor_delay = <350>; ++ ti,links = <2>; ++ ti,lanes = <4>; ++ ti,forwarding-mode = "round-robin"; ++ ti,cable-mode = "stp"; ++ ++ port@0 { ++ ti954_des1ep0: endpoint@0 { ++ ti9x3-addr = <0x0c>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ ti954_des1ep1: endpoint@1 { ++ ti9x3-addr = <0x0d>; ++ dvp-order = <0>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ }; ++ port@1 { ++ ti954_csi2ep0: endpoint { ++ csi-rate = <1450>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ ++ /* MAX9286 @ 0x2c */ ++ max9286@1 { ++ compatible = "maxim,max9286"; ++ reg = <0x2c>; ++ maxim,sensor_delay = <350>; ++ maxim,links = <4>; ++ maxim,lanes = <4>; ++ maxim,resetb-gpio = <1>; ++ maxim,fsync-mode = "automatic"; ++ maxim,timeout = <100>; ++ ++ port@0 { ++ max9286_des1ep0: endpoint@0 { ++ max9271-addr = <0x50>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in4>; ++ }; ++ max9286_des1ep1: endpoint@1 { ++ max9271-addr = <0x51>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ }; ++ max9286_des1ep2: endpoint@2 { ++ max9271-addr = <0x52>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in6>; ++ }; ++ max9286_des1ep3: endpoint@3 { ++ max9271-addr = <0x53>; ++ dvp-order = <1>; ++ remote-endpoint = <&ov106xx_in7>; ++ }; ++ }; ++ port@1 { ++ max9286_csi2ep0: endpoint { ++ csi-rate = <700>; ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ /* Slot C (CN12) */ ++ }; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* Slot A (CN10) */ ++ ++ video_a_ext0: pca9535@26 { ++ compatible = "nxp,pca9535"; ++ reg = <0x26>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A led"; ++ }; ++ }; ++ ++ video_a_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_a_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg2"; ++ }; ++ video_a_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg1"; ++ }; ++ video_a_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-A cfg0"; ++ }; ++ video_a_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR_SHDN"; ++ }; ++ video_a_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR0"; ++ }; ++ video_a_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR1"; ++ }; ++ video_a_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR2"; ++ }; ++ video_a_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A PWR3"; ++ }; ++ video_a_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-A DES_SHDN"; ++ }; ++ video_a_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-A LED"; ++ }; ++ }; ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* Slot B (CN11) */ ++ ++ video_b_ext0: pca9535@26 { ++ compatible = "nxp,pca9535"; ++ reg = <0x26>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_b_des_cfg1 { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg1"; ++ }; ++ video_b_des_cfg0 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg0"; ++ }; ++ video_b_pwr_shdn { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR_SHDN"; ++ }; ++ video_b_cam_pwr0 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR0"; ++ }; ++ video_b_cam_pwr1 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR1"; ++ }; ++ video_b_cam_pwr2 { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR2"; ++ }; ++ video_b_cam_pwr3 { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR3"; ++ }; ++ video_b_des_shdn { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B DES_SHDN"; ++ }; ++ video_b_des_led { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B led"; ++ }; ++ }; ++ ++ video_b_ext1: max7325@5c { ++ compatible = "maxim,max7325"; ++ reg = <0x5c>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ video_b_des_cfg2 { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg2"; ++ }; ++ video_b_des_cfg1 { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg1"; ++ }; ++ video_b_des_cfg0 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "Video-B cfg0"; ++ }; ++ video_b_pwr_shdn { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR_SHDN"; ++ }; ++ video_b_cam_pwr0 { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR0"; ++ }; ++ video_b_cam_pwr1 { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR1"; ++ }; ++ video_b_cam_pwr2 { ++ gpio-hog; ++ gpios = <10 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR2"; ++ }; ++ video_b_cam_pwr3 { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B PWR3"; ++ }; ++ video_b_des_shdn { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "Video-B DES_SHDN"; ++ }; ++ video_b_led { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "Video-B LED"; ++ }; ++ }; ++ }; ++ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ /* Slot C (CN12) */ ++ }; ++ }; ++}; ++ ++&i2c4 { ++ i2cswitch4: pca9548@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x74>; ++ reset-gpios= <&gpio5 15 GPIO_ACTIVE_LOW>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ /* FAN1 node - lm96063 */ ++ fan_ctrl_1:lm96063-1@4c { ++ compatible = "lm96163"; ++ reg = <0x4c>; ++ }; ++ }; ++ ++ i2c@6 { ++ /* FAN2 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ /* FAN2 node - lm96063 */ ++ fan_ctrl_2:lm96063-2@4c { ++ compatible = "lm96163"; ++ reg = <0x4c>; ++ }; ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ ++ /* Power nodes - 2 x TPS544x20 */ ++ tps_5v: tps544c20@0x2a { ++ compatible = "tps544c20"; ++ reg = <0x2c>; ++ status = "disabled"; ++ }; ++ tps_3v3: tps544c20@0x22 { ++ compatible = "tps544c20"; ++ reg = <0x24>; ++ status = "disabled"; ++ }; ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ /* CAN and power board nodes */ ++ ++ gpio_ext_pwr: pca9535@22 { ++ compatible = "nxp,pca9535"; ++ reg = <0x22>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&gpio1>; ++ interrupts = <25 IRQ_TYPE_EDGE_FALLING>; ++ ++ /* enable input DCDC after wake-up signal released */ ++ pwr_hold { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "pwr_hold"; ++ }; ++ pwr_5v_out { ++ gpio-hog; ++ gpios = <14 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "pwr_5v_out"; ++ }; ++ pwr_5v_oc { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "pwr_5v_oc"; ++ }; ++ pwr_wake8 { ++ gpio-hog; ++ gpios = <12 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "wake8"; ++ }; ++ pwr_wake7 { ++ gpio-hog; ++ gpios = <13 GPIO_ACTIVE_HIGH>; ++ input; ++ line-name = "wake7"; ++ }; ++ ++ /* CAN0 */ ++ can0_stby { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can0_stby"; ++ }; ++ can0_load { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can0_120R_load"; ++ }; ++ /* CAN1 */ ++ can1_stby { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can1_stby"; ++ }; ++ can1_load { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can1_120R_load"; ++ }; ++ /* CAN2 */ ++ can2_stby { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can2_stby"; ++ }; ++ can2_load { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can2_120R_load"; ++ }; ++ can2_rst { ++ gpio-hog; ++ gpios = <8 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "can2_rst"; ++ }; ++ /* CAN3 */ ++ can3_stby { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can3_stby"; ++ }; ++ can3_load { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "can3_120R_load"; ++ }; ++ can3_rst { ++ gpio-hog; ++ gpios = <9 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "can3_rst"; ++ }; ++ }; ++ rtc@68 { ++ compatible = "dallas,ds1338"; ++ reg = <0x68>; ++ }; ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ /* FPDLink output node - DS90UH947 */ ++ }; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ /* BCM switch node */ ++ }; ++ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ /* LED board node(s) */ ++ ++ gpio_ext_led: pca9535@22 { ++ compatible = "nxp,pca9535"; ++ reg = <0x22>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ /* gpios 0..7 are used for indication LEDs, low-active */ ++ }; ++ }; ++ ++ /* port 7 is not used */ ++ }; ++}; ++ ++&pcie_bus_clk { ++ clock-frequency = <100000000>; ++ status = "okay"; ++}; ++ ++&pciec0 { ++ status = "okay"; ++}; ++ ++&pciec1 { ++ status = "okay"; ++}; ++ ++&vin0 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin0ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <0>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in0>; ++ }; ++ }; ++ port@1 { ++ csi0ep0: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin0_max9286_des0ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep0>; ++ }; ++ vin0_ti964_des0ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep0>; ++ }; ++ vin0_ti954_des0ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin1 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin1ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <1>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in1>; ++ }; ++ }; ++ port@1 { ++ csi0ep1: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin1_max9286_des0ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep1>; ++ }; ++ vin1_ti964_des0ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep1>; ++ }; ++ vin1_ti954_des0ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des0ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin2 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin2ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <2>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in2>; ++ }; ++ }; ++ port@1 { ++ csi0ep2: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin2_max9286_des0ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep2>; ++ }; ++ vin2_ti964_des0ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin3 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin3ep0: endpoint { ++ csi,select = "csi40"; ++ virtual,channel = <3>; ++ data-lanes = <1 2 3 4>; ++ remote-endpoint = <&ov106xx_in3>; ++ }; ++ }; ++ port@1 { ++ csi0ep3: endpoint { ++ remote-endpoint = <&csi2_40_ep>; ++ }; ++ }; ++ port@2 { ++ vin3_max9286_des0ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des0ep3>; ++ }; ++ vin3_ti964_des0ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des0ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&vin4 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin4ep0: endpoint { ++ csi,select = "csi41"; ++ virtual,channel = <0>; ++ remote-endpoint = <&ov106xx_in4>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep0: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin4_max9286_des1ep0: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep0>; ++ }; ++ vin4_ti964_des1ep0: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep0>; ++ }; ++ vin4_ti954_des1ep0: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep0>; ++ }; ++ }; ++ }; ++}; ++ ++&vin5 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin5ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <1>; ++ remote-endpoint = <&ov106xx_in5>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep1: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin5_max9286_des1ep1: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep1>; ++ }; ++ vin5_ti964_des1ep1: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep1>; ++ }; ++ vin5_ti954_des1ep1: endpoint@2 { ++ remote-endpoint = <&ti954_des1ep1>; ++ }; ++ }; ++ }; ++}; ++ ++&vin6 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin6ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <2>; ++ remote-endpoint = <&ov106xx_in6>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep2: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin6_max9286_des1ep2: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep2>; ++ }; ++ vin6_ti964_des1ep2: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep2>; ++ }; ++ }; ++ }; ++}; ++ ++&vin7 { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ vin7ep0: endpoint@0 { ++ csi,select = "csi41"; ++ virtual,channel = <3>; ++ remote-endpoint = <&ov106xx_in7>; ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ port@1 { ++ csi2ep3: endpoint { ++ remote-endpoint = <&csi2_41_ep>; ++ }; ++ }; ++ port@2 { ++ vin7_max9286_des1ep3: endpoint@0 { ++ remote-endpoint = <&max9286_des1ep3>; ++ }; ++ vin7_ti964_des1ep3: endpoint@1 { ++ remote-endpoint = <&ti964_des1ep3>; ++ }; ++ }; ++ }; ++}; ++ ++&csi2_40 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_40_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&csi2_41 { ++ status = "okay"; ++ ++ virtual,channel { ++ csi2_vc0 { ++ data,type = "ycbcr422"; ++ receive,vc = <0>; ++ }; ++ csi2_vc1 { ++ data,type = "ycbcr422"; ++ receive,vc = <1>; ++ }; ++ csi2_vc2 { ++ data,type = "ycbcr422"; ++ receive,vc = <2>; ++ }; ++ csi2_vc3 { ++ data,type = "ycbcr422"; ++ receive,vc = <3>; ++ }; ++ }; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi2_41_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2 3 4>; ++ csi-rate = <300>; ++ }; ++ }; ++}; ++ ++&rcar_sound { ++ pinctrl-0 = <&sound_clk_pins>; ++ ++ /* Multi DAI */ ++ #sound-dai-cells = <1>; ++}; ++ ++&sata { ++ status = "okay"; ++}; ++ ++&ssi1 { ++ /delete-property/shared-pin; ++}; ++ ++&sdhi3 { ++ pinctrl-0 = <&sdhi3_pins>; ++ pinctrl-1 = <&sdhi3_pins_uhs>; ++ pinctrl-names = "default", "state_uhs"; ++ ++ vmmc-supply = <&vcc_sdhi3>; ++ vqmmc-supply = <&vccq_sdhi3>; ++ cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; ++ wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; ++ bus-width = <4>; ++ sd-uhs-sdr50; ++ status = "okay"; ++}; ++ ++&msiof1 { ++ status = "disabled"; ++}; ++ ++&usb2_phy0 { ++ pinctrl-0 = <&usb0_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&usb2_phy2 { ++ pinctrl-0 = <&usb2_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++}; ++ ++&xhci0 { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci2 { ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci2 { ++ status = "okay"; ++}; ++ ++&can0 { ++ pinctrl-0 = <&can0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++}; ++ ++&can1 { ++ pinctrl-0 = <&can1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ renesas,can-clock-select = <0x0>; ++}; ++ ++&canfd { ++ pinctrl-0 = <&canfd0_pins &canfd1_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ ++ renesas,can-clock-select = <0x0>; ++ ++ channel0 { ++ status = "okay"; ++ }; ++ ++ channel1 { ++ status = "okay"; ++ }; ++}; ++ ++/* uncomment to enable CN12 on VIN4-7 */ ++//#include "ulcb-vb-cn12.dtsi" diff --git a/arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi new file mode 100644 -index 0000000..beb52e9 +index 0000000..7728bdd --- /dev/null +++ b/arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi @@ -0,0 +1,578 @@ @@ -17223,8 +19266,8 @@ index 0000000..beb52e9 + }; + }; + -+ max9286-max9271@0 { -+ compatible = "maxim,max9286-max9271"; ++ max9286@0 { ++ compatible = "maxim,max9286"; + reg = <0x2c>; + maxim,sensor_delay = <350>; + maxim,links = <4>; diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0050-arm64-dts-renesas-r8a779x-add-IMP-nodes.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0050-arm64-dts-renesas-r8a779x-add-IMP-nodes.patch index b38a623..d52106e 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0050-arm64-dts-renesas-r8a779x-add-IMP-nodes.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0050-arm64-dts-renesas-r8a779x-add-IMP-nodes.patch @@ -7,14 +7,14 @@ This adds IMP resource nodes for Gen3 SoCs Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> --- - arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 98 +++++++++++++++++++++++++++ - arch/arm64/boot/dts/renesas/r8a7795.dtsi | 98 +++++++++++++++++++++++++++ - arch/arm64/boot/dts/renesas/r8a7796.dtsi | 62 +++++++++++++++++ - arch/arm64/boot/dts/renesas/r8a7797.dtsi | 99 ++++++++++++++++++++++++++++ - 4 files changed, 357 insertions(+) + arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 98 ++++++++++++++++++++++++ + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 98 ++++++++++++++++++++++++ + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 62 ++++++++++++++++ + arch/arm64/boot/dts/renesas/r8a7797.dtsi | 107 +++++++++++++++++++++++++++ + 4 files changed, 365 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi -index b3f3102..e15af8c 100644 +index 3a2d2c8..c6bc187 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi @@ -2794,6 +2794,104 @@ @@ -123,7 +123,7 @@ index b3f3102..e15af8c 100644 compatible = "renesas,imr-lx4"; reg = <0 0xfe860000 0 0x2000>; diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi -index 02c5931..8ba4cec 100644 +index 8f7d776..a01a4f3 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -2790,6 +2790,104 @@ @@ -232,7 +232,7 @@ index 02c5931..8ba4cec 100644 compatible = "renesas,imr-lx4"; reg = <0 0xfe860000 0 0x2000>; diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi -index b94d9e0..7c19f35 100644 +index f214f26..d3e91f1 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -2531,5 +2531,67 @@ @@ -304,15 +304,15 @@ index b94d9e0..7c19f35 100644 }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a7797.dtsi b/arch/arm64/boot/dts/renesas/r8a7797.dtsi -index 1be93e8..232eb19 100644 +index 118a473..05b50ca 100644 --- a/arch/arm64/boot/dts/renesas/r8a7797.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7797.dtsi -@@ -970,6 +970,112 @@ +@@ -967,6 +967,113 @@ status = "okay"; }; + imp_distributer: impdes0 { -+ compatible = "renesas,impx4-distributer"; ++ compatible = "renesas,impx5+-distributer"; + reg = <0 0xffa00000 0 0x4000>; + interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 830>; @@ -335,8 +335,8 @@ index 1be93e8..232eb19 100644 + reg = <0 0xff920000 0 0x20000>; + interrupt-parent = <&imp_distributer>; + interrupts = <1>; -+ clocks = <&cpg CPG_MOD 826>; -+ power-domains = <&sysc R8A7797_PD_A2IR1>; ++ clocks = <&cpg CPG_MOD 827>; ++ power-domains = <&sysc R8A7797_PD_A2IR0>; + }; + + imp2 { @@ -344,8 +344,8 @@ index 1be93e8..232eb19 100644 + reg = <0 0xff940000 0 0x20000>; + interrupt-parent = <&imp_distributer>; + interrupts = <2>; -+ clocks = <&cpg CPG_MOD 825>; -+ power-domains = <&sysc R8A7797_PD_A2IR2>; ++ clocks = <&cpg CPG_MOD 826>; ++ power-domains = <&sysc R8A7797_PD_A2IR1>; + }; + + imp3 { @@ -353,8 +353,8 @@ index 1be93e8..232eb19 100644 + reg = <0 0xff960000 0 0x20000>; + interrupt-parent = <&imp_distributer>; + interrupts = <3>; -+ clocks = <&cpg CPG_MOD 824>; -+ power-domains = <&sysc R8A7797_PD_A2IR3>; ++ clocks = <&cpg CPG_MOD 826>; ++ power-domains = <&sysc R8A7797_PD_A2IR1>; + }; + + impsc0 { @@ -379,28 +379,36 @@ index 1be93e8..232eb19 100644 + compatible = "renesas,impx5-dmac"; + reg = <0 0xffa10000 0 0x1000>; + interrupt-parent = <&imp_distributer>; -+ interrupts = <16>; -+ clocks = <&cpg CPG_MOD 830>; -+ power-domains = <&sysc R8A7797_PD_A3IR>; ++ interrupts = <6>; ++ clocks = <&cpg CPG_MOD 825>; ++ power-domains = <&sysc R8A7797_PD_A2IR2>; + }; + + impdm1 { + compatible = "renesas,impx5-dmac"; -+ reg = <0 0xffa10000 0 0x1000>, -+ <0 0xffa10800 0 0x0800>; ++ reg = <0 0xffa11000 0 0x1000>; + interrupt-parent = <&imp_distributer>; -+ interrupts = <17>; -+ clocks = <&cpg CPG_MOD 830>; -+ power-domains = <&sysc R8A7797_PD_A3IR>; ++ interrupts = <7>; ++ clocks = <&cpg CPG_MOD 825>; ++ power-domains = <&sysc R8A7797_PD_A2IR2>; + }; + + imppsc0 { -+ compatible = "renesas,impx5-dmac"; ++ compatible = "renesas,impx5+-psc"; + reg = <0 0xffa20000 0 0x4000>; + interrupt-parent = <&imp_distributer>; -+ interrupts = <12>; -+ clocks = <&cpg CPG_MOD 830>; -+ power-domains = <&sysc R8A7797_PD_A3IR>; ++ interrupts = <8>; ++ clocks = <&cpg CPG_MOD 825>; ++ power-domains = <&sysc R8A7797_PD_A2IR2>; ++ }; ++ ++ impcnn0 { ++ compatible = "renesas,impx5+-cnn"; ++ reg = <0 0xff9e0000 0 0x10000>; ++ interrupt-parent = <&imp_distributer>; ++ interrupts = <9>; ++ clocks = <&cpg CPG_MOD 824>; ++ power-domains = <&sysc R8A7797_PD_A2IR3>; + }; + + impc0 { @@ -410,13 +418,6 @@ index 1be93e8..232eb19 100644 + power-domains = <&sysc R8A7797_PD_A3IR>; + }; + -+ impcnn0 { -+ compatible = "renesas,impx4-legacy"; -+ reg = <0 0xff9e0000 0 0x10000>; -+ clocks = <&cpg CPG_MOD 824>; -+ power-domains = <&sysc R8A7797_PD_A2IR3>; -+ }; -+ imrlx4_ch0: imr-lx4@fe860000 { compatible = "renesas,imr-lx4"; reg = <0 0xfe860000 0 0x2000>; diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0082-gpio-pca953x-fix-interrupt-trigger.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0082-gpio-pca953x-fix-interrupt-trigger.patch new file mode 100644 index 0000000..f576759 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0082-gpio-pca953x-fix-interrupt-trigger.patch @@ -0,0 +1,28 @@ +From 03708e8a6c537752528d865964fd37be56453995 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Fri, 15 Dec 2017 02:23:49 +0300 +Subject: [PATCH] gpio: pca953x: fix interrupt trigger + +The PCA9539 chip has edge sensitive interrupt + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +--- + drivers/gpio/gpio-pca953x.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c +index fe731f0..0b3f0d8 100644 +--- a/drivers/gpio/gpio-pca953x.c ++++ b/drivers/gpio/gpio-pca953x.c +@@ -626,7 +626,7 @@ static int pca953x_irq_setup(struct pca953x_chip *chip, + client->irq, + NULL, + pca953x_irq_handler, +- IRQF_TRIGGER_LOW | IRQF_ONESHOT | ++ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT | + IRQF_SHARED, + dev_name(&client->dev), chip); + if (ret) { +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/eagle.cfg b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/eagle.cfg index 9796ba5..5b728fd 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/eagle.cfg +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/eagle.cfg @@ -23,6 +23,7 @@ CONFIG_SOC_CAMERA_MAX9286_MAX9271=y CONFIG_SOC_CAMERA_OV106XX=y CONFIG_VIDEO_RENESAS_IMR=y CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_INPUT_UINPUT=y CONFIG_TOUCHSCREEN_PROPERTIES=y CONFIG_HID_MULTITOUCH=y CONFIG_SERIAL_SH_SCI_DMA=y diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/ulcb.cfg b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/ulcb.cfg index f1c86ca..0fd7e07 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/ulcb.cfg +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/ulcb.cfg @@ -72,4 +72,9 @@ CONFIG_TOUCHSCREEN_EDT_FT5X06=y CONFIG_SERIAL_SH_SCI_DMA=y CONFIG_STAGING=y CONFIG_UIO=y +CONFIG_SENSORS_EMC2103=y +CONFIG_PMBUS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_DS1307_HWMON=y +CONFIG_SENSORS_LM63=y CONFIG_MMC_SDHI_SEQ_WORKAROUND=y diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/v3msk.cfg b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/v3msk.cfg index 211da49..34a385b 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/v3msk.cfg +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/v3msk.cfg @@ -27,6 +27,7 @@ CONFIG_SOC_CAMERA_TI954_TI9X3=y CONFIG_SOC_CAMERA_OV106XX=y CONFIG_VIDEO_RENESAS_IMR=y CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_INPUT_UINPUT=y CONFIG_TOUCHSCREEN_PROPERTIES=y CONFIG_HID_MULTITOUCH=y CONFIG_SERIAL_SH_SCI_DMA=y diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend index 6876b5c..c4cad0f 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend @@ -80,8 +80,7 @@ SRC_URI_append = " \ file://0077-MOST-dim2-add-timeouts.patch \ file://0078-MOST-aim-fix-null-pointer-crash.patch \ file://0079-Revert-dmaengine-rcar-dmac-use-TCRB-instead-of-TCR-f.patch \ - file://0080-dmaengine-rcar-dmac-ensure-CHCR-DE-bit-is-actually-0.patch \ - file://0081-dmaengine-rcar-dmac-use-TCRB-instead-of-TCR-for-resi.patch \ + file://0082-gpio-pca953x-fix-interrupt-trigger.patch \ file://0001-arm64-dts-renesas-preserve-drm-HDMI-connector-naming.patch \ file://0001-arm64-dts-renesas-disable-r8a7796-hscif0-dma.patch \ " @@ -104,12 +103,14 @@ KERNEL_DEVICETREE_append_h3ulcb = " \ renesas/r8a7795-es1-h3ulcb-had-beta.dtb \ renesas/r8a7795-es1-h3ulcb-kf.dtb \ renesas/r8a7795-es1-h3ulcb-vb.dtb \ + renesas/r8a7795-es1-h3ulcb-vb2.dtb \ renesas/r8a7795-es1-h3ulcb-vbm.dtb \ renesas/r8a7795-h3ulcb-view.dtb \ renesas/r8a7795-h3ulcb-had-alfa.dtb \ renesas/r8a7795-h3ulcb-had-beta.dtb \ renesas/r8a7795-h3ulcb-kf.dtb \ renesas/r8a7795-h3ulcb-vb.dtb \ + renesas/r8a7795-h3ulcb-vb2.dtb \ renesas/r8a7795-h3ulcb-vbm.dtb \ " @@ -126,6 +127,7 @@ KERNEL_DEVICETREE_append_salvator-x = " \ KERNEL_DEVICETREE_append_eagle = " \ renesas/r8a7797-eagle.dtb \ + renesas/r8a7797-eagle-function.dtb \ " KERNEL_DEVICETREE_append_v3msk = " \ diff --git a/meta-rcar-gen3-adas/recipes-support/glog/glog_0.3.3.bbappend b/meta-rcar-gen3-adas/recipes-support/glog/glog_0.3.3.bbappend new file mode 100644 index 0000000..b3d1db5 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-support/glog/glog_0.3.3.bbappend @@ -0,0 +1,5 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}-${PV}:" + +SRC_URI_append = " file://0001-Use-pkg-config-for-locating-gflags-and-gmock.patch" + +DEPENDS += "gflags gmock gtest" |