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authorDuy Dang <duy.dang.yw@rvc.renesas.com>2018-10-30 11:05:21 +0700
committerDuy Dang <duy.dang.yw@rvc.renesas.com>2018-12-20 09:47:58 +0700
commit67dc81a5298c0791a85d8e07b8e08c836ce7bfed (patch)
treed34f086997da185e1d79990627f50af67d46dbad
parent81198ba799c0232b737e2d521cbb3d1f6ebcd325 (diff)
rcar-gen3: IPL: Update SRCREV to follow the latest version
This commit updates SRCREV of IPL and Secure Monitor to Rev2.0.0 for these changes: [IPL] - Update DDR setting for E3(rev0.11). - Change the condition of data transfer end of SCIF transfer. - Modify address area in the DDR memory config log output. - Update H3 Ver.3.0 QoS setting rev.0.09. - Update E3 Ver.1.0 QoS setting rev.0.04. - Update H3 Ver.2.0 QoS setting rev.0.20. - Update H3 Ver.3.0 QoS setting rev.0.10. - Update M3 Ver.1.1 QoS setting rev.0.18. - Update M3N Ver.1.1 QoS setting rev.0.08. - Update E3 Ver.1.0 QoS setting rev.0.05. - Modify load destination variable of the Cert Header to static. - [H/W Restriction No.100]: + Disable TLB function of IPMMU cache on E3 Ver.1.1. + Disable TLB function of IPMMU-PV0 cache on E3 Ver.1.x. [Secure Monitor] - Add API for getting DRAM capacity information. - Change the execution timing of system RAM copy process to BL31 startup. Signed-off-by: Duy Dang <duy.dang.yw@rvc.renesas.com> Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
-rw-r--r--meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb2
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb b/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb
index 1456ff7..1eb6b75 100644
--- a/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb
+++ b/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb
@@ -13,7 +13,7 @@ S = "${WORKDIR}/git"
BRANCH = "rcar_gen3"
SRC_URI = "git://github.com/renesas-rcar/arm-trusted-firmware.git;branch=${BRANCH}"
-SRCREV = "7f126e2e718a69bec850c87bd05c4c168b32c4df"
+SRCREV = "556a11e73f3d94c7552251370f85ecf2c40ed625"
PV = "v1.5+renesas+git${SRCPV}"