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authorDuy Dang <duy.dang.yw@rvc.renesas.com>2019-02-18 08:51:50 +0700
committerDuy Dang <duy.dang.yw@renesas.com>2019-04-02 09:31:33 +0700
commitde96e0e4738e0b473c2fb77e2384e2c516990d4d (patch)
tree418836cef7f2fb836e13542051c234593163e7ca
parent5be728d6bfeb06c3174d5dffd09775d38674dd69 (diff)
rcar-gen3: u-boot: Update to version 3.9.3
This commit updates U-Boot SRCREV to Ver.3.9.3 for the following changes: - Increase off-on delay on the SD Vcc regulator. - Fix r8a779{5,6,90} DRIF conflict names by H/W UM 1.50 errata. - Apply upstream code related to mmc. - Add upstream description to DT files added by BSP. - Fix warning in writel() overflow in rcar_i2c.c. - Set environment variable containing CPU type. - Downgrade SD/MMC from UHS/HS200/HS400 modes before boot. - Unmount FS in do_fs_type(). - Support up to MMC HS200 mode with U-Boot. - Add DMA transfer address alignment check at writing. - Fix pinctrl definition according to H/W UM Rev.1.00 and errata. - Force mmc reinit when no card present. - Make DMA transfer end bit configurable and add 1uS delay after DMA completion on older IPs. - Add function to activate with suitable DT and add Enable MULTI_DTB_FIT. Change-Id: I958f86c16e7558ac51b40e68f611b7f20748877c Signed-off-by: Duy Dang <duy.dang.yw@renesas.com> Signed-off-by: Khang Nguyen <khang.nguyen.xw@renesas.com> Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
-rw-r--r--meta-rcar-gen3/recipes-bsp/u-boot/u-boot_2018.09.bb4
1 files changed, 2 insertions, 2 deletions
diff --git a/meta-rcar-gen3/recipes-bsp/u-boot/u-boot_2018.09.bb b/meta-rcar-gen3/recipes-bsp/u-boot/u-boot_2018.09.bb
index 654b5ef..dc9d167 100644
--- a/meta-rcar-gen3/recipes-bsp/u-boot/u-boot_2018.09.bb
+++ b/meta-rcar-gen3/recipes-bsp/u-boot/u-boot_2018.09.bb
@@ -4,10 +4,10 @@ require u-boot.inc
DEPENDS += "bc-native dtc-native"
UBOOT_URL = "git://github.com/renesas-rcar/u-boot.git"
-BRANCH = "v2018.09/rcar-3.9.1"
+BRANCH = "v2018.09/rcar-3.9.3"
SRC_URI = "${UBOOT_URL};branch=${BRANCH}"
-SRCREV = "4d322dccdcf49c0aab18eb703663128aec81cffc"
+SRCREV = "2b858f59e82177c8aba621b26629d797db2b7cc7"
PV = "v2018.09+git${SRCPV}"
UBOOT_SREC_SUFFIX = "srec"