KF: fix DU RGB flickering, remove SDR50/104

1) fix DU RGB port flickeringby presclaing clock in VC5
2) limit clock for DU RGB in driver adv7511 to 100Mhz
this is according to Gen3 manual limitation for this DU port
3) update README
4) remove SDR50/104 from onboard KF

6 files changed, 201 insertions, 3 deletions

diff --git a/README b/README
index 1b96155..dec877a 100644
--- a/README
+++ b/README
@@ -13,3 +13,4 @@ Supported Boards/Machines
         - Renesas Electronics Corporation. ULCB View (R8A7795/R8A7796)
         - Renesas Electronics Corporation. ULCB HAD (R8A7795)
         - Renesas Electronics Corporation. ULCB Kingfisher (R8A7795/R8A7796)
+        - Renesas Electronics Corporation. ULCB Videobox (R8A7795)
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch
index 2c2d7cc..fa1cff3 100644
--- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch
@@ -18613,8 +18613,8 @@ index 0000000..216e800
 +	vmmc-supply = <&vcc_sdhi3>;
 +	cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 +	wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
-+	sd-uhs-sdr50;
-+	sd-uhs-sdr104;
++//	sd-uhs-sdr50;
++//	sd-uhs-sdr104;
 +};
 +
 +&wlcore {
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0043-arm64-dts-renesas-ulcb-use-versaclock-for-du-rgb-and-lvds.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0043-arm64-dts-renesas-ulcb-use-versaclock-for-du-rgb-and-lvds.patch
new file mode 100644
index 0000000..1298ba8
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0043-arm64-dts-renesas-ulcb-use-versaclock-for-du-rgb-and-lvds.patch
@@ -0,0 +1,143 @@
+From 29bcecbb93b009e650dfdf9e6a1ff6efadc871bc Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Thu, 10 Aug 2017 08:41:53 +0300
+Subject: [PATCH] arm64: dts: renesas: ulcb: use versaclock for DU RGB and LVDS
+
+This allows to chgange preprogrammed clock in Versa5 clock
+generator.
+DU has PLL that is not too accurate, hence use prescaled value by VC5.
+
+[200~Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+---
+ arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts | 24 ++++++++++++++++++++++
+ arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts     | 24 ++++++++++++++++++++++
+ arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts     | 22 ++++++++++++++++++++
+ 3 files changed, 70 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts
+index 677bf88..6fe4416 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts
+@@ -229,6 +229,15 @@
+ &du {
+ 	status = "okay";
+ 
++	/* update <du_dotclkin0/3> to <programable_clk0/1> */
++	clocks = <&cpg CPG_MOD 724>,
++		 <&cpg CPG_MOD 723>,
++		 <&cpg CPG_MOD 722>,
++		 <&cpg CPG_MOD 721>,
++		 <&cpg CPG_MOD 727>,
++		 <&programmable_clk0>, <&du_dotclkin1>, <&du_dotclkin2>,
++		 <&programmable_clk1>;
++
+ 	ports {
+ 		port@1 {
+ 			endpoint {
+@@ -390,6 +399,21 @@
+ 	status = "okay";
+ 
+ 	clock-frequency = <400000>;
++
++	clk_5p49v5925: programmable_clk@6a {
++		compatible = "idt,5p49v5925";
++		reg = <0x6a>;
++
++		programmable_clk0: 5p49x_clk1@6a {
++			#clock-cells = <0>;
++			clocks = <&du_dotclkin0>;
++		};
++
++		programmable_clk1: 5p49x_clk2@6a {
++			#clock-cells = <0>;
++			clocks = <&du_dotclkin3>;
++		};
++	};
+ };
+ 
+ &rcar_sound {
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+index 7406534..e018f21 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+@@ -229,6 +229,15 @@
+ &du {
+ 	status = "okay";
+ 
++	/* update <du_dotclkin0/3> to <programable_clk0/1> */
++	clocks = <&cpg CPG_MOD 724>,
++		 <&cpg CPG_MOD 723>,
++		 <&cpg CPG_MOD 722>,
++		 <&cpg CPG_MOD 721>,
++		 <&cpg CPG_MOD 727>,
++		 <&programmable_clk0>, <&du_dotclkin1>, <&du_dotclkin2>,
++		 <&programmable_clk1>;
++
+ 	ports {
+ 		port@1 {
+ 			endpoint {
+@@ -390,6 +399,21 @@
+ 	status = "okay";
+ 
+ 	clock-frequency = <400000>;
++
++	clk_5p49v5925: programmable_clk@6a {
++		compatible = "idt,5p49v5925";
++		reg = <0x6a>;
++
++		programmable_clk0: 5p49x_clk1@6a {
++			#clock-cells = <0>;
++			clocks = <&du_dotclkin0>;
++		};
++
++		programmable_clk1: 5p49x_clk2@6a {
++			#clock-cells = <0>;
++			clocks = <&du_dotclkin3>;
++		};
++	};
+ };
+ 
+ &rcar_sound {
+diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+index 9aa4292..130c068 100644
+--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
++++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+@@ -312,6 +312,13 @@
+ &du {
+ 	status = "okay";
+ 
++	/* update <du_dotclkin0/2> to <programable_clk0/1> */
++	clocks = <&cpg CPG_MOD 724>,
++		 <&cpg CPG_MOD 723>,
++		 <&cpg CPG_MOD 722>,
++		 <&cpg CPG_MOD 727>,
++		 <&programmable_clk0>, <&du_dotclkin1>, <&programmable_clk1>;
++
+ 	ports {
+ 		port@1 {
+ 			endpoint {
+@@ -422,6 +429,21 @@
+ &i2c4 {
+ 	status = "okay";
+ 	clock-frequency = <400000>;
++
++	clk_5p49v5925: programmable_clk@6a {
++		compatible = "idt,5p49v5925";
++		reg = <0x6a>;
++
++		programmable_clk0: 5p49x_clk1@6a {
++			#clock-cells = <0>;
++			clocks = <&du_dotclkin0>;
++		};
++
++		programmable_clk1: 5p49x_clk2@6a {
++			#clock-cells = <0>;
++			clocks = <&du_dotclkin2>;
++		};
++	};
+ };
+ 
+ &rcar_sound {
+-- 
+1.9.1
+
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0064-ADV7511-limit-maximum-pixelclock.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0064-ADV7511-limit-maximum-pixelclock.patch
index 3656164..eca5884 100644
--- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0064-ADV7511-limit-maximum-pixelclock.patch
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0064-ADV7511-limit-maximum-pixelclock.patch
@@ -3,6 +3,9 @@ From: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
 Date: Fri, 9 Jun 2017 20:12:26 +0300
 Subject: [PATCH] ADV7511: limit maximum pixelclock
 
+DU0 (RGB) supports clock freq up to 100MHz only.
+Temporary set limitation in the driver since it KF is the only user atm
+
 Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
 ---
  drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 2 +-
@@ -17,7 +20,7 @@ index 9698c21813dc..8914d64b7589 100644
  			      struct drm_display_mode *mode)
  {
 -	if (mode->clock > 165000)
-+	if (mode->clock > 133000)
++	if (mode->clock > 100000)
  		return MODE_CLOCK_HIGH;
  
  	return MODE_OK;
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0070-clk-clk-5p49x-add-5P49V5925-chip.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0070-clk-clk-5p49x-add-5P49V5925-chip.patch
new file mode 100644
index 0000000..0608eca
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0070-clk-clk-5p49x-add-5P49V5925-chip.patch
@@ -0,0 +1,49 @@
+From d9e198a198e8892ac7e1e2636f55207757ee505a Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Thu, 10 Aug 2017 08:46:54 +0300
+Subject: [PATCH] clk: clk-5p49x: add 5P49V5925 chip
+
+Add 5P49V5925 chip
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+---
+ drivers/clk/clk-5p49x.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/clk/clk-5p49x.c b/drivers/clk/clk-5p49x.c
+index 928bacb..8070154 100644
+--- a/drivers/clk/clk-5p49x.c
++++ b/drivers/clk/clk-5p49x.c
+@@ -60,6 +60,10 @@ struct clk_5p49_priv {
+ 	.xtal_fre = 25000000,
+ };
+ 
++static const struct clk_5p49_info clk_5p49v5925 = {
++	.xtal_fre = 25000000,
++};
++
+ static const struct clk_5p49_info clk_5p49v6901a = {
+ 	.xtal_fre = 50000000,
+ };
+@@ -70,6 +74,10 @@ struct clk_5p49_priv {
+ 		.data = &clk_5p49v5923a,
+ 	},
+ 	{
++		.compatible = "idt,5p49v5925",
++		.data = &clk_5p49v5925,
++	},
++	{
+ 		.compatible = "idt,5p49v6901a",
+ 		.data = &clk_5p49v6901a,
+ 	},
+@@ -79,6 +87,7 @@ struct clk_5p49_priv {
+ 
+ static const struct i2c_device_id clk_5p49_id[] = {
+ 	{ "5p49v5923a",},
++	{ "5p49v5925",},
+ 	{ "5p49v6901a",},
+ 	{}
+ };
+-- 
+1.9.1
+
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend
index 041de43..91c5390 100644
--- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend
@@ -40,6 +40,7 @@ SRC_URI_append = " \
     file://0040-arm64-dts-renesas-add-ADAS-boards.patch \
     file://0041-arm64-dts-renesas-ulcb-enlarge-cma-region.patch \
     file://0042-arm64-dts-renesas-r8a7795-es1-h3ulcb-disable-eMMC.patch \
+    file://0043-arm64-dts-renesas-ulcb-use-versaclock-for-du-rgb-and-lvds.patch \
     ${@base_conditional("LVDSCAMERA_FIRST4_TYPE1", "1", " file://0050-arm64-dts-Gen3-view-boards-TYPE1-first-4-cameras.patch", "", d)} \
     ${@base_conditional("LVDSCAMERA_SECOND4_TYPE1", "1", " file://0051-arm64-dts-Gen3-view-boards-TYPE1-second-4-cameras.patch", "", d)} \
     ${@base_conditional("LVDSCAMERA_FIRST4_TYPE2", "1", " file://0052-arm64-dts-Gen3-view-boards-TYPE2-first-4-cameras.patch", "", d)} \
@@ -52,6 +53,7 @@ SRC_URI_append = " \
     file://0067-ti-st-use-proper-way-to-get-shutdown-gpio.patch \
     file://0068-drm-adv7511-use-smbus-to-retrieve-edid.patch \
     file://0069-ASoC-ak4613-Improve-counting-DAI-number.patch \
+    file://0070-clk-clk-5p49x-add-5P49V5925-chip.patch \
 "
 
 SRC_URI_append_h3ulcb = " file://ulcb.cfg"