diff options
| author |   Vladimir Barinov <vladimir.barinov@cogentembedded.com> | 2018-01-22 18:43:47 +0300 |
|---|---|---|
| committer | Vladimir Barinov <vladimir.barinov@cogentembedded.com> | 2018-01-22 18:43:47 +0300 |
| commit | a94b208793023660c3aa1fcbce38bf8a6767920a (patch) | |
| tree | 0ea4b46c57f2bb472d00c9e260122163b1a499a9 | |
| parent | 6262288744b7d4a0945e365bef3c01b3440cac01 (diff) | |
V3M/V3H: fix CMT0 timer offset
2 files changed, 4 insertions, 4 deletions
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch index dc80f98..88d2a52 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch @@ -579,9 +579,9 @@ index 0000000..0dd374f + }; + }; + -+ cmt0: timer@ffca0000 { ++ cmt0: timer@e60f0000 { + compatible = "renesas,cmt-48-r8a7797", "renesas,cmt-48-gen2"; -+ reg = <0 0xffca0000 0 0x1004>; ++ reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0051-arm64-renesas-r8a7798-Add-Renesas-R8A7798-SoC-suppor.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0051-arm64-renesas-r8a7798-Add-Renesas-R8A7798-SoC-suppor.patch index a4763d4..effd7e2 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0051-arm64-renesas-r8a7798-Add-Renesas-R8A7798-SoC-suppor.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0051-arm64-renesas-r8a7798-Add-Renesas-R8A7798-SoC-suppor.patch @@ -690,9 +690,9 @@ index 0000000..ee8e282 + }; + + -+ cmt0: timer@ffca0000 { ++ cmt0: timer@e60f0000 { + compatible = "renesas,cmt-48-r8a7798", "renesas,cmt-48-gen2"; -+ reg = <0 0xffca0000 0 0x1004>; ++ reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; |