summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorDuy Dang <duy.dang.yw@rvc.renesas.com>2019-02-15 16:16:32 +0700
committerThuy Tran <thuy.tran.xh@renesas.com>2019-05-23 16:11:57 +0700
commit62df1d0ddddcf65f37a30bd37be953abe12e7cbd (patch)
treebdaf948f314ee023dba8593b8a188d73ad462720
parentda84a3b8dab6053c494cce907dc829b2619ce650 (diff)
rcar-gen3: arm-trusted-firmware: Update SRCREV to Rev.2.0.3
This commit updates IPL and Secure Monitor to Rev.2.0.3 for the following changes: [IPL] - Add support for M3 Ver.1.3/3.0 - Add QoS setting for M3 Ver.3.0 - Add DDR setting for M3 Ver.3.0 - Add E3 Ver.1.1 to build option - Change periodic write DQ training option - Add new board revision for H3ULCB - Remove duplicate line in qos.mk - Change subslot cycle - Update DDR setting rev.0.35 - BL2/BL31: Update IPL and Secure Monitor Rev2.0.3 - BL31: Change to restore timer counter value at resume - BL31: Add DBSC4 setting before self-refresh mode [Secure Monitor] - Add SiP for getting board ID - Change Suspend To RAM function for M3 Ver.3.0 - Change condition of product code with cluster off function Change-Id: I9eb8e11e679742cf315089670dee1ae90954fc43 Signed-off-by: Duy Dang <duy.dang.yw@renesas.com> Signed-off-by: Khang Nguyen <khang.nguyen.xw@renesas.com> Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com> (cherry picked from commit 74e431ec9d3ea20c91cbd2fc6199794cbe43c720)
-rw-r--r--meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb2
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb b/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb
index b5509ad..6548376 100644
--- a/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb
+++ b/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb
@@ -13,7 +13,7 @@ S = "${WORKDIR}/git"
BRANCH = "rcar_gen3"
SRC_URI = "git://github.com/renesas-rcar/arm-trusted-firmware.git;branch=${BRANCH}"
-SRCREV = "556a11e73f3d94c7552251370f85ecf2c40ed625"
+SRCREV = "409c176d6714d132068412411c19392a3dcd7aa4"
PV = "v1.5+renesas+git${SRCPV}"