Add V3H support and Condor board

1) add uboot R-Car V3H SoC (r87798) and V3H based Condor board
2) add kernel R-Car V3H SoC (r87798) and V3H based Condor board

14 files changed, 11944 insertions, 8 deletions

diff --git a/meta-rcar-gen3-adas/conf/layer.conf b/meta-rcar-gen3-adas/conf/layer.conf
index 30ba1d7..f820387 100644
--- a/meta-rcar-gen3-adas/conf/layer.conf
+++ b/meta-rcar-gen3-adas/conf/layer.conf
@@ -78,6 +78,12 @@ IMAGE_INSTALL_append_r8a7797 += " \
     udev-rules-cvlib \
 "
 
+IMAGE_INSTALL_append_r8a7798 += " \
+    kernel-module-uio-imp \
+    kernel-module-cmemdrv \
+    udev-rules-cvlib \
+"
+
 DISTRO_FEATURES_remove="x11"
 DISTRO_FEATURES_append = " surroundview "
 DISTRO_FEATURES_append = " opencv-sdk "
diff --git a/meta-rcar-gen3-adas/conf/machine/condor.conf b/meta-rcar-gen3-adas/conf/machine/condor.conf
new file mode 100644
index 0000000..fc5e167
--- /dev/null
+++ b/meta-rcar-gen3-adas/conf/machine/condor.conf
@@ -0,0 +1,35 @@
+#@TYPE: Machine
+#@NAME: Condor machine
+#@DESCRIPTION: Machine configuration for running Condor
+
+DEFAULTTUNE ?= "cortexa53"
+require conf/machine/include/tune-cortexa53.inc
+require conf/machine/include/${SOC_FAMILY}.inc
+
+# 32BIT package install (default is disable)
+# This variables can be used only in multilib.
+USE_32BIT_PKGS ?= "0"
+USE_32BIT_WAYLAND ?= "0"
+USE_32BIT_MMP ?= "0"
+
+MACHINE_FEATURES = ""
+
+KERNEL_IMAGETYPE = "Image"
+IMAGE_FSTYPES = "tar.bz2 ext4 cpio.gz"
+
+SERIAL_CONSOLE = "115200 ttySC0"
+
+# Configuration for kernel
+PREFERRED_PROVIDER_virtual/kernel = "linux-renesas"
+KERNEL_DEVICETREE = "renesas/r8a7798-condor.dtb"
+
+# u-boot
+PREFERRED_VERSION_u-boot = "v2015.04%"
+EXTRA_IMAGEDEPENDS += " u-boot"
+UBOOT_MACHINE = "r8a7798_condor_defconfig"
+
+# libdrm
+PREFERRED_VERSION_libdrm = "2.4.68"
+
+# Add variable to Build Configuration in build log
+BUILDCFG_VARS_append = " SOC_FAMILY"
diff --git a/meta-rcar-gen3-adas/conf/machine/include/r8a7798.inc b/meta-rcar-gen3-adas/conf/machine/include/r8a7798.inc
new file mode 100644
index 0000000..e2cc4ac
--- /dev/null
+++ b/meta-rcar-gen3-adas/conf/machine/include/r8a7798.inc
@@ -0,0 +1,3 @@
+SOC_FAMILY =. "rcar-gen3:"
+require conf/machine/include/soc-family.inc
+LINUXLIBCVERSION = "4.9"
diff --git a/meta-rcar-gen3-adas/docs/sample/conf/condor/linaro-gcc/bsp/bblayers.conf b/meta-rcar-gen3-adas/docs/sample/conf/condor/linaro-gcc/bsp/bblayers.conf
new file mode 100644
index 0000000..96ff8ad
--- /dev/null
+++ b/meta-rcar-gen3-adas/docs/sample/conf/condor/linaro-gcc/bsp/bblayers.conf
@@ -0,0 +1,16 @@
+# POKY_BBLAYERS_CONF_VERSION is increased each time build/conf/bblayers.conf
+# changes incompatibly
+POKY_BBLAYERS_CONF_VERSION = "2"
+
+BBPATH = "${TOPDIR}"
+BBFILES ?= ""
+
+BBLAYERS ?= " \
+  ${TOPDIR}/../poky/meta \
+  ${TOPDIR}/../poky/meta-poky \
+  ${TOPDIR}/../poky/meta-yocto-bsp \
+  ${TOPDIR}/../meta-renesas/meta-rcar-gen3 \
+  ${TOPDIR}/../meta-linaro/meta-linaro-toolchain \
+  ${TOPDIR}/../meta-linaro/meta-optee \
+  ${TOPDIR}/../meta-openembedded/meta-oe \
+  "
diff --git a/meta-rcar-gen3-adas/docs/sample/conf/condor/linaro-gcc/bsp/local.conf b/meta-rcar-gen3-adas/docs/sample/conf/condor/linaro-gcc/bsp/local.conf
new file mode 100644
index 0000000..b7c3532
--- /dev/null
+++ b/meta-rcar-gen3-adas/docs/sample/conf/condor/linaro-gcc/bsp/local.conf
@@ -0,0 +1,267 @@
+#
+# This file is your local configuration file and is where all local user settings
+# are placed. The comments in this file give some guide to the options a new user
+# to the system might want to change but pretty much any configuration option can
+# be set in this file. More adventurous users can look at local.conf.extended
+# which contains other examples of configuration which can be placed in this file
+# but new users likely won't need any of them initially.
+#
+# Lines starting with the '#' character are commented out and in some cases the
+# default values are provided as comments to show people example syntax. Enabling
+# the option is a question of removing the # character and making any change to the
+# variable as required.
+
+#
+# Machine Selection
+#
+# You need to select a specific machine to target the build with. There are a selection
+# of emulated machines available which can boot and run in the QEMU emulator:
+#
+#MACHINE ?= "qemuarm"
+#MACHINE ?= "qemuarm64"
+#MACHINE ?= "qemumips"
+#MACHINE ?= "qemumips64"
+#MACHINE ?= "qemuppc"
+#MACHINE ?= "qemux86"
+#MACHINE ?= "qemux86-64"
+#
+# There are also the following hardware board target machines included for 
+# demonstration purposes:
+#
+#MACHINE ?= "beaglebone"
+#MACHINE ?= "genericx86"
+#MACHINE ?= "genericx86-64"
+#MACHINE ?= "mpc8315e-rdb"
+#MACHINE ?= "edgerouter"
+#
+# This sets the default machine to be qemux86 if no other machine is selected:
+MACHINE ??= "condor"
+
+SOC_FAMILY = "r8a7798"
+
+#
+# Where to place downloads
+#
+# During a first build the system will download many different source code tarballs
+# from various upstream projects. This can take a while, particularly if your network
+# connection is slow. These are all stored in DL_DIR. When wiping and rebuilding you
+# can preserve this directory to speed up this part of subsequent builds. This directory
+# is safe to share between multiple builds on the same machine too.
+#
+# The default is a downloads directory under TOPDIR which is the build directory.
+#
+#DL_DIR ?= "${TOPDIR}/downloads"
+
+#
+# Where to place shared-state files
+#
+# BitBake has the capability to accelerate builds based on previously built output.
+# This is done using "shared state" files which can be thought of as cache objects
+# and this option determines where those files are placed.
+#
+# You can wipe out TMPDIR leaving this directory intact and the build would regenerate
+# from these files if no changes were made to the configuration. If changes were made
+# to the configuration, only shared state files where the state was still valid would
+# be used (done using checksums).
+#
+# The default is a sstate-cache directory under TOPDIR.
+#
+#SSTATE_DIR ?= "${TOPDIR}/sstate-cache"
+
+#
+# Where to place the build output
+#
+# This option specifies where the bulk of the building work should be done and
+# where BitBake should place its temporary files and output. Keep in mind that
+# this includes the extraction and compilation of many applications and the toolchain
+# which can use Gigabytes of hard disk space.
+#
+# The default is a tmp directory under TOPDIR.
+#
+#TMPDIR = "${TOPDIR}/tmp"
+
+#
+# Default policy config
+#
+# The distribution setting controls which policy settings are used as defaults.
+# The default value is fine for general Yocto project use, at least initially.
+# Ultimately when creating custom policy, people will likely end up subclassing 
+# these defaults.
+#
+DISTRO ?= "poky"
+# As an example of a subclass there is a "bleeding" edge policy configuration
+# where many versions are set to the absolute latest code from the upstream 
+# source control systems. This is just mentioned here as an example, its not
+# useful to most new users.
+# DISTRO ?= "poky-bleeding"
+
+#
+# Package Management configuration
+#
+# This variable lists which packaging formats to enable. Multiple package backends
+# can be enabled at once and the first item listed in the variable will be used
+# to generate the root filesystems.
+# Options are:
+#  - 'package_deb' for debian style deb files
+#  - 'package_ipk' for ipk files are used by opkg (a debian style embedded package manager)
+#  - 'package_rpm' for rpm style packages
+# E.g.: PACKAGE_CLASSES ?= "package_rpm package_deb package_ipk"
+# We default to rpm:
+PACKAGE_CLASSES ?= "package_ipk"
+
+#
+# SDK target architecture
+#
+# This variable specifies the architecture to build SDK items for and means
+# you can build the SDK packages for architectures other than the machine you are
+# running the build on (i.e. building i686 packages on an x86_64 host).
+# Supported values are i686 and x86_64
+#SDKMACHINE ?= "i686"
+
+#
+# Extra image configuration defaults
+#
+# The EXTRA_IMAGE_FEATURES variable allows extra packages to be added to the generated
+# images. Some of these options are added to certain image types automatically. The
+# variable can contain the following options:
+#  "dbg-pkgs"       - add -dbg packages for all installed packages
+#                     (adds symbol information for debugging/profiling)
+#  "dev-pkgs"       - add -dev packages for all installed packages
+#                     (useful if you want to develop against libs in the image)
+#  "ptest-pkgs"     - add -ptest packages for all ptest-enabled packages
+#                     (useful if you want to run the package test suites)
+#  "tools-sdk"      - add development tools (gcc, make, pkgconfig etc.)
+#  "tools-debug"    - add debugging tools (gdb, strace)
+#  "eclipse-debug"  - add Eclipse remote debugging support
+#  "tools-profile"  - add profiling tools (oprofile, lttng, valgrind)
+#  "tools-testapps" - add useful testing tools (ts_print, aplay, arecord etc.)
+#  "debug-tweaks"   - make an image suitable for development
+#                     e.g. ssh root access has a blank password
+# There are other application targets that can be used here too, see
+# meta/classes/image.bbclass and meta/classes/core-image.bbclass for more details.
+# We default to enabling the debugging tweaks.
+EXTRA_IMAGE_FEATURES ?= "debug-tweaks"
+
+#
+# Additional image features
+#
+# The following is a list of additional classes to use when building images which
+# enable extra features. Some available options which can be included in this variable
+# are:
+#   - 'buildstats' collect build statistics
+#   - 'image-mklibs' to reduce shared library files size for an image
+#   - 'image-prelink' in order to prelink the filesystem image
+#   - 'image-swab' to perform host system intrusion detection
+# NOTE: if listing mklibs & prelink both, then make sure mklibs is before prelink
+# NOTE: mklibs also needs to be explicitly enabled for a given image, see local.conf.extended
+# image-prelink disabled for now due to issues with IFUNC symbol relocation
+USER_CLASSES ?= "buildstats image-mklibs"
+
+#
+# Runtime testing of images
+#
+# The build system can test booting virtual machine images under qemu (an emulator)
+# after any root filesystems are created and run tests against those images. To
+# enable this uncomment this line. See classes/testimage(-auto).bbclass for
+# further details.
+#TEST_IMAGE = "1"
+#
+# Interactive shell configuration
+#
+# Under certain circumstances the system may need input from you and to do this it
+# can launch an interactive shell. It needs to do this since the build is
+# multithreaded and needs to be able to handle the case where more than one parallel
+# process may require the user's attention. The default is iterate over the available
+# terminal types to find one that works.
+#
+# Examples of the occasions this may happen are when resolving patches which cannot
+# be applied, to use the devshell or the kernel menuconfig
+#
+# Supported values are auto, gnome, xfce, rxvt, screen, konsole (KDE 3.x only), none
+# Note: currently, Konsole support only works for KDE 3.x due to the way
+# newer Konsole versions behave
+#OE_TERMINAL = "auto"
+# By default disable interactive patch resolution (tasks will just fail instead):
+PATCHRESOLVE = "noop"
+
+#
+# Disk Space Monitoring during the build
+#
+# Monitor the disk space during the build. If there is less that 1GB of space or less
+# than 100K inodes in any key build location (TMPDIR, DL_DIR, SSTATE_DIR), gracefully
+# shutdown the build. If there is less that 100MB or 1K inodes, perform a hard abort
+# of the build. The reason for this is that running completely out of space can corrupt
+# files and damages the build in ways which may not be easily recoverable.
+# It's necesary to monitor /tmp, if there is no space left the build will fail
+# with very exotic errors.
+BB_DISKMON_DIRS = "\
+    STOPTASKS,${TMPDIR},1G,100K \
+    STOPTASKS,${DL_DIR},1G,100K \
+    STOPTASKS,${SSTATE_DIR},1G,100K \
+    STOPTASKS,/tmp,100M,100K \
+    ABORT,${TMPDIR},100M,1K \
+    ABORT,${DL_DIR},100M,1K \
+    ABORT,${SSTATE_DIR},100M,1K \
+    ABORT,/tmp,10M,1K"
+
+#
+# Shared-state files from other locations
+#
+# As mentioned above, shared state files are prebuilt cache data objects which can
+# used to accelerate build time. This variable can be used to configure the system
+# to search other mirror locations for these objects before it builds the data itself.
+#
+# This can be a filesystem directory, or a remote url such as http or ftp. These
+# would contain the sstate-cache results from previous builds (possibly from other
+# machines). This variable works like fetcher MIRRORS/PREMIRRORS and points to the
+# cache locations to check for the shared objects.
+# NOTE: if the mirror uses the same structure as SSTATE_DIR, you need to add PATH
+# at the end as shown in the examples below. This will be substituted with the
+# correct path within the directory structure.
+#SSTATE_MIRRORS ?= "\
+#file://.* http://someserver.tld/share/sstate/PATH;downloadfilename=PATH \n \
+#file://.* file:///some/local/dir/sstate/PATH"
+
+
+#
+# Qemu configuration
+#
+# By default qemu will build with a builtin VNC server where graphical output can be
+# seen. The two lines below enable the SDL backend too. By default libsdl-native will
+# be built, if you want to use your host's libSDL instead of the minimal libsdl built
+# by libsdl-native then uncomment the ASSUME_PROVIDED line below.
+PACKAGECONFIG_append_pn-qemu-native = " sdl"
+PACKAGECONFIG_append_pn-nativesdk-qemu = " sdl"
+#ASSUME_PROVIDED += "libsdl-native"
+
+# CONF_VERSION is increased each time build/conf/ changes incompatibly and is used to
+# track the version of this file when it was generated. This can safely be ignored if
+# this doesn't mean anything to you.
+CONF_VERSION = "1"
+
+# Add systemd configuration
+DISTRO_FEATURES_append = " systemd"
+VIRTUAL-RUNTIME_init_manager = "systemd"
+
+# Linaro GCC
+GCCVERSION = "linaro-5.2"
+
+# add the static lib to SDK toolchain
+SDKIMAGE_FEATURES_append = " staticdev-pkgs"
+
+# Disable optee in meta-linaro layer
+BBMASK = "meta-linaro/meta-optee/recipes-security/optee"
+
+# Mask graphic Pkgs
+BBMASK .= "|gles-user-module|kernel-module-gles|wayland-kms|libgbm"
+# Mask MMP recipes
+BBMASK .= "|kernel-module-uvcs-drv|omx-user-module"
+
+# Add for gstreamer plugins ugly
+LICENSE_FLAGS_WHITELIST = "commercial"
+
+# Linux ICCOM driver (RCG3ZLIDL4001ZNO)
+# Linux ICCOM library (RCG3ZLILL4001ZNO)
+#DISTRO_FEATURES_append = " iccom"
+
+IMAGE_INSTALL_remove = "optee-linuxdriver optee-linuxdriver-armtz optee-client"
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0018-arm-renesas-Add-Renesas-R8A7798-SoC-support.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0018-arm-renesas-Add-Renesas-R8A7798-SoC-support.patch
new file mode 100644
index 0000000..f4e3df6
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0018-arm-renesas-Add-Renesas-R8A7798-SoC-support.patch
@@ -0,0 +1,3889 @@
+From ff0bbc92aeb87872b0c8e7e05a1604bd8c1c3e98 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Mon, 22 Jan 2018 13:57:14 +0300
+Subject: [PATCH] arm: renesas: Add Renesas R8A7798 SoC support
+
+This adds Renesas R8A7798 SoC support
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Mikhail Ulyanov <mikhail.ulyanov@cogentembedded.com>
+---
+ arch/arm/cpu/armv8/Kconfig                         |    3 +
+ arch/arm/cpu/armv8/rcar_gen3/Makefile              |    3 +
+ arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c    |   40 +
+ arch/arm/cpu/armv8/rcar_gen3/cpu_info.c            |    8 +
+ arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c         | 3074 ++++++++++++++++++++
+ arch/arm/cpu/armv8/rcar_gen3/pfc.c                 |    2 +
+ arch/arm/include/asm/arch-rcar_gen3/gpio.h         |    4 +
+ arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h |  522 ++++
+ arch/arm/include/asm/arch-rcar_gen3/r8a7798.h      |   34 +
+ arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h    |    2 +
+ drivers/mtd/spi/sf_probe.c                         |    2 +-
+ drivers/net/sh_eth.h                               |    5 +-
+ drivers/serial/serial_sh.h                         |    2 +-
+ include/configs/rcar-gen3-common.h                 |    4 +
+ 14 files changed, 3701 insertions(+), 4 deletions(-)
+ create mode 100644 arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c
+ create mode 100644 arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c
+ create mode 100644 arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h
+ create mode 100644 arch/arm/include/asm/arch-rcar_gen3/r8a7798.h
+
+diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
+index 343b121..58a9259 100644
+--- a/arch/arm/cpu/armv8/Kconfig
++++ b/arch/arm/cpu/armv8/Kconfig
+@@ -44,6 +44,9 @@ config R8A77965
+ config R8A7797
+        bool "Renesas SoC R8A7797"
+ 
++config R8A7798
++       bool "Renesas SoC R8A7798"
++
+ endchoice
+ 
+ config SYS_SOC
+diff --git a/arch/arm/cpu/armv8/rcar_gen3/Makefile b/arch/arm/cpu/armv8/rcar_gen3/Makefile
+index a7a8f79..a8b7ddf 100644
+--- a/arch/arm/cpu/armv8/rcar_gen3/Makefile
++++ b/arch/arm/cpu/armv8/rcar_gen3/Makefile
+@@ -18,3 +18,6 @@ obj-$(CONFIG_R8A7796X) += lowlevel_init.o cpu_info-r8a7796.o \
+ obj-$(CONFIG_R8A7797) += lowlevel_init.o cpu_info-r8a7797.o \
+ 				pfc.o pfc-r8a7797.o prr_depend.o \
+ 				board.o
++obj-$(CONFIG_R8A7798) += lowlevel_init.o cpu_info-r8a7798.o \
++				pfc.o pfc-r8a7798.o prr_depend.o \
++				board.o
+diff --git a/arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c b/arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c
+new file mode 100644
+index 0000000..df94cd6
+--- /dev/null
++++ b/arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c
+@@ -0,0 +1,40 @@
++/*
++ * arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c
++ *	This file defines cpu information funstions.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++#include <common.h>
++#include <asm/io.h>
++
++#define PRR 0xFFF00044
++
++u32 rcar_get_cpu_type(void)
++{
++	u32 product;
++
++	product = readl(PRR);
++
++	return (product & 0x00007F00) >> 8;
++}
++
++u32 rcar_get_cpu_rev_integer(void)
++{
++	u32 product;
++
++	product = readl(PRR);
++
++	return (u32)(((product & 0x000000F0) >> 4) + 1);
++}
++
++u32 rcar_get_cpu_rev_fraction(void)
++{
++	u32 product;
++
++	product = readl(PRR);
++
++	return (u32)(product & 0x0000000F);
++}
+diff --git a/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c b/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c
+index 0046c75..a9366c0 100644
+--- a/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c
++++ b/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c
+@@ -89,6 +89,14 @@ int print_cpuinfo(void)
+ 			       CONFIG_RCAR_TARGET_STRING);
+ 		}
+ 		break;
++	case 0x56:
++		printf("CPU: Renesas Electronics R8A7798 rev %d.%d\n",
++		       rev_integer, rev_fraction);
++		if (strcmp(CONFIG_RCAR_TARGET_STRING, "r8a7798")) {
++			printf("Warning: this code supports only %s\n",
++			       CONFIG_RCAR_TARGET_STRING);
++		}
++		break;
+ 	}
+ 	return 0;
+ }
+diff --git a/arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c b/arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c
+new file mode 100644
+index 0000000..40444ba
+--- /dev/null
++++ b/arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c
+@@ -0,0 +1,3074 @@
++/*
++ * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c
++ *     This file is r8a7798 processor support - PFC hardware block.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <sh_pfc.h>
++#include <asm/gpio.h>
++
++#define CPU_32_PORT(fn, pfx, sfx)				\
++	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
++	PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),	\
++	PORT_1(fn, pfx##31, sfx)
++
++#define CPU_32_PORT1(fn, pfx, sfx)				\
++	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
++	PORT_10(fn, pfx##2, sfx)
++
++#define CPU_32_PORT2(fn, pfx, sfx)				\
++	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
++	PORT_10(fn, pfx##2, sfx)
++
++#define CPU_32_PORT_30(fn, pfx, sfx)				\
++	PORT_10(fn, pfx, sfx),					\
++	PORT_10(fn, pfx##1, sfx),				\
++	PORT_10(fn, pfx##2, sfx)
++
++#define CPU_32_PORT_28(fn, pfx, sfx)				\
++	PORT_10(fn, pfx, sfx),					\
++	PORT_10(fn, pfx##1, sfx),				\
++	PORT_1(fn, pfx##20, sfx),				\
++	PORT_1(fn, pfx##21, sfx),				\
++	PORT_1(fn, pfx##22, sfx),				\
++	PORT_1(fn, pfx##23, sfx),				\
++	PORT_1(fn, pfx##24, sfx),				\
++	PORT_1(fn, pfx##25, sfx),				\
++	PORT_1(fn, pfx##26, sfx),				\
++	PORT_1(fn, pfx##27, sfx)
++
++#define CPU_32_PORT_25(fn, pfx, sfx)				\
++	PORT_10(fn, pfx, sfx),					\
++	PORT_10(fn, pfx##1, sfx),				\
++	PORT_1(fn, pfx##20, sfx),				\
++	PORT_1(fn, pfx##21, sfx),				\
++	PORT_1(fn, pfx##22, sfx),				\
++	PORT_1(fn, pfx##23, sfx),				\
++	PORT_1(fn, pfx##24, sfx)
++
++#define CPU_32_PORT_22(fn, pfx, sfx)				\
++	PORT_10(fn, pfx, sfx),					\
++	PORT_10(fn, pfx##1, sfx),				\
++	PORT_1(fn, pfx##20, sfx),				\
++	PORT_1(fn, pfx##21, sfx)
++
++#define CPU_32_PORT_17(fn, pfx, sfx)				\
++	PORT_10(fn, pfx, sfx),					\
++	PORT_1(fn, pfx##10, sfx),				\
++	PORT_1(fn, pfx##11, sfx),				\
++	PORT_1(fn, pfx##12, sfx),				\
++	PORT_1(fn, pfx##13, sfx),				\
++	PORT_1(fn, pfx##14, sfx),				\
++	PORT_1(fn, pfx##15, sfx),				\
++	PORT_1(fn, pfx##16, sfx)
++
++#define CPU_32_PORT_15(fn, pfx, sfx)				\
++	PORT_10(fn, pfx, sfx),					\
++	PORT_1(fn, pfx##10, sfx),				\
++	PORT_1(fn, pfx##11, sfx),				\
++	PORT_1(fn, pfx##12, sfx),				\
++	PORT_1(fn, pfx##13, sfx),				\
++	PORT_1(fn, pfx##14, sfx)
++
++#define CPU_ALL_PORT(fn, pfx, sfx)		\
++	CPU_32_PORT_22(fn, pfx##_0_, sfx),	\
++	CPU_32_PORT_28(fn, pfx##_1_, sfx),	\
++	CPU_32_PORT_30(fn, pfx##_2_, sfx),	\
++	CPU_32_PORT_17(fn, pfx##_3_, sfx),	\
++	CPU_32_PORT_25(fn, pfx##_4_, sfx),	\
++	CPU_32_PORT_15(fn, pfx##_5_, sfx)
++
++#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
++#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,	\
++				       GP##pfx##_IN, GP##pfx##_OUT)
++
++#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
++#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
++
++#define GP_ALL(str)	CPU_ALL_PORT(_PORT_ALL, GP, str)
++#define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, , unused)
++#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, , unused)
++
++
++#define PORT_10_REV(fn, pfx, sfx)				\
++	PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),	\
++	PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),	\
++	PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),	\
++	PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),	\
++	PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
++
++#define CPU_32_PORT_REV(fn, pfx, sfx)					\
++	PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),		\
++	PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),	\
++	PORT_10_REV(fn, pfx, sfx)
++
++#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
++#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
++
++#define PINMUX_IPSR_IDATA(fn)			PINMUX_DATA(fn##_IMARK, GFN_##fn, IFN_##fn)
++#define PINMUX_IPSR_DATA(ipsr, fn)		PINMUX_DATA(fn##_MARK, GFN_##ipsr, FN_##fn)
++#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms)	PINMUX_DATA(fn##_MARK, FN_##ms, \
++							    FN_##ipsr, FN_##fn)
++
++enum {
++	PINMUX_RESERVED = 0,
++
++	PINMUX_DATA_BEGIN,
++	GP_ALL(DATA),
++	PINMUX_DATA_END,
++
++	PINMUX_INPUT_BEGIN,
++	GP_ALL(IN),
++	PINMUX_INPUT_END,
++
++	PINMUX_OUTPUT_BEGIN,
++	GP_ALL(OUT),
++	PINMUX_OUTPUT_END,
++
++	PINMUX_FUNCTION_BEGIN,
++	GP_ALL(FN),
++
++	/* GPSR0 */
++	GFN_DU_EXODDF_DU_ODDF_DISP_CDE,
++	GFN_DU_EXVSYNC_DU_VSYNC,
++	GFN_DU_EXHSYNC_DU_HSYNC,
++	GFN_DU_DOTCLKOUT,
++	GFN_DU_DB7,
++	GFN_DU_DB6,
++	GFN_DU_DB5,
++	GFN_DU_DB4,
++	GFN_DU_DB3,
++	GFN_DU_DB2,
++	GFN_DU_DG7,
++	GFN_DU_DG6,
++	GFN_DU_DG5,
++	GFN_DU_DG4,
++	GFN_DU_DG3,
++	GFN_DU_DG2,
++	GFN_DU_DR7,
++	GFN_DU_DR6,
++	GFN_DU_DR5,
++	GFN_DU_DR4,
++	GFN_DU_DR3,
++	GFN_DU_DR2,
++
++	/* GPSR1 */
++	GFN_DIGRF_CLKOUT,
++	GFN_DIGRF_CLKIN,
++	GFN_CANFD_CLK_A,
++	GFN_CANFD1_RX,
++	GFN_CANFD1_TX,
++	GFN_CANFD0_RX_A,
++	GFN_CANFD0_TX_A,
++	GFN_AVB0_AVTP_CAPTURE,
++	GFN_AVB0_AVTP_MATCH,
++	FN_AVB0_LINK,
++	FN_AVB0_PHY_INT,
++	FN_AVB0_MAGIC,
++	FN_AVB0_MDC,
++	FN_AVB0_MDIO,
++	FN_AVB0_TXCREFCLK,
++	FN_AVB0_TD3,
++	FN_AVB0_TD2,
++	FN_AVB0_TD1,
++	FN_AVB0_TD0,
++	FN_AVB0_TXC,
++	FN_AVB0_TX_CTL,
++	FN_AVB0_RD3,
++	FN_AVB0_RD2,
++	FN_AVB0_RD1,
++	FN_AVB0_RD0,
++	FN_AVB0_RXC,
++	FN_AVB0_RX_CTL,
++	GFN_IRQ0,
++
++	/* GPSR2 */
++	GFN_FSO_TOE_N,
++	GFN_FSO_CFE_1_N,
++	GFN_FSO_CFE_0_N,
++	GFN_SDA3,
++	GFN_SCL3,
++	GFN_MSIOF0_SS2,
++	GFN_MSIOF0_SS1,
++	GFN_MSIOF0_SYNC,
++	GFN_MSIOF0_SCK,
++	GFN_MSIOF0_TXD,
++	GFN_MSIOF0_RXD,
++	GFN_IRQ5,
++	GFN_IRQ4,
++	GFN_VI0_FIELD,
++	GFN_VI0_DATA11,
++	GFN_VI0_DATA10,
++	GFN_VI0_DATA9,
++	GFN_VI0_DATA8,
++	GFN_VI0_DATA7,
++	GFN_VI0_DATA6,
++	GFN_VI0_DATA5,
++	GFN_VI0_DATA4,
++	GFN_VI0_DATA3,
++	GFN_VI0_DATA2,
++	GFN_VI0_DATA1,
++	GFN_VI0_DATA0,
++	GFN_VI0_VSYNC_N,
++	GFN_VI0_HSYNC_N,
++	GFN_VI0_CLKENB,
++	GFN_VI0_CLK,
++
++	/* GPSR3 */
++	GFN_VI1_FIELD,
++	GFN_VI1_DATA11,
++	GFN_VI1_DATA10,
++	GFN_VI1_DATA9,
++	GFN_VI1_DATA8,
++	GFN_VI1_DATA7,
++	GFN_VI1_DATA6,
++	GFN_VI1_DATA5,
++	GFN_VI1_DATA4,
++	GFN_VI1_DATA3,
++	GFN_VI1_DATA2,
++	GFN_VI1_DATA1,
++	GFN_VI1_DATA0,
++	GFN_VI1_VSYNC_N,
++	GFN_VI1_HSYNC_N,
++	GFN_VI1_CLKENB,
++	GFN_VI1_CLK,
++
++	/* GPSR4 */
++	FN_GETHER_LINK_A,
++	FN_GETHER_PHY_INT_A,
++	FN_GETHER_MAGIC,
++	FN_GETHER_MDC_A,
++	FN_GETHER_MDIO_A,
++	FN_GETHER_TXCREFCLK_MEGA,
++	FN_GETHER_TXCREFCLK,
++	FN_GETHER_TD3,
++	FN_GETHER_TD2,
++	FN_GETHER_TD1,
++	FN_GETHER_TD0,
++	FN_GETHER_TXC,
++	FN_GETHER_TX_CTL,
++	FN_GETHER_RD3,
++	FN_GETHER_RD2,
++	FN_GETHER_RD1,
++	FN_GETHER_RD0,
++	FN_GETHER_RXC,
++	FN_GETHER_RX_CTL,
++	GFN_SDA2,
++	GFN_SCL2,
++	GFN_SDA1,
++	GFN_SCL1,
++	GFN_SDA0,
++	GFN_SCL0,
++
++	/* GPSR5 */
++	FN_RPC_INT_N,
++	FN_RPC_WP_N,
++	FN_RPC_RESET_N,
++	FN_QSPI1_SSL,
++	FN_QSPI1_IO3,
++	FN_QSPI1_IO2,
++	FN_QSPI1_MISO_IO1,
++	FN_QSPI1_MOSI_IO0,
++	FN_QSPI1_SPCLK,
++	FN_QSPI0_SSL,
++	FN_QSPI0_IO3,
++	FN_QSPI0_IO2,
++	FN_QSPI0_MISO_IO1,
++	FN_QSPI0_MOSI_IO0,
++	FN_QSPI0_SPCLK,
++
++	/* IPSR0 */
++	IFN_DU_DR2,
++	FN_SCK4,
++	FN_GETHER_RMII_CRS_DV,
++	FN_A0,
++	IFN_DU_DR3,
++	FN_RX4,
++	FN_GETHER_RMII_RX_ER,
++	FN_A1,
++	IFN_DU_DR4,
++	FN_TX4,
++	FN_GETHER_RMII_RXD0,
++	FN_A2,
++	IFN_DU_DR5,
++	FN_CTS4_N,
++	FN_GETHER_RMII_RXD1,
++	FN_A3,
++	IFN_DU_DR6,
++	FN_RTS4_N_TANS,
++	FN_GETHER_RMII_TXD_EN,
++	FN_A4,
++	IFN_DU_DR7,
++	FN_GETHER_RMII_TXD0,
++	FN_A5,
++	IFN_DU_DG2,
++	FN_GETHER_RMII_TXD1,
++	FN_A6,
++	IFN_DU_DG3,
++	FN_CPG_CPCKOUT,
++	FN_GETHER_RMII_REFCLK,
++	FN_A7,
++	FN_PWMFSW0,
++
++	/* IPSR1 */
++	IFN_DU_DG4,
++	FN_SCL5,
++	FN_A8,
++	IFN_DU_DG5,
++	FN_SDA5,
++	FN_GETHER_MDC_B,
++	FN_A9,
++	IFN_DU_DG6,
++	FN_SCIF_CLK_A,
++	FN_GETHER_MDIO_B,
++	FN_A10,
++	IFN_DU_DG7,
++	FN_HRX0_A,
++	FN_A11,
++	IFN_DU_DB2,
++	FN_HSCK0_A,
++	FN_A12,
++	FN_IRQ1,
++	IFN_DU_DB3,
++	FN_HRTS0_N_A,
++	FN_A13,
++	FN_IRQ2,
++	IFN_DU_DB4,
++	FN_HCTS0_N_A,
++	FN_A14,
++	FN_IRQ3,
++	IFN_DU_DB5,
++	FN_HTX0_A,
++	FN_PWM0_A,
++	FN_A15,
++
++	/* IPSR2 */
++	IFN_DU_DB6,
++	FN_MSIOF3_RXD,
++	FN_A16,
++	IFN_DU_DB7,
++	FN_MSIOF3_TXD,
++	FN_A17,
++	IFN_DU_DOTCLKOUT,
++	FN_MSIOF3_SS1,
++	FN_GETHER_LINK_B,
++	FN_A18,
++	IFN_DU_EXHSYNC_DU_HSYNC,
++	FN_MSIOF3_SS2,
++	FN_GETHER_PHY_INT_B,
++	FN_A19,
++	FN_FXR_TXENA_N,
++	IFN_DU_EXVSYNC_DU_VSYNC,
++	FN_MSIOF3_SCK,
++	FN_FXR_TXENB_N,
++	IFN_DU_EXODDF_DU_ODDF_DISP_CDE,
++	FN_MSIOF3_SYNC,
++	IFN_IRQ0,
++	FN_CC5_OSCOUT,
++	IFN_VI0_CLK,
++	FN_MSIOF2_SCK,
++	FN_SCK3,
++	FN_HSCK3,
++
++	/* IPSR3 */
++	IFN_VI0_CLKENB,
++	FN_MSIOF2_RXD,
++	FN_RX3,
++	FN_RD_WR_N,
++	FN_HCTS3_N,
++	IFN_VI0_HSYNC_N,
++	FN_MSIOF2_TXD,
++	FN_TX3,
++	FN_HRTS3_N,
++	IFN_VI0_VSYNC_N,
++	FN_MSIOF2_SYNC,
++	FN_CTS3_N,
++	FN_HTX3,
++	IFN_VI0_DATA0,
++	FN_MSIOF2_SS1,
++	FN_RTS3_N_TANS,
++	FN_HRX3,
++	IFN_VI0_DATA1,
++	FN_MSIOF2_SS2,
++	FN_SCK1,
++	FN_SPEEDIN_A,
++	IFN_VI0_DATA2,
++	FN_AVB0_AVTP_PPS,
++	IFN_VI0_DATA3,
++	FN_HSCK1,
++	IFN_VI0_DATA4,
++	FN_HRTS1_N,
++	FN_RX1_A,
++
++	/* IPSR4 */
++	IFN_VI0_DATA5,
++	FN_HCTS1_N,
++	FN_TX1_A,
++	IFN_VI0_DATA6,
++	FN_HTX1,
++	FN_CTS1_N,
++	IFN_VI0_DATA7,
++	FN_HRX1,
++	FN_RTS1_N_TANS,
++	IFN_VI0_DATA8,
++	FN_HSCK2,
++	IFN_VI0_DATA9,
++	FN_HCTS2_N,
++	FN_PWM1_A,
++	FN_FSO_CFE_0_N_B,
++	IFN_VI0_DATA10,
++	FN_HRTS2_N,
++	FN_PWM2_A,
++	IFN_VI0_DATA11,
++	FN_HTX2,
++	FN_PWM3_A,
++	IFN_VI0_FIELD,
++	FN_HRX2,
++	FN_PWM4_A,
++	FN_CS1_N,
++	FN_FSCLKST2_N_A,
++
++	/* IPSR5 */
++	IFN_VI1_CLK,
++	FN_MSIOF1_RXD,
++	FN_CS0_N,
++	IFN_VI1_CLKENB,
++	FN_MSIOF1_TXD,
++	FN_D0,
++	IFN_VI1_HSYNC_N,
++	FN_MSIOF1_SCK,
++	FN_D1,
++	IFN_VI1_VSYNC_N,
++	FN_MSIOF1_SYNC,
++	FN_D2,
++	IFN_VI1_DATA0,
++	FN_MSIOF1_SS1,
++	FN_D3,
++	FN_MMC_WP,
++	IFN_VI1_DATA1,
++	FN_MSIOF1_SS2,
++	FN_D4,
++	FN_MMC_CD,
++	IFN_VI1_DATA2,
++	FN_CANFD0_TX_B,
++	FN_D5,
++	FN_MMC_DS,
++	IFN_VI1_DATA3,
++	FN_CANFD0_RX_B,
++	FN_D6,
++	FN_MMC_CMD,
++
++	/* IPSR6 */
++	IFN_VI1_DATA4,
++	FN_CANFD_CLK_B,
++	FN_D7,
++	FN_MMC_D0,
++	IFN_VI1_DATA5,
++	FN_D8,
++	FN_MMC_D1,
++	IFN_VI1_DATA6,
++	FN_D9,
++	FN_MMC_D2,
++	IFN_VI1_DATA7,
++	FN_D10,
++	FN_MMC_D3,
++	IFN_VI1_DATA8,
++	FN_D11,
++	FN_MMC_CLK,
++	IFN_VI1_DATA9,
++	FN_TCLK1_A,
++	FN_D12,
++	FN_MMC_D4,
++	IFN_VI1_DATA10,
++	FN_TCLK2_A,
++	FN_D13,
++	FN_MMC_D5,
++	IFN_VI1_DATA11,
++	FN_SCL4,
++	FN_D14,
++	FN_MMC_D6,
++
++	/* IPSR7 */
++	IFN_VI1_FIELD,
++	FN_SDA4,
++	FN_D15,
++	FN_MMC_D7,
++	IFN_SCL0,
++	FN_CLKOUT,
++	IFN_SDA0,
++	FN_BS_N,
++	FN_SCK0,
++	FN_HSCK0_B,
++	IFN_SCL1,
++	FN_TPU0TO2,
++	FN_RD_N,
++	FN_CTS0_N,
++	FN_HCTS0_N_B,
++	IFN_SDA1,
++	FN_TPU0TO3,
++	FN_WE0_N,
++	FN_RTS0_N_TANS,
++	FN_HRTS0_N_B,
++	IFN_SCL2,
++	FN_WE1_N,
++	FN_RX0,
++	FN_HRX0_B,
++	IFN_SDA2,
++	FN_EX_WAIT0,
++	FN_TX0,
++	FN_HTX0_B,
++	IFN_AVB0_AVTP_MATCH,
++	FN_TPU0TO0,
++
++	/* IPSR8 */
++	IFN_AVB0_AVTP_CAPTURE,
++	FN_TPU0TO1,
++	IFN_CANFD0_TX_A,
++	FN_FXR_TXDA,
++	FN_PWM0_B,
++	FN_DU_DISP,
++	IFN_CANFD0_RX_A,
++	FN_RXDA_EXTFXR,
++	FN_PWM1_B,
++	FN_DU_CDE,
++	IFN_CANFD1_TX,
++	FN_FXR_TXDB,
++	FN_PWM2_B,
++	FN_TCLK1_B,
++	FN_TX1_B,
++	IFN_CANFD1_RX,
++	FN_RXDB_EXTFXR,
++	FN_PWM3_B,
++	FN_TCLK2_B,
++	FN_RX1_B,
++	IFN_CANFD_CLK_A,
++	FN_CLK_EXTFXR,
++	FN_PWM4_B,
++	FN_SPEEDIN_B,
++	FN_SCIF_CLK_B,
++	IFN_DIGRF_CLKIN,
++	FN_DIGRF_CLKEN_IN,
++	IFN_DIGRF_CLKOUT,
++	FN_DIGRF_CLKEN_OUT,
++
++	/* IPSR9 */
++	IFN_IRQ4,
++	FN_VI0_DATA12,
++	IFN_IRQ5,
++	FN_VI0_DATA13,
++	IFN_MSIOF0_RXD,
++	FN_DU_DR0,
++	FN_VI0_DATA14,
++	IFN_MSIOF0_TXD,
++	FN_DU_DR1,
++	FN_VI0_DATA15,
++	IFN_MSIOF0_SCK,
++	FN_DU_DG0,
++	FN_VI0_DATA16,
++	IFN_MSIOF0_SYNC,
++	FN_DU_DG1,
++	FN_VI0_DATA17,
++	IFN_MSIOF0_SS1,
++	FN_DU_DB0,
++	FN_TCLK3,
++	FN_VI0_DATA18,
++	IFN_MSIOF0_SS2,
++	FN_DU_DB1,
++	FN_TCLK4,
++	FN_VI0_DATA19,
++
++	/* IPSR10 */
++	IFN_SCL3,
++	FN_VI0_DATA20,
++	IFN_SDA3,
++	FN_VI0_DATA21,
++	IFN_FSO_CFE_0_N,
++	FN_VI0_DATA22,
++	IFN_FSO_CFE_1_N,
++	FN_VI0_DATA23,
++	IFN_FSO_TOE_N,
++
++	/* MOD_SEL0 */
++	FN_SEL_CANFD0_0, FN_SEL_CANFD0_1,
++	FN_SEL_GETHER_0, FN_SEL_GETHER_1,
++	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
++	FN_SEL_PWM0_0, FN_SEL_PWM0_1,
++	FN_SEL_PWM1_0, FN_SEL_PWM1_1,
++	FN_SEL_PWM2_0, FN_SEL_PWM2_1,
++	FN_SEL_PWM3_0, FN_SEL_PWM3_1,
++	FN_SEL_PWM4_0, FN_SEL_PWM4_1,
++	FN_SEL_RSP_0, FN_SEL_RSP_1,
++	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1,
++	FN_SEL_TMU_0, FN_SEL_TMU_1,
++
++	PINMUX_FUNCTION_END,
++
++	PINMUX_MARK_BEGIN,
++
++	/* GPSR0 */
++	DU_EXODDF_DU_ODDF_DISP_CDE_GMARK,
++	DU_EXVSYNC_DU_VSYNC_GMARK,
++	DU_EXHSYNC_DU_HSYNC_GMARK,
++	DU_DOTCLKOUT_GMARK,
++	DU_DB7_GMARK,
++	DU_DB6_GMARK,
++	DU_DB5_GMARK,
++	DU_DB4_GMARK,
++	DU_DB3_GMARK,
++	DU_DB2_GMARK,
++	DU_DG7_GMARK,
++	DU_DG6_GMARK,
++	DU_DG5_GMARK,
++	DU_DG4_GMARK,
++	DU_DG3_GMARK,
++	DU_DG2_GMARK,
++	DU_DR7_GMARK,
++	DU_DR6_GMARK,
++	DU_DR5_GMARK,
++	DU_DR4_GMARK,
++	DU_DR3_GMARK,
++	DU_DR2_GMARK,
++
++	/* GPSR1 */
++	DIGRF_CLKOUT_GMARK,
++	DIGRF_CLKIN_GMARK,
++	CANFD_CLK_A_GMARK,
++	CANFD1_RX_GMARK,
++	CANFD1_TX_GMARK,
++	CANFD0_RX_A_GMARK,
++	CANFD0_TX_A_GMARK,
++	AVB0_AVTP_CAPTURE_GMARK,
++	AVB0_AVTP_MATCH_GMARK,
++	AVB0_LINK_MARK,
++	AVB0_PHY_INT_MARK,
++	AVB0_MAGIC_MARK,
++	AVB0_MDC_MARK,
++	AVB0_MDIO_MARK,
++	AVB0_TXCREFCLK_MARK,
++	AVB0_TD3_MARK,
++	AVB0_TD2_MARK,
++	AVB0_TD1_MARK,
++	AVB0_TD0_MARK,
++	AVB0_TXC_MARK,
++	AVB0_TX_CTL_MARK,
++	AVB0_RD3_MARK,
++	AVB0_RD2_MARK,
++	AVB0_RD1_MARK,
++	AVB0_RD0_MARK,
++	AVB0_RXC_MARK,
++	AVB0_RX_CTL_MARK,
++	IRQ0_GMARK,
++
++	/* GPSR2 */
++	FSO_TOE_N_GMARK,
++	FSO_CFE_1_N_GMARK,
++	FSO_CFE_0_N_GMARK,
++	SDA3_GMARK,
++	SCL3_GMARK,
++	MSIOF0_SS2_GMARK,
++	MSIOF0_SS1_GMARK,
++	MSIOF0_SYNC_GMARK,
++	MSIOF0_SCK_GMARK,
++	MSIOF0_TXD_GMARK,
++	MSIOF0_RXD_GMARK,
++	IRQ5_GMARK,
++	IRQ4_GMARK,
++	VI0_FIELD_GMARK,
++	VI0_DATA11_GMARK,
++	VI0_DATA10_GMARK,
++	VI0_DATA9_GMARK,
++	VI0_DATA8_GMARK,
++	VI0_DATA7_GMARK,
++	VI0_DATA6_GMARK,
++	VI0_DATA5_GMARK,
++	VI0_DATA4_GMARK,
++	VI0_DATA3_GMARK,
++	VI0_DATA2_GMARK,
++	VI0_DATA1_GMARK,
++	VI0_DATA0_GMARK,
++	VI0_VSYNC_N_GMARK,
++	VI0_HSYNC_N_GMARK,
++	VI0_CLKENB_GMARK,
++	VI0_CLK_GMARK,
++
++	/* GPSR3 */
++	VI1_FIELD_GMARK,
++	VI1_DATA11_GMARK,
++	VI1_DATA10_GMARK,
++	VI1_DATA9_GMARK,
++	VI1_DATA8_GMARK,
++	VI1_DATA7_GMARK,
++	VI1_DATA6_GMARK,
++	VI1_DATA5_GMARK,
++	VI1_DATA4_GMARK,
++	VI1_DATA3_GMARK,
++	VI1_DATA2_GMARK,
++	VI1_DATA1_GMARK,
++	VI1_DATA0_GMARK,
++	VI1_VSYNC_N_GMARK,
++	VI1_HSYNC_N_GMARK,
++	VI1_CLKENB_GMARK,
++	VI1_CLK_GMARK,
++
++	/* GPSR4 */
++	GETHER_LINK_A_MARK,
++	GETHER_PHY_INT_A_MARK,
++	GETHER_MAGIC_MARK,
++	GETHER_MDC_A_MARK,
++	GETHER_MDIO_A_MARK,
++	GETHER_TXCREFCLK_MEGA_MARK,
++	GETHER_TXCREFCLK_MARK,
++	GETHER_TD3_MARK,
++	GETHER_TD2_MARK,
++	GETHER_TD1_MARK,
++	GETHER_TD0_MARK,
++	GETHER_TXC_MARK,
++	GETHER_TX_CTL_MARK,
++	GETHER_RD3_MARK,
++	GETHER_RD2_MARK,
++	GETHER_RD1_MARK,
++	GETHER_RD0_MARK,
++	GETHER_RXC_MARK,
++	GETHER_RX_CTL_MARK,
++	SDA2_GMARK,
++	SCL2_GMARK,
++	SDA1_GMARK,
++	SCL1_GMARK,
++	SDA0_GMARK,
++	SCL0_GMARK,
++
++	/* GPSR5 */
++	RPC_INT_N_MARK,
++	RPC_WP_N_MARK,
++	RPC_RESET_N_MARK,
++	QSPI1_SSL_MARK,
++	QSPI1_IO3_MARK,
++	QSPI1_IO2_MARK,
++	QSPI1_MISO_IO1_MARK,
++	QSPI1_MOSI_IO0_MARK,
++	QSPI1_SPCLK_MARK,
++	QSPI0_SSL_MARK,
++	QSPI0_IO3_MARK,
++	QSPI0_IO2_MARK,
++	QSPI0_MISO_IO1_MARK,
++	QSPI0_MOSI_IO0_MARK,
++	QSPI0_SPCLK_MARK,
++
++	/* IPSR0 */
++	DU_DR2_IMARK,
++	SCK4_MARK,
++	GETHER_RMII_CRS_DV_MARK,
++	A0_MARK,
++	DU_DR3_IMARK,
++	RX4_MARK,
++	GETHER_RMII_RX_ER_MARK,
++	A1_MARK,
++	DU_DR4_IMARK,
++	TX4_MARK,
++	GETHER_RMII_RXD0_MARK,
++	A2_MARK,
++	DU_DR5_IMARK,
++	CTS4_N_MARK,
++	GETHER_RMII_RXD1_MARK,
++	A3_MARK,
++	DU_DR6_IMARK,
++	RTS4_N_TANS_MARK,
++	GETHER_RMII_TXD_EN_MARK,
++	A4_MARK,
++	DU_DR7_IMARK,
++	GETHER_RMII_TXD0_MARK,
++	A5_MARK,
++	DU_DG2_IMARK,
++	GETHER_RMII_TXD1_MARK,
++	A6_MARK,
++	DU_DG3_IMARK,
++	CPG_CPCKOUT_MARK,
++	GETHER_RMII_REFCLK_MARK,
++	A7_MARK,
++	PWMFSW0_MARK,
++
++	/* IPSR1 */
++	DU_DG4_IMARK,
++	SCL5_MARK,
++	A8_MARK,
++	DU_DG5_IMARK,
++	SDA5_MARK,
++	GETHER_MDC_B_MARK,
++	A9_MARK,
++	DU_DG6_IMARK,
++	SCIF_CLK_A_MARK,
++	GETHER_MDIO_B_MARK,
++	A10_MARK,
++	DU_DG7_IMARK,
++	HRX0_A_MARK,
++	A11_MARK,
++	DU_DB2_IMARK,
++	HSCK0_A_MARK,
++	A12_MARK,
++	IRQ1_MARK,
++	DU_DB3_IMARK,
++	HRTS0_N_A_MARK,
++	A13_MARK,
++	IRQ2_MARK,
++	DU_DB4_IMARK,
++	HCTS0_N_A_MARK,
++	A14_MARK,
++	IRQ3_MARK,
++	DU_DB5_IMARK,
++	HTX0_A_MARK,
++	PWM0_A_MARK,
++	A15_MARK,
++
++	/* IPSR2 */
++	DU_DB6_IMARK,
++	MSIOF3_RXD_MARK,
++	A16_MARK,
++	DU_DB7_IMARK,
++	MSIOF3_TXD_MARK,
++	A17_MARK,
++	DU_DOTCLKOUT_IMARK,
++	MSIOF3_SS1_MARK,
++	GETHER_LINK_B_MARK,
++	A18_MARK,
++	DU_EXHSYNC_DU_HSYNC_IMARK,
++	MSIOF3_SS2_MARK,
++	GETHER_PHY_INT_B_MARK,
++	A19_MARK,
++	FXR_TXENA_N_MARK,
++	DU_EXVSYNC_DU_VSYNC_IMARK,
++	MSIOF3_SCK_MARK,
++	FXR_TXENB_N_MARK,
++	DU_EXODDF_DU_ODDF_DISP_CDE_IMARK,
++	MSIOF3_SYNC_MARK,
++	IRQ0_IMARK,
++	CC5_OSCOUT_MARK,
++	VI0_CLK_IMARK,
++	MSIOF2_SCK_MARK,
++	SCK3_MARK,
++	HSCK3_MARK,
++
++	/* IPSR3 */
++	VI0_CLKENB_IMARK,
++	MSIOF2_RXD_MARK,
++	RX3_MARK,
++	RD_WR_N_MARK,
++	HCTS3_N_MARK,
++	VI0_HSYNC_N_IMARK,
++	MSIOF2_TXD_MARK,
++	TX3_MARK,
++	HRTS3_N_MARK,
++	VI0_VSYNC_N_IMARK,
++	MSIOF2_SYNC_MARK,
++	CTS3_N_MARK,
++	HTX3_MARK,
++	VI0_DATA0_IMARK,
++	MSIOF2_SS1_MARK,
++	RTS3_N_TANS_MARK,
++	HRX3_MARK,
++	VI0_DATA1_IMARK,
++	MSIOF2_SS2_MARK,
++	SCK1_MARK,
++	SPEEDIN_A_MARK,
++	VI0_DATA2_IMARK,
++	AVB0_AVTP_PPS_MARK,
++	VI0_DATA3_IMARK,
++	HSCK1_MARK,
++	VI0_DATA4_IMARK,
++	HRTS1_N_MARK,
++	RX1_A_MARK,
++
++	/* IPSR4 */
++	VI0_DATA5_IMARK,
++	HCTS1_N_MARK,
++	TX1_A_MARK,
++	VI0_DATA6_IMARK,
++	HTX1_MARK,
++	CTS1_N_MARK,
++	VI0_DATA7_IMARK,
++	HRX1_MARK,
++	RTS1_N_TANS_MARK,
++	VI0_DATA8_IMARK,
++	HSCK2_MARK,
++	VI0_DATA9_IMARK,
++	HCTS2_N_MARK,
++	PWM1_A_MARK,
++	FSO_CFE_0_N_B_MARK,
++	VI0_DATA10_IMARK,
++	HRTS2_N_MARK,
++	PWM2_A_MARK,
++	VI0_DATA11_IMARK,
++	HTX2_MARK,
++	PWM3_A_MARK,
++	VI0_FIELD_IMARK,
++	HRX2_MARK,
++	PWM4_A_MARK,
++	CS1_N_MARK,
++	FSCLKST2_N_A_MARK,
++
++	/* IPSR5 */
++	VI1_CLK_IMARK,
++	MSIOF1_RXD_MARK,
++	CS0_N_MARK,
++	VI1_CLKENB_IMARK,
++	MSIOF1_TXD_MARK,
++	D0_MARK,
++	VI1_HSYNC_N_IMARK,
++	MSIOF1_SCK_MARK,
++	D1_MARK,
++	VI1_VSYNC_N_IMARK,
++	MSIOF1_SYNC_MARK,
++	D2_MARK,
++	VI1_DATA0_IMARK,
++	MSIOF1_SS1_MARK,
++	D3_MARK,
++	MMC_WP_MARK,
++	VI1_DATA1_IMARK,
++	MSIOF1_SS2_MARK,
++	D4_MARK,
++	MMC_CD_MARK,
++	VI1_DATA2_IMARK,
++	CANFD0_TX_B_MARK,
++	D5_MARK,
++	MMC_DS_MARK,
++	VI1_DATA3_IMARK,
++	CANFD0_RX_B_MARK,
++	D6_MARK,
++	MMC_CMD_MARK,
++
++	/* IPSR6 */
++	VI1_DATA4_IMARK,
++	CANFD_CLK_B_MARK,
++	D7_MARK,
++	MMC_D0_MARK,
++	VI1_DATA5_IMARK,
++	D8_MARK,
++	MMC_D1_MARK,
++	VI1_DATA6_IMARK,
++	D9_MARK,
++	MMC_D2_MARK,
++	VI1_DATA7_IMARK,
++	D10_MARK,
++	MMC_D3_MARK,
++	VI1_DATA8_IMARK,
++	D11_MARK,
++	MMC_CLK_MARK,
++	VI1_DATA9_IMARK,
++	TCLK1_A_MARK,
++	D12_MARK,
++	MMC_D4_MARK,
++	VI1_DATA10_IMARK,
++	TCLK2_A_MARK,
++	D13_MARK,
++	MMC_D5_MARK,
++	VI1_DATA11_IMARK,
++	SCL4_MARK,
++	D14_MARK,
++	MMC_D6_MARK,
++
++	/* IPSR7 */
++	VI1_FIELD_IMARK,
++	SDA4_MARK,
++	D15_MARK,
++	MMC_D7_MARK,
++	SCL0_IMARK,
++	CLKOUT_MARK,
++	SDA0_IMARK,
++	BS_N_MARK,
++	SCK0_MARK,
++	HSCK0_B_MARK,
++	SCL1_IMARK,
++	TPU0TO2_MARK,
++	RD_N_MARK,
++	CTS0_N_MARK,
++	HCTS0_N_B_MARK,
++	SDA1_IMARK,
++	TPU0TO3_MARK,
++	WE0_N_MARK,
++	RTS0_N_TANS_MARK,
++	HRTS0_N_B_MARK,
++	SCL2_IMARK,
++	WE1_N_MARK,
++	RX0_MARK,
++	HRX0_B_MARK,
++	SDA2_IMARK,
++	EX_WAIT0_MARK,
++	TX0_MARK,
++	HTX0_B_MARK,
++	AVB0_AVTP_MATCH_IMARK,
++	TPU0TO0_MARK,
++
++	/* IPSR8 */
++	AVB0_AVTP_CAPTURE_IMARK,
++	TPU0TO1_MARK,
++	CANFD0_TX_A_IMARK,
++	FXR_TXDA_MARK,
++	PWM0_B_MARK,
++	DU_DISP_MARK,
++	CANFD0_RX_A_IMARK,
++	RXDA_EXTFXR_MARK,
++	PWM1_B_MARK,
++	DU_CDE_MARK,
++	CANFD1_TX_IMARK,
++	FXR_TXDB_MARK,
++	PWM2_B_MARK,
++	TCLK1_B_MARK,
++	TX1_B_MARK,
++	CANFD1_RX_IMARK,
++	RXDB_EXTFXR_MARK,
++	PWM3_B_MARK,
++	TCLK2_B_MARK,
++	RX1_B_MARK,
++	CANFD_CLK_A_IMARK,
++	CLK_EXTFXR_MARK,
++	PWM4_B_MARK,
++	SPEEDIN_B_MARK,
++	SCIF_CLK_B_MARK,
++	DIGRF_CLKIN_IMARK,
++	DIGRF_CLKEN_IN_MARK,
++	DIGRF_CLKOUT_IMARK,
++	DIGRF_CLKEN_OUT_MARK,
++
++	/* IPSR9 */
++	IRQ4_IMARK,
++	VI0_DATA12_MARK,
++	IRQ5_IMARK,
++	VI0_DATA13_MARK,
++	MSIOF0_RXD_IMARK,
++	DU_DR0_MARK,
++	VI0_DATA14_MARK,
++	MSIOF0_TXD_IMARK,
++	DU_DR1_MARK,
++	VI0_DATA15_MARK,
++	MSIOF0_SCK_IMARK,
++	DU_DG0_MARK,
++	VI0_DATA16_MARK,
++	MSIOF0_SYNC_IMARK,
++	DU_DG1_MARK,
++	VI0_DATA17_MARK,
++	MSIOF0_SS1_IMARK,
++	DU_DB0_MARK,
++	TCLK3_MARK,
++	VI0_DATA18_MARK,
++	MSIOF0_SS2_IMARK,
++	DU_DB1_MARK,
++	TCLK4_MARK,
++	VI0_DATA19_MARK,
++
++	/* IPSR10 */
++	SCL3_IMARK,
++	VI0_DATA20_MARK,
++	SDA3_IMARK,
++	VI0_DATA21_MARK,
++	FSO_CFE_0_N_IMARK,
++	VI0_DATA22_MARK,
++	FSO_CFE_1_N_IMARK,
++	VI0_DATA23_MARK,
++	FSO_TOE_N_IMARK,
++
++	PINMUX_MARK_END,
++};
++
++static pinmux_enum_t pinmux_data[] = {
++	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
++
++	/* GPSR0 */
++	PINMUX_DATA(DU_EXODDF_DU_ODDF_DISP_CDE_GMARK, GFN_DU_EXODDF_DU_ODDF_DISP_CDE),
++	PINMUX_DATA(DU_EXVSYNC_DU_VSYNC_GMARK, GFN_DU_EXVSYNC_DU_VSYNC),
++	PINMUX_DATA(DU_EXHSYNC_DU_HSYNC_GMARK, GFN_DU_EXHSYNC_DU_HSYNC),
++	PINMUX_DATA(DU_DOTCLKOUT_GMARK, GFN_DU_DOTCLKOUT),
++	PINMUX_DATA(DU_DB7_GMARK, GFN_DU_DB7),
++	PINMUX_DATA(DU_DB6_GMARK, GFN_DU_DB6),
++	PINMUX_DATA(DU_DB5_GMARK, GFN_DU_DB5),
++	PINMUX_DATA(DU_DB4_GMARK, GFN_DU_DB4),
++	PINMUX_DATA(DU_DB3_GMARK, GFN_DU_DB3),
++	PINMUX_DATA(DU_DB2_GMARK, GFN_DU_DB2),
++	PINMUX_DATA(DU_DG7_GMARK, GFN_DU_DG7),
++	PINMUX_DATA(DU_DG6_GMARK, GFN_DU_DG6),
++	PINMUX_DATA(DU_DG5_GMARK, GFN_DU_DG5),
++	PINMUX_DATA(DU_DG4_GMARK, GFN_DU_DG4),
++	PINMUX_DATA(DU_DG3_GMARK, GFN_DU_DG3),
++	PINMUX_DATA(DU_DG2_GMARK, GFN_DU_DG2),
++	PINMUX_DATA(DU_DR7_GMARK, GFN_DU_DR7),
++	PINMUX_DATA(DU_DR6_GMARK, GFN_DU_DR6),
++	PINMUX_DATA(DU_DR5_GMARK, GFN_DU_DR5),
++	PINMUX_DATA(DU_DR4_GMARK, GFN_DU_DR4),
++	PINMUX_DATA(DU_DR3_GMARK, GFN_DU_DR3),
++	PINMUX_DATA(DU_DR2_GMARK, GFN_DU_DR2),
++
++	/* GPSR1 */
++	PINMUX_DATA(DIGRF_CLKOUT_GMARK, GFN_DIGRF_CLKOUT),
++	PINMUX_DATA(DIGRF_CLKIN_GMARK, GFN_DIGRF_CLKIN),
++	PINMUX_DATA(CANFD_CLK_A_GMARK, GFN_CANFD_CLK_A),
++	PINMUX_DATA(CANFD1_RX_GMARK, GFN_CANFD1_RX),
++	PINMUX_DATA(CANFD1_TX_GMARK, GFN_CANFD1_TX),
++	PINMUX_DATA(CANFD0_RX_A_GMARK, GFN_CANFD0_RX_A),
++	PINMUX_DATA(CANFD0_TX_A_GMARK, GFN_CANFD0_TX_A),
++	PINMUX_DATA(AVB0_AVTP_CAPTURE_GMARK, GFN_AVB0_AVTP_CAPTURE),
++	PINMUX_DATA(AVB0_AVTP_MATCH_GMARK, GFN_AVB0_AVTP_MATCH),
++	PINMUX_DATA(AVB0_LINK_MARK, FN_AVB0_LINK),
++	PINMUX_DATA(AVB0_PHY_INT_MARK, FN_AVB0_PHY_INT),
++	PINMUX_DATA(AVB0_MAGIC_MARK, FN_AVB0_MAGIC),
++	PINMUX_DATA(AVB0_MDC_MARK, FN_AVB0_MDC),
++	PINMUX_DATA(AVB0_MDIO_MARK, FN_AVB0_MDIO),
++	PINMUX_DATA(AVB0_TXCREFCLK_MARK, FN_AVB0_TXCREFCLK),
++	PINMUX_DATA(AVB0_TD3_MARK, FN_AVB0_TD3),
++	PINMUX_DATA(AVB0_TD2_MARK, FN_AVB0_TD2),
++	PINMUX_DATA(AVB0_TD1_MARK, FN_AVB0_TD1),
++	PINMUX_DATA(AVB0_TD0_MARK, FN_AVB0_TD0),
++	PINMUX_DATA(AVB0_TXC_MARK, FN_AVB0_TXC),
++	PINMUX_DATA(AVB0_TX_CTL_MARK, FN_AVB0_TX_CTL),
++	PINMUX_DATA(AVB0_RD3_MARK, FN_AVB0_RD3),
++	PINMUX_DATA(AVB0_RD2_MARK, FN_AVB0_RD2),
++	PINMUX_DATA(AVB0_RD1_MARK, FN_AVB0_RD1),
++	PINMUX_DATA(AVB0_RD0_MARK, FN_AVB0_RD0),
++	PINMUX_DATA(AVB0_RXC_MARK, FN_AVB0_RXC),
++	PINMUX_DATA(AVB0_RX_CTL_MARK, FN_AVB0_RX_CTL),
++	PINMUX_DATA(IRQ0_GMARK, GFN_IRQ0),
++
++	/* GPSR2 */
++	PINMUX_DATA(FSO_TOE_N_GMARK, GFN_FSO_TOE_N),
++	PINMUX_DATA(FSO_CFE_1_N_GMARK, GFN_FSO_CFE_1_N),
++	PINMUX_DATA(FSO_CFE_0_N_GMARK, GFN_FSO_CFE_0_N),
++	PINMUX_DATA(SDA3_GMARK, GFN_SDA3),
++	PINMUX_DATA(SCL3_GMARK, GFN_SCL3),
++	PINMUX_DATA(MSIOF0_SS2_GMARK, GFN_MSIOF0_SS2),
++	PINMUX_DATA(MSIOF0_SS1_GMARK, GFN_MSIOF0_SS1),
++	PINMUX_DATA(MSIOF0_SYNC_GMARK, GFN_MSIOF0_SYNC),
++	PINMUX_DATA(MSIOF0_SCK_GMARK, GFN_MSIOF0_SCK),
++	PINMUX_DATA(MSIOF0_TXD_GMARK, GFN_MSIOF0_TXD),
++	PINMUX_DATA(MSIOF0_RXD_GMARK, GFN_MSIOF0_RXD),
++	PINMUX_DATA(IRQ5_GMARK, GFN_IRQ5),
++	PINMUX_DATA(IRQ4_GMARK, GFN_IRQ4),
++	PINMUX_DATA(VI0_FIELD_GMARK, GFN_VI0_FIELD),
++	PINMUX_DATA(VI0_DATA11_GMARK, GFN_VI0_DATA11),
++	PINMUX_DATA(VI0_DATA10_GMARK, GFN_VI0_DATA10),
++	PINMUX_DATA(VI0_DATA9_GMARK, GFN_VI0_DATA9),
++	PINMUX_DATA(VI0_DATA8_GMARK, GFN_VI0_DATA8),
++	PINMUX_DATA(VI0_DATA7_GMARK, GFN_VI0_DATA7),
++	PINMUX_DATA(VI0_DATA6_GMARK, GFN_VI0_DATA6),
++	PINMUX_DATA(VI0_DATA5_GMARK, GFN_VI0_DATA5),
++	PINMUX_DATA(VI0_DATA4_GMARK, GFN_VI0_DATA4),
++	PINMUX_DATA(VI0_DATA3_GMARK, GFN_VI0_DATA3),
++	PINMUX_DATA(VI0_DATA2_GMARK, GFN_VI0_DATA2),
++	PINMUX_DATA(VI0_DATA1_GMARK, GFN_VI0_DATA1),
++	PINMUX_DATA(VI0_DATA0_GMARK, GFN_VI0_DATA0),
++	PINMUX_DATA(VI0_VSYNC_N_GMARK, GFN_VI0_VSYNC_N),
++	PINMUX_DATA(VI0_HSYNC_N_GMARK, GFN_VI0_HSYNC_N),
++	PINMUX_DATA(VI0_CLKENB_GMARK, GFN_VI0_CLKENB),
++	PINMUX_DATA(VI0_CLK_GMARK, GFN_VI0_CLK),
++
++	/* GPSR3 */
++	PINMUX_DATA(VI1_FIELD_GMARK, GFN_VI1_FIELD),
++	PINMUX_DATA(VI1_DATA11_GMARK, GFN_VI1_DATA11),
++	PINMUX_DATA(VI1_DATA10_GMARK, GFN_VI1_DATA10),
++	PINMUX_DATA(VI1_DATA9_GMARK, GFN_VI1_DATA9),
++	PINMUX_DATA(VI1_DATA8_GMARK, GFN_VI1_DATA8),
++	PINMUX_DATA(VI1_DATA7_GMARK, GFN_VI1_DATA7),
++	PINMUX_DATA(VI1_DATA6_GMARK, GFN_VI1_DATA6),
++	PINMUX_DATA(VI1_DATA5_GMARK, GFN_VI1_DATA5),
++	PINMUX_DATA(VI1_DATA4_GMARK, GFN_VI1_DATA4),
++	PINMUX_DATA(VI1_DATA3_GMARK, GFN_VI1_DATA3),
++	PINMUX_DATA(VI1_DATA2_GMARK, GFN_VI1_DATA2),
++	PINMUX_DATA(VI1_DATA1_GMARK, GFN_VI1_DATA1),
++	PINMUX_DATA(VI1_DATA0_GMARK, GFN_VI1_DATA0),
++	PINMUX_DATA(VI1_VSYNC_N_GMARK, GFN_VI1_VSYNC_N),
++	PINMUX_DATA(VI1_HSYNC_N_GMARK, GFN_VI1_HSYNC_N),
++	PINMUX_DATA(VI1_CLKENB_GMARK, GFN_VI1_CLKENB),
++	PINMUX_DATA(VI1_CLK_GMARK, GFN_VI1_CLK),
++
++	/* GPSR4 */
++	PINMUX_DATA(GETHER_LINK_A_MARK, FN_GETHER_LINK_A),
++	PINMUX_DATA(GETHER_PHY_INT_A_MARK, FN_GETHER_PHY_INT_A),
++	PINMUX_DATA(GETHER_MAGIC_MARK, FN_GETHER_MAGIC),
++	PINMUX_DATA(GETHER_MDC_A_MARK, FN_GETHER_MDC_A),
++	PINMUX_DATA(GETHER_MDIO_A_MARK, FN_GETHER_MDIO_A),
++	PINMUX_DATA(GETHER_TXCREFCLK_MEGA_MARK, FN_GETHER_TXCREFCLK_MEGA),
++	PINMUX_DATA(GETHER_TXCREFCLK_MARK, FN_GETHER_TXCREFCLK),
++	PINMUX_DATA(GETHER_TD3_MARK, FN_GETHER_TD3),
++	PINMUX_DATA(GETHER_TD2_MARK, FN_GETHER_TD2),
++	PINMUX_DATA(GETHER_TD1_MARK, FN_GETHER_TD1),
++	PINMUX_DATA(GETHER_TD0_MARK, FN_GETHER_TD0),
++	PINMUX_DATA(GETHER_TXC_MARK, FN_GETHER_TXC),
++	PINMUX_DATA(GETHER_TX_CTL_MARK, FN_GETHER_TX_CTL),
++	PINMUX_DATA(GETHER_RD3_MARK, FN_GETHER_RD3),
++	PINMUX_DATA(GETHER_RD2_MARK, FN_GETHER_RD2),
++	PINMUX_DATA(GETHER_RD1_MARK, FN_GETHER_RD1),
++	PINMUX_DATA(GETHER_RD0_MARK, FN_GETHER_RD0),
++	PINMUX_DATA(GETHER_RXC_MARK, FN_GETHER_RXC),
++	PINMUX_DATA(GETHER_RX_CTL_MARK, FN_GETHER_RX_CTL),
++	PINMUX_DATA(SDA2_GMARK, GFN_SDA2),
++	PINMUX_DATA(SCL2_GMARK, GFN_SCL2),
++	PINMUX_DATA(SDA1_GMARK, GFN_SDA1),
++	PINMUX_DATA(SCL1_GMARK, GFN_SCL1),
++	PINMUX_DATA(SDA0_GMARK, GFN_SDA0),
++	PINMUX_DATA(SCL0_GMARK, GFN_SCL0),
++
++	/* GPSR5 */
++	PINMUX_DATA(RPC_INT_N_MARK, FN_RPC_INT_N),
++	PINMUX_DATA(RPC_WP_N_MARK, FN_RPC_WP_N),
++	PINMUX_DATA(RPC_RESET_N_MARK, FN_RPC_RESET_N),
++	PINMUX_DATA(QSPI1_SSL_MARK, FN_QSPI1_SSL),
++	PINMUX_DATA(QSPI1_IO3_MARK, FN_QSPI1_IO3),
++	PINMUX_DATA(QSPI1_IO2_MARK, FN_QSPI1_IO2),
++	PINMUX_DATA(QSPI1_MISO_IO1_MARK, FN_QSPI1_MISO_IO1),
++	PINMUX_DATA(QSPI1_MOSI_IO0_MARK, FN_QSPI1_MOSI_IO0),
++	PINMUX_DATA(QSPI1_SPCLK_MARK, FN_QSPI1_SPCLK),
++	PINMUX_DATA(QSPI0_SSL_MARK, FN_QSPI0_SSL),
++	PINMUX_DATA(QSPI0_IO3_MARK, FN_QSPI0_IO3),
++	PINMUX_DATA(QSPI0_IO2_MARK, FN_QSPI0_IO2),
++	PINMUX_DATA(QSPI0_MISO_IO1_MARK, FN_QSPI0_MISO_IO1),
++	PINMUX_DATA(QSPI0_MOSI_IO0_MARK, FN_QSPI0_MOSI_IO0),
++	PINMUX_DATA(QSPI0_SPCLK_MARK, FN_QSPI0_SPCLK),
++
++
++	/* IPSR0 */
++	PINMUX_IPSR_IDATA(DU_DR2),
++	PINMUX_IPSR_DATA(DU_DR2, SCK4),
++	PINMUX_IPSR_DATA(DU_DR2, GETHER_RMII_CRS_DV),
++	PINMUX_IPSR_DATA(DU_DR2, A0),
++	PINMUX_IPSR_IDATA(DU_DR3),
++	PINMUX_IPSR_DATA(DU_DR3, RX4),
++	PINMUX_IPSR_DATA(DU_DR3, GETHER_RMII_RX_ER),
++	PINMUX_IPSR_DATA(DU_DR3, A1),
++	PINMUX_IPSR_IDATA(DU_DR4),
++	PINMUX_IPSR_DATA(DU_DR4, TX4),
++	PINMUX_IPSR_DATA(DU_DR4, GETHER_RMII_RXD0),
++	PINMUX_IPSR_DATA(DU_DR4, A2),
++	PINMUX_IPSR_IDATA(DU_DR5),
++	PINMUX_IPSR_DATA(DU_DR5, CTS4_N),
++	PINMUX_IPSR_DATA(DU_DR5, GETHER_RMII_RXD1),
++	PINMUX_IPSR_DATA(DU_DR5, A3),
++	PINMUX_IPSR_IDATA(DU_DR6),
++	PINMUX_IPSR_DATA(DU_DR6, RTS4_N_TANS),
++	PINMUX_IPSR_DATA(DU_DR6, GETHER_RMII_TXD_EN),
++	PINMUX_IPSR_DATA(DU_DR6, A4),
++	PINMUX_IPSR_IDATA(DU_DR7),
++	PINMUX_IPSR_DATA(DU_DR7, GETHER_RMII_TXD0),
++	PINMUX_IPSR_DATA(DU_DR7, A5),
++	PINMUX_IPSR_IDATA(DU_DG2),
++	PINMUX_IPSR_DATA(DU_DG2, GETHER_RMII_TXD1),
++	PINMUX_IPSR_DATA(DU_DG2, A6),
++	PINMUX_IPSR_IDATA(DU_DG3),
++	PINMUX_IPSR_DATA(DU_DG3, CPG_CPCKOUT),
++	PINMUX_IPSR_DATA(DU_DG3, GETHER_RMII_REFCLK),
++	PINMUX_IPSR_DATA(DU_DG3, A7),
++	PINMUX_IPSR_DATA(DU_DG3, PWMFSW0),
++
++	/* IPSR1 */
++	PINMUX_IPSR_IDATA(DU_DG4),
++	PINMUX_IPSR_DATA(DU_DG4, SCL5),
++	PINMUX_IPSR_DATA(DU_DG4, A8),
++	PINMUX_IPSR_IDATA(DU_DG5),
++	PINMUX_IPSR_DATA(DU_DG5, SDA5),
++	PINMUX_IPSR_DATA(DU_DG5, GETHER_MDC_B),
++	PINMUX_IPSR_DATA(DU_DG5, A9),
++	PINMUX_IPSR_IDATA(DU_DG6),
++	PINMUX_IPSR_DATA(DU_DG6, SCIF_CLK_A),
++	PINMUX_IPSR_DATA(DU_DG6, GETHER_MDIO_B),
++	PINMUX_IPSR_DATA(DU_DG6, A10),
++	PINMUX_IPSR_IDATA(DU_DG7),
++	PINMUX_IPSR_DATA(DU_DG7, HRX0_A),
++	PINMUX_IPSR_DATA(DU_DG7, A11),
++	PINMUX_IPSR_IDATA(DU_DB2),
++	PINMUX_IPSR_DATA(DU_DB2, HSCK0_A),
++	PINMUX_IPSR_DATA(DU_DB2, A12),
++	PINMUX_IPSR_DATA(DU_DB2, IRQ1),
++	PINMUX_IPSR_IDATA(DU_DB3),
++	PINMUX_IPSR_DATA(DU_DB3, HRTS0_N_A),
++	PINMUX_IPSR_DATA(DU_DB3, A13),
++	PINMUX_IPSR_DATA(DU_DB3, IRQ2),
++	PINMUX_IPSR_IDATA(DU_DB4),
++	PINMUX_IPSR_DATA(DU_DB4, HCTS0_N_A),
++	PINMUX_IPSR_DATA(DU_DB4, A14),
++	PINMUX_IPSR_DATA(DU_DB4, IRQ3),
++	PINMUX_IPSR_IDATA(DU_DB5),
++	PINMUX_IPSR_DATA(DU_DB5, HTX0_A),
++	PINMUX_IPSR_DATA(DU_DB5, PWM0_A),
++	PINMUX_IPSR_DATA(DU_DB5, A15),
++
++	/* IPSR2 */
++	PINMUX_IPSR_IDATA(DU_DB6),
++	PINMUX_IPSR_DATA(DU_DB6, MSIOF3_RXD),
++	PINMUX_IPSR_DATA(DU_DB6, A16),
++	PINMUX_IPSR_IDATA(DU_DB7),
++	PINMUX_IPSR_DATA(DU_DB7, MSIOF3_TXD),
++	PINMUX_IPSR_DATA(DU_DB7, A17),
++	PINMUX_IPSR_IDATA(DU_DOTCLKOUT),
++	PINMUX_IPSR_DATA(DU_DOTCLKOUT, MSIOF3_SS1),
++	PINMUX_IPSR_DATA(DU_DOTCLKOUT, GETHER_LINK_B),
++	PINMUX_IPSR_DATA(DU_DOTCLKOUT, A18),
++	PINMUX_IPSR_IDATA(DU_EXHSYNC_DU_HSYNC),
++	PINMUX_IPSR_DATA(DU_EXHSYNC_DU_HSYNC, MSIOF3_SS2),
++	PINMUX_IPSR_DATA(DU_EXHSYNC_DU_HSYNC, GETHER_PHY_INT_B),
++	PINMUX_IPSR_DATA(DU_EXHSYNC_DU_HSYNC, A19),
++	PINMUX_IPSR_DATA(DU_EXHSYNC_DU_HSYNC, FXR_TXENA_N),
++	PINMUX_IPSR_IDATA(DU_EXVSYNC_DU_VSYNC),
++	PINMUX_IPSR_DATA(DU_EXVSYNC_DU_VSYNC, MSIOF3_SCK),
++	PINMUX_IPSR_DATA(DU_EXVSYNC_DU_VSYNC, FXR_TXENB_N),
++	PINMUX_IPSR_IDATA(DU_EXODDF_DU_ODDF_DISP_CDE),
++	PINMUX_IPSR_DATA(DU_EXODDF_DU_ODDF_DISP_CDE, MSIOF3_SYNC),
++	PINMUX_IPSR_IDATA(IRQ0),
++	PINMUX_IPSR_DATA(IRQ0, CC5_OSCOUT),
++	PINMUX_IPSR_IDATA(VI0_CLK),
++	PINMUX_IPSR_DATA(VI0_CLK, MSIOF2_SCK),
++	PINMUX_IPSR_DATA(VI0_CLK, SCK3),
++	PINMUX_IPSR_DATA(VI0_CLK, HSCK3),
++
++	/* IPSR3 */
++	PINMUX_IPSR_IDATA(VI0_CLKENB),
++	PINMUX_IPSR_DATA(VI0_CLKENB, MSIOF2_RXD),
++	PINMUX_IPSR_DATA(VI0_CLKENB, RX3),
++	PINMUX_IPSR_DATA(VI0_CLKENB, RD_WR_N),
++	PINMUX_IPSR_DATA(VI0_CLKENB, HCTS3_N),
++	PINMUX_IPSR_IDATA(VI0_HSYNC_N),
++	PINMUX_IPSR_DATA(VI0_HSYNC_N, MSIOF2_TXD),
++	PINMUX_IPSR_DATA(VI0_HSYNC_N, TX3),
++	PINMUX_IPSR_DATA(VI0_HSYNC_N, HRTS3_N),
++	PINMUX_IPSR_IDATA(VI0_VSYNC_N),
++	PINMUX_IPSR_DATA(VI0_VSYNC_N, MSIOF2_SYNC),
++	PINMUX_IPSR_DATA(VI0_VSYNC_N, CTS3_N),
++	PINMUX_IPSR_DATA(VI0_VSYNC_N, HTX3),
++	PINMUX_IPSR_IDATA(VI0_DATA0),
++	PINMUX_IPSR_DATA(VI0_DATA0, MSIOF2_SS1),
++	PINMUX_IPSR_DATA(VI0_DATA0, RTS3_N_TANS),
++	PINMUX_IPSR_DATA(VI0_DATA0, HRX3),
++	PINMUX_IPSR_IDATA(VI0_DATA1),
++	PINMUX_IPSR_DATA(VI0_DATA1, MSIOF2_SS2),
++	PINMUX_IPSR_DATA(VI0_DATA1, SCK1),
++	PINMUX_IPSR_DATA(VI0_DATA1, SPEEDIN_A),
++	PINMUX_IPSR_IDATA(VI0_DATA2),
++	PINMUX_IPSR_DATA(VI0_DATA2, AVB0_AVTP_PPS),
++	PINMUX_IPSR_IDATA(VI0_DATA3),
++	PINMUX_IPSR_DATA(VI0_DATA3, HSCK1),
++	PINMUX_IPSR_IDATA(VI0_DATA4),
++	PINMUX_IPSR_DATA(VI0_DATA4, HRTS1_N),
++	PINMUX_IPSR_DATA(VI0_DATA4, RX1_A),
++
++	/* IPSR4 */
++	PINMUX_IPSR_IDATA(VI0_DATA5),
++	PINMUX_IPSR_DATA(VI0_DATA5, HCTS1_N),
++	PINMUX_IPSR_DATA(VI0_DATA5, TX1_A),
++	PINMUX_IPSR_IDATA(VI0_DATA6),
++	PINMUX_IPSR_DATA(VI0_DATA6, HTX1),
++	PINMUX_IPSR_DATA(VI0_DATA6, CTS1_N),
++	PINMUX_IPSR_IDATA(VI0_DATA7),
++	PINMUX_IPSR_DATA(VI0_DATA7, HRX1),
++	PINMUX_IPSR_DATA(VI0_DATA7, RTS1_N_TANS),
++	PINMUX_IPSR_IDATA(VI0_DATA8),
++	PINMUX_IPSR_DATA(VI0_DATA8, HSCK2),
++	PINMUX_IPSR_IDATA(VI0_DATA9),
++	PINMUX_IPSR_DATA(VI0_DATA9, HCTS2_N),
++	PINMUX_IPSR_DATA(VI0_DATA9, PWM1_A),
++	PINMUX_IPSR_DATA(VI0_DATA9, FSO_CFE_0_N_B),
++	PINMUX_IPSR_IDATA(VI0_DATA10),
++	PINMUX_IPSR_DATA(VI0_DATA10, HRTS2_N),
++	PINMUX_IPSR_DATA(VI0_DATA10, PWM2_A),
++	PINMUX_IPSR_IDATA(VI0_DATA11),
++	PINMUX_IPSR_DATA(VI0_DATA11, HTX2),
++	PINMUX_IPSR_DATA(VI0_DATA11, PWM3_A),
++	PINMUX_IPSR_IDATA(VI0_FIELD),
++	PINMUX_IPSR_DATA(VI0_FIELD, HRX2),
++	PINMUX_IPSR_DATA(VI0_FIELD, PWM4_A),
++	PINMUX_IPSR_DATA(VI0_FIELD, CS1_N),
++	PINMUX_IPSR_DATA(VI0_FIELD, FSCLKST2_N_A),
++
++	/* IPSR5 */
++	PINMUX_IPSR_IDATA(VI1_CLK),
++	PINMUX_IPSR_DATA(VI1_CLK, MSIOF1_RXD),
++	PINMUX_IPSR_DATA(VI1_CLK, CS0_N),
++	PINMUX_IPSR_IDATA(VI1_CLKENB),
++	PINMUX_IPSR_DATA(VI1_CLKENB, MSIOF1_TXD),
++	PINMUX_IPSR_DATA(VI1_CLKENB, D0),
++	PINMUX_IPSR_IDATA(VI1_HSYNC_N),
++	PINMUX_IPSR_DATA(VI1_HSYNC_N, MSIOF1_SCK),
++	PINMUX_IPSR_DATA(VI1_HSYNC_N, D1),
++	PINMUX_IPSR_IDATA(VI1_VSYNC_N),
++	PINMUX_IPSR_DATA(VI1_VSYNC_N, MSIOF1_SYNC),
++	PINMUX_IPSR_DATA(VI1_VSYNC_N, D2),
++	PINMUX_IPSR_IDATA(VI1_DATA0),
++	PINMUX_IPSR_DATA(VI1_DATA0, MSIOF1_SS1),
++	PINMUX_IPSR_DATA(VI1_DATA0, D3),
++	PINMUX_IPSR_DATA(VI1_DATA0, MMC_WP),
++	PINMUX_IPSR_IDATA(VI1_DATA1),
++	PINMUX_IPSR_DATA(VI1_DATA1, MSIOF1_SS2),
++	PINMUX_IPSR_DATA(VI1_DATA1, D4),
++	PINMUX_IPSR_DATA(VI1_DATA1, MMC_CD),
++	PINMUX_IPSR_IDATA(VI1_DATA2),
++	PINMUX_IPSR_DATA(VI1_DATA2, CANFD0_TX_B),
++	PINMUX_IPSR_DATA(VI1_DATA2, D5),
++	PINMUX_IPSR_DATA(VI1_DATA2, MMC_DS),
++	PINMUX_IPSR_IDATA(VI1_DATA3),
++	PINMUX_IPSR_DATA(VI1_DATA3, CANFD0_RX_B),
++	PINMUX_IPSR_DATA(VI1_DATA3, D6),
++	PINMUX_IPSR_DATA(VI1_DATA3, MMC_CMD),
++
++	/* IPSR6 */
++	PINMUX_IPSR_IDATA(VI1_DATA4),
++	PINMUX_IPSR_DATA(VI1_DATA4, CANFD_CLK_B),
++	PINMUX_IPSR_DATA(VI1_DATA4, D7),
++	PINMUX_IPSR_DATA(VI1_DATA4, MMC_D0),
++	PINMUX_IPSR_IDATA(VI1_DATA5),
++	PINMUX_IPSR_DATA(VI1_DATA5, D8),
++	PINMUX_IPSR_DATA(VI1_DATA5, MMC_D1),
++	PINMUX_IPSR_IDATA(VI1_DATA6),
++	PINMUX_IPSR_DATA(VI1_DATA6, D9),
++	PINMUX_IPSR_DATA(VI1_DATA6, MMC_D2),
++	PINMUX_IPSR_IDATA(VI1_DATA7),
++	PINMUX_IPSR_DATA(VI1_DATA7, D10),
++	PINMUX_IPSR_DATA(VI1_DATA7, MMC_D3),
++	PINMUX_IPSR_IDATA(VI1_DATA8),
++	PINMUX_IPSR_DATA(VI1_DATA8, D11),
++	PINMUX_IPSR_DATA(VI1_DATA8, MMC_CLK),
++	PINMUX_IPSR_IDATA(VI1_DATA9),
++	PINMUX_IPSR_DATA(VI1_DATA9, TCLK1_A),
++	PINMUX_IPSR_DATA(VI1_DATA9, D12),
++	PINMUX_IPSR_DATA(VI1_DATA9, MMC_D4),
++	PINMUX_IPSR_IDATA(VI1_DATA10),
++	PINMUX_IPSR_DATA(VI1_DATA10, TCLK2_A),
++	PINMUX_IPSR_DATA(VI1_DATA10, D13),
++	PINMUX_IPSR_DATA(VI1_DATA10, MMC_D5),
++	PINMUX_IPSR_IDATA(VI1_DATA11),
++	PINMUX_IPSR_DATA(VI1_DATA11, SCL4),
++	PINMUX_IPSR_DATA(VI1_DATA11, D14),
++	PINMUX_IPSR_DATA(VI1_DATA11, MMC_D6),
++
++	/* IPSR7 */
++	PINMUX_IPSR_IDATA(VI1_FIELD),
++	PINMUX_IPSR_DATA(VI1_FIELD, SDA4),
++	PINMUX_IPSR_DATA(VI1_FIELD, D15),
++	PINMUX_IPSR_DATA(VI1_FIELD, MMC_D7),
++	PINMUX_IPSR_IDATA(SCL0),
++	PINMUX_IPSR_DATA(SCL0, CLKOUT),
++	PINMUX_IPSR_IDATA(SDA0),
++	PINMUX_IPSR_DATA(SDA0, BS_N),
++	PINMUX_IPSR_DATA(SDA0, SCK0),
++	PINMUX_IPSR_DATA(SDA0, HSCK0_B),
++	PINMUX_IPSR_IDATA(SCL1),
++	PINMUX_IPSR_DATA(SCL1, TPU0TO2),
++	PINMUX_IPSR_DATA(SCL1, RD_N),
++	PINMUX_IPSR_DATA(SCL1, CTS0_N),
++	PINMUX_IPSR_DATA(SCL1, HCTS0_N_B),
++	PINMUX_IPSR_IDATA(SDA1),
++	PINMUX_IPSR_DATA(SDA1, TPU0TO3),
++	PINMUX_IPSR_DATA(SDA1, WE0_N),
++	PINMUX_IPSR_DATA(SDA1, RTS0_N_TANS),
++	PINMUX_IPSR_DATA(SDA1, HRTS0_N_B),
++	PINMUX_IPSR_IDATA(SCL2),
++	PINMUX_IPSR_DATA(SCL2, WE1_N),
++	PINMUX_IPSR_DATA(SCL2, RX0),
++	PINMUX_IPSR_DATA(SCL2, HRX0_B),
++	PINMUX_IPSR_IDATA(SDA2),
++	PINMUX_IPSR_DATA(SDA2, EX_WAIT0),
++	PINMUX_IPSR_DATA(SDA2, TX0),
++	PINMUX_IPSR_DATA(SDA2, HTX0_B),
++	PINMUX_IPSR_IDATA(AVB0_AVTP_MATCH),
++	PINMUX_IPSR_DATA(AVB0_AVTP_MATCH, TPU0TO0),
++
++	/* IPSR8 */
++	PINMUX_IPSR_IDATA(AVB0_AVTP_CAPTURE),
++	PINMUX_IPSR_DATA(AVB0_AVTP_CAPTURE, TPU0TO1),
++	PINMUX_IPSR_IDATA(CANFD0_TX_A),
++	PINMUX_IPSR_DATA(CANFD0_TX_A, FXR_TXDA),
++	PINMUX_IPSR_DATA(CANFD0_TX_A, PWM0_B),
++	PINMUX_IPSR_DATA(CANFD0_TX_A, DU_DISP),
++	PINMUX_IPSR_IDATA(CANFD0_RX_A),
++	PINMUX_IPSR_DATA(CANFD0_RX_A, RXDA_EXTFXR),
++	PINMUX_IPSR_DATA(CANFD0_RX_A, PWM1_B),
++	PINMUX_IPSR_DATA(CANFD0_RX_A, DU_CDE),
++	PINMUX_IPSR_IDATA(CANFD1_TX),
++	PINMUX_IPSR_DATA(CANFD1_TX, FXR_TXDB),
++	PINMUX_IPSR_DATA(CANFD1_TX, PWM2_B),
++	PINMUX_IPSR_DATA(CANFD1_TX, TCLK1_B),
++	PINMUX_IPSR_DATA(CANFD1_TX, TX1_B),
++	PINMUX_IPSR_IDATA(CANFD1_RX),
++	PINMUX_IPSR_DATA(CANFD1_RX, RXDB_EXTFXR),
++	PINMUX_IPSR_DATA(CANFD1_RX, PWM3_B),
++	PINMUX_IPSR_DATA(CANFD1_RX, TCLK2_B),
++	PINMUX_IPSR_DATA(CANFD1_RX, RX1_B),
++	PINMUX_IPSR_IDATA(CANFD_CLK_A),
++	PINMUX_IPSR_DATA(CANFD_CLK_A, CLK_EXTFXR),
++	PINMUX_IPSR_DATA(CANFD_CLK_A, PWM4_B),
++	PINMUX_IPSR_DATA(CANFD_CLK_A, SPEEDIN_B),
++	PINMUX_IPSR_DATA(CANFD_CLK_A, SCIF_CLK_B),
++	PINMUX_IPSR_IDATA(DIGRF_CLKIN),
++	PINMUX_IPSR_DATA(DIGRF_CLKIN, DIGRF_CLKEN_IN),
++	PINMUX_IPSR_IDATA(DIGRF_CLKOUT),
++	PINMUX_IPSR_DATA(DIGRF_CLKOUT, DIGRF_CLKEN_OUT),
++
++	/* IPSR9 */
++	PINMUX_IPSR_IDATA(IRQ4),
++	PINMUX_IPSR_DATA(IRQ4, VI0_DATA12),
++	PINMUX_IPSR_IDATA(IRQ5),
++	PINMUX_IPSR_DATA(IRQ5, VI0_DATA13),
++	PINMUX_IPSR_IDATA(MSIOF0_RXD),
++	PINMUX_IPSR_DATA(MSIOF0_RXD, DU_DR0),
++	PINMUX_IPSR_DATA(MSIOF0_RXD, VI0_DATA14),
++	PINMUX_IPSR_IDATA(MSIOF0_TXD),
++	PINMUX_IPSR_DATA(MSIOF0_TXD, DU_DR1),
++	PINMUX_IPSR_DATA(MSIOF0_TXD, VI0_DATA15),
++	PINMUX_IPSR_IDATA(MSIOF0_SCK),
++	PINMUX_IPSR_DATA(MSIOF0_SCK, DU_DG0),
++	PINMUX_IPSR_DATA(MSIOF0_SCK, VI0_DATA16),
++	PINMUX_IPSR_IDATA(MSIOF0_SYNC),
++	PINMUX_IPSR_DATA(MSIOF0_SYNC, DU_DG1),
++	PINMUX_IPSR_DATA(MSIOF0_SYNC, VI0_DATA17),
++	PINMUX_IPSR_IDATA(MSIOF0_SS1),
++	PINMUX_IPSR_DATA(MSIOF0_SS1, DU_DB0),
++	PINMUX_IPSR_DATA(MSIOF0_SS1, TCLK3),
++	PINMUX_IPSR_DATA(MSIOF0_SS1, VI0_DATA18),
++	PINMUX_IPSR_IDATA(MSIOF0_SS2),
++	PINMUX_IPSR_DATA(MSIOF0_SS2, DU_DB1),
++	PINMUX_IPSR_DATA(MSIOF0_SS2, TCLK4),
++	PINMUX_IPSR_DATA(MSIOF0_SS2, VI0_DATA19),
++
++	/* IPSR10 */
++	PINMUX_IPSR_IDATA(SCL3),
++	PINMUX_IPSR_DATA(SCL3, VI0_DATA20),
++	PINMUX_IPSR_IDATA(SDA3),
++	PINMUX_IPSR_DATA(SDA3, VI0_DATA21),
++	PINMUX_IPSR_IDATA(FSO_CFE_0_N),
++	PINMUX_IPSR_DATA(FSO_CFE_0_N, VI0_DATA22),
++	PINMUX_IPSR_IDATA(FSO_CFE_1_N),
++	PINMUX_IPSR_DATA(FSO_CFE_1_N, VI0_DATA23),
++	PINMUX_IPSR_IDATA(FSO_TOE_N),
++};
++
++static struct pinmux_gpio pinmux_gpios[] = {
++	PINMUX_GPIO_GP_ALL(),
++
++	/* GPSR0 */
++	GPIO_GFN(DU_EXODDF_DU_ODDF_DISP_CDE),
++	GPIO_GFN(DU_EXVSYNC_DU_VSYNC),
++	GPIO_GFN(DU_EXHSYNC_DU_HSYNC),
++	GPIO_GFN(DU_DOTCLKOUT),
++	GPIO_GFN(DU_DB7),
++	GPIO_GFN(DU_DB6),
++	GPIO_GFN(DU_DB5),
++	GPIO_GFN(DU_DB4),
++	GPIO_GFN(DU_DB3),
++	GPIO_GFN(DU_DB2),
++	GPIO_GFN(DU_DG7),
++	GPIO_GFN(DU_DG6),
++	GPIO_GFN(DU_DG5),
++	GPIO_GFN(DU_DG4),
++	GPIO_GFN(DU_DG3),
++	GPIO_GFN(DU_DG2),
++	GPIO_GFN(DU_DR7),
++	GPIO_GFN(DU_DR6),
++	GPIO_GFN(DU_DR5),
++	GPIO_GFN(DU_DR4),
++	GPIO_GFN(DU_DR3),
++	GPIO_GFN(DU_DR2),
++
++	/* GPSR1 */
++	GPIO_GFN(DIGRF_CLKOUT),
++	GPIO_GFN(DIGRF_CLKIN),
++	GPIO_GFN(CANFD_CLK_A),
++	GPIO_GFN(CANFD1_RX),
++	GPIO_GFN(CANFD1_TX),
++	GPIO_GFN(CANFD0_RX_A),
++	GPIO_GFN(CANFD0_TX_A),
++	GPIO_GFN(AVB0_AVTP_CAPTURE),
++	GPIO_GFN(AVB0_AVTP_MATCH),
++	GPIO_FN(AVB0_LINK),
++	GPIO_FN(AVB0_PHY_INT),
++	GPIO_FN(AVB0_MAGIC),
++	GPIO_FN(AVB0_MDC),
++	GPIO_FN(AVB0_MDIO),
++	GPIO_FN(AVB0_TXCREFCLK),
++	GPIO_FN(AVB0_TD3),
++	GPIO_FN(AVB0_TD2),
++	GPIO_FN(AVB0_TD1),
++	GPIO_FN(AVB0_TD0),
++	GPIO_FN(AVB0_TXC),
++	GPIO_FN(AVB0_TX_CTL),
++	GPIO_FN(AVB0_RD3),
++	GPIO_FN(AVB0_RD2),
++	GPIO_FN(AVB0_RD1),
++	GPIO_FN(AVB0_RD0),
++	GPIO_FN(AVB0_RXC),
++	GPIO_FN(AVB0_RX_CTL),
++	GPIO_GFN(IRQ0),
++
++	/* GPSR2 */
++	GPIO_GFN(FSO_TOE_N),
++	GPIO_GFN(FSO_CFE_1_N),
++	GPIO_GFN(FSO_CFE_0_N),
++	GPIO_GFN(SDA3),
++	GPIO_GFN(SCL3),
++	GPIO_GFN(MSIOF0_SS2),
++	GPIO_GFN(MSIOF0_SS1),
++	GPIO_GFN(MSIOF0_SYNC),
++	GPIO_GFN(MSIOF0_SCK),
++	GPIO_GFN(MSIOF0_TXD),
++	GPIO_GFN(MSIOF0_RXD),
++	GPIO_GFN(IRQ5),
++	GPIO_GFN(IRQ4),
++	GPIO_GFN(VI0_FIELD),
++	GPIO_GFN(VI0_DATA11),
++	GPIO_GFN(VI0_DATA10),
++	GPIO_GFN(VI0_DATA9),
++	GPIO_GFN(VI0_DATA8),
++	GPIO_GFN(VI0_DATA7),
++	GPIO_GFN(VI0_DATA6),
++	GPIO_GFN(VI0_DATA5),
++	GPIO_GFN(VI0_DATA4),
++	GPIO_GFN(VI0_DATA3),
++	GPIO_GFN(VI0_DATA2),
++	GPIO_GFN(VI0_DATA1),
++	GPIO_GFN(VI0_DATA0),
++	GPIO_GFN(VI0_VSYNC_N),
++	GPIO_GFN(VI0_HSYNC_N),
++	GPIO_GFN(VI0_CLKENB),
++	GPIO_GFN(VI0_CLK),
++
++	/* GPSR3 */
++	GPIO_GFN(VI1_FIELD),
++	GPIO_GFN(VI1_DATA11),
++	GPIO_GFN(VI1_DATA10),
++	GPIO_GFN(VI1_DATA9),
++	GPIO_GFN(VI1_DATA8),
++	GPIO_GFN(VI1_DATA7),
++	GPIO_GFN(VI1_DATA6),
++	GPIO_GFN(VI1_DATA5),
++	GPIO_GFN(VI1_DATA4),
++	GPIO_GFN(VI1_DATA3),
++	GPIO_GFN(VI1_DATA2),
++	GPIO_GFN(VI1_DATA1),
++	GPIO_GFN(VI1_DATA0),
++	GPIO_GFN(VI1_VSYNC_N),
++	GPIO_GFN(VI1_HSYNC_N),
++	GPIO_GFN(VI1_CLKENB),
++	GPIO_GFN(VI1_CLK),
++
++	/* GPSR4 */
++	GPIO_FN(GETHER_LINK_A),
++	GPIO_FN(GETHER_PHY_INT_A),
++	GPIO_FN(GETHER_MAGIC),
++	GPIO_FN(GETHER_MDC_A),
++	GPIO_FN(GETHER_MDIO_A),
++	GPIO_FN(GETHER_TXCREFCLK_MEGA),
++	GPIO_FN(GETHER_TXCREFCLK),
++	GPIO_FN(GETHER_TD3),
++	GPIO_FN(GETHER_TD2),
++	GPIO_FN(GETHER_TD1),
++	GPIO_FN(GETHER_TD0),
++	GPIO_FN(GETHER_TXC),
++	GPIO_FN(GETHER_TX_CTL),
++	GPIO_FN(GETHER_RD3),
++	GPIO_FN(GETHER_RD2),
++	GPIO_FN(GETHER_RD1),
++	GPIO_FN(GETHER_RD0),
++	GPIO_FN(GETHER_RXC),
++	GPIO_FN(GETHER_RX_CTL),
++	GPIO_GFN(SDA2),
++	GPIO_GFN(SCL2),
++	GPIO_GFN(SDA1),
++	GPIO_GFN(SCL1),
++	GPIO_GFN(SDA0),
++	GPIO_GFN(SCL0),
++
++	/* GPSR5 */
++	GPIO_FN(RPC_INT_N),
++	GPIO_FN(RPC_WP_N),
++	GPIO_FN(RPC_RESET_N),
++	GPIO_FN(QSPI1_SSL),
++	GPIO_FN(QSPI1_IO3),
++	GPIO_FN(QSPI1_IO2),
++	GPIO_FN(QSPI1_MISO_IO1),
++	GPIO_FN(QSPI1_MOSI_IO0),
++	GPIO_FN(QSPI1_SPCLK),
++	GPIO_FN(QSPI0_SSL),
++	GPIO_FN(QSPI0_IO3),
++	GPIO_FN(QSPI0_IO2),
++	GPIO_FN(QSPI0_MISO_IO1),
++	GPIO_FN(QSPI0_MOSI_IO0),
++	GPIO_FN(QSPI0_SPCLK),
++
++	/* IPSR0 */
++	GPIO_IFN(DU_DR2),
++	GPIO_FN(SCK4),
++	GPIO_FN(GETHER_RMII_CRS_DV),
++	GPIO_FN(A0),
++	GPIO_IFN(DU_DR3),
++	GPIO_FN(RX4),
++	GPIO_FN(GETHER_RMII_RX_ER),
++	GPIO_FN(A1),
++	GPIO_IFN(DU_DR4),
++	GPIO_FN(TX4),
++	GPIO_FN(GETHER_RMII_RXD0),
++	GPIO_FN(A2),
++	GPIO_IFN(DU_DR5),
++	GPIO_FN(CTS4_N),
++	GPIO_FN(GETHER_RMII_RXD1),
++	GPIO_FN(A3),
++	GPIO_IFN(DU_DR6),
++	GPIO_FN(RTS4_N_TANS),
++	GPIO_FN(GETHER_RMII_TXD_EN),
++	GPIO_FN(A4),
++	GPIO_IFN(DU_DR7),
++	GPIO_FN(GETHER_RMII_TXD0),
++	GPIO_FN(A5),
++	GPIO_IFN(DU_DG2),
++	GPIO_FN(GETHER_RMII_TXD1),
++	GPIO_FN(A6),
++	GPIO_IFN(DU_DG3),
++	GPIO_FN(CPG_CPCKOUT),
++	GPIO_FN(GETHER_RMII_REFCLK),
++	GPIO_FN(A7),
++	GPIO_FN(PWMFSW0),
++
++	/* IPSR1 */
++	GPIO_IFN(DU_DG4),
++	GPIO_FN(SCL5),
++	GPIO_FN(A8),
++	GPIO_IFN(DU_DG5),
++	GPIO_FN(SDA5),
++	GPIO_FN(GETHER_MDC_B),
++	GPIO_FN(A9),
++	GPIO_IFN(DU_DG6),
++	GPIO_FN(SCIF_CLK_A),
++	GPIO_FN(GETHER_MDIO_B),
++	GPIO_FN(A10),
++	GPIO_IFN(DU_DG7),
++	GPIO_FN(HRX0_A),
++	GPIO_FN(A11),
++	GPIO_IFN(DU_DB2),
++	GPIO_FN(HSCK0_A),
++	GPIO_FN(A12),
++	GPIO_FN(IRQ1),
++	GPIO_IFN(DU_DB3),
++	GPIO_FN(HRTS0_N_A),
++	GPIO_FN(A13),
++	GPIO_FN(IRQ2),
++	GPIO_IFN(DU_DB4),
++	GPIO_FN(HCTS0_N_A),
++	GPIO_FN(A14),
++	GPIO_FN(IRQ3),
++	GPIO_IFN(DU_DB5),
++	GPIO_FN(HTX0_A),
++	GPIO_FN(PWM0_A),
++	GPIO_FN(A15),
++
++	/* IPSR2 */
++	GPIO_IFN(DU_DB6),
++	GPIO_FN(MSIOF3_RXD),
++	GPIO_FN(A16),
++	GPIO_IFN(DU_DB7),
++	GPIO_FN(MSIOF3_TXD),
++	GPIO_FN(A17),
++	GPIO_IFN(DU_DOTCLKOUT),
++	GPIO_FN(MSIOF3_SS1),
++	GPIO_FN(GETHER_LINK_B),
++	GPIO_FN(A18),
++	GPIO_IFN(DU_EXHSYNC_DU_HSYNC),
++	GPIO_FN(MSIOF3_SS2),
++	GPIO_FN(GETHER_PHY_INT_B),
++	GPIO_FN(A19),
++	GPIO_FN(FXR_TXENA_N),
++	GPIO_IFN(DU_EXVSYNC_DU_VSYNC),
++	GPIO_FN(MSIOF3_SCK),
++	GPIO_FN(FXR_TXENB_N),
++	GPIO_IFN(DU_EXODDF_DU_ODDF_DISP_CDE),
++	GPIO_FN(MSIOF3_SYNC),
++	GPIO_IFN(IRQ0),
++	GPIO_FN(CC5_OSCOUT),
++	GPIO_IFN(VI0_CLK),
++	GPIO_FN(MSIOF2_SCK),
++	GPIO_FN(SCK3),
++	GPIO_FN(HSCK3),
++
++	/* IPSR3 */
++	GPIO_IFN(VI0_CLKENB),
++	GPIO_FN(MSIOF2_RXD),
++	GPIO_FN(RX3),
++	GPIO_FN(RD_WR_N),
++	GPIO_FN(HCTS3_N),
++	GPIO_IFN(VI0_HSYNC_N),
++	GPIO_FN(MSIOF2_TXD),
++	GPIO_FN(TX3),
++	GPIO_FN(HRTS3_N),
++	GPIO_IFN(VI0_VSYNC_N),
++	GPIO_FN(MSIOF2_SYNC),
++	GPIO_FN(CTS3_N),
++	GPIO_FN(HTX3),
++	GPIO_IFN(VI0_DATA0),
++	GPIO_FN(MSIOF2_SS1),
++	GPIO_FN(RTS3_N_TANS),
++	GPIO_FN(HRX3),
++	GPIO_IFN(VI0_DATA1),
++	GPIO_FN(MSIOF2_SS2),
++	GPIO_FN(SCK1),
++	GPIO_FN(SPEEDIN_A),
++	GPIO_IFN(VI0_DATA2),
++	GPIO_FN(AVB0_AVTP_PPS),
++	GPIO_IFN(VI0_DATA3),
++	GPIO_FN(HSCK1),
++	GPIO_IFN(VI0_DATA4),
++	GPIO_FN(HRTS1_N),
++	GPIO_FN(RX1_A),
++
++	/* IPSR4 */
++	GPIO_IFN(VI0_DATA5),
++	GPIO_FN(HCTS1_N),
++	GPIO_FN(TX1_A),
++	GPIO_IFN(VI0_DATA6),
++	GPIO_FN(HTX1),
++	GPIO_FN(CTS1_N),
++	GPIO_IFN(VI0_DATA7),
++	GPIO_FN(HRX1),
++	GPIO_FN(RTS1_N_TANS),
++	GPIO_IFN(VI0_DATA8),
++	GPIO_FN(HSCK2),
++	GPIO_IFN(VI0_DATA9),
++	GPIO_FN(HCTS2_N),
++	GPIO_FN(PWM1_A),
++	GPIO_FN(FSO_CFE_0_N_B),
++	GPIO_IFN(VI0_DATA10),
++	GPIO_FN(HRTS2_N),
++	GPIO_FN(PWM2_A),
++	GPIO_IFN(VI0_DATA11),
++	GPIO_FN(HTX2),
++	GPIO_FN(PWM3_A),
++	GPIO_IFN(VI0_FIELD),
++	GPIO_FN(HRX2),
++	GPIO_FN(PWM4_A),
++	GPIO_FN(CS1_N),
++	GPIO_FN(FSCLKST2_N_A),
++
++	/* IPSR5 */
++	GPIO_IFN(VI1_CLK),
++	GPIO_FN(MSIOF1_RXD),
++	GPIO_FN(CS0_N),
++	GPIO_IFN(VI1_CLKENB),
++	GPIO_FN(MSIOF1_TXD),
++	GPIO_FN(D0),
++	GPIO_IFN(VI1_HSYNC_N),
++	GPIO_FN(MSIOF1_SCK),
++	GPIO_FN(D1),
++	GPIO_IFN(VI1_VSYNC_N),
++	GPIO_FN(MSIOF1_SYNC),
++	GPIO_FN(D2),
++	GPIO_IFN(VI1_DATA0),
++	GPIO_FN(MSIOF1_SS1),
++	GPIO_FN(D3),
++	GPIO_FN(MMC_WP),
++	GPIO_IFN(VI1_DATA1),
++	GPIO_FN(MSIOF1_SS2),
++	GPIO_FN(D4),
++	GPIO_FN(MMC_CD),
++	GPIO_IFN(VI1_DATA2),
++	GPIO_FN(CANFD0_TX_B),
++	GPIO_FN(D5),
++	GPIO_FN(MMC_DS),
++	GPIO_IFN(VI1_DATA3),
++	GPIO_FN(CANFD0_RX_B),
++	GPIO_FN(D6),
++	GPIO_FN(MMC_CMD),
++
++	/* IPSR6 */
++	GPIO_IFN(VI1_DATA4),
++	GPIO_FN(CANFD_CLK_B),
++	GPIO_FN(D7),
++	GPIO_FN(MMC_D0),
++	GPIO_IFN(VI1_DATA5),
++	GPIO_FN(D8),
++	GPIO_FN(MMC_D1),
++	GPIO_IFN(VI1_DATA6),
++	GPIO_FN(D9),
++	GPIO_FN(MMC_D2),
++	GPIO_IFN(VI1_DATA7),
++	GPIO_FN(D10),
++	GPIO_FN(MMC_D3),
++	GPIO_IFN(VI1_DATA8),
++	GPIO_FN(D11),
++	GPIO_FN(MMC_CLK),
++	GPIO_IFN(VI1_DATA9),
++	GPIO_FN(TCLK1_A),
++	GPIO_FN(D12),
++	GPIO_FN(MMC_D4),
++	GPIO_IFN(VI1_DATA10),
++	GPIO_FN(TCLK2_A),
++	GPIO_FN(D13),
++	GPIO_FN(MMC_D5),
++	GPIO_IFN(VI1_DATA11),
++	GPIO_FN(SCL4),
++	GPIO_FN(D14),
++	GPIO_FN(MMC_D6),
++
++	/* IPSR7 */
++	GPIO_IFN(VI1_FIELD),
++	GPIO_FN(SDA4),
++	GPIO_FN(D15),
++	GPIO_FN(MMC_D7),
++	GPIO_IFN(SCL0),
++	GPIO_FN(CLKOUT),
++	GPIO_IFN(SDA0),
++	GPIO_FN(BS_N),
++	GPIO_FN(SCK0),
++	GPIO_FN(HSCK0_B),
++	GPIO_IFN(SCL1),
++	GPIO_FN(TPU0TO2),
++	GPIO_FN(RD_N),
++	GPIO_FN(CTS0_N),
++	GPIO_FN(HCTS0_N_B),
++	GPIO_IFN(SDA1),
++	GPIO_FN(TPU0TO3),
++	GPIO_FN(WE0_N),
++	GPIO_FN(RTS0_N_TANS),
++	GPIO_FN(HRTS0_N_B),
++	GPIO_IFN(SCL2),
++	GPIO_FN(WE1_N),
++	GPIO_FN(RX0),
++	GPIO_FN(HRX0_B),
++	GPIO_IFN(SDA2),
++	GPIO_FN(EX_WAIT0),
++	GPIO_FN(TX0),
++	GPIO_FN(HTX0_B),
++	GPIO_IFN(AVB0_AVTP_MATCH),
++	GPIO_FN(TPU0TO0),
++
++	/* IPSR8 */
++	GPIO_IFN(AVB0_AVTP_CAPTURE),
++	GPIO_FN(TPU0TO1),
++	GPIO_IFN(CANFD0_TX_A),
++	GPIO_FN(FXR_TXDA),
++	GPIO_FN(PWM0_B),
++	GPIO_FN(DU_DISP),
++	GPIO_IFN(CANFD0_RX_A),
++	GPIO_FN(RXDA_EXTFXR),
++	GPIO_FN(PWM1_B),
++	GPIO_FN(DU_CDE),
++	GPIO_IFN(CANFD1_TX),
++	GPIO_FN(FXR_TXDB),
++	GPIO_FN(PWM2_B),
++	GPIO_FN(TCLK1_B),
++	GPIO_FN(TX1_B),
++	GPIO_IFN(CANFD1_RX),
++	GPIO_FN(RXDB_EXTFXR),
++	GPIO_FN(PWM3_B),
++	GPIO_FN(TCLK2_B),
++	GPIO_FN(RX1_B),
++	GPIO_IFN(CANFD_CLK_A),
++	GPIO_FN(CLK_EXTFXR),
++	GPIO_FN(PWM4_B),
++	GPIO_FN(SPEEDIN_B),
++	GPIO_FN(SCIF_CLK_B),
++	GPIO_IFN(DIGRF_CLKIN),
++	GPIO_FN(DIGRF_CLKEN_IN),
++	GPIO_IFN(DIGRF_CLKOUT),
++	GPIO_FN(DIGRF_CLKEN_OUT),
++
++	/* IPSR9 */
++	GPIO_IFN(IRQ4),
++	GPIO_FN(VI0_DATA12),
++	GPIO_IFN(IRQ5),
++	GPIO_FN(VI0_DATA13),
++	GPIO_IFN(MSIOF0_RXD),
++	GPIO_FN(DU_DR0),
++	GPIO_FN(VI0_DATA14),
++	GPIO_IFN(MSIOF0_TXD),
++	GPIO_FN(DU_DR1),
++	GPIO_FN(VI0_DATA15),
++	GPIO_IFN(MSIOF0_SCK),
++	GPIO_FN(DU_DG0),
++	GPIO_FN(VI0_DATA16),
++	GPIO_IFN(MSIOF0_SYNC),
++	GPIO_FN(DU_DG1),
++	GPIO_FN(VI0_DATA17),
++	GPIO_IFN(MSIOF0_SS1),
++	GPIO_FN(DU_DB0),
++	GPIO_FN(TCLK3),
++	GPIO_FN(VI0_DATA18),
++	GPIO_IFN(MSIOF0_SS2),
++	GPIO_FN(DU_DB1),
++	GPIO_FN(TCLK4),
++	GPIO_FN(VI0_DATA19),
++
++	/* IPSR10 */
++	GPIO_IFN(SCL3),
++	GPIO_FN(VI0_DATA20),
++	GPIO_IFN(SDA3),
++	GPIO_FN(VI0_DATA21),
++	GPIO_IFN(FSO_CFE_0_N),
++	GPIO_FN(VI0_DATA22),
++	GPIO_IFN(FSO_CFE_1_N),
++	GPIO_FN(VI0_DATA23),
++	GPIO_IFN(FSO_TOE_N),
++};
++
++static struct pinmux_cfg_reg pinmux_config_regs[] = {
++	/* GPSR0(0xE6060100) md[3:1] controls initial value */
++	/*   md[3:1] .. 0     : 0x0000FFFF                  */
++	/*           .. other : 0x00000000                  */
++	{ PINMUX_CFG_REG("GPSR0", 0xE6060100, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_0_21_FN, GFN_DU_EXODDF_DU_ODDF_DISP_CDE,
++		GP_0_20_FN, GFN_DU_EXVSYNC_DU_VSYNC,
++		GP_0_19_FN, GFN_DU_EXHSYNC_DU_HSYNC,
++		GP_0_18_FN, GFN_DU_DOTCLKOUT,
++		GP_0_17_FN, GFN_DU_DB7,
++		GP_0_16_FN, GFN_DU_DB6,
++		GP_0_15_FN, GFN_DU_DB5,
++		GP_0_14_FN, GFN_DU_DB4,
++		GP_0_13_FN, GFN_DU_DB3,
++		GP_0_12_FN, GFN_DU_DB2,
++		GP_0_11_FN, GFN_DU_DG7,
++		GP_0_10_FN, GFN_DU_DG6,
++		GP_0_9_FN, GFN_DU_DG5,
++		GP_0_8_FN, GFN_DU_DG4,
++		GP_0_7_FN, GFN_DU_DG3,
++		GP_0_6_FN, GFN_DU_DG2,
++		GP_0_5_FN, GFN_DU_DR7,
++		GP_0_4_FN, GFN_DU_DR6,
++		GP_0_3_FN, GFN_DU_DR5,
++		GP_0_2_FN, GFN_DU_DR4,
++		GP_0_1_FN, GFN_DU_DR3,
++		GP_0_0_FN, GFN_DU_DR2 }
++	},
++	/* GPSR1(0xE6060104) is md[3:1] controls initial value */
++	/*   md[3:1] .. 0     : 0x0EFFFFFF                     */
++	/*           .. other : 0x00000000                     */
++	{ PINMUX_CFG_REG("GPSR1", 0xE6060104, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_1_27_FN, GFN_DIGRF_CLKOUT,
++		GP_1_26_FN, GFN_DIGRF_CLKIN,
++		GP_1_25_FN, GFN_CANFD_CLK_A,
++		GP_1_24_FN, GFN_CANFD1_RX,
++		GP_1_23_FN, GFN_CANFD1_TX,
++		GP_1_22_FN, GFN_CANFD0_RX_A,
++		GP_1_21_FN, GFN_CANFD0_TX_A,
++		GP_1_20_FN, GFN_AVB0_AVTP_CAPTURE,
++		GP_1_19_FN, GFN_AVB0_AVTP_MATCH,
++		GP_1_18_FN, FN_AVB0_LINK,
++		GP_1_17_FN, FN_AVB0_PHY_INT,
++		GP_1_16_FN, FN_AVB0_MAGIC,
++		GP_1_15_FN, FN_AVB0_MDC,
++		GP_1_14_FN, FN_AVB0_MDIO,
++		GP_1_13_FN, FN_AVB0_TXCREFCLK,
++		GP_1_12_FN, FN_AVB0_TD3,
++		GP_1_11_FN, FN_AVB0_TD2,
++		GP_1_10_FN, FN_AVB0_TD1,
++		GP_1_9_FN, FN_AVB0_TD0,
++		GP_1_8_FN, FN_AVB0_TXC,
++		GP_1_7_FN, FN_AVB0_TX_CTL,
++		GP_1_6_FN, FN_AVB0_RD3,
++		GP_1_5_FN, FN_AVB0_RD2,
++		GP_1_4_FN, FN_AVB0_RD1,
++		GP_1_3_FN, FN_AVB0_RD0,
++		GP_1_2_FN, FN_AVB0_RXC,
++		GP_1_1_FN, FN_AVB0_RX_CTL,
++		GP_1_0_FN, GFN_IRQ0 }
++	},
++	/* GPSR2(0xE6060108) is md[3:1] controls               */
++	/*   md[3:1] .. 0     : 0x000003C0                     */
++	/*           .. other : 0x00000200                     */
++	{ PINMUX_CFG_REG("GPSR2", 0xE6060108, 32, 1) {
++		0, 0,
++		0, 0,
++		GP_2_29_FN, GFN_FSO_TOE_N,
++		GP_2_28_FN, GFN_FSO_CFE_1_N,
++		GP_2_27_FN, GFN_FSO_CFE_0_N,
++		GP_2_26_FN, GFN_SDA3,
++		GP_2_25_FN, GFN_SCL3,
++		GP_2_24_FN, GFN_MSIOF0_SS2,
++		GP_2_23_FN, GFN_MSIOF0_SS1,
++		GP_2_22_FN, GFN_MSIOF0_SYNC,
++		GP_2_21_FN, GFN_MSIOF0_SCK,
++		GP_2_20_FN, GFN_MSIOF0_TXD,
++		GP_2_19_FN, GFN_MSIOF0_RXD,
++		GP_2_18_FN, GFN_IRQ5,
++		GP_2_17_FN, GFN_IRQ4,
++		GP_2_16_FN, GFN_VI0_FIELD,
++		GP_2_15_FN, GFN_VI0_DATA11,
++		GP_2_14_FN, GFN_VI0_DATA10,
++		GP_2_13_FN, GFN_VI0_DATA9,
++		GP_2_12_FN, GFN_VI0_DATA8,
++		GP_2_11_FN, GFN_VI0_DATA7,
++		GP_2_10_FN, GFN_VI0_DATA6,
++		GP_2_9_FN, GFN_VI0_DATA5,
++		GP_2_8_FN, GFN_VI0_DATA4,
++		GP_2_7_FN, GFN_VI0_DATA3,
++		GP_2_6_FN, GFN_VI0_DATA2,
++		GP_2_5_FN, GFN_VI0_DATA1,
++		GP_2_4_FN, GFN_VI0_DATA0,
++		GP_2_3_FN, GFN_VI0_VSYNC_N,
++		GP_2_2_FN, GFN_VI0_HSYNC_N,
++		GP_2_1_FN, GFN_VI0_CLKENB,
++		GP_2_0_FN, GFN_VI0_CLK }
++	},
++
++	/* GPSR3 */
++	{ PINMUX_CFG_REG("GPSR3", 0xE606010C, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_3_16_FN, GFN_VI1_FIELD,
++		GP_3_15_FN, GFN_VI1_DATA11,
++		GP_3_14_FN, GFN_VI1_DATA10,
++		GP_3_13_FN, GFN_VI1_DATA9,
++		GP_3_12_FN, GFN_VI1_DATA8,
++		GP_3_11_FN, GFN_VI1_DATA7,
++		GP_3_10_FN, GFN_VI1_DATA6,
++		GP_3_9_FN, GFN_VI1_DATA5,
++		GP_3_8_FN, GFN_VI1_DATA4,
++		GP_3_7_FN, GFN_VI1_DATA3,
++		GP_3_6_FN, GFN_VI1_DATA2,
++		GP_3_5_FN, GFN_VI1_DATA1,
++		GP_3_4_FN, GFN_VI1_DATA0,
++		GP_3_3_FN, GFN_VI1_VSYNC_N,
++		GP_3_2_FN, GFN_VI1_HSYNC_N,
++		GP_3_1_FN, GFN_VI1_CLKENB,
++		GP_3_0_FN, GFN_VI1_CLK }
++	},
++	/* GPSR4 */
++	{ PINMUX_CFG_REG("GPSR4", 0xE6060110, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_4_24_FN, FN_GETHER_LINK_A,
++		GP_4_23_FN, FN_GETHER_PHY_INT_A,
++		GP_4_22_FN, FN_GETHER_MAGIC,
++		GP_4_21_FN, FN_GETHER_MDC_A,
++		GP_4_20_FN, FN_GETHER_MDIO_A,
++		GP_4_19_FN, FN_GETHER_TXCREFCLK_MEGA,
++		GP_4_18_FN, FN_GETHER_TXCREFCLK,
++		GP_4_17_FN, FN_GETHER_TD3,
++		GP_4_16_FN, FN_GETHER_TD2,
++		GP_4_15_FN, FN_GETHER_TD1,
++		GP_4_14_FN, FN_GETHER_TD0,
++		GP_4_13_FN, FN_GETHER_TXC,
++		GP_4_12_FN, FN_GETHER_TX_CTL,
++		GP_4_11_FN, FN_GETHER_RD3,
++		GP_4_10_FN, FN_GETHER_RD2,
++		GP_4_9_FN, FN_GETHER_RD1,
++		GP_4_8_FN, FN_GETHER_RD0,
++		GP_4_7_FN, FN_GETHER_RXC,
++		GP_4_6_FN, FN_GETHER_RX_CTL,
++		GP_4_5_FN, GFN_SDA2,
++		GP_4_4_FN, GFN_SCL2,
++		GP_4_3_FN, GFN_SDA1,
++		GP_4_2_FN, GFN_SCL1,
++		GP_4_1_FN, GFN_SDA0,
++		GP_4_0_FN, GFN_SCL0 }
++	},
++	/* GPSR5 */
++	{ PINMUX_CFG_REG("GPSR5", 0xE6060114, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_5_14_FN, FN_RPC_INT_N,
++		GP_5_13_FN, FN_RPC_WP_N,
++		GP_5_12_FN, FN_RPC_RESET_N,
++		GP_5_11_FN, FN_QSPI1_SSL,
++		GP_5_10_FN, FN_QSPI1_IO3,
++		GP_5_9_FN, FN_QSPI1_IO2,
++		GP_5_8_FN, FN_QSPI1_MISO_IO1,
++		GP_5_7_FN, FN_QSPI1_MOSI_IO0,
++		GP_5_6_FN, FN_QSPI1_SPCLK,
++		GP_5_5_FN, FN_QSPI0_SSL,
++		GP_5_4_FN, FN_QSPI0_IO3,
++		GP_5_3_FN, FN_QSPI0_IO2,
++		GP_5_2_FN, FN_QSPI0_MISO_IO1,
++		GP_5_1_FN, FN_QSPI0_MOSI_IO0,
++		GP_5_0_FN, FN_QSPI0_SPCLK }
++	},
++
++	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32,
++				4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IPSR0_31_28 [4] */
++		IFN_DU_DG3, FN_CPG_CPCKOUT, FN_GETHER_RMII_REFCLK, FN_A7,
++		FN_PWMFSW0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR0_27_24 [4] */
++		IFN_DU_DG2, 0, FN_GETHER_RMII_TXD1, FN_A6,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR0_23_20 [4] */
++		IFN_DU_DR7, 0, FN_GETHER_RMII_TXD0, FN_A5,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR0_19_16 [4] */
++		IFN_DU_DR6, FN_RTS4_N_TANS, FN_GETHER_RMII_TXD_EN, FN_A4,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR0_15_12 [4] */
++		IFN_DU_DR5, FN_CTS4_N, FN_GETHER_RMII_RXD1, FN_A3,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR0_11_8 [4] */
++		IFN_DU_DR4, FN_TX4, FN_GETHER_RMII_RXD0, FN_A2,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR0_7_4 [4] */
++		IFN_DU_DR3, FN_RX4, FN_GETHER_RMII_RX_ER, FN_A1,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR0_3_0 [4] */
++		IFN_DU_DR2, FN_SCK4, FN_GETHER_RMII_CRS_DV, FN_A0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		}
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32,
++				4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IPSR1_31_28 [4] */
++		IFN_DU_DB5, FN_HTX0_A, FN_PWM0_A, FN_A15,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR1_27_24 [4] */
++		IFN_DU_DB4, FN_HCTS0_N_A, 0, FN_A14,
++		FN_IRQ3, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR1_23_20 [4] */
++		IFN_DU_DB3, FN_HRTS0_N_A, 0, FN_A13,
++		FN_IRQ2, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR1_19_16 [4] */
++		IFN_DU_DB2, FN_HSCK0_A, 0, FN_A12,
++		FN_IRQ1, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR1_15_12 [4] */
++		IFN_DU_DG7, FN_HRX0_A, 0, FN_A11,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR1_11_8 [4] */
++		IFN_DU_DG6, FN_SCIF_CLK_A, FN_GETHER_MDIO_B, FN_A10,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR1_7_4 [4] */
++		IFN_DU_DG5, FN_SDA5, FN_GETHER_MDC_B, FN_A9,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR1_3_0 [4] */
++		IFN_DU_DG4, FN_SCL5, 0, FN_A8,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0
++		}
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32,
++				4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IPSR2_31_28 [4] */
++		IFN_VI0_CLK, FN_MSIOF2_SCK, FN_SCK3, 0,
++		FN_HSCK3, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR2_27_24 [4] */
++		IFN_IRQ0, FN_CC5_OSCOUT, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR2_23_20 [4] */
++		IFN_DU_EXODDF_DU_ODDF_DISP_CDE, FN_MSIOF3_SYNC, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR2_19_16 [4] */
++		IFN_DU_EXVSYNC_DU_VSYNC, FN_MSIOF3_SCK, 0, 0,
++		FN_FXR_TXENB_N, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR2_15_12 [4] */
++		IFN_DU_EXHSYNC_DU_HSYNC, FN_MSIOF3_SS2, FN_GETHER_PHY_INT_B, FN_A19,
++		FN_FXR_TXENA_N, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR2_11_8 [4] */
++		IFN_DU_DOTCLKOUT, FN_MSIOF3_SS1, FN_GETHER_LINK_B, FN_A18,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR2_7_4 [4] */
++		IFN_DU_DB7, FN_MSIOF3_TXD, 0, FN_A17,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR2_3_0 [4] */
++		IFN_DU_DB6, FN_MSIOF3_RXD, 0, FN_A16,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		}
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32,
++				4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IPSR3_31_28 [4] */
++		IFN_VI0_DATA4, FN_HRTS1_N, FN_RX1_A, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR3_27_24 [4] */
++		IFN_VI0_DATA3, FN_HSCK1, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR3_23_20 [4] */
++		IFN_VI0_DATA2, FN_AVB0_AVTP_PPS, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR3_19_16 [4] */
++		IFN_VI0_DATA1, FN_MSIOF2_SS2, FN_SCK1, 0,
++		FN_SPEEDIN_A, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR3_15_12 [4] */
++		IFN_VI0_DATA0, FN_MSIOF2_SS1, FN_RTS3_N_TANS, 0,
++		FN_HRX3, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR3_11_8 [4] */
++		IFN_VI0_VSYNC_N, FN_MSIOF2_SYNC, FN_CTS3_N, 0,
++		FN_HTX3, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR3_7_4 [4] */
++		IFN_VI0_HSYNC_N, FN_MSIOF2_TXD, FN_TX3, 0,
++		FN_HRTS3_N, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR3_3_0 [4] */
++		IFN_VI0_CLKENB, FN_MSIOF2_RXD, FN_RX3, FN_RD_WR_N,
++		FN_HCTS3_N, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		}
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32,
++				4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IPSR4_31_28 [4] */
++		IFN_VI0_FIELD, FN_HRX2, FN_PWM4_A, FN_CS1_N,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR4_27_24 [4] */
++		IFN_VI0_DATA11, FN_HTX2, FN_PWM3_A, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR4_23_20 [4] */
++		IFN_VI0_DATA10, FN_HRTS2_N, FN_PWM2_A, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR4_19_16 [4] */
++		IFN_VI0_DATA9, FN_HCTS2_N, FN_PWM1_A, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR4_15_12 [4] */
++		IFN_VI0_DATA8, FN_HSCK2, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR4_11_8 [4] */
++		IFN_VI0_DATA7, FN_HRX1, FN_RTS1_N_TANS, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR4_7_4 [4] */
++		IFN_VI0_DATA6, FN_HTX1, FN_CTS1_N, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR4_3_0 [4] */
++		IFN_VI0_DATA5, FN_HCTS1_N, FN_TX1_A, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		}
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32,
++				4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IPSR5_31_28 [4] */
++		IFN_VI1_DATA3, FN_CANFD0_RX_B, 0, FN_D6,
++		FN_MMC_CMD, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR5_27_24 [4] */
++		IFN_VI1_DATA2, FN_CANFD0_TX_B, 0, FN_D5,
++		FN_MMC_DS, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR5_23_20 [4] */
++		IFN_VI1_DATA1, FN_MSIOF1_SS2, 0, FN_D4,
++		FN_MMC_CD, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR5_19_16 [4] */
++		IFN_VI1_DATA0, FN_MSIOF1_SS1, 0, FN_D3,
++		FN_MMC_WP, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR5_15_12 [4] */
++		IFN_VI1_VSYNC_N, FN_MSIOF1_SYNC, 0, FN_D2,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR5_11_8 [4] */
++		IFN_VI1_HSYNC_N, FN_MSIOF1_SCK, 0, FN_D1,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR5_7_4 [4] */
++		IFN_VI1_CLKENB, FN_MSIOF1_TXD, 0, FN_D0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR5_3_0 [4] */
++		IFN_VI1_CLK, FN_MSIOF1_RXD, 0, FN_CS0_N,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		}
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32,
++				4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IPSR6_31_28 [4] */
++		IFN_VI1_DATA11, FN_SCL4, 0, FN_D14,
++		FN_MMC_D6, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR6_27_24 [4] */
++		IFN_VI1_DATA10, FN_TCLK2_A, 0, FN_D13,
++		FN_MMC_D5, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR6_23_20 [4] */
++		IFN_VI1_DATA9, FN_TCLK1_A, 0, FN_D12,
++		FN_MMC_D4, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR6_19_16 [4] */
++		IFN_VI1_DATA8, 0, 0, FN_D11,
++		FN_MMC_CLK, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR6_15_12 [4] */
++		IFN_VI1_DATA7, 0, 0, FN_D10,
++		FN_MMC_D3, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR6_11_8 [4] */
++		IFN_VI1_DATA6, 0, 0, FN_D9,
++		FN_MMC_D2, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR6_7_4 [4] */
++		IFN_VI1_DATA5, 0, 0, FN_D8,
++		FN_MMC_D1, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR6_3_0 [4] */
++		IFN_VI1_DATA4, FN_CANFD_CLK_B, 0, FN_D7,
++		FN_MMC_D0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		}
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32,
++				4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IPSR7_31_28 [4] */
++		IFN_AVB0_AVTP_MATCH, FN_TPU0TO0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR7_27_24 [4] */
++		IFN_SDA2, 0, 0, FN_EX_WAIT0,
++		FN_TX0, FN_HTX0_B, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR7_23_20 [4] */
++		IFN_SCL2, 0, 0, FN_WE1_N,
++		FN_RX0, FN_HRX0_B, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR7_19_16 [4] */
++		IFN_SDA1, 0, FN_TPU0TO3, FN_WE0_N,
++		FN_RTS0_N_TANS, FN_HRTS0_N_B, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR7_15_12 [4] */
++		IFN_SCL1, 0, FN_TPU0TO2, FN_RD_N,
++		FN_CTS0_N, FN_HCTS0_N_B, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR7_11_8 [4] */
++		IFN_SDA0, 0, 0, FN_BS_N,
++		FN_SCK0, FN_HSCK0_B, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR7_7_4 [4] */
++		IFN_SCL0, 0, 0, FN_CLKOUT,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR7_3_0 [4] */
++		IFN_VI1_FIELD, FN_SDA4, 0, FN_D15,
++		FN_MMC_D7, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		}
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32,
++				4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IPSR8_31_28 [4] */
++		IFN_DIGRF_CLKOUT, FN_DIGRF_CLKEN_OUT, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR8_27_24 [4] */
++		IFN_DIGRF_CLKIN, FN_DIGRF_CLKEN_IN, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR8_23_20 [4] */
++		IFN_CANFD_CLK_A, FN_CLK_EXTFXR, FN_PWM4_B, FN_SPEEDIN_B,
++		FN_SCIF_CLK_B, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR8_19_16 [4] */
++		IFN_CANFD1_RX, FN_RXDB_EXTFXR, FN_PWM3_B, FN_TCLK2_B,
++		FN_RX1_B, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR8_15_12 [4] */
++		IFN_CANFD1_TX, FN_FXR_TXDB, FN_PWM2_B, FN_TCLK1_B,
++		FN_TX1_B, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR8_11_8 [4] */
++		IFN_CANFD0_RX_A, FN_RXDA_EXTFXR, FN_PWM1_B, FN_DU_CDE,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR8_7_4 [4] */
++		IFN_CANFD0_TX_A, FN_FXR_TXDA, FN_PWM0_B, FN_DU_DISP,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR8_3_0 [4] */
++		IFN_AVB0_AVTP_CAPTURE, FN_TPU0TO1, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		}
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32,
++				4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IPSR9_31_28 [4] */
++		IFN_MSIOF0_SS2, FN_DU_DB1, FN_TCLK4, FN_VI0_DATA19,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR9_27_24 [4] */
++		IFN_MSIOF0_SS1, FN_DU_DB0, FN_TCLK3, FN_VI0_DATA18,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR9_23_20 [4] */
++		IFN_MSIOF0_SYNC, FN_DU_DG1, 0, FN_VI0_DATA17,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR9_19_16 [4] */
++		IFN_MSIOF0_SCK, FN_DU_DG0, 0, FN_VI0_DATA16,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR9_15_12 [4] */
++		IFN_MSIOF0_TXD, FN_DU_DR1, 0, FN_VI0_DATA15,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR9_11_8 [4] */
++		IFN_MSIOF0_RXD, FN_DU_DR0, 0, FN_VI0_DATA14,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR9_7_4 [4] */
++		IFN_IRQ5, 0, 0, FN_VI0_DATA13,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR9_3_0 [4] */
++		IFN_IRQ4, 0, 0, FN_VI0_DATA12,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		}
++	},
++	{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060228, 32,
++				4, 4, 4, 4, 4, 4, 4, 4) {
++		/* IPSR10_31_28 [4] */
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR10_27_24 [4] */
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR10_23_20 [4] */
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR10_19_16 [4] */
++		IFN_FSO_TOE_N, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR10_15_12 [4] */
++		IFN_FSO_CFE_1_N, 0, 0, FN_VI0_DATA23,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR10_11_8 [4] */
++		IFN_FSO_CFE_0_N, 0, 0, FN_VI0_DATA22,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR10_7_4 [4] */
++		IFN_SDA3, 0, 0, FN_VI0_DATA21,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		/* IPSR10_3_0 [4] */
++		IFN_SCL3, 0, 0, FN_VI0_DATA20,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		0, 0, 0, 0,
++		}
++	},
++	{ PINMUX_CFG_REG("MOD_SEL0", 0xE6060500, 32, 1) {
++		/* reserved [31..24] */
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		/* reserved [23..16] */
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		/* reserved [15..11] */
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		/* SEL_CANFD0 [1] */
++		FN_SEL_CANFD0_0,
++		FN_SEL_CANFD0_1,
++		/* SEL_GETHER [1] */
++		FN_SEL_GETHER_0,
++		FN_SEL_GETHER_1,
++		/* SEL_HSCIF0 [1] */
++		FN_SEL_HSCIF0_0,
++		FN_SEL_HSCIF0_1,
++		/* SEL_PWM4 [1] */
++		FN_SEL_PWM0_0,
++		FN_SEL_PWM0_1,
++		/* SEL_PWM3 [1] */
++		FN_SEL_PWM1_0,
++		FN_SEL_PWM1_1,
++		/* SEL_PWM2 [1] */
++		FN_SEL_PWM2_0,
++		FN_SEL_PWM2_1,
++		/* SEL_PWM1 [1] */
++		FN_SEL_PWM3_0,
++		FN_SEL_PWM3_1,
++		/* SEL_PWM0 [1] */
++		FN_SEL_PWM4_0,
++		FN_SEL_PWM4_1,
++		0, 0,
++		/* SEL_RSP [1] */
++		FN_SEL_RSP_0,
++		FN_SEL_RSP_1,
++		/* SEL_SCIF1 [1] */
++		FN_SEL_SCIF1_0,
++		FN_SEL_SCIF1_1,
++		/* SEL_TMU [1] */
++		FN_SEL_TMU_0,
++		FN_SEL_TMU_1,
++		}
++	},
++
++	/* under construction */
++	{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_0_21_IN, GP_0_21_OUT,
++		GP_0_20_IN, GP_0_20_OUT,
++		GP_0_19_IN, GP_0_19_OUT,
++		GP_0_18_IN, GP_0_18_OUT,
++		GP_0_17_IN, GP_0_17_OUT,
++		GP_0_16_IN, GP_0_16_OUT,
++		GP_0_15_IN, GP_0_15_OUT,
++		GP_0_14_IN, GP_0_14_OUT,
++		GP_0_13_IN, GP_0_13_OUT,
++		GP_0_12_IN, GP_0_12_OUT,
++		GP_0_11_IN, GP_0_11_OUT,
++		GP_0_10_IN, GP_0_10_OUT,
++		GP_0_9_IN, GP_0_9_OUT,
++		GP_0_8_IN, GP_0_8_OUT,
++		GP_0_7_IN, GP_0_7_OUT,
++		GP_0_6_IN, GP_0_6_OUT,
++		GP_0_5_IN, GP_0_5_OUT,
++		GP_0_4_IN, GP_0_4_OUT,
++		GP_0_3_IN, GP_0_3_OUT,
++		GP_0_2_IN, GP_0_2_OUT,
++		GP_0_1_IN, GP_0_1_OUT,
++		GP_0_0_IN, GP_0_0_OUT,
++		}
++	},
++	{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_1_27_IN, GP_1_27_OUT,
++		GP_1_26_IN, GP_1_26_OUT,
++		GP_1_25_IN, GP_1_25_OUT,
++		GP_1_24_IN, GP_1_24_OUT,
++		GP_1_23_IN, GP_1_23_OUT,
++		GP_1_22_IN, GP_1_22_OUT,
++		GP_1_21_IN, GP_1_21_OUT,
++		GP_1_20_IN, GP_1_20_OUT,
++		GP_1_19_IN, GP_1_19_OUT,
++		GP_1_18_IN, GP_1_18_OUT,
++		GP_1_17_IN, GP_1_17_OUT,
++		GP_1_16_IN, GP_1_16_OUT,
++		GP_1_15_IN, GP_1_15_OUT,
++		GP_1_14_IN, GP_1_14_OUT,
++		GP_1_13_IN, GP_1_13_OUT,
++		GP_1_12_IN, GP_1_12_OUT,
++		GP_1_11_IN, GP_1_11_OUT,
++		GP_1_10_IN, GP_1_10_OUT,
++		GP_1_9_IN, GP_1_9_OUT,
++		GP_1_8_IN, GP_1_8_OUT,
++		GP_1_7_IN, GP_1_7_OUT,
++		GP_1_6_IN, GP_1_6_OUT,
++		GP_1_5_IN, GP_1_5_OUT,
++		GP_1_4_IN, GP_1_4_OUT,
++		GP_1_3_IN, GP_1_3_OUT,
++		GP_1_2_IN, GP_1_2_OUT,
++		GP_1_1_IN, GP_1_1_OUT,
++		GP_1_0_IN, GP_1_0_OUT,
++		}
++	},
++	{ PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) {
++		0, 0,
++		0, 0,
++		GP_2_29_IN, GP_2_29_OUT,
++		GP_2_28_IN, GP_2_28_OUT,
++		GP_2_27_IN, GP_2_27_OUT,
++		GP_2_26_IN, GP_2_26_OUT,
++		GP_2_25_IN, GP_2_25_OUT,
++		GP_2_24_IN, GP_2_24_OUT,
++		GP_2_23_IN, GP_2_23_OUT,
++		GP_2_22_IN, GP_2_22_OUT,
++		GP_2_21_IN, GP_2_21_OUT,
++		GP_2_20_IN, GP_2_20_OUT,
++		GP_2_19_IN, GP_2_19_OUT,
++		GP_2_18_IN, GP_2_18_OUT,
++		GP_2_17_IN, GP_2_17_OUT,
++		GP_2_16_IN, GP_2_16_OUT,
++		GP_2_15_IN, GP_2_15_OUT,
++		GP_2_14_IN, GP_2_14_OUT,
++		GP_2_13_IN, GP_2_13_OUT,
++		GP_2_12_IN, GP_2_12_OUT,
++		GP_2_11_IN, GP_2_11_OUT,
++		GP_2_10_IN, GP_2_10_OUT,
++		GP_2_9_IN, GP_2_9_OUT,
++		GP_2_8_IN, GP_2_8_OUT,
++		GP_2_7_IN, GP_2_7_OUT,
++		GP_2_6_IN, GP_2_6_OUT,
++		GP_2_5_IN, GP_2_5_OUT,
++		GP_2_4_IN, GP_2_4_OUT,
++		GP_2_3_IN, GP_2_3_OUT,
++		GP_2_2_IN, GP_2_2_OUT,
++		GP_2_1_IN, GP_2_1_OUT,
++		GP_2_0_IN, GP_2_0_OUT,
++		}
++	},
++	{ PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_3_16_IN, GP_3_16_OUT,
++		GP_3_15_IN, GP_3_15_OUT,
++		GP_3_14_IN, GP_3_14_OUT,
++		GP_3_13_IN, GP_3_13_OUT,
++		GP_3_12_IN, GP_3_12_OUT,
++		GP_3_11_IN, GP_3_11_OUT,
++		GP_3_10_IN, GP_3_10_OUT,
++		GP_3_9_IN, GP_3_9_OUT,
++		GP_3_8_IN, GP_3_8_OUT,
++		GP_3_7_IN, GP_3_7_OUT,
++		GP_3_6_IN, GP_3_6_OUT,
++		GP_3_5_IN, GP_3_5_OUT,
++		GP_3_4_IN, GP_3_4_OUT,
++		GP_3_3_IN, GP_3_3_OUT,
++		GP_3_2_IN, GP_3_2_OUT,
++		GP_3_1_IN, GP_3_1_OUT,
++		GP_3_0_IN, GP_3_0_OUT,
++		}
++	},
++	{ PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_4_24_IN, GP_4_24_OUT,
++		GP_4_23_IN, GP_4_23_OUT,
++		GP_4_22_IN, GP_4_22_OUT,
++		GP_4_21_IN, GP_4_21_OUT,
++		GP_4_20_IN, GP_4_20_OUT,
++		GP_4_19_IN, GP_4_19_OUT,
++		GP_4_18_IN, GP_4_18_OUT,
++		GP_4_17_IN, GP_4_17_OUT,
++		GP_4_16_IN, GP_4_16_OUT,
++		GP_4_15_IN, GP_4_15_OUT,
++		GP_4_14_IN, GP_4_14_OUT,
++		GP_4_13_IN, GP_4_13_OUT,
++		GP_4_12_IN, GP_4_12_OUT,
++		GP_4_11_IN, GP_4_11_OUT,
++		GP_4_10_IN, GP_4_10_OUT,
++		GP_4_9_IN, GP_4_9_OUT,
++		GP_4_8_IN, GP_4_8_OUT,
++		GP_4_7_IN, GP_4_7_OUT,
++		GP_4_6_IN, GP_4_6_OUT,
++		GP_4_5_IN, GP_4_5_OUT,
++		GP_4_4_IN, GP_4_4_OUT,
++		GP_4_3_IN, GP_4_3_OUT,
++		GP_4_2_IN, GP_4_2_OUT,
++		GP_4_1_IN, GP_4_1_OUT,
++		GP_4_0_IN, GP_4_0_OUT,
++		}
++	},
++	{ PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++
++		0, 0,
++		GP_5_14_IN, GP_5_14_OUT,
++		GP_5_13_IN, GP_5_13_OUT,
++		GP_5_12_IN, GP_5_12_OUT,
++		GP_5_11_IN, GP_5_11_OUT,
++		GP_5_10_IN, GP_5_10_OUT,
++		GP_5_9_IN, GP_5_9_OUT,
++		GP_5_8_IN, GP_5_8_OUT,
++		GP_5_7_IN, GP_5_7_OUT,
++		GP_5_6_IN, GP_5_6_OUT,
++		GP_5_5_IN, GP_5_5_OUT,
++		GP_5_4_IN, GP_5_4_OUT,
++		GP_5_3_IN, GP_5_3_OUT,
++		GP_5_2_IN, GP_5_2_OUT,
++		GP_5_1_IN, GP_5_1_OUT,
++		GP_5_0_IN, GP_5_0_OUT,
++		}
++	},
++	{ },
++	{ },
++	{ },
++};
++
++static struct pinmux_data_reg pinmux_data_regs[] = {
++	/* use OUTDT registers? */
++	{ PINMUX_DATA_REG("INDT0", 0xE6050008, 32) {
++		0, 0, 0, 0, 0, 0, 0, 0,
++		0, 0, GP_0_21_DATA, GP_0_20_DATA,
++		GP_0_19_DATA, GP_0_18_DATA, GP_0_17_DATA, GP_0_16_DATA,
++		GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA,
++		GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA,
++		GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA,
++		GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA }
++	},
++	{ PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
++		0, 0, 0, 0,
++		GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,
++		GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
++		GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
++		GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
++		GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
++		GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
++		GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
++	},
++	{ PINMUX_DATA_REG("INDT2", 0xE6052008, 32) {
++		0, 0, GP_2_29_DATA, GP_2_28_DATA,
++		GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA,
++		GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA,
++		GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA,
++		GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA,
++		GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA,
++		GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA,
++		GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA }
++	},
++	{ PINMUX_DATA_REG("INDT3", 0xE6053008, 32) {
++		0, 0, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, GP_3_16_DATA,
++		GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA,
++		GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA,
++		GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA,
++		GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA }
++	},
++	{ PINMUX_DATA_REG("INDT4", 0xE6054008, 32) {
++		0, 0, 0, 0, 0, 0, 0, GP_4_24_DATA,
++		GP_4_23_DATA, GP_4_22_DATA, GP_4_21_DATA, GP_4_20_DATA,
++		GP_4_19_DATA, GP_4_18_DATA, GP_4_17_DATA, GP_4_16_DATA,
++		GP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA,
++		GP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA,
++		GP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA,
++		GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA }
++	},
++	{ PINMUX_DATA_REG("INDT5", 0xE6055008, 32) {
++		0, 0, 0, 0, 0, 0, 0, 0,
++		0, 0, 0, 0, 0, 0, 0, 0,
++		0, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,
++		GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
++		GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
++		GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
++	},
++	{ },
++	{ },
++	{ },
++};
++
++static struct pinmux_info r8a7798_pinmux_info = {
++	.name = "r8a7798_pfc",
++
++	.unlock_reg = 0xe6060000, /* PMMR */
++
++	.reserved_id = PINMUX_RESERVED,
++	.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
++	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
++	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
++	.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
++	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
++
++	.first_gpio = GPIO_GP_0_0,
++	.last_gpio = GPIO_IFN_FSO_TOE_N,
++
++	.gpios = pinmux_gpios,
++	.cfg_regs = pinmux_config_regs,
++	.data_regs = pinmux_data_regs,
++
++	.gpio_data = pinmux_data,
++	.gpio_data_size = ARRAY_SIZE(pinmux_data),
++};
++
++void r8a7798_pinmux_init(void)
++{
++	register_pinmux(&r8a7798_pinmux_info);
++}
+diff --git a/arch/arm/cpu/armv8/rcar_gen3/pfc.c b/arch/arm/cpu/armv8/rcar_gen3/pfc.c
+index bd3aa0a..72c5482 100644
+--- a/arch/arm/cpu/armv8/rcar_gen3/pfc.c
++++ b/arch/arm/cpu/armv8/rcar_gen3/pfc.c
+@@ -22,5 +22,7 @@ void pinmux_init(void)
+ 	r8a7796_pinmux_init();
+ #elif defined(CONFIG_R8A7797)
+ 	r8a7797_pinmux_init();
++#elif defined(CONFIG_R8A7798)
++	r8a7798_pinmux_init();
+ #endif
+ }
+diff --git a/arch/arm/include/asm/arch-rcar_gen3/gpio.h b/arch/arm/include/asm/arch-rcar_gen3/gpio.h
+index fb8b758..cc94b5c 100644
+--- a/arch/arm/include/asm/arch-rcar_gen3/gpio.h
++++ b/arch/arm/include/asm/arch-rcar_gen3/gpio.h
+@@ -18,6 +18,8 @@
+ #include <asm/arch/r8a7796-gpio.h>
+ #elif defined(CONFIG_R8A7797)
+ #include <asm/arch/r8a7797-gpio.h>
++#elif defined(CONFIG_R8A7798)
++#include <asm/arch/r8a7798-gpio.h>
+ #endif
+ 
+ #if defined(CONFIG_R8A7795)
+@@ -27,6 +29,8 @@ void r8a7795_es_pinmux_init(void);
+ void r8a7796_pinmux_init(void);
+ #elif defined(CONFIG_R8A7797)
+ void r8a7797_pinmux_init(void);
++#elif defined(CONFIG_R8A7798)
++void r8a7798_pinmux_init(void);
+ #endif
+ void pinmux_init(void);
+ 
+diff --git a/arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h b/arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h
+new file mode 100644
+index 0000000..8d2252f
+--- /dev/null
++++ b/arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h
+@@ -0,0 +1,522 @@
++/*
++ * arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h
++ *	This file defines pin function control of gpio.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++#ifndef __ASM_R8A7798_GPIO_H__
++#define __ASM_R8A7798_GPIO_H__
++
++/* Pin Function Controller:
++ * GPIO_FN_xx - GPIO used to select pin function
++ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
++ */
++enum {
++	GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
++	GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
++	GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
++	GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
++	GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
++	GPIO_GP_0_20, GPIO_GP_0_21,
++
++	GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
++	GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
++	GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
++	GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
++	GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
++	GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
++	GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
++
++	GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
++	GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
++	GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
++	GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
++	GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
++	GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
++	GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
++	GPIO_GP_2_28, GPIO_GP_2_29,
++
++	GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
++	GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
++	GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
++	GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
++	GPIO_GP_3_16,
++
++	GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
++	GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
++	GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
++	GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
++	GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
++	GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
++	GPIO_GP_4_24,
++
++	GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
++	GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
++	GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
++	GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14,
++
++	/* GPSR0 */
++	GPIO_GFN_DU_EXODDF_DU_ODDF_DISP_CDE,
++	GPIO_GFN_DU_EXVSYNC_DU_VSYNC,
++	GPIO_GFN_DU_EXHSYNC_DU_HSYNC,
++	GPIO_GFN_DU_DOTCLKOUT,
++	GPIO_GFN_DU_DB7,
++	GPIO_GFN_DU_DB6,
++	GPIO_GFN_DU_DB5,
++	GPIO_GFN_DU_DB4,
++	GPIO_GFN_DU_DB3,
++	GPIO_GFN_DU_DB2,
++	GPIO_GFN_DU_DG7,
++	GPIO_GFN_DU_DG6,
++	GPIO_GFN_DU_DG5,
++	GPIO_GFN_DU_DG4,
++	GPIO_GFN_DU_DG3,
++	GPIO_GFN_DU_DG2,
++	GPIO_GFN_DU_DR7,
++	GPIO_GFN_DU_DR6,
++	GPIO_GFN_DU_DR5,
++	GPIO_GFN_DU_DR4,
++	GPIO_GFN_DU_DR3,
++	GPIO_GFN_DU_DR2,
++
++	/* GPSR1 */
++	GPIO_GFN_DIGRF_CLKOUT,
++	GPIO_GFN_DIGRF_CLKIN,
++	GPIO_GFN_CANFD_CLK_A,
++	GPIO_GFN_CANFD1_RX,
++	GPIO_GFN_CANFD1_TX,
++	GPIO_GFN_CANFD0_RX_A,
++	GPIO_GFN_CANFD0_TX_A,
++	GPIO_GFN_AVB0_AVTP_CAPTURE,
++	GPIO_GFN_AVB0_AVTP_MATCH,
++	GPIO_FN_AVB0_LINK,
++	GPIO_FN_AVB0_PHY_INT,
++	GPIO_FN_AVB0_MAGIC,
++	GPIO_FN_AVB0_MDC,
++	GPIO_FN_AVB0_MDIO,
++	GPIO_FN_AVB0_TXCREFCLK,
++	GPIO_FN_AVB0_TD3,
++	GPIO_FN_AVB0_TD2,
++	GPIO_FN_AVB0_TD1,
++	GPIO_FN_AVB0_TD0,
++	GPIO_FN_AVB0_TXC,
++	GPIO_FN_AVB0_TX_CTL,
++	GPIO_FN_AVB0_RD3,
++	GPIO_FN_AVB0_RD2,
++	GPIO_FN_AVB0_RD1,
++	GPIO_FN_AVB0_RD0,
++	GPIO_FN_AVB0_RXC,
++	GPIO_FN_AVB0_RX_CTL,
++	GPIO_GFN_IRQ0,
++
++	/* GPSR2 */
++	GPIO_GFN_FSO_TOE_N,
++	GPIO_GFN_FSO_CFE_1_N,
++	GPIO_GFN_FSO_CFE_0_N,
++	GPIO_GFN_SDA3,
++	GPIO_GFN_SCL3,
++	GPIO_GFN_MSIOF0_SS2,
++	GPIO_GFN_MSIOF0_SS1,
++	GPIO_GFN_MSIOF0_SYNC,
++	GPIO_GFN_MSIOF0_SCK,
++	GPIO_GFN_MSIOF0_TXD,
++	GPIO_GFN_MSIOF0_RXD,
++	GPIO_GFN_IRQ5,
++	GPIO_GFN_IRQ4,
++	GPIO_GFN_VI0_FIELD,
++	GPIO_GFN_VI0_DATA11,
++	GPIO_GFN_VI0_DATA10,
++	GPIO_GFN_VI0_DATA9,
++	GPIO_GFN_VI0_DATA8,
++	GPIO_GFN_VI0_DATA7,
++	GPIO_GFN_VI0_DATA6,
++	GPIO_GFN_VI0_DATA5,
++	GPIO_GFN_VI0_DATA4,
++	GPIO_GFN_VI0_DATA3,
++	GPIO_GFN_VI0_DATA2,
++	GPIO_GFN_VI0_DATA1,
++	GPIO_GFN_VI0_DATA0,
++	GPIO_GFN_VI0_VSYNC_N,
++	GPIO_GFN_VI0_HSYNC_N,
++	GPIO_GFN_VI0_CLKENB,
++	GPIO_GFN_VI0_CLK,
++
++	/* GPSR3 */
++	GPIO_GFN_VI1_FIELD,
++	GPIO_GFN_VI1_DATA11,
++	GPIO_GFN_VI1_DATA10,
++	GPIO_GFN_VI1_DATA9,
++	GPIO_GFN_VI1_DATA8,
++	GPIO_GFN_VI1_DATA7,
++	GPIO_GFN_VI1_DATA6,
++	GPIO_GFN_VI1_DATA5,
++	GPIO_GFN_VI1_DATA4,
++	GPIO_GFN_VI1_DATA3,
++	GPIO_GFN_VI1_DATA2,
++	GPIO_GFN_VI1_DATA1,
++	GPIO_GFN_VI1_DATA0,
++	GPIO_GFN_VI1_VSYNC_N,
++	GPIO_GFN_VI1_HSYNC_N,
++	GPIO_GFN_VI1_CLKENB,
++	GPIO_GFN_VI1_CLK,
++
++	/* GPSR4 */
++	GPIO_FN_GETHER_LINK_A,
++	GPIO_FN_GETHER_PHY_INT_A,
++	GPIO_FN_GETHER_MAGIC,
++	GPIO_FN_GETHER_MDC_A,
++	GPIO_FN_GETHER_MDIO_A,
++	GPIO_FN_GETHER_TXCREFCLK_MEGA,
++	GPIO_FN_GETHER_TXCREFCLK,
++	GPIO_FN_GETHER_TD3,
++	GPIO_FN_GETHER_TD2,
++	GPIO_FN_GETHER_TD1,
++	GPIO_FN_GETHER_TD0,
++	GPIO_FN_GETHER_TXC,
++	GPIO_FN_GETHER_TX_CTL,
++	GPIO_FN_GETHER_RD3,
++	GPIO_FN_GETHER_RD2,
++	GPIO_FN_GETHER_RD1,
++	GPIO_FN_GETHER_RD0,
++	GPIO_FN_GETHER_RXC,
++	GPIO_FN_GETHER_RX_CTL,
++	GPIO_GFN_SDA2,
++	GPIO_GFN_SCL2,
++	GPIO_GFN_SDA1,
++	GPIO_GFN_SCL1,
++	GPIO_GFN_SDA0,
++	GPIO_GFN_SCL0,
++
++	/* GPSR5 */
++	GPIO_FN_RPC_INT_N,
++	GPIO_FN_RPC_WP_N,
++	GPIO_FN_RPC_RESET_N,
++	GPIO_FN_QSPI1_SSL,
++	GPIO_FN_QSPI1_IO3,
++	GPIO_FN_QSPI1_IO2,
++	GPIO_FN_QSPI1_MISO_IO1,
++	GPIO_FN_QSPI1_MOSI_IO0,
++	GPIO_FN_QSPI1_SPCLK,
++	GPIO_FN_QSPI0_SSL,
++	GPIO_FN_QSPI0_IO3,
++	GPIO_FN_QSPI0_IO2,
++	GPIO_FN_QSPI0_MISO_IO1,
++	GPIO_FN_QSPI0_MOSI_IO0,
++	GPIO_FN_QSPI0_SPCLK,
++
++	/* IPSR0 */
++	GPIO_IFN_DU_DR2,
++	GPIO_FN_SCK4,
++	GPIO_FN_GETHER_RMII_CRS_DV,
++	GPIO_FN_A0,
++	GPIO_IFN_DU_DR3,
++	GPIO_FN_RX4,
++	GPIO_FN_GETHER_RMII_RX_ER,
++	GPIO_FN_A1,
++	GPIO_IFN_DU_DR4,
++	GPIO_FN_TX4,
++	GPIO_FN_GETHER_RMII_RXD0,
++	GPIO_FN_A2,
++	GPIO_IFN_DU_DR5,
++	GPIO_FN_CTS4_N,
++	GPIO_FN_GETHER_RMII_RXD1,
++	GPIO_FN_A3,
++	GPIO_IFN_DU_DR6,
++	GPIO_FN_RTS4_N_TANS,
++	GPIO_FN_GETHER_RMII_TXD_EN,
++	GPIO_FN_A4,
++	GPIO_IFN_DU_DR7,
++	GPIO_FN_GETHER_RMII_TXD0,
++	GPIO_FN_A5,
++	GPIO_IFN_DU_DG2,
++	GPIO_FN_GETHER_RMII_TXD1,
++	GPIO_FN_A6,
++	GPIO_IFN_DU_DG3,
++	GPIO_FN_CPG_CPCKOUT,
++	GPIO_FN_GETHER_RMII_REFCLK,
++	GPIO_FN_A7,
++	GPIO_FN_PWMFSW0,
++
++	/* IPSR1 */
++	GPIO_IFN_DU_DG4,
++	GPIO_FN_SCL5,
++	GPIO_FN_A8,
++	GPIO_IFN_DU_DG5,
++	GPIO_FN_SDA5,
++	GPIO_FN_GETHER_MDC_B,
++	GPIO_FN_A9,
++	GPIO_IFN_DU_DG6,
++	GPIO_FN_SCIF_CLK_A,
++	GPIO_FN_GETHER_MDIO_B,
++	GPIO_FN_A10,
++	GPIO_IFN_DU_DG7,
++	GPIO_FN_HRX0_A,
++	GPIO_FN_A11,
++	GPIO_IFN_DU_DB2,
++	GPIO_FN_HSCK0_A,
++	GPIO_FN_A12,
++	GPIO_FN_IRQ1,
++	GPIO_IFN_DU_DB3,
++	GPIO_FN_HRTS0_N_A,
++	GPIO_FN_A13,
++	GPIO_FN_IRQ2,
++	GPIO_IFN_DU_DB4,
++	GPIO_FN_HCTS0_N_A,
++	GPIO_FN_A14,
++	GPIO_FN_IRQ3,
++	GPIO_IFN_DU_DB5,
++	GPIO_FN_HTX0_A,
++	GPIO_FN_PWM0_A,
++	GPIO_FN_A15,
++
++	/* IPSR2 */
++	GPIO_IFN_DU_DB6,
++	GPIO_FN_MSIOF3_RXD,
++	GPIO_FN_A16,
++	GPIO_IFN_DU_DB7,
++	GPIO_FN_MSIOF3_TXD,
++	GPIO_FN_A17,
++	GPIO_IFN_DU_DOTCLKOUT,
++	GPIO_FN_MSIOF3_SS1,
++	GPIO_FN_GETHER_LINK_B,
++	GPIO_FN_A18,
++	GPIO_IFN_DU_EXHSYNC_DU_HSYNC,
++	GPIO_FN_MSIOF3_SS2,
++	GPIO_FN_GETHER_PHY_INT_B,
++	GPIO_FN_A19,
++	GPIO_FN_FXR_TXENA_N,
++	GPIO_IFN_DU_EXVSYNC_DU_VSYNC,
++	GPIO_FN_MSIOF3_SCK,
++	GPIO_FN_FXR_TXENB_N,
++	GPIO_IFN_DU_EXODDF_DU_ODDF_DISP_CDE,
++	GPIO_FN_MSIOF3_SYNC,
++	GPIO_IFN_IRQ0,
++	GPIO_FN_CC5_OSCOUT,
++	GPIO_IFN_VI0_CLK,
++	GPIO_FN_MSIOF2_SCK,
++	GPIO_FN_SCK3,
++	GPIO_FN_HSCK3,
++
++	/* IPSR3 */
++	GPIO_IFN_VI0_CLKENB,
++	GPIO_FN_MSIOF2_RXD,
++	GPIO_FN_RX3,
++	GPIO_FN_RD_WR_N,
++	GPIO_FN_HCTS3_N,
++	GPIO_IFN_VI0_HSYNC_N,
++	GPIO_FN_MSIOF2_TXD,
++	GPIO_FN_TX3,
++	GPIO_FN_HRTS3_N,
++	GPIO_IFN_VI0_VSYNC_N,
++	GPIO_FN_MSIOF2_SYNC,
++	GPIO_FN_CTS3_N,
++	GPIO_FN_HTX3,
++	GPIO_IFN_VI0_DATA0,
++	GPIO_FN_MSIOF2_SS1,
++	GPIO_FN_RTS3_N_TANS,
++	GPIO_FN_HRX3,
++	GPIO_IFN_VI0_DATA1,
++	GPIO_FN_MSIOF2_SS2,
++	GPIO_FN_SCK1,
++	GPIO_FN_SPEEDIN_A,
++	GPIO_IFN_VI0_DATA2,
++	GPIO_FN_AVB0_AVTP_PPS,
++	GPIO_IFN_VI0_DATA3,
++	GPIO_FN_HSCK1,
++	GPIO_IFN_VI0_DATA4,
++	GPIO_FN_HRTS1_N,
++	GPIO_FN_RX1_A,
++
++	/* IPSR4 */
++	GPIO_IFN_VI0_DATA5,
++	GPIO_FN_HCTS1_N,
++	GPIO_FN_TX1_A,
++	GPIO_IFN_VI0_DATA6,
++	GPIO_FN_HTX1,
++	GPIO_FN_CTS1_N,
++	GPIO_IFN_VI0_DATA7,
++	GPIO_FN_HRX1,
++	GPIO_FN_RTS1_N_TANS,
++	GPIO_IFN_VI0_DATA8,
++	GPIO_FN_HSCK2,
++	GPIO_IFN_VI0_DATA9,
++	GPIO_FN_HCTS2_N,
++	GPIO_FN_PWM1_A,
++	GPIO_FN_FSO_CFE_0_N_B,
++	GPIO_IFN_VI0_DATA10,
++	GPIO_FN_HRTS2_N,
++	GPIO_FN_PWM2_A,
++	GPIO_IFN_VI0_DATA11,
++	GPIO_FN_HTX2,
++	GPIO_FN_PWM3_A,
++	GPIO_IFN_VI0_FIELD,
++	GPIO_FN_HRX2,
++	GPIO_FN_PWM4_A,
++	GPIO_FN_CS1_N,
++	GPIO_FN_FSCLKST2_N_A,
++
++	/* IPSR5 */
++	GPIO_IFN_VI1_CLK,
++	GPIO_FN_MSIOF1_RXD,
++	GPIO_FN_CS0_N,
++	GPIO_IFN_VI1_CLKENB,
++	GPIO_FN_MSIOF1_TXD,
++	GPIO_FN_D0,
++	GPIO_IFN_VI1_HSYNC_N,
++	GPIO_FN_MSIOF1_SCK,
++	GPIO_FN_D1,
++	GPIO_IFN_VI1_VSYNC_N,
++	GPIO_FN_MSIOF1_SYNC,
++	GPIO_FN_D2,
++	GPIO_IFN_VI1_DATA0,
++	GPIO_FN_MSIOF1_SS1,
++	GPIO_FN_D3,
++	GPIO_FN_MMC_WP,
++	GPIO_IFN_VI1_DATA1,
++	GPIO_FN_MSIOF1_SS2,
++	GPIO_FN_D4,
++	GPIO_FN_MMC_CD,
++	GPIO_IFN_VI1_DATA2,
++	GPIO_FN_CANFD0_TX_B,
++	GPIO_FN_D5,
++	GPIO_FN_MMC_DS,
++	GPIO_IFN_VI1_DATA3,
++	GPIO_FN_CANFD0_RX_B,
++	GPIO_FN_D6,
++	GPIO_FN_MMC_CMD,
++
++	/* IPSR6 */
++	GPIO_IFN_VI1_DATA4,
++	GPIO_FN_CANFD_CLK_B,
++	GPIO_FN_D7,
++	GPIO_FN_MMC_D0,
++	GPIO_IFN_VI1_DATA5,
++	GPIO_FN_D8,
++	GPIO_FN_MMC_D1,
++	GPIO_IFN_VI1_DATA6,
++	GPIO_FN_D9,
++	GPIO_FN_MMC_D2,
++	GPIO_IFN_VI1_DATA7,
++	GPIO_FN_D10,
++	GPIO_FN_MMC_D3,
++	GPIO_IFN_VI1_DATA8,
++	GPIO_FN_D11,
++	GPIO_FN_MMC_CLK,
++	GPIO_IFN_VI1_DATA9,
++	GPIO_FN_TCLK1_A,
++	GPIO_FN_D12,
++	GPIO_FN_MMC_D4,
++	GPIO_IFN_VI1_DATA10,
++	GPIO_FN_TCLK2_A,
++	GPIO_FN_D13,
++	GPIO_FN_MMC_D5,
++	GPIO_IFN_VI1_DATA11,
++	GPIO_FN_SCL4,
++	GPIO_FN_D14,
++	GPIO_FN_MMC_D6,
++
++	/* IPSR7 */
++	GPIO_IFN_VI1_FIELD,
++	GPIO_FN_SDA4,
++	GPIO_FN_D15,
++	GPIO_FN_MMC_D7,
++	GPIO_IFN_SCL0,
++	GPIO_FN_CLKOUT,
++	GPIO_IFN_SDA0,
++	GPIO_FN_BS_N,
++	GPIO_FN_SCK0,
++	GPIO_FN_HSCK0_B,
++	GPIO_IFN_SCL1,
++	GPIO_FN_TPU0TO2,
++	GPIO_FN_RD_N,
++	GPIO_FN_CTS0_N,
++	GPIO_FN_HCTS0_N_B,
++	GPIO_IFN_SDA1,
++	GPIO_FN_TPU0TO3,
++	GPIO_FN_WE0_N,
++	GPIO_FN_RTS0_N_TANS,
++	GPIO_FN_HRTS0_N_B,
++	GPIO_IFN_SCL2,
++	GPIO_FN_WE1_N,
++	GPIO_FN_RX0,
++	GPIO_FN_HRX0_B,
++	GPIO_IFN_SDA2,
++	GPIO_FN_EX_WAIT0,
++	GPIO_FN_TX0,
++	GPIO_FN_HTX0_B,
++	GPIO_IFN_AVB0_AVTP_MATCH,
++	GPIO_FN_TPU0TO0,
++
++	/* IPSR8 */
++	GPIO_IFN_AVB0_AVTP_CAPTURE,
++	GPIO_FN_TPU0TO1,
++	GPIO_IFN_CANFD0_TX_A,
++	GPIO_FN_FXR_TXDA,
++	GPIO_FN_PWM0_B,
++	GPIO_FN_DU_DISP,
++	GPIO_IFN_CANFD0_RX_A,
++	GPIO_FN_RXDA_EXTFXR,
++	GPIO_FN_PWM1_B,
++	GPIO_FN_DU_CDE,
++	GPIO_IFN_CANFD1_TX,
++	GPIO_FN_FXR_TXDB,
++	GPIO_FN_PWM2_B,
++	GPIO_FN_TCLK1_B,
++	GPIO_FN_TX1_B,
++	GPIO_IFN_CANFD1_RX,
++	GPIO_FN_RXDB_EXTFXR,
++	GPIO_FN_PWM3_B,
++	GPIO_FN_TCLK2_B,
++	GPIO_FN_RX1_B,
++	GPIO_IFN_CANFD_CLK_A,
++	GPIO_FN_CLK_EXTFXR,
++	GPIO_FN_PWM4_B,
++	GPIO_FN_SPEEDIN_B,
++	GPIO_FN_SCIF_CLK_B,
++	GPIO_IFN_DIGRF_CLKIN,
++	GPIO_FN_DIGRF_CLKEN_IN,
++	GPIO_IFN_DIGRF_CLKOUT,
++	GPIO_FN_DIGRF_CLKEN_OUT,
++
++	/* IPSR9 */
++	GPIO_IFN_IRQ4,
++	GPIO_FN_VI0_DATA12,
++	GPIO_IFN_IRQ5,
++	GPIO_FN_VI0_DATA13,
++	GPIO_IFN_MSIOF0_RXD,
++	GPIO_FN_DU_DR0,
++	GPIO_FN_VI0_DATA14,
++	GPIO_IFN_MSIOF0_TXD,
++	GPIO_FN_DU_DR1,
++	GPIO_FN_VI0_DATA15,
++	GPIO_IFN_MSIOF0_SCK,
++	GPIO_FN_DU_DG0,
++	GPIO_FN_VI0_DATA16,
++	GPIO_IFN_MSIOF0_SYNC,
++	GPIO_FN_DU_DG1,
++	GPIO_FN_VI0_DATA17,
++	GPIO_IFN_MSIOF0_SS1,
++	GPIO_FN_DU_DB0,
++	GPIO_FN_TCLK3,
++	GPIO_FN_VI0_DATA18,
++	GPIO_IFN_MSIOF0_SS2,
++	GPIO_FN_DU_DB1,
++	GPIO_FN_TCLK4,
++	GPIO_FN_VI0_DATA19,
++
++	/* IPSR10 */
++	GPIO_IFN_SCL3,
++	GPIO_FN_VI0_DATA20,
++	GPIO_IFN_SDA3,
++	GPIO_FN_VI0_DATA21,
++	GPIO_IFN_FSO_CFE_0_N,
++	GPIO_FN_VI0_DATA22,
++	GPIO_IFN_FSO_CFE_1_N,
++	GPIO_FN_VI0_DATA23,
++	GPIO_IFN_FSO_TOE_N,
++};
++
++#endif /* __ASM_R8A7798_GPIO_H__ */
+diff --git a/arch/arm/include/asm/arch-rcar_gen3/r8a7798.h b/arch/arm/include/asm/arch-rcar_gen3/r8a7798.h
+new file mode 100644
+index 0000000..06514f0
+--- /dev/null
++++ b/arch/arm/include/asm/arch-rcar_gen3/r8a7798.h
+@@ -0,0 +1,34 @@
++/*
++ * arch/arm/include/asm/arch-rcar_gen3/r8a7798.h
++ *	This file defines registers and value for r8a7798.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __ASM_ARCH_R8A7798_H
++#define __ASM_ARCH_R8A7798_H
++
++#include "rcar-base.h"
++
++/* Module stop control/status register bits */
++#define MSTP0_BITS	0x00230000
++#define MSTP1_BITS	0xFFFFFFFF
++#define MSTP2_BITS	0x14062FD8
++#define MSTP3_BITS	0xFFFFFFDF
++#define MSTP4_BITS	0x80000184
++#define MSTP5_BITS	0x83FFFFFF
++#define MSTP6_BITS	0xFFFFFFFF
++#define MSTP7_BITS	0xFFFFFFFF
++#define MSTP8_BITS	0x7FF3FFF4
++#define MSTP9_BITS	0xFBF7FF97
++#define MSTP10_BITS	0xFFFEFFE0
++#define MSTP11_BITS	0x000000B7
++
++/* SDHI */
++#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000	/* either MMC0 */
++#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1
++
++#endif /* __ASM_ARCH_R8A7798_H */
+diff --git a/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h b/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h
+index c2ba0fb..c3568b0 100644
+--- a/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h
++++ b/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h
+@@ -16,6 +16,8 @@
+  #include <asm/arch/r8a7796.h>
+  #elif defined(CONFIG_R8A7797)
+  #include <asm/arch/r8a7797.h>
++ #elif defined(CONFIG_R8A7798)
++ #include <asm/arch/r8a7798.h>
+  #else
+  #error "SOC Name not defined"
+  #endif
+diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
+index 4b9a61b..95129ce 100644
+--- a/drivers/mtd/spi/sf_probe.c
++++ b/drivers/mtd/spi/sf_probe.c
+@@ -383,7 +383,7 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash)
+ 	puts("\n");
+ #endif
+ #ifndef CONFIG_SPI_FLASH_BAR
+-#ifndef CONFIG_R8A7797
++#if !defined(CONFIG_R8A7797) && !defined(CONFIG_R8A7798)
+ 	if (((flash->dual_flash == SF_SINGLE_FLASH) &&
+ 	     (flash->size > SPI_FLASH_16MB_BOUN)) ||
+ 	     ((flash->dual_flash > SF_SINGLE_FLASH) &&
+diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
+index 5cb520c..591e75d 100644
+--- a/drivers/net/sh_eth.h
++++ b/drivers/net/sh_eth.h
+@@ -226,7 +226,6 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
+ 	[RMII_MII] =  0x0790,
+ };
+ 
+-#if defined(SH_ETH_TYPE_RZ)
+ static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
+ 	[EDSR]	= 0x0000,
+ 	[EDMR]	= 0x0400,
+@@ -279,7 +278,6 @@ static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
+ 	[MAFCR]	= 0x0778,
+ 	[RMII_MII] =  0x0790,
+ };
+-#endif
+ 
+ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
+ 	[ECMR]	= 0x0100,
+@@ -361,6 +359,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
+ #elif defined(CONFIG_R7S72100)
+ #define SH_ETH_TYPE_RZ
+ #define BASE_IO_ADDR	0xE8203000
++#elif defined(CONFIG_R8A7798)
++#define SH_ETH_TYPE_RZ
++#define BASE_IO_ADDR	0xE7400000
+ #endif
+ 
+ /*
+diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
+index 478824e..ded0d3d 100644
+--- a/drivers/serial/serial_sh.h
++++ b/drivers/serial/serial_sh.h
+@@ -227,7 +227,7 @@ struct uart_port {
+ #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+ 	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) || \
+ 	defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796X) || \
+-	defined(CONFIG_R8A7797)
++	defined(CONFIG_R8A7797) || defined(CONFIG_R8A7798)
+ # define SCIF_ORER	0x0001
+ # define SCSCR_INIT(port)	(port->clk_mode == EXT_CLK ? 0x32 : 0x30)
+ 				/* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
+diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
+index 39d86dd..8124369 100644
+--- a/include/configs/rcar-gen3-common.h
++++ b/include/configs/rcar-gen3-common.h
+@@ -133,6 +133,10 @@
+  #else
+   #define PHYS_SDRAM_1_SIZE		((unsigned long)(0x40000000 - DRAM_RSV_SIZE))
+  #endif
++#elif defined(CONFIG_R8A7798)
++#define CONFIG_NR_DRAM_BANKS		1
++#define PHYS_SDRAM_1			(0x40000000 + DRAM_RSV_SIZE)	/* legacy */
++#define PHYS_SDRAM_1_SIZE		((unsigned long)(0x80000000 - DRAM_RSV_SIZE))
+ #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+ #define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_1_SIZE
+ #else
+-- 
+1.9.1
+
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0019-board-renesas-Add-Condor-board.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0019-board-renesas-Add-Condor-board.patch
new file mode 100644
index 0000000..68e0ac9
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0019-board-renesas-Add-Condor-board.patch
@@ -0,0 +1,537 @@
+From 8dba0b32243d57d48cc8b821b9252b0a7f40e5c4 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Mon, 22 Jan 2018 13:21:35 +0300
+Subject: [PATCH] board: renesas: Add Condor board
+
+Condor is a board based on R-Car V3H SoC (R8A7798)
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+---
+ arch/arm/cpu/armv8/Kconfig       |   7 ++
+ board/renesas/condor/Kconfig     |  15 +++
+ board/renesas/condor/MAINTAINERS |   6 +
+ board/renesas/condor/Makefile    |   9 ++
+ board/renesas/condor/condor.c    | 251 +++++++++++++++++++++++++++++++++++++++
+ configs/r8a7798_condor_defconfig |  10 ++
+ include/configs/r8a7798_condor.h | 159 +++++++++++++++++++++++++
+ 7 files changed, 457 insertions(+)
+ create mode 100644 board/renesas/condor/Kconfig
+ create mode 100644 board/renesas/condor/MAINTAINERS
+ create mode 100644 board/renesas/condor/Makefile
+ create mode 100644 board/renesas/condor/condor.c
+ create mode 100644 configs/r8a7798_condor_defconfig
+ create mode 100644 include/configs/r8a7798_condor.h
+
+diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
+index 343b121..0edd5db 100644
+--- a/arch/arm/cpu/armv8/Kconfig
++++ b/arch/arm/cpu/armv8/Kconfig
+@@ -22,6 +22,9 @@ config TARGET_EAGLE
+ config TARGET_V3MSK
+         bool "V3MSK board"
+ 
++config TARGET_CONDOR
++        bool "CONDOR board"
++
+ endchoice
+ 
+ config R8A7796X
+@@ -53,5 +59,6 @@ source "board/renesas/salvator-x/Kconfig"
+ source "board/renesas/ulcb/Kconfig"
+ source "board/renesas/eagle/Kconfig"
+ source "board/renesas/v3msk/Kconfig"
++source "board/renesas/condor/Kconfig"
+ 
+ endif
+diff --git a/board/renesas/condor/Kconfig b/board/renesas/condor/Kconfig
+new file mode 100644
+index 0000000..21ba79f
+--- /dev/null
++++ b/board/renesas/condor/Kconfig
+@@ -0,0 +1,15 @@
++if TARGET_CONDOR
++
++config SYS_SOC
++	default "rcar_gen3"
++
++config SYS_BOARD
++	default "condor"
++
++config SYS_VENDOR
++	default "renesas"
++
++config SYS_CONFIG_NAME
++	default "r8a7798_condor" if R8A7798
++
++endif
+diff --git a/board/renesas/condor/MAINTAINERS b/board/renesas/condor/MAINTAINERS
+new file mode 100644
+index 0000000..d0442b8
+--- /dev/null
++++ b/board/renesas/condor/MAINTAINERS
+@@ -0,0 +1,6 @@
++CONDOR BOARD
++M:	Cogent Embedded, Inc. <source@cogentembedded.com>
++S:	Maintained
++F:	board/renesas/condor/
++F:	include/configs/r8a7798_condor.h
++F:	configs/r8a7798_condor_defconfig
+diff --git a/board/renesas/condor/Makefile b/board/renesas/condor/Makefile
+new file mode 100644
+index 0000000..4c5d29b
+--- /dev/null
++++ b/board/renesas/condor/Makefile
+@@ -0,0 +1,10 @@
++#
++# board/renesas/condor/Makefile
++#
++# Copyright (C) 2018 Renesas Electronics Corp.
++# Copyright (C) 2018 Cogent Embedded, Inc.
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y	:= condor.o ../rcar-gen3-common/common.o
+diff --git a/board/renesas/condor/condor.c b/board/renesas/condor/condor.c
+new file mode 100644
+index 0000000..d31e5fd
+--- /dev/null
++++ b/board/renesas/condor/condor.c
+@@ -0,0 +1,252 @@
++/*
++ * board/renesas/condor/condor.c
++ *     This is Condor board support.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <malloc.h>
++#include <netdev.h>
++#include <dm.h>
++#include <dm/platform_data/serial_sh.h>
++#include <asm/processor.h>
++#include <asm/mach-types.h>
++#include <asm/io.h>
++#include <asm/errno.h>
++#include <asm/arch/sys_proto.h>
++#include <asm/gpio.h>
++#include <asm/arch/prr_depend.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/rcar_gen3.h>
++#include <asm/arch/rcar-mstp.h>
++#include <asm/arch/sh_sdhi.h>
++#include <i2c.h>
++#include <mmc.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#define SCIF0_MSTP207	(1 << 7)
++#define GETHER_MSTP813	(1 << 13)
++#define RAVB_MSTP812	(1 << 12)
++#define RPC_MSTP917	(1 << 17)
++#define SD0_MSTP314	(1 << 14)
++
++#define SD0CKCR		0xE6150074
++
++void s_init(void)
++{
++	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
++	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
++
++	/* Watchdog init */
++	writel(0xA5A5A500, &rwdt->rwtcsra);
++	writel(0xA5A5A500, &swdt->swtcsra);
++}
++
++int board_early_init_f(void)
++{
++	int freq;
++
++	rcar_prr_init();
++
++	writel(0xa5a5ffff, 0xe6150900);
++	writel(0x5a5a0000, 0xe6150904);
++	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, 0x02000000);
++	/* SCIF0 */
++	mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIF0_MSTP207);
++	/* SDHI0/MMC */
++	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
++	/* Gigabit Ethernet */
++	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, GETHER_MSTP813);
++	/* RAVB Ethernet */
++	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, RAVB_MSTP812);
++	/* QSPI/RPC */
++	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, RPC_MSTP917);
++
++	freq = rcar_get_sdhi_config_clk();
++	writel(freq, SD0CKCR);
++
++	return 0;
++}
++
++int board_init(void)
++{
++	/* adress of boot parameters */
++	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
++
++	/* Init PFC controller */
++	pinmux_init();
++#ifdef CONFIG_RAVB
++	gpio_request(GPIO_GFN_AVB0_AVTP_CAPTURE, NULL);
++	gpio_request(GPIO_GFN_AVB0_AVTP_MATCH, NULL);
++	gpio_request(GPIO_FN_AVB0_LINK, NULL);
++	gpio_request(GPIO_FN_AVB0_PHY_INT, NULL);
++	/* gpio_request(GPIO_FN_AVB0_MAGIC, NULL); */
++	gpio_request(GPIO_FN_AVB0_MDC, NULL);
++	gpio_request(GPIO_FN_AVB0_MDIO, NULL);
++	gpio_request(GPIO_FN_AVB0_TXCREFCLK, NULL);
++	gpio_request(GPIO_FN_AVB0_TD3, NULL);
++	gpio_request(GPIO_FN_AVB0_TD2, NULL);
++	gpio_request(GPIO_FN_AVB0_TD1, NULL);
++	gpio_request(GPIO_FN_AVB0_TD0, NULL);
++	gpio_request(GPIO_FN_AVB0_TXC, NULL);
++	gpio_request(GPIO_FN_AVB0_TX_CTL, NULL);
++	gpio_request(GPIO_FN_AVB0_RD3, NULL);
++	gpio_request(GPIO_FN_AVB0_RD2, NULL);
++	gpio_request(GPIO_FN_AVB0_RD1, NULL);
++	gpio_request(GPIO_FN_AVB0_RD0, NULL);
++	gpio_request(GPIO_FN_AVB0_RXC, NULL);
++	gpio_request(GPIO_FN_AVB0_RX_CTL, NULL);
++	gpio_request(GPIO_IFN_AVB0_AVTP_CAPTURE, NULL);
++	gpio_request(GPIO_FN_AVB0_AVTP_PPS, NULL);
++#endif
++#ifdef CONFIG_SH_ETHER
++	gpio_request(GPIO_FN_GETHER_LINK_A, NULL);
++	gpio_request(GPIO_FN_GETHER_PHY_INT_A, NULL);
++	/* GPIO_FN_GETHER_MAGIC: PHY reset gpio  */
++	gpio_request(GPIO_FN_GETHER_MDC_A, NULL);
++	gpio_request(GPIO_FN_GETHER_MDIO_A, NULL);
++	gpio_request(GPIO_FN_GETHER_TXCREFCLK, NULL);
++	gpio_request(GPIO_FN_GETHER_TXCREFCLK_MEGA, NULL);
++	gpio_request(GPIO_FN_GETHER_TD3, NULL);
++	gpio_request(GPIO_FN_GETHER_TD2, NULL);
++	gpio_request(GPIO_FN_GETHER_TD1, NULL);
++	gpio_request(GPIO_FN_GETHER_TD0, NULL);
++	gpio_request(GPIO_FN_GETHER_TXC, NULL);
++	gpio_request(GPIO_FN_GETHER_TX_CTL, NULL);
++	gpio_request(GPIO_FN_GETHER_RD3, NULL);
++	gpio_request(GPIO_FN_GETHER_RD2, NULL);
++	gpio_request(GPIO_FN_GETHER_RD1, NULL);
++	gpio_request(GPIO_FN_GETHER_RD0, NULL);
++	gpio_request(GPIO_FN_GETHER_RXC, NULL);
++	gpio_request(GPIO_FN_GETHER_RX_CTL, NULL);
++#endif
++	/* QSPI/RPC */
++	gpio_request(GPIO_FN_QSPI0_SPCLK, NULL);
++	gpio_request(GPIO_FN_QSPI0_MOSI_IO0, NULL);
++	gpio_request(GPIO_FN_QSPI0_MISO_IO1, NULL);
++	gpio_request(GPIO_FN_QSPI0_IO2, NULL);
++	gpio_request(GPIO_FN_QSPI0_IO3, NULL);
++	gpio_request(GPIO_FN_QSPI0_SSL, NULL);
++	gpio_request(GPIO_FN_QSPI1_SPCLK, NULL);
++	gpio_request(GPIO_FN_QSPI1_MOSI_IO0, NULL);
++	gpio_request(GPIO_FN_QSPI1_MISO_IO1, NULL);
++	gpio_request(GPIO_FN_QSPI1_IO2, NULL);
++	gpio_request(GPIO_FN_QSPI1_IO3, NULL);
++	gpio_request(GPIO_FN_QSPI1_SSL, NULL);
++	gpio_request(GPIO_FN_RPC_RESET_N, NULL);
++	gpio_request(GPIO_FN_RPC_WP_N, NULL);
++	gpio_request(GPIO_FN_RPC_INT_N, NULL);
++
++	return 0;
++}
++
++#ifdef CONFIG_RAVB
++#define MAHR 0xE68005C0
++#define MALR 0xE68005C8
++#endif
++#ifdef CONFIG_SH_ETHER
++#define MAHR 0xE74005C0
++#define MALR 0xE74005C8
++#endif
++int board_eth_init(bd_t *bis)
++{
++	int ret = -ENODEV;
++#ifdef CONFIG_RAVB
++	u32 val;
++	unsigned char enetaddr[6];
++
++	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
++		return ret;
++
++	/* Set Mac address */
++	val = enetaddr[0] << 24 | enetaddr[1] << 16 |
++	      enetaddr[2] << 8 | enetaddr[3];
++	writel(val, MAHR);
++
++	val = enetaddr[4] << 8 | enetaddr[5];
++	writel(val, MALR);
++
++	ret = ravb_initialize(bis);
++#endif
++#ifdef CONFIG_SH_ETHER
++	u32 val;
++	unsigned char enetaddr[6];
++
++	ret = sh_eth_initialize(bis);
++	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
++		return ret;
++
++	/* Set Mac address */
++	val = enetaddr[0] << 24 | enetaddr[1] << 16 |
++	    enetaddr[2] << 8 | enetaddr[3];
++	writel(val, MAHR);
++
++	val = enetaddr[4] << 8 | enetaddr[5];
++	writel(val, MALR);
++#endif
++	return ret;
++}
++
++/* Condor has KSZ9031RNX */
++int board_phy_config(struct phy_device *phydev)
++{
++	return 0;
++}
++
++int board_mmc_init(bd_t *bis)
++{
++	int ret = -ENODEV;
++#ifdef CONFIG_SH_SDHI
++	/* SDHI2/eMMC */
++	gpio_request(GPIO_FN_MMC_D0, NULL);
++	gpio_request(GPIO_FN_MMC_D1, NULL);
++	gpio_request(GPIO_FN_MMC_D2, NULL);
++	gpio_request(GPIO_FN_MMC_D3, NULL);
++	gpio_request(GPIO_FN_MMC_D4, NULL);
++	gpio_request(GPIO_FN_MMC_D5, NULL);
++	gpio_request(GPIO_FN_MMC_D6, NULL);
++	gpio_request(GPIO_FN_MMC_D7, NULL);
++	gpio_request(GPIO_FN_MMC_CLK, NULL);
++	gpio_request(GPIO_FN_MMC_CMD, NULL);
++	gpio_request(GPIO_FN_MMC_CD, NULL);
++	gpio_request(GPIO_FN_MMC_WP, NULL);
++
++	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 0,
++			   SH_SDHI_QUIRK_64BIT_BUF);
++#endif
++	return ret;
++}
++
++int dram_init(void)
++{
++	gd->ram_size = PHYS_SDRAM_1_SIZE;
++
++	return 0;
++}
++
++void dram_init_banksize(void)
++{
++	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++}
++
++const struct rcar_sysinfo sysinfo = {
++	CONFIG_RCAR_BOARD_STRING
++};
++
++void reset_cpu(ulong addr)
++{
++}
++
++#if defined(CONFIG_DISPLAY_BOARDINFO)
++int checkboard(void)
++{
++	printf("Board: %s\n", sysinfo.board_string);
++	return 0;
++}
++#endif
+diff --git a/configs/r8a7798_condor_defconfig b/configs/r8a7798_condor_defconfig
+new file mode 100644
+index 0000000..1cab2ae
+--- /dev/null
++++ b/configs/r8a7798_condor_defconfig
+@@ -0,0 +1,10 @@
++CONFIG_ARM=y
++CONFIG_RCAR_GEN3=y
++CONFIG_DM_SERIAL=y
++CONFIG_TARGET_CONDOR=y
++CONFIG_R8A7798=y
++CONFIG_SPL=y
++CONFIG_SH_SDHI=y
++CONFIG_SPI_FLASH=y
++CONFIG_SPI_FLASH_SPANSION=y
++CONFIG_SPI_FLASH_BAR=y
+diff --git a/include/configs/r8a7798_condor.h b/include/configs/r8a7798_condor.h
+new file mode 100644
+index 0000000..f0b2e0b
+--- /dev/null
++++ b/include/configs/r8a7798_condor.h
+@@ -0,0 +1,160 @@
++/*
++ * include/configs/r8a7798_condor.h
++ *     This file is Condor board configuration.
++ *     CPU r8a7798.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __CONDOR_H
++#define __CONDOR_H
++
++#undef DEBUG
++#define CONFIG_RCAR_BOARD_STRING "Condor"
++#define CONFIG_RCAR_TARGET_STRING "r8a7798"
++
++#include "rcar-gen3-common.h"
++
++//#define CONFIG_SYS_DCACHE_OFF
++//#define CONFIG_SYS_ICACHE_OFF
++
++/* SCIF */
++#define CONFIG_SCIF_CONSOLE
++#define CONFIG_CONS_SCIF0
++#define CONFIG_SH_SCIF_CLK_FREQ	CONFIG_S3D4_CLK_FREQ
++
++/* [A] Hyper Flash */
++/* use to RPC(SPI Multi I/O Bus Controller) */
++
++	/* underconstruction */
++
++#define CONFIG_SYS_NO_FLASH
++#if defined(CONFIG_SYS_NO_FLASH)
++#define CONFIG_SPI
++#define CONFIG_RCAR_GEN3_QSPI
++#define CONFIG_SH_QSPI_BASE	0xEE200000
++#define CONFIG_CMD_SF
++#define CONFIG_CMD_SPI
++#define CONFIG_SPI_FLASH
++#define CONFIG_SPI_FLASH_SPANSION
++#else
++#undef CONFIG_CMD_SF
++#undef CONFIG_CMD_SPI
++#undef CONFIG_SPI_FLASH
++#undef CONFIG_SPI_FLASH_SPANSION
++#endif
++
++#if 1
++/* Ethernet RAVB */
++#define CONFIG_RAVB
++#define CONFIG_RAVB_PHY_ADDR	0x0
++#define CONFIG_RAVB_PHY_MODE	PHY_INTERFACE_MODE_RGMII_ID
++#define CONFIG_NET_MULTI
++#define CONFIG_PHYLIB
++#define CONFIG_PHY_MICREL
++#define CONFIG_BITBANGMII
++#define CONFIG_BITBANGMII_MULTI
++#define CONFIG_SH_ETHER_BITBANG
++#else
++/* SH Ether */
++#define CONFIG_NET_MULTI
++#define CONFIG_SH_ETHER
++#define CONFIG_SH_ETHER_USE_PORT	0
++#define CONFIG_SH_ETHER_PHY_ADDR	0x0
++#define CONFIG_SH_ETHER_PHY_MODE	PHY_INTERFACE_MODE_RGMII_ID
++#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
++#define CONFIG_SH_ETHER_CACHE_WRITEBACK
++#define CONFIG_SH_ETHER_CACHE_INVALIDATE
++#define CONFIG_PHYLIB
++#define CONFIG_PHY_MICREL
++#define CONFIG_BITBANGMII
++#define CONFIG_BITBANGMII_MULTI
++#endif
++
++/* Board Clock */
++/* XTAL_CLK : 33.33MHz */
++#define RCAR_XTAL_CLK		33333333u
++#define CONFIG_SYS_CLK_FREQ	RCAR_XTAL_CLK
++/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
++/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz          */
++#define CONFIG_CP_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2)
++#define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 192 / 2)
++#define CONFIG_S3D2_CLK_FREQ	(266666666u/2)
++#define CONFIG_S3D4_CLK_FREQ	(266666666u/4)
++
++/* Generic Timer Definitions (use in assembler source) */
++#define COUNTER_FREQUENCY	0xFE502A /* 16.66MHz from CPclk */
++
++/* Generic Interrupt Controller Definitions */
++#define GICD_BASE	(0xF1010000)
++#define GICC_BASE	(0xF1020000)
++#define CONFIG_GICV2
++
++/* i2c */
++#define CONFIG_SYS_I2C
++#define CONFIG_SYS_I2C_SH
++#define CONFIG_SYS_I2C_SLAVE		0x60
++#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS	1
++#define CONFIG_SYS_I2C_SH_SPEED0	400000
++#define CONFIG_SH_I2C_DATA_HIGH		4
++#define CONFIG_SH_I2C_DATA_LOW		5
++#define CONFIG_SH_I2C_CLOCK		10000000
++
++#define CONFIG_SYS_I2C_POWERIC_ADDR	0x30
++
++/* USB */
++#undef CONFIG_CMD_USB
++
++/* SDHI */
++#define CONFIG_MMC
++#define CONFIG_CMD_MMC
++#define CONFIG_GENERIC_MMC
++#define CONFIG_SH_SDHI_FREQ	200000000
++#define CONFIG_SH_SDHI_MMC
++
++/* ENV setting */
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
++#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
++#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
++
++//#define CONFIG_ENV_IS_IN_MMC
++#define CONFIG_ENV_IS_IN_SPI_FLASH
++
++#if defined(CONFIG_ENV_IS_IN_MMC)
++/* Environment in eMMC, at the end of 2nd "boot sector" */
++#define CONFIG_ENV_OFFSET	(-CONFIG_ENV_SIZE)
++#define CONFIG_SYS_MMC_ENV_DEV	0
++#define CONFIG_SYS_MMC_ENV_PART	2
++#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
++/* Environment in QSPI */
++#define CONFIG_ENV_ADDR		0x700000
++#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
++#else
++#define CONFIG_ENV_IS_NOWHERE
++#endif
++
++/* Module clock supply/stop status bits */
++/* MFIS */
++#define CONFIG_SMSTP2_ENA	0x00002000
++/* serial(SCIF0) */
++#define CONFIG_SMSTP3_ENA	0x00000400
++/* INTC-AP, INTC-EX */
++#define CONFIG_SMSTP4_ENA	0x00000180
++
++#define CONFIG_EXTRA_ENV_SETTINGS \
++	"fdt_high=0xffffffffffffffff\0" \
++	"initrd_high=0xffffffffffffffff\0" \
++	"ethaddr=2E:11:22:33:44:55\0"
++
++#define CONFIG_BOOTARGS \
++	"root=/dev/nfs rw ip=dhcp"
++
++#define CONFIG_BOOTCOMMAND \
++	"bootp 0x48080000 Image; tftp 0x48000000 r8a7798-condor.dtb; " \
++	"booti 0x48080000 - 0x48000000"
++
++#endif /* __CONDOR_H */
+-- 
+1.9.1
+
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot_2015.04.bbappend b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot_2015.04.bbappend
index 8171d10..3be0e60 100644
--- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot_2015.04.bbappend
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot_2015.04.bbappend
@@ -17,6 +17,8 @@ SRC_URI_append = " \
     file://0015-board-renesas-Add-V3M-Eagle-board.patch \
     file://0016-tools-fix-build-fail.patch \
     file://0017-board-renesas-Add-V3MSK-board.patch \
+    file://0018-arm-renesas-Add-Renesas-R8A7798-SoC-support.patch \
+    file://0019-board-renesas-Add-Condor-board.patch \
     file://0021-ARM-rcar_gen3-Add-RPC-flash-definitions.patch \
     file://0022-mtd-Add-RPC-HyperFlash-support.patch \
     file://0023-board-renesas-salvator-x-Enable-RPC-clock.patch \
diff --git a/meta-rcar-gen3-adas/recipes-kernel/kernel-module-mmngr/kernel-module-mmngr.bbappend b/meta-rcar-gen3-adas/recipes-kernel/kernel-module-mmngr/kernel-module-mmngr.bbappend
index 6abdc7d..7118d46 100644
--- a/meta-rcar-gen3-adas/recipes-kernel/kernel-module-mmngr/kernel-module-mmngr.bbappend
+++ b/meta-rcar-gen3-adas/recipes-kernel/kernel-module-mmngr/kernel-module-mmngr.bbappend
@@ -2,5 +2,6 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
 
 MMNGR_CFG_eagle = "MMNGR_V3MSK"
 MMNGR_CFG_v3msk = "MMNGR_V3MSK"
+MMNGR_CFG_condor = "MMNGR_V3MSK"
 
 SRC_URI_append = " file://0002-mmngr-Add-V3MSK-board.patch"
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch
index ffaf796..483ba45 100644
--- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch
@@ -26,10 +26,11 @@ Videobox Mini board on R8A7795 SoC
 Videobox Mini board on R8A7797 SoC
 Videobox2 board on R8A7795 ES1.x SoC
 Videobox2 board on R8A7795 SoC
+Condor board on R8A7798 SoC
 
 Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
 ---
- arch/arm64/boot/dts/renesas/Makefile               |   20 +
+ arch/arm64/boot/dts/renesas/Makefile               |   21 +
  arch/arm64/boot/dts/renesas/legacy/Makefile        |    8 +
  .../renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts    | 1710 +++++++++++++++++++
  .../renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts    |  441 +++++
@@ -67,6 +68,7 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
  arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts  |  518 ++++++
  arch/arm64/boot/dts/renesas/r8a7797-v3msk-view.dts |  298 ++++
  arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts      |  314 ++++
+ arch/arm64/boot/dts/renesas/r8a7798-condor.dts     |  939 +++++++++++
  arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi      |  545 ++++++
  arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi      |   30 +
  arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi       |   46 +
@@ -75,7 +77,7 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
  arch/arm64/boot/dts/renesas/ulcb-vb.dtsi           | 1726 +++++++++++++++++++
  arch/arm64/boot/dts/renesas/ulcb-vb2.dtsi          | 1772 ++++++++++++++++++++
  arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi          |  578 +++++++
- 46 files changed, 19159 insertions(+)
+ 47 files changed, 20099 insertions(+)
  create mode 100644 arch/arm64/boot/dts/renesas/legacy/Makefile
  create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts
  create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts
@@ -113,6 +115,7 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
  create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts
  create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk-view.dts
  create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a7798-condor.dts
  create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi
  create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi
  create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi
@@ -123,10 +126,10 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
  create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi
 
 diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
-index f9c71df..1c63893 100644
+index f9c71df..3b5cff6 100644
 --- a/arch/arm64/boot/dts/renesas/Makefile
 +++ b/arch/arm64/boot/dts/renesas/Makefile
-@@ -6,5 +6,25 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
+@@ -6,5 +6,26 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
  dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb
  dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs.dtb
  
@@ -146,6 +149,7 @@ index f9c71df..1c63893 100644
 +dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-view.dtb
 +dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-kf.dtb
 +dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-vbm.dtb
++dtb-$(CONFIG_ARCH_R8A7798) += r8a7798-condor.dtb
 +
 +# ADAS legacy boards
 +subdir-y	:= legacy
@@ -12759,6 +12763,952 @@ index 0000000..91d10c5
 +	non-removable;
 +	status = "okay";
 +};
+diff --git a/arch/arm64/boot/dts/renesas/r8a7798-condor.dts b/arch/arm64/boot/dts/renesas/r8a7798-condor.dts
+new file mode 100644
+index 0000000..ed9cc28
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a7798-condor.dts
+@@ -0,0 +1,940 @@
++/*
++ * Device Tree Source for the Condor board
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++/dts-v1/;
++#include "r8a7798.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++	model = "Renesas Condor board based on r8a7798";
++	compatible = "renesas,condor", "renesas,r8a7798";
++
++	aliases {
++		serial0 = &scif0;
++		ethernet0 = &avb;
++	};
++
++	chosen {
++		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
++		stdout-path = "serial0:115200n8";
++	};
++
++
++	memory@48000000 {
++		device_type = "memory";
++		/* first 128MB is reserved for secure area. */
++		reg = <0x0 0x48000000 0x0 0x38000000>;
++	};
++
++	reserved-memory {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		/* device specific region for Lossy Decompression */
++		lossy_decompress: linux,lossy_decompress {
++			no-map;
++			reg = <0x00000000 0x6c000000 0x0 0x03000000>;
++		};
++
++		/* global autoconfigured region for contiguous allocations */
++		linux,cma {
++			compatible = "shared-dma-pool";
++			reusable;
++			reg = <0x00000000 0x6f000000 0x0 0x10000000>;
++			linux,cma-default;
++		};
++
++		/* device specific region for contiguous allocations */
++		linux,multimedia {
++			compatible = "shared-dma-pool";
++			reusable;
++			reg = <0x00000000 0x7f000000 0x0 0x01000000>;
++		};
++	};
++
++	mmngr {
++		compatible = "renesas,mmngr";
++		memory-region = <&lossy_decompress>;
++	};
++
++	mmngrbuf {
++		compatible = "renesas,mmngrbuf";
++	};
++
++	vspm_if {
++		compatible = "renesas,vspm_if";
++	};
++
++	lvds-encoder {
++		compatible = "thine,thc63lvdm83d";
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@0 {
++				reg = <0>;
++				lvds_enc_in: endpoint {
++					remote-endpoint = <&du_out_lvds0>;
++				};
++			};
++			port@1 {
++				reg = <1>;
++				lvds_enc_out: endpoint {
++					remote-endpoint = <&lvds_in>;
++				};
++			};
++		};
++	};
++
++	lvds {
++		compatible = "lvds-connector";
++
++		width-mm = <210>;
++		height-mm = <158>;
++
++		panel-timing {
++			clock-frequency = <138000000>;
++			hactive = <1920>;
++			vactive = <1080>;
++			hsync-len = <32>;
++			hfront-porch = <20>;
++			hback-porch = <160>;
++			vfront-porch = <3>;
++			vback-porch = <31>;
++			vsync-len = <5>;
++		};
++
++		port {
++			lvds_in: endpoint {
++				remote-endpoint = <&lvds_enc_out>;
++			};
++		};
++	};
++
++	hdmi-out {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con: endpoint {
++			remote-endpoint = <&adv7511_out>;
++			};
++		};
++	};
++
++	dclkin_p0: clock-out0 {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <148500000>;
++	};
++
++	msiof_ref_clk: msiof-ref-clock {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <66666666>;
++	};
++
++	vcc_3v3: regulator0 {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-VCC3V3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	vcc_vddq_vin0: regulator1 {
++		compatible = "regulator-fixed";
++		regulator-name = "VCC-VDDQ-VIN0";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++};
++
++&du {
++	status = "okay";
++
++	ports {
++		port@0 {
++			endpoint {
++				remote-endpoint = <&adv7511_in>;
++			};
++		};
++	};
++};
++
++&extal_clk {
++	clock-frequency = <16666666>;
++};
++
++&extalr_clk {
++	clock-frequency = <32768>;
++};
++
++&pfc {
++	pinctrl-0 = <&scif_clk_pins>;
++	pinctrl-names = "default";
++
++	canfd0_pins: canfd0 {
++		groups = "canfd0_data_a";
++		function = "canfd0";
++	};
++
++	scif0_pins: scif0 {
++		groups = "scif0_data";
++		function = "scif0";
++	};
++
++	scif_clk_pins: scif_clk {
++		groups = "scif_clk_b";
++		function = "scif_clk";
++	};
++
++	i2c0_pins: i2c0 {
++		groups = "i2c0";
++		function = "i2c0";
++	};
++
++	i2c1_pins: i2c1 {
++		groups = "i2c1";
++		function = "i2c1";
++	};
++
++	avb_pins: avb {
++		groups = "avb_mdc";
++		function = "avb";
++	};
++
++	sdhi2_pins_1v8: sdhi2_1v8 {
++		groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
++		function = "mmc";
++		power-source = <1800>;
++	};
++
++	sdhi2_pins_3v3: sdhi2_3v3 {
++		groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
++		function = "mmc";
++		power-source = <3300>;
++	};
++
++	tpu_pins: tpu {
++		/* GP1_19 pin; CP4 test point */
++		groups = "tpu_to0";
++		function = "tpu";
++	};
++};
++
++&scif0 {
++	pinctrl-0 = <&scif0_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++};
++
++&scif_clk {
++	clock-frequency = <14745600>;
++	status = "okay";
++};
++
++&sdhi2 {
++	/* used for on-board eMMC */
++	pinctrl-0 = <&sdhi2_pins_3v3>;
++	pinctrl-1 = <&sdhi2_pins_1v8>;
++	pinctrl-names = "default", "state_uhs";
++
++	vmmc-supply = <&vcc_3v3>;
++	vqmmc-supply = <&vcc_vddq_vin0>;
++	mmc-hs200-1_8v;
++	mmc-hs400-1_8v;
++	bus-width = <8>;
++	non-removable;
++	status = "okay";
++};
++
++&i2c0 {
++	pinctrl-0 = <&i2c0_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++	clock-frequency = <400000>;
++
++	hdmi@39{
++		compatible = "adi,adv7511w";
++		#sound-dai-cells = <0>;
++		reg = <0x39>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
++
++		adi,input-depth = <8>;
++		adi,input-colorspace = "rgb";
++		adi,input-clock = "1x";
++		adi,input-style = <1>;
++		adi,input-justification = "evenly";
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@0 {
++				reg = <0>;
++				adv7511_in: endpoint {
++					remote-endpoint = <&lvds_enc_out>;
++				};
++			};
++			port@1 {
++				reg = <1>;
++				adv7511_out: endpoint {
++					remote-endpoint = <&hdmi_con>;
++				};
++			};
++		};
++	};
++
++	gpio_exp_20: gpio@20 {
++		compatible = "onsemi,pca9654";
++		reg = <0x20>;
++		gpio-controller;
++		#gpio-cells = <2>;
++	};
++
++	gpio_exp_21: gpio@21 {
++		compatible = "onsemi,pca9654";
++		reg = <0x21>;
++		gpio-controller;
++		#gpio-cells = <2>;
++	};
++};
++
++&i2c1 {
++	pinctrl-0 = <&i2c1_pins>;
++	pinctrl-names = "default";
++
++	status = "okay";
++	clock-frequency = <400000>;
++
++	ov106xx@0 {
++		compatible = "ovti,ov106xx";
++		reg = <0x60>;
++
++		port@0 {
++			ov106xx_in0: endpoint {
++				clock-lanes = <0>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&vin0ep0>;
++			};
++		};
++		port@1 {
++			ov106xx_max9286_des0ep0: endpoint@0 {
++				remote-endpoint = <&max9286_des0ep0>;
++			};
++		};
++	};
++
++	ov106xx@1 {
++		compatible = "ovti,ov106xx";
++		reg = <0x61>;
++
++		port@0 {
++			ov106xx_in1: endpoint {
++				clock-lanes = <0>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&vin1ep0>;
++			};
++		};
++		port@1 {
++			ov106xx_max9286_des0ep1: endpoint@0 {
++				remote-endpoint = <&max9286_des0ep1>;
++			};
++		};
++	};
++
++	ov106xx@2 {
++		compatible = "ovti,ov106xx";
++		reg = <0x62>;
++
++		port@0 {
++			ov106xx_in2: endpoint {
++				clock-lanes = <0>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&vin2ep0>;
++			};
++		};
++		port@1 {
++			ov106xx_max9286_des0ep2: endpoint@0 {
++				remote-endpoint = <&max9286_des0ep2>;
++			};
++		};
++	};
++
++	ov106xx@3 {
++		compatible = "ovti,ov106xx";
++		reg = <0x63>;
++
++		port@0 {
++			ov106xx_in3: endpoint {
++				clock-lanes = <0>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&vin3ep0>;
++			};
++		};
++		port@1 {
++			ov106xx_des0ep3: endpoint {
++				remote-endpoint = <&max9286_des0ep3>;
++			};
++		};
++	};
++
++	ov106xx@4 {
++		compatible = "ovti,ov106xx";
++		reg = <0x64>;
++
++		port@0 {
++			ov106xx_in4: endpoint {
++				clock-lanes = <0>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&vin4ep0>;
++			};
++		};
++		port@1 {
++			ov106xx_max9286_des1ep0: endpoint@0 {
++				remote-endpoint = <&max9286_des1ep0>;
++			};
++		};
++	};
++
++	ov106xx@5 {
++		compatible = "ovti,ov106xx";
++		reg = <0x65>;
++
++		port@0 {
++			ov106xx_in5: endpoint {
++				clock-lanes = <0>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&vin5ep0>;
++			};
++		};
++		port@1 {
++			ov106xx_max9286_des1ep1: endpoint@0 {
++				remote-endpoint = <&max9286_des1ep1>;
++			};
++		};
++	};
++
++	ov106xx@6 {
++		compatible = "ovti,ov106xx";
++		reg = <0x66>;
++
++		port@0 {
++			ov106xx_in6: endpoint {
++				clock-lanes = <0>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&vin6ep0>;
++			};
++		};
++		port@1 {
++			ov106xx_max9286_des1ep2: endpoint@0 {
++				remote-endpoint = <&max9286_des1ep2>;
++			};
++		};
++	};
++
++	ov106xx@7 {
++		compatible = "ovti,ov106xx";
++		reg = <0x67>;
++
++		port@0 {
++			ov106xx_in7: endpoint {
++				clock-lanes = <0>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&vin7ep0>;
++			};
++		};
++		port@1 {
++			ov106xx_des1ep3: endpoint {
++				remote-endpoint = <&max9286_des1ep3>;
++			};
++		};
++	};
++
++	max9286@0 {
++		compatible = "maxim,max9286";
++		reg = <0x48>;
++		gpios = <&gpio_exp_20 0 GPIO_ACTIVE_LOW>; /* MAX9286 PWDN */
++		maxim,gpio0 = <0>;
++		maxim,sensor_delay = <100>;
++		maxim,links = <4>;
++		maxim,lanes = <4>;
++		maxim,resetb-gpio = <1>;
++		maxim,fsync-mode = "automatic";
++		maxim,timeout = <100>;
++
++		port@0 {
++			max9286_des0ep0: endpoint@0 {
++				max9271-addr = <0x50>;
++				dvp-order = <1>;
++				remote-endpoint = <&ov106xx_in0>;
++			};
++			max9286_des0ep1: endpoint@1 {
++				max9271-addr = <0x51>;
++				dvp-order = <1>;
++				remote-endpoint = <&ov106xx_in1>;
++			};
++			max9286_des0ep2: endpoint@2 {
++				max9271-addr = <0x52>;
++				dvp-order = <1>;
++				remote-endpoint = <&ov106xx_in2>;
++			};
++			max9286_des0ep3: endpoint@3 {
++				max9271-addr = <0x53>;
++				dvp-order = <1>;
++				remote-endpoint = <&ov106xx_in3>;
++			};
++		};
++		port@1 {
++			max9286_csi0ep0: endpoint {
++				csi-rate = <700>;
++				remote-endpoint = <&csi2_40_ep>;
++			};
++		};
++	};
++
++	max9286@1 {
++		compatible = "maxim,max9286";
++		reg = <0x4a>;
++		gpios = <&gpio_exp_21 0 GPIO_ACTIVE_LOW>; /* MAX9286 PWDN */
++		maxim,gpio0 = <0>;
++		maxim,sensor_delay = <100>;
++		maxim,links = <4>;
++		maxim,lanes = <4>;
++		maxim,resetb-gpio = <1>;
++		maxim,fsync-mode = "automatic";
++		maxim,timeout = <100>;
++
++		port@0 {
++			max9286_des1ep0: endpoint@0 {
++				max9271-addr = <0x54>;
++				dvp-order = <1>;
++				remote-endpoint = <&ov106xx_in4>;
++			};
++			max9286_des1ep1: endpoint@1 {
++				max9271-addr = <0x55>;
++				dvp-order = <1>;
++				remote-endpoint = <&ov106xx_in5>;
++			};
++			max9286_des1ep2: endpoint@2 {
++				max9271-addr = <0x56>;
++				dvp-order = <1>;
++				remote-endpoint = <&ov106xx_in6>;
++			};
++			max9286_des1ep3: endpoint@3 {
++				max9271-addr = <0x57>;
++				dvp-order = <1>;
++				remote-endpoint = <&ov106xx_in7>;
++			};
++		};
++		port@1 {
++			max9286_csi1ep0: endpoint {
++				csi-rate = <700>;
++				remote-endpoint = <&csi2_41_ep>;
++			};
++		};
++	};
++};
++
++&pcie_bus_clk {
++	clock-frequency = <100000000>;
++	status = "okay";
++};
++
++&pciec {
++	status = "okay";
++};
++
++&wdt0 {
++	timeout-sec = <60>;
++	status = "okay";
++};
++
++&cmt0 {
++	status = "okay";
++};
++
++&cmt1 {
++	status = "okay";
++};
++
++&cmt2 {
++	status = "okay";
++};
++
++&cmt3 {
++	status = "okay";
++};
++
++&tpu {
++	pinctrl-0 = <&tpu_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&tmu0 {
++	status = "okay";
++};
++
++&tmu1 {
++	status = "okay";
++};
++
++&tmu2 {
++	status = "okay";
++};
++
++&tmu3 {
++	status = "okay";
++};
++
++&tmu4 {
++	status = "okay";
++};
++
++&avb {
++	pinctrl-0 = <&avb_pins>;
++	pinctrl-names = "default";
++	renesas,no-ether-link;
++	phy-handle = <&phy0>;
++	status = "okay";
++	phy-int-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>;
++
++	phy0: ethernet-phy@0 {
++		rxc-skew-ps = <1500>;
++		rxdv-skew-ps = <420>; /* default */
++		rxd0-skew-ps = <420>; /* default */
++		rxd1-skew-ps = <420>; /* default */
++		rxd2-skew-ps = <420>; /* default */
++		rxd3-skew-ps = <420>; /* default */
++		txc-skew-ps = <900>; /* default */
++		txen-skew-ps = <420>; /* default */
++		txd0-skew-ps = <420>; /* default */
++		txd1-skew-ps = <420>; /* default */
++		txd2-skew-ps = <420>; /* default */
++		txd3-skew-ps = <420>; /* default */
++		reg = <0>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
++		max-speed = <1000>;
++	};
++};
++
++&vin0 {
++	status = "okay";
++
++	ports {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		port@0 {
++			vin0ep0: endpoint {
++				csi,select = "csi40";
++				virtual,channel = <0>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&ov106xx_in0>;
++			};
++		};
++		port@1 {
++			csi0ep0: endpoint {
++				remote-endpoint = <&csi2_40_ep>;
++			};
++		};
++		port@2 {
++			vin0_max9286_des0ep0: endpoint@0 {
++				remote-endpoint = <&max9286_des0ep0>;
++			};
++		};
++	};
++};
++
++&vin1 {
++	status = "okay";
++
++	ports {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		port@0 {
++			vin1ep0: endpoint {
++				csi,select = "csi40";
++				virtual,channel = <1>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&ov106xx_in1>;
++			};
++		};
++		port@1 {
++			csi0ep1: endpoint {
++				remote-endpoint = <&csi2_40_ep>;
++			};
++		};
++		port@2 {
++			vin1_max9286_des0ep1: endpoint@0 {
++				remote-endpoint = <&max9286_des0ep1>;
++			};
++		};
++	};
++};
++
++&vin2 {
++	status = "okay";
++
++	ports {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		port@0 {
++			vin2ep0: endpoint {
++				csi,select = "csi40";
++				virtual,channel = <2>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&ov106xx_in2>;
++			};
++		};
++		port@1 {
++			csi0ep2: endpoint {
++				remote-endpoint = <&csi2_40_ep>;
++			};
++		};
++		port@2 {
++			vin2_max9286_des0ep2: endpoint@0 {
++				remote-endpoint = <&max9286_des0ep2>;
++			};
++		};
++	};
++};
++
++&vin3 {
++	status = "okay";
++
++	ports {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		port@0 {
++			vin3ep0: endpoint {
++				csi,select = "csi40";
++				virtual,channel = <3>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&ov106xx_in3>;
++			};
++		};
++		port@1 {
++			csi0ep3: endpoint {
++				remote-endpoint = <&csi2_40_ep>;
++			};
++		};
++		port@2 {
++			vin3_max9286_des0ep3: endpoint@0 {
++				remote-endpoint = <&max9286_des0ep3>;
++			};
++		};
++	};
++};
++
++&vin4 {
++	status = "okay";
++
++	ports {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		port@0 {
++			vin4ep0: endpoint {
++				csi,select = "csi41";
++				virtual,channel = <0>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&ov106xx_in4>;
++			};
++		};
++		port@1 {
++			csi1ep0: endpoint {
++				remote-endpoint = <&csi2_41_ep>;
++			};
++		};
++		port@2 {
++			vin4_max9286_des1ep0: endpoint@0 {
++				remote-endpoint = <&max9286_des1ep0>;
++			};
++		};
++	};
++};
++
++&vin5 {
++	status = "okay";
++
++	ports {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		port@0 {
++			vin5ep0: endpoint {
++				csi,select = "csi41";
++				virtual,channel = <1>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&ov106xx_in5>;
++			};
++		};
++		port@1 {
++			csi1ep1: endpoint {
++				remote-endpoint = <&csi2_41_ep>;
++			};
++		};
++		port@2 {
++			vin5_max9286_des1ep1: endpoint@0 {
++				remote-endpoint = <&max9286_des1ep1>;
++			};
++		};
++	};
++};
++
++&vin6 {
++	status = "okay";
++
++	ports {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		port@0 {
++			vin6ep0: endpoint {
++				csi,select = "csi41";
++				virtual,channel = <2>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&ov106xx_in6>;
++			};
++		};
++		port@1 {
++			csi1ep2: endpoint {
++				remote-endpoint = <&csi2_41_ep>;
++			};
++		};
++		port@2 {
++			vin6_max9286_des1ep2: endpoint@0 {
++				remote-endpoint = <&max9286_des1ep2>;
++			};
++		};
++	};
++};
++
++&vin7 {
++	status = "okay";
++
++	ports {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		port@0 {
++			vin7ep0: endpoint {
++				csi,select = "csi41";
++				virtual,channel = <3>;
++				data-lanes = <1 2 3 4>;
++				remote-endpoint = <&ov106xx_in7>;
++			};
++		};
++		port@1 {
++			csi1ep3: endpoint {
++				remote-endpoint = <&csi2_41_ep>;
++			};
++		};
++		port@2 {
++			vin7_max9286_des1ep3: endpoint@0 {
++				remote-endpoint = <&max9286_des1ep3>;
++			};
++		};
++	};
++};
++
++&canfd {
++	pinctrl-0 = <&canfd0_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	channel0 {
++		status = "okay";
++	};
++};
++
++&csi2_40 {
++	status = "okay";
++
++	virtual,channel {
++		csi2_vc0 {
++			data,type = "ycbcr422";
++			receive,vc = <0>;
++		};
++		csi2_vc1 {
++			data,type = "ycbcr422";
++			receive,vc = <1>;
++		};
++		csi2_vc2 {
++			data,type = "ycbcr422";
++			receive,vc = <2>;
++		};
++		csi2_vc3 {
++			data,type = "ycbcr422";
++			receive,vc = <3>;
++		};
++	};
++
++	port {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		csi2_40_ep: endpoint {
++			clock-lanes = <0>;
++			data-lanes = <1 2 3 4>;
++			csi-rate = <300>;
++		};
++	};
++};
++
++&csi2_41 {
++	status = "okay";
++
++	virtual,channel {
++		csi2_vc0 {
++			data,type = "ycbcr422";
++			receive,vc = <0>;
++		};
++		csi2_vc1 {
++			data,type = "ycbcr422";
++			receive,vc = <1>;
++		};
++		csi2_vc2 {
++			data,type = "ycbcr422";
++			receive,vc = <2>;
++		};
++		csi2_vc3 {
++			data,type = "ycbcr422";
++			receive,vc = <3>;
++		};
++	};
++
++	port {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		csi2_41_ep: endpoint {
++			clock-lanes = <0>;
++			data-lanes = <1 2 3 4>;
++			csi-rate = <300>;
++		};
++	};
++};
 diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi
 new file mode 100644
 index 0000000..b469ca6
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0051-arm64-renesas-r8a7798-Add-Renesas-R8A7798-SoC-suppor.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0051-arm64-renesas-r8a7798-Add-Renesas-R8A7798-SoC-suppor.patch
new file mode 100644
index 0000000..a4763d4
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0051-arm64-renesas-r8a7798-Add-Renesas-R8A7798-SoC-suppor.patch
@@ -0,0 +1,6197 @@
+From e8fd03e53c50c67a2aebf19f39a9f14b583f0e2d Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Sun, 14 May 2017 14:48:08 +0300
+Subject: [PATCH] arm64: renesas: r8a7798: Add Renesas R8A7798 SoC support
+
+This adds Renesas R8A7798 SoC support
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Mikhail Ulyanov <mikhail.ulyanov@cogentembedded.com>
+---
+ arch/arm64/Kconfig.platforms                  |    8 +
+ arch/arm64/boot/dts/renesas/r8a7798.dtsi      | 1584 +++++++++++++
+ drivers/clk/renesas/Kconfig                   |    1 +
+ drivers/clk/renesas/Makefile                  |    1 +
+ drivers/clk/renesas/r8a7798-cpg-mssr.c        |  284 +++
+ drivers/clk/renesas/rcar-gen3-cpg.c           |   13 +-
+ drivers/clk/renesas/renesas-cpg-mssr.c        |    8 +
+ drivers/clk/renesas/renesas-cpg-mssr.h        |    3 +
+ drivers/cpufreq/cpufreq-dt-platdev.c          |    1 +
+ drivers/gpio/gpio-rcar.c                      |    7 +-
+ drivers/gpu/drm/rcar-du/rcar_du_drv.c         |    4 +-
+ drivers/gpu/drm/rcar-du/rcar_du_group.c       |    8 +-
+ drivers/i2c/busses/i2c-rcar.c                 |    1 +
+ drivers/iommu/ipmmu-vmsa.c                    |    6 +-
+ drivers/media/platform/soc_camera/Kconfig     |    2 +-
+ drivers/media/platform/soc_camera/rcar_csi2.c |   15 +-
+ drivers/media/platform/soc_camera/rcar_vin.c  |   97 +-
+ drivers/media/platform/vsp1/vsp1_lif.c        |   10 +-
+ drivers/mmc/host/sh_mobile_sdhi.c             |    4 +-
+ drivers/net/ethernet/renesas/ravb_main.c      |    4 +-
+ drivers/pci/host/pcie-rcar.c                  |   62 +-
+ drivers/pinctrl/sh-pfc/Kconfig                |    5 +
+ drivers/pinctrl/sh-pfc/Makefile               |    1 +
+ drivers/pinctrl/sh-pfc/core.c                 |    9 +-
+ drivers/pinctrl/sh-pfc/pfc-r8a7798.c          | 3151 +++++++++++++++++++++++++
+ drivers/pinctrl/sh-pfc/sh_pfc.h               |   11 +-
+ drivers/soc/renesas/Makefile                  |    4 +
+ drivers/soc/renesas/r8a7798-sysc.c            |   57 +
+ drivers/soc/renesas/rcar-rst.c                |    3 +
+ drivers/soc/renesas/rcar-sysc.c               |    5 +
+ drivers/soc/renesas/rcar-sysc.h               |    3 +
+ drivers/soc/renesas/rcar_ems_ctrl.c           |    8 +-
+ drivers/soc/renesas/renesas-soc.c             |   10 +
+ drivers/spi/spi-sh-msiof.c                    |    7 +-
+ drivers/thermal/rcar_gen3_thermal.c           |   13 +-
+ include/dt-bindings/clock/r8a7798-cpg-mssr.h  |   56 +
+ include/dt-bindings/power/r8a7798-sysc.h      |   46 +
+ 37 files changed, 5470 insertions(+), 42 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a7798.dtsi
+ create mode 100644 drivers/clk/renesas/r8a7798-cpg-mssr.c
+ create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7798.c
+ create mode 100644 drivers/soc/renesas/r8a7798-sysc.c
+ create mode 100644 include/dt-bindings/clock/r8a7798-cpg-mssr.h
+ create mode 100644 include/dt-bindings/power/r8a7798-sysc.h
+
+diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
+index d3b6771..119a7e3 100644
+--- a/arch/arm64/Kconfig.platforms
++++ b/arch/arm64/Kconfig.platforms
+@@ -172,6 +172,14 @@ config ARCH_R8A7797
+ 	help
+ 	  This enables support for the Renesas R-Car V3M SoC.
+ 
++config ARCH_R8A7798
++	bool "Renesas R-Car V3H SoC Platform"
++	select SYS_SUPPORTS_SH_TMU
++	select SYS_SUPPORTS_SH_CMT
++	depends on ARCH_RENESAS
++	help
++	  This enables support for the Renesas R-Car V3H SoC.
++
+ config ARCH_STRATIX10
+ 	bool "Altera's Stratix 10 SoCFPGA Family"
+ 	help
+diff --git a/arch/arm64/boot/dts/renesas/r8a7798.dtsi b/arch/arm64/boot/dts/renesas/r8a7798.dtsi
+new file mode 100644
+index 0000000..ee8e282
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a7798.dtsi
+@@ -0,0 +1,1584 @@
++/*
++ * Device Tree Source for the r8a7798 SoC
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include <dt-bindings/clock/r8a7798-cpg-mssr.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/power/r8a7798-sysc.h>
++
++/ {
++	compatible = "renesas,r8a7798";
++	#address-cells = <2>;
++	#size-cells = <2>;
++
++	aliases {
++		csi2_40 = &csi2_40;
++		csi2_41 = &csi2_41;
++		i2c0 = &i2c0;
++		i2c1 = &i2c1;
++		i2c2 = &i2c2;
++		i2c3 = &i2c3;
++		i2c4 = &i2c4;
++		i2c5 = &i2c5;
++		spi1 = &msiof0;
++		spi2 = &msiof1;
++		spi3 = &msiof2;
++		spi4 = &msiof3;
++		vin0 = &vin0;
++		vin1 = &vin1;
++		vin2 = &vin2;
++		vin3 = &vin3;
++		vin4 = &vin4;
++		vin5 = &vin5;
++		vin6 = &vin6;
++		vin7 = &vin7;
++		vin8 = &vin8;
++		vin9 = &vin9;
++		vin10 = &vin10;
++		vin11 = &vin11;
++		vin12 = &vin12;
++		vin13 = &vin13;
++		vin14 = &vin14;
++		vin15 = &vin15;
++		tsc0 = &tsc1;
++		tsc1 = &tsc2;
++	};
++
++	psci {
++		compatible = "arm,psci-1.0";
++		method = "smc";
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		a53_0: cpu@0 {
++			compatible = "arm,cortex-a53", "arm,armv8";
++			reg = <0x0>;
++			device_type = "cpu";
++			power-domains = <&sysc R8A7798_PD_CA53_CPU0>;
++			next-level-cache = <&L2_CA53>;
++			enable-method = "psci";
++			cpu-idle-states = <&CPU_SLEEP_0>;
++			#cooling-cells = <2>;
++			dynamic-power-coefficient = <277>;
++			cooling-min-level = <0>;
++			cooling-max-level = <2>;
++			clocks =<&cpg CPG_CORE R8A7798_CLK_Z2>;
++			operating-points-v2 = <&cluster0_opp_tb0>;
++			/*cpu-supply = <&vdd_dvfs>;*/
++		};
++
++		a53_1: cpu@1 {
++			compatible = "arm,cortex-a53","arm,armv8";
++			reg = <0x1>;
++			device_type = "cpu";
++			power-domains = <&sysc R8A7798_PD_CA53_CPU1>;
++			next-level-cache = <&L2_CA53>;
++			enable-method = "psci";
++			cpu-idle-states = <&CPU_SLEEP_0>;
++			operating-points-v2 = <&cluster0_opp_tb0>;
++		};
++
++		a53_2: cpu@2 {
++			compatible = "arm,cortex-a53","arm,armv8";
++			reg = <0x2>;
++			device_type = "cpu";
++			power-domains = <&sysc R8A7798_PD_CA53_CPU2>;
++			next-level-cache = <&L2_CA53>;
++			enable-method = "psci";
++			cpu-idle-states = <&CPU_SLEEP_0>;
++			operating-points-v2 = <&cluster0_opp_tb0>;
++		};
++
++		a53_3: cpu@3 {
++			compatible = "arm,cortex-a53","arm,armv8";
++			reg = <0x3>;
++			device_type = "cpu";
++			power-domains = <&sysc R8A7798_PD_CA53_CPU3>;
++			next-level-cache = <&L2_CA53>;
++			enable-method = "psci";
++			cpu-idle-states = <&CPU_SLEEP_0>;
++			operating-points-v2 = <&cluster0_opp_tb0>;
++		};
++
++		idle-states {
++			entry-method = "psci";
++
++			CPU_SLEEP_0: cpu-sleep-0 {
++				compatible = "arm,idle-state";
++				arm,psci-suspend-param = <0x0010000>;
++				local-timer-stop;
++				entry-latency-us = <639>;
++				exit-latency-us = <680>;
++				min-residency-us = <1088>;
++				status = "disabled";
++			};
++		};
++	};
++
++	L2_CA53: cache-controller@1 {
++		compatible = "cache";
++		power-domains = <&sysc R8A7798_PD_CA53_SCU>;
++		cache-unified;
++		cache-level = <2>;
++	};
++
++	cluster0_opp_tb0: opp_table0 {
++		compatible = "operating-points-v2";
++		opp-shared;
++
++		opp@1000000000 {
++			opp-hz = /bits/ 64 <1000000000>;
++			opp-microvolt = <850000>; /* TBD; section 87.2 */
++			clock-latency-ns = <300000>;
++		};
++	};
++
++	extal_clk: extal {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board */
++		clock-frequency = <0>;
++	};
++
++	extalr_clk: extalr {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		/* This value must be overridden by the board */
++		clock-frequency = <0>;
++	};
++
++	can_clk: can {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* MSIOF reference clock - to be overridden by boards that provide it */
++	msiof_ref_clk: msiof-ref-clock {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External PCIe clock - can be overridden by the board */
++	pcie_bus_clk: pcie_bus {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* External SCIF clock - to be overridden by boards that provide it */
++	scif_clk: scif {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <0>;
++	};
++
++	/* DU input dot clock - tob be overriden by boards that provide it */
++	du_dotclkin0: dclkin-0 {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <148500000>;
++	};
++
++	soc {
++		compatible = "simple-bus";
++		interrupt-parent = <&gic>;
++
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		gic: interrupt-controller@0xf1010000 {
++			compatible = "arm,gic-400";
++			#interrupt-cells = <3>;
++			#address-cells = <0>;
++			interrupt-controller;
++			reg = <0x0 0xf1010000 0 0x1000>,
++			      <0x0 0xf1020000 0 0x20000>,
++			      <0x0 0xf1040000 0 0x20000>,
++			      <0x0 0xf1060000 0 0x20000>;
++			interrupts = <GIC_PPI 9
++					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
++		};
++
++		gpio0: gpio@e6050000 {
++			compatible = "renesas,gpio-r8a7798",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6050000 0 0x50>;
++			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 0 22>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 912>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++		};
++
++		gpio1: gpio@e6051000 {
++			compatible = "renesas,gpio-r8a7798",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6051000 0 0x50>;
++			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 32 28>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 911>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++		};
++
++		gpio2: gpio@e6052000 {
++			compatible = "renesas,gpio-r8a7798",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6052000 0 0x50>;
++			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 64 29>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 910>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++		};
++
++		gpio3: gpio@e6053000 {
++			compatible = "renesas,gpio-r8a7798",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6053000 0 0x50>;
++			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 96 17>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 909>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++		};
++
++		gpio4: gpio@e6054000 {
++			compatible = "renesas,gpio-r8a7798",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6054000 0 0x50>;
++			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 128 25>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 908>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++		};
++
++		gpio5: gpio@e6055000 {
++			compatible = "renesas,gpio-r8a7798",
++				     "renesas,gpio-rcar";
++			reg = <0 0xe6055000 0 0x50>;
++			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
++			#gpio-cells = <2>;
++			gpio-controller;
++			gpio-ranges = <&pfc 0 160 15>;
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			clocks = <&cpg CPG_MOD 907>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++		};
++
++		pmu_a53 {
++			compatible = "arm,cortex-a53-pmu";
++			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-affinity = <&a53_0>,
++					     <&a53_1>,
++					     <&a53_2>,
++					     <&a53_3>;
++		};
++
++		timer {
++			compatible = "arm,armv8-timer";
++			interrupts = <GIC_PPI 13
++					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
++				     <GIC_PPI 14
++					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
++				     <GIC_PPI 11
++					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
++				     <GIC_PPI 10
++					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
++		};
++
++		wdt0: wdt@e6020000 {
++			compatible = "renesas,r8a7798-wdt", "renesas,rcar-gen3-wdt";
++			reg = <0 0xe6020000 0 0x0c>;
++			clocks = <&cpg CPG_MOD 402>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		cpg: clock-controller@e6150000 {
++			compatible = "renesas,r8a7798-cpg-mssr";
++			reg = <0 0xe6150000 0 0x1000>;
++			clocks = <&extal_clk>, <&extalr_clk>;
++			clock-names = "extal", "extalr";
++			#clock-cells = <2>;
++			#power-domain-cells = <0>;
++		};
++
++		csi2_40: csi2@feaa0000 {
++			compatible = "renesas,r8a7798-csi2";
++			reg = <0 0xfeaa0000 0 0x10000>;
++			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 716>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		csi2_41: csi2@feab0000 {
++			compatible = "renesas,r8a7798-csi2";
++			reg = <0 0xfeab0000 0 0x10000>;
++			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 715>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		prr: chipid@fff00044 {
++			compatible = "renesas,prr";
++			reg = <0 0xfff00044 0 4>;
++		};
++
++		rst: reset-controller@e6160000 {
++			compatible = "renesas,r8a7798-rst";
++			reg = <0 0xe6160000 0 0x0200>;
++		};
++
++		sysc: system-controller@e6180000 {
++			compatible = "renesas,r8a7798-sysc";
++			reg = <0 0xe6180000 0 0x0440>;
++			#power-domain-cells = <1>;
++		};
++
++		pfc: pfc@e6060000 {
++			compatible = "renesas,pfc-r8a7798";
++			reg = <0 0xe6060000 0 0x50c>;
++		};
++
++		intc_ex: interrupt-controller@e61c0000 {
++			compatible = "renesas,intc-ex-r8a7798", "renesas,irqc";
++			#interrupt-cells = <2>;
++			interrupt-controller;
++			reg = <0 0xe61c0000 0 0x200>;
++			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;		/* SPI1:IRQ1, SPI2:IRQ2, SPI3:IRQ3, SPI18:IRQ4, SPI161:IRQ5 */
++			clocks = <&cpg CPG_MOD 407>;				/* RMSTPCR4/bit7:INTC-EX */
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++		};
++
++		ipmmu_vi: mmu@febd0000 {
++			compatible = "renesas,ipmmu-r8a7798";
++			reg = <0 0xfebd0000 0 0x1000>; /* IPMMU-VI */
++			renesas,ipmmu-main = <&ipmmu_mm 14>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_vc: mmu@fe6b0000 {
++			compatible = "renesas,ipmmu-r8a7798";
++			reg = <0 0xfe6b0000 0 0x1000>; /* IPMMU-VC */
++			renesas,ipmmu-main = <&ipmmu_mm 12>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ir: mmu@ff8b0000 {
++			compatible = "renesas,ipmmu-r8a7798";
++			reg = <0 0xff8b0000 0 0x1000>; /* IPMMU-IR */
++			renesas,ipmmu-main = <&ipmmu_mm 3>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_rt: mmu@ffc80000 {
++			compatible = "renesas,ipmmu-r8a7798";
++			reg = <0 0xffc80000 0 0x1000>; /* IPMMU-RT */
++			renesas,ipmmu-main = <&ipmmu_mm 10>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_ds0: mmu@e6740000 {
++			compatible = "renesas,ipmmu-r8a7798";
++			reg = <0 0xe6740000 0 0x1000>; /* IPMMU-DS1 */
++			renesas,ipmmu-main = <&ipmmu_mm 0>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_vip0: mmu@e7b00000 {
++			compatible = "renesas,ipmmu-r8a7798";
++			reg = <0 0xe7b00000 0 0x1000>; /* IPMMU-VIP0 */
++			renesas,ipmmu-main = <&ipmmu_mm 0>; /* FIXME missing in datasheet */
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_vip1: mmu@e7960000 {
++			compatible = "renesas,ipmmu-r8a7798";
++			reg = <0 0xe7960000 0 0x1000>; /* IPMMU-VIP1 */
++			renesas,ipmmu-main = <&ipmmu_mm 0>; /* FIXME missing in datasheet */
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		ipmmu_mm: mmu@e67b0000 {
++			compatible = "renesas,ipmmu-r8a7798";
++			reg = <0 0xe67b0000 0 0x1000>; /* IPMMU-MM */
++			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
++			#iommu-cells = <1>;
++			status = "disabled";
++		};
++
++		dmac1: dma-controller@e7300000 {
++			compatible = "renesas,dmac-r8a7798",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe7300000 0 0x10000>;
++			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
++
++
++			interrupt-names = "error",
++					"ch0", "ch1", "ch2", "ch3",
++					"ch4", "ch5", "ch6", "ch7",
++					"ch8", "ch9", "ch10", "ch11",
++					"ch12", "ch13", "ch14", "ch15";
++			clocks = <&cpg CPG_MOD 218>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			#dma-cells = <1>;
++			dma-channels = <16>;
++			iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
++			       <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
++			       <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
++			       <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
++			       <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
++			       <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
++			       <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
++			       <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
++		};
++
++		dmac2: dma-controller@e7310000 {
++			compatible = "renesas,dmac-r8a7798",
++				     "renesas,rcar-dmac";
++			reg = <0 0xe7310000 0 0x10000>;
++			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH
++				      GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;		/* SPI307::SYS-DMAC2 err,
++										   SPI312~319:SYS-DMAC2.ch0~SYS-DMAC1.ch7 */
++			interrupt-names = "error",
++					"ch0", "ch1", "ch2", "ch3",
++					"ch4", "ch5", "ch6", "ch7",
++					"ch8", "ch9", "ch10", "ch11",
++					"ch12", "ch13", "ch14", "ch15";
++			clocks = <&cpg CPG_MOD 217>;				/* RMSTPCR2/bit17:SYS-DMAC2 */
++			clock-names = "fck";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			#dma-cells = <1>;
++			dma-channels = <16>;
++			iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
++			       <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
++			       <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
++			       <&ipmmu_ds0 22>, <&ipmmu_ds0 23>,
++			       <&ipmmu_ds0 24>, <&ipmmu_ds0 25>,
++			       <&ipmmu_ds0 26>, <&ipmmu_ds0 27>,
++			       <&ipmmu_ds0 28>, <&ipmmu_ds0 29>,
++			       <&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
++		};
++
++		avb: ethernet@e6800000 {
++			compatible = "renesas,etheravb-r8a7798",
++				     "renesas,etheravb-rcar-gen3";
++			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
++			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;		/* SPI39~63:Ethernet AVB.ch0~24 */
++										/* @@ errreq_avb_p[0]~[3] add (T.B.D) */
++			interrupt-names = "ch0", "ch1", "ch2", "ch3",
++					  "ch4", "ch5", "ch6", "ch7",
++					  "ch8", "ch9", "ch10", "ch11",
++					  "ch12", "ch13", "ch14", "ch15",
++					  "ch16", "ch17", "ch18", "ch19",
++					  "ch20", "ch21", "ch22", "ch23",
++					  "ch24";
++			clocks = <&cpg CPG_MOD 812>;				/* RMSTPCR8/bit12:EAVB-IF */
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			phy-mode = "rgmii-id";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		canfd: canfd@e66c0000 {
++			compatible = "renesas,r8a7798-canfd",
++				     "renesas,rcar-gen3-canfd";
++			reg = <0 0xe66c0000 0 0x8000>;
++			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
++				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 914>,
++			       <&cpg CPG_CORE R8A7798_CLK_CANFD>,
++			       <&can_clk>;
++			clock-names = "fck", "canfd", "can_clk";
++			assigned-clocks = <&cpg CPG_CORE R8A7798_CLK_CANFD>;
++			assigned-clock-rates = <40000000>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++
++			channel0 {
++				status = "disabled";
++			};
++
++			channel1 {
++				status = "disabled";
++			};
++		};
++
++
++		cmt0: timer@ffca0000 {
++			compatible = "renesas,cmt-48-r8a7798", "renesas,cmt-48-gen2";
++			reg = <0 0xffca0000 0 0x1004>;
++			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 303>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++
++			renesas,channels-mask = <0x60>;
++
++			status = "disabled";
++		};
++
++		cmt1: timer@e6130000 {
++			compatible = "renesas,cmt-48-r8a7798", "renesas,cmt-48-gen2";
++			reg = <0 0xe6130000 0 0x1004>;
++			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 302>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++
++			renesas,channels-mask = <0xff>;
++
++			status = "disabled";
++		};
++
++		cmt2: timer@e6140000 {
++			compatible = "renesas,cmt-48-r8a7798", "renesas,cmt-48-gen2";
++			reg = <0 0xe6140000 0 0x1004>;
++			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 301>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++
++			renesas,channels-mask = <0xff>;
++
++			status = "disabled";
++		};
++
++		cmt3: timer@e6148000 {
++			compatible = "renesas,cmt-48-r8a7798", "renesas,cmt-48-gen2";
++			reg = <0 0xe6148000 0 0x1004>;
++			interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 300>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++
++			renesas,channels-mask = <0xff>;
++
++			status = "disabled";
++		};
++
++		tpu: pwm@e6e80000 {
++			compatible = "renesas,tpu-r8a7798", "renesas,tpu";
++			reg = <0 0xe6e80000 0 0x100>;
++			clocks = <&cpg CPG_MOD 304>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++			#pwm-cells = <4>;
++		};
++
++		tmu0: timer@e61e0000 {
++			compatible = "renesas,tmu-r8a7798", "renesas,tmu";
++			reg = <0 0xe61e0000 0 0x30>;
++			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 125>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			#renesas,channels = <3>;
++			status = "disabled";
++		};
++
++		tmu1: timer@e6fc0000 {
++			compatible = "renesas,tmu-r8a7798", "renesas,tmu";
++			reg = <0 0xe6fc0000 0 0x30>;
++			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 124>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			#renesas,channels = <3>;
++			status = "disabled";
++		};
++
++		tmu2: timer@e6fd0000 {
++			compatible = "renesas,tmu-r8a7798", "renesas,tmu";
++			reg = <0 0xe6fd0000 0 0x30>;
++			interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 123>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			#renesas,channels = <3>;
++			status = "disabled";
++		};
++
++		tmu3: timer@e6fe0000 {
++			compatible = "renesas,tmu-r8a7798", "renesas,tmu";
++			reg = <0 0xe6fe0000 0 0x30>;
++			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 122>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			#renesas,channels = <3>;
++			status = "disabled";
++		};
++
++		tmu4: timer@ffc00000 {
++			compatible = "renesas,tmu-r8a7798", "renesas,tmu";
++			reg = <0 0xffc00000 0 0x30>;
++			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 121>;
++			clock-names = "fck";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			#renesas,channels = <3>;
++			status = "disabled";
++		};
++
++		pwm0: pwm@e6e30000 {
++			compatible = "renesas,pwm-r8a7798", "renesas,pwm-rcar";
++			reg = <0 0xe6e30000 0 0x10>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;				/* RMSTPCR5/bit23:PWM */
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		pwm1: pwm@e6e31000 {
++			compatible = "renesas,pwm-r8a7798", "renesas,pwm-rcar";
++			reg = <0 0xe6e31000 0 0x10>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;				/* RMSTPCR5/bit23:PWM */
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		pwm2: pwm@e6e32000 {
++			compatible = "renesas,pwm-r8a7798", "renesas,pwm-rcar";
++			reg = <0 0xe6e32000 0 0x10>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;				/* RMSTPCR5/bit23:PWM */
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		pwm3: pwm@e6e33000 {
++			compatible = "renesas,pwm-r8a7798", "renesas,pwm-rcar";
++			reg = <0 0xe6e33000 0 0x10>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;				/* RMSTPCR5/bit23:PWM */
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		pwm4: pwm@e6e34000 {
++			compatible = "renesas,pwm-r8a7798", "renesas,pwm-rcar";
++			reg = <0 0xe6e34000 0 0x10>;
++			#pwm-cells = <2>;
++			clocks = <&cpg CPG_MOD 523>;				/* RMSTPCR5/bit23:PWM */
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		hscif0: serial@e6540000 {
++			compatible = "renesas,hscif-r8a7798",
++				     "renesas,rcar-gen3-hscif",
++				     "renesas,hscif";
++			reg = <0 0xe6540000 0 96>;
++			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;		/* SPI154:HSCIF.ch0 */
++			clocks = <&cpg CPG_MOD 520>,
++				 <&cpg CPG_CORE R8A7798_CLK_S2D1>,
++				 <&scif_clk>;					/* RMSTPCR5/bit20:HSCIF0 */
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x31>, <&dmac1 0x30>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		hscif1: serial@e6550000 {
++			compatible = "renesas,hscif-r8a7798",
++				     "renesas,rcar-gen3-hscif",
++				     "renesas,hscif";
++			reg = <0 0xe6550000 0 96>;
++			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;		/* SPI155:HSCIF.ch1 */
++			clocks = <&cpg CPG_MOD 519>,
++				 <&cpg CPG_CORE R8A7798_CLK_S2D1>,
++				 <&scif_clk>;					/* RMSTPCR5/bit19:HSCIF1 */
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x33>, <&dmac1 0x32>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		hscif2: serial@e6560000 {
++			compatible = "renesas,hscif-r8a7798",
++				     "renesas,rcar-gen3-hscif",
++				     "renesas,hscif";
++			reg = <0 0xe6560000 0 96>;
++			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;		/* SPI144:HSCIF.ch2 */
++			clocks = <&cpg CPG_MOD 518>,
++				 <&cpg CPG_CORE R8A7798_CLK_S2D1>,
++				 <&scif_clk>;					/* RMSTPCR5/bit18:HSCIF2 */
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x35>, <&dmac1 0x34>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		hscif3: serial@e66a0000 {
++			compatible = "renesas,hscif-r8a7798",
++				     "renesas,rcar-gen3-hscif",
++				     "renesas,hscif";
++			reg = <0 0xe66a0000 0 96>;
++			//interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;		/* SPI145:HSCIF.ch3 */
++			clocks = <&cpg CPG_MOD 517>,
++				 <&cpg CPG_CORE R8A7798_CLK_S2D1>,
++				 <&scif_clk>;					/* RMSTPCR5/bit17:HSCIF3 */
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x37>, <&dmac1 0x36>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		scif0: serial@e6e60000 {
++			compatible = "renesas,scif-r8a7798",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6e60000 0 64>;
++			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;		/* SPI152:SCIF.ch0 */
++			clocks = <&cpg CPG_MOD 207>,
++				 <&cpg CPG_CORE R8A7798_CLK_S2D1>,
++				 <&scif_clk>;					/* RMSTPCR2/bit7:SCIF0 */
++			/*clock-names = "fck", "sck", "brg_int", "scif_clk"; */
++			clock-names = "fck";
++			dmas = <&dmac1 0x51>, <&dmac1 0x50>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		scif1: serial@e6e68000 {
++			compatible = "renesas,scif-r8a7798",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6e68000 0 64>;
++			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;		/* SPI153:SCIF.ch1 */
++			clocks = <&cpg CPG_MOD 206>,
++				 <&cpg CPG_CORE R8A7798_CLK_S2D1>,
++				 <&scif_clk>;					/* RMSTPCR2/bit6:SCIF1 */
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x53>, <&dmac1 0x52>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		scif3: serial@e6c50000 {
++			compatible = "renesas,scif-r8a7798",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6c50000 0 64>;
++			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;		/* SPI23:SCIF.ch3 */
++			clocks = <&cpg CPG_MOD 204>,
++				 <&cpg CPG_CORE R8A7798_CLK_S2D1>,
++				 <&scif_clk>;					/* RMSTPCR2/bit4:SCIF3 */
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x57>, <&dmac1 0x56>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		scif4: serial@e6c40000 {
++			compatible = "renesas,scif-r8a7798",
++				     "renesas,rcar-gen3-scif", "renesas,scif";
++			reg = <0 0xe6c40000 0 64>;
++			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;		/* SPI16:SCIF.ch4 */
++			clocks = <&cpg CPG_MOD 203>,
++				 <&cpg CPG_CORE R8A7798_CLK_S2D1>,
++				 <&scif_clk>;					/* RMSTPCR2/bit3:SCIF4 */
++			clock-names = "fck", "brg_int", "scif_clk";
++			dmas = <&dmac1 0x59>, <&dmac1 0x58>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		i2c0: i2c@e6500000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7798";
++			reg = <0 0xe6500000 0 0x40>;
++			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 931>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			dmas = <&dmac1 0x91>, <&dmac1 0x90>;
++			dma-names = "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		i2c1: i2c@e6508000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7798";
++			reg = <0 0xe6508000 0 0x40>;
++			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 930>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			dmas = <&dmac1 0x93>, <&dmac1 0x92>;
++			dma-names = "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		i2c2: i2c@e6510000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7798";
++			reg = <0 0xe6510000 0 0x40>;
++			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 929>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			dmas = <&dmac1 0x95>, <&dmac1 0x94>;
++			dma-names = "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		i2c3: i2c@e66d0000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7798";
++			reg = <0 0xe66d0000 0 0x40>;
++			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 928>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			dmas = <&dmac1 0x97>, <&dmac1 0x96>;
++			dma-names = "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		i2c4: i2c@e66d8000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7798";
++			reg = <0 0xe66d8000 0 0x40>;
++			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 927>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			dmas = <&dmac1 0x99>, <&dmac1 0x98>;
++			dma-names = "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		i2c5: i2c@e66e0000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,i2c-r8a7798";
++			reg = <0 0xe66e0000 0 0x40>;
++			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 00>; /* FIXME missing entry in MSSR */
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			dmas = <&dmac1 0x99>, <&dmac1 0x98>;
++			dma-names = "tx", "rx";
++			i2c-scl-internal-delay-ns = <6>;
++			status = "disabled";
++		};
++
++		msiof0: spi@e6e90000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,msiof-r8a7798";
++			reg = <0 0xe6e90000 0 0x64>;
++			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 211>, <&msiof_ref_clk>;
++			clock-names = "msiof_clk", "msiof_ref_clk";
++			dmas = <&dmac1 0x41>, <&dmac1 0x40>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		msiof1: spi@e6ea0000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,msiof-r8a7798";
++			reg = <0 0xe6ea0000 0 0x0064>;
++			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 210>, <&msiof_ref_clk>;
++			clock-names = "msiof_clk", "msiof_ref_clk";
++			dmas = <&dmac1 0x43>, <&dmac1 0x42>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		msiof2: spi@e6c00000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,msiof-r8a7798";
++			reg = <0 0xe6c00000 0 0x0064>;
++			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 209>, <&msiof_ref_clk>;
++			clock-names = "msiof_clk", "msiof_ref_clk";
++			dmas = <&dmac1 0x45>, <&dmac1 0x44>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		msiof3: spi@e6c10000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "renesas,msiof-r8a7798";
++			reg = <0 0xe6c10000 0 0x0064>;
++			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 208>, <&msiof_ref_clk>;
++			clock-names = "msiof_clk", "msiof_ref_clk";
++			dmas = <&dmac1 0x47>, <&dmac1 0x46>;
++			dma-names = "tx", "rx";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++
++		pciec: pcie@fe000000 {
++			compatible = "renesas,pcie-r8a7798",
++				     "renesas,pcie-rcar-gen3";
++			reg = <0 0xfe000000 0 0x80000>,
++				<0 0xe65d0000 0 0x8000>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			bus-range = <0x00 0xff>;
++			device_type = "pci";
++			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
++				0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
++				0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
++				0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
++			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
++			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
++				<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
++				<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 0>;
++			interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
++			clock-names = "pcie", "pcie_bus";
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		vin0: video@e6ef0000 {
++			compatible = "renesas,vin-r8a7798";
++			reg = <0 0xe6ef0000 0 0x1000>;
++			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 811>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		vin1: video@e6ef1000 {
++			compatible = "renesas,vin-r8a7798";
++			reg = <0 0xe6ef1000 0 0x1000>;
++			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 810>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		vin2: video@e6ef2000 {
++			compatible = "renesas,vin-r8a7798";
++			reg = <0 0xe6ef2000 0 0x1000>;
++			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 809>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		vin3: video@e6ef3000 {
++			compatible = "renesas,vin-r8a7798";
++			reg = <0 0xe6ef3000 0 0x1000>;
++			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 808>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		vin4: video@e6ef4000 {
++			compatible = "renesas,vin-r8a7798";
++			reg = <0 0xe6ef4000 0 0x1000>;
++			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 807>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		vin5: video@e6ef5000 {
++			compatible = "renesas,vin-r8a7798";
++			reg = <0 0xe6ef5000 0 0x1000>;
++			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 806>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		vin6: video@e6ef6000 {
++			compatible = "renesas,vin-r8a7798";
++			reg = <0 0xe6ef6000 0 0x1000>;
++			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 805>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		vin7: video@e6ef7000 {
++			compatible = "renesas,vin-r8a7798";
++			reg = <0 0xe6ef7000 0 0x1000>;
++			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 804>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		vin8: video@e6ef8000 {
++			compatible = "renesas,vin-r8a7798";
++			reg = <0 0xe6ef8000 0 0x1000>;
++			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 628>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		vin9: video@e6ef9000 {
++			compatible = "renesas,vin-r8a7798";
++			reg = <0 0xe6ef9000 0 0x1000>;
++			interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 625>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		vin10: video@e6efa000 {
++			compatible = "renesas,vin-r8a7798";
++			reg = <0 0xe6efa000 0 0x1000>;
++			interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 808>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		vin11: video@e6efb000 {
++			compatible = "renesas,vin-r8a7798";
++			reg = <0 0xe6efb000 0 0x1000>;
++			interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 618>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		vin12: video@e6efc000 {
++			compatible = "renesas,vin-r8a7798";
++			reg = <0 0xe6efc000 0 0x1000>;
++			interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 612>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		vin13: video@e6efd000 {
++			compatible = "renesas,vin-r8a7798";
++			reg = <0 0xe6efd000 0 0x1000>;
++			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 608>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		vin14: video@e6efe000 {
++			compatible = "renesas,vin-r8a7798";
++			reg = <0 0xe6efe000 0 0x1000>;
++			interrupts = <GIC_SPI 000 IRQ_TYPE_LEVEL_HIGH>; /* FIXME no info in datasheet */
++			clocks = <&cpg CPG_MOD 605>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		vin15: video@e6eff000 {
++			compatible = "renesas,vin-r8a7798";
++			reg = <0 0xe6eff000 0 0x1000>;
++			interrupts = <GIC_SPI 000 IRQ_TYPE_LEVEL_HIGH>; /* FIXME no info in datasheet */
++			clocks = <&cpg CPG_MOD 604>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			status = "disabled";
++		};
++
++		sdhi2: sd@ee140000 {
++			compatible = "renesas,sdhi-r8a7798";
++			reg = <0 0xee140000 0 0x2000>;
++			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 314>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			renesas,clk-rate = <200000000>;
++			status = "disabled";
++		};
++
++		qos@e67e0000 {
++			compatible = "renesas,qos";
++		};
++
++		vspd0: vsp@fea20000 {
++			compatible = "renesas,vsp2";
++			reg = <0 0xfea20000 0 0x4000>;
++
++			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 623>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++
++			renesas,fcp = <&fcpvd0>;
++		};
++
++		fcpvd0: fcp@fea27000 {
++			compatible = "renesas,r8a7798-fcpv", "renesas,fcpv";
++			reg = <0 0xfea27000 0 0x200>;
++			clocks = <&cpg CPG_MOD 603>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++		};
++
++		du: display@feb00000 {
++			compatible = "renesas,du-r8a7798";
++			reg = <0 0xfeb00000 0 0x80000>,
++			      <0 0xfeb90000 0 0x14>;
++			reg-names = "du", "lvds.0";
++			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 724>,
++				 <&cpg CPG_MOD 727>,
++				 <&dclkin_p0>;
++			clock-names = "du.0", "lvds.0", "dclkin.0";
++			status = "disabled";
++
++			vsps = <&vspd0>;
++
++			interlaced = <1>;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@0 {
++					reg = <0>;
++					du_out_lvds0: endpoint {
++					};
++				};
++			};
++		};
++
++		tsc1: thermal@0xe6198000 {
++			compatible = "renesas,thermal-r8a7798";
++			reg = <0 0xe6198000 0 0x5c>;
++			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 522>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			#thermal-sensor-cells = <0>;
++			status = "okay";
++		};
++
++		tsc2: thermal@0xe61a0000 {
++			compatible = "renesas,thermal-r8a7798";
++			reg = <0 0xe61a0000 0 0x5c>;
++			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 522>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++			#thermal-sensor-cells = <0>;
++			status = "okay";
++		};
++
++		thermal-zones {
++			emergency {
++				polling-delay = <1000>;
++				on-temperature = <110000>;
++				off-temperature = <95000>;
++				target_cpus = <&a53_1>,
++					      <&a53_2>,
++					      <&a53_3>;
++				status = "disabled";
++			};
++
++			sensor_thermal1: sensor-thermal1 {
++				polling-delay-passive = <250>;
++				polling-delay = <0>;
++				sustainable-power = <0>; /* TBD; HWM 87.4 */
++
++				thermal-sensors = <&tsc1>;
++
++				trips {
++					sensor1_crit: sensor1-crit {
++						temperature = <120000>;
++						hysteresis = <2000>;
++						type = "critical";
++					};
++				};
++			};
++
++			sensor_thermal2: sensor-thermal2 {
++				polling-delay-passive = <250>;
++				polling-delay = <0>;
++				sustainable-power = <0>; /* TBD; HWM 87.4 */
++
++				thermal-sensors = <&tsc2>;
++
++				trips {
++					sensor2_crit: sensor2-crit {
++						temperature = <120000>;
++						hysteresis = <2000>;
++						type = "critical";
++					};
++				};
++			};
++		};
++
++		mfis: mfis@e6260000 {
++			compatible = "renesas,mfis-r8a7798", "renesas,mfis";
++			reg = <0 0xe6260000 0 0x0200>;
++			clocks = <&cpg CPG_MOD 213>;
++			clock-names = "mfis";
++			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "eicr0";
++			status = "okay";
++		};
++
++		mfis_lock: mfis-lock@e62600c0 {
++			compatible =    "renesas,mfis-lock-r8a7798",
++					"renesas,mfis-lock";
++			reg = <0 0xe62600c0 0 0x0020>;
++			status = "okay";
++		};
++
++		imp_distributer: impdes0 {
++			compatible = "renesas,impx5+-distributer";
++			reg = <0 0xffa00000 0 0x4000>;
++			interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 830>;
++			power-domains = <&sysc R8A7798_PD_A3IR>;
++			interrupt-controller;
++			#interrupt-cells = <1>;
++		};
++
++		imp0 {
++			compatible = "renesas,impx4-legacy";
++			reg = <0 0xff900000 0 0x20000>;
++			interrupt-parent = <&imp_distributer>;
++			interrupts = <0>;
++			clocks = <&cpg CPG_MOD 827>;
++			power-domains = <&sysc R8A7798_PD_A2IR0>;
++		};
++
++		imp1 {
++			compatible = "renesas,impx4-legacy";
++			reg = <0 0xff920000 0 0x20000>;
++			interrupt-parent = <&imp_distributer>;
++			interrupts = <1>;
++			clocks = <&cpg CPG_MOD 826>;
++			power-domains = <&sysc R8A7798_PD_A2IR1>;
++		};
++
++		imp2 {
++			compatible = "renesas,impx4-legacy";
++			reg = <0 0xff940000 0 0x20000>;
++			interrupt-parent = <&imp_distributer>;
++			interrupts = <2>;
++			clocks = <&cpg CPG_MOD 825>;
++			power-domains = <&sysc R8A7798_PD_A2IR2>;
++		};
++
++		imp3 {
++			compatible = "renesas,impx4-legacy";
++			reg = <0 0xff960000 0 0x20000>;
++			interrupt-parent = <&imp_distributer>;
++			interrupts = <3>;
++			clocks = <&cpg CPG_MOD 824>;
++			power-domains = <&sysc R8A7798_PD_A2IR3>;
++		};
++
++		imp4 {
++			compatible = "renesas,impx4-legacy";
++			reg = <0 0xffa80000 0 0x20000>;
++			interrupt-parent = <&imp_distributer>;
++			interrupts = <4>;
++			clocks = <&cpg CPG_MOD 521>;
++			power-domains = <&sysc R8A7798_PD_A2IR4>;
++		};
++
++		imp5 {
++			compatible = "renesas,impslc0";
++			reg = <0 0xff9c0000 0 0x20000>;
++			interrupt-parent = <&imp_distributer>;
++			interrupts = <5>;
++			clocks = <&cpg CPG_MOD 500>;
++			power-domains = <&sysc R8A7798_PD_A2IR4>;
++		};
++
++		impsc0 {
++			compatible = "renesas,impx4-shader";
++			reg = <0 0xff980000 0 0x10000>;
++			interrupt-parent = <&imp_distributer>;
++			interrupts = <6>;
++			clocks = <&cpg CPG_MOD 829>;
++			power-domains = <&sysc R8A7798_PD_A2SC0>;
++		};
++
++		impsc1 {
++			compatible = "renesas,impx4-shader";
++			reg = <0 0xff990000 0 0x10000>;
++			interrupt-parent = <&imp_distributer>;
++			interrupts = <7>;
++			clocks = <&cpg CPG_MOD 828>;
++			power-domains = <&sysc R8A7798_PD_A2SC1>;
++		};
++
++		impsc2 {
++			compatible = "renesas,impx4-shader";
++			reg = <0 0xff9a0000 0 0x10000>;
++			interrupt-parent = <&imp_distributer>;
++			interrupts = <8>;
++			clocks = <&cpg CPG_MOD 531>;
++			power-domains = <&sysc R8A7798_PD_A2SC2>;
++		};
++
++		impsc3 {
++			compatible = "renesas,impx4-shader";
++			reg = <0 0xff9b0000 0 0x10000>;
++			interrupt-parent = <&imp_distributer>;
++			interrupts = <9>;
++			clocks = <&cpg CPG_MOD 529>;
++			power-domains = <&sysc R8A7798_PD_A2SC3>;
++		};
++
++		impsc4 {
++			compatible = "renesas,impx4-shader";
++			reg = <0 0xffa40000 0 0x10000>;
++			interrupt-parent = <&imp_distributer>;
++			interrupts = <10>;
++			clocks = <&cpg CPG_MOD 528>;
++			power-domains = <&sysc R8A7798_PD_A2SC4>;
++		};
++
++		impdm0 {
++			compatible = "renesas,impx5-dmac";
++			reg = <0 0xffa10000 0 0x1000>;
++			interrupt-parent = <&imp_distributer>;
++			interrupts = <11>;
++			clocks = <&cpg CPG_MOD 527>;
++			power-domains = <&sysc R8A7798_PD_A2PD0>;
++		};
++
++		impdm1 {
++			compatible = "renesas,impx5-dmac";
++			reg = <0 0xffa14000 0 0x1000>;
++			interrupt-parent = <&imp_distributer>;
++			interrupts = <13>;
++			clocks = <&cpg CPG_MOD 526>;
++			power-domains = <&sysc R8A7798_PD_A2PD1>;
++		};
++
++		imppsc0 {
++			compatible = "renesas,impx5+-psc";
++			reg = <0 0xffa20000 0 0x4000>;
++			interrupt-parent = <&imp_distributer>;
++			interrupts = <15>;
++			clocks = <&cpg CPG_MOD 525>;
++			power-domains = <&sysc R8A7798_PD_A2PD0>;
++		};
++
++		imppsc1 {
++			compatible = "renesas,impx5+-psc";
++			reg = <0 0xffa24000 0 0x4000>;
++			interrupt-parent = <&imp_distributer>;
++			interrupts = <16>;
++			clocks = <&cpg CPG_MOD 524>;
++			power-domains = <&sysc R8A7798_PD_A2PD1>;
++		};
++
++		impcnn0 {
++			compatible = "renesas,impx5+-cnn";
++			reg = <0 0xff9e0000 0 0x10000>;
++			interrupt-parent = <&imp_distributer>;
++			interrupts = <17>;
++			clocks = <&cpg CPG_MOD 831>;
++			power-domains = <&sysc R8A7798_PD_A2CN>;
++		};
++
++		impc0 {
++			compatible = "renesas,impx4-memory";
++			reg = <0 0xed000000 0 0x100000>;
++			clocks = <&cpg CPG_MOD 830>;
++			power-domains = <&sysc R8A7798_PD_A3IR>;
++		};
++
++		imrlx4_ch0: imr-lx4@fe860000 {
++			compatible = "renesas,imr-lx4";
++			reg = <0 0xfe860000 0 0x2000>;
++			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 823>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++		};
++
++		imrlx4_ch1: imr-lx4@fe870000 {
++			compatible = "renesas,imr-lx4";
++			reg = <0 0xfe870000 0 0x2000>;
++			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 822>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++		};
++
++		imrlx4_ch2: imr-lx4@fe880000 {
++			compatible = "renesas,imr-lx4";
++			reg = <0 0xfe880000 0 0x2000>;
++			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 821>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++		};
++
++		imrlx4_ch3: imr-lx4@fe890000 {
++			compatible = "renesas,imr-lx4";
++			reg = <0 0xfe890000 0 0x2000>;
++			interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&cpg CPG_MOD 820>;
++			power-domains = <&sysc R8A7798_PD_ALWAYS_ON>;
++		};
++	};
++};
+diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
+index b52e907..4e6d24d 100644
+--- a/drivers/clk/renesas/Kconfig
++++ b/drivers/clk/renesas/Kconfig
+@@ -6,6 +6,7 @@ config CLK_RENESAS_CPG_MSSR
+ 	default y if ARCH_R8A7796
+ 	default y if ARCH_R8A77965
+ 	default y if ARCH_R8A7797
++	default y if ARCH_R8A7798
+ 
+ config CLK_RENESAS_CPG_MSTP
+ 	bool
+diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
+index c2ef11e..9f659d5 100644
+--- a/drivers/clk/renesas/Makefile
++++ b/drivers/clk/renesas/Makefile
+@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_R8A7795)		+= r8a7795-cpg-mssr.o rcar-gen3-cpg.o
+ obj-$(CONFIG_ARCH_R8A7796)		+= r8a7796-cpg-mssr.o rcar-gen3-cpg.o
+ obj-$(CONFIG_ARCH_R8A77965)		+= r8a77965-cpg-mssr.o rcar-gen3-cpg.o
+ obj-$(CONFIG_ARCH_R8A7797)		+= r8a7797-cpg-mssr.o rcar-gen3-cpg.o
++obj-$(CONFIG_ARCH_R8A7798)		+= r8a7798-cpg-mssr.o rcar-gen3-cpg.o
+ obj-$(CONFIG_ARCH_SH73A0)		+= clk-sh73a0.o clk-div6.o
+ 
+ obj-$(CONFIG_CLK_RENESAS_CPG_MSSR)	+= renesas-cpg-mssr.o clk-div6.o
+diff --git a/drivers/clk/renesas/r8a7798-cpg-mssr.c b/drivers/clk/renesas/r8a7798-cpg-mssr.c
+new file mode 100644
+index 0000000..c7b68ac
+--- /dev/null
++++ b/drivers/clk/renesas/r8a7798-cpg-mssr.c
+@@ -0,0 +1,284 @@
++/*
++ * r8a7798 Clock Pulse Generator / Module Standby and Software Reset
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ */
++
++#include <linux/device.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/soc/renesas/rcar-rst.h>
++#include <linux/sys_soc.h>
++
++#include <dt-bindings/clock/r8a7798-cpg-mssr.h>
++
++#include "renesas-cpg-mssr.h"
++#include "rcar-gen3-cpg.h"
++
++enum clk_ids {
++	/* Core Clock Outputs exported to DT */
++	LAST_DT_CORE_CLK = R8A7798_CLK_OSC,
++
++	/* External Input Clocks */
++	CLK_EXTAL,
++	CLK_EXTALR,
++
++	/* Internal Core Clocks */
++	CLK_MAIN,
++	CLK_PLL1,
++	CLK_PLL2,
++	CLK_PLL3,
++	CLK_PLL1_DIV2,
++	CLK_PLL1_DIV4,
++	CLK_S0,
++	CLK_S1,
++	CLK_S2,
++	CLK_S3,
++	CLK_SDSRC,
++	CLK_RINT,
++
++	/* Module Clocks */
++	MOD_CLK_BASE
++};
++
++static const struct cpg_core_clk r8a7798_core_clks[] __initconst = {
++	/* External Clock Inputs */
++	DEF_INPUT("extal",  CLK_EXTAL),
++	DEF_INPUT("extalr", CLK_EXTALR),
++
++	/* Internal Core Clocks */
++	DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
++	DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
++	DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
++	DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
++
++	DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
++	DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
++	DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
++	DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
++	DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
++	DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
++	DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
++
++	/* Core Clock Outputs */
++	DEF_BASE("z2",          R8A7798_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2),
++	DEF_FIXED("ztr",        R8A7798_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
++	DEF_FIXED("ztrd2",      R8A7798_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
++	DEF_FIXED("zt",         R8A7798_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
++	DEF_FIXED("zx",         R8A7798_CLK_ZX,    CLK_PLL1_DIV2,  3, 1),
++	DEF_FIXED("s0d1",       R8A7798_CLK_S0D1,  CLK_S0,         1, 1),
++	DEF_FIXED("s0d2",       R8A7798_CLK_S0D2,  CLK_S0,         2, 1),
++	DEF_FIXED("s0d3",       R8A7798_CLK_S0D3,  CLK_S0,         3, 1),
++	DEF_FIXED("s0d4",       R8A7798_CLK_S0D4,  CLK_S0,         4, 1),
++	DEF_FIXED("s0d6",       R8A7798_CLK_S0D6,  CLK_S0,         6, 1),
++	DEF_FIXED("s0d12",      R8A7798_CLK_S0D12, CLK_S0,        12, 1),
++	DEF_FIXED("s0d24",      R8A7798_CLK_S0D24, CLK_S0,        24, 1),
++	DEF_FIXED("s1d1",       R8A7798_CLK_S1D1,  CLK_S1,         1, 1),
++	DEF_FIXED("s1d2",       R8A7798_CLK_S1D2,  CLK_S1,         2, 1),
++	DEF_FIXED("s1d4",       R8A7798_CLK_S1D4,  CLK_S1,         4, 1),
++	DEF_FIXED("s2d1",       R8A7798_CLK_S2D1,  CLK_S2,         1, 1),
++	DEF_FIXED("s2d2",       R8A7798_CLK_S2D2,  CLK_S2,         2, 1),
++	DEF_FIXED("s2d4",       R8A7798_CLK_S2D4,  CLK_S2,         4, 1),
++	DEF_FIXED("s3d1",       R8A7798_CLK_S3D1,  CLK_S3,         1, 1),
++	DEF_FIXED("s3d2",       R8A7798_CLK_S3D2,  CLK_S3,         2, 1),
++	DEF_FIXED("s3d4",       R8A7798_CLK_S3D4,  CLK_S3,         4, 1),
++
++	DEF_GEN3_SD("sd0",      R8A7798_CLK_SD0,   CLK_SDSRC,    0x0074), /* OK? */
++
++	DEF_FIXED("cl",         R8A7798_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
++	DEF_FIXED("cp",         R8A7798_CLK_CP,    CLK_EXTAL,      2, 1),
++
++	DEF_DIV6P1("canfd",     R8A7798_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
++	DEF_DIV6P1("csi0",      R8A7798_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
++	DEF_DIV6P1("mso",       R8A7798_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
++
++	DEF_BASE("osc",         R8A7798_CLK_OSC, CLK_TYPE_GEN3_OSC,  CLK_EXTAL),
++	DEF_BASE("r_int",       CLK_RINT,        CLK_TYPE_GEN3_RINT, CLK_EXTAL),
++
++	DEF_BASE("r",           R8A7798_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
++};
++
++static const struct mssr_mod_clk r8a7798_mod_clks[] __initconst = {
++	/*... skip crc, umf, disp, rt-sram, cle, smd_ */
++	DEF_MOD("tmu4",			 121,	R8A7798_CLK_S0D6),
++	DEF_MOD("tmu3",			 122,	R8A7798_CLK_S0D6),
++	DEF_MOD("tmu2",			 123,	R8A7798_CLK_S0D6),
++	DEF_MOD("tmu1",			 124,	R8A7798_CLK_S0D6),
++	DEF_MOD("tmu0",			 125,	R8A7798_CLK_CP),
++	DEF_MOD("ivcp1e",		 127,	R8A7798_CLK_S3D1), /* FIXME parent clk? */
++	DEF_MOD("scif4",		 203,	R8A7798_CLK_S3D4),
++	DEF_MOD("scif3",		 204,	R8A7798_CLK_S3D4),
++	DEF_MOD("scif1",		 206,	R8A7798_CLK_S3D4),
++	DEF_MOD("scif0",		 207,	R8A7798_CLK_S3D4),
++	DEF_MOD("msiof3",		 208,	R8A7798_CLK_MSO),
++	DEF_MOD("msiof2",		 209,	R8A7798_CLK_MSO),
++	DEF_MOD("msiof1",		 210,	R8A7798_CLK_MSO),
++	DEF_MOD("msiof0",		 211,	R8A7798_CLK_MSO),
++	DEF_MOD("mfis",			 213,	R8A7798_CLK_S2D2), /* FIXME parent clk? */
++	DEF_MOD("sys-dmac2",		 217,	R8A7798_CLK_S0D3), /* OK? */
++	DEF_MOD("sys-dmac1",		 218,	R8A7798_CLK_S0D3), /* OK? */
++	DEF_MOD("cmt3",			 300,	R8A7798_CLK_R),
++	DEF_MOD("cmt2",			 301,	R8A7798_CLK_R),
++	DEF_MOD("cmt1",			 302,	R8A7798_CLK_R),
++	DEF_MOD("cmt0",			 303,	R8A7798_CLK_R),
++	DEF_MOD("tpu",			 304,	R8A7798_CLK_S3D4),
++	DEF_MOD("sdif",			 314,	R8A7798_CLK_SD0), /* OK */
++	DEF_MOD("pciec",		 319,	R8A7798_CLK_S3D1),
++	DEF_MOD("rwdt0",		 402,	R8A7798_CLK_R),
++	DEF_MOD("intc-ex",		 407,	R8A7798_CLK_CP), /* OK */
++	DEF_MOD("intc-ap",		 408,	R8A7798_CLK_S0D3),
++	DEF_MOD("simp",			 500,	R8A7798_CLK_S1D1),
++	DEF_MOD("hscif3",		 517,	R8A7798_CLK_S3D1),
++	DEF_MOD("hscif2",		 518,	R8A7798_CLK_S3D1),
++	DEF_MOD("hscif1",		 519,	R8A7798_CLK_S3D1),
++	DEF_MOD("hscif0",		 520,	R8A7798_CLK_S3D1),
++	DEF_MOD("imp4",			 521,	R8A7798_CLK_S1D1), /* OK? */
++	DEF_MOD("thermal",		 522,	R8A7798_CLK_CP),
++	DEF_MOD("pwm",			 523,	R8A7798_CLK_S0D12),
++	DEF_MOD("imppsc1",		 524,	R8A7798_CLK_S1D1),
++	DEF_MOD("imppsc0",		 525,	R8A7798_CLK_S1D1),
++	DEF_MOD("impdma1",		 526,	R8A7798_CLK_S1D1), /* OK? */
++	DEF_MOD("impdma0",		 527,	R8A7798_CLK_S1D1), /* OK? */
++	DEF_MOD("imp-ocv4",		 528,	R8A7798_CLK_S1D1), /* OK? */
++	DEF_MOD("imp-ocv3",		 529,	R8A7798_CLK_S1D1), /* OK? */
++	DEF_MOD("imp-ocv2",		 531,	R8A7798_CLK_S1D1), /* OK? */
++	DEF_MOD("fcpvd0",		 603,	R8A7798_CLK_S3D1),
++	DEF_MOD("vin15",		 604,	R8A7798_CLK_S2D1), /* FIXME parent clk? */
++	DEF_MOD("vin14",		 605,	R8A7798_CLK_S2D1), /* FIXME parent clk? */
++	DEF_MOD("vin13",		 608,	R8A7798_CLK_S2D1), /* FIXME parent clk? */
++	DEF_MOD("vin12",		 612,	R8A7798_CLK_S2D1), /* FIXME parent clk? */
++	DEF_MOD("vin11",		 618,	R8A7798_CLK_S2D1), /* FIXME parent clk? */
++	DEF_MOD("vspd0",		 623,	R8A7798_CLK_S3D1),
++	DEF_MOD("vin10",		 625,	R8A7798_CLK_S2D1), /* FIXME parent clk? */
++	DEF_MOD("vin9",			 627,	R8A7798_CLK_S2D1), /* FIXME parent clk? */
++	DEF_MOD("vin8",			 628,	R8A7798_CLK_S2D1), /* FIXME parent clk? */
++#if 0 /* FIXME what is this? duplicated with 822,823 */
++	DEF_MOD("imr1",			 706,	R8A7798_CLK_S2D1), /* FIXME parent clk? */
++	DEF_MOD("imr0",			 707,	R8A7798_CLK_S2D1), /* FIXME parent clk? */
++#endif
++	DEF_MOD("csi41",		 715,	R8A7798_CLK_CSI0),
++	DEF_MOD("csi40",		 716,	R8A7798_CLK_CSI0),
++	DEF_MOD("du0",			 724,	R8A7798_CLK_S2D1),
++	DEF_MOD("lvds",			 727,	R8A7798_CLK_S2D1),
++	DEF_MOD("vin7",			 804,	R8A7798_CLK_S0D2), /* FIXME parent clk? */
++	DEF_MOD("vin6",			 805,	R8A7798_CLK_S0D2), /* FIXME parent clk? */
++	DEF_MOD("vin5",			 806,	R8A7798_CLK_S0D2), /* FIXME parent clk? */
++	DEF_MOD("vin4",			 807,	R8A7798_CLK_S0D2), /* FIXME parent clk? */
++	DEF_MOD("vin3",			 808,	R8A7798_CLK_S0D2), /* FIXME parent clk? */
++	DEF_MOD("vin2",			 809,	R8A7798_CLK_S0D2), /* FIXME parent clk? */
++	DEF_MOD("vin1",			 810,	R8A7798_CLK_S0D2), /* FIXME parent clk? */
++	DEF_MOD("vin0",			 811,	R8A7798_CLK_S0D2), /* FIXME parent clk? */
++	DEF_MOD("etheravb",		 812,	R8A7798_CLK_S3D2), /* OK */
++	DEF_MOD("gether",		 813,	R8A7798_CLK_S3D2), /* OK */
++	DEF_MOD("isp1",			 814,	R8A7798_CLK_S3D1), /* FIXME parent clk? */
++	DEF_MOD("isp0",			 817,	R8A7798_CLK_S3D1), /* FIXME parent clk? */
++	DEF_MOD("imr3",			 820,	R8A7798_CLK_S2D1), /* FIXME check clk? */
++	DEF_MOD("imr2",			 821,	R8A7798_CLK_S2D1), /* FIXME check clk? */
++	DEF_MOD("imr1",			 822,	R8A7798_CLK_S2D1), /* FIXME check clk? */
++	DEF_MOD("imr0",			 823,	R8A7798_CLK_S2D1), /* FIXME check clk? */
++	DEF_MOD("imp3",			 824,	R8A7798_CLK_S1D1), /* OK? figure 8.1e CPG block diag */
++	DEF_MOD("imp2",			 825,	R8A7798_CLK_S1D1), /* OK? */
++	DEF_MOD("imp1",			 826,	R8A7798_CLK_S1D1), /* OK? */
++	DEF_MOD("imp0",			 827,	R8A7798_CLK_S1D1), /* OK? */
++	DEF_MOD("imp-ocv1",		 828,	R8A7798_CLK_S1D1), /* OK? */
++	DEF_MOD("imp-ocv0",		 829,	R8A7798_CLK_S1D1), /* OK? */
++	DEF_MOD("impram",		 830,	R8A7798_CLK_S1D1), /* OK? */
++	DEF_MOD("impcnn",		 831,	R8A7798_CLK_S1D1), /* OK? */
++	DEF_MOD("gpio5",		 907,	R8A7798_CLK_CP),
++	DEF_MOD("gpio4",		 908,	R8A7798_CLK_CP),
++	DEF_MOD("gpio3",		 909,	R8A7798_CLK_CP),
++	DEF_MOD("gpio2",		 910,	R8A7798_CLK_CP),
++	DEF_MOD("gpio1",		 911,	R8A7798_CLK_CP),
++	DEF_MOD("gpio0",		 912,	R8A7798_CLK_CP),
++	DEF_MOD("can-fd",		 914,	R8A7798_CLK_S3D2),
++	/* FIXME missing MSSR for i2c5; should it be 919 as in H3/M3? */
++	/* DEF_MOD("i2c4",			 919,	R8A7798_CLK_S3D2), */
++	DEF_MOD("i2c4",			 927,	R8A7798_CLK_S0D6),
++	DEF_MOD("i2c3",			 928,	R8A7798_CLK_S0D6),
++	DEF_MOD("i2c2",			 929,	R8A7798_CLK_S3D2),
++	DEF_MOD("i2c1",			 930,	R8A7798_CLK_S3D2),
++	DEF_MOD("i2c0",			 931,	R8A7798_CLK_S3D2),
++};
++
++static const unsigned int r8a7798_crit_mod_clks[] __initconst = {
++	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
++};
++
++
++/*
++ * CPG Clock Data
++ */
++
++/*
++ *   MD		EXTAL		PLL2	PLL1	PLL3
++ * 14 13 19	(MHz)
++ *-------------------------------------------------
++ * 0  0  0 	16.66 x 1	x240	x192	x192
++ * 0  0  1 	16.66 x 1	x240	x192	x192
++ * 0  1  0 	20    x 1	x200	x160	x160
++ * 0  1  1 	20    x 1	x200	x160	x160
++ * 1  0  0 	27    x 1	x148	x118	x118
++ * 1  0  1 	27    x 1	x148	x118	x118
++ * 1  1  0 	33.33 / 2	x240	x192	x192
++ * 1  1  1 	33.33 / 2	x240	x192	x192
++ */
++#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
++					 (((md) & BIT(13)) >> 12) | \
++					 (((md) & BIT(19)) >> 19))
++
++static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = {
++	/* EXTAL div	PLL1 mult	PLL3 mult */
++	{ 1,		192,		192,},
++	{ 1,		192,		192,},
++	{ 1,		160,		160,},
++	{ 1,		160,		160,},
++	{ 1,		118,		118,},
++	{ 1,		118,		118,},
++	{ 2,		192,		192,},
++	{ 2,		192,		192,},
++};
++
++static int __init r8a7798_cpg_mssr_init(struct device *dev)
++{
++	const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
++	u32 cpg_mode;
++	int error;
++
++	error = rcar_rst_read_mode_pins(&cpg_mode);
++	if (error)
++		return error;
++
++	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
++	if (!cpg_pll_config->extal_div) {
++		dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
++		return -EINVAL;
++	}
++
++	return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
++}
++
++const struct cpg_mssr_info r8a7798_cpg_mssr_info __initconst = {
++	/* Core Clocks */
++	.core_clks = r8a7798_core_clks,
++	.num_core_clks = ARRAY_SIZE(r8a7798_core_clks),
++	.last_dt_core_clk = LAST_DT_CORE_CLK,
++	.num_total_core_clks = MOD_CLK_BASE,
++
++	/* Module Clocks */
++	.mod_clks = r8a7798_mod_clks,
++	.num_mod_clks = ARRAY_SIZE(r8a7798_mod_clks),
++	.num_hw_mod_clks = 12 * 32,
++
++	/* Critical Module Clocks */
++	.crit_mod_clks = r8a7798_crit_mod_clks,
++	.num_crit_mod_clks = ARRAY_SIZE(r8a7798_crit_mod_clks),
++
++	/* Callbacks */
++	.init = r8a7798_cpg_mssr_init,
++	.cpg_clk_register = rcar_gen3_cpg_clk_register,
++};
+diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
+index b145f14..aa4f5ce 100644
+--- a/drivers/clk/renesas/rcar-gen3-cpg.c
++++ b/drivers/clk/renesas/rcar-gen3-cpg.c
+@@ -33,6 +34,11 @@
+ 	{ /* sentinel */ }
+ };
+ 
++static const struct soc_device_attribute r8a7798[] = {
++	{ .soc_id = "r8a7798" },
++	{ }
++};
++
+ #define CPG_PLL0CR		0x00d8
+ #define CPG_PLL2CR		0x002c
+ #define CPG_PLL4CR		0x01f4
+@@ -916,6 +922,11 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
+ 		if (cpg_quirks & RCLK_CKSEL_RESEVED)
+ 			break;
+ 
++		if (soc_device_match(r8a7798) && (cpg_mode ^ BIT(29))) {
++			parent = clks[cpg_clk_extalr];
++			break;
++		}
++
+ 		/* Select parent clock of RCLK by MD28 */
+ 		if (cpg_mode & BIT(28))
+ 			parent = clks[cpg_clk_extalr];
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
+index bd901a6..759facd 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.c
++++ b/drivers/clk/renesas/renesas-cpg-mssr.c
+@@ -600,6 +602,12 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
+ 		.data = &r8a7797_cpg_mssr_info,
+ 	},
+ #endif
++#ifdef CONFIG_ARCH_R8A7798
++	{
++		.compatible = "renesas,r8a7798-cpg-mssr",
++		.data = &r8a7798_cpg_mssr_info,
++	},
++#endif
+ 	{ /* sentinel */ }
+ };
+ 
+diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
+index ce3546a..d5aaf50 100644
+--- a/drivers/clk/renesas/renesas-cpg-mssr.h
++++ b/drivers/clk/renesas/renesas-cpg-mssr.h
+@@ -136,6 +138,7 @@ struct cpg_mssr_info {
+ extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;
+ extern const struct cpg_mssr_info r8a7797_cpg_mssr_info;
++extern const struct cpg_mssr_info r8a7798_cpg_mssr_info;
+ 
+ 
+     /*
+diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
+index 5a2ec23..2d7d41c 100644
+--- a/drivers/cpufreq/cpufreq-dt-platdev.c
++++ b/drivers/cpufreq/cpufreq-dt-platdev.c
+@@ -61,6 +61,7 @@
+ 	{ .compatible = "renesas,r8a7796", },
+ 	{ .compatible = "renesas,r8a77965", },
+ 	{ .compatible = "renesas,r8a7797", },
++	{ .compatible = "renesas,r8a7798", },
+ 	{ .compatible = "renesas,sh73a0", },
+ 
+ 	{ .compatible = "rockchip,rk2928", },
+diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
+index fd15649..d4549a0 100644
+--- a/drivers/gpio/gpio-rcar.c
++++ b/drivers/gpio/gpio-rcar.c
+@@ -371,6 +372,10 @@ struct gpio_rcar_info {
+ 		/* Gen3 GPIO is identical to Gen2. */
+ 		.data = &gpio_rcar_info_gen2,
+ 	}, {
++		.compatible = "renesas,gpio-r8a7798",
++		/* Gen3 GPIO is identical to Gen2. */
++		.data = &gpio_rcar_info_gen2,
++	}, {
+ 		.compatible = "renesas,gpio-rcar",
+ 		.data = &gpio_rcar_info_gen1,
+ 	}, {
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+index f74f264..8700e13 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+@@ -360,6 +361,7 @@
+ 	{ .compatible = "renesas,du-r8a7796", .data = &rcar_du_r8a7796_info },
+ 	{ .compatible = "renesas,du-r8a77965", .data = &rcar_du_r8a77965_info },
+ 	{ .compatible = "renesas,du-r8a7797", .data = &rcar_du_r8a7797_info },
++	{ .compatible = "renesas,du-r8a7798", .data = &rcar_du_r8a7797_info },
+ 	{ }
+ };
+ 
+diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
+index 3916b63..f236103 100644
+--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
+@@ -35,8 +36,9 @@
+ #include "rcar_du_group.h"
+ #include "rcar_du_regs.h"
+ 
+-static const struct soc_device_attribute r8a7797[] = {
++static const struct soc_device_attribute r8a7797_8[] = {
+ 	{ .soc_id = "r8a7797" },
++	{ .soc_id = "r8a7798" },
+ 	{ }
+ };
+ 
+@@ -161,7 +163,7 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp)
+ 
+ 	/* Apply planes to CRTCs association. */
+ 	mutex_lock(&rgrp->lock);
+-	if (!soc_device_match(r8a7797))
++	if (!soc_device_match(r8a7797_8))
+ 		rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) |
+ 				    rgrp->dptsr_planes);
+ 
+diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
+index 149c107..0ad583a 100644
+--- a/drivers/i2c/busses/i2c-rcar.c
++++ b/drivers/i2c/busses/i2c-rcar.c
+@@ -808,6 +808,7 @@ static u32 rcar_i2c_func(struct i2c_adapter *adap)
+ 	{ .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },
+ 	{ .compatible = "renesas,i2c-r8a77965", .data = (void *)I2C_RCAR_GEN3 },
+ 	{ .compatible = "renesas,i2c-r8a7797", .data = (void *)I2C_RCAR_GEN3 },
++	{ .compatible = "renesas,i2c-r8a7798", .data = (void *)I2C_RCAR_GEN3 },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
+diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
+index 1ae9174..add0cd1 100644
+--- a/drivers/iommu/ipmmu-vmsa.c
++++ b/drivers/iommu/ipmmu-vmsa.c
+@@ -1280,6 +1281,9 @@ static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu)
+ 		.compatible = "renesas,ipmmu-r8a7797",
+ 		.data = &ipmmu_features_rcar_gen3,
+ 	}, {
++		.compatible = "renesas,ipmmu-r8a7798",
++		.data = &ipmmu_features_rcar_gen3,
++	}, {
+ 		/* Terminator */
+ 	},
+ };
+diff --git a/drivers/media/platform/soc_camera/Kconfig b/drivers/media/platform/soc_camera/Kconfig
+index 5539c5d..fc7d829 100644
+--- a/drivers/media/platform/soc_camera/Kconfig
++++ b/drivers/media/platform/soc_camera/Kconfig
+@@ -39,7 +39,7 @@ config VIDEO_RCAR_VIN_LEGACY_DEBUG
+ config VIDEO_RCAR_CSI2_LEGACY
+ 	tristate "R-Car MIPI CSI-2 Interface driver"
+ 	depends on VIDEO_DEV && SOC_CAMERA && HAVE_CLK
+-	depends on ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A7797 || COMPILE_TEST
++	depends on ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A7797 || ARCH_R8A7798 || COMPILE_TEST
+ 	---help---
+ 	  This is a v4l2 driver for the R-Car CSI-2 Interface
+ 
+diff --git a/drivers/media/platform/soc_camera/rcar_csi2.c b/drivers/media/platform/soc_camera/rcar_csi2.c
+index 2ef27e8..98f271f 100644
+--- a/drivers/media/platform/soc_camera/rcar_csi2.c
++++ b/drivers/media/platform/soc_camera/rcar_csi2.c
+@@ -163,6 +163,11 @@
+ #define RCAR_CSI2_INTSTATE_ERRSYNCESC		(1 << 1)
+ #define RCAR_CSI2_INTSTATE_ERRCONTROL		(1 << 0)
+ 
++static const struct soc_device_attribute r8a7798[] = {
++	{ .soc_id = "r8a7798" },
++	{ }
++};
++
+ static const struct soc_device_attribute r8a7797[] = {
+ 	{ .soc_id = "r8a7797" },
+ 	{ }
+@@ -410,7 +415,7 @@ static int rcar_csi2_set_phy_freq(struct rcar_csi2 *priv)
+ 		iowrite32((hs_freq_range_v3m[bps_per_lane] << 16) |
+ 				RCAR_CSI2_PHTW_DWEN | RCAR_CSI2_PHTW_CWEN | 0x44,
+ 				priv->base + RCAR_CSI2_PHTW);
+-	else if (soc_device_match(r8a7795))
++	else if (soc_device_match(r8a7795) || soc_device_match(r8a7798))
+ 		iowrite32(hs_freq_range_h3[bps_per_lane] << 16,
+ 				priv->base + RCAR_CSI2_PHYPLL);
+ 	else
+@@ -497,8 +502,8 @@ static int rcar_csi2_hwinit(struct rcar_csi2 *priv)
+ 			return -EINVAL;
+ 		}
+ 
+-		if (soc_device_match(r8a7795)) {
+-			/* Set PHY Test Interface Write Register in R-Car H3(ES2.0) */
++		if (soc_device_match(r8a7795) || soc_device_match(r8a7798)) {
++			/* Set PHY Test Interface Write Register in R-Car H3(ES2.0)/V3H */
+ 			iowrite32(0x01cc01e2, priv->base + RCAR_CSI2_PHTW);
+ 			iowrite32(0x010101e3, priv->base + RCAR_CSI2_PHTW);
+ 			iowrite32(0x010101e4, priv->base + RCAR_CSI2_PHTW);
+@@ -515,7 +520,7 @@ static int rcar_csi2_hwinit(struct rcar_csi2 *priv)
+ 		/* Set CSI0CLK Frequency Configuration Preset Register
+ 		 * in R-Car H3(ES2.0)
+ 		 */
+-		if (soc_device_match(r8a7795))
++		if (soc_device_match(r8a7795) || soc_device_match(r8a7798))
+ 			iowrite32(CSI0CLKFREQRANGE(32), priv->base + RCAR_CSI2_CSI0CLKFCPR);
+ 
+ 		/* Enable lanes */
+@@ -609,6 +614,7 @@ static int rcar_csi2_s_power(struct v4l2_subdev *sd, int on)
+ 
+ #ifdef CONFIG_OF
+ static const struct of_device_id rcar_csi2_of_table[] = {
++	{ .compatible = "renesas,r8a7798-csi2", .data = (void *)RCAR_GEN3 },
+ 	{ .compatible = "renesas,r8a7797-csi2", .data = (void *)RCAR_GEN3 },
+ 	{ .compatible = "renesas,r8a7796-csi2", .data = (void *)RCAR_GEN3 },
+ 	{ .compatible = "renesas,r8a7795-csi2", .data = (void *)RCAR_GEN3 },
+@@ -618,6 +624,7 @@ static int rcar_csi2_s_power(struct v4l2_subdev *sd, int on)
+ #endif
+ 
+ static struct platform_device_id rcar_csi2_id_table[] = {
++	{ "r8a7798-csi2",  RCAR_GEN3 },
+ 	{ "r8a7797-csi2",  RCAR_GEN3 },
+ 	{ "r8a7796-csi2",  RCAR_GEN3 },
+ 	{ "r8a7795-csi2",  RCAR_GEN3 },
+diff --git a/drivers/media/platform/soc_camera/rcar_vin.c b/drivers/media/platform/soc_camera/rcar_vin.c
+index 7bd8a77..1e098ef 100644
+--- a/drivers/media/platform/soc_camera/rcar_vin.c
++++ b/drivers/media/platform/soc_camera/rcar_vin.c
+@@ -162,7 +162,7 @@
+ #define VNCSI_IFMD_REG	0x20	/* Video n CSI2 Interface Mode Register */
+ 
+ #define VNCSI_IFMD_DES1		(1 << 26) /* CSI20 */
+-#define VNCSI_IFMD_DES0		(1 << 25) /* H3:CSI40/41, M3:CSI40, V3M:CSI40 */
++#define VNCSI_IFMD_DES0		(1 << 25) /* H3,V3H:CSI40/41, M3:CSI40, V3M:CSI40 */
+ 
+ #define VNCSI_IFMD_CSI_CHSEL(n)	(n << 0)
+ #define VNCSI_IFMD_SEL_NUMBER	5
+@@ -197,6 +197,7 @@
+ 
+ enum chip_id {
+ 	RCAR_GEN3,
++	RCAR_V3H,
+ 	RCAR_V3M,
+ 	RCAR_M3,
+ 	RCAR_H3,
+@@ -416,6 +417,69 @@ struct vin_gen3_ifmd {
+ 	},
+ };
+ 
++static const struct vin_gen3_ifmd vin_v3h_vc_ifmd[] = {
++	{ 0x0000,
++		{
++			{RCAR_CSI40, RCAR_VIRTUAL_CH0},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI40, RCAR_VIRTUAL_CH1},
++			{RCAR_CSI41, RCAR_VIRTUAL_CH0},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI41, RCAR_VIRTUAL_CH1},
++		}
++	},
++	{ 0x0001,
++		{
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI40, RCAR_VIRTUAL_CH1},
++			{RCAR_CSI40, RCAR_VIRTUAL_CH0},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI41, RCAR_VIRTUAL_CH1},
++			{RCAR_CSI41, RCAR_VIRTUAL_CH0},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++		}
++	},
++	{ 0x0002,
++		{
++			{RCAR_CSI40, RCAR_VIRTUAL_CH1},
++			{RCAR_CSI40, RCAR_VIRTUAL_CH0},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI41, RCAR_VIRTUAL_CH1},
++			{RCAR_CSI41, RCAR_VIRTUAL_CH0},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++		}
++	},
++	{ 0x0003,
++		{
++			{RCAR_CSI40, RCAR_VIRTUAL_CH0},
++			{RCAR_CSI40, RCAR_VIRTUAL_CH1},
++			{RCAR_CSI40, RCAR_VIRTUAL_CH2},
++			{RCAR_CSI40, RCAR_VIRTUAL_CH3},
++			{RCAR_CSI41, RCAR_VIRTUAL_CH0},
++			{RCAR_CSI41, RCAR_VIRTUAL_CH1},
++			{RCAR_CSI41, RCAR_VIRTUAL_CH2},
++			{RCAR_CSI41, RCAR_VIRTUAL_CH3},
++		}
++	},
++	{ 0x0004,
++		{
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++			{RCAR_CSI_CH_NONE, RCAR_VIN_CH_NONE},
++		}
++	},
++};
++
+ enum csi2_fmt {
+ 	RCAR_CSI_FMT_NONE = -1,
+ 	RCAR_CSI_RGB888,
+@@ -911,7 +975,7 @@ static int rcar_vin_videobuf_setup(struct vb2_queue *vq,
+ 	struct rcar_vin_cam *cam = icd->host_priv;
+ 
+ 	if (priv->chip == RCAR_H3 || priv->chip == RCAR_M3 ||
+-		priv->chip == RCAR_V3M) {
++	    priv->chip == RCAR_V3M || priv->chip == RCAR_V3H) {
+ 		if ((priv->ratio_h > 0x10000) || (priv->ratio_v > 0x10000)) {
+ 			dev_err(icd->parent, "Scaling rate parameter error\n");
+ 			return -EINVAL;
+@@ -1020,7 +1084,7 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv)
+ 	switch (icd->current_fmt->host_fmt->fourcc) {
+ 	case V4L2_PIX_FMT_NV12:
+ 		if (priv->chip == RCAR_H3 || priv->chip == RCAR_M3 ||
+-			priv->chip == RCAR_V3M) {
++		    priv->chip == RCAR_V3M || priv->chip == RCAR_V3H) {
+ 			iowrite32(ALIGN((cam->out_width * cam->out_height),
+ 					 0x80), priv->base + VNUVAOF_REG);
+ 			dmr = VNDMR_DTMD_YCSEP_YCBCR420;
+@@ -1056,7 +1120,7 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv)
+ 		break;
+ 	case V4L2_PIX_FMT_XBGR32:
+ 		if (priv->chip != RCAR_H3 && priv->chip != RCAR_M3 &&
+-			priv->chip != RCAR_V3M &&
++		    priv->chip != RCAR_V3M && priv->chip != RCAR_V3H &&
+ 		    priv->chip != RCAR_GEN2 && priv->chip != RCAR_H1 &&
+ 		    priv->chip != RCAR_E1)
+ 			goto e_format;
+@@ -1065,7 +1129,7 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv)
+ 		break;
+ 	case V4L2_PIX_FMT_ABGR32:
+ 		if (priv->chip != RCAR_H3 && priv->chip != RCAR_M3 &&
+-			priv->chip != RCAR_V3M)
++		    priv->chip != RCAR_V3M && priv->chip != RCAR_V3H)
+ 			goto e_format;
+ 
+ 		dmr = VNDMR_EXRGB | VNDMR_DTMD_ARGB;
+@@ -1086,7 +1150,7 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv)
+ 		vnmc |= VNMC_BPS;
+ 
+ 	if (priv->chip == RCAR_H3 || priv->chip == RCAR_M3 ||
+-		priv->chip == RCAR_V3M) {
++	    priv->chip == RCAR_V3M || priv->chip == RCAR_V3H) {
+ 		if (priv->pdata_flags & RCAR_VIN_CSI2)
+ 			vnmc &= ~VNMC_DPINE;
+ 		else
+@@ -1462,7 +1526,7 @@ static int rcar_vin_add_device(struct soc_camera_device *icd)
+ 	pm_runtime_get_sync(ici->v4l2_dev.dev);
+ 
+ 	if (priv->chip == RCAR_H3 || priv->chip == RCAR_M3 ||
+-		priv->chip == RCAR_V3M) {
++	    priv->chip == RCAR_V3M || priv->chip == RCAR_V3H) {
+ 		struct v4l2_subdev *csi2_sd = find_csi2(priv);
+ 		struct v4l2_subdev *deser_sd = find_deser(priv);
+ 		int ret = 0;
+@@ -1725,7 +1789,7 @@ static int rcar_vin_set_rect(struct soc_camera_device *icd)
+ 	}
+ 
+ 	if (priv->chip == RCAR_H3 || priv->chip == RCAR_M3 ||
+-		priv->chip == RCAR_V3M) {
++	    priv->chip == RCAR_V3M || priv->chip == RCAR_V3H) {
+ 		if ((icd->current_fmt->host_fmt->fourcc != V4L2_PIX_FMT_NV12) &&
+ 		    (icd->current_fmt->host_fmt->fourcc != V4L2_PIX_FMT_SBGGR8) &&
+ 		    (icd->current_fmt->host_fmt->fourcc != V4L2_PIX_FMT_SBGGR12)
+@@ -1883,7 +1947,7 @@ static int rcar_vin_set_bus_param(struct soc_camera_device *icd)
+ 		return ret;
+ 
+ 	if (priv->chip == RCAR_H3 || priv->chip == RCAR_M3 ||
+-		priv->chip == RCAR_V3M) {
++	    priv->chip == RCAR_V3M || priv->chip == RCAR_V3H) {
+ 		if (cfg.type == V4L2_MBUS_CSI2)
+ 			vnmc &= ~VNMC_DPINE;
+ 		else
+@@ -1891,7 +1955,7 @@ static int rcar_vin_set_bus_param(struct soc_camera_device *icd)
+ 	}
+ 
+ 	if (priv->chip == RCAR_H3 || priv->chip == RCAR_M3 ||
+-		priv->chip == RCAR_V3M)
++	    priv->chip == RCAR_V3M || priv->chip == RCAR_V3H)
+ 		val = VNDMR2_FTEV;
+ 	else
+ 		val = VNDMR2_FTEV | VNDMR2_VLV(1);
+@@ -2489,7 +2553,7 @@ static int rcar_vin_try_fmt(struct soc_camera_device *icd,
+ 		return ret;
+ 
+ 	if (priv->chip == RCAR_H3 || priv->chip == RCAR_M3 ||
+-		priv->chip == RCAR_V3M) {
++	    priv->chip == RCAR_V3M || priv->chip == RCAR_V3H) {
+ 		/* Adjust max scaling size for Gen3 */
+ 		if (pix->width > 4096)
+ 			pix->width = priv->max_width;
+@@ -2668,6 +2732,7 @@ static int rcar_vin_get_edid(struct soc_camera_device *icd,
+ 
+ #ifdef CONFIG_OF
+ static const struct of_device_id rcar_vin_of_table[] = {
++	{ .compatible = "renesas,vin-r8a7798", .data = (void *)RCAR_V3H },
+ 	{ .compatible = "renesas,vin-r8a7797", .data = (void *)RCAR_V3M },
+ 	{ .compatible = "renesas,vin-r8a7796", .data = (void *)RCAR_M3 },
+ 	{ .compatible = "renesas,vin-r8a7795", .data = (void *)RCAR_H3 },
+@@ -2989,7 +3054,7 @@ static int rcar_vin_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	if (priv->chip == RCAR_H3 || priv->chip == RCAR_M3 ||
+-		priv->chip == RCAR_V3M) {
++	    priv->chip == RCAR_V3M || priv->chip == RCAR_V3H) {
+ 		priv->max_width = 4096;
+ 		priv->max_height = 4096;
+ 	} else {
+@@ -2998,7 +3063,8 @@ static int rcar_vin_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	if ((priv->chip == RCAR_H3 || priv->chip == RCAR_M3 ||
+-	    priv->chip == RCAR_V3M) && !of_property_read_string(np, "csi,select", &str)) {
++	    priv->chip == RCAR_V3M || priv->chip == RCAR_V3H) &&
++	    !of_property_read_string(np, "csi,select", &str)) {
+ 		u32 ifmd = 0;
+ 		bool match_flag = false;
+ 		const struct vin_gen3_ifmd *gen3_ifmd_table = NULL;
+@@ -3073,6 +3139,8 @@ static int rcar_vin_probe(struct platform_device *pdev)
+ 			gen3_ifmd_table = vin_m3_vc_ifmd;
+ 		else if (priv->chip == RCAR_V3M)
+ 			gen3_ifmd_table = vin_v3_vc_ifmd;
++		else if (priv->chip == RCAR_V3H)
++			gen3_ifmd_table = vin_v3h_vc_ifmd;
+ 
+ 		for (i = 0; i < num; i++) {
+ 			if ((gen3_ifmd_table[i].v_sel[priv->index].csi2_ch
+@@ -3236,6 +3304,9 @@ static int rcar_vin_resume(struct device *dev)
+ 	} else if (priv->chip == RCAR_V3M) {
+ 		ifmd = VNCSI_IFMD_DES1;
+ 		gen3_ifmd_table = vin_v3_vc_ifmd;
++	} else if (priv->chip == RCAR_V3H) {
++		ifmd = VNCSI_IFMD_DES0;
++		gen3_ifmd_table = vin_v3h_vc_ifmd;
+ 	}
+ 
+ 	for (i = 0; i < num; i++) {
+diff --git a/drivers/media/platform/vsp1/vsp1_lif.c b/drivers/media/platform/vsp1/vsp1_lif.c
+index e79f9e6..948e88c 100644
+--- a/drivers/media/platform/vsp1/vsp1_lif.c
++++ b/drivers/media/platform/vsp1/vsp1_lif.c
+@@ -24,8 +25,9 @@
+ #define LIF_MIN_SIZE				2U
+ #define LIF_MAX_SIZE				8190U
+ 
+-static const struct soc_device_attribute r8a7797[] = {
++static const struct soc_device_attribute r8a7797_8[] = {
+ 	{ .soc_id = "r8a7797" },
++	{ .soc_id = "r8a7798" },
+ 	{ }
+ };
+ 
+@@ -151,7 +153,7 @@ static void lif_configure(struct vsp1_entity *entity,
+ 	format = vsp1_entity_get_pad_format(&lif->entity, lif->entity.config,
+ 					    LIF_PAD_SOURCE);
+ 
+-	if (vsp1_gen3_vspdl_check(vsp1) || soc_device_match(r8a7797))
++	if (vsp1_gen3_vspdl_check(vsp1) || soc_device_match(r8a7797_8))
+ 		obth = 1500;
+ 	else
+ 		obth = 3000;
+@@ -165,7 +167,7 @@ static void lif_configure(struct vsp1_entity *entity,
+ 			(format->code == 0 ? VI6_LIF_CTRL_CFMT : 0) |
+ 			VI6_LIF_CTRL_REQSEL | VI6_LIF_CTRL_LIF_EN);
+ 
+-	if (soc_device_match(r8a7797))
++	if (soc_device_match(r8a7797_8))
+ 		vsp1_lif_write(lif, dl, VI6_LIF_LBA, VI6_LIF_LBA_LBA0 |
+ 						     VI6_LIF_LBA_LBA1);
+ }
+diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c
+index 040f474..bee1116 100644
+--- a/drivers/mmc/host/sh_mobile_sdhi.c
++++ b/drivers/mmc/host/sh_mobile_sdhi.c
+@@ -141,6 +142,7 @@ struct sh_mobile_sdhi_of_data {
+ 	{ .compatible = "renesas,sdhi-r8a77965",
+ 					.data = &of_rcar_gen3_compatible, },
+ 	{ .compatible = "renesas,sdhi-r8a7797", .data = &of_rcar_gen3_compatible, },
++	{ .compatible = "renesas,sdhi-r8a7798", .data = &of_rcar_gen3_compatible, },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match);
+diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
+index 73fa286..9943197 100644
+--- a/drivers/net/ethernet/renesas/ravb_main.c
++++ b/drivers/net/ethernet/renesas/ravb_main.c
+@@ -1921,6 +1922,7 @@ static int ravb_mdio_release(struct ravb_private *priv)
+ 	{ .compatible = "renesas,etheravb-r8a7796", .data = (void *)RCAR_GEN3 },
+ 	{ .compatible = "renesas,etheravb-r8a77965", .data = (void *)RCAR_GEN3 },
+ 	{ .compatible = "renesas,etheravb-r8a7797", .data = (void *)RCAR_GEN3 },
++	{ .compatible = "renesas,etheravb-r8a7798", .data = (void *)RCAR_GEN3 },
+ 	{ .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
+ 	{ }
+ };
+diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
+index ccc29b3..2eb13c6 100644
+--- a/drivers/pci/host/pcie-rcar.c
++++ b/drivers/pci/host/pcie-rcar.c
+@@ -30,6 +31,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/slab.h>
++#include <linux/sys_soc.h>
+ 
+ #define PCIECAR			0x000010
+ #define PCIECCTLR		0x000018
+@@ -41,6 +43,8 @@
+ #define PCIEINTXR		0x000400
+ #define PCIEMSITXR		0x000840
+ 
++#define GEN3_PCIEPHYSR		0x07f0
++
+ /* Transfer control */
+ #define PCIETCTLR		0x02000
+ #define  DL_DOWN		(1 << 3)
+@@ -118,6 +122,9 @@
+ #define GEN2_PCIEPHYDATA	0x784
+ #define GEN2_PCIEPHYCTRL	0x78c
+ 
++/* R-Car Gen3 R8A7798 */
++#define R8A7798_PCIEPHYCTL	0x4000
++
+ #define INT_PCI_MSI_NR	32
+ 
+ #define RCONF(x)	(PCICONF(0)+(x))
+@@ -132,6 +139,11 @@
+ #define RCAR_PCI_MAX_RESOURCES 4
+ #define MAX_NR_INBOUND_MAPS 6
+ 
++static const struct soc_device_attribute r8a7798[] = {
++	{ .soc_id = "r8a7798" },
++	{ }
++};
++
+ struct rcar_msi {
+ 	DECLARE_BITMAP(used, INT_PCI_MSI_NR);
+ 	struct irq_domain *domain;
+@@ -151,6 +163,7 @@ static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
+ struct rcar_pcie {
+ 	struct device		*dev;
+ 	void __iomem		*base;
++	void __iomem		*phy_base;
+ 	struct list_head	resources;
+ 	int			root_bus_nr;
+ 	struct clk		*clk;
+@@ -160,6 +173,18 @@ struct rcar_pcie {
+ 
+ static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie);
+ 
++static void rcar_pci_phy_write_reg(struct rcar_pcie *pcie, unsigned long val,
++			       unsigned long reg)
++{
++	writel(val, pcie->phy_base + reg);
++}
++
++static unsigned long rcar_pci_phy_read_reg(struct rcar_pcie *pcie,
++				       unsigned long reg)
++{
++	return readl(pcie->phy_base + reg);
++}
++
+ static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
+ 			       unsigned long reg)
+ {
+@@ -672,6 +697,22 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
+ 	return 0;
+ }
+ 
++static int rcar_pcie_hw_init_r8a7798(struct rcar_pcie *pcie)
++{
++	unsigned int timeout = 10;
++
++	rcar_pci_phy_write_reg(pcie, 0, R8A7798_PCIEPHYCTL);
++
++	while (timeout--) {
++		if (rcar_pci_read_reg(pcie, GEN3_PCIEPHYSR))
++			return rcar_pcie_hw_init(pcie);
++
++		msleep(5);
++	}
++
++	return -ETIMEDOUT;
++}
++
+ static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
+ {
+ 	unsigned int timeout = 10;
+@@ -998,6 +1039,16 @@ static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
+ 	if (IS_ERR(pcie->base))
+ 		return PTR_ERR(pcie->base);
+ 
++	if (soc_device_match(r8a7798)) {
++		err = of_address_to_resource(dev->of_node, 1, &res);
++		if (err)
++			return err;
++
++		pcie->phy_base = devm_ioremap_resource(dev, &res);
++		if (IS_ERR(pcie->phy_base))
++			return PTR_ERR(pcie->base);
++	}
++
+ 	pcie->bus_clk = devm_clk_get(dev, "pcie_bus");
+ 	if (IS_ERR(pcie->bus_clk)) {
+ 		dev_err(dev, "cannot get pcie bus clock\n");
+@@ -1153,6 +1204,7 @@ static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
+ 	{ .compatible = "renesas,pcie-r8a7795", .data = rcar_pcie_hw_init },
+ 	{ .compatible = "renesas,pcie-r8a7796", .data = rcar_pcie_hw_init },
+ 	{ .compatible = "renesas,pcie-r8a77965", .data = rcar_pcie_hw_init },
++	{ .compatible = "renesas,pcie-r8a7798", .data = rcar_pcie_hw_init_r8a7798 },
+ 	{},
+ };
+ 
+@@ -1347,7 +1399,13 @@ static SIMPLE_DEV_PM_OPS(rcar_pcie_pm_ops,
+ 	},
+ 	.probe = rcar_pcie_probe,
+ };
+-builtin_platform_driver(rcar_pcie_driver);
++/* builtin_platform_driver(rcar_pcie_driver); */
++
++static int __init rcar_pcie_init(void)
++{
++	return platform_driver_register(&rcar_pcie_driver);
++}
++late_initcall(rcar_pcie_init);
+ 
+ static int rcar_pcie_pci_notifier(struct notifier_block *nb,
+ 			    unsigned long action, void *data)
+diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
+index 4aaf0be..6ae17af 100644
+--- a/drivers/pinctrl/sh-pfc/Kconfig
++++ b/drivers/pinctrl/sh-pfc/Kconfig
+@@ -89,6 +89,11 @@ config PINCTRL_PFC_R8A7797
+ 	depends on ARCH_R8A7797
+ 	select PINCTRL_SH_PFC
+ 
++config PINCTRL_PFC_R8A7798
++	def_bool y
++	depends on ARCH_R8A7798
++	select PINCTRL_SH_PFC
++
+ config PINCTRL_PFC_SH7203
+ 	def_bool y
+ 	depends on CPU_SUBTYPE_SH7203
+diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
+index e263c14..5f2f619 100644
+--- a/drivers/pinctrl/sh-pfc/Makefile
++++ b/drivers/pinctrl/sh-pfc/Makefile
+@@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7795)	+= pfc-r8a7795-es1.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A7796)	+= pfc-r8a7796.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A77965)	+= pfc-r8a77965.o
+ obj-$(CONFIG_PINCTRL_PFC_R8A7797)	+= pfc-r8a7797.o
++obj-$(CONFIG_PINCTRL_PFC_R8A7798)	+= pfc-r8a7798.o
+ obj-$(CONFIG_PINCTRL_PFC_SH7203)	+= pfc-sh7203.o
+ obj-$(CONFIG_PINCTRL_PFC_SH7264)	+= pfc-sh7264.o
+ obj-$(CONFIG_PINCTRL_PFC_SH7269)	+= pfc-sh7269.o
+diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
+index 9aba933..a75293f 100644
+--- a/drivers/pinctrl/sh-pfc/core.c
++++ b/drivers/pinctrl/sh-pfc/core.c
+@@ -552,6 +553,12 @@ static int sh_pfc_init_ranges(struct sh_pfc *pfc)
+ 		.data = &r8a7797_pinmux_info,
+ 	},
+ #endif
++#ifdef CONFIG_PINCTRL_PFC_R8A7798
++	{
++		.compatible = "renesas,pfc-r8a7798",
++		.data = &r8a7798_pinmux_info,
++	},
++#endif
+ #ifdef CONFIG_PINCTRL_PFC_SH73A0
+ 	{
+ 		.compatible = "renesas,pfc-sh73a0",
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7798.c b/drivers/pinctrl/sh-pfc/pfc-r8a7798.c
+new file mode 100644
+index 0000000..740bf4e
+--- /dev/null
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7798.c
+@@ -0,0 +1,3151 @@
++/*
++ * R8A7798 processor support - PFC hardware block.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++ *
++ * R-Car Gen3 processor support - PFC hardware block.
++ *
++ * Copyright (C) 2015  Renesas Electronics Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ */
++
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/sys_soc.h>
++
++#include "core.h"
++#include "sh_pfc.h"
++
++/* mmc in gpsr3, so do POC; check if any other reg needs it */
++#define CPU_ALL_PORT(fn, sfx)						\
++	PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
++	PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
++	PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
++	PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH |	\
++				   SH_PFC_PIN_CFG_IO_VOLTAGE),	\
++	PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
++	PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
++/*
++ * F_() : just information
++ * FM() : macro for FN_xxx / xxx_MARK
++ */
++
++/* GPSR0 */
++#define GPSR0_21	F_(DU_EXODDF_DU_ODDF_DISP_CDE,	IP2_23_20)
++#define GPSR0_20	F_(DU_EXVSYNC_DU_VSYNC,		IP2_19_16)
++#define GPSR0_19	F_(DU_EXHSYNC_DU_HSYNC,		IP2_15_12)
++#define GPSR0_18	F_(DU_DOTCLKOUT,		IP2_11_8)
++#define GPSR0_17	F_(DU_DB7,			IP2_7_4)
++#define GPSR0_16	F_(DU_DB6,			IP2_3_0)
++#define GPSR0_15	F_(DU_DB5,			IP1_31_28)
++#define GPSR0_14	F_(DU_DB4,			IP1_27_24)
++#define GPSR0_13	F_(DU_DB3,			IP1_23_20)
++#define GPSR0_12	F_(DU_DB2,			IP1_19_16)
++#define GPSR0_11	F_(DU_DG7,			IP1_15_12)
++#define GPSR0_10	F_(DU_DG6,			IP1_11_8)
++#define GPSR0_9		F_(DU_DG5,			IP1_7_4)
++#define GPSR0_8		F_(DU_DG4,			IP1_3_0)
++#define GPSR0_7		F_(DU_DG3,			IP0_31_28)
++#define GPSR0_6		F_(DU_DG2,			IP0_27_24)
++#define GPSR0_5		F_(DU_DR7,			IP0_23_20)
++#define GPSR0_4		F_(DU_DR6,			IP0_19_16)
++#define GPSR0_3		F_(DU_DR5,			IP0_15_12)
++#define GPSR0_2		F_(DU_DR4,			IP0_11_8)
++#define GPSR0_1		F_(DU_DR3,			IP0_7_4)
++#define GPSR0_0		F_(DU_DR2,			IP0_3_0)
++
++/* GPSR1 */
++#define GPSR1_27	F_(DIGRF_CLKOUT,	IP8_31_28)
++#define GPSR1_26	F_(DIGRF_CLKIN,		IP8_27_24)
++#define GPSR1_25	F_(CANFD_CLK_A,		IP8_23_20) /* OK? */
++#define GPSR1_24	F_(CANFD1_RX,		IP8_19_16)
++#define GPSR1_23	F_(CANFD1_TX,		IP8_15_12)
++#define GPSR1_22	F_(CANFD0_RX_A,		IP8_11_8)
++#define GPSR1_21	F_(CANFD0_TX_A,		IP8_7_4)
++#define GPSR1_20	F_(AVB_AVTP_CAPTURE,	IP8_3_0)
++#define GPSR1_19	F_(AVB_AVTP_MATCH,	IP7_31_28)
++#define GPSR1_18	FM(AVB_LINK)
++#define GPSR1_17	FM(AVB_PHY_INT)
++#define GPSR1_16	FM(AVB_MAGIC)
++#define GPSR1_15	FM(AVB_MDC)
++#define GPSR1_14	FM(AVB_MDIO)
++#define GPSR1_13	FM(AVB_TXCREFCLK)
++#define GPSR1_12	FM(AVB_TD3)
++#define GPSR1_11	FM(AVB_TD2)
++#define GPSR1_10	FM(AVB_TD1)
++#define GPSR1_9		FM(AVB_TD0)
++#define GPSR1_8		FM(AVB_TXC)
++#define GPSR1_7		FM(AVB_TX_CTL)
++#define GPSR1_6		FM(AVB_RD3)
++#define GPSR1_5		FM(AVB_RD2)
++#define GPSR1_4		FM(AVB_RD1)
++#define GPSR1_3		FM(AVB_RD0)
++#define GPSR1_2		FM(AVB_RXC)
++#define GPSR1_1		FM(AVB_RX_CTL)
++#define GPSR1_0		F_(IRQ0,		IP2_27_24)
++
++/* GPSR2 */
++#define GPSR2_29	F_(FSO_TOE_N,  		IP10_19_16)
++#define GPSR2_28	F_(FSO_CFE_1_N,		IP10_15_12)
++#define GPSR2_27	F_(FSO_CFE_0_N,		IP10_11_8)
++#define GPSR2_26	F_(SDA3,		IP10_7_4)
++#define GPSR2_25	F_(SCL3,		IP10_3_0)
++#define GPSR2_24	F_(MSIOF0_SS2,		IP9_31_28)
++#define GPSR2_23	F_(MSIOF0_SS1,		IP9_27_24)
++#define GPSR2_22	F_(MSIOF0_SYNC,		IP9_23_20)
++#define GPSR2_21	F_(MSIOF0_SCK,		IP9_19_16)
++#define GPSR2_20	F_(MSIOF0_TXD,		IP9_15_12)
++#define GPSR2_19	F_(MSIOF0_RXD,		IP9_11_8)
++#define GPSR2_18	F_(IRQ5,		IP9_7_4)
++#define GPSR2_17	F_(IRQ4,		IP9_3_0)
++#define GPSR2_16	F_(VI0_FIELD,		IP4_31_28)
++#define GPSR2_15	F_(VI0_DATA11,		IP4_27_24)
++#define GPSR2_14	F_(VI0_DATA10,		IP4_23_20)
++#define GPSR2_13	F_(VI0_DATA9,		IP4_19_16)
++#define GPSR2_12	F_(VI0_DATA8,		IP4_15_12)
++#define GPSR2_11	F_(VI0_DATA7,		IP4_11_8)
++#define GPSR2_10	F_(VI0_DATA6,		IP4_7_4)
++#define GPSR2_9		F_(VI0_DATA5,		IP4_3_0)
++#define GPSR2_8		F_(VI0_DATA4,		IP3_31_28)
++#define GPSR2_7		F_(VI0_DATA3,		IP3_27_24)
++#define GPSR2_6		F_(VI0_DATA2,		IP3_23_20)
++#define GPSR2_5		F_(VI0_DATA1,		IP3_19_16)
++#define GPSR2_4		F_(VI0_DATA0,		IP3_15_12)
++#define GPSR2_3		F_(VI0_VSYNC_N,		IP3_11_8)
++#define GPSR2_2		F_(VI0_HSYNC_N,		IP3_7_4)
++#define GPSR2_1		F_(VI0_CLKENB,		IP3_3_0)
++#define GPSR2_0		F_(VI0_CLK,		IP2_31_28)
++
++/* GPSR3 */
++#define GPSR3_16	F_(VI1_FIELD,		IP7_3_0)
++#define GPSR3_15	F_(VI1_DATA11,		IP6_31_28)
++#define GPSR3_14	F_(VI1_DATA10,		IP6_27_24)
++#define GPSR3_13	F_(VI1_DATA9,		IP6_23_20)
++#define GPSR3_12	F_(VI1_DATA8,		IP6_19_16)
++#define GPSR3_11	F_(VI1_DATA7,		IP6_15_12)
++#define GPSR3_10	F_(VI1_DATA6,		IP6_11_8)
++#define GPSR3_9		F_(VI1_DATA5,		IP6_7_4)
++#define GPSR3_8		F_(VI1_DATA4,		IP6_3_0)
++#define GPSR3_7		F_(VI1_DATA3,		IP5_31_28)
++#define GPSR3_6		F_(VI1_DATA2,		IP5_27_24)
++#define GPSR3_5		F_(VI1_DATA1,		IP5_23_20)
++#define GPSR3_4		F_(VI1_DATA0,		IP5_19_16)
++#define GPSR3_3		F_(VI1_VSYNC_N,		IP5_15_12)
++#define GPSR3_2		F_(VI1_HSYNC_N,		IP5_11_8)
++#define GPSR3_1		F_(VI1_CLKENB,		IP5_7_4)
++#define GPSR3_0		F_(VI1_CLK,		IP5_3_0)
++
++/* GPSR4 */
++#define GPSR4_24	FM(GETHER_LINK_A)
++#define GPSR4_23	FM(GETHER_PHY_INT_A)
++#define GPSR4_22	FM(GETHER_MAGIC)
++#define GPSR4_21	FM(GETHER_MDC_A)
++#define GPSR4_20	FM(GETHER_MDIO_A)
++#define GPSR4_19	FM(GETHER_TXCREFCLK_MEGA)
++#define GPSR4_18	FM(GETHER_TXCREFCLK)
++#define GPSR4_17	FM(GETHER_TD3)
++#define GPSR4_16	FM(GETHER_TD2)
++#define GPSR4_15	FM(GETHER_TD1)
++#define GPSR4_14	FM(GETHER_TD0)
++#define GPSR4_13	FM(GETHER_TXC)
++#define GPSR4_12	FM(GETHER_TX_CTL)
++#define GPSR4_11	FM(GETHER_RD3)
++#define GPSR4_10	FM(GETHER_RD2)
++#define GPSR4_9		FM(GETHER_RD1)
++#define GPSR4_8		FM(GETHER_RD0)
++#define GPSR4_7		FM(GETHER_RXC)
++#define GPSR4_6		FM(GETHER_RX_CTL)
++#define GPSR4_5		F_(SDA2,		IP7_27_24)
++#define GPSR4_4		F_(SCL2,		IP7_23_20)
++#define GPSR4_3		F_(SDA1,		IP7_19_16)
++#define GPSR4_2		F_(SCL1,		IP7_15_12)
++#define GPSR4_1		F_(SDA0,		IP7_11_8)
++#define GPSR4_0		F_(SCL0,		IP7_7_4)
++
++/* GPSR5 */
++#define GPSR5_14	FM(RPC_INT_N)
++#define GPSR5_13	FM(RPC_WP_N)
++#define GPSR5_12	FM(RPC_RESET_N)
++#define GPSR5_11	FM(QSPI1_SSL)
++#define GPSR5_10	FM(QSPI1_IO3)
++#define GPSR5_9		FM(QSPI1_IO2)
++#define GPSR5_8		FM(QSPI1_MISO_IO1)
++#define GPSR5_7		FM(QSPI1_MOSI_IO0)
++#define GPSR5_6		FM(QSPI1_SPCLK)
++#define GPSR5_5		FM(QSPI0_SSL)
++#define GPSR5_4		FM(QSPI0_IO3)
++#define GPSR5_3		FM(QSPI0_IO2)
++#define GPSR5_2		FM(QSPI0_MISO_IO1)
++#define GPSR5_1		FM(QSPI0_MOSI_IO0)
++#define GPSR5_0		FM(QSPI0_SPCLK)
++
++
++/* IPSRx */		/* 0 */				/* 1 */			/* 2 */				/* 3 */		/* 4 */			/* 5 */		/* 6 */		/* 7 */		/* 8 */		/* 9 */		/* A */		/* B */		/* C */		/* D */		/* E */		/* F */
++#define IP0_3_0		FM(DU_DR2)			FM(SCK4)		FM(GETHER_RMII_CRS_DV)		FM(A0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP0_7_4		FM(DU_DR3)			FM(RX4)			FM(GETHER_RMII_RX_ER)		FM(A1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP0_11_8	FM(DU_DR4)			FM(TX4)			FM(GETHER_RMII_RXD0)		FM(A2)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP0_15_12	FM(DU_DR5)			FM(CTS4_N)		FM(GETHER_RMII_RXD1)		FM(A3)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP0_19_16	FM(DU_DR6)			FM(RTS4_N_TANS)		FM(GETHER_RMII_TXD_EN)		FM(A4)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP0_23_20	FM(DU_DR7)			F_(0, 0)		FM(GETHER_RMII_TXD0)		FM(A5)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP0_27_24	FM(DU_DG2)			F_(0, 0)		FM(GETHER_RMII_TXD1)		FM(A6)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP0_31_28	FM(DU_DG3)			FM(CPG_CPCKOUT)		FM(GETHER_RMII_REFCLK)		FM(A7)		FM(PWMFSW0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP1_3_0		FM(DU_DG4)			FM(SCL5)		F_(0, 0)			FM(A8)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP1_7_4		FM(DU_DG5)			FM(SDA5)		FM(GETHER_MDC_B)		FM(A9)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP1_11_8	FM(DU_DG6)			FM(SCIF_CLK_A)		FM(GETHER_MDIO_B)		FM(A10)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP1_15_12	FM(DU_DG7)			FM(HRX0_A)		F_(0, 0)			FM(A11)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP1_19_16	FM(DU_DB2)			FM(HSCK0_A)		F_(0, 0)			FM(A12)		FM(IRQ1)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP1_23_20	FM(DU_DB3)			FM(HRTS0_N_A)		F_(0, 0)			FM(A13)		FM(IRQ2)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP1_27_24	FM(DU_DB4)			FM(HCTS0_N_A)		F_(0, 0)			FM(A14)		FM(IRQ3)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP1_31_28	FM(DU_DB5)			FM(HTX0_A)		FM(PWM0_A)			FM(A15)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP2_3_0		FM(DU_DB6)			FM(MSIOF3_RXD)		F_(0, 0)			FM(A16)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP2_7_4		FM(DU_DB7)			FM(MSIOF3_TXD)		F_(0, 0)			FM(A17)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP2_11_8	FM(DU_DOTCLKOUT)		FM(MSIOF3_SS1)		FM(GETHER_LINK_B)		FM(A18)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP2_15_12	FM(DU_EXHSYNC_DU_HSYNC)		FM(MSIOF3_SS2)		FM(GETHER_PHY_INT_B)		FM(A19)		FM(FXR_TXENA_N)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP2_19_16	FM(DU_EXVSYNC_DU_VSYNC)		FM(MSIOF3_SCK)		F_(0, 0)			F_(0, 0)	FM(FXR_TXENB_N)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP2_23_20	FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(MSIOF3_SYNC)		F_(0, 0)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP2_27_24	FM(IRQ0)			FM(CC5_OSCOUT)		F_(0, 0)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP2_31_28	FM(VI0_CLK)			FM(MSIOF2_SCK)		FM(SCK3)			F_(0, 0)	FM(HSCK3)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP3_3_0		FM(VI0_CLKENB)			FM(MSIOF2_RXD)		FM(RX3)				FM(RD_WR_N)	FM(HCTS3_N)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP3_7_4		FM(VI0_HSYNC_N)			FM(MSIOF2_TXD)		FM(TX3)				F_(0, 0)	FM(HRTS3_N)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP3_11_8	FM(VI0_VSYNC_N)			FM(MSIOF2_SYNC)		FM(CTS3_N)			F_(0, 0)	FM(HTX3)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP3_15_12	FM(VI0_DATA0)			FM(MSIOF2_SS1)		FM(RTS3_N_TANS)			F_(0, 0)	FM(HRX3)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP3_19_16	FM(VI0_DATA1)			FM(MSIOF2_SS2)		FM(SCK1)			F_(0, 0)	FM(SPEEDIN_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP3_23_20	FM(VI0_DATA2)			FM(AVB_AVTP_PPS)	F_(0, 0)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP3_27_24	FM(VI0_DATA3)			FM(HSCK1)		F_(0, 0)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP3_31_28	FM(VI0_DATA4)			FM(HRTS1_N)		FM(RX1_A)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP4_3_0		FM(VI0_DATA5)			FM(HCTS1_N)		FM(TX1_A)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP4_7_4		FM(VI0_DATA6)			FM(HTX1)		FM(CTS1_N)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP4_11_8	FM(VI0_DATA7)			FM(HRX1)		FM(RTS1_N_TANS)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP4_15_12	FM(VI0_DATA8)			FM(HSCK2)		F_(0, 0)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP4_19_16	FM(VI0_DATA9)			FM(HCTS2_N)		FM(PWM1_A)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP4_23_20	FM(VI0_DATA10)			FM(HRTS2_N)		FM(PWM2_A)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP4_27_24	FM(VI0_DATA11)			FM(HTX2)		FM(PWM3_A)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP4_31_28	FM(VI0_FIELD)			FM(HRX2)		FM(PWM4_A)			FM(CS1_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP5_3_0		FM(VI1_CLK)			FM(MSIOF1_RXD)		F_(0, 0)			FM(CS0_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP5_7_4		FM(VI1_CLKENB)			FM(MSIOF1_TXD)		F_(0, 0)			FM(D0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP5_11_8	FM(VI1_HSYNC_N)			FM(MSIOF1_SCK)		F_(0, 0)			FM(D1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP5_15_12	FM(VI1_VSYNC_N)			FM(MSIOF1_SYNC)		F_(0, 0)			FM(D2)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP5_19_16	FM(VI1_DATA0)			FM(MSIOF1_SS1)		F_(0, 0)			FM(D3)		FM(MMC_WP)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP5_23_20	FM(VI1_DATA1)			FM(MSIOF1_SS2)		F_(0, 0)			FM(D4)		FM(MMC_CD)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP5_27_24	FM(VI1_DATA2)			FM(CANFD0_TX_B)		F_(0, 0)			FM(D5)		FM(MMC_DS)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP5_31_28	FM(VI1_DATA3)			FM(CANFD0_RX_B)		F_(0, 0)			FM(D6)		FM(MMC_CMD)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP6_3_0		FM(VI1_DATA4)			FM(CANFD_CLK_B)		F_(0, 0)			FM(D7)		FM(MMC_D0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP6_7_4		FM(VI1_DATA5)			F_(0, 0)		F_(0, 0)			FM(D8)		FM(MMC_D1)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP6_11_8	FM(VI1_DATA6)			F_(0, 0)		F_(0, 0)			FM(D9)		FM(MMC_D2)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP6_15_12	FM(VI1_DATA7)			F_(0, 0)		F_(0, 0)			FM(D10)		FM(MMC_D3)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP6_19_16	FM(VI1_DATA8)			F_(0, 0)		F_(0, 0)			FM(D11)		FM(MMC_CLK)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP6_23_20	FM(VI1_DATA9)			FM(TCLK1_A)		F_(0, 0)			FM(D12)		FM(MMC_D4)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP6_27_24	FM(VI1_DATA10)			FM(TCLK2_A)		F_(0, 0)			FM(D13)		FM(MMC_D5)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP6_31_28	FM(VI1_DATA11)			FM(SCL4)		F_(0, 0)			FM(D14)		FM(MMC_D6)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP7_3_0		FM(VI1_FIELD)			FM(SDA4)		F_(0, 0)			FM(D15)		FM(MMC_D7)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP7_7_4		FM(SCL0)			F_(0, 0)		F_(0, 0)			FM(CLKOUT)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP7_11_8	FM(SDA0)			F_(0, 0)		F_(0, 0)			FM(BS_N)	FM(SCK0)		FM(HSCK0_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP7_15_12	FM(SCL1)			F_(0, 0)		FM(TPU0TO2)			FM(RD_N)	FM(CTS0_N)		FM(HCTS0_N_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP7_19_16	FM(SDA1)			F_(0, 0)		FM(TPU0TO3)			FM(WE0_N)	FM(RTS0_N_TANS)		FM(HRTS0_N_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP7_23_20	FM(SCL2)			F_(0, 0)		F_(0, 0)			FM(WE1_N)	FM(RX0)			FM(HRX0_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP7_27_24	FM(SDA2)			F_(0, 0)		F_(0, 0)			FM(EX_WAIT0)	FM(TX0)			FM(HTX0_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP7_31_28	FM(AVB_AVTP_MATCH)		FM(TPU0TO0)		F_(0, 0)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP8_3_0		FM(AVB_AVTP_CAPTURE)		FM(TPU0TO1)		F_(0, 0)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP8_7_4		FM(CANFD0_TX_A)			FM(FXR_TXDA)		FM(PWM0_B)			FM(DU_DISP)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP8_11_8	FM(CANFD0_RX_A)			FM(RXDA_EXTFXR)		FM(PWM1_B)			FM(DU_CDE)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP8_15_12	FM(CANFD1_TX)			FM(FXR_TXDB)		FM(PWM2_B)			FM(TCLK1_B)	FM(TX1_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP8_19_16	FM(CANFD1_RX)			FM(RXDB_EXTFXR)		FM(PWM3_B)			FM(TCLK2_B)	FM(RX1_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP8_23_20	FM(CANFD_CLK_A) 		FM(CLK_EXTFXR)		FM(PWM4_B)			FM(SPEEDIN_B)	FM(SCIF_CLK_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP8_27_24	FM(DIGRF_CLKIN)			FM(DIGRF_CLKEN_IN)	F_(0, 0)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP8_31_28	FM(DIGRF_CLKOUT)		FM(DIGRF_CLKEN_OUT)	F_(0, 0)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP9_3_0		FM(IRQ4)			F_(0, 0)		F_(0, 0)			FM(VI0_DATA12)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP9_7_4		FM(IRQ5)			F_(0, 0)		F_(0, 0)			FM(VI0_DATA13)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP9_11_8	FM(MSIOF0_RXD)			FM(DU_DR0)		F_(0, 0)			FM(VI0_DATA14)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP9_15_12	FM(MSIOF0_TXD)			FM(DU_DR1)		F_(0, 0)			FM(VI0_DATA15)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP9_19_16	FM(MSIOF0_SCK)			FM(DU_DG0)		F_(0, 0)			FM(VI0_DATA16)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP9_23_20	FM(MSIOF0_SYNC)			FM(DU_DG1)		F_(0, 0)			FM(VI0_DATA17)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP9_27_24	FM(MSIOF0_SS1)			FM(DU_DB0)		FM(TCLK3)			FM(VI0_DATA18)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP9_31_28	FM(MSIOF0_SS2)			FM(DU_DB1)		FM(TCLK4)			FM(VI0_DATA19)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP10_3_0	FM(SCL3)			F_(0, 0)		F_(0, 0)			FM(VI0_DATA20)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP10_7_4	FM(SDA3)			F_(0, 0)		F_(0, 0)			FM(VI0_DATA21)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP10_11_8	FM(FSO_CFE_0_N)			F_(0, 0)		F_(0, 0)			FM(VI0_DATA22)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP10_15_12	FM(FSO_CFE_1_N)			F_(0, 0)		F_(0, 0)			FM(VI0_DATA23)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP10_19_16	FM(FSO_TOE_N)			F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP10_23_20	F_(0, 0)			F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP10_27_24	F_(0, 0)			F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++#define IP10_31_28	F_(0, 0)			F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)
++
++#define PINMUX_GPSR	\
++\
++				GPSR2_29 \
++				GPSR2_28 \
++		GPSR1_27	GPSR2_27 \
++		GPSR1_26	GPSR2_26 \
++		GPSR1_25	GPSR2_25 \
++		GPSR1_24	GPSR2_24			GPSR4_24 \
++		GPSR1_23	GPSR2_23			GPSR4_23 \
++		GPSR1_22	GPSR2_22			GPSR4_22 \
++GPSR0_21	GPSR1_21	GPSR2_21			GPSR4_21 \
++GPSR0_20	GPSR1_20	GPSR2_20			GPSR4_20 \
++GPSR0_19	GPSR1_19	GPSR2_19			GPSR4_19 \
++GPSR0_18	GPSR1_18	GPSR2_18			GPSR4_18 \
++GPSR0_17	GPSR1_17	GPSR2_17			GPSR4_17 \
++GPSR0_16	GPSR1_16	GPSR2_16	GPSR3_16	GPSR4_16 \
++GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15	GPSR4_15 \
++GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14 \
++GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13 \
++GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12 \
++GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11 \
++GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10 \
++GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9 \
++GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8 \
++GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7 \
++GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6 \
++GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5 \
++GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4 \
++GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3 \
++GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2 \
++GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1 \
++GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0
++
++#define PINMUX_IPSR	\
++\
++FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
++FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
++FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
++FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
++FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
++FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
++FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
++FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
++\
++FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
++FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
++FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
++FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12	FM(IP7_15_12)	IP7_15_12 \
++FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
++FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
++FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
++FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
++\
++FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0 \
++FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4 \
++FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8 \
++FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12 \
++FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16 \
++FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20 \
++FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24 \
++FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28
++
++/*
++			Set Value = H'0					Set Value = H'1
++Register	Function		Pin			Function		Pin
++------------------------------------------------------------
++sel_canfd0	CANFD0_TX_A		CANFD0_TX_A		CANFD0_TX_B		VI1_DATA2
++		CANFD0_RX_A		CANFD0_RX_A		CANFD0_TX_B		VI1_DATA3
++		CANFD_CLK_A		CANFD_CLK_A		CANFD_CLK_B		VI1_DATA4
++sel_gether	GETHER_MDC_A		GETHER_MDC_A		GETHER_MDC_B		DU_DG5
++		GETHER_MDIO_A		GETHER_MDIO_A		GETHER_MDIO_B		DU_DG6
++		GETHER_LINK_A		GETHER_LINK_A		GETHER_LINK_B		DU_DOTCLKOUT
++		GETHER_PHY_INT_A	GETHER_PHY_INT_A	GETHER_PHY_INT_B	DU_EXHSYNC_DU_HSYNC
++sel_hscif0	HSCK0_A			DU_DB2			HSCK0_B			SDA0
++		HCTS0_N_A		DU_DB4			HCTS_N_B		SCL1
++		HRTS0_N_A		DU_DB3			HRTS_N_B		SDA1
++		HRX0_A			DU_DG7			HRX0_B			SCL2
++		HTX0_A			DU_DB5			HTX0_B			SDA2
++		SCIF_CLK_A		DU_DG6			SCIF_CLK_B		CANFD_CLK_A
++sel_pwm0	PWM0_A			DU_DB5			PWM0_B			CANFD0_TX_A
++sel_pwm1	PWM1_A			VI0_DATA9		PWM1_B			CANFD0_RX_A
++sel_pwm2	PWM2_A			VI0_DATA10		PWM2_B			CANFD1_TX
++sel_pwm3	PWM3_A			VI0_DATA11		PWM3_B			CANFD1_RX
++sel_pwm4	PWM4_A			VI0_FIELD		PWM4_B			CANFD_CLK_A
++sel_rsp		SPEEDIN_A		VI0_DATA1		SPEEDIN_B		CANFD_CLK_A
++sel_scif1	RX1_A			VI0_DATA4		RX1_B			CANFD1_RX
++		TX1_A			VI0_DATA5		TX1_B			CANFD1_TX
++sel_tmu		TCLK1_A			VI1_DATA9		TCLK1_B			CANFD1_TX
++		TCLK2_A			VI1_DATA10		TCLK2_B			CANFD1_RX
++*/
++/* MOD_SEL0 */		/* 0 */			/* 1 */			/* 2 */	/* 3 */	/* 4 */	/* 5 */	/* 6 */	/* 7 */
++#define MOD_SEL0_11	FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
++#define MOD_SEL0_10	FM(SEL_GETHER_0)	FM(SEL_GETHER_1)
++#define MOD_SEL0_9	FM(SEL_HSCIF0_0)	FM(SEL_HSCIF0_1)
++#define MOD_SEL0_8	FM(SEL_PWM0_0)		FM(SEL_PWM0_1)
++#define MOD_SEL0_7	FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
++#define MOD_SEL0_6	FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
++#define MOD_SEL0_5	FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
++#define MOD_SEL0_4	FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
++#define MOD_SEL0_2	FM(SEL_RSP_0)		FM(SEL_RSP_1)
++#define MOD_SEL0_1	FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
++#define MOD_SEL0_0	FM(SEL_TMU1_0)		FM(SEL_TMU1_1)
++
++#define PINMUX_MOD_SELS \
++\
++MOD_SEL0_11 \
++MOD_SEL0_10 \
++MOD_SEL0_9 \
++MOD_SEL0_8 \
++MOD_SEL0_7 \
++MOD_SEL0_6 \
++MOD_SEL0_5 \
++MOD_SEL0_4 \
++MOD_SEL0_2 \
++MOD_SEL0_1 \
++MOD_SEL0_0
++
++enum {
++	PINMUX_RESERVED = 0,
++
++	PINMUX_DATA_BEGIN,
++	GP_ALL(DATA),
++	PINMUX_DATA_END,
++
++#define F_(x, y)
++#define FM(x)   FN_##x,
++	PINMUX_FUNCTION_BEGIN,
++	GP_ALL(FN),
++	PINMUX_GPSR
++	PINMUX_IPSR
++	PINMUX_MOD_SELS
++	PINMUX_FUNCTION_END,
++#undef F_
++#undef FM
++
++#define F_(x, y)
++#define FM(x)	x##_MARK,
++	PINMUX_MARK_BEGIN,
++	PINMUX_GPSR
++	PINMUX_IPSR
++	PINMUX_MOD_SELS
++	PINMUX_MARK_END,
++#undef F_
++#undef FM
++};
++
++static const u16 pinmux_data[] = {
++	PINMUX_DATA_GP_ALL(),
++
++	PINMUX_SINGLE(AVB_RX_CTL),
++	PINMUX_SINGLE(AVB_RXC),
++	PINMUX_SINGLE(AVB_RD0),
++	PINMUX_SINGLE(AVB_RD1),
++	PINMUX_SINGLE(AVB_RD2),
++	PINMUX_SINGLE(AVB_RD3),
++	PINMUX_SINGLE(AVB_TX_CTL),
++	PINMUX_SINGLE(AVB_TXC),
++	PINMUX_SINGLE(AVB_TD0),
++	PINMUX_SINGLE(AVB_TD1),
++	PINMUX_SINGLE(AVB_TD2),
++	PINMUX_SINGLE(AVB_TD3),
++	PINMUX_SINGLE(AVB_TXCREFCLK),
++	PINMUX_SINGLE(AVB_MDIO),
++	PINMUX_SINGLE(AVB_MDC),
++	PINMUX_SINGLE(AVB_MAGIC),
++	PINMUX_SINGLE(AVB_PHY_INT),
++	PINMUX_SINGLE(AVB_LINK),
++
++	PINMUX_SINGLE(GETHER_RX_CTL),
++	PINMUX_SINGLE(GETHER_RXC),
++	PINMUX_SINGLE(GETHER_RD0),
++	PINMUX_SINGLE(GETHER_RD1),
++	PINMUX_SINGLE(GETHER_RD2),
++	PINMUX_SINGLE(GETHER_RD3),
++	PINMUX_SINGLE(GETHER_TX_CTL),
++	PINMUX_SINGLE(GETHER_TXC),
++	PINMUX_SINGLE(GETHER_TD0),
++	PINMUX_SINGLE(GETHER_TD1),
++	PINMUX_SINGLE(GETHER_TD2),
++	PINMUX_SINGLE(GETHER_TD3),
++	PINMUX_SINGLE(GETHER_TXCREFCLK),
++	PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
++	PINMUX_SINGLE(GETHER_MDIO_A),
++	PINMUX_SINGLE(GETHER_MDC_A),
++	PINMUX_SINGLE(GETHER_MAGIC),
++	PINMUX_SINGLE(GETHER_PHY_INT_A),
++	PINMUX_SINGLE(GETHER_LINK_A),
++
++	PINMUX_SINGLE(QSPI0_SPCLK),
++	PINMUX_SINGLE(QSPI0_MOSI_IO0),
++	PINMUX_SINGLE(QSPI0_MISO_IO1),
++	PINMUX_SINGLE(QSPI0_IO2),
++	PINMUX_SINGLE(QSPI0_IO3),
++	PINMUX_SINGLE(QSPI0_SSL),
++	PINMUX_SINGLE(QSPI1_SPCLK),
++	PINMUX_SINGLE(QSPI1_MOSI_IO0),
++	PINMUX_SINGLE(QSPI1_MISO_IO1),
++	PINMUX_SINGLE(QSPI1_IO2),
++	PINMUX_SINGLE(QSPI1_IO3),
++	PINMUX_SINGLE(QSPI1_SSL),
++	PINMUX_SINGLE(RPC_RESET_N),
++	PINMUX_SINGLE(RPC_WP_N),
++	PINMUX_SINGLE(RPC_INT_N),
++
++	/* IPSR0 */
++	PINMUX_IPSR_GPSR(IP0_3_0,	DU_DR2),
++	PINMUX_IPSR_GPSR(IP0_3_0,	SCK4),
++	PINMUX_IPSR_GPSR(IP0_3_0,	GETHER_RMII_CRS_DV),
++	PINMUX_IPSR_GPSR(IP0_3_0,	A0),
++
++	PINMUX_IPSR_GPSR(IP0_7_4,	DU_DR3),
++	PINMUX_IPSR_GPSR(IP0_7_4,	RX4),
++	PINMUX_IPSR_GPSR(IP0_7_4,	GETHER_RMII_RX_ER),
++	PINMUX_IPSR_GPSR(IP0_7_4,	A1),
++
++	PINMUX_IPSR_GPSR(IP0_11_8,	DU_DR4),
++	PINMUX_IPSR_GPSR(IP0_11_8,	TX4),
++	PINMUX_IPSR_GPSR(IP0_11_8,	GETHER_RMII_RXD0),
++	PINMUX_IPSR_GPSR(IP0_11_8,	A2),
++
++	PINMUX_IPSR_GPSR(IP0_15_12,	DU_DR5),
++	PINMUX_IPSR_GPSR(IP0_15_12,	CTS4_N),
++	PINMUX_IPSR_GPSR(IP0_15_12,	GETHER_RMII_RXD1),
++	PINMUX_IPSR_GPSR(IP0_15_12,	A3),
++
++	PINMUX_IPSR_GPSR(IP0_19_16,	DU_DR6),
++	PINMUX_IPSR_GPSR(IP0_19_16,	RTS4_N_TANS),
++	PINMUX_IPSR_GPSR(IP0_19_16,	GETHER_RMII_TXD_EN),
++	PINMUX_IPSR_GPSR(IP0_19_16,	A4),
++
++	PINMUX_IPSR_GPSR(IP0_23_20,	DU_DR7),
++	PINMUX_IPSR_GPSR(IP0_23_20,	GETHER_RMII_TXD0),
++	PINMUX_IPSR_GPSR(IP0_23_20,	A5),
++
++	PINMUX_IPSR_GPSR(IP0_27_24,	DU_DG2),
++	PINMUX_IPSR_GPSR(IP0_27_24,	GETHER_RMII_TXD1),
++	PINMUX_IPSR_GPSR(IP0_27_24,	A6),
++
++	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DG3),
++	PINMUX_IPSR_GPSR(IP0_31_28,	CPG_CPCKOUT),
++	PINMUX_IPSR_GPSR(IP0_31_28,	GETHER_RMII_REFCLK),
++	PINMUX_IPSR_GPSR(IP0_31_28,	A7),
++	PINMUX_IPSR_GPSR(IP0_31_28,	PWMFSW0),
++
++	/* IPSR1 */
++	PINMUX_IPSR_GPSR(IP1_3_0,	DU_DG4),
++	PINMUX_IPSR_GPSR(IP1_3_0,	SCL5),
++	PINMUX_IPSR_GPSR(IP1_3_0,	A8),
++
++	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DG5),
++	PINMUX_IPSR_GPSR(IP1_7_4,	SDA5),
++	PINMUX_IPSR_MSEL(IP1_7_4,	GETHER_MDC_B, SEL_GETHER_1),
++	PINMUX_IPSR_GPSR(IP1_7_4,	A9),
++
++	PINMUX_IPSR_GPSR(IP1_11_8,	DU_DG6),
++	PINMUX_IPSR_MSEL(IP1_11_8,	SCIF_CLK_A, SEL_HSCIF0_0),
++	PINMUX_IPSR_MSEL(IP1_11_8,	GETHER_MDIO_B, SEL_GETHER_1),
++	PINMUX_IPSR_GPSR(IP1_11_8,	A10),
++
++	PINMUX_IPSR_GPSR(IP1_15_12,	DU_DG7),
++	PINMUX_IPSR_MSEL(IP1_15_12,	HRX0_A, SEL_HSCIF0_0),
++	PINMUX_IPSR_GPSR(IP1_15_12,	A11),
++
++	PINMUX_IPSR_GPSR(IP1_19_16,	DU_DB2),
++	PINMUX_IPSR_MSEL(IP1_19_16,	HSCK0_A, SEL_HSCIF0_0),
++	PINMUX_IPSR_GPSR(IP1_19_16,	A12),
++	PINMUX_IPSR_GPSR(IP1_19_16,	IRQ1),
++
++	PINMUX_IPSR_GPSR(IP1_23_20,	DU_DB3),
++	PINMUX_IPSR_MSEL(IP1_23_20,	HRTS0_N_A, SEL_HSCIF0_0),
++	PINMUX_IPSR_GPSR(IP1_23_20,	A13),
++	PINMUX_IPSR_GPSR(IP1_23_20,	IRQ2),
++
++	PINMUX_IPSR_GPSR(IP1_27_24,	DU_DB4),
++	PINMUX_IPSR_MSEL(IP1_27_24,	HCTS0_N_A, SEL_HSCIF0_0),
++	PINMUX_IPSR_GPSR(IP1_27_24,	A14),
++	PINMUX_IPSR_GPSR(IP1_27_24,	IRQ3),
++
++	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB5),
++	PINMUX_IPSR_MSEL(IP1_31_28,	HTX0_A, SEL_HSCIF0_0),
++	PINMUX_IPSR_MSEL(IP1_31_28,	PWM0_A, SEL_PWM0_0),
++	PINMUX_IPSR_GPSR(IP1_31_28,	A15),
++
++	/* IPSR2 */
++	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB6),
++	PINMUX_IPSR_GPSR(IP2_3_0,	MSIOF3_RXD),
++	PINMUX_IPSR_GPSR(IP2_3_0,	A16),
++
++	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB7),
++	PINMUX_IPSR_GPSR(IP2_7_4,	MSIOF3_TXD),
++	PINMUX_IPSR_GPSR(IP2_7_4,	A17),
++
++	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DOTCLKOUT),
++	PINMUX_IPSR_GPSR(IP2_11_8,	MSIOF3_SS1),
++	PINMUX_IPSR_MSEL(IP2_11_8,	GETHER_LINK_B, SEL_GETHER_1),
++	PINMUX_IPSR_GPSR(IP2_11_8,	A18),
++
++	PINMUX_IPSR_GPSR(IP2_15_12,	DU_EXHSYNC_DU_HSYNC),
++	PINMUX_IPSR_GPSR(IP2_15_12,	MSIOF3_SS2),
++	PINMUX_IPSR_MSEL(IP2_15_12,	GETHER_PHY_INT_B, SEL_GETHER_1),
++	PINMUX_IPSR_GPSR(IP2_15_12,	A19),
++	PINMUX_IPSR_GPSR(IP2_15_12,	FXR_TXENA_N),
++
++	PINMUX_IPSR_GPSR(IP2_19_16,	DU_EXVSYNC_DU_VSYNC),
++	PINMUX_IPSR_GPSR(IP2_19_16,	MSIOF3_SCK),
++	PINMUX_IPSR_GPSR(IP2_19_16,	FXR_TXENB_N),
++
++	PINMUX_IPSR_GPSR(IP2_23_20,	DU_EXODDF_DU_ODDF_DISP_CDE),
++	PINMUX_IPSR_GPSR(IP2_23_20,	MSIOF3_SYNC),
++
++	PINMUX_IPSR_GPSR(IP2_27_24,	IRQ0),
++	PINMUX_IPSR_GPSR(IP2_27_24,	CC5_OSCOUT),
++
++	PINMUX_IPSR_GPSR(IP2_31_28,	VI0_CLK),
++	PINMUX_IPSR_GPSR(IP2_31_28,	MSIOF2_SCK),
++	PINMUX_IPSR_GPSR(IP2_31_28,	SCK3),
++	PINMUX_IPSR_GPSR(IP2_31_28,	HSCK3),
++
++	/* IPSR3 */
++	PINMUX_IPSR_GPSR(IP3_3_0,	VI0_CLKENB),
++	PINMUX_IPSR_GPSR(IP3_3_0,	MSIOF2_RXD),
++	PINMUX_IPSR_GPSR(IP3_3_0,	RX3),
++	PINMUX_IPSR_GPSR(IP3_3_0,	RD_WR_N),
++	PINMUX_IPSR_GPSR(IP3_3_0,	HCTS3_N),
++
++	PINMUX_IPSR_GPSR(IP3_7_4,	VI0_HSYNC_N),
++	PINMUX_IPSR_GPSR(IP3_7_4,	MSIOF2_TXD),
++	PINMUX_IPSR_GPSR(IP3_7_4,	TX3),
++	PINMUX_IPSR_GPSR(IP3_7_4,	HRTS3_N),
++
++	PINMUX_IPSR_GPSR(IP3_11_8,	VI0_VSYNC_N),
++	PINMUX_IPSR_GPSR(IP3_11_8,	MSIOF2_SYNC),
++	PINMUX_IPSR_GPSR(IP3_11_8,	CTS3_N),
++	PINMUX_IPSR_GPSR(IP3_11_8,	HTX3),
++
++	PINMUX_IPSR_GPSR(IP3_15_12,	VI0_DATA0),
++	PINMUX_IPSR_GPSR(IP3_15_12,	MSIOF2_SS1),
++	PINMUX_IPSR_GPSR(IP3_15_12,	RTS3_N_TANS),
++	PINMUX_IPSR_GPSR(IP3_15_12,	HRX3),
++
++	PINMUX_IPSR_GPSR(IP3_19_16,	VI0_DATA1),
++	PINMUX_IPSR_GPSR(IP3_19_16,	MSIOF2_SS2),
++	PINMUX_IPSR_GPSR(IP3_19_16,	SCK1),
++	PINMUX_IPSR_MSEL(IP3_19_16,	SPEEDIN_A, SEL_RSP_0),
++
++	PINMUX_IPSR_GPSR(IP3_23_20,	VI0_DATA2),
++	PINMUX_IPSR_GPSR(IP3_23_20,	AVB_AVTP_PPS),
++
++	PINMUX_IPSR_GPSR(IP3_27_24,	VI0_DATA3),
++	PINMUX_IPSR_GPSR(IP3_27_24,	HSCK1),
++
++	PINMUX_IPSR_GPSR(IP3_31_28,	VI0_DATA4),
++	PINMUX_IPSR_GPSR(IP3_31_28,	HRTS1_N),
++	PINMUX_IPSR_MSEL(IP3_31_28,	RX1_A, SEL_SCIF1_0),
++
++	/* IPSR4 */
++	PINMUX_IPSR_GPSR(IP4_3_0,	VI0_DATA5),
++	PINMUX_IPSR_GPSR(IP4_3_0,	HCTS1_N),
++	PINMUX_IPSR_MSEL(IP4_3_0,	TX1_A, SEL_SCIF1_0),
++
++	PINMUX_IPSR_GPSR(IP4_7_4,	VI0_DATA6),
++	PINMUX_IPSR_GPSR(IP4_7_4,	HTX1),
++	PINMUX_IPSR_GPSR(IP4_7_4,	CTS1_N),
++
++	PINMUX_IPSR_GPSR(IP4_11_8,	VI0_DATA7),
++	PINMUX_IPSR_GPSR(IP4_11_8,	HRX1),
++	PINMUX_IPSR_GPSR(IP4_11_8,	RTS1_N_TANS),
++
++	PINMUX_IPSR_GPSR(IP4_15_12,	VI0_DATA8),
++	PINMUX_IPSR_GPSR(IP4_15_12,	HSCK2),
++
++	PINMUX_IPSR_GPSR(IP4_19_16,	VI0_DATA9),
++	PINMUX_IPSR_GPSR(IP4_19_16,	HCTS2_N),
++	PINMUX_IPSR_MSEL(IP4_19_16,	PWM1_A, SEL_PWM1_0),
++
++	PINMUX_IPSR_GPSR(IP4_23_20,	VI0_DATA10),
++	PINMUX_IPSR_GPSR(IP4_23_20,	HRTS2_N),
++	PINMUX_IPSR_MSEL(IP4_23_20,	PWM2_A, SEL_PWM2_0),
++
++	PINMUX_IPSR_GPSR(IP4_27_24,	VI0_DATA11),
++	PINMUX_IPSR_GPSR(IP4_27_24,	HTX2),
++	PINMUX_IPSR_MSEL(IP4_27_24,	PWM3_A, SEL_PWM3_0),
++
++	PINMUX_IPSR_GPSR(IP4_31_28,	VI0_FIELD),
++	PINMUX_IPSR_GPSR(IP4_31_28,	HRX2),
++	PINMUX_IPSR_MSEL(IP4_31_28,	PWM4_A, SEL_PWM4_0),
++	PINMUX_IPSR_GPSR(IP4_31_28,	CS1_N),
++
++	/* IPSR5 */
++	PINMUX_IPSR_GPSR(IP5_3_0,	VI1_CLK),
++	PINMUX_IPSR_GPSR(IP5_3_0,	MSIOF1_RXD),
++	PINMUX_IPSR_GPSR(IP5_3_0,	CS0_N),
++
++	PINMUX_IPSR_GPSR(IP5_7_4,	VI1_CLKENB),
++	PINMUX_IPSR_GPSR(IP5_7_4,	MSIOF1_TXD),
++	PINMUX_IPSR_GPSR(IP5_7_4,	D0),
++
++	PINMUX_IPSR_GPSR(IP5_11_8,	VI1_HSYNC_N),
++	PINMUX_IPSR_GPSR(IP5_11_8,	MSIOF1_SCK),
++	PINMUX_IPSR_GPSR(IP5_11_8,	D1),
++
++	PINMUX_IPSR_GPSR(IP5_15_12,	VI1_VSYNC_N),
++	PINMUX_IPSR_GPSR(IP5_15_12,	MSIOF1_SYNC),
++	PINMUX_IPSR_GPSR(IP5_15_12,	D2),
++
++	PINMUX_IPSR_GPSR(IP5_19_16,	VI1_DATA0),
++	PINMUX_IPSR_GPSR(IP5_19_16,	MSIOF1_SS1),
++	PINMUX_IPSR_GPSR(IP5_19_16,	D3),
++	PINMUX_IPSR_GPSR(IP5_19_16,	MMC_WP),
++
++	PINMUX_IPSR_GPSR(IP5_23_20,	VI1_DATA1),
++	PINMUX_IPSR_GPSR(IP5_23_20,	MSIOF1_SS2),
++	PINMUX_IPSR_GPSR(IP5_23_20,	D4),
++	PINMUX_IPSR_GPSR(IP5_23_20,	MMC_CD),
++
++	PINMUX_IPSR_GPSR(IP5_27_24,	VI1_DATA2),
++	PINMUX_IPSR_MSEL(IP5_27_24,	CANFD0_TX_B, SEL_CANFD0_1),
++	PINMUX_IPSR_GPSR(IP5_27_24,	D5),
++	PINMUX_IPSR_GPSR(IP5_27_24,	MMC_DS),
++
++	PINMUX_IPSR_GPSR(IP5_31_28,	VI1_DATA3),
++	PINMUX_IPSR_MSEL(IP5_31_28,	CANFD0_RX_B, SEL_CANFD0_1),
++	PINMUX_IPSR_GPSR(IP5_31_28,	D6),
++	PINMUX_IPSR_GPSR(IP5_31_28,	MMC_CMD),
++
++	/* IPSR6 */
++	PINMUX_IPSR_GPSR(IP6_3_0,	VI1_DATA4),
++	PINMUX_IPSR_MSEL(IP6_3_0,	CANFD_CLK_B, SEL_CANFD0_1),
++	PINMUX_IPSR_GPSR(IP6_3_0,	D7),
++	PINMUX_IPSR_GPSR(IP6_3_0,	MMC_D0),
++
++	PINMUX_IPSR_GPSR(IP6_7_4,	VI1_DATA5),
++	PINMUX_IPSR_GPSR(IP6_7_4,	D8),
++	PINMUX_IPSR_GPSR(IP6_7_4,	MMC_D1),
++
++	PINMUX_IPSR_GPSR(IP6_11_8,	VI1_DATA6),
++	PINMUX_IPSR_GPSR(IP6_11_8,	D9),
++	PINMUX_IPSR_GPSR(IP6_11_8,	MMC_D2),
++
++	PINMUX_IPSR_GPSR(IP6_15_12,	VI1_DATA7),
++	PINMUX_IPSR_GPSR(IP6_15_12,	D10),
++	PINMUX_IPSR_GPSR(IP6_15_12,	MMC_D3),
++
++	PINMUX_IPSR_GPSR(IP6_19_16,	VI1_DATA8),
++	PINMUX_IPSR_GPSR(IP6_19_16,	D11),
++	PINMUX_IPSR_GPSR(IP6_19_16,	MMC_CLK),
++
++	PINMUX_IPSR_GPSR(IP6_23_20,	VI1_DATA9),
++	PINMUX_IPSR_MSEL(IP6_23_20,	TCLK1_A, SEL_TMU1_0),
++	PINMUX_IPSR_GPSR(IP6_23_20,	D12),
++	PINMUX_IPSR_GPSR(IP6_23_20,	MMC_D4),
++
++	PINMUX_IPSR_GPSR(IP6_27_24,	VI1_DATA10),
++	PINMUX_IPSR_MSEL(IP6_27_24,	TCLK2_A, SEL_TMU1_0),
++	PINMUX_IPSR_GPSR(IP6_27_24,	D13),
++	PINMUX_IPSR_GPSR(IP6_27_24,	MMC_D5),
++
++	PINMUX_IPSR_GPSR(IP6_31_28,	VI1_DATA11),
++	PINMUX_IPSR_GPSR(IP6_31_28,	SCL4),
++	PINMUX_IPSR_GPSR(IP6_31_28,	D14),
++	PINMUX_IPSR_GPSR(IP6_31_28,	MMC_D6),
++
++	/* IPSR7 */
++	PINMUX_IPSR_GPSR(IP7_3_0,	VI1_FIELD),
++	PINMUX_IPSR_GPSR(IP7_3_0,	SDA4),
++	PINMUX_IPSR_GPSR(IP7_3_0,	D15),
++	PINMUX_IPSR_GPSR(IP7_3_0,	MMC_D7),
++
++	PINMUX_IPSR_GPSR(IP7_7_4,	SCL0),
++	PINMUX_IPSR_GPSR(IP7_7_4,	CLKOUT),
++
++	PINMUX_IPSR_GPSR(IP7_11_8,	SDA0),
++	PINMUX_IPSR_GPSR(IP7_11_8,	BS_N),
++	PINMUX_IPSR_GPSR(IP7_11_8,	SCK0),
++	PINMUX_IPSR_MSEL(IP7_11_8,	HSCK0_B, SEL_HSCIF0_1),
++
++	PINMUX_IPSR_GPSR(IP7_15_12,	SCL1),
++	PINMUX_IPSR_GPSR(IP7_15_12,	TPU0TO2),
++	PINMUX_IPSR_GPSR(IP7_15_12,	RD_N),
++	PINMUX_IPSR_GPSR(IP7_15_12,	CTS0_N),
++	PINMUX_IPSR_GPSR(IP7_15_12,	HCTS0_N_B),
++
++	PINMUX_IPSR_GPSR(IP7_19_16,	SDA1),
++	PINMUX_IPSR_GPSR(IP7_19_16,	TPU0TO3),
++	PINMUX_IPSR_GPSR(IP7_19_16,	WE0_N),
++	PINMUX_IPSR_GPSR(IP7_19_16,	RTS0_N_TANS),
++	PINMUX_IPSR_GPSR(IP7_19_16,	HRTS0_N_B),
++
++	PINMUX_IPSR_GPSR(IP7_23_20,	SCL2),
++	PINMUX_IPSR_GPSR(IP7_23_20,	WE1_N),
++	PINMUX_IPSR_GPSR(IP7_23_20,	RX0),
++	PINMUX_IPSR_MSEL(IP7_23_20,	HRX0_B, SEL_HSCIF0_1),
++
++	PINMUX_IPSR_GPSR(IP7_27_24,	SDA2),
++	PINMUX_IPSR_GPSR(IP7_27_24,	EX_WAIT0),
++	PINMUX_IPSR_GPSR(IP7_27_24,	TX0),
++	PINMUX_IPSR_MSEL(IP7_27_24,	HTX0_B, SEL_HSCIF0_1),
++
++	PINMUX_IPSR_GPSR(IP7_31_28,	AVB_AVTP_MATCH),
++	PINMUX_IPSR_GPSR(IP7_31_28,	TPU0TO0),
++
++	/* IPSR8 */
++	PINMUX_IPSR_GPSR(IP8_3_0,	AVB_AVTP_CAPTURE),
++	PINMUX_IPSR_GPSR(IP8_3_0,	TPU0TO1),
++
++	PINMUX_IPSR_MSEL(IP8_7_4,	CANFD0_TX_A, SEL_CANFD0_0),
++	PINMUX_IPSR_GPSR(IP8_7_4,	FXR_TXDA),
++	PINMUX_IPSR_MSEL(IP8_7_4,	PWM0_B, SEL_PWM0_1),
++	PINMUX_IPSR_GPSR(IP8_7_4,	DU_DISP),
++
++	PINMUX_IPSR_MSEL(IP8_11_8,	CANFD0_RX_A, SEL_CANFD0_0),
++	PINMUX_IPSR_GPSR(IP8_11_8,	RXDA_EXTFXR),
++	PINMUX_IPSR_MSEL(IP8_11_8,	PWM1_B, SEL_PWM1_1),
++	PINMUX_IPSR_GPSR(IP8_11_8,	DU_CDE),
++
++	PINMUX_IPSR_GPSR(IP8_15_12,	CANFD1_TX),
++	PINMUX_IPSR_GPSR(IP8_15_12,	FXR_TXDB),
++	PINMUX_IPSR_MSEL(IP8_15_12,	PWM2_B, SEL_PWM2_1),
++	PINMUX_IPSR_MSEL(IP8_15_12,	TCLK1_B, SEL_TMU1_1),
++	PINMUX_IPSR_MSEL(IP8_15_12,	TX1_B, SEL_SCIF1_1),
++
++	PINMUX_IPSR_GPSR(IP8_19_16,	CANFD1_RX),
++	PINMUX_IPSR_GPSR(IP8_19_16,	RXDB_EXTFXR),
++	PINMUX_IPSR_MSEL(IP8_19_16,	PWM3_B, SEL_PWM3_1),
++	PINMUX_IPSR_MSEL(IP8_19_16,	TCLK2_B, SEL_TMU1_1),
++	PINMUX_IPSR_MSEL(IP8_19_16,	RX1_B, SEL_SCIF1_1),
++
++	PINMUX_IPSR_MSEL(IP8_23_20,	CANFD_CLK_A, SEL_CANFD0_0),
++	PINMUX_IPSR_GPSR(IP8_23_20,	CLK_EXTFXR),
++	PINMUX_IPSR_MSEL(IP8_23_20,	PWM4_B, SEL_PWM4_1),
++	PINMUX_IPSR_MSEL(IP8_23_20,	SPEEDIN_B, SEL_RSP_1),
++	PINMUX_IPSR_MSEL(IP8_23_20,	SCIF_CLK_B, SEL_HSCIF0_1),
++
++	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKIN),
++	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKEN_IN),
++
++	PINMUX_IPSR_GPSR(IP8_31_28,	DIGRF_CLKOUT),
++	PINMUX_IPSR_GPSR(IP8_31_28,	DIGRF_CLKEN_OUT),
++
++	/* IPSR9 */
++	PINMUX_IPSR_GPSR(IP9_3_0,	IRQ4),
++	PINMUX_IPSR_GPSR(IP9_3_0,	VI0_DATA12),
++
++	PINMUX_IPSR_GPSR(IP9_7_4,	IRQ5),
++	PINMUX_IPSR_GPSR(IP9_7_4,	VI0_DATA13),
++
++	PINMUX_IPSR_GPSR(IP9_11_8,	MSIOF0_RXD),
++	PINMUX_IPSR_GPSR(IP9_11_8,	DU_DR0),
++	PINMUX_IPSR_GPSR(IP9_11_8,	VI0_DATA14),
++
++	PINMUX_IPSR_GPSR(IP9_15_12,	MSIOF0_TXD),
++	PINMUX_IPSR_GPSR(IP9_15_12,	DU_DR1),
++	PINMUX_IPSR_GPSR(IP9_15_12,	VI0_DATA15),
++
++	PINMUX_IPSR_GPSR(IP9_19_16,	MSIOF0_SCK),
++	PINMUX_IPSR_GPSR(IP9_19_16,	DU_DG0),
++	PINMUX_IPSR_GPSR(IP9_19_16,	VI0_DATA16),
++
++	PINMUX_IPSR_GPSR(IP9_23_20,	MSIOF0_SYNC),
++	PINMUX_IPSR_GPSR(IP9_23_20,	DU_DG1),
++	PINMUX_IPSR_GPSR(IP9_23_20,	VI0_DATA17),
++
++	PINMUX_IPSR_GPSR(IP9_27_24,	MSIOF0_SS1),
++	PINMUX_IPSR_GPSR(IP9_27_24,	DU_DB0),
++	PINMUX_IPSR_GPSR(IP9_27_24,	TCLK3),
++	PINMUX_IPSR_GPSR(IP9_27_24,	VI0_DATA18),
++
++	PINMUX_IPSR_GPSR(IP9_31_28,	MSIOF0_SS2),
++	PINMUX_IPSR_GPSR(IP9_31_28,	DU_DB1),
++	PINMUX_IPSR_GPSR(IP9_31_28,	TCLK4),
++	PINMUX_IPSR_GPSR(IP9_31_28,	VI0_DATA19),
++
++	/* IPSR10 */
++	PINMUX_IPSR_GPSR(IP10_3_0,	SCL3),
++	PINMUX_IPSR_GPSR(IP10_3_0,	VI0_DATA20),
++
++	PINMUX_IPSR_GPSR(IP10_7_4,	SDA3),
++	PINMUX_IPSR_GPSR(IP10_7_4,	VI0_DATA21),
++
++	PINMUX_IPSR_GPSR(IP10_11_8,	FSO_CFE_0_N),
++	PINMUX_IPSR_GPSR(IP10_11_8,	VI0_DATA22),
++
++	PINMUX_IPSR_GPSR(IP10_15_12,	FSO_CFE_1_N),
++	PINMUX_IPSR_GPSR(IP10_15_12,	VI0_DATA23),
++
++	PINMUX_IPSR_GPSR(IP10_19_16,	FSO_TOE_N),
++};
++
++static const struct sh_pfc_pin pinmux_pins[] = {
++	PINMUX_GPIO_GP_ALL(),
++};
++
++/* - EtherAVB --------------------------------------------------------------- */
++static const unsigned int avb_rx_ctrl_pins[] = {
++	/* AVB_RX_CTL */
++	RCAR_GP_PIN(1, 1),
++};
++static const unsigned int avb_rx_ctrl_mux[] = {
++	AVB_RX_CTL_MARK,
++};
++static const unsigned int avb_rxc_pins[] = {
++	/* AVB_RXC */
++	RCAR_GP_PIN(1, 2),
++};
++static const unsigned int avb_rxc_mux[] = {
++	AVB_RXC_MARK,
++};
++static const unsigned int avb_rd0_pins[] = {
++	/* AVB_RD[0] */
++	RCAR_GP_PIN(1, 3),
++};
++static const unsigned int avb_rd0_mux[] = {
++	AVB_RD0_MARK,
++};
++static const unsigned int avb_rd1_pins[] = {
++	/* AVB_RD[1] */
++	RCAR_GP_PIN(1, 4),
++};
++static const unsigned int avb_rd1_mux[] = {
++	AVB_RD1_MARK,
++};
++static const unsigned int avb_rd2_pins[] = {
++	/* AVB_RD[2] */
++	RCAR_GP_PIN(1, 5),
++};
++static const unsigned int avb_rd2_mux[] = {
++	AVB_RD2_MARK,
++};
++static const unsigned int avb_rd3_pins[] = {
++	/* AVB_RD[3] */
++	RCAR_GP_PIN(1, 6),
++};
++static const unsigned int avb_rd3_mux[] = {
++	AVB_RD3_MARK,
++};
++static const unsigned int avb_rd4_pins[] = {
++	/* AVB_RD[3:0] */
++	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
++	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
++};
++static const unsigned int avb_rd4_mux[] = {
++	AVB_RD0_MARK, AVB_RD1_MARK,
++	AVB_RD2_MARK, AVB_RD3_MARK,
++};
++static const unsigned int avb_tx_ctrl_pins[] = {
++	/* AVB_TX_CTL */
++	RCAR_GP_PIN(1, 7),
++};
++static const unsigned int avb_tx_ctrl_mux[] = {
++	AVB_TX_CTL_MARK,
++};
++static const unsigned int avb_txc_pins[] = {
++	/* AVB_TXC */
++	RCAR_GP_PIN(1, 8),
++};
++static const unsigned int avb_txc_mux[] = {
++	AVB_TXC_MARK,
++};
++static const unsigned int avb_td0_pins[] = {
++	/* AVB_TD[0] */
++	RCAR_GP_PIN(1, 9),
++};
++static const unsigned int avb_td0_mux[] = {
++	AVB_TD0_MARK,
++};
++static const unsigned int avb_td1_pins[] = {
++	/* AVB_TD[1] */
++	RCAR_GP_PIN(1, 10),
++};
++static const unsigned int avb_td1_mux[] = {
++	AVB_TD1_MARK,
++};
++static const unsigned int avb_td2_pins[] = {
++	/* AVB_TD[2] */
++	RCAR_GP_PIN(1, 11),
++};
++static const unsigned int avb_td2_mux[] = {
++	AVB_TD2_MARK,
++};
++static const unsigned int avb_td3_pins[] = {
++	/* AVB_TD[3] */
++	RCAR_GP_PIN(1, 12),
++};
++static const unsigned int avb_td3_mux[] = {
++	AVB_TD3_MARK,
++};
++static const unsigned int avb_td4_pins[] = {
++	/* AVB_TD[3:0] */
++	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
++	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
++};
++static const unsigned int avb_td4_mux[] = {
++	AVB_TD0_MARK, AVB_TD1_MARK,
++	AVB_TD2_MARK, AVB_TD3_MARK,
++};
++static const unsigned int avb_txcrefclk_pins[] = {
++	/* AVB_TXCREFCLK */
++	RCAR_GP_PIN(1, 13),
++};
++static const unsigned int avb_txcrefclk_mux[] = {
++	AVB_TXCREFCLK_MARK,
++};
++static const unsigned int avb_mdio_pins[] = {
++	/* AVB_MDIO */
++	RCAR_GP_PIN(1, 14),
++};
++static const unsigned int avb_mdio_mux[] = {
++	AVB_MDIO_MARK,
++};
++static const unsigned int avb_mdc_pins[] = {
++	/* AVB_MDC */
++	RCAR_GP_PIN(1, 15),
++};
++static const unsigned int avb_mdc_mux[] = {
++	AVB_MDC_MARK,
++};
++static const unsigned int avb_magic_pins[] = {
++	/* AVB_MAGIC */
++	RCAR_GP_PIN(1, 16),
++};
++static const unsigned int avb_magic_mux[] = {
++	AVB_MAGIC_MARK,
++};
++static const unsigned int avb_phy_int_pins[] = {
++	/* AVB_PHY_INT */
++	RCAR_GP_PIN(1, 17),
++};
++static const unsigned int avb_phy_int_mux[] = {
++	AVB_PHY_INT_MARK,
++};
++static const unsigned int avb_link_pins[] = {
++	/* AVB_LINK */
++	RCAR_GP_PIN(1, 18),
++};
++static const unsigned int avb_link_mux[] = {
++	AVB_LINK_MARK,
++};
++static const unsigned int avb_avtp_match_pins[] = {
++	/* AVB_AVTP_MATCH */
++	RCAR_GP_PIN(1, 19),
++};
++static const unsigned int avb_avtp_match_mux[] = {
++	AVB_AVTP_MATCH_MARK,
++};
++static const unsigned int avb_avtp_capture_pins[] = {
++	/* AVB_AVTP_CAPTURE */
++	RCAR_GP_PIN(1, 20),
++};
++static const unsigned int avb_avtp_capture_mux[] = {
++	AVB_AVTP_CAPTURE_MARK,
++};
++static const unsigned int avb_avtp_pps_pins[] = {
++	/* AVB_AVTP_PPS */
++	RCAR_GP_PIN(2, 6),
++};
++static const unsigned int avb_avtp_pps_mux[] = {
++	AVB_AVTP_PPS_MARK,
++};
++
++/* - GETHER ----------------------------------------------------------------- */
++static const unsigned int gether_rx_ctrl_pins[] = {
++	/* GETHER_RX_CTL */
++	RCAR_GP_PIN(4, 6),
++};
++static const unsigned int gether_rx_ctrl_mux[] = {
++	GETHER_RX_CTL_MARK,
++};
++static const unsigned int gether_rxc_pins[] = {
++	/* GETHER_RXC */
++	RCAR_GP_PIN(4, 7),
++};
++static const unsigned int gether_rxc_mux[] = {
++	GETHER_RXC_MARK,
++};
++static const unsigned int gether_rd0_pins[] = {
++	/* GETHER_RD[0] */
++	RCAR_GP_PIN(4, 8),
++};
++static const unsigned int gether_rd0_mux[] = {
++	GETHER_RD0_MARK,
++};
++static const unsigned int gether_rd1_pins[] = {
++	/* GETHER_RD[1] */
++	RCAR_GP_PIN(4, 9),
++};
++static const unsigned int gether_rd1_mux[] = {
++	GETHER_RD1_MARK,
++};
++static const unsigned int gether_rd2_pins[] = {
++	/* GETHER_RD[2] */
++	RCAR_GP_PIN(4, 10),
++};
++static const unsigned int gether_rd2_mux[] = {
++	GETHER_RD2_MARK,
++};
++static const unsigned int gether_rd3_pins[] = {
++	/* GETHER_RD[3] */
++	RCAR_GP_PIN(4, 11),
++};
++static const unsigned int gether_rd3_mux[] = {
++	GETHER_RD3_MARK,
++};
++static const unsigned int gether_rd4_pins[] = {
++	/* GETHER_RD[3:0] */
++	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
++	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
++};
++static const unsigned int gether_rd4_mux[] = {
++	GETHER_RD0_MARK, AVB_RD1_MARK,
++	GETHER_RD2_MARK, AVB_RD3_MARK,
++};
++static const unsigned int gether_tx_ctrl_pins[] = {
++	/* GETHER_TX_CTL */
++	RCAR_GP_PIN(4, 12),
++};
++static const unsigned int gether_tx_ctrl_mux[] = {
++	GETHER_TX_CTL_MARK,
++};
++static const unsigned int gether_txc_pins[] = {
++	/* GETHER_TXC */
++	RCAR_GP_PIN(4, 13),
++};
++static const unsigned int gether_txc_mux[] = {
++	GETHER_TXC_MARK,
++};
++static const unsigned int gether_td0_pins[] = {
++	/* GETHER_TD[0] */
++	RCAR_GP_PIN(4, 14),
++};
++static const unsigned int gether_td0_mux[] = {
++	GETHER_TD0_MARK,
++};
++static const unsigned int gether_td1_pins[] = {
++	/* GETHER_TD[1] */
++	RCAR_GP_PIN(4, 15),
++};
++static const unsigned int gether_td1_mux[] = {
++	GETHER_TD1_MARK,
++};
++static const unsigned int gether_td2_pins[] = {
++	/* GETHER_TD[2] */
++	RCAR_GP_PIN(4, 16),
++};
++static const unsigned int gether_td2_mux[] = {
++	GETHER_TD2_MARK,
++};
++static const unsigned int gether_td3_pins[] = {
++	/* GETHER_TD[3] */
++	RCAR_GP_PIN(4, 17),
++};
++static const unsigned int gether_td3_mux[] = {
++	GETHER_TD3_MARK,
++};
++static const unsigned int gether_td4_pins[] = {
++	/* GETHER_TD[3:0] */
++	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
++	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(1, 17),
++};
++static const unsigned int gether_td4_mux[] = {
++	GETHER_TD0_MARK, GETHER_TD1_MARK,
++	GETHER_TD2_MARK, GETHER_TD3_MARK,
++};
++static const unsigned int gether_txcrefclk_pins[] = {
++	/* GETHER_TXCREFCLK */
++	RCAR_GP_PIN(4, 18),
++};
++static const unsigned int gether_txcrefclk_mux[] = {
++	GETHER_TXCREFCLK_MARK,
++};
++static const unsigned int gether_txcrefclk_mega_pins[] = {
++	/* GETHER_TXCREFCLK_MEGA */
++	RCAR_GP_PIN(4, 19),
++};
++static const unsigned int gether_txcrefclk_mega_mux[] = {
++	GETHER_TXCREFCLK_MEGA_MARK,
++};
++static const unsigned int gether_mdio_a_pins[] = {
++	/* GETHER_MDIO_A */
++	RCAR_GP_PIN(4, 20),
++};
++static const unsigned int gether_mdio_a_mux[] = {
++	GETHER_MDIO_A_MARK,
++};
++static const unsigned int gether_mdc_a_pins[] = {
++	/* GETHER_MDC_A */
++	RCAR_GP_PIN(4, 21),
++};
++static const unsigned int gether_mdc_a_mux[] = {
++	GETHER_MDC_A_MARK,
++};
++static const unsigned int gether_magic_pins[] = {
++	/* GETHER_MAGIC */
++	RCAR_GP_PIN(4, 22),
++};
++static const unsigned int gether_magic_mux[] = {
++	GETHER_MAGIC_MARK,
++};
++static const unsigned int gether_phy_int_a_pins[] = {
++	/* GETHER_PHY_INT_A */
++	RCAR_GP_PIN(4, 23),
++};
++static const unsigned int gether_phy_int_a_mux[] = {
++	GETHER_PHY_INT_A_MARK,
++};
++static const unsigned int gether_link_a_pins[] = {
++	/* GETHER_LINK_A */
++	RCAR_GP_PIN(4, 24),
++};
++static const unsigned int gether_link_a_mux[] = {
++	GETHER_LINK_A_MARK,
++};
++
++static const unsigned int gether_mdio_b_pins[] = {
++	/* GETHER_MDIO_B */
++	RCAR_GP_PIN(0, 10),
++};
++static const unsigned int gether_mdio_b_mux[] = {
++	GETHER_MDIO_B_MARK,
++};
++static const unsigned int gether_mdc_b_pins[] = {
++	/* GETHER_MDC_B */
++	RCAR_GP_PIN(0, 9),
++};
++static const unsigned int gether_mdc_b_mux[] = {
++	GETHER_MDC_B_MARK,
++};
++static const unsigned int gether_phy_int_b_pins[] = {
++	/* GETHER_PHY_INT_B */
++	RCAR_GP_PIN(0, 19),
++};
++static const unsigned int gether_phy_int_b_mux[] = {
++	GETHER_PHY_INT_B_MARK,
++};
++static const unsigned int gether_link_b_pins[] = {
++	/* GETHER_LINK_B */
++	RCAR_GP_PIN(0, 18),
++};
++static const unsigned int gether_link_b_mux[] = {
++	GETHER_LINK_B_MARK,
++};
++
++/* OK? */
++static const unsigned int gether_rmii_pins[] = {
++	/* GETHER_RMII_CRS_DV GETHER_RMII_RX_ER GETHER_RMII_RXD0 GETHER_RMII_RXD1 */
++	/* GETHER_RMII_TXD_EN GETHER_RMII_TXD0 GETHER_RMII_TXD1 GETHER_RMII_REFCLK */
++	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
++	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
++	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
++};
++static const unsigned int gether_rmii_mux[] = {
++	GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
++	GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
++	GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
++	GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
++};
++
++/* - CANFD0 ----------------------------------------------------------------- */
++static const unsigned int canfd0_data_a_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
++};
++static const unsigned int canfd0_data_a_mux[] = {
++	CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
++};
++static const unsigned int canfd_clk_a_pins[] = {
++	/* CLK */
++	RCAR_GP_PIN(1, 25),
++};
++static const unsigned int canfd_clk_a_mux[] = {
++	CANFD_CLK_A_MARK,
++};
++static const unsigned int canfd0_data_b_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
++};
++static const unsigned int canfd0_data_b_mux[] = {
++	CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
++};
++static const unsigned int canfd_clk_b_pins[] = {
++	/* CLK */
++	RCAR_GP_PIN(3, 8),
++};
++static const unsigned int canfd_clk_b_mux[] = {
++	CANFD_CLK_B_MARK,
++};
++
++/* - CANFD1 ----------------------------------------------------------------- */
++static const unsigned int canfd1_data_pins[] = {
++	/* TX, RX */
++	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
++};
++static const unsigned int canfd1_data_mux[] = {
++	CANFD1_TX_MARK, CANFD1_RX_MARK,
++};
++
++/* - DU --------------------------------------------------------------------- */
++/* D_[1:0] ??? */
++static const unsigned int du_rgb666_pins[] = {
++	/* R[7:0] */
++	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
++	RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
++	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
++	/* G[7:0] */
++	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
++	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
++	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
++	/* B[7:0] */
++	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
++	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
++	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
++};
++static const unsigned int du_rgb666_mux[] = {
++	DU_DR7_MARK, DU_DR6_MARK,
++	DU_DR5_MARK, DU_DR4_MARK,
++	DU_DR3_MARK, DU_DR2_MARK,
++	DU_DG7_MARK, DU_DG6_MARK,
++	DU_DG5_MARK, DU_DG4_MARK,
++	DU_DG3_MARK, DU_DG2_MARK,
++	DU_DB7_MARK, DU_DB6_MARK,
++	DU_DB5_MARK, DU_DB4_MARK,
++	DU_DB3_MARK, DU_DB2_MARK,
++};
++static const unsigned int du_clk_out_0_pins[] = {
++	/* CLKOUT0 */
++	RCAR_GP_PIN(0, 18),
++};
++static const unsigned int du_clk_out_0_mux[] = {
++	DU_DOTCLKOUT_MARK,
++};
++static const unsigned int du_clk_out_1_pins[] = {
++	/* CLKOUT1 */
++	RCAR_GP_PIN(0, 18),		/* @@ */
++};
++static const unsigned int du_clk_out_1_mux[] = {
++	DU_DOTCLKOUT_MARK,
++};
++static const unsigned int du_sync_pins[] = {
++	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
++	RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
++};
++static const unsigned int du_sync_mux[] = {
++	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
++};
++static const unsigned int du_oddf_pins[] = {
++	/* EXDISP/EXODDF/EXCDE */
++	RCAR_GP_PIN(0, 21),
++};
++static const unsigned int du_oddf_mux[] = {
++	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
++};
++static const unsigned int du_cde_pins[] = {
++	/* CDE */
++	RCAR_GP_PIN(1, 22),
++};
++static const unsigned int du_cde_mux[] = {
++	DU_CDE_MARK,
++};
++static const unsigned int du_disp_pins[] = {
++	/* DISP */
++	RCAR_GP_PIN(1, 21),
++};
++static const unsigned int du_disp_mux[] = {
++	DU_DISP_MARK,
++};
++
++/* - HSCIF0 ----------------------------------------------------------------- */
++static const unsigned int hscif0_data_a_pins[] = {
++	/* HRX0_A, HTX0_A */
++	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
++};
++static const unsigned int hscif0_data_a_mux[] = {
++	HRX0_A_MARK, HTX0_A_MARK,
++};
++static const unsigned int hscif0_clk_a_pins[] = {
++	/* HSCK0_A */
++	RCAR_GP_PIN(0, 12),
++};
++static const unsigned int hscif0_clk_a_mux[] = {
++	HSCK0_A_MARK,
++};
++static const unsigned int hscif0_ctrl_a_pins[] = {
++	/* HRTS0#_A, HCTS0#_A */
++	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
++};
++static const unsigned int hscif0_ctrl_a_mux[] = {
++	HRTS0_N_A_MARK, HCTS0_N_A_MARK,
++};
++
++static const unsigned int hscif0_data_b_pins[] = {
++	/* HRX0_B, HTX0_B */
++	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
++};
++static const unsigned int hscif0_data_b_mux[] = {
++	HRX0_B_MARK, HTX0_B_MARK,
++};
++static const unsigned int hscif0_clk_b_pins[] = {
++	/* HSCK0_B */
++	RCAR_GP_PIN(0, 12),
++};
++static const unsigned int hscif0_clk_b_mux[] = {
++	HSCK0_B_MARK,
++};
++static const unsigned int hscif0_ctrl_b_pins[] = {
++	/* HRTS0#_B, HCTS0#_B */
++	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
++};
++static const unsigned int hscif0_ctrl_b_mux[] = {
++	HRTS0_N_B_MARK, HCTS0_N_B_MARK,
++};
++
++/* - HSCIF1 ----------------------------------------------------------------- */
++static const unsigned int hscif1_data_pins[] = {
++	/* HRX1, HTX1 */
++	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
++};
++static const unsigned int hscif1_data_mux[] = {
++	HRX1_MARK, HTX1_MARK,
++};
++static const unsigned int hscif1_clk_pins[] = {
++	/* HSCK1 */
++	RCAR_GP_PIN(2, 7),
++};
++static const unsigned int hscif1_clk_mux[] = {
++	HSCK1_MARK,
++};
++static const unsigned int hscif1_ctrl_pins[] = {
++	/* HRTS1#, HCTS1# */
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++};
++static const unsigned int hscif1_ctrl_mux[] = {
++	HRTS1_N_MARK, HCTS1_N_MARK,
++};
++
++/* - HSCIF2 ----------------------------------------------------------------- */
++static const unsigned int hscif2_data_pins[] = {
++	/* HRX2, HTX2 */
++	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
++};
++static const unsigned int hscif2_data_mux[] = {
++	HRX2_MARK, HTX2_MARK,
++};
++static const unsigned int hscif2_clk_pins[] = {
++	/* HSCK2 */
++	RCAR_GP_PIN(2, 12),
++};
++static const unsigned int hscif2_clk_mux[] = {
++	HSCK2_MARK,
++};
++static const unsigned int hscif2_ctrl_pins[] = {
++	/* HRTS2#, HCTS2# */
++	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
++};
++static const unsigned int hscif2_ctrl_mux[] = {
++	HRTS2_N_MARK, HCTS2_N_MARK,
++};
++
++/* - HSCIF3 ----------------------------------------------------------------- */
++static const unsigned int hscif3_data_pins[] = {
++	/* HRX3, HTX3 */
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
++};
++static const unsigned int hscif3_data_mux[] = {
++	HRX3_MARK, HTX3_MARK,
++};
++static const unsigned int hscif3_clk_pins[] = {
++	/* HSCK3 */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int hscif3_clk_mux[] = {
++	HSCK3_MARK,
++};
++static const unsigned int hscif3_ctrl_pins[] = {
++	/* HRTS3#, HCTS3# */
++	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
++};
++static const unsigned int hscif3_ctrl_mux[] = {
++	HRTS3_N_MARK, HCTS3_N_MARK,
++};
++
++/* - SCIF Clock ------------------------------------------------------------- */
++static const unsigned int scif_clk_a_pins[] = {
++	/* SCIF_CLK */
++	RCAR_GP_PIN(0, 10),
++};
++static const unsigned int scif_clk_a_mux[] = {
++	SCIF_CLK_A_MARK,
++};
++static const unsigned int scif_clk_b_pins[] = {
++	/* SCIF_CLK */
++	RCAR_GP_PIN(1, 25),
++};
++static const unsigned int scif_clk_b_mux[] = {
++	SCIF_CLK_B_MARK,
++};
++
++/* - I2C -------------------------------------------------------------------- */
++static const unsigned int i2c0_pins[] = {
++	/* SDA0, SCL0 */
++	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
++};
++static const unsigned int i2c0_mux[] = {
++	SDA0_MARK, SCL0_MARK,
++};
++static const unsigned int i2c1_pins[] = {
++	/* SDA1, SCL1 */
++	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
++};
++static const unsigned int i2c1_mux[] = {
++	SDA1_MARK, SCL1_MARK,
++};
++static const unsigned int i2c2_pins[] = {
++	/* SDA2, SCL2 */
++	RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
++};
++static const unsigned int i2c2_mux[] = {
++	SDA2_MARK, SCL2_MARK,
++};
++static const unsigned int i2c3_pins[] = {
++	/* SDA3, SCL3 */
++	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
++};
++static const unsigned int i2c3_mux[] = {
++	SDA3_MARK, SCL3_MARK,
++};
++static const unsigned int i2c4_pins[] = {
++	/* SDA4, SCL4 */
++	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
++};
++static const unsigned int i2c4_mux[] = {
++	SDA4_MARK, SCL4_MARK,
++};
++static const unsigned int i2c5_pins[] = {
++	/* SDA5, SCL5 */
++	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
++};
++static const unsigned int i2c5_mux[] = {
++	SDA5_MARK, SCL5_MARK,
++};
++
++/* - INTC-EX ---------------------------------------------------------------- */
++static const unsigned int intc_ex_irq0_pins[] = {
++	/* IRQ0 */
++	RCAR_GP_PIN(1, 0),
++};
++static const unsigned int intc_ex_irq0_mux[] = {
++	IRQ0_MARK,
++};
++static const unsigned int intc_ex_irq1_pins[] = {
++	/* IRQ1 */
++	RCAR_GP_PIN(0, 12),
++};
++static const unsigned int intc_ex_irq1_mux[] = {
++	IRQ1_MARK,
++};
++static const unsigned int intc_ex_irq2_pins[] = {
++	/* IRQ2 */
++	RCAR_GP_PIN(0, 13),
++};
++static const unsigned int intc_ex_irq2_mux[] = {
++	IRQ2_MARK,
++};
++static const unsigned int intc_ex_irq3_pins[] = {
++	/* IRQ3 */
++	RCAR_GP_PIN(0, 14),
++};
++static const unsigned int intc_ex_irq3_mux[] = {
++	IRQ3_MARK,
++};
++static const unsigned int intc_ex_irq4_pins[] = {
++	/* IRQ4 */
++	RCAR_GP_PIN(2, 17),
++};
++static const unsigned int intc_ex_irq4_mux[] = {
++	IRQ4_MARK,
++};
++static const unsigned int intc_ex_irq5_pins[] = {
++	/* IRQ5 */
++	RCAR_GP_PIN(2, 18),
++};
++static const unsigned int intc_ex_irq5_mux[] = {
++	IRQ5_MARK,
++};
++
++/* - MSIOF0 ----------------------------------------------------------------- */
++static const unsigned int msiof0_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(2, 21),
++};
++static const unsigned int msiof0_clk_mux[] = {
++	MSIOF0_SCK_MARK,
++};
++static const unsigned int msiof0_sync_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(2, 22),
++};
++static const unsigned int msiof0_sync_mux[] = {
++	MSIOF0_SYNC_MARK,
++};
++static const unsigned int msiof0_ss1_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(2, 23),
++};
++static const unsigned int msiof0_ss1_mux[] = {
++	MSIOF0_SS1_MARK,
++};
++static const unsigned int msiof0_ss2_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(2, 24),
++};
++static const unsigned int msiof0_ss2_mux[] = {
++	MSIOF0_SS2_MARK,
++};
++static const unsigned int msiof0_txd_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(2, 20),
++};
++static const unsigned int msiof0_txd_mux[] = {
++	MSIOF0_TXD_MARK,
++};
++static const unsigned int msiof0_rxd_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(2, 19),
++};
++static const unsigned int msiof0_rxd_mux[] = {
++	MSIOF0_RXD_MARK,
++};
++
++/* - MSIOF1 ----------------------------------------------------------------- */
++static const unsigned int msiof1_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(3, 2),
++};
++static const unsigned int msiof1_clk_mux[] = {
++	MSIOF1_SCK_MARK,
++};
++static const unsigned int msiof1_sync_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(3, 3),
++};
++static const unsigned int msiof1_sync_mux[] = {
++	MSIOF1_SYNC_MARK,
++};
++static const unsigned int msiof1_ss1_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(3, 4),
++};
++static const unsigned int msiof1_ss1_mux[] = {
++	MSIOF1_SS1_MARK,
++};
++static const unsigned int msiof1_ss2_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(3, 5),
++};
++static const unsigned int msiof1_ss2_mux[] = {
++	MSIOF1_SS2_MARK,
++};
++static const unsigned int msiof1_txd_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(3, 1),
++};
++static const unsigned int msiof1_txd_mux[] = {
++	MSIOF1_TXD_MARK,
++};
++static const unsigned int msiof1_rxd_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(3, 0),
++};
++static const unsigned int msiof1_rxd_mux[] = {
++	MSIOF1_RXD_MARK,
++};
++
++/* - MSIOF2 ----------------------------------------------------------------- */
++static const unsigned int msiof2_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int msiof2_clk_mux[] = {
++	MSIOF2_SCK_MARK,
++};
++static const unsigned int msiof2_sync_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(2, 3),
++};
++static const unsigned int msiof2_sync_mux[] = {
++	MSIOF2_SYNC_MARK,
++};
++static const unsigned int msiof2_ss1_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(2, 4),
++};
++static const unsigned int msiof2_ss1_mux[] = {
++	MSIOF2_SS1_MARK,
++};
++static const unsigned int msiof2_ss2_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(2, 5),
++};
++static const unsigned int msiof2_ss2_mux[] = {
++	MSIOF2_SS2_MARK,
++};
++static const unsigned int msiof2_txd_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(2, 2),
++};
++static const unsigned int msiof2_txd_mux[] = {
++	MSIOF2_TXD_MARK,
++};
++static const unsigned int msiof2_rxd_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(2, 1),
++};
++static const unsigned int msiof2_rxd_mux[] = {
++	MSIOF2_RXD_MARK,
++};
++
++/* - MSIOF3 ----------------------------------------------------------------- */
++static const unsigned int msiof3_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(0, 20),
++};
++static const unsigned int msiof3_clk_mux[] = {
++	MSIOF3_SCK_MARK,
++};
++static const unsigned int msiof3_sync_pins[] = {
++	/* SYNC */
++	RCAR_GP_PIN(0, 21),
++};
++static const unsigned int msiof3_sync_mux[] = {
++	MSIOF3_SYNC_MARK,
++};
++static const unsigned int msiof3_ss1_pins[] = {
++	/* SS1 */
++	RCAR_GP_PIN(0, 18),
++};
++static const unsigned int msiof3_ss1_mux[] = {
++	MSIOF3_SS1_MARK,
++};
++static const unsigned int msiof3_ss2_pins[] = {
++	/* SS2 */
++	RCAR_GP_PIN(0, 19),
++};
++static const unsigned int msiof3_ss2_mux[] = {
++	MSIOF3_SS2_MARK,
++};
++static const unsigned int msiof3_txd_pins[] = {
++	/* TXD */
++	RCAR_GP_PIN(0, 17),
++};
++static const unsigned int msiof3_txd_mux[] = {
++	MSIOF3_TXD_MARK,
++};
++static const unsigned int msiof3_rxd_pins[] = {
++	/* RXD */
++	RCAR_GP_PIN(0, 16),
++};
++static const unsigned int msiof3_rxd_mux[] = {
++	MSIOF3_RXD_MARK,
++};
++
++/* - TPU ------------------------------------------------------------------- */
++static const unsigned int tpu_to0_pins[] = {
++	/* TPU0TO0 */
++	RCAR_GP_PIN(1, 19),
++};
++static const unsigned int tpu_to0_mux[] = {
++	TPU0TO0_MARK,
++};
++static const unsigned int tpu_to1_pins[] = {
++	/* TPU0TO1 */
++	RCAR_GP_PIN(1, 20),
++};
++static const unsigned int tpu_to1_mux[] = {
++	TPU0TO1_MARK,
++};
++static const unsigned int tpu_to2_pins[] = {
++	/* TPU0TO2 */
++	RCAR_GP_PIN(4, 2),
++};
++static const unsigned int tpu_to2_mux[] = {
++	TPU0TO2_MARK,
++};
++static const unsigned int tpu_to3_pins[] = {
++	/* TPU0TO3 */
++	RCAR_GP_PIN(4, 3),
++};
++static const unsigned int tpu_to3_mux[] = {
++	TPU0TO3_MARK,
++};
++
++/* - PWM0 ------------------------------------------------------------------- */
++static const unsigned int pwm0_a_pins[] = {
++	/* PWM0 */
++	RCAR_GP_PIN(0, 15),
++};
++static const unsigned int pwm0_a_mux[] = {
++	PWM0_A_MARK,
++};
++static const unsigned int pwm0_b_pins[] = {
++	/* PWM0 */
++	RCAR_GP_PIN(1, 21),
++};
++static const unsigned int pwm0_b_mux[] = {
++	PWM0_B_MARK,
++};
++
++/* - PWM1 ------------------------------------------------------------------- */
++static const unsigned int pwm1_a_pins[] = {
++	/* PWM1 */
++	RCAR_GP_PIN(2, 13),
++};
++static const unsigned int pwm1_a_mux[] = {
++	PWM1_A_MARK,
++};
++static const unsigned int pwm1_b_pins[] = {
++	/* PWM1 */
++	RCAR_GP_PIN(1, 22),
++};
++static const unsigned int pwm1_b_mux[] = {
++	PWM1_B_MARK,
++};
++
++/* - PWM2 ------------------------------------------------------------------- */
++static const unsigned int pwm2_a_pins[] = {
++	/* PWM2 */
++	RCAR_GP_PIN(2, 14),
++};
++static const unsigned int pwm2_a_mux[] = {
++	PWM2_A_MARK,
++};
++static const unsigned int pwm2_b_pins[] = {
++	/* PWM2 */
++	RCAR_GP_PIN(1, 23),
++};
++static const unsigned int pwm2_b_mux[] = {
++	PWM2_B_MARK,
++};
++
++/* - PWM3 ------------------------------------------------------------------- */
++static const unsigned int pwm3_a_pins[] = {
++	/* PWM3 */
++	RCAR_GP_PIN(2, 15),
++};
++static const unsigned int pwm3_a_mux[] = {
++	PWM3_A_MARK,
++};
++static const unsigned int pwm3_b_pins[] = {
++	/* PWM3 */
++	RCAR_GP_PIN(1, 24),
++};
++static const unsigned int pwm3_b_mux[] = {
++	PWM3_B_MARK,
++};
++
++/* - PWM4 ------------------------------------------------------------------- */
++static const unsigned int pwm4_a_pins[] = {
++	/* PWM4 */
++	RCAR_GP_PIN(2, 16),
++};
++static const unsigned int pwm4_a_mux[] = {
++	PWM4_A_MARK,
++};
++static const unsigned int pwm4_b_pins[] = {
++	/* PWM4 */
++	RCAR_GP_PIN(1, 25),
++};
++static const unsigned int pwm4_b_mux[] = {
++	PWM4_B_MARK,
++};
++
++/* - SCIF0 ------------------------------------------------------------------ */
++static const unsigned int scif0_data_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
++};
++static const unsigned int scif0_data_mux[] = {
++	RX0_MARK, TX0_MARK,
++};
++static const unsigned int scif0_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(4, 1),
++};
++static const unsigned int scif0_clk_mux[] = {
++	SCK0_MARK,
++};
++static const unsigned int scif0_ctrl_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
++};
++static const unsigned int scif0_ctrl_mux[] = {
++	RTS0_N_TANS_MARK, CTS0_N_MARK,
++};
++
++/* - SCIF1 ------------------------------------------------------------------ */
++static const unsigned int scif1_data_a_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++};
++static const unsigned int scif1_data_a_mux[] = {
++	RX1_A_MARK, TX1_A_MARK,
++};
++static const unsigned int scif1_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(2, 5),
++};
++static const unsigned int scif1_clk_mux[] = {
++	SCK1_MARK,
++};
++static const unsigned int scif1_ctrl_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
++};
++static const unsigned int scif1_ctrl_mux[] = {
++	RTS1_N_TANS_MARK, CTS1_N_MARK,
++};
++static const unsigned int scif1_data_b_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
++};
++static const unsigned int scif1_data_b_mux[] = {
++	RX1_B_MARK, TX1_B_MARK,
++};
++
++/* - SCIF3 ------------------------------------------------------------------ */
++static const unsigned int scif3_data_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
++};
++static const unsigned int scif3_data_mux[] = {
++	RX3_MARK, TX3_MARK,
++};
++static const unsigned int scif3_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int scif3_clk_mux[] = {
++	SCK3_MARK,
++};
++static const unsigned int scif3_ctrl_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
++};
++static const unsigned int scif3_ctrl_mux[] = {
++	RTS3_N_TANS_MARK, CTS3_N_MARK,
++};
++
++/* - SCIF4 ------------------------------------------------------------------ */
++static const unsigned int scif4_data_pins[] = {
++	/* RX, TX */
++	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
++};
++static const unsigned int scif4_data_mux[] = {
++	RX4_MARK, TX4_MARK,
++};
++static const unsigned int scif4_clk_pins[] = {
++	/* SCK */
++	RCAR_GP_PIN(0, 0),
++};
++static const unsigned int scif4_clk_mux[] = {
++	SCK4_MARK,
++};
++static const unsigned int scif4_ctrl_pins[] = {
++	/* RTS, CTS */
++	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
++};
++static const unsigned int scif4_ctrl_mux[] = {
++	RTS4_N_TANS_MARK, CTS4_N_MARK,
++};
++
++/* - MMC -------------------------------------------------------------------- */
++static const unsigned int mmc_data1_pins[] = {
++	/* D0 */
++	RCAR_GP_PIN(3, 8),
++};
++static const unsigned int mmc_data1_mux[] = {
++	MMC_D0_MARK,
++};
++static const unsigned int mmc_data4_pins[] = {
++	/* D[0:3] */
++	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++};
++static const unsigned int mmc_data4_mux[] = {
++	MMC_D0_MARK, MMC_D1_MARK,
++	MMC_D2_MARK, MMC_D3_MARK,
++};
++static const unsigned int mmc_data8_pins[] = {
++	/* D[0:7] */
++	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
++	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
++};
++static const unsigned int mmc_data8_mux[] = {
++	MMC_D0_MARK, MMC_D1_MARK,
++	MMC_D2_MARK, MMC_D3_MARK,
++	MMC_D4_MARK, MMC_D5_MARK,
++	MMC_D6_MARK, MMC_D7_MARK,
++};
++static const unsigned int mmc_ctrl_pins[] = {
++	/* CLK, CMD */
++	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
++};
++static const unsigned int mmc_ctrl_mux[] = {
++	MMC_CLK_MARK, MMC_CMD_MARK,
++};
++static const unsigned int mmc_cd_pins[] = {
++	/* CD */
++	RCAR_GP_PIN(3, 5),
++};
++static const unsigned int mmc_cd_mux[] = {
++	MMC_CD_MARK,
++};
++static const unsigned int mmc_wp_pins[] = {
++	/* WP */
++	RCAR_GP_PIN(3, 4),
++};
++static const unsigned int mmc_wp_mux[] = {
++	MMC_WP_MARK,
++};
++static const unsigned int mmc_ds_pins[] = {
++	/* DS */
++	RCAR_GP_PIN(3, 6),
++};
++static const unsigned int mmc_ds_mux[] = {
++	MMC_DS_MARK,
++};
++
++/* - TMU -------------------------------------------------------------------- */
++static const unsigned int tmu_tclk1_a_pins[] = {
++	/* TCLK1 */
++	RCAR_GP_PIN(3, 13),
++};
++static const unsigned int tmu_tclk1_a_mux[] = {
++	TCLK1_A_MARK,
++};
++static const unsigned int tmu_tclk1_b_pins[] = {
++	/* TCLK1 */
++	RCAR_GP_PIN(1, 23),
++};
++static const unsigned int tmu_tclk1_b_mux[] = {
++	TCLK1_B_MARK,
++};
++static const unsigned int tmu_tclk2_a_pins[] = {
++	/* TCLK2 */
++	RCAR_GP_PIN(3, 14),
++};
++static const unsigned int tmu_tclk2_a_mux[] = {
++	TCLK2_A_MARK,
++};
++static const unsigned int tmu_tclk2_b_pins[] = {
++	/* TCLK2 */
++	RCAR_GP_PIN(1, 24),
++};
++static const unsigned int tmu_tclk2_b_mux[] = {
++	TCLK2_B_MARK,
++};
++
++/* - VIN0 ------------------------------------------------------------------- */
++static const unsigned int vin0_data8_pins[] = {
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
++};
++static const unsigned int vin0_data8_mux[] = {
++	VI0_DATA0_MARK, VI0_DATA1_MARK,
++	VI0_DATA2_MARK, VI0_DATA3_MARK,
++	VI0_DATA4_MARK, VI0_DATA5_MARK,
++	VI0_DATA6_MARK, VI0_DATA7_MARK,
++};
++static const unsigned int vin0_data10_pins[] = {
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
++	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
++};
++static const unsigned int vin0_data10_mux[] = {
++	VI0_DATA0_MARK, VI0_DATA1_MARK,
++	VI0_DATA2_MARK, VI0_DATA3_MARK,
++	VI0_DATA4_MARK, VI0_DATA5_MARK,
++	VI0_DATA6_MARK, VI0_DATA7_MARK,
++	VI0_DATA8_MARK,  VI0_DATA9_MARK,
++};
++static const unsigned int vin0_data12_pins[] = {
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
++	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
++	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
++};
++static const unsigned int vin0_data12_mux[] = {
++	VI0_DATA0_MARK, VI0_DATA1_MARK,
++	VI0_DATA2_MARK, VI0_DATA3_MARK,
++	VI0_DATA4_MARK, VI0_DATA5_MARK,
++	VI0_DATA6_MARK, VI0_DATA7_MARK,
++	VI0_DATA8_MARK,  VI0_DATA9_MARK,
++	VI0_DATA10_MARK, VI0_DATA11_MARK,
++};
++static const unsigned int vin0_data16_pins[] = {
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
++	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
++	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
++	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
++	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
++};
++static const unsigned int vin0_data16_mux[] = {
++	VI0_DATA0_MARK, VI0_DATA1_MARK,
++	VI0_DATA2_MARK, VI0_DATA3_MARK,
++	VI0_DATA4_MARK, VI0_DATA5_MARK,
++	VI0_DATA6_MARK, VI0_DATA7_MARK,
++	VI0_DATA8_MARK,  VI0_DATA9_MARK,
++	VI0_DATA10_MARK, VI0_DATA11_MARK,
++	VI0_DATA12_MARK, VI0_DATA13_MARK,
++	VI0_DATA14_MARK, VI0_DATA15_MARK,
++};
++static const unsigned int vin0_data20_pins[] = {
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
++	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
++	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
++	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
++	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
++	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
++	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
++};
++static const unsigned int vin0_data20_mux[] = {
++	VI0_DATA0_MARK, VI0_DATA1_MARK,
++	VI0_DATA2_MARK, VI0_DATA3_MARK,
++	VI0_DATA4_MARK, VI0_DATA5_MARK,
++	VI0_DATA6_MARK, VI0_DATA7_MARK,
++	VI0_DATA8_MARK,  VI0_DATA9_MARK,
++	VI0_DATA10_MARK, VI0_DATA11_MARK,
++	VI0_DATA12_MARK, VI0_DATA13_MARK,
++	VI0_DATA14_MARK, VI0_DATA15_MARK,
++	VI0_DATA16_MARK, VI0_DATA17_MARK,
++	VI0_DATA18_MARK, VI0_DATA19_MARK,
++};
++static const unsigned int vin0_data24_pins[] = {
++	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
++	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
++	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
++	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
++	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
++	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
++	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
++	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
++	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
++	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
++	RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
++	RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
++};
++static const unsigned int vin0_data24_mux[] = {
++	VI0_DATA0_MARK, VI0_DATA1_MARK,
++	VI0_DATA2_MARK, VI0_DATA3_MARK,
++	VI0_DATA4_MARK, VI0_DATA5_MARK,
++	VI0_DATA6_MARK, VI0_DATA7_MARK,
++	VI0_DATA8_MARK,  VI0_DATA9_MARK,
++	VI0_DATA10_MARK, VI0_DATA11_MARK,
++	VI0_DATA12_MARK, VI0_DATA13_MARK,
++	VI0_DATA14_MARK, VI0_DATA15_MARK,
++	VI0_DATA16_MARK, VI0_DATA17_MARK,
++	VI0_DATA18_MARK, VI0_DATA19_MARK,
++	VI0_DATA20_MARK, VI0_DATA21_MARK,
++	VI0_DATA22_MARK, VI0_DATA23_MARK,
++};
++static const unsigned int vin0_sync_pins[] = {
++	/* VSYNC_N, HSYNC_N */
++	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
++};
++static const unsigned int vin0_sync_mux[] = {
++	VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
++};
++static const unsigned int vin0_field_pins[] = {
++	/* FIELD */
++	RCAR_GP_PIN(2, 16),
++};
++static const unsigned int vin0_field_mux[] = {
++	VI0_FIELD_MARK,
++};
++static const unsigned int vin0_clkenb_pins[] = {
++	/* CLKENB */
++	RCAR_GP_PIN(2, 1),
++};
++static const unsigned int vin0_clkenb_mux[] = {
++	VI0_CLKENB_MARK,
++};
++static const unsigned int vin0_clk_pins[] = {
++	/* CLK */
++	RCAR_GP_PIN(2, 0),
++};
++static const unsigned int vin0_clk_mux[] = {
++	VI0_CLK_MARK,
++};
++/* - VIN1 ------------------------------------------------------------------- */
++static const unsigned int vin1_data8_pins[] = {
++	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
++	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
++	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++};
++static const unsigned int vin1_data8_mux[] = {
++	VI1_DATA0_MARK, VI1_DATA1_MARK,
++	VI1_DATA2_MARK, VI1_DATA3_MARK,
++	VI1_DATA4_MARK, VI1_DATA5_MARK,
++	VI1_DATA6_MARK, VI1_DATA7_MARK,
++};
++static const unsigned int vin1_data10_pins[] = {
++	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
++	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
++	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
++};
++static const unsigned int vin1_data10_mux[] = {
++	VI1_DATA0_MARK, VI1_DATA1_MARK,
++	VI1_DATA2_MARK, VI1_DATA3_MARK,
++	VI1_DATA4_MARK, VI1_DATA5_MARK,
++	VI1_DATA6_MARK, VI1_DATA7_MARK,
++	VI1_DATA8_MARK,  VI1_DATA9_MARK,
++};
++static const unsigned int vin1_data12_pins[] = {
++	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
++	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
++	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
++	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
++	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
++};
++static const unsigned int vin1_data12_mux[] = {
++	VI1_DATA0_MARK, VI1_DATA1_MARK,
++	VI1_DATA2_MARK, VI1_DATA3_MARK,
++	VI1_DATA4_MARK, VI1_DATA5_MARK,
++	VI1_DATA6_MARK, VI1_DATA7_MARK,
++	VI1_DATA8_MARK,  VI1_DATA9_MARK,
++	VI1_DATA10_MARK, VI1_DATA11_MARK,
++};
++static const unsigned int vin1_sync_pins[] = {
++	/* VSYNC_N, HSYNC_N */
++	 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
++};
++static const unsigned int vin1_sync_mux[] = {
++	VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
++};
++static const unsigned int vin1_field_pins[] = {
++	/* FIELD */
++	RCAR_GP_PIN(3, 16),
++};
++static const unsigned int vin1_field_mux[] = {
++	VI1_FIELD_MARK,
++};
++static const unsigned int vin1_clkenb_pins[] = {
++	/* CLKENB */
++	RCAR_GP_PIN(3, 1),
++};
++static const unsigned int vin1_clkenb_mux[] = {
++	VI1_CLKENB_MARK,
++};
++static const unsigned int vin1_clk_pins[] = {
++	/* CLK */
++	RCAR_GP_PIN(3, 0),
++};
++static const unsigned int vin1_clk_mux[] = {
++	VI1_CLK_MARK,
++};
++
++static const struct sh_pfc_pin_group pinmux_groups[] = {
++	SH_PFC_PIN_GROUP(avb_rx_ctrl),
++	SH_PFC_PIN_GROUP(avb_rxc),
++	SH_PFC_PIN_GROUP(avb_rd0),
++	SH_PFC_PIN_GROUP(avb_rd1),
++	SH_PFC_PIN_GROUP(avb_rd2),
++	SH_PFC_PIN_GROUP(avb_rd3),
++	SH_PFC_PIN_GROUP(avb_rd4),
++	SH_PFC_PIN_GROUP(avb_tx_ctrl),
++	SH_PFC_PIN_GROUP(avb_txc),
++	SH_PFC_PIN_GROUP(avb_td0),
++	SH_PFC_PIN_GROUP(avb_td1),
++	SH_PFC_PIN_GROUP(avb_td2),
++	SH_PFC_PIN_GROUP(avb_td3),
++	SH_PFC_PIN_GROUP(avb_td4),
++	SH_PFC_PIN_GROUP(avb_txcrefclk),
++	SH_PFC_PIN_GROUP(avb_mdio),
++	SH_PFC_PIN_GROUP(avb_mdc),
++	SH_PFC_PIN_GROUP(avb_magic),
++	SH_PFC_PIN_GROUP(avb_phy_int),
++	SH_PFC_PIN_GROUP(avb_link),
++	SH_PFC_PIN_GROUP(avb_avtp_match),
++	SH_PFC_PIN_GROUP(avb_avtp_capture),
++	SH_PFC_PIN_GROUP(avb_avtp_pps),
++	SH_PFC_PIN_GROUP(gether_rx_ctrl),
++	SH_PFC_PIN_GROUP(gether_rxc),
++	SH_PFC_PIN_GROUP(gether_rd0),
++	SH_PFC_PIN_GROUP(gether_rd1),
++	SH_PFC_PIN_GROUP(gether_rd2),
++	SH_PFC_PIN_GROUP(gether_rd3),
++	SH_PFC_PIN_GROUP(gether_rd4),
++	SH_PFC_PIN_GROUP(gether_tx_ctrl),
++	SH_PFC_PIN_GROUP(gether_txc),
++	SH_PFC_PIN_GROUP(gether_td0),
++	SH_PFC_PIN_GROUP(gether_td1),
++	SH_PFC_PIN_GROUP(gether_td2),
++	SH_PFC_PIN_GROUP(gether_td3),
++	SH_PFC_PIN_GROUP(gether_td4),
++	SH_PFC_PIN_GROUP(gether_txcrefclk),
++	SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
++	SH_PFC_PIN_GROUP(gether_mdio_a),
++	SH_PFC_PIN_GROUP(gether_mdio_b),
++	SH_PFC_PIN_GROUP(gether_mdc_a),
++	SH_PFC_PIN_GROUP(gether_mdc_b),
++	SH_PFC_PIN_GROUP(gether_magic),
++	SH_PFC_PIN_GROUP(gether_phy_int_a),
++	SH_PFC_PIN_GROUP(gether_phy_int_b),
++	SH_PFC_PIN_GROUP(gether_link_a),
++	SH_PFC_PIN_GROUP(gether_link_b),
++	SH_PFC_PIN_GROUP(gether_rmii),
++	SH_PFC_PIN_GROUP(canfd0_data_a),
++	SH_PFC_PIN_GROUP(canfd_clk_a),
++	SH_PFC_PIN_GROUP(canfd0_data_b),
++	SH_PFC_PIN_GROUP(canfd_clk_b),
++	SH_PFC_PIN_GROUP(canfd1_data),
++	SH_PFC_PIN_GROUP(du_rgb666),
++	SH_PFC_PIN_GROUP(du_clk_out_0),
++	SH_PFC_PIN_GROUP(du_clk_out_1),
++	SH_PFC_PIN_GROUP(du_sync),
++	SH_PFC_PIN_GROUP(du_oddf),
++	SH_PFC_PIN_GROUP(du_cde),
++	SH_PFC_PIN_GROUP(du_disp),
++	SH_PFC_PIN_GROUP(hscif0_data_a),
++	SH_PFC_PIN_GROUP(hscif0_clk_a),
++	SH_PFC_PIN_GROUP(hscif0_ctrl_a),
++	SH_PFC_PIN_GROUP(hscif0_data_b),
++	SH_PFC_PIN_GROUP(hscif0_clk_b),
++	SH_PFC_PIN_GROUP(hscif0_ctrl_b),
++	SH_PFC_PIN_GROUP(hscif1_data),
++	SH_PFC_PIN_GROUP(hscif1_clk),
++	SH_PFC_PIN_GROUP(hscif1_ctrl),
++	SH_PFC_PIN_GROUP(hscif2_data),
++	SH_PFC_PIN_GROUP(hscif2_clk),
++	SH_PFC_PIN_GROUP(hscif2_ctrl),
++	SH_PFC_PIN_GROUP(hscif3_data),
++	SH_PFC_PIN_GROUP(hscif3_clk),
++	SH_PFC_PIN_GROUP(hscif3_ctrl),
++	SH_PFC_PIN_GROUP(scif_clk_a),
++	SH_PFC_PIN_GROUP(scif_clk_b),
++	SH_PFC_PIN_GROUP(i2c0),
++	SH_PFC_PIN_GROUP(i2c1),
++	SH_PFC_PIN_GROUP(i2c2),
++	SH_PFC_PIN_GROUP(i2c3),
++	SH_PFC_PIN_GROUP(i2c4),
++	SH_PFC_PIN_GROUP(i2c5),
++	SH_PFC_PIN_GROUP(intc_ex_irq0),
++	SH_PFC_PIN_GROUP(intc_ex_irq1),
++	SH_PFC_PIN_GROUP(intc_ex_irq2),
++	SH_PFC_PIN_GROUP(intc_ex_irq3),
++	SH_PFC_PIN_GROUP(intc_ex_irq4),
++	SH_PFC_PIN_GROUP(intc_ex_irq5),
++	SH_PFC_PIN_GROUP(msiof0_clk),
++	SH_PFC_PIN_GROUP(msiof0_sync),
++	SH_PFC_PIN_GROUP(msiof0_ss1),
++	SH_PFC_PIN_GROUP(msiof0_ss2),
++	SH_PFC_PIN_GROUP(msiof0_txd),
++	SH_PFC_PIN_GROUP(msiof0_rxd),
++	SH_PFC_PIN_GROUP(msiof1_clk),
++	SH_PFC_PIN_GROUP(msiof1_sync),
++	SH_PFC_PIN_GROUP(msiof1_ss1),
++	SH_PFC_PIN_GROUP(msiof1_ss2),
++	SH_PFC_PIN_GROUP(msiof1_txd),
++	SH_PFC_PIN_GROUP(msiof1_rxd),
++	SH_PFC_PIN_GROUP(msiof2_clk),
++	SH_PFC_PIN_GROUP(msiof2_sync),
++	SH_PFC_PIN_GROUP(msiof2_ss1),
++	SH_PFC_PIN_GROUP(msiof2_ss2),
++	SH_PFC_PIN_GROUP(msiof2_txd),
++	SH_PFC_PIN_GROUP(msiof2_rxd),
++	SH_PFC_PIN_GROUP(msiof3_clk),
++	SH_PFC_PIN_GROUP(msiof3_sync),
++	SH_PFC_PIN_GROUP(msiof3_ss1),
++	SH_PFC_PIN_GROUP(msiof3_ss2),
++	SH_PFC_PIN_GROUP(msiof3_txd),
++	SH_PFC_PIN_GROUP(msiof3_rxd),
++	SH_PFC_PIN_GROUP(tpu_to0),
++	SH_PFC_PIN_GROUP(tpu_to1),
++	SH_PFC_PIN_GROUP(tpu_to2),
++	SH_PFC_PIN_GROUP(tpu_to3),
++	SH_PFC_PIN_GROUP(pwm0_a),
++	SH_PFC_PIN_GROUP(pwm0_b),
++	SH_PFC_PIN_GROUP(pwm1_a),
++	SH_PFC_PIN_GROUP(pwm1_b),
++	SH_PFC_PIN_GROUP(pwm2_a),
++	SH_PFC_PIN_GROUP(pwm2_b),
++	SH_PFC_PIN_GROUP(pwm3_a),
++	SH_PFC_PIN_GROUP(pwm3_b),
++	SH_PFC_PIN_GROUP(pwm4_a),
++	SH_PFC_PIN_GROUP(pwm4_b),
++	SH_PFC_PIN_GROUP(scif0_data),
++	SH_PFC_PIN_GROUP(scif0_clk),
++	SH_PFC_PIN_GROUP(scif0_ctrl),
++	SH_PFC_PIN_GROUP(scif1_data_a),
++	SH_PFC_PIN_GROUP(scif1_clk),
++	SH_PFC_PIN_GROUP(scif1_ctrl),
++	SH_PFC_PIN_GROUP(scif1_data_b),
++	SH_PFC_PIN_GROUP(scif3_data),
++	SH_PFC_PIN_GROUP(scif3_clk),
++	SH_PFC_PIN_GROUP(scif3_ctrl),
++	SH_PFC_PIN_GROUP(scif4_data),
++	SH_PFC_PIN_GROUP(scif4_clk),
++	SH_PFC_PIN_GROUP(scif4_ctrl),
++	SH_PFC_PIN_GROUP(mmc_data1),
++	SH_PFC_PIN_GROUP(mmc_data4),
++	SH_PFC_PIN_GROUP(mmc_data8),
++	SH_PFC_PIN_GROUP(mmc_ctrl),
++	SH_PFC_PIN_GROUP(mmc_cd),
++	SH_PFC_PIN_GROUP(mmc_wp),
++	SH_PFC_PIN_GROUP(mmc_ds),
++	SH_PFC_PIN_GROUP(tmu_tclk1_a),
++	SH_PFC_PIN_GROUP(tmu_tclk1_b),
++	SH_PFC_PIN_GROUP(tmu_tclk2_a),
++	SH_PFC_PIN_GROUP(tmu_tclk2_b),
++	SH_PFC_PIN_GROUP(vin0_data8),
++	SH_PFC_PIN_GROUP(vin0_data10),
++	SH_PFC_PIN_GROUP(vin0_data12),
++	SH_PFC_PIN_GROUP(vin0_data16),
++	SH_PFC_PIN_GROUP(vin0_data20),
++	SH_PFC_PIN_GROUP(vin0_data24),
++	SH_PFC_PIN_GROUP(vin0_sync),
++	SH_PFC_PIN_GROUP(vin0_field),
++	SH_PFC_PIN_GROUP(vin0_clkenb),
++	SH_PFC_PIN_GROUP(vin0_clk),
++	SH_PFC_PIN_GROUP(vin1_data8),
++	SH_PFC_PIN_GROUP(vin1_data10),
++	SH_PFC_PIN_GROUP(vin1_data12),
++	SH_PFC_PIN_GROUP(vin1_sync),
++	SH_PFC_PIN_GROUP(vin1_field),
++	SH_PFC_PIN_GROUP(vin1_clkenb),
++	SH_PFC_PIN_GROUP(vin1_clk),
++};
++
++static const char * const avb_groups[] = {
++	"avb_rx_ctrl",
++	"avb_rxc",
++	"avb_rd1",
++	"avb_rd4",
++	"avb_tx_ctrl",
++	"avb_txc",
++	"avb_td1",
++	"avb_td4",
++	"avb_txcrefclk",
++	"avb_mdio",
++	"avb_mdc",
++	"avb_magic",
++	"avb_phy_int",
++	"avb_link",
++	"avb_avtp_match",
++	"avb_avtp_capture",
++	"avb_avtp_pps",
++};
++
++static const char * const gether_groups[] = {
++	"gether_rx_ctrl",
++	"gether_rxc",
++	"gether_rd1",
++	"gether_rd4",
++	"gether_tx_ctrl",
++	"gether_txc",
++	"gether_td1",
++	"gether_td4",
++	"gether_txcrefclk",
++	"gether_txcrefclk_mega",
++	"gether_mdio_a",
++	"gether_mdc_a",
++	"gether_mdio_b",
++	"gether_mdc_b",
++	"gether_magic",
++	"gether_phy_int_a",
++	"gether_link_a",
++	"gether_phy_int_b",
++	"gether_link_b",
++	"gether_rmii",
++};
++
++static const char * const canfd0_groups[] = {
++	"canfd0_data_a",
++	"canfd_clk_a",
++	"canfd0_data_b",
++	"canfd_clk_b",
++};
++
++static const char * const canfd1_groups[] = {
++	"canfd1_data",
++};
++
++static const char * const du_groups[] = {
++	"du_rgb666",
++	"du_clk_out_0",
++	"du_clk_out_1",
++	"du_sync",
++	"du_oddf",
++	"du_cde",
++	"du_disp",
++};
++
++static const char * const hscif0_groups[] = {
++	"hscif0_data_a",
++	"hscif0_clk_a",
++	"hscif0_ctrl_a",
++	"hscif0_data_b",
++	"hscif0_clk_b",
++	"hscif0_ctrl_b",
++};
++
++static const char * const hscif1_groups[] = {
++	"hscif1_data",
++	"hscif1_clk",
++	"hscif1_ctrl",
++};
++
++static const char * const hscif2_groups[] = {
++	"hscif2_data",
++	"hscif2_clk",
++	"hscif2_ctrl",
++};
++
++static const char * const hscif3_groups[] = {
++	"hscif3_data",
++	"hscif3_clk",
++	"hscif3_ctrl",
++};
++
++static const char * const scif_clk_groups[] = {
++	"scif_clk_a",
++	"scif_clk_b",
++};
++
++static const char * const i2c0_groups[] = {
++	"i2c0",
++};
++
++static const char * const i2c1_groups[] = {
++	"i2c1",
++};
++
++static const char * const i2c2_groups[] = {
++	"i2c2",
++};
++
++static const char * const i2c3_groups[] = {
++	"i2c3",
++};
++
++static const char * const i2c4_groups[] = {
++	"i2c4",
++};
++
++static const char * const i2c5_groups[] = {
++	"i2c5",
++};
++
++static const char * const intc_ex_groups[] = {
++	"intc_ex_irq0",
++	"intc_ex_irq1",
++	"intc_ex_irq2",
++	"intc_ex_irq3",
++	"intc_ex_irq4",
++	"intc_ex_irq5",
++};
++
++static const char * const msiof0_groups[] = {
++	"msiof0_clk",
++	"msiof0_sync",
++	"msiof0_ss1",
++	"msiof0_ss2",
++	"msiof0_txd",
++	"msiof0_rxd",
++};
++
++static const char * const msiof1_groups[] = {
++	"msiof1_clk",
++	"msiof1_sync",
++	"msiof1_ss1",
++	"msiof1_ss2",
++	"msiof1_txd",
++	"msiof1_rxd",
++};
++
++static const char * const msiof2_groups[] = {
++	"msiof2_clk",
++	"msiof2_sync",
++	"msiof2_ss1",
++	"msiof2_ss2",
++	"msiof2_txd",
++	"msiof2_rxd",
++};
++
++static const char * const msiof3_groups[] = {
++	"msiof3_clk",
++	"msiof3_sync",
++	"msiof3_ss1",
++	"msiof3_ss2",
++	"msiof3_txd",
++	"msiof3_rxd",
++};
++
++static const char * const tpu_groups[] = {
++	"tpu_to0",
++	"tpu_to1",
++	"tpu_to2",
++	"tpu_to3",
++};
++
++static const char * const pwm0_groups[] = {
++	"pwm0_a",
++	"pwm0_b",
++};
++
++static const char * const pwm1_groups[] = {
++	"pwm1_a",
++	"pwm1_b",
++};
++
++static const char * const pwm2_groups[] = {
++	"pwm2_a",
++	"pwm2_b",
++};
++
++static const char * const pwm3_groups[] = {
++	"pwm3_a",
++	"pwm3_b",
++};
++
++static const char * const pwm4_groups[] = {
++	"pwm4_a",
++	"pwm4_b",
++};
++
++static const char * const scif0_groups[] = {
++	"scif0_data",
++//	"scif0_clk",
++//	"scif0_ctrl",
++};
++
++static const char * const scif1_groups[] = {
++	"scif1_data_a",
++	"scif1_clk",
++	"scif1_ctrl",
++	"scif1_data_b",
++};
++
++static const char * const scif3_groups[] = {
++	"scif3_data",
++	"scif3_clk",
++	"scif3_ctrl",
++};
++
++static const char * const scif4_groups[] = {
++	"scif4_data",
++	"scif4_clk",
++	"scif4_ctrl",
++};
++
++static const char * const mmc_groups[] = {
++	"mmc_data1",
++	"mmc_data4",
++	"mmc_data8",
++	"mmc_ctrl",
++	"mmc_cd",
++	"mmc_wp",
++	"mmc_ds",
++};
++
++static const char * const tmu_groups[] = {
++	"tmu_tclk1_a",
++	"tmu_tclk1_b",
++	"tmu_tclk2_a",
++	"tmu_tclk2_b",
++};
++
++static const char * const vin0_groups[] = {
++	"vin0_data8",
++	"vin0_data10",
++	"vin0_data12",
++	"vin0_data16",
++	"vin0_data20",
++	"vin0_data24",
++	"vin0_sync",
++	"vin0_field",
++	"vin0_clkenb",
++	"vin0_clk",
++};
++
++static const char * const vin1_groups[] = {
++	"vin1_data8",
++	"vin1_data10",
++	"vin1_data12",
++	"vin1_sync",
++	"vin1_field",
++	"vin1_clkenb",
++	"vin1_clk",
++};
++
++static const struct sh_pfc_function pinmux_functions[] = {
++	SH_PFC_FUNCTION(avb),
++	SH_PFC_FUNCTION(gether),
++	SH_PFC_FUNCTION(canfd0),
++	SH_PFC_FUNCTION(canfd1),
++	SH_PFC_FUNCTION(du),
++	SH_PFC_FUNCTION(hscif0),
++	SH_PFC_FUNCTION(hscif1),
++	SH_PFC_FUNCTION(hscif2),
++	SH_PFC_FUNCTION(hscif3),
++	SH_PFC_FUNCTION(scif_clk),
++	SH_PFC_FUNCTION(i2c0),
++	SH_PFC_FUNCTION(i2c1),
++	SH_PFC_FUNCTION(i2c2),
++	SH_PFC_FUNCTION(i2c3),
++	SH_PFC_FUNCTION(i2c4),
++	SH_PFC_FUNCTION(i2c5),
++	SH_PFC_FUNCTION(intc_ex),
++	SH_PFC_FUNCTION(msiof0),
++	SH_PFC_FUNCTION(msiof1),
++	SH_PFC_FUNCTION(msiof2),
++	SH_PFC_FUNCTION(msiof3),
++	SH_PFC_FUNCTION(tpu),
++	SH_PFC_FUNCTION(pwm0),
++	SH_PFC_FUNCTION(pwm1),
++	SH_PFC_FUNCTION(pwm2),
++	SH_PFC_FUNCTION(pwm3),
++	SH_PFC_FUNCTION(pwm4),
++	SH_PFC_FUNCTION(scif0),
++	SH_PFC_FUNCTION(scif1),
++	SH_PFC_FUNCTION(scif3),
++	SH_PFC_FUNCTION(scif4),
++	SH_PFC_FUNCTION(mmc),
++	SH_PFC_FUNCTION(tmu),
++	SH_PFC_FUNCTION(vin0),
++	SH_PFC_FUNCTION(vin1),
++};
++
++static const struct pinmux_cfg_reg pinmux_config_regs[] = {
++#define F_(x, y)	FN_##y
++#define FM(x)		FN_##x
++	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_0_21_FN,	GPSR0_21,
++		GP_0_20_FN,	GPSR0_20,
++		GP_0_19_FN,	GPSR0_19,
++		GP_0_18_FN,	GPSR0_18,
++		GP_0_17_FN,	GPSR0_17,
++		GP_0_16_FN,	GPSR0_16,
++		GP_0_15_FN,	GPSR0_15,
++		GP_0_14_FN,	GPSR0_14,
++		GP_0_13_FN,	GPSR0_13,
++		GP_0_12_FN,	GPSR0_12,
++		GP_0_11_FN,	GPSR0_11,
++		GP_0_10_FN,	GPSR0_10,
++		GP_0_9_FN,	GPSR0_9,
++		GP_0_8_FN,	GPSR0_8,
++		GP_0_7_FN,	GPSR0_7,
++		GP_0_6_FN,	GPSR0_6,
++		GP_0_5_FN,	GPSR0_5,
++		GP_0_4_FN,	GPSR0_4,
++		GP_0_3_FN,	GPSR0_3,
++		GP_0_2_FN,	GPSR0_2,
++		GP_0_1_FN,	GPSR0_1,
++		GP_0_0_FN,	GPSR0_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_1_27_FN,	GPSR1_27,
++		GP_1_26_FN,	GPSR1_26,
++		GP_1_25_FN,	GPSR1_25,
++		GP_1_24_FN,	GPSR1_24,
++		GP_1_23_FN,	GPSR1_23,
++		GP_1_22_FN,	GPSR1_22,
++		GP_1_21_FN,	GPSR1_21,
++		GP_1_20_FN,	GPSR1_20,
++		GP_1_19_FN,	GPSR1_19,
++		GP_1_18_FN,	GPSR1_18,
++		GP_1_17_FN,	GPSR1_17,
++		GP_1_16_FN,	GPSR1_16,
++		GP_1_15_FN,	GPSR1_15,
++		GP_1_14_FN,	GPSR1_14,
++		GP_1_13_FN,	GPSR1_13,
++		GP_1_12_FN,	GPSR1_12,
++		GP_1_11_FN,	GPSR1_11,
++		GP_1_10_FN,	GPSR1_10,
++		GP_1_9_FN,	GPSR1_9,
++		GP_1_8_FN,	GPSR1_8,
++		GP_1_7_FN,	GPSR1_7,
++		GP_1_6_FN,	GPSR1_6,
++		GP_1_5_FN,	GPSR1_5,
++		GP_1_4_FN,	GPSR1_4,
++		GP_1_3_FN,	GPSR1_3,
++		GP_1_2_FN,	GPSR1_2,
++		GP_1_1_FN,	GPSR1_1,
++		GP_1_0_FN,	GPSR1_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
++		0, 0,
++		0, 0,
++		GP_2_29_FN,	GPSR2_29,
++		GP_2_28_FN,	GPSR2_28,
++		GP_2_27_FN,	GPSR2_27,
++		GP_2_26_FN,	GPSR2_26,
++		GP_2_25_FN,	GPSR2_25,
++		GP_2_24_FN,	GPSR2_24,
++		GP_2_23_FN,	GPSR2_23,
++		GP_2_22_FN,	GPSR2_22,
++		GP_2_21_FN,	GPSR2_21,
++		GP_2_20_FN,	GPSR2_20,
++		GP_2_19_FN,	GPSR2_19,
++		GP_2_18_FN,	GPSR2_18,
++		GP_2_17_FN,	GPSR2_17,
++		GP_2_16_FN,	GPSR2_16,
++		GP_2_15_FN,	GPSR2_15,
++		GP_2_14_FN,	GPSR2_14,
++		GP_2_13_FN,	GPSR2_13,
++		GP_2_12_FN,	GPSR2_12,
++		GP_2_11_FN,	GPSR2_11,
++		GP_2_10_FN,	GPSR2_10,
++		GP_2_9_FN,	GPSR2_9,
++		GP_2_8_FN,	GPSR2_8,
++		GP_2_7_FN,	GPSR2_7,
++		GP_2_6_FN,	GPSR2_6,
++		GP_2_5_FN,	GPSR2_5,
++		GP_2_4_FN,	GPSR2_4,
++		GP_2_3_FN,	GPSR2_3,
++		GP_2_2_FN,	GPSR2_2,
++		GP_2_1_FN,	GPSR2_1,
++		GP_2_0_FN,	GPSR2_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_3_16_FN,	GPSR3_16,
++		GP_3_15_FN,	GPSR3_15,
++		GP_3_14_FN,	GPSR3_14,
++		GP_3_13_FN,	GPSR3_13,
++		GP_3_12_FN,	GPSR3_12,
++		GP_3_11_FN,	GPSR3_11,
++		GP_3_10_FN,	GPSR3_10,
++		GP_3_9_FN,	GPSR3_9,
++		GP_3_8_FN,	GPSR3_8,
++		GP_3_7_FN,	GPSR3_7,
++		GP_3_6_FN,	GPSR3_6,
++		GP_3_5_FN,	GPSR3_5,
++		GP_3_4_FN,	GPSR3_4,
++		GP_3_3_FN,	GPSR3_3,
++		GP_3_2_FN,	GPSR3_2,
++		GP_3_1_FN,	GPSR3_1,
++		GP_3_0_FN,	GPSR3_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_4_24_FN,	GPSR4_24,
++		GP_4_23_FN,	GPSR4_23,
++		GP_4_22_FN,	GPSR4_22,
++		GP_4_21_FN,	GPSR4_21,
++		GP_4_20_FN,	GPSR4_20,
++		GP_4_19_FN,	GPSR4_19,
++		GP_4_18_FN,	GPSR4_18,
++		GP_4_17_FN,	GPSR4_17,
++		GP_4_16_FN,	GPSR4_16,
++		GP_4_15_FN,	GPSR4_15,
++		GP_4_14_FN,	GPSR4_14,
++		GP_4_13_FN,	GPSR4_13,
++		GP_4_12_FN,	GPSR4_12,
++		GP_4_11_FN,	GPSR4_11,
++		GP_4_10_FN,	GPSR4_10,
++		GP_4_9_FN,	GPSR4_9,
++		GP_4_8_FN,	GPSR4_8,
++		GP_4_7_FN,	GPSR4_7,
++		GP_4_6_FN,	GPSR4_6,
++		GP_4_5_FN,	GPSR4_5,
++		GP_4_4_FN,	GPSR4_4,
++		GP_4_3_FN,	GPSR4_3,
++		GP_4_2_FN,	GPSR4_2,
++		GP_4_1_FN,	GPSR4_1,
++		GP_4_0_FN,	GPSR4_0, }
++	},
++	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		GP_5_14_FN,	GPSR5_14,
++		GP_5_13_FN,	GPSR5_13,
++		GP_5_12_FN,	GPSR5_12,
++		GP_5_11_FN,	GPSR5_11,
++		GP_5_10_FN,	GPSR5_10,
++		GP_5_9_FN,	GPSR5_9,
++		GP_5_8_FN,	GPSR5_8,
++		GP_5_7_FN,	GPSR5_7,
++		GP_5_6_FN,	GPSR5_6,
++		GP_5_5_FN,	GPSR5_5,
++		GP_5_4_FN,	GPSR5_4,
++		GP_5_3_FN,	GPSR5_3,
++		GP_5_2_FN,	GPSR5_2,
++		GP_5_1_FN,	GPSR5_1,
++		GP_5_0_FN,	GPSR5_0, }
++	},
++#undef F_
++#undef FM
++
++#define F_(x, y)	x,
++#define FM(x)		FN_##x,
++	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
++		IP0_31_28
++		IP0_27_24
++		IP0_23_20
++		IP0_19_16
++		IP0_15_12
++		IP0_11_8
++		IP0_7_4
++		IP0_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
++		IP1_31_28
++		IP1_27_24
++		IP1_23_20
++		IP1_19_16
++		IP1_15_12
++		IP1_11_8
++		IP1_7_4
++		IP1_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
++		IP2_31_28
++		IP2_27_24
++		IP2_23_20
++		IP2_19_16
++		IP2_15_12
++		IP2_11_8
++		IP2_7_4
++		IP2_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
++		IP3_31_28
++		IP3_27_24
++		IP3_23_20
++		IP3_19_16
++		IP3_15_12
++		IP3_11_8
++		IP3_7_4
++		IP3_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
++		IP4_31_28
++		IP4_27_24
++		IP4_23_20
++		IP4_19_16
++		IP4_15_12
++		IP4_11_8
++		IP4_7_4
++		IP4_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
++		IP5_31_28
++		IP5_27_24
++		IP5_23_20
++		IP5_19_16
++		IP5_15_12
++		IP5_11_8
++		IP5_7_4
++		IP5_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
++		IP6_31_28
++		IP6_27_24
++		IP6_23_20
++		IP6_19_16
++		IP6_15_12
++		IP6_11_8
++		IP6_7_4
++		IP6_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
++		IP7_31_28
++		IP7_27_24
++		IP7_23_20
++		IP7_19_16
++		IP7_15_12
++		IP7_11_8
++		IP7_7_4
++		IP7_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
++		IP8_31_28
++		IP8_27_24
++		IP8_23_20
++		IP8_19_16
++		IP8_15_12
++		IP8_11_8
++		IP8_7_4
++		IP8_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
++		IP8_31_28
++		IP8_27_24
++		IP8_23_20
++		IP8_19_16
++		IP8_15_12
++		IP8_11_8
++		IP8_7_4
++		IP8_3_0 }
++	},
++	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
++		IP8_31_28
++		IP8_27_24
++		IP8_23_20
++		IP8_19_16
++		IP8_15_12
++		IP8_11_8
++		IP8_7_4
++		IP8_3_0 }
++	},
++#undef F_
++#undef FM
++
++#define F_(x, y)	x,
++#define FM(x)		FN_##x,
++	{ PINMUX_CFG_REG("MOD_SEL0", 0xe6060500, 32, 1) {
++		/* RESERVED 31..12 */
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		0, 0,
++		MOD_SEL0_11
++		MOD_SEL0_10
++		MOD_SEL0_9
++		MOD_SEL0_8
++		MOD_SEL0_7
++		MOD_SEL0_6
++		MOD_SEL0_5
++		MOD_SEL0_4
++		0, 0,
++		MOD_SEL0_2
++		MOD_SEL0_1
++		MOD_SEL0_0 }
++	},
++	{ },
++};
++
++#define POC0 0xe6060380
++#define POC1 0xe6060384
++#define POC2 0xe6060388
++
++/* TODO make it nice */
++static int r8a7798_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
++{
++	int bit = -EINVAL;
++
++	*pocctrl = POC0;
++
++	if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
++		bit = pin & 0x1f;
++	else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
++		bit = (pin & 0x1f) + 22;
++
++	if (bit != -EINVAL)
++		goto out;
++
++	*pocctrl = POC1;
++
++	if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
++		bit = (pin & 0x1f) - 10;
++	else if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
++		bit = (pin & 0x1f) + 7;
++	else if (pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24))
++		bit = (pin & 0x1f) + 7;
++
++	if (bit != -EINVAL)
++		goto out;
++
++	*pocctrl = POC2;
++
++	if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
++		bit = (pin & 0x1f) - 25;
++
++out:
++	return bit;
++}
++
++static const struct sh_pfc_soc_operations pinmux_ops = {
++	.pin_to_pocctrl = r8a7798_pin_to_pocctrl,
++};
++
++const struct sh_pfc_soc_info r8a7798_pinmux_info = {
++	.name = "r8a77980_pfc",
++	.ops = &pinmux_ops,
++	.unlock_reg = 0xe6060000, /* PMMR */
++
++	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
++
++	.pins = pinmux_pins,
++	.nr_pins = ARRAY_SIZE(pinmux_pins),
++	.groups = pinmux_groups,
++	.nr_groups = ARRAY_SIZE(pinmux_groups),
++	.functions = pinmux_functions,
++	.nr_functions = ARRAY_SIZE(pinmux_functions),
++
++	.cfg_regs = pinmux_config_regs,
++
++	.pinmux_data = pinmux_data,
++	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
++};
+diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
+index 062af89..31df6d4 100644
+--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
+@@ -289,6 +291,7 @@ struct sh_pfc_soc_info {
+ extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
+ extern const struct sh_pfc_soc_info r8a7797_pinmux_info;
++extern const struct sh_pfc_soc_info r8a7798_pinmux_info;
+ extern const struct sh_pfc_soc_info sh7203_pinmux_info;
+ extern const struct sh_pfc_soc_info sh7264_pinmux_info;
+ extern const struct sh_pfc_soc_info sh7269_pinmux_info;
+@@ -465,9 +468,13 @@ struct sh_pfc_soc_info {
+ 	PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
+ #define PORT_GP_24(bank, fn, sfx)	PORT_GP_CFG_24(bank, fn, sfx, 0)
+ 
+-#define PORT_GP_CFG_26(bank, fn, sfx, cfg)				\
++#define PORT_GP_CFG_25(bank, fn, sfx, cfg)				\
+ 	PORT_GP_CFG_24(bank, fn, sfx, cfg),				\
+-	PORT_GP_CFG_1(bank, 24, fn, sfx, cfg),				\
++	PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
++#define PORT_GP_24(bank, fn, sfx)	PORT_GP_CFG_24(bank, fn, sfx, 0)
++
++#define PORT_GP_CFG_26(bank, fn, sfx, cfg)				\
++	PORT_GP_CFG_25(bank, fn, sfx, cfg),				\
+ 	PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
+ #define PORT_GP_26(bank, fn, sfx)	PORT_GP_CFG_26(bank, fn, sfx, 0)
+ 
+diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
+index 2ba6a76..164b3e7 100644
+--- a/drivers/soc/renesas/Makefile
++++ b/drivers/soc/renesas/Makefile
+@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_R8A7795)	+= rcar-rst.o
+ obj-$(CONFIG_ARCH_R8A7796)	+= rcar-rst.o
+ obj-$(CONFIG_ARCH_R8A77965)	+= rcar-rst.o
+ obj-$(CONFIG_ARCH_R8A7797)	+= rcar-rst.o
++obj-$(CONFIG_ARCH_R8A7798)	+= rcar-rst.o
+ 
+ obj-$(CONFIG_ARCH_R8A7743)	+= rcar-sysc.o r8a7743-sysc.o
+ obj-$(CONFIG_ARCH_R8A7745)	+= rcar-sysc.o r8a7745-sysc.o
+@@ -20,15 +21,18 @@ obj-$(CONFIG_ARCH_R8A7795)	+= rcar-sysc.o r8a7795-sysc.o
+ obj-$(CONFIG_ARCH_R8A7796)	+= rcar-sysc.o r8a7796-sysc.o
+ obj-$(CONFIG_ARCH_R8A77965)	+= rcar-sysc.o r8a77965-sysc.o
+ obj-$(CONFIG_ARCH_R8A7797)	+= rcar-sysc.o r8a7797-sysc.o
++obj-$(CONFIG_ARCH_R8A7798)	+= rcar-sysc.o r8a7798-sysc.o
+ 
+ obj-$(CONFIG_ARCH_R8A7795)	+= rcar-avs.o
+ obj-$(CONFIG_ARCH_R8A7796)	+= rcar-avs.o
+ obj-$(CONFIG_ARCH_R8A77965)	+= rcar-avs.o
+ obj-$(CONFIG_ARCH_R8A7797)	+= rcar-avs.o
++obj-$(CONFIG_ARCH_R8A7798)	+= rcar-avs.o
+ # EMS for R-Car Gen3
+ obj-$(CONFIG_ARCH_R8A7795)	+= rcar_ems_ctrl.o
+ obj-$(CONFIG_ARCH_R8A7796)	+= rcar_ems_ctrl.o
+ obj-$(CONFIG_ARCH_R8A77965)	+= rcar_ems_ctrl.o
+ obj-$(CONFIG_ARCH_R8A7797)	+= rcar_ems_ctrl.o
++obj-$(CONFIG_ARCH_R8A7798)	+= rcar_ems_ctrl.o
+ 
+ obj-$(CONFIG_RCAR_DDR_BACKUP)	+= s2ram_ddr_backup.o
+diff --git a/drivers/soc/renesas/r8a7798-sysc.c b/drivers/soc/renesas/r8a7798-sysc.c
+new file mode 100644
+index 0000000..d530488
+--- /dev/null
++++ b/drivers/soc/renesas/r8a7798-sysc.c
+@@ -0,0 +1,57 @@
++/*
++ * Renesas R-Car V3H System Controller
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ */
++
++#include <linux/bug.h>
++#include <linux/kernel.h>
++
++#include <dt-bindings/power/r8a7798-sysc.h>
++
++#include "rcar-sysc.h"
++
++static const struct rcar_sysc_area r8a7798_areas[] __initconst = {
++	{ "always-on",	    0, 0, R8A7798_PD_ALWAYS_ON,	-1, PD_ALWAYS_ON },
++	{ "ca53-scu",	0x140, 0, R8A7798_PD_CA53_SCU,	R8A7798_PD_ALWAYS_ON,
++	  PD_SCU },
++	{ "ca53-cpu0",	0x200, 0, R8A7798_PD_CA53_CPU0,	R8A7798_PD_CA53_SCU,
++	  PD_CPU_NOCR },
++	{ "ca53-cpu1",	0x200, 1, R8A7798_PD_CA53_CPU1,	R8A7798_PD_CA53_SCU,
++	  PD_CPU_NOCR },
++	{ "ca53-cpu2",	0x200, 2, R8A7798_PD_CA53_CPU2,	R8A7798_PD_CA53_SCU,
++	  PD_CPU_NOCR },
++	{ "ca53-cpu3",	0x200, 3, R8A7798_PD_CA53_CPU3,	R8A7798_PD_CA53_SCU,
++	  PD_CPU_NOCR },
++	{ "cr7",	0x240, 0, R8A7798_PD_CR7,	R8A7798_PD_ALWAYS_ON },
++
++	{ "a3ir", 	0x180, 0, R8A7798_PD_A3IR,	R8A7798_PD_ALWAYS_ON },
++	{ "a2ir0",	0x400, 0, R8A7798_PD_A2IR0,	R8A7798_PD_ALWAYS_ON },
++	{ "a2ir1",	0x400, 1, R8A7798_PD_A2IR1,	R8A7798_PD_A2IR0 },
++	{ "a2ir2",	0x400, 2, R8A7798_PD_A2IR2,	R8A7798_PD_A2IR0 },
++	{ "a2ir3",	0x400, 3, R8A7798_PD_A2IR3,	R8A7798_PD_A2IR0 },
++	{ "a2ir4",	0x400, 4, R8A7798_PD_A2IR4,	R8A7798_PD_A2IR0 },
++	{ "a2ir5",	0x400, 5, R8A7798_PD_A2IR5,	R8A7798_PD_A2IR0 },
++	{ "a2sc0", 	0x400, 6, R8A7798_PD_A2SC0,	R8A7798_PD_ALWAYS_ON },
++	{ "a2sc1", 	0x400, 7, R8A7798_PD_A2SC1,	R8A7798_PD_A2SC0 },
++	{ "a2sc2", 	0x400, 8, R8A7798_PD_A2SC2,	R8A7798_PD_A2SC0 },
++	{ "a2sc3", 	0x400, 9, R8A7798_PD_A2SC3,	R8A7798_PD_A2SC0 },
++	{ "a2sc4", 	0x400, 10, R8A7798_PD_A2SC4,	R8A7798_PD_A2SC0 },
++	{ "a2pd0", 	0x400, 11, R8A7798_PD_A2PD0,	R8A7798_PD_ALWAYS_ON }, /* OK? */
++	{ "a2pd1", 	0x400, 12, R8A7798_PD_A2PD1,	R8A7798_PD_A2PD0 }, /* OK? */
++	{ "a2cn", 	0x400, 13, R8A7798_PD_A2CN,	R8A7798_PD_ALWAYS_ON }, /* OK? */
++
++	{ "a3vip", 	0x2c0, 0, R8A7798_PD_A3VIP,	R8A7798_PD_ALWAYS_ON }, /* OK? */
++	{ "a3vip1", 	0x300, 0, R8A7798_PD_A3VIP1,	R8A7798_PD_A3VIP }, /* OK? */
++	{ "a3vip2", 	0x280, 0, R8A7798_PD_A3VIP2,	R8A7798_PD_A3VIP }, /* OK? */
++};
++
++const struct rcar_sysc_info r8a7798_sysc_info __initconst = {
++	.areas = r8a7798_areas,
++	.num_areas = ARRAY_SIZE(r8a7798_areas),
++};
+diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
+index bc3632b..19b441b 100644
+--- a/drivers/soc/renesas/rcar-rst.c
++++ b/drivers/soc/renesas/rcar-rst.c
+@@ -43,6 +45,7 @@ struct rst_config {
+ 	{ .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen2 },
+ 	{ .compatible = "renesas,r8a77965-rst", .data = &rcar_rst_gen2 },
+ 	{ .compatible = "renesas,r8a7797-rst", .data = &rcar_rst_gen2 },
++	{ .compatible = "renesas,r8a7798-rst", .data = &rcar_rst_gen2 },
+ 	{ /* sentinel */ }
+ };
+ 
+diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
+index 1d5d440..87d5c21 100644
+--- a/drivers/soc/renesas/rcar-sysc.c
++++ b/drivers/soc/renesas/rcar-sysc.c
+@@ -327,6 +329,9 @@ static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
+ #ifdef CONFIG_ARCH_R8A7797
+ 	{ .compatible = "renesas,r8a7797-sysc", .data = &r8a7797_sysc_info },
+ #endif
++#ifdef CONFIG_ARCH_R8A7798
++	{ .compatible = "renesas,r8a7798-sysc", .data = &r8a7798_sysc_info },
++#endif
+ 	{ /* sentinel */ }
+ };
+ 
+diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
+index 1eb4e6d..c3b5bce 100644
+--- a/drivers/soc/renesas/rcar-sysc.h
++++ b/drivers/soc/renesas/rcar-sysc.h
+@@ -62,4 +64,5 @@ struct rcar_sysc_info {
+ extern const struct rcar_sysc_info r8a7796_sysc_info;
+ extern const struct rcar_sysc_info r8a77965_sysc_info;
+ extern const struct rcar_sysc_info r8a7797_sysc_info;
++extern const struct rcar_sysc_info r8a7798_sysc_info;
+ #endif /* __SOC_RENESAS_RCAR_SYSC_H__ */
+diff --git a/drivers/soc/renesas/rcar_ems_ctrl.c b/drivers/soc/renesas/rcar_ems_ctrl.c
+index 388c570..007e203 100644
+--- a/drivers/soc/renesas/rcar_ems_ctrl.c
++++ b/drivers/soc/renesas/rcar_ems_ctrl.c
+@@ -30,8 +31,9 @@
+ 
+ #define EMS_THERMAL_ZONE_MAX	10
+ 
+-static const struct soc_device_attribute r8a7797[] = {
++static const struct soc_device_attribute r8a7797_8[] = {
+ 	{ .soc_id = "r8a7797" },
++	{ .soc_id = "r8a7798" },
+ 	{ }
+ };
+ 
+@@ -274,7 +276,7 @@ static int __init rcar_ems_cpu_shutdown_init(void)
+ 
+ 	for_each_online_cpu(cpu) {
+ 		tmp_node  = of_get_cpu_node(cpu, NULL);
+-		if (soc_device_match(r8a7797)) {
++		if (soc_device_match(r8a7797_8)) {
+ 			if (!of_device_is_compatible(tmp_node, "arm,cortex-a53"))
+ 				continue;
+ 		}
+diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
+index 63f943d..c107f7c 100644
+--- a/drivers/soc/renesas/renesas-soc.c
++++ b/drivers/soc/renesas/renesas-soc.c
+@@ -144,6 +146,11 @@ struct renesas_soc {
+ 	.id	= 0x54,
+ };
+ 
++static const struct renesas_soc soc_rcar_v3h __initconst __maybe_unused = {
++	.family	= &fam_rcar_gen3,
++	.id	= 0x56,
++};
++
+ static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = {
+ 	.family	= &fam_shmobile,
+ 	.id	= 0x37,
+@@ -199,6 +206,9 @@ struct renesas_soc {
+ #ifdef CONFIG_ARCH_R8A7797
+ 	{ .compatible = "renesas,r8a7797",	.data = &soc_rcar_v3m },
+ #endif
++#ifdef CONFIG_ARCH_R8A7798
++	{ .compatible = "renesas,r8a7798",	.data = &soc_rcar_v3h },
++#endif
+ #ifdef CONFIG_ARCH_SH73A0
+ 	{ .compatible = "renesas,sh73a0",	.data = &soc_shmobile_ag5 },
+ #endif
+diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
+index a2606fe..bbe2526 100644
+--- a/drivers/spi/spi-sh-msiof.c
++++ b/drivers/spi/spi-sh-msiof.c
+@@ -217,7 +218,8 @@ static int msiof_rcar_is_gen3(struct device *dev)
+ 	return of_device_is_compatible(node, "renesas,msiof-r8a7795") ||
+ 		of_device_is_compatible(node, "renesas,msiof-r8a7796") ||
+ 		of_device_is_compatible(node, "renesas,msiof-r8a77965") ||
+-		of_device_is_compatible(node, "renesas,msiof-r8a7797");
++		of_device_is_compatible(node, "renesas,msiof-r8a7797") ||
++		of_device_is_compatible(node, "renesas,msiof-r8a7798");
+ }
+ 
+ static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
+@@ -1192,6 +1194,7 @@ static int sh_msiof_transfer_one(struct spi_master *master,
+ 	{ .compatible = "renesas,msiof-r8a7796",   .data = &r8a779x_data },
+ 	{ .compatible = "renesas,msiof-r8a77965",  .data = &r8a779x_data },
+ 	{ .compatible = "renesas,msiof-r8a7797",   .data = &r8a779x_data },
++	{ .compatible = "renesas,msiof-r8a7798",   .data = &r8a779x_data },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, sh_msiof_match);
+diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c
+index a23dd44..44bc4fd 100644
+--- a/drivers/thermal/rcar_gen3_thermal.c
++++ b/drivers/thermal/rcar_gen3_thermal.c
+@@ -415,6 +416,11 @@ static int rcar_gen3_r8a7797_thermal_init(struct rcar_thermal_priv *priv)
+ 	return 0;
+ }
+ 
++static int rcar_gen3_r8a7798_thermal_init(struct rcar_thermal_priv *priv)
++{
++	return rcar_gen3_r8a7796_thermal_init(priv);
++}
++
+ /*
+  *		Interrupt
+  */
+@@ -500,11 +506,16 @@ static int rcar_gen3_thermal_remove(struct platform_device *pdev)
+ 	.thermal_init = rcar_gen3_r8a7797_thermal_init,
+ };
+ 
++static const struct rcar_thermal_data r8a7798_data = {
++	.thermal_init = rcar_gen3_r8a7798_thermal_init,
++};
++
+ static const struct of_device_id rcar_thermal_dt_ids[] = {
+ 	{ .compatible = "renesas,thermal-r8a7795", .data = &r8a7795_data},
+ 	{ .compatible = "renesas,thermal-r8a7796", .data = &r8a7796_data},
+ 	{ .compatible = "renesas,thermal-r8a77965", .data = &r8a7796_data},
+ 	{ .compatible = "renesas,thermal-r8a7797", .data = &r8a7797_data},
++	{ .compatible = "renesas,thermal-r8a7798", .data = &r8a7798_data},
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, rcar_thermal_dt_ids);
+diff --git a/include/dt-bindings/clock/r8a7798-cpg-mssr.h b/include/dt-bindings/clock/r8a7798-cpg-mssr.h
+new file mode 100644
+index 0000000..6c2d97a
+--- /dev/null
++++ b/include/dt-bindings/clock/r8a7798-cpg-mssr.h
+@@ -0,0 +1,56 @@
++/*
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++#ifndef __DT_BINDINGS_CLOCK_R8A7798_CPG_MSSR_H__
++#define __DT_BINDINGS_CLOCK_R8A7798_CPG_MSSR_H__
++
++#include <dt-bindings/clock/renesas-cpg-mssr.h>
++
++/* r8a7798 CPG Core Clocks */
++#define R8A7798_CLK_Z2			0
++#define R8A7798_CLK_ZR			1
++#define R8A7798_CLK_ZTR			2
++#define R8A7798_CLK_ZTRD2		3
++#define R8A7798_CLK_ZT			4
++#define R8A7798_CLK_ZX			5
++#define R8A7798_CLK_S0D1		6
++#define R8A7798_CLK_S0D2		7
++#define R8A7798_CLK_S0D3		8
++#define R8A7798_CLK_S0D4		9
++#define R8A7798_CLK_S0D6		10
++#define R8A7798_CLK_S0D12		11
++#define R8A7798_CLK_S0D24		12
++#define R8A7798_CLK_S1D1		13
++#define R8A7798_CLK_S1D2		14
++#define R8A7798_CLK_S1D4		15
++#define R8A7798_CLK_S2D1		16
++#define R8A7798_CLK_S2D2		17
++#define R8A7798_CLK_S2D4		18
++#define R8A7798_CLK_S3D1		19
++#define R8A7798_CLK_S3D2		20
++#define R8A7798_CLK_S3D4		21
++#define R8A7798_CLK_LB			22
++#define R8A7798_CLK_CL			23
++#define R8A7798_CLK_ZB3			24
++#define R8A7798_CLK_ZB3D2		25
++#define R8A7798_CLK_ZB3D4		26
++#define R8A7798_CLK_SD0H		27
++#define R8A7798_CLK_SD0			28
++#define R8A7798_CLK_RPC			29
++#define R8A7798_CLK_RPCD2		30
++#define R8A7798_CLK_MSO			31
++#define R8A7798_CLK_CANFD		32
++#define R8A7798_CLK_CSI0		33
++#define R8A7798_CLK_CSIREF		34
++#define R8A7798_CLK_CP			35
++#define R8A7798_CLK_CPEX		36
++#define R8A7798_CLK_R			37
++#define R8A7798_CLK_OSC			38
++
++#endif /* __DT_BINDINGS_CLOCK_R8A7798_CPG_MSSR_H__ */
+diff --git a/include/dt-bindings/power/r8a7798-sysc.h b/include/dt-bindings/power/r8a7798-sysc.h
+new file mode 100644
+index 0000000..2451b16
+--- /dev/null
++++ b/include/dt-bindings/power/r8a7798-sysc.h
+@@ -0,0 +1,46 @@
++/*
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ */
++#ifndef __DT_BINDINGS_POWER_R8A7798_SYSC_H__
++#define __DT_BINDINGS_POWER_R8A7798_SYSC_H__
++
++/*
++ * These power domain indices match the numbers of the interrupt bits
++ * representing the power areas in the various Interrupt Registers
++ * (e.g. SYSCISR, Interrupt Status Register)
++ */
++
++#define R8A7798_PD_A2SC2		0
++#define R8A7798_PD_A2SC3		1
++#define R8A7798_PD_A2SC4		2
++#define R8A7798_PD_A2PD0		3
++#define R8A7798_PD_A2PD1		4
++#define R8A7798_PD_CA53_CPU0		5
++#define R8A7798_PD_CA53_CPU1		6
++#define R8A7798_PD_CA53_CPU2		7
++#define R8A7798_PD_CA53_CPU3		8
++#define R8A7798_PD_A2CN			10
++#define R8A7798_PD_A3VIP		11
++#define R8A7798_PD_A2IR5		12
++#define R8A7798_PD_CR7			13
++#define R8A7798_PD_A2IR4		15
++#define R8A7798_PD_CA53_SCU		21
++#define R8A7798_PD_A2IR0		23
++#define R8A7798_PD_A3IR			24
++#define R8A7798_PD_A3VIP1		25
++#define R8A7798_PD_A3VIP2		26
++#define R8A7798_PD_A2IR1		27
++#define R8A7798_PD_A2IR2		28
++#define R8A7798_PD_A2IR3		29
++#define R8A7798_PD_A2SC0		30
++#define R8A7798_PD_A2SC1		31
++
++/* Always-on power area */
++#define R8A7798_PD_ALWAYS_ON		32
++
++#endif /* __DT_BINDINGS_POWER_R8A7798_SYSC_H__ */
+-- 
+1.9.1
+
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0104-media-vsp1-extend-DRM-VSP1-interface.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0104-media-vsp1-extend-DRM-VSP1-interface.patch
index 2f6fa35..ecd0fd5 100644
--- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0104-media-vsp1-extend-DRM-VSP1-interface.patch
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0104-media-vsp1-extend-DRM-VSP1-interface.patch
@@ -198,7 +198,7 @@ index e79f9e6..753763d 100644
 +			(format->code != MEDIA_BUS_FMT_ARGB8888_1X32 ? VI6_LIF_CTRL_CFMT : 0) |
  			VI6_LIF_CTRL_REQSEL | VI6_LIF_CTRL_LIF_EN);
  
- 	if (soc_device_match(r8a7797))
+ 	if (soc_device_match(r8a7797_8))
 diff --git a/drivers/media/platform/vsp1/vsp1_pipe.c b/drivers/media/platform/vsp1/vsp1_pipe.c
 index 8379962..86d4a85 100644
 --- a/drivers/media/platform/vsp1/vsp1_pipe.c
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/condor.cfg b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/condor.cfg
new file mode 100644
index 0000000..46f8879
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/condor.cfg
@@ -0,0 +1,29 @@
+CONFIG_ARCH_R8A7798=y
+CONFIG_CAN=y
+CONFIG_CAN_BCM=y
+CONFIG_CAN_RAW=y
+CONFIG_CAN_DEV=y
+CONFIG_CAN_CALC_BITTIMING=y
+CONFIG_CAN_RCAR=y
+CONFIG_CAN_RCAR_CANFD=y
+CONFIG_DUMMY=y
+CONFIG_DRM_I2C_ADV7511=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_VIDEO_ADV_DEBUG=y
+CONFIG_VIDEO_RCAR_VIN_LEGACY=y
+CONFIG_VIDEO_RCAR_CSI2_LEGACY=y
+# CONFIG_VIDEO_RCAR_VIN is not set
+# CONFIG_VIDEO_RCAR_CSI2 is not set
+CONFIG_SOC_CAMERA=y
+CONFIG_SOC_CAMERA_SCALE_CROP=y
+CONFIG_SOC_CAMERA_PLATFORM=y
+CONFIG_SOC_CAMERA_MAX9286_MAX9271=y
+CONFIG_SOC_CAMERA_OV106XX=y
+CONFIG_VIDEO_RENESAS_IMR=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_TOUCHSCREEN_PROPERTIES=y
+CONFIG_HID_MULTITOUCH=y
+CONFIG_SERIAL_SH_SCI_DMA=y
+CONFIG_UIO=y
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend
index 110d8bb..f21ad58 100644
--- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend
@@ -2,6 +2,7 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
 
 COMPATIBLE_MACHINE_eagle = "eagle"
 COMPATIBLE_MACHINE_v3msk = "v3msk"
+COMPATIBLE_MACHINE_condor = "condor"
 
 SRC_URI_append = " \
     ${@bb.utils.contains('MACHINE_FEATURES', 'h3ulcb-had', ' file://hyperflash.cfg', '', d)} \
@@ -51,6 +52,7 @@ SRC_URI_append = " \
     ${@base_conditional("KF_ENABLE_MOST", "1", " file://0048-arm64-dts-renesas-ulcb-kf-enable-most.patch", "", d)} \
     file://0049-clk-r8a779x-add-IMP-clock.patch \
     file://0050-arm64-dts-renesas-r8a779x-add-IMP-nodes.patch \
+    file://0051-arm64-renesas-r8a7798-Add-Renesas-R8A7798-SoC-suppor.patch \
     ${@base_conditional("LVDSCAMERA_FIRST4_TYPE1", "1", " file://0050-arm64-dts-Gen3-view-boards-TYPE1-first-4-cameras.patch", "", d)} \
     ${@base_conditional("LVDSCAMERA_SECOND4_TYPE1", "1", " file://0051-arm64-dts-Gen3-view-boards-TYPE1-second-4-cameras.patch", "", d)} \
     ${@base_conditional("LVDSCAMERA_FIRST4_TYPE2", "1", " file://0052-arm64-dts-Gen3-view-boards-TYPE2-first-4-cameras.patch", "", d)} \
@@ -71,9 +73,6 @@ SRC_URI_append = " \
     file://0078-MOST-aim-fix-null-pointer-crash.patch \
     file://0079-Revert-dmaengine-rcar-dmac-use-TCRB-instead-of-TCR-f.patch \
     file://0082-gpio-pca953x-fix-interrupt-trigger.patch \
-"
-
-SRC_URI_append_r8a7797 = " \
     file://0103-gpu-drm-rcar-du-Extend-VSP1-DRM-interface.patch \
     file://0104-media-vsp1-extend-DRM-VSP1-interface.patch \
     file://0105-media-rcar-imr-IMR-driver-updates-for-raw-DL.patch \
@@ -84,6 +83,7 @@ SRC_URI_append_m3ulcb = " file://ulcb.cfg"
 SRC_URI_append_salvator-x = " file://salvator-x.cfg"
 SRC_URI_append_eagle = " file://eagle.cfg"
 SRC_URI_append_v3msk = " file://v3msk.cfg"
+SRC_URI_append_condor = " file://condor.cfg"
 
 KERNEL_DEVICETREE_append_h3ulcb = " \
     renesas/r8a7795-es1-h3ulcb-view.dtb \
@@ -124,3 +124,7 @@ KERNEL_DEVICETREE_append_v3msk = " \
     renesas/r8a7797-v3msk-vbm.dtb \
     renesas/r8a7797-v3msk-view.dtb \
 "
+
+KERNEL_DEVICETREE_append_condor = " \
+    renesas/r8a7798-condor.dtb \
+"