diff options
| author |   Vladimir Barinov <vladimir.barinov@cogentembedded.com> | 2018-02-02 19:49:48 +0300 |
|---|---|---|
| committer | Vladimir Barinov <vladimir.barinov@cogentembedded.com> | 2018-02-26 23:24:53 +0300 |
| commit | 542444ddb5346f081a294ae768841dfedcd6f917 (patch) | |
| tree | 6b0646ea0b84c4f5cc55d450adf40371b7eb7969 /meta-rcar-gen3-adas/recipes-bsp/u-boot | |
| parent | 29b6249c5aa7b243248cf4623a41a1f0be4c70a4 (diff) | |
V3M SK: fix CPLD access in uboot
Diffstat (limited to 'meta-rcar-gen3-adas/recipes-bsp/u-boot')
| -rw-r--r-- | meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch index f5bcc9c..306bc1b 100644 --- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch @@ -78,8 +78,8 @@ index 0000000..c39eb76 +M: Cogent Embedded, Inc. <source@cogentembedded.com> +S: Maintained +F: board/renesas/v3msk/ -+F: include/configs/r8a7797_v3msk.h -+F: configs/r8a7797_v3msk_defconfig ++F: include/configs/v3msk.h ++F: configs/v3msk_defconfig diff --git a/board/renesas/v3msk/Makefile b/board/renesas/v3msk/Makefile new file mode 100644 index 0000000..1f2ea42 @@ -100,7 +100,7 @@ new file mode 100644 index 0000000..ffb0637 --- /dev/null +++ b/board/renesas/v3msk/cpld.c -@@ -0,0 +1,164 @@ +@@ -0,0 +1,170 @@ +/* + * V3MSK board CPLD access support + * @@ -144,6 +144,9 @@ index 0000000..ffb0637 +#define PFC_PUEN2 0xe6060408 +#define PUEN_CANFD1_TX (1 << 29) + ++#define GP0_MSTP912 (1 << 12) ++#define GP1_MSTP911 (1 << 11) ++ +#define MDIO_DELAY 10 /* microseconds */ + +#define mdio_bb_active_mdio() gpio_direction_output(MOSI, 0) @@ -180,6 +183,9 @@ index 0000000..ffb0637 + /* PULL-UP on MISO line (should be pulled up after POR on V3M) */ + writel(readl(PFC_PUEN2) | PUEN_CANFD1_TX, PFC_PUEN2); +#endif ++ /* GPIO0 and GPIO1 */ ++ mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, GP0_MSTP912 | GP1_MSTP911); ++ + gpio_request(MDC, NULL); + gpio_request(ENABLEZ, NULL); + gpio_request(MOSI, NULL); |