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authorHarunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>2018-01-19 20:43:09 +0900
committerHarunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>2018-01-19 20:43:09 +0900
commit2e1a7e39e012ea4436c819f46cfcac05fb161184 (patch)
tree094a98fe4f8a2970fdd7a86e1562125f096db049 /meta-rcar-gen3-adas/recipes-bsp/u-boot
parent89ae3df5fc1ec66b573f724c0e462bde0eabe783 (diff)
parent87b938882b4c672c775c7a0908f4a8b711a16c95 (diff)
Merge remote-tracking branch 'cogent/v2.23.1' into test
Change-Id: I2615a0e01b209fb359245a56996185e046cdb94a Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
Diffstat (limited to 'meta-rcar-gen3-adas/recipes-bsp/u-boot')
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch21
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch26
2 files changed, 30 insertions, 17 deletions
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch
index 8545634..050d98f 100644
--- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch
@@ -3510,19 +3510,7 @@ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-comm
index 0a959f7..ec20aba 100644
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
-@@ -93,7 +93,11 @@
- #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 }
-
- /* MEMORY */
-+#if defined(CONFIG_R8A7797)
-+#define CONFIG_SYS_TEXT_BASE 0x58280000
-+#else
- #define CONFIG_SYS_TEXT_BASE 0x50000000
-+#endif
- #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7fff0)
-
-
-@@ -124,6 +128,14 @@
+@@ -124,6 +128,17 @@
#define PHYS_SDRAM_1_SIZE ((unsigned long)(0x80000000 - DRAM_RSV_SIZE))
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
@@ -3530,8 +3518,11 @@ index 0a959f7..ec20aba 100644
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE) /* legacy */
+#define PHYS_SDRAM_1_SIZE ((unsigned long)(0x40000000 - DRAM_RSV_SIZE))
-+#define PHYS_SDRAM_2 0x0600000000 /* ext */
-+#define PHYS_SDRAM_2_SIZE ((unsigned long)0x80000000)
++ #if defined(CONFIG_TARGET_V3MSK)
++ #define PHYS_SDRAM_1_SIZE ((unsigned long)(0x80000000 - DRAM_RSV_SIZE))
++ #else
++ #define PHYS_SDRAM_1_SIZE ((unsigned long)(0x40000000 - DRAM_RSV_SIZE))
++ #endif
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
#else
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch
index 479f23f..ecbbfea 100644
--- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch
@@ -8,8 +8,9 @@ This is only for H3ULCB.HAD
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
- include/configs/h3ulcb.h | 4 ++--
- 1 file changed, 1 insertions(+), 1 deletions(-)
+ include/configs/h3ulcb.h | 4 ++--
+ board/renesas/ulcb/ulcb.c | 3 +++
+ 2 file changed, 4 insertions(+), 1 deletions(-)
diff --git a/include/configs/h3ulcb.h b/include/configs/h3ulcb.h
index b9be845..3da2e5a 100644
@@ -23,6 +24,27 @@ index b9be845..3da2e5a 100644
+#define CONFIG_CONS_SCIF1
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
+diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
+index 0d8752f..1be01cf 100644
+--- a/board/renesas/ulcb/ulcb.c
++++ b/board/renesas/ulcb/ulcb.c
+@@ -29,6 +29,7 @@
+
+ DECLARE_GLOBAL_DATA_PTR;
+
++#define SCIF1_MSTP206 (1 << 6)
+ #define SCIF2_MSTP310 (1 << 10)
+ #define ETHERAVB_MSTP812 (1 << 12)
+ #define DVFS_MSTP926 (1 << 26)
+@@ -49,6 +50,8 @@ int board_early_init_f(void)
+
+ rcar_prr_init();
+
++ /* SCIF1 */
++ mstp_clrbits_le32(SMSTPCR2, SMSTPCR2, SCIF1_MSTP206);
+ /* SCIF2 */
+ mstp_clrbits_le32(SMSTPCR3, SMSTPCR3, SCIF2_MSTP310);
+ /* EHTERAVB */
--
1.9.1