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authorVladimir Barinov <vladimir.barinov@cogentembedded.com>2018-01-08 15:41:23 +0300
committerVladimir Barinov <vladimir.barinov@cogentembedded.com>2018-01-08 15:41:23 +0300
commitdefc4efcf6c6bb6cd6dc0741bb0864d885aed9dc (patch)
tree86727c7a123b6488c7943f51fd29acf763158c85 /meta-rcar-gen3-adas/recipes-bsp
parentcab418c222a69d570913df84ff906d5c4493c453 (diff)
RDRIVE: fix console hang on SCIF1
RDRIVE uses console on SCIF1. Since IPL code removed SCIF1 clock enablement then we have to add clock enable in uboot
Diffstat (limited to 'meta-rcar-gen3-adas/recipes-bsp')
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch26
1 files changed, 24 insertions, 2 deletions
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch
index 479f23f..ecbbfea 100644
--- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch
@@ -8,8 +8,9 @@ This is only for H3ULCB.HAD
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
- include/configs/h3ulcb.h | 4 ++--
- 1 file changed, 1 insertions(+), 1 deletions(-)
+ include/configs/h3ulcb.h | 4 ++--
+ board/renesas/ulcb/ulcb.c | 3 +++
+ 2 file changed, 4 insertions(+), 1 deletions(-)
diff --git a/include/configs/h3ulcb.h b/include/configs/h3ulcb.h
index b9be845..3da2e5a 100644
@@ -23,6 +24,27 @@ index b9be845..3da2e5a 100644
+#define CONFIG_CONS_SCIF1
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
+diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
+index 0d8752f..1be01cf 100644
+--- a/board/renesas/ulcb/ulcb.c
++++ b/board/renesas/ulcb/ulcb.c
+@@ -29,6 +29,7 @@
+
+ DECLARE_GLOBAL_DATA_PTR;
+
++#define SCIF1_MSTP206 (1 << 6)
+ #define SCIF2_MSTP310 (1 << 10)
+ #define ETHERAVB_MSTP812 (1 << 12)
+ #define DVFS_MSTP926 (1 << 26)
+@@ -49,6 +50,8 @@ int board_early_init_f(void)
+
+ rcar_prr_init();
+
++ /* SCIF1 */
++ mstp_clrbits_le32(SMSTPCR2, SMSTPCR2, SCIF1_MSTP206);
+ /* SCIF2 */
+ mstp_clrbits_le32(SMSTPCR3, SMSTPCR3, SCIF2_MSTP310);
+ /* EHTERAVB */
--
1.9.1