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authorHarunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>2018-04-27 14:30:40 +0900
committerHarunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>2018-04-27 14:30:40 +0900
commitf8fb4a95d6f0ca9a92d3b9155e54ac1f3695a20d (patch)
tree7f5a50447e8a940b274c53581dc8af01e2fe0db6 /meta-rcar-gen3-adas/recipes-bsp
parent2e1a7e39e012ea4436c819f46cfcac05fb161184 (diff)
parentf4fad8b9a0d29946c39bb760b76bc9c16448555a (diff)
Merge remote-tracking branch 'cogent/v2.23.1' into sandbox/kingfisher_v2.23.1.20180427
Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> Conflicts: meta-rcar-gen3-adas/conf/layer.conf meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/ulcb.cfg meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend meta-rcar-gen3-adas/recipes-multimedia/pulseaudio/pulseaudio_8.0.bbappend Change-Id: Ib0345634b8bec6a85357152138355d8f932bafc0
Diffstat (limited to 'meta-rcar-gen3-adas/recipes-bsp')
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/alsa-state/alsa-state.bbappend1
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/alsa-state/alsa-state/h3ulcb/asound.state321
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bbappend15
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0003-plat-renesas-rcar-V3M-support.patch41
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0004-plat-renesas-rcar-V3H-support.patch2551
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/br-test/br-test.bb23
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/br-test/files/br-test.tar.gzbin0 -> 2569 bytes
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/cr7-loader/cr7-loader_git.bb47
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/spidev-test/files/spidev-test.tar.gzbin0 -> 6242 bytes
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/spidev-test/spidev-test_1.0.bb21
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0012-ARM-rcar_gen3-Add-I2C-definitions.patch32
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/00121-i2c-rcar_i2c-add-16bit-addressing.patch88
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch25
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0015-board-renesas-Add-V3M-Eagle-board.patch130
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch56
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0018-arm-renesas-Add-Renesas-R8A7798-SoC-support.patch3945
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0019-board-renesas-Add-Condor-board.patch560
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0020-board-renesas-Add-V3MZF-board.patch477
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/00201-board-renesas-Add-V3HSK-board.patch697
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0021-ARM-rcar_gen3-Add-RPC-flash-definitions.patch4
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot_2015.04.bbappend6
21 files changed, 8944 insertions, 96 deletions
diff --git a/meta-rcar-gen3-adas/recipes-bsp/alsa-state/alsa-state.bbappend b/meta-rcar-gen3-adas/recipes-bsp/alsa-state/alsa-state.bbappend
new file mode 100644
index 0000000..311e911
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-bsp/alsa-state/alsa-state.bbappend
@@ -0,0 +1 @@
+FILESEXTRAPATHS_prepend_h3ulcb := "${THISDIR}/${PN}/h3ulcb:"
diff --git a/meta-rcar-gen3-adas/recipes-bsp/alsa-state/alsa-state/h3ulcb/asound.state b/meta-rcar-gen3-adas/recipes-bsp/alsa-state/alsa-state/h3ulcb/asound.state
new file mode 100644
index 0000000..b52ef26
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-bsp/alsa-state/alsa-state/h3ulcb/asound.state
@@ -0,0 +1,321 @@
+state.ak4613 {
+ control.1 {
+ iface MIXER
+ name 'Digital Playback Volume1'
+ value.0 255
+ value.1 255
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 255'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.2 {
+ iface MIXER
+ name 'Digital Playback Volume2'
+ value.0 255
+ value.1 255
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 255'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.3 {
+ iface MIXER
+ name 'Digital Playback Volume3'
+ value.0 255
+ value.1 255
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 255'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.4 {
+ iface MIXER
+ name 'Digital Playback Volume4'
+ value.0 255
+ value.1 255
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 255'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.5 {
+ iface MIXER
+ name 'Digital Playback Volume5'
+ value.0 255
+ value.1 255
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 255'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.6 {
+ iface MIXER
+ name 'Digital Playback Volume6'
+ value.0 255
+ value.1 255
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 255'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.7 {
+ iface MIXER
+ name 'DVC Out Playback Volume'
+ value.0 7885285
+ value.1 7885285
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 8388607'
+ }
+ }
+ control.8 {
+ iface MIXER
+ name 'DVC Out Mute Switch'
+ value.0 false
+ value.1 false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.9 {
+ iface MIXER
+ name 'DVC Out Ramp Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.10 {
+ iface MIXER
+ name 'DVC Out Ramp Up Rate'
+ value '128 dB/1 step'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 '128 dB/1 step'
+ item.1 '64 dB/1 step'
+ item.2 '32 dB/1 step'
+ item.3 '16 dB/1 step'
+ item.4 '8 dB/1 step'
+ item.5 '4 dB/1 step'
+ item.6 '2 dB/1 step'
+ item.7 '1 dB/1 step'
+ item.8 '0.5 dB/1 step'
+ item.9 '0.25 dB/1 step'
+ item.10 '0.125 dB/1 step'
+ item.11 '0.125 dB/2 steps'
+ item.12 '0.125 dB/4 steps'
+ item.13 '0.125 dB/8 steps'
+ item.14 '0.125 dB/16 steps'
+ item.15 '0.125 dB/32 steps'
+ item.16 '0.125 dB/64 steps'
+ item.17 '0.125 dB/128 steps'
+ item.18 '0.125 dB/256 steps'
+ item.19 '0.125 dB/512 steps'
+ item.20 '0.125 dB/1024 steps'
+ item.21 '0.125 dB/2048 steps'
+ item.22 '0.125 dB/4096 steps'
+ item.23 '0.125 dB/8192 steps'
+ }
+ }
+ control.11 {
+ iface MIXER
+ name 'DVC Out Ramp Down Rate'
+ value '128 dB/1 step'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 '128 dB/1 step'
+ item.1 '64 dB/1 step'
+ item.2 '32 dB/1 step'
+ item.3 '16 dB/1 step'
+ item.4 '8 dB/1 step'
+ item.5 '4 dB/1 step'
+ item.6 '2 dB/1 step'
+ item.7 '1 dB/1 step'
+ item.8 '0.5 dB/1 step'
+ item.9 '0.25 dB/1 step'
+ item.10 '0.125 dB/1 step'
+ item.11 '0.125 dB/2 steps'
+ item.12 '0.125 dB/4 steps'
+ item.13 '0.125 dB/8 steps'
+ item.14 '0.125 dB/16 steps'
+ item.15 '0.125 dB/32 steps'
+ item.16 '0.125 dB/64 steps'
+ item.17 '0.125 dB/128 steps'
+ item.18 '0.125 dB/256 steps'
+ item.19 '0.125 dB/512 steps'
+ item.20 '0.125 dB/1024 steps'
+ item.21 '0.125 dB/2048 steps'
+ item.22 '0.125 dB/4096 steps'
+ item.23 '0.125 dB/8192 steps'
+ }
+ }
+ control.12 {
+ iface MIXER
+ name 'SRC Out Rate Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.13 {
+ iface MIXER
+ name 'SRC Out Rate'
+ value 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 192000'
+ }
+ }
+ control.14 {
+ iface MIXER
+ name 'DVC In Capture Volume'
+ value.0 6388607
+ value.1 6388607
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 8388607'
+ }
+ }
+ control.15 {
+ iface MIXER
+ name 'DVC In Mute Switch'
+ value.0 false
+ value.1 false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.16 {
+ iface MIXER
+ name 'DVC In Ramp Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.17 {
+ iface MIXER
+ name 'DVC In Ramp Up Rate'
+ value '128 dB/1 step'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 '128 dB/1 step'
+ item.1 '64 dB/1 step'
+ item.2 '32 dB/1 step'
+ item.3 '16 dB/1 step'
+ item.4 '8 dB/1 step'
+ item.5 '4 dB/1 step'
+ item.6 '2 dB/1 step'
+ item.7 '1 dB/1 step'
+ item.8 '0.5 dB/1 step'
+ item.9 '0.25 dB/1 step'
+ item.10 '0.125 dB/1 step'
+ item.11 '0.125 dB/2 steps'
+ item.12 '0.125 dB/4 steps'
+ item.13 '0.125 dB/8 steps'
+ item.14 '0.125 dB/16 steps'
+ item.15 '0.125 dB/32 steps'
+ item.16 '0.125 dB/64 steps'
+ item.17 '0.125 dB/128 steps'
+ item.18 '0.125 dB/256 steps'
+ item.19 '0.125 dB/512 steps'
+ item.20 '0.125 dB/1024 steps'
+ item.21 '0.125 dB/2048 steps'
+ item.22 '0.125 dB/4096 steps'
+ item.23 '0.125 dB/8192 steps'
+ }
+ }
+ control.18 {
+ iface MIXER
+ name 'DVC In Ramp Down Rate'
+ value '128 dB/1 step'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 '128 dB/1 step'
+ item.1 '64 dB/1 step'
+ item.2 '32 dB/1 step'
+ item.3 '16 dB/1 step'
+ item.4 '8 dB/1 step'
+ item.5 '4 dB/1 step'
+ item.6 '2 dB/1 step'
+ item.7 '1 dB/1 step'
+ item.8 '0.5 dB/1 step'
+ item.9 '0.25 dB/1 step'
+ item.10 '0.125 dB/1 step'
+ item.11 '0.125 dB/2 steps'
+ item.12 '0.125 dB/4 steps'
+ item.13 '0.125 dB/8 steps'
+ item.14 '0.125 dB/16 steps'
+ item.15 '0.125 dB/32 steps'
+ item.16 '0.125 dB/64 steps'
+ item.17 '0.125 dB/128 steps'
+ item.18 '0.125 dB/256 steps'
+ item.19 '0.125 dB/512 steps'
+ item.20 '0.125 dB/1024 steps'
+ item.21 '0.125 dB/2048 steps'
+ item.22 '0.125 dB/4096 steps'
+ item.23 '0.125 dB/8192 steps'
+ }
+ }
+}
diff --git a/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bbappend b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bbappend
index d2ac495..0bf05d1 100644
--- a/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bbappend
+++ b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bbappend
@@ -2,7 +2,11 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
COMPATIBLE_MACHINE_eagle = "eagle"
COMPATIBLE_MACHINE_v3msk = "v3msk"
+COMPATIBLE_MACHINE_v3mzf = "v3mzf"
+COMPATIBLE_MACHINE_condor = "condor"
+COMPATIBLE_MACHINE_v3hsk = "v3hsk"
ATFW_OPT_r8a7797 = "LSI=V3M RCAR_DRAM_SPLIT=0 RCAR_LOSSY_ENABLE=0 PMIC_ROHM_BD9571=0 RCAR_SYSTEM_SUSPEND=0 SPD=none"
+ATFW_OPT_r8a7798 = "LSI=V3H RCAR_DRAM_SPLIT=0 RCAR_LOSSY_ENABLE=0 PMIC_ROHM_BD9571=0 RCAR_SYSTEM_SUSPEND=0 SPD=none RCAR_SECURE_BOOT=0"
ATFW_OPT_append = " ${@base_conditional("CA57CA53BOOT", "1", " PSCI_DISABLE_BIGLITTLE_IN_CA57BOOT=0", "", d)}"
ATFW_OPT_append += " ${@base_conditional("DISABLE_RPC_ACCESS", "1", " RCAR_DISABLE_NONSECURE_RPC_ACCESS=1", "", d)}"
@@ -12,9 +16,20 @@ SRC_URI_append = " \
file://0001-plat-renesas-rcar-Make-RPC-secure-settings-optional.patch \
file://0002-plat-renesas-rcar-kingfisher-reboot-fix-power-off-on-reset.diff \
file://0003-plat-renesas-rcar-V3M-support.patch \
+ file://0004-plat-renesas-rcar-V3H-support.patch \
"
do_deploy_append() {
install -m 0644 ${S}/tools/dummy_create/bootparam_sa0.bin ${DEPLOYDIR}/bootparam_sa0.bin
install -m 0644 ${S}/tools/dummy_create/cert_header_sa6.bin ${DEPLOYDIR}/cert_header_sa6.bin
}
+
+do_deploy_append_r8a7797() {
+ rm ${DEPLOYDIR}/bootparam_sa0.bin
+ rm ${DEPLOYDIR}/bootparam_sa0.srec
+}
+
+do_deploy_append_r8a7798() {
+ rm ${DEPLOYDIR}/bootparam_sa0.bin
+ rm ${DEPLOYDIR}/bootparam_sa0.srec
+}
diff --git a/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0003-plat-renesas-rcar-V3M-support.patch b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0003-plat-renesas-rcar-V3M-support.patch
index 822895a..292f5fe 100644
--- a/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0003-plat-renesas-rcar-V3M-support.patch
+++ b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0003-plat-renesas-rcar-V3M-support.patch
@@ -20,6 +20,7 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
plat/renesas/rcar/drivers/rom/rom_api.c | 18 +-
plat/renesas/rcar/drivers/scif/scif.S | 29 +-
plat/renesas/rcar/include/bl2_dma_register.h | 4 +
+ plat/renesas/rcar/include/platform_def.h | 6 +
plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c | 1076 ++++++++++++++++++++
plat/renesas/rcar/pfc/V3M/pfc_init_v3m.h | 37 +
plat/renesas/rcar/pfc/pfc.mk | 7 +
@@ -29,8 +30,8 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
plat/renesas/rcar/qos/V3M/qos_init_v3m.h | 37 +
plat/renesas/rcar/qos/qos.mk | 7 +
plat/renesas/rcar/qos/qos_init.c | 25 +
- plat/renesas/rcar/rcar_def.h | 1 +
- 23 files changed, 2490 insertions(+), 13 deletions(-)
+ plat/renesas/rcar/rcar_def.h | 5 +
+ 24 files changed, 2500 insertions(+), 13 deletions(-)
mode change 100644 => 100755 plat/renesas/rcar/bl2_rcar_setup.c
create mode 100644 plat/renesas/rcar/ddr/V3M/boot_init_dram_regdef_v3m.h
create mode 100644 plat/renesas/rcar/ddr/V3M/boot_init_dram_v3m.h
@@ -1169,6 +1170,26 @@ index 7c7e7a8..4bc9341 100644
#if (DMACH==0) /* SYS-DMAC0 (CH0) */
#define SYS_DMAC_BIT ((uint32_t)1U << 19U)
+diff --git a/plat/renesas/rcar/include/platform_def.h b/plat/renesas/rcar/include/platform_def.h
+index ae5dfab..59685c1 100644
+--- a/plat/renesas/rcar/include/platform_def.h
++++ b/plat/renesas/rcar/include/platform_def.h
+@@ -149,9 +149,15 @@
+ * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
+ * size plus a little space for growth.
+ */
++#if RCAR_LSI == RCAR_V3M
++#define RCAR_SECRAM_BASE (0xE6300000)
++#define BL2_BASE (0xE6344000)
++#define BL2_LIMIT (0xE636E800)
++#else
+ #define RCAR_SECRAM_BASE (0xE6300000)
+ #define BL2_BASE (0xE6304000)
+ #define BL2_LIMIT (0xE632E800)
++#endif
+
+ /*******************************************************************************
+ * BL31 specific defines.
diff --git a/plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c b/plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c
new file mode 100644
index 0000000..0344189
@@ -2989,10 +3010,22 @@ index ca0f311..86ee492 100644
#error "Don't have QoS initialize routine(Unknown chip)."
#endif
diff --git a/plat/renesas/rcar/rcar_def.h b/plat/renesas/rcar/rcar_def.h
-index 03e0f14..103f754 100644
+index 03e0f14..ddbca3b 100644
--- a/plat/renesas/rcar/rcar_def.h
+++ b/plat/renesas/rcar/rcar_def.h
-@@ -255,6 +255,7 @@
+@@ -79,7 +79,11 @@
+ #define DEVICE_RCAR_BASE 0xE6000000U
+ #define DEVICE_RCAR_SIZE 0x00300000U
+
++#if RCAR_LSI == RCAR_V3M
++#define DEVICE_RCAR_BASE2 MAKE_U(0xE6370000)
++#else
+ #define DEVICE_RCAR_BASE2 MAKE_U(0xE6360000)
++#endif
+ #define DEVICE_RCAR_SIZE2 0x19CA0000U
+
+ #define DEVICE_SRAM_BASE 0xE6310000
+@@ -255,6 +259,7 @@
#define RCAR_CUT_MASK (0x000000FFU)
#define RCAR_PRODUCT_H3 (0x00004F00U)
#define RCAR_PRODUCT_M3 (0x00005200U)
diff --git a/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0004-plat-renesas-rcar-V3H-support.patch b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0004-plat-renesas-rcar-V3H-support.patch
new file mode 100644
index 0000000..5d6d1ae
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0004-plat-renesas-rcar-V3H-support.patch
@@ -0,0 +1,2551 @@
+From 2259b001b23c4328ec197604a2d430dcf3c3f78a Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Sat, 10 Feb 2018 00:52:28 +0300
+Subject: [PATCH] plat: renesas: rcar: V3H support
+
+This adds R-Car V3H support.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+---
+ plat/renesas/rcar/bl2_cpg_init.c | 68 ++
+ plat/renesas/rcar/bl2_rcar_setup.c | 11 +-
+ plat/renesas/rcar/ddr/boot_init_dram.c | 7 +
+ plat/renesas/rcar/drivers/rom/rom_api.c | 17 +-
+ plat/renesas/rcar/drivers/scif/scif.S | 2 +-
+ plat/renesas/rcar/include/bl2_dma_register.h | 2 +-
+ plat/renesas/rcar/include/platform_def.h | 4 +
+ plat/renesas/rcar/pfc/V3H/pfc_init_v3h.c | 1196 ++++++++++++++++++++++++++
+ plat/renesas/rcar/pfc/V3H/pfc_init_v3h.h | 37 +
+ plat/renesas/rcar/pfc/pfc.mk | 7 +
+ plat/renesas/rcar/pfc/pfc_init.c | 21 +
+ plat/renesas/rcar/platform.mk | 18 +
+ plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.c | 651 ++++++++++++++
+ plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.h | 37 +
+ plat/renesas/rcar/qos/qos.mk | 7 +
+ plat/renesas/rcar/qos/qos_init.c | 26 +
+ plat/renesas/rcar/rcar_def.h | 3 +-
+ tools/dummy_create/makefile | 5 +
+ 18 files changed, 2113 insertions(+), 6 deletions(-)
+ create mode 100644 plat/renesas/rcar/pfc/V3H/pfc_init_v3h.c
+ create mode 100644 plat/renesas/rcar/pfc/V3H/pfc_init_v3h.h
+ create mode 100644 plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.c
+ create mode 100644 plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.h
+
+diff --git a/plat/renesas/rcar/bl2_cpg_init.c b/plat/renesas/rcar/bl2_cpg_init.c
+index 3b424e0..9e945a0 100644
+--- a/plat/renesas/rcar/bl2_cpg_init.c
++++ b/plat/renesas/rcar/bl2_cpg_init.c
+@@ -52,6 +52,10 @@ static void bl2_system_cpg_init_m3n(void);
+ static void bl2_realtime_cpg_init_v3m(void);
+ static void bl2_system_cpg_init_v3m(void);
+ #endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M) */
++#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3H)
++static void bl2_realtime_cpg_init_v3h(void);
++static void bl2_system_cpg_init_v3h(void);
++#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3H) */
+
+ typedef struct {
+ uintptr_t adr;
+@@ -367,6 +371,60 @@ static void bl2_system_cpg_init_v3m(void)
+ }
+ #endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M) */
+
++#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3H)
++static void bl2_realtime_cpg_init_v3h(void)
++{
++ /* CPG (REALTIME) registers */
++
++ /* Realtime Module Stop Control Register 0 */
++ cpg_write(RMSTPCR0, 0x00230000U);
++ /* Realtime Module Stop Control Register 1 */
++ cpg_write(RMSTPCR1, 0xFFFFFFFFU);
++ /* Realtime Module Stop Control Register 2 */
++ cpg_write(RMSTPCR2, 0x14062FD8U);
++ /* Realtime Module Stop Control Register 3 */
++ cpg_write(RMSTPCR3, 0xFFFFFFDFU);
++ /* Realtime Module Stop Control Register 4 */
++ cpg_write(RMSTPCR4, 0x80000184U);
++ /* Realtime Module Stop Control Register 5 */
++ cpg_write(RMSTPCR5, 0x83FFFFFFU);
++ /* Realtime Module Stop Control Register 6 */
++ cpg_write(RMSTPCR6, 0xFFFFFFFFU);
++ /* Realtime Module Stop Control Register 7 */
++ cpg_write(RMSTPCR7, 0xFFFFFFFFU);
++ /* Realtime Module Stop Control Register 8 */
++ cpg_write(RMSTPCR8, 0x7FF3FFF4U);
++ /* Realtime Module Stop Control Register 9 */
++ cpg_write(RMSTPCR9, 0xFFFFFFFEU);
++}
++
++static void bl2_system_cpg_init_v3h(void)
++{
++ /* CPG (SYSTEM) registers */
++
++ /* System Module Stop Control Register 0 */
++ cpg_write(SMSTPCR0, 0x00210000U);
++ /* System Module Stop Control Register 1 */
++ cpg_write(SMSTPCR1, 0xFFFFFFFFU);
++ /* System Module Stop Control Register 2 */
++ cpg_write(SMSTPCR2, 0x340E2FDCU);
++ /* System Module Stop Control Register 3 */
++ cpg_write(SMSTPCR3, 0xFFFFFBDFU);
++ /* System Module Stop Control Register 4 */
++ cpg_write(SMSTPCR4, 0x80000004U);
++ /* System Module Stop Control Register 5 */
++ cpg_write(SMSTPCR5, 0xC3FFFFFFU);
++ /* System Module Stop Control Register 6 */
++ cpg_write(SMSTPCR6, 0xFFFFFFFFU);
++ /* System Module Stop Control Register 7 */
++ cpg_write(SMSTPCR7, 0xFFFFFFFFU);
++ /* System Module Stop Control Register 8 */
++ cpg_write(SMSTPCR8, 0x01F1FFF5U);
++ /* System Module Stop Control Register 9 */
++ cpg_write(SMSTPCR9, 0xFFFFFFFEU);
++}
++#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3H) */
++
+ void bl2_cpg_init(void)
+ {
+ uint32_t modemr;
+@@ -398,6 +456,9 @@ void bl2_cpg_init(void)
+ case RCAR_PRODUCT_v3m:
+ bl2_realtime_cpg_init_v3m();
+ break;
++ case RCAR_PRODUCT_v3h:
++ bl2_realtime_cpg_init_v3h();
++ break;
+ default:
+ panic();
+ break;
+@@ -410,6 +471,8 @@ void bl2_cpg_init(void)
+ bl2_realtime_cpg_init_m3n();
+ #elif RCAR_LSI == RCAR_V3M
+ bl2_realtime_cpg_init_v3m();
++#elif RCAR_LSI == RCAR_V3H
++ bl2_realtime_cpg_init_v3h();
+ #else /* RCAR_LSI == RCAR_XX */
+ #error "Don't have CPG initialize routine(unknown)."
+ #endif /* RCAR_LSI == RCAR_XX */
+@@ -435,6 +498,9 @@ void bl2_system_cpg_init(void)
+ case RCAR_PRODUCT_V3M:
+ bl2_system_cpg_init_v3m();
+ break;
++ case RCAR_PRODUCT_V3H:
++ bl2_system_cpg_init_v3h();
++ break;
+ default:
+ panic();
+ break;
+@@ -447,6 +513,8 @@ void bl2_system_cpg_init(void)
+ bl2_system_cpg_init_m3n();
+ #elif RCAR_LSI == RCAR_V3M
+ bl2_system_cpg_init_v3m();
++#elif RCAR_LSI == RCAR_V3H
++ bl2_system_cpg_init_v3h();
+ #else /* RCAR_LSI == RCAR_XX */
+ #error "Don't have CPG initialize routine(unknown)."
+ #endif /* RCAR_LSI == RCAR_XX */
+diff --git a/plat/renesas/rcar/bl2_rcar_setup.c b/plat/renesas/rcar/bl2_rcar_setup.c
+index 19f887c..ffa5e3c 100755
+--- a/plat/renesas/rcar/bl2_rcar_setup.c
++++ b/plat/renesas/rcar/bl2_rcar_setup.c
+@@ -141,6 +141,9 @@
+ #elif RCAR_LSI == RCAR_V3M
+ #define TARGET_PRODUCT RCAR_PRODUCT_V3M
+ #define TARGET_NAME "R-Car V3M"
++#elif RCAR_LSI == RCAR_V3H
++#define TARGET_PRODUCT RCAR_PRODUCT_V3H
++#define TARGET_NAME "R-Car V3H"
+ #endif
+
+ /* for SuspendToRAM */
+@@ -392,6 +395,7 @@ void bl2_early_platform_setup(meminfo_t *mem_layout)
+ const char *product_m3 = "M3";
+ const char *product_m3n = "M3N";
+ const char *product_v3m = "V3M";
++ const char *product_v3h = "V3H";
+ const char *lcs_cm = "CM";
+ const char *lcs_dm = "DM";
+ const char *lcs_sd = "SD";
+@@ -469,6 +473,9 @@ void bl2_early_platform_setup(meminfo_t *mem_layout)
+ case RCAR_PRODUCT_V3M:
+ str = product_v3m;
+ break;
++ case RCAR_PRODUCT_V3H:
++ str = product_v3h;
++ break;
+ default:
+ str = unknown;
+ break;
+@@ -513,7 +520,7 @@ void bl2_early_platform_setup(meminfo_t *mem_layout)
+ }
+ #endif /* RCAR_LSI != RCAR_AUTO */
+
+-#if RCAR_LSI != RCAR_V3M
++#if (RCAR_LSI != RCAR_V3M) && (RCAR_LSI != RCAR_V3H)
+ /* Initialize AVS Settings */
+ bl2_avs_init();
+
+@@ -547,7 +554,7 @@ void bl2_early_platform_setup(meminfo_t *mem_layout)
+ (void)sprintf(msg, "BL2: Boot device is %s\n", str);
+ NOTICE("%s", msg);
+
+-#if RCAR_LSI != RCAR_V3M
++#if (RCAR_LSI != RCAR_V3M) && (RCAR_LSI != RCAR_V3H)
+ /* Proceed with separated AVS processing */
+ bl2_avs_setting();
+ #endif
+diff --git a/plat/renesas/rcar/ddr/boot_init_dram.c b/plat/renesas/rcar/ddr/boot_init_dram.c
+index 87360a6..28b0a9f 100644
+--- a/plat/renesas/rcar/ddr/boot_init_dram.c
++++ b/plat/renesas/rcar/ddr/boot_init_dram.c
+@@ -3594,6 +3594,13 @@ int32_t InitDram(void)
+ }
+ #endif
+
++#if RCAR_LSI == RCAR_V3H
++ if (Prr_Product == PRR_PRODUCT_V3H) {
++ /* dram initialized by CR7 */
++ return INITDRAM_OK;
++ }
++#endif
++
+ if (Prr_Product == PRR_PRODUCT_H3) {
+ if(PRR_PRODUCT_11>=Prr_Cut){
+ pDDR_REGDEF_TBL = (uint32_t *)&DDR_REGDEF_TBL[0][0];
+diff --git a/plat/renesas/rcar/drivers/rom/rom_api.c b/plat/renesas/rcar/drivers/rom/rom_api.c
+index 186660d..812f6a9 100644
+--- a/plat/renesas/rcar/drivers/rom/rom_api.c
++++ b/plat/renesas/rcar/drivers/rom/rom_api.c
+@@ -54,7 +54,8 @@ static uint32_t get_table_index(void);
+ #define OLD_API_TABLE3 (2U) /* M3 WS1.0/1.05 */
+ #define NEW_API_TABLE (3U) /* M3 WS1.06 or later, M3N, E3, V3M WS2.0 */
+ #define NEW_API_TABLE2 (4U) /* V3M WS1.0 */
+-#define API_TABLE_MAX (5U) /* table max */
++#define NEW_API_TABLE3 (5U) /* V3H WS1.0 */
++#define API_TABLE_MAX (6U) /* table max */
+
+
+
+@@ -69,6 +70,7 @@ uint32_t ROM_SecureBootAPI( uint32_t *pKeyCert,
+ 0xEB1102FCU, /* M3 WS1.0/1.05 */
+ 0xEB100180U, /* M3 WS1.06 or later, M3N, E3, V3M WS2.0 */
+ 0xEB110128U, /* V3M WS1.0 */
++ 0xEB101960U, /* V3H WS1.0 */
+ };
+
+ ROM_SECURE_BOOT_API func;
+@@ -83,6 +85,10 @@ uint32_t ROM_SecureBootAPI( uint32_t *pKeyCert,
+
+ uint32_t ROM_GetLcs(uint32_t *pLcs)
+ {
++#if RCAR_LSI == RCAR_V3H
++ *pLcs = 0xff;
++ return 0;
++#else
+ /* Get LCS stete API address table */
+ static const uintptr_t ROM_GetLcs_table[API_TABLE_MAX] = {
+ 0xEB10DFE0U, /* H3 WS1.0/WS1.1 */
+@@ -90,6 +96,7 @@ uint32_t ROM_GetLcs(uint32_t *pLcs)
+ 0xEB110578U, /* M3 WS1.0/1.05 */
+ 0xEB10018CU, /* M3 WS1.06 or later, M3N, E3, V3M WS2.0 */
+ 0xEB1103A4U, /* V3M WS1.0 */
++ 0xEB101940U, /* V3H WS1.0 */
+ };
+
+ ROM_GETLCS_API func;
+@@ -99,6 +106,7 @@ uint32_t ROM_GetLcs(uint32_t *pLcs)
+ func = (ROM_GETLCS_API)ROM_GetLcs_table[index];
+
+ return func(pLcs);
++#endif
+ }
+
+
+@@ -145,6 +153,13 @@ static uint32_t get_table_index(void)
+ index = NEW_API_TABLE; /* V3M WS2.0 or later */
+ }
+ break;
++ case RCAR_PRODUCT_V3H:
++ if (cut_ver == RCAR_CUT_ES10) {
++ index = NEW_API_TABLE3; /* V3H WS1.0 */
++ } else {
++ index = NEW_API_TABLE3; /* */
++ }
++ break;
+ default:
+ index = NEW_API_TABLE; /* assume that M3N and E3 */
+ break;
+diff --git a/plat/renesas/rcar/drivers/scif/scif.S b/plat/renesas/rcar/drivers/scif/scif.S
+index bb9bfef..5349478 100644
+--- a/plat/renesas/rcar/drivers/scif/scif.S
++++ b/plat/renesas/rcar/drivers/scif/scif.S
+@@ -50,7 +50,7 @@
+ #define SCIF0_BASE (0xE6E60000) /* SCIF-0 base address */
+ #define SCIF2_BASE (0xE6E88000) /* SCIF-2 base address */
+
+-#if RCAR_LSI == RCAR_V3M /* V3M */
++#if (RCAR_LSI == RCAR_V3M) || (RCAR_LSI == RCAR_V3H) /* V3M/V3H */
+ #define SCIF_BASE SCIF0_BASE
+ #define CPG_SMSTPCR CPG_SMSTPCR2
+ #define MSTP MSTP207
+diff --git a/plat/renesas/rcar/include/bl2_dma_register.h b/plat/renesas/rcar/include/bl2_dma_register.h
+index 4bc9341..195515a 100644
+--- a/plat/renesas/rcar/include/bl2_dma_register.h
++++ b/plat/renesas/rcar/include/bl2_dma_register.h
+@@ -32,7 +32,7 @@
+ #ifndef BL2_DMA_REGISTER_H__
+ #define BL2_DMA_REGISTER_H__
+
+-#if RCAR_LSI == RCAR_V3M /* V3M */
++#if (RCAR_LSI == RCAR_V3M) || (RCAR_LSI == RCAR_V3H) /* V3M/V3H */
+ #define DMACH 16 /* DMA CH setting (0/16/32) */
+ #else
+ #define DMACH 0 /* DMA CH setting (0/16/32) */
+diff --git a/plat/renesas/rcar/include/platform_def.h b/plat/renesas/rcar/include/platform_def.h
+index 59685c1..edaa59f 100644
+--- a/plat/renesas/rcar/include/platform_def.h
++++ b/plat/renesas/rcar/include/platform_def.h
+@@ -153,6 +153,10 @@
+ #define RCAR_SECRAM_BASE (0xE6300000)
+ #define BL2_BASE (0xE6344000)
+ #define BL2_LIMIT (0xE636E800)
++#elif RCAR_LSI == RCAR_V3H
++#define RCAR_SECRAM_BASE (0xEB200000)
++#define BL2_BASE (0xEB244000)
++#define BL2_LIMIT (0xEB26E800)
+ #else
+ #define RCAR_SECRAM_BASE (0xE6300000)
+ #define BL2_BASE (0xE6304000)
+diff --git a/plat/renesas/rcar/pfc/V3H/pfc_init_v3h.c b/plat/renesas/rcar/pfc/V3H/pfc_init_v3h.c
+new file mode 100644
+index 0000000..351747a
+--- /dev/null
++++ b/plat/renesas/rcar/pfc/V3H/pfc_init_v3h.c
+@@ -0,0 +1,1196 @@
++/*
++ * Copyright (c) 2015-2017, Renesas Electronics Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * - Redistributions of source code must retain the above copyright notice,
++ * this list of conditions and the following disclaimer.
++ *
++ * - Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ *
++ * - Neither the name of Renesas nor the names of its contributors may be
++ * used to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <stdint.h> /* for uint32_t */
++#include <mmio.h>
++#include "pfc_init_v3h.h"
++
++
++/* GPIO base address */
++#define GPIO_BASE (0xE6050000U)
++
++/* GPIO registers */
++#define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U)
++#define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U)
++#define GPIO_OUTDT0 (GPIO_BASE + 0x0008U)
++#define GPIO_INDT0 (GPIO_BASE + 0x000CU)
++#define GPIO_INTDT0 (GPIO_BASE + 0x0010U)
++#define GPIO_INTCLR0 (GPIO_BASE + 0x0014U)
++#define GPIO_INTMSK0 (GPIO_BASE + 0x0018U)
++#define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU)
++#define GPIO_POSNEG0 (GPIO_BASE + 0x0020U)
++#define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U)
++#define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U)
++#define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U)
++#define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU)
++#define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U)
++#define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U)
++#define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U)
++#define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU)
++#define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U)
++#define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U)
++#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U)
++#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
++#define GPIO_INTDT1 (GPIO_BASE + 0x1010U)
++#define GPIO_INTCLR1 (GPIO_BASE + 0x1014U)
++#define GPIO_INTMSK1 (GPIO_BASE + 0x1018U)
++#define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU)
++#define GPIO_POSNEG1 (GPIO_BASE + 0x1020U)
++#define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U)
++#define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U)
++#define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U)
++#define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU)
++#define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U)
++#define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U)
++#define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U)
++#define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU)
++#define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U)
++#define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U)
++#define GPIO_OUTDT2 (GPIO_BASE + 0x2008U)
++#define GPIO_INDT2 (GPIO_BASE + 0x200CU)
++#define GPIO_INTDT2 (GPIO_BASE + 0x2010U)
++#define GPIO_INTCLR2 (GPIO_BASE + 0x2014U)
++#define GPIO_INTMSK2 (GPIO_BASE + 0x2018U)
++#define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU)
++#define GPIO_POSNEG2 (GPIO_BASE + 0x2020U)
++#define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U)
++#define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U)
++#define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U)
++#define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU)
++#define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U)
++#define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U)
++#define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U)
++#define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU)
++#define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U)
++#define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U)
++#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U)
++#define GPIO_INDT3 (GPIO_BASE + 0x300CU)
++#define GPIO_INTDT3 (GPIO_BASE + 0x3010U)
++#define GPIO_INTCLR3 (GPIO_BASE + 0x3014U)
++#define GPIO_INTMSK3 (GPIO_BASE + 0x3018U)
++#define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU)
++#define GPIO_POSNEG3 (GPIO_BASE + 0x3020U)
++#define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U)
++#define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U)
++#define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U)
++#define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU)
++#define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U)
++#define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U)
++#define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U)
++#define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU)
++#define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U)
++#define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U)
++#define GPIO_OUTDT4 (GPIO_BASE + 0x4008U)
++#define GPIO_INDT4 (GPIO_BASE + 0x400CU)
++#define GPIO_INTDT4 (GPIO_BASE + 0x4010U)
++#define GPIO_INTCLR4 (GPIO_BASE + 0x4014U)
++#define GPIO_INTMSK4 (GPIO_BASE + 0x4018U)
++#define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU)
++#define GPIO_POSNEG4 (GPIO_BASE + 0x4020U)
++#define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U)
++#define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U)
++#define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U)
++#define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU)
++#define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U)
++#define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U)
++#define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U)
++#define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU)
++#define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U)
++#define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U)
++#define GPIO_OUTDT5 (GPIO_BASE + 0x5008U)
++#define GPIO_INDT5 (GPIO_BASE + 0x500CU)
++#define GPIO_INTDT5 (GPIO_BASE + 0x5010U)
++#define GPIO_INTCLR5 (GPIO_BASE + 0x5014U)
++#define GPIO_INTMSK5 (GPIO_BASE + 0x5018U)
++#define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU)
++#define GPIO_POSNEG5 (GPIO_BASE + 0x5020U)
++#define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U)
++#define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U)
++#define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U)
++#define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU)
++#define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U)
++#define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U)
++#define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U)
++#define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU)
++
++/* Pin functon base address */
++#define PFC_BASE (0xE6060000U)
++
++/* Pin functon registers */
++#define PFC_PMMR (PFC_BASE + 0x0000U)
++#define PFC_GPSR0 (PFC_BASE + 0x0100U)
++#define PFC_GPSR1 (PFC_BASE + 0x0104U)
++#define PFC_GPSR2 (PFC_BASE + 0x0108U)
++#define PFC_GPSR3 (PFC_BASE + 0x010CU)
++#define PFC_GPSR4 (PFC_BASE + 0x0110U)
++#define PFC_GPSR5 (PFC_BASE + 0x0114U)
++#define PFC_IPSR0 (PFC_BASE + 0x0200U)
++#define PFC_IPSR1 (PFC_BASE + 0x0204U)
++#define PFC_IPSR2 (PFC_BASE + 0x0208U)
++#define PFC_IPSR3 (PFC_BASE + 0x020CU)
++#define PFC_IPSR4 (PFC_BASE + 0x0210U)
++#define PFC_IPSR5 (PFC_BASE + 0x0214U)
++#define PFC_IPSR6 (PFC_BASE + 0x0218U)
++#define PFC_IPSR7 (PFC_BASE + 0x021CU)
++#define PFC_IPSR8 (PFC_BASE + 0x0220U)
++#define PFC_IPSR9 (PFC_BASE + 0x0224U)
++#define PFC_IPSR10 (PFC_BASE + 0x0228U)
++#define PFC_IOCTRL0 (PFC_BASE + 0x0300U)
++#define PFC_IOCTRL1 (PFC_BASE + 0x0304U)
++#define PFC_IOCTRL2 (PFC_BASE + 0x0308U)
++#define PFC_IOCTRL3 (PFC_BASE + 0x030CU)
++#define PFC_IOCTRL4 (PFC_BASE + 0x0310U)
++#define PFC_IOCTRL5 (PFC_BASE + 0x0314U)
++#define PFC_IOCTRL6 (PFC_BASE + 0x0318U)
++#define PFC_IOCTRL7 (PFC_BASE + 0x031CU)
++#define PFC_IOCTRL8 (PFC_BASE + 0x0320U)
++#define PFC_IOCTRL9 (PFC_BASE + 0x0324U)
++#define PFC_IOCTRL10 (PFC_BASE + 0x0328U)
++#define PFC_IOCTRL11 (PFC_BASE + 0x032CU)
++#define PFC_IOCTRL12 (PFC_BASE + 0x0330U)
++#define PFC_IOCTRL13 (PFC_BASE + 0x0334U)
++#define PFC_IOCTRL14 (PFC_BASE + 0x0338U)
++#define PFC_IOCTRL15 (PFC_BASE + 0x033CU)
++#define PFC_IOCTRL16 (PFC_BASE + 0x0340U)
++#define PFC_IOCTRL17 (PFC_BASE + 0x0344U)
++#define PFC_IOCTRL18 (PFC_BASE + 0x0348U)
++#define PFC_IOCTRL19 (PFC_BASE + 0x034CU)
++#define PFC_IOCTRL30 (PFC_BASE + 0x0380U)
++#define PFC_IOCTRL31 (PFC_BASE + 0x0384U)
++#define PFC_IOCTRL32 (PFC_BASE + 0x0388U)
++#define PFC_IOCTRL33 (PFC_BASE + 0x038CU)
++#define PFC_IOCTRL40 (PFC_BASE + 0x03C0U)
++#define PFC_TSREG (PFC_BASE + 0x03E4U)
++#define PFC_PUEN0 (PFC_BASE + 0x0400U)
++#define PFC_PUEN1 (PFC_BASE + 0x0404U)
++#define PFC_PUEN2 (PFC_BASE + 0x0408U)
++#define PFC_PUEN3 (PFC_BASE + 0x040CU)
++#define PFC_PUEN4 (PFC_BASE + 0x0410U)
++#define PFC_PUD0 (PFC_BASE + 0x0440U)
++#define PFC_PUD1 (PFC_BASE + 0x0444U)
++#define PFC_PUD2 (PFC_BASE + 0x0448U)
++#define PFC_PUD3 (PFC_BASE + 0x044CU)
++#define PFC_PUD4 (PFC_BASE + 0x0450U)
++#define PFC_MOD_SEL0 (PFC_BASE + 0x0500U)
++
++#define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U)
++#define GPSR0_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U)
++#define GPSR0_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U)
++#define GPSR0_DU_EXHSYNC_DU_HSYNC_A ((uint32_t)0U << 19U)
++#define GPSR0_DU_DOTCLKOUT ((uint32_t)1U << 18U)
++#define GPSR0_DU_DB7 ((uint32_t)1U << 17U)
++#define GPSR0_DU_DB6 ((uint32_t)1U << 16U)
++#define GPSR0_DU_DB5 ((uint32_t)1U << 15U)
++#define GPSR0_DU_DB4 ((uint32_t)1U << 14U)
++#define GPSR0_DU_DB3 ((uint32_t)1U << 13U)
++#define GPSR0_DU_DB2 ((uint32_t)1U << 12U)
++#define GPSR0_DU_DG7 ((uint32_t)1U << 11U)
++#define GPSR0_DU_DG6 ((uint32_t)1U << 10U)
++#define GPSR0_DU_DG5 ((uint32_t)1U << 9U)
++#define GPSR0_DU_DG4 ((uint32_t)1U << 8U)
++#define GPSR0_DU_DG3 ((uint32_t)1U << 7U)
++#define GPSR0_DU_DG2 ((uint32_t)1U << 6U)
++#define GPSR0_DU_DR7 ((uint32_t)1U << 5U)
++#define GPSR0_DU_DR6 ((uint32_t)1U << 4U)
++#define GPSR0_DU_DR5 ((uint32_t)1U << 3U)
++#define GPSR0_DU_DR4 ((uint32_t)1U << 2U)
++#define GPSR0_DU_DR3 ((uint32_t)1U << 1U)
++#define GPSR0_DU_DR2 ((uint32_t)1U << 0U)
++#define GPSR1_DIGRF_CLKOUT ((uint32_t)1U << 27U)
++#define GPSR1_DIGRF_CLKIN ((uint32_t)1U << 26U)
++#define GPSR1_CANFD_CLK_A ((uint32_t)1U << 25U)
++#define GPSR1_CANFD1_RX ((uint32_t)1U << 24U)
++#define GPSR1_CANFD1_TX ((uint32_t)1U << 23U)
++#define GPSR1_CANFD0_RX_A ((uint32_t)1U << 22U)
++#define GPSR1_CANFD0_TX_A ((uint32_t)1U << 21U)
++#define GPSR1_AVB_AVTP_CAPTURE ((uint32_t)1U << 20U)
++#define GPSR1_AVB_AVTP_MATCH ((uint32_t)1U << 19U)
++#define GPSR1_AVB_LINK ((uint32_t)1U << 18U)
++#define GPSR1_AVB_PHY_INT ((uint32_t)1U << 17U)
++#define GPSR1_AVB_MAGIC ((uint32_t)1U << 16U)
++#define GPSR1_AVB_MDC ((uint32_t)1U << 15U)
++#define GPSR1_AVB_MDIO ((uint32_t)1U << 14U)
++#define GPSR1_AVB_TXCREFCLK ((uint32_t)1U << 13U)
++#define GPSR1_AVB_TD3 ((uint32_t)1U << 12U)
++#define GPSR1_AVB_TD2 ((uint32_t)1U << 11U)
++#define GPSR1_AVB_TD1 ((uint32_t)1U << 10U)
++#define GPSR1_AVB_TD0 ((uint32_t)1U << 9U)
++#define GPSR1_AVB_TXC ((uint32_t)1U << 8U)
++#define GPSR1_AVB_TX_CTL ((uint32_t)1U << 7U)
++#define GPSR1_AVB_RD3 ((uint32_t)1U << 6U)
++#define GPSR1_AVB_RD2 ((uint32_t)1U << 5U)
++#define GPSR1_AVB_RD1 ((uint32_t)1U << 4U)
++#define GPSR1_AVB_RD0 ((uint32_t)1U << 3U)
++#define GPSR1_AVB_RXC ((uint32_t)1U << 2U)
++#define GPSR1_AVB_RX_CTL ((uint32_t)1U << 1U)
++#define GPSR1_IRQ0 ((uint32_t)1U << 0U)
++#define GPSR2_FSO_TOE ((uint32_t)1U << 29U)
++#define GPSR2_FSO_CFE_1 ((uint32_t)1U << 28U)
++#define GPSR2_FSO_CFE_0 ((uint32_t)1U << 27U)
++#define GPSR2_SDA3 ((uint32_t)1U << 26U)
++#define GPSR2_SCL3 ((uint32_t)1U << 25U)
++#define GPSR2_MSIOF0_SS2 ((uint32_t)1U << 24U)
++#define GPSR2_MSIOF0_SS1 ((uint32_t)1U << 23U)
++#define GPSR2_MSIOF0_SYNC ((uint32_t)1U << 22U)
++#define GPSR2_MSIOF0_SCK ((uint32_t)1U << 21U)
++#define GPSR2_MSIOF0_TXD ((uint32_t)1U << 20U)
++#define GPSR2_MSIOF0_RXD ((uint32_t)1U << 19U)
++#define GPSR2_IRQ5 ((uint32_t)1U << 18U)
++#define GPSR2_IRQ4 ((uint32_t)1U << 17U)
++#define GPSR2_VI0_FIELD ((uint32_t)1U << 16U)
++#define GPSR2_VI0_DATA11 ((uint32_t)1U << 15U)
++#define GPSR2_VI0_DATA10 ((uint32_t)1U << 14U)
++#define GPSR2_VI0_DATA9 ((uint32_t)1U << 13U)
++#define GPSR2_VI0_DATA8 ((uint32_t)1U << 12U)
++#define GPSR2_VI0_DATA7 ((uint32_t)1U << 11U)
++#define GPSR2_VI0_DATA6 ((uint32_t)1U << 10U)
++#define GPSR2_VI0_DATA5 ((uint32_t)1U << 9U)
++#define GPSR2_VI0_DATA4 ((uint32_t)1U << 8U)
++#define GPSR2_VI0_DATA3 ((uint32_t)1U << 7U)
++#define GPSR2_VI0_DATA2 ((uint32_t)1U << 6U)
++#define GPSR2_VI0_DATA1 ((uint32_t)1U << 5U)
++#define GPSR2_VI0_DATA0 ((uint32_t)1U << 4U)
++#define GPSR2_VI0_VSYNC ((uint32_t)1U << 3U)
++#define GPSR2_VI0_HSYNC ((uint32_t)1U << 2U)
++#define GPSR2_VI0_CLKENB ((uint32_t)1U << 1U)
++#define GPSR2_VI0_CLK ((uint32_t)1U << 0U)
++#define GPSR3_VI1_FIELD ((uint32_t)1U << 16U)
++#define GPSR3_VI1_DATA11 ((uint32_t)1U << 15U)
++#define GPSR3_VI1_DATA10 ((uint32_t)1U << 14U)
++#define GPSR3_VI1_DATA9 ((uint32_t)1U << 13U)
++#define GPSR3_VI1_DATA8 ((uint32_t)1U << 12U)
++#define GPSR3_VI1_DATA7 ((uint32_t)1U << 11U)
++#define GPSR3_VI1_DATA6 ((uint32_t)1U << 10U)
++#define GPSR3_VI1_DATA5 ((uint32_t)1U << 9U)
++#define GPSR3_VI1_DATA4 ((uint32_t)1U << 8U)
++#define GPSR3_VI1_DATA3 ((uint32_t)1U << 7U)
++#define GPSR3_VI1_DATA2 ((uint32_t)1U << 6U)
++#define GPSR3_VI1_DATA1 ((uint32_t)1U << 5U)
++#define GPSR3_VI1_DATA0 ((uint32_t)1U << 4U)
++#define GPSR3_VI1_VSYNC ((uint32_t)1U << 3U)
++#define GPSR3_VI1_HSYNC ((uint32_t)1U << 2U)
++#define GPSR3_VI1_CLKENB ((uint32_t)1U << 1U)
++#define GPSR3_VI1_CLK ((uint32_t)1U << 0U)
++#define GPSR4_GETHER_LINK_A ((uint32_t)1U << 24U)
++#define GPSR4_GETHER_PHY_INT_A ((uint32_t)1U << 23U)
++#define GPSR4_GETHER_MAGIC ((uint32_t)1U << 22U)
++#define GPSR4_GETHER_MDC_A ((uint32_t)1U << 21U)
++#define GPSR4_GETHER_MDIO_A ((uint32_t)1U << 20U)
++#define GPSR4_GETHER_TXCREFCLK_MEGA ((uint32_t)1U << 19U)
++#define GPSR4_GETHER_TXCREFCLK ((uint32_t)1U << 18U)
++#define GPSR4_GETHER_TD3 ((uint32_t)1U << 17U)
++#define GPSR4_GETHER_TD2 ((uint32_t)1U << 16U)
++#define GPSR4_GETHER_TD1 ((uint32_t)1U << 15U)
++#define GPSR4_GETHER_TD0 ((uint32_t)1U << 14U)
++#define GPSR4_GETHER_TXC ((uint32_t)1U << 13U)
++#define GPSR4_GETHER_TX_CTL ((uint32_t)1U << 12U)
++#define GPSR4_GETHER_RD3 ((uint32_t)1U << 11U)
++#define GPSR4_GETHER_RD2 ((uint32_t)1U << 10U)
++#define GPSR4_GETHER_RD1 ((uint32_t)1U << 9U)
++#define GPSR4_GETHER_RD0 ((uint32_t)1U << 8U)
++#define GPSR4_GETHER_RXC ((uint32_t)1U << 7U)
++#define GPSR4_GETHER_RX_CTL ((uint32_t)1U << 6U)
++#define GPSR4_SDA2 ((uint32_t)1U << 5U)
++#define GPSR4_SCL2 ((uint32_t)1U << 4U)
++#define GPSR4_SDA1 ((uint32_t)1U << 3U)
++#define GPSR4_SCL1 ((uint32_t)1U << 2U)
++#define GPSR4_SDA0 ((uint32_t)1U << 1U)
++#define GPSR4_SCL0 ((uint32_t)1U << 0U)
++#define GPSR5_RPC_INT ((uint32_t)1U << 14U)
++#define GPSR5_RPC_WP ((uint32_t)1U << 13U)
++#define GPSR5_RPC_RESET ((uint32_t)1U << 12U)
++#define GPSR5_QSPI1_SSL ((uint32_t)1U << 11U)
++#define GPSR5_QSPI1_IO3 ((uint32_t)1U << 10U)
++#define GPSR5_QSPI1_IO2 ((uint32_t)1U << 9U)
++#define GPSR5_QSPI1_MISO_IO1 ((uint32_t)1U << 8U)
++#define GPSR5_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U)
++#define GPSR5_QSPI1_SPCLK ((uint32_t)1U << 6U)
++#define GPSR5_QSPI0_SSL ((uint32_t)1U << 5U)
++#define GPSR5_QSPI0_IO3 ((uint32_t)1U << 4U)
++#define GPSR5_QSPI0_IO2 ((uint32_t)1U << 3U)
++#define GPSR5_QSPI0_MISO_IO1 ((uint32_t)1U << 2U)
++#define GPSR5_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U)
++#define GPSR5_QSPI0_SPCLK ((uint32_t)1U << 0U)
++
++#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
++#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
++#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
++#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
++#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
++#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
++#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
++#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
++
++#define IOCTRL0_MASK (0x00000000U)
++#define IOCTRL1_MASK (0x00000000U)
++#define IOCTRL2_MASK (0x00000000U)
++#define IOCTRL3_MASK (0x00000000U)
++#define IOCTRL4_MASK (0x00000000U)
++#define IOCTRL5_MASK (0x00000000U)
++#define IOCTRL6_MASK (0x00000000U)
++#define IOCTRL7_MASK (0x00000000U)
++#define IOCTRL8_MASK (0x00000000U)
++#define IOCTRL9_MASK (0x00000000U)
++#define IOCTRL10_MASK (0x00000000U)
++#define IOCTRL11_MASK (0x00000000U)
++#define IOCTRL12_MASK (0x00000000U)
++#define IOCTRL13_MASK (0x00000000U)
++#define IOCTRL14_MASK (0x00000000U)
++#define IOCTRL15_MASK (0x00000000U)
++#define IOCTRL16_MASK (0x00000000U)
++#define IOCTRL17_MASK (0x00000000U)
++#define IOCTRL18_MASK (0x00000000U)
++#define IOCTRL19_MASK (0x00000000U)
++
++#define IOCTRL0_DRV3_GETHER_DR2 ((uint32_t)1U << 30U)
++#define IOCTRL0_DRV2_GETHER_DR2 ((uint32_t)1U << 29U)
++#define IOCTRL0_DRV1_GETHER_DR2 ((uint32_t)1U << 28U)
++#define IOCTRL0_DRV3_GETHER_DR3 ((uint32_t)1U << 26U)
++#define IOCTRL0_DRV2_GETHER_DR3 ((uint32_t)1U << 25U)
++#define IOCTRL0_DRV1_GETHER_DR3 ((uint32_t)1U << 24U)
++#define IOCTRL0_DRV3_GETHER_DR4 ((uint32_t)1U << 22U)
++#define IOCTRL0_DRV2_GETHER_DR4 ((uint32_t)1U << 21U)
++#define IOCTRL0_DRV1_GETHER_DR4 ((uint32_t)1U << 20U)
++#define IOCTRL0_DRV3_GETHER_DR5 ((uint32_t)1U << 18U)
++#define IOCTRL0_DRV2_GETHER_DR5 ((uint32_t)1U << 17U)
++#define IOCTRL0_DRV1_GETHER_DR5 ((uint32_t)1U << 16U)
++#define IOCTRL0_DRV3_GETHER_DR6 ((uint32_t)1U << 14U)
++#define IOCTRL0_DRV2_GETHER_DR6 ((uint32_t)1U << 13U)
++#define IOCTRL0_DRV1_GETHER_DR6 ((uint32_t)1U << 12U)
++#define IOCTRL0_DRV3_GETHER_DR7 ((uint32_t)1U << 10U)
++#define IOCTRL0_DRV2_GETHER_DR7 ((uint32_t)1U << 9U)
++#define IOCTRL0_DRV1_GETHER_DR7 ((uint32_t)1U << 8U)
++#define IOCTRL0_DRV3_GETHER_DG2 ((uint32_t)1U << 6U)
++#define IOCTRL0_DRV2_GETHER_DG2 ((uint32_t)1U << 5U)
++#define IOCTRL0_DRV1_GETHER_DG2 ((uint32_t)1U << 4U)
++#define IOCTRL0_DRV3_GETHER_DG3 ((uint32_t)1U << 2U)
++#define IOCTRL0_DRV2_GETHER_DG3 ((uint32_t)1U << 1U)
++#define IOCTRL0_DRV1_GETHER_DG3 ((uint32_t)1U << 0U)
++#define IOCTRL1_DRV3_GETHER_DG4 ((uint32_t)1U << 30U)
++#define IOCTRL1_DRV2_GETHER_DG4 ((uint32_t)1U << 29U)
++#define IOCTRL1_DRV1_GETHER_DG4 ((uint32_t)1U << 28U)
++#define IOCTRL1_DRV3_GETHER_DG5 ((uint32_t)1U << 26U)
++#define IOCTRL1_DRV2_GETHER_DG5 ((uint32_t)1U << 25U)
++#define IOCTRL1_DRV1_GETHER_DG5 ((uint32_t)1U << 24U)
++#define IOCTRL1_DRV3_GETHER_DG6 ((uint32_t)1U << 22U)
++#define IOCTRL1_DRV2_GETHER_DG6 ((uint32_t)1U << 21U)
++#define IOCTRL1_DRV1_GETHER_DG6 ((uint32_t)1U << 20U)
++#define IOCTRL1_DRV3_GETHER_DG7 ((uint32_t)1U << 18U)
++#define IOCTRL1_DRV2_GETHER_DG7 ((uint32_t)1U << 17U)
++#define IOCTRL1_DRV1_GETHER_DG7 ((uint32_t)1U << 16U)
++#define IOCTRL1_DRV3_GETHER_DB2 ((uint32_t)1U << 14U)
++#define IOCTRL1_DRV2_GETHER_DB2 ((uint32_t)1U << 13U)
++#define IOCTRL1_DRV1_GETHER_DB2 ((uint32_t)1U << 12U)
++#define IOCTRL1_DRV3_GETHER_DB3 ((uint32_t)1U << 10U)
++#define IOCTRL1_DRV2_GETHER_DB3 ((uint32_t)1U << 9U)
++#define IOCTRL1_DRV1_GETHER_DB3 ((uint32_t)1U << 8U)
++#define IOCTRL1_DRV3_GETHER_DB4 ((uint32_t)1U << 6U)
++#define IOCTRL1_DRV2_GETHER_DB4 ((uint32_t)1U << 5U)
++#define IOCTRL1_DRV1_GETHER_DB4 ((uint32_t)1U << 4U)
++#define IOCTRL1_DRV3_GETHER_DB5 ((uint32_t)1U << 2U)
++#define IOCTRL1_DRV2_GETHER_DB5 ((uint32_t)1U << 1U)
++#define IOCTRL1_DRV1_GETHER_DB5 ((uint32_t)1U << 0U)
++#define IOCTRL2_DRV3_GETHER_DB6 ((uint32_t)1U << 30U)
++#define IOCTRL2_DRV2_GETHER_DB6 ((uint32_t)1U << 29U)
++#define IOCTRL2_DRV1_GETHER_DB6 ((uint32_t)1U << 28U)
++#define IOCTRL2_DRV3_GETHER_DB7 ((uint32_t)1U << 26U)
++#define IOCTRL2_DRV2_GETHER_DB7 ((uint32_t)1U << 25U)
++#define IOCTRL2_DRV1_GETHER_DB7 ((uint32_t)1U << 24U)
++#define IOCTRL2_DRV3_DU_DOTCLKOUT ((uint32_t)1U << 22U)
++#define IOCTRL2_DRV2_DU_DOTCLKOUT ((uint32_t)1U << 21U)
++#define IOCTRL2_DRV1_DU_DOTCLKOUT ((uint32_t)1U << 20U)
++#define IOCTRL2_DRV3_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 18U)
++#define IOCTRL2_DRV2_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 17U)
++#define IOCTRL2_DRV1_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 16U)
++#define IOCTRL2_DRV3_DU_EXHSYNC_DU_VSYNC ((uint32_t)1U << 14U)
++#define IOCTRL2_DRV2_DU_EXHSYNC_DU_VSYNC ((uint32_t)1U << 13U)
++#define IOCTRL2_DRV1_DU_EXHSYNC_DU_VSYNC ((uint32_t)1U << 12U)
++#define IOCTRL2_DRV3_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 10U)
++#define IOCTRL2_DRV2_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 9U)
++#define IOCTRL2_DRV1_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 8U)
++#define IOCTRL3_DRV2_DU_DOTCLKIN ((uint32_t)1U << 29U)
++#define IOCTRL3_DRV1_DU_DOTCLKIN ((uint32_t)1U << 28U)
++#define IOCTRL3_DRV3_PRESETOUT ((uint32_t)1U << 22U)
++#define IOCTRL3_DRV2_PRESETOUT ((uint32_t)1U << 21U)
++#define IOCTRL3_DRV1_PRESETOUT ((uint32_t)1U << 20U)
++#define IOCTRL3_DRV2_FSCLKST ((uint32_t)1U << 1U)
++#define IOCTRL3_DRV1_FSCLKST ((uint32_t)1U << 0U)
++#define IOCTRL4_DRV2_FSCLKST2 ((uint32_t)1U << 29U)
++#define IOCTRL4_DRV1_FSCLKST2 ((uint32_t)1U << 28U)
++#define IOCTRL4_DRV3_IRQ0 ((uint32_t)1U << 22U)
++#define IOCTRL4_DRV2_IRQ0 ((uint32_t)1U << 21U)
++#define IOCTRL4_DRV1_IRQ0 ((uint32_t)1U << 20U)
++#define IOCTRL4_DRV2_DCUTMS ((uint32_t)1U << 9U)
++#define IOCTRL4_DRV1_DCUTMS ((uint32_t)1U << 8U)
++#define IOCTRL4_DRV2_DCUTDO_LPDO ((uint32_t)1U << 1U)
++#define IOCTRL4_DRV1_DCUTDO_LPDO ((uint32_t)1U << 0U)
++#define IOCTRL5_DRV2_DCURDY_LPDCLKOUT ((uint32_t)1U << 29U)
++#define IOCTRL5_DRV1_DCURDY_LPDCLKOUT ((uint32_t)1U << 28U)
++#define IOCTRL5_DRV3_VI0_CLK ((uint32_t)1U << 26U)
++#define IOCTRL5_DRV2_VI0_CLK ((uint32_t)1U << 25U)
++#define IOCTRL5_DRV1_VI0_CLK ((uint32_t)1U << 24U)
++#define IOCTRL5_DRV3_VI0_CLKENB ((uint32_t)1U << 22U)
++#define IOCTRL5_DRV2_VI0_CLKENB ((uint32_t)1U << 21U)
++#define IOCTRL5_DRV1_VI0_CLKENB ((uint32_t)1U << 20U)
++#define IOCTRL5_DRV3_VI0_HSYNC ((uint32_t)1U << 18U)
++#define IOCTRL5_DRV2_VI0_HSYNC ((uint32_t)1U << 17U)
++#define IOCTRL5_DRV1_VI0_HSYNC ((uint32_t)1U << 16U)
++#define IOCTRL5_DRV3_VI0_VSYNC ((uint32_t)1U << 14U)
++#define IOCTRL5_DRV2_VI0_VSYNC ((uint32_t)1U << 13U)
++#define IOCTRL5_DRV1_VI0_VSYNC ((uint32_t)1U << 12U)
++#define IOCTRL5_DRV3_VI0_DATA0 ((uint32_t)1U << 10U)
++#define IOCTRL5_DRV2_VI0_DATA0 ((uint32_t)1U << 9U)
++#define IOCTRL5_DRV1_VI0_DATA0 ((uint32_t)1U << 8U)
++#define IOCTRL5_DRV3_VI0_DATA1 ((uint32_t)1U << 6U)
++#define IOCTRL5_DRV2_VI0_DATA1 ((uint32_t)1U << 5U)
++#define IOCTRL5_DRV1_VI0_DATA1 ((uint32_t)1U << 4U)
++#define IOCTRL5_DRV3_VI0_DATA2 ((uint32_t)1U << 2U)
++#define IOCTRL5_DRV2_VI0_DATA2 ((uint32_t)1U << 1U)
++#define IOCTRL5_DRV1_VI0_DATA2 ((uint32_t)1U << 0U)
++#define IOCTRL6_DRV3_VI0_DATA3 ((uint32_t)1U << 30U)
++#define IOCTRL6_DRV2_VI0_DATA3 ((uint32_t)1U << 29U)
++#define IOCTRL6_DRV1_VI0_DATA3 ((uint32_t)1U << 28U)
++#define IOCTRL6_DRV3_VI0_DATA4 ((uint32_t)1U << 26U)
++#define IOCTRL6_DRV2_VI0_DATA4 ((uint32_t)1U << 25U)
++#define IOCTRL6_DRV1_VI0_DATA4 ((uint32_t)1U << 24U)
++#define IOCTRL6_DRV3_VI0_DATA5 ((uint32_t)1U << 22U)
++#define IOCTRL6_DRV2_VI0_DATA5 ((uint32_t)1U << 21U)
++#define IOCTRL6_DRV1_VI0_DATA5 ((uint32_t)1U << 20U)
++#define IOCTRL6_DRV3_VI0_DATA6 ((uint32_t)1U << 18U)
++#define IOCTRL6_DRV2_VI0_DATA6 ((uint32_t)1U << 17U)
++#define IOCTRL6_DRV1_VI0_DATA6 ((uint32_t)1U << 16U)
++#define IOCTRL6_DRV3_VI0_DATA7 ((uint32_t)1U << 14U)
++#define IOCTRL6_DRV2_VI0_DATA7 ((uint32_t)1U << 13U)
++#define IOCTRL6_DRV1_VI0_DATA7 ((uint32_t)1U << 12U)
++#define IOCTRL6_DRV3_VI0_DATA8 ((uint32_t)1U << 10U)
++#define IOCTRL6_DRV2_VI0_DATA8 ((uint32_t)1U << 9U)
++#define IOCTRL6_DRV1_VI0_DATA8 ((uint32_t)1U << 8U)
++#define IOCTRL6_DRV3_VI0_DATA9 ((uint32_t)1U << 6U)
++#define IOCTRL6_DRV2_VI0_DATA9 ((uint32_t)1U << 5U)
++#define IOCTRL6_DRV1_VI0_DATA9 ((uint32_t)1U << 4U)
++#define IOCTRL6_DRV3_VI0_DATA10 ((uint32_t)1U << 2U)
++#define IOCTRL6_DRV2_VI0_DATA10 ((uint32_t)1U << 1U)
++#define IOCTRL6_DRV1_VI0_DATA10 ((uint32_t)1U << 0U)
++#define IOCTRL7_DRV3_VI0_DATA11 ((uint32_t)1U << 30U)
++#define IOCTRL7_DRV2_VI0_DATA11 ((uint32_t)1U << 29U)
++#define IOCTRL7_DRV1_VI0_DATA11 ((uint32_t)1U << 28U)
++#define IOCTRL7_DRV3_VI0_FIELD ((uint32_t)1U << 26U)
++#define IOCTRL7_DRV2_VI0_FIELD ((uint32_t)1U << 25U)
++#define IOCTRL7_DRV1_VI0_FIELD ((uint32_t)1U << 24U)
++#define IOCTRL7_DRV3_VI1_CLK ((uint32_t)1U << 22U)
++#define IOCTRL7_DRV2_VI1_CLK ((uint32_t)1U << 21U)
++#define IOCTRL7_DRV1_VI1_CLK ((uint32_t)1U << 20U)
++#define IOCTRL7_DRV3_VI1_CLKENB ((uint32_t)1U << 18U)
++#define IOCTRL7_DRV2_VI1_CLKENB ((uint32_t)1U << 17U)
++#define IOCTRL7_DRV1_VI1_CLKENB ((uint32_t)1U << 16U)
++#define IOCTRL7_DRV3_VI1_HSYNC ((uint32_t)1U << 14U)
++#define IOCTRL7_DRV2_VI1_HSYNC ((uint32_t)1U << 13U)
++#define IOCTRL7_DRV1_VI1_HSYNC ((uint32_t)1U << 12U)
++#define IOCTRL7_DRV3_VI1_VSYNC ((uint32_t)1U << 10U)
++#define IOCTRL7_DRV2_VI1_VSYNC ((uint32_t)1U << 9U)
++#define IOCTRL7_DRV1_VI1_VSYNC ((uint32_t)1U << 8U)
++#define IOCTRL7_DRV3_VI1_DATA0 ((uint32_t)1U << 6U)
++#define IOCTRL7_DRV2_VI1_DATA0 ((uint32_t)1U << 5U)
++#define IOCTRL7_DRV1_VI1_DATA0 ((uint32_t)1U << 4U)
++#define IOCTRL7_DRV3_VI1_DATA1 ((uint32_t)1U << 2U)
++#define IOCTRL7_DRV2_VI1_DATA1 ((uint32_t)1U << 1U)
++#define IOCTRL7_DRV1_VI1_DATA1 ((uint32_t)1U << 0U)
++#define IOCTRL8_DRV3_VI1_DATA2 ((uint32_t)1U << 30U)
++#define IOCTRL8_DRV2_VI1_DATA2 ((uint32_t)1U << 29U)
++#define IOCTRL8_DRV1_VI1_DATA2 ((uint32_t)1U << 28U)
++#define IOCTRL8_DRV3_VI1_DATA3 ((uint32_t)1U << 26U)
++#define IOCTRL8_DRV2_VI1_DATA3 ((uint32_t)1U << 25U)
++#define IOCTRL8_DRV1_VI1_DATA3 ((uint32_t)1U << 24U)
++#define IOCTRL8_DRV3_VI1_DATA4 ((uint32_t)1U << 22U)
++#define IOCTRL8_DRV2_VI1_DATA4 ((uint32_t)1U << 21U)
++#define IOCTRL8_DRV1_VI1_DATA4 ((uint32_t)1U << 20U)
++#define IOCTRL8_DRV3_VI1_DATA5 ((uint32_t)1U << 18U)
++#define IOCTRL8_DRV2_VI1_DATA5 ((uint32_t)1U << 17U)
++#define IOCTRL8_DRV1_VI1_DATA5 ((uint32_t)1U << 16U)
++#define IOCTRL8_DRV3_VI1_DATA6 ((uint32_t)1U << 14U)
++#define IOCTRL8_DRV2_VI1_DATA6 ((uint32_t)1U << 13U)
++#define IOCTRL8_DRV1_VI1_DATA6 ((uint32_t)1U << 12U)
++#define IOCTRL8_DRV3_VI1_DATA7 ((uint32_t)1U << 10U)
++#define IOCTRL8_DRV2_VI1_DATA7 ((uint32_t)1U << 9U)
++#define IOCTRL8_DRV1_VI1_DATA7 ((uint32_t)1U << 8U)
++#define IOCTRL8_DRV3_VI1_DATA8 ((uint32_t)1U << 6U)
++#define IOCTRL8_DRV2_VI1_DATA8 ((uint32_t)1U << 5U)
++#define IOCTRL8_DRV1_VI1_DATA8 ((uint32_t)1U << 4U)
++#define IOCTRL8_DRV3_VI1_DATA9 ((uint32_t)1U << 2U)
++#define IOCTRL8_DRV2_VI1_DATA9 ((uint32_t)1U << 1U)
++#define IOCTRL8_DRV1_VI1_DATA9 ((uint32_t)1U << 0U)
++#define IOCTRL9_DRV3_VI1_DATA10 ((uint32_t)1U << 30U)
++#define IOCTRL9_DRV2_VI1_DATA10 ((uint32_t)1U << 29U)
++#define IOCTRL9_DRV1_VI1_DATA10 ((uint32_t)1U << 28U)
++#define IOCTRL9_DRV3_VI1_DATA11 ((uint32_t)1U << 26U)
++#define IOCTRL9_DRV2_VI1_DATA11 ((uint32_t)1U << 25U)
++#define IOCTRL9_DRV1_VI1_DATA11 ((uint32_t)1U << 24U)
++#define IOCTRL9_DRV3_VI1_FIELD ((uint32_t)1U << 22U)
++#define IOCTRL9_DRV2_VI1_FIELD ((uint32_t)1U << 21U)
++#define IOCTRL9_DRV1_VI1_FIELD ((uint32_t)1U << 20U)
++#define IOCTRL9_DRV3_VI1_SCL0 ((uint32_t)1U << 18U)
++#define IOCTRL9_DRV2_VI1_SCL0 ((uint32_t)1U << 17U)
++#define IOCTRL9_DRV1_VI1_SCL0 ((uint32_t)1U << 16U)
++#define IOCTRL9_DRV3_VI1_SDA0 ((uint32_t)1U << 14U)
++#define IOCTRL9_DRV2_VI1_SDA0 ((uint32_t)1U << 13U)
++#define IOCTRL9_DRV1_VI1_SDA0 ((uint32_t)1U << 12U)
++#define IOCTRL9_DRV3_VI1_SCL1 ((uint32_t)1U << 10U)
++#define IOCTRL9_DRV2_VI1_SCL1 ((uint32_t)1U << 9U)
++#define IOCTRL9_DRV1_VI1_SCL1 ((uint32_t)1U << 8U)
++#define IOCTRL9_DRV3_VI1_SDA1 ((uint32_t)1U << 6U)
++#define IOCTRL9_DRV2_VI1_SDA1 ((uint32_t)1U << 5U)
++#define IOCTRL9_DRV1_VI1_SDA1 ((uint32_t)1U << 4U)
++#define IOCTRL9_DRV3_VI1_SCL2 ((uint32_t)1U << 2U)
++#define IOCTRL9_DRV2_VI1_SCL2 ((uint32_t)1U << 1U)
++#define IOCTRL9_DRV1_VI1_SCL2 ((uint32_t)1U << 0U)
++#define IOCTRL10_DRV3_VI1_SDA2 ((uint32_t)1U << 30U)
++#define IOCTRL10_DRV2_VI1_SDA2 ((uint32_t)1U << 29U)
++#define IOCTRL10_DRV1_VI1_SDA2 ((uint32_t)1U << 28U)
++#define IOCTRL10_DRV3_AVB_RX_CTL ((uint32_t)1U << 26U)
++#define IOCTRL10_DRV2_AVB_RX_CTL ((uint32_t)1U << 25U)
++#define IOCTRL10_DRV1_AVB_RX_CTL ((uint32_t)1U << 24U)
++#define IOCTRL10_DRV3_AVB_RX_RXC ((uint32_t)1U << 22U)
++#define IOCTRL10_DRV2_AVB_RX_RXC ((uint32_t)1U << 21U)
++#define IOCTRL10_DRV1_AVB_RX_RXC ((uint32_t)1U << 20U)
++#define IOCTRL10_DRV3_AVB_RX_RD0 ((uint32_t)1U << 18U)
++#define IOCTRL10_DRV2_AVB_RX_RD0 ((uint32_t)1U << 17U)
++#define IOCTRL10_DRV1_AVB_RX_RD0 ((uint32_t)1U << 16U)
++#define IOCTRL10_DRV3_AVB_RX_RD1 ((uint32_t)1U << 14U)
++#define IOCTRL10_DRV2_AVB_RX_RD1 ((uint32_t)1U << 13U)
++#define IOCTRL10_DRV1_AVB_RX_RD1 ((uint32_t)1U << 12U)
++#define IOCTRL10_DRV3_AVB_RX_RD2 ((uint32_t)1U << 10U)
++#define IOCTRL10_DRV2_AVB_RX_RD2 ((uint32_t)1U << 9U)
++#define IOCTRL10_DRV1_AVB_RX_RD2 ((uint32_t)1U << 8U)
++#define IOCTRL10_DRV3_AVB_RX_RD3 ((uint32_t)1U << 6U)
++#define IOCTRL10_DRV2_AVB_RX_RD3 ((uint32_t)1U << 5U)
++#define IOCTRL10_DRV1_AVB_RX_RD3 ((uint32_t)1U << 4U)
++#define IOCTRL10_DRV3_AVB_TX_CTL ((uint32_t)1U << 2U)
++#define IOCTRL10_DRV2_AVB_TX_CTL ((uint32_t)1U << 1U)
++#define IOCTRL10_DRV1_AVB_TX_CTL ((uint32_t)1U << 0U)
++#define IOCTRL11_DRV3_AVB_TXC ((uint32_t)1U << 30U)
++#define IOCTRL11_DRV2_AVB_TXC ((uint32_t)1U << 29U)
++#define IOCTRL11_DRV1_AVB_TXC ((uint32_t)1U << 28U)
++#define IOCTRL11_DRV3_AVB_TD0 ((uint32_t)1U << 26U)
++#define IOCTRL11_DRV2_AVB_TD0 ((uint32_t)1U << 25U)
++#define IOCTRL11_DRV1_AVB_TD0 ((uint32_t)1U << 24U)
++#define IOCTRL11_DRV3_AVB_TD1 ((uint32_t)1U << 22U)
++#define IOCTRL11_DRV2_AVB_TD1 ((uint32_t)1U << 21U)
++#define IOCTRL11_DRV1_AVB_TD1 ((uint32_t)1U << 20U)
++#define IOCTRL11_DRV3_AVB_TD2 ((uint32_t)1U << 18U)
++#define IOCTRL11_DRV2_AVB_TD2 ((uint32_t)1U << 17U)
++#define IOCTRL11_DRV1_AVB_TD2 ((uint32_t)1U << 16U)
++#define IOCTRL11_DRV3_AVB_TD3 ((uint32_t)1U << 14U)
++#define IOCTRL11_DRV2_AVB_TD3 ((uint32_t)1U << 13U)
++#define IOCTRL11_DRV1_AVB_TD3 ((uint32_t)1U << 12U)
++#define IOCTRL11_DRV3_AVB_TXCREFCLK ((uint32_t)1U << 10U)
++#define IOCTRL11_DRV2_AVB_TXCREFCLK ((uint32_t)1U << 9U)
++#define IOCTRL11_DRV1_AVB_TXCREFCLK ((uint32_t)1U << 8U)
++#define IOCTRL11_DRV3_AVB_MDIO ((uint32_t)1U << 6U)
++#define IOCTRL11_DRV2_AVB_MDIO ((uint32_t)1U << 5U)
++#define IOCTRL11_DRV1_AVB_MDIO ((uint32_t)1U << 4U)
++#define IOCTRL11_DRV3_AVB_MDC ((uint32_t)1U << 2U)
++#define IOCTRL11_DRV2_AVB_MDC ((uint32_t)1U << 1U)
++#define IOCTRL11_DRV1_AVB_MDC ((uint32_t)1U << 0U)
++#define IOCTRL12_DRV3_AVB_MAGIC ((uint32_t)1U << 30U)
++#define IOCTRL12_DRV2_AVB_MAGIC ((uint32_t)1U << 29U)
++#define IOCTRL12_DRV1_AVB_MAGIC ((uint32_t)1U << 28U)
++#define IOCTRL12_DRV3_AVB_PHY_INT ((uint32_t)1U << 26U)
++#define IOCTRL12_DRV2_AVB_PHY_INT ((uint32_t)1U << 25U)
++#define IOCTRL12_DRV1_AVB_PHY_INT ((uint32_t)1U << 24U)
++#define IOCTRL12_DRV3_AVB_LINK ((uint32_t)1U << 22U)
++#define IOCTRL12_DRV2_AVB_LINK ((uint32_t)1U << 21U)
++#define IOCTRL12_DRV1_AVB_LINK ((uint32_t)1U << 20U)
++#define IOCTRL12_DRV3_AVB_AVTP_MATCH ((uint32_t)1U << 18U)
++#define IOCTRL12_DRV2_AVB_AVTP_MATCH ((uint32_t)1U << 17U)
++#define IOCTRL12_DRV1_AVB_AVTP_MATCH ((uint32_t)1U << 16U)
++#define IOCTRL12_DRV3_AVB_AVTP_CAPTURE ((uint32_t)1U << 14U)
++#define IOCTRL12_DRV2_AVB_AVTP_CAPTURE ((uint32_t)1U << 13U)
++#define IOCTRL12_DRV1_AVB_AVTP_CAPTURE ((uint32_t)1U << 12U)
++#define IOCTRL12_DRV3_GETHER_RX_CTL ((uint32_t)1U << 10U)
++#define IOCTRL12_DRV2_GETHER_RX_CTL ((uint32_t)1U << 9U)
++#define IOCTRL12_DRV1_GETHER_RX_CTL ((uint32_t)1U << 8U)
++#define IOCTRL12_DRV3_GETHER_RXC ((uint32_t)1U << 6U)
++#define IOCTRL12_DRV2_GETHER_RXC ((uint32_t)1U << 5U)
++#define IOCTRL12_DRV1_GETHER_RXC ((uint32_t)1U << 4U)
++#define IOCTRL12_DRV3_GETHER_RD0 ((uint32_t)1U << 2U)
++#define IOCTRL12_DRV2_GETHER_RD0 ((uint32_t)1U << 1U)
++#define IOCTRL12_DRV1_GETHER_RD0 ((uint32_t)1U << 0U)
++#define IOCTRL13_DRV3_GETHER_RD1 ((uint32_t)1U << 30U)
++#define IOCTRL13_DRV2_GETHER_RD1 ((uint32_t)1U << 29U)
++#define IOCTRL13_DRV1_GETHER_RD1 ((uint32_t)1U << 28U)
++#define IOCTRL13_DRV3_GETHER_RD2 ((uint32_t)1U << 26U)
++#define IOCTRL13_DRV2_GETHER_RD2 ((uint32_t)1U << 25U)
++#define IOCTRL13_DRV1_GETHER_RD2 ((uint32_t)1U << 24U)
++#define IOCTRL13_DRV3_GETHER_RD3 ((uint32_t)1U << 22U)
++#define IOCTRL13_DRV2_GETHER_RD3 ((uint32_t)1U << 21U)
++#define IOCTRL13_DRV1_GETHER_RD3 ((uint32_t)1U << 20U)
++#define IOCTRL13_DRV3_GETHER_TX_CTL ((uint32_t)1U << 18U)
++#define IOCTRL13_DRV2_GETHER_TX_CTL ((uint32_t)1U << 17U)
++#define IOCTRL13_DRV1_GETHER_TX_CTL ((uint32_t)1U << 16U)
++#define IOCTRL13_DRV3_GETHER_TXC ((uint32_t)1U << 14U)
++#define IOCTRL13_DRV2_GETHER_TXC ((uint32_t)1U << 13U)
++#define IOCTRL13_DRV1_GETHER_TXC ((uint32_t)1U << 12U)
++#define IOCTRL13_DRV3_GETHER_TD0 ((uint32_t)1U << 10U)
++#define IOCTRL13_DRV2_GETHER_TD0 ((uint32_t)1U << 9U)
++#define IOCTRL13_DRV1_GETHER_TD0 ((uint32_t)1U << 8U)
++#define IOCTRL13_DRV3_GETHER_TD1 ((uint32_t)1U << 6U)
++#define IOCTRL13_DRV2_GETHER_TD1 ((uint32_t)1U << 5U)
++#define IOCTRL13_DRV1_GETHER_TD1 ((uint32_t)1U << 4U)
++#define IOCTRL13_DRV3_GETHER_TD2 ((uint32_t)1U << 2U)
++#define IOCTRL13_DRV2_GETHER_TD2 ((uint32_t)1U << 1U)
++#define IOCTRL13_DRV1_GETHER_TD2 ((uint32_t)1U << 0U)
++#define IOCTRL13_DRV3_GETHER_TD3 ((uint32_t)1U << 30U)
++#define IOCTRL13_DRV2_GETHER_TD3 ((uint32_t)1U << 29U)
++#define IOCTRL13_DRV1_GETHER_TD3 ((uint32_t)1U << 28U)
++#define IOCTRL14_DRV3_GETHER_TXCREFCLK ((uint32_t)1U << 26U)
++#define IOCTRL14_DRV2_GETHER_TXCREFCLK ((uint32_t)1U << 25U)
++#define IOCTRL14_DRV1_GETHER_TXCREFCLK ((uint32_t)1U << 24U)
++#define IOCTRL14_DRV3_GETHER_TXCREFCLK_MEGA ((uint32_t)1U << 22U)
++#define IOCTRL14_DRV2_GETHER_TXCREFCLK_MEGA ((uint32_t)1U << 21U)
++#define IOCTRL14_DRV1_GETHER_TXCREFCLK_MEGA ((uint32_t)1U << 20U)
++#define IOCTRL14_DRV3_GETHER_MDIO ((uint32_t)1U << 18U)
++#define IOCTRL14_DRV2_GETHER_MDIO ((uint32_t)1U << 17U)
++#define IOCTRL14_DRV1_GETHER_MDIO ((uint32_t)1U << 16U)
++#define IOCTRL14_DRV3_GETHER_MDC ((uint32_t)1U << 14U)
++#define IOCTRL14_DRV2_GETHER_MDC ((uint32_t)1U << 13U)
++#define IOCTRL14_DRV1_GETHER_MDC ((uint32_t)1U << 12U)
++#define IOCTRL14_DRV3_GETHER_MAGIC ((uint32_t)1U << 10U)
++#define IOCTRL14_DRV2_GETHER_MAGIC ((uint32_t)1U << 9U)
++#define IOCTRL14_DRV1_GETHER_MAGIC ((uint32_t)1U << 8U)
++#define IOCTRL14_DRV3_GETHER_PHY_INT ((uint32_t)1U << 6U)
++#define IOCTRL14_DRV2_GETHER_PHY_INT ((uint32_t)1U << 5U)
++#define IOCTRL14_DRV1_GETHER_PHY_INT ((uint32_t)1U << 4U)
++#define IOCTRL14_DRV3_GETHER_LINK ((uint32_t)1U << 2U)
++#define IOCTRL14_DRV2_GETHER_LINK ((uint32_t)1U << 1U)
++#define IOCTRL14_DRV1_GETHER_LINK ((uint32_t)1U << 0U)
++#define IOCTRL15_DRV3_CANFD0_TX ((uint32_t)1U << 30U)
++#define IOCTRL15_DRV2_CANFD0_TX ((uint32_t)1U << 29U)
++#define IOCTRL15_DRV1_CANFD0_TX ((uint32_t)1U << 28U)
++#define IOCTRL15_DRV3_CANFD0_RX ((uint32_t)1U << 26U)
++#define IOCTRL15_DRV2_CANFD0_RX ((uint32_t)1U << 25U)
++#define IOCTRL15_DRV1_CANFD0_RX ((uint32_t)1U << 24U)
++#define IOCTRL15_DRV3_CANFD1_TX ((uint32_t)1U << 22U)
++#define IOCTRL15_DRV2_CANFD1_TX ((uint32_t)1U << 21U)
++#define IOCTRL15_DRV1_CANFD1_TX ((uint32_t)1U << 20U)
++#define IOCTRL15_DRV3_CANFD1_RX ((uint32_t)1U << 18U)
++#define IOCTRL15_DRV2_CANFD1_RX ((uint32_t)1U << 17U)
++#define IOCTRL15_DRV1_CANFD1_RX ((uint32_t)1U << 16U)
++#define IOCTRL15_DRV3_CAN_CLK ((uint32_t)1U << 14U)
++#define IOCTRL15_DRV2_CAN_CLK ((uint32_t)1U << 13U)
++#define IOCTRL15_DRV1_CAN_CLK ((uint32_t)1U << 12U)
++#define IOCTRL15_DRV2_QSPI0_SPCLK ((uint32_t)1U << 9U)
++#define IOCTRL15_DRV1_QSPI0_SPCLK ((uint32_t)1U << 8U)
++#define IOCTRL15_DRV2_QSPI0_MOSI_IO0 ((uint32_t)1U << 5U)
++#define IOCTRL15_DRV1_QSPI0_MOSI_IO0 ((uint32_t)1U << 4U)
++#define IOCTRL15_DRV2_QSPI0_MOSI_IO1 ((uint32_t)1U << 1U)
++#define IOCTRL15_DRV1_QSPI0_MOSI_IO1 ((uint32_t)1U << 0U)
++#define IOCTRL16_DRV2_QSPI0_MOSI_IO2 ((uint32_t)1U << 29U)
++#define IOCTRL16_DRV1_QSPI0_MOSI_IO2 ((uint32_t)1U << 28U)
++#define IOCTRL16_DRV2_QSPI0_MOSI_IO3 ((uint32_t)1U << 25U)
++#define IOCTRL16_DRV1_QSPI0_MOSI_IO3 ((uint32_t)1U << 24U)
++#define IOCTRL16_DRV2_QSPI0_SSL ((uint32_t)1U << 21U)
++#define IOCTRL16_DRV1_QSPI0_SSL ((uint32_t)1U << 20U)
++#define IOCTRL16_DRV2_QSPI1_SPCLK ((uint32_t)1U << 17U)
++#define IOCTRL16_DRV1_QSPI1_SPCLK ((uint32_t)1U << 16U)
++#define IOCTRL16_DRV2_QSPI1_MOSI_IO0 ((uint32_t)1U << 13U)
++#define IOCTRL16_DRV1_QSPI1_MOSI_IO0 ((uint32_t)1U << 12U)
++#define IOCTRL16_DRV2_QSPI1_MOSI_IO1 ((uint32_t)1U << 9U)
++#define IOCTRL16_DRV1_QSPI1_MOSI_IO1 ((uint32_t)1U << 8U)
++#define IOCTRL16_DRV2_QSPI1_IO2 ((uint32_t)1U << 5U)
++#define IOCTRL16_DRV1_QSPI1_IO2 ((uint32_t)1U << 4U)
++#define IOCTRL16_DRV2_QSPI1_IO3 ((uint32_t)1U << 1U)
++#define IOCTRL16_DRV1_QSPI1_IO3 ((uint32_t)1U << 0U)
++#define IOCTRL17_DRV2_QSPI1_SSL ((uint32_t)1U << 29U)
++#define IOCTRL17_DRV1_QSPI1_SSL ((uint32_t)1U << 28U)
++#define IOCTRL17_DRV2_QSPI1_RPC_RESET ((uint32_t)1U << 25U)
++#define IOCTRL17_DRV1_QSPI1_RPC_RESET ((uint32_t)1U << 24U)
++#define IOCTRL17_DRV2_RPC_WP ((uint32_t)1U << 21U)
++#define IOCTRL17_DRV1_RPC_WP ((uint32_t)1U << 20U)
++#define IOCTRL17_DRV2_RPC_INT ((uint32_t)1U << 17U)
++#define IOCTRL17_DRV1_RPC_INT ((uint32_t)1U << 16U)
++#define IOCTRL17_DRV2_DIGRF_CLKIN ((uint32_t)1U << 13U)
++#define IOCTRL17_DRV1_DIGRF_CLKIN ((uint32_t)1U << 12U)
++#define IOCTRL17_DRV2_DIGRF_CLKOUT ((uint32_t)1U << 9U)
++#define IOCTRL17_DRV1_DIGRF_CLKOUT ((uint32_t)1U << 8U)
++#define IOCTRL17_DRV2_RPC_IRQ4 ((uint32_t)1U << 5U)
++#define IOCTRL17_DRV1_RPC_IRQ4 ((uint32_t)1U << 4U)
++#define IOCTRL17_DRV2_RPC_IRQ5 ((uint32_t)1U << 1U)
++#define IOCTRL17_DRV1_RPC_IRQ5 ((uint32_t)1U << 0U)
++#define IOCTRL18_DRV3_SCL3 ((uint32_t)1U << 30U)
++#define IOCTRL18_DRV2_SCL3 ((uint32_t)1U << 29U)
++#define IOCTRL18_DRV1_SCL3 ((uint32_t)1U << 28U)
++#define IOCTRL18_DRV3_SDA3 ((uint32_t)1U << 26U)
++#define IOCTRL18_DRV2_SDA3 ((uint32_t)1U << 25U)
++#define IOCTRL18_DRV1_SDA3 ((uint32_t)1U << 24U)
++#define IOCTRL18_DRV3_MSIOF0_RXD ((uint32_t)1U << 22U)
++#define IOCTRL18_DRV2_MSIOF0_RXD ((uint32_t)1U << 21U)
++#define IOCTRL18_DRV1_MSIOF0_RXD ((uint32_t)1U << 20U)
++#define IOCTRL18_DRV3_MSIOF0_TXD ((uint32_t)1U << 18U)
++#define IOCTRL18_DRV2_MSIOF0_TXD ((uint32_t)1U << 17U)
++#define IOCTRL18_DRV1_MSIOF0_TXD ((uint32_t)1U << 16U)
++#define IOCTRL18_DRV3_MSIOF0_SCK ((uint32_t)1U << 14U)
++#define IOCTRL18_DRV2_MSIOF0_SCK ((uint32_t)1U << 13U)
++#define IOCTRL18_DRV1_MSIOF0_SCK ((uint32_t)1U << 12U)
++#define IOCTRL18_DRV3_MSIOF0_SYNC ((uint32_t)1U << 10U)
++#define IOCTRL18_DRV2_MSIOF0_SYNC ((uint32_t)1U << 9U)
++#define IOCTRL18_DRV1_MSIOF0_SYNC ((uint32_t)1U << 8U)
++#define IOCTRL18_DRV3_MSIOF0_SS1 ((uint32_t)1U << 6U)
++#define IOCTRL18_DRV2_MSIOF0_SS1 ((uint32_t)1U << 5U)
++#define IOCTRL18_DRV1_MSIOF0_SS1 ((uint32_t)1U << 4U)
++#define IOCTRL18_DRV3_MSIOF0_SS2 ((uint32_t)1U << 2U)
++#define IOCTRL18_DRV2_MSIOF0_SS2 ((uint32_t)1U << 1U)
++#define IOCTRL18_DRV1_MSIOF0_SS2 ((uint32_t)1U << 0U)
++#define IOCTRL19_DRV3_FSO_CFE_0 ((uint32_t)1U << 30U)
++#define IOCTRL19_DRV2_FSO_CFE_0 ((uint32_t)1U << 29U)
++#define IOCTRL19_DRV1_FSO_CFE_0 ((uint32_t)1U << 28U)
++#define IOCTRL19_DRV3_FSO_CFE_1 ((uint32_t)1U << 26U)
++#define IOCTRL19_DRV2_FSO_CFE_1 ((uint32_t)1U << 25U)
++#define IOCTRL19_DRV1_FSO_CFE_1 ((uint32_t)1U << 24U)
++#define IOCTRL19_DRV3_FSO_TOE ((uint32_t)1U << 22U)
++#define IOCTRL19_DRV2_FSO_TOE ((uint32_t)1U << 21U)
++#define IOCTRL19_DRV1_FSO_TOE ((uint32_t)1U << 20U)
++
++#define IOCTRL30_POC_VI0_DATA5 ((uint32_t)1U << 31U)
++#define IOCTRL30_POC_VI0_DATA4 ((uint32_t)1U << 30U)
++#define IOCTRL30_POC_VI0_DATA3 ((uint32_t)1U << 29U)
++#define IOCTRL30_POC_VI0_DATA2 ((uint32_t)1U << 28U)
++#define IOCTRL30_POC_VI0_DATA1 ((uint32_t)1U << 27U)
++#define IOCTRL30_POC_VI0_DATA0 ((uint32_t)1U << 26U)
++#define IOCTRL30_POC_VI0_VSYNC_N ((uint32_t)1U << 25U)
++#define IOCTRL30_POC_VI0_HSYNC_N ((uint32_t)1U << 24U)
++#define IOCTRL30_POC_VI0_CLKENB ((uint32_t)1U << 23U)
++#define IOCTRL30_POC_VI0_CLK ((uint32_t)1U << 22U)
++#define IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U)
++#define IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U)
++#define IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U)
++#define IOCTRL30_POC_DU_DOTCLKOUT ((uint32_t)1U << 18U)
++#define IOCTRL30_POC_DU_DB7 ((uint32_t)1U << 17U)
++#define IOCTRL30_POC_DU_DB6 ((uint32_t)1U << 16U)
++#define IOCTRL30_POC_DU_DB5 ((uint32_t)1U << 15U)
++#define IOCTRL30_POC_DU_DB4 ((uint32_t)1U << 14U)
++#define IOCTRL30_POC_DU_DB3 ((uint32_t)1U << 13U)
++#define IOCTRL30_POC_DU_DB2 ((uint32_t)1U << 12U)
++#define IOCTRL30_POC_DU_DG7 ((uint32_t)1U << 11U)
++#define IOCTRL30_POC_DU_DG6 ((uint32_t)1U << 10U)
++#define IOCTRL30_POC_DU_DG5 ((uint32_t)1U << 9U)
++#define IOCTRL30_POC_DU_DG4 ((uint32_t)1U << 8U)
++#define IOCTRL30_POC_DU_DG3 ((uint32_t)1U << 7U)
++#define IOCTRL30_POC_DU_DG2 ((uint32_t)1U << 6U)
++#define IOCTRL30_POC_DU_DR7 ((uint32_t)1U << 5U)
++#define IOCTRL30_POC_DU_DR6 ((uint32_t)1U << 4U)
++#define IOCTRL30_POC_DU_DR5 ((uint32_t)1U << 3U)
++#define IOCTRL30_POC_DU_DR4 ((uint32_t)1U << 2U)
++#define IOCTRL30_POC_DU_DR3 ((uint32_t)1U << 1U)
++#define IOCTRL30_POC_DU_DR2 ((uint32_t)1U << 0U)
++
++#define IOCTRL31_POC_MSIOF0_SS2 ((uint32_t)1U << 31U)
++#define IOCTRL31_POC_MSIOF0_SS1 ((uint32_t)1U << 30U)
++#define IOCTRL31_POC_MSIOF0_SYNC ((uint32_t)1U << 29U)
++#define IOCTRL31_POC_MSIOF0_SCK ((uint32_t)1U << 28U)
++#define IOCTRL31_POC_MSIOF0_TXD ((uint32_t)1U << 27U)
++#define IOCTRL31_POC_MSIOF0_RXD ((uint32_t)1U << 26U)
++#define IOCTRL31_POC_MSIOF0_IRQ5 ((uint32_t)1U << 25U)
++#define IOCTRL31_POC_MSIOF0_IRQ4 ((uint32_t)1U << 24U)
++#define IOCTRL31_POC_VI1_FIELD ((uint32_t)1U << 23U)
++#define IOCTRL31_POC_VI1_DATA11 ((uint32_t)1U << 22U)
++#define IOCTRL31_POC_VI1_DATA10 ((uint32_t)1U << 21U)
++#define IOCTRL31_POC_VI1_DATA9 ((uint32_t)1U << 20U)
++#define IOCTRL31_POC_VI1_DATA8 ((uint32_t)1U << 19U)
++#define IOCTRL31_POC_VI1_DATA7 ((uint32_t)1U << 18U)
++#define IOCTRL31_POC_VI1_DATA6 ((uint32_t)1U << 17U)
++#define IOCTRL31_POC_VI1_DATA5 ((uint32_t)1U << 16U)
++#define IOCTRL31_POC_VI1_DATA4 ((uint32_t)1U << 15U)
++#define IOCTRL31_POC_VI1_DATA3 ((uint32_t)1U << 14U)
++#define IOCTRL31_POC_VI1_DATA2 ((uint32_t)1U << 13U)
++#define IOCTRL31_POC_VI1_DATA1 ((uint32_t)1U << 12U)
++#define IOCTRL31_POC_VI1_DATA0 ((uint32_t)1U << 11U)
++#define IOCTRL31_POC_VI1_VSYNC ((uint32_t)1U << 10U)
++#define IOCTRL31_POC_VI1_HSYNC ((uint32_t)1U << 9U)
++#define IOCTRL31_POC_VI1_CLKENB ((uint32_t)1U << 8U)
++#define IOCTRL31_POC_VI1_CLK ((uint32_t)1U << 7U)
++#define IOCTRL31_POC_VI0_FIELD ((uint32_t)1U << 6U)
++#define IOCTRL31_POC_VI0_DATA11 ((uint32_t)1U << 5U)
++#define IOCTRL31_POC_VI0_DATA10 ((uint32_t)1U << 4U)
++#define IOCTRL31_POC_VI0_DATA9 ((uint32_t)1U << 3U)
++#define IOCTRL31_POC_VI0_DATA8 ((uint32_t)1U << 2U)
++#define IOCTRL31_POC_VI0_DATA7 ((uint32_t)1U << 1U)
++#define IOCTRL31_POC_VI0_DATA6 ((uint32_t)1U << 0U)
++#define IOCTRL32_POC_FSO_TOE ((uint32_t)1U << 4U)
++#define IOCTRL32_POC_FSO_CFE_1 ((uint32_t)1U << 3U)
++#define IOCTRL32_POC_FSO_CFE_0 ((uint32_t)1U << 2U)
++#define IOCTRL32_POC_SDA3 ((uint32_t)1U << 1U)
++#define IOCTRL32_POC_SCL3 ((uint32_t)1U << 0U)
++#define IOCTRL40_SD0TDSEL1 ((uint32_t)1U << 1U)
++#define IOCTRL40_SD0TDSEL0 ((uint32_t)1U << 0U)
++
++#define MOD_sel_canfd0_A ((uint32_t)0U << 11U)
++#define MOD_sel_canfd0_B ((uint32_t)1U << 11U)
++#define MOD_sel_gether_A ((uint32_t)0U << 10U)
++#define MOD_sel_gether_B ((uint32_t)1U << 10U)
++#define MOD_sel_hscif0_A ((uint32_t)0U << 9U)
++#define MOD_sel_hscif0_B ((uint32_t)1U << 9U)
++#define MOD_sel_pwm0_A ((uint32_t)0U << 8U)
++#define MOD_sel_pwm0_B ((uint32_t)1U << 8U)
++#define MOD_sel_pwm1_A ((uint32_t)0U << 7U)
++#define MOD_sel_pwm1_B ((uint32_t)1U << 7U)
++#define MOD_sel_pwm2_A ((uint32_t)0U << 6U)
++#define MOD_sel_pwm2_B ((uint32_t)1U << 6U)
++#define MOD_sel_pwm3_A ((uint32_t)0U << 5U)
++#define MOD_sel_pwm3_B ((uint32_t)1U << 5U)
++#define MOD_sel_pwm4_A ((uint32_t)0U << 4U)
++#define MOD_sel_pwm4_B ((uint32_t)1U << 4U)
++#define MOD_sel_rsp_A ((uint32_t)0U << 2U)
++#define MOD_sel_rsp_B ((uint32_t)1U << 2U)
++#define MOD_sel_scif1_A ((uint32_t)0U << 1U)
++#define MOD_sel_scif1_B ((uint32_t)1U << 1U)
++#define MOD_sel_tmu_A ((uint32_t)0U << 0U)
++#define MOD_sel_tmu_B ((uint32_t)1U << 0U)
++
++
++static void pfc_reg_write(uint32_t addr, uint32_t data);
++
++static void pfc_reg_write(uint32_t addr, uint32_t data)
++{
++ mmio_write_32(PFC_PMMR, ~data);
++ mmio_write_32((uintptr_t)addr, data);
++}
++
++
++void pfc_init_v3h(void)
++{
++
++ /* initialize module select */
++ pfc_reg_write(PFC_MOD_SEL0, MOD_sel_canfd0_A
++ | MOD_sel_gether_A
++ | MOD_sel_hscif0_B
++ | MOD_sel_pwm0_A
++ | MOD_sel_pwm1_A
++ | MOD_sel_pwm2_A
++ | MOD_sel_pwm3_A
++ | MOD_sel_pwm4_A
++ | MOD_sel_rsp_A
++ | MOD_sel_scif1_A
++ | MOD_sel_tmu_A);
++
++ /* initialize peripheral function select */
++ pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
++ | IPSR_24_FUNC(0)
++ | IPSR_20_FUNC(0)
++ | IPSR_16_FUNC(0)
++ | IPSR_12_FUNC(0)
++ | IPSR_8_FUNC(0)
++ | IPSR_4_FUNC(0)
++ | IPSR_0_FUNC(0));
++ pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0)
++ | IPSR_24_FUNC(0)
++ | IPSR_20_FUNC(0)
++ | IPSR_16_FUNC(0)
++ | IPSR_12_FUNC(0)
++ | IPSR_8_FUNC(0)
++ | IPSR_4_FUNC(0)
++ | IPSR_0_FUNC(0));
++ pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
++ | IPSR_24_FUNC(0)
++ | IPSR_20_FUNC(0)
++ | IPSR_16_FUNC(0)
++ | IPSR_12_FUNC(0)
++ | IPSR_8_FUNC(0)
++ | IPSR_4_FUNC(0)
++ | IPSR_0_FUNC(0));
++ pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(0)
++ | IPSR_24_FUNC(0)
++ | IPSR_20_FUNC(0)
++ | IPSR_16_FUNC(0)
++ | IPSR_12_FUNC(0)
++ | IPSR_8_FUNC(0)
++ | IPSR_4_FUNC(0)
++ | IPSR_0_FUNC(0));
++ pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
++ | IPSR_24_FUNC(0)
++ | IPSR_20_FUNC(0)
++ | IPSR_16_FUNC(0)
++ | IPSR_12_FUNC(0)
++ | IPSR_8_FUNC(0)
++ | IPSR_4_FUNC(0)
++ | IPSR_0_FUNC(0));
++ pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(4)
++ | IPSR_24_FUNC(4)
++ | IPSR_20_FUNC(0)
++ | IPSR_16_FUNC(0)
++ | IPSR_12_FUNC(0)
++ | IPSR_8_FUNC(0)
++ | IPSR_4_FUNC(0)
++ | IPSR_0_FUNC(0));
++ pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(4)
++ | IPSR_24_FUNC(4)
++ | IPSR_20_FUNC(4)
++ | IPSR_16_FUNC(4)
++ | IPSR_12_FUNC(4)
++ | IPSR_8_FUNC(4)
++ | IPSR_4_FUNC(4)
++ | IPSR_0_FUNC(4));
++ pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
++ | IPSR_24_FUNC(4)
++ | IPSR_20_FUNC(4)
++ | IPSR_16_FUNC(0)
++ | IPSR_12_FUNC(0)
++ | IPSR_8_FUNC(0)
++ | IPSR_4_FUNC(0)
++ | IPSR_0_FUNC(4));
++ pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0)
++ | IPSR_24_FUNC(0)
++ | IPSR_20_FUNC(4)
++ | IPSR_16_FUNC(0)
++ | IPSR_12_FUNC(0)
++ | IPSR_8_FUNC(0)
++ | IPSR_4_FUNC(0)
++ | IPSR_0_FUNC(0));
++ pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
++ | IPSR_24_FUNC(0)
++ | IPSR_20_FUNC(0)
++ | IPSR_16_FUNC(0)
++ | IPSR_12_FUNC(0)
++ | IPSR_8_FUNC(0)
++ | IPSR_4_FUNC(0)
++ | IPSR_0_FUNC(0));
++ pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0)
++ | IPSR_24_FUNC(0)
++ | IPSR_20_FUNC(0)
++ | IPSR_16_FUNC(0)
++ | IPSR_12_FUNC(0)
++ | IPSR_8_FUNC(0)
++ | IPSR_4_FUNC(0)
++ | IPSR_0_FUNC(0));
++
++ /* initialize GPIO/perihperal function select */
++ pfc_reg_write(PFC_GPSR0, 0x00000000);
++
++ pfc_reg_write(PFC_GPSR1, GPSR1_DIGRF_CLKOUT
++ | GPSR1_DIGRF_CLKIN
++ | GPSR1_CANFD_CLK_A
++ | GPSR1_CANFD0_RX_A
++ | GPSR1_CANFD0_TX_A
++ | GPSR1_AVB_LINK
++ | GPSR1_AVB_PHY_INT
++ | GPSR1_AVB_MDC
++ | GPSR1_AVB_MDIO
++ | GPSR1_AVB_TXCREFCLK
++ | GPSR1_AVB_TD3
++ | GPSR1_AVB_TD2
++ | GPSR1_AVB_TD1
++ | GPSR1_AVB_TD0
++ | GPSR1_AVB_TXC
++ | GPSR1_AVB_TX_CTL
++ | GPSR1_AVB_RD3
++ | GPSR1_AVB_RD2
++ | GPSR1_AVB_RD1
++ | GPSR1_AVB_RD0
++ | GPSR1_AVB_RXC
++ | GPSR1_AVB_RX_CTL
++ | GPSR1_IRQ0);
++
++ pfc_reg_write(PFC_GPSR2, 0x00000000);
++
++ pfc_reg_write(PFC_GPSR3, GPSR3_VI1_FIELD
++ | GPSR3_VI1_DATA11
++ | GPSR3_VI1_DATA10
++ | GPSR3_VI1_DATA9
++ | GPSR3_VI1_DATA8
++ | GPSR3_VI1_DATA7
++ | GPSR3_VI1_DATA6
++ | GPSR3_VI1_DATA5
++ | GPSR3_VI1_DATA4
++ | GPSR3_VI1_DATA3
++ | GPSR3_VI1_DATA2);
++
++ pfc_reg_write(PFC_GPSR4, GPSR4_GETHER_LINK_A
++ | GPSR4_GETHER_PHY_INT_A
++ | GPSR4_GETHER_MDC_A
++ | GPSR4_GETHER_MDIO_A
++ | GPSR4_GETHER_TXCREFCLK_MEGA
++ | GPSR4_GETHER_TXCREFCLK
++ | GPSR4_GETHER_TD3
++ | GPSR4_GETHER_TD2
++ | GPSR4_GETHER_TD1
++ | GPSR4_GETHER_TD0
++ | GPSR4_GETHER_TXC
++ | GPSR4_GETHER_TX_CTL
++ | GPSR4_GETHER_RD3
++ | GPSR4_GETHER_RD2
++ | GPSR4_GETHER_RD1
++ | GPSR4_GETHER_RD0
++ | GPSR4_GETHER_RXC
++ | GPSR4_GETHER_RX_CTL
++ | GPSR4_SDA2
++ | GPSR4_SCL2
++ | GPSR4_SDA1
++ | GPSR4_SCL1
++ | GPSR4_SDA0
++ | GPSR4_SCL0);
++
++ pfc_reg_write(PFC_GPSR5, GPSR5_QSPI1_SSL
++ | GPSR5_QSPI1_IO3
++ | GPSR5_QSPI1_IO2
++ | GPSR5_QSPI1_MISO_IO1
++ | GPSR5_QSPI1_MOSI_IO0
++ | GPSR5_QSPI1_SPCLK
++ | GPSR5_QSPI0_SSL
++ | GPSR5_QSPI0_IO3
++ | GPSR5_QSPI0_IO2
++ | GPSR5_QSPI0_MISO_IO1
++ | GPSR5_QSPI0_MOSI_IO0
++ | GPSR5_QSPI0_SPCLK);
++
++
++
++ /* initialize POC Control */
++
++ pfc_reg_write(PFC_IOCTRL30, IOCTRL30_POC_VI0_DATA5
++ | IOCTRL30_POC_VI0_DATA4
++ | IOCTRL30_POC_VI0_DATA3
++ | IOCTRL30_POC_VI0_DATA2
++ | IOCTRL30_POC_VI0_DATA1
++ | IOCTRL30_POC_VI0_DATA0
++ | IOCTRL30_POC_VI0_VSYNC_N
++ | IOCTRL30_POC_VI0_HSYNC_N
++ | IOCTRL30_POC_VI0_CLKENB
++ | IOCTRL30_POC_VI0_CLK
++ | IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE
++ | IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC
++ | IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC
++ | IOCTRL30_POC_DU_DOTCLKOUT
++ | IOCTRL30_POC_DU_DB7
++ | IOCTRL30_POC_DU_DB6
++ | IOCTRL30_POC_DU_DB5
++ | IOCTRL30_POC_DU_DB4
++ | IOCTRL30_POC_DU_DB3
++ | IOCTRL30_POC_DU_DB2
++ | IOCTRL30_POC_DU_DG7
++ | IOCTRL30_POC_DU_DG6
++ | IOCTRL30_POC_DU_DG5
++ | IOCTRL30_POC_DU_DG4
++ | IOCTRL30_POC_DU_DG3
++ | IOCTRL30_POC_DU_DG2
++ | IOCTRL30_POC_DU_DR7
++ | IOCTRL30_POC_DU_DR6
++ | IOCTRL30_POC_DU_DR5
++ | IOCTRL30_POC_DU_DR4
++ | IOCTRL30_POC_DU_DR3
++ | IOCTRL30_POC_DU_DR2);
++
++ pfc_reg_write(PFC_IOCTRL31, IOCTRL31_POC_MSIOF0_SS2
++ | IOCTRL31_POC_MSIOF0_SS1
++ | IOCTRL31_POC_MSIOF0_SYNC
++ | IOCTRL31_POC_MSIOF0_SCK
++ | IOCTRL31_POC_MSIOF0_TXD
++ | IOCTRL31_POC_MSIOF0_RXD
++ | IOCTRL31_POC_MSIOF0_IRQ5
++ | IOCTRL31_POC_MSIOF0_IRQ4
++ | IOCTRL31_POC_VI1_FIELD
++ | IOCTRL31_POC_VI1_DATA11
++ | IOCTRL31_POC_VI1_DATA10
++ | IOCTRL31_POC_VI1_DATA9
++ | IOCTRL31_POC_VI1_DATA8
++ | IOCTRL31_POC_VI1_DATA7
++ | IOCTRL31_POC_VI1_DATA6
++ | IOCTRL31_POC_VI1_DATA5
++ | IOCTRL31_POC_VI1_DATA4
++ | IOCTRL31_POC_VI1_DATA3
++ | IOCTRL31_POC_VI1_DATA2
++ | IOCTRL31_POC_VI1_DATA1
++ | IOCTRL31_POC_VI1_DATA0
++ | IOCTRL31_POC_VI1_VSYNC
++ | IOCTRL31_POC_VI1_HSYNC
++ | IOCTRL31_POC_VI1_CLKENB
++ | IOCTRL31_POC_VI1_CLK
++ | IOCTRL31_POC_VI0_FIELD
++ | IOCTRL31_POC_VI0_DATA11
++ | IOCTRL31_POC_VI0_DATA10
++ | IOCTRL31_POC_VI0_DATA9
++ | IOCTRL31_POC_VI0_DATA8
++ | IOCTRL31_POC_VI0_DATA7
++ | IOCTRL31_POC_VI0_DATA6
++ | IOCTRL31_POC_VI0_DATA6);
++
++ pfc_reg_write(PFC_IOCTRL32, IOCTRL32_POC_FSO_TOE
++ | IOCTRL32_POC_FSO_CFE_1
++ | IOCTRL32_POC_FSO_CFE_0
++ | IOCTRL32_POC_SDA3
++ | IOCTRL32_POC_SCL3);
++
++ pfc_reg_write(PFC_IOCTRL33,0x00000000);
++
++ pfc_reg_write(PFC_IOCTRL40,0x00000000);
++
++
++ /* initialize LSI pin pull-up/down control */
++ pfc_reg_write(PFC_PUD0,0x80000000U);
++ pfc_reg_write(PFC_PUD1,0x1B01C77CU);
++ pfc_reg_write(PFC_PUD2,0x00000000U);
++ pfc_reg_write(PFC_PUD3,0x0F800008U);
++ pfc_reg_write(PFC_PUD4,0x03807C00U);
++
++ /* initialize LSI pin pull-enable register */
++ pfc_reg_write(PFC_PUEN0,0x0035F721U);
++ pfc_reg_write(PFC_PUEN1,0x7E01C700U);
++ pfc_reg_write(PFC_PUEN2,0x003F0000U);
++ pfc_reg_write(PFC_PUEN3,0x07000000U);
++ pfc_reg_write(PFC_PUEN4,0x0381E800U);
++
++ /* initialize positive/negative logic select */
++ mmio_write_32(GPIO_POSNEG0, 0x00000000U);
++ mmio_write_32(GPIO_POSNEG1, 0x00000000U);
++ mmio_write_32(GPIO_POSNEG2, 0x00000000U);
++ mmio_write_32(GPIO_POSNEG3, 0x00000000U);
++ mmio_write_32(GPIO_POSNEG4, 0x00000000U);
++ mmio_write_32(GPIO_POSNEG5, 0x00000000U);
++
++ /* initialize general IO/interrupt switching */
++ mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
++ mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
++ mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
++ mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
++ mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
++ mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
++
++ /* initialize general output register */
++ mmio_write_32(GPIO_OUTDT1, 0x00010000U);
++ mmio_write_32(GPIO_OUTDT4, 0x00400000U);
++ mmio_write_32(GPIO_OUTDT5, 0x00007000U);
++
++ /* initialize general input/output switching */
++ mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
++ mmio_write_32(GPIO_INOUTSEL1, 0x00010000U);
++ mmio_write_32(GPIO_INOUTSEL2, 0x00000000U);
++ mmio_write_32(GPIO_INOUTSEL3, 0x00000000U);
++ mmio_write_32(GPIO_INOUTSEL4, 0x00400000U);
++ mmio_write_32(GPIO_INOUTSEL5, 0x00007000U);
++}
+diff --git a/plat/renesas/rcar/pfc/V3H/pfc_init_v3h.h b/plat/renesas/rcar/pfc/V3H/pfc_init_v3h.h
+new file mode 100644
+index 0000000..6ecedb5
+--- /dev/null
++++ b/plat/renesas/rcar/pfc/V3H/pfc_init_v3h.h
+@@ -0,0 +1,37 @@
++/*
++ * Copyright (c) 2015-2017, Renesas Electronics Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * - Redistributions of source code must retain the above copyright notice,
++ * this list of conditions and the following disclaimer.
++ *
++ * - Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ *
++ * - Neither the name of Renesas nor the names of its contributors may be
++ * used to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef PFC_INIT_V3H_H__
++#define PFC_INIT_V3H_H__
++
++void pfc_init_v3h(void);
++
++#endif /* PFC_INIT_V3H_H__ */
+diff --git a/plat/renesas/rcar/pfc/pfc.mk b/plat/renesas/rcar/pfc/pfc.mk
+index 0ccbe3c..33c76ba 100644
+--- a/plat/renesas/rcar/pfc/pfc.mk
++++ b/plat/renesas/rcar/pfc/pfc.mk
+@@ -35,6 +35,7 @@ ifeq (${RCAR_LSI},${RCAR_AUTO})
+ BL2_SOURCES += plat/renesas/rcar/pfc/M3/pfc_init_m3.c
+ BL2_SOURCES += plat/renesas/rcar/pfc/M3N/pfc_init_m3n.c
+ BL2_SOURCES += plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c
++ BL2_SOURCES += plat/renesas/rcar/pfc/V3H/pfc_init_v3h.c
+
+ else ifdef RCAR_LSI_CUT_COMPAT
+ ifeq (${RCAR_LSI},${RCAR_H3})
+@@ -50,6 +51,9 @@ else ifdef RCAR_LSI_CUT_COMPAT
+ ifeq (${RCAR_LSI},${RCAR_V3M})
+ BL2_SOURCES += plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c
+ endif
++ ifeq (${RCAR_LSI},${RCAR_V3H})
++ BL2_SOURCES += plat/renesas/rcar/pfc/V3H/pfc_init_v3h.c
++ endif
+ else
+ ifeq (${RCAR_LSI},${RCAR_H3})
+ ifeq (${LSI_CUT},10)
+@@ -71,6 +75,9 @@ else
+ ifeq (${RCAR_LSI},${RCAR_V3M})
+ BL2_SOURCES += plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c
+ endif
++ ifeq (${RCAR_LSI},${RCAR_V3H})
++ BL2_SOURCES += plat/renesas/rcar/pfc/V3H/pfc_init_v3h.c
++ endif
+ endif
+
+ BL2_SOURCES += plat/renesas/rcar/pfc/pfc_init.c
+diff --git a/plat/renesas/rcar/pfc/pfc_init.c b/plat/renesas/rcar/pfc/pfc_init.c
+index c270851..94675b1 100644
+--- a/plat/renesas/rcar/pfc/pfc_init.c
++++ b/plat/renesas/rcar/pfc/pfc_init.c
+@@ -40,6 +40,7 @@
+ #include "M3/pfc_init_m3.h"
+ #include "M3N/pfc_init_m3n.h"
+ #include "V3M/pfc_init_v3m.h"
++ #include "V3H/pfc_init_v3h.h"
+ #endif
+ #if RCAR_LSI == RCAR_H3 /* H3 */
+ #include "H3/pfc_init_h3_v1.h"
+@@ -50,10 +51,14 @@
+ #endif
+ #if RCAR_LSI == RCAR_M3N /* M3N */
+ #include "M3N/pfc_init_m3n.h"
++ #include "V3H/pfc_init_v3h.h"
+ #endif
+ #if RCAR_LSI == RCAR_V3M /* V3M */
+ #include "V3M/pfc_init_v3m.h"
+ #endif
++#if RCAR_LSI == RCAR_V3H /* V3H */
++ #include "V3H/pfc_init_v3h.h"
++#endif
+
+ /* Product Register */
+ #define PRR (0xFFF00044U)
+@@ -63,6 +68,7 @@
+ #define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
+ #define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */
+ #define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
++#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */
+ #define PRR_PRODUCT_10 (0x00U)
+ #define PRR_PRODUCT_11 (0x01U)
+ #define PRR_PRODUCT_20 (0x10U)
+@@ -111,6 +117,9 @@ void pfc_init(void)
+ case RCAR_PRODUCT_V3M:
+ pfc_init_v3m();
+ break;
++ case RCAR_PRODUCT_V3H:
++ pfc_init_v3h();
++ break;
+ default:
+ PRR_PRODUCT_ERR(reg);
+ break;
+@@ -159,6 +168,13 @@ void pfc_init(void)
+ pfc_init_v3m();
+ #endif
+ break;
++ case PRR_PRODUCT_V3H:
++#if RCAR_LSI != RCAR_V3H
++ PRR_PRODUCT_ERR(reg);
++#else
++ pfc_init_v3h();
++#endif
++ break;
+ default:
+ PRR_PRODUCT_ERR(reg);
+ break;
+@@ -205,6 +221,11 @@ void pfc_init(void)
+ PRR_PRODUCT_ERR(reg);
+ }
+ pfc_init_v3m();
++ #elif RCAR_LSI == RCAR_V3H /* V3H */
++ if ((PRR_PRODUCT_V3H) != (reg & PRR_PRODUCT_MASK)) {
++ PRR_PRODUCT_ERR(reg);
++ }
++ pfc_init_v3h();
+ #else
+ #error "Don't have PFC initialize routine(unknown)."
+ #endif
+diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
+index 550d829..a19d246 100644
+--- a/plat/renesas/rcar/platform.mk
++++ b/plat/renesas/rcar/platform.mk
+@@ -113,11 +113,13 @@ RCAR_H3:=0
+ RCAR_M3:=1
+ RCAR_M3N:=2
+ RCAR_V3M:=3
++RCAR_V3H:=4
+ RCAR_AUTO:=99
+ $(eval $(call add_define,RCAR_H3))
+ $(eval $(call add_define,RCAR_M3))
+ $(eval $(call add_define,RCAR_M3N))
+ $(eval $(call add_define,RCAR_V3M))
++$(eval $(call add_define,RCAR_V3H))
+ $(eval $(call add_define,RCAR_AUTO))
+ RCAR_CUT_10:=0
+ RCAR_CUT_11:=1
+@@ -195,6 +197,22 @@ else
+ endif
+ $(eval $(call add_define,RCAR_LSI_CUT))
+ endif
++ else ifeq (${LSI},V3H)
++ RCAR_LSI:=${RCAR_V3H}
++ ifndef LSI_CUT
++ # enable compatible function.
++ RCAR_LSI_CUT_COMPAT := 1
++ $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
++ else
++ # disable compatible function.
++ ifeq (${LSI_CUT},10)
++ RCAR_LSI_CUT:=0
++ endif
++ ifeq (${LSI_CUT},20)
++ RCAR_LSI_CUT:=10
++ endif
++ $(eval $(call add_define,RCAR_LSI_CUT))
++ endif
+ else
+ $(error "Error: ${LSI} is not supported.")
+ endif
+diff --git a/plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.c b/plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.c
+new file mode 100644
+index 0000000..af56e33
+--- /dev/null
++++ b/plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.c
+@@ -0,0 +1,651 @@
++/*
++ * Copyright (c) 2015-2017, Renesas Electronics Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * - Redistributions of source code must retain the above copyright notice,
++ * this list of conditions and the following disclaimer.
++ *
++ * - Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ *
++ * - Neither the name of Renesas nor the names of its contributors may be
++ * used to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <stdint.h>
++#include <debug.h>
++#include "qos_init_v3h_v10.h"
++
++
++#define RCAR_QOS_VERSION "rev.0.14"
++
++#define RCAR_QOS_NONE (3U)
++#define RCAR_QOS_TYPE_DEFAULT (0U)
++
++#define RCAR_DRAM_SPLIT_LINEAR (0U)
++#define RCAR_DRAM_SPLIT_4CH (1U)
++#define RCAR_DRAM_SPLIT_2CH (2U)
++#define RCAR_DRAM_SPLIT_AUTO (3U)
++
++#define RST_BASE (0xE6160000U)
++#define RST_MODEMR (RST_BASE + 0x0060U)
++
++#define DBSC_BASE (0xE6790000U)
++#define DBSC_DBDFIPMSTRCNF (DBSC_BASE + 0x0520U)
++#define DBSC_AXARB (DBSC_BASE + 0x0800U)
++#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
++#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
++#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
++#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
++#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
++#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
++#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
++#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
++#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
++#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
++#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
++#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
++#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
++#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
++#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
++#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
++#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
++#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
++#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
++#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
++#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
++#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
++#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
++#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
++#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
++#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
++#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
++#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
++#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
++#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
++#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
++#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
++#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
++#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
++#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
++#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
++#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
++#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
++#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
++#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
++#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
++#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
++#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
++#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
++#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
++#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
++#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
++#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
++#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
++#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
++#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
++#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
++#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
++#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
++#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
++#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
++#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
++#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
++#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
++#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
++#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
++#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
++#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
++#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
++#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
++#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
++#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
++#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
++#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
++#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
++#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
++#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
++#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
++#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
++#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
++
++#define AXI_BASE (0xE6784000U)
++#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
++#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
++#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
++#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
++#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
++#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
++#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
++#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
++#define ADSPLCR0_SWP (0x0CU)
++
++#define MSTAT_BASE (0xE67E0000U)
++#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
++#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
++#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
++#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
++#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
++#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
++#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
++
++#define RALLOC_BASE (0xE67F0000U)
++#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
++#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
++#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
++#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
++#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
++#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
++#define RALLOC_EC (RALLOC_BASE + 0x003CU)
++#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
++#define RALLOC_FSS (RALLOC_BASE + 0x0048U)
++#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
++#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
++#define RALLOC_EARLYR (RALLOC_BASE + 0x0060U)
++#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
++#define RALLOC_STATGEN0 (RALLOC_BASE + 0x0088U)
++
++#define ACTIVE_OR (0xFD812030U)
++
++#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
++
++static inline void io_write_32(uintptr_t addr, uint32_t value)
++{
++ *(volatile uint32_t*)addr = value;
++}
++
++static inline void io_write_64(uintptr_t addr, uint64_t value)
++{
++ *(volatile uint64_t*)addr = value;
++}
++
++typedef struct {
++ uintptr_t addr;
++ uint64_t value;
++} mstat_slot_t;
++
++
++#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
++static const mstat_slot_t mstat_fix[] = {
++ {0x0000U, 0x0000000000000000U},
++ {0x0008U, 0x0000000000000000U},
++ {0x0010U, 0x0000000000000000U},
++ {0x0018U, 0x0000000000000000U},
++ {0x0020U, 0x0000000000000000U},
++ {0x0028U, 0x0000000000000000U},
++ {0x0030U, 0x001004030000FFFFU},
++ {0x0038U, 0x001008060000FFFFU},
++ {0x0040U, 0x001424120000FFFFU},
++ {0x0048U, 0x0000000000000000U},
++ {0x0050U, 0x001404010000FFFFU},
++ {0x0058U, 0x0014100F0000FFFFU},
++ {0x0060U, 0x00140C0C0000FFFFU},
++ {0x0068U, 0x0000000000000000U},
++ {0x0070U, 0x001404010000FFFFU},
++ {0x0078U, 0x001008060000FFFFU},
++ {0x0080U, 0x0000000000000000U},
++ {0x0088U, 0x001424120000FFFFU},
++ {0x0090U, 0x00140C0C0000FFFFU},
++ {0x0098U, 0x0000000000000000U},
++ {0x00A0U, 0x000C04020000FFFFU},
++ {0x00A8U, 0x000C04010000FFFFU},
++ {0x00B0U, 0x000C04010000FFFFU},
++ {0x00B8U, 0x0000000000000000U},
++ {0x00C0U, 0x000C04020000FFFFU},
++ {0x00C8U, 0x000C04010000FFFFU},
++ {0x00D0U, 0x000C04010000FFFFU},
++ {0x00D8U, 0x001020080000FFFFU},
++ {0x00E0U, 0x001008080000FFFFU},
++ {0x00E8U, 0x0000000000000000U},
++ {0x00F0U, 0x001020080000FFFFU},
++ {0x00F8U, 0x000C08060000FFFFU},
++ {0x0100U, 0x0000000000000000U},
++ {0x0108U, 0x0000000000000000U},
++ {0x0110U, 0x001008080000FFFFU},
++ {0x0118U, 0x000C100F0000FFFFU},
++ {0x0120U, 0x000C100F0000FFFFU},
++ {0x0128U, 0x0000000000000000U},
++ {0x0130U, 0x0000000000000000U},
++ {0x0138U, 0x00100C0A0000FFFFU},
++ {0x0140U, 0x00100C0A0000FFFFU},
++ {0x0148U, 0x0000000000000000U},
++ {0x0150U, 0x00100C0C0000FFFFU},
++ {0x0158U, 0x00100C0C0000FFFFU},
++ {0x0160U, 0x00100C0A0000FFFFU},
++ {0x0168U, 0x00100C0A0000FFFFU},
++ {0x0170U, 0x0000000000000000U},
++ {0x0178U, 0x001008050000FFFFU},
++ {0x0180U, 0x001008050000FFFFU},
++ {0x0188U, 0x0000000000000000U},
++ {0x0190U, 0x00102C2A0000FFFFU},
++ {0x0198U, 0x00102C2A0000FFFFU},
++ {0x01A0U, 0x00100C0A0000FFFFU},
++ {0x01A8U, 0x00100C0A0000FFFFU},
++ {0x01B0U, 0x0000000000000000U},
++ {0x01B8U, 0x0000000000000000U},
++ {0x01C0U, 0x0000000000000000U},
++ {0x01C8U, 0x0000000000000000U},
++ {0x01D0U, 0x0000000000000000U},
++ {0x01D8U, 0x0000000000000000U},
++ {0x01E0U, 0x0000000000000000U},
++ {0x01E8U, 0x0000000000000000U},
++ {0x01F0U, 0x0000000000000000U},
++ {0x01F8U, 0x0000000000000000U},
++ {0x0200U, 0x0000000000000000U},
++ {0x0208U, 0x0000000000000000U},
++ {0x0210U, 0x0000000000000000U},
++ {0x0218U, 0x0000000000000000U},
++ {0x0220U, 0x0000000000000000U},
++ {0x0228U, 0x0000000000000000U},
++ {0x0230U, 0x0000000000000000U},
++ {0x0238U, 0x0000000000000000U},
++ {0x0240U, 0x0000000000000000U},
++ {0x0248U, 0x0000000000000000U},
++ {0x0250U, 0x0000000000000000U},
++ {0x0258U, 0x0000000000000000U},
++ {0x0260U, 0x0000000000000000U},
++ {0x0268U, 0x001408010000FFFFU},
++ {0x0270U, 0x001404010000FFFFU},
++ {0x0278U, 0x0000000000000000U},
++ {0x0280U, 0x0000000000000000U},
++ {0x0288U, 0x0000000000000000U},
++ {0x0290U, 0x001408010000FFFFU},
++ {0x0298U, 0x001404010000FFFFU},
++ {0x02A0U, 0x000C04010000FFFFU},
++ {0x02A8U, 0x000C04010000FFFFU},
++ {0x02B0U, 0x001404010000FFFFU},
++ {0x02B8U, 0x0000000000000000U},
++ {0x02C0U, 0x0000000000000000U},
++ {0x02C8U, 0x0000000000000000U},
++ {0x02D0U, 0x000C04010000FFFFU},
++ {0x02D8U, 0x000C04010000FFFFU},
++ {0x02E0U, 0x001404010000FFFFU},
++ {0x02E8U, 0x0000000000000000U},
++ {0x02F0U, 0x0000000000000000U},
++ {0x02F8U, 0x0000000000000000U},
++ {0x0300U, 0x0000000000000000U},
++ {0x0308U, 0x0000000000000000U},
++ {0x0310U, 0x0000000000000000U},
++ {0x0318U, 0x0000000000000000U},
++ {0x0320U, 0x0000000000000000U},
++ {0x0328U, 0x0000000000000000U},
++ {0x0330U, 0x0000000000000000U},
++ {0x0338U, 0x0000000000000000U},
++ {0x0340U, 0x0000000000000000U},
++ {0x0348U, 0x0000000000000000U},
++ {0x0350U, 0x0000000000000000U},
++ {0x0358U, 0x0000000000000000U},
++ {0x0360U, 0x0000000000000000U},
++ {0x0368U, 0x0000000000000000U},
++};
++
++static const mstat_slot_t mstat_be[] = {
++ {0x0000U, 0x001200100C89C401U},
++ {0x0008U, 0x001200100C89C401U},
++ {0x0010U, 0x001200100C89C401U},
++ {0x0018U, 0x001200100C89C401U},
++ {0x0020U, 0x0000000000000000U},
++ {0x0028U, 0x001200100C80FC01U},
++ {0x0030U, 0x0000000000000000U},
++ {0x0038U, 0x0000000000000000U},
++ {0x0040U, 0x0000000000000000U},
++ {0x0048U, 0x0000000000000000U},
++ {0x0050U, 0x0000000000000000U},
++ {0x0058U, 0x0000000000000000U},
++ {0x0060U, 0x0000000000000000U},
++ {0x0068U, 0x0000000000000000U},
++ {0x0070U, 0x0000000000000000U},
++ {0x0078U, 0x0000000000000000U},
++ {0x0080U, 0x0000000000000000U},
++ {0x0088U, 0x0000000000000000U},
++ {0x0090U, 0x0000000000000000U},
++ {0x0098U, 0x0000000000000000U},
++ {0x00A0U, 0x0000000000000000U},
++ {0x00A8U, 0x0000000000000000U},
++ {0x00B0U, 0x0000000000000000U},
++ {0x00B8U, 0x0000000000000000U},
++ {0x00C0U, 0x0000000000000000U},
++ {0x00C8U, 0x0000000000000000U},
++ {0x00D0U, 0x0000000000000000U},
++ {0x00D8U, 0x0000000000000000U},
++ {0x00E0U, 0x0000000000000000U},
++ {0x00E8U, 0x0000000000000000U},
++ {0x00F0U, 0x0000000000000000U},
++ {0x00F8U, 0x0000000000000000U},
++ {0x0100U, 0x0000000000000000U},
++ {0x0108U, 0x0000000000000000U},
++ {0x0110U, 0x0000000000000000U},
++ {0x0118U, 0x0000000000000000U},
++ {0x0120U, 0x0000000000000000U},
++ {0x0128U, 0x0000000000000000U},
++ {0x0130U, 0x0000000000000000U},
++ {0x0138U, 0x0000000000000000U},
++ {0x0140U, 0x0000000000000000U},
++ {0x0148U, 0x0000000000000000U},
++ {0x0150U, 0x0000000000000000U},
++ {0x0158U, 0x0000000000000000U},
++ {0x0160U, 0x0000000000000000U},
++ {0x0168U, 0x0000000000000000U},
++ {0x0170U, 0x0000000000000000U},
++ {0x0178U, 0x0000000000000000U},
++ {0x0180U, 0x0000000000000000U},
++ {0x0188U, 0x0000000000000000U},
++ {0x0190U, 0x0000000000000000U},
++ {0x0198U, 0x0000000000000000U},
++ {0x01A0U, 0x0000000000000000U},
++ {0x01A8U, 0x0000000000000000U},
++ {0x01B0U, 0x0000000000000000U},
++ {0x01B8U, 0x0000000000000000U},
++ {0x01C0U, 0x001100800C8FFC01U},
++ {0x01C8U, 0x001100800C8FFC01U},
++ {0x01D0U, 0x001100800C8FFC01U},
++ {0x01D8U, 0x001100800C8FFC01U},
++ {0x01E0U, 0x0000000000000000U},
++ {0x01E8U, 0x001200100C80FC01U},
++ {0x01F0U, 0x001100100C80FC01U},
++ {0x01F8U, 0x0000000000000000U},
++ {0x0200U, 0x0000000000000000U},
++ {0x0208U, 0x001200100C80FC01U},
++ {0x0210U, 0x001100100C80FC01U},
++ {0x0218U, 0x001100100C825801U},
++ {0x0220U, 0x001100100C825801U},
++ {0x0228U, 0x0000000000000000U},
++ {0x0230U, 0x001100100C825801U},
++ {0x0238U, 0x001100100C825801U},
++ {0x0240U, 0x001200100C8BB801U},
++ {0x0248U, 0x001100200C8FFC01U},
++ {0x0250U, 0x001200100C8BB801U},
++ {0x0258U, 0x001100200C8FFC01U},
++ {0x0260U, 0x001100100C84E401U},
++ {0x0268U, 0x0000000000000000U},
++ {0x0270U, 0x0000000000000000U},
++ {0x0278U, 0x001100100C81F401U},
++ {0x0280U, 0x0000000000000000U},
++ {0x0288U, 0x0000000000000000U},
++ {0x0290U, 0x0000000000000000U},
++ {0x0298U, 0x0000000000000000U},
++ {0x02A0U, 0x0000000000000000U},
++ {0x02A8U, 0x0000000000000000U},
++ {0x02B0U, 0x0000000000000000U},
++ {0x02B8U, 0x001100100C803401U},
++ {0x02C0U, 0x0000000000000000U},
++ {0x02C8U, 0x0000000000000000U},
++ {0x02D0U, 0x0000000000000000U},
++ {0x02D8U, 0x0000000000000000U},
++ {0x02E0U, 0x0000000000000000U},
++ {0x02E8U, 0x001100100C803401U},
++ {0x02F0U, 0x001100300C8FFC01U},
++ {0x02F8U, 0x001100500C8FFC01U},
++ {0x0300U, 0x0000000000000000U},
++ {0x0308U, 0x001100300C8FFC01U},
++ {0x0310U, 0x001100500C8FFC01U},
++ {0x0318U, 0x001200100C803401U},
++ {0x0320U, 0x001100300C8FFC01U},
++ {0x0328U, 0x001100500C8FFC01U},
++ {0x0330U, 0x001100300C8FFC01U},
++ {0x0338U, 0x001100500C8FFC01U},
++ {0x0340U, 0x0000000000000000U},
++ {0x0348U, 0x0000000000000000U},
++ {0x0350U, 0x0000000000000000U},
++ {0x0358U, 0x0000000000000000U},
++ {0x0360U, 0x0000000000000000U},
++ {0x0368U, 0x0000000000000000U},
++};
++#endif
++
++static void dbsc_setting(void)
++{
++ uint32_t md=0;
++
++ /* BUFCAM settings */
++ //DBSC_DBCAM0CNF0 not set
++ io_write_32(DBSC_DBCAM0CNF1, 0x00043218U); //dbcam0cnf1
++ io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U); //dbcam0cnf2
++ io_write_32(DBSC_DBCAM0CNF3, 0x00000000U); //dbcam0cnf3
++ io_write_32(DBSC_DBSCHCNT0, 0x000F0037U); //dbschcnt0
++ //DBSC_DBSCHCNT1 not set
++ io_write_32(DBSC_DBSCHSZ0, 0x00000001U); //dbschsz0
++ io_write_32(DBSC_DBSCHRW0, 0x22421111U); //dbschrw0
++ io_write_32(DBSC_DBSCHRW1, 0x00000034U); //dbschrw1
++
++ md = (*((volatile uint32_t*)RST_MODEMR) & 0x000A0000) >> 17;
++
++ switch (md) {
++ case 0x0:
++ /* DDR3200 */
++ io_write_32(DBSC_SCFCTST2, 0x012F1123U);
++ break;
++ case 0x1: //MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4)
++ /* DDR2800 */
++ io_write_32(DBSC_SCFCTST2, 0x012F1123U);
++ break;
++ case 0x4: //MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4)
++ /* DDR2400 */
++ io_write_32(DBSC_SCFCTST2, 0x012F1123U);
++ break;
++ default: //MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4)
++ /* DDR1600 */
++ io_write_32(DBSC_SCFCTST2, 0x012F1123U);
++ break;
++ }
++
++ /* QoS Settings */
++ io_write_32(DBSC_DBSCHQOS_0_0, 0x00000F00U);
++ io_write_32(DBSC_DBSCHQOS_0_1, 0x00000B00U);
++ io_write_32(DBSC_DBSCHQOS_0_2, 0x00000000U);
++ io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000U);
++ //DBSC_DBSCHQOS_1_0 not set
++ //DBSC_DBSCHQOS_1_1 not set
++ //DBSC_DBSCHQOS_1_2 not set
++ //DBSC_DBSCHQOS_1_3 not set
++ //DBSC_DBSCHQOS_2_0 not set
++ //DBSC_DBSCHQOS_2_1 not set
++ //DBSC_DBSCHQOS_2_2 not set
++ //DBSC_DBSCHQOS_2_3 not set
++ //DBSC_DBSCHQOS_3_0 not set
++ //DBSC_DBSCHQOS_3_1 not set
++ //DBSC_DBSCHQOS_3_2 not set
++ //DBSC_DBSCHQOS_3_3 not set
++ io_write_32(DBSC_DBSCHQOS_4_0, 0x00000300U);
++ io_write_32(DBSC_DBSCHQOS_4_1, 0x000002F0U);
++ io_write_32(DBSC_DBSCHQOS_4_2, 0x00000200U);
++ io_write_32(DBSC_DBSCHQOS_4_3, 0x00000100U);
++ //DBSC_DBSCHQOS_5_0 not set
++ //DBSC_DBSCHQOS_5_1 not set
++ //DBSC_DBSCHQOS_5_2 not set
++ //DBSC_DBSCHQOS_5_3 not set
++ //DBSC_DBSCHQOS_6_0 not set
++ //DBSC_DBSCHQOS_6_1 not set
++ //DBSC_DBSCHQOS_6_2 not set
++ //DBSC_DBSCHQOS_6_3 not set
++ //DBSC_DBSCHQOS_7_0 not set
++ //DBSC_DBSCHQOS_7_1 not set
++ //DBSC_DBSCHQOS_7_2 not set
++ //DBSC_DBSCHQOS_7_3 not set
++ //DBSC_DBSCHQOS_8_0 not set
++ //DBSC_DBSCHQOS_8_1 not set
++ //DBSC_DBSCHQOS_8_2 not set
++ //DBSC_DBSCHQOS_8_3 not set
++ io_write_32(DBSC_DBSCHQOS_9_0, 0x00000300U);
++ io_write_32(DBSC_DBSCHQOS_9_1, 0x000002F0U);
++ io_write_32(DBSC_DBSCHQOS_9_2, 0x00000200U);
++ io_write_32(DBSC_DBSCHQOS_9_3, 0x00000100U);
++ //DBSC_DBSCHQOS_10_0 not set
++ //DBSC_DBSCHQOS_10_1 not set
++ //DBSC_DBSCHQOS_10_2 not set
++ //DBSC_DBSCHQOS_10_3 not set
++ //DBSC_DBSCHQOS_11_0 not set
++ //DBSC_DBSCHQOS_11_1 not set
++ //DBSC_DBSCHQOS_11_2 not set
++ //DBSC_DBSCHQOS_11_3 not set
++ io_write_32(DBSC_DBSCHQOS_12_0, 0x00000040U);
++ io_write_32(DBSC_DBSCHQOS_12_1, 0x00000030U);
++ io_write_32(DBSC_DBSCHQOS_12_2, 0x00000020U);
++ io_write_32(DBSC_DBSCHQOS_12_3, 0x00000010U);
++ io_write_32(DBSC_DBSCHQOS_13_0, 0x00000100U);
++ io_write_32(DBSC_DBSCHQOS_13_1, 0x000000F0U);
++ io_write_32(DBSC_DBSCHQOS_13_2, 0x000000A0U);
++ io_write_32(DBSC_DBSCHQOS_13_3, 0x00000040U);
++ io_write_32(DBSC_DBSCHQOS_14_0, 0x000000C0U);
++ io_write_32(DBSC_DBSCHQOS_14_1, 0x000000B0U);
++ io_write_32(DBSC_DBSCHQOS_14_2, 0x00000080U);
++ io_write_32(DBSC_DBSCHQOS_14_3, 0x00000040U);
++ io_write_32(DBSC_DBSCHQOS_15_0, 0x00000040U);
++ io_write_32(DBSC_DBSCHQOS_15_1, 0x00000030U);
++ io_write_32(DBSC_DBSCHQOS_15_2, 0x00000020U);
++ io_write_32(DBSC_DBSCHQOS_15_3, 0x00000010U);
++}
++
++void qos_init_v3h_v10(void)
++{
++ /* this setting value is H3 *
++ * Respond by updating in the future */
++ dbsc_setting();
++
++ /* DRAM Split Address mapping */
++#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
++ (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
++ NOTICE("BL2: DRAM Split is 4ch\n");
++ io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
++ | ADSPLCR0_SPLITSEL(0xFFU)
++ | ADSPLCR0_AREA(0x1BU)
++ | ADSPLCR0_SWP);
++ io_write_32(AXI_ADSPLCR1, 0x00000000U);
++ io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
++ io_write_32(AXI_ADSPLCR3, 0x00000000U);
++#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
++ NOTICE("BL2: DRAM Split is 2ch\n");
++ io_write_32(AXI_ADSPLCR0, 0x00000000U);
++ io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
++ | ADSPLCR0_SPLITSEL(0xFFU)
++ | ADSPLCR0_AREA(0x1BU)
++ | ADSPLCR0_SWP);
++ io_write_32(AXI_ADSPLCR2, 0x00000000U);
++ io_write_32(AXI_ADSPLCR3, 0x00000000U);
++#else
++ NOTICE("BL2: DRAM Split is OFF\n");
++#endif
++
++#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
++#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
++ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
++#endif
++
++ /* Resource Alloc setting */
++ io_write_32(RALLOC_RAS, 0x00000044U);
++ io_write_32(RALLOC_FIXTH, 0x000F0005U);
++ io_write_32(RALLOC_REGGD, 0x00000000U);
++ io_write_64(RALLOC_DANN, 0x0404010002020201U);
++ io_write_32(RALLOC_DANT, 0x0020100AU);
++ io_write_32(RALLOC_EC, 0x00000000U);
++ io_write_64(RALLOC_EMS, 0x0000000000000000U);
++ io_write_32(RALLOC_FSS, 0x000003e8U);
++ io_write_32(RALLOC_INSFC, 0xC7840001U);
++ io_write_32(RALLOC_BERR, 0x00000000U);
++ io_write_32(RALLOC_EARLYR, 0x00000000U);
++ io_write_32(RALLOC_RACNT0, 0x00010003U);
++
++ /* GPU Boost Mode */
++ io_write_32(RALLOC_STATGEN0, 0x00000001U);
++ io_write_32(ACTIVE_OR, 0x00000000U); /* 0:enable, 1:disable */
++
++ /* MSTAT setting */
++ io_write_32(MSTAT_SL_INIT, 0x0305007DU);
++ io_write_32(MSTAT_REF_ARS, 0x00330000U);
++
++ /* MSTAT SRAM setting */
++ {
++ uint32_t i;
++
++ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
++ io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
++ mstat_fix[i].value);
++ io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
++ mstat_fix[i].value);
++ }
++ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
++ io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
++ mstat_be[i].value);
++ io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
++ mstat_be[i].value);
++ }
++ }
++
++ /* AXI-IF arbitration setting */
++ io_write_32(DBSC_AXARB, 0x00000000U);
++
++ /* 3DG bus Leaf setting */
++ io_write_32(0xFD820800U, 0x00000000U);
++ io_write_32(0xFD821800U, 0x00000000U);
++ io_write_32(0xFD822800U, 0x00000000U);
++ io_write_32(0xFD823800U, 0x00000000U);
++ io_write_32(0xFD824800U, 0x00000000U);
++ io_write_32(0xFD825800U, 0x00000000U);
++ io_write_32(0xFD826800U, 0x00000000U);
++ io_write_32(0xFD827800U, 0x00000000U);
++
++ /* VIO bus Leaf setting */
++ io_write_32(0xFEB89800, 0x00000000U);
++ io_write_32(0xFEB8A800, 0x00000000U);
++ io_write_32(0xFEB8B800, 0x00000000U);
++ io_write_32(0xFEB8C800, 0x00000000U);
++
++ /* HSC bus Leaf setting */
++ io_write_32(0xE6430800, 0x00000000U);
++ io_write_32(0xE6431800, 0x00000000U);
++ io_write_32(0xE6432800, 0x00000000U);
++ io_write_32(0xE6433800, 0x00000000U);
++
++ /* MP bus Leaf setting */
++ io_write_32(0xEC620800, 0x00000000U);
++ io_write_32(0xEC621800, 0x00000000U);
++
++ /* PERIE bus Leaf setting */
++ io_write_32(0xE7760800, 0x00000000U);
++ io_write_32(0xE7768800, 0x00000000U);
++
++ /* PERIW bus Leaf setting */
++ io_write_32(0xE6760800, 0x00000000U);
++ io_write_32(0xE6768800, 0x00000000U);
++
++ /* RT bus Leaf setting */
++ io_write_32(0xFFC50800U, 0x00000000U);
++ io_write_32(0xFFC51800U, 0x00000000U);
++
++ /* CCI bus Leaf setting */
++ io_write_32(0xF1300800, 0x00000003U);
++ io_write_32(0xF1340800, 0x00000003U);
++ io_write_32(0xF1380800, 0x00000003U);
++ io_write_32(0xF13C0800, 0x00000003U);
++
++ /* Resource Alloc start */
++ io_write_32(RALLOC_RAEN, 0x00000001U);
++
++ /* MSTAT start */
++ io_write_32(MSTAT_STATQC, 0x00000001U);
++#else
++ NOTICE("BL2: QoS is None\n");
++
++ /* Resource Alloc setting */
++ io_write_32(RALLOC_EC, 0x00000000U);
++ /* Resource Alloc start */
++ io_write_32(RALLOC_RAEN, 0x00000001U);
++#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
++}
+diff --git a/plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.h b/plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.h
+new file mode 100644
+index 0000000..893d46f
+--- /dev/null
++++ b/plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.h
+@@ -0,0 +1,37 @@
++/*
++ * Copyright (c) 2015-2017, Renesas Electronics Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * - Redistributions of source code must retain the above copyright notice,
++ * this list of conditions and the following disclaimer.
++ *
++ * - Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ *
++ * - Neither the name of Renesas nor the names of its contributors may be
++ * used to endorse or promote products derived from this software without
++ * specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef QOS_INIT_H_H3_V20__
++#define QOS_INIT_H_H3_V20__
++
++void qos_init_v3h_v10(void);
++
++#endif /* QOS_INIT_H_H3_V20__ */
+diff --git a/plat/renesas/rcar/qos/qos.mk b/plat/renesas/rcar/qos/qos.mk
+index 161ab74..39c9c49 100644
+--- a/plat/renesas/rcar/qos/qos.mk
++++ b/plat/renesas/rcar/qos/qos.mk
+@@ -37,6 +37,7 @@ ifeq (${RCAR_LSI},${RCAR_AUTO})
+ BL2_SOURCES += plat/renesas/rcar/qos/M3/qos_init_m3_v11.c
+ BL2_SOURCES += plat/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+ BL2_SOURCES += plat/renesas/rcar/qos/V3M/qos_init_v3m.c
++ BL2_SOURCES += plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.c
+ else ifdef RCAR_LSI_CUT_COMPAT
+ ifeq (${RCAR_LSI},${RCAR_H3})
+ BL2_SOURCES += plat/renesas/rcar/qos/H3/qos_init_h3_v10.c
+@@ -53,6 +54,9 @@ else ifdef RCAR_LSI_CUT_COMPAT
+ ifeq (${RCAR_LSI},${RCAR_V3M})
+ BL2_SOURCES += plat/renesas/rcar/qos/V3M/qos_init_v3m.c
+ endif
++ ifeq (${RCAR_LSI},${RCAR_V3H})
++ BL2_SOURCES += plat/renesas/rcar/qos/V3H/qos_init_v3h_v10.c
++ endif
+ else
+ ifeq (${RCAR_LSI},${RCAR_H3})
+ ifeq (${LSI_CUT},10)
+@@ -87,6 +91,9 @@ else
+ ifeq (${RCAR_LSI},${RCAR_V3M})
+ BL2_SOURCES += plat/renesas/rcar/qos/V3M/qos_init_v3m.c
+ endif
++ ifeq (${RCAR_LSI},${RCAR_V3H})
++ BL2_SOURCES += plat/renesas/rcar/qos/V3M/qos_init_v3h_v10.c
++ endif
+ endif
+
+ BL2_SOURCES += plat/renesas/rcar/qos/qos_init.c
+diff --git a/plat/renesas/rcar/qos/qos_init.c b/plat/renesas/rcar/qos/qos_init.c
+index 86ee492..07aaac2 100644
+--- a/plat/renesas/rcar/qos/qos_init.c
++++ b/plat/renesas/rcar/qos/qos_init.c
+@@ -42,6 +42,7 @@
+ #include "M3/qos_init_m3_v11.h"
+ #include "M3N/qos_init_m3n_v10.h"
+ #include "V3M/qos_init_v3m.h"
++ #include "V3H/qos_init_v3h_v10.h"
+ #endif
+ #if RCAR_LSI == RCAR_H3 /* H3 */
+ #include "H3/qos_init_h3_v10.h"
+@@ -54,10 +55,14 @@
+ #endif
+ #if RCAR_LSI == RCAR_M3N /* M3N */
+ #include "M3N/qos_init_m3n_v10.h"
++ #include "V3H/qos_init_v3h.h"
+ #endif
+ #if RCAR_LSI == RCAR_V3M /* V3M */
+ #include "V3M/qos_init_v3m.h"
+ #endif
++#if RCAR_LSI == RCAR_V3H /* V3H */
++ #include "V3H/qos_init_v3h_v10.h"
++#endif
+
+ /* Product Register */
+ #define PRR (0xFFF00044U)
+@@ -67,6 +72,7 @@
+ #define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
+ #define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */
+ #define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
++#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */
+ #define PRR_PRODUCT_10 (0x00U)
+ #define PRR_PRODUCT_11 (0x01U)
+ #define PRR_PRODUCT_20 (0x10U)
+@@ -147,6 +153,19 @@ void qos_init(void)
+ PRR_PRODUCT_ERR(reg);
+ #endif
+ break;
++ case PRR_PRODUCT_V3H:
++ #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3H)
++ switch (reg & PRR_CUT_MASK) {
++ case PRR_PRODUCT_10:
++ case PRR_PRODUCT_20:
++ default:
++ qos_init_v3h_v10();
++ break;
++ }
++ #else
++ PRR_PRODUCT_ERR(reg);
++ #endif
++ break;
+ default:
+ PRR_PRODUCT_ERR(reg);
+ break;
+@@ -205,6 +224,13 @@ void qos_init(void)
+ PRR_PRODUCT_ERR(reg);
+ }
+ qos_init_v3m();
++ #elif RCAR_LSI == RCAR_V3H /* V3H */
++ /* V3H Cut 10 or later */
++ if ((PRR_PRODUCT_V3H)
++ != (reg & (PRR_PRODUCT_MASK))) {
++ PRR_PRODUCT_ERR(reg);
++ }
++ qos_init_v3h_v10();
+ #else
+ #error "Don't have QoS initialize routine(Unknown chip)."
+ #endif
+diff --git a/plat/renesas/rcar/rcar_def.h b/plat/renesas/rcar/rcar_def.h
+index ddbca3b..d8fd976 100644
+--- a/plat/renesas/rcar/rcar_def.h
++++ b/plat/renesas/rcar/rcar_def.h
+@@ -79,7 +79,7 @@
+ #define DEVICE_RCAR_BASE 0xE6000000U
+ #define DEVICE_RCAR_SIZE 0x00300000U
+
+-#if RCAR_LSI == RCAR_V3M
++#if RCAR_LSI == RCAR_V3M || RCAR_LSI == RCAR_V3H
+ #define DEVICE_RCAR_BASE2 MAKE_U(0xE6370000)
+ #else
+ #define DEVICE_RCAR_BASE2 MAKE_U(0xE6360000)
+@@ -261,6 +261,7 @@
+ #define RCAR_PRODUCT_M3 (0x00005200U)
+ #define RCAR_PRODUCT_V3M (0x00005400U)
+ #define RCAR_PRODUCT_M3N (0x00005500U)
++#define RCAR_PRODUCT_V3H (0x00005600U)
+ #define RCAR_CUT_ES10 (0x00000000U)
+ #define RCAR_CUT_ES11 (0x00000001U)
+ #define RCAR_CUT_ES20 (0x00000010U)
+diff --git a/tools/dummy_create/makefile b/tools/dummy_create/makefile
+index f73dc30..eb83556 100644
+--- a/tools/dummy_create/makefile
++++ b/tools/dummy_create/makefile
+@@ -110,8 +110,13 @@ $(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6)
+ -o $(OUTPUT_FILE_SA6) \
+ -Map $(FILE_NAME_SA6).map \
+
++ifeq (${LSI},V3H)
++ $(objcopy) -O srec --adjust-vma=0xEB220000 --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec
++ $(objcopy) -O binary --adjust-vma=0xEB220000 --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin
++else
+ $(objcopy) -O srec --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec
+ $(objcopy) -O binary --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin
++endif
+
+ ###################################################
+ # Compile
+--
+1.9.1
+
diff --git a/meta-rcar-gen3-adas/recipes-bsp/br-test/br-test.bb b/meta-rcar-gen3-adas/recipes-bsp/br-test/br-test.bb
new file mode 100644
index 0000000..c3c13f2
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-bsp/br-test/br-test.bb
@@ -0,0 +1,23 @@
+SUMMARY = "Tool to communicate with Broadcom switch"
+SECTION = "core"
+
+LICENSE = "CLOSED"
+
+PE = "1"
+PV = "0.1"
+
+SRC_URI = " \
+ file://br-test.tar.gz \
+"
+
+S = "${WORKDIR}/br-test"
+
+do_install() {
+ install -d ${D}${bindir}
+
+ install -m 755 br_test ${D}${bindir}
+}
+
+FILES_${PN} = " \
+ ${bindir}/br_test \
+"
diff --git a/meta-rcar-gen3-adas/recipes-bsp/br-test/files/br-test.tar.gz b/meta-rcar-gen3-adas/recipes-bsp/br-test/files/br-test.tar.gz
new file mode 100644
index 0000000..14dfa8c
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-bsp/br-test/files/br-test.tar.gz
Binary files differ
diff --git a/meta-rcar-gen3-adas/recipes-bsp/cr7-loader/cr7-loader_git.bb b/meta-rcar-gen3-adas/recipes-bsp/cr7-loader/cr7-loader_git.bb
new file mode 100644
index 0000000..767692c
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-bsp/cr7-loader/cr7-loader_git.bb
@@ -0,0 +1,47 @@
+DESCRIPTION = "CR7 Loader"
+
+LICENSE = "BSD"
+LIC_FILES_CHKSUM = "file://license.md;md5=9b6b96211116d6143a7f1d681d39b13d"
+
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+inherit deploy
+
+S = "${WORKDIR}/git"
+
+BRANCH = "rcar_gen3"
+SRC_URI = "git://github.com/CogentEmbedded/cr7-loader.git;branch=${BRANCH}"
+SRCREV = "f06b622d9f91771076e755aea1aad5fddcb6f172"
+
+PV = "v1.0+renesas+git"
+
+COMPATIBLE_MACHINE = "eagle|condor|v3msk|v3mzf|v3hsk"
+PLATFORM = "rcar"
+
+CR7_OPT_r8a7797 = "LSI=V3M RCAR_DRAM_SPLIT=0 RCAR_KICK_MAIN_CPU=2 RCAR_SECURE_BOOT=0"
+CR7_OPT_r8a7798 = "LSI=V3H RCAR_DRAM_SPLIT=0 RCAR_KICK_MAIN_CPU=2 RCAR_SECURE_BOOT=0"
+
+do_compile() {
+ wget https://releases.linaro.org/components/toolchain/binaries/5.1-2015.08/arm-eabi/gcc-linaro-5.1-2015.08-x86_64_arm-eabi.tar.xz
+ tar xfJ gcc-linaro-5.1-2015.08-x86_64_arm-eabi.tar.xz
+
+ CROSS_COMPILE=./gcc-linaro-5.1-2015.08-x86_64_arm-eabi/bin/arm-eabi- make ${CR7_OPT} clean
+ CROSS_COMPILE=./gcc-linaro-5.1-2015.08-x86_64_arm-eabi/bin/arm-eabi- make ${CR7_OPT}
+}
+
+do_deploy() {
+ # Create deploy folder
+ install -d ${DEPLOYDIR}
+
+ # Copy CR7 Loader to deploy folder
+ install -m 0644 ${S}/cr7_loader.elf ${DEPLOYDIR}/cr7-${MACHINE}.elf
+ install -m 0644 ${S}/cr7_loader.bin ${DEPLOYDIR}/cr7-${MACHINE}.bin
+ install -m 0644 ${S}/cr7_loader.srec ${DEPLOYDIR}/cr7-${MACHINE}.srec
+
+ install -m 0644 ${S}/bootparam_sa0.srec ${DEPLOYDIR}/bootparam_sa0.bin
+ install -m 0644 ${S}/bootparam_sa0.srec ${DEPLOYDIR}/bootparam_sa0.srec
+
+ install -m 0644 ${S}/cert_header_sa3.srec ${DEPLOYDIR}/cert_header_sa3.srec
+}
+
+addtask deploy before do_build after do_compile
diff --git a/meta-rcar-gen3-adas/recipes-bsp/spidev-test/files/spidev-test.tar.gz b/meta-rcar-gen3-adas/recipes-bsp/spidev-test/files/spidev-test.tar.gz
new file mode 100644
index 0000000..afa5f1a
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-bsp/spidev-test/files/spidev-test.tar.gz
Binary files differ
diff --git a/meta-rcar-gen3-adas/recipes-bsp/spidev-test/spidev-test_1.0.bb b/meta-rcar-gen3-adas/recipes-bsp/spidev-test/spidev-test_1.0.bb
new file mode 100644
index 0000000..06d39b6
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-bsp/spidev-test/spidev-test_1.0.bb
@@ -0,0 +1,21 @@
+SUMMARY = "SPI device test utility"
+LICENSE = "GPLv2"
+LIC_FILES_CHKSUM = "file://COPYING;md5=d47c37512bd65656e8f130581ee80783"
+
+S = "${WORKDIR}/spidev-test"
+
+SRC_URI = " \
+ file://spidev-test.tar.gz \
+"
+
+do_compile() {
+ cd ${S}
+ make all || die
+}
+
+do_install() {
+ install -d ${D}${bindir}
+ install -m 755 ${S}/spidev_test ${D}${bindir}
+}
+
+FILES_${PN} = "${bindir}/spidev_test"
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0012-ARM-rcar_gen3-Add-I2C-definitions.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0012-ARM-rcar_gen3-Add-I2C-definitions.patch
new file mode 100644
index 0000000..020fb0e
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0012-ARM-rcar_gen3-Add-I2C-definitions.patch
@@ -0,0 +1,32 @@
+From ca6dafba06be8ae842fa2eb7d189e1e2510c7784 Mon Sep 17 00:00:00 2001
+From: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>
+Date: Wed, 31 Jan 2018 16:12:00 +0300
+Subject: [PATCH 1/2] ARM: rcar_gen3: Add I2C definitions
+
+ARM: rcar_gen3: add support rcar-i2c for gen3
+
+Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>
+---
+ arch/arm/include/asm/arch-rcar_gen3/rcar-base.h | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h b/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h
+index 6ba8afd..d81f34b 100644
+--- a/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h
++++ b/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h
+@@ -78,6 +78,12 @@
+ /* SH-I2C */
+ #define CONFIG_SYS_I2C_SH_BASE0 0xE60B0000
+
++/* RCAR-I2C */
++#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6500000
++#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6508000
++#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6510000
++#define CONFIG_SYS_RCAR_I2C3_BASE 0xE66D0000
++
+ /* PFC */
+ #define PFC_PUEN6 0xE6060418
+ #define PUEN_USB1_OVC (1 << 2)
+--
+1.9.1
+
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/00121-i2c-rcar_i2c-add-16bit-addressing.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/00121-i2c-rcar_i2c-add-16bit-addressing.patch
new file mode 100644
index 0000000..ccd0dcd
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/00121-i2c-rcar_i2c-add-16bit-addressing.patch
@@ -0,0 +1,88 @@
+From ae18804d5b0542066b92d6f269748cd0e860b37f Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Fri, 16 Feb 2018 22:13:02 +0300
+Subject: [PATCH] i2c: rcar_i2c: add 16bit addressing
+
+This adds 16bit addressing for RCAR I2C
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+---
+ drivers/i2c/rcar_i2c.c | 37 +++++++++++++++++++++++++++++++------
+ 1 file changed, 31 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
+index 90ad116..017ae0b 100644
+--- a/drivers/i2c/rcar_i2c.c
++++ b/drivers/i2c/rcar_i2c.c
+@@ -88,9 +88,21 @@ static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev)
+ }
+
+ static int
+-rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size)
++rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, int alen, u8 *val, int size)
+ {
+- rcar_i2c_raw_rw_common(dev, chip, addr);
++ if (alen == sizeof(u8)) {
++ rcar_i2c_raw_rw_common(dev, chip, addr);
++ } else {
++ rcar_i2c_raw_rw_common(dev, chip, addr >> 8);
++
++ /* set send date */
++ writel(addr & 0xff, &dev->icrxdtxd);
++ /* start SCLclk */
++ writel(~MSR_MDE, &dev->icmsr);
++
++ while (!(readl(&dev->icmsr) & MSR_MDE))
++ udelay(10);
++ }
+
+ /* set send date */
+ writel(*val, &dev->icrxdtxd);
+@@ -111,11 +123,23 @@ rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size)
+ }
+
+ static u8
+-rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr)
++rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr, int alen)
+ {
+ u8 ret;
+
+- rcar_i2c_raw_rw_common(dev, chip, addr);
++ if (alen == sizeof(u8)) {
++ rcar_i2c_raw_rw_common(dev, chip, addr);
++ } else {
++ rcar_i2c_raw_rw_common(dev, chip, addr >> 8);
++
++ /* set send date */
++ writel(addr & 0xff, &dev->icrxdtxd);
++ /* start SCLclk */
++ writel(~MSR_MDE, &dev->icmsr);
++
++ while (!(readl(&dev->icmsr) & MSR_MDE))
++ udelay(10);
++ }
+
+ /* set slave address, receive */
+ writel((chip << 1) | 1, &dev->icmar);
+@@ -236,7 +260,7 @@ static int rcar_i2c_read(struct i2c_adapter *adap, uint8_t chip,
+ int i;
+
+ for (i = 0; i < len; i++)
+- data[i] = rcar_i2c_raw_read(dev, chip, addr + i);
++ data[i] = rcar_i2c_raw_read(dev, chip, addr + i, alen);
+
+ return 0;
+ }
+@@ -245,7 +269,8 @@ static int rcar_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
+ int alen, u8 *data, int len)
+ {
+ struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
+- return rcar_i2c_raw_write(dev, chip, addr, data, len);
++
++ return rcar_i2c_raw_write(dev, chip, addr, alen, data, len);
+ }
+
+ static int
+--
+1.9.1
+
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch
index 050d98f..1aeed9c 100644
--- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch
@@ -19,9 +19,10 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
arch/arm/include/asm/arch-rcar_gen3/r8a7797.h | 33 +
arch/arm/include/asm/arch-rcar_gen3/rcar-base.h | 5 +
arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h | 2 +
+ drivers/net/Kconfig | 2 +-
drivers/serial/serial_sh.h | 3 +-
- include/configs/rcar-gen3-common.h | 12 +
- 14 files changed, 3360 insertions(+), 1 deletion(-)
+ include/configs/rcar-gen3-common.h | 10 +
+ 15 files changed, 3359 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7797.c
create mode 100644 arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7797.c
create mode 100644 arch/arm/include/asm/arch-rcar_gen3/r8a7797-gpio.h
@@ -3464,7 +3465,7 @@ index 0000000..09e83ba
+
+#endif /* __ASM_ARCH_R8A7797_H */
diff --git a/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h b/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h
-index 18c1a74..fa24fc4 100644
+index 4e07576..f0813a8 100644
--- a/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h
+++ b/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h
@@ -70,6 +70,11 @@
@@ -3492,6 +3493,19 @@ index b412fad..c2ba0fb 100644
#else
#error "SOC Name not defined"
#endif
+diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
+index b1b796d..1a26543 100644
+--- a/drivers/net/Kconfig
++++ b/drivers/net/Kconfig
+@@ -2,7 +2,7 @@ menu "Network Device Support"
+
+ config RAVB_1000BASE
+ bool "Renesas Ethernet AVB support 1000Base"
+- default y if R8A7795 || R8A7796X
++ default y if R8A7795 || R8A7796X || R8A7797
+ depends on RCAR_GEN3
+
+ endmenu
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index fe71e9a..478824e 100644
--- a/drivers/serial/serial_sh.h
@@ -3507,17 +3521,16 @@ index fe71e9a..478824e 100644
# define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
/* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
-index 0a959f7..ec20aba 100644
+index 0a959f7..dc5560d 100644
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
-@@ -124,6 +128,17 @@
+@@ -124,6 +124,16 @@
#define PHYS_SDRAM_1_SIZE ((unsigned long)(0x80000000 - DRAM_RSV_SIZE))
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
+#elif defined(CONFIG_R8A7797)
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE) /* legacy */
-+#define PHYS_SDRAM_1_SIZE ((unsigned long)(0x40000000 - DRAM_RSV_SIZE))
+ #if defined(CONFIG_TARGET_V3MSK)
+ #define PHYS_SDRAM_1_SIZE ((unsigned long)(0x80000000 - DRAM_RSV_SIZE))
+ #else
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0015-board-renesas-Add-V3M-Eagle-board.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0015-board-renesas-Add-V3M-Eagle-board.patch
index 5b300eb..7593dd8 100644
--- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0015-board-renesas-Add-V3M-Eagle-board.patch
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0015-board-renesas-Add-V3M-Eagle-board.patch
@@ -9,12 +9,12 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
arch/arm/cpu/armv8/Kconfig | 4 +
board/renesas/eagle/Kconfig | 15 +++
- board/renesas/eagle/MAINTAINERS | 6 ++
+ board/renesas/eagle/MAINTAINERS | 6 +
board/renesas/eagle/Makefile | 9 ++
- board/renesas/eagle/eagle.c | 224 ++++++++++++++++++++++++++++++++++++++++
+ board/renesas/eagle/eagle.c | 252 ++++++++++++++++++++++++++++++++++++++++
configs/r8a7797_eagle_defconfig | 9 ++
- include/configs/r8a7797_eagle.h | 152 +++++++++++++++++++++++++++
- 7 files changed, 419 insertions(+)
+ include/configs/r8a7797_eagle.h | 152 ++++++++++++++++++++++++
+ 7 files changed, 447 insertions(+)
create mode 100644 board/renesas/eagle/Kconfig
create mode 100644 board/renesas/eagle/MAINTAINERS
create mode 100644 board/renesas/eagle/Makefile
@@ -93,10 +93,10 @@ index 0000000..87d63e1
+obj-y := eagle.o ../rcar-gen3-common/common.o
diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c
new file mode 100644
-index 0000000..4eda15c
+index 0000000..48ea727
--- /dev/null
+++ b/board/renesas/eagle/eagle.c
-@@ -0,0 +1,224 @@
+@@ -0,0 +1,252 @@
+/*
+ * board/renesas/eagle/eagle.c
+ * This file is Eagle board support.
@@ -128,27 +128,31 @@ index 0000000..4eda15c
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SCIF0_MSTP207 (1 << 7)
++#define SD0_MSTP314 (1 << 14)
+#define ETHERAVB_MSTP812 (1 << 12)
-+#define RPC_MSTP917 (1 << 17)
++#define RPC_MSTP917 (1 << 17)
++#define I2C0_MSTP931 (1 << 31)
++
++#define SD0CKCR 0xE6150074
++
++#define PFC_PMMR 0xe6060000
++#define PFC_POC1 0xe6060384
++#define POC_MMC_3V3 0x003ff000
+
-+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
-+ u32 stc;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
-+
-+ /* CPU frequency setting. Set to 0.8GHz */
-+ stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
-+ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+}
+
+int board_early_init_f(void)
+{
++ int freq;
++
+ rcar_prr_init();
+
+ writel(0xa5a5ffff, 0xe6150900);
@@ -156,10 +160,17 @@ index 0000000..4eda15c
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, 0x02000000);
+ /* SCIF0 */
+ mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIF0_MSTP207);
++ /* SDHI2/MMC */
++ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
+ /* EHTERAVB */
+ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
+ /* QSPI */
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, RPC_MSTP917);
++ /* I2C0 */
++ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, I2C0_MSTP931);
++
++ freq = rcar_get_sdhi_config_clk();
++ writel(freq, SD0CKCR);
+
+ return 0;
+}
@@ -178,7 +189,7 @@ index 0000000..4eda15c
+ gpio_request(GPIO_FN_AVB0_AVTP_MATCH, NULL);
+ gpio_request(GPIO_FN_AVB0_LINK, NULL);
+ gpio_request(GPIO_FN_AVB0_PHY_INT, NULL);
-+ gpio_request(GPIO_FN_AVB0_MAGIC, NULL);
++ /* gpio_request(GPIO_FN_AVB0_MAGIC, NULL); */
+ gpio_request(GPIO_FN_AVB0_MDC, NULL);
+ gpio_request(GPIO_FN_AVB0_MDIO, NULL);
+ gpio_request(GPIO_FN_AVB0_TXCREFCLK, NULL);
@@ -208,8 +219,8 @@ index 0000000..4eda15c
+ udelay(1);
+#endif
+
-+ /* QSPI */
+#if !defined(CONFIG_SYS_NO_FLASH)
++ /* QSPI */
+ gpio_request(GPIO_FN_QSPI0_SPCLK, NULL);
+ gpio_request(GPIO_FN_QSPI0_MOSI_IO0, NULL);
+ gpio_request(GPIO_FN_QSPI0_MISO_IO1, NULL);
@@ -226,6 +237,12 @@ index 0000000..4eda15c
+ gpio_request(GPIO_FN_RPC_WP_N, NULL);
+ gpio_request(GPIO_FN_RPC_INT_N, NULL);
+#endif
++
++#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_RCAR)
++ /* I2C0 to access PMIC */
++ gpio_request(GPIO_IFN_SDA0, NULL);
++ gpio_request(GPIO_IFN_SCL0, NULL);
++#endif
+ return 0;
+}
+
@@ -265,22 +282,39 @@ index 0000000..4eda15c
+
+int board_mmc_init(bd_t *bis)
+{
-+ return -ENODEV;
++ int ret = -ENODEV;
++#ifdef CONFIG_SH_SDHI
++ u32 val;
++
++ /* SDHI2/eMMC */
++ gpio_request(GPIO_FN_MMC_D0, NULL);
++ gpio_request(GPIO_FN_MMC_D1, NULL);
++ gpio_request(GPIO_FN_MMC_D2, NULL);
++ gpio_request(GPIO_FN_MMC_D3, NULL);
++ gpio_request(GPIO_FN_MMC_D4, NULL);
++ gpio_request(GPIO_FN_MMC_D5, NULL);
++ gpio_request(GPIO_FN_MMC_D6, NULL);
++ gpio_request(GPIO_FN_MMC_D7, NULL);
++ gpio_request(GPIO_FN_MMC_CLK, NULL);
++ gpio_request(GPIO_FN_MMC_CMD, NULL);
++ gpio_request(GPIO_FN_MMC_CD, NULL);
++ gpio_request(GPIO_FN_MMC_WP, NULL);
++
++ val = readl(PFC_POC1);
++ val &= ~POC_MMC_3V3; /* POC = 1.8V */
++ writel(~val, PFC_PMMR);
++ writel(val, PFC_POC1);
++
++ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 0,
++ SH_SDHI_QUIRK_64BIT_BUF);
++#endif
++ return ret;
+}
+
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
-+#if (CONFIG_NR_DRAM_BANKS >= 2)
-+ gd->ram_size += PHYS_SDRAM_2_SIZE;
-+#endif
-+#if (CONFIG_NR_DRAM_BANKS >= 3)
-+ gd->ram_size += PHYS_SDRAM_3_SIZE;
-+#endif
-+#if (CONFIG_NR_DRAM_BANKS >= 4)
-+ gd->ram_size += PHYS_SDRAM_4_SIZE;
-+#endif
+
+ return 0;
+}
@@ -289,18 +323,6 @@ index 0000000..4eda15c
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-+#if (CONFIG_NR_DRAM_BANKS >= 2)
-+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-+#endif
-+#if (CONFIG_NR_DRAM_BANKS >= 3)
-+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-+#endif
-+#if (CONFIG_NR_DRAM_BANKS >= 4)
-+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-+#endif
+}
+
+const struct rcar_sysinfo sysinfo = {
@@ -309,8 +331,14 @@ index 0000000..4eda15c
+
+void reset_cpu(ulong addr)
+{
-+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
-+ i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
++#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_RCAR)
++ u8 val;
++
++ i2c_set_bus_num(0);
++ i2c_init(400000, 0);
++ i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
++ val |= 0x02;
++ i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+#endif
+}
+
@@ -338,7 +366,7 @@ index 0000000..d68e28f
+CONFIG_SPI_FLASH_SPANSION=y
diff --git a/include/configs/r8a7797_eagle.h b/include/configs/r8a7797_eagle.h
new file mode 100644
-index 0000000..a4ae6bf
+index 0000000..c6ab5b7
--- /dev/null
+++ b/include/configs/r8a7797_eagle.h
@@ -0,0 +1,152 @@
@@ -362,8 +390,8 @@ index 0000000..a4ae6bf
+#include "rcar-gen3-common.h"
+
+/* Cache Definitions */
-+#define CONFIG_SYS_DCACHE_OFF
-+#define CONFIG_SYS_ICACHE_OFF
++//#define CONFIG_SYS_DCACHE_OFF
++//#define CONFIG_SYS_ICACHE_OFF
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
@@ -412,6 +440,7 @@ index 0000000..a4ae6bf
+#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2)
+#define CONFIG_S3D2_CLK_FREQ (266666666u/2)
+#define CONFIG_S3D4_CLK_FREQ (266666666u/4)
++#define CONFIG_S2D2_CLK_FREQ (133333333u)
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
@@ -423,15 +452,14 @@ index 0000000..a4ae6bf
+
+/* i2c */
+#define CONFIG_SYS_I2C
-+#define CONFIG_SYS_I2C_SH
-+#define CONFIG_SYS_I2C_SLAVE 0x60
-+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1
-+#define CONFIG_SYS_I2C_SH_SPEED0 400000
-+#define CONFIG_SH_I2C_DATA_HIGH 4
-+#define CONFIG_SH_I2C_DATA_LOW 5
-+#define CONFIG_SH_I2C_CLOCK 10000000
-+
-+#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30
++#define CONFIG_SYS_I2C_RCAR
++#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
++#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
++#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
++#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
++#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
++#define CONFIG_SYS_I2C_POWERIC_ADDR 0x5A
++#define CONFIG_HP_CLK_FREQ CONFIG_S2D2_CLK_FREQ
+
+/* USB */
+#undef CONFIG_CMD_USB
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch
index 773ca26..34b7129 100644
--- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch
@@ -11,12 +11,12 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
board/renesas/v3msk/Kconfig | 15 +++
board/renesas/v3msk/MAINTAINERS | 6 ++
board/renesas/v3msk/Makefile | 9 ++
- board/renesas/v3msk/cpld.c | 164 +++++++++++++++++++++++++++++++
+ board/renesas/v3msk/cpld.c | 164 ++++++++++++++++++++++++++++++++
board/renesas/v3msk/mdio_bb.h | 156 ++++++++++++++++++++++++++++++
- board/renesas/v3msk/v3msk.c | 209 ++++++++++++++++++++++++++++++++++++++++
+ board/renesas/v3msk/v3msk.c | 204 ++++++++++++++++++++++++++++++++++++++++
configs/v3msk_defconfig | 9 ++
- include/configs/v3msk.h | 145 ++++++++++++++++++++++++++++
- 9 files changed, 717 insertions(+)
+ include/configs/v3msk.h | 133 ++++++++++++++++++++++++++
+ 9 files changed, 700 insertions(+)
create mode 100644 board/renesas/v3msk/Kconfig
create mode 100644 board/renesas/v3msk/MAINTAINERS
create mode 100644 board/renesas/v3msk/Makefile
@@ -78,8 +78,8 @@ index 0000000..c39eb76
+M: Cogent Embedded, Inc. <source@cogentembedded.com>
+S: Maintained
+F: board/renesas/v3msk/
-+F: include/configs/r8a7797_v3msk.h
-+F: configs/r8a7797_v3msk_defconfig
++F: include/configs/v3msk.h
++F: configs/v3msk_defconfig
diff --git a/board/renesas/v3msk/Makefile b/board/renesas/v3msk/Makefile
new file mode 100644
index 0000000..1f2ea42
@@ -100,7 +100,7 @@ new file mode 100644
index 0000000..ffb0637
--- /dev/null
+++ b/board/renesas/v3msk/cpld.c
-@@ -0,0 +1,164 @@
+@@ -0,0 +1,172 @@
+/*
+ * V3MSK board CPLD access support
+ *
@@ -144,6 +144,9 @@ index 0000000..ffb0637
+#define PFC_PUEN2 0xe6060408
+#define PUEN_CANFD1_TX (1 << 29)
+
++#define GP0_MSTP912 (1 << 12)
++#define GP1_MSTP911 (1 << 11)
++
+#define MDIO_DELAY 10 /* microseconds */
+
+#define mdio_bb_active_mdio() gpio_direction_output(MOSI, 0)
@@ -180,6 +183,9 @@ index 0000000..ffb0637
+ /* PULL-UP on MISO line (should be pulled up after POR on V3M) */
+ writel(readl(PFC_PUEN2) | PUEN_CANFD1_TX, PFC_PUEN2);
+#endif
++ /* GPIO0 and GPIO1 */
++ mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, GP0_MSTP912 | GP1_MSTP911);
++
+ gpio_request(MDC, NULL);
+ gpio_request(ENABLEZ, NULL);
+ gpio_request(MOSI, NULL);
@@ -194,7 +200,9 @@ index 0000000..ffb0637
+ * we must shutdown this chip to use bb pins
+ */
+ gpio_request(GPIO_GP_0_12, NULL);
++ gpio_request(GPIO_GP_0_14, NULL);
+ gpio_direction_output(GPIO_GP_0_12, 1);
++ gpio_direction_output(GPIO_GP_0_14, 1);
+}
+
+static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -429,10 +437,10 @@ index 0000000..0311006
+}
diff --git a/board/renesas/v3msk/v3msk.c b/board/renesas/v3msk/v3msk.c
new file mode 100644
-index 0000000..b0de041
+index 0000000..4e4ee1f
--- /dev/null
+++ b/board/renesas/v3msk/v3msk.c
-@@ -0,0 +1,209 @@
+@@ -0,0 +1,203 @@
+/*
+ * board/renesas/v3msk/v3msk.c
+ * This is V3MSK board support.
@@ -470,20 +478,14 @@ index 0000000..b0de041
+
+#define SD0CKCR 0xE6150074
+
-+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
-+ u32 stc;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
-+
-+ /* CPU frequency setting. Set to 0.8GHz */
-+ stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
-+ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+}
+
+int board_early_init_f(void)
@@ -497,7 +499,7 @@ index 0000000..b0de041
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, 0x02000000);
+ /* SCIF0 */
+ mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIF0_MSTP207);
-+ /* SDHI0/MMC */
++ /* SDHI2/MMC */
+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
+ /* EHTERAVB */
+ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
@@ -659,10 +661,10 @@ index 0000000..d32840c
+CONFIG_SPI_FLASH_SPANSION=y
diff --git a/include/configs/v3msk.h b/include/configs/v3msk.h
new file mode 100644
-index 0000000..8998da4
+index 0000000..225d462
--- /dev/null
+++ b/include/configs/v3msk.h
-@@ -0,0 +1,145 @@
+@@ -0,0 +1,133 @@
+/*
+ * include/configs/v3msk.h
+ * This file is V3MSK board configuration.
@@ -742,18 +744,6 @@ index 0000000..8998da4
+#define GICC_BASE (0xF1020000)
+#define CONFIG_GICV2
+
-+/* i2c */
-+#define CONFIG_SYS_I2C
-+#define CONFIG_SYS_I2C_SH
-+#define CONFIG_SYS_I2C_SLAVE 0x60
-+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1
-+#define CONFIG_SYS_I2C_SH_SPEED0 400000
-+#define CONFIG_SH_I2C_DATA_HIGH 4
-+#define CONFIG_SH_I2C_DATA_LOW 5
-+#define CONFIG_SH_I2C_CLOCK 10000000
-+
-+#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30
-+
+/* USB */
+#undef CONFIG_CMD_USB
+
@@ -770,8 +760,8 @@ index 0000000..8998da4
+#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
-+#define CONFIG_ENV_IS_IN_MMC
-+//#define CONFIG_ENV_IS_IN_SPI_FLASH
++//#define CONFIG_ENV_IS_IN_MMC
++#define CONFIG_ENV_IS_IN_SPI_FLASH
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+/* Environment in eMMC, at the end of 2nd "boot sector" */
@@ -804,7 +794,7 @@ index 0000000..8998da4
+ "root=/dev/nfs rw ip=dhcp"
+
+#define CONFIG_BOOTCOMMAND \
-+ "bootp 0x48080000 Image; tftp 0x48000000 Image-r8a7797-v3msk.dtb; " \
++ "bootp 0x48080000 Image; tftp 0x48000000 r8a7797-v3msk.dtb; " \
+ "booti 0x48080000 - 0x48000000"
+
+#endif /* __V3MSK_H */
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0018-arm-renesas-Add-Renesas-R8A7798-SoC-support.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0018-arm-renesas-Add-Renesas-R8A7798-SoC-support.patch
new file mode 100644
index 0000000..905aee9
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0018-arm-renesas-Add-Renesas-R8A7798-SoC-support.patch
@@ -0,0 +1,3945 @@
+From ff0bbc92aeb87872b0c8e7e05a1604bd8c1c3e98 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Mon, 22 Jan 2018 13:57:14 +0300
+Subject: [PATCH] arm: renesas: Add Renesas R8A7798 SoC support
+
+This adds Renesas R8A7798 SoC support
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Mikhail Ulyanov <mikhail.ulyanov@cogentembedded.com>
+---
+ arch/arm/cpu/armv8/Kconfig | 3 +
+ arch/arm/cpu/armv8/rcar_gen3/Makefile | 3 +
+ arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c | 40 +
+ arch/arm/cpu/armv8/rcar_gen3/cpu_info.c | 8 +
+ arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c | 3074 ++++++++++++++++++++
+ arch/arm/cpu/armv8/rcar_gen3/pfc.c | 2 +
+ arch/arm/include/asm/arch-rcar_gen3/gpio.h | 4 +
+ arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h | 522 ++++
+ arch/arm/include/asm/arch-rcar_gen3/r8a7798.h | 34 +
+ arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h | 2 +
+ drivers/mtd/spi/sf_probe.c | 2 +-
+ drivers/net/Kconfig | 2 +-
+ drivers/net/sh_eth.c | 11 +-
+ drivers/net/sh_eth.h | 7 +-
+ drivers/serial/serial_sh.h | 2 +-
+ include/configs/rcar-gen3-common.h | 6 +
+ 16 files changed, 3715 insertions(+), 7 deletions(-)
+ create mode 100644 arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c
+ create mode 100644 arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c
+ create mode 100644 arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h
+ create mode 100644 arch/arm/include/asm/arch-rcar_gen3/r8a7798.h
+
+diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
+index 343b121..58a9259 100644
+--- a/arch/arm/cpu/armv8/Kconfig
++++ b/arch/arm/cpu/armv8/Kconfig
+@@ -44,6 +44,9 @@ config R8A77965
+ config R8A7797
+ bool "Renesas SoC R8A7797"
+
++config R8A7798
++ bool "Renesas SoC R8A7798"
++
+ endchoice
+
+ config SYS_SOC
+diff --git a/arch/arm/cpu/armv8/rcar_gen3/Makefile b/arch/arm/cpu/armv8/rcar_gen3/Makefile
+index a7a8f79..a8b7ddf 100644
+--- a/arch/arm/cpu/armv8/rcar_gen3/Makefile
++++ b/arch/arm/cpu/armv8/rcar_gen3/Makefile
+@@ -18,3 +18,6 @@ obj-$(CONFIG_R8A7796X) += lowlevel_init.o cpu_info-r8a7796.o \
+ obj-$(CONFIG_R8A7797) += lowlevel_init.o cpu_info-r8a7797.o \
+ pfc.o pfc-r8a7797.o prr_depend.o \
+ board.o
++obj-$(CONFIG_R8A7798) += lowlevel_init.o cpu_info-r8a7798.o \
++ pfc.o pfc-r8a7798.o prr_depend.o \
++ board.o
+diff --git a/arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c b/arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c
+new file mode 100644
+index 0000000..df94cd6
+--- /dev/null
++++ b/arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c
+@@ -0,0 +1,40 @@
++/*
++ * arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c
++ * This file defines cpu information funstions.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++#include <common.h>
++#include <asm/io.h>
++
++#define PRR 0xFFF00044
++
++u32 rcar_get_cpu_type(void)
++{
++ u32 product;
++
++ product = readl(PRR);
++
++ return (product & 0x00007F00) >> 8;
++}
++
++u32 rcar_get_cpu_rev_integer(void)
++{
++ u32 product;
++
++ product = readl(PRR);
++
++ return (u32)(((product & 0x000000F0) >> 4) + 1);
++}
++
++u32 rcar_get_cpu_rev_fraction(void)
++{
++ u32 product;
++
++ product = readl(PRR);
++
++ return (u32)(product & 0x0000000F);
++}
+diff --git a/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c b/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c
+index 0046c75..a9366c0 100644
+--- a/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c
++++ b/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c
+@@ -89,6 +89,14 @@ int print_cpuinfo(void)
+ CONFIG_RCAR_TARGET_STRING);
+ }
+ break;
++ case 0x56:
++ printf("CPU: Renesas Electronics R8A7798 rev %d.%d\n",
++ rev_integer, rev_fraction);
++ if (strcmp(CONFIG_RCAR_TARGET_STRING, "r8a7798")) {
++ printf("Warning: this code supports only %s\n",
++ CONFIG_RCAR_TARGET_STRING);
++ }
++ break;
+ }
+ return 0;
+ }
+diff --git a/arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c b/arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c
+new file mode 100644
+index 0000000..40444ba
+--- /dev/null
++++ b/arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c
+@@ -0,0 +1,3074 @@
++/*
++ * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c
++ * This file is r8a7798 processor support - PFC hardware block.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <sh_pfc.h>
++#include <asm/gpio.h>
++
++#define CPU_32_PORT(fn, pfx, sfx) \
++ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
++ PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
++ PORT_1(fn, pfx##31, sfx)
++
++#define CPU_32_PORT1(fn, pfx, sfx) \
++ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
++ PORT_10(fn, pfx##2, sfx)
++
++#define CPU_32_PORT2(fn, pfx, sfx) \
++ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
++ PORT_10(fn, pfx##2, sfx)
++
++#define CPU_32_PORT_30(fn, pfx, sfx) \
++ PORT_10(fn, pfx, sfx), \
++ PORT_10(fn, pfx##1, sfx), \
++ PORT_10(fn, pfx##2, sfx)
++
++#define CPU_32_PORT_28(fn, pfx, sfx) \
++ PORT_10(fn, pfx, sfx), \
++ PORT_10(fn, pfx##1, sfx), \
++ PORT_1(fn, pfx##20, sfx), \
++ PORT_1(fn, pfx##21, sfx), \
++ PORT_1(fn, pfx##22, sfx), \
++ PORT_1(fn, pfx##23, sfx), \
++ PORT_1(fn, pfx##24, sfx), \
++ PORT_1(fn, pfx##25, sfx), \
++ PORT_1(fn, pfx##26, sfx), \
++ PORT_1(fn, pfx##27, sfx)
++
++#define CPU_32_PORT_25(fn, pfx, sfx) \
++ PORT_10(fn, pfx, sfx), \
++ PORT_10(fn, pfx##1, sfx), \
++ PORT_1(fn, pfx##20, sfx), \
++ PORT_1(fn, pfx##21, sfx), \
++ PORT_1(fn, pfx##22, sfx), \
++ PORT_1(fn, pfx##23, sfx), \
++ PORT_1(fn, pfx##24, sfx)
++
++#define CPU_32_PORT_22(fn, pfx, sfx) \
++ PORT_10(fn, pfx, sfx), \
++ PORT_10(fn, pfx##1, sfx), \
++ PORT_1(fn, pfx##20, sfx), \
++ PORT_1(fn, pfx##21, sfx)
++
++#define CPU_32_PORT_17(fn, pfx, sfx) \
++ PORT_10(fn, pfx, sfx), \
++ PORT_1(fn, pfx##10, sfx), \
++ PORT_1(fn, pfx##11, sfx), \
++ PORT_1(fn, pfx##12, sfx), \
++ PORT_1(fn, pfx##13, sfx), \
++ PORT_1(fn, pfx##14, sfx), \
++ PORT_1(fn, pfx##15, sfx), \
++ PORT_1(fn, pfx##16, sfx)
++
++#define CPU_32_PORT_15(fn, pfx, sfx) \
++ PORT_10(fn, pfx, sfx), \
++ PORT_1(fn, pfx##10, sfx), \
++ PORT_1(fn, pfx##11, sfx), \
++ PORT_1(fn, pfx##12, sfx), \
++ PORT_1(fn, pfx##13, sfx), \
++ PORT_1(fn, pfx##14, sfx)
++
++#define CPU_ALL_PORT(fn, pfx, sfx) \
++ CPU_32_PORT_22(fn, pfx##_0_, sfx), \
++ CPU_32_PORT_28(fn, pfx##_1_, sfx), \
++ CPU_32_PORT_30(fn, pfx##_2_, sfx), \
++ CPU_32_PORT_17(fn, pfx##_3_, sfx), \
++ CPU_32_PORT_25(fn, pfx##_4_, sfx), \
++ CPU_32_PORT_15(fn, pfx##_5_, sfx)
++
++#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
++#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
++ GP##pfx##_IN, GP##pfx##_OUT)
++
++#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
++#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
++
++#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
++#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
++#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
++
++
++#define PORT_10_REV(fn, pfx, sfx) \
++ PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
++ PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
++ PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
++ PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
++ PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
++
++#define CPU_32_PORT_REV(fn, pfx, sfx) \
++ PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
++ PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
++ PORT_10_REV(fn, pfx, sfx)
++
++#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
++#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
++
++#define PINMUX_IPSR_IDATA(fn) PINMUX_DATA(fn##_IMARK, GFN_##fn, IFN_##fn)
++#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, GFN_##ipsr, FN_##fn)
++#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
++ FN_##ipsr, FN_##fn)
++
++enum {
++ PINMUX_RESERVED = 0,
++
++ PINMUX_DATA_BEGIN,
++ GP_ALL(DATA),
++ PINMUX_DATA_END,
++
++ PINMUX_INPUT_BEGIN,
++ GP_ALL(IN),
++ PINMUX_INPUT_END,
++
++ PINMUX_OUTPUT_BEGIN,
++ GP_ALL(OUT),
++ PINMUX_OUTPUT_END,
++
++ PINMUX_FUNCTION_BEGIN,
++ GP_ALL(FN),
++
++ /* GPSR0 */
++ GFN_DU_EXODDF_DU_ODDF_DISP_CDE,
++ GFN_DU_EXVSYNC_DU_VSYNC,
++ GFN_DU_EXHSYNC_DU_HSYNC,
++ GFN_DU_DOTCLKOUT,
++ GFN_DU_DB7,
++ GFN_DU_DB6,
++ GFN_DU_DB5,
++ GFN_DU_DB4,
++ GFN_DU_DB3,
++ GFN_DU_DB2,
++ GFN_DU_DG7,
++ GFN_DU_DG6,
++ GFN_DU_DG5,
++ GFN_DU_DG4,
++ GFN_DU_DG3,
++ GFN_DU_DG2,
++ GFN_DU_DR7,
++ GFN_DU_DR6,
++ GFN_DU_DR5,
++ GFN_DU_DR4,
++ GFN_DU_DR3,
++ GFN_DU_DR2,
++
++ /* GPSR1 */
++ GFN_DIGRF_CLKOUT,
++ GFN_DIGRF_CLKIN,
++ GFN_CANFD_CLK_A,
++ GFN_CANFD1_RX,
++ GFN_CANFD1_TX,
++ GFN_CANFD0_RX_A,
++ GFN_CANFD0_TX_A,
++ GFN_AVB0_AVTP_CAPTURE,
++ GFN_AVB0_AVTP_MATCH,
++ FN_AVB0_LINK,
++ FN_AVB0_PHY_INT,
++ FN_AVB0_MAGIC,
++ FN_AVB0_MDC,
++ FN_AVB0_MDIO,
++ FN_AVB0_TXCREFCLK,
++ FN_AVB0_TD3,
++ FN_AVB0_TD2,
++ FN_AVB0_TD1,
++ FN_AVB0_TD0,
++ FN_AVB0_TXC,
++ FN_AVB0_TX_CTL,
++ FN_AVB0_RD3,
++ FN_AVB0_RD2,
++ FN_AVB0_RD1,
++ FN_AVB0_RD0,
++ FN_AVB0_RXC,
++ FN_AVB0_RX_CTL,
++ GFN_IRQ0,
++
++ /* GPSR2 */
++ GFN_FSO_TOE_N,
++ GFN_FSO_CFE_1_N,
++ GFN_FSO_CFE_0_N,
++ GFN_SDA3,
++ GFN_SCL3,
++ GFN_MSIOF0_SS2,
++ GFN_MSIOF0_SS1,
++ GFN_MSIOF0_SYNC,
++ GFN_MSIOF0_SCK,
++ GFN_MSIOF0_TXD,
++ GFN_MSIOF0_RXD,
++ GFN_IRQ5,
++ GFN_IRQ4,
++ GFN_VI0_FIELD,
++ GFN_VI0_DATA11,
++ GFN_VI0_DATA10,
++ GFN_VI0_DATA9,
++ GFN_VI0_DATA8,
++ GFN_VI0_DATA7,
++ GFN_VI0_DATA6,
++ GFN_VI0_DATA5,
++ GFN_VI0_DATA4,
++ GFN_VI0_DATA3,
++ GFN_VI0_DATA2,
++ GFN_VI0_DATA1,
++ GFN_VI0_DATA0,
++ GFN_VI0_VSYNC_N,
++ GFN_VI0_HSYNC_N,
++ GFN_VI0_CLKENB,
++ GFN_VI0_CLK,
++
++ /* GPSR3 */
++ GFN_VI1_FIELD,
++ GFN_VI1_DATA11,
++ GFN_VI1_DATA10,
++ GFN_VI1_DATA9,
++ GFN_VI1_DATA8,
++ GFN_VI1_DATA7,
++ GFN_VI1_DATA6,
++ GFN_VI1_DATA5,
++ GFN_VI1_DATA4,
++ GFN_VI1_DATA3,
++ GFN_VI1_DATA2,
++ GFN_VI1_DATA1,
++ GFN_VI1_DATA0,
++ GFN_VI1_VSYNC_N,
++ GFN_VI1_HSYNC_N,
++ GFN_VI1_CLKENB,
++ GFN_VI1_CLK,
++
++ /* GPSR4 */
++ FN_GETHER_LINK_A,
++ FN_GETHER_PHY_INT_A,
++ FN_GETHER_MAGIC,
++ FN_GETHER_MDC_A,
++ FN_GETHER_MDIO_A,
++ FN_GETHER_TXCREFCLK_MEGA,
++ FN_GETHER_TXCREFCLK,
++ FN_GETHER_TD3,
++ FN_GETHER_TD2,
++ FN_GETHER_TD1,
++ FN_GETHER_TD0,
++ FN_GETHER_TXC,
++ FN_GETHER_TX_CTL,
++ FN_GETHER_RD3,
++ FN_GETHER_RD2,
++ FN_GETHER_RD1,
++ FN_GETHER_RD0,
++ FN_GETHER_RXC,
++ FN_GETHER_RX_CTL,
++ GFN_SDA2,
++ GFN_SCL2,
++ GFN_SDA1,
++ GFN_SCL1,
++ GFN_SDA0,
++ GFN_SCL0,
++
++ /* GPSR5 */
++ FN_RPC_INT_N,
++ FN_RPC_WP_N,
++ FN_RPC_RESET_N,
++ FN_QSPI1_SSL,
++ FN_QSPI1_IO3,
++ FN_QSPI1_IO2,
++ FN_QSPI1_MISO_IO1,
++ FN_QSPI1_MOSI_IO0,
++ FN_QSPI1_SPCLK,
++ FN_QSPI0_SSL,
++ FN_QSPI0_IO3,
++ FN_QSPI0_IO2,
++ FN_QSPI0_MISO_IO1,
++ FN_QSPI0_MOSI_IO0,
++ FN_QSPI0_SPCLK,
++
++ /* IPSR0 */
++ IFN_DU_DR2,
++ FN_SCK4,
++ FN_GETHER_RMII_CRS_DV,
++ FN_A0,
++ IFN_DU_DR3,
++ FN_RX4,
++ FN_GETHER_RMII_RX_ER,
++ FN_A1,
++ IFN_DU_DR4,
++ FN_TX4,
++ FN_GETHER_RMII_RXD0,
++ FN_A2,
++ IFN_DU_DR5,
++ FN_CTS4_N,
++ FN_GETHER_RMII_RXD1,
++ FN_A3,
++ IFN_DU_DR6,
++ FN_RTS4_N_TANS,
++ FN_GETHER_RMII_TXD_EN,
++ FN_A4,
++ IFN_DU_DR7,
++ FN_GETHER_RMII_TXD0,
++ FN_A5,
++ IFN_DU_DG2,
++ FN_GETHER_RMII_TXD1,
++ FN_A6,
++ IFN_DU_DG3,
++ FN_CPG_CPCKOUT,
++ FN_GETHER_RMII_REFCLK,
++ FN_A7,
++ FN_PWMFSW0,
++
++ /* IPSR1 */
++ IFN_DU_DG4,
++ FN_SCL5,
++ FN_A8,
++ IFN_DU_DG5,
++ FN_SDA5,
++ FN_GETHER_MDC_B,
++ FN_A9,
++ IFN_DU_DG6,
++ FN_SCIF_CLK_A,
++ FN_GETHER_MDIO_B,
++ FN_A10,
++ IFN_DU_DG7,
++ FN_HRX0_A,
++ FN_A11,
++ IFN_DU_DB2,
++ FN_HSCK0_A,
++ FN_A12,
++ FN_IRQ1,
++ IFN_DU_DB3,
++ FN_HRTS0_N_A,
++ FN_A13,
++ FN_IRQ2,
++ IFN_DU_DB4,
++ FN_HCTS0_N_A,
++ FN_A14,
++ FN_IRQ3,
++ IFN_DU_DB5,
++ FN_HTX0_A,
++ FN_PWM0_A,
++ FN_A15,
++
++ /* IPSR2 */
++ IFN_DU_DB6,
++ FN_MSIOF3_RXD,
++ FN_A16,
++ IFN_DU_DB7,
++ FN_MSIOF3_TXD,
++ FN_A17,
++ IFN_DU_DOTCLKOUT,
++ FN_MSIOF3_SS1,
++ FN_GETHER_LINK_B,
++ FN_A18,
++ IFN_DU_EXHSYNC_DU_HSYNC,
++ FN_MSIOF3_SS2,
++ FN_GETHER_PHY_INT_B,
++ FN_A19,
++ FN_FXR_TXENA_N,
++ IFN_DU_EXVSYNC_DU_VSYNC,
++ FN_MSIOF3_SCK,
++ FN_FXR_TXENB_N,
++ IFN_DU_EXODDF_DU_ODDF_DISP_CDE,
++ FN_MSIOF3_SYNC,
++ IFN_IRQ0,
++ FN_CC5_OSCOUT,
++ IFN_VI0_CLK,
++ FN_MSIOF2_SCK,
++ FN_SCK3,
++ FN_HSCK3,
++
++ /* IPSR3 */
++ IFN_VI0_CLKENB,
++ FN_MSIOF2_RXD,
++ FN_RX3,
++ FN_RD_WR_N,
++ FN_HCTS3_N,
++ IFN_VI0_HSYNC_N,
++ FN_MSIOF2_TXD,
++ FN_TX3,
++ FN_HRTS3_N,
++ IFN_VI0_VSYNC_N,
++ FN_MSIOF2_SYNC,
++ FN_CTS3_N,
++ FN_HTX3,
++ IFN_VI0_DATA0,
++ FN_MSIOF2_SS1,
++ FN_RTS3_N_TANS,
++ FN_HRX3,
++ IFN_VI0_DATA1,
++ FN_MSIOF2_SS2,
++ FN_SCK1,
++ FN_SPEEDIN_A,
++ IFN_VI0_DATA2,
++ FN_AVB0_AVTP_PPS,
++ IFN_VI0_DATA3,
++ FN_HSCK1,
++ IFN_VI0_DATA4,
++ FN_HRTS1_N,
++ FN_RX1_A,
++
++ /* IPSR4 */
++ IFN_VI0_DATA5,
++ FN_HCTS1_N,
++ FN_TX1_A,
++ IFN_VI0_DATA6,
++ FN_HTX1,
++ FN_CTS1_N,
++ IFN_VI0_DATA7,
++ FN_HRX1,
++ FN_RTS1_N_TANS,
++ IFN_VI0_DATA8,
++ FN_HSCK2,
++ IFN_VI0_DATA9,
++ FN_HCTS2_N,
++ FN_PWM1_A,
++ FN_FSO_CFE_0_N_B,
++ IFN_VI0_DATA10,
++ FN_HRTS2_N,
++ FN_PWM2_A,
++ IFN_VI0_DATA11,
++ FN_HTX2,
++ FN_PWM3_A,
++ IFN_VI0_FIELD,
++ FN_HRX2,
++ FN_PWM4_A,
++ FN_CS1_N,
++ FN_FSCLKST2_N_A,
++
++ /* IPSR5 */
++ IFN_VI1_CLK,
++ FN_MSIOF1_RXD,
++ FN_CS0_N,
++ IFN_VI1_CLKENB,
++ FN_MSIOF1_TXD,
++ FN_D0,
++ IFN_VI1_HSYNC_N,
++ FN_MSIOF1_SCK,
++ FN_D1,
++ IFN_VI1_VSYNC_N,
++ FN_MSIOF1_SYNC,
++ FN_D2,
++ IFN_VI1_DATA0,
++ FN_MSIOF1_SS1,
++ FN_D3,
++ FN_MMC_WP,
++ IFN_VI1_DATA1,
++ FN_MSIOF1_SS2,
++ FN_D4,
++ FN_MMC_CD,
++ IFN_VI1_DATA2,
++ FN_CANFD0_TX_B,
++ FN_D5,
++ FN_MMC_DS,
++ IFN_VI1_DATA3,
++ FN_CANFD0_RX_B,
++ FN_D6,
++ FN_MMC_CMD,
++
++ /* IPSR6 */
++ IFN_VI1_DATA4,
++ FN_CANFD_CLK_B,
++ FN_D7,
++ FN_MMC_D0,
++ IFN_VI1_DATA5,
++ FN_D8,
++ FN_MMC_D1,
++ IFN_VI1_DATA6,
++ FN_D9,
++ FN_MMC_D2,
++ IFN_VI1_DATA7,
++ FN_D10,
++ FN_MMC_D3,
++ IFN_VI1_DATA8,
++ FN_D11,
++ FN_MMC_CLK,
++ IFN_VI1_DATA9,
++ FN_TCLK1_A,
++ FN_D12,
++ FN_MMC_D4,
++ IFN_VI1_DATA10,
++ FN_TCLK2_A,
++ FN_D13,
++ FN_MMC_D5,
++ IFN_VI1_DATA11,
++ FN_SCL4,
++ FN_D14,
++ FN_MMC_D6,
++
++ /* IPSR7 */
++ IFN_VI1_FIELD,
++ FN_SDA4,
++ FN_D15,
++ FN_MMC_D7,
++ IFN_SCL0,
++ FN_CLKOUT,
++ IFN_SDA0,
++ FN_BS_N,
++ FN_SCK0,
++ FN_HSCK0_B,
++ IFN_SCL1,
++ FN_TPU0TO2,
++ FN_RD_N,
++ FN_CTS0_N,
++ FN_HCTS0_N_B,
++ IFN_SDA1,
++ FN_TPU0TO3,
++ FN_WE0_N,
++ FN_RTS0_N_TANS,
++ FN_HRTS0_N_B,
++ IFN_SCL2,
++ FN_WE1_N,
++ FN_RX0,
++ FN_HRX0_B,
++ IFN_SDA2,
++ FN_EX_WAIT0,
++ FN_TX0,
++ FN_HTX0_B,
++ IFN_AVB0_AVTP_MATCH,
++ FN_TPU0TO0,
++
++ /* IPSR8 */
++ IFN_AVB0_AVTP_CAPTURE,
++ FN_TPU0TO1,
++ IFN_CANFD0_TX_A,
++ FN_FXR_TXDA,
++ FN_PWM0_B,
++ FN_DU_DISP,
++ IFN_CANFD0_RX_A,
++ FN_RXDA_EXTFXR,
++ FN_PWM1_B,
++ FN_DU_CDE,
++ IFN_CANFD1_TX,
++ FN_FXR_TXDB,
++ FN_PWM2_B,
++ FN_TCLK1_B,
++ FN_TX1_B,
++ IFN_CANFD1_RX,
++ FN_RXDB_EXTFXR,
++ FN_PWM3_B,
++ FN_TCLK2_B,
++ FN_RX1_B,
++ IFN_CANFD_CLK_A,
++ FN_CLK_EXTFXR,
++ FN_PWM4_B,
++ FN_SPEEDIN_B,
++ FN_SCIF_CLK_B,
++ IFN_DIGRF_CLKIN,
++ FN_DIGRF_CLKEN_IN,
++ IFN_DIGRF_CLKOUT,
++ FN_DIGRF_CLKEN_OUT,
++
++ /* IPSR9 */
++ IFN_IRQ4,
++ FN_VI0_DATA12,
++ IFN_IRQ5,
++ FN_VI0_DATA13,
++ IFN_MSIOF0_RXD,
++ FN_DU_DR0,
++ FN_VI0_DATA14,
++ IFN_MSIOF0_TXD,
++ FN_DU_DR1,
++ FN_VI0_DATA15,
++ IFN_MSIOF0_SCK,
++ FN_DU_DG0,
++ FN_VI0_DATA16,
++ IFN_MSIOF0_SYNC,
++ FN_DU_DG1,
++ FN_VI0_DATA17,
++ IFN_MSIOF0_SS1,
++ FN_DU_DB0,
++ FN_TCLK3,
++ FN_VI0_DATA18,
++ IFN_MSIOF0_SS2,
++ FN_DU_DB1,
++ FN_TCLK4,
++ FN_VI0_DATA19,
++
++ /* IPSR10 */
++ IFN_SCL3,
++ FN_VI0_DATA20,
++ IFN_SDA3,
++ FN_VI0_DATA21,
++ IFN_FSO_CFE_0_N,
++ FN_VI0_DATA22,
++ IFN_FSO_CFE_1_N,
++ FN_VI0_DATA23,
++ IFN_FSO_TOE_N,
++
++ /* MOD_SEL0 */
++ FN_SEL_CANFD0_0, FN_SEL_CANFD0_1,
++ FN_SEL_GETHER_0, FN_SEL_GETHER_1,
++ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
++ FN_SEL_PWM0_0, FN_SEL_PWM0_1,
++ FN_SEL_PWM1_0, FN_SEL_PWM1_1,
++ FN_SEL_PWM2_0, FN_SEL_PWM2_1,
++ FN_SEL_PWM3_0, FN_SEL_PWM3_1,
++ FN_SEL_PWM4_0, FN_SEL_PWM4_1,
++ FN_SEL_RSP_0, FN_SEL_RSP_1,
++ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1,
++ FN_SEL_TMU_0, FN_SEL_TMU_1,
++
++ PINMUX_FUNCTION_END,
++
++ PINMUX_MARK_BEGIN,
++
++ /* GPSR0 */
++ DU_EXODDF_DU_ODDF_DISP_CDE_GMARK,
++ DU_EXVSYNC_DU_VSYNC_GMARK,
++ DU_EXHSYNC_DU_HSYNC_GMARK,
++ DU_DOTCLKOUT_GMARK,
++ DU_DB7_GMARK,
++ DU_DB6_GMARK,
++ DU_DB5_GMARK,
++ DU_DB4_GMARK,
++ DU_DB3_GMARK,
++ DU_DB2_GMARK,
++ DU_DG7_GMARK,
++ DU_DG6_GMARK,
++ DU_DG5_GMARK,
++ DU_DG4_GMARK,
++ DU_DG3_GMARK,
++ DU_DG2_GMARK,
++ DU_DR7_GMARK,
++ DU_DR6_GMARK,
++ DU_DR5_GMARK,
++ DU_DR4_GMARK,
++ DU_DR3_GMARK,
++ DU_DR2_GMARK,
++
++ /* GPSR1 */
++ DIGRF_CLKOUT_GMARK,
++ DIGRF_CLKIN_GMARK,
++ CANFD_CLK_A_GMARK,
++ CANFD1_RX_GMARK,
++ CANFD1_TX_GMARK,
++ CANFD0_RX_A_GMARK,
++ CANFD0_TX_A_GMARK,
++ AVB0_AVTP_CAPTURE_GMARK,
++ AVB0_AVTP_MATCH_GMARK,
++ AVB0_LINK_MARK,
++ AVB0_PHY_INT_MARK,
++ AVB0_MAGIC_MARK,
++ AVB0_MDC_MARK,
++ AVB0_MDIO_MARK,
++ AVB0_TXCREFCLK_MARK,
++ AVB0_TD3_MARK,
++ AVB0_TD2_MARK,
++ AVB0_TD1_MARK,
++ AVB0_TD0_MARK,
++ AVB0_TXC_MARK,
++ AVB0_TX_CTL_MARK,
++ AVB0_RD3_MARK,
++ AVB0_RD2_MARK,
++ AVB0_RD1_MARK,
++ AVB0_RD0_MARK,
++ AVB0_RXC_MARK,
++ AVB0_RX_CTL_MARK,
++ IRQ0_GMARK,
++
++ /* GPSR2 */
++ FSO_TOE_N_GMARK,
++ FSO_CFE_1_N_GMARK,
++ FSO_CFE_0_N_GMARK,
++ SDA3_GMARK,
++ SCL3_GMARK,
++ MSIOF0_SS2_GMARK,
++ MSIOF0_SS1_GMARK,
++ MSIOF0_SYNC_GMARK,
++ MSIOF0_SCK_GMARK,
++ MSIOF0_TXD_GMARK,
++ MSIOF0_RXD_GMARK,
++ IRQ5_GMARK,
++ IRQ4_GMARK,
++ VI0_FIELD_GMARK,
++ VI0_DATA11_GMARK,
++ VI0_DATA10_GMARK,
++ VI0_DATA9_GMARK,
++ VI0_DATA8_GMARK,
++ VI0_DATA7_GMARK,
++ VI0_DATA6_GMARK,
++ VI0_DATA5_GMARK,
++ VI0_DATA4_GMARK,
++ VI0_DATA3_GMARK,
++ VI0_DATA2_GMARK,
++ VI0_DATA1_GMARK,
++ VI0_DATA0_GMARK,
++ VI0_VSYNC_N_GMARK,
++ VI0_HSYNC_N_GMARK,
++ VI0_CLKENB_GMARK,
++ VI0_CLK_GMARK,
++
++ /* GPSR3 */
++ VI1_FIELD_GMARK,
++ VI1_DATA11_GMARK,
++ VI1_DATA10_GMARK,
++ VI1_DATA9_GMARK,
++ VI1_DATA8_GMARK,
++ VI1_DATA7_GMARK,
++ VI1_DATA6_GMARK,
++ VI1_DATA5_GMARK,
++ VI1_DATA4_GMARK,
++ VI1_DATA3_GMARK,
++ VI1_DATA2_GMARK,
++ VI1_DATA1_GMARK,
++ VI1_DATA0_GMARK,
++ VI1_VSYNC_N_GMARK,
++ VI1_HSYNC_N_GMARK,
++ VI1_CLKENB_GMARK,
++ VI1_CLK_GMARK,
++
++ /* GPSR4 */
++ GETHER_LINK_A_MARK,
++ GETHER_PHY_INT_A_MARK,
++ GETHER_MAGIC_MARK,
++ GETHER_MDC_A_MARK,
++ GETHER_MDIO_A_MARK,
++ GETHER_TXCREFCLK_MEGA_MARK,
++ GETHER_TXCREFCLK_MARK,
++ GETHER_TD3_MARK,
++ GETHER_TD2_MARK,
++ GETHER_TD1_MARK,
++ GETHER_TD0_MARK,
++ GETHER_TXC_MARK,
++ GETHER_TX_CTL_MARK,
++ GETHER_RD3_MARK,
++ GETHER_RD2_MARK,
++ GETHER_RD1_MARK,
++ GETHER_RD0_MARK,
++ GETHER_RXC_MARK,
++ GETHER_RX_CTL_MARK,
++ SDA2_GMARK,
++ SCL2_GMARK,
++ SDA1_GMARK,
++ SCL1_GMARK,
++ SDA0_GMARK,
++ SCL0_GMARK,
++
++ /* GPSR5 */
++ RPC_INT_N_MARK,
++ RPC_WP_N_MARK,
++ RPC_RESET_N_MARK,
++ QSPI1_SSL_MARK,
++ QSPI1_IO3_MARK,
++ QSPI1_IO2_MARK,
++ QSPI1_MISO_IO1_MARK,
++ QSPI1_MOSI_IO0_MARK,
++ QSPI1_SPCLK_MARK,
++ QSPI0_SSL_MARK,
++ QSPI0_IO3_MARK,
++ QSPI0_IO2_MARK,
++ QSPI0_MISO_IO1_MARK,
++ QSPI0_MOSI_IO0_MARK,
++ QSPI0_SPCLK_MARK,
++
++ /* IPSR0 */
++ DU_DR2_IMARK,
++ SCK4_MARK,
++ GETHER_RMII_CRS_DV_MARK,
++ A0_MARK,
++ DU_DR3_IMARK,
++ RX4_MARK,
++ GETHER_RMII_RX_ER_MARK,
++ A1_MARK,
++ DU_DR4_IMARK,
++ TX4_MARK,
++ GETHER_RMII_RXD0_MARK,
++ A2_MARK,
++ DU_DR5_IMARK,
++ CTS4_N_MARK,
++ GETHER_RMII_RXD1_MARK,
++ A3_MARK,
++ DU_DR6_IMARK,
++ RTS4_N_TANS_MARK,
++ GETHER_RMII_TXD_EN_MARK,
++ A4_MARK,
++ DU_DR7_IMARK,
++ GETHER_RMII_TXD0_MARK,
++ A5_MARK,
++ DU_DG2_IMARK,
++ GETHER_RMII_TXD1_MARK,
++ A6_MARK,
++ DU_DG3_IMARK,
++ CPG_CPCKOUT_MARK,
++ GETHER_RMII_REFCLK_MARK,
++ A7_MARK,
++ PWMFSW0_MARK,
++
++ /* IPSR1 */
++ DU_DG4_IMARK,
++ SCL5_MARK,
++ A8_MARK,
++ DU_DG5_IMARK,
++ SDA5_MARK,
++ GETHER_MDC_B_MARK,
++ A9_MARK,
++ DU_DG6_IMARK,
++ SCIF_CLK_A_MARK,
++ GETHER_MDIO_B_MARK,
++ A10_MARK,
++ DU_DG7_IMARK,
++ HRX0_A_MARK,
++ A11_MARK,
++ DU_DB2_IMARK,
++ HSCK0_A_MARK,
++ A12_MARK,
++ IRQ1_MARK,
++ DU_DB3_IMARK,
++ HRTS0_N_A_MARK,
++ A13_MARK,
++ IRQ2_MARK,
++ DU_DB4_IMARK,
++ HCTS0_N_A_MARK,
++ A14_MARK,
++ IRQ3_MARK,
++ DU_DB5_IMARK,
++ HTX0_A_MARK,
++ PWM0_A_MARK,
++ A15_MARK,
++
++ /* IPSR2 */
++ DU_DB6_IMARK,
++ MSIOF3_RXD_MARK,
++ A16_MARK,
++ DU_DB7_IMARK,
++ MSIOF3_TXD_MARK,
++ A17_MARK,
++ DU_DOTCLKOUT_IMARK,
++ MSIOF3_SS1_MARK,
++ GETHER_LINK_B_MARK,
++ A18_MARK,
++ DU_EXHSYNC_DU_HSYNC_IMARK,
++ MSIOF3_SS2_MARK,
++ GETHER_PHY_INT_B_MARK,
++ A19_MARK,
++ FXR_TXENA_N_MARK,
++ DU_EXVSYNC_DU_VSYNC_IMARK,
++ MSIOF3_SCK_MARK,
++ FXR_TXENB_N_MARK,
++ DU_EXODDF_DU_ODDF_DISP_CDE_IMARK,
++ MSIOF3_SYNC_MARK,
++ IRQ0_IMARK,
++ CC5_OSCOUT_MARK,
++ VI0_CLK_IMARK,
++ MSIOF2_SCK_MARK,
++ SCK3_MARK,
++ HSCK3_MARK,
++
++ /* IPSR3 */
++ VI0_CLKENB_IMARK,
++ MSIOF2_RXD_MARK,
++ RX3_MARK,
++ RD_WR_N_MARK,
++ HCTS3_N_MARK,
++ VI0_HSYNC_N_IMARK,
++ MSIOF2_TXD_MARK,
++ TX3_MARK,
++ HRTS3_N_MARK,
++ VI0_VSYNC_N_IMARK,
++ MSIOF2_SYNC_MARK,
++ CTS3_N_MARK,
++ HTX3_MARK,
++ VI0_DATA0_IMARK,
++ MSIOF2_SS1_MARK,
++ RTS3_N_TANS_MARK,
++ HRX3_MARK,
++ VI0_DATA1_IMARK,
++ MSIOF2_SS2_MARK,
++ SCK1_MARK,
++ SPEEDIN_A_MARK,
++ VI0_DATA2_IMARK,
++ AVB0_AVTP_PPS_MARK,
++ VI0_DATA3_IMARK,
++ HSCK1_MARK,
++ VI0_DATA4_IMARK,
++ HRTS1_N_MARK,
++ RX1_A_MARK,
++
++ /* IPSR4 */
++ VI0_DATA5_IMARK,
++ HCTS1_N_MARK,
++ TX1_A_MARK,
++ VI0_DATA6_IMARK,
++ HTX1_MARK,
++ CTS1_N_MARK,
++ VI0_DATA7_IMARK,
++ HRX1_MARK,
++ RTS1_N_TANS_MARK,
++ VI0_DATA8_IMARK,
++ HSCK2_MARK,
++ VI0_DATA9_IMARK,
++ HCTS2_N_MARK,
++ PWM1_A_MARK,
++ FSO_CFE_0_N_B_MARK,
++ VI0_DATA10_IMARK,
++ HRTS2_N_MARK,
++ PWM2_A_MARK,
++ VI0_DATA11_IMARK,
++ HTX2_MARK,
++ PWM3_A_MARK,
++ VI0_FIELD_IMARK,
++ HRX2_MARK,
++ PWM4_A_MARK,
++ CS1_N_MARK,
++ FSCLKST2_N_A_MARK,
++
++ /* IPSR5 */
++ VI1_CLK_IMARK,
++ MSIOF1_RXD_MARK,
++ CS0_N_MARK,
++ VI1_CLKENB_IMARK,
++ MSIOF1_TXD_MARK,
++ D0_MARK,
++ VI1_HSYNC_N_IMARK,
++ MSIOF1_SCK_MARK,
++ D1_MARK,
++ VI1_VSYNC_N_IMARK,
++ MSIOF1_SYNC_MARK,
++ D2_MARK,
++ VI1_DATA0_IMARK,
++ MSIOF1_SS1_MARK,
++ D3_MARK,
++ MMC_WP_MARK,
++ VI1_DATA1_IMARK,
++ MSIOF1_SS2_MARK,
++ D4_MARK,
++ MMC_CD_MARK,
++ VI1_DATA2_IMARK,
++ CANFD0_TX_B_MARK,
++ D5_MARK,
++ MMC_DS_MARK,
++ VI1_DATA3_IMARK,
++ CANFD0_RX_B_MARK,
++ D6_MARK,
++ MMC_CMD_MARK,
++
++ /* IPSR6 */
++ VI1_DATA4_IMARK,
++ CANFD_CLK_B_MARK,
++ D7_MARK,
++ MMC_D0_MARK,
++ VI1_DATA5_IMARK,
++ D8_MARK,
++ MMC_D1_MARK,
++ VI1_DATA6_IMARK,
++ D9_MARK,
++ MMC_D2_MARK,
++ VI1_DATA7_IMARK,
++ D10_MARK,
++ MMC_D3_MARK,
++ VI1_DATA8_IMARK,
++ D11_MARK,
++ MMC_CLK_MARK,
++ VI1_DATA9_IMARK,
++ TCLK1_A_MARK,
++ D12_MARK,
++ MMC_D4_MARK,
++ VI1_DATA10_IMARK,
++ TCLK2_A_MARK,
++ D13_MARK,
++ MMC_D5_MARK,
++ VI1_DATA11_IMARK,
++ SCL4_MARK,
++ D14_MARK,
++ MMC_D6_MARK,
++
++ /* IPSR7 */
++ VI1_FIELD_IMARK,
++ SDA4_MARK,
++ D15_MARK,
++ MMC_D7_MARK,
++ SCL0_IMARK,
++ CLKOUT_MARK,
++ SDA0_IMARK,
++ BS_N_MARK,
++ SCK0_MARK,
++ HSCK0_B_MARK,
++ SCL1_IMARK,
++ TPU0TO2_MARK,
++ RD_N_MARK,
++ CTS0_N_MARK,
++ HCTS0_N_B_MARK,
++ SDA1_IMARK,
++ TPU0TO3_MARK,
++ WE0_N_MARK,
++ RTS0_N_TANS_MARK,
++ HRTS0_N_B_MARK,
++ SCL2_IMARK,
++ WE1_N_MARK,
++ RX0_MARK,
++ HRX0_B_MARK,
++ SDA2_IMARK,
++ EX_WAIT0_MARK,
++ TX0_MARK,
++ HTX0_B_MARK,
++ AVB0_AVTP_MATCH_IMARK,
++ TPU0TO0_MARK,
++
++ /* IPSR8 */
++ AVB0_AVTP_CAPTURE_IMARK,
++ TPU0TO1_MARK,
++ CANFD0_TX_A_IMARK,
++ FXR_TXDA_MARK,
++ PWM0_B_MARK,
++ DU_DISP_MARK,
++ CANFD0_RX_A_IMARK,
++ RXDA_EXTFXR_MARK,
++ PWM1_B_MARK,
++ DU_CDE_MARK,
++ CANFD1_TX_IMARK,
++ FXR_TXDB_MARK,
++ PWM2_B_MARK,
++ TCLK1_B_MARK,
++ TX1_B_MARK,
++ CANFD1_RX_IMARK,
++ RXDB_EXTFXR_MARK,
++ PWM3_B_MARK,
++ TCLK2_B_MARK,
++ RX1_B_MARK,
++ CANFD_CLK_A_IMARK,
++ CLK_EXTFXR_MARK,
++ PWM4_B_MARK,
++ SPEEDIN_B_MARK,
++ SCIF_CLK_B_MARK,
++ DIGRF_CLKIN_IMARK,
++ DIGRF_CLKEN_IN_MARK,
++ DIGRF_CLKOUT_IMARK,
++ DIGRF_CLKEN_OUT_MARK,
++
++ /* IPSR9 */
++ IRQ4_IMARK,
++ VI0_DATA12_MARK,
++ IRQ5_IMARK,
++ VI0_DATA13_MARK,
++ MSIOF0_RXD_IMARK,
++ DU_DR0_MARK,
++ VI0_DATA14_MARK,
++ MSIOF0_TXD_IMARK,
++ DU_DR1_MARK,
++ VI0_DATA15_MARK,
++ MSIOF0_SCK_IMARK,
++ DU_DG0_MARK,
++ VI0_DATA16_MARK,
++ MSIOF0_SYNC_IMARK,
++ DU_DG1_MARK,
++ VI0_DATA17_MARK,
++ MSIOF0_SS1_IMARK,
++ DU_DB0_MARK,
++ TCLK3_MARK,
++ VI0_DATA18_MARK,
++ MSIOF0_SS2_IMARK,
++ DU_DB1_MARK,
++ TCLK4_MARK,
++ VI0_DATA19_MARK,
++
++ /* IPSR10 */
++ SCL3_IMARK,
++ VI0_DATA20_MARK,
++ SDA3_IMARK,
++ VI0_DATA21_MARK,
++ FSO_CFE_0_N_IMARK,
++ VI0_DATA22_MARK,
++ FSO_CFE_1_N_IMARK,
++ VI0_DATA23_MARK,
++ FSO_TOE_N_IMARK,
++
++ PINMUX_MARK_END,
++};
++
++static pinmux_enum_t pinmux_data[] = {
++ PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
++
++ /* GPSR0 */
++ PINMUX_DATA(DU_EXODDF_DU_ODDF_DISP_CDE_GMARK, GFN_DU_EXODDF_DU_ODDF_DISP_CDE),
++ PINMUX_DATA(DU_EXVSYNC_DU_VSYNC_GMARK, GFN_DU_EXVSYNC_DU_VSYNC),
++ PINMUX_DATA(DU_EXHSYNC_DU_HSYNC_GMARK, GFN_DU_EXHSYNC_DU_HSYNC),
++ PINMUX_DATA(DU_DOTCLKOUT_GMARK, GFN_DU_DOTCLKOUT),
++ PINMUX_DATA(DU_DB7_GMARK, GFN_DU_DB7),
++ PINMUX_DATA(DU_DB6_GMARK, GFN_DU_DB6),
++ PINMUX_DATA(DU_DB5_GMARK, GFN_DU_DB5),
++ PINMUX_DATA(DU_DB4_GMARK, GFN_DU_DB4),
++ PINMUX_DATA(DU_DB3_GMARK, GFN_DU_DB3),
++ PINMUX_DATA(DU_DB2_GMARK, GFN_DU_DB2),
++ PINMUX_DATA(DU_DG7_GMARK, GFN_DU_DG7),
++ PINMUX_DATA(DU_DG6_GMARK, GFN_DU_DG6),
++ PINMUX_DATA(DU_DG5_GMARK, GFN_DU_DG5),
++ PINMUX_DATA(DU_DG4_GMARK, GFN_DU_DG4),
++ PINMUX_DATA(DU_DG3_GMARK, GFN_DU_DG3),
++ PINMUX_DATA(DU_DG2_GMARK, GFN_DU_DG2),
++ PINMUX_DATA(DU_DR7_GMARK, GFN_DU_DR7),
++ PINMUX_DATA(DU_DR6_GMARK, GFN_DU_DR6),
++ PINMUX_DATA(DU_DR5_GMARK, GFN_DU_DR5),
++ PINMUX_DATA(DU_DR4_GMARK, GFN_DU_DR4),
++ PINMUX_DATA(DU_DR3_GMARK, GFN_DU_DR3),
++ PINMUX_DATA(DU_DR2_GMARK, GFN_DU_DR2),
++
++ /* GPSR1 */
++ PINMUX_DATA(DIGRF_CLKOUT_GMARK, GFN_DIGRF_CLKOUT),
++ PINMUX_DATA(DIGRF_CLKIN_GMARK, GFN_DIGRF_CLKIN),
++ PINMUX_DATA(CANFD_CLK_A_GMARK, GFN_CANFD_CLK_A),
++ PINMUX_DATA(CANFD1_RX_GMARK, GFN_CANFD1_RX),
++ PINMUX_DATA(CANFD1_TX_GMARK, GFN_CANFD1_TX),
++ PINMUX_DATA(CANFD0_RX_A_GMARK, GFN_CANFD0_RX_A),
++ PINMUX_DATA(CANFD0_TX_A_GMARK, GFN_CANFD0_TX_A),
++ PINMUX_DATA(AVB0_AVTP_CAPTURE_GMARK, GFN_AVB0_AVTP_CAPTURE),
++ PINMUX_DATA(AVB0_AVTP_MATCH_GMARK, GFN_AVB0_AVTP_MATCH),
++ PINMUX_DATA(AVB0_LINK_MARK, FN_AVB0_LINK),
++ PINMUX_DATA(AVB0_PHY_INT_MARK, FN_AVB0_PHY_INT),
++ PINMUX_DATA(AVB0_MAGIC_MARK, FN_AVB0_MAGIC),
++ PINMUX_DATA(AVB0_MDC_MARK, FN_AVB0_MDC),
++ PINMUX_DATA(AVB0_MDIO_MARK, FN_AVB0_MDIO),
++ PINMUX_DATA(AVB0_TXCREFCLK_MARK, FN_AVB0_TXCREFCLK),
++ PINMUX_DATA(AVB0_TD3_MARK, FN_AVB0_TD3),
++ PINMUX_DATA(AVB0_TD2_MARK, FN_AVB0_TD2),
++ PINMUX_DATA(AVB0_TD1_MARK, FN_AVB0_TD1),
++ PINMUX_DATA(AVB0_TD0_MARK, FN_AVB0_TD0),
++ PINMUX_DATA(AVB0_TXC_MARK, FN_AVB0_TXC),
++ PINMUX_DATA(AVB0_TX_CTL_MARK, FN_AVB0_TX_CTL),
++ PINMUX_DATA(AVB0_RD3_MARK, FN_AVB0_RD3),
++ PINMUX_DATA(AVB0_RD2_MARK, FN_AVB0_RD2),
++ PINMUX_DATA(AVB0_RD1_MARK, FN_AVB0_RD1),
++ PINMUX_DATA(AVB0_RD0_MARK, FN_AVB0_RD0),
++ PINMUX_DATA(AVB0_RXC_MARK, FN_AVB0_RXC),
++ PINMUX_DATA(AVB0_RX_CTL_MARK, FN_AVB0_RX_CTL),
++ PINMUX_DATA(IRQ0_GMARK, GFN_IRQ0),
++
++ /* GPSR2 */
++ PINMUX_DATA(FSO_TOE_N_GMARK, GFN_FSO_TOE_N),
++ PINMUX_DATA(FSO_CFE_1_N_GMARK, GFN_FSO_CFE_1_N),
++ PINMUX_DATA(FSO_CFE_0_N_GMARK, GFN_FSO_CFE_0_N),
++ PINMUX_DATA(SDA3_GMARK, GFN_SDA3),
++ PINMUX_DATA(SCL3_GMARK, GFN_SCL3),
++ PINMUX_DATA(MSIOF0_SS2_GMARK, GFN_MSIOF0_SS2),
++ PINMUX_DATA(MSIOF0_SS1_GMARK, GFN_MSIOF0_SS1),
++ PINMUX_DATA(MSIOF0_SYNC_GMARK, GFN_MSIOF0_SYNC),
++ PINMUX_DATA(MSIOF0_SCK_GMARK, GFN_MSIOF0_SCK),
++ PINMUX_DATA(MSIOF0_TXD_GMARK, GFN_MSIOF0_TXD),
++ PINMUX_DATA(MSIOF0_RXD_GMARK, GFN_MSIOF0_RXD),
++ PINMUX_DATA(IRQ5_GMARK, GFN_IRQ5),
++ PINMUX_DATA(IRQ4_GMARK, GFN_IRQ4),
++ PINMUX_DATA(VI0_FIELD_GMARK, GFN_VI0_FIELD),
++ PINMUX_DATA(VI0_DATA11_GMARK, GFN_VI0_DATA11),
++ PINMUX_DATA(VI0_DATA10_GMARK, GFN_VI0_DATA10),
++ PINMUX_DATA(VI0_DATA9_GMARK, GFN_VI0_DATA9),
++ PINMUX_DATA(VI0_DATA8_GMARK, GFN_VI0_DATA8),
++ PINMUX_DATA(VI0_DATA7_GMARK, GFN_VI0_DATA7),
++ PINMUX_DATA(VI0_DATA6_GMARK, GFN_VI0_DATA6),
++ PINMUX_DATA(VI0_DATA5_GMARK, GFN_VI0_DATA5),
++ PINMUX_DATA(VI0_DATA4_GMARK, GFN_VI0_DATA4),
++ PINMUX_DATA(VI0_DATA3_GMARK, GFN_VI0_DATA3),
++ PINMUX_DATA(VI0_DATA2_GMARK, GFN_VI0_DATA2),
++ PINMUX_DATA(VI0_DATA1_GMARK, GFN_VI0_DATA1),
++ PINMUX_DATA(VI0_DATA0_GMARK, GFN_VI0_DATA0),
++ PINMUX_DATA(VI0_VSYNC_N_GMARK, GFN_VI0_VSYNC_N),
++ PINMUX_DATA(VI0_HSYNC_N_GMARK, GFN_VI0_HSYNC_N),
++ PINMUX_DATA(VI0_CLKENB_GMARK, GFN_VI0_CLKENB),
++ PINMUX_DATA(VI0_CLK_GMARK, GFN_VI0_CLK),
++
++ /* GPSR3 */
++ PINMUX_DATA(VI1_FIELD_GMARK, GFN_VI1_FIELD),
++ PINMUX_DATA(VI1_DATA11_GMARK, GFN_VI1_DATA11),
++ PINMUX_DATA(VI1_DATA10_GMARK, GFN_VI1_DATA10),
++ PINMUX_DATA(VI1_DATA9_GMARK, GFN_VI1_DATA9),
++ PINMUX_DATA(VI1_DATA8_GMARK, GFN_VI1_DATA8),
++ PINMUX_DATA(VI1_DATA7_GMARK, GFN_VI1_DATA7),
++ PINMUX_DATA(VI1_DATA6_GMARK, GFN_VI1_DATA6),
++ PINMUX_DATA(VI1_DATA5_GMARK, GFN_VI1_DATA5),
++ PINMUX_DATA(VI1_DATA4_GMARK, GFN_VI1_DATA4),
++ PINMUX_DATA(VI1_DATA3_GMARK, GFN_VI1_DATA3),
++ PINMUX_DATA(VI1_DATA2_GMARK, GFN_VI1_DATA2),
++ PINMUX_DATA(VI1_DATA1_GMARK, GFN_VI1_DATA1),
++ PINMUX_DATA(VI1_DATA0_GMARK, GFN_VI1_DATA0),
++ PINMUX_DATA(VI1_VSYNC_N_GMARK, GFN_VI1_VSYNC_N),
++ PINMUX_DATA(VI1_HSYNC_N_GMARK, GFN_VI1_HSYNC_N),
++ PINMUX_DATA(VI1_CLKENB_GMARK, GFN_VI1_CLKENB),
++ PINMUX_DATA(VI1_CLK_GMARK, GFN_VI1_CLK),
++
++ /* GPSR4 */
++ PINMUX_DATA(GETHER_LINK_A_MARK, FN_GETHER_LINK_A),
++ PINMUX_DATA(GETHER_PHY_INT_A_MARK, FN_GETHER_PHY_INT_A),
++ PINMUX_DATA(GETHER_MAGIC_MARK, FN_GETHER_MAGIC),
++ PINMUX_DATA(GETHER_MDC_A_MARK, FN_GETHER_MDC_A),
++ PINMUX_DATA(GETHER_MDIO_A_MARK, FN_GETHER_MDIO_A),
++ PINMUX_DATA(GETHER_TXCREFCLK_MEGA_MARK, FN_GETHER_TXCREFCLK_MEGA),
++ PINMUX_DATA(GETHER_TXCREFCLK_MARK, FN_GETHER_TXCREFCLK),
++ PINMUX_DATA(GETHER_TD3_MARK, FN_GETHER_TD3),
++ PINMUX_DATA(GETHER_TD2_MARK, FN_GETHER_TD2),
++ PINMUX_DATA(GETHER_TD1_MARK, FN_GETHER_TD1),
++ PINMUX_DATA(GETHER_TD0_MARK, FN_GETHER_TD0),
++ PINMUX_DATA(GETHER_TXC_MARK, FN_GETHER_TXC),
++ PINMUX_DATA(GETHER_TX_CTL_MARK, FN_GETHER_TX_CTL),
++ PINMUX_DATA(GETHER_RD3_MARK, FN_GETHER_RD3),
++ PINMUX_DATA(GETHER_RD2_MARK, FN_GETHER_RD2),
++ PINMUX_DATA(GETHER_RD1_MARK, FN_GETHER_RD1),
++ PINMUX_DATA(GETHER_RD0_MARK, FN_GETHER_RD0),
++ PINMUX_DATA(GETHER_RXC_MARK, FN_GETHER_RXC),
++ PINMUX_DATA(GETHER_RX_CTL_MARK, FN_GETHER_RX_CTL),
++ PINMUX_DATA(SDA2_GMARK, GFN_SDA2),
++ PINMUX_DATA(SCL2_GMARK, GFN_SCL2),
++ PINMUX_DATA(SDA1_GMARK, GFN_SDA1),
++ PINMUX_DATA(SCL1_GMARK, GFN_SCL1),
++ PINMUX_DATA(SDA0_GMARK, GFN_SDA0),
++ PINMUX_DATA(SCL0_GMARK, GFN_SCL0),
++
++ /* GPSR5 */
++ PINMUX_DATA(RPC_INT_N_MARK, FN_RPC_INT_N),
++ PINMUX_DATA(RPC_WP_N_MARK, FN_RPC_WP_N),
++ PINMUX_DATA(RPC_RESET_N_MARK, FN_RPC_RESET_N),
++ PINMUX_DATA(QSPI1_SSL_MARK, FN_QSPI1_SSL),
++ PINMUX_DATA(QSPI1_IO3_MARK, FN_QSPI1_IO3),
++ PINMUX_DATA(QSPI1_IO2_MARK, FN_QSPI1_IO2),
++ PINMUX_DATA(QSPI1_MISO_IO1_MARK, FN_QSPI1_MISO_IO1),
++ PINMUX_DATA(QSPI1_MOSI_IO0_MARK, FN_QSPI1_MOSI_IO0),
++ PINMUX_DATA(QSPI1_SPCLK_MARK, FN_QSPI1_SPCLK),
++ PINMUX_DATA(QSPI0_SSL_MARK, FN_QSPI0_SSL),
++ PINMUX_DATA(QSPI0_IO3_MARK, FN_QSPI0_IO3),
++ PINMUX_DATA(QSPI0_IO2_MARK, FN_QSPI0_IO2),
++ PINMUX_DATA(QSPI0_MISO_IO1_MARK, FN_QSPI0_MISO_IO1),
++ PINMUX_DATA(QSPI0_MOSI_IO0_MARK, FN_QSPI0_MOSI_IO0),
++ PINMUX_DATA(QSPI0_SPCLK_MARK, FN_QSPI0_SPCLK),
++
++
++ /* IPSR0 */
++ PINMUX_IPSR_IDATA(DU_DR2),
++ PINMUX_IPSR_DATA(DU_DR2, SCK4),
++ PINMUX_IPSR_DATA(DU_DR2, GETHER_RMII_CRS_DV),
++ PINMUX_IPSR_DATA(DU_DR2, A0),
++ PINMUX_IPSR_IDATA(DU_DR3),
++ PINMUX_IPSR_DATA(DU_DR3, RX4),
++ PINMUX_IPSR_DATA(DU_DR3, GETHER_RMII_RX_ER),
++ PINMUX_IPSR_DATA(DU_DR3, A1),
++ PINMUX_IPSR_IDATA(DU_DR4),
++ PINMUX_IPSR_DATA(DU_DR4, TX4),
++ PINMUX_IPSR_DATA(DU_DR4, GETHER_RMII_RXD0),
++ PINMUX_IPSR_DATA(DU_DR4, A2),
++ PINMUX_IPSR_IDATA(DU_DR5),
++ PINMUX_IPSR_DATA(DU_DR5, CTS4_N),
++ PINMUX_IPSR_DATA(DU_DR5, GETHER_RMII_RXD1),
++ PINMUX_IPSR_DATA(DU_DR5, A3),
++ PINMUX_IPSR_IDATA(DU_DR6),
++ PINMUX_IPSR_DATA(DU_DR6, RTS4_N_TANS),
++ PINMUX_IPSR_DATA(DU_DR6, GETHER_RMII_TXD_EN),
++ PINMUX_IPSR_DATA(DU_DR6, A4),
++ PINMUX_IPSR_IDATA(DU_DR7),
++ PINMUX_IPSR_DATA(DU_DR7, GETHER_RMII_TXD0),
++ PINMUX_IPSR_DATA(DU_DR7, A5),
++ PINMUX_IPSR_IDATA(DU_DG2),
++ PINMUX_IPSR_DATA(DU_DG2, GETHER_RMII_TXD1),
++ PINMUX_IPSR_DATA(DU_DG2, A6),
++ PINMUX_IPSR_IDATA(DU_DG3),
++ PINMUX_IPSR_DATA(DU_DG3, CPG_CPCKOUT),
++ PINMUX_IPSR_DATA(DU_DG3, GETHER_RMII_REFCLK),
++ PINMUX_IPSR_DATA(DU_DG3, A7),
++ PINMUX_IPSR_DATA(DU_DG3, PWMFSW0),
++
++ /* IPSR1 */
++ PINMUX_IPSR_IDATA(DU_DG4),
++ PINMUX_IPSR_DATA(DU_DG4, SCL5),
++ PINMUX_IPSR_DATA(DU_DG4, A8),
++ PINMUX_IPSR_IDATA(DU_DG5),
++ PINMUX_IPSR_DATA(DU_DG5, SDA5),
++ PINMUX_IPSR_DATA(DU_DG5, GETHER_MDC_B),
++ PINMUX_IPSR_DATA(DU_DG5, A9),
++ PINMUX_IPSR_IDATA(DU_DG6),
++ PINMUX_IPSR_DATA(DU_DG6, SCIF_CLK_A),
++ PINMUX_IPSR_DATA(DU_DG6, GETHER_MDIO_B),
++ PINMUX_IPSR_DATA(DU_DG6, A10),
++ PINMUX_IPSR_IDATA(DU_DG7),
++ PINMUX_IPSR_DATA(DU_DG7, HRX0_A),
++ PINMUX_IPSR_DATA(DU_DG7, A11),
++ PINMUX_IPSR_IDATA(DU_DB2),
++ PINMUX_IPSR_DATA(DU_DB2, HSCK0_A),
++ PINMUX_IPSR_DATA(DU_DB2, A12),
++ PINMUX_IPSR_DATA(DU_DB2, IRQ1),
++ PINMUX_IPSR_IDATA(DU_DB3),
++ PINMUX_IPSR_DATA(DU_DB3, HRTS0_N_A),
++ PINMUX_IPSR_DATA(DU_DB3, A13),
++ PINMUX_IPSR_DATA(DU_DB3, IRQ2),
++ PINMUX_IPSR_IDATA(DU_DB4),
++ PINMUX_IPSR_DATA(DU_DB4, HCTS0_N_A),
++ PINMUX_IPSR_DATA(DU_DB4, A14),
++ PINMUX_IPSR_DATA(DU_DB4, IRQ3),
++ PINMUX_IPSR_IDATA(DU_DB5),
++ PINMUX_IPSR_DATA(DU_DB5, HTX0_A),
++ PINMUX_IPSR_DATA(DU_DB5, PWM0_A),
++ PINMUX_IPSR_DATA(DU_DB5, A15),
++
++ /* IPSR2 */
++ PINMUX_IPSR_IDATA(DU_DB6),
++ PINMUX_IPSR_DATA(DU_DB6, MSIOF3_RXD),
++ PINMUX_IPSR_DATA(DU_DB6, A16),
++ PINMUX_IPSR_IDATA(DU_DB7),
++ PINMUX_IPSR_DATA(DU_DB7, MSIOF3_TXD),
++ PINMUX_IPSR_DATA(DU_DB7, A17),
++ PINMUX_IPSR_IDATA(DU_DOTCLKOUT),
++ PINMUX_IPSR_DATA(DU_DOTCLKOUT, MSIOF3_SS1),
++ PINMUX_IPSR_DATA(DU_DOTCLKOUT, GETHER_LINK_B),
++ PINMUX_IPSR_DATA(DU_DOTCLKOUT, A18),
++ PINMUX_IPSR_IDATA(DU_EXHSYNC_DU_HSYNC),
++ PINMUX_IPSR_DATA(DU_EXHSYNC_DU_HSYNC, MSIOF3_SS2),
++ PINMUX_IPSR_DATA(DU_EXHSYNC_DU_HSYNC, GETHER_PHY_INT_B),
++ PINMUX_IPSR_DATA(DU_EXHSYNC_DU_HSYNC, A19),
++ PINMUX_IPSR_DATA(DU_EXHSYNC_DU_HSYNC, FXR_TXENA_N),
++ PINMUX_IPSR_IDATA(DU_EXVSYNC_DU_VSYNC),
++ PINMUX_IPSR_DATA(DU_EXVSYNC_DU_VSYNC, MSIOF3_SCK),
++ PINMUX_IPSR_DATA(DU_EXVSYNC_DU_VSYNC, FXR_TXENB_N),
++ PINMUX_IPSR_IDATA(DU_EXODDF_DU_ODDF_DISP_CDE),
++ PINMUX_IPSR_DATA(DU_EXODDF_DU_ODDF_DISP_CDE, MSIOF3_SYNC),
++ PINMUX_IPSR_IDATA(IRQ0),
++ PINMUX_IPSR_DATA(IRQ0, CC5_OSCOUT),
++ PINMUX_IPSR_IDATA(VI0_CLK),
++ PINMUX_IPSR_DATA(VI0_CLK, MSIOF2_SCK),
++ PINMUX_IPSR_DATA(VI0_CLK, SCK3),
++ PINMUX_IPSR_DATA(VI0_CLK, HSCK3),
++
++ /* IPSR3 */
++ PINMUX_IPSR_IDATA(VI0_CLKENB),
++ PINMUX_IPSR_DATA(VI0_CLKENB, MSIOF2_RXD),
++ PINMUX_IPSR_DATA(VI0_CLKENB, RX3),
++ PINMUX_IPSR_DATA(VI0_CLKENB, RD_WR_N),
++ PINMUX_IPSR_DATA(VI0_CLKENB, HCTS3_N),
++ PINMUX_IPSR_IDATA(VI0_HSYNC_N),
++ PINMUX_IPSR_DATA(VI0_HSYNC_N, MSIOF2_TXD),
++ PINMUX_IPSR_DATA(VI0_HSYNC_N, TX3),
++ PINMUX_IPSR_DATA(VI0_HSYNC_N, HRTS3_N),
++ PINMUX_IPSR_IDATA(VI0_VSYNC_N),
++ PINMUX_IPSR_DATA(VI0_VSYNC_N, MSIOF2_SYNC),
++ PINMUX_IPSR_DATA(VI0_VSYNC_N, CTS3_N),
++ PINMUX_IPSR_DATA(VI0_VSYNC_N, HTX3),
++ PINMUX_IPSR_IDATA(VI0_DATA0),
++ PINMUX_IPSR_DATA(VI0_DATA0, MSIOF2_SS1),
++ PINMUX_IPSR_DATA(VI0_DATA0, RTS3_N_TANS),
++ PINMUX_IPSR_DATA(VI0_DATA0, HRX3),
++ PINMUX_IPSR_IDATA(VI0_DATA1),
++ PINMUX_IPSR_DATA(VI0_DATA1, MSIOF2_SS2),
++ PINMUX_IPSR_DATA(VI0_DATA1, SCK1),
++ PINMUX_IPSR_DATA(VI0_DATA1, SPEEDIN_A),
++ PINMUX_IPSR_IDATA(VI0_DATA2),
++ PINMUX_IPSR_DATA(VI0_DATA2, AVB0_AVTP_PPS),
++ PINMUX_IPSR_IDATA(VI0_DATA3),
++ PINMUX_IPSR_DATA(VI0_DATA3, HSCK1),
++ PINMUX_IPSR_IDATA(VI0_DATA4),
++ PINMUX_IPSR_DATA(VI0_DATA4, HRTS1_N),
++ PINMUX_IPSR_DATA(VI0_DATA4, RX1_A),
++
++ /* IPSR4 */
++ PINMUX_IPSR_IDATA(VI0_DATA5),
++ PINMUX_IPSR_DATA(VI0_DATA5, HCTS1_N),
++ PINMUX_IPSR_DATA(VI0_DATA5, TX1_A),
++ PINMUX_IPSR_IDATA(VI0_DATA6),
++ PINMUX_IPSR_DATA(VI0_DATA6, HTX1),
++ PINMUX_IPSR_DATA(VI0_DATA6, CTS1_N),
++ PINMUX_IPSR_IDATA(VI0_DATA7),
++ PINMUX_IPSR_DATA(VI0_DATA7, HRX1),
++ PINMUX_IPSR_DATA(VI0_DATA7, RTS1_N_TANS),
++ PINMUX_IPSR_IDATA(VI0_DATA8),
++ PINMUX_IPSR_DATA(VI0_DATA8, HSCK2),
++ PINMUX_IPSR_IDATA(VI0_DATA9),
++ PINMUX_IPSR_DATA(VI0_DATA9, HCTS2_N),
++ PINMUX_IPSR_DATA(VI0_DATA9, PWM1_A),
++ PINMUX_IPSR_DATA(VI0_DATA9, FSO_CFE_0_N_B),
++ PINMUX_IPSR_IDATA(VI0_DATA10),
++ PINMUX_IPSR_DATA(VI0_DATA10, HRTS2_N),
++ PINMUX_IPSR_DATA(VI0_DATA10, PWM2_A),
++ PINMUX_IPSR_IDATA(VI0_DATA11),
++ PINMUX_IPSR_DATA(VI0_DATA11, HTX2),
++ PINMUX_IPSR_DATA(VI0_DATA11, PWM3_A),
++ PINMUX_IPSR_IDATA(VI0_FIELD),
++ PINMUX_IPSR_DATA(VI0_FIELD, HRX2),
++ PINMUX_IPSR_DATA(VI0_FIELD, PWM4_A),
++ PINMUX_IPSR_DATA(VI0_FIELD, CS1_N),
++ PINMUX_IPSR_DATA(VI0_FIELD, FSCLKST2_N_A),
++
++ /* IPSR5 */
++ PINMUX_IPSR_IDATA(VI1_CLK),
++ PINMUX_IPSR_DATA(VI1_CLK, MSIOF1_RXD),
++ PINMUX_IPSR_DATA(VI1_CLK, CS0_N),
++ PINMUX_IPSR_IDATA(VI1_CLKENB),
++ PINMUX_IPSR_DATA(VI1_CLKENB, MSIOF1_TXD),
++ PINMUX_IPSR_DATA(VI1_CLKENB, D0),
++ PINMUX_IPSR_IDATA(VI1_HSYNC_N),
++ PINMUX_IPSR_DATA(VI1_HSYNC_N, MSIOF1_SCK),
++ PINMUX_IPSR_DATA(VI1_HSYNC_N, D1),
++ PINMUX_IPSR_IDATA(VI1_VSYNC_N),
++ PINMUX_IPSR_DATA(VI1_VSYNC_N, MSIOF1_SYNC),
++ PINMUX_IPSR_DATA(VI1_VSYNC_N, D2),
++ PINMUX_IPSR_IDATA(VI1_DATA0),
++ PINMUX_IPSR_DATA(VI1_DATA0, MSIOF1_SS1),
++ PINMUX_IPSR_DATA(VI1_DATA0, D3),
++ PINMUX_IPSR_DATA(VI1_DATA0, MMC_WP),
++ PINMUX_IPSR_IDATA(VI1_DATA1),
++ PINMUX_IPSR_DATA(VI1_DATA1, MSIOF1_SS2),
++ PINMUX_IPSR_DATA(VI1_DATA1, D4),
++ PINMUX_IPSR_DATA(VI1_DATA1, MMC_CD),
++ PINMUX_IPSR_IDATA(VI1_DATA2),
++ PINMUX_IPSR_DATA(VI1_DATA2, CANFD0_TX_B),
++ PINMUX_IPSR_DATA(VI1_DATA2, D5),
++ PINMUX_IPSR_DATA(VI1_DATA2, MMC_DS),
++ PINMUX_IPSR_IDATA(VI1_DATA3),
++ PINMUX_IPSR_DATA(VI1_DATA3, CANFD0_RX_B),
++ PINMUX_IPSR_DATA(VI1_DATA3, D6),
++ PINMUX_IPSR_DATA(VI1_DATA3, MMC_CMD),
++
++ /* IPSR6 */
++ PINMUX_IPSR_IDATA(VI1_DATA4),
++ PINMUX_IPSR_DATA(VI1_DATA4, CANFD_CLK_B),
++ PINMUX_IPSR_DATA(VI1_DATA4, D7),
++ PINMUX_IPSR_DATA(VI1_DATA4, MMC_D0),
++ PINMUX_IPSR_IDATA(VI1_DATA5),
++ PINMUX_IPSR_DATA(VI1_DATA5, D8),
++ PINMUX_IPSR_DATA(VI1_DATA5, MMC_D1),
++ PINMUX_IPSR_IDATA(VI1_DATA6),
++ PINMUX_IPSR_DATA(VI1_DATA6, D9),
++ PINMUX_IPSR_DATA(VI1_DATA6, MMC_D2),
++ PINMUX_IPSR_IDATA(VI1_DATA7),
++ PINMUX_IPSR_DATA(VI1_DATA7, D10),
++ PINMUX_IPSR_DATA(VI1_DATA7, MMC_D3),
++ PINMUX_IPSR_IDATA(VI1_DATA8),
++ PINMUX_IPSR_DATA(VI1_DATA8, D11),
++ PINMUX_IPSR_DATA(VI1_DATA8, MMC_CLK),
++ PINMUX_IPSR_IDATA(VI1_DATA9),
++ PINMUX_IPSR_DATA(VI1_DATA9, TCLK1_A),
++ PINMUX_IPSR_DATA(VI1_DATA9, D12),
++ PINMUX_IPSR_DATA(VI1_DATA9, MMC_D4),
++ PINMUX_IPSR_IDATA(VI1_DATA10),
++ PINMUX_IPSR_DATA(VI1_DATA10, TCLK2_A),
++ PINMUX_IPSR_DATA(VI1_DATA10, D13),
++ PINMUX_IPSR_DATA(VI1_DATA10, MMC_D5),
++ PINMUX_IPSR_IDATA(VI1_DATA11),
++ PINMUX_IPSR_DATA(VI1_DATA11, SCL4),
++ PINMUX_IPSR_DATA(VI1_DATA11, D14),
++ PINMUX_IPSR_DATA(VI1_DATA11, MMC_D6),
++
++ /* IPSR7 */
++ PINMUX_IPSR_IDATA(VI1_FIELD),
++ PINMUX_IPSR_DATA(VI1_FIELD, SDA4),
++ PINMUX_IPSR_DATA(VI1_FIELD, D15),
++ PINMUX_IPSR_DATA(VI1_FIELD, MMC_D7),
++ PINMUX_IPSR_IDATA(SCL0),
++ PINMUX_IPSR_DATA(SCL0, CLKOUT),
++ PINMUX_IPSR_IDATA(SDA0),
++ PINMUX_IPSR_DATA(SDA0, BS_N),
++ PINMUX_IPSR_DATA(SDA0, SCK0),
++ PINMUX_IPSR_DATA(SDA0, HSCK0_B),
++ PINMUX_IPSR_IDATA(SCL1),
++ PINMUX_IPSR_DATA(SCL1, TPU0TO2),
++ PINMUX_IPSR_DATA(SCL1, RD_N),
++ PINMUX_IPSR_DATA(SCL1, CTS0_N),
++ PINMUX_IPSR_DATA(SCL1, HCTS0_N_B),
++ PINMUX_IPSR_IDATA(SDA1),
++ PINMUX_IPSR_DATA(SDA1, TPU0TO3),
++ PINMUX_IPSR_DATA(SDA1, WE0_N),
++ PINMUX_IPSR_DATA(SDA1, RTS0_N_TANS),
++ PINMUX_IPSR_DATA(SDA1, HRTS0_N_B),
++ PINMUX_IPSR_IDATA(SCL2),
++ PINMUX_IPSR_DATA(SCL2, WE1_N),
++ PINMUX_IPSR_DATA(SCL2, RX0),
++ PINMUX_IPSR_DATA(SCL2, HRX0_B),
++ PINMUX_IPSR_IDATA(SDA2),
++ PINMUX_IPSR_DATA(SDA2, EX_WAIT0),
++ PINMUX_IPSR_DATA(SDA2, TX0),
++ PINMUX_IPSR_DATA(SDA2, HTX0_B),
++ PINMUX_IPSR_IDATA(AVB0_AVTP_MATCH),
++ PINMUX_IPSR_DATA(AVB0_AVTP_MATCH, TPU0TO0),
++
++ /* IPSR8 */
++ PINMUX_IPSR_IDATA(AVB0_AVTP_CAPTURE),
++ PINMUX_IPSR_DATA(AVB0_AVTP_CAPTURE, TPU0TO1),
++ PINMUX_IPSR_IDATA(CANFD0_TX_A),
++ PINMUX_IPSR_DATA(CANFD0_TX_A, FXR_TXDA),
++ PINMUX_IPSR_DATA(CANFD0_TX_A, PWM0_B),
++ PINMUX_IPSR_DATA(CANFD0_TX_A, DU_DISP),
++ PINMUX_IPSR_IDATA(CANFD0_RX_A),
++ PINMUX_IPSR_DATA(CANFD0_RX_A, RXDA_EXTFXR),
++ PINMUX_IPSR_DATA(CANFD0_RX_A, PWM1_B),
++ PINMUX_IPSR_DATA(CANFD0_RX_A, DU_CDE),
++ PINMUX_IPSR_IDATA(CANFD1_TX),
++ PINMUX_IPSR_DATA(CANFD1_TX, FXR_TXDB),
++ PINMUX_IPSR_DATA(CANFD1_TX, PWM2_B),
++ PINMUX_IPSR_DATA(CANFD1_TX, TCLK1_B),
++ PINMUX_IPSR_DATA(CANFD1_TX, TX1_B),
++ PINMUX_IPSR_IDATA(CANFD1_RX),
++ PINMUX_IPSR_DATA(CANFD1_RX, RXDB_EXTFXR),
++ PINMUX_IPSR_DATA(CANFD1_RX, PWM3_B),
++ PINMUX_IPSR_DATA(CANFD1_RX, TCLK2_B),
++ PINMUX_IPSR_DATA(CANFD1_RX, RX1_B),
++ PINMUX_IPSR_IDATA(CANFD_CLK_A),
++ PINMUX_IPSR_DATA(CANFD_CLK_A, CLK_EXTFXR),
++ PINMUX_IPSR_DATA(CANFD_CLK_A, PWM4_B),
++ PINMUX_IPSR_DATA(CANFD_CLK_A, SPEEDIN_B),
++ PINMUX_IPSR_DATA(CANFD_CLK_A, SCIF_CLK_B),
++ PINMUX_IPSR_IDATA(DIGRF_CLKIN),
++ PINMUX_IPSR_DATA(DIGRF_CLKIN, DIGRF_CLKEN_IN),
++ PINMUX_IPSR_IDATA(DIGRF_CLKOUT),
++ PINMUX_IPSR_DATA(DIGRF_CLKOUT, DIGRF_CLKEN_OUT),
++
++ /* IPSR9 */
++ PINMUX_IPSR_IDATA(IRQ4),
++ PINMUX_IPSR_DATA(IRQ4, VI0_DATA12),
++ PINMUX_IPSR_IDATA(IRQ5),
++ PINMUX_IPSR_DATA(IRQ5, VI0_DATA13),
++ PINMUX_IPSR_IDATA(MSIOF0_RXD),
++ PINMUX_IPSR_DATA(MSIOF0_RXD, DU_DR0),
++ PINMUX_IPSR_DATA(MSIOF0_RXD, VI0_DATA14),
++ PINMUX_IPSR_IDATA(MSIOF0_TXD),
++ PINMUX_IPSR_DATA(MSIOF0_TXD, DU_DR1),
++ PINMUX_IPSR_DATA(MSIOF0_TXD, VI0_DATA15),
++ PINMUX_IPSR_IDATA(MSIOF0_SCK),
++ PINMUX_IPSR_DATA(MSIOF0_SCK, DU_DG0),
++ PINMUX_IPSR_DATA(MSIOF0_SCK, VI0_DATA16),
++ PINMUX_IPSR_IDATA(MSIOF0_SYNC),
++ PINMUX_IPSR_DATA(MSIOF0_SYNC, DU_DG1),
++ PINMUX_IPSR_DATA(MSIOF0_SYNC, VI0_DATA17),
++ PINMUX_IPSR_IDATA(MSIOF0_SS1),
++ PINMUX_IPSR_DATA(MSIOF0_SS1, DU_DB0),
++ PINMUX_IPSR_DATA(MSIOF0_SS1, TCLK3),
++ PINMUX_IPSR_DATA(MSIOF0_SS1, VI0_DATA18),
++ PINMUX_IPSR_IDATA(MSIOF0_SS2),
++ PINMUX_IPSR_DATA(MSIOF0_SS2, DU_DB1),
++ PINMUX_IPSR_DATA(MSIOF0_SS2, TCLK4),
++ PINMUX_IPSR_DATA(MSIOF0_SS2, VI0_DATA19),
++
++ /* IPSR10 */
++ PINMUX_IPSR_IDATA(SCL3),
++ PINMUX_IPSR_DATA(SCL3, VI0_DATA20),
++ PINMUX_IPSR_IDATA(SDA3),
++ PINMUX_IPSR_DATA(SDA3, VI0_DATA21),
++ PINMUX_IPSR_IDATA(FSO_CFE_0_N),
++ PINMUX_IPSR_DATA(FSO_CFE_0_N, VI0_DATA22),
++ PINMUX_IPSR_IDATA(FSO_CFE_1_N),
++ PINMUX_IPSR_DATA(FSO_CFE_1_N, VI0_DATA23),
++ PINMUX_IPSR_IDATA(FSO_TOE_N),
++};
++
++static struct pinmux_gpio pinmux_gpios[] = {
++ PINMUX_GPIO_GP_ALL(),
++
++ /* GPSR0 */
++ GPIO_GFN(DU_EXODDF_DU_ODDF_DISP_CDE),
++ GPIO_GFN(DU_EXVSYNC_DU_VSYNC),
++ GPIO_GFN(DU_EXHSYNC_DU_HSYNC),
++ GPIO_GFN(DU_DOTCLKOUT),
++ GPIO_GFN(DU_DB7),
++ GPIO_GFN(DU_DB6),
++ GPIO_GFN(DU_DB5),
++ GPIO_GFN(DU_DB4),
++ GPIO_GFN(DU_DB3),
++ GPIO_GFN(DU_DB2),
++ GPIO_GFN(DU_DG7),
++ GPIO_GFN(DU_DG6),
++ GPIO_GFN(DU_DG5),
++ GPIO_GFN(DU_DG4),
++ GPIO_GFN(DU_DG3),
++ GPIO_GFN(DU_DG2),
++ GPIO_GFN(DU_DR7),
++ GPIO_GFN(DU_DR6),
++ GPIO_GFN(DU_DR5),
++ GPIO_GFN(DU_DR4),
++ GPIO_GFN(DU_DR3),
++ GPIO_GFN(DU_DR2),
++
++ /* GPSR1 */
++ GPIO_GFN(DIGRF_CLKOUT),
++ GPIO_GFN(DIGRF_CLKIN),
++ GPIO_GFN(CANFD_CLK_A),
++ GPIO_GFN(CANFD1_RX),
++ GPIO_GFN(CANFD1_TX),
++ GPIO_GFN(CANFD0_RX_A),
++ GPIO_GFN(CANFD0_TX_A),
++ GPIO_GFN(AVB0_AVTP_CAPTURE),
++ GPIO_GFN(AVB0_AVTP_MATCH),
++ GPIO_FN(AVB0_LINK),
++ GPIO_FN(AVB0_PHY_INT),
++ GPIO_FN(AVB0_MAGIC),
++ GPIO_FN(AVB0_MDC),
++ GPIO_FN(AVB0_MDIO),
++ GPIO_FN(AVB0_TXCREFCLK),
++ GPIO_FN(AVB0_TD3),
++ GPIO_FN(AVB0_TD2),
++ GPIO_FN(AVB0_TD1),
++ GPIO_FN(AVB0_TD0),
++ GPIO_FN(AVB0_TXC),
++ GPIO_FN(AVB0_TX_CTL),
++ GPIO_FN(AVB0_RD3),
++ GPIO_FN(AVB0_RD2),
++ GPIO_FN(AVB0_RD1),
++ GPIO_FN(AVB0_RD0),
++ GPIO_FN(AVB0_RXC),
++ GPIO_FN(AVB0_RX_CTL),
++ GPIO_GFN(IRQ0),
++
++ /* GPSR2 */
++ GPIO_GFN(FSO_TOE_N),
++ GPIO_GFN(FSO_CFE_1_N),
++ GPIO_GFN(FSO_CFE_0_N),
++ GPIO_GFN(SDA3),
++ GPIO_GFN(SCL3),
++ GPIO_GFN(MSIOF0_SS2),
++ GPIO_GFN(MSIOF0_SS1),
++ GPIO_GFN(MSIOF0_SYNC),
++ GPIO_GFN(MSIOF0_SCK),
++ GPIO_GFN(MSIOF0_TXD),
++ GPIO_GFN(MSIOF0_RXD),
++ GPIO_GFN(IRQ5),
++ GPIO_GFN(IRQ4),
++ GPIO_GFN(VI0_FIELD),
++ GPIO_GFN(VI0_DATA11),
++ GPIO_GFN(VI0_DATA10),
++ GPIO_GFN(VI0_DATA9),
++ GPIO_GFN(VI0_DATA8),
++ GPIO_GFN(VI0_DATA7),
++ GPIO_GFN(VI0_DATA6),
++ GPIO_GFN(VI0_DATA5),
++ GPIO_GFN(VI0_DATA4),
++ GPIO_GFN(VI0_DATA3),
++ GPIO_GFN(VI0_DATA2),
++ GPIO_GFN(VI0_DATA1),
++ GPIO_GFN(VI0_DATA0),
++ GPIO_GFN(VI0_VSYNC_N),
++ GPIO_GFN(VI0_HSYNC_N),
++ GPIO_GFN(VI0_CLKENB),
++ GPIO_GFN(VI0_CLK),
++
++ /* GPSR3 */
++ GPIO_GFN(VI1_FIELD),
++ GPIO_GFN(VI1_DATA11),
++ GPIO_GFN(VI1_DATA10),
++ GPIO_GFN(VI1_DATA9),
++ GPIO_GFN(VI1_DATA8),
++ GPIO_GFN(VI1_DATA7),
++ GPIO_GFN(VI1_DATA6),
++ GPIO_GFN(VI1_DATA5),
++ GPIO_GFN(VI1_DATA4),
++ GPIO_GFN(VI1_DATA3),
++ GPIO_GFN(VI1_DATA2),
++ GPIO_GFN(VI1_DATA1),
++ GPIO_GFN(VI1_DATA0),
++ GPIO_GFN(VI1_VSYNC_N),
++ GPIO_GFN(VI1_HSYNC_N),
++ GPIO_GFN(VI1_CLKENB),
++ GPIO_GFN(VI1_CLK),
++
++ /* GPSR4 */
++ GPIO_FN(GETHER_LINK_A),
++ GPIO_FN(GETHER_PHY_INT_A),
++ GPIO_FN(GETHER_MAGIC),
++ GPIO_FN(GETHER_MDC_A),
++ GPIO_FN(GETHER_MDIO_A),
++ GPIO_FN(GETHER_TXCREFCLK_MEGA),
++ GPIO_FN(GETHER_TXCREFCLK),
++ GPIO_FN(GETHER_TD3),
++ GPIO_FN(GETHER_TD2),
++ GPIO_FN(GETHER_TD1),
++ GPIO_FN(GETHER_TD0),
++ GPIO_FN(GETHER_TXC),
++ GPIO_FN(GETHER_TX_CTL),
++ GPIO_FN(GETHER_RD3),
++ GPIO_FN(GETHER_RD2),
++ GPIO_FN(GETHER_RD1),
++ GPIO_FN(GETHER_RD0),
++ GPIO_FN(GETHER_RXC),
++ GPIO_FN(GETHER_RX_CTL),
++ GPIO_GFN(SDA2),
++ GPIO_GFN(SCL2),
++ GPIO_GFN(SDA1),
++ GPIO_GFN(SCL1),
++ GPIO_GFN(SDA0),
++ GPIO_GFN(SCL0),
++
++ /* GPSR5 */
++ GPIO_FN(RPC_INT_N),
++ GPIO_FN(RPC_WP_N),
++ GPIO_FN(RPC_RESET_N),
++ GPIO_FN(QSPI1_SSL),
++ GPIO_FN(QSPI1_IO3),
++ GPIO_FN(QSPI1_IO2),
++ GPIO_FN(QSPI1_MISO_IO1),
++ GPIO_FN(QSPI1_MOSI_IO0),
++ GPIO_FN(QSPI1_SPCLK),
++ GPIO_FN(QSPI0_SSL),
++ GPIO_FN(QSPI0_IO3),
++ GPIO_FN(QSPI0_IO2),
++ GPIO_FN(QSPI0_MISO_IO1),
++ GPIO_FN(QSPI0_MOSI_IO0),
++ GPIO_FN(QSPI0_SPCLK),
++
++ /* IPSR0 */
++ GPIO_IFN(DU_DR2),
++ GPIO_FN(SCK4),
++ GPIO_FN(GETHER_RMII_CRS_DV),
++ GPIO_FN(A0),
++ GPIO_IFN(DU_DR3),
++ GPIO_FN(RX4),
++ GPIO_FN(GETHER_RMII_RX_ER),
++ GPIO_FN(A1),
++ GPIO_IFN(DU_DR4),
++ GPIO_FN(TX4),
++ GPIO_FN(GETHER_RMII_RXD0),
++ GPIO_FN(A2),
++ GPIO_IFN(DU_DR5),
++ GPIO_FN(CTS4_N),
++ GPIO_FN(GETHER_RMII_RXD1),
++ GPIO_FN(A3),
++ GPIO_IFN(DU_DR6),
++ GPIO_FN(RTS4_N_TANS),
++ GPIO_FN(GETHER_RMII_TXD_EN),
++ GPIO_FN(A4),
++ GPIO_IFN(DU_DR7),
++ GPIO_FN(GETHER_RMII_TXD0),
++ GPIO_FN(A5),
++ GPIO_IFN(DU_DG2),
++ GPIO_FN(GETHER_RMII_TXD1),
++ GPIO_FN(A6),
++ GPIO_IFN(DU_DG3),
++ GPIO_FN(CPG_CPCKOUT),
++ GPIO_FN(GETHER_RMII_REFCLK),
++ GPIO_FN(A7),
++ GPIO_FN(PWMFSW0),
++
++ /* IPSR1 */
++ GPIO_IFN(DU_DG4),
++ GPIO_FN(SCL5),
++ GPIO_FN(A8),
++ GPIO_IFN(DU_DG5),
++ GPIO_FN(SDA5),
++ GPIO_FN(GETHER_MDC_B),
++ GPIO_FN(A9),
++ GPIO_IFN(DU_DG6),
++ GPIO_FN(SCIF_CLK_A),
++ GPIO_FN(GETHER_MDIO_B),
++ GPIO_FN(A10),
++ GPIO_IFN(DU_DG7),
++ GPIO_FN(HRX0_A),
++ GPIO_FN(A11),
++ GPIO_IFN(DU_DB2),
++ GPIO_FN(HSCK0_A),
++ GPIO_FN(A12),
++ GPIO_FN(IRQ1),
++ GPIO_IFN(DU_DB3),
++ GPIO_FN(HRTS0_N_A),
++ GPIO_FN(A13),
++ GPIO_FN(IRQ2),
++ GPIO_IFN(DU_DB4),
++ GPIO_FN(HCTS0_N_A),
++ GPIO_FN(A14),
++ GPIO_FN(IRQ3),
++ GPIO_IFN(DU_DB5),
++ GPIO_FN(HTX0_A),
++ GPIO_FN(PWM0_A),
++ GPIO_FN(A15),
++
++ /* IPSR2 */
++ GPIO_IFN(DU_DB6),
++ GPIO_FN(MSIOF3_RXD),
++ GPIO_FN(A16),
++ GPIO_IFN(DU_DB7),
++ GPIO_FN(MSIOF3_TXD),
++ GPIO_FN(A17),
++ GPIO_IFN(DU_DOTCLKOUT),
++ GPIO_FN(MSIOF3_SS1),
++ GPIO_FN(GETHER_LINK_B),
++ GPIO_FN(A18),
++ GPIO_IFN(DU_EXHSYNC_DU_HSYNC),
++ GPIO_FN(MSIOF3_SS2),
++ GPIO_FN(GETHER_PHY_INT_B),
++ GPIO_FN(A19),
++ GPIO_FN(FXR_TXENA_N),
++ GPIO_IFN(DU_EXVSYNC_DU_VSYNC),
++ GPIO_FN(MSIOF3_SCK),
++ GPIO_FN(FXR_TXENB_N),
++ GPIO_IFN(DU_EXODDF_DU_ODDF_DISP_CDE),
++ GPIO_FN(MSIOF3_SYNC),
++ GPIO_IFN(IRQ0),
++ GPIO_FN(CC5_OSCOUT),
++ GPIO_IFN(VI0_CLK),
++ GPIO_FN(MSIOF2_SCK),
++ GPIO_FN(SCK3),
++ GPIO_FN(HSCK3),
++
++ /* IPSR3 */
++ GPIO_IFN(VI0_CLKENB),
++ GPIO_FN(MSIOF2_RXD),
++ GPIO_FN(RX3),
++ GPIO_FN(RD_WR_N),
++ GPIO_FN(HCTS3_N),
++ GPIO_IFN(VI0_HSYNC_N),
++ GPIO_FN(MSIOF2_TXD),
++ GPIO_FN(TX3),
++ GPIO_FN(HRTS3_N),
++ GPIO_IFN(VI0_VSYNC_N),
++ GPIO_FN(MSIOF2_SYNC),
++ GPIO_FN(CTS3_N),
++ GPIO_FN(HTX3),
++ GPIO_IFN(VI0_DATA0),
++ GPIO_FN(MSIOF2_SS1),
++ GPIO_FN(RTS3_N_TANS),
++ GPIO_FN(HRX3),
++ GPIO_IFN(VI0_DATA1),
++ GPIO_FN(MSIOF2_SS2),
++ GPIO_FN(SCK1),
++ GPIO_FN(SPEEDIN_A),
++ GPIO_IFN(VI0_DATA2),
++ GPIO_FN(AVB0_AVTP_PPS),
++ GPIO_IFN(VI0_DATA3),
++ GPIO_FN(HSCK1),
++ GPIO_IFN(VI0_DATA4),
++ GPIO_FN(HRTS1_N),
++ GPIO_FN(RX1_A),
++
++ /* IPSR4 */
++ GPIO_IFN(VI0_DATA5),
++ GPIO_FN(HCTS1_N),
++ GPIO_FN(TX1_A),
++ GPIO_IFN(VI0_DATA6),
++ GPIO_FN(HTX1),
++ GPIO_FN(CTS1_N),
++ GPIO_IFN(VI0_DATA7),
++ GPIO_FN(HRX1),
++ GPIO_FN(RTS1_N_TANS),
++ GPIO_IFN(VI0_DATA8),
++ GPIO_FN(HSCK2),
++ GPIO_IFN(VI0_DATA9),
++ GPIO_FN(HCTS2_N),
++ GPIO_FN(PWM1_A),
++ GPIO_FN(FSO_CFE_0_N_B),
++ GPIO_IFN(VI0_DATA10),
++ GPIO_FN(HRTS2_N),
++ GPIO_FN(PWM2_A),
++ GPIO_IFN(VI0_DATA11),
++ GPIO_FN(HTX2),
++ GPIO_FN(PWM3_A),
++ GPIO_IFN(VI0_FIELD),
++ GPIO_FN(HRX2),
++ GPIO_FN(PWM4_A),
++ GPIO_FN(CS1_N),
++ GPIO_FN(FSCLKST2_N_A),
++
++ /* IPSR5 */
++ GPIO_IFN(VI1_CLK),
++ GPIO_FN(MSIOF1_RXD),
++ GPIO_FN(CS0_N),
++ GPIO_IFN(VI1_CLKENB),
++ GPIO_FN(MSIOF1_TXD),
++ GPIO_FN(D0),
++ GPIO_IFN(VI1_HSYNC_N),
++ GPIO_FN(MSIOF1_SCK),
++ GPIO_FN(D1),
++ GPIO_IFN(VI1_VSYNC_N),
++ GPIO_FN(MSIOF1_SYNC),
++ GPIO_FN(D2),
++ GPIO_IFN(VI1_DATA0),
++ GPIO_FN(MSIOF1_SS1),
++ GPIO_FN(D3),
++ GPIO_FN(MMC_WP),
++ GPIO_IFN(VI1_DATA1),
++ GPIO_FN(MSIOF1_SS2),
++ GPIO_FN(D4),
++ GPIO_FN(MMC_CD),
++ GPIO_IFN(VI1_DATA2),
++ GPIO_FN(CANFD0_TX_B),
++ GPIO_FN(D5),
++ GPIO_FN(MMC_DS),
++ GPIO_IFN(VI1_DATA3),
++ GPIO_FN(CANFD0_RX_B),
++ GPIO_FN(D6),
++ GPIO_FN(MMC_CMD),
++
++ /* IPSR6 */
++ GPIO_IFN(VI1_DATA4),
++ GPIO_FN(CANFD_CLK_B),
++ GPIO_FN(D7),
++ GPIO_FN(MMC_D0),
++ GPIO_IFN(VI1_DATA5),
++ GPIO_FN(D8),
++ GPIO_FN(MMC_D1),
++ GPIO_IFN(VI1_DATA6),
++ GPIO_FN(D9),
++ GPIO_FN(MMC_D2),
++ GPIO_IFN(VI1_DATA7),
++ GPIO_FN(D10),
++ GPIO_FN(MMC_D3),
++ GPIO_IFN(VI1_DATA8),
++ GPIO_FN(D11),
++ GPIO_FN(MMC_CLK),
++ GPIO_IFN(VI1_DATA9),
++ GPIO_FN(TCLK1_A),
++ GPIO_FN(D12),
++ GPIO_FN(MMC_D4),
++ GPIO_IFN(VI1_DATA10),
++ GPIO_FN(TCLK2_A),
++ GPIO_FN(D13),
++ GPIO_FN(MMC_D5),
++ GPIO_IFN(VI1_DATA11),
++ GPIO_FN(SCL4),
++ GPIO_FN(D14),
++ GPIO_FN(MMC_D6),
++
++ /* IPSR7 */
++ GPIO_IFN(VI1_FIELD),
++ GPIO_FN(SDA4),
++ GPIO_FN(D15),
++ GPIO_FN(MMC_D7),
++ GPIO_IFN(SCL0),
++ GPIO_FN(CLKOUT),
++ GPIO_IFN(SDA0),
++ GPIO_FN(BS_N),
++ GPIO_FN(SCK0),
++ GPIO_FN(HSCK0_B),
++ GPIO_IFN(SCL1),
++ GPIO_FN(TPU0TO2),
++ GPIO_FN(RD_N),
++ GPIO_FN(CTS0_N),
++ GPIO_FN(HCTS0_N_B),
++ GPIO_IFN(SDA1),
++ GPIO_FN(TPU0TO3),
++ GPIO_FN(WE0_N),
++ GPIO_FN(RTS0_N_TANS),
++ GPIO_FN(HRTS0_N_B),
++ GPIO_IFN(SCL2),
++ GPIO_FN(WE1_N),
++ GPIO_FN(RX0),
++ GPIO_FN(HRX0_B),
++ GPIO_IFN(SDA2),
++ GPIO_FN(EX_WAIT0),
++ GPIO_FN(TX0),
++ GPIO_FN(HTX0_B),
++ GPIO_IFN(AVB0_AVTP_MATCH),
++ GPIO_FN(TPU0TO0),
++
++ /* IPSR8 */
++ GPIO_IFN(AVB0_AVTP_CAPTURE),
++ GPIO_FN(TPU0TO1),
++ GPIO_IFN(CANFD0_TX_A),
++ GPIO_FN(FXR_TXDA),
++ GPIO_FN(PWM0_B),
++ GPIO_FN(DU_DISP),
++ GPIO_IFN(CANFD0_RX_A),
++ GPIO_FN(RXDA_EXTFXR),
++ GPIO_FN(PWM1_B),
++ GPIO_FN(DU_CDE),
++ GPIO_IFN(CANFD1_TX),
++ GPIO_FN(FXR_TXDB),
++ GPIO_FN(PWM2_B),
++ GPIO_FN(TCLK1_B),
++ GPIO_FN(TX1_B),
++ GPIO_IFN(CANFD1_RX),
++ GPIO_FN(RXDB_EXTFXR),
++ GPIO_FN(PWM3_B),
++ GPIO_FN(TCLK2_B),
++ GPIO_FN(RX1_B),
++ GPIO_IFN(CANFD_CLK_A),
++ GPIO_FN(CLK_EXTFXR),
++ GPIO_FN(PWM4_B),
++ GPIO_FN(SPEEDIN_B),
++ GPIO_FN(SCIF_CLK_B),
++ GPIO_IFN(DIGRF_CLKIN),
++ GPIO_FN(DIGRF_CLKEN_IN),
++ GPIO_IFN(DIGRF_CLKOUT),
++ GPIO_FN(DIGRF_CLKEN_OUT),
++
++ /* IPSR9 */
++ GPIO_IFN(IRQ4),
++ GPIO_FN(VI0_DATA12),
++ GPIO_IFN(IRQ5),
++ GPIO_FN(VI0_DATA13),
++ GPIO_IFN(MSIOF0_RXD),
++ GPIO_FN(DU_DR0),
++ GPIO_FN(VI0_DATA14),
++ GPIO_IFN(MSIOF0_TXD),
++ GPIO_FN(DU_DR1),
++ GPIO_FN(VI0_DATA15),
++ GPIO_IFN(MSIOF0_SCK),
++ GPIO_FN(DU_DG0),
++ GPIO_FN(VI0_DATA16),
++ GPIO_IFN(MSIOF0_SYNC),
++ GPIO_FN(DU_DG1),
++ GPIO_FN(VI0_DATA17),
++ GPIO_IFN(MSIOF0_SS1),
++ GPIO_FN(DU_DB0),
++ GPIO_FN(TCLK3),
++ GPIO_FN(VI0_DATA18),
++ GPIO_IFN(MSIOF0_SS2),
++ GPIO_FN(DU_DB1),
++ GPIO_FN(TCLK4),
++ GPIO_FN(VI0_DATA19),
++
++ /* IPSR10 */
++ GPIO_IFN(SCL3),
++ GPIO_FN(VI0_DATA20),
++ GPIO_IFN(SDA3),
++ GPIO_FN(VI0_DATA21),
++ GPIO_IFN(FSO_CFE_0_N),
++ GPIO_FN(VI0_DATA22),
++ GPIO_IFN(FSO_CFE_1_N),
++ GPIO_FN(VI0_DATA23),
++ GPIO_IFN(FSO_TOE_N),
++};
++
++static struct pinmux_cfg_reg pinmux_config_regs[] = {
++ /* GPSR0(0xE6060100) md[3:1] controls initial value */
++ /* md[3:1] .. 0 : 0x0000FFFF */
++ /* .. other : 0x00000000 */
++ { PINMUX_CFG_REG("GPSR0", 0xE6060100, 32, 1) {
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ GP_0_21_FN, GFN_DU_EXODDF_DU_ODDF_DISP_CDE,
++ GP_0_20_FN, GFN_DU_EXVSYNC_DU_VSYNC,
++ GP_0_19_FN, GFN_DU_EXHSYNC_DU_HSYNC,
++ GP_0_18_FN, GFN_DU_DOTCLKOUT,
++ GP_0_17_FN, GFN_DU_DB7,
++ GP_0_16_FN, GFN_DU_DB6,
++ GP_0_15_FN, GFN_DU_DB5,
++ GP_0_14_FN, GFN_DU_DB4,
++ GP_0_13_FN, GFN_DU_DB3,
++ GP_0_12_FN, GFN_DU_DB2,
++ GP_0_11_FN, GFN_DU_DG7,
++ GP_0_10_FN, GFN_DU_DG6,
++ GP_0_9_FN, GFN_DU_DG5,
++ GP_0_8_FN, GFN_DU_DG4,
++ GP_0_7_FN, GFN_DU_DG3,
++ GP_0_6_FN, GFN_DU_DG2,
++ GP_0_5_FN, GFN_DU_DR7,
++ GP_0_4_FN, GFN_DU_DR6,
++ GP_0_3_FN, GFN_DU_DR5,
++ GP_0_2_FN, GFN_DU_DR4,
++ GP_0_1_FN, GFN_DU_DR3,
++ GP_0_0_FN, GFN_DU_DR2 }
++ },
++ /* GPSR1(0xE6060104) is md[3:1] controls initial value */
++ /* md[3:1] .. 0 : 0x0EFFFFFF */
++ /* .. other : 0x00000000 */
++ { PINMUX_CFG_REG("GPSR1", 0xE6060104, 32, 1) {
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ GP_1_27_FN, GFN_DIGRF_CLKOUT,
++ GP_1_26_FN, GFN_DIGRF_CLKIN,
++ GP_1_25_FN, GFN_CANFD_CLK_A,
++ GP_1_24_FN, GFN_CANFD1_RX,
++ GP_1_23_FN, GFN_CANFD1_TX,
++ GP_1_22_FN, GFN_CANFD0_RX_A,
++ GP_1_21_FN, GFN_CANFD0_TX_A,
++ GP_1_20_FN, GFN_AVB0_AVTP_CAPTURE,
++ GP_1_19_FN, GFN_AVB0_AVTP_MATCH,
++ GP_1_18_FN, FN_AVB0_LINK,
++ GP_1_17_FN, FN_AVB0_PHY_INT,
++ GP_1_16_FN, FN_AVB0_MAGIC,
++ GP_1_15_FN, FN_AVB0_MDC,
++ GP_1_14_FN, FN_AVB0_MDIO,
++ GP_1_13_FN, FN_AVB0_TXCREFCLK,
++ GP_1_12_FN, FN_AVB0_TD3,
++ GP_1_11_FN, FN_AVB0_TD2,
++ GP_1_10_FN, FN_AVB0_TD1,
++ GP_1_9_FN, FN_AVB0_TD0,
++ GP_1_8_FN, FN_AVB0_TXC,
++ GP_1_7_FN, FN_AVB0_TX_CTL,
++ GP_1_6_FN, FN_AVB0_RD3,
++ GP_1_5_FN, FN_AVB0_RD2,
++ GP_1_4_FN, FN_AVB0_RD1,
++ GP_1_3_FN, FN_AVB0_RD0,
++ GP_1_2_FN, FN_AVB0_RXC,
++ GP_1_1_FN, FN_AVB0_RX_CTL,
++ GP_1_0_FN, GFN_IRQ0 }
++ },
++ /* GPSR2(0xE6060108) is md[3:1] controls */
++ /* md[3:1] .. 0 : 0x000003C0 */
++ /* .. other : 0x00000200 */
++ { PINMUX_CFG_REG("GPSR2", 0xE6060108, 32, 1) {
++ 0, 0,
++ 0, 0,
++ GP_2_29_FN, GFN_FSO_TOE_N,
++ GP_2_28_FN, GFN_FSO_CFE_1_N,
++ GP_2_27_FN, GFN_FSO_CFE_0_N,
++ GP_2_26_FN, GFN_SDA3,
++ GP_2_25_FN, GFN_SCL3,
++ GP_2_24_FN, GFN_MSIOF0_SS2,
++ GP_2_23_FN, GFN_MSIOF0_SS1,
++ GP_2_22_FN, GFN_MSIOF0_SYNC,
++ GP_2_21_FN, GFN_MSIOF0_SCK,
++ GP_2_20_FN, GFN_MSIOF0_TXD,
++ GP_2_19_FN, GFN_MSIOF0_RXD,
++ GP_2_18_FN, GFN_IRQ5,
++ GP_2_17_FN, GFN_IRQ4,
++ GP_2_16_FN, GFN_VI0_FIELD,
++ GP_2_15_FN, GFN_VI0_DATA11,
++ GP_2_14_FN, GFN_VI0_DATA10,
++ GP_2_13_FN, GFN_VI0_DATA9,
++ GP_2_12_FN, GFN_VI0_DATA8,
++ GP_2_11_FN, GFN_VI0_DATA7,
++ GP_2_10_FN, GFN_VI0_DATA6,
++ GP_2_9_FN, GFN_VI0_DATA5,
++ GP_2_8_FN, GFN_VI0_DATA4,
++ GP_2_7_FN, GFN_VI0_DATA3,
++ GP_2_6_FN, GFN_VI0_DATA2,
++ GP_2_5_FN, GFN_VI0_DATA1,
++ GP_2_4_FN, GFN_VI0_DATA0,
++ GP_2_3_FN, GFN_VI0_VSYNC_N,
++ GP_2_2_FN, GFN_VI0_HSYNC_N,
++ GP_2_1_FN, GFN_VI0_CLKENB,
++ GP_2_0_FN, GFN_VI0_CLK }
++ },
++
++ /* GPSR3 */
++ { PINMUX_CFG_REG("GPSR3", 0xE606010C, 32, 1) {
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ GP_3_16_FN, GFN_VI1_FIELD,
++ GP_3_15_FN, GFN_VI1_DATA11,
++ GP_3_14_FN, GFN_VI1_DATA10,
++ GP_3_13_FN, GFN_VI1_DATA9,
++ GP_3_12_FN, GFN_VI1_DATA8,
++ GP_3_11_FN, GFN_VI1_DATA7,
++ GP_3_10_FN, GFN_VI1_DATA6,
++ GP_3_9_FN, GFN_VI1_DATA5,
++ GP_3_8_FN, GFN_VI1_DATA4,
++ GP_3_7_FN, GFN_VI1_DATA3,
++ GP_3_6_FN, GFN_VI1_DATA2,
++ GP_3_5_FN, GFN_VI1_DATA1,
++ GP_3_4_FN, GFN_VI1_DATA0,
++ GP_3_3_FN, GFN_VI1_VSYNC_N,
++ GP_3_2_FN, GFN_VI1_HSYNC_N,
++ GP_3_1_FN, GFN_VI1_CLKENB,
++ GP_3_0_FN, GFN_VI1_CLK }
++ },
++ /* GPSR4 */
++ { PINMUX_CFG_REG("GPSR4", 0xE6060110, 32, 1) {
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ GP_4_24_FN, FN_GETHER_LINK_A,
++ GP_4_23_FN, FN_GETHER_PHY_INT_A,
++ GP_4_22_FN, FN_GETHER_MAGIC,
++ GP_4_21_FN, FN_GETHER_MDC_A,
++ GP_4_20_FN, FN_GETHER_MDIO_A,
++ GP_4_19_FN, FN_GETHER_TXCREFCLK_MEGA,
++ GP_4_18_FN, FN_GETHER_TXCREFCLK,
++ GP_4_17_FN, FN_GETHER_TD3,
++ GP_4_16_FN, FN_GETHER_TD2,
++ GP_4_15_FN, FN_GETHER_TD1,
++ GP_4_14_FN, FN_GETHER_TD0,
++ GP_4_13_FN, FN_GETHER_TXC,
++ GP_4_12_FN, FN_GETHER_TX_CTL,
++ GP_4_11_FN, FN_GETHER_RD3,
++ GP_4_10_FN, FN_GETHER_RD2,
++ GP_4_9_FN, FN_GETHER_RD1,
++ GP_4_8_FN, FN_GETHER_RD0,
++ GP_4_7_FN, FN_GETHER_RXC,
++ GP_4_6_FN, FN_GETHER_RX_CTL,
++ GP_4_5_FN, GFN_SDA2,
++ GP_4_4_FN, GFN_SCL2,
++ GP_4_3_FN, GFN_SDA1,
++ GP_4_2_FN, GFN_SCL1,
++ GP_4_1_FN, GFN_SDA0,
++ GP_4_0_FN, GFN_SCL0 }
++ },
++ /* GPSR5 */
++ { PINMUX_CFG_REG("GPSR5", 0xE6060114, 32, 1) {
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ GP_5_14_FN, FN_RPC_INT_N,
++ GP_5_13_FN, FN_RPC_WP_N,
++ GP_5_12_FN, FN_RPC_RESET_N,
++ GP_5_11_FN, FN_QSPI1_SSL,
++ GP_5_10_FN, FN_QSPI1_IO3,
++ GP_5_9_FN, FN_QSPI1_IO2,
++ GP_5_8_FN, FN_QSPI1_MISO_IO1,
++ GP_5_7_FN, FN_QSPI1_MOSI_IO0,
++ GP_5_6_FN, FN_QSPI1_SPCLK,
++ GP_5_5_FN, FN_QSPI0_SSL,
++ GP_5_4_FN, FN_QSPI0_IO3,
++ GP_5_3_FN, FN_QSPI0_IO2,
++ GP_5_2_FN, FN_QSPI0_MISO_IO1,
++ GP_5_1_FN, FN_QSPI0_MOSI_IO0,
++ GP_5_0_FN, FN_QSPI0_SPCLK }
++ },
++
++ { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32,
++ 4, 4, 4, 4, 4, 4, 4, 4) {
++ /* IPSR0_31_28 [4] */
++ IFN_DU_DG3, FN_CPG_CPCKOUT, FN_GETHER_RMII_REFCLK, FN_A7,
++ FN_PWMFSW0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR0_27_24 [4] */
++ IFN_DU_DG2, 0, FN_GETHER_RMII_TXD1, FN_A6,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR0_23_20 [4] */
++ IFN_DU_DR7, 0, FN_GETHER_RMII_TXD0, FN_A5,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR0_19_16 [4] */
++ IFN_DU_DR6, FN_RTS4_N_TANS, FN_GETHER_RMII_TXD_EN, FN_A4,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR0_15_12 [4] */
++ IFN_DU_DR5, FN_CTS4_N, FN_GETHER_RMII_RXD1, FN_A3,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR0_11_8 [4] */
++ IFN_DU_DR4, FN_TX4, FN_GETHER_RMII_RXD0, FN_A2,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR0_7_4 [4] */
++ IFN_DU_DR3, FN_RX4, FN_GETHER_RMII_RX_ER, FN_A1,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR0_3_0 [4] */
++ IFN_DU_DR2, FN_SCK4, FN_GETHER_RMII_CRS_DV, FN_A0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ }
++ },
++ { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32,
++ 4, 4, 4, 4, 4, 4, 4, 4) {
++ /* IPSR1_31_28 [4] */
++ IFN_DU_DB5, FN_HTX0_A, FN_PWM0_A, FN_A15,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR1_27_24 [4] */
++ IFN_DU_DB4, FN_HCTS0_N_A, 0, FN_A14,
++ FN_IRQ3, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR1_23_20 [4] */
++ IFN_DU_DB3, FN_HRTS0_N_A, 0, FN_A13,
++ FN_IRQ2, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR1_19_16 [4] */
++ IFN_DU_DB2, FN_HSCK0_A, 0, FN_A12,
++ FN_IRQ1, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR1_15_12 [4] */
++ IFN_DU_DG7, FN_HRX0_A, 0, FN_A11,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR1_11_8 [4] */
++ IFN_DU_DG6, FN_SCIF_CLK_A, FN_GETHER_MDIO_B, FN_A10,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR1_7_4 [4] */
++ IFN_DU_DG5, FN_SDA5, FN_GETHER_MDC_B, FN_A9,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR1_3_0 [4] */
++ IFN_DU_DG4, FN_SCL5, 0, FN_A8,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0
++ }
++ },
++ { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32,
++ 4, 4, 4, 4, 4, 4, 4, 4) {
++ /* IPSR2_31_28 [4] */
++ IFN_VI0_CLK, FN_MSIOF2_SCK, FN_SCK3, 0,
++ FN_HSCK3, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR2_27_24 [4] */
++ IFN_IRQ0, FN_CC5_OSCOUT, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR2_23_20 [4] */
++ IFN_DU_EXODDF_DU_ODDF_DISP_CDE, FN_MSIOF3_SYNC, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR2_19_16 [4] */
++ IFN_DU_EXVSYNC_DU_VSYNC, FN_MSIOF3_SCK, 0, 0,
++ FN_FXR_TXENB_N, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR2_15_12 [4] */
++ IFN_DU_EXHSYNC_DU_HSYNC, FN_MSIOF3_SS2, FN_GETHER_PHY_INT_B, FN_A19,
++ FN_FXR_TXENA_N, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR2_11_8 [4] */
++ IFN_DU_DOTCLKOUT, FN_MSIOF3_SS1, FN_GETHER_LINK_B, FN_A18,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR2_7_4 [4] */
++ IFN_DU_DB7, FN_MSIOF3_TXD, 0, FN_A17,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR2_3_0 [4] */
++ IFN_DU_DB6, FN_MSIOF3_RXD, 0, FN_A16,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ }
++ },
++ { PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32,
++ 4, 4, 4, 4, 4, 4, 4, 4) {
++ /* IPSR3_31_28 [4] */
++ IFN_VI0_DATA4, FN_HRTS1_N, FN_RX1_A, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR3_27_24 [4] */
++ IFN_VI0_DATA3, FN_HSCK1, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR3_23_20 [4] */
++ IFN_VI0_DATA2, FN_AVB0_AVTP_PPS, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR3_19_16 [4] */
++ IFN_VI0_DATA1, FN_MSIOF2_SS2, FN_SCK1, 0,
++ FN_SPEEDIN_A, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR3_15_12 [4] */
++ IFN_VI0_DATA0, FN_MSIOF2_SS1, FN_RTS3_N_TANS, 0,
++ FN_HRX3, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR3_11_8 [4] */
++ IFN_VI0_VSYNC_N, FN_MSIOF2_SYNC, FN_CTS3_N, 0,
++ FN_HTX3, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR3_7_4 [4] */
++ IFN_VI0_HSYNC_N, FN_MSIOF2_TXD, FN_TX3, 0,
++ FN_HRTS3_N, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR3_3_0 [4] */
++ IFN_VI0_CLKENB, FN_MSIOF2_RXD, FN_RX3, FN_RD_WR_N,
++ FN_HCTS3_N, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ }
++ },
++ { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32,
++ 4, 4, 4, 4, 4, 4, 4, 4) {
++ /* IPSR4_31_28 [4] */
++ IFN_VI0_FIELD, FN_HRX2, FN_PWM4_A, FN_CS1_N,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR4_27_24 [4] */
++ IFN_VI0_DATA11, FN_HTX2, FN_PWM3_A, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR4_23_20 [4] */
++ IFN_VI0_DATA10, FN_HRTS2_N, FN_PWM2_A, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR4_19_16 [4] */
++ IFN_VI0_DATA9, FN_HCTS2_N, FN_PWM1_A, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR4_15_12 [4] */
++ IFN_VI0_DATA8, FN_HSCK2, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR4_11_8 [4] */
++ IFN_VI0_DATA7, FN_HRX1, FN_RTS1_N_TANS, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR4_7_4 [4] */
++ IFN_VI0_DATA6, FN_HTX1, FN_CTS1_N, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR4_3_0 [4] */
++ IFN_VI0_DATA5, FN_HCTS1_N, FN_TX1_A, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ }
++ },
++ { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32,
++ 4, 4, 4, 4, 4, 4, 4, 4) {
++ /* IPSR5_31_28 [4] */
++ IFN_VI1_DATA3, FN_CANFD0_RX_B, 0, FN_D6,
++ FN_MMC_CMD, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR5_27_24 [4] */
++ IFN_VI1_DATA2, FN_CANFD0_TX_B, 0, FN_D5,
++ FN_MMC_DS, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR5_23_20 [4] */
++ IFN_VI1_DATA1, FN_MSIOF1_SS2, 0, FN_D4,
++ FN_MMC_CD, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR5_19_16 [4] */
++ IFN_VI1_DATA0, FN_MSIOF1_SS1, 0, FN_D3,
++ FN_MMC_WP, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR5_15_12 [4] */
++ IFN_VI1_VSYNC_N, FN_MSIOF1_SYNC, 0, FN_D2,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR5_11_8 [4] */
++ IFN_VI1_HSYNC_N, FN_MSIOF1_SCK, 0, FN_D1,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR5_7_4 [4] */
++ IFN_VI1_CLKENB, FN_MSIOF1_TXD, 0, FN_D0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR5_3_0 [4] */
++ IFN_VI1_CLK, FN_MSIOF1_RXD, 0, FN_CS0_N,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ }
++ },
++ { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32,
++ 4, 4, 4, 4, 4, 4, 4, 4) {
++ /* IPSR6_31_28 [4] */
++ IFN_VI1_DATA11, FN_SCL4, 0, FN_D14,
++ FN_MMC_D6, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR6_27_24 [4] */
++ IFN_VI1_DATA10, FN_TCLK2_A, 0, FN_D13,
++ FN_MMC_D5, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR6_23_20 [4] */
++ IFN_VI1_DATA9, FN_TCLK1_A, 0, FN_D12,
++ FN_MMC_D4, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR6_19_16 [4] */
++ IFN_VI1_DATA8, 0, 0, FN_D11,
++ FN_MMC_CLK, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR6_15_12 [4] */
++ IFN_VI1_DATA7, 0, 0, FN_D10,
++ FN_MMC_D3, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR6_11_8 [4] */
++ IFN_VI1_DATA6, 0, 0, FN_D9,
++ FN_MMC_D2, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR6_7_4 [4] */
++ IFN_VI1_DATA5, 0, 0, FN_D8,
++ FN_MMC_D1, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR6_3_0 [4] */
++ IFN_VI1_DATA4, FN_CANFD_CLK_B, 0, FN_D7,
++ FN_MMC_D0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ }
++ },
++ { PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32,
++ 4, 4, 4, 4, 4, 4, 4, 4) {
++ /* IPSR7_31_28 [4] */
++ IFN_AVB0_AVTP_MATCH, FN_TPU0TO0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR7_27_24 [4] */
++ IFN_SDA2, 0, 0, FN_EX_WAIT0,
++ FN_TX0, FN_HTX0_B, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR7_23_20 [4] */
++ IFN_SCL2, 0, 0, FN_WE1_N,
++ FN_RX0, FN_HRX0_B, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR7_19_16 [4] */
++ IFN_SDA1, 0, FN_TPU0TO3, FN_WE0_N,
++ FN_RTS0_N_TANS, FN_HRTS0_N_B, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR7_15_12 [4] */
++ IFN_SCL1, 0, FN_TPU0TO2, FN_RD_N,
++ FN_CTS0_N, FN_HCTS0_N_B, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR7_11_8 [4] */
++ IFN_SDA0, 0, 0, FN_BS_N,
++ FN_SCK0, FN_HSCK0_B, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR7_7_4 [4] */
++ IFN_SCL0, 0, 0, FN_CLKOUT,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR7_3_0 [4] */
++ IFN_VI1_FIELD, FN_SDA4, 0, FN_D15,
++ FN_MMC_D7, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ }
++ },
++ { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32,
++ 4, 4, 4, 4, 4, 4, 4, 4) {
++ /* IPSR8_31_28 [4] */
++ IFN_DIGRF_CLKOUT, FN_DIGRF_CLKEN_OUT, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR8_27_24 [4] */
++ IFN_DIGRF_CLKIN, FN_DIGRF_CLKEN_IN, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR8_23_20 [4] */
++ IFN_CANFD_CLK_A, FN_CLK_EXTFXR, FN_PWM4_B, FN_SPEEDIN_B,
++ FN_SCIF_CLK_B, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR8_19_16 [4] */
++ IFN_CANFD1_RX, FN_RXDB_EXTFXR, FN_PWM3_B, FN_TCLK2_B,
++ FN_RX1_B, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR8_15_12 [4] */
++ IFN_CANFD1_TX, FN_FXR_TXDB, FN_PWM2_B, FN_TCLK1_B,
++ FN_TX1_B, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR8_11_8 [4] */
++ IFN_CANFD0_RX_A, FN_RXDA_EXTFXR, FN_PWM1_B, FN_DU_CDE,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR8_7_4 [4] */
++ IFN_CANFD0_TX_A, FN_FXR_TXDA, FN_PWM0_B, FN_DU_DISP,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR8_3_0 [4] */
++ IFN_AVB0_AVTP_CAPTURE, FN_TPU0TO1, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ }
++ },
++ { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32,
++ 4, 4, 4, 4, 4, 4, 4, 4) {
++ /* IPSR9_31_28 [4] */
++ IFN_MSIOF0_SS2, FN_DU_DB1, FN_TCLK4, FN_VI0_DATA19,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR9_27_24 [4] */
++ IFN_MSIOF0_SS1, FN_DU_DB0, FN_TCLK3, FN_VI0_DATA18,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR9_23_20 [4] */
++ IFN_MSIOF0_SYNC, FN_DU_DG1, 0, FN_VI0_DATA17,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR9_19_16 [4] */
++ IFN_MSIOF0_SCK, FN_DU_DG0, 0, FN_VI0_DATA16,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR9_15_12 [4] */
++ IFN_MSIOF0_TXD, FN_DU_DR1, 0, FN_VI0_DATA15,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR9_11_8 [4] */
++ IFN_MSIOF0_RXD, FN_DU_DR0, 0, FN_VI0_DATA14,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR9_7_4 [4] */
++ IFN_IRQ5, 0, 0, FN_VI0_DATA13,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR9_3_0 [4] */
++ IFN_IRQ4, 0, 0, FN_VI0_DATA12,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ }
++ },
++ { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060228, 32,
++ 4, 4, 4, 4, 4, 4, 4, 4) {
++ /* IPSR10_31_28 [4] */
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR10_27_24 [4] */
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR10_23_20 [4] */
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR10_19_16 [4] */
++ IFN_FSO_TOE_N, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR10_15_12 [4] */
++ IFN_FSO_CFE_1_N, 0, 0, FN_VI0_DATA23,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR10_11_8 [4] */
++ IFN_FSO_CFE_0_N, 0, 0, FN_VI0_DATA22,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR10_7_4 [4] */
++ IFN_SDA3, 0, 0, FN_VI0_DATA21,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ /* IPSR10_3_0 [4] */
++ IFN_SCL3, 0, 0, FN_VI0_DATA20,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ 0, 0, 0, 0,
++ }
++ },
++ { PINMUX_CFG_REG("MOD_SEL0", 0xE6060500, 32, 1) {
++ /* reserved [31..24] */
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ /* reserved [23..16] */
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ /* reserved [15..11] */
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ /* SEL_CANFD0 [1] */
++ FN_SEL_CANFD0_0,
++ FN_SEL_CANFD0_1,
++ /* SEL_GETHER [1] */
++ FN_SEL_GETHER_0,
++ FN_SEL_GETHER_1,
++ /* SEL_HSCIF0 [1] */
++ FN_SEL_HSCIF0_0,
++ FN_SEL_HSCIF0_1,
++ /* SEL_PWM4 [1] */
++ FN_SEL_PWM0_0,
++ FN_SEL_PWM0_1,
++ /* SEL_PWM3 [1] */
++ FN_SEL_PWM1_0,
++ FN_SEL_PWM1_1,
++ /* SEL_PWM2 [1] */
++ FN_SEL_PWM2_0,
++ FN_SEL_PWM2_1,
++ /* SEL_PWM1 [1] */
++ FN_SEL_PWM3_0,
++ FN_SEL_PWM3_1,
++ /* SEL_PWM0 [1] */
++ FN_SEL_PWM4_0,
++ FN_SEL_PWM4_1,
++ 0, 0,
++ /* SEL_RSP [1] */
++ FN_SEL_RSP_0,
++ FN_SEL_RSP_1,
++ /* SEL_SCIF1 [1] */
++ FN_SEL_SCIF1_0,
++ FN_SEL_SCIF1_1,
++ /* SEL_TMU [1] */
++ FN_SEL_TMU_0,
++ FN_SEL_TMU_1,
++ }
++ },
++
++ /* under construction */
++ { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) {
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ GP_0_21_IN, GP_0_21_OUT,
++ GP_0_20_IN, GP_0_20_OUT,
++ GP_0_19_IN, GP_0_19_OUT,
++ GP_0_18_IN, GP_0_18_OUT,
++ GP_0_17_IN, GP_0_17_OUT,
++ GP_0_16_IN, GP_0_16_OUT,
++ GP_0_15_IN, GP_0_15_OUT,
++ GP_0_14_IN, GP_0_14_OUT,
++ GP_0_13_IN, GP_0_13_OUT,
++ GP_0_12_IN, GP_0_12_OUT,
++ GP_0_11_IN, GP_0_11_OUT,
++ GP_0_10_IN, GP_0_10_OUT,
++ GP_0_9_IN, GP_0_9_OUT,
++ GP_0_8_IN, GP_0_8_OUT,
++ GP_0_7_IN, GP_0_7_OUT,
++ GP_0_6_IN, GP_0_6_OUT,
++ GP_0_5_IN, GP_0_5_OUT,
++ GP_0_4_IN, GP_0_4_OUT,
++ GP_0_3_IN, GP_0_3_OUT,
++ GP_0_2_IN, GP_0_2_OUT,
++ GP_0_1_IN, GP_0_1_OUT,
++ GP_0_0_IN, GP_0_0_OUT,
++ }
++ },
++ { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ GP_1_27_IN, GP_1_27_OUT,
++ GP_1_26_IN, GP_1_26_OUT,
++ GP_1_25_IN, GP_1_25_OUT,
++ GP_1_24_IN, GP_1_24_OUT,
++ GP_1_23_IN, GP_1_23_OUT,
++ GP_1_22_IN, GP_1_22_OUT,
++ GP_1_21_IN, GP_1_21_OUT,
++ GP_1_20_IN, GP_1_20_OUT,
++ GP_1_19_IN, GP_1_19_OUT,
++ GP_1_18_IN, GP_1_18_OUT,
++ GP_1_17_IN, GP_1_17_OUT,
++ GP_1_16_IN, GP_1_16_OUT,
++ GP_1_15_IN, GP_1_15_OUT,
++ GP_1_14_IN, GP_1_14_OUT,
++ GP_1_13_IN, GP_1_13_OUT,
++ GP_1_12_IN, GP_1_12_OUT,
++ GP_1_11_IN, GP_1_11_OUT,
++ GP_1_10_IN, GP_1_10_OUT,
++ GP_1_9_IN, GP_1_9_OUT,
++ GP_1_8_IN, GP_1_8_OUT,
++ GP_1_7_IN, GP_1_7_OUT,
++ GP_1_6_IN, GP_1_6_OUT,
++ GP_1_5_IN, GP_1_5_OUT,
++ GP_1_4_IN, GP_1_4_OUT,
++ GP_1_3_IN, GP_1_3_OUT,
++ GP_1_2_IN, GP_1_2_OUT,
++ GP_1_1_IN, GP_1_1_OUT,
++ GP_1_0_IN, GP_1_0_OUT,
++ }
++ },
++ { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) {
++ 0, 0,
++ 0, 0,
++ GP_2_29_IN, GP_2_29_OUT,
++ GP_2_28_IN, GP_2_28_OUT,
++ GP_2_27_IN, GP_2_27_OUT,
++ GP_2_26_IN, GP_2_26_OUT,
++ GP_2_25_IN, GP_2_25_OUT,
++ GP_2_24_IN, GP_2_24_OUT,
++ GP_2_23_IN, GP_2_23_OUT,
++ GP_2_22_IN, GP_2_22_OUT,
++ GP_2_21_IN, GP_2_21_OUT,
++ GP_2_20_IN, GP_2_20_OUT,
++ GP_2_19_IN, GP_2_19_OUT,
++ GP_2_18_IN, GP_2_18_OUT,
++ GP_2_17_IN, GP_2_17_OUT,
++ GP_2_16_IN, GP_2_16_OUT,
++ GP_2_15_IN, GP_2_15_OUT,
++ GP_2_14_IN, GP_2_14_OUT,
++ GP_2_13_IN, GP_2_13_OUT,
++ GP_2_12_IN, GP_2_12_OUT,
++ GP_2_11_IN, GP_2_11_OUT,
++ GP_2_10_IN, GP_2_10_OUT,
++ GP_2_9_IN, GP_2_9_OUT,
++ GP_2_8_IN, GP_2_8_OUT,
++ GP_2_7_IN, GP_2_7_OUT,
++ GP_2_6_IN, GP_2_6_OUT,
++ GP_2_5_IN, GP_2_5_OUT,
++ GP_2_4_IN, GP_2_4_OUT,
++ GP_2_3_IN, GP_2_3_OUT,
++ GP_2_2_IN, GP_2_2_OUT,
++ GP_2_1_IN, GP_2_1_OUT,
++ GP_2_0_IN, GP_2_0_OUT,
++ }
++ },
++ { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) {
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ GP_3_16_IN, GP_3_16_OUT,
++ GP_3_15_IN, GP_3_15_OUT,
++ GP_3_14_IN, GP_3_14_OUT,
++ GP_3_13_IN, GP_3_13_OUT,
++ GP_3_12_IN, GP_3_12_OUT,
++ GP_3_11_IN, GP_3_11_OUT,
++ GP_3_10_IN, GP_3_10_OUT,
++ GP_3_9_IN, GP_3_9_OUT,
++ GP_3_8_IN, GP_3_8_OUT,
++ GP_3_7_IN, GP_3_7_OUT,
++ GP_3_6_IN, GP_3_6_OUT,
++ GP_3_5_IN, GP_3_5_OUT,
++ GP_3_4_IN, GP_3_4_OUT,
++ GP_3_3_IN, GP_3_3_OUT,
++ GP_3_2_IN, GP_3_2_OUT,
++ GP_3_1_IN, GP_3_1_OUT,
++ GP_3_0_IN, GP_3_0_OUT,
++ }
++ },
++ { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) {
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ GP_4_24_IN, GP_4_24_OUT,
++ GP_4_23_IN, GP_4_23_OUT,
++ GP_4_22_IN, GP_4_22_OUT,
++ GP_4_21_IN, GP_4_21_OUT,
++ GP_4_20_IN, GP_4_20_OUT,
++ GP_4_19_IN, GP_4_19_OUT,
++ GP_4_18_IN, GP_4_18_OUT,
++ GP_4_17_IN, GP_4_17_OUT,
++ GP_4_16_IN, GP_4_16_OUT,
++ GP_4_15_IN, GP_4_15_OUT,
++ GP_4_14_IN, GP_4_14_OUT,
++ GP_4_13_IN, GP_4_13_OUT,
++ GP_4_12_IN, GP_4_12_OUT,
++ GP_4_11_IN, GP_4_11_OUT,
++ GP_4_10_IN, GP_4_10_OUT,
++ GP_4_9_IN, GP_4_9_OUT,
++ GP_4_8_IN, GP_4_8_OUT,
++ GP_4_7_IN, GP_4_7_OUT,
++ GP_4_6_IN, GP_4_6_OUT,
++ GP_4_5_IN, GP_4_5_OUT,
++ GP_4_4_IN, GP_4_4_OUT,
++ GP_4_3_IN, GP_4_3_OUT,
++ GP_4_2_IN, GP_4_2_OUT,
++ GP_4_1_IN, GP_4_1_OUT,
++ GP_4_0_IN, GP_4_0_OUT,
++ }
++ },
++ { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) {
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++ 0, 0,
++
++ 0, 0,
++ GP_5_14_IN, GP_5_14_OUT,
++ GP_5_13_IN, GP_5_13_OUT,
++ GP_5_12_IN, GP_5_12_OUT,
++ GP_5_11_IN, GP_5_11_OUT,
++ GP_5_10_IN, GP_5_10_OUT,
++ GP_5_9_IN, GP_5_9_OUT,
++ GP_5_8_IN, GP_5_8_OUT,
++ GP_5_7_IN, GP_5_7_OUT,
++ GP_5_6_IN, GP_5_6_OUT,
++ GP_5_5_IN, GP_5_5_OUT,
++ GP_5_4_IN, GP_5_4_OUT,
++ GP_5_3_IN, GP_5_3_OUT,
++ GP_5_2_IN, GP_5_2_OUT,
++ GP_5_1_IN, GP_5_1_OUT,
++ GP_5_0_IN, GP_5_0_OUT,
++ }
++ },
++ { },
++ { },
++ { },
++};
++
++static struct pinmux_data_reg pinmux_data_regs[] = {
++ /* use OUTDT registers? */
++ { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) {
++ 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, GP_0_21_DATA, GP_0_20_DATA,
++ GP_0_19_DATA, GP_0_18_DATA, GP_0_17_DATA, GP_0_16_DATA,
++ GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA,
++ GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA,
++ GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA,
++ GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA }
++ },
++ { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
++ 0, 0, 0, 0,
++ GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,
++ GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
++ GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
++ GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
++ GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
++ GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
++ GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
++ },
++ { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) {
++ 0, 0, GP_2_29_DATA, GP_2_28_DATA,
++ GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA,
++ GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA,
++ GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA,
++ GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA,
++ GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA,
++ GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA,
++ GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA }
++ },
++ { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) {
++ 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, GP_3_16_DATA,
++ GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA,
++ GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA,
++ GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA,
++ GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA }
++ },
++ { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) {
++ 0, 0, 0, 0, 0, 0, 0, GP_4_24_DATA,
++ GP_4_23_DATA, GP_4_22_DATA, GP_4_21_DATA, GP_4_20_DATA,
++ GP_4_19_DATA, GP_4_18_DATA, GP_4_17_DATA, GP_4_16_DATA,
++ GP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA,
++ GP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA,
++ GP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA,
++ GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA }
++ },
++ { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) {
++ 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,
++ GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
++ GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
++ GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
++ },
++ { },
++ { },
++ { },
++};
++
++static struct pinmux_info r8a7798_pinmux_info = {
++ .name = "r8a7798_pfc",
++
++ .unlock_reg = 0xe6060000, /* PMMR */
++
++ .reserved_id = PINMUX_RESERVED,
++ .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
++ .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
++ .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
++ .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
++ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
++
++ .first_gpio = GPIO_GP_0_0,
++ .last_gpio = GPIO_IFN_FSO_TOE_N,
++
++ .gpios = pinmux_gpios,
++ .cfg_regs = pinmux_config_regs,
++ .data_regs = pinmux_data_regs,
++
++ .gpio_data = pinmux_data,
++ .gpio_data_size = ARRAY_SIZE(pinmux_data),
++};
++
++void r8a7798_pinmux_init(void)
++{
++ register_pinmux(&r8a7798_pinmux_info);
++}
+diff --git a/arch/arm/cpu/armv8/rcar_gen3/pfc.c b/arch/arm/cpu/armv8/rcar_gen3/pfc.c
+index bd3aa0a..72c5482 100644
+--- a/arch/arm/cpu/armv8/rcar_gen3/pfc.c
++++ b/arch/arm/cpu/armv8/rcar_gen3/pfc.c
+@@ -22,5 +22,7 @@ void pinmux_init(void)
+ r8a7796_pinmux_init();
+ #elif defined(CONFIG_R8A7797)
+ r8a7797_pinmux_init();
++#elif defined(CONFIG_R8A7798)
++ r8a7798_pinmux_init();
+ #endif
+ }
+diff --git a/arch/arm/include/asm/arch-rcar_gen3/gpio.h b/arch/arm/include/asm/arch-rcar_gen3/gpio.h
+index fb8b758..cc94b5c 100644
+--- a/arch/arm/include/asm/arch-rcar_gen3/gpio.h
++++ b/arch/arm/include/asm/arch-rcar_gen3/gpio.h
+@@ -18,6 +18,8 @@
+ #include <asm/arch/r8a7796-gpio.h>
+ #elif defined(CONFIG_R8A7797)
+ #include <asm/arch/r8a7797-gpio.h>
++#elif defined(CONFIG_R8A7798)
++#include <asm/arch/r8a7798-gpio.h>
+ #endif
+
+ #if defined(CONFIG_R8A7795)
+@@ -27,6 +29,8 @@ void r8a7795_es_pinmux_init(void);
+ void r8a7796_pinmux_init(void);
+ #elif defined(CONFIG_R8A7797)
+ void r8a7797_pinmux_init(void);
++#elif defined(CONFIG_R8A7798)
++void r8a7798_pinmux_init(void);
+ #endif
+ void pinmux_init(void);
+
+diff --git a/arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h b/arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h
+new file mode 100644
+index 0000000..8d2252f
+--- /dev/null
++++ b/arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h
+@@ -0,0 +1,522 @@
++/*
++ * arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h
++ * This file defines pin function control of gpio.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++#ifndef __ASM_R8A7798_GPIO_H__
++#define __ASM_R8A7798_GPIO_H__
++
++/* Pin Function Controller:
++ * GPIO_FN_xx - GPIO used to select pin function
++ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
++ */
++enum {
++ GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
++ GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
++ GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
++ GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
++ GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
++ GPIO_GP_0_20, GPIO_GP_0_21,
++
++ GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
++ GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
++ GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
++ GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
++ GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
++ GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
++ GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
++
++ GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
++ GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
++ GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
++ GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
++ GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
++ GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
++ GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
++ GPIO_GP_2_28, GPIO_GP_2_29,
++
++ GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
++ GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
++ GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
++ GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
++ GPIO_GP_3_16,
++
++ GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
++ GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
++ GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
++ GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
++ GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
++ GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
++ GPIO_GP_4_24,
++
++ GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
++ GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
++ GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
++ GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14,
++
++ /* GPSR0 */
++ GPIO_GFN_DU_EXODDF_DU_ODDF_DISP_CDE,
++ GPIO_GFN_DU_EXVSYNC_DU_VSYNC,
++ GPIO_GFN_DU_EXHSYNC_DU_HSYNC,
++ GPIO_GFN_DU_DOTCLKOUT,
++ GPIO_GFN_DU_DB7,
++ GPIO_GFN_DU_DB6,
++ GPIO_GFN_DU_DB5,
++ GPIO_GFN_DU_DB4,
++ GPIO_GFN_DU_DB3,
++ GPIO_GFN_DU_DB2,
++ GPIO_GFN_DU_DG7,
++ GPIO_GFN_DU_DG6,
++ GPIO_GFN_DU_DG5,
++ GPIO_GFN_DU_DG4,
++ GPIO_GFN_DU_DG3,
++ GPIO_GFN_DU_DG2,
++ GPIO_GFN_DU_DR7,
++ GPIO_GFN_DU_DR6,
++ GPIO_GFN_DU_DR5,
++ GPIO_GFN_DU_DR4,
++ GPIO_GFN_DU_DR3,
++ GPIO_GFN_DU_DR2,
++
++ /* GPSR1 */
++ GPIO_GFN_DIGRF_CLKOUT,
++ GPIO_GFN_DIGRF_CLKIN,
++ GPIO_GFN_CANFD_CLK_A,
++ GPIO_GFN_CANFD1_RX,
++ GPIO_GFN_CANFD1_TX,
++ GPIO_GFN_CANFD0_RX_A,
++ GPIO_GFN_CANFD0_TX_A,
++ GPIO_GFN_AVB0_AVTP_CAPTURE,
++ GPIO_GFN_AVB0_AVTP_MATCH,
++ GPIO_FN_AVB0_LINK,
++ GPIO_FN_AVB0_PHY_INT,
++ GPIO_FN_AVB0_MAGIC,
++ GPIO_FN_AVB0_MDC,
++ GPIO_FN_AVB0_MDIO,
++ GPIO_FN_AVB0_TXCREFCLK,
++ GPIO_FN_AVB0_TD3,
++ GPIO_FN_AVB0_TD2,
++ GPIO_FN_AVB0_TD1,
++ GPIO_FN_AVB0_TD0,
++ GPIO_FN_AVB0_TXC,
++ GPIO_FN_AVB0_TX_CTL,
++ GPIO_FN_AVB0_RD3,
++ GPIO_FN_AVB0_RD2,
++ GPIO_FN_AVB0_RD1,
++ GPIO_FN_AVB0_RD0,
++ GPIO_FN_AVB0_RXC,
++ GPIO_FN_AVB0_RX_CTL,
++ GPIO_GFN_IRQ0,
++
++ /* GPSR2 */
++ GPIO_GFN_FSO_TOE_N,
++ GPIO_GFN_FSO_CFE_1_N,
++ GPIO_GFN_FSO_CFE_0_N,
++ GPIO_GFN_SDA3,
++ GPIO_GFN_SCL3,
++ GPIO_GFN_MSIOF0_SS2,
++ GPIO_GFN_MSIOF0_SS1,
++ GPIO_GFN_MSIOF0_SYNC,
++ GPIO_GFN_MSIOF0_SCK,
++ GPIO_GFN_MSIOF0_TXD,
++ GPIO_GFN_MSIOF0_RXD,
++ GPIO_GFN_IRQ5,
++ GPIO_GFN_IRQ4,
++ GPIO_GFN_VI0_FIELD,
++ GPIO_GFN_VI0_DATA11,
++ GPIO_GFN_VI0_DATA10,
++ GPIO_GFN_VI0_DATA9,
++ GPIO_GFN_VI0_DATA8,
++ GPIO_GFN_VI0_DATA7,
++ GPIO_GFN_VI0_DATA6,
++ GPIO_GFN_VI0_DATA5,
++ GPIO_GFN_VI0_DATA4,
++ GPIO_GFN_VI0_DATA3,
++ GPIO_GFN_VI0_DATA2,
++ GPIO_GFN_VI0_DATA1,
++ GPIO_GFN_VI0_DATA0,
++ GPIO_GFN_VI0_VSYNC_N,
++ GPIO_GFN_VI0_HSYNC_N,
++ GPIO_GFN_VI0_CLKENB,
++ GPIO_GFN_VI0_CLK,
++
++ /* GPSR3 */
++ GPIO_GFN_VI1_FIELD,
++ GPIO_GFN_VI1_DATA11,
++ GPIO_GFN_VI1_DATA10,
++ GPIO_GFN_VI1_DATA9,
++ GPIO_GFN_VI1_DATA8,
++ GPIO_GFN_VI1_DATA7,
++ GPIO_GFN_VI1_DATA6,
++ GPIO_GFN_VI1_DATA5,
++ GPIO_GFN_VI1_DATA4,
++ GPIO_GFN_VI1_DATA3,
++ GPIO_GFN_VI1_DATA2,
++ GPIO_GFN_VI1_DATA1,
++ GPIO_GFN_VI1_DATA0,
++ GPIO_GFN_VI1_VSYNC_N,
++ GPIO_GFN_VI1_HSYNC_N,
++ GPIO_GFN_VI1_CLKENB,
++ GPIO_GFN_VI1_CLK,
++
++ /* GPSR4 */
++ GPIO_FN_GETHER_LINK_A,
++ GPIO_FN_GETHER_PHY_INT_A,
++ GPIO_FN_GETHER_MAGIC,
++ GPIO_FN_GETHER_MDC_A,
++ GPIO_FN_GETHER_MDIO_A,
++ GPIO_FN_GETHER_TXCREFCLK_MEGA,
++ GPIO_FN_GETHER_TXCREFCLK,
++ GPIO_FN_GETHER_TD3,
++ GPIO_FN_GETHER_TD2,
++ GPIO_FN_GETHER_TD1,
++ GPIO_FN_GETHER_TD0,
++ GPIO_FN_GETHER_TXC,
++ GPIO_FN_GETHER_TX_CTL,
++ GPIO_FN_GETHER_RD3,
++ GPIO_FN_GETHER_RD2,
++ GPIO_FN_GETHER_RD1,
++ GPIO_FN_GETHER_RD0,
++ GPIO_FN_GETHER_RXC,
++ GPIO_FN_GETHER_RX_CTL,
++ GPIO_GFN_SDA2,
++ GPIO_GFN_SCL2,
++ GPIO_GFN_SDA1,
++ GPIO_GFN_SCL1,
++ GPIO_GFN_SDA0,
++ GPIO_GFN_SCL0,
++
++ /* GPSR5 */
++ GPIO_FN_RPC_INT_N,
++ GPIO_FN_RPC_WP_N,
++ GPIO_FN_RPC_RESET_N,
++ GPIO_FN_QSPI1_SSL,
++ GPIO_FN_QSPI1_IO3,
++ GPIO_FN_QSPI1_IO2,
++ GPIO_FN_QSPI1_MISO_IO1,
++ GPIO_FN_QSPI1_MOSI_IO0,
++ GPIO_FN_QSPI1_SPCLK,
++ GPIO_FN_QSPI0_SSL,
++ GPIO_FN_QSPI0_IO3,
++ GPIO_FN_QSPI0_IO2,
++ GPIO_FN_QSPI0_MISO_IO1,
++ GPIO_FN_QSPI0_MOSI_IO0,
++ GPIO_FN_QSPI0_SPCLK,
++
++ /* IPSR0 */
++ GPIO_IFN_DU_DR2,
++ GPIO_FN_SCK4,
++ GPIO_FN_GETHER_RMII_CRS_DV,
++ GPIO_FN_A0,
++ GPIO_IFN_DU_DR3,
++ GPIO_FN_RX4,
++ GPIO_FN_GETHER_RMII_RX_ER,
++ GPIO_FN_A1,
++ GPIO_IFN_DU_DR4,
++ GPIO_FN_TX4,
++ GPIO_FN_GETHER_RMII_RXD0,
++ GPIO_FN_A2,
++ GPIO_IFN_DU_DR5,
++ GPIO_FN_CTS4_N,
++ GPIO_FN_GETHER_RMII_RXD1,
++ GPIO_FN_A3,
++ GPIO_IFN_DU_DR6,
++ GPIO_FN_RTS4_N_TANS,
++ GPIO_FN_GETHER_RMII_TXD_EN,
++ GPIO_FN_A4,
++ GPIO_IFN_DU_DR7,
++ GPIO_FN_GETHER_RMII_TXD0,
++ GPIO_FN_A5,
++ GPIO_IFN_DU_DG2,
++ GPIO_FN_GETHER_RMII_TXD1,
++ GPIO_FN_A6,
++ GPIO_IFN_DU_DG3,
++ GPIO_FN_CPG_CPCKOUT,
++ GPIO_FN_GETHER_RMII_REFCLK,
++ GPIO_FN_A7,
++ GPIO_FN_PWMFSW0,
++
++ /* IPSR1 */
++ GPIO_IFN_DU_DG4,
++ GPIO_FN_SCL5,
++ GPIO_FN_A8,
++ GPIO_IFN_DU_DG5,
++ GPIO_FN_SDA5,
++ GPIO_FN_GETHER_MDC_B,
++ GPIO_FN_A9,
++ GPIO_IFN_DU_DG6,
++ GPIO_FN_SCIF_CLK_A,
++ GPIO_FN_GETHER_MDIO_B,
++ GPIO_FN_A10,
++ GPIO_IFN_DU_DG7,
++ GPIO_FN_HRX0_A,
++ GPIO_FN_A11,
++ GPIO_IFN_DU_DB2,
++ GPIO_FN_HSCK0_A,
++ GPIO_FN_A12,
++ GPIO_FN_IRQ1,
++ GPIO_IFN_DU_DB3,
++ GPIO_FN_HRTS0_N_A,
++ GPIO_FN_A13,
++ GPIO_FN_IRQ2,
++ GPIO_IFN_DU_DB4,
++ GPIO_FN_HCTS0_N_A,
++ GPIO_FN_A14,
++ GPIO_FN_IRQ3,
++ GPIO_IFN_DU_DB5,
++ GPIO_FN_HTX0_A,
++ GPIO_FN_PWM0_A,
++ GPIO_FN_A15,
++
++ /* IPSR2 */
++ GPIO_IFN_DU_DB6,
++ GPIO_FN_MSIOF3_RXD,
++ GPIO_FN_A16,
++ GPIO_IFN_DU_DB7,
++ GPIO_FN_MSIOF3_TXD,
++ GPIO_FN_A17,
++ GPIO_IFN_DU_DOTCLKOUT,
++ GPIO_FN_MSIOF3_SS1,
++ GPIO_FN_GETHER_LINK_B,
++ GPIO_FN_A18,
++ GPIO_IFN_DU_EXHSYNC_DU_HSYNC,
++ GPIO_FN_MSIOF3_SS2,
++ GPIO_FN_GETHER_PHY_INT_B,
++ GPIO_FN_A19,
++ GPIO_FN_FXR_TXENA_N,
++ GPIO_IFN_DU_EXVSYNC_DU_VSYNC,
++ GPIO_FN_MSIOF3_SCK,
++ GPIO_FN_FXR_TXENB_N,
++ GPIO_IFN_DU_EXODDF_DU_ODDF_DISP_CDE,
++ GPIO_FN_MSIOF3_SYNC,
++ GPIO_IFN_IRQ0,
++ GPIO_FN_CC5_OSCOUT,
++ GPIO_IFN_VI0_CLK,
++ GPIO_FN_MSIOF2_SCK,
++ GPIO_FN_SCK3,
++ GPIO_FN_HSCK3,
++
++ /* IPSR3 */
++ GPIO_IFN_VI0_CLKENB,
++ GPIO_FN_MSIOF2_RXD,
++ GPIO_FN_RX3,
++ GPIO_FN_RD_WR_N,
++ GPIO_FN_HCTS3_N,
++ GPIO_IFN_VI0_HSYNC_N,
++ GPIO_FN_MSIOF2_TXD,
++ GPIO_FN_TX3,
++ GPIO_FN_HRTS3_N,
++ GPIO_IFN_VI0_VSYNC_N,
++ GPIO_FN_MSIOF2_SYNC,
++ GPIO_FN_CTS3_N,
++ GPIO_FN_HTX3,
++ GPIO_IFN_VI0_DATA0,
++ GPIO_FN_MSIOF2_SS1,
++ GPIO_FN_RTS3_N_TANS,
++ GPIO_FN_HRX3,
++ GPIO_IFN_VI0_DATA1,
++ GPIO_FN_MSIOF2_SS2,
++ GPIO_FN_SCK1,
++ GPIO_FN_SPEEDIN_A,
++ GPIO_IFN_VI0_DATA2,
++ GPIO_FN_AVB0_AVTP_PPS,
++ GPIO_IFN_VI0_DATA3,
++ GPIO_FN_HSCK1,
++ GPIO_IFN_VI0_DATA4,
++ GPIO_FN_HRTS1_N,
++ GPIO_FN_RX1_A,
++
++ /* IPSR4 */
++ GPIO_IFN_VI0_DATA5,
++ GPIO_FN_HCTS1_N,
++ GPIO_FN_TX1_A,
++ GPIO_IFN_VI0_DATA6,
++ GPIO_FN_HTX1,
++ GPIO_FN_CTS1_N,
++ GPIO_IFN_VI0_DATA7,
++ GPIO_FN_HRX1,
++ GPIO_FN_RTS1_N_TANS,
++ GPIO_IFN_VI0_DATA8,
++ GPIO_FN_HSCK2,
++ GPIO_IFN_VI0_DATA9,
++ GPIO_FN_HCTS2_N,
++ GPIO_FN_PWM1_A,
++ GPIO_FN_FSO_CFE_0_N_B,
++ GPIO_IFN_VI0_DATA10,
++ GPIO_FN_HRTS2_N,
++ GPIO_FN_PWM2_A,
++ GPIO_IFN_VI0_DATA11,
++ GPIO_FN_HTX2,
++ GPIO_FN_PWM3_A,
++ GPIO_IFN_VI0_FIELD,
++ GPIO_FN_HRX2,
++ GPIO_FN_PWM4_A,
++ GPIO_FN_CS1_N,
++ GPIO_FN_FSCLKST2_N_A,
++
++ /* IPSR5 */
++ GPIO_IFN_VI1_CLK,
++ GPIO_FN_MSIOF1_RXD,
++ GPIO_FN_CS0_N,
++ GPIO_IFN_VI1_CLKENB,
++ GPIO_FN_MSIOF1_TXD,
++ GPIO_FN_D0,
++ GPIO_IFN_VI1_HSYNC_N,
++ GPIO_FN_MSIOF1_SCK,
++ GPIO_FN_D1,
++ GPIO_IFN_VI1_VSYNC_N,
++ GPIO_FN_MSIOF1_SYNC,
++ GPIO_FN_D2,
++ GPIO_IFN_VI1_DATA0,
++ GPIO_FN_MSIOF1_SS1,
++ GPIO_FN_D3,
++ GPIO_FN_MMC_WP,
++ GPIO_IFN_VI1_DATA1,
++ GPIO_FN_MSIOF1_SS2,
++ GPIO_FN_D4,
++ GPIO_FN_MMC_CD,
++ GPIO_IFN_VI1_DATA2,
++ GPIO_FN_CANFD0_TX_B,
++ GPIO_FN_D5,
++ GPIO_FN_MMC_DS,
++ GPIO_IFN_VI1_DATA3,
++ GPIO_FN_CANFD0_RX_B,
++ GPIO_FN_D6,
++ GPIO_FN_MMC_CMD,
++
++ /* IPSR6 */
++ GPIO_IFN_VI1_DATA4,
++ GPIO_FN_CANFD_CLK_B,
++ GPIO_FN_D7,
++ GPIO_FN_MMC_D0,
++ GPIO_IFN_VI1_DATA5,
++ GPIO_FN_D8,
++ GPIO_FN_MMC_D1,
++ GPIO_IFN_VI1_DATA6,
++ GPIO_FN_D9,
++ GPIO_FN_MMC_D2,
++ GPIO_IFN_VI1_DATA7,
++ GPIO_FN_D10,
++ GPIO_FN_MMC_D3,
++ GPIO_IFN_VI1_DATA8,
++ GPIO_FN_D11,
++ GPIO_FN_MMC_CLK,
++ GPIO_IFN_VI1_DATA9,
++ GPIO_FN_TCLK1_A,
++ GPIO_FN_D12,
++ GPIO_FN_MMC_D4,
++ GPIO_IFN_VI1_DATA10,
++ GPIO_FN_TCLK2_A,
++ GPIO_FN_D13,
++ GPIO_FN_MMC_D5,
++ GPIO_IFN_VI1_DATA11,
++ GPIO_FN_SCL4,
++ GPIO_FN_D14,
++ GPIO_FN_MMC_D6,
++
++ /* IPSR7 */
++ GPIO_IFN_VI1_FIELD,
++ GPIO_FN_SDA4,
++ GPIO_FN_D15,
++ GPIO_FN_MMC_D7,
++ GPIO_IFN_SCL0,
++ GPIO_FN_CLKOUT,
++ GPIO_IFN_SDA0,
++ GPIO_FN_BS_N,
++ GPIO_FN_SCK0,
++ GPIO_FN_HSCK0_B,
++ GPIO_IFN_SCL1,
++ GPIO_FN_TPU0TO2,
++ GPIO_FN_RD_N,
++ GPIO_FN_CTS0_N,
++ GPIO_FN_HCTS0_N_B,
++ GPIO_IFN_SDA1,
++ GPIO_FN_TPU0TO3,
++ GPIO_FN_WE0_N,
++ GPIO_FN_RTS0_N_TANS,
++ GPIO_FN_HRTS0_N_B,
++ GPIO_IFN_SCL2,
++ GPIO_FN_WE1_N,
++ GPIO_FN_RX0,
++ GPIO_FN_HRX0_B,
++ GPIO_IFN_SDA2,
++ GPIO_FN_EX_WAIT0,
++ GPIO_FN_TX0,
++ GPIO_FN_HTX0_B,
++ GPIO_IFN_AVB0_AVTP_MATCH,
++ GPIO_FN_TPU0TO0,
++
++ /* IPSR8 */
++ GPIO_IFN_AVB0_AVTP_CAPTURE,
++ GPIO_FN_TPU0TO1,
++ GPIO_IFN_CANFD0_TX_A,
++ GPIO_FN_FXR_TXDA,
++ GPIO_FN_PWM0_B,
++ GPIO_FN_DU_DISP,
++ GPIO_IFN_CANFD0_RX_A,
++ GPIO_FN_RXDA_EXTFXR,
++ GPIO_FN_PWM1_B,
++ GPIO_FN_DU_CDE,
++ GPIO_IFN_CANFD1_TX,
++ GPIO_FN_FXR_TXDB,
++ GPIO_FN_PWM2_B,
++ GPIO_FN_TCLK1_B,
++ GPIO_FN_TX1_B,
++ GPIO_IFN_CANFD1_RX,
++ GPIO_FN_RXDB_EXTFXR,
++ GPIO_FN_PWM3_B,
++ GPIO_FN_TCLK2_B,
++ GPIO_FN_RX1_B,
++ GPIO_IFN_CANFD_CLK_A,
++ GPIO_FN_CLK_EXTFXR,
++ GPIO_FN_PWM4_B,
++ GPIO_FN_SPEEDIN_B,
++ GPIO_FN_SCIF_CLK_B,
++ GPIO_IFN_DIGRF_CLKIN,
++ GPIO_FN_DIGRF_CLKEN_IN,
++ GPIO_IFN_DIGRF_CLKOUT,
++ GPIO_FN_DIGRF_CLKEN_OUT,
++
++ /* IPSR9 */
++ GPIO_IFN_IRQ4,
++ GPIO_FN_VI0_DATA12,
++ GPIO_IFN_IRQ5,
++ GPIO_FN_VI0_DATA13,
++ GPIO_IFN_MSIOF0_RXD,
++ GPIO_FN_DU_DR0,
++ GPIO_FN_VI0_DATA14,
++ GPIO_IFN_MSIOF0_TXD,
++ GPIO_FN_DU_DR1,
++ GPIO_FN_VI0_DATA15,
++ GPIO_IFN_MSIOF0_SCK,
++ GPIO_FN_DU_DG0,
++ GPIO_FN_VI0_DATA16,
++ GPIO_IFN_MSIOF0_SYNC,
++ GPIO_FN_DU_DG1,
++ GPIO_FN_VI0_DATA17,
++ GPIO_IFN_MSIOF0_SS1,
++ GPIO_FN_DU_DB0,
++ GPIO_FN_TCLK3,
++ GPIO_FN_VI0_DATA18,
++ GPIO_IFN_MSIOF0_SS2,
++ GPIO_FN_DU_DB1,
++ GPIO_FN_TCLK4,
++ GPIO_FN_VI0_DATA19,
++
++ /* IPSR10 */
++ GPIO_IFN_SCL3,
++ GPIO_FN_VI0_DATA20,
++ GPIO_IFN_SDA3,
++ GPIO_FN_VI0_DATA21,
++ GPIO_IFN_FSO_CFE_0_N,
++ GPIO_FN_VI0_DATA22,
++ GPIO_IFN_FSO_CFE_1_N,
++ GPIO_FN_VI0_DATA23,
++ GPIO_IFN_FSO_TOE_N,
++};
++
++#endif /* __ASM_R8A7798_GPIO_H__ */
+diff --git a/arch/arm/include/asm/arch-rcar_gen3/r8a7798.h b/arch/arm/include/asm/arch-rcar_gen3/r8a7798.h
+new file mode 100644
+index 0000000..06514f0
+--- /dev/null
++++ b/arch/arm/include/asm/arch-rcar_gen3/r8a7798.h
+@@ -0,0 +1,34 @@
++/*
++ * arch/arm/include/asm/arch-rcar_gen3/r8a7798.h
++ * This file defines registers and value for r8a7798.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __ASM_ARCH_R8A7798_H
++#define __ASM_ARCH_R8A7798_H
++
++#include "rcar-base.h"
++
++/* Module stop control/status register bits */
++#define MSTP0_BITS 0x00230000
++#define MSTP1_BITS 0xFFFFFFFF
++#define MSTP2_BITS 0x14062FD8
++#define MSTP3_BITS 0xFFFFFFDF
++#define MSTP4_BITS 0x80000184
++#define MSTP5_BITS 0x83FFFFFF
++#define MSTP6_BITS 0xFFFFFFFF
++#define MSTP7_BITS 0xFFFFFFFF
++#define MSTP8_BITS 0x7FF3FFF4
++#define MSTP9_BITS 0xFBF7FF97
++#define MSTP10_BITS 0xFFFEFFE0
++#define MSTP11_BITS 0x000000B7
++
++/* SDHI */
++#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */
++#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1
++
++#endif /* __ASM_ARCH_R8A7798_H */
+diff --git a/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h b/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h
+index c2ba0fb..c3568b0 100644
+--- a/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h
++++ b/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h
+@@ -16,6 +16,8 @@
+ #include <asm/arch/r8a7796.h>
+ #elif defined(CONFIG_R8A7797)
+ #include <asm/arch/r8a7797.h>
++ #elif defined(CONFIG_R8A7798)
++ #include <asm/arch/r8a7798.h>
+ #else
+ #error "SOC Name not defined"
+ #endif
+diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
+index 4b9a61b..95129ce 100644
+--- a/drivers/mtd/spi/sf_probe.c
++++ b/drivers/mtd/spi/sf_probe.c
+@@ -383,7 +383,7 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash)
+ puts("\n");
+ #endif
+ #ifndef CONFIG_SPI_FLASH_BAR
+-#ifndef CONFIG_R8A7797
++#if !defined(CONFIG_R8A7797) && !defined(CONFIG_R8A7798)
+ if (((flash->dual_flash == SF_SINGLE_FLASH) &&
+ (flash->size > SPI_FLASH_16MB_BOUN)) ||
+ ((flash->dual_flash > SF_SINGLE_FLASH) &&
+diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
+index 1a26543..b19ece1 100644
+--- a/drivers/net/Kconfig
++++ b/drivers/net/Kconfig
+@@ -2,7 +2,7 @@ menu "Network Device Support"
+
+ config RAVB_1000BASE
+ bool "Renesas Ethernet AVB support 1000Base"
+- default y if R8A7795 || R8A7796X || R8A7797
++ default y if R8A7795 || R8A7796X || R8A7797 || R8A7798
+ depends on RCAR_GEN3
+
+ endmenu
+diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
+index 4bf493e..8226591 100644
+--- a/drivers/net/sh_eth.c
++++ b/drivers/net/sh_eth.c
+@@ -380,8 +380,12 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
+ struct phy_device *phy;
+
+ /* Configure e-dmac registers */
++ val = EMDR_DESC | EDMR_EL;
++#if defined(CONFIG_R8A7798)
++ val |= EDMR_NBST;
++#endif
+ sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) |
+- (EMDR_DESC | EDMR_EL), EDMR);
++ val, EDMR);
+
+ sh_eth_write(eth, 0, EESIPR);
+ sh_eth_write(eth, 0, TRSCER);
+@@ -417,7 +421,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
+ #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
+ sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
+ #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+- defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
++ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) || \
++ defined(CONFIG_R8A7798)
+ sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
+ #endif
+ /* Configure phy */
+@@ -444,7 +449,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
+ sh_eth_write(eth, 1, RTRATE);
+ #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
+ defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
+- defined(CONFIG_R8A7794)
++ defined(CONFIG_R8A7794) || defined(CONFIG_R8A7798)
+ val = ECMR_RTM;
+ #endif
+ } else if (phy->speed == 10) {
+diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
+index 5cb520c..3c30d42 100644
+--- a/drivers/net/sh_eth.h
++++ b/drivers/net/sh_eth.h
+@@ -361,6 +361,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
+ #elif defined(CONFIG_R7S72100)
+ #define SH_ETH_TYPE_RZ
+ #define BASE_IO_ADDR 0xE8203000
++#elif defined(CONFIG_R8A7798)
++#define SH_ETH_TYPE_GETHER
++#define BASE_IO_ADDR 0xE7400000
+ #endif
+
+ /*
+@@ -377,6 +380,7 @@ enum EDSR_BIT {
+
+ /* EDMR */
+ enum DMAC_M_BIT {
++ EDMR_NBST = 0x80, /* DMA transfer burst mode */
+ EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
+ #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
+ EDMR_SRST = 0x03, /* Receive/Send reset */
+@@ -567,7 +571,8 @@ enum FELIC_MODE_BIT {
+ #ifdef CONFIG_CPU_SH7724
+ ECMR_RTM = 0x00000010,
+ #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+- defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
++ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) || \
++ defined(CONFIG_R8A7798)
+ ECMR_RTM = 0x00000004,
+ #endif
+
+diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
+index 478824e..ded0d3d 100644
+--- a/drivers/serial/serial_sh.h
++++ b/drivers/serial/serial_sh.h
+@@ -227,7 +227,7 @@ struct uart_port {
+ #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) || \
+ defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796X) || \
+- defined(CONFIG_R8A7797)
++ defined(CONFIG_R8A7797) || defined(CONFIG_R8A7798)
+ # define SCIF_ORER 0x0001
+ # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
+ /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
+diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
+index dc5560d..a3721ad 100644
+--- a/include/configs/rcar-gen3-common.h
++++ b/include/configs/rcar-gen3-common.h
+@@ -134,6 +134,12 @@
+ #endif
+ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+ #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
++#elif defined(CONFIG_R8A7798)
++#define CONFIG_NR_DRAM_BANKS 1
++#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE) /* legacy */
++#define PHYS_SDRAM_1_SIZE ((unsigned long)(0x80000000 - DRAM_RSV_SIZE))
++#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
++#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
+ #else
+ #define CONFIG_NR_DRAM_BANKS 1
+ #define CONFIG_SYS_SDRAM_BASE 0x40000000
+--
+1.9.1
+
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0019-board-renesas-Add-Condor-board.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0019-board-renesas-Add-Condor-board.patch
new file mode 100644
index 0000000..704c4b9
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0019-board-renesas-Add-Condor-board.patch
@@ -0,0 +1,560 @@
+From 4b72eea699c087004b12f759da98e7c6a3d663fa Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Mon, 22 Jan 2018 13:21:35 +0300
+Subject: [PATCH] board: renesas: Add Condor board
+
+Condor is a board based on R-Car V3H SoC (R8A7798)
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+
+%% original patch: 0019-board-renesas-Add-Condor-board.patch
+---
+ arch/arm/cpu/armv8/Kconfig | 4 +
+ board/renesas/condor/Kconfig | 15 +++
+ board/renesas/condor/MAINTAINERS | 6 +
+ board/renesas/condor/Makefile | 10 ++
+ board/renesas/condor/condor.c | 272 +++++++++++++++++++++++++++++++++++++++
+ configs/r8a7798_condor_defconfig | 10 ++
+ include/configs/r8a7798_condor.h | 161 +++++++++++++++++++++++
+ 7 files changed, 478 insertions(+)
+ create mode 100644 board/renesas/condor/Kconfig
+ create mode 100644 board/renesas/condor/MAINTAINERS
+ create mode 100644 board/renesas/condor/Makefile
+ create mode 100644 board/renesas/condor/condor.c
+ create mode 100644 configs/r8a7798_condor_defconfig
+ create mode 100644 include/configs/r8a7798_condor.h
+
+diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
+index 58a9259..0edd5db 100644
+--- a/arch/arm/cpu/armv8/Kconfig
++++ b/arch/arm/cpu/armv8/Kconfig
+@@ -22,6 +22,9 @@ config TARGET_EAGLE
+ config TARGET_V3MSK
+ bool "V3MSK board"
+
++config TARGET_CONDOR
++ bool "CONDOR board"
++
+ endchoice
+
+ config R8A7796X
+@@ -56,5 +59,6 @@ source "board/renesas/salvator-x/Kconfig"
+ source "board/renesas/ulcb/Kconfig"
+ source "board/renesas/eagle/Kconfig"
+ source "board/renesas/v3msk/Kconfig"
++source "board/renesas/condor/Kconfig"
+
+ endif
+diff --git a/board/renesas/condor/Kconfig b/board/renesas/condor/Kconfig
+new file mode 100644
+index 0000000..21ba79f
+--- /dev/null
++++ b/board/renesas/condor/Kconfig
+@@ -0,0 +1,15 @@
++if TARGET_CONDOR
++
++config SYS_SOC
++ default "rcar_gen3"
++
++config SYS_BOARD
++ default "condor"
++
++config SYS_VENDOR
++ default "renesas"
++
++config SYS_CONFIG_NAME
++ default "r8a7798_condor" if R8A7798
++
++endif
+diff --git a/board/renesas/condor/MAINTAINERS b/board/renesas/condor/MAINTAINERS
+new file mode 100644
+index 0000000..9076b24
+--- /dev/null
++++ b/board/renesas/condor/MAINTAINERS
+@@ -0,0 +1,6 @@
++CONDOR BOARD
++M: Cogent Embedded, Inc. <source@cogentembedded.com>
++S: Maintained
++F: board/renesas/condor/
++F: include/configs/r8a7798_condor.h
++F: configs/r8a7798_condor_defconfig
+diff --git a/board/renesas/condor/Makefile b/board/renesas/condor/Makefile
+new file mode 100644
+index 0000000..d11d859
+--- /dev/null
++++ b/board/renesas/condor/Makefile
+@@ -0,0 +1,10 @@
++#
++# board/renesas/condor/Makefile
++#
++# Copyright (C) 2018 Renesas Electronics Corp.
++# Copyright (C) 2018 Cogent Embedded, Inc.
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y := condor.o ../rcar-gen3-common/common.o
+diff --git a/board/renesas/condor/condor.c b/board/renesas/condor/condor.c
+new file mode 100644
+index 0000000..dfbfe87
+--- /dev/null
++++ b/board/renesas/condor/condor.c
+@@ -0,0 +1,272 @@
++/*
++ * board/renesas/condor/condor.c
++ * This is Condor board support.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <malloc.h>
++#include <netdev.h>
++#include <dm.h>
++#include <dm/platform_data/serial_sh.h>
++#include <asm/processor.h>
++#include <asm/mach-types.h>
++#include <asm/io.h>
++#include <asm/errno.h>
++#include <asm/arch/sys_proto.h>
++#include <asm/gpio.h>
++#include <asm/arch/prr_depend.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/rcar_gen3.h>
++#include <asm/arch/rcar-mstp.h>
++#include <asm/arch/sh_sdhi.h>
++#include <i2c.h>
++#include <mmc.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#define SCIF0_MSTP207 (1 << 7)
++#define GETHER_MSTP813 (1 << 13)
++#define RAVB_MSTP812 (1 << 12)
++#define RPC_MSTP917 (1 << 17)
++#define SD0_MSTP314 (1 << 14)
++#define I2C0_MSTP931 (1 << 31)
++
++#define SD0CKCR 0xE6150074
++
++#define PFC_PMMR 0xe6060000
++#define PFC_POC1 0xe6060384
++#define POC_MMC_3V3 0x00fff800
++
++void s_init(void)
++{
++ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
++ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
++
++ /* Watchdog init */
++ writel(0xA5A5A500, &rwdt->rwtcsra);
++ writel(0xA5A5A500, &swdt->swtcsra);
++}
++
++int board_early_init_f(void)
++{
++ int freq;
++
++ rcar_prr_init();
++
++ writel(0xa5a5ffff, 0xe6150900);
++ writel(0x5a5a0000, 0xe6150904);
++ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, 0x02000000);
++ /* SCIF0 */
++ mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIF0_MSTP207);
++ /* SDHI0/MMC */
++ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
++#if defined(CONFIG_RAVB)
++ /* RAVB Ethernet */
++ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, RAVB_MSTP812);
++#elif defined(CONFIG_SH_ETHER)
++ /* Gigabit Ethernet */
++ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, GETHER_MSTP813);
++#endif
++ /* QSPI/RPC */
++ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, RPC_MSTP917);
++ /* I2C0 */
++ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, I2C0_MSTP931);
++
++ freq = rcar_get_sdhi_config_clk();
++ writel(freq, SD0CKCR);
++
++ return 0;
++}
++
++int board_init(void)
++{
++ /* address of boot parameters */
++ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
++
++ /* Init PFC controller */
++ pinmux_init();
++#if defined(CONFIG_RAVB)
++ gpio_request(GPIO_GFN_AVB0_AVTP_CAPTURE, NULL);
++ gpio_request(GPIO_GFN_AVB0_AVTP_MATCH, NULL);
++ gpio_request(GPIO_FN_AVB0_LINK, NULL);
++ gpio_request(GPIO_FN_AVB0_PHY_INT, NULL);
++ /* gpio_request(GPIO_FN_AVB0_MAGIC, NULL); - PHY reset gpio */
++ gpio_request(GPIO_FN_AVB0_MDC, NULL);
++ gpio_request(GPIO_FN_AVB0_MDIO, NULL);
++ gpio_request(GPIO_FN_AVB0_TXCREFCLK, NULL);
++ gpio_request(GPIO_FN_AVB0_TD3, NULL);
++ gpio_request(GPIO_FN_AVB0_TD2, NULL);
++ gpio_request(GPIO_FN_AVB0_TD1, NULL);
++ gpio_request(GPIO_FN_AVB0_TD0, NULL);
++ gpio_request(GPIO_FN_AVB0_TXC, NULL);
++ gpio_request(GPIO_FN_AVB0_TX_CTL, NULL);
++ gpio_request(GPIO_FN_AVB0_RD3, NULL);
++ gpio_request(GPIO_FN_AVB0_RD2, NULL);
++ gpio_request(GPIO_FN_AVB0_RD1, NULL);
++ gpio_request(GPIO_FN_AVB0_RD0, NULL);
++ gpio_request(GPIO_FN_AVB0_RXC, NULL);
++ gpio_request(GPIO_FN_AVB0_RX_CTL, NULL);
++ gpio_request(GPIO_IFN_AVB0_AVTP_CAPTURE, NULL);
++ gpio_request(GPIO_FN_AVB0_AVTP_PPS, NULL);
++
++ /* PHY_RST */
++ gpio_request(GPIO_GP_1_16, NULL);
++ gpio_direction_output(GPIO_GP_1_16, 0);
++ mdelay(20);
++ gpio_set_value(GPIO_GP_1_16, 1);
++ udelay(1);
++#elif defined(CONFIG_SH_ETHER)
++ gpio_request(GPIO_FN_GETHER_LINK_A, NULL);
++ gpio_request(GPIO_FN_GETHER_PHY_INT_A, NULL);
++ /* gpio_request(GPIO_FN_GETHER_MAGIC, NULL); - PHY reset gpio */
++ gpio_request(GPIO_FN_GETHER_MDC_A, NULL);
++ gpio_request(GPIO_FN_GETHER_MDIO_A, NULL);
++ gpio_request(GPIO_FN_GETHER_TXCREFCLK, NULL);
++ gpio_request(GPIO_FN_GETHER_TXCREFCLK_MEGA, NULL);
++ gpio_request(GPIO_FN_GETHER_TD3, NULL);
++ gpio_request(GPIO_FN_GETHER_TD2, NULL);
++ gpio_request(GPIO_FN_GETHER_TD1, NULL);
++ gpio_request(GPIO_FN_GETHER_TD0, NULL);
++ gpio_request(GPIO_FN_GETHER_TXC, NULL);
++ gpio_request(GPIO_FN_GETHER_TX_CTL, NULL);
++ gpio_request(GPIO_FN_GETHER_RD3, NULL);
++ gpio_request(GPIO_FN_GETHER_RD2, NULL);
++ gpio_request(GPIO_FN_GETHER_RD1, NULL);
++ gpio_request(GPIO_FN_GETHER_RD0, NULL);
++ gpio_request(GPIO_FN_GETHER_RXC, NULL);
++ gpio_request(GPIO_FN_GETHER_RX_CTL, NULL);
++
++ /* PHY_RST */
++ gpio_request(GPIO_GP_4_22, NULL);
++ gpio_direction_output(GPIO_GP_4_22, 0);
++ mdelay(20);
++ gpio_set_value(GPIO_GP_4_22, 1);
++ udelay(1);
++#endif
++ /* QSPI/RPC */
++ gpio_request(GPIO_FN_QSPI0_SPCLK, NULL);
++ gpio_request(GPIO_FN_QSPI0_MOSI_IO0, NULL);
++ gpio_request(GPIO_FN_QSPI0_MISO_IO1, NULL);
++ gpio_request(GPIO_FN_QSPI0_IO2, NULL);
++ gpio_request(GPIO_FN_QSPI0_IO3, NULL);
++ gpio_request(GPIO_FN_QSPI0_SSL, NULL);
++ gpio_request(GPIO_FN_QSPI1_SPCLK, NULL);
++ gpio_request(GPIO_FN_QSPI1_MOSI_IO0, NULL);
++ gpio_request(GPIO_FN_QSPI1_MISO_IO1, NULL);
++ gpio_request(GPIO_FN_QSPI1_IO2, NULL);
++ gpio_request(GPIO_FN_QSPI1_IO3, NULL);
++ gpio_request(GPIO_FN_QSPI1_SSL, NULL);
++ gpio_request(GPIO_FN_RPC_RESET_N, NULL);
++ gpio_request(GPIO_FN_RPC_WP_N, NULL);
++ gpio_request(GPIO_FN_RPC_INT_N, NULL);
++
++ return 0;
++}
++
++#if defined(CONFIG_RAVB)
++#define MAHR 0xE68005C0
++#define MALR 0xE68005C8
++#elif defined(CONFIG_SH_ETHER)
++#define MAHR 0xE74005C0
++#define MALR 0xE74005C8
++#endif
++int board_eth_init(bd_t *bis)
++{
++ int ret = -ENODEV;
++
++ u32 val;
++ unsigned char enetaddr[6];
++
++ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
++ return ret;
++
++ /* Set Mac address */
++ val = enetaddr[0] << 24 | enetaddr[1] << 16 |
++ enetaddr[2] << 8 | enetaddr[3];
++ writel(val, MAHR);
++
++ val = enetaddr[4] << 8 | enetaddr[5];
++ writel(val, MALR);
++#if defined(CONFIG_RAVB)
++ ret = ravb_initialize(bis);
++#elif defined(CONFIG_SH_ETHER)
++ ret = sh_eth_initialize(bis);
++#endif
++ return ret;
++}
++
++/* Condor has KSZ9031RNX */
++int board_phy_config(struct phy_device *phydev)
++{
++ return 0;
++}
++
++int board_mmc_init(bd_t *bis)
++{
++ int ret = -ENODEV;
++#ifdef CONFIG_SH_SDHI
++ u32 val;
++
++ /* SDHI2/eMMC */
++ gpio_request(GPIO_FN_MMC_D0, NULL);
++ gpio_request(GPIO_FN_MMC_D1, NULL);
++ gpio_request(GPIO_FN_MMC_D2, NULL);
++ gpio_request(GPIO_FN_MMC_D3, NULL);
++ gpio_request(GPIO_FN_MMC_D4, NULL);
++ gpio_request(GPIO_FN_MMC_D5, NULL);
++ gpio_request(GPIO_FN_MMC_D6, NULL);
++ gpio_request(GPIO_FN_MMC_D7, NULL);
++ gpio_request(GPIO_FN_MMC_CLK, NULL);
++ gpio_request(GPIO_FN_MMC_CMD, NULL);
++ gpio_request(GPIO_FN_MMC_CD, NULL);
++ gpio_request(GPIO_FN_MMC_WP, NULL);
++
++ val = readl(PFC_POC1);
++ val &= ~POC_MMC_3V3; /* POC = 1.8V */
++ writel(~val, PFC_PMMR);
++ writel(val, PFC_POC1);
++
++ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 0,
++ SH_SDHI_QUIRK_64BIT_BUF);
++#endif
++ return ret;
++}
++
++int dram_init(void)
++{
++ gd->ram_size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
++
++void dram_init_banksize(void)
++{
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++}
++
++const struct rcar_sysinfo sysinfo = {
++ CONFIG_RCAR_BOARD_STRING
++};
++
++void reset_cpu(ulong addr)
++{
++#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_RCAR)
++ i2c_set_bus_num(0);
++ i2c_init(400000, 0);
++ i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
++#endif
++}
++
++#if defined(CONFIG_DISPLAY_BOARDINFO)
++int checkboard(void)
++{
++ printf("Board: %s\n", sysinfo.board_string);
++ return 0;
++}
++#endif
+diff --git a/configs/r8a7798_condor_defconfig b/configs/r8a7798_condor_defconfig
+new file mode 100644
+index 0000000..1cab2ae
+--- /dev/null
++++ b/configs/r8a7798_condor_defconfig
+@@ -0,0 +1,10 @@
++CONFIG_ARM=y
++CONFIG_RCAR_GEN3=y
++CONFIG_DM_SERIAL=y
++CONFIG_TARGET_CONDOR=y
++CONFIG_R8A7798=y
++CONFIG_SPL=y
++CONFIG_SH_SDHI=y
++CONFIG_SPI_FLASH=y
++CONFIG_SPI_FLASH_SPANSION=y
++CONFIG_SPI_FLASH_BAR=y
+diff --git a/include/configs/r8a7798_condor.h b/include/configs/r8a7798_condor.h
+new file mode 100644
+index 0000000..6bcc79a
+--- /dev/null
++++ b/include/configs/r8a7798_condor.h
+@@ -0,0 +1,161 @@
++/*
++ * include/configs/r8a7798_condor.h
++ * This file is Condor board configuration.
++ * CPU r8a7798.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __CONDOR_H
++#define __CONDOR_H
++
++#undef DEBUG
++#define CONFIG_RCAR_BOARD_STRING "Condor"
++#define CONFIG_RCAR_TARGET_STRING "r8a7798"
++
++#include "rcar-gen3-common.h"
++
++//#define CONFIG_SYS_DCACHE_OFF
++//#define CONFIG_SYS_ICACHE_OFF
++
++/* SCIF */
++#define CONFIG_SCIF_CONSOLE
++#define CONFIG_CONS_SCIF0
++#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
++
++/* [A] Hyper Flash */
++/* use to RPC(SPI Multi I/O Bus Controller) */
++
++ /* underconstruction */
++
++#define CONFIG_SYS_NO_FLASH
++#if defined(CONFIG_SYS_NO_FLASH)
++#define CONFIG_SPI
++#define CONFIG_RCAR_GEN3_QSPI
++#define CONFIG_SH_QSPI_BASE 0xEE200000
++#define CONFIG_CMD_SF
++#define CONFIG_CMD_SPI
++#define CONFIG_SPI_FLASH
++#define CONFIG_SPI_FLASH_SPANSION
++#else
++#undef CONFIG_CMD_SF
++#undef CONFIG_CMD_SPI
++#undef CONFIG_SPI_FLASH
++#undef CONFIG_SPI_FLASH_SPANSION
++#endif
++
++#if 0
++/* Ethernet RAVB */
++#define CONFIG_RAVB
++#define CONFIG_RAVB_PHY_ADDR 0x0
++#define CONFIG_RAVB_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID
++#define CONFIG_NET_MULTI
++#define CONFIG_PHYLIB
++#define CONFIG_PHY_MICREL
++#define CONFIG_BITBANGMII
++#define CONFIG_BITBANGMII_MULTI
++#define CONFIG_SH_ETHER_BITBANG
++#else
++/* GETHER */
++#define CONFIG_NET_MULTI
++#define CONFIG_SH_ETHER
++#define CONFIG_SH_ETHER_USE_PORT 0
++#define CONFIG_SH_ETHER_PHY_ADDR 0x0
++#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID
++#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
++#define CONFIG_SH_ETHER_CACHE_WRITEBACK
++#define CONFIG_SH_ETHER_CACHE_INVALIDATE
++#define CONFIG_PHYLIB
++#define CONFIG_PHY_MICREL
++#define CONFIG_BITBANGMII
++#define CONFIG_BITBANGMII_MULTI
++#endif
++
++/* Board Clock */
++/* XTAL_CLK : 33.33MHz */
++#define RCAR_XTAL_CLK 33333333u
++#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK
++/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
++/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */
++#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
++#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2)
++#define CONFIG_S3D2_CLK_FREQ (266666666u/2)
++#define CONFIG_S3D4_CLK_FREQ (266666666u/4)
++#define CONFIG_S3D2_CLK_FREQ (133333333u)
++
++
++/* Generic Timer Definitions (use in assembler source) */
++#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
++
++/* Generic Interrupt Controller Definitions */
++#define GICD_BASE (0xF1010000)
++#define GICC_BASE (0xF1020000)
++#define CONFIG_GICV2
++
++/* i2c */
++#define CONFIG_SYS_I2C
++#define CONFIG_SYS_I2C_RCAR
++#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
++#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
++#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
++#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
++#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
++#define CONFIG_HP_CLK_FREQ CONFIG_S3D2_CLK_FREQ
++#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30
++
++/* USB */
++#undef CONFIG_CMD_USB
++
++/* SDHI */
++#define CONFIG_MMC
++#define CONFIG_CMD_MMC
++#define CONFIG_GENERIC_MMC
++#define CONFIG_SH_SDHI_FREQ 200000000
++#define CONFIG_SH_SDHI_MMC
++
++/* ENV setting */
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_SECT_SIZE (256 * 1024)
++#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
++#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
++
++//#define CONFIG_ENV_IS_IN_MMC
++#define CONFIG_ENV_IS_IN_SPI_FLASH
++
++#if defined(CONFIG_ENV_IS_IN_MMC)
++/* Environment in eMMC, at the end of 2nd "boot sector" */
++#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
++#define CONFIG_SYS_MMC_ENV_DEV 0
++#define CONFIG_SYS_MMC_ENV_PART 2
++#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
++/* Environment in QSPI */
++#define CONFIG_ENV_ADDR 0x700000
++#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
++#else
++#define CONFIG_ENV_IS_NOWHERE
++#endif
++
++/* Module clock supply/stop status bits */
++/* MFIS */
++#define CONFIG_SMSTP2_ENA 0x00002000
++/* serial(SCIF0) */
++#define CONFIG_SMSTP3_ENA 0x00000400
++/* INTC-AP, INTC-EX */
++#define CONFIG_SMSTP4_ENA 0x00000180
++
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ "fdt_high=0xffffffffffffffff\0" \
++ "initrd_high=0xffffffffffffffff\0" \
++ "ethaddr=2E:11:22:33:44:55\0"
++
++#define CONFIG_BOOTARGS \
++ "root=/dev/nfs rw ip=dhcp"
++
++#define CONFIG_BOOTCOMMAND \
++ "bootp 0x48080000 Image; tftp 0x48000000 r8a7798-condor.dtb; " \
++ "booti 0x48080000 - 0x48000000"
++
++#endif /* __CONDOR_H */
+--
+2.7.4
+
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0020-board-renesas-Add-V3MZF-board.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0020-board-renesas-Add-V3MZF-board.patch
new file mode 100644
index 0000000..a746262
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0020-board-renesas-Add-V3MZF-board.patch
@@ -0,0 +1,477 @@
+From 0d3af8c73ded0f32c988b4cdc6fa8eb0d75d719a Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Fri, 2 Feb 2018 19:28:08 +0300
+Subject: [PATCH] board: renesas: Add V3M ZF board
+
+V3M ZF B0 is a board based on R-Car V3M SoC (R8A7797)
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+---
+ arch/arm/cpu/armv8/Kconfig | 4 +
+ board/renesas/v3mzf/Kconfig | 15 +++
+ board/renesas/v3mzf/MAINTAINERS | 6 ++
+ board/renesas/v3mzf/Makefile | 9 ++
+ board/renesas/v3mzf/v3mzf.c | 214 ++++++++++++++++++++++++++++++++++++++++
+ configs/v3mzf_defconfig | 9 ++
+ include/configs/v3mzf.h | 137 +++++++++++++++++++++++++
+ 7 files changed, 394 insertions(+)
+ create mode 100644 board/renesas/v3mzf/Kconfig
+ create mode 100644 board/renesas/v3mzf/MAINTAINERS
+ create mode 100644 board/renesas/v3mzf/Makefile
+ create mode 100644 board/renesas/v3mzf/v3mzf.c
+ create mode 100644 configs/v3mzf_defconfig
+ create mode 100644 include/configs/v3mzf.h
+
+diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
+index 0edd5db..a2706a6 100644
+--- a/arch/arm/cpu/armv8/Kconfig
++++ b/arch/arm/cpu/armv8/Kconfig
+@@ -22,6 +22,9 @@ config TARGET_EAGLE
+ config TARGET_V3MSK
+ bool "V3MSK board"
+
++config TARGET_V3MZF
++ bool "V3MZF board"
++
+ config TARGET_CONDOR
+ bool "CONDOR board"
+
+@@ -60,5 +63,6 @@ source "board/renesas/ulcb/Kconfig"
+ source "board/renesas/eagle/Kconfig"
+ source "board/renesas/v3msk/Kconfig"
+ source "board/renesas/condor/Kconfig"
++source "board/renesas/v3mzf/Kconfig"
+
+ endif
+diff --git a/board/renesas/v3mzf/Kconfig b/board/renesas/v3mzf/Kconfig
+new file mode 100644
+index 0000000..11c7922
+--- /dev/null
++++ b/board/renesas/v3mzf/Kconfig
+@@ -0,0 +1,15 @@
++if TARGET_V3MZF
++
++config SYS_SOC
++ default "rcar_gen3"
++
++config SYS_BOARD
++ default "v3mzf"
++
++config SYS_VENDOR
++ default "renesas"
++
++config SYS_CONFIG_NAME
++ default "v3mzf" if R8A7797
++
++endif
+diff --git a/board/renesas/v3mzf/MAINTAINERS b/board/renesas/v3mzf/MAINTAINERS
+new file mode 100644
+index 0000000..140af42
+--- /dev/null
++++ b/board/renesas/v3mzf/MAINTAINERS
+@@ -0,0 +1,6 @@
++V3MZF BOARD
++M: Cogent Embedded, Inc. <source@cogentembedded.com>
++S: Maintained
++F: board/renesas/v3mzf/
++F: include/configs/v3mzf.h
++F: configs/v3mzf_defconfig
+diff --git a/board/renesas/v3mzf/Makefile b/board/renesas/v3mzf/Makefile
+new file mode 100644
+index 0000000..ed31453
+--- /dev/null
++++ b/board/renesas/v3mzf/Makefile
+@@ -0,0 +1,9 @@
++#
++# board/renesas/v3mzf/Makefile
++#
++# Copyright (C) 2018 Cogent Embedded, Inc.
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y := v3mzf.o ../rcar-gen3-common/common.o
+diff --git a/board/renesas/v3mzf/v3mzf.c b/board/renesas/v3mzf/v3mzf.c
+new file mode 100644
+index 0000000..fa1e299
+--- /dev/null
++++ b/board/renesas/v3mzf/v3mzf.c
+@@ -0,0 +1,217 @@
++/*
++ * board/renesas/v3mzf/v3mzf.c
++ * This is V3MZF board support.
++ *
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <malloc.h>
++#include <netdev.h>
++#include <dm.h>
++#include <dm/platform_data/serial_sh.h>
++#include <asm/processor.h>
++#include <asm/mach-types.h>
++#include <asm/io.h>
++#include <asm/errno.h>
++#include <asm/arch/sys_proto.h>
++#include <asm/gpio.h>
++#include <asm/arch/prr_depend.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/rcar_gen3.h>
++#include <asm/arch/rcar-mstp.h>
++#include <asm/arch/sh_sdhi.h>
++#include <i2c.h>
++#include <mmc.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#define SCIF0_MSTP207 (1 << 7)
++#define ETHERAVB_MSTP812 (1 << 12)
++#define RPC_MSTP917 (1 << 17)
++#define SD0_MSTP314 (1 << 14)
++#define GP1_MSTP911 (1 << 11)
++
++#define SD0CKCR 0xE6150074
++
++void s_init(void)
++{
++ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
++ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
++
++ /* Watchdog init */
++ writel(0xA5A5A500, &rwdt->rwtcsra);
++ writel(0xA5A5A500, &swdt->swtcsra);
++}
++
++int board_early_init_f(void)
++{
++ int freq;
++
++ rcar_prr_init();
++
++ writel(0xa5a5ffff, 0xe6150900);
++ writel(0x5a5a0000, 0xe6150904);
++ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, 0x02000000);
++ /* SCIF0 */
++ mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIF0_MSTP207);
++ /* SDHI2/MMC */
++ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
++ /* EHTERAVB */
++ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
++ /* QSPI/RPC */
++ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, RPC_MSTP917);
++ /* GPIO1 */
++ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, GP1_MSTP911);
++
++ freq = rcar_get_sdhi_config_clk();
++ writel(freq, SD0CKCR);
++
++ return 0;
++}
++
++int board_init(void)
++{
++ /* adress of boot parameters */
++ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
++
++ /* Init PFC controller */
++ pinmux_init();
++#ifdef CONFIG_RAVB
++ /* GPSR1 */
++ gpio_request(GPIO_GFN_AVB0_AVTP_CAPTURE, NULL);
++ gpio_request(GPIO_FN_AVB0_AVTP_MATCH, NULL);
++ gpio_request(GPIO_FN_AVB0_LINK, NULL);
++ gpio_request(GPIO_FN_AVB0_PHY_INT, NULL);
++ /* gpio_request(GPIO_FN_AVB0_MAGIC, NULL); */
++ gpio_request(GPIO_FN_AVB0_MDC, NULL);
++ gpio_request(GPIO_FN_AVB0_MDIO, NULL);
++ gpio_request(GPIO_FN_AVB0_TXCREFCLK, NULL);
++ gpio_request(GPIO_FN_AVB0_TD3, NULL);
++ gpio_request(GPIO_FN_AVB0_TD2, NULL);
++ gpio_request(GPIO_FN_AVB0_TD1, NULL);
++ gpio_request(GPIO_FN_AVB0_TD0, NULL);
++ gpio_request(GPIO_FN_AVB0_TXC, NULL);
++ gpio_request(GPIO_FN_AVB0_TX_CTL, NULL);
++ gpio_request(GPIO_FN_AVB0_RD3, NULL);
++ gpio_request(GPIO_FN_AVB0_RD2, NULL);
++ gpio_request(GPIO_FN_AVB0_RD1, NULL);
++ gpio_request(GPIO_FN_AVB0_RD0, NULL);
++ gpio_request(GPIO_FN_AVB0_RXC, NULL);
++ gpio_request(GPIO_FN_AVB0_RX_CTL, NULL);
++ /* IPSR7 */
++ gpio_request(GPIO_IFN_AVB0_AVTP_CAPTURE, NULL);
++ /* IPSR3 */
++ gpio_request(GPIO_FN_AVB0_AVTP_PPS, NULL);
++
++ /* AVB_PHY_RST */
++ gpio_request(GPIO_GP_1_16, NULL);
++ gpio_direction_output(GPIO_GP_1_16, 0);
++ mdelay(20);
++ gpio_set_value(GPIO_GP_1_16, 1);
++ udelay(1);
++#endif
++ /* QSPI/RPC */
++ gpio_request(GPIO_FN_QSPI0_SPCLK, NULL);
++ gpio_request(GPIO_FN_QSPI0_MOSI_IO0, NULL);
++ gpio_request(GPIO_FN_QSPI0_MISO_IO1, NULL);
++ gpio_request(GPIO_FN_QSPI0_IO2, NULL);
++ gpio_request(GPIO_FN_QSPI0_IO3, NULL);
++ gpio_request(GPIO_FN_QSPI0_SSL, NULL);
++ gpio_request(GPIO_FN_QSPI1_SPCLK, NULL);
++ gpio_request(GPIO_FN_QSPI1_MOSI_IO0, NULL);
++ gpio_request(GPIO_FN_QSPI1_MISO_IO1, NULL);
++ gpio_request(GPIO_FN_QSPI1_IO2, NULL);
++ gpio_request(GPIO_FN_QSPI1_IO3, NULL);
++ gpio_request(GPIO_FN_QSPI1_SSL, NULL);
++ gpio_request(GPIO_FN_RPC_RESET_N, NULL);
++ gpio_request(GPIO_FN_RPC_WP_N, NULL);
++ gpio_request(GPIO_FN_RPC_INT_N, NULL);
++
++ return 0;
++}
++
++#define MAHR 0xE68005C0
++#define MALR 0xE68005C8
++int board_eth_init(bd_t *bis)
++{
++ int ret = -ENODEV;
++ u32 val;
++ unsigned char enetaddr[6];
++
++ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
++ return ret;
++
++ /* Set Mac address */
++ val = enetaddr[0] << 24 | enetaddr[1] << 16 |
++ enetaddr[2] << 8 | enetaddr[3];
++ writel(val, MAHR);
++
++ val = enetaddr[4] << 8 | enetaddr[5];
++ writel(val, MALR);
++#ifdef CONFIG_RAVB
++ ret = ravb_initialize(bis);
++#endif
++ return ret;
++}
++
++/* V3MZF has KSZ9031RNX */
++int board_phy_config(struct phy_device *phydev)
++{
++ return 0;
++}
++
++int board_mmc_init(bd_t *bis)
++{
++ int ret = -ENODEV;
++#ifdef CONFIG_SH_SDHI
++ /* SDHI2/eMMC */
++ gpio_request(GPIO_FN_MMC_D0, NULL);
++ gpio_request(GPIO_FN_MMC_D1, NULL);
++ gpio_request(GPIO_FN_MMC_D2, NULL);
++ gpio_request(GPIO_FN_MMC_D3, NULL);
++ gpio_request(GPIO_FN_MMC_D4, NULL);
++ gpio_request(GPIO_FN_MMC_D5, NULL);
++ gpio_request(GPIO_FN_MMC_D6, NULL);
++ gpio_request(GPIO_FN_MMC_D7, NULL);
++ gpio_request(GPIO_FN_MMC_CLK, NULL);
++ gpio_request(GPIO_FN_MMC_CMD, NULL);
++ gpio_request(GPIO_FN_MMC_CD, NULL);
++ gpio_request(GPIO_FN_MMC_WP, NULL);
++
++ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 0,
++ SH_SDHI_QUIRK_64BIT_BUF);
++#endif
++ return ret;
++}
++
++int dram_init(void)
++{
++ gd->ram_size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
++
++void dram_init_banksize(void)
++{
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++}
++
++const struct rcar_sysinfo sysinfo = {
++ CONFIG_RCAR_BOARD_STRING
++};
++
++void reset_cpu(ulong addr)
++{
++}
++
++#if defined(CONFIG_DISPLAY_BOARDINFO)
++int checkboard(void)
++{
++ printf("Board: %s\n", sysinfo.board_string);
++ return 0;
++}
++#endif
+diff --git a/configs/v3mzf_defconfig b/configs/v3mzf_defconfig
+new file mode 100644
+index 0000000..49f02e7
+--- /dev/null
++++ b/configs/v3mzf_defconfig
+@@ -0,0 +1,9 @@
++CONFIG_ARM=y
++CONFIG_RCAR_GEN3=y
++CONFIG_DM_SERIAL=y
++CONFIG_TARGET_V3MZF=y
++CONFIG_R8A7797=y
++CONFIG_SPL=y
++CONFIG_SH_SDHI=y
++CONFIG_SPI_FLASH=y
++CONFIG_SPI_FLASH_SPANSION=y
+diff --git a/include/configs/v3mzf.h b/include/configs/v3mzf.h
+new file mode 100644
+index 0000000..8ce53aa
+--- /dev/null
++++ b/include/configs/v3mzf.h
+@@ -0,0 +1,137 @@
++/*
++ * include/configs/v3mzf.h
++ * This file is V3MZF board configuration.
++ * CPU r8a7797.
++ *
++ * Copyright (C) 2017 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __V3MZF_H
++#define __V3MZF_H
++
++#undef DEBUG
++#define CONFIG_RCAR_BOARD_STRING "V3MZF"
++#define CONFIG_RCAR_TARGET_STRING "r8a7797"
++
++#include "rcar-gen3-common.h"
++
++/* Cache Definitions */
++//#define CONFIG_SYS_DCACHE_OFF
++//#define CONFIG_SYS_ICACHE_OFF
++
++/* SCIF */
++#define CONFIG_SCIF_CONSOLE
++#define CONFIG_CONS_SCIF0
++#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
++
++/* [A] Hyper Flash */
++/* use to RPC(SPI Multi I/O Bus Controller) */
++
++ /* underconstruction */
++
++#define CONFIG_SYS_NO_FLASH
++#if defined(CONFIG_SYS_NO_FLASH)
++#define CONFIG_SPI
++#define CONFIG_RCAR_GEN3_QSPI
++#define CONFIG_SH_QSPI_BASE 0xEE200000
++#define CONFIG_CMD_SF
++#define CONFIG_CMD_SPI
++#define CONFIG_SPI_FLASH
++#define CONFIG_SPI_FLASH_SPANSION
++#else
++#undef CONFIG_CMD_SF
++#undef CONFIG_CMD_SPI
++#undef CONFIG_SPI_FLASH
++#undef CONFIG_SPI_FLASH_SPANSION
++#endif
++
++/* Ethernet RAVB */
++#define CONFIG_RAVB
++#define CONFIG_RAVB_PHY_ADDR 0x0
++#define CONFIG_RAVB_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID
++#define CONFIG_NET_MULTI
++#define CONFIG_PHYLIB
++#define CONFIG_PHY_MICREL
++#define CONFIG_BITBANGMII
++#define CONFIG_BITBANGMII_MULTI
++#define CONFIG_SH_ETHER_BITBANG
++
++/* Board Clock */
++/* XTAL_CLK : 33.33MHz */
++#define RCAR_XTAL_CLK 33333333u
++#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK
++/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
++/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */
++#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
++#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2)
++#define CONFIG_S3D2_CLK_FREQ (266666666u/2)
++#define CONFIG_S3D4_CLK_FREQ (266666666u/4)
++
++/* Generic Timer Definitions (use in assembler source) */
++#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
++
++/* Generic Interrupt Controller Definitions */
++#define GICD_BASE (0xF1010000)
++#define GICC_BASE (0xF1020000)
++#define CONFIG_GICV2
++
++/* USB */
++#undef CONFIG_CMD_USB
++
++/* SDHI */
++#define CONFIG_MMC
++#define CONFIG_CMD_MMC
++#define CONFIG_GENERIC_MMC
++#define CONFIG_SH_SDHI_FREQ 200000000
++#define CONFIG_SH_SDHI_MMC
++
++/* ENV setting */
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_SECT_SIZE (256 * 1024)
++#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
++#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
++
++//#define CONFIG_ENV_IS_IN_MMC
++#define CONFIG_ENV_IS_IN_SPI_FLASH
++
++#if defined(CONFIG_ENV_IS_IN_MMC)
++/* Environment in eMMC, at the end of 2nd "boot sector" */
++#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
++#define CONFIG_SYS_MMC_ENV_DEV 0
++#define CONFIG_SYS_MMC_ENV_PART 2
++#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
++/* Environment in QSPI */
++#define CONFIG_ENV_ADDR 0x700000
++#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
++#else
++#define CONFIG_ENV_IS_NOWHERE
++#endif
++
++/* Module clock supply/stop status bits */
++/* MFIS */
++#define CONFIG_SMSTP2_ENA 0x00002000
++/* serial(SCIF0) */
++#define CONFIG_SMSTP3_ENA 0x00000400
++/* INTC-AP, INTC-EX */
++#define CONFIG_SMSTP4_ENA 0x00000180
++
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ "fdt_high=0xffffffffffffffff\0" \
++ "initrd_high=0xffffffffffffffff\0" \
++ "ethact=ravb\0" \
++ "ethaddr=2E:11:22:33:44:55\0"
++
++#define CONFIG_BOOTARGS \
++ "root=/dev/nfs rw ip=dhcp"
++
++#define CONFIG_BOOTCOMMAND \
++ "bootp 0x48080000 Image; tftp 0x48000000 r8a7797-v3mzf.dtb; " \
++ "booti 0x48080000 - 0x48000000"
++
++#define CONFIG_CMD_MEMTEST
++#define CONFIG_SYS_MEMTEST_START 0x40000000
++#define CONFIG_SYS_MEMTEST_END 0x80000000
++
++#endif /* __V3MZF_H */
+--
+1.9.1
+
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/00201-board-renesas-Add-V3HSK-board.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/00201-board-renesas-Add-V3HSK-board.patch
new file mode 100644
index 0000000..dc07609
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/00201-board-renesas-Add-V3HSK-board.patch
@@ -0,0 +1,697 @@
+From 519ee2d3ff6049263277b24dd8326a27a8d102e2 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Tue, 13 Feb 2018 17:17:39 +0300
+Subject: [PATCH] board: renesas: Add V3H Starter Kit board
+
+V3H Starter Kit is a board based on R-Car V3H SoC (R8A7798)
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+---
+ arch/arm/cpu/armv8/Kconfig | 4 +
+ board/renesas/v3hsk/Kconfig | 15 +++
+ board/renesas/v3hsk/Makefile | 10 ++
+ board/renesas/v3hsk/cpld.c | 152 +++++++++++++++++++++++++
+ board/renesas/v3hsk/v3hsk.c | 266 +++++++++++++++++++++++++++++++++++++++++++
+ configs/v3hsk_defconfig | 10 ++
+ include/configs/v3hsk.h | 160 ++++++++++++++++++++++++++
+ 7 files changed, 617 insertions(+)
+ create mode 100644 board/renesas/v3hsk/Kconfig
+ create mode 100644 board/renesas/v3hsk/Makefile
+ create mode 100644 board/renesas/v3hsk/cpld.c
+ create mode 100644 board/renesas/v3hsk/v3hsk.c
+ create mode 100644 configs/v3hsk_defconfig
+ create mode 100644 include/configs/v3hsk.h
+
+diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
+index a2706a6..7309838 100644
+--- a/arch/arm/cpu/armv8/Kconfig
++++ b/arch/arm/cpu/armv8/Kconfig
+@@ -28,6 +28,9 @@ config TARGET_V3MZF
+ config TARGET_CONDOR
+ bool "CONDOR board"
+
++config TARGET_V3HSK
++ bool "V3HSK board"
++
+ endchoice
+
+ config R8A7796X
+@@ -64,5 +67,6 @@ source "board/renesas/eagle/Kconfig"
+ source "board/renesas/v3msk/Kconfig"
+ source "board/renesas/condor/Kconfig"
+ source "board/renesas/v3mzf/Kconfig"
++source "board/renesas/v3hsk/Kconfig"
+
+ endif
+diff --git a/board/renesas/v3hsk/Kconfig b/board/renesas/v3hsk/Kconfig
+new file mode 100644
+index 0000000..2346ee8
+--- /dev/null
++++ b/board/renesas/v3hsk/Kconfig
+@@ -0,0 +1,15 @@
++if TARGET_V3HSK
++
++config SYS_SOC
++ default "rcar_gen3"
++
++config SYS_BOARD
++ default "v3hsk"
++
++config SYS_VENDOR
++ default "renesas"
++
++config SYS_CONFIG_NAME
++ default "v3hsk" if R8A7798
++
++endif
+diff --git a/board/renesas/v3hsk/Makefile b/board/renesas/v3hsk/Makefile
+new file mode 100644
+index 0000000..fb037fe
+--- /dev/null
++++ b/board/renesas/v3hsk/Makefile
+@@ -0,0 +1,10 @@
++#
++# board/renesas/v3hsk/Makefile
++#
++# Copyright (C) 2018 Renesas Electronics Corp.
++# Copyright (C) 2018 Cogent Embedded, Inc.
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y := v3hsk.o ../rcar-gen3-common/common.o cpld.o
+diff --git a/board/renesas/v3hsk/cpld.c b/board/renesas/v3hsk/cpld.c
+new file mode 100644
+index 0000000..7c95534
+--- /dev/null
++++ b/board/renesas/v3hsk/cpld.c
+@@ -0,0 +1,152 @@
++/*
++ * V3HSK board CPLD access support
++ *
++ * Copyright (C) 2018 Renesas Electronics Corporation
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <i2c.h>
++
++#define ADDR_PRODUCT_0 0x0000 /* R */
++#define ADDR_PRODUCT_1 0x0001 /* R */
++#define ADDR_PRODUCT_2 0x0002 /* R */
++#define ADDR_PRODUCT_3 0x0003 /* R */
++#define ADDR_CPLD_VERSION_D 0x0004 /* R */
++#define ADDR_CPLD_VERSION_M 0x0005 /* R */
++#define ADDR_CPLD_VERSION_Y_0 0x0006 /* R */
++#define ADDR_CPLD_VERSION_Y_1 0x0007 /* R */
++#define ADDR_MODE_SET_0 0x0008 /* R */
++#define ADDR_MODE_SET_1 0x0009 /* R */
++#define ADDR_MODE_SET_2 0x000A /* R */
++#define ADDR_MODE_SET_3 0x000B /* R */
++#define ADDR_MODE_SET_4 0x000C /* R */
++#define ADDR_MODE_LAST_0 0x0018 /* R */
++#define ADDR_MODE_LAST_1 0x0019 /* R */
++#define ADDR_MODE_LAST_2 0x001A /* R */
++#define ADDR_MODE_LAST_3 0x001B /* R */
++#define ADDR_MODE_LAST_4 0x001C /* R */
++#define ADDR_DIPSW4 0x0020 /* R */
++#define ADDR_DIPSW5 0x0021 /* R */
++#define ADDR_RESET 0x0024 /* R/W */
++#define ADDR_POWER_CFG 0x0025 /* R/W */
++#define ADDR_PERI_CFG_0 0x0030 /* R/W */
++#define ADDR_PERI_CFG_1 0x0031 /* R/W */
++#define ADDR_PERI_CFG_2 0x0032 /* R/W */
++#define ADDR_PERI_CFG_3 0x0033 /* R/W */
++#define ADDR_LEDS 0x0034 /* R/W */
++#define ADDR_LEDS_CFG 0x0035 /* R/W */
++#define ADDR_UART_CFG 0x0036 /* R/W */
++#define ADDR_UART_STATUS 0x0037 /* R */
++
++#define ADDR_PCB_VERSION_0 0x1000 /* R */
++#define ADDR_PCB_VERSION_1 0x1001 /* R */
++#define ADDR_SOC_VERSION_0 0x1002 /* R */
++#define ADDR_SOC_VERSION_1 0x1003 /* R */
++#define ADDR_PCB_SN_0 0x1004 /* R */
++#define ADDR_PCB_SN_1 0x1005 /* R */
++
++static u16 cpld_read(u16 addr)
++{
++ u8 data;
++
++ /* random flash reads require 2 reads: first read is unreliable */
++ if (addr >= ADDR_PCB_VERSION_0)
++ i2c_read(CONFIG_SYS_I2C_CPLD_ADDR, addr, 2, &data, 1);
++
++ i2c_read(CONFIG_SYS_I2C_CPLD_ADDR, addr, 2, &data, 1);
++
++ return data;
++}
++
++static void cpld_write(u16 addr, u8 data)
++{
++ i2c_write(CONFIG_SYS_I2C_CPLD_ADDR, addr, 2, &data, 1);
++}
++
++static void cpld_init(void)
++{
++ i2c_set_bus_num(0);
++ i2c_init(400000, 0);
++}
++
++static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
++{
++ u16 addr, val;
++
++ cpld_init();
++
++ if (argc == 2 && strcmp(argv[1], "info") == 0) {
++ printf("Product: 0x%08x\n",
++ (cpld_read(ADDR_PRODUCT_3) << 24) |
++ (cpld_read(ADDR_PRODUCT_2) << 16) |
++ (cpld_read(ADDR_PRODUCT_1) << 8) |
++ cpld_read(ADDR_PRODUCT_0));
++ printf("CPLD version: 0x%08x\n",
++ (cpld_read(ADDR_CPLD_VERSION_Y_1) << 24) |
++ (cpld_read(ADDR_CPLD_VERSION_Y_0) << 16) |
++ (cpld_read(ADDR_CPLD_VERSION_M) << 8) |
++ cpld_read(ADDR_CPLD_VERSION_D));
++ printf("Mode setting (MD0..26): 0x%08x\n",
++ (cpld_read(ADDR_MODE_LAST_3) << 24) |
++ (cpld_read(ADDR_MODE_LAST_2) << 16) |
++ (cpld_read(ADDR_MODE_LAST_1) << 8) |
++ cpld_read(ADDR_MODE_LAST_0));
++ printf("DIPSW (SW4, SW5): 0x%02x, 0x%x\n",
++ cpld_read(ADDR_DIPSW4) ^ 0xff,
++ (cpld_read(ADDR_DIPSW5) ^ 0xff) & 0xf);
++ printf("Power config: 0x%08x\n",
++ cpld_read(ADDR_POWER_CFG));
++ printf("Periferals config: 0x%08x\n",
++ (cpld_read(ADDR_PERI_CFG_3) << 24) |
++ (cpld_read(ADDR_PERI_CFG_2) << 16) |
++ (cpld_read(ADDR_PERI_CFG_1) << 8) |
++ cpld_read(ADDR_PERI_CFG_0));
++ printf("PCB version: %d.%d\n",
++ (cpld_read(ADDR_PCB_VERSION_1) >> 8) |
++ (cpld_read(ADDR_PCB_VERSION_0) & 0xff));
++ printf("SOC version: %d.%d\n",
++ (cpld_read(ADDR_SOC_VERSION_1) << 8) |
++ (cpld_read(ADDR_SOC_VERSION_0) & 0xff));
++ printf("PCB S/N: %d\n",
++ (cpld_read(ADDR_PCB_SN_1) << 8) |
++ cpld_read(ADDR_PCB_SN_0));
++ return 0;
++ }
++
++ if (argc < 3)
++ return CMD_RET_USAGE;
++
++ addr = simple_strtoul(argv[2], NULL, 16);
++ if (!(addr >= ADDR_PRODUCT_0 && addr <= ADDR_UART_STATUS)) {
++ printf("cpld invalid addr\n");
++ return CMD_RET_USAGE;
++ }
++
++ if (argc == 3 && strcmp(argv[1], "read") == 0) {
++ printf("0x%x\n", cpld_read(addr));
++ } else if (argc == 4 && strcmp(argv[1], "write") == 0) {
++ val = simple_strtoul(argv[3], NULL, 16);
++ cpld_write(addr, val);
++ }
++
++ return 0;
++}
++
++U_BOOT_CMD(
++ cpld, 4, 1, do_cpld,
++ "CPLD access",
++ "info\n"
++ "cpld read addr\n"
++ "cpld write addr val\n"
++);
++
++void reset_cpu(ulong addr)
++{
++#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_RCAR)
++ cpld_init();
++ cpld_write(ADDR_RESET, 1);
++#endif
++}
+diff --git a/board/renesas/v3hsk/v3hsk.c b/board/renesas/v3hsk/v3hsk.c
+new file mode 100644
+index 0000000..55e965e
+--- /dev/null
++++ b/board/renesas/v3hsk/v3hsk.c
+@@ -0,0 +1,266 @@
++/*
++ * board/renesas/v3hsk/v3hsk.c
++ * This is V3HSK board support.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <malloc.h>
++#include <netdev.h>
++#include <dm.h>
++#include <dm/platform_data/serial_sh.h>
++#include <asm/processor.h>
++#include <asm/mach-types.h>
++#include <asm/io.h>
++#include <asm/errno.h>
++#include <asm/arch/sys_proto.h>
++#include <asm/gpio.h>
++#include <asm/arch/prr_depend.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/rcar_gen3.h>
++#include <asm/arch/rcar-mstp.h>
++#include <asm/arch/sh_sdhi.h>
++#include <i2c.h>
++#include <mmc.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#define SCIF0_MSTP207 (1 << 7)
++#define GETHER_MSTP813 (1 << 13)
++#define RPC_MSTP917 (1 << 17)
++#define SD0_MSTP314 (1 << 14)
++#define I2C0_MSTP931 (1 << 31)
++
++#define SD0CKCR 0xE6150074
++
++#define PFC_PMMR 0xe6060000
++#define PFC_POC1 0xe6060384
++#define POC_MMC_3V3 0x00fff800
++
++void s_init(void)
++{
++ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
++ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
++
++ /* Watchdog init */
++ writel(0xA5A5A500, &rwdt->rwtcsra);
++ writel(0xA5A5A500, &swdt->swtcsra);
++}
++
++int board_early_init_f(void)
++{
++ int freq;
++
++ rcar_prr_init();
++
++ writel(0xa5a5ffff, 0xe6150900);
++ writel(0x5a5a0000, 0xe6150904);
++ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, 0x02000000);
++ /* SCIF0 */
++ mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIF0_MSTP207);
++ /* SDHI0/MMC */
++ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
++#if defined(CONFIG_RAVB)
++ /* RAVB Ethernet */
++ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, RAVB_MSTP812);
++#elif defined(CONFIG_SH_ETHER)
++ /* Gigabit Ethernet */
++ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, GETHER_MSTP813);
++#endif
++ /* QSPI/RPC */
++ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, RPC_MSTP917);
++ /* I2C0 */
++ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, I2C0_MSTP931);
++
++ freq = rcar_get_sdhi_config_clk();
++ writel(freq, SD0CKCR);
++
++ return 0;
++}
++
++int board_init(void)
++{
++ /* address of boot parameters */
++ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
++
++ /* Init PFC controller */
++ pinmux_init();
++#if defined(CONFIG_RAVB)
++ gpio_request(GPIO_GFN_AVB0_AVTP_CAPTURE, NULL);
++ gpio_request(GPIO_GFN_AVB0_AVTP_MATCH, NULL);
++ gpio_request(GPIO_FN_AVB0_LINK, NULL);
++ gpio_request(GPIO_FN_AVB0_PHY_INT, NULL);
++ /* gpio_request(GPIO_FN_AVB0_MAGIC, NULL); - PHY reset gpio */
++ gpio_request(GPIO_FN_AVB0_MDC, NULL);
++ gpio_request(GPIO_FN_AVB0_MDIO, NULL);
++ gpio_request(GPIO_FN_AVB0_TXCREFCLK, NULL);
++ gpio_request(GPIO_FN_AVB0_TD3, NULL);
++ gpio_request(GPIO_FN_AVB0_TD2, NULL);
++ gpio_request(GPIO_FN_AVB0_TD1, NULL);
++ gpio_request(GPIO_FN_AVB0_TD0, NULL);
++ gpio_request(GPIO_FN_AVB0_TXC, NULL);
++ gpio_request(GPIO_FN_AVB0_TX_CTL, NULL);
++ gpio_request(GPIO_FN_AVB0_RD3, NULL);
++ gpio_request(GPIO_FN_AVB0_RD2, NULL);
++ gpio_request(GPIO_FN_AVB0_RD1, NULL);
++ gpio_request(GPIO_FN_AVB0_RD0, NULL);
++ gpio_request(GPIO_FN_AVB0_RXC, NULL);
++ gpio_request(GPIO_FN_AVB0_RX_CTL, NULL);
++ gpio_request(GPIO_IFN_AVB0_AVTP_CAPTURE, NULL);
++ gpio_request(GPIO_FN_AVB0_AVTP_PPS, NULL);
++
++ /* PHY_RST */
++ gpio_request(GPIO_GP_1_16, NULL);
++ gpio_direction_output(GPIO_GP_1_16, 0);
++ mdelay(20);
++ gpio_set_value(GPIO_GP_1_16, 1);
++ udelay(1);
++#elif defined(CONFIG_SH_ETHER)
++ gpio_request(GPIO_FN_GETHER_LINK_A, NULL);
++ gpio_request(GPIO_FN_GETHER_PHY_INT_A, NULL);
++ /* gpio_request(GPIO_FN_GETHER_MAGIC, NULL); - PHY reset gpio */
++ gpio_request(GPIO_FN_GETHER_MDC_A, NULL);
++ gpio_request(GPIO_FN_GETHER_MDIO_A, NULL);
++ gpio_request(GPIO_FN_GETHER_TXCREFCLK, NULL);
++ gpio_request(GPIO_FN_GETHER_TXCREFCLK_MEGA, NULL);
++ gpio_request(GPIO_FN_GETHER_TD3, NULL);
++ gpio_request(GPIO_FN_GETHER_TD2, NULL);
++ gpio_request(GPIO_FN_GETHER_TD1, NULL);
++ gpio_request(GPIO_FN_GETHER_TD0, NULL);
++ gpio_request(GPIO_FN_GETHER_TXC, NULL);
++ gpio_request(GPIO_FN_GETHER_TX_CTL, NULL);
++ gpio_request(GPIO_FN_GETHER_RD3, NULL);
++ gpio_request(GPIO_FN_GETHER_RD2, NULL);
++ gpio_request(GPIO_FN_GETHER_RD1, NULL);
++ gpio_request(GPIO_FN_GETHER_RD0, NULL);
++ gpio_request(GPIO_FN_GETHER_RXC, NULL);
++ gpio_request(GPIO_FN_GETHER_RX_CTL, NULL);
++
++ /* PHY_RST */
++ gpio_request(GPIO_GP_4_22, NULL);
++ gpio_direction_output(GPIO_GP_4_22, 0);
++ mdelay(20);
++ gpio_set_value(GPIO_GP_4_22, 1);
++ udelay(1);
++#endif
++ /* QSPI/RPC */
++ gpio_request(GPIO_FN_QSPI0_SPCLK, NULL);
++ gpio_request(GPIO_FN_QSPI0_MOSI_IO0, NULL);
++ gpio_request(GPIO_FN_QSPI0_MISO_IO1, NULL);
++ gpio_request(GPIO_FN_QSPI0_IO2, NULL);
++ gpio_request(GPIO_FN_QSPI0_IO3, NULL);
++ gpio_request(GPIO_FN_QSPI0_SSL, NULL);
++ gpio_request(GPIO_FN_QSPI1_SPCLK, NULL);
++ gpio_request(GPIO_FN_QSPI1_MOSI_IO0, NULL);
++ gpio_request(GPIO_FN_QSPI1_MISO_IO1, NULL);
++ gpio_request(GPIO_FN_QSPI1_IO2, NULL);
++ gpio_request(GPIO_FN_QSPI1_IO3, NULL);
++ gpio_request(GPIO_FN_QSPI1_SSL, NULL);
++ gpio_request(GPIO_FN_RPC_RESET_N, NULL);
++ gpio_request(GPIO_FN_RPC_WP_N, NULL);
++ gpio_request(GPIO_FN_RPC_INT_N, NULL);
++#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_RCAR)
++ /* I2C0 to access PMIC */
++ gpio_request(GPIO_IFN_SDA0, NULL);
++ gpio_request(GPIO_IFN_SCL0, NULL);
++#endif
++ return 0;
++}
++
++#if defined(CONFIG_RAVB)
++#define MAHR 0xE68005C0
++#define MALR 0xE68005C8
++#elif defined(CONFIG_SH_ETHER)
++#define MAHR 0xE74005C0
++#define MALR 0xE74005C8
++#endif
++int board_eth_init(bd_t *bis)
++{
++ int ret = -ENODEV;
++
++ u32 val;
++ unsigned char enetaddr[6];
++
++ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
++ return ret;
++
++ /* Set Mac address */
++ val = enetaddr[0] << 24 | enetaddr[1] << 16 |
++ enetaddr[2] << 8 | enetaddr[3];
++ writel(val, MAHR);
++
++ val = enetaddr[4] << 8 | enetaddr[5];
++ writel(val, MALR);
++#if defined(CONFIG_RAVB)
++ ret = ravb_initialize(bis);
++#elif defined(CONFIG_SH_ETHER)
++ ret = sh_eth_initialize(bis);
++#endif
++ return ret;
++}
++
++/* V3HSK has KSZ9031RNX */
++int board_phy_config(struct phy_device *phydev)
++{
++ return 0;
++}
++
++int board_mmc_init(bd_t *bis)
++{
++ int ret = -ENODEV;
++#ifdef CONFIG_SH_SDHI
++ u32 val;
++
++ /* SDHI2/eMMC */
++ gpio_request(GPIO_FN_MMC_D0, NULL);
++ gpio_request(GPIO_FN_MMC_D1, NULL);
++ gpio_request(GPIO_FN_MMC_D2, NULL);
++ gpio_request(GPIO_FN_MMC_D3, NULL);
++ gpio_request(GPIO_FN_MMC_D4, NULL);
++ gpio_request(GPIO_FN_MMC_D5, NULL);
++ gpio_request(GPIO_FN_MMC_D6, NULL);
++ gpio_request(GPIO_FN_MMC_D7, NULL);
++ gpio_request(GPIO_FN_MMC_CLK, NULL);
++ gpio_request(GPIO_FN_MMC_CMD, NULL);
++ gpio_request(GPIO_FN_MMC_CD, NULL);
++ gpio_request(GPIO_FN_MMC_WP, NULL);
++
++ val = readl(PFC_POC1);
++ val &= ~POC_MMC_3V3; /* POC = 1.8V */
++ writel(~val, PFC_PMMR);
++ writel(val, PFC_POC1);
++
++ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 0,
++ SH_SDHI_QUIRK_64BIT_BUF);
++#endif
++ return ret;
++}
++
++int dram_init(void)
++{
++ gd->ram_size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
++
++void dram_init_banksize(void)
++{
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++}
++
++const struct rcar_sysinfo sysinfo = {
++ CONFIG_RCAR_BOARD_STRING
++};
++
++#if defined(CONFIG_DISPLAY_BOARDINFO)
++int checkboard(void)
++{
++ printf("Board: %s\n", sysinfo.board_string);
++ return 0;
++}
++#endif
+diff --git a/configs/v3hsk_defconfig b/configs/v3hsk_defconfig
+new file mode 100644
+index 0000000..938ffe9
+--- /dev/null
++++ b/configs/v3hsk_defconfig
+@@ -0,0 +1,10 @@
++CONFIG_ARM=y
++CONFIG_RCAR_GEN3=y
++CONFIG_DM_SERIAL=y
++CONFIG_TARGET_V3HSK=y
++CONFIG_R8A7798=y
++CONFIG_SPL=y
++CONFIG_SH_SDHI=y
++CONFIG_SPI_FLASH=y
++CONFIG_SPI_FLASH_SPANSION=y
++CONFIG_SPI_FLASH_BAR=y
+diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h
+new file mode 100644
+index 0000000..9f7ac49
+--- /dev/null
++++ b/include/configs/v3hsk.h
+@@ -0,0 +1,160 @@
++/*
++ * include/configs/v3hsk.h
++ * This file is V3HSK board configuration.
++ * CPU r8a7798.
++ *
++ * Copyright (C) 2018 Renesas Electronics Corp.
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef __V3HSK_H
++#define __V3HSK_H
++
++#undef DEBUG
++#define CONFIG_RCAR_BOARD_STRING "V3HSK"
++#define CONFIG_RCAR_TARGET_STRING "r8a7798"
++
++#include "rcar-gen3-common.h"
++
++//#define CONFIG_SYS_DCACHE_OFF
++//#define CONFIG_SYS_ICACHE_OFF
++
++/* SCIF */
++#define CONFIG_SCIF_CONSOLE
++#define CONFIG_CONS_SCIF0
++#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
++
++/* [A] Hyper Flash */
++/* use to RPC(SPI Multi I/O Bus Controller) */
++
++ /* underconstruction */
++
++#define CONFIG_SYS_NO_FLASH
++#if defined(CONFIG_SYS_NO_FLASH)
++#define CONFIG_SPI
++#define CONFIG_RCAR_GEN3_QSPI
++#define CONFIG_SH_QSPI_BASE 0xEE200000
++#define CONFIG_CMD_SF
++#define CONFIG_CMD_SPI
++#define CONFIG_SPI_FLASH
++#define CONFIG_SPI_FLASH_SPANSION
++#else
++#undef CONFIG_CMD_SF
++#undef CONFIG_CMD_SPI
++#undef CONFIG_SPI_FLASH
++#undef CONFIG_SPI_FLASH_SPANSION
++#endif
++
++#if 0
++/* Ethernet RAVB */
++#define CONFIG_RAVB
++#define CONFIG_RAVB_PHY_ADDR 0x0
++#define CONFIG_RAVB_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID
++#define CONFIG_NET_MULTI
++#define CONFIG_PHYLIB
++#define CONFIG_PHY_MICREL
++#define CONFIG_BITBANGMII
++#define CONFIG_BITBANGMII_MULTI
++#define CONFIG_SH_ETHER_BITBANG
++#else
++/* GETHER */
++#define CONFIG_NET_MULTI
++#define CONFIG_SH_ETHER
++#define CONFIG_SH_ETHER_USE_PORT 0
++#define CONFIG_SH_ETHER_PHY_ADDR 0x0
++#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID
++#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
++#define CONFIG_SH_ETHER_CACHE_WRITEBACK
++#define CONFIG_SH_ETHER_CACHE_INVALIDATE
++#define CONFIG_PHYLIB
++#define CONFIG_PHY_MICREL
++#define CONFIG_BITBANGMII
++#define CONFIG_BITBANGMII_MULTI
++#endif
++
++/* Board Clock */
++/* XTAL_CLK : 33.33MHz */
++#define RCAR_XTAL_CLK 33333333u
++#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK
++/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
++/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */
++#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
++#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2)
++#define CONFIG_S3D2_CLK_FREQ (266666666u/2)
++#define CONFIG_S3D4_CLK_FREQ (266666666u/4)
++#define CONFIG_S2D2_CLK_FREQ (133333333u)
++
++/* Generic Timer Definitions (use in assembler source) */
++#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
++
++/* Generic Interrupt Controller Definitions */
++#define GICD_BASE (0xF1010000)
++#define GICC_BASE (0xF1020000)
++#define CONFIG_GICV2
++
++/* i2c */
++#define CONFIG_SYS_I2C
++#define CONFIG_SYS_I2C_RCAR
++#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
++#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
++#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
++#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
++#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 1
++#define CONFIG_SYS_I2C_CPLD_ADDR 0x70
++#define CONFIG_HP_CLK_FREQ CONFIG_S2D2_CLK_FREQ
++
++/* USB */
++#undef CONFIG_CMD_USB
++
++/* SDHI */
++#define CONFIG_MMC
++#define CONFIG_CMD_MMC
++#define CONFIG_GENERIC_MMC
++#define CONFIG_SH_SDHI_FREQ 200000000
++#define CONFIG_SH_SDHI_MMC
++
++/* ENV setting */
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_SECT_SIZE (256 * 1024)
++#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
++#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
++
++//#define CONFIG_ENV_IS_IN_MMC
++#define CONFIG_ENV_IS_IN_SPI_FLASH
++
++#if defined(CONFIG_ENV_IS_IN_MMC)
++/* Environment in eMMC, at the end of 2nd "boot sector" */
++#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
++#define CONFIG_SYS_MMC_ENV_DEV 0
++#define CONFIG_SYS_MMC_ENV_PART 2
++#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
++/* Environment in QSPI */
++#define CONFIG_ENV_ADDR 0x700000
++#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
++#else
++#define CONFIG_ENV_IS_NOWHERE
++#endif
++
++/* Module clock supply/stop status bits */
++/* MFIS */
++#define CONFIG_SMSTP2_ENA 0x00002000
++/* serial(SCIF0) */
++#define CONFIG_SMSTP3_ENA 0x00000400
++/* INTC-AP, INTC-EX */
++#define CONFIG_SMSTP4_ENA 0x00000180
++
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ "fdt_high=0xffffffffffffffff\0" \
++ "initrd_high=0xffffffffffffffff\0" \
++ "ethaddr=2E:11:22:33:44:55\0"
++
++#define CONFIG_BOOTARGS \
++ "root=/dev/nfs rw ip=dhcp"
++
++#define CONFIG_BOOTCOMMAND \
++ "bootp 0x48080000 Image; tftp 0x48000000 r8a7798-v3hsk.dtb; " \
++ "booti 0x48080000 - 0x48000000"
++
++#endif /* __V3HSK_H */
+--
+1.9.1
+
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0021-ARM-rcar_gen3-Add-RPC-flash-definitions.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0021-ARM-rcar_gen3-Add-RPC-flash-definitions.patch
index b47c724..cea18c3 100644
--- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0021-ARM-rcar_gen3-Add-RPC-flash-definitions.patch
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0021-ARM-rcar_gen3-Add-RPC-flash-definitions.patch
@@ -17,8 +17,8 @@ index 59d34b8..538cdc2 100644
--- a/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h
+++ b/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h
@@ -78,6 +78,12 @@
- /* SH-I2C */
- #define CONFIG_SYS_I2C_SH_BASE0 0xE60B0000
+ #define CONFIG_SYS_RCAR_I2C2_BASE 0xE6510000
+ #define CONFIG_SYS_RCAR_I2C3_BASE 0xE66D0000
+/* RPC */
+#define CONFIG_SYS_RPC_BASE 0xEE200000
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot_2015.04.bbappend b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot_2015.04.bbappend
index 044c598..9653201 100644
--- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot_2015.04.bbappend
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot_2015.04.bbappend
@@ -15,10 +15,16 @@ SRC_URI_append = " \
file://0009-configs-rcar-gen3-common-Enable-askenv-command.patch \
file://0010-configs-rcar-gen3-common-Enable-hush-parser.patch \
file://0011-configs-rcar-gen3-common-Enable-GPT-support.patch \
+ file://0012-ARM-rcar_gen3-Add-I2C-definitions.patch \
+ file://00121-i2c-rcar_i2c-add-16bit-addressing.patch \
file://0013-mtd-spi-QSPI-flash-support.patch \
file://0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch \
file://0015-board-renesas-Add-V3M-Eagle-board.patch \
file://0017-board-renesas-Add-V3MSK-board.patch \
+ file://0018-arm-renesas-Add-Renesas-R8A7798-SoC-support.patch \
+ file://0019-board-renesas-Add-Condor-board.patch \
+ file://0020-board-renesas-Add-V3MZF-board.patch \
+ file://00201-board-renesas-Add-V3HSK-board.patch \
file://0021-ARM-rcar_gen3-Add-RPC-flash-definitions.patch \
file://0022-mtd-Add-RPC-HyperFlash-support.patch \
file://0023-board-renesas-salvator-x-Enable-RPC-clock.patch \