diff options
| author |   Vladimir Barinov <vladimir.barinov@cogentembedded.com> | 2018-02-06 18:07:25 +0300 |
|---|---|---|
| committer | Vladimir Barinov <vladimir.barinov@cogentembedded.com> | 2018-02-26 23:24:54 +0300 |
| commit | fde2ed05f7f4abdea0fd5622809fd171bc5fae6e (patch) | |
| tree | 6e7dcf0bb6154fef008cfee74f39b8962f64baa8 /meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0051-arm64-renesas-r8a7798-Add-Renesas-R8A7798-SoC-suppor.patch | |
| parent | e2886a6764e9209e81258eafed4c908f887cbca7 (diff) | |
Adds RSE support for V3H IMR
This adds RSE support for V3H IMR
Diffstat (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0051-arm64-renesas-r8a7798-Add-Renesas-R8A7798-SoC-suppor.patch')
| -rw-r--r-- | meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0051-arm64-renesas-r8a7798-Add-Renesas-R8A7798-SoC-suppor.patch | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0051-arm64-renesas-r8a7798-Add-Renesas-R8A7798-SoC-suppor.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0051-arm64-renesas-r8a7798-Add-Renesas-R8A7798-SoC-suppor.patch index 5a27c48..9d0db6d 100644 --- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0051-arm64-renesas-r8a7798-Add-Renesas-R8A7798-SoC-suppor.patch +++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0051-arm64-renesas-r8a7798-Add-Renesas-R8A7798-SoC-suppor.patch @@ -79,7 +79,7 @@ new file mode 100644 index 0000000..e2b3404 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7798.dtsi -@@ -0,0 +1,1628 @@ +@@ -0,0 +1,1630 @@ +/* + * Device Tree Source for the r8a7798 SoC + * @@ -1697,6 +1697,7 @@ index 0000000..e2b3404 + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 707>; + power-domains = <&sysc R8A7798_PD_ALWAYS_ON>; ++ rse; + }; + + imrlx4_ch5: imr-lx4@fe8b0000 { @@ -1705,6 +1706,7 @@ index 0000000..e2b3404 + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 706>; + power-domains = <&sysc R8A7798_PD_ALWAYS_ON>; ++ rse; + }; + }; +}; |