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authorVladimir Barinov <vladimir.barinov@cogentembedded.com>2017-09-25 07:59:11 +0300
committerVladimir Barinov <vladimir.barinov@cogentembedded.com>2017-09-25 07:59:11 +0300
commitc949a23c050f08fbefef44fd2ec3d4926317b9ed (patch)
treea71afbf23169cf31edc93d3326b68aff2551ea16 /meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0077-MOST-dim2-add-timeouts.patch
parent5a76ca6303891c2a21dee88a10d12ba6791e7798 (diff)
Add MOST
Diffstat (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0077-MOST-dim2-add-timeouts.patch')
-rw-r--r--meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0077-MOST-dim2-add-timeouts.patch46
1 files changed, 46 insertions, 0 deletions
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0077-MOST-dim2-add-timeouts.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0077-MOST-dim2-add-timeouts.patch
new file mode 100644
index 0000000..d47c5c6
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0077-MOST-dim2-add-timeouts.patch
@@ -0,0 +1,46 @@
+From f02aa2831e169a9f17eebb2784db4c95944ba927 Mon Sep 17 00:00:00 2001
+From: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
+Date: Mon, 25 Sep 2017 07:13:29 +0300
+Subject: [PATCH] MOST: dim2: add timeouts
+
+Get rid from loop hang if device not functional
+
+Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+---
+ drivers/staging/most/hdm-dim2/dim2_hal.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/staging/most/hdm-dim2/dim2_hal.c b/drivers/staging/most/hdm-dim2/dim2_hal.c
+index 231138c..ee0e307 100644
+--- a/drivers/staging/most/hdm-dim2/dim2_hal.c
++++ b/drivers/staging/most/hdm-dim2/dim2_hal.c
+@@ -18,6 +18,7 @@
+ #include "dim2_errors.h"
+ #include "dim2_reg.h"
+ #include <linux/stddef.h>
++#include <linux/delay.h>
+
+ /*
+ * Size factor for isochronous DBR buffer.
+@@ -148,11 +149,16 @@ static void free_dbr(int offs, int size)
+
+ static void dim2_transfer_madr(u32 val)
+ {
++ int timeout = 1000;
+ dimcb_io_write(&g.dim2->MADR, val);
+
+ /* wait for transfer completion */
+- while ((dimcb_io_read(&g.dim2->MCTL) & 1) != 1)
++ while ((dimcb_io_read(&g.dim2->MCTL) & 1) != 1) {
++ if (--timeout == 0)
++ break;
++ udelay(1);
+ continue;
++ }
+
+ dimcb_io_write(&g.dim2->MCTL, 0); /* clear transfer complete */
+ }
+--
+1.9.1
+