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authorHarunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>2018-01-19 20:43:09 +0900
committerHarunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>2018-01-19 20:43:09 +0900
commit2e1a7e39e012ea4436c819f46cfcac05fb161184 (patch)
tree094a98fe4f8a2970fdd7a86e1562125f096db049 /meta-rcar-gen3-adas/recipes-kernel/linux
parent89ae3df5fc1ec66b573f724c0e462bde0eabe783 (diff)
parent87b938882b4c672c775c7a0908f4a8b711a16c95 (diff)
Merge remote-tracking branch 'cogent/v2.23.1' into test
Change-Id: I2615a0e01b209fb359245a56996185e046cdb94a Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
Diffstat (limited to 'meta-rcar-gen3-adas/recipes-kernel/linux')
-rw-r--r--meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch229
-rw-r--r--meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0030-Gen3-LVDS-cameras.patch1123
-rw-r--r--meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch2263
-rw-r--r--meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0050-arm64-dts-renesas-r8a779x-add-IMP-nodes.patch73
-rw-r--r--meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0082-gpio-pca953x-fix-interrupt-trigger.patch28
-rw-r--r--meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/eagle.cfg1
-rw-r--r--meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/ulcb.cfg5
-rw-r--r--meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/v3msk.cfg1
-rw-r--r--meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend6
9 files changed, 3407 insertions, 322 deletions
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch
index d6726a3..ffe7684 100644
--- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0018-arm64-renesas-r8a7797-Add-Renesas-R8A7797-SoC-suppor.patch
@@ -8,10 +8,10 @@ This adds Renesas R8A7797 SoC support
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
arch/arm64/Kconfig.platforms | 6 +
- arch/arm64/boot/dts/renesas/r8a7797.dtsi | 1002 ++++++++++
+ arch/arm64/boot/dts/renesas/r8a7797.dtsi | 1156 +++++++++++
drivers/clk/renesas/Kconfig | 1 +
drivers/clk/renesas/Makefile | 1 +
- drivers/clk/renesas/r8a7797-cpg-mssr.c | 222 +++
+ drivers/clk/renesas/r8a7797-cpg-mssr.c | 231 +++
drivers/clk/renesas/rcar-gen3-cpg.c | 41 +-
drivers/clk/renesas/rcar-gen3-cpg.h | 6 +
drivers/clk/renesas/renesas-cpg-mssr.c | 6 +
@@ -34,7 +34,7 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
drivers/pinctrl/sh-pfc/Kconfig | 5 +
drivers/pinctrl/sh-pfc/Makefile | 1 +
drivers/pinctrl/sh-pfc/core.c | 7 +
- drivers/pinctrl/sh-pfc/pfc-r8a7797.c | 2586 +++++++++++++++++++++++++
+ drivers/pinctrl/sh-pfc/pfc-r8a7797.c | 2628 +++++++++++++++++++++++++
drivers/pinctrl/sh-pfc/sh_pfc.h | 12 +
drivers/soc/renesas/Makefile | 4 +
drivers/soc/renesas/r8a7797-sysc.c | 39 +
@@ -47,7 +47,7 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
drivers/thermal/rcar_gen3_thermal.c | 29 +
include/dt-bindings/clock/r8a7797-cpg-mssr.h | 48 +
include/dt-bindings/power/r8a7797-sysc.h | 32 +
- 40 files changed, 4281 insertions(+), 29 deletions(-)
+ 40 files changed, 4486 insertions(+), 29 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r8a7797.dtsi
create mode 100644 drivers/clk/renesas/r8a7797-cpg-mssr.c
create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7797.c
@@ -74,10 +74,10 @@ index ebe0a37..d3b6771 100644
help
diff --git a/arch/arm64/boot/dts/renesas/r8a7797.dtsi b/arch/arm64/boot/dts/renesas/r8a7797.dtsi
new file mode 100644
-index 0000000..6eaa5ba
+index 0000000..0dd374f
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7797.dtsi
-@@ -0,0 +1,1002 @@
+@@ -0,0 +1,1156 @@
+/*
+ * Device Tree Source for the r8a7797 SoC
+ *
@@ -577,6 +577,158 @@ index 0000000..6eaa5ba
+ };
+ };
+
++ cmt0: timer@ffca0000 {
++ compatible = "renesas,cmt-48-r8a7797", "renesas,cmt-48-gen2";
++ reg = <0 0xffca0000 0 0x1004>;
++ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 303>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>;
++
++ renesas,channels-mask = <0x60>;
++
++ status = "disabled";
++ };
++
++ cmt1: timer@e6130000 {
++ compatible = "renesas,cmt-48-r8a7797", "renesas,cmt-48-gen2";
++ reg = <0 0xe6130000 0 0x1004>;
++ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 302>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>;
++
++ renesas,channels-mask = <0xff>;
++
++ status = "disabled";
++ };
++
++ cmt2: timer@e6140000 {
++ compatible = "renesas,cmt-48-r8a7797", "renesas,cmt-48-gen2";
++ reg = <0 0xe6140000 0 0x1004>;
++ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 301>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>;
++
++ renesas,channels-mask = <0xff>;
++
++ status = "disabled";
++ };
++
++ cmt3: timer@e6148000 {
++ compatible = "renesas,cmt-48-r8a7797", "renesas,cmt-48-gen2";
++ reg = <0 0xe6148000 0 0x1004>;
++ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 300>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>;
++
++ renesas,channels-mask = <0xff>;
++
++ status = "disabled";
++ };
++
++ tpu: pwm@e6e80000 {
++ compatible = "renesas,tpu-r8a7797", "renesas,tpu";
++ reg = <0 0xe6e80000 0 0x100>;
++ clocks = <&cpg CPG_MOD 304>;
++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>;
++ status = "disabled";
++ #pwm-cells = <4>;
++ };
++
++ tmu0: timer@e61e0000 {
++ compatible = "renesas,tmu-r8a7797", "renesas,tmu";
++ reg = <0 0xe61e0000 0 0x30>;
++ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 125>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>;
++ #renesas,channels = <3>;
++ status = "disabled";
++ };
++
++ tmu1: timer@e6fc0000 {
++ compatible = "renesas,tmu-r8a7797", "renesas,tmu";
++ reg = <0 0xe6fc0000 0 0x30>;
++ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 124>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>;
++ #renesas,channels = <3>;
++ status = "disabled";
++ };
++
++ tmu2: timer@e6fd0000 {
++ compatible = "renesas,tmu-r8a7797", "renesas,tmu";
++ reg = <0 0xe6fd0000 0 0x30>;
++ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 123>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>;
++ #renesas,channels = <3>;
++ status = "disabled";
++ };
++
++ tmu3: timer@e6fe0000 {
++ compatible = "renesas,tmu-r8a7797", "renesas,tmu";
++ reg = <0 0xe6fe0000 0 0x30>;
++ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 122>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>;
++ #renesas,channels = <3>;
++ status = "disabled";
++ };
++
++ tmu4: timer@ffc00000 {
++ compatible = "renesas,tmu-r8a7797", "renesas,tmu";
++ reg = <0 0xffc00000 0 0x30>;
++ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 121>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A7797_PD_ALWAYS_ON>;
++ #renesas,channels = <3>;
++ status = "disabled";
++ };
++
+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a7797", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 0x10>;
@@ -970,8 +1122,10 @@ index 0000000..6eaa5ba
+ };
+
+ tsc1: thermal@0xe6190000 {
-+ compatible = "renesas,thermal-r8a7797";
-+ reg = <0 0xe6190000 0 0x5c>;
++ compatible = "renesas,rcar-thermal";
++ reg = <0 0xe6190000 0 0x14
++ 0 0xe6190100 0 0x38>;
++
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; /* SPI67~69:Thermal Sensor.ch0~2 */
@@ -1106,10 +1260,10 @@ index 2c224e9..c2ef11e 100644
obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o clk-div6.o
diff --git a/drivers/clk/renesas/r8a7797-cpg-mssr.c b/drivers/clk/renesas/r8a7797-cpg-mssr.c
new file mode 100644
-index 0000000..29dfe4a
+index 0000000..6f481a4
--- /dev/null
+++ b/drivers/clk/renesas/r8a7797-cpg-mssr.c
-@@ -0,0 +1,222 @@
+@@ -0,0 +1,231 @@
+/*
+ * r8a7797 Clock Pulse Generator / Module Standby and Software Reset
+ *
@@ -1204,6 +1358,10 @@ index 0000000..29dfe4a
+};
+
+static const struct mssr_mod_clk r8a7797_mod_clks[] __initconst = {
++ DEF_MOD("tmu4", 121, R8A7797_CLK_S2D2),
++ DEF_MOD("tmu3", 122, R8A7797_CLK_S2D2),
++ DEF_MOD("tmu2", 123, R8A7797_CLK_S2D2),
++ DEF_MOD("tmu1", 124, R8A7797_CLK_S2D2),
+ DEF_MOD("ivcp1e", 127, R8A7797_CLK_S2D1),
+ DEF_MOD("scif4", 203, R8A7797_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("scif3", 204, R8A7797_CLK_S2D4), /* @@ H3=S3D4 */
@@ -1216,6 +1374,11 @@ index 0000000..29dfe4a
+ DEF_MOD("mfis", 213, R8A7797_CLK_S2D2), /* @@ H3=S3D2 */
+ DEF_MOD("sys-dmac2", 217, R8A7797_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("sys-dmac1", 218, R8A7797_CLK_S2D1), /* @@ H3=S3D1 */
++ DEF_MOD("cmt3", 300, R8A7797_CLK_R),
++ DEF_MOD("cmt2", 301, R8A7797_CLK_R),
++ DEF_MOD("cmt1", 302, R8A7797_CLK_R),
++ DEF_MOD("cmt0", 303, R8A7797_CLK_R),
++ DEF_MOD("tpu", 304, R8A7797_CLK_S2D4),
+ DEF_MOD("sdif", 314, R8A7797_CLK_SD0),
+ DEF_MOD("rwdt0", 402, R8A7797_CLK_R),
+ DEF_MOD("intc-ex", 407, R8A7797_CLK_CP),
@@ -2166,10 +2329,10 @@ index a6a8f65..9aba933 100644
.compatible = "renesas,pfc-sh73a0",
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7797.c b/drivers/pinctrl/sh-pfc/pfc-r8a7797.c
new file mode 100644
-index 0000000..9b6127f
+index 0000000..6b83f44
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7797.c
-@@ -0,0 +1,2586 @@
+@@ -0,0 +1,2628 @@
+/*
+ * R8A7797 processor support - PFC hardware block.
+ *
@@ -3572,6 +3735,36 @@ index 0000000..9b6127f
+ MSIOF3_RXD_MARK,
+};
+
++/* - TPU ------------------------------------------------------------------- */
++static const unsigned int tpu_to0_pins[] = {
++ /* TPU0TO0 */
++ RCAR_GP_PIN(4, 0),
++};
++static const unsigned int tpu_to0_mux[] = {
++ TPU0TO0_MARK,
++};
++static const unsigned int tpu_to1_pins[] = {
++ /* TPU0TO1 */
++ RCAR_GP_PIN(4, 1),
++};
++static const unsigned int tpu_to1_mux[] = {
++ TPU0TO1_MARK,
++};
++static const unsigned int tpu_to2_pins[] = {
++ /* TPU0TO2 */
++ RCAR_GP_PIN(4, 2),
++};
++static const unsigned int tpu_to2_mux[] = {
++ TPU0TO2_MARK,
++};
++static const unsigned int tpu_to3_pins[] = {
++ /* TPU0TO3 */
++ RCAR_GP_PIN(4, 3),
++};
++static const unsigned int tpu_to3_mux[] = {
++ TPU0TO3_MARK,
++};
++
+/* - PWM0 ------------------------------------------------------------------- */
+static const unsigned int pwm0_a_pins[] = {
+ /* PWM0 */
@@ -4062,6 +4255,10 @@ index 0000000..9b6127f
+ SH_PFC_PIN_GROUP(msiof3_ss2),
+ SH_PFC_PIN_GROUP(msiof3_txd),
+ SH_PFC_PIN_GROUP(msiof3_rxd),
++ SH_PFC_PIN_GROUP(tpu_to0),
++ SH_PFC_PIN_GROUP(tpu_to1),
++ SH_PFC_PIN_GROUP(tpu_to2),
++ SH_PFC_PIN_GROUP(tpu_to3),
+ SH_PFC_PIN_GROUP(pwm0_a),
+ SH_PFC_PIN_GROUP(pwm0_b),
+ SH_PFC_PIN_GROUP(pwm1_a),
@@ -4246,6 +4443,13 @@ index 0000000..9b6127f
+ "msiof3_rxd",
+};
+
++static const char * const tpu_groups[] = {
++ "tpu_to0",
++ "tpu_to1",
++ "tpu_to2",
++ "tpu_to3",
++};
++
+static const char * const pwm0_groups[] = {
+ "pwm0_a",
+ "pwm0_b",
@@ -4361,6 +4565,7 @@ index 0000000..9b6127f
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(msiof3),
++ SH_PFC_FUNCTION(tpu),
+ SH_PFC_FUNCTION(pwm0),
+ SH_PFC_FUNCTION(pwm1),
+ SH_PFC_FUNCTION(pwm2),
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0030-Gen3-LVDS-cameras.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0030-Gen3-LVDS-cameras.patch
index 75b3fb9..00928d1 100644
--- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0030-Gen3-LVDS-cameras.patch
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0030-Gen3-LVDS-cameras.patch
@@ -5,38 +5,42 @@ Subject: [PATCH] Gen3: LVDS cameras
This add Gen3 LVDS cameras support:
- deserializers: MAX9286, TI964, TI954, TI960
-- cameras: ov10635, ov490+ov10640, ov495+OV2775, ar0132
+- cameras: ov10635, ov490+ov10640, ov495+OV2775, ar0132, ap0101+ar014x
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
drivers/media/i2c/soc_camera/Kconfig | 47 +
drivers/media/i2c/soc_camera/Makefile | 7 +
+ drivers/media/i2c/soc_camera/ap0101_ar014x.c | 536 ++++++++++
+ drivers/media/i2c/soc_camera/ap0101_ar014x.h | 28 +
drivers/media/i2c/soc_camera/ar0132.c | 581 +++++++++++
drivers/media/i2c/soc_camera/ar0132.h | 213 ++++
- drivers/media/i2c/soc_camera/max9286_max9271.c | 607 ++++++++++++
- drivers/media/i2c/soc_camera/max9286_max9271.h | 244 +++++
+ drivers/media/i2c/soc_camera/max9286.c | 672 +++++++++++++
+ drivers/media/i2c/soc_camera/max9286.h | 244 +++++
drivers/media/i2c/soc_camera/ov10635.c | 758 ++++++++++++++
- drivers/media/i2c/soc_camera/ov10635.h | 1139 ++++++++++++++++++++++
+ drivers/media/i2c/soc_camera/ov10635.h | 1139 +++++++++++++++++++++
drivers/media/i2c/soc_camera/ov10635_debug.h | 54 +
- drivers/media/i2c/soc_camera/ov106xx.c | 106 ++
- drivers/media/i2c/soc_camera/ov490_ov10640.c | 1092 +++++++++++++++++++++
- drivers/media/i2c/soc_camera/ov490_ov10640.h | 93 ++
- drivers/media/i2c/soc_camera/ov495_ov2775.c | 658 +++++++++++++
+ drivers/media/i2c/soc_camera/ov106xx.c | 117 +++
+ drivers/media/i2c/soc_camera/ov490_ov10640.c | 1156 ++++++++++++++++++++++
+ drivers/media/i2c/soc_camera/ov490_ov10640.h | 102 ++
+ drivers/media/i2c/soc_camera/ov495_ov2775.c | 658 ++++++++++++
drivers/media/i2c/soc_camera/ov495_ov2775.h | 23 +
drivers/media/i2c/soc_camera/ti954_ti9x3.c | 431 ++++++++
- drivers/media/i2c/soc_camera/ti964_ti9x3.c | 399 ++++++++
+ drivers/media/i2c/soc_camera/ti964_ti9x3.c | 400 ++++++++
drivers/media/i2c/soc_camera/ti9x4_ti9x3.h | 153 +++
drivers/media/platform/soc_camera/rcar_csi2.c | 297 ++++--
- drivers/media/platform/soc_camera/rcar_vin.c | 174 +++-
+ drivers/media/platform/soc_camera/rcar_vin.c | 211 +++-
drivers/media/platform/soc_camera/soc_camera.c | 17 +-
drivers/media/platform/soc_camera/soc_mediabus.c | 16 +
include/media/drv-intf/soc_mediabus.h | 3 +
include/media/soc_camera.h | 1 +
- 23 files changed, 7004 insertions(+), 109 deletions(-)
+ 25 files changed, 7755 insertions(+), 109 deletions(-)
+ create mode 100644 drivers/media/i2c/soc_camera/ap0101_ar014x.c
+ create mode 100644 drivers/media/i2c/soc_camera/ap0101_ar014x.h
create mode 100644 drivers/media/i2c/soc_camera/ar0132.c
create mode 100644 drivers/media/i2c/soc_camera/ar0132.h
- create mode 100644 drivers/media/i2c/soc_camera/max9286_max9271.c
- create mode 100644 drivers/media/i2c/soc_camera/max9286_max9271.h
+ create mode 100644 drivers/media/i2c/soc_camera/max9286.c
+ create mode 100644 drivers/media/i2c/soc_camera/max9286.h
create mode 100644 drivers/media/i2c/soc_camera/ov10635.c
create mode 100644 drivers/media/i2c/soc_camera/ov10635.h
create mode 100644 drivers/media/i2c/soc_camera/ov10635_debug.h
@@ -108,12 +112,12 @@ index 7704bcf..82da59f 100644
tristate "mt9m001 support"
depends on SOC_CAMERA && I2C
diff --git a/drivers/media/i2c/soc_camera/Makefile b/drivers/media/i2c/soc_camera/Makefile
-index 6f994f9..7d4c1ab 100644
+index 6f994f9..e88f6a9 100644
--- a/drivers/media/i2c/soc_camera/Makefile
+++ b/drivers/media/i2c/soc_camera/Makefile
@@ -1,8 +1,15 @@
obj-$(CONFIG_SOC_CAMERA_IMX074) += imx074.o
-+obj-$(CONFIG_SOC_CAMERA_MAX9286_MAX9271) += max9286_max9271.o
++obj-$(CONFIG_SOC_CAMERA_MAX9286_MAX9271) += max9286.o
+obj-$(CONFIG_SOC_CAMERA_TI964_TI9X3) += ti964_ti9x3.o
+obj-$(CONFIG_SOC_CAMERA_TI954_TI9X3) += ti954_ti9x3.o
obj-$(CONFIG_SOC_CAMERA_MT9M001) += mt9m001.o
@@ -127,14 +131,590 @@ index 6f994f9..7d4c1ab 100644
obj-$(CONFIG_SOC_CAMERA_OV2640) += ov2640.o
obj-$(CONFIG_SOC_CAMERA_OV5642) += ov5642.o
obj-$(CONFIG_SOC_CAMERA_OV6650) += ov6650.o
+diff --git a/drivers/media/i2c/soc_camera/ap0101_ar014x.c b/drivers/media/i2c/soc_camera/ap0101_ar014x.c
+new file mode 100644
+index 0000000..4757657
+--- /dev/null
++++ b/drivers/media/i2c/soc_camera/ap0101_ar014x.c
+@@ -0,0 +1,536 @@
++/*
++ * ON Semiconductor AP0101-AR014X sensor camera driver
++ *
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++#include <linux/delay.h>
++#include <linux/init.h>
++#include <linux/i2c.h>
++#include <linux/module.h>
++#include <linux/videodev2.h>
++
++#include <media/soc_camera.h>
++#include <media/v4l2-common.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-of.h>
++
++#include "ap0101_ar014x.h"
++
++#define AP0101_I2C_ADDR 0x5d
++
++#define AP0101_PID 0x0000
++#define AP0101_VERSION_REG 0x0160
++
++#define AP0101_MEDIA_BUS_FMT MEDIA_BUS_FMT_YUYV8_2X8
++
++struct ap0101_priv {
++ struct v4l2_subdev sd;
++ struct v4l2_ctrl_handler hdl;
++ struct media_pad pad;
++ struct v4l2_rect rect;
++ int init_complete;
++ u8 id[6];
++ int exposure;
++ int gain;
++ int autogain;
++ /* serializers */
++ int max9286_addr;
++ int max9271_addr;
++ int port;
++ int gpio_resetb;
++ int gpio_fsin;
++
++};
++
++static inline struct ap0101_priv *to_ap0101(const struct i2c_client *client)
++{
++ return container_of(i2c_get_clientdata(client), struct ap0101_priv, sd);
++}
++
++static void ap0101_s_port(struct i2c_client *client, int fwd_en)
++{
++ struct ap0101_priv *priv = to_ap0101(client);
++ int tmp_addr;
++
++ if (priv->max9286_addr) {
++ tmp_addr = client->addr;
++ client->addr = priv->max9286_addr; /* Deserializer I2C address */
++ reg8_write(client, 0x0a, fwd_en ? 0x11 << priv->port : 0); /* Enable/disable reverse/forward control for this port */
++ client->addr = tmp_addr;
++ };
++}
++
++static int ap0101_set_regs(struct i2c_client *client,
++ const struct ap0101_reg *regs, int nr_regs)
++{
++ int i;
++
++ for (i = 0; i < nr_regs; i++) {
++ if (regs[i].reg == AP0101_DELAY) {
++ mdelay(regs[i].val);
++ continue;
++ }
++
++ reg16_write16(client, regs[i].reg, regs[i].val);
++ }
++
++ return 0;
++}
++
++static int ap0101_s_stream(struct v4l2_subdev *sd, int enable)
++{
++ return 0;
++}
++
++static int ap0101_get_fmt(struct v4l2_subdev *sd,
++ struct v4l2_subdev_pad_config *cfg,
++ struct v4l2_subdev_format *format)
++{
++ struct v4l2_mbus_framefmt *mf = &format->format;
++ struct i2c_client *client = v4l2_get_subdevdata(sd);
++ struct ap0101_priv *priv = to_ap0101(client);
++
++ if (format->pad)
++ return -EINVAL;
++
++ mf->width = priv->rect.width;
++ mf->height = priv->rect.height;
++ mf->code = AP0101_MEDIA_BUS_FMT;
++ mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
++ mf->field = V4L2_FIELD_NONE;
++
++ return 0;
++}
++
++static int ap0101_set_fmt(struct v4l2_subdev *sd,
++ struct v4l2_subdev_pad_config *cfg,
++ struct v4l2_subdev_format *format)
++{
++ struct v4l2_mbus_framefmt *mf = &format->format;
++
++ mf->code = AP0101_MEDIA_BUS_FMT;
++ mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
++ mf->field = V4L2_FIELD_NONE;
++
++ if (format->which == V4L2_SUBDEV_FORMAT_TRY)
++ cfg->try_fmt = *mf;
++
++ return 0;
++}
++
++static int ap0101_enum_mbus_code(struct v4l2_subdev *sd,
++ struct v4l2_subdev_pad_config *cfg,
++ struct v4l2_subdev_mbus_code_enum *code)
++{
++ if (code->pad || code->index > 0)
++ return -EINVAL;
++
++ code->code = AP0101_MEDIA_BUS_FMT;
++
++ return 0;
++}
++
++static int ap0101_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
++{
++ struct i2c_client *client = v4l2_get_subdevdata(sd);
++ struct ap0101_priv *priv = to_ap0101(client);
++
++ memcpy(edid->edid, priv->id, 6);
++
++ edid->edid[6] = 0xff;
++ edid->edid[7] = client->addr;
++ edid->edid[8] = AP0101_VERSION_REG >> 8;
++ edid->edid[9] = AP0101_VERSION_REG & 0xff;
++
++ return 0;
++}
++
++static int ap0101_set_selection(struct v4l2_subdev *sd,
++ struct v4l2_subdev_pad_config *cfg,
++ struct v4l2_subdev_selection *sel)
++{
++ struct v4l2_rect *rect = &sel->r;
++ struct i2c_client *client = v4l2_get_subdevdata(sd);
++ struct ap0101_priv *priv = to_ap0101(client);
++
++ if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
++ sel->target != V4L2_SEL_TGT_CROP)
++ return -EINVAL;
++
++ rect->left = ALIGN(rect->left, 2);
++ rect->top = ALIGN(rect->top, 2);
++ rect->width = ALIGN(rect->width, 2);
++ rect->height = ALIGN(rect->height, 2);
++
++ if ((rect->left + rect->width > AP0101_MAX_WIDTH) ||
++ (rect->top + rect->height > AP0101_MAX_HEIGHT))
++ *rect = priv->rect;
++
++ priv->rect.left = rect->left;
++ priv->rect.top = rect->top;
++ priv->rect.width = rect->width;
++ priv->rect.height = rect->height;
++
++ return 0;
++}
++
++static int ap0101_get_selection(struct v4l2_subdev *sd,
++ struct v4l2_subdev_pad_config *cfg,
++ struct v4l2_subdev_selection *sel)
++{
++ struct i2c_client *client = v4l2_get_subdevdata(sd);
++ struct ap0101_priv *priv = to_ap0101(client);
++
++ if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
++ return -EINVAL;
++
++ switch (sel->target) {
++ case V4L2_SEL_TGT_CROP_BOUNDS:
++ sel->r.left = 0;
++ sel->r.top = 0;
++ sel->r.width = AP0101_MAX_WIDTH;
++ sel->r.height = AP0101_MAX_HEIGHT;
++ return 0;
++ case V4L2_SEL_TGT_CROP_DEFAULT:
++ sel->r.left = 0;
++ sel->r.top = 0;
++ sel->r.width = AP0101_MAX_WIDTH;
++ sel->r.height = AP0101_MAX_HEIGHT;
++ return 0;
++ case V4L2_SEL_TGT_CROP:
++ sel->r = priv->rect;
++ return 0;
++ default:
++ return -EINVAL;
++ }
++}
++
++static int ap0101_g_mbus_config(struct v4l2_subdev *sd,
++ struct v4l2_mbus_config *cfg)
++{
++ cfg->flags = V4L2_MBUS_CSI2_1_LANE | V4L2_MBUS_CSI2_CHANNEL_0 |
++ V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
++ cfg->type = V4L2_MBUS_CSI2;
++
++ return 0;
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ap0101_g_register(struct v4l2_subdev *sd,
++ struct v4l2_dbg_register *reg)
++{
++ struct i2c_client *client = v4l2_get_subdevdata(sd);
++ int ret;
++ u16 val = 0;
++
++ ret = reg16_read16(client, (u16)reg->reg, &val);
++ if (ret < 0)
++ return ret;
++
++ reg->val = val;
++ reg->size = sizeof(u16);
++
++ return 0;
++}
++
++static int ap0101_s_register(struct v4l2_subdev *sd,
++ const struct v4l2_dbg_register *reg)
++{
++ struct i2c_client *client = v4l2_get_subdevdata(sd);
++
++ return reg16_write16(client, (u16)reg->reg, (u16)reg->val);
++}
++#endif
++
++static struct v4l2_subdev_core_ops ap0101_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++ .g_register = ap0101_g_register,
++ .s_register = ap0101_s_register,
++#endif
++};
++
++static int ap0101_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++ struct v4l2_subdev *sd = to_sd(ctrl);
++ struct i2c_client *client = v4l2_get_subdevdata(sd);
++ struct ap0101_priv *priv = to_ap0101(client);
++ int ret = -EINVAL;
++
++ if (!priv->init_complete)
++ return 0;
++
++ switch (ctrl->id) {
++ case V4L2_CID_BRIGHTNESS:
++ case V4L2_CID_CONTRAST:
++ case V4L2_CID_SATURATION:
++ case V4L2_CID_HUE:
++ case V4L2_CID_GAMMA:
++ case V4L2_CID_SHARPNESS:
++ case V4L2_CID_AUTOGAIN:
++ case V4L2_CID_GAIN:
++ case V4L2_CID_EXPOSURE:
++ case V4L2_CID_HFLIP:
++ case V4L2_CID_VFLIP:
++ break;
++ }
++
++ return ret;
++}
++
++static const struct v4l2_ctrl_ops ap0101_ctrl_ops = {
++ .s_ctrl = ap0101_s_ctrl,
++};
++
++static struct v4l2_subdev_video_ops ap0101_video_ops = {
++ .s_stream = ap0101_s_stream,
++ .g_mbus_config = ap0101_g_mbus_config,
++};
++
++static const struct v4l2_subdev_pad_ops ap0101_subdev_pad_ops = {
++ .get_edid = ap0101_get_edid,
++ .enum_mbus_code = ap0101_enum_mbus_code,
++ .get_selection = ap0101_get_selection,
++ .set_selection = ap0101_set_selection,
++ .get_fmt = ap0101_get_fmt,
++ .set_fmt = ap0101_set_fmt,
++};
++
++static struct v4l2_subdev_ops ap0101_subdev_ops = {
++ .core = &ap0101_core_ops,
++ .video = &ap0101_video_ops,
++ .pad = &ap0101_subdev_pad_ops,
++};
++
++static void ap0101_otp_id_read(struct i2c_client *client)
++{
++}
++
++static ssize_t ap0101_otp_id_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct v4l2_subdev *sd = i2c_get_clientdata(to_i2c_client(dev));
++ struct i2c_client *client = v4l2_get_subdevdata(sd);
++ struct ap0101_priv *priv = to_ap0101(client);
++
++ return snprintf(buf, 32, "%02x:%02x:%02x:%02x:%02x:%02x\n",
++ priv->id[0], priv->id[1], priv->id[2], priv->id[3], priv->id[4], priv->id[5]);
++}
++
++static DEVICE_ATTR(otp_id_ap0101, S_IRUGO, ap0101_otp_id_show, NULL);
++
++static int ap0101_initialize(struct i2c_client *client)
++{
++ struct ap0101_priv *priv = to_ap0101(client);
++ u16 pid = 0;
++ int ret = 0;
++
++ ap0101_s_port(client, 1);
++
++ /* check and show model ID */
++ reg16_read16(client, AP0101_PID, &pid);
++
++ if (pid != AP0101_VERSION_REG) {
++ dev_dbg(&client->dev, "Product ID error %x\n", pid);
++ ret = -ENODEV;
++ goto err;
++ }
++
++ /* Program wizard registers */
++ ap0101_set_regs(client, ap0101_regs_wizard, ARRAY_SIZE(ap0101_regs_wizard));
++
++ /* Read OTP IDs */
++ ap0101_otp_id_read(client);
++
++ dev_info(&client->dev, "ap0101 PID %x, res %dx%d, OTP_ID %02x:%02x:%02x:%02x:%02x:%02x\n",
++ pid, AP0101_MAX_WIDTH, AP0101_MAX_HEIGHT, priv->id[0], priv->id[1], priv->id[2], priv->id[3], priv->id[4], priv->id[5]);
++err:
++ ap0101_s_port(client, 0);
++
++ return ret;
++}
++
++static int ap0101_parse_dt(struct device_node *np, struct ap0101_priv *priv)
++{
++ struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
++ int i;
++ struct device_node *endpoint = NULL, *rendpoint = NULL;
++ int tmp_addr = 0;
++
++ for (i = 0; ; i++) {
++ endpoint = of_graph_get_next_endpoint(np, endpoint);
++ if (!endpoint)
++ break;
++
++ of_node_put(endpoint);
++
++ rendpoint = of_parse_phandle(endpoint, "remote-endpoint", 0);
++ if (!rendpoint)
++ continue;
++
++ if (!of_property_read_u32(rendpoint, "max9271-addr", &priv->max9271_addr) &&
++ !of_property_read_u32(rendpoint->parent->parent, "reg", &priv->max9286_addr) &&
++ !kstrtouint(strrchr(rendpoint->full_name, '@') + 1, 0, &priv->port))
++ break;
++ }
++
++ if (!priv->max9286_addr) {
++ dev_err(&client->dev, "deserializer does not present for AP0101\n");
++ return -EINVAL;
++ }
++
++ ap0101_s_port(client, 1);
++
++ /* setup I2C translator address */
++ tmp_addr = client->addr;
++ if (priv->max9286_addr) {
++ client->addr = priv->max9271_addr; /* Serializer I2C address */
++
++ reg8_write(client, 0x09, tmp_addr << 1); /* Sensor translated I2C address */
++ reg8_write(client, 0x0A, AP0101_I2C_ADDR << 1); /* Sensor native I2C address */
++ usleep_range(2000, 2500); /* wait 2ms */
++ };
++ client->addr = tmp_addr;
++
++ mdelay(10);
++
++ return 0;
++}
++
++static int ap0101_probe(struct i2c_client *client,
++ const struct i2c_device_id *did)
++{
++ struct ap0101_priv *priv;
++ int ret;
++
++ priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ v4l2_i2c_subdev_init(&priv->sd, client, &ap0101_subdev_ops);
++ priv->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++ priv->exposure = 0x100;
++ priv->gain = 0x100;
++ priv->autogain = 1;
++ v4l2_ctrl_handler_init(&priv->hdl, 4);
++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops,
++ V4L2_CID_BRIGHTNESS, 0, 16, 1, 7);
++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops,
++ V4L2_CID_CONTRAST, 0, 16, 1, 7);
++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops,
++ V4L2_CID_SATURATION, 0, 7, 1, 2);
++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops,
++ V4L2_CID_HUE, 0, 23, 1, 12);
++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops,
++ V4L2_CID_GAMMA, -128, 128, 1, 0);
++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops,
++ V4L2_CID_SHARPNESS, 0, 10, 1, 3);
++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops,
++ V4L2_CID_AUTOGAIN, 0, 1, 1, priv->autogain);
++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops,
++ V4L2_CID_GAIN, 0, 0xffff, 1, priv->gain);
++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops,
++ V4L2_CID_EXPOSURE, 0, 0xffff, 1, priv->exposure);
++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops,
++ V4L2_CID_HFLIP, 0, 1, 1, 1);
++ v4l2_ctrl_new_std(&priv->hdl, &ap0101_ctrl_ops,
++ V4L2_CID_VFLIP, 0, 1, 1, 0);
++ priv->sd.ctrl_handler = &priv->hdl;
++
++ ret = priv->hdl.error;
++ if (ret)
++ goto cleanup;
++
++ v4l2_ctrl_handler_setup(&priv->hdl);
++
++ priv->pad.flags = MEDIA_PAD_FL_SOURCE;
++ priv->sd.entity.flags |= MEDIA_ENT_F_CAM_SENSOR;
++ ret = media_entity_pads_init(&priv->sd.entity, 1, &priv->pad);
++ if (ret < 0)
++ goto cleanup;
++
++ ret = ap0101_parse_dt(client->dev.of_node, priv);
++ if (ret)
++ goto cleanup;
++
++ ret = ap0101_initialize(client);
++ if (ret < 0)
++ goto cleanup;
++
++ priv->rect.left = 0;
++ priv->rect.top = 0;
++ priv->rect.width = AP0101_MAX_WIDTH;
++ priv->rect.height = AP0101_MAX_HEIGHT;
++
++ ret = v4l2_async_register_subdev(&priv->sd);
++ if (ret)
++ goto cleanup;
++
++ if (device_create_file(&client->dev, &dev_attr_otp_id_ap0101) != 0) {
++ dev_err(&client->dev, "sysfs otp_id entry creation failed\n");
++ goto cleanup;
++ }
++
++ priv->init_complete = 1;
++
++ return 0;
++
++cleanup:
++ media_entity_cleanup(&priv->sd.entity);
++ v4l2_ctrl_handler_free(&priv->hdl);
++ v4l2_device_unregister_subdev(&priv->sd);
++#ifdef CONFIG_SOC_CAMERA_AP0101
++ v4l_err(client, "failed to probe @ 0x%02x (%s)\n",
++ client->addr, client->adapter->name);
++#endif
++ return ret;
++}
++
++static int ap0101_remove(struct i2c_client *client)
++{
++ struct ap0101_priv *priv = i2c_get_clientdata(client);
++
++ device_remove_file(&client->dev, &dev_attr_otp_id_ap0101);
++ v4l2_async_unregister_subdev(&priv->sd);
++ media_entity_cleanup(&priv->sd.entity);
++ v4l2_ctrl_handler_free(&priv->hdl);
++ v4l2_device_unregister_subdev(&priv->sd);
++
++ return 0;
++}
++
++#ifdef CONFIG_SOC_CAMERA_AP0101
++static const struct i2c_device_id ap0101_id[] = {
++ { "ap0101", 0 },
++ { }
++};
++MODULE_DEVICE_TABLE(i2c, ap0101_id);
++
++static const struct of_device_id ap0101_of_ids[] = {
++ { .compatible = "aptina,ap0101", },
++ { }
++};
++MODULE_DEVICE_TABLE(of, ap0101_of_ids);
++
++static struct i2c_driver ap0101_i2c_driver = {
++ .driver = {
++ .name = "ap0101",
++ .of_match_table = ap0101_of_ids,
++ },
++ .probe = ap0101_probe,
++ .remove = ap0101_remove,
++ .id_table = ap0101_id,
++};
++
++module_i2c_driver(ap0101_i2c_driver);
++
++MODULE_DESCRIPTION("SoC Camera driver for AP0101");
++MODULE_AUTHOR("Vladimir Barinov");
++MODULE_LICENSE("GPL");
++#endif
+diff --git a/drivers/media/i2c/soc_camera/ap0101_ar014x.h b/drivers/media/i2c/soc_camera/ap0101_ar014x.h
+new file mode 100644
+index 0000000..16599a1
+--- /dev/null
++++ b/drivers/media/i2c/soc_camera/ap0101_ar014x.h
+@@ -0,0 +1,28 @@
++/*
++ * ON Semiconductor ap0101-ar014x sensor camera wizard 1280x720@30/UYVY/BT601/8bit
++ *
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++#define AP0101_MAX_WIDTH 1280
++#define AP0101_MAX_HEIGHT 720
++
++#define AP0101_DELAY 0xffff
++
++struct ap0101_reg {
++ u16 reg;
++ u16 val;
++};
++
++static const struct ap0101_reg ap0101_regs_wizard[] = {
++/* enable FSIN */
++{0xc88c, 0x0303},
++{0xfc00, 0x2800},
++{0x0040, 0x8100},
++{AP0101_DELAY, 100},
++};
diff --git a/drivers/media/i2c/soc_camera/ar0132.c b/drivers/media/i2c/soc_camera/ar0132.c
new file mode 100644
-index 0000000..decbf5f
+index 0000000..bbaeeaae
--- /dev/null
+++ b/drivers/media/i2c/soc_camera/ar0132.c
@@ -0,0 +1,581 @@
+/*
-+ * Aptina AR0132 sensor camera driver
++ * ON Semiconductor AR0132 sensor camera driver
+ *
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
@@ -716,12 +1296,12 @@ index 0000000..decbf5f
+#endif
diff --git a/drivers/media/i2c/soc_camera/ar0132.h b/drivers/media/i2c/soc_camera/ar0132.h
new file mode 100644
-index 0000000..055841d
+index 0000000..bcee0e5
--- /dev/null
+++ b/drivers/media/i2c/soc_camera/ar0132.h
@@ -0,0 +1,213 @@
+/*
-+ * OmniVision ar0132 sensor camera wizard 1110x620@30/BGGR/BT601/12bit
++ * ON Semiconductor ar0132 sensor camera wizard 1110x620@30/BGGR/BT601/12bit
+ *
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
@@ -933,16 +1513,16 @@ index 0000000..055841d
+{0x31D0, 0x0001},
+{0x30B0, 0x2002},
+};
-diff --git a/drivers/media/i2c/soc_camera/max9286_max9271.c b/drivers/media/i2c/soc_camera/max9286_max9271.c
+diff --git a/drivers/media/i2c/soc_camera/max9286.c b/drivers/media/i2c/soc_camera/max9286.c
new file mode 100644
-index 0000000..91223a0
+index 0000000..20ef2de
--- /dev/null
-+++ b/drivers/media/i2c/soc_camera/max9286_max9271.c
-@@ -0,0 +1,607 @@
++++ b/drivers/media/i2c/soc_camera/max9286.c
+@@ -0,0 +1,672 @@
+/*
-+ * MAXIM max9286-max9271 GMSL driver
++ * MAXIM max9286 GMSL driver
+ *
-+ * Copyright (C) 2015-2017 Cogent Embedded, Inc.
++ * Copyright (C) 2015-2018 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
@@ -963,7 +1543,7 @@ index 0000000..91223a0
+#include <media/v4l2-of.h>
+#include <media/v4l2-subdev.h>
+
-+#include "max9286_max9271.h"
++#include "max9286.h"
+
+#define MAXIM_I2C_I2C_SPEED_837KHZ (0x7 << 2) /* 837kbps */
+#define MAXIM_I2C_I2C_SPEED_533KHZ (0x6 << 2) /* 533kbps */
@@ -974,7 +1554,7 @@ index 0000000..91223a0
+#define MAXIM_I2C_I2C_SPEED_028KHZ (0x1 << 2) /* 28.3 kbps */
+#define MAXIM_I2C_I2C_SPEED MAXIM_I2C_I2C_SPEED_339KHZ
+
-+struct max9286_max9271_priv {
++struct max9286_priv {
+ struct v4l2_subdev sd[4];
+ struct device_node *sd_of_node[4];
+ int des_addr;
@@ -988,47 +1568,68 @@ index 0000000..91223a0
+ char pclk_rising_edge;
+ int gpio_resetb;
+ int active_low_resetb;
++ int him;
++ int hsync;
++ int vsync;
+ int timeout;
+ atomic_t use_count;
+ u32 csi2_outord;
+ struct i2c_client *client;
+ int max9271_addr_map[4];
++ int ser_id;
+ struct regulator *poc_supply[4]; /* PoC power supply */
+};
+
-+static int force_conf_link;
-+static int force_poc_trig;
-+#ifndef MODULE
-+static __init int max9286_max9271_force_conf_link(char *str)
-+{
-+ /* force configuration link */
-+ /* used only if robust firmware flashing required (f.e. recovery) */
-+ force_conf_link = 1;
-+ return 0;
-+}
-+early_param("force_conf_link", max9286_max9271_force_conf_link);
++static int conf_link;
++module_param(conf_link, int, 0644);
++MODULE_PARM_DESC(conf_link, " Force configuration link. Used only if robust firmware flashing required (f.e. recovery)");
++
++static int poc_trig;
++module_param(poc_trig, int, 0644);
++MODULE_PARM_DESC(poc_trig, " Use PoC triggering during reverse channel setup. Useful on systems with dedicated PoC and unstable ser-des lock */");
++
++static int him;
++module_param(him, int, 0644);
++MODULE_PARM_DESC(him, " Use High-Immunity mode (default: leagacy mode) */");
++
++static int fsync_period;
++module_param(fsync_period, int, 0644);
++MODULE_PARM_DESC(fsync_period, " Frame sync period (default: 3.2MHz) */");
++
++static int hsync;
++module_param(hsync, int, 0644);
++MODULE_PARM_DESC(hsync, " HSYNC invertion (default: 0 - not inverted) */");
+
-+static __init int max9286_max9271_force_poc_trig(char *str)
++static int vsync = 1;
++module_param(vsync, int, 0644);
++MODULE_PARM_DESC(vsync, " VSYNC invertion (default: 1 - inverted) */");
++
++static char* ser_name(int id)
+{
-+ /* force PoC triggering during reverse channel setup */
-+ /* to be used on systems with dedicated PoC and unstable ser-des lock */
-+ force_poc_trig = 1;
-+ return 0;
++ switch (id) {
++ case MAX9271_ID:
++ return "MAX9271";
++ case MAX96705_ID:
++ return "MAX96705";
++ default:
++ return "unknown";
++ }
+}
-+early_param("force_poc_trig", max9286_max9271_force_poc_trig);
-+#endif
+
-+static void max9286_max9271_preinit(struct i2c_client *client, int addr)
++static void max9286_preinit(struct i2c_client *client, int addr)
+{
++ struct max9286_priv *priv = i2c_get_clientdata(client);
++
+ client->addr = addr; /* MAX9286-CAMx I2C */
+ reg8_write(client, 0x0a, 0x00); /* disable reverse control for all cams */
+ reg8_write(client, 0x00, 0x00); /* disable all GMSL links [0:3] */
+ usleep_range(2000, 2500); /* wait 2ms after any change of reverse channel settings */
++ reg8_write(client, 0x1c, priv->him ? 0xf4 : 0x04); /* high-immunity or legacy mode */
+}
+
-+static void max9286_max9271_sensor_reset(struct i2c_client *client, int addr, int reset_on)
++static void max9286_sensor_reset(struct i2c_client *client, int addr, int reset_on)
+{
-+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client);
++ struct max9286_priv *priv = i2c_get_clientdata(client);
+
+ if (priv->gpio_resetb < 1 || priv->gpio_resetb > 5)
+ return;
@@ -1040,9 +1641,9 @@ index 0000000..91223a0
+ reg8_write(client, 0x0e, 0x42 | BIT(priv->gpio_resetb)); /* set GPIOn direction output */
+}
+
-+static void max9286_max9271_postinit(struct i2c_client *client, int addr)
++static void max9286_postinit(struct i2c_client *client, int addr)
+{
-+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client);
++ struct max9286_priv *priv = i2c_get_clientdata(client);
+ int idx;
+
+ for (idx = 0; idx < priv->links; idx++) {
@@ -1050,7 +1651,7 @@ index 0000000..91223a0
+ reg8_write(client, 0x0a, 0x11 << idx); /* enable reverse/forward control for CAMx */
+
+ client->addr = priv->max9271_addr_map[idx]; /* MAX9271-CAMx I2C */
-+ max9286_max9271_sensor_reset(client, client->addr, 0); /* sensor unreset */
++ max9286_sensor_reset(client, client->addr, 0); /* sensor unreset */
+ }
+
+ client->addr = addr; /* MAX9286 I2C */
@@ -1062,9 +1663,9 @@ index 0000000..91223a0
+ usleep_range(5000, 5500); /* wait 2ms after any change of reverse channel settings */
+}
+
-+static int max9286_max9271_reverse_channel_setup(struct i2c_client *client, int idx)
++static int max9286_reverse_channel_setup(struct i2c_client *client, int idx)
+{
-+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client);
++ struct max9286_priv *priv = i2c_get_clientdata(client);
+ u8 val = 0;
+ int timeout = priv->timeout;
+ char timeout_str[10];
@@ -1087,8 +1688,8 @@ index 0000000..91223a0
+ client->addr = 0x40; /* MAX9271-CAMx I2C */
+ reg8_write(client, 0x04, 0x43); /* wake-up, enable reverse_control/conf_link */
+ usleep_range(2000, 2500); /* wait 2ms after any change of reverse channel settings */
-+ reg8_write(client, 0x08, 0x1); /* reverse channel receiver high threshold enable */
-+ reg8_write(client, 0x97, 0x5f); /* enable reverse control channel programming (MAX96705-MAX96711 only) */
++ reg8_write(client, 0x08, 0x01); /* reverse channel receiver high threshold enable */
++ reg8_write(client, 0x97, priv->him ? 0xaf : 0x5f); /* enable reverse control channel programming (MAX96705-MAX96711 only) */
+ usleep_range(2000, 2500); /* wait 2ms after any change of reverse channel settings */
+
+ client->addr = priv->des_addr; /* MAX9286-CAMx I2C */
@@ -1097,20 +1698,23 @@ index 0000000..91223a0
+
+ client->addr = 0x40; /* MAX9271-CAMx I2C */
+ reg8_read(client, 0x1e, &val); /* read max9271 ID */
-+ if (val == MAX9271_ID || val == MAX96705_ID || --timeout == 0)
++ if (val == MAX9271_ID || val == MAX96705_ID || --timeout == 0) {
++ priv->ser_id = val;
+ break;
++ }
+
+ /* Check if already initialized (after reboot/reset ?) */
+ client->addr = priv->max9271_addr_map[idx]; /* MAX9271-CAMx I2C */
+ reg8_read(client, 0x1e, &val); /* read max9271 ID */
+ if (val == MAX9271_ID || val == MAX96705_ID) {
++ priv->ser_id = val;
+ reg8_write(client, 0x04, 0x43); /* enable reverse_control/conf_link */
+ usleep_range(2000, 2500); /* wait 2ms after any change of reverse channel settings */
+ ret = -EADDRINUSE;
+ break;
+ }
+
-+ if (timeout == priv->timeout / 2 && force_poc_trig) {
++ if (timeout == priv->timeout / 2 && poc_trig) {
+ if (!IS_ERR(priv->poc_supply[idx])) {
+ if (regulator_disable(priv->poc_supply[idx]))
+ dev_err(&client->dev, "fail to disable POC%d regulator\n", idx);
@@ -1121,7 +1725,7 @@ index 0000000..91223a0
+ }
+ }
+
-+ max9286_max9271_sensor_reset(client, client->addr, 1); /* sensor reset */
++ max9286_sensor_reset(client, client->addr, 1); /* sensor reset */
+
+ if (!timeout) {
+ ret = -ETIMEDOUT;
@@ -1134,7 +1738,7 @@ index 0000000..91223a0
+
+out:
+ sprintf(timeout_str, "retries=%d", priv->timeout - timeout);
-+ dev_info(&client->dev, "link%d MAX9271 %sat 0x%x %s %s\n", idx,
++ dev_info(&client->dev, "link%d %s %sat 0x%x %s %s\n", idx, ser_name(priv->ser_id),
+ ret == -EADDRINUSE ? "already " : "", priv->max9271_addr_map[idx],
+ ret == -ETIMEDOUT ? "not found: timeout GMSL link establish" : "",
+ priv->timeout - timeout? timeout_str : "");
@@ -1142,9 +1746,9 @@ index 0000000..91223a0
+ return ret;
+}
+
-+static void max9286_max9271_initial_setup(struct i2c_client *client)
++static void max9286_initial_setup(struct i2c_client *client)
+{
-+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client);
++ struct max9286_priv *priv = i2c_get_clientdata(client);
+
+ /* Initial setup */
+ client->addr = priv->des_addr; /* MAX9286-CAMx I2C */
@@ -1167,10 +1771,11 @@ index 0000000..91223a0
+ dev_err(&client->dev, "CSI2 lanes number is invalid (%d)\n", priv->lanes);
+ }
+
++ reg8_write(client, 0x06, priv->fsync_period & 0xff);
++ reg8_write(client, 0x07, (priv->fsync_period >> 8) & 0xff);
++ reg8_write(client, 0x08, priv->fsync_period >> 16);
++
+ if (strcmp(priv->fsync_mode, "manual") == 0) {
-+ reg8_write(client, 0x06, priv->fsync_period & 0xff);
-+ reg8_write(client, 0x07, (priv->fsync_period >> 8) & 0xff);
-+ reg8_write(client, 0x08, priv->fsync_period >> 16);
+ reg8_write(client, 0x01, 0x00); /* manual: FRAMESYNC set manually via [0x06:0x08] regs */
+ } else if (strcmp(priv->fsync_mode, "automatic") == 0) {
+ reg8_write(client, 0x01, 0x02); /* automatic: FRAMESYNC taken from the slowest Link */
@@ -1182,12 +1787,13 @@ index 0000000..91223a0
+
+ reg8_write(client, 0x63, 0); /* disable overlap window */
+ reg8_write(client, 0x64, 0);
-+ reg8_write(client, 0x0c, 0x89); /* enable HS/VS encoding, use D14/15 for HS/VS, invert VS */
++ reg8_write(client, 0x0c, 0x91 | (priv->vsync ? BIT(3) : 0) | (priv->hsync ? BIT(2) : 0)); /* enable HS/VS encoding, use D14/15 for HS/VS, invert HS/VS */
++ reg8_write(client, 0x19, 0x0c); /* Drive HSTRAIL state for 120ns after the last payload bit */
+}
+
-+static void max9286_max9271_gmsl_link_setup(struct i2c_client *client, int idx)
++static void max9286_gmsl_link_setup(struct i2c_client *client, int idx)
+{
-+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client);
++ struct max9286_priv *priv = i2c_get_clientdata(client);
+
+ /* GMSL setup */
+ client->addr = 0x40; /* MAX9271-CAMx I2C */
@@ -1197,6 +1803,27 @@ index 0000000..91223a0
+ reg8_write(client, 0x02, 0xff); /* spread spectrum +-4%, pclk range automatic, Gbps automatic */
+ usleep_range(2000, 2500); /* wait 2ms */
+
++ if (priv->ser_id == MAX96705_ID) {
++ /* setup crossbar in DBL mode: reverse DVP bus */
++ reg8_write(client, 0x20, 0x07);
++ reg8_write(client, 0x21, 0x06);
++ reg8_write(client, 0x22, 0x05);
++ reg8_write(client, 0x23, 0x04);
++ reg8_write(client, 0x24, 0x03);
++ reg8_write(client, 0x25, 0x02);
++ reg8_write(client, 0x26, 0x01);
++ reg8_write(client, 0x27, 0x00);
++
++ reg8_write(client, 0x30, 0x17);
++ reg8_write(client, 0x31, 0x16);
++ reg8_write(client, 0x32, 0x15);
++ reg8_write(client, 0x33, 0x14);
++ reg8_write(client, 0x34, 0x13);
++ reg8_write(client, 0x35, 0x12);
++ reg8_write(client, 0x36, 0x11);
++ reg8_write(client, 0x37, 0x10);
++ }
++
+ client->addr = priv->des_addr; /* MAX9286-CAMx I2C */
+ reg8_write(client, 0x34, 0x22 | MAXIM_I2C_I2C_SPEED); /* disable artificial ACK, I2C speed set */
+ usleep_range(2000, 2500); /* wait 2ms */
@@ -1223,9 +1850,9 @@ index 0000000..91223a0
+#endif
+}
+
-+static int max9286_max9271_initialize(struct i2c_client *client)
++static int max9286_initialize(struct i2c_client *client)
+{
-+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client);
++ struct max9286_priv *priv = i2c_get_clientdata(client);
+ int idx, ret;
+
+ dev_info(&client->dev, "LINKs=%d, LANES=%d, FSYNC mode=%s, FSYNC period=%d, PCLK edge=%s\n",
@@ -1233,10 +1860,10 @@ index 0000000..91223a0
+ priv->pclk_rising_edge ? "rising" : "falling");
+
+ if (priv->des_quirk_addr)
-+ max9286_max9271_preinit(client, priv->des_quirk_addr);
++ max9286_preinit(client, priv->des_quirk_addr);
+
-+ max9286_max9271_preinit(client, priv->des_addr);
-+ max9286_max9271_initial_setup(client);
++ max9286_preinit(client, priv->des_addr);
++ max9286_initial_setup(client);
+
+ for (idx = 0; idx < priv->links; idx++) {
+ if (!IS_ERR(priv->poc_supply[idx])) {
@@ -1244,13 +1871,13 @@ index 0000000..91223a0
+ dev_err(&client->dev, "fail to enable POC%d regulator\n", idx);
+ }
+
-+ ret = max9286_max9271_reverse_channel_setup(client, idx);
++ ret = max9286_reverse_channel_setup(client, idx);
+ if (ret)
+ continue;
-+ max9286_max9271_gmsl_link_setup(client, idx);
++ max9286_gmsl_link_setup(client, idx);
+ }
+
-+ max9286_max9271_postinit(client, priv->des_addr);
++ max9286_postinit(client, priv->des_addr);
+
+ client->addr = priv->des_addr;
+
@@ -1258,10 +1885,10 @@ index 0000000..91223a0
+}
+
+#ifdef CONFIG_VIDEO_ADV_DEBUG
-+static int max9286_max9271_g_register(struct v4l2_subdev *sd,
++static int max9286_g_register(struct v4l2_subdev *sd,
+ struct v4l2_dbg_register *reg)
+{
-+ struct max9286_max9271_priv *priv = v4l2_get_subdevdata(sd);
++ struct max9286_priv *priv = v4l2_get_subdevdata(sd);
+ struct i2c_client *client = priv->client;
+ int ret;
+ u8 val = 0;
@@ -1276,19 +1903,19 @@ index 0000000..91223a0
+ return 0;
+}
+
-+static int max9286_max9271_s_register(struct v4l2_subdev *sd,
++static int max9286_s_register(struct v4l2_subdev *sd,
+ const struct v4l2_dbg_register *reg)
+{
-+ struct max9286_max9271_priv *priv = v4l2_get_subdevdata(sd);
++ struct max9286_priv *priv = v4l2_get_subdevdata(sd);
+ struct i2c_client *client = priv->client;
+
+ return reg8_write(client, (u8)reg->reg, (u8)reg->val);
+}
+#endif
+
-+static int max9286_max9271_s_power(struct v4l2_subdev *sd, int on)
++static int max9286_s_power(struct v4l2_subdev *sd, int on)
+{
-+ struct max9286_max9271_priv *priv = v4l2_get_subdevdata(sd);
++ struct max9286_priv *priv = v4l2_get_subdevdata(sd);
+ struct i2c_client *client = priv->client;
+
+ if (on) {
@@ -1302,9 +1929,9 @@ index 0000000..91223a0
+ return 0;
+}
+
-+static int max9286_max9271_registered_async(struct v4l2_subdev *sd)
++static int max9286_registered_async(struct v4l2_subdev *sd)
+{
-+ struct max9286_max9271_priv *priv = v4l2_get_subdevdata(sd);
++ struct max9286_priv *priv = v4l2_get_subdevdata(sd);
+ struct i2c_client *client = priv->client;
+ int idx, tmp_addr;
+
@@ -1316,7 +1943,7 @@ index 0000000..91223a0
+ reg8_write(client, 0x0a, 0x11 << idx); /* enable reverse/forward control for CAMx */
+
+ client->addr = priv->max9271_addr_map[idx]; /* MAX9271-CAMx */
-+ reg8_write(client, 0x04, force_conf_link ? 0x43 : 0x83); /* enable reverse_control/serial_link */
++ reg8_write(client, 0x04, conf_link ? 0x43 : 0x83); /* enable serial_link */
+ usleep_range(2000, 2500); /* wait 2ms after changing reverse_control */
+
+ client->addr = priv->des_addr; /* MAX9286 I2C */
@@ -1327,22 +1954,22 @@ index 0000000..91223a0
+ return 0;
+}
+
-+static struct v4l2_subdev_core_ops max9286_max9271_subdev_core_ops = {
++static struct v4l2_subdev_core_ops max9286_subdev_core_ops = {
+#ifdef CONFIG_VIDEO_ADV_DEBUG
-+ .g_register = max9286_max9271_g_register,
-+ .s_register = max9286_max9271_s_register,
++ .g_register = max9286_g_register,
++ .s_register = max9286_s_register,
+#endif
-+ .s_power = max9286_max9271_s_power,
-+ .registered_async = max9286_max9271_registered_async,
++ .s_power = max9286_s_power,
++ .registered_async = max9286_registered_async,
+};
+
-+static struct v4l2_subdev_ops max9286_max9271_subdev_ops = {
-+ .core = &max9286_max9271_subdev_core_ops,
++static struct v4l2_subdev_ops max9286_subdev_ops = {
++ .core = &max9286_subdev_core_ops,
+};
+
-+static int max9286_max9271_parse_dt(struct i2c_client *client)
++static int max9286_parse_dt(struct i2c_client *client)
+{
-+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client);
++ struct max9286_priv *priv = i2c_get_clientdata(client);
+ struct device_node *np = client->dev.of_node;
+ struct device_node *endpoint = NULL;
+ struct property *prop;
@@ -1402,6 +2029,24 @@ index 0000000..91223a0
+ priv->timeout = 100;
+ if (of_property_read_u32(np, "maxim,i2c-quirk", &priv->des_quirk_addr))
+ priv->des_quirk_addr = 0;
++ if (of_property_read_u32(np, "maxim,him", &priv->him))
++ priv->him = 0;
++ if (of_property_read_u32(np, "maxim,hsync", &priv->hsync))
++ priv->hsync = 0;
++ if (of_property_read_u32(np, "maxim,vsync", &priv->vsync))
++ priv->vsync = 1;
++
++ /* module params override dts */
++ if (him)
++ priv->him = him;
++ if (fsync_period) {
++ priv->fsync_period = fsync_period;
++ priv->fsync_mode = fsync_mode_default;
++ }
++ if (hsync)
++ priv->hsync = hsync;
++ if (!vsync)
++ priv->vsync = vsync;
+
+ for (i = 0; i < priv->links; i++) {
+ endpoint = of_graph_get_next_endpoint(np, endpoint);
@@ -1421,9 +2066,9 @@ index 0000000..91223a0
+ return 0;
+}
+
-+static void max9286_max9271_setup_remote_endpoint(struct i2c_client *client)
++static void max9286_setup_remote_endpoint(struct i2c_client *client)
+{
-+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client);
++ struct max9286_priv *priv = i2c_get_clientdata(client);
+ struct device_node *np = client->dev.of_node;
+ struct device_node *endpoint = NULL, *rendpoint = NULL;
+ int i;
@@ -1454,10 +2099,10 @@ index 0000000..91223a0
+ }
+}
+
-+static int max9286_max9271_probe(struct i2c_client *client,
++static int max9286_probe(struct i2c_client *client,
+ const struct i2c_device_id *did)
+{
-+ struct max9286_max9271_priv *priv;
++ struct max9286_priv *priv;
+ int err, i;
+ char supply_name[10];
+
@@ -1471,7 +2116,7 @@ index 0000000..91223a0
+ atomic_set(&priv->use_count, 0);
+ priv->csi2_outord = 0xff;
+
-+ err = max9286_max9271_parse_dt(client);
++ err = max9286_parse_dt(client);
+ if (err)
+ goto out;
+
@@ -1480,14 +2125,14 @@ index 0000000..91223a0
+ priv->poc_supply[i] = devm_regulator_get_optional(&client->dev, supply_name);
+ }
+
-+ err = max9286_max9271_initialize(client);
++ err = max9286_initialize(client);
+ if (err < 0)
+ goto out;
+
-+ max9286_max9271_setup_remote_endpoint(client);
++ max9286_setup_remote_endpoint(client);
+
+ for (i = 0; i < 4; i++) {
-+ v4l2_subdev_init(&priv->sd[i], &max9286_max9271_subdev_ops);
++ v4l2_subdev_init(&priv->sd[i], &max9286_subdev_ops);
+ priv->sd[i].owner = client->dev.driver->owner;
+ priv->sd[i].dev = &client->dev;
+ priv->sd[i].grp_id = i;
@@ -1506,9 +2151,9 @@ index 0000000..91223a0
+ return err;
+}
+
-+static int max9286_max9271_remove(struct i2c_client *client)
++static int max9286_remove(struct i2c_client *client)
+{
-+ struct max9286_max9271_priv *priv = i2c_get_clientdata(client);
++ struct max9286_priv *priv = i2c_get_clientdata(client);
+ int i;
+
+ for (i = 0; i < 4; i++) {
@@ -1519,38 +2164,38 @@ index 0000000..91223a0
+ return 0;
+}
+
-+static const struct of_device_id max9286_max9271_dt_ids[] = {
-+ { .compatible = "maxim,max9286-max9271" },
++static const struct of_device_id max9286_dt_ids[] = {
++ { .compatible = "maxim,max9286" },
+ {},
+};
-+MODULE_DEVICE_TABLE(of, max9286_max9271_dt_ids);
++MODULE_DEVICE_TABLE(of, max9286_dt_ids);
+
-+static const struct i2c_device_id max9286_max9271_id[] = {
-+ { "max9286_max9271", 0 },
++static const struct i2c_device_id max9286_id[] = {
++ { "max9286", 0 },
+ { }
+};
-+MODULE_DEVICE_TABLE(i2c, max9286_max9271_id);
++MODULE_DEVICE_TABLE(i2c, max9286_id);
+
-+static struct i2c_driver max9286_max9271_i2c_driver = {
++static struct i2c_driver max9286_i2c_driver = {
+ .driver = {
-+ .name = "max9286_max9271",
-+ .of_match_table = of_match_ptr(max9286_max9271_dt_ids),
++ .name = "max9286",
++ .of_match_table = of_match_ptr(max9286_dt_ids),
+ },
-+ .probe = max9286_max9271_probe,
-+ .remove = max9286_max9271_remove,
-+ .id_table = max9286_max9271_id,
++ .probe = max9286_probe,
++ .remove = max9286_remove,
++ .id_table = max9286_id,
+};
+
-+module_i2c_driver(max9286_max9271_i2c_driver);
++module_i2c_driver(max9286_i2c_driver);
+
-+MODULE_DESCRIPTION("GMSL driver for MAX9286-MAX9271");
++MODULE_DESCRIPTION("GMSL driver for MAX9286");
+MODULE_AUTHOR("Vladimir Barinov");
+MODULE_LICENSE("GPL");
-diff --git a/drivers/media/i2c/soc_camera/max9286_max9271.h b/drivers/media/i2c/soc_camera/max9286_max9271.h
+diff --git a/drivers/media/i2c/soc_camera/max9286.h b/drivers/media/i2c/soc_camera/max9286.h
new file mode 100644
index 0000000..6c2a9e0
--- /dev/null
-+++ b/drivers/media/i2c/soc_camera/max9286_max9271.h
++++ b/drivers/media/i2c/soc_camera/max9286.h
@@ -0,0 +1,244 @@
+/*
+ * MAXIM max9286-max9271 GMSL driver include file
@@ -1798,7 +2443,7 @@ index 0000000..6c2a9e0
+#endif /* _MAX9286_MAX9271_H */
diff --git a/drivers/media/i2c/soc_camera/ov10635.c b/drivers/media/i2c/soc_camera/ov10635.c
new file mode 100644
-index 0000000..6296647
+index 0000000..c8da1f4
--- /dev/null
+++ b/drivers/media/i2c/soc_camera/ov10635.c
@@ -0,0 +1,758 @@
@@ -1824,7 +2469,7 @@ index 0000000..6296647
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-of.h>
+
-+#include "max9286_max9271.h"
++#include "max9286.h"
+#include "ov10635.h"
+
+#define OV10635_I2C_ADDR 0x30
@@ -3767,10 +4412,10 @@ index 0000000..4c3515a
+#endif
diff --git a/drivers/media/i2c/soc_camera/ov106xx.c b/drivers/media/i2c/soc_camera/ov106xx.c
new file mode 100644
-index 0000000..f2bb706
+index 0000000..4c797f9
--- /dev/null
+++ b/drivers/media/i2c/soc_camera/ov106xx.c
-@@ -0,0 +1,106 @@
+@@ -0,0 +1,117 @@
+/*
+ * OmniVision ov10635/ov490-ov10640/ov495-ov2775 sensor camera driver
+ *
@@ -3786,12 +4431,14 @@ index 0000000..f2bb706
+#include "ov490_ov10640.c"
+#include "ov495_ov2775.c"
+#include "ar0132.c"
++#include "ap0101_ar014x.c"
+
+static enum {
+ ID_OV10635,
+ ID_OV490_OV10640,
+ ID_OV495_OV2775,
+ ID_AR0132,
++ ID_AP0101_AR014X,
+} chip_id;
+
+static int ov106xx_probe(struct i2c_client *client,
@@ -3824,6 +4471,12 @@ index 0000000..f2bb706
+ goto out;
+ }
+
++ ret = ap0101_probe(client, did);
++ if (!ret) {
++ chip_id = ID_AP0101_AR014X;
++ goto out;
++ }
++
+ v4l_err(client, "failed to probe @ 0x%02x (%s)\n",
+ client->addr, client->adapter->name);
+out:
@@ -3845,6 +4498,9 @@ index 0000000..f2bb706
+ case ID_AR0132:
+ ar0132_remove(client);
+ break;
++ case ID_AP0101_AR014X:
++ ap0101_remove(client);
++ break;
+ };
+
+ return 0;
@@ -3874,15 +4530,15 @@ index 0000000..f2bb706
+
+module_i2c_driver(ov106xx_i2c_driver);
+
-+MODULE_DESCRIPTION("SoC Camera driver for OV10635 or OV490/OV10640 or OV495/OV2775 or AR0132");
++MODULE_DESCRIPTION("SoC Camera driver for OV10635 or OV490/OV10640 or OV495/OV2775 or AR0132 or AP0101/AR014X");
+MODULE_AUTHOR("Vladimir Barinov");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/i2c/soc_camera/ov490_ov10640.c b/drivers/media/i2c/soc_camera/ov490_ov10640.c
new file mode 100644
-index 0000000..813c08e
+index 0000000..be7098e
--- /dev/null
+++ b/drivers/media/i2c/soc_camera/ov490_ov10640.c
-@@ -0,0 +1,1092 @@
+@@ -0,0 +1,1156 @@
+/*
+ * OmniVision ov490-ov10640 sensor camera driver
+ *
@@ -3905,7 +4561,7 @@ index 0000000..813c08e
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-of.h>
+
-+#include "max9286_max9271.h"
++#include "max9286.h"
+#include "ov490_ov10640.h"
+
+#define OV490_I2C_ADDR 0x24
@@ -3933,6 +4589,11 @@ index 0000000..813c08e
+ int exposure;
+ int gain;
+ int autogain;
++ int red;
++ int green_r;
++ int green_b;
++ int blue;
++ int awb;
+ int dvp_order;
+ /* serializers */
+ int max9286_addr;
@@ -4369,6 +5030,54 @@ index 0000000..813c08e
+ usleep_range(100, 150); /* wait 100 us */
+ ret |= reg16_write(client, 0x00C0, 0xea);
+ break;
++ case V4L2_CID_AUTO_WHITE_BALANCE:
++ case V4L2_CID_RED_BALANCE:
++ case V4L2_CID_BLUE_BALANCE:
++ if (ctrl->id == V4L2_CID_AUTO_WHITE_BALANCE)
++ priv->awb = ctrl->val;
++ if (ctrl->id == V4L2_CID_RED_BALANCE) {
++ priv->red = ctrl->val;
++ priv->red <<= 8;
++ priv->green_r = priv->red / 2;
++ }
++ if (ctrl->id == V4L2_CID_BLUE_BALANCE) {
++ priv->blue = ctrl->val;
++ priv->blue <<= 8;
++ priv->green_b = priv->blue / 2;
++ }
++
++ ret = reg16_write(client, 0xFFFD, 0x80);
++ ret |= reg16_write(client, 0xFFFE, 0x19);
++ usleep_range(100, 150); /* wait 100 us */
++ ret |= reg16_write(client, 0x5000, !priv->awb);
++ ret |= reg16_write(client, 0x5001, priv->red >> 8);
++ ret |= reg16_write(client, 0x5002, priv->red & 0xff);
++ ret |= reg16_write(client, 0x5003, priv->green_r >> 8);
++ ret |= reg16_write(client, 0x5004, priv->green_r & 0xff);
++ ret |= reg16_write(client, 0x5005, priv->green_b >> 8);
++ ret |= reg16_write(client, 0x5006, priv->green_b & 0xff);
++ ret |= reg16_write(client, 0x5007, priv->blue >> 8);
++ ret |= reg16_write(client, 0x5008, priv->blue & 0xff);
++ ret |= reg16_write(client, 0x5009, priv->red >> 8);
++ ret |= reg16_write(client, 0x500a, priv->red & 0xff);
++ ret |= reg16_write(client, 0x500b, priv->green_r >> 8);
++ ret |= reg16_write(client, 0x500c, priv->green_r & 0xff);
++ ret |= reg16_write(client, 0x500d, priv->green_b >> 8);
++ ret |= reg16_write(client, 0x500e, priv->green_b & 0xff);
++ ret |= reg16_write(client, 0x500f, priv->blue >> 8);
++ ret |= reg16_write(client, 0x5010, priv->blue & 0xff);
++ ret |= reg16_write(client, 0x5011, priv->red >> 8);
++ ret |= reg16_write(client, 0x5012, priv->red & 0xff);
++ ret |= reg16_write(client, 0x5013, priv->green_r >> 8);
++ ret |= reg16_write(client, 0x5014, priv->green_r & 0xff);
++ ret |= reg16_write(client, 0x5015, priv->green_b >> 8);
++ ret |= reg16_write(client, 0x5016, priv->green_b & 0xff);
++ ret |= reg16_write(client, 0x5017, priv->blue >> 8);
++ ret |= reg16_write(client, 0x5018, priv->blue & 0xff);
++ ret |= reg16_write(client, 0xFFFE, 0x80);
++ usleep_range(100, 150); /* wait 100 us */
++ ret |= reg16_write(client, 0x00C0, 0xeb);
++ break;
+ case V4L2_CID_HFLIP:
+#if 1
+ ret = reg16_write(client, 0xFFFD, 0x80);
@@ -4855,6 +5564,11 @@ index 0000000..813c08e
+ priv->exposure = 0x100;
+ priv->gain = 0x100;
+ priv->autogain = 1;
++ priv->red = 0x400;
++ priv->blue = 0x400;
++ priv->green_r = priv->red / 2;
++ priv->green_b = priv->blue / 2;
++ priv->awb = 1;
+ v4l2_ctrl_handler_init(&priv->hdl, 4);
+ v4l2_ctrl_new_std(&priv->hdl, &ov490_ctrl_ops,
+ V4L2_CID_BRIGHTNESS, 0, 16, 1, 7);
@@ -4875,6 +5589,12 @@ index 0000000..813c08e
+ v4l2_ctrl_new_std(&priv->hdl, &ov490_ctrl_ops,
+ V4L2_CID_EXPOSURE, 0, 0xffff, 1, priv->exposure);
+ v4l2_ctrl_new_std(&priv->hdl, &ov490_ctrl_ops,
++ V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, priv->autogain);
++ v4l2_ctrl_new_std(&priv->hdl, &ov490_ctrl_ops,
++ V4L2_CID_RED_BALANCE, 2, 0xf, 1, priv->red >> 8);
++ v4l2_ctrl_new_std(&priv->hdl, &ov490_ctrl_ops,
++ V4L2_CID_BLUE_BALANCE, 2, 0xf, 1, priv->blue >> 8);
++ v4l2_ctrl_new_std(&priv->hdl, &ov490_ctrl_ops,
+ V4L2_CID_HFLIP, 0, 1, 1, 1);
+ v4l2_ctrl_new_std(&priv->hdl, &ov490_ctrl_ops,
+ V4L2_CID_VFLIP, 0, 1, 1, 0);
@@ -4977,10 +5697,10 @@ index 0000000..813c08e
+#endif
diff --git a/drivers/media/i2c/soc_camera/ov490_ov10640.h b/drivers/media/i2c/soc_camera/ov490_ov10640.h
new file mode 100644
-index 0000000..8c9ecf1
+index 0000000..b22e93e
--- /dev/null
+++ b/drivers/media/i2c/soc_camera/ov490_ov10640.h
-@@ -0,0 +1,93 @@
+@@ -0,0 +1,102 @@
+/*
+ * OmniVision ov490-ov10640 sensor camera wizard 1280x1080@30/UYVY/BT601/8bit
+ *
@@ -4992,6 +5712,8 @@ index 0000000..8c9ecf1
+ * option) any later version.
+ */
+
++//#define OV490_DISPLAY_PATTERN
++
+struct ov490_reg {
+ u16 reg;
+ u8 val;
@@ -5073,6 +5795,13 @@ index 0000000..8c9ecf1
+{0x5001, 0x00},
+{0xfffe, 0x80},
+{0x00c0, 0xdc},
++#ifdef OV490_DISPLAY_PATTERN
++{0xfffd, 0x80},
++{0xfffe, 0x19},
++{0x5000, 0x02},
++{0xfffe, 0x80},
++{0x00c0, 0xd6},
++#endif
+};
diff --git a/drivers/media/i2c/soc_camera/ov495_ov2775.c b/drivers/media/i2c/soc_camera/ov495_ov2775.c
new file mode 100644
@@ -6206,10 +6935,10 @@ index 0000000..1672173
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/i2c/soc_camera/ti964_ti9x3.c b/drivers/media/i2c/soc_camera/ti964_ti9x3.c
new file mode 100644
-index 0000000..770d306
+index 0000000..bffd7c2
--- /dev/null
+++ b/drivers/media/i2c/soc_camera/ti964_ti9x3.c
-@@ -0,0 +1,399 @@
+@@ -0,0 +1,400 @@
+/*
+ * TI (ti964/ti960)-(ti913/ti953) FPDLinkIII driver
+ *
@@ -6281,7 +7010,8 @@ index 0000000..770d306
+ reg8_write(client, 0x1f, 0x00); /* CSI rate 1.5/1.6Gbps */
+ break;
+ case 800: /* REFCLK = 25MHZ */
-+ reg8_write(client, 0x1f, 0x02); /* CSI rate 800Mbps */
++ case 700: /* REFCLK = 22.5MHZ */
++ reg8_write(client, 0x1f, 0x02); /* CSI rate 700/800Mbps */
+ break;
+ case 400: /* REFCLK = 25MHZ */
+ reg8_write(client, 0x1f, 0x03); /* CSI rate 400Mbps */
@@ -7255,10 +7985,24 @@ index 4d95da6..2ef27e8 100644
return 0;
diff --git a/drivers/media/platform/soc_camera/rcar_vin.c b/drivers/media/platform/soc_camera/rcar_vin.c
-index 74fb005..496a8bd 100644
+index 74fb005..ac75af6 100644
--- a/drivers/media/platform/soc_camera/rcar_vin.c
+++ b/drivers/media/platform/soc_camera/rcar_vin.c
-@@ -106,6 +106,7 @@
+@@ -95,17 +95,21 @@
+ #define VNC8A_REG 0xF0 /* Video n Coefficient Set C8A Register */
+ #define VNC8B_REG 0xF4 /* Video n Coefficient Set C8B Register */
+ #define VNC8C_REG 0xF8 /* Video n Coefficient Set C8C Register */
++#define VNLUTP_REG 0x100 /* Video n Lookup table pointer */
++#define VNLUTD_REG 0x104 /* Video n Lookup table data register */
+
+ /* Register bit fields for R-Car VIN */
+ /* Video n Main Control Register bits */
+ #define VNMC_DPINE (1 << 27)
+ #define VNMC_SCLE (1 << 26)
+ #define VNMC_FOC (1 << 21)
++#define VNMC_LUTE (1 << 20)
+ #define VNMC_YCAL (1 << 19)
+ #define VNMC_INF_YUV8_BT656 (0 << 16)
#define VNMC_INF_YUV8_BT601 (1 << 16)
#define VNMC_INF_YUV10_BT656 (2 << 16)
#define VNMC_INF_YUV10_BT601 (3 << 16)
@@ -7266,7 +8010,7 @@ index 74fb005..496a8bd 100644
#define VNMC_INF_YUV16 (5 << 16)
#define VNMC_INF_RGB888 (6 << 16)
#define VNMC_INF_MASK (7 << 16)
-@@ -138,6 +139,7 @@
+@@ -138,6 +142,7 @@
#define VNINTS_FOS (1 << 0)
/* Video n Data Mode Register bits */
@@ -7274,7 +8018,18 @@ index 74fb005..496a8bd 100644
#define VNDMR_EXRGB (1 << 8)
#define VNDMR_BPSM (1 << 4)
#define VNDMR_DTMD_YCSEP (1 << 1)
-@@ -408,6 +410,7 @@ enum csi2_fmt {
+@@ -178,6 +183,10 @@
+ #define RCAR_VIN_BT656 (1 << 3)
+ #define RCAR_VIN_CSI2 (1 << 4)
+
++static int lut_reverse;
++module_param(lut_reverse, int, 0644);
++MODULE_PARM_DESC(lut_reverse, " Use LUT for data order reverse (only 8-bit data allowed)*/");
++
+ static int ifmd0_reg_match[VNCSI_IFMD_SEL_NUMBER];
+ static int ifmd4_reg_match[VNCSI_IFMD_SEL_NUMBER];
+ static int ifmd0_init = true;
+@@ -408,6 +417,7 @@ enum csi2_fmt {
RCAR_CSI_FMT_NONE = -1,
RCAR_CSI_RGB888,
RCAR_CSI_YCBCR422,
@@ -7282,11 +8037,12 @@ index 74fb005..496a8bd 100644
};
struct vin_coeff {
-@@ -773,10 +776,13 @@ struct rcar_vin_priv {
+@@ -773,10 +783,14 @@ struct rcar_vin_priv {
enum csi2_fmt csi_fmt;
enum virtual_ch vc;
bool csi_sync;
+ bool deser_sync;
++ int lut_updated;
struct rcar_vin_async_client *async_client;
/* Asynchronous CSI2 linking */
@@ -7296,7 +8052,16 @@ index 74fb005..496a8bd 100644
/* Synchronous probing compatibility */
struct platform_device *csi2_pdev;
-@@ -989,6 +995,10 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv)
+@@ -939,6 +953,8 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv)
+ struct rcar_vin_cam *cam = icd->host_priv;
+ u32 vnmc, dmr, interrupts;
+ bool progressive = false, output_is_yuv = false, input_is_yuv = false;
++ int i;
++ u32 lutd;
+
+ switch (priv->field) {
+ case V4L2_FIELD_TOP:
+@@ -989,6 +1005,10 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv)
VNMC_INF_YUV10_BT656 : VNMC_INF_YUV10_BT601;
input_is_yuv = true;
break;
@@ -7307,7 +8072,7 @@ index 74fb005..496a8bd 100644
default:
break;
}
-@@ -1021,6 +1031,10 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv)
+@@ -1021,6 +1041,10 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv)
dmr = 0;
output_is_yuv = true;
break;
@@ -7318,7 +8083,7 @@ index 74fb005..496a8bd 100644
case V4L2_PIX_FMT_ARGB555:
dmr = VNDMR_DTMD_ARGB;
break;
-@@ -1043,6 +1057,10 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv)
+@@ -1043,6 +1067,10 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv)
dmr = VNDMR_EXRGB | VNDMR_DTMD_ARGB;
break;
@@ -7329,7 +8094,7 @@ index 74fb005..496a8bd 100644
default:
goto e_format;
}
-@@ -1061,7 +1079,9 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv)
+@@ -1061,7 +1089,9 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv)
else
vnmc |= VNMC_DPINE;
@@ -7340,7 +8105,41 @@ index 74fb005..496a8bd 100644
&& is_scaling(cam))
vnmc |= VNMC_SCLE;
}
-@@ -1211,6 +1231,10 @@ static void rcar_vin_videobuf_queue(struct vb2_buffer *vb)
+@@ -1073,6 +1103,33 @@ static int rcar_vin_setup(struct rcar_vin_priv *priv)
+ if (vin_debug)
+ interrupts |= VNIE_FOE;
+
++ if (lut_reverse && !priv->lut_updated) {
++ iowrite32(0, priv->base + VNLUTP_REG);
++
++ for (i = 0; i < 1024; i++) {
++ /* reverse MSB 8bits image at 10bit LUT address */
++ lutd = ((i >> 2) & BIT(0) ? BIT(7) : 0);
++ lutd |= ((i >> 2) & BIT(1) ? BIT(6) : 0);
++ lutd |= ((i >> 2) & BIT(2) ? BIT(5) : 0);
++ lutd |= ((i >> 2) & BIT(3) ? BIT(4) : 0);
++ lutd |= ((i >> 2) & BIT(4) ? BIT(3) : 0);
++ lutd |= ((i >> 2) & BIT(5) ? BIT(2) : 0);
++ lutd |= ((i >> 2) & BIT(6) ? BIT(1) : 0);
++ lutd |= ((i >> 2) & BIT(7) ? BIT(0) : 0);
++#if 0
++ /* strait (no any density convertion, used for testing) */
++ lutd = i >> 2;
++#endif
++ lutd = (lutd << 16) | (lutd << 8) | lutd;
++ iowrite32(lutd, priv->base + VNLUTD_REG);
++ }
++ /* update LUT table once */
++ priv->lut_updated = 1;
++ }
++
++ if (lut_reverse)
++ vnmc |= VNMC_LUTE;
++
+ /* ack interrupts */
+ iowrite32(interrupts, priv->base + VNINTS_REG);
+ /* enable interrupts */
+@@ -1211,6 +1268,10 @@ static void rcar_vin_videobuf_queue(struct vb2_buffer *vb)
*/
static void rcar_vin_wait_stop_streaming(struct rcar_vin_priv *priv)
{
@@ -7351,14 +8150,14 @@ index 74fb005..496a8bd 100644
while (priv->state != STOPPED) {
/* issue stop if running */
if (priv->state == RUNNING)
-@@ -1361,6 +1385,31 @@ static struct v4l2_subdev *find_csi2(struct rcar_vin_priv *pcdev)
+@@ -1361,6 +1422,31 @@ static struct v4l2_subdev *find_csi2(struct rcar_vin_priv *pcdev)
return NULL;
}
+static struct v4l2_subdev *find_deser(struct rcar_vin_priv *pcdev)
+{
+ struct v4l2_subdev *sd;
-+ char name[] = "max9286_max9271";
++ char name[] = "max9286";
+ char name2[] = "ti964_ti9x3";
+ char name3[] = "ti954_ti9x3";
+
@@ -7383,7 +8182,7 @@ index 74fb005..496a8bd 100644
static int rcar_vin_add_device(struct soc_camera_device *icd)
{
struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
-@@ -1375,7 +1424,8 @@ static int rcar_vin_add_device(struct soc_camera_device *icd)
+@@ -1375,7 +1461,8 @@ static int rcar_vin_add_device(struct soc_camera_device *icd)
if (priv->chip == RCAR_H3 || priv->chip == RCAR_M3 ||
priv->chip == RCAR_V3M) {
struct v4l2_subdev *csi2_sd = find_csi2(priv);
@@ -7393,7 +8192,7 @@ index 74fb005..496a8bd 100644
if (csi2_sd) {
csi2_sd->grp_id = soc_camera_grp_id(icd);
-@@ -1390,6 +1440,18 @@ static int rcar_vin_add_device(struct soc_camera_device *icd)
+@@ -1390,6 +1477,18 @@ static int rcar_vin_add_device(struct soc_camera_device *icd)
if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
return ret;
}
@@ -7412,7 +8211,7 @@ index 74fb005..496a8bd 100644
/*
* -ENODEV is special:
* either csi2_sd == NULL or the CSI-2 driver
-@@ -1417,6 +1479,7 @@ static void rcar_vin_remove_device(struct soc_camera_device *icd)
+@@ -1417,6 +1516,7 @@ static void rcar_vin_remove_device(struct soc_camera_device *icd)
struct rcar_vin_priv *priv = ici->priv;
struct vb2_v4l2_buffer *vbuf;
struct v4l2_subdev *csi2_sd = find_csi2(priv);
@@ -7420,7 +8219,7 @@ index 74fb005..496a8bd 100644
int i;
/* disable capture, disable interrupts */
-@@ -1443,6 +1506,8 @@ static void rcar_vin_remove_device(struct soc_camera_device *icd)
+@@ -1443,6 +1543,8 @@ static void rcar_vin_remove_device(struct soc_camera_device *icd)
if ((csi2_sd) && (priv->csi_sync))
v4l2_subdev_call(csi2_sd, core, s_power, 0);
@@ -7429,7 +8228,7 @@ index 74fb005..496a8bd 100644
dev_dbg(icd->parent, "R-Car VIN driver detached from camera %d\n",
icd->devnum);
-@@ -1621,13 +1686,19 @@ static int rcar_vin_set_rect(struct soc_camera_device *icd)
+@@ -1621,13 +1723,19 @@ static int rcar_vin_set_rect(struct soc_camera_device *icd)
if (priv->chip == RCAR_H3 || priv->chip == RCAR_M3 ||
priv->chip == RCAR_V3M) {
@@ -7451,7 +8250,7 @@ index 74fb005..496a8bd 100644
(icd->current_fmt->host_fmt->fourcc == V4L2_PIX_FMT_NV16) ||
(icd->current_fmt->host_fmt->fourcc == V4L2_PIX_FMT_NV12))
iowrite32(ALIGN(cam->out_width, 0x20),
-@@ -1868,6 +1939,14 @@ static bool rcar_vin_packing_supported(const struct soc_mbus_pixelfmt *fmt)
+@@ -1868,6 +1976,14 @@ static bool rcar_vin_packing_supported(const struct soc_mbus_pixelfmt *fmt)
.layout = SOC_MBUS_LAYOUT_PACKED,
},
{
@@ -7466,7 +8265,7 @@ index 74fb005..496a8bd 100644
.fourcc = V4L2_PIX_FMT_RGB565,
.name = "RGB565",
.bits_per_sample = 16,
-@@ -1899,6 +1978,22 @@ static bool rcar_vin_packing_supported(const struct soc_mbus_pixelfmt *fmt)
+@@ -1899,6 +2015,22 @@ static bool rcar_vin_packing_supported(const struct soc_mbus_pixelfmt *fmt)
.order = SOC_MBUS_ORDER_LE,
.layout = SOC_MBUS_LAYOUT_PACKED,
},
@@ -7489,7 +8288,7 @@ index 74fb005..496a8bd 100644
};
static int rcar_vin_get_formats(struct soc_camera_device *icd, unsigned int idx,
-@@ -2012,6 +2107,8 @@ static int rcar_vin_get_formats(struct soc_camera_device *icd, unsigned int idx,
+@@ -2012,6 +2144,8 @@ static int rcar_vin_get_formats(struct soc_camera_device *icd, unsigned int idx,
case MEDIA_BUS_FMT_YUYV8_2X8:
case MEDIA_BUS_FMT_YUYV10_2X10:
case MEDIA_BUS_FMT_RGB888_1X24:
@@ -7498,7 +8297,7 @@ index 74fb005..496a8bd 100644
if (cam->extra_fmt)
break;
-@@ -2218,12 +2315,15 @@ static int rcar_vin_set_fmt(struct soc_camera_device *icd,
+@@ -2218,12 +2352,15 @@ static int rcar_vin_set_fmt(struct soc_camera_device *icd,
case V4L2_PIX_FMT_ABGR32:
case V4L2_PIX_FMT_UYVY:
case V4L2_PIX_FMT_YUYV:
@@ -7514,7 +8313,7 @@ index 74fb005..496a8bd 100644
default:
can_scale = false;
break;
-@@ -2316,7 +2416,8 @@ static int rcar_vin_try_fmt(struct soc_camera_device *icd,
+@@ -2316,7 +2453,8 @@ static int rcar_vin_try_fmt(struct soc_camera_device *icd,
/* odd number clipping by pixel post clip processing, */
/* it is outputted to a memory per even pixels. */
if ((pixfmt == V4L2_PIX_FMT_NV16) || (pixfmt == V4L2_PIX_FMT_NV12) ||
@@ -7524,7 +8323,7 @@ index 74fb005..496a8bd 100644
v4l_bound_align_image(&pix->width, 5, priv->max_width, 1,
&pix->height, 2, priv->max_height, 0, 0);
else
-@@ -2486,6 +2587,19 @@ static int rcar_vin_cropcap(struct soc_camera_device *icd,
+@@ -2486,6 +2624,19 @@ static int rcar_vin_cropcap(struct soc_camera_device *icd,
}
#endif
@@ -7544,7 +8343,7 @@ index 74fb005..496a8bd 100644
static struct soc_camera_host_ops rcar_vin_host_ops = {
.owner = THIS_MODULE,
.add = rcar_vin_add_device,
-@@ -2504,6 +2618,7 @@ static int rcar_vin_cropcap(struct soc_camera_device *icd,
+@@ -2504,6 +2655,7 @@ static int rcar_vin_cropcap(struct soc_camera_device *icd,
.get_selection = rcar_vin_get_selection,
.cropcap = rcar_vin_cropcap,
#endif
@@ -7552,7 +8351,7 @@ index 74fb005..496a8bd 100644
};
#ifdef CONFIG_OF
-@@ -2524,7 +2639,7 @@ static int rcar_vin_cropcap(struct soc_camera_device *icd,
+@@ -2524,7 +2676,7 @@ static int rcar_vin_cropcap(struct soc_camera_device *icd,
MODULE_DEVICE_TABLE(of, rcar_vin_of_table);
#endif
@@ -7561,7 +8360,7 @@ index 74fb005..496a8bd 100644
static DECLARE_BITMAP(device_map, MAP_MAX_NUM);
static DEFINE_MUTEX(list_lock);
-@@ -2714,7 +2829,11 @@ static int rcar_vin_probe(struct platform_device *pdev)
+@@ -2714,7 +2866,11 @@ static int rcar_vin_probe(struct platform_device *pdev)
const char *str;
unsigned int i;
struct device_node *epn = NULL, *ren = NULL;
@@ -7573,7 +8372,7 @@ index 74fb005..496a8bd 100644
match = of_match_device(of_match_ptr(rcar_vin_of_table), &pdev->dev);
-@@ -2741,13 +2860,27 @@ static int rcar_vin_probe(struct platform_device *pdev)
+@@ -2741,13 +2897,27 @@ static int rcar_vin_probe(struct platform_device *pdev)
dev_dbg(&pdev->dev, "node name:%s\n",
of_node_full_name(ren->parent));
@@ -7584,7 +8383,7 @@ index 74fb005..496a8bd 100644
+ }
- of_node_put(ren);
-+ if (strcmp(ren->parent->name, "max9286-max9271") == 0) {
++ if (strcmp(ren->parent->name, "max9286") == 0) {
+ max9286_ren = of_parse_phandle(epn, "remote-endpoint", 0);
+ max9286_use = true;
+ }
@@ -7605,7 +8404,7 @@ index 74fb005..496a8bd 100644
}
ret = v4l2_of_parse_endpoint(np, &ep);
-@@ -2799,6 +2932,7 @@ static int rcar_vin_probe(struct platform_device *pdev)
+@@ -2799,6 +2969,7 @@ static int rcar_vin_probe(struct platform_device *pdev)
priv->ici.drv_name = dev_name(&pdev->dev);
priv->ici.ops = &rcar_vin_host_ops;
priv->csi_sync = false;
@@ -7613,7 +8412,7 @@ index 74fb005..496a8bd 100644
priv->pdata_flags = pdata_flags;
if (!match) {
-@@ -2983,7 +3117,25 @@ static int rcar_vin_probe(struct platform_device *pdev)
+@@ -2983,7 +3154,25 @@ static int rcar_vin_probe(struct platform_device *pdev)
goto cleanup;
if (csi_use) {
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch
index 9db9056..5387ae8 100644
--- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0040-arm64-dts-renesas-add-ADAS-boards.patch
@@ -18,45 +18,51 @@ Kingfisher board on R8A7797 SoC
Videobox board on R8A7795 ES1.x SoC
Videobox board on R8A7795 SoC
Eagle board on R8A7797 SoC
+Eagle Function board on R8A7797 SoC
V3MSK board on R8A7797 SoC
V3MSK.View board on R8A7797 SoC
Videobox Mini board on R8A7795 ES1.x SoC
Videobox Mini board on R8A7795 SoC
Videobox Mini board on R8A7797 SoC
+Videobox2 board on R8A7795 ES1.x SoC
+Videobox2 board on R8A7795 SoC
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
- arch/arm64/boot/dts/renesas/Makefile | 19 +
+ arch/arm64/boot/dts/renesas/Makefile | 20 +
arch/arm64/boot/dts/renesas/legacy/Makefile | 8 +
.../renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts | 1710 +++++++++++++++++++
.../renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts | 441 +++++
.../dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts | 1724 +++++++++++++++++++
- .../dts/renesas/legacy/r8a7795-h3ulcb-kf-v1.dts | 465 ++++++
- .../dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts | 1214 ++++++++++++++
- .../dts/renesas/legacy/r8a7796-m3ulcb-kf-v1.dts | 465 ++++++
+ .../dts/renesas/legacy/r8a7795-h3ulcb-kf-v1.dts | 465 +++++
+ .../dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts | 1214 +++++++++++++
+ .../dts/renesas/legacy/r8a7796-m3ulcb-kf-v1.dts | 465 +++++
.../dts/renesas/legacy/r8a7797-v3msk-kf-v0.dts | 82 +
.../boot/dts/renesas/legacy/ulcb-kf-cmos.dtsi | 75 +
.../arm64/boot/dts/renesas/legacy/ulcb-kf-rpi.dtsi | 77 +
.../dts/renesas/r8a7795-es1-h3ulcb-had-alfa.dts | 22 +
.../dts/renesas/r8a7795-es1-h3ulcb-had-beta.dts | 23 +
- .../boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi | 225 +++
+ .../boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi | 221 +++
.../boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts | 39 +
.../boot/dts/renesas/r8a7795-es1-h3ulcb-vb.dts | 69 +
+ .../boot/dts/renesas/r8a7795-es1-h3ulcb-vb2.dts | 77 +
.../boot/dts/renesas/r8a7795-es1-h3ulcb-vbm.dts | 26 +
- .../boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts | 546 +++++++
- .../dts/renesas/r8a7795-es1-salvator-x-view.dts | 552 +++++++
+ .../boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts | 546 ++++++
+ .../dts/renesas/r8a7795-es1-salvator-x-view.dts | 552 ++++++
.../boot/dts/renesas/r8a7795-h3ulcb-had-alfa.dts | 22 +
.../boot/dts/renesas/r8a7795-h3ulcb-had-beta.dts | 23 +
- .../arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi | 219 +++
+ .../arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi | 215 +++
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts | 39 +
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts | 68 +
+ arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb2.dts | 68 +
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vbm.dts | 26 +
- .../arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts | 546 +++++++
- .../boot/dts/renesas/r8a7795-salvator-x-view.dts | 552 +++++++
+ .../arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts | 546 ++++++
+ .../boot/dts/renesas/r8a7795-salvator-x-view.dts | 552 ++++++
arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts | 40 +
.../arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts | 287 ++++
.../boot/dts/renesas/r8a7796-salvator-x-view.dts | 318 ++++
- arch/arm64/boot/dts/renesas/r8a7797-eagle.dts | 560 +++++++
+ .../boot/dts/renesas/r8a7797-eagle-function.dts | 62 +
+ arch/arm64/boot/dts/renesas/r8a7797-eagle.dts | 575 +++++++
arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts | 578 +++++++
arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts | 518 ++++++
arch/arm64/boot/dts/renesas/r8a7797-v3msk-view.dts | 298 ++++
@@ -64,11 +70,12 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi | 545 ++++++
arch/arm64/boot/dts/renesas/ulcb-kf-most.dtsi | 30 +
arch/arm64/boot/dts/renesas/ulcb-kf-sd3.dtsi | 46 +
- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 1541 +++++++++++++++++
+ arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 1542 +++++++++++++++++
arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi | 515 ++++++
- arch/arm64/boot/dts/renesas/ulcb-vb.dtsi | 1726 ++++++++++++++++++++
+ arch/arm64/boot/dts/renesas/ulcb-vb.dtsi | 1726 +++++++++++++++++++
+ arch/arm64/boot/dts/renesas/ulcb-vb2.dtsi | 1792 ++++++++++++++++++++
arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi | 578 +++++++
- 42 files changed, 17171 insertions(+)
+ 46 files changed, 19179 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/legacy/Makefile
create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts
create mode 100644 arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v1.dts
@@ -84,6 +91,7 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb.dts
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb2.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vbm.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts
@@ -92,12 +100,14 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb.dts
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb2.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vbm.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-eagle-function.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-eagle.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts
@@ -109,13 +119,14 @@ Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
create mode 100644 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vb.dtsi
+ create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vb2.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
-index f9c71df..af88350 100644
+index f9c71df..1c63893 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
-@@ -6,5 +6,24 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
+@@ -6,5 +6,25 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs.dtb
@@ -128,8 +139,9 @@ index f9c71df..af88350 100644
+dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-had-alfa.dtb r8a7795-h3ulcb-had-beta.dtb r8a7795-es1-h3ulcb-had-alfa.dtb r8a7795-es1-h3ulcb-had-beta.dtb
+dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb r8a7795-es1-h3ulcb-kf.dtb
+dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-vb.dtb r8a7795-es1-h3ulcb-vb.dtb
++dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-vb2.dtb r8a7795-es1-h3ulcb-vb2.dtb
+dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-vbm.dtb r8a7795-es1-h3ulcb-vbm.dtb
-+dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-eagle.dtb
++dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-eagle.dtb r8a7797-eagle-function.dtb
+dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk.dtb
+dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-view.dtb
+dtb-$(CONFIG_ARCH_R8A7797) += r8a7797-v3msk-kf.dtb
@@ -156,7 +168,7 @@ index 0000000..7f25079
+clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts
new file mode 100644
-index 0000000..2fee788
+index 0000000..fe07e22
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/legacy/r8a7795-es1-h3ulcb-kf-v0.dts
@@ -0,0 +1,1710 @@
@@ -895,8 +907,8 @@ index 0000000..2fee788
+ };
+
+ /* MAX9286 @ 0x2c */
-+ max9286-max9271@0 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@0 {
++ compatible = "maxim,max9286";
+ reg = <0x2c>;
+ maxim,sensor_delay = <350>;
+ maxim,links = <4>;
@@ -1104,8 +1116,8 @@ index 0000000..2fee788
+ };
+
+ /* MAX9286 @ 0x2c */
-+ max9286-max9271@1 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@1 {
++ compatible = "maxim,max9286";
+ reg = <0x2c>;
+ maxim,sensor_delay = <350>;
+ maxim,links = <4>;
@@ -2319,7 +2331,7 @@ index 0000000..ac6a12b
+};
diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts
new file mode 100644
-index 0000000..78c766b
+index 0000000..c19bc58
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/legacy/r8a7795-h3ulcb-kf-v0.dts
@@ -0,0 +1,1724 @@
@@ -3058,8 +3070,8 @@ index 0000000..78c766b
+ };
+
+ /* MAX9286 @ 0x2c */
-+ max9286-max9271@0 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@0 {
++ compatible = "maxim,max9286";
+ reg = <0x2c>;
+ maxim,sensor_delay = <350>;
+ maxim,links = <4>;
@@ -3267,8 +3279,8 @@ index 0000000..78c766b
+ };
+
+ /* MAX9286 @ 0x2c */
-+ max9286-max9271@1 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@1 {
++ compatible = "maxim,max9286";
+ reg = <0x2c>;
+ maxim,sensor_delay = <350>;
+ maxim,links = <4>;
@@ -4520,7 +4532,7 @@ index 0000000..14b6f52
+};
diff --git a/arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts b/arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts
new file mode 100644
-index 0000000..ffa1879
+index 0000000..8e7de0f
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/legacy/r8a7796-m3ulcb-kf-v0.dts
@@ -0,0 +1,1214 @@
@@ -5259,8 +5271,8 @@ index 0000000..ffa1879
+ };
+
+ /* MAX9286 @ 0x2c */
-+ max9286-max9271@0 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@0 {
++ compatible = "maxim,max9286";
+ reg = <0x2c>;
+ maxim,sensor_delay = <350>;
+ maxim,links = <4>;
@@ -6520,10 +6532,10 @@ index 0000000..2f8b274
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi
new file mode 100644
-index 0000000..d50ff7a
+index 0000000..dd399f4
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi
-@@ -0,0 +1,225 @@
+@@ -0,0 +1,221 @@
+/*
+ * Device Tree Source for the H3ULCB.HAD board on r8a7795 ES1.x
+ *
@@ -6546,15 +6558,11 @@ index 0000000..d50ff7a
+ model = "Renesas H3ULCB.HAD board based on r8a7795";
+
+ aliases {
-+ serial1 = &scif1;
++ serial0 = &scif1;
+ spi1 = &spi0_gpio;
+ spi2 = &spi1_gpio;
+ };
+
-+ chosen {
-+ stdout-path = "serial1:115200n8";
-+ };
-+
+ spi0_gpio: spi_gpio@0 {
+ compatible = "spi-gpio";
+ num-chipselects = <1>;
@@ -6869,6 +6877,89 @@ index 0000000..549a717
+&hsusb {
+ status = "okay";
+};
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb2.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb2.dts
+new file mode 100644
+index 0000000..1a8db57
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vb2.dts
+@@ -0,0 +1,77 @@
++/*
++ * Device Tree Source for the H3ULCB Videobox board V2 on r8a7795
++ *
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include "r8a7795-es1-h3ulcb.dts"
++#include "ulcb-vb2.dtsi"
++
++/ {
++ model = "Renesas H3ULCB Videobox board based on r8a7795";
++
++ hdmi1-out {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi1_con: endpoint {
++ remote-endpoint = <&rcar_dw_hdmi1_out>;
++ };
++ };
++ };
++};
++
++&pfc {
++ usb31_pins: usb31 {
++ groups = "usb31";
++ function = "usb31";
++ };
++};
++
++&du {
++ ports {
++ port@2 {
++ endpoint {
++ remote-endpoint = <&rcar_dw_hdmi1_in>;
++ };
++ };
++ port@3 {
++ endpoint {
++ remote-endpoint = <&lvds_enc_in>;
++ };
++ };
++ };
++};
++
++&hdmi1 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ rcar_dw_hdmi1_in: endpoint {
++ remote-endpoint = <&du_out_hdmi1>;
++ };
++ };
++ port@1 {
++ reg = <1>;
++ rcar_dw_hdmi1_out: endpoint {
++ remote-endpoint = <&hdmi1_con>;
++ };
++ };
++ };
++};
++
++&xhci1 {
++ status = "okay";
++ pinctrl-0 = <&usb31_pins>;
++ pinctrl-names = "default";
++};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vbm.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-vbm.dts
new file mode 100644
index 0000000..323722c
@@ -6903,7 +6994,7 @@ index 0000000..323722c
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts
new file mode 100644
-index 0000000..de56fa4
+index 0000000..6eb7cac
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-view.dts
@@ -0,0 +1,546 @@
@@ -7069,8 +7160,8 @@ index 0000000..de56fa4
+ };
+ };
+
-+ max9286-max9271@0 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@0 {
++ compatible = "maxim,max9286";
+ reg = <0x4c>;
+ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ maxim,sensor_delay = <0>;
@@ -7111,8 +7202,8 @@ index 0000000..de56fa4
+ };
+ };
+
-+ max9286-max9271@1 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@1 {
++ compatible = "maxim,max9286";
+ reg = <0x6c>;
+ gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
+ maxim,sensor_delay = <0>;
@@ -7455,7 +7546,7 @@ index 0000000..de56fa4
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts
new file mode 100644
-index 0000000..3f3d66a
+index 0000000..d4caf46
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x-view.dts
@@ -0,0 +1,552 @@
@@ -7636,8 +7727,8 @@ index 0000000..3f3d66a
+ };
+ };
+
-+ max9286-max9271@0 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@0 {
++ compatible = "maxim,max9286";
+ reg = <0x4c>;
+ gpios = <&gpio6 30 GPIO_ACTIVE_LOW>;
+ maxim,sensor_delay = <0>;
@@ -7678,8 +7769,8 @@ index 0000000..3f3d66a
+ };
+ };
+
-+ max9286-max9271@1 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@1 {
++ compatible = "maxim,max9286";
+ reg = <0x6c>;
+ maxim,sensor_delay = <0>;
+ maxim,links = <4>;
@@ -8070,10 +8161,10 @@ index 0000000..805067e
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi
new file mode 100644
-index 0000000..4a00426
+index 0000000..d1bbea4
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-had.dtsi
-@@ -0,0 +1,219 @@
+@@ -0,0 +1,215 @@
+/*
+ * Device Tree Source for the H3ULCB.HAD board on r8a7795
+ *
@@ -8096,15 +8187,11 @@ index 0000000..4a00426
+ model = "Renesas H3ULCB.HAD board based on r8a7795";
+
+ aliases {
-+ serial1 = &scif1;
++ serial0 = &scif1;
+ spi1 = &spi0_gpio;
+ spi2 = &spi1_gpio;
+ };
+
-+ chosen {
-+ stdout-path = "serial1:115200n8";
-+ };
-+
+ spi0_gpio: spi_gpio@0 {
+ compatible = "spi-gpio";
+ num-chipselects = <1>;
@@ -8412,6 +8499,80 @@ index 0000000..330bba2
+&hsusb0 {
+ status = "okay";
+};
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb2.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb2.dts
+new file mode 100644
+index 0000000..e862d3e
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb2.dts
+@@ -0,0 +1,68 @@
++/*
++ * Device Tree Source for the H3ULCB Videobox board V2 on r8a7795
++ *
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include "r8a7795-h3ulcb.dts"
++#include "ulcb-vb2.dtsi"
++
++/ {
++ model = "Renesas H3ULCB Videobox board based on r8a7795";
++
++ hdmi1-out {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi1_con: endpoint {
++ remote-endpoint = <&rcar_dw_hdmi1_out>;
++ };
++ };
++ };
++};
++
++&du {
++ ports {
++ port@2 {
++ endpoint {
++ remote-endpoint = <&rcar_dw_hdmi1_in>;
++ };
++ };
++ port@3 {
++ endpoint {
++ remote-endpoint = <&lvds_enc_in>;
++ };
++ };
++ };
++};
++
++&hdmi1 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ rcar_dw_hdmi1_in: endpoint {
++ remote-endpoint = <&du_out_hdmi1>;
++ };
++ };
++ port@1 {
++ reg = <1>;
++ rcar_dw_hdmi1_out: endpoint {
++ remote-endpoint = <&hdmi1_con>;
++ };
++ };
++ };
++};
++
++&hsusb0 {
++ status = "okay";
++};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vbm.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vbm.dts
new file mode 100644
index 0000000..87f1889
@@ -8446,7 +8607,7 @@ index 0000000..87f1889
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts
new file mode 100644
-index 0000000..2c24b85
+index 0000000..8541518
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-view.dts
@@ -0,0 +1,546 @@
@@ -8612,8 +8773,8 @@ index 0000000..2c24b85
+ };
+ };
+
-+ max9286-max9271@0 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@0 {
++ compatible = "maxim,max9286";
+ reg = <0x4c>;
+ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ maxim,sensor_delay = <0>;
@@ -8654,8 +8815,8 @@ index 0000000..2c24b85
+ };
+ };
+
-+ max9286-max9271@1 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@1 {
++ compatible = "maxim,max9286";
+ reg = <0x6c>;
+ gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
+ maxim,sensor_delay = <0>;
@@ -8998,7 +9159,7 @@ index 0000000..2c24b85
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts
new file mode 100644
-index 0000000..fb12a39f3
+index 0000000..14539ea
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x-view.dts
@@ -0,0 +1,552 @@
@@ -9179,8 +9340,8 @@ index 0000000..fb12a39f3
+ };
+ };
+
-+ max9286-max9271@0 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@0 {
++ compatible = "maxim,max9286";
+ reg = <0x4c>;
+ gpios = <&gpio6 30 GPIO_ACTIVE_LOW>;
+ maxim,sensor_delay = <0>;
@@ -9221,8 +9382,8 @@ index 0000000..fb12a39f3
+ };
+ };
+
-+ max9286-max9271@1 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@1 {
++ compatible = "maxim,max9286";
+ reg = <0x6c>;
+ maxim,sensor_delay = <0>;
+ maxim,links = <4>;
@@ -9602,7 +9763,7 @@ index 0000000..a409402
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts
new file mode 100644
-index 0000000..1ac0041
+index 0000000..ea7f378
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-view.dts
@@ -0,0 +1,287 @@
@@ -9696,8 +9857,8 @@ index 0000000..1ac0041
+ };
+ };
+
-+ max9286-max9271@0 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@0 {
++ compatible = "maxim,max9286";
+ reg = <0x4c>;
+ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ maxim,sensor_delay = <0>;
@@ -9895,7 +10056,7 @@ index 0000000..1ac0041
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts
new file mode 100644
-index 0000000..cc6866c
+index 0000000..319120f
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x-view.dts
@@ -0,0 +1,318 @@
@@ -10004,8 +10165,8 @@ index 0000000..cc6866c
+ };
+ };
+
-+ max9286-max9271@0 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@0 {
++ compatible = "maxim,max9286";
+ reg = <0x4c>;
+ gpios = <&gpio6 30 GPIO_ACTIVE_LOW>;
+ maxim,sensor_delay = <0>;
@@ -10217,12 +10378,80 @@ index 0000000..cc6866c
+ pinctrl-names = "default";
+ status = "okay";
+};
+diff --git a/arch/arm64/boot/dts/renesas/r8a7797-eagle-function.dts b/arch/arm64/boot/dts/renesas/r8a7797-eagle-function.dts
+new file mode 100644
+index 0000000..82d6513
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a7797-eagle-function.dts
+@@ -0,0 +1,62 @@
++/*
++ * Device Tree Source for the Eagle Function board on r8a7797
++ *
++ * Copyright (C) 2017 Renesas Electronics Corp.
++ * Copyright (C) 2017 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include "r8a7797-eagle.dts"
++
++/ {
++ model = "Renesas Eagle Function board based on r8a7797";
++
++ vcc_3v3: regulator0 {
++ compatible = "regulator-fixed";
++ regulator-name = "fixed-VCC3V3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vcc_vddq_vin0: regulator1 {
++ compatible = "regulator-fixed";
++ regulator-name = "VCC-VDDQ-VIN0";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++};
++
++&pfc {
++ sdhi2_pins_1v8: sdhi2_1v8 {
++ groups = "mmc_data8", "mmc_ctrl";
++ function = "mmc";
++ power-source = <1800>;
++ };
++
++ sdhi2_pins_3v3: sdhi2_3v3 {
++ groups = "mmc_data8", "mmc_ctrl";
++ function = "mmc";
++ power-source = <3300>;
++ };
++};
++
++&sdhi2 {
++ /* used for on-board eMMC */
++ pinctrl-0 = <&sdhi2_pins_3v3>;
++ pinctrl-1 = <&sdhi2_pins_1v8>;
++ pinctrl-names = "default", "state_uhs";
++
++ vmmc-supply = <&vcc_3v3>;
++ vqmmc-supply = <&vcc_vddq_vin0>;
++ mmc-hs200-1_8v;
++ bus-width = <8>;
++ non-removable;
++ status = "okay";
++};
diff --git a/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts b/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts
new file mode 100644
-index 0000000..3fb3bf1
+index 0000000..ce7a88e
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7797-eagle.dts
-@@ -0,0 +1,560 @@
+@@ -0,0 +1,575 @@
+/*
+ * Device Tree Source for the Eagle board
+ *
@@ -10394,6 +10623,11 @@ index 0000000..3fb3bf1
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
++ canfd0_pins: canfd0 {
++ groups = "canfd0_data_a";
++ function = "canfd0";
++ };
++
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
@@ -10563,8 +10797,8 @@ index 0000000..3fb3bf1
+ };
+ };
+
-+ max9286-max9271@0 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@0 {
++ compatible = "maxim,max9286";
+ reg = <0x48>;
+ gpios = <&gpio_ext 0 GPIO_ACTIVE_LOW>; /* CSI0 DE_PDn */
+ maxim,gpio0 = <0>;
@@ -10750,6 +10984,16 @@ index 0000000..3fb3bf1
+ };
+};
+
++&canfd {
++ pinctrl-0 = <&canfd0_pins>;
++ pinctrl-names = "default";
++ status = "okay";
++
++ channel0 {
++ status = "okay";
++ };
++};
++
+&csi2_40 {
+ status = "okay";
+
@@ -10785,7 +11029,7 @@ index 0000000..3fb3bf1
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts
new file mode 100644
-index 0000000..979cebe
+index 0000000..b92fe83
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-kf.dts
@@ -0,0 +1,578 @@
@@ -11041,8 +11285,8 @@ index 0000000..979cebe
+ };
+
+ /* MAX9286 @ 0x2c */
-+ max9286-max9271@0 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@0 {
++ compatible = "maxim,max9286";
+ reg = <0x2c>;
+ maxim,sensor_delay = <350>;
+ maxim,links = <4>;
@@ -11369,7 +11613,7 @@ index 0000000..979cebe
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts
new file mode 100644
-index 0000000..4292b7b
+index 0000000..26f8c70
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-vbm.dts
@@ -0,0 +1,518 @@
@@ -11580,8 +11824,8 @@ index 0000000..4292b7b
+ };
+ };
+
-+ max9286-max9271@0 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@0 {
++ compatible = "maxim,max9286";
+ reg = <0x2c>;
+ maxim,sensor_delay = <350>;
+ maxim,links = <4>;
@@ -11661,7 +11905,7 @@ index 0000000..4292b7b
+ };
+ port@1 {
+ ti964_csi0ep0: endpoint {
-+ csi-rate = <1450>;
++ csi-rate = <700>;
+ remote-endpoint = <&csi2_40_ep>;
+ };
+ };
@@ -11893,7 +12137,7 @@ index 0000000..4292b7b
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk-view.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-view.dts
new file mode 100644
-index 0000000..573e2bc
+index 0000000..6f82385
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk-view.dts
@@ -0,0 +1,298 @@
@@ -12026,8 +12270,8 @@ index 0000000..573e2bc
+ };
+ };
+
-+ max9286-max9271@0 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@0 {
++ compatible = "maxim,max9286";
+ reg = <0x6c>;
+ gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ maxim,sensor_delay = <0>;
@@ -12517,7 +12761,7 @@ index 0000000..91d10c5
+};
diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi
new file mode 100644
-index 0000000..589a774
+index 0000000..b469ca6
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf-cn11.dtsi
@@ -0,0 +1,545 @@
@@ -12747,8 +12991,8 @@ index 0000000..589a774
+ };
+
+ /* MAX9286 @ 0x2c */
-+ max9286-max9271@1 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@1 {
++ compatible = "maxim,max9286";
+ reg = <0x2c>;
+ maxim,sensor_delay = <350>;
+ maxim,links = <4>;
@@ -12756,10 +13000,10 @@ index 0000000..589a774
+ maxim,resetb-gpio = <1>;
+ maxim,fsync-mode = "automatic";
+ maxim,timeout = <100>;
-+ POC0-supply = <&pwr0B>;
-+ POC1-supply = <&pwr1B>;
-+ POC2-supply = <&pwr2B>;
-+ POC3-supply = <&pwr3B>;
++ POC0-supply = <&pwr1B>;
++ POC1-supply = <&pwr0B>;
++ POC2-supply = <&pwr3B>;
++ POC3-supply = <&pwr2B>;
+
+ port@0 {
+ max9286_des1ep0: endpoint@0 {
@@ -13156,10 +13400,10 @@ index 0000000..b854216
+};
diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
new file mode 100644
-index 0000000..5958450
+index 0000000..d7ffd79
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
-@@ -0,0 +1,1541 @@
+@@ -0,0 +1,1542 @@
+/*
+ * Device Tree Source for the ULCB Kingfisher board
+ *
@@ -14130,19 +14374,20 @@ index 0000000..5958450
+ };
+
+ /* MAX9286 @ 0x2c */
-+ max9286-max9271@0 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@0 {
++ compatible = "maxim,max9286";
+ reg = <0x2c>;
+ maxim,sensor_delay = <350>;
+ maxim,links = <4>;
+ maxim,lanes = <4>;
+ maxim,resetb-gpio = <1>;
+ maxim,fsync-mode = "automatic";
++
+ maxim,timeout = <100>;
-+ POC0-supply = <&pwr0A>;
-+ POC1-supply = <&pwr1A>;
-+ POC2-supply = <&pwr2A>;
-+ POC3-supply = <&pwr3A>;
++ POC0-supply = <&pwr1A>;
++ POC1-supply = <&pwr0A>;
++ POC2-supply = <&pwr3A>;
++ POC3-supply = <&pwr2A>;
+
+ port@0 {
+ max9286_des0ep0: endpoint@0 {
@@ -14703,7 +14948,7 @@ index 0000000..5958450
+
diff --git a/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi
new file mode 100644
-index 0000000..92ed4a4
+index 0000000..d5c4f46
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/ulcb-vb-cn12.dtsi
@@ -0,0 +1,515 @@
@@ -14888,8 +15133,8 @@ index 0000000..92ed4a4
+ };
+
+ /* MAX9286 @ 0x2c */
-+ max9286-max9271@2 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@2 {
++ compatible = "maxim,max9286";
+ reg = <0x2c>;
+ maxim,sensor_delay = <350>;
+ maxim,links = <4>;
@@ -15224,7 +15469,7 @@ index 0000000..92ed4a4
+};
diff --git a/arch/arm64/boot/dts/renesas/ulcb-vb.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vb.dtsi
new file mode 100644
-index 0000000..193153e
+index 0000000..4fcb320
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/ulcb-vb.dtsi
@@ -0,0 +1,1726 @@
@@ -15831,8 +16076,8 @@ index 0000000..193153e
+ };
+
+ /* MAX9286 @ 0x2c */
-+ max9286-max9271@0 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@0 {
++ compatible = "maxim,max9286";
+ reg = <0x2c>;
+ maxim,sensor_delay = <350>;
+ maxim,links = <4>;
@@ -16040,8 +16285,8 @@ index 0000000..193153e
+ };
+
+ /* MAX9286 @ 0x2c */
-+ max9286-max9271@1 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@1 {
++ compatible = "maxim,max9286";
+ reg = <0x2c>;
+ maxim,sensor_delay = <350>;
+ maxim,links = <4>;
@@ -16954,9 +17199,1807 @@ index 0000000..193153e
+
+/* uncomment to enable CN12 on VIN4-7 */
+//#include "ulcb-vb-cn12.dtsi"
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-vb2.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vb2.dtsi
+new file mode 100644
+index 0000000..67b6085
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/ulcb-vb2.dtsi
+@@ -0,0 +1,1792 @@
++/*
++ * Device Tree Source for the ULCB Videobox V2 board
++ *
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++/ {
++ leds {
++ compatible = "gpio-leds";
++
++ led5 {
++ gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
++ };
++ led6 {
++ gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
++ };
++ /* D13 - status 0 */
++ led_ext00 {
++ gpios = <&gpio_ext_led 0 GPIO_ACTIVE_LOW>;
++ /* linux,default-trigger = "heartbeat"; */
++ };
++ /* D14 - status 1 */
++ led_ext01 {
++ gpios = <&gpio_ext_led 1 GPIO_ACTIVE_LOW>;
++ /* linux,default-trigger = "mmc1"; */
++ };
++ /* D16 - HDMI0 */
++ led_ext02 {
++ gpios = <&gpio_ext_led 2 GPIO_ACTIVE_LOW>;
++ };
++ /* D18 - HDMI1 */
++ led_ext03 {
++ gpios = <&gpio_ext_led 3 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ snd_clk: snd_clk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <24576000>;
++ clock-output-names = "scki";
++ };
++
++ vcc_sdhi3: regulator-vcc-sdhi3 {
++ compatible = "regulator-fixed";
++
++ regulator-name = "SDHI3 Vcc";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++
++ vccq_sdhi3: regulator-vccq-sdhi3 {
++ compatible = "regulator-fixed";
++
++ regulator-name = "SDHI3 VccQ";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ fpdlink_switch: regulator@8 {
++ compatible = "regulator-fixed";
++ regulator-name = "fpdlink_on";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio1 20 0>;
++ enable-active-high;
++ regulator-always-on;
++ };
++
++ hub_reset: regulator@9 {
++ compatible = "regulator-fixed";
++ regulator-name = "hub_reset";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio5 5 0>;
++ enable-active-high;
++ regulator-always-on;
++ };
++
++ hub_power: regulator@10 {
++ compatible = "regulator-fixed";
++ regulator-name = "hub_power";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio6 28 0>;
++ enable-active-high;
++ regulator-always-on;
++ };
++
++ /delete-node/sound;
++
++ rsnd_ak4613: sound@0 {
++ pinctrl-0 = <&sound_0_pins>;
++ pinctrl-names = "default";
++ compatible = "simple-audio-card";
++
++ simple-audio-card,format = "left_j";
++ simple-audio-card,name = "ak4613";
++
++ simple-audio-card,bitclock-master = <&sndcpu>;
++ simple-audio-card,frame-master = <&sndcpu>;
++
++ sndcpu: simple-audio-card,cpu@1 {
++ sound-dai = <&rcar_sound>;
++ };
++
++ sndcodec: simple-audio-card,codec@1 {
++ sound-dai = <&ak4613>;
++ };
++ };
++
++ lvds-encoder {
++ compatible = "thine,thc63lvdm83d";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ port@0 {
++ reg = <0>;
++ lvds_enc_in: endpoint {
++ remote-endpoint = <&du_out_lvds0>;
++ };
++ };
++ port@1 {
++ reg = <1>;
++ lvds_enc_out: endpoint {
++ remote-endpoint = <&lvds_in>;
++ };
++ };
++ };
++ };
++
++ lvds {
++ compatible = "lvds-connector";
++
++ width-mm = <210>;
++ height-mm = <158>;
++
++ panel-timing {
++ /* 1280x800 @60Hz */
++ clock-frequency = <65000000>;
++ hactive = <1280>;
++ vactive = <800>;
++ hsync-len = <40>;
++ hfront-porch = <80>;
++ hback-porch = <40>;
++ vfront-porch = <14>;
++ vback-porch = <14>;
++ vsync-len = <4>;
++ };
++
++ port {
++ lvds_in: endpoint {
++ remote-endpoint = <&lvds_enc_out>;
++ };
++ };
++ };
++
++ excan_ref_clk: excan-ref-clock {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <16000000>;
++ };
++
++ spi_gpio_sw {
++ compatible = "spi-gpio";
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++ gpio-sck = <&gpio0 8 GPIO_ACTIVE_HIGH>;
++ gpio-miso = <&gpio0 10 GPIO_ACTIVE_HIGH>;
++ gpio-mosi = <&gpio0 11 GPIO_ACTIVE_HIGH>;
++ cs-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
++ num-chipselects = <1>;
++
++ spidev: spidev@0 {
++ compatible = "spidev", "spi-gpio";
++ reg = <0>;
++ spi-max-frequency = <25000000>;
++ spi-cpha;
++ spi-cpol;
++ };
++ };
++
++ spi_gpio_can {
++ compatible = "spi-gpio";
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++ gpio-sck = <&gpio1 2 GPIO_ACTIVE_HIGH>;
++ gpio-miso = <&gpio1 3 GPIO_ACTIVE_HIGH>;
++ gpio-mosi = <&gpio1 1 GPIO_ACTIVE_HIGH>;
++ cs-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH
++ &gpio1 4 GPIO_ACTIVE_HIGH>;
++ num-chipselects = <2>;
++
++ spican0: spidev@0 {
++ compatible = "microchip,mcp2515";
++ reg = <0>;
++ clocks = <&excan_ref_clk>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <15 GPIO_ACTIVE_LOW>;
++ spi-max-frequency = <10000000>;
++ };
++ spican1: spidev@1 {
++ compatible = "microchip,mcp2515";
++ reg = <1>;
++ clocks = <&excan_ref_clk>;
++ interrupt-parent = <&gpio1>;
++ interrupts = <5 GPIO_ACTIVE_LOW>;
++ spi-max-frequency = <10000000>;
++ };
++ };
++};
++
++&pfc {
++ hscif4_pins: hscif4 {
++ groups = "hscif4_data_a", "hscif4_ctrl";
++ function = "hscif4";
++ };
++
++ /delete-node/sound;
++
++ sound_0_pins: sound1 {
++ groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
++ function = "ssi";
++ };
++
++ usb0_pins: usb0 {
++ groups = "usb0";
++ function = "usb0";
++ };
++
++ usb2_pins: usb2 {
++ groups = "usb2";
++ function = "usb2";
++ };
++
++ can0_pins: can0 {
++ groups = "can0_data_a";
++ function = "can0";
++ };
++
++ can1_pins: can1 {
++ groups = "can1_data";
++ function = "can1";
++ };
++
++ canfd0_pins: canfd0 {
++ groups = "canfd0_data_a";
++ function = "canfd0";
++ };
++
++ canfd1_pins: canfd1 {
++ groups = "canfd1_data";
++ function = "canfd1";
++ };
++
++ sdhi3_pins: sd3 {
++ groups = "sdhi3_data4", "sdhi3_ctrl";
++ function = "sdhi3";
++ power-source = <3300>;
++ };
++
++ sdhi3_pins_uhs: sd3_uhs {
++ groups = "sdhi3_data4", "sdhi3_ctrl";
++ function = "sdhi3";
++ power-source = <1800>;
++ };
++};
++
++&gpio0 {
++ video_a_irq {
++ gpio-hog;
++ gpios = <12 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-A irq";
++ };
++
++ video_b_irq {
++ gpio-hog;
++ gpios = <13 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-B irq";
++ };
++
++ video_c_irq {
++ gpio-hog;
++ gpios = <14 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-C irq";
++ };
++};
++
++&gpio1 {
++ gpioext_4_22_irq {
++ gpio-hog;
++ gpios = <25 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "0x22@i2c4 irq";
++ };
++ m2_0_sleep {
++ gpio-hog;
++ gpios = <6 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "M2 0 SLEEP#";
++ };
++ m2_1_sleep {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "M2 1 SLEEP#";
++ };
++ m2_0_pcie_det {
++ gpio-hog;
++ gpios = <18 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "M.2 0 PCIe/SATA";
++ };
++ m2_1_pcie_det {
++ gpio-hog;
++ gpios = <19 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "M.2 1 PCIe/SATA";
++ };
++ m2_1_rst {
++ gpio-hog;
++ gpios = <11 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "M.2 1 RST#";
++ };
++ switch_ext_phy_reset {
++ gpio-hog;
++ gpios = <16 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "BR ext phy reset";
++ };
++ switch_sw_reset {
++ gpio-hog;
++ gpios = <17 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "BR switch reset";
++ };
++ switch_1v2_en {
++ gpio-hog;
++ gpios = <27 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "BR 1.2V en";
++ };
++};
++
++&gpio2 {
++ m2_0_wake {
++ gpio-hog;
++ gpios = <1 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "M.2 0 WAKE#";
++ };
++ m2_0_clkreq {
++ gpio-hog;
++ gpios = <5 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "M.2 0 CLKREQ#";
++ };
++ switch_3v3_en {
++ gpio-hog;
++ gpios = <4 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "BR 3.3V en";
++ };
++};
++
++&gpio3 {
++ switch_int_phy_reset {
++ gpio-hog;
++ gpios = <15 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "BR int phy reset";
++ };
++};
++
++&gpio5 {
++ switch_2v5_en {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "BR 2.5V en";
++ };
++ switch_25mhz_en {
++ gpio-hog;
++ gpios = <8 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "BR 25MHz clk en";
++ };
++};
++
++&gpio6 {
++ m2_1_wake {
++ gpio-hog;
++ gpios = <4 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "M.2 1 WAKE#";
++ };
++ m2_1_clkreq {
++ gpio-hog;
++ gpios = <10 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "M.2 1 CLKREQ#";
++ };
++
++ m2_0_rst {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "M.2 0 RST#";
++ };
++};
++
++&i2c2 {
++ clock-frequency = <400000>;
++
++ i2cswitch2: pca9548@74 {
++ compatible = "nxp,pca9548";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x74>;
++ reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>;
++
++ i2c@4 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <4>;
++ /* USB3.0 HUB node(s) */
++ /* addr of TUSB8041 is 100.0100 = 0x44 */
++ };
++
++ i2c@1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++ /* Slot A (CN10) */
++
++ ov106xx@0 {
++ compatible = "ovti,ov106xx";
++ reg = <0x60>;
++
++ port@0 {
++ ov106xx_in0: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&vin0ep0>;
++ };
++ };
++ port@1 {
++ ov106xx_max9286_des0ep0: endpoint@0 {
++ remote-endpoint = <&max9286_des0ep0>;
++ };
++ ov106xx_ti964_des0ep0: endpoint@1 {
++ remote-endpoint = <&ti964_des0ep0>;
++ };
++ ov106xx_ti954_des0ep0: endpoint@2 {
++ remote-endpoint = <&ti954_des0ep0>;
++ };
++ };
++ };
++
++ ov106xx@1 {
++ compatible = "ovti,ov106xx";
++ reg = <0x61>;
++
++ port@0 {
++ ov106xx_in1: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&vin1ep0>;
++ };
++ };
++ port@1 {
++ ov106xx_max9286_des0ep1: endpoint@0 {
++ remote-endpoint = <&max9286_des0ep1>;
++ };
++ ov106xx_ti964_des0ep1: endpoint@1 {
++ remote-endpoint = <&ti964_des0ep1>;
++ };
++ ov106xx_ti954_des0ep1: endpoint@2 {
++ remote-endpoint = <&ti954_des0ep1>;
++ };
++ };
++ };
++
++ ov106xx@2 {
++ compatible = "ovti,ov106xx";
++ reg = <0x62>;
++
++ port@0 {
++ ov106xx_in2: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&vin2ep0>;
++ };
++ };
++ port@1 {
++ ov106xx_max9286_des0ep2: endpoint@0 {
++ remote-endpoint = <&max9286_des0ep2>;
++ };
++ ov106xx_ti964_des0ep2: endpoint@1 {
++ remote-endpoint = <&ti964_des0ep2>;
++ };
++ };
++ };
++
++ ov106xx@3 {
++ compatible = "ovti,ov106xx";
++ reg = <0x63>;
++
++ port@0 {
++ ov106xx_in3: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&vin3ep0>;
++ };
++ };
++ port@1 {
++ ov106xx_max9286_des0ep3: endpoint@0 {
++ remote-endpoint = <&max9286_des0ep3>;
++ };
++ ov106xx_ti964_des0ep3: endpoint@1 {
++ remote-endpoint = <&ti964_des0ep3>;
++ };
++ };
++ };
++
++ /* DS90UB964 @ 0x3a */
++ ti964-ti9x3@0 {
++ compatible = "ti,ti964-ti9x3";
++ reg = <0x3a>;
++ ti,sensor_delay = <350>;
++ ti,links = <4>;
++ ti,lanes = <4>;
++ ti,forwarding-mode = "round-robin";
++ ti,cable-mode = "stp";
++
++ port@0 {
++ ti964_des0ep0: endpoint@0 {
++ ti9x3-addr = <0x0c>;
++ dvp-order = <0>;
++ remote-endpoint = <&ov106xx_in0>;
++ };
++ ti964_des0ep1: endpoint@1 {
++ ti9x3-addr = <0x0d>;
++ dvp-order = <0>;
++ remote-endpoint = <&ov106xx_in1>;
++ };
++ ti964_des0ep2: endpoint@2 {
++ ti9x3-addr = <0x0e>;
++ dvp-order = <0>;
++ remote-endpoint = <&ov106xx_in2>;
++ };
++ ti964_des0ep3: endpoint@3 {
++ ti9x3-addr = <0x0f>;
++ dvp-order = <0>;
++ remote-endpoint = <&ov106xx_in3>;
++ };
++ };
++ port@1 {
++ ti964_csi0ep0: endpoint {
++ csi-rate = <1450>;
++ remote-endpoint = <&csi2_40_ep>;
++ };
++ };
++ };
++
++ /* DS90UB954 @ 0x38 */
++ ti954-ti9x3@0 {
++ compatible = "ti,ti954-ti9x3";
++ reg = <0x38>;
++ /* gpios = <&video_a_ext1 10 GPIO_ACTIVE_HIGH>; */
++ ti,sensor_delay = <350>;
++ ti,links = <2>;
++ ti,lanes = <4>;
++ ti,forwarding-mode = "round-robin";
++ ti,cable-mode = "stp";
++
++ port@0 {
++ ti954_des0ep0: endpoint@0 {
++ ti9x3-addr = <0x0c>;
++ dvp-order = <0>;
++ remote-endpoint = <&ov106xx_in0>;
++ };
++ ti954_des0ep1: endpoint@1 {
++ ti9x3-addr = <0x0d>;
++ dvp-order = <0>;
++ remote-endpoint = <&ov106xx_in1>;
++ };
++ };
++ port@1 {
++ ti954_csi0ep0: endpoint {
++ csi-rate = <1450>;
++ remote-endpoint = <&csi2_40_ep>;
++ };
++ };
++ };
++
++ /* MAX9286 @ 0x2c */
++ max9286@0 {
++ compatible = "maxim,max9286";
++ reg = <0x2c>;
++ maxim,sensor_delay = <350>;
++ maxim,links = <4>;
++ maxim,lanes = <4>;
++ maxim,resetb-gpio = <1>;
++ maxim,fsync-mode = "automatic";
++ maxim,timeout = <100>;
++
++ port@0 {
++ max9286_des0ep0: endpoint@0 {
++ max9271-addr = <0x50>;
++ dvp-order = <1>;
++ remote-endpoint = <&ov106xx_in0>;
++ };
++ max9286_des0ep1: endpoint@1 {
++ max9271-addr = <0x51>;
++ dvp-order = <1>;
++ remote-endpoint = <&ov106xx_in1>;
++ };
++ max9286_des0ep2: endpoint@2 {
++ max9271-addr = <0x52>;
++ dvp-order = <1>;
++ remote-endpoint = <&ov106xx_in2>;
++ };
++ max9286_des0ep3: endpoint@3 {
++ max9271-addr = <0x53>;
++ dvp-order = <1>;
++ remote-endpoint = <&ov106xx_in3>;
++ };
++ };
++ port@1 {
++ max9286_csi0ep0: endpoint {
++ csi-rate = <700>;
++ remote-endpoint = <&csi2_40_ep>;
++ };
++ };
++ };
++ };
++
++ i2c@3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++ /* Slot B (CN11) */
++
++ ov106xx@4 {
++ compatible = "ovti,ov106xx";
++ reg = <0x64>;
++
++ port@0 {
++ ov106xx_in4: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&vin4ep0>;
++ };
++ };
++ port@1 {
++ ov106xx_max9286_des1ep0: endpoint@0 {
++ remote-endpoint = <&max9286_des1ep0>;
++ };
++ ov106xx_ti964_des1ep0: endpoint@1 {
++ remote-endpoint = <&ti964_des1ep0>;
++ };
++ ov106xx_ti954_des1ep0: endpoint@2 {
++ remote-endpoint = <&ti954_des1ep0>;
++ };
++ };
++ };
++
++ ov106xx@5 {
++ compatible = "ovti,ov106xx";
++ reg = <0x65>;
++
++ port@0 {
++ ov106xx_in5: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&vin5ep0>;
++ };
++ };
++ port@1 {
++ ov106xx_max9286_des1ep1: endpoint@0 {
++ remote-endpoint = <&max9286_des1ep1>;
++ };
++ ov106xx_ti964_des1ep1: endpoint@1 {
++ remote-endpoint = <&ti964_des1ep1>;
++ };
++ ov106xx_ti954_des1ep1: endpoint@2 {
++ remote-endpoint = <&ti954_des1ep1>;
++ };
++ };
++ };
++
++ ov106xx@6 {
++ compatible = "ovti,ov106xx";
++ reg = <0x66>;
++
++ port@0 {
++ ov106xx_in6: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&vin6ep0>;
++ };
++ };
++ port@1 {
++ ov106xx_max9286_des1ep2: endpoint@0 {
++ remote-endpoint = <&max9286_des1ep2>;
++ };
++ ov106xx_ti964_des1ep2: endpoint@1 {
++ remote-endpoint = <&ti964_des1ep2>;
++ };
++ };
++ };
++
++ ov106xx@7 {
++ compatible = "ovti,ov106xx";
++ reg = <0x67>;
++
++ port@0 {
++ ov106xx_in7: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&vin7ep0>;
++ };
++ };
++ port@1 {
++ ov106xx_max9286_des1ep3: endpoint@0 {
++ remote-endpoint = <&max9286_des1ep3>;
++ };
++ ov106xx_ti964_des1ep3: endpoint@1 {
++ remote-endpoint = <&ti964_des1ep3>;
++ };
++ };
++ };
++
++ /* DS90UB964 @ 0x3a */
++ ti964-ti9x3@1 {
++ compatible = "ti,ti964-ti9x3";
++ reg = <0x3a>;
++ ti,sensor_delay = <350>;
++ ti,links = <4>;
++ ti,lanes = <4>;
++ ti,forwarding-mode = "round-robin";
++ ti,cable-mode = "stp";
++
++ port@0 {
++ ti964_des1ep0: endpoint@0 {
++ ti9x3-addr = <0x0c>;
++ dvp-order = <0>;
++ remote-endpoint = <&ov106xx_in4>;
++ };
++ ti964_des1ep1: endpoint@1 {
++ ti9x3-addr = <0x0d>;
++ dvp-order = <0>;
++ remote-endpoint = <&ov106xx_in5>;
++ };
++ ti964_des1ep2: endpoint@2 {
++ ti9x3-addr = <0x0e>;
++ dvp-order = <0>;
++ remote-endpoint = <&ov106xx_in6>;
++ };
++ ti964_des1ep3: endpoint@3 {
++ ti9x3-addr = <0x0f>;
++ dvp-order = <0>;
++ remote-endpoint = <&ov106xx_in7>;
++ };
++ };
++ port@1 {
++ ti964_csi2ep0: endpoint {
++ csi-rate = <1450>;
++ remote-endpoint = <&csi2_41_ep>;
++ };
++ };
++ };
++
++ /* DS90UB954 @ 0x38 */
++ ti954-ti9x3@1 {
++ compatible = "ti,ti954-ti9x3";
++ reg = <0x38>;
++ /* gpios = <&video_b_ext1 10 GPIO_ACTIVE_HIGH>; */
++ ti,sensor_delay = <350>;
++ ti,links = <2>;
++ ti,lanes = <4>;
++ ti,forwarding-mode = "round-robin";
++ ti,cable-mode = "stp";
++
++ port@0 {
++ ti954_des1ep0: endpoint@0 {
++ ti9x3-addr = <0x0c>;
++ dvp-order = <0>;
++ remote-endpoint = <&ov106xx_in4>;
++ };
++ ti954_des1ep1: endpoint@1 {
++ ti9x3-addr = <0x0d>;
++ dvp-order = <0>;
++ remote-endpoint = <&ov106xx_in5>;
++ };
++ };
++ port@1 {
++ ti954_csi2ep0: endpoint {
++ csi-rate = <1450>;
++ remote-endpoint = <&csi2_41_ep>;
++ };
++ };
++ };
++
++ /* MAX9286 @ 0x2c */
++ max9286@1 {
++ compatible = "maxim,max9286";
++ reg = <0x2c>;
++ maxim,sensor_delay = <350>;
++ maxim,links = <4>;
++ maxim,lanes = <4>;
++ maxim,resetb-gpio = <1>;
++ maxim,fsync-mode = "automatic";
++ maxim,timeout = <100>;
++
++ port@0 {
++ max9286_des1ep0: endpoint@0 {
++ max9271-addr = <0x50>;
++ dvp-order = <1>;
++ remote-endpoint = <&ov106xx_in4>;
++ };
++ max9286_des1ep1: endpoint@1 {
++ max9271-addr = <0x51>;
++ dvp-order = <1>;
++ remote-endpoint = <&ov106xx_in5>;
++ };
++ max9286_des1ep2: endpoint@2 {
++ max9271-addr = <0x52>;
++ dvp-order = <1>;
++ remote-endpoint = <&ov106xx_in6>;
++ };
++ max9286_des1ep3: endpoint@3 {
++ max9271-addr = <0x53>;
++ dvp-order = <1>;
++ remote-endpoint = <&ov106xx_in7>;
++ };
++ };
++ port@1 {
++ max9286_csi2ep0: endpoint {
++ csi-rate = <700>;
++ remote-endpoint = <&csi2_41_ep>;
++ };
++ };
++ };
++ };
++
++ i2c@7 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <7>;
++ /* Slot C (CN12) */
++ };
++
++ i2c@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++ /* Slot A (CN10) */
++
++ video_a_ext0: pca9535@26 {
++ compatible = "nxp,pca9535";
++ reg = <0x26>;
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ video_a_des_cfg1 {
++ gpio-hog;
++ gpios = <5 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-A cfg1";
++ };
++ video_a_des_cfg0 {
++ gpio-hog;
++ gpios = <6 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-A cfg0";
++ };
++ video_a_pwr_shdn {
++ gpio-hog;
++ gpios = <3 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A PWR_SHDN";
++ };
++ video_a_cam_pwr0 {
++ gpio-hog;
++ gpios = <12 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A PWR0";
++ };
++ video_a_cam_pwr1 {
++ gpio-hog;
++ gpios = <13 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A PWR1";
++ };
++ video_a_cam_pwr2 {
++ gpio-hog;
++ gpios = <14 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A PWR2";
++ };
++ video_a_cam_pwr3 {
++ gpio-hog;
++ gpios = <15 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A PWR3";
++ };
++ video_a_des_shdn {
++ gpio-hog;
++ gpios = <4 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A DES_SHDN";
++ };
++ video_a_des_led {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "Video-A led";
++ };
++ };
++
++ video_a_ext1: max7325@5c {
++ compatible = "maxim,max7325";
++ reg = <0x5c>;
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ video_a_des_cfg2 {
++ gpio-hog;
++ gpios = <4 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-A cfg2";
++ };
++ video_a_des_cfg1 {
++ gpio-hog;
++ gpios = <6 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-A cfg1";
++ };
++ video_a_des_cfg0 {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-A cfg0";
++ };
++ video_a_pwr_shdn {
++ gpio-hog;
++ gpios = <14 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A PWR_SHDN";
++ };
++ video_a_cam_pwr0 {
++ gpio-hog;
++ gpios = <8 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A PWR0";
++ };
++ video_a_cam_pwr1 {
++ gpio-hog;
++ gpios = <9 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A PWR1";
++ };
++ video_a_cam_pwr2 {
++ gpio-hog;
++ gpios = <10 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A PWR2";
++ };
++ video_a_cam_pwr3 {
++ gpio-hog;
++ gpios = <11 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A PWR3";
++ };
++ video_a_des_shdn {
++ gpio-hog;
++ gpios = <13 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A DES_SHDN";
++ };
++ video_a_led {
++ gpio-hog;
++ gpios = <12 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "Video-A LED";
++ };
++ };
++ };
++
++ i2c@2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++ /* Slot B (CN11) */
++
++ video_b_ext0: pca9535@26 {
++ compatible = "nxp,pca9535";
++ reg = <0x26>;
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ video_b_des_cfg1 {
++ gpio-hog;
++ gpios = <5 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-B cfg1";
++ };
++ video_b_des_cfg0 {
++ gpio-hog;
++ gpios = <6 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-B cfg0";
++ };
++ video_b_pwr_shdn {
++ gpio-hog;
++ gpios = <3 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B PWR_SHDN";
++ };
++ video_b_cam_pwr0 {
++ gpio-hog;
++ gpios = <12 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B PWR0";
++ };
++ video_b_cam_pwr1 {
++ gpio-hog;
++ gpios = <13 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B PWR1";
++ };
++ video_b_cam_pwr2 {
++ gpio-hog;
++ gpios = <14 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B PWR2";
++ };
++ video_b_cam_pwr3 {
++ gpio-hog;
++ gpios = <15 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B PWR3";
++ };
++ video_b_des_shdn {
++ gpio-hog;
++ gpios = <4 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B DES_SHDN";
++ };
++ video_b_des_led {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "Video-B led";
++ };
++ };
++
++ video_b_ext1: max7325@5c {
++ compatible = "maxim,max7325";
++ reg = <0x5c>;
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ video_b_des_cfg2 {
++ gpio-hog;
++ gpios = <4 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-B cfg2";
++ };
++ video_b_des_cfg1 {
++ gpio-hog;
++ gpios = <6 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-B cfg1";
++ };
++ video_b_des_cfg0 {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-B cfg0";
++ };
++ video_b_pwr_shdn {
++ gpio-hog;
++ gpios = <14 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B PWR_SHDN";
++ };
++ video_b_cam_pwr0 {
++ gpio-hog;
++ gpios = <8 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B PWR0";
++ };
++ video_b_cam_pwr1 {
++ gpio-hog;
++ gpios = <9 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B PWR1";
++ };
++ video_b_cam_pwr2 {
++ gpio-hog;
++ gpios = <10 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B PWR2";
++ };
++ video_b_cam_pwr3 {
++ gpio-hog;
++ gpios = <11 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B PWR3";
++ };
++ video_b_des_shdn {
++ gpio-hog;
++ gpios = <13 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B DES_SHDN";
++ };
++ video_b_led {
++ gpio-hog;
++ gpios = <12 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "Video-B LED";
++ };
++ };
++ };
++
++ i2c@5 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <5>;
++ /* Slot C (CN12) */
++ };
++ };
++};
++
++&i2c4 {
++ i2cswitch4: pca9548@74 {
++ compatible = "nxp,pca9548";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x74>;
++ reset-gpios= <&gpio5 15 GPIO_ACTIVE_LOW>;
++
++ i2c@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++ /* FAN1 node - lm96063 */
++ fan_ctrl_1:lm96063-1@4c {
++ compatible = "lm96163";
++ reg = <0x4c>;
++ };
++ };
++
++ i2c@6 {
++ /* FAN2 */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <6>;
++ /* FAN2 node - lm96063 */
++ fan_ctrl_2:lm96063-2@4c {
++ compatible = "lm96163";
++ reg = <0x4c>;
++ };
++ };
++
++ i2c@1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++
++ /* Power nodes - 2 x TPS544x20 */
++ tps_5v: tps544c20@0x2a {
++ compatible = "tps544c20";
++ reg = <0x2c>;
++ status = "disabled";
++ };
++ tps_3v3: tps544c20@0x22 {
++ compatible = "tps544c20";
++ reg = <0x24>;
++ status = "disabled";
++ };
++ };
++
++ i2c@2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++ /* CAN and power board nodes */
++
++ gpio_ext_pwr: pca9535@22 {
++ compatible = "nxp,pca9535";
++ reg = <0x22>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ interrupt-parent = <&gpio1>;
++ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
++
++ /* enable input DCDC after wake-up signal released */
++ pwr_hold {
++ gpio-hog;
++ gpios = <11 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "pwr_hold";
++ };
++ pwr_5v_out {
++ gpio-hog;
++ gpios = <14 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "pwr_5v_out";
++ };
++ pwr_5v_oc {
++ gpio-hog;
++ gpios = <15 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "pwr_5v_oc";
++ };
++ pwr_wake8 {
++ gpio-hog;
++ gpios = <12 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "wake8";
++ };
++ pwr_wake7 {
++ gpio-hog;
++ gpios = <13 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "wake7";
++ };
++
++ /* CAN0 */
++ can0_stby {
++ gpio-hog;
++ gpios = <4 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "can0_stby";
++ };
++ can0_load {
++ gpio-hog;
++ gpios = <0 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "can0_120R_load";
++ };
++ /* CAN1 */
++ can1_stby {
++ gpio-hog;
++ gpios = <5 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "can1_stby";
++ };
++ can1_load {
++ gpio-hog;
++ gpios = <1 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "can1_120R_load";
++ };
++ /* CAN2 */
++ can2_stby {
++ gpio-hog;
++ gpios = <6 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "can2_stby";
++ };
++ can2_load {
++ gpio-hog;
++ gpios = <2 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "can2_120R_load";
++ };
++ can2_rst {
++ gpio-hog;
++ gpios = <8 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "can2_rst";
++ };
++ /* CAN3 */
++ can3_stby {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "can3_stby";
++ };
++ can3_load {
++ gpio-hog;
++ gpios = <3 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "can3_120R_load";
++ };
++ can3_rst {
++ gpio-hog;
++ gpios = <9 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "can3_rst";
++ };
++ };
++ rtc@68 {
++ compatible = "dallas,ds1338";
++ reg = <0x68>;
++ };
++ };
++
++ i2c@3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++ /* FPDLink output node - DS90UH947 */
++ };
++
++ i2c@4 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <4>;
++ /* BCM switch node */
++ };
++
++ i2c@5 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <5>;
++ /* LED board node(s) */
++
++ gpio_ext_led: pca9535@22 {
++ compatible = "nxp,pca9535";
++ reg = <0x22>;
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ /* gpios 0..7 are used for indication LEDs, low-active */
++ };
++ };
++
++ /* port 7 is not used */
++ };
++};
++
++&pcie_bus_clk {
++ clock-frequency = <100000000>;
++ status = "okay";
++};
++
++&pciec0 {
++ status = "okay";
++};
++
++&pciec1 {
++ status = "okay";
++};
++
++&vin0 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ vin0ep0: endpoint {
++ csi,select = "csi40";
++ virtual,channel = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&ov106xx_in0>;
++ };
++ };
++ port@1 {
++ csi0ep0: endpoint {
++ remote-endpoint = <&csi2_40_ep>;
++ };
++ };
++ port@2 {
++ vin0_max9286_des0ep0: endpoint@0 {
++ remote-endpoint = <&max9286_des0ep0>;
++ };
++ vin0_ti964_des0ep0: endpoint@1 {
++ remote-endpoint = <&ti964_des0ep0>;
++ };
++ vin0_ti954_des0ep0: endpoint@2 {
++ remote-endpoint = <&ti954_des0ep0>;
++ };
++ };
++ };
++};
++
++&vin1 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ vin1ep0: endpoint {
++ csi,select = "csi40";
++ virtual,channel = <1>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&ov106xx_in1>;
++ };
++ };
++ port@1 {
++ csi0ep1: endpoint {
++ remote-endpoint = <&csi2_40_ep>;
++ };
++ };
++ port@2 {
++ vin1_max9286_des0ep1: endpoint@0 {
++ remote-endpoint = <&max9286_des0ep1>;
++ };
++ vin1_ti964_des0ep1: endpoint@1 {
++ remote-endpoint = <&ti964_des0ep1>;
++ };
++ vin1_ti954_des0ep1: endpoint@2 {
++ remote-endpoint = <&ti954_des0ep1>;
++ };
++ };
++ };
++};
++
++&vin2 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ vin2ep0: endpoint {
++ csi,select = "csi40";
++ virtual,channel = <2>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&ov106xx_in2>;
++ };
++ };
++ port@1 {
++ csi0ep2: endpoint {
++ remote-endpoint = <&csi2_40_ep>;
++ };
++ };
++ port@2 {
++ vin2_max9286_des0ep2: endpoint@0 {
++ remote-endpoint = <&max9286_des0ep2>;
++ };
++ vin2_ti964_des0ep2: endpoint@1 {
++ remote-endpoint = <&ti964_des0ep2>;
++ };
++ };
++ };
++};
++
++&vin3 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ vin3ep0: endpoint {
++ csi,select = "csi40";
++ virtual,channel = <3>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&ov106xx_in3>;
++ };
++ };
++ port@1 {
++ csi0ep3: endpoint {
++ remote-endpoint = <&csi2_40_ep>;
++ };
++ };
++ port@2 {
++ vin3_max9286_des0ep3: endpoint@0 {
++ remote-endpoint = <&max9286_des0ep3>;
++ };
++ vin3_ti964_des0ep3: endpoint@1 {
++ remote-endpoint = <&ti964_des0ep3>;
++ };
++ };
++ };
++};
++
++&vin4 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ vin4ep0: endpoint {
++ csi,select = "csi41";
++ virtual,channel = <0>;
++ remote-endpoint = <&ov106xx_in4>;
++ data-lanes = <1 2 3 4>;
++ };
++ };
++ port@1 {
++ csi2ep0: endpoint {
++ remote-endpoint = <&csi2_41_ep>;
++ };
++ };
++ port@2 {
++ vin4_max9286_des1ep0: endpoint@0 {
++ remote-endpoint = <&max9286_des1ep0>;
++ };
++ vin4_ti964_des1ep0: endpoint@1 {
++ remote-endpoint = <&ti964_des1ep0>;
++ };
++ vin4_ti954_des1ep0: endpoint@2 {
++ remote-endpoint = <&ti954_des1ep0>;
++ };
++ };
++ };
++};
++
++&vin5 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ vin5ep0: endpoint@0 {
++ csi,select = "csi41";
++ virtual,channel = <1>;
++ remote-endpoint = <&ov106xx_in5>;
++ data-lanes = <1 2 3 4>;
++ };
++ };
++ port@1 {
++ csi2ep1: endpoint {
++ remote-endpoint = <&csi2_41_ep>;
++ };
++ };
++ port@2 {
++ vin5_max9286_des1ep1: endpoint@0 {
++ remote-endpoint = <&max9286_des1ep1>;
++ };
++ vin5_ti964_des1ep1: endpoint@1 {
++ remote-endpoint = <&ti964_des1ep1>;
++ };
++ vin5_ti954_des1ep1: endpoint@2 {
++ remote-endpoint = <&ti954_des1ep1>;
++ };
++ };
++ };
++};
++
++&vin6 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ vin6ep0: endpoint@0 {
++ csi,select = "csi41";
++ virtual,channel = <2>;
++ remote-endpoint = <&ov106xx_in6>;
++ data-lanes = <1 2 3 4>;
++ };
++ };
++ port@1 {
++ csi2ep2: endpoint {
++ remote-endpoint = <&csi2_41_ep>;
++ };
++ };
++ port@2 {
++ vin6_max9286_des1ep2: endpoint@0 {
++ remote-endpoint = <&max9286_des1ep2>;
++ };
++ vin6_ti964_des1ep2: endpoint@1 {
++ remote-endpoint = <&ti964_des1ep2>;
++ };
++ };
++ };
++};
++
++&vin7 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ vin7ep0: endpoint@0 {
++ csi,select = "csi41";
++ virtual,channel = <3>;
++ remote-endpoint = <&ov106xx_in7>;
++ data-lanes = <1 2 3 4>;
++ };
++ };
++ port@1 {
++ csi2ep3: endpoint {
++ remote-endpoint = <&csi2_41_ep>;
++ };
++ };
++ port@2 {
++ vin7_max9286_des1ep3: endpoint@0 {
++ remote-endpoint = <&max9286_des1ep3>;
++ };
++ vin7_ti964_des1ep3: endpoint@1 {
++ remote-endpoint = <&ti964_des1ep3>;
++ };
++ };
++ };
++};
++
++&csi2_40 {
++ status = "okay";
++
++ virtual,channel {
++ csi2_vc0 {
++ data,type = "ycbcr422";
++ receive,vc = <0>;
++ };
++ csi2_vc1 {
++ data,type = "ycbcr422";
++ receive,vc = <1>;
++ };
++ csi2_vc2 {
++ data,type = "ycbcr422";
++ receive,vc = <2>;
++ };
++ csi2_vc3 {
++ data,type = "ycbcr422";
++ receive,vc = <3>;
++ };
++ };
++
++ port {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ csi2_40_ep: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ csi-rate = <300>;
++ };
++ };
++};
++
++&csi2_41 {
++ status = "okay";
++
++ virtual,channel {
++ csi2_vc0 {
++ data,type = "ycbcr422";
++ receive,vc = <0>;
++ };
++ csi2_vc1 {
++ data,type = "ycbcr422";
++ receive,vc = <1>;
++ };
++ csi2_vc2 {
++ data,type = "ycbcr422";
++ receive,vc = <2>;
++ };
++ csi2_vc3 {
++ data,type = "ycbcr422";
++ receive,vc = <3>;
++ };
++ };
++
++ port {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ csi2_41_ep: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ csi-rate = <300>;
++ };
++ };
++};
++
++&rcar_sound {
++ pinctrl-0 = <&sound_clk_pins>;
++
++ /* Multi DAI */
++ #sound-dai-cells = <1>;
++};
++
++&sata {
++ status = "okay";
++};
++
++&ssi1 {
++ /delete-property/shared-pin;
++};
++
++&sdhi3 {
++ pinctrl-0 = <&sdhi3_pins>;
++ pinctrl-1 = <&sdhi3_pins_uhs>;
++ pinctrl-names = "default", "state_uhs";
++
++ vmmc-supply = <&vcc_sdhi3>;
++ vqmmc-supply = <&vccq_sdhi3>;
++ cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
++ wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
++ bus-width = <4>;
++ sd-uhs-sdr50;
++ status = "okay";
++};
++
++&msiof1 {
++ status = "disabled";
++};
++
++&usb2_phy0 {
++ pinctrl-0 = <&usb0_pins>;
++ pinctrl-names = "default";
++
++ status = "okay";
++};
++
++&usb2_phy2 {
++ pinctrl-0 = <&usb2_pins>;
++ pinctrl-names = "default";
++
++ status = "okay";
++};
++
++&xhci0 {
++ status = "okay";
++};
++
++&ehci0 {
++ status = "okay";
++};
++
++&ehci2 {
++ status = "okay";
++};
++
++&ohci0 {
++ status = "okay";
++};
++
++&ohci2 {
++ status = "okay";
++};
++
++&can0 {
++ pinctrl-0 = <&can0_pins>;
++ pinctrl-names = "default";
++ status = "okay";
++
++ renesas,can-clock-select = <0x0>;
++};
++
++&can1 {
++ pinctrl-0 = <&can1_pins>;
++ pinctrl-names = "default";
++ status = "okay";
++
++ renesas,can-clock-select = <0x0>;
++};
++
++&canfd {
++ pinctrl-0 = <&canfd0_pins &canfd1_pins>;
++ pinctrl-names = "default";
++ status = "disabled";
++
++ renesas,can-clock-select = <0x0>;
++
++ channel0 {
++ status = "okay";
++ };
++
++ channel1 {
++ status = "okay";
++ };
++};
++
++/* uncomment to enable CN12 on VIN4-7 */
++//#include "ulcb-vb-cn12.dtsi"
diff --git a/arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi
new file mode 100644
-index 0000000..beb52e9
+index 0000000..7728bdd
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/ulcb-vbm.dtsi
@@ -0,0 +1,578 @@
@@ -17223,8 +19266,8 @@ index 0000000..beb52e9
+ };
+ };
+
-+ max9286-max9271@0 {
-+ compatible = "maxim,max9286-max9271";
++ max9286@0 {
++ compatible = "maxim,max9286";
+ reg = <0x2c>;
+ maxim,sensor_delay = <350>;
+ maxim,links = <4>;
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0050-arm64-dts-renesas-r8a779x-add-IMP-nodes.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0050-arm64-dts-renesas-r8a779x-add-IMP-nodes.patch
index b38a623..d52106e 100644
--- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0050-arm64-dts-renesas-r8a779x-add-IMP-nodes.patch
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0050-arm64-dts-renesas-r8a779x-add-IMP-nodes.patch
@@ -7,14 +7,14 @@ This adds IMP resource nodes for Gen3 SoCs
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
- arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 98 +++++++++++++++++++++++++++
- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 98 +++++++++++++++++++++++++++
- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 62 +++++++++++++++++
- arch/arm64/boot/dts/renesas/r8a7797.dtsi | 99 ++++++++++++++++++++++++++++
- 4 files changed, 357 insertions(+)
+ arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 98 ++++++++++++++++++++++++
+ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 98 ++++++++++++++++++++++++
+ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 62 ++++++++++++++++
+ arch/arm64/boot/dts/renesas/r8a7797.dtsi | 107 +++++++++++++++++++++++++++
+ 4 files changed, 365 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
-index b3f3102..e15af8c 100644
+index 3a2d2c8..c6bc187 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -2794,6 +2794,104 @@
@@ -123,7 +123,7 @@ index b3f3102..e15af8c 100644
compatible = "renesas,imr-lx4";
reg = <0 0xfe860000 0 0x2000>;
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
-index 02c5931..8ba4cec 100644
+index 8f7d776..a01a4f3 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -2790,6 +2790,104 @@
@@ -232,7 +232,7 @@ index 02c5931..8ba4cec 100644
compatible = "renesas,imr-lx4";
reg = <0 0xfe860000 0 0x2000>;
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
-index b94d9e0..7c19f35 100644
+index f214f26..d3e91f1 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -2531,5 +2531,67 @@
@@ -304,15 +304,15 @@ index b94d9e0..7c19f35 100644
};
};
diff --git a/arch/arm64/boot/dts/renesas/r8a7797.dtsi b/arch/arm64/boot/dts/renesas/r8a7797.dtsi
-index 1be93e8..232eb19 100644
+index 118a473..05b50ca 100644
--- a/arch/arm64/boot/dts/renesas/r8a7797.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7797.dtsi
-@@ -970,6 +970,112 @@
+@@ -967,6 +967,113 @@
status = "okay";
};
+ imp_distributer: impdes0 {
-+ compatible = "renesas,impx4-distributer";
++ compatible = "renesas,impx5+-distributer";
+ reg = <0 0xffa00000 0 0x4000>;
+ interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 830>;
@@ -335,8 +335,8 @@ index 1be93e8..232eb19 100644
+ reg = <0 0xff920000 0 0x20000>;
+ interrupt-parent = <&imp_distributer>;
+ interrupts = <1>;
-+ clocks = <&cpg CPG_MOD 826>;
-+ power-domains = <&sysc R8A7797_PD_A2IR1>;
++ clocks = <&cpg CPG_MOD 827>;
++ power-domains = <&sysc R8A7797_PD_A2IR0>;
+ };
+
+ imp2 {
@@ -344,8 +344,8 @@ index 1be93e8..232eb19 100644
+ reg = <0 0xff940000 0 0x20000>;
+ interrupt-parent = <&imp_distributer>;
+ interrupts = <2>;
-+ clocks = <&cpg CPG_MOD 825>;
-+ power-domains = <&sysc R8A7797_PD_A2IR2>;
++ clocks = <&cpg CPG_MOD 826>;
++ power-domains = <&sysc R8A7797_PD_A2IR1>;
+ };
+
+ imp3 {
@@ -353,8 +353,8 @@ index 1be93e8..232eb19 100644
+ reg = <0 0xff960000 0 0x20000>;
+ interrupt-parent = <&imp_distributer>;
+ interrupts = <3>;
-+ clocks = <&cpg CPG_MOD 824>;
-+ power-domains = <&sysc R8A7797_PD_A2IR3>;
++ clocks = <&cpg CPG_MOD 826>;
++ power-domains = <&sysc R8A7797_PD_A2IR1>;
+ };
+
+ impsc0 {
@@ -379,28 +379,36 @@ index 1be93e8..232eb19 100644
+ compatible = "renesas,impx5-dmac";
+ reg = <0 0xffa10000 0 0x1000>;
+ interrupt-parent = <&imp_distributer>;
-+ interrupts = <16>;
-+ clocks = <&cpg CPG_MOD 830>;
-+ power-domains = <&sysc R8A7797_PD_A3IR>;
++ interrupts = <6>;
++ clocks = <&cpg CPG_MOD 825>;
++ power-domains = <&sysc R8A7797_PD_A2IR2>;
+ };
+
+ impdm1 {
+ compatible = "renesas,impx5-dmac";
-+ reg = <0 0xffa10000 0 0x1000>,
-+ <0 0xffa10800 0 0x0800>;
++ reg = <0 0xffa11000 0 0x1000>;
+ interrupt-parent = <&imp_distributer>;
-+ interrupts = <17>;
-+ clocks = <&cpg CPG_MOD 830>;
-+ power-domains = <&sysc R8A7797_PD_A3IR>;
++ interrupts = <7>;
++ clocks = <&cpg CPG_MOD 825>;
++ power-domains = <&sysc R8A7797_PD_A2IR2>;
+ };
+
+ imppsc0 {
-+ compatible = "renesas,impx5-dmac";
++ compatible = "renesas,impx5+-psc";
+ reg = <0 0xffa20000 0 0x4000>;
+ interrupt-parent = <&imp_distributer>;
-+ interrupts = <12>;
-+ clocks = <&cpg CPG_MOD 830>;
-+ power-domains = <&sysc R8A7797_PD_A3IR>;
++ interrupts = <8>;
++ clocks = <&cpg CPG_MOD 825>;
++ power-domains = <&sysc R8A7797_PD_A2IR2>;
++ };
++
++ impcnn0 {
++ compatible = "renesas,impx5+-cnn";
++ reg = <0 0xff9e0000 0 0x10000>;
++ interrupt-parent = <&imp_distributer>;
++ interrupts = <9>;
++ clocks = <&cpg CPG_MOD 824>;
++ power-domains = <&sysc R8A7797_PD_A2IR3>;
+ };
+
+ impc0 {
@@ -410,13 +418,6 @@ index 1be93e8..232eb19 100644
+ power-domains = <&sysc R8A7797_PD_A3IR>;
+ };
+
-+ impcnn0 {
-+ compatible = "renesas,impx4-legacy";
-+ reg = <0 0xff9e0000 0 0x10000>;
-+ clocks = <&cpg CPG_MOD 824>;
-+ power-domains = <&sysc R8A7797_PD_A2IR3>;
-+ };
-+
imrlx4_ch0: imr-lx4@fe860000 {
compatible = "renesas,imr-lx4";
reg = <0 0xfe860000 0 0x2000>;
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0082-gpio-pca953x-fix-interrupt-trigger.patch b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0082-gpio-pca953x-fix-interrupt-trigger.patch
new file mode 100644
index 0000000..f576759
--- /dev/null
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0082-gpio-pca953x-fix-interrupt-trigger.patch
@@ -0,0 +1,28 @@
+From 03708e8a6c537752528d865964fd37be56453995 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Fri, 15 Dec 2017 02:23:49 +0300
+Subject: [PATCH] gpio: pca953x: fix interrupt trigger
+
+The PCA9539 chip has edge sensitive interrupt
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+---
+ drivers/gpio/gpio-pca953x.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
+index fe731f0..0b3f0d8 100644
+--- a/drivers/gpio/gpio-pca953x.c
++++ b/drivers/gpio/gpio-pca953x.c
+@@ -626,7 +626,7 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
+ client->irq,
+ NULL,
+ pca953x_irq_handler,
+- IRQF_TRIGGER_LOW | IRQF_ONESHOT |
++ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT |
+ IRQF_SHARED,
+ dev_name(&client->dev), chip);
+ if (ret) {
+--
+1.9.1
+
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/eagle.cfg b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/eagle.cfg
index 9796ba5..5b728fd 100644
--- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/eagle.cfg
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/eagle.cfg
@@ -23,6 +23,7 @@ CONFIG_SOC_CAMERA_MAX9286_MAX9271=y
CONFIG_SOC_CAMERA_OV106XX=y
CONFIG_VIDEO_RENESAS_IMR=y
CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_UINPUT=y
CONFIG_TOUCHSCREEN_PROPERTIES=y
CONFIG_HID_MULTITOUCH=y
CONFIG_SERIAL_SH_SCI_DMA=y
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/ulcb.cfg b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/ulcb.cfg
index f1c86ca..0fd7e07 100644
--- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/ulcb.cfg
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/ulcb.cfg
@@ -72,4 +72,9 @@ CONFIG_TOUCHSCREEN_EDT_FT5X06=y
CONFIG_SERIAL_SH_SCI_DMA=y
CONFIG_STAGING=y
CONFIG_UIO=y
+CONFIG_SENSORS_EMC2103=y
+CONFIG_PMBUS=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_DS1307_HWMON=y
+CONFIG_SENSORS_LM63=y
CONFIG_MMC_SDHI_SEQ_WORKAROUND=y
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/v3msk.cfg b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/v3msk.cfg
index 211da49..34a385b 100644
--- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/v3msk.cfg
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/v3msk.cfg
@@ -27,6 +27,7 @@ CONFIG_SOC_CAMERA_TI954_TI9X3=y
CONFIG_SOC_CAMERA_OV106XX=y
CONFIG_VIDEO_RENESAS_IMR=y
CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_UINPUT=y
CONFIG_TOUCHSCREEN_PROPERTIES=y
CONFIG_HID_MULTITOUCH=y
CONFIG_SERIAL_SH_SCI_DMA=y
diff --git a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend
index 6876b5c..c4cad0f 100644
--- a/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend
+++ b/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas_4.9.bbappend
@@ -80,8 +80,7 @@ SRC_URI_append = " \
file://0077-MOST-dim2-add-timeouts.patch \
file://0078-MOST-aim-fix-null-pointer-crash.patch \
file://0079-Revert-dmaengine-rcar-dmac-use-TCRB-instead-of-TCR-f.patch \
- file://0080-dmaengine-rcar-dmac-ensure-CHCR-DE-bit-is-actually-0.patch \
- file://0081-dmaengine-rcar-dmac-use-TCRB-instead-of-TCR-for-resi.patch \
+ file://0082-gpio-pca953x-fix-interrupt-trigger.patch \
file://0001-arm64-dts-renesas-preserve-drm-HDMI-connector-naming.patch \
file://0001-arm64-dts-renesas-disable-r8a7796-hscif0-dma.patch \
"
@@ -104,12 +103,14 @@ KERNEL_DEVICETREE_append_h3ulcb = " \
renesas/r8a7795-es1-h3ulcb-had-beta.dtb \
renesas/r8a7795-es1-h3ulcb-kf.dtb \
renesas/r8a7795-es1-h3ulcb-vb.dtb \
+ renesas/r8a7795-es1-h3ulcb-vb2.dtb \
renesas/r8a7795-es1-h3ulcb-vbm.dtb \
renesas/r8a7795-h3ulcb-view.dtb \
renesas/r8a7795-h3ulcb-had-alfa.dtb \
renesas/r8a7795-h3ulcb-had-beta.dtb \
renesas/r8a7795-h3ulcb-kf.dtb \
renesas/r8a7795-h3ulcb-vb.dtb \
+ renesas/r8a7795-h3ulcb-vb2.dtb \
renesas/r8a7795-h3ulcb-vbm.dtb \
"
@@ -126,6 +127,7 @@ KERNEL_DEVICETREE_append_salvator-x = " \
KERNEL_DEVICETREE_append_eagle = " \
renesas/r8a7797-eagle.dtb \
+ renesas/r8a7797-eagle-function.dtb \
"
KERNEL_DEVICETREE_append_v3msk = " \