summaryrefslogtreecommitdiffstats
path: root/meta-rcar-gen3-adas
diff options
context:
space:
mode:
authorVladimir Barinov <vladimir.barinov@cogentembedded.com>2018-02-16 22:20:14 +0300
committerVladimir Barinov <vladimir.barinov@cogentembedded.com>2018-02-26 23:24:57 +0300
commitdae88899a1665c66491b8d40f383b6c04a5be558 (patch)
tree187fee2be0ca1aed1e7a59f2b0cd0b2416a85eb2 /meta-rcar-gen3-adas
parentea8f876b1ec11533ea57492fa4ec06be73a80763 (diff)
V3HSK: add access to CPLD
This add CPLD access for V3HSK
Diffstat (limited to 'meta-rcar-gen3-adas')
-rw-r--r--meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/00201-board-renesas-Add-V3HSK-board.patch229
1 files changed, 189 insertions, 40 deletions
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/00201-board-renesas-Add-V3HSK-board.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/00201-board-renesas-Add-V3HSK-board.patch
index 94067dc..dc07609 100644
--- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/00201-board-renesas-Add-V3HSK-board.patch
+++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/00201-board-renesas-Add-V3HSK-board.patch
@@ -7,17 +7,17 @@ V3H Starter Kit is a board based on R-Car V3H SoC (R8A7798)
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
- arch/arm/cpu/armv8/Kconfig | 4 +
- board/renesas/v3hsk/Kconfig | 15 +++
- board/renesas/v3hsk/MAINTAINERS | 6 +
- board/renesas/v3hsk/Makefile | 10 ++
- board/renesas/v3hsk/v3hsk.c | 263 ++++++++++++++++++++++++++++++++++++++++
- configs/v3hsk_defconfig | 10 ++
- include/configs/v3hsk.h | 160 ++++++++++++++++++++++++
- 7 files changed, 468 insertions(+)
+ arch/arm/cpu/armv8/Kconfig | 4 +
+ board/renesas/v3hsk/Kconfig | 15 +++
+ board/renesas/v3hsk/Makefile | 10 ++
+ board/renesas/v3hsk/cpld.c | 152 +++++++++++++++++++++++++
+ board/renesas/v3hsk/v3hsk.c | 266 +++++++++++++++++++++++++++++++++++++++++++
+ configs/v3hsk_defconfig | 10 ++
+ include/configs/v3hsk.h | 160 ++++++++++++++++++++++++++
+ 7 files changed, 617 insertions(+)
create mode 100644 board/renesas/v3hsk/Kconfig
- create mode 100644 board/renesas/v3hsk/MAINTAINERS
create mode 100644 board/renesas/v3hsk/Makefile
+ create mode 100644 board/renesas/v3hsk/cpld.c
create mode 100644 board/renesas/v3hsk/v3hsk.c
create mode 100644 configs/v3hsk_defconfig
create mode 100644 include/configs/v3hsk.h
@@ -64,21 +64,9 @@ index 0000000..2346ee8
+ default "v3hsk" if R8A7798
+
+endif
-diff --git a/board/renesas/v3hsk/MAINTAINERS b/board/renesas/v3hsk/MAINTAINERS
-new file mode 100644
-index 0000000..f9176b5
---- /dev/null
-+++ b/board/renesas/v3hsk/MAINTAINERS
-@@ -0,0 +1,6 @@
-+CONDOR BOARD
-+M: Cogent Embedded, Inc. <source@cogentembedded.com>
-+S: Maintained
-+F: board/renesas/v3hsk/
-+F: include/configs/v3hsk.h
-+F: configs/v3hsk_defconfig
diff --git a/board/renesas/v3hsk/Makefile b/board/renesas/v3hsk/Makefile
new file mode 100644
-index 0000000..0ac2642
+index 0000000..fb037fe
--- /dev/null
+++ b/board/renesas/v3hsk/Makefile
@@ -0,0 +1,10 @@
@@ -91,13 +79,171 @@ index 0000000..0ac2642
+# SPDX-License-Identifier: GPL-2.0+
+#
+
-+obj-y := v3hsk.o ../rcar-gen3-common/common.o
++obj-y := v3hsk.o ../rcar-gen3-common/common.o cpld.o
+diff --git a/board/renesas/v3hsk/cpld.c b/board/renesas/v3hsk/cpld.c
+new file mode 100644
+index 0000000..7c95534
+--- /dev/null
++++ b/board/renesas/v3hsk/cpld.c
+@@ -0,0 +1,152 @@
++/*
++ * V3HSK board CPLD access support
++ *
++ * Copyright (C) 2018 Renesas Electronics Corporation
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <i2c.h>
++
++#define ADDR_PRODUCT_0 0x0000 /* R */
++#define ADDR_PRODUCT_1 0x0001 /* R */
++#define ADDR_PRODUCT_2 0x0002 /* R */
++#define ADDR_PRODUCT_3 0x0003 /* R */
++#define ADDR_CPLD_VERSION_D 0x0004 /* R */
++#define ADDR_CPLD_VERSION_M 0x0005 /* R */
++#define ADDR_CPLD_VERSION_Y_0 0x0006 /* R */
++#define ADDR_CPLD_VERSION_Y_1 0x0007 /* R */
++#define ADDR_MODE_SET_0 0x0008 /* R */
++#define ADDR_MODE_SET_1 0x0009 /* R */
++#define ADDR_MODE_SET_2 0x000A /* R */
++#define ADDR_MODE_SET_3 0x000B /* R */
++#define ADDR_MODE_SET_4 0x000C /* R */
++#define ADDR_MODE_LAST_0 0x0018 /* R */
++#define ADDR_MODE_LAST_1 0x0019 /* R */
++#define ADDR_MODE_LAST_2 0x001A /* R */
++#define ADDR_MODE_LAST_3 0x001B /* R */
++#define ADDR_MODE_LAST_4 0x001C /* R */
++#define ADDR_DIPSW4 0x0020 /* R */
++#define ADDR_DIPSW5 0x0021 /* R */
++#define ADDR_RESET 0x0024 /* R/W */
++#define ADDR_POWER_CFG 0x0025 /* R/W */
++#define ADDR_PERI_CFG_0 0x0030 /* R/W */
++#define ADDR_PERI_CFG_1 0x0031 /* R/W */
++#define ADDR_PERI_CFG_2 0x0032 /* R/W */
++#define ADDR_PERI_CFG_3 0x0033 /* R/W */
++#define ADDR_LEDS 0x0034 /* R/W */
++#define ADDR_LEDS_CFG 0x0035 /* R/W */
++#define ADDR_UART_CFG 0x0036 /* R/W */
++#define ADDR_UART_STATUS 0x0037 /* R */
++
++#define ADDR_PCB_VERSION_0 0x1000 /* R */
++#define ADDR_PCB_VERSION_1 0x1001 /* R */
++#define ADDR_SOC_VERSION_0 0x1002 /* R */
++#define ADDR_SOC_VERSION_1 0x1003 /* R */
++#define ADDR_PCB_SN_0 0x1004 /* R */
++#define ADDR_PCB_SN_1 0x1005 /* R */
++
++static u16 cpld_read(u16 addr)
++{
++ u8 data;
++
++ /* random flash reads require 2 reads: first read is unreliable */
++ if (addr >= ADDR_PCB_VERSION_0)
++ i2c_read(CONFIG_SYS_I2C_CPLD_ADDR, addr, 2, &data, 1);
++
++ i2c_read(CONFIG_SYS_I2C_CPLD_ADDR, addr, 2, &data, 1);
++
++ return data;
++}
++
++static void cpld_write(u16 addr, u8 data)
++{
++ i2c_write(CONFIG_SYS_I2C_CPLD_ADDR, addr, 2, &data, 1);
++}
++
++static void cpld_init(void)
++{
++ i2c_set_bus_num(0);
++ i2c_init(400000, 0);
++}
++
++static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
++{
++ u16 addr, val;
++
++ cpld_init();
++
++ if (argc == 2 && strcmp(argv[1], "info") == 0) {
++ printf("Product: 0x%08x\n",
++ (cpld_read(ADDR_PRODUCT_3) << 24) |
++ (cpld_read(ADDR_PRODUCT_2) << 16) |
++ (cpld_read(ADDR_PRODUCT_1) << 8) |
++ cpld_read(ADDR_PRODUCT_0));
++ printf("CPLD version: 0x%08x\n",
++ (cpld_read(ADDR_CPLD_VERSION_Y_1) << 24) |
++ (cpld_read(ADDR_CPLD_VERSION_Y_0) << 16) |
++ (cpld_read(ADDR_CPLD_VERSION_M) << 8) |
++ cpld_read(ADDR_CPLD_VERSION_D));
++ printf("Mode setting (MD0..26): 0x%08x\n",
++ (cpld_read(ADDR_MODE_LAST_3) << 24) |
++ (cpld_read(ADDR_MODE_LAST_2) << 16) |
++ (cpld_read(ADDR_MODE_LAST_1) << 8) |
++ cpld_read(ADDR_MODE_LAST_0));
++ printf("DIPSW (SW4, SW5): 0x%02x, 0x%x\n",
++ cpld_read(ADDR_DIPSW4) ^ 0xff,
++ (cpld_read(ADDR_DIPSW5) ^ 0xff) & 0xf);
++ printf("Power config: 0x%08x\n",
++ cpld_read(ADDR_POWER_CFG));
++ printf("Periferals config: 0x%08x\n",
++ (cpld_read(ADDR_PERI_CFG_3) << 24) |
++ (cpld_read(ADDR_PERI_CFG_2) << 16) |
++ (cpld_read(ADDR_PERI_CFG_1) << 8) |
++ cpld_read(ADDR_PERI_CFG_0));
++ printf("PCB version: %d.%d\n",
++ (cpld_read(ADDR_PCB_VERSION_1) >> 8) |
++ (cpld_read(ADDR_PCB_VERSION_0) & 0xff));
++ printf("SOC version: %d.%d\n",
++ (cpld_read(ADDR_SOC_VERSION_1) << 8) |
++ (cpld_read(ADDR_SOC_VERSION_0) & 0xff));
++ printf("PCB S/N: %d\n",
++ (cpld_read(ADDR_PCB_SN_1) << 8) |
++ cpld_read(ADDR_PCB_SN_0));
++ return 0;
++ }
++
++ if (argc < 3)
++ return CMD_RET_USAGE;
++
++ addr = simple_strtoul(argv[2], NULL, 16);
++ if (!(addr >= ADDR_PRODUCT_0 && addr <= ADDR_UART_STATUS)) {
++ printf("cpld invalid addr\n");
++ return CMD_RET_USAGE;
++ }
++
++ if (argc == 3 && strcmp(argv[1], "read") == 0) {
++ printf("0x%x\n", cpld_read(addr));
++ } else if (argc == 4 && strcmp(argv[1], "write") == 0) {
++ val = simple_strtoul(argv[3], NULL, 16);
++ cpld_write(addr, val);
++ }
++
++ return 0;
++}
++
++U_BOOT_CMD(
++ cpld, 4, 1, do_cpld,
++ "CPLD access",
++ "info\n"
++ "cpld read addr\n"
++ "cpld write addr val\n"
++);
++
++void reset_cpu(ulong addr)
++{
++#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_RCAR)
++ cpld_init();
++ cpld_write(ADDR_RESET, 1);
++#endif
++}
diff --git a/board/renesas/v3hsk/v3hsk.c b/board/renesas/v3hsk/v3hsk.c
new file mode 100644
-index 0000000..df61428
+index 0000000..55e965e
--- /dev/null
+++ b/board/renesas/v3hsk/v3hsk.c
-@@ -0,0 +1,263 @@
+@@ -0,0 +1,266 @@
+/*
+ * board/renesas/v3hsk/v3hsk.c
+ * This is V3HSK board support.
@@ -133,6 +279,7 @@ index 0000000..df61428
+#define GETHER_MSTP813 (1 << 13)
+#define RPC_MSTP917 (1 << 17)
+#define SD0_MSTP314 (1 << 14)
++#define I2C0_MSTP931 (1 << 31)
+
+#define SD0CKCR 0xE6150074
+
@@ -172,6 +319,8 @@ index 0000000..df61428
+#endif
+ /* QSPI/RPC */
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, RPC_MSTP917);
++ /* I2C0 */
++ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, I2C0_MSTP931);
+
+ freq = rcar_get_sdhi_config_clk();
+ writel(freq, SD0CKCR);
@@ -260,7 +409,11 @@ index 0000000..df61428
+ gpio_request(GPIO_FN_RPC_RESET_N, NULL);
+ gpio_request(GPIO_FN_RPC_WP_N, NULL);
+ gpio_request(GPIO_FN_RPC_INT_N, NULL);
-+
++#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_RCAR)
++ /* I2C0 to access PMIC */
++ gpio_request(GPIO_IFN_SDA0, NULL);
++ gpio_request(GPIO_IFN_SCL0, NULL);
++#endif
+ return 0;
+}
+
@@ -350,10 +503,6 @@ index 0000000..df61428
+ CONFIG_RCAR_BOARD_STRING
+};
+
-+void reset_cpu(ulong addr)
-+{
-+}
-+
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+int checkboard(void)
+{
@@ -379,7 +528,7 @@ index 0000000..938ffe9
+CONFIG_SPI_FLASH_BAR=y
diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h
new file mode 100644
-index 0000000..6aa6625
+index 0000000..9f7ac49
--- /dev/null
+++ b/include/configs/v3hsk.h
@@ -0,0 +1,160 @@
@@ -469,6 +618,7 @@ index 0000000..6aa6625
+#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2)
+#define CONFIG_S3D2_CLK_FREQ (266666666u/2)
+#define CONFIG_S3D4_CLK_FREQ (266666666u/4)
++#define CONFIG_S2D2_CLK_FREQ (133333333u)
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
@@ -480,15 +630,14 @@ index 0000000..6aa6625
+
+/* i2c */
+#define CONFIG_SYS_I2C
-+#define CONFIG_SYS_I2C_SH
-+#define CONFIG_SYS_I2C_SLAVE 0x60
-+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1
-+#define CONFIG_SYS_I2C_SH_SPEED0 400000
-+#define CONFIG_SH_I2C_DATA_HIGH 4
-+#define CONFIG_SH_I2C_DATA_LOW 5
-+#define CONFIG_SH_I2C_CLOCK 10000000
-+
-+#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30
++#define CONFIG_SYS_I2C_RCAR
++#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
++#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
++#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
++#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
++#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 1
++#define CONFIG_SYS_I2C_CPLD_ADDR 0x70
++#define CONFIG_HP_CLK_FREQ CONFIG_S2D2_CLK_FREQ
+
+/* USB */
+#undef CONFIG_CMD_USB