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authorKhang Nguyen <khang.nguyen.xv@rvc.renesas.com>2018-04-12 07:58:18 +0700
committerThuy Tran <thuy.tran.xh@rvc.renesas.com>2018-04-21 09:04:25 +0700
commitcd0a1c72e360e4656b9d56ce11f01655d1a2d9b4 (patch)
treeda394b668bf43c7214528e8b54d82380f018f71c /meta-rcar-gen3/include
parentea79aabf3d6975c829488c6367ccbff745164703 (diff)
rcar-gen3: IPL: Update SRCREV to follow the latest version
This commit updates IPL and Secure Monitor to Rev1.0.20 rev2 for following changes: [IPL] - [H/W Restriction No.100] Disable TLB function on IPMMU-PV1 cache on H3 Ver.2.0. - Update H3 Ver.3.0 QoS setting rev.0.06. - Fix the IPL cannot load images to 40-bit address space with eMMC when D-Cache enables. - Add processing to read MSTP status into BL2. - Delete unnecessary register setting. - Add the SWTCNT setting of E3. - Change the unit of transfer size to 256 bytes for RPC, and improved DMA transfer processing. - Add DDR Memory Config log. [Secure Monitor] - Add processing to read MSTP status into BL31. For optee_os, it updates reversion to Rev1.0.13 for following change: - Add processing to read MSTP status into MFIS. It deletes the option which enables Lossy area for E3. It also supports build option for H3: - For R-Car H3 SiP DDR 8GiB (2GiB x 4ch), specify "RCAR_DRAM_SPLIT=1" - For R-Car H3 SiP DDR 4GiB (2GiB X 2ch), specify "RCAR_DRAM_SPLIT=2 RCAR_DRAM_CHANNEL=5" - For R-Car H3 SiP DDR 4GiB (1GiB x 4ch), specify "RCAR_DRAM_SPLIT=1 RCAR_DRAM_LPDDR4_MEMCONF=0" Signed-off-by: Khang Nguyen <khang.nguyen.xv@rvc.renesas.com> Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
Diffstat (limited to 'meta-rcar-gen3/include')
-rw-r--r--meta-rcar-gen3/include/arm-trusted-firmware-control.inc11
1 files changed, 11 insertions, 0 deletions
diff --git a/meta-rcar-gen3/include/arm-trusted-firmware-control.inc b/meta-rcar-gen3/include/arm-trusted-firmware-control.inc
new file mode 100644
index 0000000..8622c0b
--- /dev/null
+++ b/meta-rcar-gen3/include/arm-trusted-firmware-control.inc
@@ -0,0 +1,11 @@
+# This function is to add more IPL options to build with H3 (SoC: r8a7795)
+
+def get_ipl_config_opt(d):
+ option = d.getVar('H3_OPTION')
+ if option == "1":
+ d.setVar('IPL_CONFIG_OPT','RCAR_DRAM_SPLIT=1')
+ elif option == "2":
+ d.setVar('IPL_CONFIG_OPT','RCAR_DRAM_SPLIT=2 RCAR_DRAM_CHANNEL=5')
+ else:
+ d.setVar('IPL_CONFIG_OPT','RCAR_DRAM_SPLIT=1 RCAR_DRAM_LPDDR4_MEMCONF=0')
+ return d.getVar('IPL_CONFIG_OPT')