rcar-gen3: IPL: Support generating all variants of IPL binaries

This commit provides the capability to generate IPL binaries for
H3/H3ULCB/E3 build variants at the same time.

- For H3 SiP
 - *.srec: use for H3 SiP DDR 4GiB (1GiB x 4ch)
 - *-4x2g.srec: use for H3 SiP DDR 8GiB (2GiB x 4ch)
 - *-2x2g.srec: use for H3 SiP DDR 4GiB (2GiB x 2ch)

- For H3ULCB SiP
 - *.srec: use for H3ULCB SiP DDR 4GiB (1GiB x 4ch)
 - *-4x2g.srec: use for H3ULCB SiP DDR 8GiB (2GiB x 4ch)

- For E3 SiP
 - *.srec: use for E3 SiP DDR 1GiB
 - *-4d.srec: use for E3 SiP DDR 2GiB

Signed-off-by: Thuy Tran <thuy.tran.xh@renesas.com>
Signed-off-by: Khang Nguyen <khang.nguyen.xw@renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>

2 files changed, 60 insertions, 13 deletions

diff --git a/meta-rcar-gen3/include/arm-trusted-firmware-control.inc b/meta-rcar-gen3/include/arm-trusted-firmware-control.inc
index 8622c0b..013598d 100644
--- a/meta-rcar-gen3/include/arm-trusted-firmware-control.inc
+++ b/meta-rcar-gen3/include/arm-trusted-firmware-control.inc
@@ -1,11 +1,58 @@
-# This function is to add more IPL options to build with H3 (SoC: r8a7795)
-
-def get_ipl_config_opt(d):
-    option = d.getVar('H3_OPTION')
-    if option == "1":
-        d.setVar('IPL_CONFIG_OPT','RCAR_DRAM_SPLIT=1')
-    elif option == "2":
-        d.setVar('IPL_CONFIG_OPT','RCAR_DRAM_SPLIT=2 RCAR_DRAM_CHANNEL=5')
-    else:
-        d.setVar('IPL_CONFIG_OPT','RCAR_DRAM_SPLIT=1 RCAR_DRAM_LPDDR4_MEMCONF=0')
-    return d.getVar('IPL_CONFIG_OPT')
+# This function is to generate IPL binaries for H3/H3ULCB (SoC: r8a7795), E3 (SoC: r8a7790)
+
+# IPL build options for H3/E3/H3ULCB
+EXTRA_ATFW_OPT ?= ""
+EXTRA_ATFW_CONF ?= ""
+
+do_ipl_opt_compile () {
+    oe_runmake distclean
+    oe_runmake bl2 bl31 dummytool PLAT=${PLATFORM} ${EXTRA_ATFW_OPT} ${ATFW_OPT_LOSSY}
+}
+
+do_ipl_opt_deploy () {
+    install -d ${DEPLOYDIR}
+
+    # Copy IPL to deploy folder
+    install -m 0644 ${S}/build/${PLATFORM}/release/bl2/bl2.elf ${DEPLOYDIR}/bl2-${MACHINE}-${EXTRA_ATFW_CONF}.elf
+    install -m 0644 ${S}/build/${PLATFORM}/release/bl2.bin ${DEPLOYDIR}/bl2-${MACHINE}-${EXTRA_ATFW_CONF}.bin
+    install -m 0644 ${S}/build/${PLATFORM}/release/bl2.srec ${DEPLOYDIR}/bl2-${MACHINE}-${EXTRA_ATFW_CONF}.srec
+    install -m 0644 ${S}/build/${PLATFORM}/release/bl31/bl31.elf ${DEPLOYDIR}/bl31-${MACHINE}-${EXTRA_ATFW_CONF}.elf
+    install -m 0644 ${S}/build/${PLATFORM}/release/bl31.bin ${DEPLOYDIR}/bl31-${MACHINE}-${EXTRA_ATFW_CONF}.bin
+    install -m 0644 ${S}/build/${PLATFORM}/release/bl31.srec ${DEPLOYDIR}/bl31-${MACHINE}-${EXTRA_ATFW_CONF}.srec
+    install -m 0644 ${S}/tools/dummy_create/bootparam_sa0.srec ${DEPLOYDIR}/bootparam_sa0-${EXTRA_ATFW_CONF}.srec
+    install -m 0644 ${S}/tools/dummy_create/cert_header_sa6.srec ${DEPLOYDIR}/cert_header_sa6-${EXTRA_ATFW_CONF}.srec
+}
+
+# For IPL compile options for H3/H3ULCB (SoC: r8a7795), E3 (SoC: r8a7790)
+python do_extra_ipl_opt() {
+    soc = d.getVar('SOC_FAMILY')
+    soc = soc.split(':')[1]
+    machine = d.getVar('MACHINE_ARCH')
+
+    if soc == "r8a7795":
+        # For H3 SiP DDR 4GiB (2GiB x 2ch)
+        if machine != "h3ulcb":
+            d.setVar('EXTRA_ATFW_CONF', '2x2g')
+            d.setVar('EXTRA_ATFW_OPT', ' LSI=H3 RCAR_DRAM_SPLIT=2 RCAR_DRAM_CHANNEL=5 ')
+            bb.build.exec_func('do_ipl_opt_compile', d)
+            bb.build.exec_func('do_ipl_opt_deploy', d)
+
+        # For H3/H3ULCB SiP DDR 8GiB (2GiB x 4ch)
+        d.setVar('EXTRA_ATFW_CONF', '4x2g')
+        d.setVar('EXTRA_ATFW_OPT', ' LSI=H3 RCAR_DRAM_SPLIT=1 ')
+        d.setVar('EXTRA_ATFW_OPT_append_ulcb', ' RCAR_GEN3_ULCB=1 PMIC_LEVEL_MODE=0 ')
+        bb.build.exec_func('do_ipl_opt_compile', d)
+        bb.build.exec_func('do_ipl_opt_deploy', d)
+
+    # For E3 SiP DDR 2GiB
+    if soc == "r8a77990":
+        d.setVar('EXTRA_ATFW_CONF', '4d')
+        d.setVar('EXTRA_ATFW_OPT', ' LSI=E3 RCAR_SA0_SIZE=0 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=1 RCAR_DRAM_DDR3L_MEMDUAL=1 ')
+        bb.build.exec_func('do_ipl_opt_compile', d)
+        bb.build.exec_func('do_ipl_opt_deploy', d)
+}
+
+do_ipl_opt_compile[dirs] = "${B}"
+do_ipl_opt_deploy[dirs] = "${B}"
+
+addtask extra_ipl_opt after do_configure before do_compile
diff --git a/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb b/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb
index 096d25d..1456ff7 100644
--- a/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb
+++ b/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb
@@ -19,9 +19,8 @@ PV = "v1.5+renesas+git${SRCPV}"
 
 COMPATIBLE_MACHINE = "(salvator-x|ulcb|ebisu)"
 PLATFORM = "rcar"
-H3_IPL_OPTION = "${@get_ipl_config_opt(d)}"
 ATFW_OPT_LOSSY = "${@base_conditional("USE_MULTIMEDIA", "1", "RCAR_LOSSY_ENABLE=1", "", d)}"
-ATFW_OPT_r8a7795 = "LSI=H3 ${H3_IPL_OPTION} ${ATFW_OPT_LOSSY}"
+ATFW_OPT_r8a7795 = "LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_DRAM_LPDDR4_MEMCONF=0 ${ATFW_OPT_LOSSY}"
 ATFW_OPT_r8a7796 = "LSI=M3 RCAR_DRAM_SPLIT=2 ${ATFW_OPT_LOSSY}"
 ATFW_OPT_r8a77965 = "LSI=M3N ${ATFW_OPT_LOSSY}"
 ATFW_OPT_r8a77990 = "LSI=E3 RCAR_SA0_SIZE=0 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=0 RCAR_DRAM_DDR3L_MEMDUAL=0"
@@ -37,6 +36,7 @@ AS[unexport] = "1"
 LD[unexport] = "1"
 
 do_compile() {
+    oe_runmake distclean
     oe_runmake bl2 bl31 dummytool PLAT=${PLATFORM} ${ATFW_OPT}
 }