diff options
Diffstat (limited to 'meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files')
| -rw-r--r-- | meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0002-plat-renesas-rcar-kingfisher-reboot-fix-power-off-on-reset.diff | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0002-plat-renesas-rcar-kingfisher-reboot-fix-power-off-on-reset.diff b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0002-plat-renesas-rcar-kingfisher-reboot-fix-power-off-on-reset.diff new file mode 100644 index 0000000..144b013 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0002-plat-renesas-rcar-kingfisher-reboot-fix-power-off-on-reset.diff @@ -0,0 +1,37 @@ +From 04ad289ba1e861ab1dd915d7327095173707c236 Mon Sep 17 00:00:00 2001 +From: Sergii Boryshchenko <sergii.boryshchenko@globallogic.com> +Date: Thu, 30 Nov 2017 14:53:52 +0200 +Subject: [PATCH] kingfisher: reboot: fix power-off on reset + +Method cpld_reset_cpu of bl31 is called from the Linux kernel and uses +GPIO6, GPIO2 pins as SPI bus lines to control the CPLD device. But in the +kernel GPIO6_8 pin are initialized to work in interrupt mode instead of +the input/output mode. This leads to the fact that the SPI bus becomes +non-functional. In this patch we switch the GPIO6_8 pin back to the +input-output mode. + +Signed-off-by: Sergii Boryshchenko <sergii.boryshchenko@globallogic.com> +--- + +diff --git a/plat/renesas/rcar/drivers/cpld/ulcb_cpld.c b/plat/renesas/rcar/drivers/cpld/ulcb_cpld.c +index b0117ef..b171d79 100644 +--- a/plat/renesas/rcar/drivers/cpld/ulcb_cpld.c ++++ b/plat/renesas/rcar/drivers/cpld/ulcb_cpld.c +@@ -49,6 +49,9 @@ + #define GPIO_INOUTSEL2 0xE6052004 + #define GPIO_INOUTSEL6 0xE6055404 + ++/* General IO/Interrupt Switching Register */ ++#define GPIO_IOINTSEL6 0xE6055400 ++ + /* GPIO/perihperal function select */ + #define PFC_GPSR2 0xE6060108 + #define PFC_GPSR6 0xE6060118 +@@ -115,6 +118,7 @@ + gpio_pfc(PFC_GPSR2, SSTBZ); + gpio_pfc(PFC_GPSR6, MOSI); + ++ gpio_set_value(GPIO_IOINTSEL6, SCLK, 0); + gpio_set_value(GPIO_OUTDT6, SCLK, 0); + gpio_set_value(GPIO_OUTDT2, SSTBZ, 1); + gpio_set_value(GPIO_OUTDT6, MOSI, 0); |