diff options
Diffstat (limited to 'meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware')
3 files changed, 135 insertions, 0 deletions
diff --git a/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bbappend b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bbappend new file mode 100644 index 0000000..aefd88a --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bbappend @@ -0,0 +1,14 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/files:" + +ATFW_OPT_append = " ${@base_conditional("CA57CA53BOOT", "1", " PSCI_DISABLE_BIGLITTLE_IN_CA57BOOT=0", "", d)}" +ATFW_OPT_append += " ${@base_conditional("DISABLE_RPC_ACCESS", "1", " RCAR_DISABLE_NONSECURE_RPC_ACCESS=1", "", d)}" + +SRC_URI_append = " \ + file://0001-plat-renesas-rcar-Make-RPC-secure-settings-optional.patch \ + file://0002-plat-renesas-rcar-kingfisher-reboot-fix-power-off-on-reset.diff \ +" + +do_deploy_append() { + install -m 0644 ${S}/tools/dummy_create/bootparam_sa0.bin ${DEPLOYDIR}/bootparam_sa0.bin + install -m 0644 ${S}/tools/dummy_create/cert_header_sa6.bin ${DEPLOYDIR}/cert_header_sa6.bin +} diff --git a/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0001-plat-renesas-rcar-Make-RPC-secure-settings-optional.patch b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0001-plat-renesas-rcar-Make-RPC-secure-settings-optional.patch new file mode 100644 index 0000000..06a6fe1 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0001-plat-renesas-rcar-Make-RPC-secure-settings-optional.patch @@ -0,0 +1,84 @@ +From 88373fb822f737b60c8c71ca799ec50efaebf5bc Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Tue, 4 Jul 2017 21:09:26 +0300 +Subject: [PATCH] plat: renesas: rcar: Make RPC secure settings optional + +This adds RCAR_DISABLE_NONSECURE_RPC_ACCESS make variable which +disables non-secure RPC access when set to a non-zero value. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + plat/renesas/rcar/bl2_secure_setting.c | 4 ++++ + plat/renesas/rcar/bl31_rcar_setup.c | 16 ++++++++++++++++ + plat/renesas/rcar/platform.mk | 6 ++++++ + 3 files changed, 26 insertions(+) + +diff --git a/plat/renesas/rcar/bl2_secure_setting.c b/plat/renesas/rcar/bl2_secure_setting.c +index 3ab651f..40e6a36 100644 +--- a/plat/renesas/rcar/bl2_secure_setting.c ++++ b/plat/renesas/rcar/bl2_secure_setting.c +@@ -108,7 +108,9 @@ static const struct { + /** Security attribute setting for slave ports 13 */ + /* Bit22: RPC slave ports. */ + /* 0: registers can be accessed from secure resource only. */ ++#if (RCAR_DISABLE_NONSECURE_RPC_ACCESS != 0) + {SEC_SEL13, 0xFFBFFFFFU}, ++#endif + + /** Security attribute setting for slave ports 14 */ + /* Bit27: System Timer (SCMT) slave ports. */ +@@ -232,8 +234,10 @@ static const struct { + /** Security group 1 attribute setting for slave ports 13 */ + /* Bit22: RPC slave ports. */ + /* SecurityGroup3 */ ++#if (RCAR_DISABLE_NONSECURE_RPC_ACCESS != 0) + {SEC_GRP0COND13, 0x00400000U}, + {SEC_GRP1COND13, 0x00400000U}, ++#endif + + /** Security group 0 attribute setting for slave ports 14 */ + /** Security group 1 attribute setting for slave ports 14 */ +diff --git a/plat/renesas/rcar/bl31_rcar_setup.c b/plat/renesas/rcar/bl31_rcar_setup.c +index cc6ad2c..c91297d 100644 +--- a/plat/renesas/rcar/bl31_rcar_setup.c ++++ b/plat/renesas/rcar/bl31_rcar_setup.c +@@ -232,3 +232,19 @@ int32_t bl31_plat_denied_cpu_off_chk(void) + return rc; + } + ++/******************************************************************************* ++ * Perform the runtime platform specific setup here. ++ ******************************************************************************/ ++void bl31_plat_runtime_setup(void) ++{ ++#if (RCAR_DISABLE_NONSECURE_RPC_ACCESS == 0) ++ /* Enable non-secure access to the RPC HyperFlash region. */ ++ mmio_write_32(0xee2000b8, 0x155); ++ mmio_write_32(0xee200000, mmio_read_32(0xee200000) & 0x7fffffff); ++#endif ++ /* ++ * Finish the use of console driver in BL31 so that any runtime logs ++ * from BL31 will be suppressed. ++ */ ++ console_uninit(); ++} +diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk +index 6abc088..60f41ae 100644 +--- a/plat/renesas/rcar/platform.mk ++++ b/plat/renesas/rcar/platform.mk +@@ -223,6 +223,12 @@ RCAR_GEN3_ULCB := 0 + endif + $(eval $(call add_define,RCAR_GEN3_ULCB)) + ++# Process RCAR_DISABLE_NONSECURE_RPC_ACCESS flag ++ifndef RCAR_DISABLE_NONSECURE_RPC_ACCESS ++RCAR_DISABLE_NONSECURE_RPC_ACCESS := 0 ++endif ++$(eval $(call add_define,RCAR_DISABLE_NONSECURE_RPC_ACCESS)) ++ + include plat/renesas/rcar/ddr/ddr.mk + include plat/renesas/rcar/qos/qos.mk + include plat/renesas/rcar/pfc/pfc.mk +-- +2.7.5 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0002-plat-renesas-rcar-kingfisher-reboot-fix-power-off-on-reset.diff b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0002-plat-renesas-rcar-kingfisher-reboot-fix-power-off-on-reset.diff new file mode 100644 index 0000000..144b013 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0002-plat-renesas-rcar-kingfisher-reboot-fix-power-off-on-reset.diff @@ -0,0 +1,37 @@ +From 04ad289ba1e861ab1dd915d7327095173707c236 Mon Sep 17 00:00:00 2001 +From: Sergii Boryshchenko <sergii.boryshchenko@globallogic.com> +Date: Thu, 30 Nov 2017 14:53:52 +0200 +Subject: [PATCH] kingfisher: reboot: fix power-off on reset + +Method cpld_reset_cpu of bl31 is called from the Linux kernel and uses +GPIO6, GPIO2 pins as SPI bus lines to control the CPLD device. But in the +kernel GPIO6_8 pin are initialized to work in interrupt mode instead of +the input/output mode. This leads to the fact that the SPI bus becomes +non-functional. In this patch we switch the GPIO6_8 pin back to the +input-output mode. + +Signed-off-by: Sergii Boryshchenko <sergii.boryshchenko@globallogic.com> +--- + +diff --git a/plat/renesas/rcar/drivers/cpld/ulcb_cpld.c b/plat/renesas/rcar/drivers/cpld/ulcb_cpld.c +index b0117ef..b171d79 100644 +--- a/plat/renesas/rcar/drivers/cpld/ulcb_cpld.c ++++ b/plat/renesas/rcar/drivers/cpld/ulcb_cpld.c +@@ -49,6 +49,9 @@ + #define GPIO_INOUTSEL2 0xE6052004 + #define GPIO_INOUTSEL6 0xE6055404 + ++/* General IO/Interrupt Switching Register */ ++#define GPIO_IOINTSEL6 0xE6055400 ++ + /* GPIO/perihperal function select */ + #define PFC_GPSR2 0xE6060108 + #define PFC_GPSR6 0xE6060118 +@@ -115,6 +118,7 @@ + gpio_pfc(PFC_GPSR2, SSTBZ); + gpio_pfc(PFC_GPSR6, MOSI); + ++ gpio_set_value(GPIO_IOINTSEL6, SCLK, 0); + gpio_set_value(GPIO_OUTDT6, SCLK, 0); + gpio_set_value(GPIO_OUTDT2, SSTBZ, 1); + gpio_set_value(GPIO_OUTDT6, MOSI, 0); |