diff options
Diffstat (limited to 'meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0024-board-renesas-ulcb-Enable-RPC-clock.patch')
| -rw-r--r-- | meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0024-board-renesas-ulcb-Enable-RPC-clock.patch | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0024-board-renesas-ulcb-Enable-RPC-clock.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0024-board-renesas-ulcb-Enable-RPC-clock.patch new file mode 100644 index 0000000..1e2c155 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0024-board-renesas-ulcb-Enable-RPC-clock.patch @@ -0,0 +1,37 @@ +From 721d2a219485d106b577701e8643638a500bba30 Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Wed, 2 Nov 2016 21:31:24 +0300 +Subject: [PATCH] board: renesas: ulcb: Enable RPC clock + +The RPC clock should have been enabled by the ARM trusted firmware. +Enable it here just in case. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + board/renesas/ulcb/ulcb.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c +index 3939f97..2e9baac 100644 +--- a/board/renesas/ulcb/ulcb.c ++++ b/board/renesas/ulcb/ulcb.c +@@ -33,6 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; + #define SCIF2_MSTP310 (1 << 10) + #define ETHERAVB_MSTP812 (1 << 12) + #define DVFS_MSTP926 (1 << 26) ++#define RPC_MSTP917 (1 << 17) + #define SD0_MSTP314 (1 << 14) + #define SD1_MSTP313 (1 << 13) + #define SD2_MSTP312 (1 << 12) +@@ -53,6 +54,8 @@ int board_early_init_f(void) + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310); + /* EHTERAVB */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812); ++ /* RPC */ ++ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, RPC_MSTP917); + /* eMMC */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312); + /* SDHI0 */ +-- +1.9.3 + |