diff options
Diffstat (limited to 'meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot')
26 files changed, 8355 insertions, 0 deletions
diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0001-net-phy-support-fixed-PHY.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0001-net-phy-support-fixed-PHY.patch new file mode 100644 index 0000000..e745be7 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0001-net-phy-support-fixed-PHY.patch @@ -0,0 +1,115 @@ +From 1f65b4710c1f51d01032db201543d0a8269a715f Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Fri, 20 May 2016 01:18:44 +0300 +Subject: [PATCH] uboot: net: support fixed-PHY + +Add support for fixed-PHY + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +--- + drivers/net/phy/Makefile | 1 + + drivers/net/phy/fixed.c | 43 +++++++++++++++++++++++++++++++++++++++++++ + drivers/net/phy/phy.c | 5 ++++- + include/phy.h | 1 + + 6 files changed, 57 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/phy/fixed.c + +diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile +index d096db8..497785e 100644 +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -17,6 +17,7 @@ obj-$(CONFIG_PHY_BROADCOM) += broadcom.o + obj-$(CONFIG_PHY_CORTINA) += cortina.o + obj-$(CONFIG_PHY_DAVICOM) += davicom.o + obj-$(CONFIG_PHY_ET1011C) += et1011c.o ++obj-$(CONFIG_PHY_FIXED) += fixed.o + obj-$(CONFIG_PHY_LXT) += lxt.o + obj-$(CONFIG_PHY_MARVELL) += marvell.o + obj-$(CONFIG_PHY_MICREL) += micrel.o +diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c +new file mode 100644 +index 0000000..4d44aad +--- /dev/null ++++ b/drivers/net/phy/fixed.c +@@ -0,0 +1,43 @@ ++/* ++ * Fixed PHY driver ++ * ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * Copyright (C) 2016 Cogent Embedded, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <config.h> ++#include <common.h> ++#include <phy.h> ++ ++int fixed_config(struct phy_device *phydev) ++{ ++ phydev->speed = CONFIG_PHY_FIXED_SPEED; ++ phydev->duplex = CONFIG_PHY_FIXED_DUPLEX; ++ phydev->link = 1; ++ ++ return 0; ++} ++ ++static int fixed_startup(struct phy_device *phydev) ++{ ++ return 0; ++} ++ ++static struct phy_driver fixed_driver = { ++ .uid = 0x0, ++ .mask = 0x0, ++ .name = "fixed-PHY", ++ .features = PHY_10G_FEATURES, ++ .config = &fixed_config, ++ .startup = &fixed_startup, ++ .shutdown = &genphy_shutdown, ++}; ++ ++int phy_fixed_init(void) ++{ ++ phy_register(&fixed_driver); ++ ++ return 0; ++} +diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c +index df7e945..3ee6402 100644 +--- a/drivers/net/phy/phy.c ++++ b/drivers/net/phy/phy.c +@@ -484,6 +484,9 @@ int phy_init(void) + #ifdef CONFIG_PHY_VITESSE + phy_vitesse_init(); + #endif ++#ifdef CONFIG_PHY_FIXED ++ phy_fixed_init(); ++#endif + + return 0; + } +@@ -764,7 +767,7 @@ void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev) + phydev->dev->name, dev->name); + } + phydev->dev = dev; +- debug("%s connected to %s\n", dev->name, phydev->drv->name); ++ printf("%s connected to %s\n", dev->name, phydev->drv->name); + } + + struct phy_device *phy_connect(struct mii_dev *bus, int addr, +diff --git a/include/phy.h b/include/phy.h +index d117fc1..c2f2cbc 100644 +--- a/include/phy.h ++++ b/include/phy.h +@@ -239,6 +239,7 @@ int phy_realtek_init(void); + int phy_smsc_init(void); + int phy_teranetics_init(void); + int phy_vitesse_init(void); ++int phy_fixed_init(void); + + int board_phy_config(struct phy_device *phydev); + +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0002-net-ravb-remove-APSR-quirk.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0002-net-ravb-remove-APSR-quirk.patch new file mode 100644 index 0000000..60c9e14 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0002-net-ravb-remove-APSR-quirk.patch @@ -0,0 +1,33 @@ +From 1247dea7b49d7e66e1848da71e28ff5fe9acf5e1 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Thu, 16 Jun 2016 11:41:43 +0300 +Subject: [PATCH] uboot: ravb: remove APSR quirk + +Remove 2ns delay interoduces by DMAC APSR. This is +not used in linux kernel, hence it is important to skips this +in uboot. + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +--- + drivers/net/ravb.c | 5 ----- + 1 files changed, 0 insertions(+), 5 deletions(-) + +diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c +index c168381..f4d7aed 100644 +--- a/drivers/net/ravb.c ++++ b/drivers/net/ravb.c +@@ -428,11 +428,6 @@ static int ravb_dmac_init(struct ravb_dev *eth) + /* FIFO size set */ + ravb_write(eth, 0x00222210, TGC); + +- if (CONFIG_RAVB_PHY_MODE == PHY_INTERFACE_MODE_RGMII_ID) { +- /* delay CLK: 2ns */ +- ravb_write(eth, 0x1ul << 14, APSR); +- } +- + return ret; + } + +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0003-net-ravb-fix-unsafe-phy-access.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0003-net-ravb-fix-unsafe-phy-access.patch new file mode 100644 index 0000000..584d6d5 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0003-net-ravb-fix-unsafe-phy-access.patch @@ -0,0 +1,30 @@ +From 63534a79e2fb1e4102fe38f339ecb891682a781e Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Fri, 23 Sep 2016 18:26:53 +0300 +Subject: [PATCH] net: ravb: fix unsafe phy access + +This fixes the ravb driver crash for phy/phyless glue +that do not have writeext field + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +--- + drivers/net/ravb.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c +index f4d7aed..5d90a3e 100644 +--- a/drivers/net/ravb.c ++++ b/drivers/net/ravb.c +@@ -475,7 +475,8 @@ static int ravb_config(struct ravb_dev *eth, bd_t *bd) + ravb_write(eth, ECMR_CHG_DM | ECMR_RE | ECMR_TE, ECMR); + } + +- phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f<<5) | 0x19); ++ if (phy->drv->writeext) ++ phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f<<5) | 0x19); + + err_phy_cfg: + return ret; +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0004-configs-rcar-gen3-add-CMD_GPIO.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0004-configs-rcar-gen3-add-CMD_GPIO.patch new file mode 100644 index 0000000..f95994f --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0004-configs-rcar-gen3-add-CMD_GPIO.patch @@ -0,0 +1,27 @@ +From 3e733c036e8f50cf073b598074ce9fd6796ec89f Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Sun, 31 Jul 2016 03:59:13 +0300 +Subject: [PATCH] configs: rcar-gen3: add CMD_GPIO + +Enable CONFIG_CMD_GPIO + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +--- + include/configs/rcar-gen3-common.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h +index 63b80a4..50cfa8a 100644 +--- a/include/configs/rcar-gen3-common.h ++++ b/include/configs/rcar-gen3-common.h +@@ -31,6 +31,7 @@ + #define CONFIG_CMD_EXT2 + #define CONFIG_CMD_EXT4 + #define CONFIG_CMD_EXT4_WRITE ++#define CONFIG_CMD_GPIO + + #define CONFIG_SYS_THUMB_BUILD + #define CONFIG_SYS_GENERIC_BOARD +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0005-common-cmd_source.c-Fix-the-source-command-failure-u.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0005-common-cmd_source.c-Fix-the-source-command-failure-u.patch new file mode 100644 index 0000000..81a205f --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0005-common-cmd_source.c-Fix-the-source-command-failure-u.patch @@ -0,0 +1,53 @@ +From 5b189130c95630cf68c50255fb0d1ed0515cb92a Mon Sep 17 00:00:00 2001 +From: Gong Qianyu <Qianyu.Gong@freescale.com> +Date: Thu, 30 Jul 2015 14:00:01 +0800 +Subject: [PATCH] common/cmd_source.c: Fix the source command failure + under 64-bit platform + +Modify the data pointer type from ulong* to u32*. + +For arm64 type "ulong" could be 64-bit. Then in line 88 of common/cmd_source.c: +"while (*data++);" data will point to the next 64 bits each time. As the uImage +file generated by mkimage tool keeps the same data format in either 32-bit or 64-bit +platform, the difference would cause failure in 64-bit platform. + +Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + common/cmd_source.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/common/cmd_source.c b/common/cmd_source.c +index 6881bc9..291e5f4 100644 +--- a/common/cmd_source.c ++++ b/common/cmd_source.c +@@ -32,7 +32,7 @@ source (ulong addr, const char *fit_uname) + #if defined(CONFIG_IMAGE_FORMAT_LEGACY) + const image_header_t *hdr; + #endif +- ulong *data; ++ u32 *data; + int verify; + void *buf; + #if defined(CONFIG_FIT) +@@ -73,7 +73,7 @@ source (ulong addr, const char *fit_uname) + } + + /* get length of script */ +- data = (ulong *)image_get_data (hdr); ++ data = (u32 *)image_get_data (hdr); + + if ((len = uimage_to_cpu (*data)) == 0) { + puts ("Empty Script\n"); +@@ -127,7 +127,7 @@ source (ulong addr, const char *fit_uname) + return 1; + } + +- data = (ulong *)fit_data; ++ data = (u32 *)fit_data; + len = (ulong)fit_len; + break; + #endif +-- +1.9.3 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0006-configs-rcar-gen3-common-Enable-U-Boot-scripts.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0006-configs-rcar-gen3-common-Enable-U-Boot-scripts.patch new file mode 100644 index 0000000..aa92851 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0006-configs-rcar-gen3-common-Enable-U-Boot-scripts.patch @@ -0,0 +1,30 @@ +From 3defaae29edd09e89ea0d05082a7a8d5d2cb48d0 Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Sat, 10 Sep 2016 04:26:24 +0300 +Subject: [PATCH] configs: rcar-gen3-common: Enable U-Boot scripts + +This enables "source" command, which can be used +for running U-Boot scripts in order to simplify +flashing procedure. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + include/configs/rcar-gen3-common.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h +index 50cfa8a..bab2c2c 100644 +--- a/include/configs/rcar-gen3-common.h ++++ b/include/configs/rcar-gen3-common.h +@@ -33,6 +33,8 @@ + #define CONFIG_CMD_EXT4_WRITE + #define CONFIG_CMD_GPIO + ++#define CONFIG_CMD_SOURCE ++ + #define CONFIG_SYS_THUMB_BUILD + #define CONFIG_SYS_GENERIC_BOARD + +-- +1.9.3 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0007-configs-rcar-gen3-common-Enable-echo-command.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0007-configs-rcar-gen3-common-Enable-echo-command.patch new file mode 100644 index 0000000..fe5ab67 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0007-configs-rcar-gen3-common-Enable-echo-command.patch @@ -0,0 +1,28 @@ +From bb2193f5970ca989910df135010f39d0931c79fb Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Sat, 10 Sep 2016 05:20:07 +0300 +Subject: [PATCH] configs: rcar-gen3-common: Enable echo command + +This enables "echo" command, which can be used +to make U-Boot scripts more verbose. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + include/configs/rcar-gen3-common.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h +index bab2c2c..7b75562 100644 +--- a/include/configs/rcar-gen3-common.h ++++ b/include/configs/rcar-gen3-common.h +@@ -34,6 +34,7 @@ + #define CONFIG_CMD_GPIO + + #define CONFIG_CMD_SOURCE ++#define CONFIG_CMD_ECHO + + #define CONFIG_SYS_THUMB_BUILD + #define CONFIG_SYS_GENERIC_BOARD +-- +1.9.3 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0008-configs-rcar-gen3-common-Enable-setexpr-command.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0008-configs-rcar-gen3-common-Enable-setexpr-command.patch new file mode 100644 index 0000000..34e0942 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0008-configs-rcar-gen3-common-Enable-setexpr-command.patch @@ -0,0 +1,28 @@ +From d26edbbf50868a39e840c5f775a9e48f063ec638 Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Tue, 20 Sep 2016 23:20:15 +0300 +Subject: [PATCH] configs: rcar-gen3-common: Enable setexpr command + +This enables "setexpr" command, which can be used +to evaluate expressions. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + include/configs/rcar-gen3-common.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h +index 7b75562..aaeaf57 100644 +--- a/include/configs/rcar-gen3-common.h ++++ b/include/configs/rcar-gen3-common.h +@@ -35,6 +35,7 @@ + + #define CONFIG_CMD_SOURCE + #define CONFIG_CMD_ECHO ++#define CONFIG_CMD_SETEXPR + + #define CONFIG_SYS_THUMB_BUILD + #define CONFIG_SYS_GENERIC_BOARD +-- +1.9.3 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0009-configs-rcar-gen3-common-Enable-askenv-command.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0009-configs-rcar-gen3-common-Enable-askenv-command.patch new file mode 100644 index 0000000..4cb1b03 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0009-configs-rcar-gen3-common-Enable-askenv-command.patch @@ -0,0 +1,28 @@ +From 5e9a9694daa132d7b4acfd334fe3fe7f3a25b839 Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Wed, 21 Sep 2016 02:19:13 +0300 +Subject: [PATCH] configs: rcar-gen3-common: Enable askenv command + +This enables "askenv" command, which can be used +in U-Boot scripts for user input. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + include/configs/rcar-gen3-common.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h +index aaeaf57..2c2a5a5 100644 +--- a/include/configs/rcar-gen3-common.h ++++ b/include/configs/rcar-gen3-common.h +@@ -36,6 +36,7 @@ + #define CONFIG_CMD_SOURCE + #define CONFIG_CMD_ECHO + #define CONFIG_CMD_SETEXPR ++#define CONFIG_CMD_ASKENV + + #define CONFIG_SYS_THUMB_BUILD + #define CONFIG_SYS_GENERIC_BOARD +-- +1.9.3 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0010-configs-rcar-gen3-common-Enable-hush-parser.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0010-configs-rcar-gen3-common-Enable-hush-parser.patch new file mode 100644 index 0000000..b02cd7a --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0010-configs-rcar-gen3-common-Enable-hush-parser.patch @@ -0,0 +1,30 @@ +From d3687cb45f88245068027956b3e42f13f854dbc0 Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Mon, 12 Sep 2016 21:00:01 +0300 +Subject: [PATCH] configs: rcar-gen3-common: Enable hush parser + +This enables hush parser, which supports +conditionals and can be used to make +U-Boot scripts more flexible. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + include/configs/rcar-gen3-common.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h +index 2c2a5a5..aa692e5 100644 +--- a/include/configs/rcar-gen3-common.h ++++ b/include/configs/rcar-gen3-common.h +@@ -41,6 +41,8 @@ + #define CONFIG_SYS_THUMB_BUILD + #define CONFIG_SYS_GENERIC_BOARD + ++#define CONFIG_SYS_HUSH_PARSER ++ + #define CONFIG_REMAKE_ELF + + /* boot option */ +-- +1.9.3 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0011-configs-rcar-gen3-common-Enable-GPT-support.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0011-configs-rcar-gen3-common-Enable-GPT-support.patch new file mode 100644 index 0000000..a45cbc7 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0011-configs-rcar-gen3-common-Enable-GPT-support.patch @@ -0,0 +1,32 @@ +From 04c11b42dc2eca5858e393c80e15d72c73440fb9 Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Fri, 21 Oct 2016 01:21:55 +0300 +Subject: [PATCH] configs: rcar-gen3-common: Enable GPT support + +This enables GPT support in rcar-gen3-common.h. +It can be used for disk partitioning in U-Boot. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + include/configs/rcar-gen3-common.h | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h +index aa692e5..0fc46ab 100644 +--- a/include/configs/rcar-gen3-common.h ++++ b/include/configs/rcar-gen3-common.h +@@ -38,6 +38,11 @@ + #define CONFIG_CMD_SETEXPR + #define CONFIG_CMD_ASKENV + ++#define CONFIG_EFI_PARTITION ++#define CONFIG_PARTITION_UUIDS ++#define CONFIG_RANDOM_UUID ++#define CONFIG_CMD_GPT ++ + #define CONFIG_SYS_THUMB_BUILD + #define CONFIG_SYS_GENERIC_BOARD + +-- +1.9.3 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0013-mtd-spi-QSPI-flash-support.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0013-mtd-spi-QSPI-flash-support.patch new file mode 100644 index 0000000..a4e8a7c --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0013-mtd-spi-QSPI-flash-support.patch @@ -0,0 +1,1763 @@ +From 423d01a1b367d82a3855972483530968309cbbd4 Mon Sep 17 00:00:00 2001 +From: Daisuke Matsushita <daisuke.matsushita.ns@hitachi.com> +Date: Tue, 21 Mar 2017 15:05:15 +0900 +Subject: [PATCH] mtd: spi: Add QSPI flash + +This supports QSPI flash + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +--- + arch/arm/include/asm/arch-rcar_gen3/rcar-base.h | 1 + drivers/mtd/spi/sf.c | 15 + drivers/mtd/spi/sf_internal.h | 195 ++++++--- + drivers/mtd/spi/sf_ops.c | 64 +++ + drivers/mtd/spi/sf_params.c | 249 +++++++----- + drivers/mtd/spi/sf_probe.c | 72 +-- + drivers/spi/Makefile | 1 + drivers/spi/rcar_gen3_qspi.c | 484 ++++++++++++++++++++++++ + drivers/spi/rcar_gen3_qspi.h | 301 ++++++++++++++ + include/linux/bitops.h | 1 + include/spi.h | 22 - + 11 files changed, 1191 insertions(+), 214 deletions(-) + create mode 100644 drivers/spi/rcar_gen3_qspi.c + create mode 100644 drivers/spi/rcar_gen3_qspi.h + +diff --git a/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h b/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h +index 59d34b8..b75e4fb 100644 +--- a/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h ++++ b/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h +@@ -18,6 +18,7 @@ + #define LBSC_BASE 0xEE220200 + #define TMU_BASE 0xE61E0000 + #define GPIO5_BASE 0xE6055000 ++#define SH_QSPI_BASE 0xEE200000 + + /* SCIF */ + #define SCIF0_BASE 0xE6E60000 +diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c +index 664e860..4e27bab 100644 +--- a/drivers/mtd/spi/sf.c ++++ b/drivers/mtd/spi/sf.c +@@ -8,7 +8,11 @@ + */ + + #include <common.h> ++#if defined(CONFIG_RCAR_GEN3) ++#include "../../spi/rcar_gen3_qspi.h" ++#else + #include <spi.h> ++#endif + + static int spi_flash_read_write(struct spi_slave *spi, + const u8 *cmd, size_t cmd_len, +@@ -25,16 +29,13 @@ static int spi_flash_read_write(struct spi_slave *spi, + if (data_len == 0) + flags |= SPI_XFER_END; + +- ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); ++ ret = spi_xfer_cmd(spi, *cmd); + if (ret) { +- debug("SF: Failed to send command (%zu bytes): %d\n", +- cmd_len, ret); ++ debug("SF: Failed to send command (%zu bytes): %d\n", cmd_len, ret); + } else if (data_len != 0) { +- ret = spi_xfer(spi, data_len * 8, data_out, data_in, +- SPI_XFER_END); ++ ret = spi_xfer(spi, data_len * 8, data_out, data_in, flags|SPI_XFER_END); + if (ret) +- debug("SF: Failed to transfer %zu bytes of data: %d\n", +- data_len, ret); ++ debug("SF: Failed to transfer %zu bytes of data: %d\n", data_len, ret); + } + + return ret; +diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h +index 785f7a9..aacee1a 100644 +--- a/drivers/mtd/spi/sf_internal.h ++++ b/drivers/mtd/spi/sf_internal.h +@@ -12,6 +12,7 @@ + + #include <linux/types.h> + #include <linux/compiler.h> ++#include <spi_flash.h> + + /* Dual SPI flash memories - see SPI_COMM_DUAL_... */ + enum spi_dual_flash { +@@ -20,33 +21,6 @@ enum spi_dual_flash { + SF_DUAL_PARALLEL_FLASH = 1 << 1, + }; + +-/* Enum list - Full read commands */ +-enum spi_read_cmds { +- ARRAY_SLOW = 1 << 0, +- ARRAY_FAST = 1 << 1, +- DUAL_OUTPUT_FAST = 1 << 2, +- DUAL_IO_FAST = 1 << 3, +- QUAD_OUTPUT_FAST = 1 << 4, +- QUAD_IO_FAST = 1 << 5, +-}; +- +-/* Normal - Extended - Full command set */ +-#define RD_NORM (ARRAY_SLOW | ARRAY_FAST) +-#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST) +-#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST) +- +-/* sf param flags */ +-enum { +- SECT_4K = 1 << 0, +- SECT_32K = 1 << 1, +- E_FSR = 1 << 2, +- SST_BP = 1 << 3, +- SST_WP = 1 << 4, +- WR_QPP = 1 << 5, +-}; +- +-#define SST_WR (SST_BP | SST_WP) +- + #define SPI_FLASH_3B_ADDR_LEN 3 + #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) + #define SPI_FLASH_16MB_BOUN 0x1000000 +@@ -57,31 +31,101 @@ enum { + #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 + #define SPI_FLASH_CFI_MFR_WINBOND 0xef + +-/* Erase commands */ +-#define CMD_ERASE_4K 0x20 +-#define CMD_ERASE_32K 0x52 +-#define CMD_ERASE_CHIP 0xc7 +-#define CMD_ERASE_64K 0xd8 ++/* Read Device ID */ ++#define CMD_READ_ID 0x9f ++#define CMD_READ_SFDP 0x5a ++#define CMD_READ_QUAD_ID 0xaf + +-/* Write commands */ ++/* Register Access */ ++#define CMD_READ_STATUS 0x05 ++#define CMD_READ_STATUS2 0x07 ++#define CMD_READ_STATUS1 0x35 ++#define CMD_READ_CONFIG 0x35 ++#define CMD_READ_ANY_REG 0x65 + #define CMD_WRITE_STATUS 0x01 +-#define CMD_PAGE_PROGRAM 0x02 + #define CMD_WRITE_DISABLE 0x04 +-#define CMD_READ_STATUS 0x05 +-#define CMD_QUAD_PAGE_PROGRAM 0x32 +-#define CMD_READ_STATUS1 0x35 + #define CMD_WRITE_ENABLE 0x06 +-#define CMD_READ_CONFIG 0x35 +-#define CMD_FLAG_STATUS 0x70 ++#define CMD_WRITE_ANY_REG 0x71 ++#define CMD_CLSR 0x30 ++#define CMD_CLSR_ALT 0x82 ++#define CMD_4BYTE_ADDR_MODE 0xb7 ++#define CMD_SET_BURST_LEN 0xc0 ++#define CMD_EVALUATE_ERASE_STATUS 0xd0 ++#define CMD_ECC_READ 0x19 ++#define CMD_ECC_READ_ADDR4 0x18 ++#define CMD_DLPRD 0x41 ++#define CMD_PNVDLR 0x43 ++#define CMD_WVDLR 0x4a + + /* Read commands */ + #define CMD_READ_ARRAY_SLOW 0x03 ++#define CMD_READ_ARRAY_SLOW_ADDR4 0x13 + #define CMD_READ_ARRAY_FAST 0x0b ++#define CMD_READ_ARRAY_FAST_ADDR4 0x0c + #define CMD_READ_DUAL_OUTPUT_FAST 0x3b + #define CMD_READ_DUAL_IO_FAST 0xbb ++#define CMD_READ_DUAL_IO_FAST_ADDR4 0xbc + #define CMD_READ_QUAD_OUTPUT_FAST 0x6b + #define CMD_READ_QUAD_IO_FAST 0xeb +-#define CMD_READ_ID 0x9f ++#define CMD_READ_QUAD_IO_FAST_ADDR4 0xec ++#define CMD_READ_QUAD_IO_DDR 0xed ++#define CMD_READ_QUAD_IO_DDR_ADDR4 0xee ++ ++/* Write commands */ ++#define CMD_PAGE_PROGRAM 0x02 ++#define CMD_PAGE_PROGRAM_ADDR4 0x12 ++#define CMD_QUAD_PAGE_PROGRAM 0x32 ++#define CMD_FLAG_STATUS 0x70 ++ ++/* Erase commands */ ++#define CMD_ERASE_4K 0x20 ++#define CMD_ERASE_4K_ADDR4 0x21 ++#define CMD_ERASE_32K 0x52 ++#define CMD_ERASE_CHIP 0xc7 ++#define CMD_ERASE_64K 0xd8 ++#define CMD_ERASE_256K_ADDR4 0xdc ++#define CMD_BULK_ERASE 0x60 ++#define CMD_BULK_ERASE_ALT 0xc7 ++ ++/* Erase Program / Suspend Program */ ++#define CMD_EPS 0x75 ++#define CMD_EPS_ALT 0x85 ++#define CMD_EPS_ALT2 0xb0 ++#define CMD_EPR 0x7a ++#define CMD_EPR_ALT 0x8a ++#define CMD_EPR_ALT2 0x30 ++ ++/* One Time Program Array */ ++#define CMD_OTP_PROGRAM 0x42 ++#define CMD_OTP_READ 0x4b ++ ++/* Advanced Sector Protection */ ++#define CMD_DYB_READ 0xfa ++#define CMD_DYB_READ_ADDR4 0xe0 ++#define CMD_DYB_WRITE 0xfb ++#define CMD_DYB_WRITE_ADDR4 0xe1 ++#define CMD_PPB_READ 0xfc ++#define CMD_PPB_READ_ADDR4 0xe2 ++#define CMD_PPB_PROGRAM 0xfd ++#define CMD_PPB_PROGRAM_ADDR4 0xe3 ++#define CMD_PPB_ERASE 0xe4 ++#define CMD_ASP_READ 0x2b ++#define CMD_ASP_PROGRAM 0x2f ++#define CMD_PPB_LOCKBIT_READ 0xa7 ++#define CMD_PPB_LOCKBIT_WRITE 0xa6 ++#define CMD_PASSWD_READ 0xe7 ++#define CMD_PASSWD_PROGRAM 0xe8 ++#define CMD_PASSWD_UNLOCK 0xe9 ++ ++/* Reset */ ++#define CMD_SOFT_RESET_ENABLE 0x66 ++#define CMD_SOFT_RESET 0x99 ++#define CMD_LEGACY_SOFT_RESET 0xf0 ++#define CMD_MODE_BIT_RESET 0xff ++ ++/* DPD */ ++#define CMD_ENT_DEEP_POWER_DOWN 0xb9 ++#define CMD_REL_DEEP_POWER_DOWN 0xab + + /* Bank addr access commands */ + #ifdef CONFIG_SPI_FLASH_BAR +@@ -94,13 +138,22 @@ enum { + /* Common status */ + #define STATUS_WIP (1 << 0) + #define STATUS_QEB_WINSPAN (1 << 1) +-#define STATUS_QEB_MXIC (1 << 6) ++#define STATUS_QEB_MXIC (1 << 6) + #define STATUS_PEC (1 << 7) + + #ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN + #define STATUS_SRWD (1 << 7) /* SR write protect */ + #endif + ++/* Status Register 1(SR1V) */ ++#define SR1V_WEL (1 << 1) ++#define SR1V_WIP (1 << 0) ++ ++/* Status Register 2(SR2V) */ ++#define SR2V_ESTAT (1 << 2) ++#define SR2V_ES (1 << 1) ++#define SR2V_PS (1 << 0) ++ + /* Flash timeout values */ + #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) + #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) +@@ -117,25 +170,43 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, + const void *buf); + #endif + +-/** +- * struct spi_flash_params - SPI/QSPI flash device params structure +- * +- * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) +- * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id]) +- * @ext_jedec: Device ext_jedec ID +- * @sector_size: Sector size of this device +- * @nr_sectors: No.of sectors on this device +- * @e_rd_cmd: Enum list for read commands +- * @flags: Important param, for flash specific behaviour +- */ ++#define JEDEC_MFR(info) ((info)->id[0]) ++#define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2])) ++#define JEDEC_EXT(info) (((info)->id[3]) << 8 | ((info)->id[4])) ++#define JEDEC_FID(info) ((info)->id[5]) ++#define SPI_FLASH_MAX_ID_LEN 6 ++ + struct spi_flash_params { +- const char *name; +- u32 jedec; +- u16 ext_jedec; +- u32 sector_size; +- u32 nr_sectors; +- u8 e_rd_cmd; +- u16 flags; ++ /* Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) */ ++ const char *name; ++ ++ /* ++ * This array stores the ID bytes. ++ * The first three bytes are the JEDIC ID. ++ * JEDEC ID zero means "no ID" (mostly older chips). ++ */ ++ u8 id[SPI_FLASH_MAX_ID_LEN]; ++ u8 id_len; ++ ++ /* ++ * The size listed here is what works with SPINOR_OP_SE, which isn't ++ * necessarily called a "sector" by the vendor. ++ */ ++ u32 sector_size; ++ u32 n_sectors; ++ ++ u16 page_size; ++ ++ u16 flags; ++#define SECT_4K BIT(0) /* CMD_ERASE_4K works uniformly */ ++#define E_FSR BIT(1) /* use flag status register for */ ++#define SST_WR BIT(2) /* use SST byte/word programming */ ++#define WR_QPP BIT(3) /* use Quad Page Program */ ++#define RD_QUAD BIT(4) /* use Quad Read */ ++#define RD_DUAL BIT(5) /* use Dual Read */ ++#define RD_QUADIO BIT(6) /* use Quad IO Read */ ++#define RD_DUALIO BIT(7) /* use Dual IO Read */ ++#define RD_FULL (RD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO) + }; + + extern const struct spi_flash_params spi_flash_params_table[]; +@@ -164,6 +235,12 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); + /* Read the status register */ + int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs); + ++/* Read the status register2 */ ++int spi_flash_cmd_read_status2(struct spi_flash *flash, u8 *rs); ++ ++/* Evaluate Erase Status */ ++int spi_flash_cmd_evaluate_erase_status(struct spi_flash *flash, u32 addr); ++ + /* Program the status register */ + int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws); + +diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c +index 34bc54e..6af38c1 100644 +--- a/drivers/mtd/spi/sf_ops.c ++++ b/drivers/mtd/spi/sf_ops.c +@@ -11,7 +11,11 @@ + #include <common.h> + #include <errno.h> + #include <malloc.h> ++#if defined(CONFIG_RCAR_GEN3) ++#include "../../spi/rcar_gen3_qspi.h" ++#else + #include <spi.h> ++#endif + #include <spi_flash.h> + #include <watchdog.h> + +@@ -40,6 +44,38 @@ int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs) + return 0; + } + ++int spi_flash_cmd_read_status2(struct spi_flash *flash, u8 *rs) ++{ ++ int ret; ++ u8 cmd; ++ ++ cmd = CMD_READ_STATUS2; ++ ret = spi_flash_read_common(flash, &cmd, 1, rs, 1); ++ if (ret < 0) { ++ debug("SF: fail to read status register2\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++int spi_flash_cmd_evaluate_erase_status(struct spi_flash *flash, u32 addr) ++{ ++ int ret; ++ u8 cmd; ++ ++ cmd = CMD_EVALUATE_ERASE_STATUS; ++ spi_set_addr(addr & 0x00ffffff); ++ ++ ret = spi_xfer_cmd(flash->spi, (int)cmd); ++ if (ret < 0) { ++ debug("SF: fail to Evaluate Erase Status\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ + int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws) + { + u8 cmd; +@@ -158,7 +194,10 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) + { + struct spi_slave *spi = flash->spi; + unsigned long timebase; ++#ifdef CONFIG_SF_DUAL_FLASH + unsigned long flags = SPI_XFER_BEGIN; ++#endif ++ + int ret; + u8 status; + u8 check_status = 0x0; +@@ -174,7 +213,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) + if (spi->flags & SPI_XFER_U_PAGE) + flags |= SPI_XFER_U_PAGE; + #endif +- ret = spi_xfer(spi, 8, &cmd, NULL, flags); ++ ret = spi_xfer_cmd(spi, cmd); + if (ret) { + debug("SF: fail to read %s status register\n", + cmd == CMD_READ_STATUS ? "read" : "flag"); +@@ -250,6 +289,8 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) + u32 erase_size, erase_addr; + u8 cmd[SPI_FLASH_CMD_LEN]; + int ret = -1; ++ u8 read_sts; ++ int wait_msec, wait_interval; + + erase_size = flash->erase_size; + if (offset % erase_size || len % erase_size) { +@@ -270,6 +311,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) + if (ret < 0) + return ret; + #endif ++ spi_set_addr(erase_addr); + spi_flash_addr(erase_addr, cmd); + + debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], +@@ -285,6 +327,24 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) + len -= erase_size; + } + ++ /* Wait for Erase Complete */ ++ wait_msec = 0; ++ wait_interval = 100; ++ while (wait_msec < 3000) { /* Max 3sec */ ++ mdelay(wait_interval); ++ ret = spi_flash_cmd_evaluate_erase_status(flash, offset-erase_size); ++ WaitReadyDevice(flash->spi); ++ ret = spi_flash_cmd_read_status2(flash, &read_sts); ++ if (read_sts & SR2V_ESTAT) { ++ break; ++ } ++ wait_msec += wait_interval; ++ } ++ ++ if ((ret != 0) || (read_sts != SR2V_ESTAT)) { ++ ret = -1; ++ } ++ + return ret; + } + +@@ -319,6 +379,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, + chunk_len = min(chunk_len, + (size_t)flash->spi->max_write_size); + ++ spi_set_addr(write_addr); + spi_flash_addr(write_addr, cmd); + + debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", +@@ -409,6 +470,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, + else + read_len = remain_len; + ++ spi_set_addr(read_addr); + spi_flash_addr(read_addr, cmd); + + ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); +diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c +index c12e8c6..bd19bfb 100644 +--- a/drivers/mtd/spi/sf_params.c ++++ b/drivers/mtd/spi/sf_params.c +@@ -12,129 +12,172 @@ + + #include "sf_internal.h" + +-/* SPI/QSPI flash device params structure */ ++/* Used when the "_ext_id" is two bytes at most */ ++#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ ++ .id = { \ ++ ((_jedec_id) >> 16) & 0xff, \ ++ ((_jedec_id) >> 8) & 0xff, \ ++ (_jedec_id) & 0xff, \ ++ ((_ext_id) >> 8) & 0xff, \ ++ (_ext_id) & 0xff, \ ++ }, \ ++ .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ ++ .sector_size = (_sector_size), \ ++ .n_sectors = (_n_sectors), \ ++ .page_size = 256, \ ++ .flags = (_flags), ++ ++#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ ++ .id = { \ ++ ((_jedec_id) >> 16) & 0xff, \ ++ ((_jedec_id) >> 8) & 0xff, \ ++ (_jedec_id) & 0xff, \ ++ ((_ext_id) >> 16) & 0xff, \ ++ ((_ext_id) >> 8) & 0xff, \ ++ (_ext_id) & 0xff, \ ++ }, \ ++ .id_len = 6, \ ++ .sector_size = (_sector_size), \ ++ .n_sectors = (_n_sectors), \ ++ .page_size = 256, \ ++ .flags = (_flags), ++ + const struct spi_flash_params spi_flash_params_table[] = { + #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ +- {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K}, +- {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, +- {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, +- {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K}, +- {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K}, +- {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, +- {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, +- {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, ++ {"at45db011d", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) }, ++ {"at45db021d", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) }, ++ {"at45db041d", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) }, ++ {"at45db081d", INFO(0x1f2500, 0x0, 64 * 1024, 16, SECT_4K) }, ++ {"at45db161d", INFO(0x1f2600, 0x0, 64 * 1024, 32, SECT_4K) }, ++ {"at45db321d", INFO(0x1f2700, 0x0, 64 * 1024, 64, SECT_4K) }, ++ {"at45db641d", INFO(0x1f2800, 0x0, 64 * 1024, 128, SECT_4K) }, ++ {"at25df321a", INFO(0x1f4701, 0x0, 64 * 1024, 64, SECT_4K) }, ++ {"at25df321", INFO(0x1f4700, 0x0, 64 * 1024, 64, SECT_4K) }, ++ {"at26df081a", INFO(0x1f4501, 0x0, 64 * 1024, 16, SECT_4K) }, + #endif + #ifdef CONFIG_SPI_FLASH_EON /* EON */ +- {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, RD_NORM, 0}, +- {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, +- {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, RD_NORM, 0}, +- {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, RD_NORM, 0}, ++ {"en25q32b", INFO(0x1c3016, 0x0, 64 * 1024, 64, 0) }, ++ {"en25q64", INFO(0x1c3017, 0x0, 64 * 1024, 128, SECT_4K) }, ++ {"en25q128b", INFO(0x1c3018, 0x0, 64 * 1024, 256, 0) }, ++ {"en25s64", INFO(0x1c3817, 0x0, 64 * 1024, 128, 0) }, + #endif + #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ +- {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, +- {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, ++ {"gd25q64b", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) }, ++ {"gd25lq32", INFO(0xc86016, 0x0, 64 * 1024, 64, SECT_4K) }, ++#endif ++#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ ++ {"is25lp032", INFO(0x9d6016, 0x0, 64 * 1024, 64, 0) }, ++ {"is25lp064", INFO(0x9d6017, 0x0, 64 * 1024, 128, 0) }, ++ {"is25lp128", INFO(0x9d6018, 0x0, 64 * 1024, 256, 0) }, + #endif + #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ +- {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0}, +- {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, RD_NORM, 0}, +- {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, RD_NORM, 0}, +- {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, RD_NORM, 0}, +- {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, RD_NORM, 0}, +- {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, RD_NORM, 0}, +- {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, +- {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP}, +- {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP}, +- {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, ++ {"mx25l2006e", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) }, ++ {"mx25l4005", INFO(0xc22013, 0x0, 64 * 1024, 8, 0) }, ++ {"mx25l8005", INFO(0xc22014, 0x0, 64 * 1024, 16, 0) }, ++ {"mx25l1605d", INFO(0xc22015, 0x0, 64 * 1024, 32, 0) }, ++ {"mx25l3205d", INFO(0xc22016, 0x0, 64 * 1024, 64, 0) }, ++ {"mx25l6405d", INFO(0xc22017, 0x0, 64 * 1024, 128, 0) }, ++ {"mx25l12805", INFO(0xc22018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, ++ {"mx25l25635f", INFO(0xc22019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, ++ {"mx25l51235f", INFO(0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, ++ {"mx25l12855e", INFO(0xc22618, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, ++ {"mx66u51235f", INFO(0xc2253a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, ++ {"mx66l1g45g", INFO(0xc2201b, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP) }, + #endif + #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ +- {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, RD_NORM, 0}, +- {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, RD_NORM, 0}, +- {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, RD_NORM, 0}, +- {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, RD_NORM, 0}, +- {"S25FL116K", 0x014015, 0x0, 64 * 1024, 128, RD_NORM, 0}, +- {"S25FL164K", 0x014017, 0x0140, 64 * 1024, 128, RD_NORM, 0}, +- {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP}, +- {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP}, +- {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP}, +- {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP}, +- {"S25FL128S_256K", 0x012018, 0x4d00, 256 * 1024, 64, RD_FULL, WR_QPP}, +- {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP}, +- {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP}, +- {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP}, +- {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP}, +- {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP}, +- {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP}, ++ {"s25fl008a", INFO(0x010213, 0x0, 64 * 1024, 16, 0) }, ++ {"s25fl016a", INFO(0x010214, 0x0, 64 * 1024, 32, 0) }, ++ {"s25fl032a", INFO(0x010215, 0x0, 64 * 1024, 64, 0) }, ++ {"s25fl064a", INFO(0x010216, 0x0, 64 * 1024, 128, 0) }, ++ {"s25fl116k", INFO(0x014015, 0x0, 64 * 1024, 128, 0) }, ++ {"s25fl164k", INFO(0x014017, 0x0140, 64 * 1024, 128, 0) }, ++ {"s25fl128p_256k", INFO(0x012018, 0x0300, 256 * 1024, 64, RD_FULL | WR_QPP) }, ++ {"s25fl128p_64k", INFO(0x012018, 0x0301, 64 * 1024, 256, RD_FULL | WR_QPP) }, ++ {"s25fl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, RD_FULL | WR_QPP) }, ++ {"s25fl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, RD_FULL | WR_QPP) }, ++ {"s25fl128s_256k", INFO(0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP) }, ++ {"s25fl128s_64k", INFO(0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP) }, ++ {"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP) }, ++ {"s25fl256s_64k", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) }, ++ {"s25fs256s_64k", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, ++ {"s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 2048, RD_FULL | WR_QPP | SECT_4K) }, ++ {"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP) }, ++ {"s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP) }, ++ {"s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, RD_FULL | WR_QPP) }, + #endif + #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ +- {"M25P10", 0x202011, 0x0, 32 * 1024, 4, RD_NORM, 0}, +- {"M25P20", 0x202012, 0x0, 64 * 1024, 4, RD_NORM, 0}, +- {"M25P40", 0x202013, 0x0, 64 * 1024, 8, RD_NORM, 0}, +- {"M25P80", 0x202014, 0x0, 64 * 1024, 16, RD_NORM, 0}, +- {"M25P16", 0x202015, 0x0, 64 * 1024, 32, RD_NORM, 0}, +- {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, RD_NORM, 0}, +- {"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_EXTN, 0}, +- {"M25P32", 0x202016, 0x0, 64 * 1024, 64, RD_NORM, 0}, +- {"M25P64", 0x202017, 0x0, 64 * 1024, 128, RD_NORM, 0}, +- {"M25P128", 0x202018, 0x0, 256 * 1024, 64, RD_NORM, 0}, +- {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, +- {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, +- {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, +- {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, +- {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, +- {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, +- {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, +- {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, +- {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, +- {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, +- {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, +- {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, +- {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, ++ {"m25p10", INFO(0x202011, 0x0, 32 * 1024, 4, 0) }, ++ {"m25p20", INFO(0x202012, 0x0, 64 * 1024, 4, 0) }, ++ {"m25p40", INFO(0x202013, 0x0, 64 * 1024, 8, 0) }, ++ {"m25p80", INFO(0x202014, 0x0, 64 * 1024, 16, 0) }, ++ {"m25p16", INFO(0x202015, 0x0, 64 * 1024, 32, 0) }, ++ {"m25pE16", INFO(0x208015, 0x1000, 64 * 1024, 32, 0) }, ++ {"m25pX16", INFO(0x207115, 0x1000, 64 * 1024, 32, RD_QUAD | RD_DUAL) }, ++ {"m25p32", INFO(0x202016, 0x0, 64 * 1024, 64, 0) }, ++ {"m25p64", INFO(0x202017, 0x0, 64 * 1024, 128, 0) }, ++ {"m25p128", INFO(0x202018, 0x0, 256 * 1024, 64, 0) }, ++ {"m25pX64", INFO(0x207117, 0x0, 64 * 1024, 128, SECT_4K) }, ++ {"n25q016a", INFO(0x20bb15, 0x0, 64 * 1024, 32, SECT_4K) }, ++ {"n25q32", INFO(0x20ba16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, ++ {"n25q32a", INFO(0x20bb16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, ++ {"n25q64", INFO(0x20ba17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, ++ {"n25q64a", INFO(0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, ++ {"n25q128", INFO(0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, ++ {"n25q128a", INFO(0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, ++ {"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, ++ {"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, ++ {"n25q512", INFO(0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, ++ {"n25q512a", INFO(0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, ++ {"n25q1024", INFO(0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, ++ {"n25q1024a", INFO(0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, ++ {"mt25qu02g", INFO(0x20bb22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, ++ {"mt25ql02g", INFO(0x20ba22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + #endif + #ifdef CONFIG_SPI_FLASH_SST /* SST */ +- {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR}, +- {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR}, +- {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K | SST_WR}, +- {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K | SST_WR}, +- {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, +- {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM, SECT_4K | SST_WR}, +- {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WR}, +- {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WR}, +- {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR}, +- {"SST25WF040B", 0x621613, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR}, +- {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR}, ++ {"sst25vf040b", INFO(0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, ++ {"sst25vf080b", INFO(0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) }, ++ {"sst25vf016b", INFO(0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WR) }, ++ {"sst25vf032b", INFO(0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WR) }, ++ {"sst25vf064c", INFO(0xbf254b, 0x0, 64 * 1024, 128, SECT_4K) }, ++ {"sst25wf512", INFO(0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WR) }, ++ {"sst25wf010", INFO(0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WR) }, ++ {"sst25wf020", INFO(0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WR) }, ++ {"sst25wf040", INFO(0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, ++ {"sst25wf040b", INFO(0x621613, 0x0, 64 * 1024, 8, SECT_4K) }, ++ {"sst25wf080", INFO(0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) }, + #endif + #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ +- {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, RD_NORM, 0}, +- {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, RD_NORM, 0}, +- {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, RD_NORM, 0}, +- {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, +- {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K}, +- {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, +- {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, +- {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, +- {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, +- {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, +- {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, +- {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, +- {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, +- {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, +- {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, +- {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, +- {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, +- {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, ++ {"w25p80", INFO(0xef2014, 0x0, 64 * 1024, 16, 0) }, ++ {"w25p16", INFO(0xef2015, 0x0, 64 * 1024, 32, 0) }, ++ {"w25p32", INFO(0xef2016, 0x0, 64 * 1024, 64, 0) }, ++ {"w25x40", INFO(0xef3013, 0x0, 64 * 1024, 8, SECT_4K) }, ++ {"w25x16", INFO(0xef3015, 0x0, 64 * 1024, 32, SECT_4K) }, ++ {"w25x32", INFO(0xef3016, 0x0, 64 * 1024, 64, SECT_4K) }, ++ {"w25x64", INFO(0xef3017, 0x0, 64 * 1024, 128, SECT_4K) }, ++ {"w25q80bl", INFO(0xef4014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) }, ++ {"w25q16cl", INFO(0xef4015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, ++ {"w25q32bv", INFO(0xef4016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, ++ {"w25q64cv", INFO(0xef4017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, ++ {"w25q128bv", INFO(0xef4018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, ++ {"w25q256", INFO(0xef4019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, ++ {"w25q80bw", INFO(0xef5014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) }, ++ {"w25q16dw", INFO(0xef6015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, ++ {"w25q32dw", INFO(0xef6016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, ++ {"w25q64dw", INFO(0xef6017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, ++ {"w25q128fw", INFO(0xef6018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, + #endif + {}, /* Empty entry to terminate the list */ + /* + * Note: + * Below paired flash devices has similar spi_flash params. +- * (S25FL129P_64K, S25FL128S_64K) +- * (W25Q80BL, W25Q80BV) +- * (W25Q16CL, W25Q16DV) +- * (W25Q32BV, W25Q32FV_SPI) +- * (W25Q64CV, W25Q64FV_SPI) +- * (W25Q128BV, W25Q128FV_SPI) +- * (W25Q32DW, W25Q32FV_QPI) +- * (W25Q64DW, W25Q64FV_QPI) +- * (W25Q128FW, W25Q128FV_QPI) ++ * (s25fl129p_64k, s25fl128s_64k) ++ * (w25q80bl, w25q80bv) ++ * (w25q16cl, w25q16dv) ++ * (w25q32bv, w25q32fv_spi) ++ * (w25q64cv, w25q64fv_spi) ++ * (w25q128bv, w25q128fv_spi) ++ * (w25q32dw, w25q32fv_qpi) ++ * (w25q64dw, w25q64fv_qpi) ++ * (w25q128fw, w25q128fv_qpi) + */ + }; +diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c +index 4103723..28ef787 100644 +--- a/drivers/mtd/spi/sf_probe.c ++++ b/drivers/mtd/spi/sf_probe.c +@@ -21,16 +21,6 @@ + + DECLARE_GLOBAL_DATA_PTR; + +-/* Read commands array */ +-static u8 spi_read_cmds_array[] = { +- CMD_READ_ARRAY_SLOW, +- CMD_READ_ARRAY_FAST, +- CMD_READ_DUAL_OUTPUT_FAST, +- CMD_READ_DUAL_IO_FAST, +- CMD_READ_QUAD_OUTPUT_FAST, +- CMD_READ_QUAD_IO_FAST, +-}; +- + #ifdef CONFIG_SPI_FLASH_MACRONIX + static int spi_flash_set_qeb_mxic(struct spi_flash *flash) + { +@@ -102,19 +92,27 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode, + struct spi_flash *flash) + { + const struct spi_flash_params *params; +- u8 cmd; ++ u8 manufacture_id = idcode[0]; + u16 jedec = idcode[1] << 8 | idcode[2]; + u16 ext_jedec = idcode[3] << 8 | idcode[4]; ++ u8 family_id = idcode[5]; + + /* Validate params from spi_flash_params table */ + params = spi_flash_params_table; + for (; params->name != NULL; params++) { +- if ((params->jedec >> 16) == idcode[0]) { +- if ((params->jedec & 0xFFFF) == jedec) { +- if (params->ext_jedec == 0) +- break; +- else if (params->ext_jedec == ext_jedec) ++ if (JEDEC_MFR(params) == manufacture_id) { ++ if (JEDEC_ID(params) == jedec) { ++ if (params->id_len - 3 == 0) { + break; ++ } else if (params->id_len - 3 == 2) { ++ if (JEDEC_EXT(params) == ext_jedec) { ++ break; ++ } ++ } else { ++ if ((JEDEC_EXT(params) == (ext_jedec & 0xFF00)) && (JEDEC_FID(params) == family_id)) { ++ break; ++ } ++ } + } + } + } +@@ -149,48 +147,48 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode, + + /* Compute the flash size */ + flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; ++ flash->page_size = params->page_size; + /* + * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the + * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with + * the 0x4d00 Extended JEDEC code have 512b pages. All of the others + * have 256b pages. + */ +- if (ext_jedec == 0x4d00) { +- if ((jedec == 0x0215) || (jedec == 0x216)) +- flash->page_size = 256; +- else ++ if ((ext_jedec & 0xFF00) == 0x4d00) { ++ if ((jedec != 0x0215) && (jedec != 0x0216) && (jedec != 0x220)) { + flash->page_size = 512; +- } else { +- flash->page_size = 256; ++ } + } ++ + flash->page_size <<= flash->shift; + flash->sector_size = params->sector_size << flash->shift; +- flash->size = flash->sector_size * params->nr_sectors << flash->shift; ++ flash->size = flash->sector_size * params->n_sectors << flash->shift; + #ifdef CONFIG_SF_DUAL_FLASH + if (flash->dual_flash & SF_DUAL_STACKED_FLASH) + flash->size <<= 1; + #endif + ++#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS + /* Compute erase sector and command */ + if (params->flags & SECT_4K) { + flash->erase_cmd = CMD_ERASE_4K; + flash->erase_size = 4096 << flash->shift; +- } else if (params->flags & SECT_32K) { +- flash->erase_cmd = CMD_ERASE_32K; +- flash->erase_size = 32768 << flash->shift; +- } else { +- flash->erase_cmd = CMD_ERASE_64K; ++ } else ++#endif ++ { ++ flash->erase_cmd = CMD_ERASE_256K_ADDR4; + flash->erase_size = flash->sector_size; + } + + /* Look for the fastest read cmd */ +- cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx); +- if (cmd) { +- cmd = spi_read_cmds_array[cmd - 1]; +- flash->read_cmd = cmd; ++ if (flash->spi->op_mode_rx & SPI_RX_SLOW) { ++ flash->read_cmd = CMD_READ_ARRAY_SLOW; ++ } else if ((flash->spi->op_mode_rx & SPI_RX_QUAD) && (params->flags & RD_QUAD)) { ++ flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST; ++ } else if ((flash->spi->op_mode_rx & SPI_RX_DUAL) && (params->flags & RD_DUAL)) { ++ flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST; + } else { +- /* Go for default supported read cmd */ +- flash->read_cmd = CMD_READ_ARRAY_FAST; ++ flash->read_cmd = CMD_READ_ARRAY_FAST_ADDR4; + } + + /* Not require to look for fastest only two write cmds yet */ +@@ -198,7 +196,7 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode, + flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; + else + /* Go for default supported write cmd */ +- flash->write_cmd = CMD_PAGE_PROGRAM; ++ flash->write_cmd = CMD_PAGE_PROGRAM_ADDR4; + + /* Read dummy_byte: dummy byte is determined based on the + * dummy cycles of a particular command. +@@ -324,7 +322,7 @@ static int spi_enable_wp_pin(struct spi_flash *flash) + */ + int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash) + { +- u8 idcode[5]; ++ u8 idcode[SPI_FLASH_MAX_ID_LEN]; + int ret; + + /* Setup spi_slave */ +@@ -385,6 +383,7 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash) + puts("\n"); + #endif + #ifndef CONFIG_SPI_FLASH_BAR ++#ifndef CONFIG_R8A7797 + if (((flash->dual_flash == SF_SINGLE_FLASH) && + (flash->size > SPI_FLASH_16MB_BOUN)) || + ((flash->dual_flash > SF_SINGLE_FLASH) && +@@ -393,6 +392,7 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash) + puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); + } + #endif ++#endif + if (spi_enable_wp_pin(flash)) + puts("Enable WP pin failed\n"); + +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index ce6f1cc..fd1dd7c 100644 +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -39,6 +39,7 @@ obj-$(CONFIG_MXC_SPI) += mxc_spi.o + obj-$(CONFIG_MXS_SPI) += mxs_spi.o + obj-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o + obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o ++obj-$(CONFIG_RCAR_GEN3_QSPI) += rcar_gen3_qspi.o + obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o + obj-$(CONFIG_SH_SPI) += sh_spi.o + obj-$(CONFIG_SH_QSPI) += sh_qspi.o +diff --git a/drivers/spi/rcar_gen3_qspi.c b/drivers/spi/rcar_gen3_qspi.c +new file mode 100644 +index 0000000..5095b07 +--- /dev/null ++++ b/drivers/spi/rcar_gen3_qspi.c +@@ -0,0 +1,485 @@ ++/* ++ * R-CarH3 QSPI (Quad SPI) driver ++ * ++ */ ++ ++#include <common.h> ++#include <malloc.h> ++#include "rcar_gen3_qspi.h" ++#include <asm/arch/rcar_gen3.h> ++#include <asm/arch/rpc-flash.h> ++#include <asm/io.h> ++ ++#include "../mtd/spi/sf_internal.h" ++ ++/* if DEBUG_PRINT defined, Output debug log */ ++//#define DEBUG_PRINT ++#ifdef DEBUG_PRINT ++#define debug_print(format, arg...) printf("[DBG] " format, ## arg) ++#else ++#define debug_print(format, arg...) do {} while(0) ++#endif ++ ++struct rcar_gen3_qspi_regs { ++ unsigned int cmncr; ++ unsigned int ssldr; ++ unsigned int dummy0; ++ unsigned int drcr; ++ unsigned int drcmr; ++ unsigned int drear; ++ unsigned int dropr; ++ unsigned int drenr; ++ unsigned int smcr; ++ unsigned int smcmr; ++ unsigned int smadr; ++ unsigned int smopr; ++ unsigned int smenr; ++ unsigned int dummy1; ++ unsigned int smrdr0; ++ unsigned int smrdr1; ++ unsigned int smwdr0; ++ unsigned int smwdr1; ++ unsigned int cmnsr; ++ unsigned int dummy2[3]; ++ unsigned int drdmcr; ++ unsigned int drdrenr; ++ unsigned int smdmcr; ++ unsigned int smdrenr; ++ unsigned int dummy3[5]; ++ unsigned int phycnt; ++ unsigned int phyoffset1; ++ unsigned int phyoffset2; ++ unsigned int phyint; ++ unsigned int dummy4[7]; ++ unsigned int div_reg; ++}; ++ ++struct sh_qspi_slave { ++ struct spi_slave slave; ++ struct rcar_gen3_qspi_regs *regs; ++}; ++ ++const SPI_COMMAND spi_cmd_tbl[] = { ++ { CMD_READ_ID, SPI_CMD_READ, SPI_DATA_ENABLE, 0, 0, "Read ID (JEDEC Manufacturer ID and JEDEC CFI)" }, ++ { CMD_READ_SFDP, SPI_CMD_READ, SPI_DATA_ENABLE, 3, 8, "Read JEDEC Serial Flash Discoverable Parameters" }, ++ { CMD_READ_QUAD_ID, SPI_CMD_READ, SPI_DATA_ENABLE, 0, 0, "Read Quad ID" }, ++ { CMD_READ_STATUS, SPI_CMD_READ, SPI_DATA_ENABLE, 0, 0, "Read Status Register-1" }, ++ { CMD_READ_STATUS2, SPI_CMD_READ, SPI_DATA_ENABLE, 0, 0, "Read Status Register-2" }, ++ { CMD_READ_CONFIG, SPI_CMD_READ, SPI_DATA_ENABLE, 0, 0, "Read Configuration Register-1" }, ++ { CMD_READ_ANY_REG, SPI_CMD_READ, SPI_DATA_ENABLE, 3, 8, "Read Any Register" }, ++ { CMD_WRITE_STATUS, SPI_CMD_WRITE, SPI_DATA_ENABLE, 0, 0, "Write Register (Status-1, Configuration-1)" }, ++ { CMD_WRITE_DISABLE, SPI_CMD_OTHER, SPI_DATA_DISABLE, 0, 0, "Write Disable" }, ++ { CMD_WRITE_ENABLE, SPI_CMD_OTHER, SPI_DATA_DISABLE, 0, 0, "Write Enable" }, ++ { CMD_WRITE_ANY_REG, SPI_CMD_WRITE, SPI_DATA_ENABLE, 3, 0, "Write Any Register" }, ++ { CMD_CLSR, SPI_CMD_OTHER, SPI_DATA_DISABLE, 0, 0, "Clear Status Register-1 - Erase/Prog. Fail Reset" }, ++ { CMD_CLSR_ALT, SPI_CMD_OTHER, SPI_DATA_DISABLE, 0, 0, "Clear Status Register-1 - Erase/Prog. Fail Reset" }, ++ { CMD_4BYTE_ADDR_MODE, SPI_CMD_OTHER, SPI_DATA_DISABLE, 0, 0, "Enter 4-byte Address Mode" }, ++ { CMD_SET_BURST_LEN, SPI_CMD_WRITE, SPI_DATA_ENABLE, 0, 0, "Set Burst Length" }, ++ { CMD_EVALUATE_ERASE_STATUS, SPI_CMD_OTHER, SPI_DATA_DISABLE, 3, 0, "Evaluate Erase Status" }, ++ { CMD_ECC_READ, SPI_CMD_READ, SPI_DATA_ENABLE, 3, 8, "ECC Read (3- or 4-byte address)" }, ++ { CMD_ECC_READ_ADDR4, SPI_CMD_READ, SPI_DATA_ENABLE, 4, 8, "ECC Read (4-byte address)" }, ++ { CMD_DLPRD, SPI_CMD_READ, SPI_DATA_ENABLE, 0, 0, "Data Learning Pattern Read" }, ++ { CMD_PNVDLR, SPI_CMD_WRITE, SPI_DATA_ENABLE, 0, 0, "Program NV Data Learning Register" }, ++ { CMD_WVDLR, SPI_CMD_WRITE, SPI_DATA_ENABLE, 0, 0, "Write Volatile Data Learning Register" }, ++ { CMD_READ_ARRAY_SLOW, SPI_CMD_READ, SPI_DATA_ENABLE, 3, 0, "Read (3- or 4-byte address)" }, ++ { CMD_READ_ARRAY_SLOW_ADDR4, SPI_CMD_READ, SPI_DATA_ENABLE, 4, 0, "Read (4-byte address)" }, ++ { CMD_READ_ARRAY_FAST, SPI_CMD_READ, SPI_DATA_ENABLE, 3, 8, "Fast Read (3- or 4-byte address)" }, ++ { CMD_READ_ARRAY_FAST_ADDR4, SPI_CMD_READ, SPI_DATA_ENABLE, 4, 8, "Fast Read (4-byte address)" }, ++ { CMD_READ_DUAL_IO_FAST, SPI_CMD_READ, SPI_DATA_ENABLE, 3, 8, "Dual I/O Read (3- or 4-byte address)" }, ++ { CMD_READ_DUAL_IO_FAST_ADDR4, SPI_CMD_READ, SPI_DATA_ENABLE, 4, 8, "Dual I/O Read (4-byte address)" }, ++ { CMD_READ_QUAD_IO_FAST, SPI_CMD_READ, SPI_DATA_ENABLE, 3, 8, "Quad I/O Read (3- or 4-byte address)" }, ++ { CMD_READ_QUAD_IO_FAST_ADDR4, SPI_CMD_READ, SPI_DATA_ENABLE, 4, 8, "Quad I/O Read (4-byte address)" }, ++ { CMD_READ_QUAD_IO_DDR, SPI_CMD_READ, SPI_DATA_ENABLE, 3, 8, "DDR Quad I/O Read (3- or 4-byte address)" }, ++ { CMD_READ_QUAD_IO_DDR_ADDR4, SPI_CMD_READ, SPI_DATA_ENABLE, 4, 8, "DDR Quad I/O Read (4-byte address)" }, ++ { CMD_PAGE_PROGRAM, SPI_CMD_WRITE, SPI_DATA_ENABLE, 3, 0, "Page Program (3- or 4-byte address)" }, ++ { CMD_PAGE_PROGRAM_ADDR4, SPI_CMD_WRITE, SPI_DATA_ENABLE, 4, 0, "Page Program (4-byte address)" }, ++ { CMD_ERASE_4K, SPI_CMD_ERASE, SPI_DATA_DISABLE, 3, 0, "Parameter 4 kB-sector Erase (3- or 4-byte address)" }, ++ { CMD_ERASE_4K_ADDR4, SPI_CMD_ERASE, SPI_DATA_DISABLE, 4, 0, "Parameter 4 kB-sector Erase (4-byte address)" }, ++ { CMD_ERASE_64K, SPI_CMD_ERASE, SPI_DATA_DISABLE, 3, 0, "Erase 256 kB (3- or 4-byte address)" }, ++ { CMD_ERASE_256K_ADDR4, SPI_CMD_ERASE, SPI_DATA_DISABLE, 4, 0, "Erase 256 kB (4-byte address)" }, ++ { CMD_BULK_ERASE, SPI_CMD_ERASE, SPI_DATA_DISABLE, 0, 0, "Bulk Erase" }, ++ { CMD_BULK_ERASE_ALT, SPI_CMD_ERASE, SPI_DATA_DISABLE, 0, 0, "Bulk Erase (alternate command)" }, ++ { CMD_EPS, SPI_CMD_ERASE, SPI_DATA_DISABLE, 0, 0, "Erase / Program Suspend" }, ++ { CMD_EPS_ALT, SPI_CMD_ERASE, SPI_DATA_DISABLE, 0, 0, "Erase / Program Suspend" }, ++ { CMD_EPS_ALT2, SPI_CMD_ERASE, SPI_DATA_DISABLE, 0, 0, "Erase / Program Suspend" }, ++ { CMD_EPR, SPI_CMD_ERASE, SPI_DATA_DISABLE, 0, 0, "Erase / Program Resume" }, ++ { CMD_EPR_ALT, SPI_CMD_ERASE, SPI_DATA_DISABLE, 0, 0, "Erase / Program Resume" }, ++ { CMD_EPR_ALT2, SPI_CMD_ERASE, SPI_DATA_DISABLE, 0, 0, "Erase / Program Resume" }, ++ { CMD_OTP_PROGRAM, SPI_CMD_WRITE, SPI_DATA_ENABLE, 3, 0, "OTP Program" }, ++ { CMD_OTP_READ, SPI_CMD_WRITE, SPI_DATA_ENABLE, 3, 0, "OTP Read" }, ++ { CMD_DYB_READ, SPI_CMD_READ, SPI_DATA_ENABLE, 3, 0, "DYB Read" }, ++ { CMD_DYB_READ_ADDR4, SPI_CMD_READ, SPI_DATA_ENABLE, 4, 0, "DYB Read" }, ++ { CMD_DYB_WRITE, SPI_CMD_WRITE, SPI_DATA_ENABLE, 3, 0, "DYB Write" }, ++ { CMD_DYB_WRITE_ADDR4, SPI_CMD_WRITE, SPI_DATA_ENABLE, 4, 0, "DYB Write" }, ++ { CMD_PPB_READ, SPI_CMD_READ, SPI_DATA_ENABLE, 3, 0, "PPB Read" }, ++ { CMD_PPB_READ_ADDR4, SPI_CMD_READ, SPI_DATA_ENABLE, 3, 0, "PPB Read" }, ++ { CMD_PPB_PROGRAM, SPI_CMD_WRITE, SPI_DATA_DISABLE, 3, 0, "PPB Program" }, ++ { CMD_PPB_PROGRAM_ADDR4, SPI_CMD_WRITE, SPI_DATA_DISABLE, 3, 0, "PPB Program" }, ++ { CMD_PPB_ERASE, SPI_CMD_OTHER, SPI_DATA_DISABLE, 0, 0, "PPB Erase" }, ++ { CMD_ASP_READ, SPI_CMD_READ, SPI_DATA_ENABLE, 0, 0, "ASP Read" }, ++ { CMD_ASP_PROGRAM, SPI_CMD_WRITE, SPI_DATA_ENABLE, 0, 0, "ASP Program" }, ++ { CMD_PPB_LOCKBIT_READ, SPI_CMD_READ, SPI_DATA_ENABLE, 0, 0, "PPB Lock Bit Read" }, ++ { CMD_PPB_LOCKBIT_WRITE, SPI_CMD_WRITE, SPI_DATA_DISABLE, 0, 0, "PPB Lock Bit Write" }, ++ { CMD_PASSWD_READ, SPI_CMD_READ, SPI_DATA_ENABLE, 0, 0, "Password Read" }, ++ { CMD_PASSWD_PROGRAM, SPI_CMD_WRITE, SPI_DATA_ENABLE, 0, 0, "Password Program" }, ++ { CMD_PASSWD_UNLOCK, SPI_CMD_OTHER, SPI_DATA_ENABLE, 0, 0, "Password Unlock" }, ++ { CMD_SOFT_RESET_ENABLE, SPI_CMD_OTHER, SPI_DATA_DISABLE, 0, 0, "Software Reset Enable" }, ++ { CMD_SOFT_RESET, SPI_CMD_OTHER, SPI_DATA_DISABLE, 0, 0, "Software Reset" }, ++ { CMD_LEGACY_SOFT_RESET, SPI_CMD_OTHER, SPI_DATA_DISABLE, 0, 0, "Legacy Software Reset" }, ++ { CMD_MODE_BIT_RESET, SPI_CMD_OTHER, SPI_DATA_DISABLE, 0, 0, "Mode Bit Reset" }, ++ { CMD_ENT_DEEP_POWER_DOWN, SPI_CMD_OTHER, SPI_DATA_DISABLE, 0, 0, "Enter Deep Power-Down Mode" }, ++ { CMD_REL_DEEP_POWER_DOWN, SPI_CMD_OTHER, SPI_DATA_DISABLE, 0, 0, "Release from Deep Power-Down Mode" }, ++ { SPI_COMMAND_LAST, SPI_CMD_OTHER, SPI_DATA_DISABLE, 0, 0, "Last Command" }, ++}; ++ ++static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave) ++{ ++ return container_of(slave, struct sh_qspi_slave, slave); ++} ++ ++void spi_set_addr(uint32_t addr) ++{ ++ debug_print("Set Addr: %08X\n", addr); ++ out_le32(SH_QSPI_BASE + RPC_SMADR, addr); ++ return; ++} ++ ++static void rcar_gen3_qspi_init(void) ++{ ++ out_le32(SH_QSPI_BASE + RPC_PHYCNT, 0x80000260); ++ out_le32(SH_QSPI_BASE + RPC_CMNCR, 0x81FFF300); ++ ++ return; ++} ++ ++int spi_cs_is_valid(unsigned int bus, unsigned int cs) ++{ ++ return 1; ++} ++ ++void spi_cs_activate(struct spi_slave *slave) ++{ ++ out_le32(SH_QSPI_BASE + RPC_PHYCNT, 0x80000260); ++ ++ return; ++} ++ ++void spi_cs_deactivate(struct spi_slave *slave) ++{ ++ out_le32(SH_QSPI_BASE + RPC_SMCR, SPI_SMCR_SPIE); ++ WaitRpcTxEnd(); ++ out_le32(SH_QSPI_BASE + RPC_PHYCNT, 0x00000274); ++ out_le32(SH_QSPI_BASE + RPC_DRCR, 0x01FF0301); ++ ++ return; ++} ++ ++void spi_init(void) ++{ ++ /* nothing to do */ ++} ++ ++struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, ++ unsigned int max_hz, unsigned int mode) ++{ ++ struct sh_qspi_slave *ss; ++ ++ if (!spi_cs_is_valid(bus, cs)) ++ return NULL; ++ ++ ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs); ++ if (!ss) { ++ printf("SPI_error: Fail to allocate sh_qspi_slave\n"); ++ return NULL; ++ } ++ ++ ss->regs = (struct rcar_gen3_qspi_regs *)SH_QSPI_BASE; ++ ++ /* Init R-Car-Gen3 QSPI */ ++ rcar_gen3_qspi_init(); ++ ++ return &ss->slave; ++} ++ ++void spi_free_slave(struct spi_slave *slave) ++{ ++ struct sh_qspi_slave *spi = to_sh_qspi(slave); ++ ++ free(spi); ++} ++ ++int spi_claim_bus(struct spi_slave *slave) ++{ ++ return 0; ++} ++ ++void spi_release_bus(struct spi_slave *slave) ++{ ++} ++ ++#define BUFFER_SIZE (128) ++int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, ++ void *din, unsigned long flags) ++{ ++ unsigned long nbyte, rnbyte, wnbyte; ++ int i, ret = 0; ++ uint32_t *tdata_l = (uint32_t *)dout; ++ uint32_t *rdata_l = (uint32_t *)din; ++ uint8_t *ptr_b; ++ uint32_t readVal, writeVal; ++ ++ if (dout == NULL && din == NULL) { ++ if (flags & SPI_XFER_END) ++ spi_cs_deactivate(slave); ++ return 0; ++ } ++ ++ if (bitlen % 8) { ++ printf("%s: bitlen is not 8bit alined %d", __func__, bitlen); ++ return 1; ++ } ++ ++ if (flags & SPI_XFER_BEGIN) { ++ spi_cs_activate(slave); ++ } ++ ++ /* Set Data Enable 32bit */ ++ readVal = in_le32(SH_QSPI_BASE + RPC_SMENR); ++ writeVal = (readVal & 0xffff0000); ++ writeVal |= SPI_SMENR_SPIDE_32BIT; ++ out_le32(SH_QSPI_BASE + RPC_SMENR, writeVal); ++ ++ nbyte = bitlen / 8; ++ if (tdata_l != NULL) ++ wnbyte = nbyte; ++ else ++ wnbyte = 0; ++ ++ if (rdata_l != NULL) ++ rnbyte = nbyte; ++ else ++ rnbyte = 0; ++ ++ while (wnbyte > 0) { ++ if (wnbyte < BYTE_32BIT) { ++ out_8(RPC_SMWDR0, *(uint8_t*)tdata_l); ++ /* Set Data Enable 8bit */ ++ readVal = in_le32(SH_QSPI_BASE + RPC_SMENR); ++ writeVal = (readVal & 0xffff0000); ++ writeVal |= SPI_SMENR_SPIDE_8BIT; ++ out_le32(SH_QSPI_BASE + RPC_SMENR, writeVal); ++ }else{ ++ out_le32(SH_QSPI_BASE + RPC_SMWDR0, *tdata_l); ++ } ++ ++ if (wnbyte >= BYTE_32BIT) { ++ tdata_l++; ++ wnbyte -= BYTE_32BIT; ++ }else{ ++ ptr_b = (uint8_t*) tdata_l; ++ ptr_b++; ++ tdata_l = (uint32_t*) ptr_b; ++ wnbyte -= BYTE_8BIT; ++ } ++ ++ if (wnbyte > 0) { ++ out_le32(SH_QSPI_BASE + RPC_SMCR, SPI_SMCR_SSLKP | SPI_SMCR_SPIWE | SPI_SMCR_SPIE); ++ }else{ ++ out_le32(SH_QSPI_BASE + RPC_SMCR, SPI_SMCR_SPIWE | SPI_SMCR_SPIE); ++ } ++ ++ WaitRpcTxEnd(); ++ ++ if (wnbyte == 0) { ++ WaitReadyDevice(slave); ++ } ++ } ++ ++ while (rnbyte > 0) { ++ if (rnbyte < BYTE_32BIT) { ++ readVal = in_le32(SH_QSPI_BASE + RPC_SMRDR0); ++ ptr_b = (uint8_t*) rdata_l; ++ for(i=0; i<rnbyte; i++) { ++ *ptr_b = (readVal >> (8*i)) & 0x000000ff; ++ ptr_b++; ++ } ++ }else{ ++ *rdata_l = in_le32(SH_QSPI_BASE + RPC_SMRDR0); ++ } ++ ++ rdata_l++; ++ ++ if(slave->spi_cmd->cmd_code == CMD_READ_ARRAY_FAST_ADDR4) { ++ readVal = in_le32(SH_QSPI_BASE + RPC_SMENR); ++ writeVal = readVal | 0x0000CF00; ++ out_le32(SH_QSPI_BASE + RPC_SMENR, writeVal); ++ readVal = in_le32(SH_QSPI_BASE + RPC_SMADR); ++ readVal += BYTE_32BIT; ++ spi_set_addr(readVal); ++ out_le32(SH_QSPI_BASE + RPC_SMCR, SPI_SMCR_SPIRE | SPI_SMCR_SPIE); ++ }else{ ++ if (rnbyte > BYTE_32BIT) { ++ out_le32(SH_QSPI_BASE + RPC_SMCR, SPI_SMCR_SSLKP | SPI_SMCR_SPIRE | SPI_SMCR_SPIE); ++ }else{ ++ out_le32(SH_QSPI_BASE + RPC_SMCR, SPI_SMCR_SPIRE | SPI_SMCR_SPIE); ++ } ++ } ++ ++ WaitRpcTxEnd(); ++ ++ if (rnbyte >= BYTE_32BIT) { ++ rnbyte -= BYTE_32BIT; ++ }else{ ++ rnbyte = 0; ++ } ++ } ++ ++ if (flags & SPI_XFER_END){ ++ spi_cs_deactivate(slave); ++ } ++ ++ return ret; ++} ++ ++int spi_xfer_cmd(struct spi_slave *slave, int cmd_no) ++{ ++ uint32_t readVal, writeVal, dummy_cyc; ++ const SPI_COMMAND *cur_cmd_tbl; ++ cur_cmd_tbl = spi_cmd_tbl; ++ ++ while(cur_cmd_tbl->cmd_code != SPI_COMMAND_LAST) { ++ if(cur_cmd_tbl->cmd_code != cmd_no) { ++ cur_cmd_tbl++; ++ continue; ++ } ++ ++ slave->spi_cmd = cur_cmd_tbl; ++ ++ spi_cs_activate(slave); ++ out_le32(SH_QSPI_BASE + RPC_SMCMR, cmd_no << SPI_SMCMR_CMD_BIT); ++ debug_print("SPI CODE:0x%02X [ %s ]\n", cur_cmd_tbl->cmd_code, cur_cmd_tbl->cmd_desc); ++ ++ readVal = in_le32(SH_QSPI_BASE + RPC_SMENR); ++ writeVal = readVal & 0xFFFF0000; ++ writeVal |= SPI_SMENR_CDE; ++ ++ /* Setting Address */ ++ switch (cur_cmd_tbl->addr_len) { ++ case 3: ++ writeVal |= SPI_SMENR_ADE_3BYTE; ++ break; ++ case 4: ++ writeVal |= SPI_SMENR_ADE_4BYTE; ++ break; ++ default: ++ writeVal |= SPI_SMENR_ADE_DISABLE; ++ break; ++ } ++ ++ /* Setting dummy cycle */ ++ if (cur_cmd_tbl->dummy_len != 0) { ++ writeVal |= SPI_SMENR_DME; ++ dummy_cyc = cur_cmd_tbl->dummy_len - 1; ++ out_le32(SH_QSPI_BASE + RPC_SMDMCR, dummy_cyc); ++ } ++ out_le32(SH_QSPI_BASE + RPC_SMENR, writeVal); ++ ++ switch(cur_cmd_tbl->rw_type) { ++ case SPI_CMD_READ: ++ readVal = in_le32(SH_QSPI_BASE + RPC_SMENR); ++ writeVal = readVal & 0xFFFFFFF0; ++ writeVal |= SPI_SMENR_SPIDE_32BIT; ++ out_le32(SH_QSPI_BASE + RPC_SMENR, writeVal); ++ ++ if(cur_cmd_tbl->data_enable == SPI_DATA_ENABLE) { ++ if(cur_cmd_tbl->cmd_code == CMD_READ_ARRAY_FAST_ADDR4) { ++ out_le32(SH_QSPI_BASE + RPC_SMCR, SPI_SMCR_SPIRE | SPI_SMCR_SPIE); ++ }else{ ++ out_le32(SH_QSPI_BASE + RPC_SMCR, SPI_SMCR_SSLKP | SPI_SMCR_SPIRE | SPI_SMCR_SPIE); ++ } ++ }else{ ++ out_le32(SH_QSPI_BASE + RPC_SMCR, SPI_SMCR_SPIRE | SPI_SMCR_SPIE); ++ } ++ break; ++ case SPI_CMD_WRITE: ++ if(cur_cmd_tbl->data_enable == SPI_DATA_ENABLE) { ++ out_le32(SH_QSPI_BASE + RPC_SMCR, SPI_SMCR_SSLKP | SPI_SMCR_SPIWE | SPI_SMCR_SPIE); ++ }else{ ++ out_le32(SH_QSPI_BASE + RPC_SMCR, SPI_SMCR_SPIWE | SPI_SMCR_SPIE); ++ } ++ break; ++ default: ++ if(cur_cmd_tbl->data_enable == SPI_DATA_ENABLE) { ++ out_le32(SH_QSPI_BASE + RPC_SMCR, SPI_SMCR_SSLKP | SPI_SMCR_SPIE); ++ }else{ ++ out_le32(SH_QSPI_BASE + RPC_SMCR, SPI_SMCR_SPIE); ++ } ++ break; ++ } ++ ++ WaitRpcTxEnd(); ++ ++ if (cur_cmd_tbl->data_enable != SPI_DATA_ENABLE) { ++ spi_cs_deactivate(slave); ++ } ++ break; ++ } ++ ++ if(cur_cmd_tbl->cmd_code == SPI_COMMAND_LAST) { ++ printf("Unknown SPI Command : %02x\n", cmd_no); ++ return -1; ++ } ++ return 0; ++} ++ ++void WaitRpcTxEnd(void) ++{ ++ uint32_t dataL=0; ++ ++ while(1) { ++ dataL = in_le32(SH_QSPI_BASE + RPC_CMNSR); ++ if(dataL & 0x00000001) { ++ break; ++ } ++ // Wait for TEND = 1 ++ if(ctrlc()) { ++ puts("abort\n"); ++ return; ++ } ++ udelay(1); ++ } ++ return; ++} ++ ++void WaitReadyDevice(struct spi_slave *slave) ++{ ++ int ret; ++ u8 status; ++ while(1) { ++ ret = spi_get_read_status(slave, &status); ++ if (ret < 0) { ++ printf("SF: fail to get read status\n"); ++ return; ++ } ++ if ((status & SR1V_WIP) == 0) { ++ break; ++ } ++ udelay(1); ++ } ++ return; ++} ++ ++int spi_get_read_status(struct spi_slave *slave, u8 *rs) ++{ ++ int ret; ++ u8 cmd; ++ ++ cmd = CMD_READ_STATUS; ++ ret = spi_flash_cmd_read(slave, &cmd, 1, rs, 1); ++ if (ret < 0) { ++ debug("SF: fail to get read status register\n"); ++ return ret; ++ } ++ ++ return 0; ++} +diff --git a/drivers/spi/rcar_gen3_qspi.h b/drivers/spi/rcar_gen3_qspi.h +new file mode 100644 +index 0000000..deb18d3 +--- /dev/null ++++ b/drivers/spi/rcar_gen3_qspi.h +@@ -0,0 +1,301 @@ ++/* ++ * Common R-Car-Gen3 QSPI Interface: Controller-specific definitions ++ * ++ */ ++ ++#ifndef _R_CAR_GEN3_QSPI_H_ ++#define _R_CAR_GEN3_QSPI_H_ ++ ++/* SPI transfer flags */ ++#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */ ++#define SPI_XFER_END 0x02 /* Deassert CS after transfer */ ++#define SPI_XFER_MMAP 0x08 /* Memory Mapped start */ ++#define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */ ++#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) ++#define SPI_XFER_U_PAGE (1 << 5) ++ ++#define SPI_COMMAND_LAST 0xffffffff ++#define SPI_SMCMR_CMD_BIT 16 ++ ++#define SPI_CMD_OTHER 0 ++#define SPI_CMD_READ 1 ++#define SPI_CMD_WRITE 2 ++#define SPI_CMD_ERASE 3 ++ ++#define SPI_DATA_DISABLE 0 ++#define SPI_DATA_ENABLE 1 ++ ++#define SPI_SMCR_SPIE 0x00000001 ++#define SPI_SMCR_SPIWE 0x00000002 ++#define SPI_SMCR_SPIRE 0x00000004 ++#define SPI_SMCR_SSLKP 0x00000100 ++ ++#define SPI_SMENR_DME (1 << 15) ++#define SPI_SMENR_CDE (1 << 14) ++#define SPI_SMENR_ADE_DISABLE (0x0 << 8) ++#define SPI_SMENR_ADE_3BYTE (0x7 << 8) ++#define SPI_SMENR_ADE_4BYTE (0xF << 8) ++#define SPI_SMENR_SPIDE_DISABLE (0x0) ++#define SPI_SMENR_SPIDE_8BIT (0x8) ++#define SPI_SMENR_SPIDE_16BIT (0xC) ++#define SPI_SMENR_SPIDE_32BIT (0xF) ++ ++#define BYTE_32BIT (4) ++#define BYTE_8BIT (1) ++ ++typedef struct { ++ uint32_t cmd_code; ++ uint8_t rw_type; ++ uint32_t data_enable; ++ uint32_t addr_len; ++ uint32_t dummy_len; ++ char* cmd_desc; ++} SPI_COMMAND; ++ ++/** ++ * struct spi_slave - Representation of a SPI slave ++ * ++ * For driver model this is the per-child data used by the SPI bus. It can ++ * be accessed using dev_get_parentdata() on the slave device. The SPI uclass ++ * sets uip per_child_auto_alloc_size to sizeof(struct spi_slave), and the ++ * driver should not override it. Two platform data fields (max_hz and mode) ++ * are copied into this structure to provide an initial value. This allows ++ * them to be changed, since we should never change platform data in drivers. ++ * ++ * If not using driver model, drivers are expected to extend this with ++ * controller-specific data. ++ * ++ * @dev: SPI slave device ++ * @max_hz: Maximum speed for this slave ++ * @mode: SPI mode to use for this slave (see SPI mode flags) ++ * @bus: ID of the bus that the slave is attached to. For ++ * driver model this is the sequence number of the SPI ++ * bus (bus->seq) so does not need to be stored ++ * @cs: ID of the chip select connected to the slave. ++ * @op_mode_rx: SPI RX operation mode. ++ * @op_mode_tx: SPI TX operation mode. ++ * @wordlen: Size of SPI word in number of bits ++ * @max_write_size: If non-zero, the maximum number of bytes which can ++ * be written at once, excluding command bytes. ++ * @memory_map: Address of read-only SPI flash access. ++ * @option: Varies SPI bus options - separate, shared bus. ++ * @flags: Indication of SPI flags. ++ */ ++struct spi_slave { ++#ifdef CONFIG_DM_SPI ++ struct udevice *dev; /* struct spi_slave is dev->parentdata */ ++ uint max_hz; ++ uint mode; ++#else ++ unsigned int bus; ++ unsigned int cs; ++#endif ++ u8 op_mode_rx; ++ u8 op_mode_tx; ++ unsigned int wordlen; ++ unsigned int max_write_size; ++ void *memory_map; ++ u8 option; ++ u8 flags; ++ const SPI_COMMAND *spi_cmd; ++}; ++ ++/** ++ * Initialization, must be called once on start up. ++ * ++ * TODO: I don't think we really need this. ++ */ ++void spi_init(void); ++ ++/** ++ * spi_do_alloc_slave - Allocate a new SPI slave (internal) ++ * ++ * Allocate and zero all fields in the spi slave, and set the bus/chip ++ * select. Use the helper macro spi_alloc_slave() to call this. ++ * ++ * @offset: Offset of struct spi_slave within slave structure. ++ * @size: Size of slave structure. ++ * @bus: Bus ID of the slave chip. ++ * @cs: Chip select ID of the slave chip on the specified bus. ++ */ ++void *spi_do_alloc_slave(int offset, int size, unsigned int bus, ++ unsigned int cs); ++ ++/** ++ * spi_alloc_slave - Allocate a new SPI slave ++ * ++ * Allocate and zero all fields in the spi slave, and set the bus/chip ++ * select. ++ * ++ * @_struct: Name of structure to allocate (e.g. struct tegra_spi). ++ * This structure must contain a member 'struct spi_slave *slave'. ++ * @bus: Bus ID of the slave chip. ++ * @cs: Chip select ID of the slave chip on the specified bus. ++ */ ++#define spi_alloc_slave(_struct, bus, cs) \ ++ spi_do_alloc_slave(offsetof(_struct, slave), \ ++ sizeof(_struct), bus, cs) ++ ++/** ++ * spi_alloc_slave_base - Allocate a new SPI slave with no private data ++ * ++ * Allocate and zero all fields in the spi slave, and set the bus/chip ++ * select. ++ * ++ * @bus: Bus ID of the slave chip. ++ * @cs: Chip select ID of the slave chip on the specified bus. ++ */ ++#define spi_alloc_slave_base(bus, cs) \ ++ spi_do_alloc_slave(0, sizeof(struct spi_slave), bus, cs) ++ ++/** ++ * Set up communications parameters for a SPI slave. ++ * ++ * This must be called once for each slave. Note that this function ++ * usually doesn't touch any actual hardware, it only initializes the ++ * contents of spi_slave so that the hardware can be easily ++ * initialized later. ++ * ++ * @bus: Bus ID of the slave chip. ++ * @cs: Chip select ID of the slave chip on the specified bus. ++ * @max_hz: Maximum SCK rate in Hz. ++ * @mode: Clock polarity, clock phase and other parameters. ++ * ++ * Returns: A spi_slave reference that can be used in subsequent SPI ++ * calls, or NULL if one or more of the parameters are not supported. ++ */ ++struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, ++ unsigned int max_hz, unsigned int mode); ++ ++/** ++ * Free any memory associated with a SPI slave. ++ * ++ * @slave: The SPI slave ++ */ ++void spi_free_slave(struct spi_slave *slave); ++ ++/** ++ * Claim the bus and prepare it for communication with a given slave. ++ * ++ * This must be called before doing any transfers with a SPI slave. It ++ * will enable and initialize any SPI hardware as necessary, and make ++ * sure that the SCK line is in the correct idle state. It is not ++ * allowed to claim the same bus for several slaves without releasing ++ * the bus in between. ++ * ++ * @slave: The SPI slave ++ * ++ * Returns: 0 if the bus was claimed successfully, or a negative value ++ * if it wasn't. ++ */ ++int spi_claim_bus(struct spi_slave *slave); ++ ++/** ++ * Release the SPI bus ++ * ++ * This must be called once for every call to spi_claim_bus() after ++ * all transfers have finished. It may disable any SPI hardware as ++ * appropriate. ++ * ++ * @slave: The SPI slave ++ */ ++void spi_release_bus(struct spi_slave *slave); ++ ++/** ++ * Set the word length for SPI transactions ++ * ++ * Set the word length (number of bits per word) for SPI transactions. ++ * ++ * @slave: The SPI slave ++ * @wordlen: The number of bits in a word ++ * ++ * Returns: 0 on success, -1 on failure. ++ */ ++int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen); ++ ++/** ++ * SPI transfer ++ * ++ * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks ++ * "bitlen" bits in the SPI MISO port. That's just the way SPI works. ++ * ++ * The source of the outgoing bits is the "dout" parameter and the ++ * destination of the input bits is the "din" parameter. Note that "dout" ++ * and "din" can point to the same memory location, in which case the ++ * input data overwrites the output data (since both are buffered by ++ * temporary variables, this is OK). ++ * ++ * spi_xfer() interface: ++ * @slave: The SPI slave which will be sending/receiving the data. ++ * @bitlen: How many bits to write and read. ++ * @dout: Pointer to a string of bits to send out. The bits are ++ * held in a byte array and are sent MSB first. ++ * @din: Pointer to a string of bits that will be filled in. ++ * @flags: A bitwise combination of SPI_XFER_* flags. ++ * ++ * Returns: 0 on success, not 0 on failure ++ */ ++int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, ++ void *din, unsigned long flags); ++ ++/** ++ * Determine if a SPI chipselect is valid. ++ * This function is provided by the board if the low-level SPI driver ++ * needs it to determine if a given chipselect is actually valid. ++ * ++ * Returns: 1 if bus:cs identifies a valid chip on this board, 0 ++ * otherwise. ++ */ ++int spi_cs_is_valid(unsigned int bus, unsigned int cs); ++ ++#ifndef CONFIG_DM_SPI ++/** ++ * Activate a SPI chipselect. ++ * This function is provided by the board code when using a driver ++ * that can't control its chipselects automatically (e.g. ++ * common/soft_spi.c). When called, it should activate the chip select ++ * to the device identified by "slave". ++ */ ++void spi_cs_activate(struct spi_slave *slave); ++ ++/** ++ * Deactivate a SPI chipselect. ++ * This function is provided by the board code when using a driver ++ * that can't control its chipselects automatically (e.g. ++ * common/soft_spi.c). When called, it should deactivate the chip ++ * select to the device identified by "slave". ++ */ ++void spi_cs_deactivate(struct spi_slave *slave); ++ ++/** ++ * Set transfer speed. ++ * This sets a new speed to be applied for next spi_xfer(). ++ * @slave: The SPI slave ++ * @hz: The transfer speed ++ */ ++void spi_set_speed(struct spi_slave *slave, uint hz); ++#endif ++ ++ ++/** ++ * Set up a SPI slave for a particular device tree node ++ * ++ * This calls spi_setup_slave() with the correct bus number. Call ++ * spi_free_slave() to free it later. ++ * ++ * @param blob: Device tree blob ++ * @param slave_node: Slave node to use ++ * @param spi_node: SPI peripheral node to use ++ * @return pointer to new spi_slave structure ++ */ ++struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node, ++ int spi_node); ++ ++/* QSPI Flash Read/Write function */ ++void spi_set_addr(uint32_t addr); ++int spi_xfer_cmd(struct spi_slave *slave, int cmd_no); ++void WaitRpcTxEnd(void); ++void WaitReadyDevice(struct spi_slave *slave); ++int spi_get_read_status(struct spi_slave *slave, u8 *rs); ++ ++#endif /* _R_CAR_GEN3_QSPI_H_ */ +diff --git a/include/linux/bitops.h b/include/linux/bitops.h +index e724310..3bf04d2 100644 +--- a/include/linux/bitops.h ++++ b/include/linux/bitops.h +@@ -104,6 +104,7 @@ static inline unsigned int generic_hweight8(unsigned int w) + return (res & 0x0F) + ((res >> 4) & 0x0F); + } + ++#define BIT(nr) (1UL << (nr)) + #define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) + #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) + +diff --git a/include/spi.h b/include/spi.h +index c58e453..d6978c7 100644 +--- a/include/spi.h ++++ b/include/spi.h +@@ -11,18 +11,24 @@ + #define _SPI_H_ + + /* SPI mode flags */ +-#define SPI_CPHA 0x01 /* clock phase */ +-#define SPI_CPOL 0x02 /* clock polarity */ ++#define SPI_CPHA BIT(0) /* clock phase */ ++#define SPI_CPOL BIT(1) /* clock polarity */ + #define SPI_MODE_0 (0|0) /* (original MicroWire) */ + #define SPI_MODE_1 (0|SPI_CPHA) + #define SPI_MODE_2 (SPI_CPOL|0) + #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) +-#define SPI_CS_HIGH 0x04 /* CS active high */ +-#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ +-#define SPI_3WIRE 0x10 /* SI/SO signals shared */ +-#define SPI_LOOP 0x20 /* loopback mode */ +-#define SPI_SLAVE 0x40 /* slave mode */ +-#define SPI_PREAMBLE 0x80 /* Skip preamble bytes */ ++#define SPI_CS_HIGH BIT(2) /* CS active high */ ++#define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */ ++#define SPI_3WIRE BIT(4) /* SI/SO signals shared */ ++#define SPI_LOOP BIT(5) /* loopback mode */ ++#define SPI_SLAVE BIT(6) /* slave mode */ ++#define SPI_PREAMBLE BIT(7) /* Skip preamble bytes */ ++#define SPI_TX_BYTE BIT(8) /* transmit with 1 wire byte */ ++#define SPI_TX_DUAL BIT(9) /* transmit with 2 wires */ ++#define SPI_TX_QUAD BIT(10) /* transmit with 4 wires */ ++#define SPI_RX_SLOW BIT(11) /* receive with 1 wire slow */ ++#define SPI_RX_DUAL BIT(12) /* receive with 2 wires */ ++#define SPI_RX_QUAD BIT(13) /* receive with 4 wires */ + + /* SPI transfer flags */ + #define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */ +-- +1.9.1 diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch new file mode 100644 index 0000000..8545634 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0014-arm-renesas-Add-Renesas-R8A7797-SoC-support.patch @@ -0,0 +1,3542 @@ +From 02cc2edc21e6c6895cf0304beecae4d990225ea2 Mon Sep 17 00:00:00 2001 +From: Daisuke Matsushita <daisuke.matsushita.ns@hitachi.com> +Date: Tue, 21 Mar 2017 15:05:15 +0900 +Subject: [PATCH] arm: renesas: Add Renesas R8A7797 SoC support + +This adds Renesas R8A7797 SoC support + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +--- + arch/arm/cpu/armv8/Kconfig | 3 + + arch/arm/cpu/armv8/rcar_gen3/Makefile | 3 + + arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7797.c | 39 + + arch/arm/cpu/armv8/rcar_gen3/cpu_info.c | 8 + + arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7797.c | 2764 ++++++++++++++++++++ + arch/arm/cpu/armv8/rcar_gen3/pfc.c | 2 + + arch/arm/cpu/armv8/rcar_gen3/prr_depend.c | 27 + + arch/arm/include/asm/arch-rcar_gen3/gpio.h | 4 + + arch/arm/include/asm/arch-rcar_gen3/r8a7797-gpio.h | 456 ++++ + arch/arm/include/asm/arch-rcar_gen3/r8a7797.h | 33 + + arch/arm/include/asm/arch-rcar_gen3/rcar-base.h | 5 + + arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h | 2 + + drivers/serial/serial_sh.h | 3 +- + include/configs/rcar-gen3-common.h | 12 + + 14 files changed, 3360 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7797.c + create mode 100644 arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7797.c + create mode 100644 arch/arm/include/asm/arch-rcar_gen3/r8a7797-gpio.h + create mode 100644 arch/arm/include/asm/arch-rcar_gen3/r8a7797.h + +diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig +index 01646e9..dfd9bab 100644 +--- a/arch/arm/cpu/armv8/Kconfig ++++ b/arch/arm/cpu/armv8/Kconfig +@@ -35,6 +35,9 @@ config R8A77965 + bool "Renesas SoC R8A77965" + select R8A7796X + ++config R8A7797 ++ bool "Renesas SoC R8A7797" ++ + endchoice + + config SYS_SOC +diff --git a/arch/arm/cpu/armv8/rcar_gen3/Makefile b/arch/arm/cpu/armv8/rcar_gen3/Makefile +index 01ecaa1..a7a8f79 100644 +--- a/arch/arm/cpu/armv8/rcar_gen3/Makefile ++++ b/arch/arm/cpu/armv8/rcar_gen3/Makefile +@@ -15,3 +15,6 @@ obj-$(CONFIG_R8A7795) += lowlevel_init.o cpu_info-r8a7795.o \ + obj-$(CONFIG_R8A7796X) += lowlevel_init.o cpu_info-r8a7796.o \ + pfc.o pfc-r8a7796.o prr_depend.o \ + board.o ++obj-$(CONFIG_R8A7797) += lowlevel_init.o cpu_info-r8a7797.o \ ++ pfc.o pfc-r8a7797.o prr_depend.o \ ++ board.o +diff --git a/arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7797.c b/arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7797.c +new file mode 100644 +index 0000000..cc8e1e6 +--- /dev/null ++++ b/arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7797.c +@@ -0,0 +1,39 @@ ++/* ++ * arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7797.c ++ * This file defines cpu information funstions. ++ * ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++#include <common.h> ++#include <asm/io.h> ++ ++#define PRR 0xFFF00044 ++ ++u32 rcar_get_cpu_type(void) ++{ ++ u32 product; ++ ++ product = readl(PRR); ++ ++ return (product & 0x00007F00) >> 8; ++} ++ ++u32 rcar_get_cpu_rev_integer(void) ++{ ++ u32 product; ++ ++ product = readl(PRR); ++ ++ return (u32)(((product & 0x000000F0) >> 4) + 1); ++} ++ ++u32 rcar_get_cpu_rev_fraction(void) ++{ ++ u32 product; ++ ++ product = readl(PRR); ++ ++ return (u32)(product & 0x0000000F); ++} +diff --git a/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c b/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c +index 1a699e4..0046c75 100644 +--- a/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c ++++ b/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c +@@ -81,6 +81,14 @@ int print_cpuinfo(void) + CONFIG_RCAR_TARGET_STRING); + } + break; ++ case 0x54: ++ printf("CPU: Renesas Electronics R8A7797 rev %d.%d\n", ++ rev_integer, rev_fraction); ++ if (strcmp(CONFIG_RCAR_TARGET_STRING, "r8a7797")) { ++ printf("Warning: this code supports only %s\n", ++ CONFIG_RCAR_TARGET_STRING); ++ } ++ break; + } + return 0; + } +diff --git a/arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7797.c b/arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7797.c +new file mode 100644 +index 0000000..3b2f75e +--- /dev/null ++++ b/arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7797.c +@@ -0,0 +1,2764 @@ ++/* ++ * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7797.c ++ * This file is r8a7797 processor support - PFC hardware block. ++ * ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <sh_pfc.h> ++#include <asm/gpio.h> ++ ++#define CPU_32_PORT(fn, pfx, sfx) \ ++ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ ++ PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ ++ PORT_1(fn, pfx##31, sfx) ++ ++#define CPU_32_PORT1(fn, pfx, sfx) \ ++ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ ++ PORT_10(fn, pfx##2, sfx) ++ ++#define CPU_32_PORT2(fn, pfx, sfx) \ ++ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ ++ PORT_10(fn, pfx##2, sfx) ++ ++#define CPU_32_PORT_28(fn, pfx, sfx) \ ++ PORT_10(fn, pfx, sfx), \ ++ PORT_10(fn, pfx##1, sfx), \ ++ PORT_1(fn, pfx##20, sfx), \ ++ PORT_1(fn, pfx##21, sfx), \ ++ PORT_1(fn, pfx##22, sfx), \ ++ PORT_1(fn, pfx##23, sfx), \ ++ PORT_1(fn, pfx##24, sfx), \ ++ PORT_1(fn, pfx##25, sfx), \ ++ PORT_1(fn, pfx##26, sfx), \ ++ PORT_1(fn, pfx##27, sfx) ++ ++#define CPU_32_PORT_22(fn, pfx, sfx) \ ++ PORT_10(fn, pfx, sfx), \ ++ PORT_10(fn, pfx##1, sfx), \ ++ PORT_1(fn, pfx##20, sfx), \ ++ PORT_1(fn, pfx##21, sfx) ++ ++#define CPU_32_PORT_17(fn, pfx, sfx) \ ++ PORT_10(fn, pfx, sfx), \ ++ PORT_1(fn, pfx##10, sfx), \ ++ PORT_1(fn, pfx##11, sfx), \ ++ PORT_1(fn, pfx##12, sfx), \ ++ PORT_1(fn, pfx##13, sfx), \ ++ PORT_1(fn, pfx##14, sfx), \ ++ PORT_1(fn, pfx##15, sfx), \ ++ PORT_1(fn, pfx##16, sfx) ++ ++#define CPU_32_PORT_15(fn, pfx, sfx) \ ++ PORT_10(fn, pfx, sfx), \ ++ PORT_1(fn, pfx##10, sfx), \ ++ PORT_1(fn, pfx##11, sfx), \ ++ PORT_1(fn, pfx##12, sfx), \ ++ PORT_1(fn, pfx##13, sfx), \ ++ PORT_1(fn, pfx##14, sfx) ++ ++#define CPU_32_PORT_6(fn, pfx, sfx) \ ++ PORT_1(fn, pfx##0, sfx), \ ++ PORT_1(fn, pfx##1, sfx), \ ++ PORT_1(fn, pfx##2, sfx), \ ++ PORT_1(fn, pfx##3, sfx), \ ++ PORT_1(fn, pfx##4, sfx), \ ++ PORT_1(fn, pfx##5, sfx) ++ ++ ++/* --gen3-- */ ++/* GP_0_0_DATA -> GP_5_14_DATA */ ++/* except for GP0[22] - [31], ++ GP1[28] - [31], ++ GP2[17] - [31], ++ GP3[17] - [31], ++ GP4[6] - [31], ++ GP5[15] - [31], */ ++ ++#define CPU_ALL_PORT(fn, pfx, sfx) \ ++ CPU_32_PORT_22(fn, pfx##_0_, sfx), \ ++ CPU_32_PORT_28(fn, pfx##_1_, sfx), \ ++ CPU_32_PORT_17(fn, pfx##_2_, sfx), \ ++ CPU_32_PORT_17(fn, pfx##_3_, sfx), \ ++ CPU_32_PORT_6(fn, pfx##_4_, sfx), \ ++ CPU_32_PORT_15(fn, pfx##_5_, sfx) ++ ++#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) ++#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ ++ GP##pfx##_IN, GP##pfx##_OUT) ++ ++#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT ++#define _GP_INDT(pfx, sfx) GP##pfx##_DATA ++ ++#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) ++#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) ++#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) ++ ++ ++#define PORT_10_REV(fn, pfx, sfx) \ ++ PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ ++ PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ ++ PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ ++ PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ ++ PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) ++ ++#define CPU_32_PORT_REV(fn, pfx, sfx) \ ++ PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ ++ PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ ++ PORT_10_REV(fn, pfx, sfx) ++ ++#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) ++#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) ++ ++#define PINMUX_IPSR_IDATA(fn) PINMUX_DATA(fn##_IMARK, GFN_##fn, IFN_##fn) ++#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, GFN_##ipsr, FN_##fn) ++#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ ++ FN_##ipsr, FN_##fn) ++ ++enum { ++ PINMUX_RESERVED = 0, ++ ++ PINMUX_DATA_BEGIN, ++ GP_ALL(DATA), ++ PINMUX_DATA_END, ++ ++ PINMUX_INPUT_BEGIN, ++ GP_ALL(IN), ++ PINMUX_INPUT_END, ++ ++ PINMUX_OUTPUT_BEGIN, ++ GP_ALL(OUT), ++ PINMUX_OUTPUT_END, ++ ++ PINMUX_FUNCTION_BEGIN, ++ GP_ALL(FN), ++ ++ /* GPSR0 */ ++ GFN_DU_EXODDF_DU_ODDF_DISP_CDE, ++ GFN_DU_EXVSYNC_DU_VSYNC, ++ GFN_DU_EXHSYNC_DU_HSYNC, ++ GFN_DU_DOTCLKOUT, ++ GFN_DU_DB7, ++ GFN_DU_DB6, ++ GFN_DU_DB5, ++ GFN_DU_DB4, ++ GFN_DU_DB3, ++ GFN_DU_DB2, ++ GFN_DU_DG7, ++ GFN_DU_DG6, ++ GFN_DU_DG5, ++ GFN_DU_DG4, ++ GFN_DU_DG3, ++ GFN_DU_DG2, ++ GFN_DU_DR7, ++ GFN_DU_DR6, ++ GFN_DU_DR5, ++ GFN_DU_DR4, ++ GFN_DU_DR3, ++ GFN_DU_DR2, ++ ++ /* GPSR1 */ ++ GFN_DIGRF_CLKOUT, ++ GFN_DIGRF_CLKIN, ++ GFN_CANFD_CLK_A, ++ GFN_CANFD1_RX, ++ GFN_CANFD1_TX, ++ GFN_CANFD0_RX_A, ++ GFN_CANFD0_TX_A, ++ GFN_AVB0_AVTP_CAPTURE, ++ FN_AVB0_AVTP_MATCH, ++ FN_AVB0_LINK, ++ FN_AVB0_PHY_INT, ++ FN_AVB0_MAGIC, ++ FN_AVB0_MDC, ++ FN_AVB0_MDIO, ++ FN_AVB0_TXCREFCLK, ++ FN_AVB0_TD3, ++ FN_AVB0_TD2, ++ FN_AVB0_TD1, ++ FN_AVB0_TD0, ++ FN_AVB0_TXC, ++ FN_AVB0_TX_CTL, ++ FN_AVB0_RD3, ++ FN_AVB0_RD2, ++ FN_AVB0_RD1, ++ FN_AVB0_RD0, ++ FN_AVB0_RXC, ++ FN_AVB0_RX_CTL, ++ GFN_IRQ0, ++ ++ /* GPSR2 */ ++ GFN_VI0_FIELD, ++ GFN_VI0_DATA11, ++ GFN_VI0_DATA10, ++ GFN_VI0_DATA9, ++ GFN_VI0_DATA8, ++ GFN_VI0_DATA7, ++ GFN_VI0_DATA6, ++ GFN_VI0_DATA5, ++ GFN_VI0_DATA4, ++ GFN_VI0_DATA3, ++ GFN_VI0_DATA2, ++ GFN_VI0_DATA1, ++ GFN_VI0_DATA0, ++ GFN_VI0_VSYNC_N, ++ GFN_VI0_HSYNC_N, ++ GFN_VI0_CLKENB, ++ GFN_VI0_CLK, ++ ++ /* GPSR3 */ ++ GFN_VI1_FIELD, ++ GFN_VI1_DATA11, ++ GFN_VI1_DATA10, ++ GFN_VI1_DATA9, ++ GFN_VI1_DATA8, ++ GFN_VI1_DATA7, ++ GFN_VI1_DATA6, ++ GFN_VI1_DATA5, ++ GFN_VI1_DATA4, ++ GFN_VI1_DATA3, ++ GFN_VI1_DATA2, ++ GFN_VI1_DATA1, ++ GFN_VI1_DATA0, ++ GFN_VI1_VSYNC_N, ++ GFN_VI1_HSYNC_N, ++ GFN_VI1_CLKENB, ++ GFN_VI1_CLK, ++ ++ /* GPSR4 */ ++ GFN_SDA2, ++ GFN_SCL2, ++ GFN_SDA1, ++ GFN_SCL1, ++ GFN_SDA0, ++ GFN_SCL0, ++ ++ /* GPSR5 */ ++ FN_RPC_INT_N, ++ FN_RPC_WP_N, ++ FN_RPC_RESET_N, ++ FN_QSPI1_SSL, ++ FN_QSPI1_IO3, ++ FN_QSPI1_IO2, ++ FN_QSPI1_MISO_IO1, ++ FN_QSPI1_MOSI_IO0, ++ FN_QSPI1_SPCLK, ++ FN_QSPI0_SSL, ++ FN_QSPI0_IO3, ++ FN_QSPI0_IO2, ++ FN_QSPI0_MISO_IO1, ++ FN_QSPI0_MOSI_IO0, ++ FN_QSPI0_SPCLK, ++ ++ /* IPSR0 */ ++ IFN_DU_DR2, ++ FN_HSCK0, ++ FN_A0, ++ IFN_DU_DR3, ++ FN_HRTS0_N, ++ FN_A1, ++ IFN_DU_DR4, ++ FN_HCTS0_N, ++ FN_A2, ++ IFN_DU_DR5, ++ FN_HTX0, ++ FN_A3, ++ IFN_DU_DR6, ++ FN_MSIOF3_RXD, ++ FN_A4, ++ IFN_DU_DR7, ++ FN_MSIOF3_TXD, ++ FN_A5, ++ IFN_DU_DG2, ++ FN_MSIOF3_SS1, ++ FN_A6, ++ IFN_DU_DG3, ++ FN_MSIOF3_SS2, ++ FN_A7, ++ FN_PWMFSW0, ++ ++ /* IPSR1 */ ++ IFN_DU_DG4, ++ FN_A8, ++ FN_FSO_CFE_0_N_A, ++ IFN_DU_DG5, ++ FN_A9, ++ FN_FSO_CFE_1_N_A, ++ IFN_DU_DG6, ++ FN_A10, ++ FN_FSO_TOE_N_A, ++ IFN_DU_DG7, ++ FN_A11, ++ FN_IRQ1, ++ IFN_DU_DB2, ++ FN_A12, ++ FN_IRQ2, ++ IFN_DU_DB3, ++ FN_A13, ++ FN_FXR_CLKOUT1, ++ IFN_DU_DB4, ++ FN_A14, ++ FN_FXR_CLKOUT2, ++ IFN_DU_DB5, ++ FN_A15, ++ FN_FXR_TXENA_N, ++ ++ /* IPSR2 */ ++ IFN_DU_DB6, ++ FN_A16, ++ FN_FXR_TXENB_N, ++ IFN_DU_DB7, ++ FN_A17, ++ FN_STPWT_EXTFXR, ++ IFN_DU_DOTCLKOUT, ++ FN_SCIF_CLK_A, ++ FN_A18, ++ IFN_DU_EXHSYNC_DU_HSYNC, ++ FN_HRX0, ++ FN_A19, ++ FN_IRQ3, ++ IFN_DU_EXVSYNC_DU_VSYNC, ++ FN_MSIOF3_SCK, ++ FN_A20, ++ IFN_DU_EXODDF_DU_ODDF_DISP_CDE, ++ FN_MSIOF3_SYNC, ++ FN_A21, ++ IFN_IRQ0, ++ FN_CC5_OSCOUT, ++ IFN_VI0_CLK, ++ FN_MSIOF2_SCK, ++ FN_SCK3, ++ FN_HSCK3, ++ ++ /* IPSR3 */ ++ IFN_VI0_CLKENB, ++ FN_MSIOF2_RXD, ++ FN_RX3, ++ FN_RD_WR_N, ++ FN_HCTS3_N, ++ IFN_VI0_HSYNC_N, ++ FN_MSIOF2_TXD, ++ FN_TX3, ++ FN_HRTS3_N, ++ IFN_VI0_VSYNC_N, ++ FN_MSIOF2_SYNC, ++ FN_CTS3_N, ++ FN_HTX3, ++ IFN_VI0_DATA0, ++ FN_MSIOF2_SS1, ++ FN_RTS3_N_TANS, ++ FN_HRX3, ++ IFN_VI0_DATA1, ++ FN_MSIOF2_SS2, ++ FN_SCK1, ++ FN_SPEEDIN_A, ++ IFN_VI0_DATA2, ++ FN_AVB0_AVTP_PPS, ++ FN_SDA3_A, ++ IFN_VI0_DATA3, ++ FN_HSCK1, ++ FN_SCL3_A, ++ IFN_VI0_DATA4, ++ FN_HRTS1_N, ++ FN_RX1_A, ++ ++ /* IPSR4 */ ++ IFN_VI0_DATA5, ++ FN_HCTS1_N, ++ FN_TX1_A, ++ IFN_VI0_DATA6, ++ FN_HTX1, ++ FN_CTS1_N, ++ IFN_VI0_DATA7, ++ FN_HRX1, ++ FN_RTS1_N_TANS, ++ IFN_VI0_DATA8, ++ FN_HSCK2, ++ FN_PWM0_A, ++ FN_A22, ++ IFN_VI0_DATA9, ++ FN_HCTS2_N, ++ FN_PWM1_A, ++ FN_A23, ++ FN_FSO_CFE_0_N_B, ++ IFN_VI0_DATA10, ++ FN_HRTS2_N, ++ FN_PWM2_A, ++ FN_A24, ++ FN_FSO_CFE_1_N_B, ++ IFN_VI0_DATA11, ++ FN_HTX2, ++ FN_PWM3_A, ++ FN_A25, ++ FN_FSO_TOE_N_B, ++ IFN_VI0_FIELD, ++ FN_HRX2, ++ FN_PWM4_A, ++ FN_CS1_N_A26, ++ FN_FSCLKST2_N_A, ++ ++ /* IPSR5 */ ++ IFN_VI1_CLK, ++ FN_MSIOF1_RXD, ++ FN_CS0_N, ++ IFN_VI1_CLKENB, ++ FN_MSIOF1_TXD, ++ FN_D0, ++ IFN_VI1_HSYNC_N, ++ FN_MSIOF1_SCK, ++ FN_D1, ++ IFN_VI1_VSYNC_N, ++ FN_MSIOF1_SYNC, ++ FN_D2, ++ IFN_VI1_DATA0, ++ FN_MSIOF1_SS1, ++ FN_D3, ++ IFN_VI1_DATA1, ++ FN_MSIOF1_SS2, ++ FN_D4, ++ FN_MMC_CMD, ++ IFN_VI1_DATA2, ++ FN_CANFD0_TX_B, ++ FN_D5, ++ FN_MMC_D0, ++ IFN_VI1_DATA3, ++ FN_CANFD0_RX_B, ++ FN_D6, ++ FN_MMC_D1, ++ ++ /* IPSR6 */ ++ IFN_VI1_DATA4, ++ FN_CANFD_CLK_B, ++ FN_D7, ++ FN_MMC_D2, ++ IFN_VI1_DATA5, ++ FN_SCK4, ++ FN_D8, ++ FN_MMC_D3, ++ IFN_VI1_DATA6, ++ FN_RX4, ++ FN_D9, ++ FN_MMC_CLK, ++ IFN_VI1_DATA7, ++ FN_TX4, ++ FN_D10, ++ FN_MMC_D4, ++ IFN_VI1_DATA8, ++ FN_CTS4_N, ++ FN_D11, ++ FN_MMC_D5, ++ IFN_VI1_DATA9, ++ FN_RTS4_N_TANS, ++ FN_D12, ++ FN_MMC_D6, ++ FN_SCL3_B, ++ IFN_VI1_DATA10, ++ FN_D13, ++ FN_MMC_D7, ++ FN_SDA3_B, ++ IFN_VI1_DATA11, ++ FN_SCL4, ++ FN_IRQ4, ++ FN_D14, ++ FN_MMC_WP, ++ ++ /* IPSR7 */ ++ IFN_VI1_FIELD, ++ FN_SDA4, ++ FN_IRQ5, ++ FN_D15, ++ FN_MMC_CD, ++ IFN_SCL0, ++ FN_DU_DR0, ++ FN_TPU0TO0, ++ FN_CLKOUT, ++ FN_MSIOF0_RXD, ++ IFN_SDA0, ++ FN_DU_DR1, ++ FN_TPU0TO1, ++ FN_BS_N, ++ FN_SCK0, ++ FN_MSIOF0_TXD, ++ IFN_SCL1, ++ FN_DU_DG0, ++ FN_TPU0TO2, ++ FN_RD_N, ++ FN_CTS0_N, ++ FN_MSIOF0_SCK, ++ IFN_SDA1, ++ FN_DU_DG1, ++ FN_TPU0TO3, ++ FN_WE0_N, ++ FN_RTS0_N_TANS, ++ FN_MSIOF0_SYNC, ++ IFN_SCL2, ++ FN_DU_DB0, ++ FN_TCLK1_A, ++ FN_WE1_N, ++ FN_RX0, ++ FN_MSIOF0_SS1, ++ IFN_SDA2, ++ FN_DU_DB1, ++ FN_TCLK2_A, ++ FN_EX_WAIT0, ++ FN_TX0, ++ FN_MSIOF0_SS2, ++ IFN_AVB0_AVTP_CAPTURE, ++ FN_FSCLKST2_N_B, ++ ++ /* IPSR8 */ ++ IFN_CANFD0_TX_A, ++ FN_FXR_TXDA, ++ FN_PWM0_B, ++ FN_DU_DISP, ++ FN_FSCLKST2_N_C, ++ IFN_CANFD0_RX_A, ++ FN_RXDA_EXTFXR, ++ FN_PWM1_B, ++ FN_DU_CDE, ++ IFN_CANFD1_TX, ++ FN_FXR_TXDB, ++ FN_PWM2_B, ++ FN_TCLK1_B, ++ FN_TX1_B, ++ IFN_CANFD1_RX, ++ FN_RXDB_EXTFXR, ++ FN_PWM3_B, ++ FN_TCLK2_B, ++ FN_RX1_B, ++ IFN_CANFD_CLK_A, ++ FN_CLK_EXTFXR, ++ FN_PWM4_B, ++ FN_SPEEDIN_B, ++ FN_SCIF_CLK_B, ++ IFN_DIGRF_CLKIN, ++ FN_DIGRF_CLKEN_IN, ++ IFN_DIGRF_CLKOUT, ++ FN_DIGRF_CLKEN_OUT, ++ ++ /* MOD_SEL0 */ ++ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, ++ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, ++ FN_SEL_CANFD0_0, FN_SEL_CANFD0_1, ++ FN_SEL_PWM4_0, FN_SEL_PWM4_1, ++ FN_SEL_PWM3_0, FN_SEL_PWM3_1, ++ FN_SEL_PWM2_0, FN_SEL_PWM2_1, ++ FN_SEL_PWM1_0, FN_SEL_PWM1_1, ++ FN_SEL_PWM0_0, FN_SEL_PWM0_1, ++ FN_SEL_RFSO_0, FN_SEL_RFSO_1, ++ FN_SEL_RSP_0, FN_SEL_RSP_1, ++ FN_SEL_TMU_0, FN_SEL_TMU_1, ++ ++ PINMUX_FUNCTION_END, ++ ++ PINMUX_MARK_BEGIN, ++ ++ /* GPSR0 */ ++ DU_EXODDF_DU_ODDF_DISP_CDE_GMARK, ++ DU_EXVSYNC_DU_VSYNC_GMARK, ++ DU_EXHSYNC_DU_HSYNC_GMARK, ++ DU_DOTCLKOUT_GMARK, ++ DU_DB7_GMARK, ++ DU_DB6_GMARK, ++ DU_DB5_GMARK, ++ DU_DB4_GMARK, ++ DU_DB3_GMARK, ++ DU_DB2_GMARK, ++ DU_DG7_GMARK, ++ DU_DG6_GMARK, ++ DU_DG5_GMARK, ++ DU_DG4_GMARK, ++ DU_DG3_GMARK, ++ DU_DG2_GMARK, ++ DU_DR7_GMARK, ++ DU_DR6_GMARK, ++ DU_DR5_GMARK, ++ DU_DR4_GMARK, ++ DU_DR3_GMARK, ++ DU_DR2_GMARK, ++ ++ /* GPSR1 */ ++ DIGRF_CLKOUT_GMARK, ++ DIGRF_CLKIN_GMARK, ++ CANFD_CLK_A_GMARK, ++ CANFD1_RX_GMARK, ++ CANFD1_TX_GMARK, ++ CANFD0_RX_A_GMARK, ++ CANFD0_TX_A_GMARK, ++ AVB0_AVTP_CAPTURE_GMARK, ++ AVB0_AVTP_MATCH_MARK, ++ AVB0_LINK_MARK, ++ AVB0_PHY_INT_MARK, ++ AVB0_MAGIC_MARK, ++ AVB0_MDC_MARK, ++ AVB0_MDIO_MARK, ++ AVB0_TXCREFCLK_MARK, ++ AVB0_TD3_MARK, ++ AVB0_TD2_MARK, ++ AVB0_TD1_MARK, ++ AVB0_TD0_MARK, ++ AVB0_TXC_MARK, ++ AVB0_TX_CTL_MARK, ++ AVB0_RD3_MARK, ++ AVB0_RD2_MARK, ++ AVB0_RD1_MARK, ++ AVB0_RD0_MARK, ++ AVB0_RXC_MARK, ++ AVB0_RX_CTL_MARK, ++ IRQ0_GMARK, ++ ++ /* GPSR2 */ ++ VI0_FIELD_GMARK, ++ VI0_DATA11_GMARK, ++ VI0_DATA10_GMARK, ++ VI0_DATA9_GMARK, ++ VI0_DATA8_GMARK, ++ VI0_DATA7_GMARK, ++ VI0_DATA6_GMARK, ++ VI0_DATA5_GMARK, ++ VI0_DATA4_GMARK, ++ VI0_DATA3_GMARK, ++ VI0_DATA2_GMARK, ++ VI0_DATA1_GMARK, ++ VI0_DATA0_GMARK, ++ VI0_VSYNC_N_GMARK, ++ VI0_HSYNC_N_GMARK, ++ VI0_CLKENB_GMARK, ++ VI0_CLK_GMARK, ++ ++ /* GPSR3 */ ++ VI1_FIELD_GMARK, ++ VI1_DATA11_GMARK, ++ VI1_DATA10_GMARK, ++ VI1_DATA9_GMARK, ++ VI1_DATA8_GMARK, ++ VI1_DATA7_GMARK, ++ VI1_DATA6_GMARK, ++ VI1_DATA5_GMARK, ++ VI1_DATA4_GMARK, ++ VI1_DATA3_GMARK, ++ VI1_DATA2_GMARK, ++ VI1_DATA1_GMARK, ++ VI1_DATA0_GMARK, ++ VI1_VSYNC_N_GMARK, ++ VI1_HSYNC_N_GMARK, ++ VI1_CLKENB_GMARK, ++ VI1_CLK_GMARK, ++ ++ /* GPSR4 */ ++ SDA2_GMARK, ++ SCL2_GMARK, ++ SDA1_GMARK, ++ SCL1_GMARK, ++ SDA0_GMARK, ++ SCL0_GMARK, ++ ++ /* GPSR5 */ ++ RPC_INT_N_MARK, ++ RPC_WP_N_MARK, ++ RPC_RESET_N_MARK, ++ QSPI1_SSL_MARK, ++ QSPI1_IO3_MARK, ++ QSPI1_IO2_MARK, ++ QSPI1_MISO_IO1_MARK, ++ QSPI1_MOSI_IO0_MARK, ++ QSPI1_SPCLK_MARK, ++ QSPI0_SSL_MARK, ++ QSPI0_IO3_MARK, ++ QSPI0_IO2_MARK, ++ QSPI0_MISO_IO1_MARK, ++ QSPI0_MOSI_IO0_MARK, ++ QSPI0_SPCLK_MARK, ++ ++ /* IPSR0 */ ++ DU_DR2_IMARK, ++ HSCK0_MARK, ++ A0_MARK, ++ DU_DR3_IMARK, ++ HRTS0_N_MARK, ++ A1_MARK, ++ DU_DR4_IMARK, ++ HCTS0_N_MARK, ++ A2_MARK, ++ DU_DR5_IMARK, ++ HTX0_MARK, ++ A3_MARK, ++ DU_DR6_IMARK, ++ MSIOF3_RXD_MARK, ++ A4_MARK, ++ DU_DR7_IMARK, ++ MSIOF3_TXD_MARK, ++ A5_MARK, ++ DU_DG2_IMARK, ++ MSIOF3_SS1_MARK, ++ A6_MARK, ++ DU_DG3_IMARK, ++ MSIOF3_SS2_MARK, ++ A7_MARK, ++ PWMFSW0_MARK, ++ ++ /* IPSR1 */ ++ DU_DG4_IMARK, ++ A8_MARK, ++ FSO_CFE_0_N_A_MARK, ++ DU_DG5_IMARK, ++ A9_MARK, ++ FSO_CFE_1_N_A_MARK, ++ DU_DG6_IMARK, ++ A10_MARK, ++ FSO_TOE_N_A_MARK, ++ DU_DG7_IMARK, ++ A11_MARK, ++ IRQ1_MARK, ++ DU_DB2_IMARK, ++ A12_MARK, ++ IRQ2_MARK, ++ DU_DB3_IMARK, ++ A13_MARK, ++ FXR_CLKOUT1_MARK, ++ DU_DB4_IMARK, ++ A14_MARK, ++ FXR_CLKOUT2_MARK, ++ DU_DB5_IMARK, ++ A15_MARK, ++ FXR_TXENA_N_MARK, ++ ++ /* IPSR2 */ ++ DU_DB6_IMARK, ++ A16_MARK, ++ FXR_TXENB_N_MARK, ++ DU_DB7_IMARK, ++ A17_MARK, ++ STPWT_EXTFXR_MARK, ++ DU_DOTCLKOUT_IMARK, ++ SCIF_CLK_A_MARK, ++ A18_MARK, ++ DU_EXHSYNC_DU_HSYNC_IMARK, ++ HRX0_MARK, ++ A19_MARK, ++ IRQ3_MARK, ++ DU_EXVSYNC_DU_VSYNC_IMARK, ++ MSIOF3_SCK_MARK, ++ A20_MARK, ++ DU_EXODDF_DU_ODDF_DISP_CDE_IMARK, ++ MSIOF3_SYNC_MARK, ++ A21_MARK, ++ IRQ0_IMARK, ++ CC5_OSCOUT_MARK, ++ VI0_CLK_IMARK, ++ MSIOF2_SCK_MARK, ++ SCK3_MARK, ++ HSCK3_MARK, ++ ++ /* IPSR3 */ ++ VI0_CLKENB_IMARK, ++ MSIOF2_RXD_MARK, ++ RX3_MARK, ++ RD_WR_N_MARK, ++ HCTS3_N_MARK, ++ VI0_HSYNC_N_IMARK, ++ MSIOF2_TXD_MARK, ++ TX3_MARK, ++ HRTS3_N_MARK, ++ VI0_VSYNC_N_IMARK, ++ MSIOF2_SYNC_MARK, ++ CTS3_N_MARK, ++ HTX3_MARK, ++ VI0_DATA0_IMARK, ++ MSIOF2_SS1_MARK, ++ RTS3_N_TANS_MARK, ++ HRX3_MARK, ++ VI0_DATA1_IMARK, ++ MSIOF2_SS2_MARK, ++ SCK1_MARK, ++ SPEEDIN_A_MARK, ++ VI0_DATA2_IMARK, ++ AVB0_AVTP_PPS_MARK, ++ SDA3_A_MARK, ++ VI0_DATA3_IMARK, ++ HSCK1_MARK, ++ SCL3_A_MARK, ++ VI0_DATA4_IMARK, ++ HRTS1_N_MARK, ++ RX1_A_MARK, ++ ++ /* IPSR4 */ ++ VI0_DATA5_IMARK, ++ HCTS1_N_MARK, ++ TX1_A_MARK, ++ VI0_DATA6_IMARK, ++ HTX1_MARK, ++ CTS1_N_MARK, ++ VI0_DATA7_IMARK, ++ HRX1_MARK, ++ RTS1_N_TANS_MARK, ++ VI0_DATA8_IMARK, ++ HSCK2_MARK, ++ PWM0_A_MARK, ++ A22_MARK, ++ VI0_DATA9_IMARK, ++ HCTS2_N_MARK, ++ PWM1_A_MARK, ++ A23_MARK, ++ FSO_CFE_0_N_B_MARK, ++ VI0_DATA10_IMARK, ++ HRTS2_N_MARK, ++ PWM2_A_MARK, ++ A24_MARK, ++ FSO_CFE_1_N_B_MARK, ++ VI0_DATA11_IMARK, ++ HTX2_MARK, ++ PWM3_A_MARK, ++ A25_MARK, ++ FSO_TOE_N_B_MARK, ++ VI0_FIELD_IMARK, ++ HRX2_MARK, ++ PWM4_A_MARK, ++ CS1_N_A26_MARK, ++ FSCLKST2_N_A_MARK, ++ ++ /* IPSR5 */ ++ VI1_CLK_IMARK, ++ MSIOF1_RXD_MARK, ++ CS0_N_MARK, ++ VI1_CLKENB_IMARK, ++ MSIOF1_TXD_MARK, ++ D0_MARK, ++ VI1_HSYNC_N_IMARK, ++ MSIOF1_SCK_MARK, ++ D1_MARK, ++ VI1_VSYNC_N_IMARK, ++ MSIOF1_SYNC_MARK, ++ D2_MARK, ++ VI1_DATA0_IMARK, ++ MSIOF1_SS1_MARK, ++ D3_MARK, ++ VI1_DATA1_IMARK, ++ MSIOF1_SS2_MARK, ++ D4_MARK, ++ MMC_CMD_MARK, ++ VI1_DATA2_IMARK, ++ CANFD0_TX_B_MARK, ++ D5_MARK, ++ MMC_D0_MARK, ++ VI1_DATA3_IMARK, ++ CANFD0_RX_B_MARK, ++ D6_MARK, ++ MMC_D1_MARK, ++ ++ /* IPSR6 */ ++ VI1_DATA4_IMARK, ++ CANFD_CLK_B_MARK, ++ D7_MARK, ++ MMC_D2_MARK, ++ VI1_DATA5_IMARK, ++ SCK4_MARK, ++ D8_MARK, ++ MMC_D3_MARK, ++ VI1_DATA6_IMARK, ++ RX4_MARK, ++ D9_MARK, ++ MMC_CLK_MARK, ++ VI1_DATA7_IMARK, ++ TX4_MARK, ++ D10_MARK, ++ MMC_D4_MARK, ++ VI1_DATA8_IMARK, ++ CTS4_N_MARK, ++ D11_MARK, ++ MMC_D5_MARK, ++ VI1_DATA9_IMARK, ++ RTS4_N_TANS_MARK, ++ D12_MARK, ++ MMC_D6_MARK, ++ SCL3_B_MARK, ++ VI1_DATA10_IMARK, ++ D13_MARK, ++ MMC_D7_MARK, ++ SDA3_B_MARK, ++ VI1_DATA11_IMARK, ++ SCL4_MARK, ++ IRQ4_MARK, ++ D14_MARK, ++ MMC_WP_MARK, ++ ++ /* IPSR7 */ ++ VI1_FIELD_IMARK, ++ SDA4_MARK, ++ IRQ5_MARK, ++ D15_MARK, ++ MMC_CD_MARK, ++ SCL0_IMARK, ++ DU_DR0_MARK, ++ TPU0TO0_MARK, ++ CLKOUT_MARK, ++ MSIOF0_RXD_MARK, ++ SDA0_IMARK, ++ DU_DR1_MARK, ++ TPU0TO1_MARK, ++ BS_N_MARK, ++ SCK0_MARK, ++ MSIOF0_TXD_MARK, ++ SCL1_IMARK, ++ DU_DG0_MARK, ++ TPU0TO2_MARK, ++ RD_N_MARK, ++ CTS0_N_MARK, ++ MSIOF0_SCK_MARK, ++ SDA1_IMARK, ++ DU_DG1_MARK, ++ TPU0TO3_MARK, ++ WE0_N_MARK, ++ RTS0_N_TANS_MARK, ++ MSIOF0_SYNC_MARK, ++ SCL2_IMARK, ++ DU_DB0_MARK, ++ TCLK1_A_MARK, ++ WE1_N_MARK, ++ RX0_MARK, ++ MSIOF0_SS1_MARK, ++ SDA2_IMARK, ++ DU_DB1_MARK, ++ TCLK2_A_MARK, ++ EX_WAIT0_MARK, ++ TX0_MARK, ++ MSIOF0_SS2_MARK, ++ AVB0_AVTP_CAPTURE_IMARK, ++ FSCLKST2_N_B_MARK, ++ ++ /* IPSR8 */ ++ CANFD0_TX_A_IMARK, ++ FXR_TXDA_MARK, ++ PWM0_B_MARK, ++ DU_DISP_MARK, ++ FSCLKST2_N_C_MARK, ++ CANFD0_RX_A_IMARK, ++ RXDA_EXTFXR_MARK, ++ PWM1_B_MARK, ++ DU_CDE_MARK, ++ CANFD1_TX_IMARK, ++ FXR_TXDB_MARK, ++ PWM2_B_MARK, ++ TCLK1_B_MARK, ++ TX1_B_MARK, ++ CANFD1_RX_IMARK, ++ RXDB_EXTFXR_MARK, ++ PWM3_B_MARK, ++ TCLK2_B_MARK, ++ RX1_B_MARK, ++ CANFD_CLK_A_IMARK, ++ CLK_EXTFXR_MARK, ++ PWM4_B_MARK, ++ SPEEDIN_B_MARK, ++ SCIF_CLK_B_MARK, ++ DIGRF_CLKIN_IMARK, ++ DIGRF_CLKEN_IN_MARK, ++ DIGRF_CLKOUT_IMARK, ++ DIGRF_CLKEN_OUT_MARK, ++ ++ PINMUX_MARK_END, ++}; ++ ++static pinmux_enum_t pinmux_data[] = { ++ PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ ++ ++ /* GPSR0 */ ++ PINMUX_DATA(DU_EXODDF_DU_ODDF_DISP_CDE_GMARK, GFN_DU_EXODDF_DU_ODDF_DISP_CDE), ++ PINMUX_DATA(DU_EXVSYNC_DU_VSYNC_GMARK, GFN_DU_EXVSYNC_DU_VSYNC), ++ PINMUX_DATA(DU_EXHSYNC_DU_HSYNC_GMARK, GFN_DU_EXHSYNC_DU_HSYNC), ++ PINMUX_DATA(DU_DOTCLKOUT_GMARK, GFN_DU_DOTCLKOUT), ++ PINMUX_DATA(DU_DB7_GMARK, GFN_DU_DB7), ++ PINMUX_DATA(DU_DB6_GMARK, GFN_DU_DB6), ++ PINMUX_DATA(DU_DB5_GMARK, GFN_DU_DB5), ++ PINMUX_DATA(DU_DB4_GMARK, GFN_DU_DB4), ++ PINMUX_DATA(DU_DB3_GMARK, GFN_DU_DB3), ++ PINMUX_DATA(DU_DB2_GMARK, GFN_DU_DB2), ++ PINMUX_DATA(DU_DG7_GMARK, GFN_DU_DG7), ++ PINMUX_DATA(DU_DG6_GMARK, GFN_DU_DG6), ++ PINMUX_DATA(DU_DG5_GMARK, GFN_DU_DG5), ++ PINMUX_DATA(DU_DG4_GMARK, GFN_DU_DG4), ++ PINMUX_DATA(DU_DG3_GMARK, GFN_DU_DG3), ++ PINMUX_DATA(DU_DG2_GMARK, GFN_DU_DG2), ++ PINMUX_DATA(DU_DR7_GMARK, GFN_DU_DR7), ++ PINMUX_DATA(DU_DR6_GMARK, GFN_DU_DR6), ++ PINMUX_DATA(DU_DR5_GMARK, GFN_DU_DR5), ++ PINMUX_DATA(DU_DR4_GMARK, GFN_DU_DR4), ++ PINMUX_DATA(DU_DR3_GMARK, GFN_DU_DR3), ++ PINMUX_DATA(DU_DR2_GMARK, GFN_DU_DR2), ++ ++ /* GPSR1 */ ++ PINMUX_DATA(DIGRF_CLKOUT_GMARK, GFN_DIGRF_CLKOUT), ++ PINMUX_DATA(DIGRF_CLKIN_GMARK, GFN_DIGRF_CLKIN), ++ PINMUX_DATA(CANFD_CLK_A_GMARK, GFN_CANFD_CLK_A), ++ PINMUX_DATA(CANFD1_RX_GMARK, GFN_CANFD1_RX), ++ PINMUX_DATA(CANFD1_TX_GMARK, GFN_CANFD1_TX), ++ PINMUX_DATA(CANFD0_RX_A_GMARK, GFN_CANFD0_RX_A), ++ PINMUX_DATA(CANFD0_TX_A_GMARK, GFN_CANFD0_TX_A), ++ PINMUX_DATA(AVB0_AVTP_CAPTURE_GMARK, GFN_AVB0_AVTP_CAPTURE), ++ PINMUX_DATA(AVB0_AVTP_MATCH_MARK, FN_AVB0_AVTP_MATCH), ++ PINMUX_DATA(AVB0_LINK_MARK, FN_AVB0_LINK), ++ PINMUX_DATA(AVB0_PHY_INT_MARK, FN_AVB0_PHY_INT), ++ PINMUX_DATA(AVB0_MAGIC_MARK, FN_AVB0_MAGIC), ++ PINMUX_DATA(AVB0_MDC_MARK, FN_AVB0_MDC), ++ PINMUX_DATA(AVB0_MDIO_MARK, FN_AVB0_MDIO), ++ PINMUX_DATA(AVB0_TXCREFCLK_MARK, FN_AVB0_TXCREFCLK), ++ PINMUX_DATA(AVB0_TD3_MARK, FN_AVB0_TD3), ++ PINMUX_DATA(AVB0_TD2_MARK, FN_AVB0_TD2), ++ PINMUX_DATA(AVB0_TD1_MARK, FN_AVB0_TD1), ++ PINMUX_DATA(AVB0_TD0_MARK, FN_AVB0_TD0), ++ PINMUX_DATA(AVB0_TXC_MARK, FN_AVB0_TXC), ++ PINMUX_DATA(AVB0_TX_CTL_MARK, FN_AVB0_TX_CTL), ++ PINMUX_DATA(AVB0_RD3_MARK, FN_AVB0_RD3), ++ PINMUX_DATA(AVB0_RD2_MARK, FN_AVB0_RD2), ++ PINMUX_DATA(AVB0_RD1_MARK, FN_AVB0_RD1), ++ PINMUX_DATA(AVB0_RD0_MARK, FN_AVB0_RD0), ++ PINMUX_DATA(AVB0_RXC_MARK, FN_AVB0_RXC), ++ PINMUX_DATA(AVB0_RX_CTL_MARK, FN_AVB0_RX_CTL), ++ PINMUX_DATA(IRQ0_GMARK, GFN_IRQ0), ++ ++ /* GPSR2 */ ++ PINMUX_DATA(VI0_FIELD_GMARK, GFN_VI0_FIELD), ++ PINMUX_DATA(VI0_DATA11_GMARK, GFN_VI0_DATA11), ++ PINMUX_DATA(VI0_DATA10_GMARK, GFN_VI0_DATA10), ++ PINMUX_DATA(VI0_DATA9_GMARK, GFN_VI0_DATA9), ++ PINMUX_DATA(VI0_DATA8_GMARK, GFN_VI0_DATA8), ++ PINMUX_DATA(VI0_DATA7_GMARK, GFN_VI0_DATA7), ++ PINMUX_DATA(VI0_DATA6_GMARK, GFN_VI0_DATA6), ++ PINMUX_DATA(VI0_DATA5_GMARK, GFN_VI0_DATA5), ++ PINMUX_DATA(VI0_DATA4_GMARK, GFN_VI0_DATA4), ++ PINMUX_DATA(VI0_DATA3_GMARK, GFN_VI0_DATA3), ++ PINMUX_DATA(VI0_DATA2_GMARK, GFN_VI0_DATA2), ++ PINMUX_DATA(VI0_DATA1_GMARK, GFN_VI0_DATA1), ++ PINMUX_DATA(VI0_DATA0_GMARK, GFN_VI0_DATA0), ++ PINMUX_DATA(VI0_VSYNC_N_GMARK, GFN_VI0_VSYNC_N), ++ PINMUX_DATA(VI0_HSYNC_N_GMARK, GFN_VI0_HSYNC_N), ++ PINMUX_DATA(VI0_CLKENB_GMARK, GFN_VI0_CLKENB), ++ PINMUX_DATA(VI0_CLK_GMARK, GFN_VI0_CLK), ++ ++ /* GPSR3 */ ++ PINMUX_DATA(VI1_FIELD_GMARK, GFN_VI1_FIELD), ++ PINMUX_DATA(VI1_DATA11_GMARK, GFN_VI1_DATA11), ++ PINMUX_DATA(VI1_DATA10_GMARK, GFN_VI1_DATA10), ++ PINMUX_DATA(VI1_DATA9_GMARK, GFN_VI1_DATA9), ++ PINMUX_DATA(VI1_DATA8_GMARK, GFN_VI1_DATA8), ++ PINMUX_DATA(VI1_DATA7_GMARK, GFN_VI1_DATA7), ++ PINMUX_DATA(VI1_DATA6_GMARK, GFN_VI1_DATA6), ++ PINMUX_DATA(VI1_DATA5_GMARK, GFN_VI1_DATA5), ++ PINMUX_DATA(VI1_DATA4_GMARK, GFN_VI1_DATA4), ++ PINMUX_DATA(VI1_DATA3_GMARK, GFN_VI1_DATA3), ++ PINMUX_DATA(VI1_DATA2_GMARK, GFN_VI1_DATA2), ++ PINMUX_DATA(VI1_DATA1_GMARK, GFN_VI1_DATA1), ++ PINMUX_DATA(VI1_DATA0_GMARK, GFN_VI1_DATA0), ++ PINMUX_DATA(VI1_VSYNC_N_GMARK, GFN_VI1_VSYNC_N), ++ PINMUX_DATA(VI1_HSYNC_N_GMARK, GFN_VI1_HSYNC_N), ++ PINMUX_DATA(VI1_CLKENB_GMARK, GFN_VI1_CLKENB), ++ PINMUX_DATA(VI1_CLK_GMARK, GFN_VI1_CLK), ++ ++ /* GPSR4 */ ++ PINMUX_DATA(SDA2_GMARK, GFN_SDA2), ++ PINMUX_DATA(SCL2_GMARK, GFN_SCL2), ++ PINMUX_DATA(SDA1_GMARK, GFN_SDA1), ++ PINMUX_DATA(SCL1_GMARK, GFN_SCL1), ++ PINMUX_DATA(SDA0_GMARK, GFN_SDA0), ++ PINMUX_DATA(SCL0_GMARK, GFN_SCL0), ++ ++ /* GPSR5 */ ++ PINMUX_DATA(RPC_INT_N_MARK, FN_RPC_INT_N), ++ PINMUX_DATA(RPC_WP_N_MARK, FN_RPC_WP_N), ++ PINMUX_DATA(RPC_RESET_N_MARK, FN_RPC_RESET_N), ++ PINMUX_DATA(QSPI1_SSL_MARK, FN_QSPI1_SSL), ++ PINMUX_DATA(QSPI1_IO3_MARK, FN_QSPI1_IO3), ++ PINMUX_DATA(QSPI1_IO2_MARK, FN_QSPI1_IO2), ++ PINMUX_DATA(QSPI1_MISO_IO1_MARK, FN_QSPI1_MISO_IO1), ++ PINMUX_DATA(QSPI1_MOSI_IO0_MARK, FN_QSPI1_MOSI_IO0), ++ PINMUX_DATA(QSPI1_SPCLK_MARK, FN_QSPI1_SPCLK), ++ PINMUX_DATA(QSPI0_SSL_MARK, FN_QSPI0_SSL), ++ PINMUX_DATA(QSPI0_IO3_MARK, FN_QSPI0_IO3), ++ PINMUX_DATA(QSPI0_IO2_MARK, FN_QSPI0_IO2), ++ PINMUX_DATA(QSPI0_MISO_IO1_MARK, FN_QSPI0_MISO_IO1), ++ PINMUX_DATA(QSPI0_MOSI_IO0_MARK, FN_QSPI0_MOSI_IO0), ++ PINMUX_DATA(QSPI0_SPCLK_MARK, FN_QSPI0_SPCLK), ++ ++ ++ /* IPSR0 */ ++ PINMUX_IPSR_IDATA(DU_DR2), ++ PINMUX_IPSR_DATA(DU_DR2, HSCK0), ++ PINMUX_IPSR_DATA(DU_DR2, A0), ++ PINMUX_IPSR_IDATA(DU_DR3), ++ PINMUX_IPSR_DATA(DU_DR3, HRTS0_N), ++ PINMUX_IPSR_DATA(DU_DR3, A1), ++ PINMUX_IPSR_IDATA(DU_DR4), ++ PINMUX_IPSR_DATA(DU_DR4, HCTS0_N), ++ PINMUX_IPSR_DATA(DU_DR4, A2), ++ PINMUX_IPSR_IDATA(DU_DR5), ++ PINMUX_IPSR_DATA(DU_DR5, HTX0), ++ PINMUX_IPSR_DATA(DU_DR5, A3), ++ PINMUX_IPSR_IDATA(DU_DR6), ++ PINMUX_IPSR_DATA(DU_DR6, MSIOF3_RXD), ++ PINMUX_IPSR_DATA(DU_DR6, A4), ++ PINMUX_IPSR_IDATA(DU_DR7), ++ PINMUX_IPSR_DATA(DU_DR7, MSIOF3_TXD), ++ PINMUX_IPSR_DATA(DU_DR7, A5), ++ PINMUX_IPSR_IDATA(DU_DG2), ++ PINMUX_IPSR_DATA(DU_DG2, MSIOF3_SS1), ++ PINMUX_IPSR_DATA(DU_DG2, A6), ++ PINMUX_IPSR_IDATA(DU_DG3), ++ PINMUX_IPSR_DATA(DU_DG3, MSIOF3_SS2), ++ PINMUX_IPSR_DATA(DU_DG3, A7), ++ PINMUX_IPSR_DATA(DU_DG3, PWMFSW0), ++ ++ /* IPSR1 */ ++ PINMUX_IPSR_IDATA(DU_DG4), ++ PINMUX_IPSR_DATA(DU_DG4, A8), ++ PINMUX_IPSR_DATA(DU_DG4, FSO_CFE_0_N_A), ++ PINMUX_IPSR_IDATA(DU_DG5), ++ PINMUX_IPSR_DATA(DU_DG5, A9), ++ PINMUX_IPSR_DATA(DU_DG5, FSO_CFE_1_N_A), ++ PINMUX_IPSR_IDATA(DU_DG6), ++ PINMUX_IPSR_DATA(DU_DG6, A10), ++ PINMUX_IPSR_DATA(DU_DG6, FSO_TOE_N_A), ++ PINMUX_IPSR_IDATA(DU_DG7), ++ PINMUX_IPSR_DATA(DU_DG7, A11), ++ PINMUX_IPSR_DATA(DU_DG7, IRQ1), ++ PINMUX_IPSR_IDATA(DU_DB2), ++ PINMUX_IPSR_DATA(DU_DB2, A12), ++ PINMUX_IPSR_DATA(DU_DB2, IRQ2), ++ PINMUX_IPSR_IDATA(DU_DB3), ++ PINMUX_IPSR_DATA(DU_DB3, A13), ++ PINMUX_IPSR_DATA(DU_DB3, FXR_CLKOUT1), ++ PINMUX_IPSR_IDATA(DU_DB4), ++ PINMUX_IPSR_DATA(DU_DB4, A14), ++ PINMUX_IPSR_DATA(DU_DB4, FXR_CLKOUT2), ++ PINMUX_IPSR_IDATA(DU_DB5), ++ PINMUX_IPSR_DATA(DU_DB5, A15), ++ PINMUX_IPSR_DATA(DU_DB5, FXR_TXENA_N), ++ ++ /* IPSR2 */ ++ PINMUX_IPSR_IDATA(DU_DB6), ++ PINMUX_IPSR_DATA(DU_DB6, A16), ++ PINMUX_IPSR_DATA(DU_DB6, FXR_TXENB_N), ++ PINMUX_IPSR_IDATA(DU_DB7), ++ PINMUX_IPSR_DATA(DU_DB7, A17), ++ PINMUX_IPSR_DATA(DU_DB7, STPWT_EXTFXR), ++ PINMUX_IPSR_IDATA(DU_DOTCLKOUT), ++ PINMUX_IPSR_DATA(DU_DOTCLKOUT, SCIF_CLK_A), ++ PINMUX_IPSR_DATA(DU_DOTCLKOUT, A18), ++ PINMUX_IPSR_IDATA(DU_EXHSYNC_DU_HSYNC), ++ PINMUX_IPSR_DATA(DU_EXHSYNC_DU_HSYNC, HRX0), ++ PINMUX_IPSR_DATA(DU_EXHSYNC_DU_HSYNC, A19), ++ PINMUX_IPSR_DATA(DU_EXHSYNC_DU_HSYNC, IRQ3), ++ PINMUX_IPSR_IDATA(DU_EXVSYNC_DU_VSYNC), ++ PINMUX_IPSR_DATA(DU_EXVSYNC_DU_VSYNC, MSIOF3_SCK), ++ PINMUX_IPSR_DATA(DU_EXVSYNC_DU_VSYNC, A20), ++ PINMUX_IPSR_IDATA(DU_EXODDF_DU_ODDF_DISP_CDE), ++ PINMUX_IPSR_DATA(DU_EXODDF_DU_ODDF_DISP_CDE, MSIOF3_SYNC), ++ PINMUX_IPSR_DATA(DU_EXODDF_DU_ODDF_DISP_CDE, A21), ++ PINMUX_IPSR_IDATA(IRQ0), ++ PINMUX_IPSR_DATA(IRQ0, CC5_OSCOUT), ++ PINMUX_IPSR_IDATA(VI0_CLK), ++ PINMUX_IPSR_DATA(VI0_CLK, MSIOF2_SCK), ++ PINMUX_IPSR_DATA(VI0_CLK, SCK3), ++ PINMUX_IPSR_DATA(VI0_CLK, HSCK3), ++ ++ /* IPSR3 */ ++ PINMUX_IPSR_IDATA(VI0_CLKENB), ++ PINMUX_IPSR_DATA(VI0_CLKENB, MSIOF2_RXD), ++ PINMUX_IPSR_DATA(VI0_CLKENB, RX3), ++ PINMUX_IPSR_DATA(VI0_CLKENB, RD_WR_N), ++ PINMUX_IPSR_DATA(VI0_CLKENB, HCTS3_N), ++ PINMUX_IPSR_IDATA(VI0_HSYNC_N), ++ PINMUX_IPSR_DATA(VI0_HSYNC_N, MSIOF2_TXD), ++ PINMUX_IPSR_DATA(VI0_HSYNC_N, TX3), ++ PINMUX_IPSR_DATA(VI0_HSYNC_N, HRTS3_N), ++ PINMUX_IPSR_IDATA(VI0_VSYNC_N), ++ PINMUX_IPSR_DATA(VI0_VSYNC_N, MSIOF2_SYNC), ++ PINMUX_IPSR_DATA(VI0_VSYNC_N, CTS3_N), ++ PINMUX_IPSR_DATA(VI0_VSYNC_N, HTX3), ++ PINMUX_IPSR_IDATA(VI0_DATA0), ++ PINMUX_IPSR_DATA(VI0_DATA0, MSIOF2_SS1), ++ PINMUX_IPSR_DATA(VI0_DATA0, RTS3_N_TANS), ++ PINMUX_IPSR_DATA(VI0_DATA0, HRX3), ++ PINMUX_IPSR_IDATA(VI0_DATA1), ++ PINMUX_IPSR_DATA(VI0_DATA1, MSIOF2_SS2), ++ PINMUX_IPSR_DATA(VI0_DATA3, SCK1), ++ PINMUX_IPSR_DATA(VI0_DATA1, SPEEDIN_A), ++ PINMUX_IPSR_IDATA(VI0_DATA2), ++ PINMUX_IPSR_DATA(VI0_DATA2, AVB0_AVTP_PPS), ++ PINMUX_IPSR_DATA(VI0_DATA2, SDA3_A), ++ PINMUX_IPSR_IDATA(VI0_DATA3), ++ PINMUX_IPSR_DATA(VI0_DATA3, HSCK1), ++ PINMUX_IPSR_DATA(VI0_DATA1, SCL3_A), ++ PINMUX_IPSR_IDATA(VI0_DATA4), ++ PINMUX_IPSR_DATA(VI0_DATA4, HRTS1_N), ++ PINMUX_IPSR_DATA(VI0_DATA4, RX1_A), ++ ++ /* IPSR4 */ ++ PINMUX_IPSR_IDATA(VI0_DATA5), ++ PINMUX_IPSR_DATA(VI0_DATA5, HCTS1_N), ++ PINMUX_IPSR_DATA(VI0_DATA5, TX1_A), ++ PINMUX_IPSR_IDATA(VI0_DATA6), ++ PINMUX_IPSR_DATA(VI0_DATA6, HTX1), ++ PINMUX_IPSR_DATA(VI0_DATA6, CTS1_N), ++ PINMUX_IPSR_IDATA(VI0_DATA7), ++ PINMUX_IPSR_DATA(VI0_DATA7, HRX1), ++ PINMUX_IPSR_DATA(VI0_DATA7, RTS1_N_TANS), ++ PINMUX_IPSR_IDATA(VI0_DATA8), ++ PINMUX_IPSR_DATA(VI0_DATA8, HSCK2), ++ PINMUX_IPSR_DATA(VI0_DATA8, PWM0_A), ++ PINMUX_IPSR_DATA(VI0_DATA8, A22), ++ PINMUX_IPSR_IDATA(VI0_DATA9), ++ PINMUX_IPSR_DATA(VI0_DATA9, HCTS2_N), ++ PINMUX_IPSR_DATA(VI0_DATA9, PWM1_A), ++ PINMUX_IPSR_DATA(VI0_DATA9, A23), ++ PINMUX_IPSR_DATA(VI0_DATA9, FSO_CFE_0_N_B), ++ PINMUX_IPSR_IDATA(VI0_DATA10), ++ PINMUX_IPSR_DATA(VI0_DATA10, HRTS2_N), ++ PINMUX_IPSR_DATA(VI0_DATA10, PWM2_A), ++ PINMUX_IPSR_DATA(VI0_DATA10, A24), ++ PINMUX_IPSR_DATA(VI0_DATA10, FSO_CFE_1_N_B), ++ PINMUX_IPSR_IDATA(VI0_DATA11), ++ PINMUX_IPSR_DATA(VI0_DATA11, HTX2), ++ PINMUX_IPSR_DATA(VI0_DATA11, PWM3_A), ++ PINMUX_IPSR_DATA(VI0_DATA11, A25), ++ PINMUX_IPSR_DATA(VI0_DATA11, FSO_TOE_N_B), ++ PINMUX_IPSR_IDATA(VI0_FIELD), ++ PINMUX_IPSR_DATA(VI0_FIELD, HRX2), ++ PINMUX_IPSR_DATA(VI0_FIELD, PWM4_A), ++ PINMUX_IPSR_DATA(VI0_FIELD, CS1_N_A26), ++ PINMUX_IPSR_DATA(VI0_FIELD, FSCLKST2_N_A), ++ ++ /* IPSR5 */ ++ PINMUX_IPSR_IDATA(VI1_CLK), ++ PINMUX_IPSR_DATA(VI1_CLK, MSIOF1_RXD), ++ PINMUX_IPSR_DATA(VI1_CLK, CS0_N), ++ PINMUX_IPSR_IDATA(VI1_CLKENB), ++ PINMUX_IPSR_DATA(VI1_CLKENB, MSIOF1_TXD), ++ PINMUX_IPSR_DATA(VI1_CLKENB, D0), ++ PINMUX_IPSR_IDATA(VI1_HSYNC_N), ++ PINMUX_IPSR_DATA(VI1_HSYNC_N, MSIOF1_SCK), ++ PINMUX_IPSR_DATA(VI1_HSYNC_N, D1), ++ PINMUX_IPSR_IDATA(VI1_VSYNC_N), ++ PINMUX_IPSR_DATA(VI1_VSYNC_N, MSIOF1_SYNC), ++ PINMUX_IPSR_DATA(VI1_VSYNC_N, D2), ++ PINMUX_IPSR_IDATA(VI1_DATA0), ++ PINMUX_IPSR_DATA(VI1_DATA0, MSIOF1_SS1), ++ PINMUX_IPSR_DATA(VI1_DATA0, D3), ++ PINMUX_IPSR_IDATA(VI1_DATA1), ++ PINMUX_IPSR_DATA(VI1_DATA1, MSIOF1_SS2), ++ PINMUX_IPSR_DATA(VI1_DATA1, D4), ++ PINMUX_IPSR_DATA(VI1_DATA1, MMC_CMD), ++ PINMUX_IPSR_IDATA(VI1_DATA2), ++ PINMUX_IPSR_DATA(VI1_DATA2, CANFD0_TX_B), ++ PINMUX_IPSR_DATA(VI1_DATA2, D5), ++ PINMUX_IPSR_DATA(VI1_DATA2, MMC_D0), ++ PINMUX_IPSR_IDATA(VI1_DATA3), ++ PINMUX_IPSR_DATA(VI1_DATA3, CANFD0_RX_B), ++ PINMUX_IPSR_DATA(VI1_DATA3, D6), ++ PINMUX_IPSR_DATA(VI1_DATA3, MMC_D1), ++ ++ /* IPSR6 */ ++ PINMUX_IPSR_IDATA(VI1_DATA4), ++ PINMUX_IPSR_DATA(VI1_DATA4, CANFD_CLK_B), ++ PINMUX_IPSR_DATA(VI1_DATA4, D7), ++ PINMUX_IPSR_DATA(VI1_DATA4, MMC_D2), ++ PINMUX_IPSR_IDATA(VI1_DATA5), ++ PINMUX_IPSR_DATA(VI1_DATA5, SCK4), ++ PINMUX_IPSR_DATA(VI1_DATA5, D8), ++ PINMUX_IPSR_DATA(VI1_DATA5, MMC_D3), ++ PINMUX_IPSR_IDATA(VI1_DATA6), ++ PINMUX_IPSR_DATA(VI1_DATA6, RX4), ++ PINMUX_IPSR_DATA(VI1_DATA6, D9), ++ PINMUX_IPSR_DATA(VI1_DATA6, MMC_CLK), ++ PINMUX_IPSR_IDATA(VI1_DATA7), ++ PINMUX_IPSR_DATA(VI1_DATA7, TX4), ++ PINMUX_IPSR_DATA(VI1_DATA7, D10), ++ PINMUX_IPSR_DATA(VI1_DATA7, MMC_D4), ++ PINMUX_IPSR_IDATA(VI1_DATA8), ++ PINMUX_IPSR_DATA(VI1_DATA8, CTS4_N), ++ PINMUX_IPSR_DATA(VI1_DATA8, D11), ++ PINMUX_IPSR_DATA(VI1_DATA8, MMC_D5), ++ PINMUX_IPSR_IDATA(VI1_DATA9), ++ PINMUX_IPSR_DATA(VI1_DATA9, RTS4_N_TANS), ++ PINMUX_IPSR_DATA(VI1_DATA9, D12), ++ PINMUX_IPSR_DATA(VI1_DATA9, MMC_D6), ++ PINMUX_IPSR_DATA(VI1_DATA9, SCL3_B), ++ PINMUX_IPSR_IDATA(VI1_DATA10), ++ PINMUX_IPSR_DATA(VI1_DATA10, D13), ++ PINMUX_IPSR_DATA(VI1_DATA10, MMC_D7), ++ PINMUX_IPSR_DATA(VI1_DATA10, SDA3_B), ++ PINMUX_IPSR_IDATA(VI1_DATA11), ++ PINMUX_IPSR_DATA(VI1_DATA11, SCL4), ++ PINMUX_IPSR_DATA(VI1_DATA11, IRQ4), ++ PINMUX_IPSR_DATA(VI1_DATA11, D14), ++ PINMUX_IPSR_DATA(VI1_DATA11, MMC_WP), ++ ++ /* IPSR7 */ ++ PINMUX_IPSR_IDATA(VI1_FIELD), ++ PINMUX_IPSR_DATA(VI1_FIELD, SDA4), ++ PINMUX_IPSR_DATA(VI1_FIELD, IRQ5), ++ PINMUX_IPSR_DATA(VI1_FIELD, D15), ++ PINMUX_IPSR_DATA(VI1_FIELD, MMC_CD), ++ PINMUX_IPSR_IDATA(SCL0), ++ PINMUX_IPSR_DATA(SCL0, DU_DR0), ++ PINMUX_IPSR_DATA(SCL0, TPU0TO0), ++ PINMUX_IPSR_DATA(SCL0, CLKOUT), ++ PINMUX_IPSR_DATA(SCL0, MSIOF0_RXD), ++ PINMUX_IPSR_IDATA(SDA0), ++ PINMUX_IPSR_DATA(SDA0, DU_DR1), ++ PINMUX_IPSR_DATA(SDA0, TPU0TO1), ++ PINMUX_IPSR_DATA(SDA0, BS_N), ++ PINMUX_IPSR_DATA(SDA0, SCK0), ++ PINMUX_IPSR_DATA(SDA0, MSIOF0_TXD), ++ PINMUX_IPSR_IDATA(SCL1), ++ PINMUX_IPSR_DATA(SCL1, DU_DG0), ++ PINMUX_IPSR_DATA(SCL1, TPU0TO2), ++ PINMUX_IPSR_DATA(SCL1, RD_N), ++ PINMUX_IPSR_DATA(SCL1, CTS0_N), ++ PINMUX_IPSR_DATA(SCL1, MSIOF0_SCK), ++ PINMUX_IPSR_IDATA(SDA1), ++ PINMUX_IPSR_DATA(SDA1, DU_DG1), ++ PINMUX_IPSR_DATA(SDA1, TPU0TO3), ++ PINMUX_IPSR_DATA(SDA1, WE0_N), ++ PINMUX_IPSR_DATA(SDA1, RTS0_N_TANS), ++ PINMUX_IPSR_DATA(SDA1, MSIOF0_SYNC), ++ PINMUX_IPSR_IDATA(SCL2), ++ PINMUX_IPSR_DATA(SCL2, DU_DB0), ++ PINMUX_IPSR_DATA(SCL2, TCLK1_A), ++ PINMUX_IPSR_DATA(SCL2, WE1_N), ++ PINMUX_IPSR_DATA(SCL2, RX0), ++ PINMUX_IPSR_DATA(SCL2, MSIOF0_SS1), ++ PINMUX_IPSR_IDATA(SDA2), ++ PINMUX_IPSR_DATA(SDA2, DU_DB1), ++ PINMUX_IPSR_DATA(SDA2, TCLK2_A), ++ PINMUX_IPSR_DATA(SDA2, EX_WAIT0), ++ PINMUX_IPSR_DATA(SDA2, TX0), ++ PINMUX_IPSR_DATA(SDA2, MSIOF0_SS2), ++ PINMUX_IPSR_IDATA(AVB0_AVTP_CAPTURE), ++ PINMUX_IPSR_DATA(AVB0_AVTP_CAPTURE, FSCLKST2_N_B), ++ ++ /* IPSR8 */ ++ PINMUX_IPSR_IDATA(CANFD0_TX_A), ++ PINMUX_IPSR_DATA(CANFD0_TX_A, FXR_TXDA), ++ PINMUX_IPSR_DATA(CANFD0_TX_A, PWM0_B), ++ PINMUX_IPSR_DATA(CANFD0_TX_A, DU_DISP), ++ PINMUX_IPSR_DATA(CANFD0_TX_A, FSCLKST2_N_C), ++ PINMUX_IPSR_IDATA(CANFD0_RX_A), ++ PINMUX_IPSR_DATA(CANFD0_RX_A, RXDA_EXTFXR), ++ PINMUX_IPSR_DATA(CANFD0_RX_A, PWM1_B), ++ PINMUX_IPSR_DATA(CANFD0_RX_A, DU_CDE), ++ PINMUX_IPSR_IDATA(CANFD1_TX), ++ PINMUX_IPSR_DATA(CANFD1_TX, FXR_TXDB), ++ PINMUX_IPSR_DATA(CANFD1_TX, PWM2_B), ++ PINMUX_IPSR_DATA(CANFD1_TX, TCLK1_B), ++ PINMUX_IPSR_DATA(CANFD1_TX, TX1_B), ++ PINMUX_IPSR_IDATA(CANFD1_RX), ++ PINMUX_IPSR_DATA(CANFD1_RX, RXDB_EXTFXR), ++ PINMUX_IPSR_DATA(CANFD1_RX, PWM3_B), ++ PINMUX_IPSR_DATA(CANFD1_RX, TCLK2_B), ++ PINMUX_IPSR_DATA(CANFD1_RX, RX1_B), ++ PINMUX_IPSR_IDATA(CANFD_CLK_A), ++ PINMUX_IPSR_DATA(CANFD_CLK_A, CLK_EXTFXR), ++ PINMUX_IPSR_DATA(CANFD_CLK_A, PWM4_B), ++ PINMUX_IPSR_DATA(CANFD_CLK_A, SPEEDIN_B), ++ PINMUX_IPSR_DATA(CANFD_CLK_A, SCIF_CLK_B), ++ PINMUX_IPSR_IDATA(DIGRF_CLKIN), ++ PINMUX_IPSR_DATA(DIGRF_CLKIN, DIGRF_CLKEN_IN), ++ PINMUX_IPSR_IDATA(DIGRF_CLKOUT), ++ PINMUX_IPSR_DATA(DIGRF_CLKOUT, DIGRF_CLKEN_OUT), ++}; ++ ++static struct pinmux_gpio pinmux_gpios[] = { ++ PINMUX_GPIO_GP_ALL(), ++ ++ /* GPSR0 */ ++ GPIO_GFN(DU_EXODDF_DU_ODDF_DISP_CDE), ++ GPIO_GFN(DU_EXVSYNC_DU_VSYNC), ++ GPIO_GFN(DU_EXHSYNC_DU_HSYNC), ++ GPIO_GFN(DU_DOTCLKOUT), ++ GPIO_GFN(DU_DB7), ++ GPIO_GFN(DU_DB6), ++ GPIO_GFN(DU_DB5), ++ GPIO_GFN(DU_DB4), ++ GPIO_GFN(DU_DB3), ++ GPIO_GFN(DU_DB2), ++ GPIO_GFN(DU_DG7), ++ GPIO_GFN(DU_DG6), ++ GPIO_GFN(DU_DG5), ++ GPIO_GFN(DU_DG4), ++ GPIO_GFN(DU_DG3), ++ GPIO_GFN(DU_DG2), ++ GPIO_GFN(DU_DR7), ++ GPIO_GFN(DU_DR6), ++ GPIO_GFN(DU_DR5), ++ GPIO_GFN(DU_DR4), ++ GPIO_GFN(DU_DR3), ++ GPIO_GFN(DU_DR2), ++ ++ /* GPSR1 */ ++ GPIO_GFN(DIGRF_CLKOUT), ++ GPIO_GFN(DIGRF_CLKIN), ++ GPIO_GFN(CANFD_CLK_A), ++ GPIO_GFN(CANFD1_RX), ++ GPIO_GFN(CANFD1_TX), ++ GPIO_GFN(CANFD0_RX_A), ++ GPIO_GFN(CANFD0_TX_A), ++ GPIO_GFN(AVB0_AVTP_CAPTURE), ++ GPIO_FN(AVB0_AVTP_MATCH), ++ GPIO_FN(AVB0_LINK), ++ GPIO_FN(AVB0_PHY_INT), ++ GPIO_FN(AVB0_MAGIC), ++ GPIO_FN(AVB0_MDC), ++ GPIO_FN(AVB0_MDIO), ++ GPIO_FN(AVB0_TXCREFCLK), ++ GPIO_FN(AVB0_TD3), ++ GPIO_FN(AVB0_TD2), ++ GPIO_FN(AVB0_TD1), ++ GPIO_FN(AVB0_TD0), ++ GPIO_FN(AVB0_TXC), ++ GPIO_FN(AVB0_TX_CTL), ++ GPIO_FN(AVB0_RD3), ++ GPIO_FN(AVB0_RD2), ++ GPIO_FN(AVB0_RD1), ++ GPIO_FN(AVB0_RD0), ++ GPIO_FN(AVB0_RXC), ++ GPIO_FN(AVB0_RX_CTL), ++ GPIO_GFN(IRQ0), ++ ++ /* GPSR2 */ ++ GPIO_GFN(VI0_FIELD), ++ GPIO_GFN(VI0_DATA11), ++ GPIO_GFN(VI0_DATA10), ++ GPIO_GFN(VI0_DATA9), ++ GPIO_GFN(VI0_DATA8), ++ GPIO_GFN(VI0_DATA7), ++ GPIO_GFN(VI0_DATA6), ++ GPIO_GFN(VI0_DATA5), ++ GPIO_GFN(VI0_DATA4), ++ GPIO_GFN(VI0_DATA3), ++ GPIO_GFN(VI0_DATA2), ++ GPIO_GFN(VI0_DATA1), ++ GPIO_GFN(VI0_DATA0), ++ GPIO_GFN(VI0_VSYNC_N), ++ GPIO_GFN(VI0_HSYNC_N), ++ GPIO_GFN(VI0_CLKENB), ++ GPIO_GFN(VI0_CLK), ++ ++ /* GPSR3 */ ++ GPIO_GFN(VI1_FIELD), ++ GPIO_GFN(VI1_DATA11), ++ GPIO_GFN(VI1_DATA10), ++ GPIO_GFN(VI1_DATA9), ++ GPIO_GFN(VI1_DATA8), ++ GPIO_GFN(VI1_DATA7), ++ GPIO_GFN(VI1_DATA6), ++ GPIO_GFN(VI1_DATA5), ++ GPIO_GFN(VI1_DATA4), ++ GPIO_GFN(VI1_DATA3), ++ GPIO_GFN(VI1_DATA2), ++ GPIO_GFN(VI1_DATA1), ++ GPIO_GFN(VI1_DATA0), ++ GPIO_GFN(VI1_VSYNC_N), ++ GPIO_GFN(VI1_HSYNC_N), ++ GPIO_GFN(VI1_CLKENB), ++ GPIO_GFN(VI1_CLK), ++ ++ /* GPSR4 */ ++ GPIO_GFN(SDA2), ++ GPIO_GFN(SCL2), ++ GPIO_GFN(SDA1), ++ GPIO_GFN(SCL1), ++ GPIO_GFN(SDA0), ++ GPIO_GFN(SCL0), ++ ++ /* GPSR5 */ ++ GPIO_FN(RPC_INT_N), ++ GPIO_FN(RPC_WP_N), ++ GPIO_FN(RPC_RESET_N), ++ GPIO_FN(QSPI1_SSL), ++ GPIO_FN(QSPI1_IO3), ++ GPIO_FN(QSPI1_IO2), ++ GPIO_FN(QSPI1_MISO_IO1), ++ GPIO_FN(QSPI1_MOSI_IO0), ++ GPIO_FN(QSPI1_SPCLK), ++ GPIO_FN(QSPI0_SSL), ++ GPIO_FN(QSPI0_IO3), ++ GPIO_FN(QSPI0_IO2), ++ GPIO_FN(QSPI0_MISO_IO1), ++ GPIO_FN(QSPI0_MOSI_IO0), ++ GPIO_FN(QSPI0_SPCLK), ++ ++ /* IPSR0 */ ++ GPIO_IFN(DU_DR2), ++ GPIO_FN(HSCK0), ++ GPIO_FN(A0), ++ GPIO_IFN(DU_DR3), ++ GPIO_FN(HRTS0_N), ++ GPIO_FN(A1), ++ GPIO_IFN(DU_DR4), ++ GPIO_FN(HCTS0_N), ++ GPIO_FN(A2), ++ GPIO_IFN(DU_DR5), ++ GPIO_FN(HTX0), ++ GPIO_FN(A3), ++ GPIO_IFN(DU_DR6), ++ GPIO_FN(MSIOF3_RXD), ++ GPIO_FN(A4), ++ GPIO_IFN(DU_DR7), ++ GPIO_FN(MSIOF3_TXD), ++ GPIO_FN(A5), ++ GPIO_IFN(DU_DG2), ++ GPIO_FN(MSIOF3_SS1), ++ GPIO_FN(A6), ++ GPIO_IFN(DU_DG3), ++ GPIO_FN(MSIOF3_SS2), ++ GPIO_FN(A7), ++ GPIO_FN(PWMFSW0), ++ ++ /* IPSR1 */ ++ GPIO_IFN(DU_DG4), ++ GPIO_FN(A8), ++ GPIO_FN(FSO_CFE_0_N_A), ++ GPIO_IFN(DU_DG5), ++ GPIO_FN(A9), ++ GPIO_FN(FSO_CFE_1_N_A), ++ GPIO_IFN(DU_DG6), ++ GPIO_FN(A10), ++ GPIO_FN(FSO_TOE_N_A), ++ GPIO_IFN(DU_DG7), ++ GPIO_FN(A11), ++ GPIO_FN(IRQ1), ++ GPIO_IFN(DU_DB2), ++ GPIO_FN(A12), ++ GPIO_FN(IRQ2), ++ GPIO_IFN(DU_DB3), ++ GPIO_FN(A13), ++ GPIO_FN(FXR_CLKOUT1), ++ GPIO_IFN(DU_DB4), ++ GPIO_FN(A14), ++ GPIO_FN(FXR_CLKOUT2), ++ GPIO_IFN(DU_DB5), ++ GPIO_FN(A15), ++ GPIO_FN(FXR_TXENA_N), ++ ++ /* IPSR2 */ ++ GPIO_IFN(DU_DB6), ++ GPIO_FN(A16), ++ GPIO_FN(FXR_TXENB_N), ++ GPIO_IFN(DU_DB7), ++ GPIO_FN(A17), ++ GPIO_FN(STPWT_EXTFXR), ++ GPIO_IFN(DU_DOTCLKOUT), ++ GPIO_FN(SCIF_CLK_A), ++ GPIO_FN(A18), ++ GPIO_IFN(DU_EXHSYNC_DU_HSYNC), ++ GPIO_FN(HRX0), ++ GPIO_FN(A19), ++ GPIO_FN(IRQ3), ++ GPIO_IFN(DU_EXVSYNC_DU_VSYNC), ++ GPIO_FN(MSIOF3_SCK), ++ GPIO_FN(A20), ++ GPIO_IFN(DU_EXODDF_DU_ODDF_DISP_CDE), ++ GPIO_FN(MSIOF3_SYNC), ++ GPIO_FN(A21), ++ GPIO_IFN(IRQ0), ++ GPIO_FN(CC5_OSCOUT), ++ GPIO_IFN(VI0_CLK), ++ GPIO_FN(MSIOF2_SCK), ++ GPIO_FN(SCK3), ++ GPIO_FN(HSCK3), ++ ++ /* IPSR3 */ ++ GPIO_IFN(VI0_CLKENB), ++ GPIO_FN(MSIOF2_RXD), ++ GPIO_FN(RX3), ++ GPIO_FN(RD_WR_N), ++ GPIO_FN(HCTS3_N), ++ GPIO_IFN(VI0_HSYNC_N), ++ GPIO_FN(MSIOF2_TXD), ++ GPIO_FN(TX3), ++ GPIO_FN(HRTS3_N), ++ GPIO_IFN(VI0_VSYNC_N), ++ GPIO_FN(MSIOF2_SYNC), ++ GPIO_FN(CTS3_N), ++ GPIO_FN(HTX3), ++ GPIO_IFN(VI0_DATA0), ++ GPIO_FN(MSIOF2_SS1), ++ GPIO_FN(RTS3_N_TANS), ++ GPIO_FN(HRX3), ++ GPIO_IFN(VI0_DATA1), ++ GPIO_FN(MSIOF2_SS2), ++ GPIO_FN(SCK1), ++ GPIO_FN(SPEEDIN_A), ++ GPIO_IFN(VI0_DATA2), ++ GPIO_FN(AVB0_AVTP_PPS), ++ GPIO_FN(SDA3_A), ++ GPIO_IFN(VI0_DATA3), ++ GPIO_FN(HSCK1), ++ GPIO_FN(SCL3_A), ++ GPIO_IFN(VI0_DATA4), ++ GPIO_FN(HRTS1_N), ++ GPIO_FN(RX1_A), ++ ++ /* IPSR4 */ ++ GPIO_IFN(VI0_DATA5), ++ GPIO_FN(HCTS1_N), ++ GPIO_FN(TX1_A), ++ GPIO_IFN(VI0_DATA6), ++ GPIO_FN(HTX1), ++ GPIO_FN(CTS1_N), ++ GPIO_IFN(VI0_DATA7), ++ GPIO_FN(HRX1), ++ GPIO_FN(RTS1_N_TANS), ++ GPIO_IFN(VI0_DATA8), ++ GPIO_FN(HSCK2), ++ GPIO_FN(PWM0_A), ++ GPIO_FN(A22), ++ GPIO_IFN(VI0_DATA9), ++ GPIO_FN(HCTS2_N), ++ GPIO_FN(PWM1_A), ++ GPIO_FN(A23), ++ GPIO_FN(FSO_CFE_0_N_B), ++ GPIO_IFN(VI0_DATA10), ++ GPIO_FN(HRTS2_N), ++ GPIO_FN(PWM2_A), ++ GPIO_FN(A24), ++ GPIO_FN(FSO_CFE_1_N_B), ++ GPIO_IFN(VI0_DATA11), ++ GPIO_FN(HTX2), ++ GPIO_FN(PWM3_A), ++ GPIO_FN(A25), ++ GPIO_FN(FSO_TOE_N_B), ++ GPIO_IFN(VI0_FIELD), ++ GPIO_FN(HRX2), ++ GPIO_FN(PWM4_A), ++ GPIO_FN(CS1_N_A26), ++ GPIO_FN(FSCLKST2_N_A), ++ ++ /* IPSR5 */ ++ GPIO_IFN(VI1_CLK), ++ GPIO_FN(MSIOF1_RXD), ++ GPIO_FN(CS0_N), ++ GPIO_IFN(VI1_CLKENB), ++ GPIO_FN(MSIOF1_TXD), ++ GPIO_FN(D0), ++ GPIO_IFN(VI1_HSYNC_N), ++ GPIO_FN(MSIOF1_SCK), ++ GPIO_FN(D1), ++ GPIO_IFN(VI1_VSYNC_N), ++ GPIO_FN(MSIOF1_SYNC), ++ GPIO_FN(D2), ++ GPIO_IFN(VI1_DATA0), ++ GPIO_FN(MSIOF1_SS1), ++ GPIO_FN(D3), ++ GPIO_IFN(VI1_DATA1), ++ GPIO_FN(MSIOF1_SS2), ++ GPIO_FN(D4), ++ GPIO_FN(MMC_CMD), ++ GPIO_IFN(VI1_DATA2), ++ GPIO_FN(CANFD0_TX_B), ++ GPIO_FN(D5), ++ GPIO_FN(MMC_D0), ++ GPIO_IFN(VI1_DATA3), ++ GPIO_FN(CANFD0_RX_B), ++ GPIO_FN(D6), ++ GPIO_FN(MMC_D1), ++ ++ /* IPSR6 */ ++ GPIO_IFN(VI1_DATA4), ++ GPIO_FN(CANFD_CLK_B), ++ GPIO_FN(D7), ++ GPIO_FN(MMC_D2), ++ GPIO_IFN(VI1_DATA5), ++ GPIO_FN(SCK4), ++ GPIO_FN(D8), ++ GPIO_FN(MMC_D3), ++ GPIO_IFN(VI1_DATA6), ++ GPIO_FN(RX4), ++ GPIO_FN(D9), ++ GPIO_FN(MMC_CLK), ++ GPIO_IFN(VI1_DATA7), ++ GPIO_FN(TX4), ++ GPIO_FN(D10), ++ GPIO_FN(MMC_D4), ++ GPIO_IFN(VI1_DATA8), ++ GPIO_FN(CTS4_N), ++ GPIO_FN(D11), ++ GPIO_FN(MMC_D5), ++ GPIO_IFN(VI1_DATA9), ++ GPIO_FN(RTS4_N_TANS), ++ GPIO_FN(D12), ++ GPIO_FN(MMC_D6), ++ GPIO_FN(SCL3_B), ++ GPIO_IFN(VI1_DATA10), ++ GPIO_FN(D13), ++ GPIO_FN(MMC_D7), ++ GPIO_FN(SDA3_B), ++ GPIO_IFN(VI1_DATA11), ++ GPIO_FN(SCL4), ++ GPIO_FN(IRQ4), ++ GPIO_FN(D14), ++ GPIO_FN(MMC_WP), ++ ++ /* IPSR7 */ ++ GPIO_IFN(VI1_FIELD), ++ GPIO_FN(SDA4), ++ GPIO_FN(IRQ5), ++ GPIO_FN(D15), ++ GPIO_FN(MMC_CD), ++ GPIO_IFN(SCL0), ++ GPIO_FN(DU_DR0), ++ GPIO_FN(TPU0TO0), ++ GPIO_FN(CLKOUT), ++ GPIO_FN(MSIOF0_RXD), ++ GPIO_IFN(SDA0), ++ GPIO_FN(DU_DR1), ++ GPIO_FN(TPU0TO1), ++ GPIO_FN(BS_N), ++ GPIO_FN(SCK0), ++ GPIO_FN(MSIOF0_TXD), ++ GPIO_IFN(SCL1), ++ GPIO_FN(DU_DG0), ++ GPIO_FN(TPU0TO2), ++ GPIO_FN(RD_N), ++ GPIO_FN(CTS0_N), ++ GPIO_FN(MSIOF0_SCK), ++ GPIO_IFN(SDA1), ++ GPIO_FN(DU_DG1), ++ GPIO_FN(TPU0TO3), ++ GPIO_FN(WE0_N), ++ GPIO_FN(RTS0_N_TANS), ++ GPIO_FN(MSIOF0_SYNC), ++ GPIO_IFN(SCL2), ++ GPIO_FN(DU_DB0), ++ GPIO_FN(TCLK1_A), ++ GPIO_FN(WE1_N), ++ GPIO_FN(RX0), ++ GPIO_FN(MSIOF0_SS1), ++ GPIO_IFN(SDA2), ++ GPIO_FN(DU_DB1), ++ GPIO_FN(TCLK2_A), ++ GPIO_FN(EX_WAIT0), ++ GPIO_FN(TX0), ++ GPIO_FN(MSIOF0_SS2), ++ GPIO_IFN(AVB0_AVTP_CAPTURE), ++ GPIO_FN(FSCLKST2_N_B), ++ ++ /* IPSR8 */ ++ GPIO_IFN(CANFD0_TX_A), ++ GPIO_FN(FXR_TXDA), ++ GPIO_FN(PWM0_B), ++ GPIO_FN(DU_DISP), ++ GPIO_FN(FSCLKST2_N_C), ++ GPIO_IFN(CANFD0_RX_A), ++ GPIO_FN(RXDA_EXTFXR), ++ GPIO_FN(PWM1_B), ++ GPIO_FN(DU_CDE), ++ GPIO_IFN(CANFD1_TX), ++ GPIO_FN(FXR_TXDB), ++ GPIO_FN(PWM2_B), ++ GPIO_FN(TCLK1_B), ++ GPIO_FN(TX1_B), ++ GPIO_IFN(CANFD1_RX), ++ GPIO_FN(RXDB_EXTFXR), ++ GPIO_FN(PWM3_B), ++ GPIO_FN(TCLK2_B), ++ GPIO_FN(RX1_B), ++ GPIO_IFN(CANFD_CLK_A), ++ GPIO_FN(CLK_EXTFXR), ++ GPIO_FN(PWM4_B), ++ GPIO_FN(SPEEDIN_B), ++ GPIO_FN(SCIF_CLK_B), ++ GPIO_IFN(DIGRF_CLKIN), ++ GPIO_FN(DIGRF_CLKEN_IN), ++ GPIO_IFN(DIGRF_CLKOUT), ++ GPIO_FN(DIGRF_CLKEN_OUT), ++ ++}; ++ ++static struct pinmux_cfg_reg pinmux_config_regs[] = { ++ /* GPSR0(0xE6060100) md[3:1] controls initial value */ ++ /* md[3:1] .. 0 : 0x0000FFFF */ ++ /* .. other : 0x00000000 */ ++ { PINMUX_CFG_REG("GPSR0", 0xE6060100, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_0_21_FN, GFN_DU_EXODDF_DU_ODDF_DISP_CDE, ++ GP_0_20_FN, GFN_DU_EXVSYNC_DU_VSYNC, ++ GP_0_19_FN, GFN_DU_EXHSYNC_DU_HSYNC, ++ GP_0_18_FN, GFN_DU_DOTCLKOUT, ++ GP_0_17_FN, GFN_DU_DB7, ++ GP_0_16_FN, GFN_DU_DB6, ++ GP_0_15_FN, GFN_DU_DB5, ++ GP_0_14_FN, GFN_DU_DB4, ++ GP_0_13_FN, GFN_DU_DB3, ++ GP_0_12_FN, GFN_DU_DB2, ++ GP_0_11_FN, GFN_DU_DG7, ++ GP_0_10_FN, GFN_DU_DG6, ++ GP_0_9_FN, GFN_DU_DG5, ++ GP_0_8_FN, GFN_DU_DG4, ++ GP_0_7_FN, GFN_DU_DG3, ++ GP_0_6_FN, GFN_DU_DG2, ++ GP_0_5_FN, GFN_DU_DR7, ++ GP_0_4_FN, GFN_DU_DR6, ++ GP_0_3_FN, GFN_DU_DR5, ++ GP_0_2_FN, GFN_DU_DR4, ++ GP_0_1_FN, GFN_DU_DR3, ++ GP_0_0_FN, GFN_DU_DR2 } ++ }, ++ /* GPSR1(0xE6060104) is md[3:1] controls initial value */ ++ /* md[3:1] .. 0 : 0x0EFFFFFF */ ++ /* .. other : 0x00000000 */ ++ { PINMUX_CFG_REG("GPSR1", 0xE6060104, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_1_27_FN, GFN_DIGRF_CLKOUT, ++ GP_1_26_FN, GFN_DIGRF_CLKIN, ++ GP_1_25_FN, GFN_CANFD_CLK_A, ++ GP_1_24_FN, GFN_CANFD1_RX, ++ GP_1_23_FN, GFN_CANFD1_TX, ++ GP_1_22_FN, GFN_CANFD0_RX_A, ++ GP_1_21_FN, GFN_CANFD0_TX_A, ++ GP_1_20_FN, GFN_AVB0_AVTP_CAPTURE, ++ GP_1_19_FN, FN_AVB0_AVTP_MATCH, ++ GP_1_18_FN, FN_AVB0_LINK, ++ GP_1_17_FN, FN_AVB0_PHY_INT, ++ GP_1_16_FN, FN_AVB0_MAGIC, ++ GP_1_15_FN, FN_AVB0_MDC, ++ GP_1_14_FN, FN_AVB0_MDIO, ++ GP_1_13_FN, FN_AVB0_TXCREFCLK, ++ GP_1_12_FN, FN_AVB0_TD3, ++ GP_1_11_FN, FN_AVB0_TD2, ++ GP_1_10_FN, FN_AVB0_TD1, ++ GP_1_9_FN, FN_AVB0_TD0, ++ GP_1_8_FN, FN_AVB0_TXC, ++ GP_1_7_FN, FN_AVB0_TX_CTL, ++ GP_1_6_FN, FN_AVB0_RD3, ++ GP_1_5_FN, FN_AVB0_RD2, ++ GP_1_4_FN, FN_AVB0_RD1, ++ GP_1_3_FN, FN_AVB0_RD0, ++ GP_1_2_FN, FN_AVB0_RXC, ++ GP_1_1_FN, FN_AVB0_RX_CTL, ++ GP_1_0_FN, GFN_IRQ0 } ++ }, ++ /* GPSR2(0xE6060108) is md[3:1] controls */ ++ /* md[3:1] .. 0 : 0x000003C0 */ ++ /* .. other : 0x00000200 */ ++ { PINMUX_CFG_REG("GPSR2", 0xE6060108, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_2_16_FN, GFN_VI0_FIELD, ++ GP_2_15_FN, GFN_VI0_DATA11, ++ GP_2_14_FN, GFN_VI0_DATA10, ++ GP_2_13_FN, GFN_VI0_DATA9, ++ GP_2_12_FN, GFN_VI0_DATA8, ++ GP_2_11_FN, GFN_VI0_DATA7, ++ GP_2_10_FN, GFN_VI0_DATA6, ++ GP_2_9_FN, GFN_VI0_DATA5, ++ GP_2_8_FN, GFN_VI0_DATA4, ++ GP_2_7_FN, GFN_VI0_DATA3, ++ GP_2_6_FN, GFN_VI0_DATA2, ++ GP_2_5_FN, GFN_VI0_DATA1, ++ GP_2_4_FN, GFN_VI0_DATA0, ++ GP_2_3_FN, GFN_VI0_VSYNC_N, ++ GP_2_2_FN, GFN_VI0_HSYNC_N, ++ GP_2_1_FN, GFN_VI0_CLKENB, ++ GP_2_0_FN, GFN_VI0_CLK } ++ }, ++ ++ /* GPSR3 */ ++ { PINMUX_CFG_REG("GPSR3", 0xE606010C, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_3_16_FN, GFN_VI1_FIELD, ++ GP_3_15_FN, GFN_VI1_DATA11, ++ GP_3_14_FN, GFN_VI1_DATA10, ++ GP_3_13_FN, GFN_VI1_DATA9, ++ GP_3_12_FN, GFN_VI1_DATA8, ++ GP_3_11_FN, GFN_VI1_DATA7, ++ GP_3_10_FN, GFN_VI1_DATA6, ++ GP_3_9_FN, GFN_VI1_DATA5, ++ GP_3_8_FN, GFN_VI1_DATA4, ++ GP_3_7_FN, GFN_VI1_DATA3, ++ GP_3_6_FN, GFN_VI1_DATA2, ++ GP_3_5_FN, GFN_VI1_DATA1, ++ GP_3_4_FN, GFN_VI1_DATA0, ++ GP_3_3_FN, GFN_VI1_VSYNC_N, ++ GP_3_2_FN, GFN_VI1_HSYNC_N, ++ GP_3_1_FN, GFN_VI1_CLKENB, ++ GP_3_0_FN, GFN_VI1_CLK } ++ }, ++ /* GPSR4 */ ++ { PINMUX_CFG_REG("GPSR4", 0xE6060110, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_4_5_FN, GFN_SDA2, ++ GP_4_4_FN, GFN_SCL2, ++ GP_4_3_FN, GFN_SDA1, ++ GP_4_2_FN, GFN_SCL1, ++ GP_4_1_FN, GFN_SDA0, ++ GP_4_0_FN, GFN_SCL0 } ++ }, ++ /* GPSR5 */ ++ { PINMUX_CFG_REG("GPSR5", 0xE6060114, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_5_14_FN, FN_RPC_INT_N, ++ GP_5_13_FN, FN_RPC_WP_N, ++ GP_5_12_FN, FN_RPC_RESET_N, ++ GP_5_11_FN, FN_QSPI1_SSL, ++ GP_5_10_FN, FN_QSPI1_IO3, ++ GP_5_9_FN, FN_QSPI1_IO2, ++ GP_5_8_FN, FN_QSPI1_MISO_IO1, ++ GP_5_7_FN, FN_QSPI1_MOSI_IO0, ++ GP_5_6_FN, FN_QSPI1_SPCLK, ++ GP_5_5_FN, FN_QSPI0_SSL, ++ GP_5_4_FN, FN_QSPI0_IO3, ++ GP_5_3_FN, FN_QSPI0_IO2, ++ GP_5_2_FN, FN_QSPI0_MISO_IO1, ++ GP_5_1_FN, FN_QSPI0_MOSI_IO0, ++ GP_5_0_FN, FN_QSPI0_SPCLK } ++ }, ++ ++ { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32, ++ 4, 4, 4, 4, 4, 4, 4, 4) { ++ /* IPSR0_31_28 [4] */ ++ IFN_DU_DG3, FN_MSIOF3_SS2, 0, FN_A7, ++ FN_PWMFSW0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR0_27_24 [4] */ ++ IFN_DU_DG2, FN_MSIOF3_SS1, 0, FN_A6, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR0_23_20 [4] */ ++ IFN_DU_DR7, FN_MSIOF3_TXD, 0, FN_A5, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR0_19_16 [4] */ ++ IFN_DU_DR6, FN_MSIOF3_RXD, 0, FN_A4, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR0_15_12 [4] */ ++ IFN_DU_DR5, FN_HTX0, 0, FN_A3, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR0_11_8 [4] */ ++ IFN_DU_DR4, FN_HCTS0_N, 0, FN_A2, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR0_7_4 [4] */ ++ IFN_DU_DR3, FN_HRTS0_N, 0, FN_A1, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR0_3_0 [4] */ ++ IFN_DU_DR2, FN_HSCK0, 0, FN_A0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32, ++ 4, 4, 4, 4, 4, 4, 4, 4) { ++ /* IPSR1_31_28 [4] */ ++ IFN_DU_DB5, 0, 0, FN_A15, ++ FN_FXR_TXENA_N, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR1_27_24 [4] */ ++ IFN_DU_DB4, 0, 0, FN_A14, ++ FN_FXR_CLKOUT2, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR1_23_20 [4] */ ++ IFN_DU_DB3, 0, 0, FN_A13, ++ FN_FXR_CLKOUT1, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR1_19_16 [4] */ ++ IFN_DU_DB2, 0, 0, FN_A12, ++ FN_IRQ2, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR1_15_12 [4] */ ++ IFN_DU_DG7, 0, 0, FN_A11, ++ FN_IRQ1, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR1_11_8 [4] */ ++ IFN_DU_DG6, 0, 0, FN_A10, ++ FN_FSO_TOE_N_A, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR1_7_4 [4] */ ++ IFN_DU_DG5, 0, 0, FN_A9, ++ FN_FSO_CFE_1_N_A, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR1_3_0 [4] */ ++ IFN_DU_DG4, 0, 0, FN_A8, ++ FN_FSO_CFE_0_N_A, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0 ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32, ++ 4, 4, 4, 4, 4, 4, 4, 4) { ++ /* IPSR2_31_28 [4] */ ++ IFN_VI0_CLK, FN_MSIOF2_SCK, FN_SCK3, 0, ++ FN_HSCK3, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR2_27_24 [4] */ ++ IFN_IRQ0, FN_CC5_OSCOUT, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR2_23_20 [4] */ ++ IFN_DU_EXODDF_DU_ODDF_DISP_CDE, FN_MSIOF3_SYNC, 0, FN_A21, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR2_19_16 [4] */ ++ IFN_DU_EXVSYNC_DU_VSYNC, FN_MSIOF3_SCK, 0, FN_A20, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR2_15_12 [4] */ ++ IFN_DU_EXHSYNC_DU_HSYNC, FN_HRX0, 0, FN_A19, ++ FN_IRQ3, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR2_11_8 [4] */ ++ IFN_DU_DOTCLKOUT, FN_SCIF_CLK_A, 0, FN_A18, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR2_7_4 [4] */ ++ IFN_DU_DB7, 0, 0, FN_A17, ++ FN_STPWT_EXTFXR, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR2_3_0 [4] */ ++ IFN_DU_DB6, 0, 0, FN_A16, ++ FN_FXR_TXENB_N, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32, ++ 4, 4, 4, 4, 4, 4, 4, 4) { ++ /* IPSR3_31_28 [4] */ ++ IFN_VI0_DATA4, FN_HRTS1_N, FN_RX1_A, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR3_27_24 [4] */ ++ IFN_VI0_DATA3, FN_HSCK1, FN_SCL3_A, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR3_23_20 [4] */ ++ IFN_VI0_DATA2, FN_AVB0_AVTP_PPS, FN_SDA3_A, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR3_19_16 [4] */ ++ IFN_VI0_DATA1, FN_MSIOF2_SS2, FN_SCK1, 0, ++ FN_SPEEDIN_A, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR3_15_12 [4] */ ++ IFN_VI0_DATA0, FN_MSIOF2_SS1, FN_RTS3_N_TANS, 0, ++ FN_HRX3, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR3_11_8 [4] */ ++ IFN_VI0_VSYNC_N, FN_MSIOF2_SYNC, FN_CTS3_N, 0, ++ FN_HTX3, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR3_7_4 [4] */ ++ IFN_VI0_HSYNC_N, FN_MSIOF2_TXD, FN_TX3, 0, ++ FN_HRTS3_N, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR3_3_0 [4] */ ++ IFN_VI0_CLKENB, FN_MSIOF2_RXD, FN_RX3, FN_RD_WR_N, ++ FN_HCTS3_N, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32, ++ 4, 4, 4, 4, 4, 4, 4, 4) { ++ /* IPSR4_31_28 [4] */ ++ IFN_VI0_FIELD, FN_HRX2, FN_PWM4_A, FN_CS1_N_A26, ++ FN_FSCLKST2_N_A, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR4_27_24 [4] */ ++ IFN_VI0_DATA11, FN_HTX2, FN_PWM3_A, FN_A25, ++ FN_FSO_TOE_N_B, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR4_23_20 [4] */ ++ IFN_VI0_DATA10, FN_HRTS2_N, FN_PWM2_A, FN_A24, ++ FN_FSO_CFE_1_N_B, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR4_19_16 [4] */ ++ IFN_VI0_DATA9, FN_HCTS2_N, FN_PWM1_A, FN_A23, ++ FN_FSO_CFE_0_N_B, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR4_15_12 [4] */ ++ IFN_VI0_DATA8, FN_HSCK2, FN_PWM0_A, FN_A22, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR4_11_8 [4] */ ++ IFN_VI0_DATA7, FN_HRX1, FN_RTS1_N_TANS, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR4_7_4 [4] */ ++ IFN_VI0_DATA6, FN_HTX1, FN_CTS1_N, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR4_3_0 [4] */ ++ IFN_VI0_DATA5, FN_HCTS1_N, FN_TX1_A, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32, ++ 4, 4, 4, 4, 4, 4, 4, 4) { ++ /* IPSR5_31_28 [4] */ ++ IFN_VI1_DATA3, FN_CANFD0_RX_B, 0, FN_D6, ++ FN_MMC_D1, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR5_27_24 [4] */ ++ IFN_VI1_DATA2, FN_CANFD0_TX_B, 0, FN_D5, ++ FN_MMC_D0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR5_23_20 [4] */ ++ IFN_VI1_DATA1, FN_MSIOF1_SS2, 0, FN_D4, ++ FN_MMC_CMD, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR5_19_16 [4] */ ++ IFN_VI1_DATA0, FN_MSIOF1_SS1, 0, FN_D3, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR5_15_12 [4] */ ++ IFN_VI1_VSYNC_N, FN_MSIOF1_SYNC, 0, FN_D2, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR5_11_8 [4] */ ++ IFN_VI1_HSYNC_N, FN_MSIOF1_SCK, 0, FN_D1, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR5_7_4 [4] */ ++ IFN_VI1_CLKENB, FN_MSIOF1_TXD, 0, FN_D0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR5_3_0 [4] */ ++ IFN_VI1_CLK, FN_MSIOF1_RXD, 0, FN_CS0_N, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32, ++ 4, 4, 4, 4, 4, 4, 4, 4) { ++ /* IPSR6_31_28 [4] */ ++ IFN_VI1_DATA11, FN_SCL4, FN_IRQ4, FN_D14, ++ FN_MMC_WP, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR6_27_24 [4] */ ++ IFN_VI1_DATA10, 0, 0, FN_D13, ++ FN_MMC_D7, FN_SDA3_B, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR6_23_20 [4] */ ++ IFN_VI1_DATA9, 0, FN_RTS4_N_TANS, FN_D12, ++ FN_MMC_D6, FN_SCL3_B, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR6_19_16 [4] */ ++ IFN_VI1_DATA8, 0, FN_CTS4_N, FN_D11, ++ FN_MMC_D5, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR6_15_12 [4] */ ++ IFN_VI1_DATA7, 0, FN_TX4, FN_D10, ++ FN_MMC_D4, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR6_11_8 [4] */ ++ IFN_VI1_DATA6, 0, FN_RX4, FN_D9, ++ FN_MMC_CLK, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR6_7_4 [4] */ ++ IFN_VI1_DATA5, 0, FN_SCK4, FN_D8, ++ FN_MMC_D3, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR6_3_0 [4] */ ++ IFN_VI1_DATA4, FN_CANFD_CLK_B, 0, FN_D7, ++ FN_MMC_D2, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32, ++ 4, 4, 4, 4, 4, 4, 4, 4) { ++ /* IPSR7_31_28 [4] */ ++ IFN_AVB0_AVTP_CAPTURE, 0, 0, 0, ++ FN_FSCLKST2_N_B, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR7_27_24 [4] */ ++ IFN_SDA2, FN_DU_DB1, FN_TCLK2_A, FN_EX_WAIT0, ++ FN_TX0, FN_MSIOF0_SS2, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR7_23_20 [4] */ ++ IFN_SCL2, FN_DU_DB0, FN_TCLK1_A, FN_WE1_N, ++ FN_RX0, FN_MSIOF0_SS1, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR7_19_16 [4] */ ++ IFN_SDA1, FN_DU_DG1, FN_TPU0TO3, FN_WE0_N, ++ FN_RTS0_N_TANS, FN_MSIOF0_SYNC, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR7_15_12 [4] */ ++ IFN_SCL1, FN_DU_DG0, FN_TPU0TO2, FN_RD_N, ++ FN_CTS0_N, FN_MSIOF0_SCK, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR7_11_8 [4] */ ++ IFN_SDA0, FN_DU_DR1, FN_TPU0TO1, FN_BS_N, ++ FN_SCK0, FN_MSIOF0_TXD, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR7_7_4 [4] */ ++ IFN_SCL0, FN_DU_DR0, FN_TPU0TO0, FN_CLKOUT, ++ 0, FN_MSIOF0_RXD, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR7_3_0 [4] */ ++ IFN_VI1_FIELD, FN_SDA4, FN_IRQ5, FN_D15, ++ FN_MMC_CD, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ } ++ }, ++ { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32, ++ 4, 4, 4, 4, 4, 4, 4, 4) { ++ /* IPSR8_31_28 [4] */ ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR8_27_24 [4] */ ++ IFN_DIGRF_CLKOUT, FN_DIGRF_CLKEN_OUT, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR8_23_20 [4] */ ++ IFN_DIGRF_CLKIN, FN_DIGRF_CLKEN_IN, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR8_19_16 [4] */ ++ IFN_CANFD_CLK_A, FN_CLK_EXTFXR, FN_PWM4_B, FN_SPEEDIN_B, ++ FN_SCIF_CLK_B, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR8_15_12 [4] */ ++ IFN_CANFD1_RX, FN_RXDB_EXTFXR, FN_PWM3_B, FN_TCLK2_B, ++ FN_RX1_B, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR8_11_8 [4] */ ++ IFN_CANFD1_TX, FN_FXR_TXDB, FN_PWM2_B, FN_TCLK1_B, ++ FN_TX1_B, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR8_7_4 [4] */ ++ IFN_CANFD0_RX_A, FN_RXDA_EXTFXR, FN_PWM1_B, FN_DU_CDE, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ /* IPSR8_3_0 [4] */ ++ IFN_CANFD0_TX_A, FN_FXR_TXDA, FN_PWM0_B, FN_DU_DISP, ++ FN_FSCLKST2_N_C, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ } ++ }, ++ { PINMUX_CFG_REG("MOD_SEL0", 0xE6060500, 32, 1) { ++ /* reserved [31..24] */ ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ /* reserved [23..16] */ ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ /* reserved [15..11] */ ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ /* SEL_HSCIF0 [1] */ ++ FN_SEL_HSCIF0_0, ++ FN_SEL_HSCIF0_1, ++ /* SEL_SCIF1 [1] */ ++ FN_SEL_SCIF1_0, ++ FN_SEL_SCIF1_1, ++ /* SEL_CANFD0 [1] */ ++ FN_SEL_CANFD0_0, ++ FN_SEL_CANFD0_1, ++ /* SEL_PWM4 [1] */ ++ FN_SEL_PWM4_0, ++ FN_SEL_PWM4_1, ++ /* SEL_PWM3 [1] */ ++ FN_SEL_PWM3_0, ++ FN_SEL_PWM3_1, ++ /* SEL_PWM2 [1] */ ++ FN_SEL_PWM2_0, ++ FN_SEL_PWM2_1, ++ /* SEL_PWM1 [1] */ ++ FN_SEL_PWM1_0, ++ FN_SEL_PWM1_1, ++ /* SEL_PWM0 [1] */ ++ FN_SEL_PWM0_0, ++ FN_SEL_PWM0_1, ++ /* SEL_RFSO [1] */ ++ FN_SEL_RFSO_0, ++ FN_SEL_RFSO_1, ++ /* SEL_RSP [1] */ ++ FN_SEL_RSP_0, ++ FN_SEL_RSP_1, ++ /* SEL_TMU [1] */ ++ FN_SEL_TMU_0, ++ FN_SEL_TMU_1, ++ } ++ }, ++ ++ /* under construction */ ++ { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ ++ 0, 0, ++ 0, 0, ++ GP_0_21_IN, GP_0_21_OUT, ++ GP_0_20_IN, GP_0_20_OUT, ++ GP_0_19_IN, GP_0_19_OUT, ++ GP_0_18_IN, GP_0_18_OUT, ++ GP_0_17_IN, GP_0_17_OUT, ++ GP_0_16_IN, GP_0_16_OUT, ++ GP_0_15_IN, GP_0_15_OUT, ++ GP_0_14_IN, GP_0_14_OUT, ++ GP_0_13_IN, GP_0_13_OUT, ++ GP_0_12_IN, GP_0_12_OUT, ++ GP_0_11_IN, GP_0_11_OUT, ++ GP_0_10_IN, GP_0_10_OUT, ++ GP_0_9_IN, GP_0_9_OUT, ++ GP_0_8_IN, GP_0_8_OUT, ++ GP_0_7_IN, GP_0_7_OUT, ++ GP_0_6_IN, GP_0_6_OUT, ++ GP_0_5_IN, GP_0_5_OUT, ++ GP_0_4_IN, GP_0_4_OUT, ++ GP_0_3_IN, GP_0_3_OUT, ++ GP_0_2_IN, GP_0_2_OUT, ++ GP_0_1_IN, GP_0_1_OUT, ++ GP_0_0_IN, GP_0_0_OUT, ++ } ++ }, ++ { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_1_27_IN, GP_1_27_OUT, ++ GP_1_26_IN, GP_1_26_OUT, ++ GP_1_25_IN, GP_1_25_OUT, ++ GP_1_24_IN, GP_1_24_OUT, ++ GP_1_23_IN, GP_1_23_OUT, ++ GP_1_22_IN, GP_1_22_OUT, ++ GP_1_21_IN, GP_1_21_OUT, ++ GP_1_20_IN, GP_1_20_OUT, ++ GP_1_19_IN, GP_1_19_OUT, ++ GP_1_18_IN, GP_1_18_OUT, ++ GP_1_17_IN, GP_1_17_OUT, ++ GP_1_16_IN, GP_1_16_OUT, ++ GP_1_15_IN, GP_1_15_OUT, ++ GP_1_14_IN, GP_1_14_OUT, ++ GP_1_13_IN, GP_1_13_OUT, ++ GP_1_12_IN, GP_1_12_OUT, ++ GP_1_11_IN, GP_1_11_OUT, ++ GP_1_10_IN, GP_1_10_OUT, ++ GP_1_9_IN, GP_1_9_OUT, ++ GP_1_8_IN, GP_1_8_OUT, ++ GP_1_7_IN, GP_1_7_OUT, ++ GP_1_6_IN, GP_1_6_OUT, ++ GP_1_5_IN, GP_1_5_OUT, ++ GP_1_4_IN, GP_1_4_OUT, ++ GP_1_3_IN, GP_1_3_OUT, ++ GP_1_2_IN, GP_1_2_OUT, ++ GP_1_1_IN, GP_1_1_OUT, ++ GP_1_0_IN, GP_1_0_OUT, ++ } ++ }, ++ { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_2_16_IN, GP_2_16_OUT, ++ GP_2_15_IN, GP_2_15_OUT, ++ GP_2_14_IN, GP_2_14_OUT, ++ GP_2_13_IN, GP_2_13_OUT, ++ GP_2_12_IN, GP_2_12_OUT, ++ GP_2_11_IN, GP_2_11_OUT, ++ GP_2_10_IN, GP_2_10_OUT, ++ GP_2_9_IN, GP_2_9_OUT, ++ GP_2_8_IN, GP_2_8_OUT, ++ GP_2_7_IN, GP_2_7_OUT, ++ GP_2_6_IN, GP_2_6_OUT, ++ GP_2_5_IN, GP_2_5_OUT, ++ GP_2_4_IN, GP_2_4_OUT, ++ GP_2_3_IN, GP_2_3_OUT, ++ GP_2_2_IN, GP_2_2_OUT, ++ GP_2_1_IN, GP_2_1_OUT, ++ GP_2_0_IN, GP_2_0_OUT, ++ } ++ }, ++ { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_3_16_IN, GP_3_16_OUT, ++ GP_3_15_IN, GP_3_15_OUT, ++ GP_3_14_IN, GP_3_14_OUT, ++ GP_3_13_IN, GP_3_13_OUT, ++ GP_3_12_IN, GP_3_12_OUT, ++ GP_3_11_IN, GP_3_11_OUT, ++ GP_3_10_IN, GP_3_10_OUT, ++ GP_3_9_IN, GP_3_9_OUT, ++ GP_3_8_IN, GP_3_8_OUT, ++ GP_3_7_IN, GP_3_7_OUT, ++ GP_3_6_IN, GP_3_6_OUT, ++ GP_3_5_IN, GP_3_5_OUT, ++ GP_3_4_IN, GP_3_4_OUT, ++ GP_3_3_IN, GP_3_3_OUT, ++ GP_3_2_IN, GP_3_2_OUT, ++ GP_3_1_IN, GP_3_1_OUT, ++ GP_3_0_IN, GP_3_0_OUT, ++ } ++ }, ++ { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ ++ 0, 0, ++ 0, 0, ++ GP_4_5_IN, GP_4_5_OUT, ++ GP_4_4_IN, GP_4_4_OUT, ++ GP_4_3_IN, GP_4_3_OUT, ++ GP_4_2_IN, GP_4_2_OUT, ++ GP_4_1_IN, GP_4_1_OUT, ++ GP_4_0_IN, GP_4_0_OUT, ++ } ++ }, ++ { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ ++ 0, 0, ++ GP_5_14_IN, GP_5_14_OUT, ++ GP_5_13_IN, GP_5_13_OUT, ++ GP_5_12_IN, GP_5_12_OUT, ++ GP_5_11_IN, GP_5_11_OUT, ++ GP_5_10_IN, GP_5_10_OUT, ++ GP_5_9_IN, GP_5_9_OUT, ++ GP_5_8_IN, GP_5_8_OUT, ++ GP_5_7_IN, GP_5_7_OUT, ++ GP_5_6_IN, GP_5_6_OUT, ++ GP_5_5_IN, GP_5_5_OUT, ++ GP_5_4_IN, GP_5_4_OUT, ++ GP_5_3_IN, GP_5_3_OUT, ++ GP_5_2_IN, GP_5_2_OUT, ++ GP_5_1_IN, GP_5_1_OUT, ++ GP_5_0_IN, GP_5_0_OUT, ++ } ++ }, ++ { }, ++ { }, ++ { }, ++}; ++ ++static struct pinmux_data_reg pinmux_data_regs[] = { ++ /* use OUTDT registers? */ ++ { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, GP_0_21_DATA, GP_0_20_DATA, ++ GP_0_19_DATA, GP_0_18_DATA, GP_0_17_DATA, GP_0_16_DATA, ++ GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA, ++ GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA, ++ GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA, ++ GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA } ++ }, ++ { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { ++ 0, 0, 0, 0, ++ GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA, ++ GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, ++ GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, ++ GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, ++ GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, ++ GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, ++ GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } ++ }, ++ { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, GP_2_16_DATA, ++ GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA, ++ GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA, ++ GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA, ++ GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA } ++ }, ++ { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, GP_3_16_DATA, ++ GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA, ++ GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA, ++ GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA, ++ GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA } ++ }, ++ { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, GP_4_5_DATA, GP_4_4_DATA, ++ GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA } ++ }, ++ { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA, ++ GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA, ++ GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, ++ GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA } ++ }, ++ { }, ++ { }, ++ { }, ++}; ++ ++static struct pinmux_info r8a7797_pinmux_info = { ++ .name = "r8a7797_pfc", ++ ++ .unlock_reg = 0xe6060000, /* PMMR */ ++ ++ .reserved_id = PINMUX_RESERVED, ++ .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, ++ .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, ++ .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, ++ .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, ++ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, ++ ++ .first_gpio = GPIO_GP_0_0, ++ .last_gpio = GPIO_FN_DIGRF_CLKEN_OUT, ++ ++ .gpios = pinmux_gpios, ++ .cfg_regs = pinmux_config_regs, ++ .data_regs = pinmux_data_regs, ++ ++ .gpio_data = pinmux_data, ++ .gpio_data_size = ARRAY_SIZE(pinmux_data), ++}; ++ ++void r8a7797_pinmux_init(void) ++{ ++ register_pinmux(&r8a7797_pinmux_info); ++} +diff --git a/arch/arm/cpu/armv8/rcar_gen3/pfc.c b/arch/arm/cpu/armv8/rcar_gen3/pfc.c +index 0543f11..bd3aa0a 100644 +--- a/arch/arm/cpu/armv8/rcar_gen3/pfc.c ++++ b/arch/arm/cpu/armv8/rcar_gen3/pfc.c +@@ -20,5 +20,7 @@ void pinmux_init(void) + r8a7795_pinmux_init(); + #elif defined(CONFIG_R8A7796X) + r8a7796_pinmux_init(); ++#elif defined(CONFIG_R8A7797) ++ r8a7797_pinmux_init(); + #endif + } +diff --git a/arch/arm/cpu/armv8/rcar_gen3/prr_depend.c b/arch/arm/cpu/armv8/rcar_gen3/prr_depend.c +index 776c596..8de3a16 100644 +--- a/arch/arm/cpu/armv8/rcar_gen3/prr_depend.c ++++ b/arch/arm/cpu/armv8/rcar_gen3/prr_depend.c +@@ -98,10 +98,37 @@ int rcar_need_reconfig_sdhi_drvctrl(void) + #define SDH800_SD200 (SD_SRCFC_DIV1 | SD_FC_DIV4) + #define SDH400_SD200 (SD_SRCFC_DIV1 | SD_FC_DIV2) + ++/* ++ * for sd/mmc function(V3M) ++ */ ++#define SDHFC_BIT (8) ++#define SD_SDHFC_DIV2 (0 << SDHFC_BIT) ++#define SD_SDHFC_DIV3 (1 << SDHFC_BIT) ++#define SD_SDHFC_DIV4 (2 << SDHFC_BIT) ++#define SD_SDHFC_DIV6 (3 << SDHFC_BIT) ++#define SD_SDHFC_DIV8 (4 << SDHFC_BIT) ++#define SD_SDHFC_DIV12 (5 << SDHFC_BIT) ++#define SD_SDHFC_DIV16 (6 << SDHFC_BIT) ++#define SD_SDHFC_DIV18 (7 << SDHFC_BIT) ++#define SD_SDHFC_DIV24 (8 << SDHFC_BIT) ++#define SD_SDHFC_DIV36 (10 << SDHFC_BIT) ++#define SD_SDHFC_DIV48 (11 << SDHFC_BIT) ++#define SD0FC_BIT (4) ++#define SD_SD0FC_DIV8 (4 << SD0FC_BIT) ++#define SD_SD0FC_DIV10 (12 << SD0FC_BIT) ++#define SD_SD0FC_DIV12 (5 << SD0FC_BIT) ++#define SD_SD0FC_DIV16 (6 << SD0FC_BIT) ++#define SD_SD0FC_DIV18 (7 << SD0FC_BIT) ++#define SD_SD0FC_DIV24 (8 << SD0FC_BIT) ++#define SD_SD0FC_DIV36 (10 << SD0FC_BIT) ++#define SD_SD0FC_DIV48 (11 << SD0FC_BIT) ++ + int rcar_get_sdhi_config_clk(void) + { + if (RCAR_PRR_IS_PRODUCT(H3) && (!RCAR_PRR_CHK_CUT(H3, WS10))) + return SDH400_SD200; ++ else if (RCAR_PRR_IS_PRODUCT(V3M)) ++ return (SD_SDHFC_DIV2 | SD_SD0FC_DIV8); + else + return SDH800_SD200; + } +diff --git a/arch/arm/include/asm/arch-rcar_gen3/gpio.h b/arch/arm/include/asm/arch-rcar_gen3/gpio.h +index c58edf4..fb8b758 100644 +--- a/arch/arm/include/asm/arch-rcar_gen3/gpio.h ++++ b/arch/arm/include/asm/arch-rcar_gen3/gpio.h +@@ -16,6 +16,8 @@ + #include <asm/arch/r8a7795-gpio.h> + #elif defined(CONFIG_R8A7796X) + #include <asm/arch/r8a7796-gpio.h> ++#elif defined(CONFIG_R8A7797) ++#include <asm/arch/r8a7797-gpio.h> + #endif + + #if defined(CONFIG_R8A7795) +@@ -23,6 +25,8 @@ void r8a7795_pinmux_init(void); + void r8a7795_es_pinmux_init(void); + #elif defined(CONFIG_R8A7796X) + void r8a7796_pinmux_init(void); ++#elif defined(CONFIG_R8A7797) ++void r8a7797_pinmux_init(void); + #endif + void pinmux_init(void); + +diff --git a/arch/arm/include/asm/arch-rcar_gen3/r8a7797-gpio.h b/arch/arm/include/asm/arch-rcar_gen3/r8a7797-gpio.h +new file mode 100644 +index 0000000..40cccd9 +--- /dev/null ++++ b/arch/arm/include/asm/arch-rcar_gen3/r8a7797-gpio.h +@@ -0,0 +1,456 @@ ++/* ++ * arch/arm/include/asm/arch-rcar_gen3/r8a7797-gpio.h ++ * This file defines pin function control of gpio. ++ * ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++#ifndef __ASM_R8A7797_GPIO_H__ ++#define __ASM_R8A7797_GPIO_H__ ++ ++/* Pin Function Controller: ++ * GPIO_FN_xx - GPIO used to select pin function ++ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU ++ */ ++enum { ++ GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, ++ GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, ++ GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, ++ GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, ++ GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, ++ GPIO_GP_0_20, GPIO_GP_0_21, ++ ++ GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, ++ GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, ++ GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, ++ GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, ++ GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, ++ GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, ++ GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, ++ ++ GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, ++ GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, ++ GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, ++ GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, ++ GPIO_GP_2_16, ++ ++ GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, ++ GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, ++ GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, ++ GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, ++ GPIO_GP_3_16, ++ ++ GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, ++ GPIO_GP_4_4, GPIO_GP_4_5, ++ ++ GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, ++ GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, ++ GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, ++ GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, ++ ++ /* GPSR0 */ ++ GPIO_GFN_DU_EXODDF_DU_ODDF_DISP_CDE, ++ GPIO_GFN_DU_EXVSYNC_DU_VSYNC, ++ GPIO_GFN_DU_EXHSYNC_DU_HSYNC, ++ GPIO_GFN_DU_DOTCLKOUT, ++ GPIO_GFN_DU_DB7, ++ GPIO_GFN_DU_DB6, ++ GPIO_GFN_DU_DB5, ++ GPIO_GFN_DU_DB4, ++ GPIO_GFN_DU_DB3, ++ GPIO_GFN_DU_DB2, ++ GPIO_GFN_DU_DG7, ++ GPIO_GFN_DU_DG6, ++ GPIO_GFN_DU_DG5, ++ GPIO_GFN_DU_DG4, ++ GPIO_GFN_DU_DG3, ++ GPIO_GFN_DU_DG2, ++ GPIO_GFN_DU_DR7, ++ GPIO_GFN_DU_DR6, ++ GPIO_GFN_DU_DR5, ++ GPIO_GFN_DU_DR4, ++ GPIO_GFN_DU_DR3, ++ GPIO_GFN_DU_DR2, ++ ++ /* GPSR1 */ ++ GPIO_GFN_DIGRF_CLKOUT, ++ GPIO_GFN_DIGRF_CLKIN, ++ GPIO_GFN_CANFD_CLK_A, ++ GPIO_GFN_CANFD1_RX, ++ GPIO_GFN_CANFD1_TX, ++ GPIO_GFN_CANFD0_RX_A, ++ GPIO_GFN_CANFD0_TX_A, ++ GPIO_GFN_AVB0_AVTP_CAPTURE, ++ GPIO_FN_AVB0_AVTP_MATCH, ++ GPIO_FN_AVB0_LINK, ++ GPIO_FN_AVB0_PHY_INT, ++ GPIO_FN_AVB0_MAGIC, ++ GPIO_FN_AVB0_MDC, ++ GPIO_FN_AVB0_MDIO, ++ GPIO_FN_AVB0_TXCREFCLK, ++ GPIO_FN_AVB0_TD3, ++ GPIO_FN_AVB0_TD2, ++ GPIO_FN_AVB0_TD1, ++ GPIO_FN_AVB0_TD0, ++ GPIO_FN_AVB0_TXC, ++ GPIO_FN_AVB0_TX_CTL, ++ GPIO_FN_AVB0_RD3, ++ GPIO_FN_AVB0_RD2, ++ GPIO_FN_AVB0_RD1, ++ GPIO_FN_AVB0_RD0, ++ GPIO_FN_AVB0_RXC, ++ GPIO_FN_AVB0_RX_CTL, ++ GPIO_GFN_IRQ0, ++ ++ /* GPSR2 */ ++ GPIO_GFN_VI0_FIELD, ++ GPIO_GFN_VI0_DATA11, ++ GPIO_GFN_VI0_DATA10, ++ GPIO_GFN_VI0_DATA9, ++ GPIO_GFN_VI0_DATA8, ++ GPIO_GFN_VI0_DATA7, ++ GPIO_GFN_VI0_DATA6, ++ GPIO_GFN_VI0_DATA5, ++ GPIO_GFN_VI0_DATA4, ++ GPIO_GFN_VI0_DATA3, ++ GPIO_GFN_VI0_DATA2, ++ GPIO_GFN_VI0_DATA1, ++ GPIO_GFN_VI0_DATA0, ++ GPIO_GFN_VI0_VSYNC_N, ++ GPIO_GFN_VI0_HSYNC_N, ++ GPIO_GFN_VI0_CLKENB, ++ GPIO_GFN_VI0_CLK, ++ ++ /* GPSR3 */ ++ GPIO_GFN_VI1_FIELD, ++ GPIO_GFN_VI1_DATA11, ++ GPIO_GFN_VI1_DATA10, ++ GPIO_GFN_VI1_DATA9, ++ GPIO_GFN_VI1_DATA8, ++ GPIO_GFN_VI1_DATA7, ++ GPIO_GFN_VI1_DATA6, ++ GPIO_GFN_VI1_DATA5, ++ GPIO_GFN_VI1_DATA4, ++ GPIO_GFN_VI1_DATA3, ++ GPIO_GFN_VI1_DATA2, ++ GPIO_GFN_VI1_DATA1, ++ GPIO_GFN_VI1_DATA0, ++ GPIO_GFN_VI1_VSYNC_N, ++ GPIO_GFN_VI1_HSYNC_N, ++ GPIO_GFN_VI1_CLKENB, ++ GPIO_GFN_VI1_CLK, ++ ++ /* GPSR4 */ ++ GPIO_GFN_SDA2, ++ GPIO_GFN_SCL2, ++ GPIO_GFN_SDA1, ++ GPIO_GFN_SCL1, ++ GPIO_GFN_SDA0, ++ GPIO_GFN_SCL0, ++ ++ /* GPSR5 */ ++ GPIO_FN_RPC_INT_N, ++ GPIO_FN_RPC_WP_N, ++ GPIO_FN_RPC_RESET_N, ++ GPIO_FN_QSPI1_SSL, ++ GPIO_FN_QSPI1_IO3, ++ GPIO_FN_QSPI1_IO2, ++ GPIO_FN_QSPI1_MISO_IO1, ++ GPIO_FN_QSPI1_MOSI_IO0, ++ GPIO_FN_QSPI1_SPCLK, ++ GPIO_FN_QSPI0_SSL, ++ GPIO_FN_QSPI0_IO3, ++ GPIO_FN_QSPI0_IO2, ++ GPIO_FN_QSPI0_MISO_IO1, ++ GPIO_FN_QSPI0_MOSI_IO0, ++ GPIO_FN_QSPI0_SPCLK, ++ ++ /* IPSR0 */ ++ GPIO_IFN_DU_DR2, ++ GPIO_FN_HSCK0, ++ GPIO_FN_A0, ++ GPIO_IFN_DU_DR3, ++ GPIO_FN_HRTS0_N, ++ GPIO_FN_A1, ++ GPIO_IFN_DU_DR4, ++ GPIO_FN_HCTS0_N, ++ GPIO_FN_A2, ++ GPIO_IFN_DU_DR5, ++ GPIO_FN_HTX0, ++ GPIO_FN_A3, ++ GPIO_IFN_DU_DR6, ++ GPIO_FN_MSIOF3_RXD, ++ GPIO_FN_A4, ++ GPIO_IFN_DU_DR7, ++ GPIO_FN_MSIOF3_TXD, ++ GPIO_FN_A5, ++ GPIO_IFN_DU_DG2, ++ GPIO_FN_MSIOF3_SS1, ++ GPIO_FN_A6, ++ GPIO_IFN_DU_DG3, ++ GPIO_FN_MSIOF3_SS2, ++ GPIO_FN_A7, ++ GPIO_FN_PWMFSW0, ++ ++ /* IPSR1 */ ++ GPIO_IFN_DU_DG4, ++ GPIO_FN_A8, ++ GPIO_FN_FSO_CFE_0_N_A, ++ GPIO_IFN_DU_DG5, ++ GPIO_FN_A9, ++ GPIO_FN_FSO_CFE_1_N_A, ++ GPIO_IFN_DU_DG6, ++ GPIO_FN_A10, ++ GPIO_FN_FSO_TOE_N_A, ++ GPIO_IFN_DU_DG7, ++ GPIO_FN_A11, ++ GPIO_FN_IRQ1, ++ GPIO_IFN_DU_DB2, ++ GPIO_FN_A12, ++ GPIO_FN_IRQ2, ++ GPIO_IFN_DU_DB3, ++ GPIO_FN_A13, ++ GPIO_FN_FXR_CLKOUT1, ++ GPIO_IFN_DU_DB4, ++ GPIO_FN_A14, ++ GPIO_FN_FXR_CLKOUT2, ++ GPIO_IFN_DU_DB5, ++ GPIO_FN_A15, ++ GPIO_FN_FXR_TXENA_N, ++ ++ /* IPSR2 */ ++ GPIO_IFN_DU_DB6, ++ GPIO_FN_A16, ++ GPIO_FN_FXR_TXENB_N, ++ GPIO_IFN_DU_DB7, ++ GPIO_FN_A17, ++ GPIO_FN_STPWT_EXTFXR, ++ GPIO_IFN_DU_DOTCLKOUT, ++ GPIO_FN_SCIF_CLK_A, ++ GPIO_FN_A18, ++ GPIO_IFN_DU_EXHSYNC_DU_HSYNC, ++ GPIO_FN_HRX0, ++ GPIO_FN_A19, ++ GPIO_FN_IRQ3, ++ GPIO_IFN_DU_EXVSYNC_DU_VSYNC, ++ GPIO_FN_MSIOF3_SCK, ++ GPIO_FN_A20, ++ GPIO_IFN_DU_EXODDF_DU_ODDF_DISP_CDE, ++ GPIO_FN_MSIOF3_SYNC, ++ GPIO_FN_A21, ++ GPIO_IFN_IRQ0, ++ GPIO_FN_CC5_OSCOUT, ++ GPIO_IFN_VI0_CLK, ++ GPIO_FN_MSIOF2_SCK, ++ GPIO_FN_SCK3, ++ GPIO_FN_HSCK3, ++ ++ /* IPSR3 */ ++ GPIO_IFN_VI0_CLKENB, ++ GPIO_FN_MSIOF2_RXD, ++ GPIO_FN_RX3, ++ GPIO_FN_RD_WR_N, ++ GPIO_FN_HCTS3_N, ++ GPIO_IFN_VI0_HSYNC_N, ++ GPIO_FN_MSIOF2_TXD, ++ GPIO_FN_TX3, ++ GPIO_FN_HRTS3_N, ++ GPIO_IFN_VI0_VSYNC_N, ++ GPIO_FN_MSIOF2_SYNC, ++ GPIO_FN_CTS3_N, ++ GPIO_FN_HTX3, ++ GPIO_IFN_VI0_DATA0, ++ GPIO_FN_MSIOF2_SS1, ++ GPIO_FN_RTS3_N_TANS, ++ GPIO_FN_HRX3, ++ GPIO_IFN_VI0_DATA1, ++ GPIO_FN_MSIOF2_SS2, ++ GPIO_FN_SCK1, ++ GPIO_FN_SPEEDIN_A, ++ GPIO_IFN_VI0_DATA2, ++ GPIO_FN_AVB0_AVTP_PPS, ++ GPIO_FN_SDA3_A, ++ GPIO_IFN_VI0_DATA3, ++ GPIO_FN_HSCK1, ++ GPIO_FN_SCL3_A, ++ GPIO_IFN_VI0_DATA4, ++ GPIO_FN_HRTS1_N, ++ GPIO_FN_RX1_A, ++ ++ /* IPSR4 */ ++ GPIO_IFN_VI0_DATA5, ++ GPIO_FN_HCTS1_N, ++ GPIO_FN_TX1_A, ++ GPIO_IFN_VI0_DATA6, ++ GPIO_FN_HTX1, ++ GPIO_FN_CTS1_N, ++ GPIO_IFN_VI0_DATA7, ++ GPIO_FN_HRX1, ++ GPIO_FN_RTS1_N_TANS, ++ GPIO_IFN_VI0_DATA8, ++ GPIO_FN_HSCK2, ++ GPIO_FN_PWM0_A, ++ GPIO_FN_A22, ++ GPIO_IFN_VI0_DATA9, ++ GPIO_FN_HCTS2_N, ++ GPIO_FN_PWM1_A, ++ GPIO_FN_A23, ++ GPIO_FN_FSO_CFE_0_N_B, ++ GPIO_IFN_VI0_DATA10, ++ GPIO_FN_HRTS2_N, ++ GPIO_FN_PWM2_A, ++ GPIO_FN_A24, ++ GPIO_FN_FSO_CFE_1_N_B, ++ GPIO_IFN_VI0_DATA11, ++ GPIO_FN_HTX2, ++ GPIO_FN_PWM3_A, ++ GPIO_FN_A25, ++ GPIO_FN_FSO_TOE_N_B, ++ GPIO_IFN_VI0_FIELD, ++ GPIO_FN_HRX2, ++ GPIO_FN_PWM4_A, ++ GPIO_FN_CS1_N_A26, ++ GPIO_FN_FSCLKST2_N_A, ++ ++ /* IPSR5 */ ++ GPIO_IFN_VI1_CLK, ++ GPIO_FN_MSIOF1_RXD, ++ GPIO_FN_CS0_N, ++ GPIO_IFN_VI1_CLKENB, ++ GPIO_FN_MSIOF1_TXD, ++ GPIO_FN_D0, ++ GPIO_IFN_VI1_HSYNC_N, ++ GPIO_FN_MSIOF1_SCK, ++ GPIO_FN_D1, ++ GPIO_IFN_VI1_VSYNC_N, ++ GPIO_FN_MSIOF1_SYNC, ++ GPIO_FN_D2, ++ GPIO_IFN_VI1_DATA0, ++ GPIO_FN_MSIOF1_SS1, ++ GPIO_FN_D3, ++ GPIO_IFN_VI1_DATA1, ++ GPIO_FN_MSIOF1_SS2, ++ GPIO_FN_D4, ++ GPIO_FN_MMC_CMD, ++ GPIO_IFN_VI1_DATA2, ++ GPIO_FN_CANFD0_TX_B, ++ GPIO_FN_D5, ++ GPIO_FN_MMC_D0, ++ GPIO_IFN_VI1_DATA3, ++ GPIO_FN_CANFD0_RX_B, ++ GPIO_FN_D6, ++ GPIO_FN_MMC_D1, ++ ++ /* IPSR6 */ ++ GPIO_IFN_VI1_DATA4, ++ GPIO_FN_CANFD_CLK_B, ++ GPIO_FN_D7, ++ GPIO_FN_MMC_D2, ++ GPIO_IFN_VI1_DATA5, ++ GPIO_FN_SCK4, ++ GPIO_FN_D8, ++ GPIO_FN_MMC_D3, ++ GPIO_IFN_VI1_DATA6, ++ GPIO_FN_RX4, ++ GPIO_FN_D9, ++ GPIO_FN_MMC_CLK, ++ GPIO_IFN_VI1_DATA7, ++ GPIO_FN_TX4, ++ GPIO_FN_D10, ++ GPIO_FN_MMC_D4, ++ GPIO_IFN_VI1_DATA8, ++ GPIO_FN_CTS4_N, ++ GPIO_FN_D11, ++ GPIO_FN_MMC_D5, ++ GPIO_IFN_VI1_DATA9, ++ GPIO_FN_RTS4_N_TANS, ++ GPIO_FN_D12, ++ GPIO_FN_MMC_D6, ++ GPIO_FN_SCL3_B, ++ GPIO_IFN_VI1_DATA10, ++ GPIO_FN_D13, ++ GPIO_FN_MMC_D7, ++ GPIO_FN_SDA3_B, ++ GPIO_IFN_VI1_DATA11, ++ GPIO_FN_SCL4, ++ GPIO_FN_IRQ4, ++ GPIO_FN_D14, ++ GPIO_FN_MMC_WP, ++ ++ /* IPSR7 */ ++ GPIO_IFN_VI1_FIELD, ++ GPIO_FN_SDA4, ++ GPIO_FN_IRQ5, ++ GPIO_FN_D15, ++ GPIO_FN_MMC_CD, ++ GPIO_IFN_SCL0, ++ GPIO_FN_DU_DR0, ++ GPIO_FN_TPU0TO0, ++ GPIO_FN_CLKOUT, ++ GPIO_FN_MSIOF0_RXD, ++ GPIO_IFN_SDA0, ++ GPIO_FN_DU_DR1, ++ GPIO_FN_TPU0TO1, ++ GPIO_FN_BS_N, ++ GPIO_FN_SCK0, ++ GPIO_FN_MSIOF0_TXD, ++ GPIO_IFN_SCL1, ++ GPIO_FN_DU_DG0, ++ GPIO_FN_TPU0TO2, ++ GPIO_FN_RD_N, ++ GPIO_FN_CTS0_N, ++ GPIO_FN_MSIOF0_SCK, ++ GPIO_IFN_SDA1, ++ GPIO_FN_DU_DG1, ++ GPIO_FN_TPU0TO3, ++ GPIO_FN_WE0_N, ++ GPIO_FN_RTS0_N_TANS, ++ GPIO_FN_MSIOF0_SYNC, ++ GPIO_IFN_SCL2, ++ GPIO_FN_DU_DB0, ++ GPIO_FN_TCLK1_A, ++ GPIO_FN_WE1_N, ++ GPIO_FN_RX0, ++ GPIO_FN_MSIOF0_SS1, ++ GPIO_IFN_SDA2, ++ GPIO_FN_DU_DB1, ++ GPIO_FN_TCLK2_A, ++ GPIO_FN_EX_WAIT0, ++ GPIO_FN_TX0, ++ GPIO_FN_MSIOF0_SS2, ++ GPIO_IFN_AVB0_AVTP_CAPTURE, ++ GPIO_FN_FSCLKST2_N_B, ++ ++ /* IPSR8 */ ++ GPIO_IFN_CANFD0_TX_A, ++ GPIO_FN_FXR_TXDA, ++ GPIO_FN_PWM0_B, ++ GPIO_FN_DU_DISP, ++ GPIO_FN_FSCLKST2_N_C, ++ GPIO_IFN_CANFD0_RX_A, ++ GPIO_FN_RXDA_EXTFXR, ++ GPIO_FN_PWM1_B, ++ GPIO_FN_DU_CDE, ++ GPIO_IFN_CANFD1_TX, ++ GPIO_FN_FXR_TXDB, ++ GPIO_FN_PWM2_B, ++ GPIO_FN_TCLK1_B, ++ GPIO_FN_TX1_B, ++ GPIO_IFN_CANFD1_RX, ++ GPIO_FN_RXDB_EXTFXR, ++ GPIO_FN_PWM3_B, ++ GPIO_FN_TCLK2_B, ++ GPIO_FN_RX1_B, ++ GPIO_IFN_CANFD_CLK_A, ++ GPIO_FN_CLK_EXTFXR, ++ GPIO_FN_PWM4_B, ++ GPIO_FN_SPEEDIN_B, ++ GPIO_FN_SCIF_CLK_B, ++ GPIO_IFN_DIGRF_CLKIN, ++ GPIO_FN_DIGRF_CLKEN_IN, ++ GPIO_IFN_DIGRF_CLKOUT, ++ GPIO_FN_DIGRF_CLKEN_OUT, ++}; ++ ++#endif /* __ASM_R8A7797_GPIO_H__ */ +diff --git a/arch/arm/include/asm/arch-rcar_gen3/r8a7797.h b/arch/arm/include/asm/arch-rcar_gen3/r8a7797.h +new file mode 100644 +index 0000000..09e83ba +--- /dev/null ++++ b/arch/arm/include/asm/arch-rcar_gen3/r8a7797.h +@@ -0,0 +1,33 @@ ++/* ++ * arch/arm/include/asm/arch-rcar_gen3/r8a7797.h ++ * This file defines registers and value for r8a7797. ++ * ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __ASM_ARCH_R8A7797_H ++#define __ASM_ARCH_R8A7797_H ++ ++#include "rcar-base.h" ++ ++/* Module stop control/status register bits */ ++#define MSTP0_BITS 0x00230000 ++#define MSTP1_BITS 0xFFFFFFFF ++#define MSTP2_BITS 0x14062FD8 ++#define MSTP3_BITS 0xFFFFFFDF ++#define MSTP4_BITS 0x80000184 ++#define MSTP5_BITS 0x83FFFFFF ++#define MSTP6_BITS 0xFFFFFFFF ++#define MSTP7_BITS 0xFFFFFFFF ++#define MSTP8_BITS 0x7FF3FFF4 ++#define MSTP9_BITS 0xFBF7FF97 ++#define MSTP10_BITS 0xFFFEFFE0 ++#define MSTP11_BITS 0x000000B7 ++ ++/* SDHI */ ++#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */ ++#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1 ++ ++#endif /* __ASM_ARCH_R8A7797_H */ +diff --git a/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h b/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h +index 18c1a74..fa24fc4 100644 +--- a/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h ++++ b/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h +@@ -70,6 +70,11 @@ + #define SMSTPCR10 0xE6150998 + #define SMSTPCR11 0xE615099C + ++/* PLL */ ++#define PLL0CR 0xE61500D8 ++#define PLL0_STC_MASK 0x7F000000 ++#define PLL0_STC_BIT 24 ++ + /* SH-I2C */ + #define CONFIG_SYS_I2C_SH_BASE0 0xE60B0000 + +diff --git a/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h b/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h +index b412fad..c2ba0fb 100644 +--- a/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h ++++ b/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h +@@ -14,6 +14,8 @@ + #include <asm/arch/r8a7795.h> + #elif defined(CONFIG_R8A7796X) + #include <asm/arch/r8a7796.h> ++ #elif defined(CONFIG_R8A7797) ++ #include <asm/arch/r8a7797.h> + #else + #error "SOC Name not defined" + #endif +diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h +index fe71e9a..478824e 100644 +--- a/drivers/serial/serial_sh.h ++++ b/drivers/serial/serial_sh.h +@@ -226,7 +226,8 @@ struct uart_port { + # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ + #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) || \ +- defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796X) ++ defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796X) || \ ++ defined(CONFIG_R8A7797) + # define SCIF_ORER 0x0001 + # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30) + /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ +diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h +index 0a959f7..ec20aba 100644 +--- a/include/configs/rcar-gen3-common.h ++++ b/include/configs/rcar-gen3-common.h +@@ -93,7 +93,11 @@ + #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 } + + /* MEMORY */ ++#if defined(CONFIG_R8A7797) ++#define CONFIG_SYS_TEXT_BASE 0x58280000 ++#else + #define CONFIG_SYS_TEXT_BASE 0x50000000 ++#endif + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7fff0) + + +@@ -124,6 +128,14 @@ + #define PHYS_SDRAM_1_SIZE ((unsigned long)(0x80000000 - DRAM_RSV_SIZE)) + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE ++#elif defined(CONFIG_R8A7797) ++#define CONFIG_NR_DRAM_BANKS 1 ++#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE) /* legacy */ ++#define PHYS_SDRAM_1_SIZE ((unsigned long)(0x40000000 - DRAM_RSV_SIZE)) ++#define PHYS_SDRAM_2 0x0600000000 /* ext */ ++#define PHYS_SDRAM_2_SIZE ((unsigned long)0x80000000) ++#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 ++#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE + #else + #define CONFIG_NR_DRAM_BANKS 1 + #define CONFIG_SYS_SDRAM_BASE 0x40000000 +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0015-board-renesas-Add-V3M-Eagle-board.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0015-board-renesas-Add-V3M-Eagle-board.patch new file mode 100644 index 0000000..5b300eb --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0015-board-renesas-Add-V3M-Eagle-board.patch @@ -0,0 +1,499 @@ +From 423d01a1b367d82a3855972483530968309cbbd4 Mon Sep 17 00:00:00 2001 +From: Daisuke Matsushita <daisuke.matsushita.ns@hitachi.com> +Date: Tue, 21 Mar 2017 15:05:15 +0900 +Subject: [PATCH] board: renesas: Add V3M Eagle board + +V3M Eagle is a board based on R-Car V3M SoC (R8A7797) + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +--- + arch/arm/cpu/armv8/Kconfig | 4 + + board/renesas/eagle/Kconfig | 15 +++ + board/renesas/eagle/MAINTAINERS | 6 ++ + board/renesas/eagle/Makefile | 9 ++ + board/renesas/eagle/eagle.c | 224 ++++++++++++++++++++++++++++++++++++++++ + configs/r8a7797_eagle_defconfig | 9 ++ + include/configs/r8a7797_eagle.h | 152 +++++++++++++++++++++++++++ + 7 files changed, 419 insertions(+) + create mode 100644 board/renesas/eagle/Kconfig + create mode 100644 board/renesas/eagle/MAINTAINERS + create mode 100644 board/renesas/eagle/Makefile + create mode 100644 board/renesas/eagle/eagle.c + create mode 100644 configs/r8a7797_eagle_defconfig + create mode 100644 include/configs/r8a7797_eagle.h + +diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig +index dfd9bab..c857214 100644 +--- a/arch/arm/cpu/armv8/Kconfig ++++ b/arch/arm/cpu/armv8/Kconfig +@@ -16,6 +16,9 @@ config TARGET_SALVATOR_X + config TARGET_ULCB + bool "ULCB board" + ++config TARGET_EAGLE ++ bool "EAGLE board" ++ + endchoice + + config R8A7796X +@@ -45,5 +48,6 @@ config SYS_SOC + + source "board/renesas/salvator-x/Kconfig" + source "board/renesas/ulcb/Kconfig" ++source "board/renesas/eagle/Kconfig" + + endif +diff --git a/board/renesas/eagle/Kconfig b/board/renesas/eagle/Kconfig +new file mode 100644 +index 0000000..dffbbeb +--- /dev/null ++++ b/board/renesas/eagle/Kconfig +@@ -0,0 +1,15 @@ ++if TARGET_EAGLE ++ ++config SYS_SOC ++ default "rcar_gen3" ++ ++config SYS_BOARD ++ default "eagle" ++ ++config SYS_VENDOR ++ default "renesas" ++ ++config SYS_CONFIG_NAME ++ default "r8a7797_eagle" if R8A7797 ++ ++endif +diff --git a/board/renesas/eagle/MAINTAINERS b/board/renesas/eagle/MAINTAINERS +new file mode 100644 +index 0000000..c411373 +--- /dev/null ++++ b/board/renesas/eagle/MAINTAINERS +@@ -0,0 +1,6 @@ ++EAGLE BOARD ++M: foo <foo@renesas.com> ++S: Maintained ++F: board/renesas/eagle/ ++F: include/configs/r8a7797_eagle.h ++F: configs/r8a7797_eagle_defconfig +diff --git a/board/renesas/eagle/Makefile b/board/renesas/eagle/Makefile +new file mode 100644 +index 0000000..87d63e1 +--- /dev/null ++++ b/board/renesas/eagle/Makefile +@@ -0,0 +1,9 @@ ++# ++# board/renesas/eagle/Makefile ++# ++# Copyright (C) 2016 Renesas Electronics Corporation ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++obj-y := eagle.o ../rcar-gen3-common/common.o +diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c +new file mode 100644 +index 0000000..4eda15c +--- /dev/null ++++ b/board/renesas/eagle/eagle.c +@@ -0,0 +1,224 @@ ++/* ++ * board/renesas/eagle/eagle.c ++ * This file is Eagle board support. ++ * ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <malloc.h> ++#include <netdev.h> ++#include <dm.h> ++#include <dm/platform_data/serial_sh.h> ++#include <asm/processor.h> ++#include <asm/mach-types.h> ++#include <asm/io.h> ++#include <asm/errno.h> ++#include <asm/arch/sys_proto.h> ++#include <asm/gpio.h> ++#include <asm/arch/prr_depend.h> ++#include <asm/arch/gpio.h> ++#include <asm/arch/rcar_gen3.h> ++#include <asm/arch/rcar-mstp.h> ++#include <asm/arch/sh_sdhi.h> ++#include <i2c.h> ++#include <mmc.h> ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define SCIF0_MSTP207 (1 << 7) ++#define ETHERAVB_MSTP812 (1 << 12) ++#define RPC_MSTP917 (1 << 17) ++ ++#define CLK2MHZ(clk) (clk / 1000 / 1000) ++void s_init(void) ++{ ++ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; ++ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; ++ u32 stc; ++ ++ /* Watchdog init */ ++ writel(0xA5A5A500, &rwdt->rwtcsra); ++ writel(0xA5A5A500, &swdt->swtcsra); ++ ++ /* CPU frequency setting. Set to 0.8GHz */ ++ stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; ++ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); ++} ++ ++int board_early_init_f(void) ++{ ++ rcar_prr_init(); ++ ++ writel(0xa5a5ffff, 0xe6150900); ++ writel(0x5a5a0000, 0xe6150904); ++ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, 0x02000000); ++ /* SCIF0 */ ++ mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIF0_MSTP207); ++ /* EHTERAVB */ ++ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812); ++ /* QSPI */ ++ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, RPC_MSTP917); ++ ++ return 0; ++} ++ ++int board_init(void) ++{ ++ /* adress of boot parameters */ ++ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; ++ ++ /* Init PFC controller */ ++ pinmux_init(); ++ ++#ifdef CONFIG_RAVB ++ /* GPSR1 */ ++ gpio_request(GPIO_GFN_AVB0_AVTP_CAPTURE, NULL); ++ gpio_request(GPIO_FN_AVB0_AVTP_MATCH, NULL); ++ gpio_request(GPIO_FN_AVB0_LINK, NULL); ++ gpio_request(GPIO_FN_AVB0_PHY_INT, NULL); ++ gpio_request(GPIO_FN_AVB0_MAGIC, NULL); ++ gpio_request(GPIO_FN_AVB0_MDC, NULL); ++ gpio_request(GPIO_FN_AVB0_MDIO, NULL); ++ gpio_request(GPIO_FN_AVB0_TXCREFCLK, NULL); ++ gpio_request(GPIO_FN_AVB0_TD3, NULL); ++ gpio_request(GPIO_FN_AVB0_TD2, NULL); ++ gpio_request(GPIO_FN_AVB0_TD1, NULL); ++ gpio_request(GPIO_FN_AVB0_TD0, NULL); ++ gpio_request(GPIO_FN_AVB0_TXC, NULL); ++ gpio_request(GPIO_FN_AVB0_TX_CTL, NULL); ++ gpio_request(GPIO_FN_AVB0_RD3, NULL); ++ gpio_request(GPIO_FN_AVB0_RD2, NULL); ++ gpio_request(GPIO_FN_AVB0_RD1, NULL); ++ gpio_request(GPIO_FN_AVB0_RD0, NULL); ++ gpio_request(GPIO_FN_AVB0_RXC, NULL); ++ gpio_request(GPIO_FN_AVB0_RX_CTL, NULL); ++ ++ /* IPSR7 */ ++ gpio_request(GPIO_IFN_AVB0_AVTP_CAPTURE, NULL); ++ /* IPSR3 */ ++ gpio_request(GPIO_FN_AVB0_AVTP_PPS, NULL); ++ ++ /* AVB_PHY_RST */ ++ gpio_request(GPIO_GP_1_16, NULL); ++ gpio_direction_output(GPIO_GP_1_16, 0); ++ mdelay(20); ++ gpio_set_value(GPIO_GP_1_16, 1); ++ udelay(1); ++#endif ++ ++ /* QSPI */ ++#if !defined(CONFIG_SYS_NO_FLASH) ++ gpio_request(GPIO_FN_QSPI0_SPCLK, NULL); ++ gpio_request(GPIO_FN_QSPI0_MOSI_IO0, NULL); ++ gpio_request(GPIO_FN_QSPI0_MISO_IO1, NULL); ++ gpio_request(GPIO_FN_QSPI0_IO2, NULL); ++ gpio_request(GPIO_FN_QSPI0_IO3, NULL); ++ gpio_request(GPIO_FN_QSPI0_SSL, NULL); ++ gpio_request(GPIO_FN_QSPI1_SPCLK, NULL); ++ gpio_request(GPIO_FN_QSPI1_MOSI_IO0, NULL); ++ gpio_request(GPIO_FN_QSPI1_MISO_IO1, NULL); ++ gpio_request(GPIO_FN_QSPI1_IO2, NULL); ++ gpio_request(GPIO_FN_QSPI1_IO3, NULL); ++ gpio_request(GPIO_FN_QSPI1_SSL, NULL); ++ gpio_request(GPIO_FN_RPC_RESET_N, NULL); ++ gpio_request(GPIO_FN_RPC_WP_N, NULL); ++ gpio_request(GPIO_FN_RPC_INT_N, NULL); ++#endif ++ return 0; ++} ++ ++#define MAHR 0xE68005C0 ++#define MALR 0xE68005C8 ++int board_eth_init(bd_t *bis) ++{ ++ int ret = -ENODEV; ++ u32 val; ++ unsigned char enetaddr[6]; ++ ++ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) ++ return ret; ++ ++ /* Set Mac address */ ++ val = enetaddr[0] << 24 | enetaddr[1] << 16 | ++ enetaddr[2] << 8 | enetaddr[3]; ++ writel(val, MAHR); ++ ++ val = enetaddr[4] << 8 | enetaddr[5]; ++ writel(val, MALR); ++ ++#ifdef CONFIG_RAVB ++ ret = ravb_initialize(bis); ++#endif ++ return ret; ++} ++ ++/* Salvator-X has KSZ9031RNX */ ++/* Tri-color dual-LED mode(Pin 41 pull-down) */ ++int board_phy_config(struct phy_device *phydev) ++{ ++ /* hardware use default(Tri-color:0) setting. */ ++ ++ return 0; ++} ++ ++int board_mmc_init(bd_t *bis) ++{ ++ return -ENODEV; ++} ++ ++ ++int dram_init(void) ++{ ++ gd->ram_size = PHYS_SDRAM_1_SIZE; ++#if (CONFIG_NR_DRAM_BANKS >= 2) ++ gd->ram_size += PHYS_SDRAM_2_SIZE; ++#endif ++#if (CONFIG_NR_DRAM_BANKS >= 3) ++ gd->ram_size += PHYS_SDRAM_3_SIZE; ++#endif ++#if (CONFIG_NR_DRAM_BANKS >= 4) ++ gd->ram_size += PHYS_SDRAM_4_SIZE; ++#endif ++ ++ return 0; ++} ++ ++void dram_init_banksize(void) ++{ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++#if (CONFIG_NR_DRAM_BANKS >= 2) ++ gd->bd->bi_dram[1].start = PHYS_SDRAM_2; ++ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; ++#endif ++#if (CONFIG_NR_DRAM_BANKS >= 3) ++ gd->bd->bi_dram[2].start = PHYS_SDRAM_3; ++ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; ++#endif ++#if (CONFIG_NR_DRAM_BANKS >= 4) ++ gd->bd->bi_dram[3].start = PHYS_SDRAM_4; ++ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; ++#endif ++} ++ ++const struct rcar_sysinfo sysinfo = { ++ CONFIG_RCAR_BOARD_STRING ++}; ++ ++void reset_cpu(ulong addr) ++{ ++#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) ++ i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80); ++#endif ++} ++ ++#if defined(CONFIG_DISPLAY_BOARDINFO) ++int checkboard(void) ++{ ++ printf("Board: %s\n", sysinfo.board_string); ++ return 0; ++} ++#endif +diff --git a/configs/r8a7797_eagle_defconfig b/configs/r8a7797_eagle_defconfig +new file mode 100644 +index 0000000..d68e28f +--- /dev/null ++++ b/configs/r8a7797_eagle_defconfig +@@ -0,0 +1,9 @@ ++CONFIG_ARM=y ++CONFIG_RCAR_GEN3=y ++CONFIG_DM_SERIAL=y ++CONFIG_TARGET_EAGLE=y ++CONFIG_R8A7797=y ++CONFIG_SPL=y ++CONFIG_SH_SDHI=y ++CONFIG_SPI_FLASH=y ++CONFIG_SPI_FLASH_SPANSION=y +diff --git a/include/configs/r8a7797_eagle.h b/include/configs/r8a7797_eagle.h +new file mode 100644 +index 0000000..a4ae6bf +--- /dev/null ++++ b/include/configs/r8a7797_eagle.h +@@ -0,0 +1,152 @@ ++/* ++ * include/configs/eagle.h ++ * This file is eagle board configuration. ++ * CPU r8a7797. ++ * ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __EAGLE_H ++#define __EAGLE_H ++ ++#undef DEBUG ++#define CONFIG_RCAR_BOARD_STRING "R-Car EAGLE" ++#define CONFIG_RCAR_TARGET_STRING "r8a7797" ++ ++#include "rcar-gen3-common.h" ++ ++/* Cache Definitions */ ++#define CONFIG_SYS_DCACHE_OFF ++#define CONFIG_SYS_ICACHE_OFF ++ ++/* SCIF */ ++#define CONFIG_SCIF_CONSOLE ++#define CONFIG_CONS_SCIF0 ++#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ ++ ++/* [A] Hyper Flash */ ++/* use to RPC(SPI Multi I/O Bus Controller) */ ++ ++ /* underconstruction */ ++ ++#define CONFIG_SYS_NO_FLASH ++#if defined(CONFIG_SYS_NO_FLASH) ++#define CONFIG_SPI ++#define CONFIG_RCAR_GEN3_QSPI ++#define CONFIG_SH_QSPI_BASE 0xEE200000 ++#define CONFIG_CMD_SF ++#define CONFIG_CMD_SPI ++#define CONFIG_SPI_FLASH ++#define CONFIG_SPI_FLASH_SPANSION ++#else ++#undef CONFIG_CMD_SF ++#undef CONFIG_CMD_SPI ++#undef CONFIG_SPI_FLASH ++#undef CONFIG_SPI_FLASH_SPANSION ++#endif ++ ++/* Ethernet RAVB */ ++#define CONFIG_RAVB ++#define CONFIG_RAVB_PHY_ADDR 0x0 ++#define CONFIG_RAVB_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID ++#define CONFIG_NET_MULTI ++#define CONFIG_PHYLIB ++#define CONFIG_PHY_MICREL ++#define CONFIG_BITBANGMII ++#define CONFIG_BITBANGMII_MULTI ++#define CONFIG_SH_ETHER_BITBANG ++ ++/* Board Clock */ ++/* XTAL_CLK : 33.33MHz */ ++#define RCAR_XTAL_CLK 33333333u ++#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK ++/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ ++/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ ++#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) ++#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) ++#define CONFIG_S3D2_CLK_FREQ (266666666u/2) ++#define CONFIG_S3D4_CLK_FREQ (266666666u/4) ++ ++/* Generic Timer Definitions (use in assembler source) */ ++#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ ++ ++/* Generic Interrupt Controller Definitions */ ++#define GICD_BASE (0xF1010000) ++#define GICC_BASE (0xF1020000) ++#define CONFIG_GICV2 ++ ++/* i2c */ ++#define CONFIG_SYS_I2C ++#define CONFIG_SYS_I2C_SH ++#define CONFIG_SYS_I2C_SLAVE 0x60 ++#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 ++#define CONFIG_SYS_I2C_SH_SPEED0 400000 ++#define CONFIG_SH_I2C_DATA_HIGH 4 ++#define CONFIG_SH_I2C_DATA_LOW 5 ++#define CONFIG_SH_I2C_CLOCK 10000000 ++ ++#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 ++ ++/* USB */ ++#undef CONFIG_CMD_USB ++ ++/* Module clock supply/stop status bits */ ++/* MFIS */ ++#define CONFIG_SMSTP2_ENA 0x00002000 ++/* serial(SCIF0) */ ++#define CONFIG_SMSTP3_ENA 0x00000400 ++/* INTC-AP, INTC-EX */ ++#define CONFIG_SMSTP4_ENA 0x00000180 ++ ++/* SDHI */ ++#define CONFIG_MMC ++#define CONFIG_CMD_MMC ++#define CONFIG_GENERIC_MMC ++#define CONFIG_SH_SDHI_FREQ 200000000 ++#define CONFIG_SH_SDHI_MMC ++ ++#define CONFIG_SH_MMCIF ++#define CONFIG_SH_MMCIF_ADDR 0xee140000 ++#define CONFIG_SH_MMCIF_CLK (CONFIG_SH_SDHI_FREQ) ++ ++/* Environment */ ++#define CONFIG_ENV_IS_IN_SPI_FLASH ++ ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_SECT_SIZE (256 * 1024) ++#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) ++ ++/* Environment in eMMC, at the end of 2nd "boot sector" */ ++#if defined(CONFIG_ENV_IS_IN_MMC) ++#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) ++#define CONFIG_SYS_MMC_ENV_DEV 0 ++#define CONFIG_SYS_MMC_ENV_PART 2 ++#define CONFIG_GENERIC_MMC ++ ++#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) ++/* Environment in QSPI */ ++#define CONFIG_ENV_ADDR 0x700000 ++#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) ++ ++#else ++/* Unused Environment */ ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "fdt_high=0xffffffffffffffff\0" \ ++ "initrd_high=0xffffffffffffffff\0" \ ++ "ethact=ravb\0" ++ ++#define CONFIG_BOOTARGS \ ++ "root=/dev/nfs rw " \ ++ "nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" ++ ++#define CONFIG_BOOTCOMMAND \ ++ "tftp 0x48080000 Image; " \ ++ "tftp 0x48000000 Image-r8a7797-eagle.dtb; " \ ++ "booti 0x48080000 - 0x48000000" ++ ++#endif /* __EAGLE_H */ +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch new file mode 100644 index 0000000..773ca26 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch @@ -0,0 +1,813 @@ +From 2e9bb759bda6ce52a446c2b7f7d79d51140c4316 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Fri, 17 Nov 2017 13:01:38 +0300 +Subject: [PATCH] board: renesas: Add V3M Starter Kit board + +V3M Starter Kit is a board based on R-Car V3M SoC (R8A7797) + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +--- + arch/arm/cpu/armv8/Kconfig | 4 + + board/renesas/v3msk/Kconfig | 15 +++ + board/renesas/v3msk/MAINTAINERS | 6 ++ + board/renesas/v3msk/Makefile | 9 ++ + board/renesas/v3msk/cpld.c | 164 +++++++++++++++++++++++++++++++ + board/renesas/v3msk/mdio_bb.h | 156 ++++++++++++++++++++++++++++++ + board/renesas/v3msk/v3msk.c | 209 ++++++++++++++++++++++++++++++++++++++++ + configs/v3msk_defconfig | 9 ++ + include/configs/v3msk.h | 145 ++++++++++++++++++++++++++++ + 9 files changed, 717 insertions(+) + create mode 100644 board/renesas/v3msk/Kconfig + create mode 100644 board/renesas/v3msk/MAINTAINERS + create mode 100644 board/renesas/v3msk/Makefile + create mode 100644 board/renesas/v3msk/cpld.c + create mode 100644 board/renesas/v3msk/mdio_bb.h + create mode 100644 board/renesas/v3msk/v3msk.c + create mode 100644 configs/v3msk_defconfig + create mode 100644 include/configs/v3msk.h + +diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig +index c857214..343b121 100644 +--- a/arch/arm/cpu/armv8/Kconfig ++++ b/arch/arm/cpu/armv8/Kconfig +@@ -19,6 +19,9 @@ config TARGET_ULCB + config TARGET_EAGLE + bool "EAGLE board" + ++config TARGET_V3MSK ++ bool "V3MSK board" ++ + endchoice + + config R8A7796X +@@ -49,5 +52,6 @@ config SYS_SOC + source "board/renesas/salvator-x/Kconfig" + source "board/renesas/ulcb/Kconfig" + source "board/renesas/eagle/Kconfig" ++source "board/renesas/v3msk/Kconfig" + + endif +diff --git a/board/renesas/v3msk/Kconfig b/board/renesas/v3msk/Kconfig +new file mode 100644 +index 0000000..dafbaef +--- /dev/null ++++ b/board/renesas/v3msk/Kconfig +@@ -0,0 +1,15 @@ ++if TARGET_V3MSK ++ ++config SYS_SOC ++ default "rcar_gen3" ++ ++config SYS_BOARD ++ default "v3msk" ++ ++config SYS_VENDOR ++ default "renesas" ++ ++config SYS_CONFIG_NAME ++ default "v3msk" if R8A7797 ++ ++endif +diff --git a/board/renesas/v3msk/MAINTAINERS b/board/renesas/v3msk/MAINTAINERS +new file mode 100644 +index 0000000..c39eb76 +--- /dev/null ++++ b/board/renesas/v3msk/MAINTAINERS +@@ -0,0 +1,6 @@ ++V3MSK BOARD ++M: Cogent Embedded, Inc. <source@cogentembedded.com> ++S: Maintained ++F: board/renesas/v3msk/ ++F: include/configs/r8a7797_v3msk.h ++F: configs/r8a7797_v3msk_defconfig +diff --git a/board/renesas/v3msk/Makefile b/board/renesas/v3msk/Makefile +new file mode 100644 +index 0000000..1f2ea42 +--- /dev/null ++++ b/board/renesas/v3msk/Makefile +@@ -0,0 +1,9 @@ ++# ++# board/renesas/v3msk/Makefile ++# ++# Copyright (C) 2017 Cogent Embedded, Inc. ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++obj-y := v3msk.o ../rcar-gen3-common/common.o cpld.o +diff --git a/board/renesas/v3msk/cpld.c b/board/renesas/v3msk/cpld.c +new file mode 100644 +index 0000000..ffb0637 +--- /dev/null ++++ b/board/renesas/v3msk/cpld.c +@@ -0,0 +1,164 @@ ++/* ++ * V3MSK board CPLD access support ++ * ++ * Copyright (C) 2017 Renesas Electronics Corporation ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <asm/arch/prr_depend.h> ++#include <asm/arch/rcar-mstp.h> ++#include <asm/io.h> ++#include <asm/gpio.h> ++ ++#define ENABLEZ GPIO_GP_1_19 ++#define MDC GPIO_GP_1_21 ++#define MOSI GPIO_GP_1_22 ++#define MISO GPIO_GP_1_23 ++ ++#define ADDR_PRODUCT_L 0x000 /* R */ ++#define ADDR_PRODUCT_H 0x001 /* R */ ++#define ADDR_CPLD_VERSION_D 0x002 /* R */ ++#define ADDR_CPLD_VERSION_Y 0x003 /* R */ ++#define ADDR_MODE_SET_L 0x004 /* R/W */ ++#define ADDR_MODE_SET_H 0x005 /* R/W */ ++#define ADDR_MODE_APPLIED_L 0x006 /* R */ ++#define ADDR_MODE_APPLIED_H 0x007 /* R */ ++#define ADDR_DIPSW 0x008 /* R */ ++#define ADDR_RESET 0x00A /* R/W */ ++#define ADDR_POWER_CFG 0x00B /* R/W */ ++#define ADDR_PERI_CFG1 0x00C /* R/W */ ++#define ADDR_PERI_CFG2 0x00D /* R/W */ ++#define ADDR_LEDS 0x00E /* R/W */ ++#define ADDR_PCB_VERSION 0x300 /* R */ ++#define ADDR_SOC_VERSION 0x301 /* R */ ++#define ADDR_PCB_SN_L 0x302 /* R */ ++#define ADDR_PCB_SN_H 0x303 /* R */ ++ ++/* LSI pin pull-up control */ ++#define PFC_PUEN2 0xe6060408 ++#define PUEN_CANFD1_TX (1 << 29) ++ ++#define MDIO_DELAY 10 /* microseconds */ ++ ++#define mdio_bb_active_mdio() gpio_direction_output(MOSI, 0) ++#define mdio_bb_tristate_mdio() gpio_direction_input(MOSI) ++#define mdio_bb_set_mdio(val) gpio_set_value(MOSI, val) ++#define mdio_bb_get_mdio() gpio_get_value(MISO) ++#define mdio_bb_set_mdc(val) gpio_set_value(MDC, val) ++ ++#include "mdio_bb.h" ++ ++static int cpld_initialized; ++ ++static u16 cpld_read(u16 addr) ++{ ++ /* random flash reads require 2 reads: first read is unreliable */ ++ if (addr >= ADDR_PCB_VERSION) ++ mdio_bb_read(addr >> 5, addr & 0x1f); ++ ++ return mdio_bb_read(addr >> 5, addr & 0x1f); ++} ++ ++static void cpld_write(u16 addr, u16 data) ++{ ++ mdio_bb_write(addr >> 5, addr & 0x1f, data); ++} ++ ++static void cpld_init(void) ++{ ++ if (cpld_initialized) ++ return; ++ ++ cpld_initialized = 1; ++#if 0 ++ /* PULL-UP on MISO line (should be pulled up after POR on V3M) */ ++ writel(readl(PFC_PUEN2) | PUEN_CANFD1_TX, PFC_PUEN2); ++#endif ++ gpio_request(MDC, NULL); ++ gpio_request(ENABLEZ, NULL); ++ gpio_request(MOSI, NULL); ++ gpio_request(MISO, NULL); ++ ++ gpio_direction_output(MDC, 0); ++ gpio_direction_output(ENABLEZ, 0); ++ gpio_direction_output(MOSI, 0); ++ gpio_direction_input(MISO); ++ ++ /* V3MSK Videobox Mini board has CANFD PHY connected ++ * we must shutdown this chip to use bb pins ++ */ ++ gpio_request(GPIO_GP_0_12, NULL); ++ gpio_direction_output(GPIO_GP_0_12, 1); ++} ++ ++static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ u16 addr, val; ++ ++ cpld_init(); ++ ++ if (argc == 2 && strcmp(argv[1], "info") == 0) { ++ printf("Product: 0x%08x\n", ++ (cpld_read(ADDR_PRODUCT_H) << 16) | ++ cpld_read(ADDR_PRODUCT_L)); ++ printf("CPLD version: 0x%08x\n", ++ (cpld_read(ADDR_CPLD_VERSION_Y) << 16) | ++ cpld_read(ADDR_CPLD_VERSION_D)); ++ printf("Mode setting (MD0..26): 0x%08x\n", ++ (cpld_read(ADDR_MODE_APPLIED_H) << 16) | ++ cpld_read(ADDR_MODE_APPLIED_L)); ++ printf("DIPSW (SW4, SW5): 0x%02x, 0x%x\n", ++ (cpld_read(ADDR_DIPSW) & 0xff) ^ 0xff, ++ (cpld_read(ADDR_DIPSW) >> 8) ^ 0xf); ++ printf("Power config: 0x%08x\n", ++ cpld_read(ADDR_POWER_CFG)); ++ printf("Periferals config: 0x%08x\n", ++ (cpld_read(ADDR_PERI_CFG2) << 16) | ++ cpld_read(ADDR_PERI_CFG1)); ++ printf("PCB version: %d.%d\n", ++ cpld_read(ADDR_PCB_VERSION) >> 8, ++ cpld_read(ADDR_PCB_VERSION) & 0xff); ++ printf("SOC version: %d.%d\n", ++ cpld_read(ADDR_SOC_VERSION) >> 8, ++ cpld_read(ADDR_SOC_VERSION) & 0xff); ++ printf("PCB S/N: %d\n", ++ (cpld_read(ADDR_PCB_SN_H) << 16 ) | ++ cpld_read(ADDR_PCB_SN_L)); ++ return 0; ++ } ++ ++ if (argc < 3) ++ return CMD_RET_USAGE; ++ ++ addr = simple_strtoul(argv[2], NULL, 16); ++ if (!(addr >= ADDR_PRODUCT_L && addr <= ADDR_LEDS)) { ++ printf("cpld invalid addr\n"); ++ return CMD_RET_USAGE; ++ } ++ ++ if (argc == 3 && strcmp(argv[1], "read") == 0) { ++ printf("0x%x\n", cpld_read(addr)); ++ } else if (argc == 4 && strcmp(argv[1], "write") == 0) { ++ val = simple_strtoul(argv[3], NULL, 16); ++ cpld_write(addr, val); ++ } ++ ++ return 0; ++} ++ ++U_BOOT_CMD( ++ cpld, 4, 1, do_cpld, ++ "CPLD access", ++ "info\n" ++ "cpld read addr\n" ++ "cpld write addr val\n" ++); ++ ++void reset_cpu(ulong addr) ++{ ++ cpld_init(); ++ cpld_write(ADDR_RESET, 1); ++} +diff --git a/board/renesas/v3msk/mdio_bb.h b/board/renesas/v3msk/mdio_bb.h +new file mode 100644 +index 0000000..0311006 +--- /dev/null ++++ b/board/renesas/v3msk/mdio_bb.h +@@ -0,0 +1,156 @@ ++/* ++ * Bit-banged MDIO interface ++ * ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * based on drivers/net/phy/miiphybb.c ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++ ++static void mdio_bb_delay(void) ++{ ++ udelay(MDIO_DELAY); ++} ++ ++/* Send the preamble, address, and register (common to read and write) */ ++static void mdio_bb_pre(u8 op, u8 addr, u8 reg) ++{ ++ int i; ++ ++ /* 32-bit preamble */ ++ mdio_bb_active_mdio(); ++ mdio_bb_set_mdio(1); ++ for (i = 0; i < 32; i++) { ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++ } ++ /* send the ST (2-bits of '01') */ ++ mdio_bb_set_mdio(0); ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++ mdio_bb_set_mdio(1); ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++ /* send the OP (2-bits of Opcode: '10'-read, '01'-write) */ ++ mdio_bb_set_mdio(op >> 1); ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++ mdio_bb_set_mdio(op & 1); ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++ /* send the PA5 (5-bits of PHY address) */ ++ for (i = 0; i < 5; i++) { ++ mdio_bb_set_mdio(addr & 0x10); /* MSB first */ ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++ addr <<= 1; ++ } ++ /* send the RA5 (5-bits of register address) */ ++ for (i = 0; i < 5; i++) { ++ mdio_bb_set_mdio(reg & 0x10); /* MSB first */ ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++ reg <<= 1; ++ } ++} ++ ++static int mdio_bb_read(u8 addr, u8 reg) ++{ ++ int i; ++ u16 data = 0; ++ ++ mdio_bb_pre(2, addr, reg); ++ /* tri-state MDIO */ ++ mdio_bb_tristate_mdio(); ++ /* read TA (2-bits of turn-around, last bit must be '0') */ ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++ /* check the turnaround bit: the PHY should drive line to zero */ ++ if (mdio_bb_get_mdio() != 0) { ++ printf ("PHY didn't drive TA low\n"); ++ for (i = 0; i < 32; i++) { ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++ } ++ /* There is no PHY, set value to 0xFFFF */ ++ return 0xFFFF; ++ } ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ /* read 16-bits of data */ ++ for (i = 0; i < 16; i++) { ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++ data <<= 1; ++ data |= mdio_bb_get_mdio(); ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ } ++ ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++#ifdef DEBUG ++ printf("cpld_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, data); ++#endif ++ return data; ++} ++ ++static void mdio_bb_write(u8 addr, u8 reg, u16 val) ++{ ++ int i; ++ ++ mdio_bb_pre(1, addr, reg); ++ /* send the TA (2-bits of turn-around '10') */ ++ mdio_bb_set_mdio(1); ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++ mdio_bb_set_mdio(0); ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++ /* write 16-bits of data */ ++ for (i = 0; i < 16; i++) { ++ mdio_bb_set_mdio(val & 0x8000); /* MSB first */ ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++ val <<= 1; ++ } ++ /* tri-state MDIO */ ++ mdio_bb_tristate_mdio(); ++ mdio_bb_set_mdc(0); ++ mdio_bb_delay(); ++ mdio_bb_set_mdc(1); ++ mdio_bb_delay(); ++} +diff --git a/board/renesas/v3msk/v3msk.c b/board/renesas/v3msk/v3msk.c +new file mode 100644 +index 0000000..b0de041 +--- /dev/null ++++ b/board/renesas/v3msk/v3msk.c +@@ -0,0 +1,209 @@ ++/* ++ * board/renesas/v3msk/v3msk.c ++ * This is V3MSK board support. ++ * ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <malloc.h> ++#include <netdev.h> ++#include <dm.h> ++#include <dm/platform_data/serial_sh.h> ++#include <asm/processor.h> ++#include <asm/mach-types.h> ++#include <asm/io.h> ++#include <asm/errno.h> ++#include <asm/arch/sys_proto.h> ++#include <asm/gpio.h> ++#include <asm/arch/prr_depend.h> ++#include <asm/arch/gpio.h> ++#include <asm/arch/rcar_gen3.h> ++#include <asm/arch/rcar-mstp.h> ++#include <asm/arch/sh_sdhi.h> ++#include <i2c.h> ++#include <mmc.h> ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define SCIF0_MSTP207 (1 << 7) ++#define ETHERAVB_MSTP812 (1 << 12) ++#define RPC_MSTP917 (1 << 17) ++#define SD0_MSTP314 (1 << 14) ++ ++#define SD0CKCR 0xE6150074 ++ ++#define CLK2MHZ(clk) (clk / 1000 / 1000) ++void s_init(void) ++{ ++ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; ++ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; ++ u32 stc; ++ ++ /* Watchdog init */ ++ writel(0xA5A5A500, &rwdt->rwtcsra); ++ writel(0xA5A5A500, &swdt->swtcsra); ++ ++ /* CPU frequency setting. Set to 0.8GHz */ ++ stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; ++ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); ++} ++ ++int board_early_init_f(void) ++{ ++ int freq; ++ ++ rcar_prr_init(); ++ ++ writel(0xa5a5ffff, 0xe6150900); ++ writel(0x5a5a0000, 0xe6150904); ++ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, 0x02000000); ++ /* SCIF0 */ ++ mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIF0_MSTP207); ++ /* SDHI0/MMC */ ++ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314); ++ /* EHTERAVB */ ++ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812); ++ /* QSPI/RPC */ ++ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, RPC_MSTP917); ++ ++ freq = rcar_get_sdhi_config_clk(); ++ writel(freq, SD0CKCR); ++ ++ return 0; ++} ++ ++int board_init(void) ++{ ++ /* adress of boot parameters */ ++ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; ++ ++ /* Init PFC controller */ ++ pinmux_init(); ++#ifdef CONFIG_RAVB ++ /* GPSR1 */ ++ gpio_request(GPIO_GFN_AVB0_AVTP_CAPTURE, NULL); ++ gpio_request(GPIO_FN_AVB0_AVTP_MATCH, NULL); ++ gpio_request(GPIO_FN_AVB0_LINK, NULL); ++ gpio_request(GPIO_FN_AVB0_PHY_INT, NULL); ++ /* gpio_request(GPIO_FN_AVB0_MAGIC, NULL); */ ++ gpio_request(GPIO_FN_AVB0_MDC, NULL); ++ gpio_request(GPIO_FN_AVB0_MDIO, NULL); ++ gpio_request(GPIO_FN_AVB0_TXCREFCLK, NULL); ++ gpio_request(GPIO_FN_AVB0_TD3, NULL); ++ gpio_request(GPIO_FN_AVB0_TD2, NULL); ++ gpio_request(GPIO_FN_AVB0_TD1, NULL); ++ gpio_request(GPIO_FN_AVB0_TD0, NULL); ++ gpio_request(GPIO_FN_AVB0_TXC, NULL); ++ gpio_request(GPIO_FN_AVB0_TX_CTL, NULL); ++ gpio_request(GPIO_FN_AVB0_RD3, NULL); ++ gpio_request(GPIO_FN_AVB0_RD2, NULL); ++ gpio_request(GPIO_FN_AVB0_RD1, NULL); ++ gpio_request(GPIO_FN_AVB0_RD0, NULL); ++ gpio_request(GPIO_FN_AVB0_RXC, NULL); ++ gpio_request(GPIO_FN_AVB0_RX_CTL, NULL); ++ /* IPSR7 */ ++ gpio_request(GPIO_IFN_AVB0_AVTP_CAPTURE, NULL); ++ /* IPSR3 */ ++ gpio_request(GPIO_FN_AVB0_AVTP_PPS, NULL); ++#endif ++ /* QSPI/RPC */ ++ gpio_request(GPIO_FN_QSPI0_SPCLK, NULL); ++ gpio_request(GPIO_FN_QSPI0_MOSI_IO0, NULL); ++ gpio_request(GPIO_FN_QSPI0_MISO_IO1, NULL); ++ gpio_request(GPIO_FN_QSPI0_IO2, NULL); ++ gpio_request(GPIO_FN_QSPI0_IO3, NULL); ++ gpio_request(GPIO_FN_QSPI0_SSL, NULL); ++ gpio_request(GPIO_FN_QSPI1_SPCLK, NULL); ++ gpio_request(GPIO_FN_QSPI1_MOSI_IO0, NULL); ++ gpio_request(GPIO_FN_QSPI1_MISO_IO1, NULL); ++ gpio_request(GPIO_FN_QSPI1_IO2, NULL); ++ gpio_request(GPIO_FN_QSPI1_IO3, NULL); ++ gpio_request(GPIO_FN_QSPI1_SSL, NULL); ++ gpio_request(GPIO_FN_RPC_RESET_N, NULL); ++ gpio_request(GPIO_FN_RPC_WP_N, NULL); ++ gpio_request(GPIO_FN_RPC_INT_N, NULL); ++ ++ return 0; ++} ++ ++#define MAHR 0xE68005C0 ++#define MALR 0xE68005C8 ++int board_eth_init(bd_t *bis) ++{ ++ int ret = -ENODEV; ++ u32 val; ++ unsigned char enetaddr[6]; ++ ++ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) ++ return ret; ++ ++ /* Set Mac address */ ++ val = enetaddr[0] << 24 | enetaddr[1] << 16 | ++ enetaddr[2] << 8 | enetaddr[3]; ++ writel(val, MAHR); ++ ++ val = enetaddr[4] << 8 | enetaddr[5]; ++ writel(val, MALR); ++#ifdef CONFIG_RAVB ++ ret = ravb_initialize(bis); ++#endif ++ return ret; ++} ++ ++/* V3MSK has KSZ9031RNX */ ++int board_phy_config(struct phy_device *phydev) ++{ ++ return 0; ++} ++ ++int board_mmc_init(bd_t *bis) ++{ ++ int ret = -ENODEV; ++#ifdef CONFIG_SH_SDHI ++ /* SDHI2/eMMC */ ++ gpio_request(GPIO_FN_MMC_D0, NULL); ++ gpio_request(GPIO_FN_MMC_D1, NULL); ++ gpio_request(GPIO_FN_MMC_D2, NULL); ++ gpio_request(GPIO_FN_MMC_D3, NULL); ++ gpio_request(GPIO_FN_MMC_D4, NULL); ++ gpio_request(GPIO_FN_MMC_D5, NULL); ++ gpio_request(GPIO_FN_MMC_D6, NULL); ++ gpio_request(GPIO_FN_MMC_D7, NULL); ++ gpio_request(GPIO_FN_MMC_CLK, NULL); ++ gpio_request(GPIO_FN_MMC_CMD, NULL); ++ gpio_request(GPIO_FN_MMC_CD, NULL); ++ gpio_request(GPIO_FN_MMC_WP, NULL); ++ ++ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 0, ++ SH_SDHI_QUIRK_64BIT_BUF); ++#endif ++ return ret; ++} ++ ++int dram_init(void) ++{ ++ gd->ram_size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} ++ ++void dram_init_banksize(void) ++{ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++} ++ ++const struct rcar_sysinfo sysinfo = { ++ CONFIG_RCAR_BOARD_STRING ++}; ++ ++#if defined(CONFIG_DISPLAY_BOARDINFO) ++int checkboard(void) ++{ ++ printf("Board: %s\n", sysinfo.board_string); ++ return 0; ++} ++#endif +diff --git a/configs/v3msk_defconfig b/configs/v3msk_defconfig +new file mode 100644 +index 0000000..d32840c +--- /dev/null ++++ b/configs/v3msk_defconfig +@@ -0,0 +1,9 @@ ++CONFIG_ARM=y ++CONFIG_RCAR_GEN3=y ++CONFIG_DM_SERIAL=y ++CONFIG_TARGET_V3MSK=y ++CONFIG_R8A7797=y ++CONFIG_SPL=y ++CONFIG_SH_SDHI=y ++CONFIG_SPI_FLASH=y ++CONFIG_SPI_FLASH_SPANSION=y +diff --git a/include/configs/v3msk.h b/include/configs/v3msk.h +new file mode 100644 +index 0000000..8998da4 +--- /dev/null ++++ b/include/configs/v3msk.h +@@ -0,0 +1,145 @@ ++/* ++ * include/configs/v3msk.h ++ * This file is V3MSK board configuration. ++ * CPU r8a7797. ++ * ++ * Copyright (C) 2017 Cogent Embedded, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __V3MSK_H ++#define __V3MSK_H ++ ++#undef DEBUG ++#define CONFIG_RCAR_BOARD_STRING "V3MSK" ++#define CONFIG_RCAR_TARGET_STRING "r8a7797" ++ ++#include "rcar-gen3-common.h" ++ ++/* Cache Definitions */ ++//#define CONFIG_SYS_DCACHE_OFF ++//#define CONFIG_SYS_ICACHE_OFF ++ ++/* SCIF */ ++#define CONFIG_SCIF_CONSOLE ++#define CONFIG_CONS_SCIF0 ++#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ ++ ++/* [A] Hyper Flash */ ++/* use to RPC(SPI Multi I/O Bus Controller) */ ++ ++ /* underconstruction */ ++ ++#define CONFIG_SYS_NO_FLASH ++#if defined(CONFIG_SYS_NO_FLASH) ++#define CONFIG_SPI ++#define CONFIG_RCAR_GEN3_QSPI ++#define CONFIG_SH_QSPI_BASE 0xEE200000 ++#define CONFIG_CMD_SF ++#define CONFIG_CMD_SPI ++#define CONFIG_SPI_FLASH ++#define CONFIG_SPI_FLASH_SPANSION ++#else ++#undef CONFIG_CMD_SF ++#undef CONFIG_CMD_SPI ++#undef CONFIG_SPI_FLASH ++#undef CONFIG_SPI_FLASH_SPANSION ++#endif ++ ++/* Ethernet RAVB */ ++#define CONFIG_RAVB ++#define CONFIG_RAVB_PHY_ADDR 0x0 ++#define CONFIG_RAVB_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID ++#define CONFIG_NET_MULTI ++#define CONFIG_PHYLIB ++#define CONFIG_PHY_MICREL ++#define CONFIG_BITBANGMII ++#define CONFIG_BITBANGMII_MULTI ++#define CONFIG_SH_ETHER_BITBANG ++ ++/* Board Clock */ ++/* XTAL_CLK : 33.33MHz */ ++#define RCAR_XTAL_CLK 33333333u ++#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK ++/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ ++/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ ++#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) ++#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) ++#define CONFIG_S3D2_CLK_FREQ (266666666u/2) ++#define CONFIG_S3D4_CLK_FREQ (266666666u/4) ++ ++/* Generic Timer Definitions (use in assembler source) */ ++#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ ++ ++/* Generic Interrupt Controller Definitions */ ++#define GICD_BASE (0xF1010000) ++#define GICC_BASE (0xF1020000) ++#define CONFIG_GICV2 ++ ++/* i2c */ ++#define CONFIG_SYS_I2C ++#define CONFIG_SYS_I2C_SH ++#define CONFIG_SYS_I2C_SLAVE 0x60 ++#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 ++#define CONFIG_SYS_I2C_SH_SPEED0 400000 ++#define CONFIG_SH_I2C_DATA_HIGH 4 ++#define CONFIG_SH_I2C_DATA_LOW 5 ++#define CONFIG_SH_I2C_CLOCK 10000000 ++ ++#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 ++ ++/* USB */ ++#undef CONFIG_CMD_USB ++ ++/* SDHI */ ++#define CONFIG_MMC ++#define CONFIG_CMD_MMC ++#define CONFIG_GENERIC_MMC ++#define CONFIG_SH_SDHI_FREQ 200000000 ++#define CONFIG_SH_SDHI_MMC ++ ++/* ENV setting */ ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_SECT_SIZE (256 * 1024) ++#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) ++#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) ++ ++#define CONFIG_ENV_IS_IN_MMC ++//#define CONFIG_ENV_IS_IN_SPI_FLASH ++ ++#if defined(CONFIG_ENV_IS_IN_MMC) ++/* Environment in eMMC, at the end of 2nd "boot sector" */ ++#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) ++#define CONFIG_SYS_MMC_ENV_DEV 0 ++#define CONFIG_SYS_MMC_ENV_PART 2 ++#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) ++/* Environment in QSPI */ ++#define CONFIG_ENV_ADDR 0x700000 ++#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++/* Module clock supply/stop status bits */ ++/* MFIS */ ++#define CONFIG_SMSTP2_ENA 0x00002000 ++/* serial(SCIF0) */ ++#define CONFIG_SMSTP3_ENA 0x00000400 ++/* INTC-AP, INTC-EX */ ++#define CONFIG_SMSTP4_ENA 0x00000180 ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "fdt_high=0xffffffffffffffff\0" \ ++ "initrd_high=0xffffffffffffffff\0" \ ++ "ethact=ravb\0" \ ++ "ethaddr=2E:11:22:33:44:55\0" ++ ++#define CONFIG_BOOTARGS \ ++ "root=/dev/nfs rw ip=dhcp" ++ ++#define CONFIG_BOOTCOMMAND \ ++ "bootp 0x48080000 Image; tftp 0x48000000 Image-r8a7797-v3msk.dtb; " \ ++ "booti 0x48080000 - 0x48000000" ++ ++#endif /* __V3MSK_H */ +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0021-ARM-rcar_gen3-Add-RPC-flash-definitions.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0021-ARM-rcar_gen3-Add-RPC-flash-definitions.patch new file mode 100644 index 0000000..b47c724 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0021-ARM-rcar_gen3-Add-RPC-flash-definitions.patch @@ -0,0 +1,224 @@ +From 2b31e91d7ea86934badebcebb2309b09b79725ca Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Mon, 4 Apr 2016 18:39:26 +0300 +Subject: [PATCH] ARM: rcar_gen3: Add RPC flash definitions + +This adds common RPC flash definitions to RCAR Gen3 platform. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + arch/arm/include/asm/arch-rcar_gen3/rcar-base.h | 6 + + arch/arm/include/asm/arch-rcar_gen3/rpc-flash.h | 184 ++++++++++++++++++++++++ + 2 files changed, 190 insertions(+) + create mode 100644 arch/arm/include/asm/arch-rcar_gen3/rpc-flash.h + +diff --git a/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h b/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h +index 59d34b8..538cdc2 100644 +--- a/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h ++++ b/arch/arm/include/asm/arch-rcar_gen3/rcar-base.h +@@ -78,6 +78,12 @@ + /* SH-I2C */ + #define CONFIG_SYS_I2C_SH_BASE0 0xE60B0000 + ++/* RPC */ ++#define CONFIG_SYS_RPC_BASE 0xEE200000 ++ ++#define CONFIG_SYS_RPC_FLASH_BASE 0x08000000 ++#define CONFIG_SYS_RPC_FLASH_SIZE 0x04000000 ++ + /* PFC */ + #define PFC_PUEN6 0xE6060418 + #define PUEN_USB1_OVC (1 << 2) +diff --git a/arch/arm/include/asm/arch-rcar_gen3/rpc-flash.h b/arch/arm/include/asm/arch-rcar_gen3/rpc-flash.h +new file mode 100644 +index 0000000..403aaee +--- /dev/null ++++ b/arch/arm/include/asm/arch-rcar_gen3/rpc-flash.h +@@ -0,0 +1,184 @@ ++/* ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * Copyright (C) 2016 Cogent Embedded, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0 ++ */ ++ ++#ifndef __RPC_FLASH_H__ ++#define __RPC_FLASH_H__ ++ ++#include <common.h> ++#include <flash.h> ++#include <asm/io.h> ++#include <asm/arch/rcar_gen3.h> ++ ++#define RPC_CMNCR 0x0000 /* R/W */ ++#define RPC_CMNCR_MD (0x1 << 31) ++#define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16) ++#define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18) ++#define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20) ++#define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22) ++#define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \ ++ RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3)) ++#define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8) ++#define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12) ++#define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14) ++#define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \ ++ RPC_CMNCR_IO3FV(3)) ++#define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0) ++ ++#define RPC_SSLDR 0x0004 /* R/W */ ++#define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16) ++#define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8) ++#define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0) ++ ++#define RPC_DRCR 0x000C /* R/W */ ++#define RPC_DRCR_SSLN (0x1 << 24) ++#define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16) ++#define RPC_DRCR_RCF (0x1 << 9) ++#define RPC_DRCR_RBE (0x1 << 8) ++#define RPC_DRCR_SSLE (0x1 << 0) ++ ++#define RPC_DRCMR 0x0010 /* R/W */ ++#define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16) ++#define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0) ++ ++#define RPC_DREAR 0x0014 /* R/W */ ++#define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16) ++#define RPC_DREAR_EAC(v) (((v) & 0x7) << 0) ++ ++#define RPC_DROPR 0x0018 /* R/W */ ++#define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24) ++#define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16) ++#define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8) ++#define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0) ++ ++#define RPC_DRENR 0x001C /* R/W */ ++#define RPC_DRENR_CDB(o) (((o) & 0x3) << 30) ++#define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28) ++#define RPC_DRENR_ADB(o) (((o) & 0x3) << 24) ++#define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20) ++#define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16) ++#define RPC_DRENR_DME (0x1 << 15) ++#define RPC_DRENR_CDE (0x1 << 14) ++#define RPC_DRENR_OCDE (0x1 << 12) ++#define RPC_DRENR_ADE(v) (((v) & 0xF) << 8) ++#define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4) ++ ++#define RPC_SMCR 0x0020 /* R/W */ ++#define RPC_SMCR_SSLKP (0x1 << 8) ++#define RPC_SMCR_SPIRE (0x1 << 2) ++#define RPC_SMCR_SPIWE (0x1 << 1) ++#define RPC_SMCR_SPIE (0x1 << 0) ++ ++#define RPC_SMCMR 0x0024 /* R/W */ ++#define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16) ++#define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0) ++ ++#define RPC_SMADR 0x0028 /* R/W */ ++#define RPC_SMOPR 0x002C /* R/W */ ++#define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0) ++#define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8) ++#define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16) ++#define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24) ++ ++#define RPC_SMENR 0x0030 /* R/W */ ++#define RPC_SMENR_CDB(o) (((o) & 0x3) << 30) ++#define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28) ++#define RPC_SMENR_ADB(o) (((o) & 0x3) << 24) ++#define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20) ++#define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16) ++#define RPC_SMENR_DME (0x1 << 15) ++#define RPC_SMENR_CDE (0x1 << 14) ++#define RPC_SMENR_OCDE (0x1 << 12) ++#define RPC_SMENR_ADE(v) (((v) & 0xF) << 8) ++#define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4) ++#define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0) ++ ++#define RPC_SMRDR0 0x0038 /* R */ ++#define RPC_SMRDR1 0x003C /* R */ ++#define RPC_SMWDR0 0x0040 /* R/W */ ++#define RPC_SMWDR1 0x0044 /* R/W */ ++#define RPC_CMNSR 0x0048 /* R */ ++#define RPC_CMNSR_SSLF (0x1 << 1) ++#define RPC_CMNSR_TEND (0x1 << 0) ++ ++#define RPC_DRDMCR 0x0058 /* R/W */ ++#define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0) ++ ++#define RPC_DRDRENR 0x005C /* R/W */ ++#define RPC_DRDRENR_HYPE (0x5 << 12) ++#define RPC_DRDRENR_ADDRE (0x1 << 0x8) ++#define RPC_DRDRENR_OPDRE (0x1 << 0x4) ++#define RPC_DRDRENR_DRDRE (0x1 << 0x0) ++ ++#define RPC_SMDMCR 0x0060 /* R/W */ ++#define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0) ++ ++#define RPC_SMDRENR 0x0064 /* R/W */ ++#define RPC_SMDRENR_HYPE (0x5 << 12) ++#define RPC_SMDRENR_ADDRE (0x1 << 0x8) ++#define RPC_SMDRENR_OPDRE (0x1 << 0x4) ++#define RPC_SMDRENR_SPIDRE (0x1 << 0x0) ++ ++#define RPC_PHYCNT 0x007C /* R/W */ ++#define RPC_PHYCNT_CAL (0x1 << 31) ++#define PRC_PHYCNT_OCTA_AA (0x1 << 22) ++#define PRC_PHYCNT_OCTA_SA (0x2 << 22) ++#define PRC_PHYCNT_EXDS (0x1 << 21) ++#define RPC_PHYCNT_OCT (0x1 << 20) ++#define RPC_PHYCNT_WBUF2 (0x1 << 4) ++#define RPC_PHYCNT_WBUF (0x1 << 2) ++#define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0) ++ ++#define RPC_PHYINT 0x0088 /* R/W */ ++#define RPC_PHYINT_RSTEN (0x1 << 18) ++#define RPC_PHYINT_WPEN (0x1 << 17) ++#define RPC_PHYINT_INTEN (0x1 << 16) ++#define RPC_PHYINT_RST (0x1 << 2) ++#define RPC_PHYINT_WP (0x1 << 1) ++#define RPC_PHYINT_INT (0x1 << 0) ++ ++#define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */ ++#define RPC_WBUF_SIZE 0x100 ++ ++#ifndef CONFIG_SYS_NO_FLASH ++static inline phys_addr_t rpc_addr(flash_info_t *info, u32 offset) ++{ ++ return offset + CONFIG_SYS_RPC_BASE; ++} ++ ++static inline u32 rpc_readl(flash_info_t *info, u32 offset) ++{ ++ u32 val; ++ ++ val = readl(rpc_addr(info, offset)); ++ return val; ++} ++ ++static inline void rpc_writel(flash_info_t *info, u32 offset, u32 val) ++{ ++ writel(val, rpc_addr(info, offset)); ++} ++ ++static inline void rpc_setl(flash_info_t *info, u32 offset, u32 msk, u32 set) ++{ ++ phys_addr_t addr; ++ u32 val; ++ ++ addr = rpc_addr(info, offset); ++ val = readl(addr); ++ val &= msk; ++ val |= set; ++ writel(val, addr); ++} ++ ++static void rpc_wait_tend(flash_info_t *info) ++{ ++ while (!(rpc_readl(info, RPC_CMNSR) & RPC_CMNSR_TEND)) ++ barrier(); ++} ++#endif /* CONFIG_SYS_NO_FLASH */ ++ ++#endif /* __RPC_FLASH_H__ */ +-- +1.9.3 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0022-mtd-Add-RPC-HyperFlash-support.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0022-mtd-Add-RPC-HyperFlash-support.patch new file mode 100644 index 0000000..8d34bce --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0022-mtd-Add-RPC-HyperFlash-support.patch @@ -0,0 +1,727 @@ +From 00ea5714ecc7ca61919cb3942d0edf20e8190160 Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Mon, 4 Apr 2016 18:40:39 +0300 +Subject: [PATCH] mtd: Add RPC HyperFlash support + +This adds RCAR Gen3 RPC HyperFlash driver. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + drivers/mtd/Makefile | 1 + + drivers/mtd/rpc_hyperflash.c | 695 +++++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 696 insertions(+) + create mode 100644 drivers/mtd/rpc_hyperflash.c + +diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile +index 5467a95..8e794a2 100644 +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -18,3 +18,4 @@ obj-$(CONFIG_FTSMC020) += ftsmc020.o + obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o + obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o + obj-$(CONFIG_ST_SMI) += st_smi.o ++obj-$(CONFIG_RPC_HYPERFLASH) += rpc_hyperflash.o +diff --git a/drivers/mtd/rpc_hyperflash.c b/drivers/mtd/rpc_hyperflash.c +new file mode 100644 +index 0000000..fc67ecd +--- /dev/null ++++ b/drivers/mtd/rpc_hyperflash.c +@@ -0,0 +1,695 @@ ++/* ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * Copyright (C) 2016 Cogent Embedded, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0 ++ */ ++ ++#include <asm/arch/rpc-flash.h> ++ ++#define RPC_HF_CMD_CA47 (0x1 << 7) /* Read */ ++#define RPC_HF_CMD_CA46 (0x1 << 6) /* Register space */ ++#define RPC_HF_CMD_CA45 (0x1 << 5) /* Liner burst */ ++ ++#define RPC_HF_CMD_READ_REG (RPC_HF_CMD_CA47 | RPC_HF_CMD_CA46) ++#define RPC_HF_CMD_READ_MEM RPC_HF_CMD_CA47 ++#define RPC_HF_CMD_WRITE_REG RPC_HF_CMD_CA46 ++#define RPC_HF_CMD_WRITE_MEM 0x0 ++ ++#define RPC_HF_ERASE_SIZE 0x40000 ++ ++#define RPC_CFI_STATUS_DRB (0x1 << 7) ++#define RPC_CFI_STATUS_ESSB (0x1 << 6) ++#define RPC_CFI_STATUS_ESB (0x1 << 5) ++#define RPC_CFI_STATUS_PSB (0x1 << 4) ++#define RPC_CFI_STATUS_WBASB (0x1 << 3) ++#define RPC_CFI_STATUS_PSSB (0x1 << 2) ++#define RPC_CFI_STATUS_SLSB (0x1 << 1) ++#define RPC_CFI_STATUS_ESTAT (0x1 << 0) ++ ++#define RPC_CFI_UNLOCK1 (0x555 << 1) ++#define RPC_CFI_UNLOCK2 (0x2AA << 1) ++ ++#define RPC_CFI_CMD_UNLOCK_START 0xAA ++#define RPC_CFI_CMD_UNLOCK_ACK 0x55 ++#define RPC_CFI_CMD_RESET 0xF0 ++#define RPC_CFI_CMD_READ_STATUS 0x70 ++#define RPC_CFI_CMD_READ_ID 0x90 ++#define RPC_CFI_CMD_WRITE 0xA0 ++#define RPC_CFI_CMD_ERASE_START 0x80 ++#define RPC_CFI_CMD_ERASE_SECTOR 0x30 ++ ++#define RPC_CFI_ID_MASK 0x000F ++#define RPC_CFI_ID_MAN_SPANSION 0x0001 ++#define RPC_CFI_ID_TYPE_HYPERFLASH 0x000E ++ ++enum rpc_hf_size { ++ RPC_HF_SIZE_16BIT = RPC_SMENR_SPIDE(0x8), ++ RPC_HF_SIZE_32BIT = RPC_SMENR_SPIDE(0xC), ++ RPC_HF_SIZE_64BIT = RPC_SMENR_SPIDE(0xF), ++}; ++ ++static inline u32 rpc_hf_flash_map(flash_info_t *info, int sector) ++{ ++ return info->start[sector] - CONFIG_SYS_RPC_FLASH_BASE; ++} ++ ++static inline int rpc_hf_flash_sector(flash_info_t *info, u32 addr) ++{ ++ return (addr - info->start[0]) / RPC_HF_ERASE_SIZE; ++} ++ ++static inline int rpc_hf_flash_sector_size(flash_info_t *info, int sector) ++{ ++ return RPC_HF_ERASE_SIZE; ++} ++ ++static void rpc_hf_mode_man(flash_info_t *info) ++{ ++ rpc_wait_tend(info); ++ ++ /* ++ * RPC_PHYCNT = 0x80000263 ++ * bit31 CAL = 1 : PHY calibration ++ * bit1-0 PHYMEM[1:0] = 11 : HyperFlash ++ */ ++ rpc_setl(info, RPC_PHYCNT, ++ ~(RPC_PHYCNT_WBUF | RPC_PHYCNT_WBUF2 | ++ RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3)), ++ RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3)); ++ ++ /* ++ * RPC_CMNCR = 0x81FFF301 ++ * bit31 MD = 1 : Manual mode ++ * bit1-0 BSZ[1:0] = 01 : QSPI Flash x 2 or HyperFlash ++ */ ++ rpc_setl(info, RPC_CMNCR, ++ ~(RPC_CMNCR_MD | RPC_CMNCR_BSZ(3)), ++ RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | ++ RPC_CMNCR_MD | RPC_CMNCR_BSZ(1)); ++} ++ ++static void rpc_hf_mode_ext(flash_info_t *info) ++{ ++ rpc_wait_tend(info); ++ ++ /* ++ * RPC_PHYCNT = 0x80000263 ++ * bit31 CAL = 1 : PHY calibration ++ * bit1-0 PHYMEM[1:0] = 11 : HyperFlash ++ */ ++ rpc_setl(info, RPC_PHYCNT, ++ ~(RPC_PHYCNT_WBUF | RPC_PHYCNT_WBUF2 | ++ RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3)), ++ RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3)); ++ ++ /* ++ * RPC_CMNCR = 0x81FFF301 ++ * bit31 MD = 1 : Manual mode ++ * bit1-0 BSZ[1:0] = 01 : QSPI Flash x 2 or HyperFlash ++ */ ++ rpc_setl(info, RPC_CMNCR, ++ ~(RPC_CMNCR_MD | RPC_CMNCR_BSZ(3)), ++ RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | ++ RPC_CMNCR_BSZ(1)); ++ ++ /* ++ * RPC_DRCR = 0x001F0100 ++ * bit21-16 RBURST[4:0] = 11111 : Read burst 32 64-bit data units ++ * bit9 RCF = 1 : Clear cache ++ * bit8 RBE = 1 : Read burst enable ++ */ ++ rpc_writel(info, RPC_DRCR, ++ RPC_DRCR_RBURST(0x1F) | RPC_DRCR_RCF | RPC_DRCR_RBE); ++ ++ rpc_writel(info, RPC_DRCMR, RPC_DRCMR_CMD(0xA0)); ++ rpc_writel(info, RPC_DRENR, ++ RPC_DRENR_CDB(2) | RPC_DRENR_OCDB(2) | ++ RPC_DRENR_ADB(2) | RPC_DRENR_SPIDB(2) | ++ RPC_DRENR_CDE | RPC_DRENR_OCDE | RPC_DRENR_ADE(4)); ++ rpc_writel(info, RPC_DRDMCR, RPC_DRDMCR_DMCYC(0xE)); ++ rpc_writel(info, RPC_DRDRENR, ++ RPC_DRDRENR_HYPE | RPC_DRDRENR_ADDRE | RPC_DRDRENR_DRDRE); ++ ++ /* Dummy read */ ++ rpc_readl(info, RPC_DRCR); ++} ++ ++static void rpc_hf_xfer(flash_info_t *info, u32 addr, u16 *data, ++ enum rpc_hf_size size, u8 cmd) ++{ ++ u32 val; ++ ++ rpc_hf_mode_man(info); ++ ++ /* ++ * bit23-21 CMD[7:5] : CA47-45 ++ * CA47 = 0/1 : Write/Read ++ * CA46 = 0/1 : Memory Space/Register Space ++ * CA45 = 0/1 : Wrapped Burst/Linear Burst ++ */ ++ rpc_writel(info, RPC_SMCMR, RPC_SMCMR_CMD(cmd)); ++ ++ rpc_writel(info, RPC_SMADR, addr >> 1); ++ ++ rpc_writel(info, RPC_SMOPR, 0x0); ++ ++ /* ++ * RPC_SMDRENR = 0x00005101 ++ * bit14-12 HYPE = 101: Hyperflash mode ++ * bit8 ADDRE = 1 : Address DDR transfer ++ * bit0 SPIDRE = 1 : DATA DDR transfer ++ */ ++ rpc_writel(info, RPC_SMDRENR, ++ RPC_SMDRENR_HYPE | RPC_SMDRENR_ADDRE | RPC_SMDRENR_SPIDRE); ++ ++ val = RPC_SMENR_CDB(2) | RPC_SMENR_OCDB(2) | ++ RPC_SMENR_ADB(2) | RPC_SMENR_SPIDB(2) | ++ RPC_SMENR_CDE | RPC_SMENR_OCDE | RPC_SMENR_ADE(4) | size; ++ ++ if (cmd & RPC_HF_CMD_CA47) ++ goto read_transfer; ++ ++ /* ++ * RPC_SMENR = 0xA222540x ++ * bit31-30 CDB[1:0] = 10 : 4bit width command ++ * bit25-24 ADB[1:0] = 10 : 4bit width address ++ * bit17-16 SPIDB[1:0] = 10 : 4bit width transfer data ++ * bit15 DME = 0 : dummy cycle disable ++ * bit14 CDE = 1 : Command enable ++ * bit12 OCDE = 1 : Option Command enable ++ * bit11-8 ADE[3:0] = 0100 : ADR[23:0] output ++ * bit7-4 OPDE[3:0] = 0000 : Option data disable ++ * bit3-0 SPIDE[3:0] = xxxx : Transfer size ++ */ ++ rpc_writel(info, RPC_SMENR, val); ++ ++ switch (size) { ++ case RPC_HF_SIZE_64BIT: ++ val = cmd & RPC_HF_CMD_CA46 ? ++ cpu_to_be16(data[0]) | cpu_to_be16(data[1]) << 16 : ++ data[0] | data[1] << 16; ++ rpc_writel(info, RPC_SMWDR1, val); ++ val = cmd & RPC_HF_CMD_CA46 ? ++ cpu_to_be16(data[2]) | cpu_to_be16(data[3]) << 16 : ++ data[2] | data[3] << 16; ++ break; ++ case RPC_HF_SIZE_32BIT: ++ val = cmd & RPC_HF_CMD_CA46 ? ++ cpu_to_be16(data[0]) | cpu_to_be16(data[1]) << 16 : ++ data[0] | data[1] << 16; ++ break; ++ default: ++ val = cmd & RPC_HF_CMD_CA46 ? ++ cpu_to_be16(data[0]) << 16 : ++ data[0] << 16; ++ break; ++ } ++ ++ rpc_writel(info, RPC_SMWDR0, val); ++ /* ++ * RPC_SMCR = 0x00000003 ++ * bit1 SPIWE = 1 : Data write enable ++ * bit0 SPIE = 1 : SPI transfer start ++ */ ++ rpc_writel(info, RPC_SMCR, RPC_SMCR_SPIWE | RPC_SMCR_SPIE); ++ return; ++ ++read_transfer: ++ rpc_writel(info, RPC_SMDMCR, RPC_SMDMCR_DMCYC(0xE)); ++ val |= RPC_SMENR_DME; ++ ++ /* ++ * RPC_SMENR = 0xA222D40x ++ * bit31-30 CDB[1:0] = 10 : 4bit width command ++ * bit25-24 ADB[1:0] = 10 : 4bit width address ++ * bit17-16 SPIDB[1:0] = 10 : 4bit width transfer data ++ * bit15 DME = 1 : dummy cycle disable ++ * bit14 CDE = 1 : Command enable ++ * bit12 OCDE = 1 : Option Command enable ++ * bit11-8 ADE[3:0] = 0100 : ADR[23:0] output (24 Bit Address) ++ * bit7-4 OPDE[3:0] = 0000 : Option data disable ++ * bit3-0 SPIDE[3:0] = xxxx : Transfer size ++ */ ++ rpc_writel(info, RPC_SMENR, val); ++ ++ /* ++ * RPC_SMCR = 0x00000005 ++ * bit2 SPIRE = 1 : Data read disable ++ * bit0 SPIE = 1 : SPI transfer start ++ */ ++ rpc_writel(info, RPC_SMCR, RPC_SMCR_SPIRE | RPC_SMCR_SPIE); ++ ++ rpc_wait_tend(info); ++ val = rpc_readl(info, RPC_SMRDR0); ++ ++ /* ++ * Read data from either register or memory space. ++ * Register space is always big-endian. ++ */ ++ switch (size) { ++ case RPC_HF_SIZE_64BIT: ++ if (cmd & RPC_HF_CMD_CA46) { ++ data[3] = be16_to_cpu((val >> 16) & 0xFFFF); ++ data[2] = be16_to_cpu(val & 0xFFFF); ++ } else { ++ data[3] = (val >> 16) & 0xFFFF; ++ data[2] = val & 0xFFFF; ++ } ++ val = rpc_readl(info, RPC_SMRDR1); ++ if (cmd & RPC_HF_CMD_CA46) { ++ data[1] = be16_to_cpu((val >> 16) & 0xFFFF); ++ data[0] = be16_to_cpu(val & 0xFFFF); ++ } else { ++ data[1] = (val >> 16) & 0xFFFF; ++ data[0] = val & 0xFFFF; ++ } ++ break; ++ case RPC_HF_SIZE_32BIT: ++ if (cmd & RPC_HF_CMD_CA46) { ++ data[1] = be16_to_cpu((val >> 16) & 0xFFFF); ++ data[0] = be16_to_cpu(val & 0xFFFF); ++ } else { ++ data[1] = (val >> 16) & 0xFFFF; ++ data[0] = val & 0xFFFF; ++ } ++ break; ++ default: ++ data[0] = cmd & RPC_HF_CMD_CA46 ? ++ be16_to_cpu((val >> 16) & 0xFFFF) : ++ (val >> 16) & 0xFFFF; ++ break; ++ } ++} ++ ++static void rpc_hf_wbuf_enable(flash_info_t *info, u32 addr) ++{ ++ rpc_wait_tend(info); ++ ++ /* ++ * RPC_PHYCNT = 0x80000277 ++ * bit31 CAL = 1 : PHY calibration ++ * bit4 WBUF2 = 1 : Write buffer enable 2 ++ * bit2 WBUF = 1 : Write buffer enable ++ * bit1-0 PHYMEM[1:0] = 11 : HyperFlash ++ */ ++ rpc_setl(info, RPC_PHYCNT, ++ ~(RPC_PHYCNT_WBUF2 | RPC_PHYCNT_WBUF | ++ RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3)), ++ RPC_PHYCNT_WBUF2 | RPC_PHYCNT_WBUF | ++ RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3)); ++ ++ /* ++ * RPC_DRCR = 0x001F0100 ++ * bit21-16 RBURST[4:0] = 11111 : Read burst 32 64-bit data units ++ * bit9 RCF = 1 : Clear cache ++ * bit8 RBE = 1 : Read burst enable ++ */ ++ rpc_writel(info, RPC_DRCR, ++ RPC_DRCR_RBURST(0x1F) | RPC_DRCR_RCF | RPC_DRCR_RBE); ++ ++ rpc_writel(info, RPC_SMCMR, RPC_SMCMR_CMD(RPC_HF_CMD_WRITE_MEM)); ++ ++ rpc_writel(info, RPC_SMADR, addr >> 1); ++ ++ rpc_writel(info, RPC_SMOPR, 0x0); ++ ++ /* ++ * RPC_SMDRENR = 0x00005101 ++ * bit14-12 HYPE = 101:Hyperflash mode ++ * bit8 ADDRE = 1 : Address DDR transfer ++ * bit0 SPIDRE = 1 : DATA DDR transfer ++ */ ++ rpc_writel(info, RPC_SMDRENR, ++ RPC_SMDRENR_HYPE | RPC_SMDRENR_ADDRE | RPC_SMDRENR_SPIDRE); ++ ++ /* ++ * RPC_SMENR = 0xA222540F ++ * bit31-30 CDB[1:0] = 10 : 4bit width command ++ * bit25-24 ADB[1:0] = 10 : 4bit width address ++ * bit17-16 SPIDB[1:0] = 10 : 4bit width transfer data ++ * bit15 DME = 0 : dummy cycle disable ++ * bit14 CDE = 1 : Command enable ++ * bit12 OCDE = 1 : Option Command enable ++ * bit11-8 ADE[3:0] = 0100 : ADR[23:0] output (24 Bit Address) ++ * bit7-4 OPDE[3:0] = 0000 : Option data disable ++ * bit3-0 SPIDE[3:0] = 1111 : 64-bit transfer size ++ */ ++ rpc_writel(info, RPC_SMENR, ++ RPC_SMENR_CDB(2) | RPC_SMENR_OCDB(2) | ++ RPC_SMENR_ADB(2) | RPC_SMENR_SPIDB(2) | ++ RPC_SMENR_CDE | RPC_SMENR_OCDE | ++ RPC_SMENR_ADE(4) | RPC_HF_SIZE_64BIT); ++ ++ /* Dummy read */ ++ rpc_readl(info, RPC_DRCR); ++} ++ ++static inline void rpc_hf_write_cmd(flash_info_t *info, u32 addr, u16 cmd) ++{ ++ rpc_hf_xfer(info, addr, &cmd, RPC_HF_SIZE_16BIT, RPC_HF_CMD_WRITE_REG); ++} ++ ++static inline void rpc_hf_read_reg(flash_info_t *info, u32 addr, u16 *data, ++ enum rpc_hf_size size) ++{ ++ rpc_hf_xfer(info, addr, data, size, RPC_HF_CMD_READ_REG); ++} ++ ++static inline void rpc_hf_write_reg(flash_info_t *info, u32 addr, u16 *data, ++ enum rpc_hf_size size) ++{ ++ rpc_hf_xfer(info, addr, data, size, RPC_HF_CMD_WRITE_REG); ++} ++ ++static inline void rpc_hf_read_mem(flash_info_t *info, u32 addr, u16 *data, ++ enum rpc_hf_size size) ++{ ++ rpc_hf_xfer(info, addr, data, size, RPC_HF_CMD_READ_MEM); ++} ++ ++static inline void rpc_hf_write_mem(flash_info_t *info, u32 addr, u16 *data, ++ enum rpc_hf_size size) ++{ ++ rpc_hf_xfer(info, addr, data, size, RPC_HF_CMD_WRITE_MEM); ++} ++ ++static void rpc_hf_wp(flash_info_t *info, int enable) ++{ ++ rpc_setl(info, RPC_PHYINT, ~RPC_PHYINT_WP, enable ? RPC_PHYINT_WP : 0); ++} ++ ++static void rpc_hf_unlock(flash_info_t *info, u32 addr) ++{ ++ rpc_hf_write_cmd(info, addr + RPC_CFI_UNLOCK1, ++ RPC_CFI_CMD_UNLOCK_START); ++ rpc_hf_write_cmd(info, addr + RPC_CFI_UNLOCK2, ++ RPC_CFI_CMD_UNLOCK_ACK); ++} ++ ++static inline int rpc_hf_status(flash_info_t *info, u32 addr, ++ int iterations, int delay) ++{ ++ int retval; ++ u16 status = 0; ++ ++ while (iterations-- > 0) { ++ rpc_hf_write_cmd(info, addr + RPC_CFI_UNLOCK1, ++ RPC_CFI_CMD_READ_STATUS); ++ rpc_hf_read_reg(info, addr, &status, RPC_HF_SIZE_16BIT); ++ ++ if (status & RPC_CFI_STATUS_DRB) ++ break; ++ ++ if (delay) ++ udelay(delay); ++ } ++ ++ if (!(status & RPC_CFI_STATUS_DRB)) { ++ retval = ERR_TIMOUT; ++ goto out; ++ } ++ ++ if (status & RPC_CFI_STATUS_PSB) { ++ retval = ERR_PROG_ERROR; ++ goto out; ++ } ++ ++ if (status & RPC_CFI_STATUS_ESB) { ++ retval = ERR_NOT_ERASED; ++ goto out; ++ } ++ ++ return ERR_OK; ++ ++out: ++ rpc_hf_write_cmd(info, 0, RPC_CFI_CMD_RESET); ++ return retval; ++} ++ ++static int rpc_hf_sector_erase(flash_info_t *info, int sector) ++{ ++ u32 addr = rpc_hf_flash_map(info, sector); ++ ++ rpc_hf_unlock(info, addr); ++ rpc_hf_write_cmd(info, addr + RPC_CFI_UNLOCK1, RPC_CFI_CMD_ERASE_START); ++ rpc_hf_unlock(info, addr); ++ rpc_hf_write_cmd(info, addr, RPC_CFI_CMD_ERASE_SECTOR); ++ ++ return rpc_hf_status(info, addr, 10000, 1000); ++} ++ ++static ulong rpc_hf_get_size(phys_addr_t base, int banknum) ++{ ++ flash_info_t *info = &flash_info[banknum]; ++ u16 data[2] = { 0, 0 }; ++ ulong id, size = 0; ++ ushort sectors, i; ++ ++ info->flash_id = FLASH_UNKNOWN; ++ info->sector_count = -1; ++ info->size = 0; ++ ++ rpc_hf_mode_ext(info); ++ ++ rpc_hf_wp(info, 0); ++ ++ rpc_hf_unlock(info, 0); ++ rpc_hf_write_cmd(info, RPC_CFI_UNLOCK1, RPC_CFI_CMD_READ_ID); ++ ++ rpc_hf_read_reg(info, 0x0, data, RPC_HF_SIZE_32BIT); ++ if ((data[0] & RPC_CFI_ID_MASK) != RPC_CFI_ID_MAN_SPANSION || ++ (data[1] & RPC_CFI_ID_MASK) != RPC_CFI_ID_TYPE_HYPERFLASH) ++ goto out; ++ ++ id = data[0] | data[1] << 16; ++ ++ rpc_hf_read_reg(info, 0x27 << 1, data, RPC_HF_SIZE_16BIT); ++ size = 1 << data[0]; ++ ++ if (size & (RPC_HF_ERASE_SIZE - 1)) ++ goto out; ++ ++ sectors = size / RPC_HF_ERASE_SIZE; ++ if (sectors < 1 || sectors > CONFIG_SYS_MAX_FLASH_SECT) ++ goto out; ++ ++ info->flash_id = id; ++ info->size = size; ++ info->sector_count = sectors; ++ ++ for (i = 0; i < sectors; i++) { ++ info->start[i] = base; ++ base += RPC_HF_ERASE_SIZE; ++ } ++ ++out: ++ rpc_hf_write_cmd(info, 0, RPC_CFI_CMD_RESET); ++ rpc_hf_mode_ext(info); ++ return info->size; ++} ++ ++/* ++ * Flash erase, returns: ++ * ERR_OK : OK ++ * ERR_ABORTED : Aborted by user ++ * ERR_PROTECTED : Protected sector ++ */ ++int flash_erase(flash_info_t *info, int s_first, int s_last) ++{ ++ int s, retval = ERR_OK; ++ ++ puts("Erasing Flash... "); ++ for (s = s_first; s <= s_last; s++) { ++ if (ctrlc()) { ++ printf("aborted sector %i\n", s); ++ retval = ERR_ABORTED; ++ goto out; ++ } ++ ++ if (info->protect[s]) { ++ printf("protected sector %i\n", s); ++ retval = ERR_PROTECTED; ++ goto out; ++ } ++ ++ putc('.'); ++ ++ retval = rpc_hf_sector_erase(info, s); ++ if (retval != ERR_OK) { ++ printf("error sector %i\n", s); ++ goto out; ++ } ++ } ++ puts("done\n"); ++ ++out: ++ rpc_hf_mode_ext(info); ++ return retval; ++} ++ ++/* ++ * Copy memory to flash, returns: ++ * ERR_OK : OK ++ * ERR_ABORTED : Aborted by user ++ * ERR_PROTECTED : Protected sector ++ */ ++int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) ++{ ++ union { ++ u8 b[4]; ++ u16 w[2]; ++ u32 d; ++ } data; ++ ulong offset, size; ++ int sector, idx, retval; ++ u8 last; ++ ++ retval = ERR_OK; ++ idx = 0; ++ ++ /* Handle unaligned start */ ++ if (addr & 0x1) { ++ addr--; ++ data.b[idx] = readb(addr); ++ idx++; ++ } ++ ++ /* Handle unaligned end */ ++ offset = addr + idx + cnt; ++ last = offset & 0x1 ? readb(offset) : 0xFF; ++ ++ sector = rpc_hf_flash_sector(info, addr); ++ offset = addr - info->start[sector]; ++ size = rpc_hf_flash_sector_size(info, sector) - offset; ++ offset += rpc_hf_flash_map(info, sector); ++ ++ while (cnt) { ++ if (ctrlc()) { ++ retval = ERR_ABORTED; ++ goto out; ++ } ++ ++ if (info->protect[sector]) { ++ retval = ERR_PROTECTED; ++ goto out; ++ } ++ ++ if (size > cnt) ++ size = cnt; ++ ++ putc('.'); ++ ++ cnt -= size; ++ while (size) { ++ rpc_hf_unlock(info, info->start[sector]); ++ rpc_hf_write_cmd(info, ++ info->start[sector] + RPC_CFI_UNLOCK1, ++ RPC_CFI_CMD_WRITE); ++ ++ if (size > 0x7) { ++ u32 wbuf = RPC_WBUF; ++ int block = size >= RPC_WBUF_SIZE ? ++ RPC_WBUF_SIZE : size & ~0x7; ++ ++ rpc_hf_wbuf_enable(info, offset); ++ offset += block; ++ ++ block >>= 3; ++ while (block--) { ++ while (idx < 4) { ++ data.b[idx++] = *src++; ++ size--; ++ } ++ rpc_writel(info, wbuf, data.d); ++ wbuf += 4; ++ ++ idx = 0; ++ while (idx < 4) { ++ data.b[idx++] = *src++; ++ size--; ++ } ++ rpc_writel(info, wbuf, data.d); ++ wbuf += 4; ++ ++ idx = 0; ++ } ++ ++ rpc_writel(info, RPC_SMCR, ++ RPC_SMCR_SPIWE | RPC_SMCR_SPIE); ++ } else { ++ enum rpc_hf_size bits; ++ ++ while (idx < 4) { ++ data.b[idx++] = *src++; ++ size--; ++ ++ if (!size) ++ break; ++ } ++ ++ if (idx & 0x1) ++ data.b[idx++] = last; ++ ++ switch (idx) { ++ case 2: ++ bits = RPC_HF_SIZE_16BIT; ++ break; ++ default: ++ bits = RPC_HF_SIZE_32BIT; ++ break; ++ } ++ ++ rpc_hf_write_mem(info, offset, data.w, bits); ++ offset += idx; ++ idx = 0; ++ } ++ ++ rpc_wait_tend(info); ++ rpc_setl(info, RPC_PHYCNT, ++ ~(RPC_PHYCNT_WBUF | RPC_PHYCNT_WBUF2 | ++ RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3)), ++ RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3)); ++ ++ retval = rpc_hf_status(info, info->start[sector], ++ 1000000, 10); ++ if (retval) ++ goto out; ++ } ++ ++ sector++; ++ offset = rpc_hf_flash_map(info, sector); ++ size = rpc_hf_flash_sector_size(info, sector); ++ } ++ ++out: ++ rpc_hf_mode_ext(info); ++ return retval; ++} ++ ++/* Print flash information */ ++void flash_print_info(flash_info_t *info) ++{ ++ if (info->flash_id == FLASH_UNKNOWN) ++ return; ++ ++ printf("HyperFlash Id: %lx\n", info->flash_id); ++ printf("Base Address: %lx\n", info->start[0]); ++ printf("Size: %lu MiB\n", info->size >> 20); ++ printf("Sectors: %u\n", info->sector_count); ++} ++ ++flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; ++ ++unsigned long flash_init(void) ++{ ++ int i; ++ ++ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { ++ flash_info[i].flash_id = FLASH_UNKNOWN; ++ flash_info[i].sector_count = -1; ++ flash_info[i].size = 0; ++ } ++ ++ return rpc_hf_get_size(CONFIG_SYS_RPC_FLASH_BASE, 0); ++} +-- +1.9.3 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0023-board-renesas-salvator-x-Enable-RPC-clock.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0023-board-renesas-salvator-x-Enable-RPC-clock.patch new file mode 100644 index 0000000..bcbf1f6 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0023-board-renesas-salvator-x-Enable-RPC-clock.patch @@ -0,0 +1,37 @@ +From 23e0725daf7ab27d9fa85201b4097112d8c74e1e Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Sat, 11 Jun 2016 00:50:06 +0300 +Subject: [PATCH] board: renesas: salvator-x: Enable RPC clock + +The RPC clock should have been enabled by the ARM trusted firmware. +Enable it here just in case. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + board/renesas/salvator-x/salvator-x.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c +index 491d378..803636e 100644 +--- a/board/renesas/salvator-x/salvator-x.c ++++ b/board/renesas/salvator-x/salvator-x.c +@@ -31,6 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; + #define SCIF2_MSTP310 (1 << 10) + #define ETHERAVB_MSTP812 (1 << 12) + #define DVFS_MSTP926 (1 << 26) ++#define RPC_MSTP917 (1 << 17) + #define SD0_MSTP314 (1 << 14) + #define SD1_MSTP313 (1 << 13) + #define SD2_MSTP312 (1 << 12) /* either MMC0 */ +@@ -51,6 +52,8 @@ int board_early_init_f(void) + mstp_clrbits_le32(SMSTPCR3, SMSTPCR3, SCIF2_MSTP310); + /* EHTERAVB */ + mstp_clrbits_le32(SMSTPCR8, SMSTPCR8, ETHERAVB_MSTP812); ++ /* RPC */ ++ mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, RPC_MSTP917); + /* eMMC */ + mstp_clrbits_le32(SMSTPCR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312); + /* SDHI0, 3 */ +-- +1.9.3 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0024-board-renesas-ulcb-Enable-RPC-clock.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0024-board-renesas-ulcb-Enable-RPC-clock.patch new file mode 100644 index 0000000..6328773 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0024-board-renesas-ulcb-Enable-RPC-clock.patch @@ -0,0 +1,37 @@ +From 721d2a219485d106b577701e8643638a500bba30 Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Wed, 2 Nov 2016 21:31:24 +0300 +Subject: [PATCH] board: renesas: ulcb: Enable RPC clock + +The RPC clock should have been enabled by the ARM trusted firmware. +Enable it here just in case. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + board/renesas/ulcb/ulcb.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c +index 3939f97..2e9baac 100644 +--- a/board/renesas/ulcb/ulcb.c ++++ b/board/renesas/ulcb/ulcb.c +@@ -33,6 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; + #define SCIF2_MSTP310 (1 << 10) + #define ETHERAVB_MSTP812 (1 << 12) + #define DVFS_MSTP926 (1 << 26) ++#define RPC_MSTP917 (1 << 17) + #define SD0_MSTP314 (1 << 14) + #define SD1_MSTP313 (1 << 13) + #define SD2_MSTP312 (1 << 12) +@@ -53,6 +54,8 @@ int board_early_init_f(void) + mstp_clrbits_le32(SMSTPCR3, SMSTPCR3, SCIF2_MSTP310); + /* EHTERAVB */ + mstp_clrbits_le32(SMSTPCR8, SMSTPCR8, ETHERAVB_MSTP812); ++ /* RPC */ ++ mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, RPC_MSTP917); + /* eMMC */ + mstp_clrbits_le32(SMSTPCR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312); + /* SDHI0 */ +-- +1.9.3 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0025-configs-r8a7795_salvator-x-Enable-RPC-HyperFlash-sup.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0025-configs-r8a7795_salvator-x-Enable-RPC-HyperFlash-sup.patch new file mode 100644 index 0000000..55f141e --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0025-configs-r8a7795_salvator-x-Enable-RPC-HyperFlash-sup.patch @@ -0,0 +1,35 @@ +From 3b35b4c283d4dc95cf92d4a5e15f1a048eb4013f Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Mon, 4 Apr 2016 18:41:55 +0300 +Subject: [PATCH] configs: r8a7795_salvator-x: Enable RPC HyperFlash support + +This enables flash commands along with the RPC HyperFlash support. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + include/configs/r8a7795_salvator-x.h | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/include/configs/r8a7795_salvator-x.h b/include/configs/r8a7795_salvator-x.h +index d5c4c93..db5eae5 100644 +--- a/include/configs/r8a7795_salvator-x.h ++++ b/include/configs/r8a7795_salvator-x.h +@@ -28,10 +28,13 @@ + + /* [A] Hyper Flash */ + /* use to RPC(SPI Multi I/O Bus Controller) */ ++#define CONFIG_RPC_HYPERFLASH + +- /* underconstruction */ ++#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_RPC_FLASH_BASE ++#define CONFIG_SYS_MAX_FLASH_BANKS 1 ++#define CONFIG_SYS_MAX_FLASH_SECT 256 + +-#define CONFIG_SYS_NO_FLASH ++#define CONFIG_CMD_FLASH + + /* Ethernet RAVB */ + #define CONFIG_RAVB +-- +1.9.3 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0026-configs-r8a7796_salvator-x-Enable-RPC-HyperFlash-sup.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0026-configs-r8a7796_salvator-x-Enable-RPC-HyperFlash-sup.patch new file mode 100644 index 0000000..cbc8ac2 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0026-configs-r8a7796_salvator-x-Enable-RPC-HyperFlash-sup.patch @@ -0,0 +1,35 @@ +From 573a190264dabefd8899c681f62d3eb3ec94a78f Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Wed, 2 Nov 2016 22:17:32 +0300 +Subject: [PATCH] configs: r8a7796_salvator-x: Enable RPC HyperFlash support + +This enables flash commands along with the RPC HyperFlash support. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + include/configs/r8a7796_salvator-x.h | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/include/configs/r8a7796_salvator-x.h b/include/configs/r8a7796_salvator-x.h +index 2926b95..6d6a2ef 100644 +--- a/include/configs/r8a7796_salvator-x.h ++++ b/include/configs/r8a7796_salvator-x.h +@@ -28,10 +28,13 @@ + + /* [A] Hyper Flash */ + /* use to RPC(SPI Multi I/O Bus Controller) */ ++#define CONFIG_RPC_HYPERFLASH + +- /* underconstruction */ ++#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_RPC_FLASH_BASE ++#define CONFIG_SYS_MAX_FLASH_BANKS 1 ++#define CONFIG_SYS_MAX_FLASH_SECT 256 + +-#define CONFIG_SYS_NO_FLASH ++#define CONFIG_CMD_FLASH + + /* Ethernet RAVB */ + #define CONFIG_RAVB +-- +1.9.3 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0027-configs-h3ulcb-Enable-RPC-HyperFlash-support.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0027-configs-h3ulcb-Enable-RPC-HyperFlash-support.patch new file mode 100644 index 0000000..ecc5768 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0027-configs-h3ulcb-Enable-RPC-HyperFlash-support.patch @@ -0,0 +1,36 @@ +From be046fe3844db04b04a0c1051375ce7bde7c1dc7 Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Wed, 2 Nov 2016 21:34:50 +0300 +Subject: [PATCH] configs: h3ulcb: Enable RPC HyperFlash support + +This enables flash commands along with the RPC HyperFlash support. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + include/configs/h3ulcb.h | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +diff --git a/include/configs/h3ulcb.h b/include/configs/h3ulcb.h +index 73e856d..edda5e8 100644 +--- a/include/configs/h3ulcb.h ++++ b/include/configs/h3ulcb.h +@@ -27,7 +27,15 @@ + #define CONFIG_CONS_SCIF2 + #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ + +-#define CONFIG_SYS_NO_FLASH ++/* [A] Hyper Flash */ ++/* use to RPC(SPI Multi I/O Bus Controller) */ ++#define CONFIG_RPC_HYPERFLASH ++ ++#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_RPC_FLASH_BASE ++#define CONFIG_SYS_MAX_FLASH_BANKS 1 ++#define CONFIG_SYS_MAX_FLASH_SECT 256 ++ ++#define CONFIG_CMD_FLASH + + /* Ethernet RAVB */ + #define CONFIG_RAVB +-- +1.9.3 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0028-configs-m3ulcb-Enable-RPC-HyperFlash-support.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0028-configs-m3ulcb-Enable-RPC-HyperFlash-support.patch new file mode 100644 index 0000000..9903433 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0028-configs-m3ulcb-Enable-RPC-HyperFlash-support.patch @@ -0,0 +1,36 @@ +From 592ada9568e8cd9ebbee8f3a609435471e5357d6 Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Wed, 2 Nov 2016 21:33:43 +0300 +Subject: [PATCH] configs: m3ulcb: Enable RPC HyperFlash support + +This enables flash commands along with the RPC HyperFlash support. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + include/configs/m3ulcb.h | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +diff --git a/include/configs/m3ulcb.h b/include/configs/m3ulcb.h +index a242079..e3fd75b 100644 +--- a/include/configs/m3ulcb.h ++++ b/include/configs/m3ulcb.h +@@ -27,7 +27,15 @@ + #define CONFIG_CONS_SCIF2 + #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ + +-#define CONFIG_SYS_NO_FLASH ++/* [A] Hyper Flash */ ++/* use to RPC(SPI Multi I/O Bus Controller) */ ++#define CONFIG_RPC_HYPERFLASH ++ ++#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_RPC_FLASH_BASE ++#define CONFIG_SYS_MAX_FLASH_BANKS 1 ++#define CONFIG_SYS_MAX_FLASH_SECT 256 ++ ++#define CONFIG_CMD_FLASH + + /* MEMORY */ + /* M3ULCB has 2 banks each 1GB */ +-- +1.9.3 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch new file mode 100644 index 0000000..479f23f --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0041-board-renesas-ulcb-console-on-scif1.patch @@ -0,0 +1,28 @@ +From 4afdb59d00b3cf8c92006b929bd9e48f4f87d6ce Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Thu, 19 May 2016 08:32:56 +0300 +Subject: [PATCH] uboot: H3ULCB console on scif1 + +Set console on SCIF1 port for H3ULCB. +This is only for H3ULCB.HAD + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +--- + include/configs/h3ulcb.h | 4 ++-- + 1 file changed, 1 insertions(+), 1 deletions(-) + +diff --git a/include/configs/h3ulcb.h b/include/configs/h3ulcb.h +index b9be845..3da2e5a 100644 +--- a/include/configs/h3ulcb.h ++++ b/include/configs/h3ulcb.h +@@ -23,6 +23,6 @@ + + /* SCIF */ + #define CONFIG_SCIF_CONSOLE +-#define CONFIG_CONS_SCIF2 ++#define CONFIG_CONS_SCIF1 + #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ + +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0042-board-renesas-ulcb-set-all-RAVB-pins-strengh-to-maximum.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0042-board-renesas-ulcb-set-all-RAVB-pins-strengh-to-maximum.patch new file mode 100644 index 0000000..638fa7c --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0042-board-renesas-ulcb-set-all-RAVB-pins-strengh-to-maximum.patch @@ -0,0 +1,55 @@ +From b247dea7b49d7e66e1848da71e28ff5fe9acf5e1 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Thu, 16 Jun 2016 11:41:43 +0300 +Subject: [PATCH] board: renesas: ulcb: set all RAVB pins strengh to maximum + +This is only for H3ULCB.HAD with custom TTTeck ethernet switch +parameters + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +--- + board/renesas/ulcb/ulcb.c | 21 +++++++++++++++++++++ + 2 files changed, 21 insertions(+), 5 deletions(-) + +diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c +index 5652014..f77f946 100644 +--- a/board/renesas/ulcb/ulcb.c ++++ b/board/renesas/ulcb/ulcb.c +@@ -72,6 +72,22 @@ int board_early_init_f(void) + + DECLARE_GLOBAL_DATA_PTR; + ++#define PFC_PMMR 0xE6060000 ++#define PFC_DRVCTRL1 0xE6060304 ++#define PFC_DRVCTRL2 0xE6060308 ++#define PFC_DRVCTRL3 0xE606030C ++ ++static void write_drvctrl(u32 value, u32 modify_bit, void *reg) ++{ ++ u32 val; ++ ++ val = readl(reg); ++ val &= ~modify_bit; ++ val |= value; ++ writel(~val, PFC_PMMR); ++ writel(val, reg); ++} ++ + int board_init(void) + { + u32 val; +@@ -86,6 +102,11 @@ int board_init(void) + val = readl(PFC_PUEN6) | PUEN_USB1_OVC | PUEN_USB1_PWEN; + writel(val, PFC_PUEN6); + ++ /* EtherAVB pin strength */ ++ write_drvctrl(0x00000007, 0x00000007, (void *)PFC_DRVCTRL1); ++ write_drvctrl(0x77777777, 0x77777777, (void *)PFC_DRVCTRL2); ++ write_drvctrl(0x77700000, 0x77700000, (void *)PFC_DRVCTRL3); ++ + #ifdef CONFIG_RAVB + #if defined(CONFIG_R8A7795) + if (rcar_is_legacy()) { +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0043-board-renesas-ulcb-support-fixed-PHY.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0043-board-renesas-ulcb-support-fixed-PHY.patch new file mode 100644 index 0000000..b646d99 --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0043-board-renesas-ulcb-support-fixed-PHY.patch @@ -0,0 +1,54 @@ +From 8f65b4710c1f51d01032db201543d0a8269a715f Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Fri, 20 May 2016 01:18:44 +0300 +Subject: [PATCH] board: renesas/ ulcb: support fixed-PHY + +Add support for fixed-PHY on ULCB board + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +--- + board/renesas/ulcb/ulcb.c | 5 +++++ + include/configs/h3ulcb.h | 3 +++ + 2 files changed, 8 insertions(+), 0 deletion(-) + +diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c +index 32a63c9..dcca4f8 100644 +--- a/board/renesas/ulcb/ulcb.c ++++ b/board/renesas/ulcb/ulcb.c +@@ -26,6 +26,7 @@ + #include <asm/arch/sh_sdhi.h> + #include <i2c.h> + #include <mmc.h> ++#include <phy.h> + + DECLARE_GLOBAL_DATA_PTR; + +@@ -193,6 +193,10 @@ int board_eth_init(bd_t *bis) + /* ULCB has KSZ9031RNX */ + int board_phy_config(struct phy_device *phydev) + { ++#ifdef CONFIG_PHY_FIXED ++ if (!strncmp(phydev->drv->name, "fixed-PHY", 9) && phydev->drv->config) ++ return phydev->drv->config(phydev); ++#endif + return 0; + } + +diff --git a/include/configs/h3ulcb.h b/include/configs/h3ulcb.h +index 8582b64..b9be845 100644 +--- a/include/configs/h3ulcb.h ++++ b/include/configs/h3ulcb.h +@@ -40,7 +40,9 @@ + #define CONFIG_RAVB_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID + #define CONFIG_NET_MULTI + #define CONFIG_PHYLIB +-#define CONFIG_PHY_MICREL ++#define CONFIG_PHY_FIXED ++#define CONFIG_PHY_FIXED_SPEED SPEED_1000 ++#define CONFIG_PHY_FIXED_DUPLEX DUPLEX_FULL + #define CONFIG_BITBANGMII + #define CONFIG_BITBANGMII_MULTI + #define CONFIG_SH_ETHER_BITBANG +-- +1.9.1 + |