diff options
Diffstat (limited to 'meta-rcar-gen3-adas/recipes-bsp')
4 files changed, 556 insertions, 1 deletions
diff --git a/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bbappend b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bbappend index 253762c..0de1218 100644 --- a/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bbappend +++ b/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bbappend @@ -4,6 +4,7 @@ COMPATIBLE_MACHINE_eagle = "eagle" COMPATIBLE_MACHINE_v3msk = "v3msk" COMPATIBLE_MACHINE_v3mzf = "v3mzf" COMPATIBLE_MACHINE_condor = "condor" +COMPATIBLE_MACHINE_v3hsk = "v3hsk" ATFW_OPT_r8a7797 = "LSI=V3M RCAR_DRAM_SPLIT=0 RCAR_LOSSY_ENABLE=0 PMIC_ROHM_BD9571=0 RCAR_SYSTEM_SUSPEND=0 SPD=none" ATFW_OPT_r8a7798 = "LSI=V3H RCAR_DRAM_SPLIT=0 RCAR_LOSSY_ENABLE=0 PMIC_ROHM_BD9571=0 RCAR_SYSTEM_SUSPEND=0 SPD=none RCAR_SECURE_BOOT=0" @@ -27,3 +28,8 @@ do_deploy_append_condor() { rm ${DEPLOYDIR}/bootparam_sa0.bin rm ${DEPLOYDIR}/bootparam_sa0.srec } + +do_deploy_append_v3hsk() { + rm ${DEPLOYDIR}/bootparam_sa0.bin + rm ${DEPLOYDIR}/bootparam_sa0.srec +} diff --git a/meta-rcar-gen3-adas/recipes-bsp/cr7-loader/cr7-loader_git.bb b/meta-rcar-gen3-adas/recipes-bsp/cr7-loader/cr7-loader_git.bb index bc80d42..e990273 100644 --- a/meta-rcar-gen3-adas/recipes-bsp/cr7-loader/cr7-loader_git.bb +++ b/meta-rcar-gen3-adas/recipes-bsp/cr7-loader/cr7-loader_git.bb @@ -15,7 +15,7 @@ SRCREV = "9570cd170e876801370560bb0c417816cbfe21d2" PV = "v1.0+renesas+git" -COMPATIBLE_MACHINE = "condor" +COMPATIBLE_MACHINE = "condor|v3hsk" PLATFORM = "rcar" do_compile() { diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/00201-board-renesas-Add-V3HSK-board.patch b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/00201-board-renesas-Add-V3HSK-board.patch new file mode 100644 index 0000000..94067dc --- /dev/null +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/00201-board-renesas-Add-V3HSK-board.patch @@ -0,0 +1,548 @@ +From 519ee2d3ff6049263277b24dd8326a27a8d102e2 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Tue, 13 Feb 2018 17:17:39 +0300 +Subject: [PATCH] board: renesas: Add V3H Starter Kit board + +V3H Starter Kit is a board based on R-Car V3H SoC (R8A7798) + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +--- + arch/arm/cpu/armv8/Kconfig | 4 + + board/renesas/v3hsk/Kconfig | 15 +++ + board/renesas/v3hsk/MAINTAINERS | 6 + + board/renesas/v3hsk/Makefile | 10 ++ + board/renesas/v3hsk/v3hsk.c | 263 ++++++++++++++++++++++++++++++++++++++++ + configs/v3hsk_defconfig | 10 ++ + include/configs/v3hsk.h | 160 ++++++++++++++++++++++++ + 7 files changed, 468 insertions(+) + create mode 100644 board/renesas/v3hsk/Kconfig + create mode 100644 board/renesas/v3hsk/MAINTAINERS + create mode 100644 board/renesas/v3hsk/Makefile + create mode 100644 board/renesas/v3hsk/v3hsk.c + create mode 100644 configs/v3hsk_defconfig + create mode 100644 include/configs/v3hsk.h + +diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig +index a2706a6..7309838 100644 +--- a/arch/arm/cpu/armv8/Kconfig ++++ b/arch/arm/cpu/armv8/Kconfig +@@ -28,6 +28,9 @@ config TARGET_V3MZF + config TARGET_CONDOR + bool "CONDOR board" + ++config TARGET_V3HSK ++ bool "V3HSK board" ++ + endchoice + + config R8A7796X +@@ -64,5 +67,6 @@ source "board/renesas/eagle/Kconfig" + source "board/renesas/v3msk/Kconfig" + source "board/renesas/condor/Kconfig" + source "board/renesas/v3mzf/Kconfig" ++source "board/renesas/v3hsk/Kconfig" + + endif +diff --git a/board/renesas/v3hsk/Kconfig b/board/renesas/v3hsk/Kconfig +new file mode 100644 +index 0000000..2346ee8 +--- /dev/null ++++ b/board/renesas/v3hsk/Kconfig +@@ -0,0 +1,15 @@ ++if TARGET_V3HSK ++ ++config SYS_SOC ++ default "rcar_gen3" ++ ++config SYS_BOARD ++ default "v3hsk" ++ ++config SYS_VENDOR ++ default "renesas" ++ ++config SYS_CONFIG_NAME ++ default "v3hsk" if R8A7798 ++ ++endif +diff --git a/board/renesas/v3hsk/MAINTAINERS b/board/renesas/v3hsk/MAINTAINERS +new file mode 100644 +index 0000000..f9176b5 +--- /dev/null ++++ b/board/renesas/v3hsk/MAINTAINERS +@@ -0,0 +1,6 @@ ++CONDOR BOARD ++M: Cogent Embedded, Inc. <source@cogentembedded.com> ++S: Maintained ++F: board/renesas/v3hsk/ ++F: include/configs/v3hsk.h ++F: configs/v3hsk_defconfig +diff --git a/board/renesas/v3hsk/Makefile b/board/renesas/v3hsk/Makefile +new file mode 100644 +index 0000000..0ac2642 +--- /dev/null ++++ b/board/renesas/v3hsk/Makefile +@@ -0,0 +1,10 @@ ++# ++# board/renesas/v3hsk/Makefile ++# ++# Copyright (C) 2018 Renesas Electronics Corp. ++# Copyright (C) 2018 Cogent Embedded, Inc. ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++obj-y := v3hsk.o ../rcar-gen3-common/common.o +diff --git a/board/renesas/v3hsk/v3hsk.c b/board/renesas/v3hsk/v3hsk.c +new file mode 100644 +index 0000000..df61428 +--- /dev/null ++++ b/board/renesas/v3hsk/v3hsk.c +@@ -0,0 +1,263 @@ ++/* ++ * board/renesas/v3hsk/v3hsk.c ++ * This is V3HSK board support. ++ * ++ * Copyright (C) 2018 Renesas Electronics Corp. ++ * Copyright (C) 2018 Cogent Embedded, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <malloc.h> ++#include <netdev.h> ++#include <dm.h> ++#include <dm/platform_data/serial_sh.h> ++#include <asm/processor.h> ++#include <asm/mach-types.h> ++#include <asm/io.h> ++#include <asm/errno.h> ++#include <asm/arch/sys_proto.h> ++#include <asm/gpio.h> ++#include <asm/arch/prr_depend.h> ++#include <asm/arch/gpio.h> ++#include <asm/arch/rcar_gen3.h> ++#include <asm/arch/rcar-mstp.h> ++#include <asm/arch/sh_sdhi.h> ++#include <i2c.h> ++#include <mmc.h> ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define SCIF0_MSTP207 (1 << 7) ++#define GETHER_MSTP813 (1 << 13) ++#define RPC_MSTP917 (1 << 17) ++#define SD0_MSTP314 (1 << 14) ++ ++#define SD0CKCR 0xE6150074 ++ ++#define PFC_PMMR 0xe6060000 ++#define PFC_POC1 0xe6060384 ++#define POC_MMC_3V3 0x00fff800 ++ ++void s_init(void) ++{ ++ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; ++ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; ++ ++ /* Watchdog init */ ++ writel(0xA5A5A500, &rwdt->rwtcsra); ++ writel(0xA5A5A500, &swdt->swtcsra); ++} ++ ++int board_early_init_f(void) ++{ ++ int freq; ++ ++ rcar_prr_init(); ++ ++ writel(0xa5a5ffff, 0xe6150900); ++ writel(0x5a5a0000, 0xe6150904); ++ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, 0x02000000); ++ /* SCIF0 */ ++ mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIF0_MSTP207); ++ /* SDHI0/MMC */ ++ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314); ++#if defined(CONFIG_RAVB) ++ /* RAVB Ethernet */ ++ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, RAVB_MSTP812); ++#elif defined(CONFIG_SH_ETHER) ++ /* Gigabit Ethernet */ ++ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, GETHER_MSTP813); ++#endif ++ /* QSPI/RPC */ ++ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, RPC_MSTP917); ++ ++ freq = rcar_get_sdhi_config_clk(); ++ writel(freq, SD0CKCR); ++ ++ return 0; ++} ++ ++int board_init(void) ++{ ++ /* address of boot parameters */ ++ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; ++ ++ /* Init PFC controller */ ++ pinmux_init(); ++#if defined(CONFIG_RAVB) ++ gpio_request(GPIO_GFN_AVB0_AVTP_CAPTURE, NULL); ++ gpio_request(GPIO_GFN_AVB0_AVTP_MATCH, NULL); ++ gpio_request(GPIO_FN_AVB0_LINK, NULL); ++ gpio_request(GPIO_FN_AVB0_PHY_INT, NULL); ++ /* gpio_request(GPIO_FN_AVB0_MAGIC, NULL); - PHY reset gpio */ ++ gpio_request(GPIO_FN_AVB0_MDC, NULL); ++ gpio_request(GPIO_FN_AVB0_MDIO, NULL); ++ gpio_request(GPIO_FN_AVB0_TXCREFCLK, NULL); ++ gpio_request(GPIO_FN_AVB0_TD3, NULL); ++ gpio_request(GPIO_FN_AVB0_TD2, NULL); ++ gpio_request(GPIO_FN_AVB0_TD1, NULL); ++ gpio_request(GPIO_FN_AVB0_TD0, NULL); ++ gpio_request(GPIO_FN_AVB0_TXC, NULL); ++ gpio_request(GPIO_FN_AVB0_TX_CTL, NULL); ++ gpio_request(GPIO_FN_AVB0_RD3, NULL); ++ gpio_request(GPIO_FN_AVB0_RD2, NULL); ++ gpio_request(GPIO_FN_AVB0_RD1, NULL); ++ gpio_request(GPIO_FN_AVB0_RD0, NULL); ++ gpio_request(GPIO_FN_AVB0_RXC, NULL); ++ gpio_request(GPIO_FN_AVB0_RX_CTL, NULL); ++ gpio_request(GPIO_IFN_AVB0_AVTP_CAPTURE, NULL); ++ gpio_request(GPIO_FN_AVB0_AVTP_PPS, NULL); ++ ++ /* PHY_RST */ ++ gpio_request(GPIO_GP_1_16, NULL); ++ gpio_direction_output(GPIO_GP_1_16, 0); ++ mdelay(20); ++ gpio_set_value(GPIO_GP_1_16, 1); ++ udelay(1); ++#elif defined(CONFIG_SH_ETHER) ++ gpio_request(GPIO_FN_GETHER_LINK_A, NULL); ++ gpio_request(GPIO_FN_GETHER_PHY_INT_A, NULL); ++ /* gpio_request(GPIO_FN_GETHER_MAGIC, NULL); - PHY reset gpio */ ++ gpio_request(GPIO_FN_GETHER_MDC_A, NULL); ++ gpio_request(GPIO_FN_GETHER_MDIO_A, NULL); ++ gpio_request(GPIO_FN_GETHER_TXCREFCLK, NULL); ++ gpio_request(GPIO_FN_GETHER_TXCREFCLK_MEGA, NULL); ++ gpio_request(GPIO_FN_GETHER_TD3, NULL); ++ gpio_request(GPIO_FN_GETHER_TD2, NULL); ++ gpio_request(GPIO_FN_GETHER_TD1, NULL); ++ gpio_request(GPIO_FN_GETHER_TD0, NULL); ++ gpio_request(GPIO_FN_GETHER_TXC, NULL); ++ gpio_request(GPIO_FN_GETHER_TX_CTL, NULL); ++ gpio_request(GPIO_FN_GETHER_RD3, NULL); ++ gpio_request(GPIO_FN_GETHER_RD2, NULL); ++ gpio_request(GPIO_FN_GETHER_RD1, NULL); ++ gpio_request(GPIO_FN_GETHER_RD0, NULL); ++ gpio_request(GPIO_FN_GETHER_RXC, NULL); ++ gpio_request(GPIO_FN_GETHER_RX_CTL, NULL); ++ ++ /* PHY_RST */ ++ gpio_request(GPIO_GP_4_22, NULL); ++ gpio_direction_output(GPIO_GP_4_22, 0); ++ mdelay(20); ++ gpio_set_value(GPIO_GP_4_22, 1); ++ udelay(1); ++#endif ++ /* QSPI/RPC */ ++ gpio_request(GPIO_FN_QSPI0_SPCLK, NULL); ++ gpio_request(GPIO_FN_QSPI0_MOSI_IO0, NULL); ++ gpio_request(GPIO_FN_QSPI0_MISO_IO1, NULL); ++ gpio_request(GPIO_FN_QSPI0_IO2, NULL); ++ gpio_request(GPIO_FN_QSPI0_IO3, NULL); ++ gpio_request(GPIO_FN_QSPI0_SSL, NULL); ++ gpio_request(GPIO_FN_QSPI1_SPCLK, NULL); ++ gpio_request(GPIO_FN_QSPI1_MOSI_IO0, NULL); ++ gpio_request(GPIO_FN_QSPI1_MISO_IO1, NULL); ++ gpio_request(GPIO_FN_QSPI1_IO2, NULL); ++ gpio_request(GPIO_FN_QSPI1_IO3, NULL); ++ gpio_request(GPIO_FN_QSPI1_SSL, NULL); ++ gpio_request(GPIO_FN_RPC_RESET_N, NULL); ++ gpio_request(GPIO_FN_RPC_WP_N, NULL); ++ gpio_request(GPIO_FN_RPC_INT_N, NULL); ++ ++ return 0; ++} ++ ++#if defined(CONFIG_RAVB) ++#define MAHR 0xE68005C0 ++#define MALR 0xE68005C8 ++#elif defined(CONFIG_SH_ETHER) ++#define MAHR 0xE74005C0 ++#define MALR 0xE74005C8 ++#endif ++int board_eth_init(bd_t *bis) ++{ ++ int ret = -ENODEV; ++ ++ u32 val; ++ unsigned char enetaddr[6]; ++ ++ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) ++ return ret; ++ ++ /* Set Mac address */ ++ val = enetaddr[0] << 24 | enetaddr[1] << 16 | ++ enetaddr[2] << 8 | enetaddr[3]; ++ writel(val, MAHR); ++ ++ val = enetaddr[4] << 8 | enetaddr[5]; ++ writel(val, MALR); ++#if defined(CONFIG_RAVB) ++ ret = ravb_initialize(bis); ++#elif defined(CONFIG_SH_ETHER) ++ ret = sh_eth_initialize(bis); ++#endif ++ return ret; ++} ++ ++/* V3HSK has KSZ9031RNX */ ++int board_phy_config(struct phy_device *phydev) ++{ ++ return 0; ++} ++ ++int board_mmc_init(bd_t *bis) ++{ ++ int ret = -ENODEV; ++#ifdef CONFIG_SH_SDHI ++ u32 val; ++ ++ /* SDHI2/eMMC */ ++ gpio_request(GPIO_FN_MMC_D0, NULL); ++ gpio_request(GPIO_FN_MMC_D1, NULL); ++ gpio_request(GPIO_FN_MMC_D2, NULL); ++ gpio_request(GPIO_FN_MMC_D3, NULL); ++ gpio_request(GPIO_FN_MMC_D4, NULL); ++ gpio_request(GPIO_FN_MMC_D5, NULL); ++ gpio_request(GPIO_FN_MMC_D6, NULL); ++ gpio_request(GPIO_FN_MMC_D7, NULL); ++ gpio_request(GPIO_FN_MMC_CLK, NULL); ++ gpio_request(GPIO_FN_MMC_CMD, NULL); ++ gpio_request(GPIO_FN_MMC_CD, NULL); ++ gpio_request(GPIO_FN_MMC_WP, NULL); ++ ++ val = readl(PFC_POC1); ++ val &= ~POC_MMC_3V3; /* POC = 1.8V */ ++ writel(~val, PFC_PMMR); ++ writel(val, PFC_POC1); ++ ++ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 0, ++ SH_SDHI_QUIRK_64BIT_BUF); ++#endif ++ return ret; ++} ++ ++int dram_init(void) ++{ ++ gd->ram_size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} ++ ++void dram_init_banksize(void) ++{ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++} ++ ++const struct rcar_sysinfo sysinfo = { ++ CONFIG_RCAR_BOARD_STRING ++}; ++ ++void reset_cpu(ulong addr) ++{ ++} ++ ++#if defined(CONFIG_DISPLAY_BOARDINFO) ++int checkboard(void) ++{ ++ printf("Board: %s\n", sysinfo.board_string); ++ return 0; ++} ++#endif +diff --git a/configs/v3hsk_defconfig b/configs/v3hsk_defconfig +new file mode 100644 +index 0000000..938ffe9 +--- /dev/null ++++ b/configs/v3hsk_defconfig +@@ -0,0 +1,10 @@ ++CONFIG_ARM=y ++CONFIG_RCAR_GEN3=y ++CONFIG_DM_SERIAL=y ++CONFIG_TARGET_V3HSK=y ++CONFIG_R8A7798=y ++CONFIG_SPL=y ++CONFIG_SH_SDHI=y ++CONFIG_SPI_FLASH=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_BAR=y +diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h +new file mode 100644 +index 0000000..6aa6625 +--- /dev/null ++++ b/include/configs/v3hsk.h +@@ -0,0 +1,160 @@ ++/* ++ * include/configs/v3hsk.h ++ * This file is V3HSK board configuration. ++ * CPU r8a7798. ++ * ++ * Copyright (C) 2018 Renesas Electronics Corp. ++ * Copyright (C) 2018 Cogent Embedded, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __V3HSK_H ++#define __V3HSK_H ++ ++#undef DEBUG ++#define CONFIG_RCAR_BOARD_STRING "V3HSK" ++#define CONFIG_RCAR_TARGET_STRING "r8a7798" ++ ++#include "rcar-gen3-common.h" ++ ++//#define CONFIG_SYS_DCACHE_OFF ++//#define CONFIG_SYS_ICACHE_OFF ++ ++/* SCIF */ ++#define CONFIG_SCIF_CONSOLE ++#define CONFIG_CONS_SCIF0 ++#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ ++ ++/* [A] Hyper Flash */ ++/* use to RPC(SPI Multi I/O Bus Controller) */ ++ ++ /* underconstruction */ ++ ++#define CONFIG_SYS_NO_FLASH ++#if defined(CONFIG_SYS_NO_FLASH) ++#define CONFIG_SPI ++#define CONFIG_RCAR_GEN3_QSPI ++#define CONFIG_SH_QSPI_BASE 0xEE200000 ++#define CONFIG_CMD_SF ++#define CONFIG_CMD_SPI ++#define CONFIG_SPI_FLASH ++#define CONFIG_SPI_FLASH_SPANSION ++#else ++#undef CONFIG_CMD_SF ++#undef CONFIG_CMD_SPI ++#undef CONFIG_SPI_FLASH ++#undef CONFIG_SPI_FLASH_SPANSION ++#endif ++ ++#if 0 ++/* Ethernet RAVB */ ++#define CONFIG_RAVB ++#define CONFIG_RAVB_PHY_ADDR 0x0 ++#define CONFIG_RAVB_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID ++#define CONFIG_NET_MULTI ++#define CONFIG_PHYLIB ++#define CONFIG_PHY_MICREL ++#define CONFIG_BITBANGMII ++#define CONFIG_BITBANGMII_MULTI ++#define CONFIG_SH_ETHER_BITBANG ++#else ++/* GETHER */ ++#define CONFIG_NET_MULTI ++#define CONFIG_SH_ETHER ++#define CONFIG_SH_ETHER_USE_PORT 0 ++#define CONFIG_SH_ETHER_PHY_ADDR 0x0 ++#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID ++#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 ++#define CONFIG_SH_ETHER_CACHE_WRITEBACK ++#define CONFIG_SH_ETHER_CACHE_INVALIDATE ++#define CONFIG_PHYLIB ++#define CONFIG_PHY_MICREL ++#define CONFIG_BITBANGMII ++#define CONFIG_BITBANGMII_MULTI ++#endif ++ ++/* Board Clock */ ++/* XTAL_CLK : 33.33MHz */ ++#define RCAR_XTAL_CLK 33333333u ++#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK ++/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ ++/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ ++#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) ++#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) ++#define CONFIG_S3D2_CLK_FREQ (266666666u/2) ++#define CONFIG_S3D4_CLK_FREQ (266666666u/4) ++ ++/* Generic Timer Definitions (use in assembler source) */ ++#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ ++ ++/* Generic Interrupt Controller Definitions */ ++#define GICD_BASE (0xF1010000) ++#define GICC_BASE (0xF1020000) ++#define CONFIG_GICV2 ++ ++/* i2c */ ++#define CONFIG_SYS_I2C ++#define CONFIG_SYS_I2C_SH ++#define CONFIG_SYS_I2C_SLAVE 0x60 ++#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 ++#define CONFIG_SYS_I2C_SH_SPEED0 400000 ++#define CONFIG_SH_I2C_DATA_HIGH 4 ++#define CONFIG_SH_I2C_DATA_LOW 5 ++#define CONFIG_SH_I2C_CLOCK 10000000 ++ ++#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 ++ ++/* USB */ ++#undef CONFIG_CMD_USB ++ ++/* SDHI */ ++#define CONFIG_MMC ++#define CONFIG_CMD_MMC ++#define CONFIG_GENERIC_MMC ++#define CONFIG_SH_SDHI_FREQ 200000000 ++#define CONFIG_SH_SDHI_MMC ++ ++/* ENV setting */ ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_SECT_SIZE (256 * 1024) ++#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) ++#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) ++ ++//#define CONFIG_ENV_IS_IN_MMC ++#define CONFIG_ENV_IS_IN_SPI_FLASH ++ ++#if defined(CONFIG_ENV_IS_IN_MMC) ++/* Environment in eMMC, at the end of 2nd "boot sector" */ ++#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) ++#define CONFIG_SYS_MMC_ENV_DEV 0 ++#define CONFIG_SYS_MMC_ENV_PART 2 ++#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) ++/* Environment in QSPI */ ++#define CONFIG_ENV_ADDR 0x700000 ++#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++/* Module clock supply/stop status bits */ ++/* MFIS */ ++#define CONFIG_SMSTP2_ENA 0x00002000 ++/* serial(SCIF0) */ ++#define CONFIG_SMSTP3_ENA 0x00000400 ++/* INTC-AP, INTC-EX */ ++#define CONFIG_SMSTP4_ENA 0x00000180 ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "fdt_high=0xffffffffffffffff\0" \ ++ "initrd_high=0xffffffffffffffff\0" \ ++ "ethaddr=2E:11:22:33:44:55\0" ++ ++#define CONFIG_BOOTARGS \ ++ "root=/dev/nfs rw ip=dhcp" ++ ++#define CONFIG_BOOTCOMMAND \ ++ "bootp 0x48080000 Image; tftp 0x48000000 r8a7798-v3hsk.dtb; " \ ++ "booti 0x48080000 - 0x48000000" ++ ++#endif /* __V3HSK_H */ +-- +1.9.1 + diff --git a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot_2015.04.bbappend b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot_2015.04.bbappend index d912f32..146c392 100644 --- a/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot_2015.04.bbappend +++ b/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot_2015.04.bbappend @@ -21,6 +21,7 @@ SRC_URI_append = " \ file://0018-arm-renesas-Add-Renesas-R8A7798-SoC-support.patch \ file://0019-board-renesas-Add-Condor-board.patch \ file://0020-board-renesas-Add-V3MZF-board.patch \ + file://00201-board-renesas-Add-V3HSK-board.patch \ file://0021-ARM-rcar_gen3-Add-RPC-flash-definitions.patch \ file://0022-mtd-Add-RPC-HyperFlash-support.patch \ file://0023-board-renesas-salvator-x-Enable-RPC-clock.patch \ |