diff options
Diffstat (limited to 'meta-rcar-gen3')
7 files changed, 4 insertions, 434 deletions
diff --git a/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware/0001-Update-IPL-patch-for-DDR-setting-rev.0.33.patch b/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware/0001-Update-IPL-patch-for-DDR-setting-rev.0.33.patch deleted file mode 100644 index 93e2c88..0000000 --- a/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware/0001-Update-IPL-patch-for-DDR-setting-rev.0.33.patch +++ /dev/null @@ -1,195 +0,0 @@ -From 21abfbb558967dbfad75ed18abdb426dbb185eb9 Mon Sep 17 00:00:00 2001 -From: Chiaki Fujii <chiaki.fujii.wj@renesas.com> -Date: Tue, 16 Oct 2018 14:34:22 +0900 -Subject: [PATCH] Update IPL: patch for DDR setting rev.0.33 - -[IPL] -- Update DDR setting (rev.0.33patch2) 20180926 - -Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> -Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> ---- - plat/renesas/rcar/ddr/ddr_b/boot_init_dram.c | 72 +++++++++++----------- - .../renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h | 2 +- - 2 files changed, 36 insertions(+), 38 deletions(-) - -diff --git a/plat/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/plat/renesas/rcar/ddr/ddr_b/boot_init_dram.c -index 4cee117..aa81968 100644 ---- a/plat/renesas/rcar/ddr/ddr_b/boot_init_dram.c -+++ b/plat/renesas/rcar/ddr/ddr_b/boot_init_dram.c -@@ -275,7 +275,7 @@ static void dbsc_regset_post(void); - static uint32_t dfi_init_start(void); - static void change_lpddr4_en(uint32_t mode); - static uint32_t set_term_code(void); --static void ddr_register_set(uint32_t ch); -+static void ddr_register_set(void); - static inline uint32_t wait_freqchgreq(uint32_t assert); - static inline void set_freqchgack(uint32_t assert); - static inline void set_dfifrequency(uint32_t freq); -@@ -1919,7 +1919,11 @@ static void dbsc_regset(void) - /* WRCSGAP = 5 */ - tmp[1] = 5; - /* RDCSLAT = RDLAT_ADJ +2*/ -- tmp[2] = tmp[3] +2; -+ if(Prr_Product==PRR_PRODUCT_M3){ -+ tmp[2] = tmp[3]; -+ } else { -+ tmp[2] = tmp[3] +2; -+ } - /* RDCSGAP = 6 */ - if(Prr_Product==PRR_PRODUCT_M3) { - tmp[3] = 4; -@@ -2467,36 +2471,34 @@ static uint32_t set_term_code(void) - /******************************************************************************* - * DDR mode register setting - ******************************************************************************/ --static void ddr_register_set(uint32_t ch) -+static void ddr_register_set(void) - { - int32_t fspwp; -- uint32_t chind; - uint32_t tmp; - -- chind = ch<<20; - for(fspwp=1;fspwp>=0;fspwp--){ - /*MR13,fspwp*/ -- send_dbcmd(0x0e040d08|chind|(fspwp<<6)); -+ send_dbcmd(0x0e840d08|(fspwp<<6)); - - tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR1_DATA_Fx_CSx[fspwp][0]); -- send_dbcmd(0x0e040100|chind|tmp); -+ send_dbcmd(0x0e840100|tmp); - - tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR2_DATA_Fx_CSx[fspwp][0]); -- send_dbcmd(0x0e040200|chind|tmp); -+ send_dbcmd(0x0e840200|tmp); - - tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_Fx_CSx[fspwp][0]); -- send_dbcmd(0x0e040300|chind|tmp); -+ send_dbcmd(0x0e840300|tmp); - - tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_Fx_CSx[fspwp][0]); -- send_dbcmd(0x0e040b00|chind|tmp); -+ send_dbcmd(0x0e840b00|tmp); - - tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_Fx_CSx[fspwp][0]); -- send_dbcmd(0x0e040c00|chind|tmp); -+ send_dbcmd(0x0e840c00|tmp); - - tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR14_DATA_Fx_CSx[fspwp][0]); -- send_dbcmd(0x0e040e00|chind|tmp); -+ send_dbcmd(0x0e840e00|tmp); - /* MR22 */ -- send_dbcmd(0x0e041600|chind|0x16); -+ send_dbcmd(0x0e841616); - } - } - -@@ -2690,7 +2692,7 @@ static uint32_t init_ddr(void) - int32_t i; - uint32_t dataL; - uint32_t phytrainingok; -- uint32_t ch; -+ uint32_t ch, slice; - uint32_t err; - - MSG_LF("init_ddr:0\n"); -@@ -2794,6 +2796,9 @@ static uint32_t init_ddr(void) - if(err)return(INITDRAM_ERR_O); - MSG_LF("init_ddr:5\n"); - -+ /* PDX */ -+ send_dbcmd(0x08840001); -+ - /*********************************************************************** - set ie_mode=1 - ***********************************************************************/ -@@ -2818,23 +2823,14 @@ static uint32_t init_ddr(void) - /* CMOS MODE */ - change_lpddr4_en(0); - -- ch=0x08; -- -- /* PDE */ -- send_dbcmd(0x08040000|(0x00100000 * ch)); -- -- /* PDX */ -- send_dbcmd(0x08040001|(0x00100000 * ch)); -- -- /* MR22 (ODTCS & RQZ */ -- send_dbcmd(0x0e041600|(0x00100000 * ch)|0x16); -+ /* MRS */ -+ ddr_register_set(); - - /* ZQCAL start */ -- send_dbcmd(0x0d04004F|(0x00100000 * ch)); -- micro_wait(100); -+ send_dbcmd(0x0d84004F); - - /* ZQLAT */ -- send_dbcmd(0x0d040051|(0x00100000 * ch)); -+ send_dbcmd(0x0d840051); - - /*********************************************************************** - Thermal sensor setting -@@ -2843,12 +2839,6 @@ static uint32_t init_ddr(void) - dataL = ((*((volatile uint32_t*)THS1_THCTR)) & 0xFFFFFFBF) | 0x00000001; - *((volatile uint32_t*)THS1_THCTR) = dataL; - -- /*********************************************************************** -- setup DDR mode registers -- ***********************************************************************/ -- foreach_vch(ch) { -- ddr_register_set(ch); -- } - /* LPDDR4 MODE */ - change_lpddr4_en(1); - -@@ -2868,7 +2858,15 @@ static uint32_t init_ddr(void) - exec pi_training - ***********************************************************************/ - ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); -- ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01); -+ if((Prr_Product==PRR_PRODUCT_H3)&&(Prr_Cut<=PRR_PRODUCT_11)){ -+ ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01); -+ } else { -+ foreach_vch(ch){ -+ for(slice=0;slice<SLICE_CNT;slice++){ -+ ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, ((ch_have_this_cs[1])>>ch) & 0x01); -+ } -+ } -+ } - - phytrainingok = pi_training_go(); - -@@ -3728,11 +3726,11 @@ int32_t InitDram(void) - Thermal sensor setting - ***********************************************************************/ - dataL = *((volatile uint32_t*)CPG_MSTPSR5); -- if(dataL & BIT22){ // case THS/TSC Standby -- dataL &= ~(BIT22); -+ if(dataL & (1<<22)){ // case THS/TSC Standby -+ dataL &= ~(1<<22); - *((volatile uint32_t*)CPG_CPGWPR) = ~dataL; - *((volatile uint32_t*)CPG_SMSTPCR5) = dataL; -- while( (BIT22) & *((volatile uint32_t*)CPG_MSTPSR5) ); // wait bit=0 -+ while((1<<22) & *((volatile uint32_t*)CPG_MSTPSR5)); // wait bit=0 - } - - /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */ -diff --git a/plat/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/plat/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h -index 6170481..d5c03ae 100644 ---- a/plat/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h -+++ b/plat/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h -@@ -4,7 +4,7 @@ - * SPDX-License-Identifier: BSD-3-Clause - */ - --#define RCAR_DDR_VERSION "rev.0.33" -+#define RCAR_DDR_VERSION "rev.0.33patch2" - #define DRAM_CH_CNT 0x04 - #define SLICE_CNT 0x04 - #define CS_CNT 0x02 --- -1.9.1 - diff --git a/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb b/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb index aaba697..096d25d 100644 --- a/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb +++ b/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_git.bb @@ -1,7 +1,7 @@ DESCRIPTION = "ARM Trusted Firmware" LICENSE = "BSD" -LIC_FILES_CHKSUM = "file://license.rst;md5=33065335ea03d977d0569f270b39603e" +LIC_FILES_CHKSUM = "file://license.rst;md5=e927e02bca647e14efd87e9e914b2443" PACKAGE_ARCH = "${MACHINE_ARCH}" @@ -13,14 +13,9 @@ S = "${WORKDIR}/git" BRANCH = "rcar_gen3" SRC_URI = "git://github.com/renesas-rcar/arm-trusted-firmware.git;branch=${BRANCH}" -SRCREV = "d4a607b7ea3886d8d1098192d2c657face631202" +SRCREV = "7f126e2e718a69bec850c87bd05c4c168b32c4df" -# Update DDR Setting -SRC_URI_append = " \ - file://0001-Update-IPL-patch-for-DDR-setting-rev.0.33.patch \ -" - -PV = "v1.4+renesas+git${SRCPV}" +PV = "v1.5+renesas+git${SRCPV}" COMPATIBLE_MACHINE = "(salvator-x|ulcb|ebisu)" PLATFORM = "rcar" diff --git a/meta-rcar-gen3/recipes-bsp/optee/optee-os/0001-OPTEE_PROVIDER-188185-Fix-a-contxt-size-allocated-by.patch b/meta-rcar-gen3/recipes-bsp/optee/optee-os/0001-OPTEE_PROVIDER-188185-Fix-a-contxt-size-allocated-by.patch deleted file mode 100644 index eada5c5..0000000 --- a/meta-rcar-gen3/recipes-bsp/optee/optee-os/0001-OPTEE_PROVIDER-188185-Fix-a-contxt-size-allocated-by.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 88085caf87cf1060c0db269f021efdea617fbef9 Mon Sep 17 00:00:00 2001 -From: Tomohiro Fujiwara <tomohiro.fujiwara.cw@hitachi.com> -Date: Wed, 26 Sep 2018 10:12:02 +0900 -Subject: [PATCH 1/2] [OPTEE_PROVIDER][#188185] Fix a contxt size allocated by - the OP-TEE OS - -This commit adds a compile option for deciding a context size used by -HASH algorithm of SS6.3-Secure Driver. - -Signed-off-by: Tomohiro Fujiwara <tomohiro.fujiwara.cw@hitachi.com> ---- - core/core.mk | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/core/core.mk b/core/core.mk -index c428cd00..405b1e76 100644 ---- a/core/core.mk -+++ b/core/core.mk -@@ -90,6 +90,7 @@ base-prefix := - - ifeq ($(CFG_CRYPT_HW_CRYPTOENGINE),y) - core-platform-cflags += -DENABLE_CRYPTOENGINE -+core-platform-cflags += -DDX_CC_TEE -DCRYS_NO_CRYS_COMBINED_SUPPORT - - ifeq ($(CFG_CRYPT_ENABLE_CEPKA),y) - libname = crypto_engine_pka --- -2.14.1.windows.1 - diff --git a/meta-rcar-gen3/recipes-bsp/optee/optee-os/0001-Update-optee_os-Rev1.0.16-rev2.patch b/meta-rcar-gen3/recipes-bsp/optee/optee-os/0001-Update-optee_os-Rev1.0.16-rev2.patch deleted file mode 100644 index 6265cfc..0000000 --- a/meta-rcar-gen3/recipes-bsp/optee/optee-os/0001-Update-optee_os-Rev1.0.16-rev2.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 35f6b872b7bd4cd0245f4c8b2e4a2cdc86fe8151 Mon Sep 17 00:00:00 2001 -From: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> -Date: Tue, 16 Oct 2018 15:31:31 +0900 -Subject: [PATCH] Update optee_os Rev1.0.16 rev2 - - - Fix to set the initial value for a parameter in TEE_AEInit. - - Fix to clear the read cache of standalone_fs_create. ---- - core/arch/arm/plat-rcar/tee/tee_standalone_fs.c | 4 ++++ - lib/libutee/tee_api_operations.c | 1 + - 2 files changed, 5 insertions(+) - -diff --git a/core/arch/arm/plat-rcar/tee/tee_standalone_fs.c b/core/arch/arm/plat-rcar/tee/tee_standalone_fs.c -index c51b2cd..a475940 100644 ---- a/core/arch/arm/plat-rcar/tee/tee_standalone_fs.c -+++ b/core/arch/arm/plat-rcar/tee/tee_standalone_fs.c -@@ -942,6 +942,10 @@ static void spi_write_record_data(struct spif_record_info *record_info, - } - - record_info->record_head.data_len = dpos; -+ -+ if (g_record_data_rdesc != NULL) { -+ g_record_data_rdesc = NULL; -+ } - } - - static void spi_get_parent_dir(const char *path, size_t path_len, -diff --git a/lib/libutee/tee_api_operations.c b/lib/libutee/tee_api_operations.c -index 2b11fd2..036ec13 100644 ---- a/lib/libutee/tee_api_operations.c -+++ b/lib/libutee/tee_api_operations.c -@@ -1343,6 +1343,7 @@ TEE_Result TEE_AEInit(TEE_OperationHandle operation, const void *nonce, - if (res != TEE_SUCCESS) - goto out; - -+ operation->buffer_offs = 0U; - operation->ae_tag_len = tagLen / 8; - operation->info.handleState |= TEE_HANDLE_FLAG_INITIALIZED; - --- -1.9.1 - diff --git a/meta-rcar-gen3/recipes-bsp/optee/optee-os/0001-plat-rcar-fix-MMU-configuration-of-shared-memory.patch b/meta-rcar-gen3/recipes-bsp/optee/optee-os/0001-plat-rcar-fix-MMU-configuration-of-shared-memory.patch deleted file mode 100644 index f1d0739..0000000 --- a/meta-rcar-gen3/recipes-bsp/optee/optee-os/0001-plat-rcar-fix-MMU-configuration-of-shared-memory.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 67e2c72b2a20c859bc5cb7a2ea91b9bd9732c3a4 Mon Sep 17 00:00:00 2001 -From: Jun Miyauchi <jun.miyauchi.sr@hitachi.com> -Date: Fri, 26 Oct 2018 10:39:08 +0900 -Subject: [PATCH] plat-rcar: fix MMU configuration of shared memory - -Signed-off-by: Jun Miyauchi <jun.miyauchi.sr@hitachi.com> ---- - core/arch/arm/plat-rcar/platform_config.h | 12 +++++------- - 1 file changed, 5 insertions(+), 7 deletions(-) - -diff --git a/core/arch/arm/plat-rcar/platform_config.h b/core/arch/arm/plat-rcar/platform_config.h -index ebc12557..3c8fd8af 100644 ---- a/core/arch/arm/plat-rcar/platform_config.h -+++ b/core/arch/arm/plat-rcar/platform_config.h -@@ -48,11 +48,11 @@ - #define CFG_TA_RAM_SIZE (0x01E00000U) /* TA RAM size */ - - #define CFG_SHMEM_START (0x47E00000U) /* Share Memory address */ --#define CFG_SHMEM_SIZE (0x00200000U) /* Share Memory size */ -- /* plus OP-TEE Log Area NS size(1MB) */ -+#define CFG_SHMEM_SIZE (0x00100000U) /* Share Memory size */ - - #define OPTEE_LOG_BASE (0x46400000U) /* OP-TEE Log Area address */ - #define OPTEE_LOG_NS_BASE (0x47FEC000U) /* OP-TEE Log Area NS address */ -+#define OPTEE_LOG_NS_SIZE (0x00014000U) /* OP-TEE Log Area NS size */ - - #define TA_VERIFICATION_BASE (0x46200000U) /* TA area for verification */ - #define TA_VERIFICATION_SIZE (0x00100000U) /* TA verification size */ -@@ -121,11 +121,9 @@ - #define MEMORY1_EXEC false - - /* LOG Area for Normal World */ --/* Map with CFG_SHMEM_START --#define MEMORY2_BASE ROUNDDOWN(OPTEE_LOG_NS_BASE, MEM_SECTION_SIZE) --*/ --#define MEMORY2_SIZE (MEM_SECTION_SIZE) --#define MEMORY2_TYPE MEM_AREA_IO_NSEC -+#define MEMORY2_BASE (OPTEE_LOG_NS_BASE) -+#define MEMORY2_SIZE (OPTEE_LOG_NS_SIZE) -+#define MEMORY2_TYPE MEM_AREA_RAM_NSEC - #define MEMORY2_SECURE false - #define MEMORY2_CACHED false - #define MEMORY2_DEVICE false --- -2.14.1 - diff --git a/meta-rcar-gen3/recipes-bsp/optee/optee-os/0002-OPTEE_PROVIDER-188122-Fix-to-exclusive-control-for-R.patch b/meta-rcar-gen3/recipes-bsp/optee/optee-os/0002-OPTEE_PROVIDER-188122-Fix-to-exclusive-control-for-R.patch deleted file mode 100644 index bac23ad..0000000 --- a/meta-rcar-gen3/recipes-bsp/optee/optee-os/0002-OPTEE_PROVIDER-188122-Fix-to-exclusive-control-for-R.patch +++ /dev/null @@ -1,105 +0,0 @@ -From f6ba4b6f808158a9daf39bc7224da806a9e3547d Mon Sep 17 00:00:00 2001 -From: Tomohiro Fujiwara <tomohiro.fujiwara.cw@hitachi.com> -Date: Wed, 26 Sep 2018 23:12:17 +0900 -Subject: [PATCH 2/2] [OPTEE_PROVIDER][#188122] Fix to exclusive control for - RSA/ECDSA - -This commit fixes to be exclusive in order to other processes are not -executed between build key process and sign/verify/enc/dec process. - -Signed-off-by: Tomohiro Fujiwara <tomohiro.fujiwara.cw@hitachi.com> ---- - core/lib/libcryptoengine/tee_pka_provider.c | 4 ++++ - core/lib/libcryptoengine/tee_provider_common.h | 1 + - core/lib/libcryptoengine/tee_ss_provider.c | 6 ++++++ - 3 files changed, 11 insertions(+) - -diff --git a/core/lib/libcryptoengine/tee_pka_provider.c b/core/lib/libcryptoengine/tee_pka_provider.c -index 453bc31a..c5df6737 100644 ---- a/core/lib/libcryptoengine/tee_pka_provider.c -+++ b/core/lib/libcryptoengine/tee_pka_provider.c -@@ -20,6 +20,8 @@ static SSError_t pka_get_ecc_keysize(uint32_t curve, - static void userProcessCompletedFunc(CRYSError_t opStatus __unused, - void* pVerifContext __unused); - -+static struct mutex pka_ecdsa_mutex = MUTEX_INITIALIZER; -+ - /* - * brief: Translate CRYS API AES error into SS provider error. - * -@@ -239,6 +241,7 @@ TEE_Result ss_ecc_verify_pka(struct ecc_public_key *key, const uint8_t *msg, - res = pka_get_ecc_digest(messageSizeInBytes, &eccHash); - } - -+ mutex_lock(&pka_ecdsa_mutex); - if (res == SS_SUCCESS) { - /* build public key */ - *publKeyIn_ptr = (uint8_t)CRYS_EC_PointUncompressed; -@@ -274,6 +277,7 @@ TEE_Result ss_ecc_verify_pka(struct ecc_public_key *key, const uint8_t *msg, - res = pka_translate_error_pka2ss_ecc(pka_res); - PROV_DMSG("Result: res=0x%08x\n", res); - } -+ mutex_unlock(&pka_ecdsa_mutex); - - ss_free((void *)publKeyX_ptr); - ss_free((void *)publKeyY_ptr); -diff --git a/core/lib/libcryptoengine/tee_provider_common.h b/core/lib/libcryptoengine/tee_provider_common.h -index 823c7bfa..ed2de568 100644 ---- a/core/lib/libcryptoengine/tee_provider_common.h -+++ b/core/lib/libcryptoengine/tee_provider_common.h -@@ -8,6 +8,7 @@ - - #include <crypto/crypto.h> - #include <tee/tee_cryp_utl.h> -+#include <kernel/mutex.h> - #include <mpalib.h> - #include <stdlib.h> - #include <string.h> -diff --git a/core/lib/libcryptoengine/tee_ss_provider.c b/core/lib/libcryptoengine/tee_ss_provider.c -index 77a12d7c..3e9f93a1 100644 ---- a/core/lib/libcryptoengine/tee_ss_provider.c -+++ b/core/lib/libcryptoengine/tee_ss_provider.c -@@ -282,6 +282,8 @@ static SSError_t ss_crys_aesccm_update(void *ctx, uint8_t *dataIn_ptr, - static void ss_backup_cb(enum suspend_to_ram_state state, uint32_t cpu_id); - static TEE_Result crypto_hw_init_crypto_engine(void); - -+static struct mutex secure_ecdsa_mutex = MUTEX_INITIALIZER; -+ - static SSError_t ss_crys_aes_update(void *ctx, uint8_t *dataIn_ptr, - uint32_t dataInSize, uint8_t *dataOut_ptr, CRYSError_t *crysRes) - { -@@ -3090,6 +3092,7 @@ TEE_Result crypto_hw_acipher_ecc_sign(struct ecc_keypair *key, - res = ss_get_ecc_digest(messageSizeInBytes, &eccHashMode); - } - -+ mutex_lock(&secure_ecdsa_mutex); - if (res == SS_SUCCESS) { - PROV_DMSG("CALL: CRYS_ECPKI_BuildPrivKey()\n"); - crys_res = CRYS_ECPKI_BuildPrivKey(domain_id, privKeySizeIn_ptr, -@@ -3107,6 +3110,7 @@ TEE_Result crypto_hw_acipher_ecc_sign(struct ecc_keypair *key, - res = ss_translate_error_crys2ss_ecc(crys_res); - PROV_DMSG("Result: crys_res=0x%08x -> res=0x%08x\n",crys_res,res); - } -+ mutex_unlock(&secure_ecdsa_mutex); - - ss_free((void *)signUserContext_ptr); - ss_free((void *)privKeySizeIn_ptr); -@@ -3193,6 +3197,7 @@ static SSError_t ss_ecc_verify_secure(struct ecc_public_key *key, - res = ss_get_ecc_digest(messageSizeInBytes, &eccHashMode); - } - -+ mutex_lock(&secure_ecdsa_mutex); - if (res == SS_SUCCESS) { - /* build public key */ - *publKeyIn_ptr = (uint8_t)CRYS_EC_PointUncompressed; -@@ -3217,6 +3222,7 @@ static SSError_t ss_ecc_verify_secure(struct ecc_public_key *key, - PROV_DMSG("Result: crys_res=0x%08x -> res=0x%08x\n", crys_res, - res); - } -+ mutex_unlock(&secure_ecdsa_mutex); - - ss_free((void *)publKeyX_ptr); - ss_free((void *)publKeyY_ptr); --- -2.14.1.windows.1 - diff --git a/meta-rcar-gen3/recipes-bsp/optee/optee-os_git.bb b/meta-rcar-gen3/recipes-bsp/optee/optee-os_git.bb index 7d697fb..293f262 100644 --- a/meta-rcar-gen3/recipes-bsp/optee/optee-os_git.bb +++ b/meta-rcar-gen3/recipes-bsp/optee/optee-os_git.bb @@ -13,7 +13,7 @@ inherit deploy pythonnative PV = "3.1.0+renesas+git${SRCPV}" BRANCH = "rcar_gen3" -SRCREV_renesas = "459c612224e123658a2ad29a91a3d186342d24a9" +SRCREV_renesas = "35f6b872b7bd4cd0245f4c8b2e4a2cdc86fe8151" SRCREV_officialgit = "e77020396508fc086d7a4d6137388b116e4a662f" SRCREV_FORMAT = "renesas_officialgit" @@ -22,14 +22,6 @@ SRC_URI = " \ git://github.com/OP-TEE/optee_os.git;branch=master;name=officialgit;destsuffix=git_official \ " -# Patch for Yv3.9.0.1 -SRC_URI_append = " \ - file://0001-OPTEE_PROVIDER-188185-Fix-a-contxt-size-allocated-by.patch \ - file://0002-OPTEE_PROVIDER-188122-Fix-to-exclusive-control-for-R.patch \ - file://0001-Update-optee_os-Rev1.0.16-rev2.patch \ - file://0001-plat-rcar-fix-MMU-configuration-of-shared-memory.patch \ -" - COMPATIBLE_MACHINE = "(salvator-x|h3ulcb|m3ulcb|ebisu)" PLATFORM = "rcar" |