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This commit updates IPL and Secure Monitor to Rev.2.0.3 for the
following changes:
[IPL]
- Add support for M3 Ver.1.3/3.0
- Add QoS setting for M3 Ver.3.0
- Add DDR setting for M3 Ver.3.0
- Add E3 Ver.1.1 to build option
- Change periodic write DQ training option
- Add new board revision for H3ULCB
- Remove duplicate line in qos.mk
- Change subslot cycle
- Update DDR setting rev.0.35
- BL2/BL31: Update IPL and Secure Monitor Rev2.0.3
- BL31: Change to restore timer counter value at resume
- BL31: Add DBSC4 setting before self-refresh mode
[Secure Monitor]
- Add SiP for getting board ID
- Change Suspend To RAM function for M3 Ver.3.0
- Change condition of product code with cluster off function
Change-Id: I9eb8e11e679742cf315089670dee1ae90954fc43
Signed-off-by: Duy Dang <duy.dang.yw@renesas.com>
Signed-off-by: Khang Nguyen <khang.nguyen.xw@renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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This commit updates SRCREV of IPL and Secure Monitor to Rev2.0.0
for these changes:
[IPL]
- Update DDR setting for E3(rev0.11).
- Change the condition of data transfer end of SCIF transfer.
- Modify address area in the DDR memory config log output.
- Update H3 Ver.3.0 QoS setting rev.0.09.
- Update E3 Ver.1.0 QoS setting rev.0.04.
- Update H3 Ver.2.0 QoS setting rev.0.20.
- Update H3 Ver.3.0 QoS setting rev.0.10.
- Update M3 Ver.1.1 QoS setting rev.0.18.
- Update M3N Ver.1.1 QoS setting rev.0.08.
- Update E3 Ver.1.0 QoS setting rev.0.05.
- Modify load destination variable of the Cert Header to static.
- [H/W Restriction No.100]:
+ Disable TLB function of IPMMU cache on E3 Ver.1.1.
+ Disable TLB function of IPMMU-PV0 cache on E3 Ver.1.x.
[Secure Monitor]
- Add API for getting DRAM capacity information.
- Change the execution timing of system RAM copy process to BL31
startup.
Signed-off-by: Duy Dang <duy.dang.yw@rvc.renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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This commit provides the capability to generate IPL binaries for
H3/H3ULCB/E3 build variants at the same time.
- For H3 SiP
- *.srec: use for H3 SiP DDR 4GiB (1GiB x 4ch)
- *-4x2g.srec: use for H3 SiP DDR 8GiB (2GiB x 4ch)
- *-2x2g.srec: use for H3 SiP DDR 4GiB (2GiB x 2ch)
- For H3ULCB SiP
- *.srec: use for H3ULCB SiP DDR 4GiB (1GiB x 4ch)
- *-4x2g.srec: use for H3ULCB SiP DDR 8GiB (2GiB x 4ch)
- For E3 SiP
- *.srec: use for E3 SiP DDR 1GiB
- *-4d.srec: use for E3 SiP DDR 2GiB
Signed-off-by: Thuy Tran <thuy.tran.xh@renesas.com>
Signed-off-by: Khang Nguyen <khang.nguyen.xw@renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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This commit updates IPL and Secure Monitor to Rev1.0.23 rev2 for
the following changes:
[IPL]
- plat: rcar: BL2: Correct MMU configuration.
- plat: rcar: Fix suspicious line in platform.mk.
- Change the definition value of BL2_LIMIT to end of System RAM.
- Update IPL boot message.
- Version up the base version to v1.5 of arm-trusted-firmware.
- Update DDR setting (rev.0.34).
- Modify the alignment of l2_tzram_layout to CACHE_WRITEBACK_GRANULE.
- Update H3 Ver.3.0 QoS setting rev.0.08.
- Update M3N Ver.1.1 QoS setting rev.0.07.
- Update E3 Ver.1.0 QoS setting rev.0.03.
- Fix the system WDT detection log is not output when D-Cache is enabled.
- Change the timer counter of micro_wait to the Generic Timer.
- Fix to log the timestamp at beginning of line.
- Change the timer counter for processing time measurement to the Generic Timer.
- Modify the DDR log output of IPL boot message.
[Secure Monitor]
- Version up the base version of arm-trusted-firmware.
https://github.com/ARM-software/arm-trusted-firmware
Commit ID ed8112606c54d85781fc8429160883d6310ece32 [Tag: v1.5]
- Backport the workaround for CVE-2018-3639.
Update optee_os Rev1.0.16 rev2
- Fix a contxt size allocated by OP-TEE OS with HW engine.
- Fix to exclusive control in ECDSA operation used by HW engine.
- Fix to set the initial value for a parameter in TEE_AEInit.
- Fix to clear the read cache of standalone_fs_create.
Signed-off-by: Khang Nguyen <khang.nguyen.xw@renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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The new version of arm-trusted-firmware sets the default build
for Ebisu 2GB DRAM board which is not supported.
This commit switches the build option back to Ebisu 1GB DRAM.
Signed-off-by: Duy Dang <duy.dang.yw@rvc.renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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This commit applies a patch for updating DDR setting.
Signed-off-by: Duy Dang <duy.dang.yw@rvc.renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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This commit updates IPL/Secure Monitor for the following changes:
Update IPL and Secure Monitor Rev1.0.22
[IPL]
- Update CPG setting.
- Add support Ebisu-4D board.
- Change the timing to invalidate of instruction cache.
- Fixed a bug in the exception handler.
- Update DDR setting for E3.
[Secure Monitor]
- Add the wait processing that is placed in the system RAM area for
Suspend To RAM.
Update optee_os Rev1.0.15
- Fix the polling process of the HyperFlash driver waiting for HW
completion.
- Fix incorrect memory access in RSA processing using a provider for
a HW engine driver.
- Fix a conditional branch in a mutex_destroy function.
Signed-off-by: Khang Nguyen <khang.nguyen.xw@renesas.com>
Signed-off-by: Duy Dang <duy.dang.yw@rvc.renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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This commit changes the following contents:
- Upgrade IPL and Secure Monitor Rev1.0.21 rev2.
- Upgrade optee_os Rev1.0.14 rev2.
Signed-off-by: Khang Nguyen <khang.nguyen.xv@rvc.renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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This commit updates IPL and Secure Monitor to Rev1.0.20 rev2 for
following changes:
[IPL]
- [H/W Restriction No.100] Disable TLB function on IPMMU-PV1 cache on
H3 Ver.2.0.
- Update H3 Ver.3.0 QoS setting rev.0.06.
- Fix the IPL cannot load images to 40-bit address space with eMMC when
D-Cache enables.
- Add processing to read MSTP status into BL2.
- Delete unnecessary register setting.
- Add the SWTCNT setting of E3.
- Change the unit of transfer size to 256 bytes for RPC, and improved
DMA transfer processing.
- Add DDR Memory Config log.
[Secure Monitor]
- Add processing to read MSTP status into BL31.
For optee_os, it updates reversion to Rev1.0.13 for following change:
- Add processing to read MSTP status into MFIS.
It deletes the option which enables Lossy area for E3.
It also supports build option for H3:
- For R-Car H3 SiP DDR 8GiB (2GiB x 4ch), specify "RCAR_DRAM_SPLIT=1"
- For R-Car H3 SiP DDR 4GiB (2GiB X 2ch), specify "RCAR_DRAM_SPLIT=2
RCAR_DRAM_CHANNEL=5"
- For R-Car H3 SiP DDR 4GiB (1GiB x 4ch), specify "RCAR_DRAM_SPLIT=1
RCAR_DRAM_LPDDR4_MEMCONF=0"
Signed-off-by: Khang Nguyen <khang.nguyen.xv@rvc.renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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This commit updates IPL and Secure Monitor to Rev1.0.19 rev2 for
following changes:
[IPL]
- Add processing of Suspend To RAM for E3.
- Update DDR setting for E3(rev0.06).
- Update E3 Ver1.0 QoS setting rev.0.02.
- Update M3N Ver.1.0 QoS setting rev.0.06.
- Fix the LSI_CUT judgement of PFC setting.
- Change definition of end address of system ram for BL2.
[Secure Monitor]
- Fix the primary CPU decision function that runs at startup.
- Change the SelfRefresh sequence of Suspend To RAM.
- Add the DVFS SCL setting of E3.
Signed-off-by: Khang Nguyen <khang.nguyen.xv@rvc.renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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This commit changes following contents:
- Update IPL and Secure Monitor Rev1.0.19.
- Update optee_os Rev1.0.12.
It also updates recipes to add support E3 board.
Signed-off-by: Khang Nguyen <khang.nguyen.xv@rvc.renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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This commit changes following contents:
- Update IPL and Secure Monitor Rev1.0.18 rev2
- Update optee_os Rev1.0.11 rev2
Signed-off-by: Thuy Tran <thuy.tran.xh@rvc.renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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This commit updates IPL components versions as below:
- Update IPL and Secure Monitor Rev1.0.17 rev2.
- Update optee_os Rev1.0.10.
Signed-off-by: Thuy Tran <thuy.tran.xh@rvc.renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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This commit updates IPL components versions as below:
- Update IPL and Secure Monitor Rev1.0.16 rev4.
- Update optee_os to Rev1.0.9 rev2.
- Update optee_linuxdriver to Rev1.0.7 rev2.
Signed-off-by: Thao Nguyen <thao.nguyen.yb@renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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This commit updates IPL and Secure Monitor to Rev1.0.15 rev3.
Signed-off-by: Thao Nguyen <thao.nguyen.yb@renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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The operation mode of the PMIC for Salvator-X and ULCB are different:
- ULCB : PULSE MODE (PMIC_LEVEL_MODE=0)
- Salvator-X : LEVEL MODE (PMIC_LEVEL_MODE=1(default))
This commit updates arm-trusted-firmware recipe to check
PMIC_LEVEL_MODE option and to control the corresponding PMIC.
Change-Id: I152c1286d525000f58c678ec37eb6aac9502ac45
Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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This commit changes following contents:
- Update IPL and Secure Monitor Rev1.0.14 rev2.
- Update optee_os Rev1.0.8.
Change-Id: Ibc16e31545b762451eb3704f817cd0d53fc1a50d
Signed-off-by: Thao Nguyen <thao.nguyen.yb@rvc.renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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This commit is to add judge state for ULCB.
If machine is ulcb, "RCAR_GEN3_ULCB=1" will be added to compile option.
Change-Id: Ia05f33a4362c4a7a302c8c0fc5785415f27b15b5
Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Thao Nguyen <thao.nguyen.yb@rvc.renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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This commit changes following contents:
- Update IPL and Secure Monitor Rev1.0.13 rev2.
- Update optee_os Rev1.0.7 rev2.
Change-Id: I0feeaad39dc13c79b7a2f2b8faaac4955413dcff
Signed-off-by: Thao Nguyen <thao.nguyen.yb@rvc.renesas.com>
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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Renesas BSP v3.5.1 (kernel v4.9 stable)
[Environment]
poky: yocto-2.1.2 (cca8dd15c8096626052f6d8d25ff1e9a606104a3)
meta-openembedded: 55c8a76da5dc099a7bc3838495c672140cedb78e
meta-linaro: 2f51d38048599d9878f149d6d15539fb97603f8f
[Information]
- U-boot: Changed load address from H'49000000 to H'50000000
- XDG_RUNTIME_DIR has been changed from "/run/user/root" to "/run/user/0"
- Change location of include directory, which stores common user header
files, to $(INCSHARED)
- In BSP Only, core-image-weston is not supported even though
local-wayland.conf is provided.
- Please set Salvator-x SW7 Pin-1. In after Yocto BSP v2.12.0, it is
　necessary to enable BKUP_TRG signal for Suspend to RAM.
- The dtb filename was changed in R-Car H3. Only
"Image-r8a7795-es1-salvator-x.dtb" is supported in this version.
Please use "Image-r8a7795-es1-salvator-x.dtb" It supports R-Car H3
WS1.0 and WS1.1.
- Please update your local.conf and bblayers.conf corresponding to Yocto
v2.16.0 package. You can refer to meta-rcargen3/docs/sample/conf/ for
updated contents.
- You have to re-compile out-of-recipe software like user application by
v2.16.0 SDK toolchains.
- In some boards, the resuming from System Suspend to RAM may cause
unstable operation or failed to resume.
Signed-off-by: Takamitsu Honda <takamitsu.honda.pv@renesas.com>
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Duy Dang
Thuy Tran
Khang Nguyen
Khang Nguyen
Thuy Tran
Thao Nguyen
Yusuke Goda
Thao Nguyen
Takamitsu Honda