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From 238ab2a2f90819ef4a050b8d2a8f1b1359e2a28a Mon Sep 17 00:00:00 2001
From: Yusuke Goda <yusuke.goda.sx@renesas.com>
Date: Thu, 11 May 2017 19:46:18 +0900
Subject: [PATCH] board: ulcb: Fix reset command clock setting
Reset command uses the power control of the PMIC via CPLD.
CPLD is connected by GPIO2 and GPIO6, so GPIO2 and GPIO6
clock need to be supplied.
Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
---
board/renesas/ulcb/cpld.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/board/renesas/ulcb/cpld.c b/board/renesas/ulcb/cpld.c
index abc7c84..66922d7 100644
--- a/board/renesas/ulcb/cpld.c
+++ b/board/renesas/ulcb/cpld.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <asm/arch/prr_depend.h>
+#include <asm/arch/rcar-mstp.h>
#include <asm/io.h>
#include <asm/gpio.h>
@@ -24,6 +25,9 @@
#define MISO GPIO_GP_6_10
#endif
+#define GP2_MSTP910 (1 << 10)
+#define GP6_MSTP906 (1 << 6)
+
#define CPLD_ADDR_MODE 0x00 /* RW */
#define CPLD_ADDR_MUX 0x02 /* RW */
#define CPLD_ADDR_DIPSW6 0x08 /* R */
@@ -103,6 +107,9 @@ static void cpld_init(void)
val |= PUEN_SSI_SDATA4;
writel(val, PFC_PUEN5);
+ /* GPIO2, GPIO6 for reset */
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, GP6_MSTP906 | GP2_MSTP910);
+
gpio_request(SCLK, NULL);
gpio_request(SSTBZ, NULL);
gpio_request(MOSI, NULL);
--
1.9.1
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