path: root/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0017-board-renesas-Add-V3MSK-board.patch

From 2e9bb759bda6ce52a446c2b7f7d79d51140c4316 Mon Sep 17 00:00:00 2001
From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Date: Fri, 17 Nov 2017 13:01:38 +0300
Subject: [PATCH] board: renesas: Add V3M Starter Kit board

V3M Starter Kit is a board based on R-Car V3M SoC (R8A7797)

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
 arch/arm/cpu/armv8/Kconfig      |   4 +
 board/renesas/v3msk/Kconfig     |  15 +++
 board/renesas/v3msk/MAINTAINERS |   6 ++
 board/renesas/v3msk/Makefile    |   9 ++
 board/renesas/v3msk/cpld.c      | 164 ++++++++++++++++++++++++++++++++
 board/renesas/v3msk/mdio_bb.h   | 156 ++++++++++++++++++++++++++++++
 board/renesas/v3msk/v3msk.c     | 204 ++++++++++++++++++++++++++++++++++++++++
 configs/v3msk_defconfig         |   9 ++
 include/configs/v3msk.h         | 133 ++++++++++++++++++++++++++
 9 files changed, 700 insertions(+)
 create mode 100644 board/renesas/v3msk/Kconfig
 create mode 100644 board/renesas/v3msk/MAINTAINERS
 create mode 100644 board/renesas/v3msk/Makefile
 create mode 100644 board/renesas/v3msk/cpld.c
 create mode 100644 board/renesas/v3msk/mdio_bb.h
 create mode 100644 board/renesas/v3msk/v3msk.c
 create mode 100644 configs/v3msk_defconfig
 create mode 100644 include/configs/v3msk.h

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index c857214..343b121 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -19,6 +19,9 @@ config TARGET_ULCB
 config TARGET_EAGLE
         bool "EAGLE board"
 
+config TARGET_V3MSK
+        bool "V3MSK board"
+
 endchoice
 
 config R8A7796X
@@ -49,5 +52,6 @@ config SYS_SOC
 source "board/renesas/salvator-x/Kconfig"
 source "board/renesas/ulcb/Kconfig"
 source "board/renesas/eagle/Kconfig"
+source "board/renesas/v3msk/Kconfig"
 
 endif
diff --git a/board/renesas/v3msk/Kconfig b/board/renesas/v3msk/Kconfig
new file mode 100644
index 0000000..dafbaef
--- /dev/null
+++ b/board/renesas/v3msk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_V3MSK
+
+config SYS_SOC
+	default "rcar_gen3"
+
+config SYS_BOARD
+	default "v3msk"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "v3msk" if R8A7797
+
+endif
diff --git a/board/renesas/v3msk/MAINTAINERS b/board/renesas/v3msk/MAINTAINERS
new file mode 100644
index 0000000..c39eb76
--- /dev/null
+++ b/board/renesas/v3msk/MAINTAINERS
@@ -0,0 +1,6 @@
+V3MSK BOARD
+M:	Cogent Embedded, Inc. <source@cogentembedded.com>
+S:	Maintained
+F:	board/renesas/v3msk/
+F:	include/configs/v3msk.h
+F:	configs/v3msk_defconfig
diff --git a/board/renesas/v3msk/Makefile b/board/renesas/v3msk/Makefile
new file mode 100644
index 0000000..1f2ea42
--- /dev/null
+++ b/board/renesas/v3msk/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/v3msk/Makefile
+#
+# Copyright (C) 2017 Cogent Embedded, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y	:= v3msk.o ../rcar-gen3-common/common.o cpld.o
diff --git a/board/renesas/v3msk/cpld.c b/board/renesas/v3msk/cpld.c
new file mode 100644
index 0000000..ffb0637
--- /dev/null
+++ b/board/renesas/v3msk/cpld.c
@@ -0,0 +1,172 @@
+/*
+ * V3MSK board CPLD access support
+ *
+ * Copyright (C) 2017 Renesas Electronics Corporation
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/prr_depend.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#define ENABLEZ			GPIO_GP_1_19
+#define MDC			GPIO_GP_1_21
+#define MOSI			GPIO_GP_1_22
+#define MISO			GPIO_GP_1_23
+
+#define ADDR_PRODUCT_L		0x000 /* R */
+#define ADDR_PRODUCT_H		0x001 /* R */
+#define ADDR_CPLD_VERSION_D	0x002 /* R */
+#define ADDR_CPLD_VERSION_Y	0x003 /* R */
+#define ADDR_MODE_SET_L		0x004 /* R/W */
+#define ADDR_MODE_SET_H		0x005 /* R/W */
+#define ADDR_MODE_APPLIED_L	0x006 /* R */
+#define ADDR_MODE_APPLIED_H	0x007 /* R */
+#define ADDR_DIPSW		0x008 /* R */
+#define ADDR_RESET		0x00A /* R/W */
+#define ADDR_POWER_CFG		0x00B /* R/W */
+#define ADDR_PERI_CFG1		0x00C /* R/W */
+#define ADDR_PERI_CFG2		0x00D /* R/W */
+#define ADDR_LEDS		0x00E /* R/W */
+#define ADDR_PCB_VERSION	0x300 /* R */
+#define ADDR_SOC_VERSION	0x301 /* R */
+#define ADDR_PCB_SN_L		0x302 /* R */
+#define ADDR_PCB_SN_H		0x303 /* R */
+
+/* LSI pin pull-up control */
+#define PFC_PUEN2		0xe6060408
+#define PUEN_CANFD1_TX		(1 << 29)
+
+#define GP0_MSTP912		(1 << 12)
+#define GP1_MSTP911		(1 << 11)
+
+#define MDIO_DELAY		10 /* microseconds */
+
+#define mdio_bb_active_mdio()	gpio_direction_output(MOSI, 0)
+#define mdio_bb_tristate_mdio()	gpio_direction_input(MOSI)
+#define mdio_bb_set_mdio(val)	gpio_set_value(MOSI, val)
+#define mdio_bb_get_mdio()	gpio_get_value(MISO)
+#define mdio_bb_set_mdc(val)	gpio_set_value(MDC, val)
+
+#include "mdio_bb.h"
+
+static int cpld_initialized;
+
+static u16 cpld_read(u16 addr)
+{
+	/* random flash reads require 2 reads: first read is unreliable */
+	if (addr >= ADDR_PCB_VERSION)
+		mdio_bb_read(addr >> 5, addr & 0x1f);
+
+	return mdio_bb_read(addr >> 5, addr & 0x1f);
+}
+
+static void cpld_write(u16 addr, u16 data)
+{
+	mdio_bb_write(addr >> 5, addr & 0x1f, data);
+}
+
+static void cpld_init(void)
+{
+	if (cpld_initialized)
+		return;
+
+	cpld_initialized = 1;
+#if 0
+	/* PULL-UP on MISO line (should be pulled up after POR on V3M) */
+	writel(readl(PFC_PUEN2) | PUEN_CANFD1_TX, PFC_PUEN2);
+#endif
+	/* GPIO0 and GPIO1 */
+	mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, GP0_MSTP912 | GP1_MSTP911);
+
+	gpio_request(MDC, NULL);
+	gpio_request(ENABLEZ, NULL);
+	gpio_request(MOSI, NULL);
+	gpio_request(MISO, NULL);
+
+	gpio_direction_output(MDC, 0);
+	gpio_direction_output(ENABLEZ, 0);
+	gpio_direction_output(MOSI, 0);
+	gpio_direction_input(MISO);
+
+	/* V3MSK Videobox Mini board has CANFD PHY connected
+	 * we must shutdown this chip to use bb pins
+	 */
+	gpio_request(GPIO_GP_0_12, NULL);
+	gpio_request(GPIO_GP_0_14, NULL);
+	gpio_direction_output(GPIO_GP_0_12, 1);
+	gpio_direction_output(GPIO_GP_0_14, 1);
+}
+
+static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u16 addr, val;
+
+	cpld_init();
+
+	if (argc == 2 && strcmp(argv[1], "info") == 0) {
+		printf("Product:                0x%08x\n",
+		       (cpld_read(ADDR_PRODUCT_H) << 16) |
+			cpld_read(ADDR_PRODUCT_L));
+		printf("CPLD version:           0x%08x\n",
+		       (cpld_read(ADDR_CPLD_VERSION_Y) << 16) |
+			cpld_read(ADDR_CPLD_VERSION_D));
+		printf("Mode setting (MD0..26): 0x%08x\n",
+		       (cpld_read(ADDR_MODE_APPLIED_H) << 16) |
+			cpld_read(ADDR_MODE_APPLIED_L));
+		printf("DIPSW (SW4, SW5):       0x%02x, 0x%x\n",
+			(cpld_read(ADDR_DIPSW) & 0xff) ^ 0xff,
+			(cpld_read(ADDR_DIPSW) >> 8) ^ 0xf);
+		printf("Power config:           0x%08x\n",
+			cpld_read(ADDR_POWER_CFG));
+		printf("Periferals config:      0x%08x\n",
+		       (cpld_read(ADDR_PERI_CFG2) << 16) |
+			cpld_read(ADDR_PERI_CFG1));
+		printf("PCB version:            %d.%d\n",
+			cpld_read(ADDR_PCB_VERSION) >> 8,
+			cpld_read(ADDR_PCB_VERSION) & 0xff);
+		printf("SOC version:            %d.%d\n",
+			cpld_read(ADDR_SOC_VERSION) >> 8,
+			cpld_read(ADDR_SOC_VERSION) & 0xff);
+		printf("PCB S/N:                %d\n",
+		       (cpld_read(ADDR_PCB_SN_H) << 16 ) |
+			cpld_read(ADDR_PCB_SN_L));
+		return 0;
+	}
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+	if (!(addr >= ADDR_PRODUCT_L && addr <= ADDR_LEDS)) {
+		printf("cpld invalid addr\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (argc == 3 && strcmp(argv[1], "read") == 0) {
+		printf("0x%x\n", cpld_read(addr));
+	} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
+		val = simple_strtoul(argv[3], NULL, 16);
+		cpld_write(addr, val);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	cpld, 4, 1, do_cpld,
+	"CPLD access",
+	"info\n"
+	"cpld read addr\n"
+	"cpld write addr val\n"
+);
+
+void reset_cpu(ulong addr)
+{
+	cpld_init();
+	cpld_write(ADDR_RESET, 1);
+}
diff --git a/board/renesas/v3msk/mdio_bb.h b/board/renesas/v3msk/mdio_bb.h
new file mode 100644
index 0000000..0311006
--- /dev/null
+++ b/board/renesas/v3msk/mdio_bb.h
@@ -0,0 +1,156 @@
+/*
+ * Bit-banged MDIO interface
+ *
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *   based on drivers/net/phy/miiphybb.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+static void mdio_bb_delay(void)
+{
+	udelay(MDIO_DELAY);
+}
+
+/* Send the preamble, address, and register (common to read and write) */
+static void mdio_bb_pre(u8 op, u8 addr, u8 reg)
+{
+	int i;
+
+	/* 32-bit preamble */
+	mdio_bb_active_mdio();
+	mdio_bb_set_mdio(1);
+	for (i = 0; i < 32; i++) {
+		mdio_bb_set_mdc(0);
+		mdio_bb_delay();
+		mdio_bb_set_mdc(1);
+		mdio_bb_delay();
+	}
+	/* send the ST (2-bits of '01') */
+	mdio_bb_set_mdio(0);
+	mdio_bb_set_mdc(0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(1);
+	mdio_bb_delay();
+	mdio_bb_set_mdio(1);
+	mdio_bb_set_mdc(0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(1);
+	mdio_bb_delay();
+	/* send the OP (2-bits of Opcode: '10'-read, '01'-write) */
+	mdio_bb_set_mdio(op >> 1);
+	mdio_bb_set_mdc(0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(1);
+	mdio_bb_delay();
+	mdio_bb_set_mdio(op & 1);
+	mdio_bb_set_mdc(0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(1);
+	mdio_bb_delay();
+	/* send the PA5 (5-bits of PHY address) */
+	for (i = 0; i < 5; i++) {
+		mdio_bb_set_mdio(addr & 0x10); /* MSB first */
+		mdio_bb_set_mdc(0);
+		mdio_bb_delay();
+		mdio_bb_set_mdc(1);
+		mdio_bb_delay();
+		addr <<= 1;
+	}
+	/* send the RA5 (5-bits of register address) */
+	for (i = 0; i < 5; i++) {
+		mdio_bb_set_mdio(reg & 0x10); /* MSB first */
+		mdio_bb_set_mdc(0);
+		mdio_bb_delay();
+		mdio_bb_set_mdc(1);
+		mdio_bb_delay();
+		reg <<= 1;
+	}
+}
+
+static int mdio_bb_read(u8 addr, u8 reg)
+{
+	int i;
+	u16 data = 0;
+
+	mdio_bb_pre(2, addr, reg);
+	/* tri-state MDIO */
+	mdio_bb_tristate_mdio();
+	/* read TA (2-bits of turn-around, last bit must be '0') */
+	mdio_bb_set_mdc(0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(1);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(1);
+	mdio_bb_delay();
+	/* check the turnaround bit: the PHY should drive line to zero */
+	if (mdio_bb_get_mdio() != 0) {
+		printf ("PHY didn't drive TA low\n");
+		for (i = 0; i < 32; i++) {
+			mdio_bb_set_mdc(0);
+			mdio_bb_delay();
+			mdio_bb_set_mdc(1);
+			mdio_bb_delay();
+		}
+		/* There is no PHY, set value to 0xFFFF */
+		return 0xFFFF;
+	}
+	mdio_bb_set_mdc(0);
+	mdio_bb_delay();
+	/* read 16-bits of data */
+	for (i = 0; i < 16; i++) {
+		mdio_bb_set_mdc(1);
+		mdio_bb_delay();
+		data <<= 1;
+		data |= mdio_bb_get_mdio();
+		mdio_bb_set_mdc(0);
+		mdio_bb_delay();
+	}
+
+	mdio_bb_set_mdc(1);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(1);
+	mdio_bb_delay();
+#ifdef DEBUG
+	printf("cpld_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, data);
+#endif
+	return data;
+}
+
+static void mdio_bb_write(u8 addr, u8 reg, u16 val)
+{
+	int i;
+
+	mdio_bb_pre(1, addr, reg);
+	/* send the TA (2-bits of turn-around '10') */
+	mdio_bb_set_mdio(1);
+	mdio_bb_set_mdc(0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(1);
+	mdio_bb_delay();
+	mdio_bb_set_mdio(0);
+	mdio_bb_set_mdc(0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(1);
+	mdio_bb_delay();
+	/* write 16-bits of data */
+	for (i = 0; i < 16; i++) {
+		mdio_bb_set_mdio(val & 0x8000); /* MSB first */
+		mdio_bb_set_mdc(0);
+		mdio_bb_delay();
+		mdio_bb_set_mdc(1);
+		mdio_bb_delay();
+		val <<= 1;
+	}
+	/* tri-state MDIO */
+	mdio_bb_tristate_mdio();
+	mdio_bb_set_mdc(0);
+	mdio_bb_delay();
+	mdio_bb_set_mdc(1);
+	mdio_bb_delay();
+}
diff --git a/board/renesas/v3msk/v3msk.c b/board/renesas/v3msk/v3msk.c
new file mode 100644
index 0000000..4e4ee1f
--- /dev/null
+++ b/board/renesas/v3msk/v3msk.c
@@ -0,0 +1,203 @@
+/*
+ * board/renesas/v3msk/v3msk.c
+ *     This is V3MSK board support.
+ *
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/prr_depend.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rcar_gen3.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SCIF0_MSTP207	(1 << 7)
+#define ETHERAVB_MSTP812	(1 << 12)
+#define RPC_MSTP917	(1 << 17)
+#define SD0_MSTP314	(1 << 14)
+
+#define SD0CKCR		0xE6150074
+
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+}
+
+int board_early_init_f(void)
+{
+	int freq;
+
+	rcar_prr_init();
+
+	writel(0xa5a5ffff, 0xe6150900);
+	writel(0x5a5a0000, 0xe6150904);
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, 0x02000000);
+	/* SCIF0 */
+	mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIF0_MSTP207);
+	/* SDHI2/MMC */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
+	/* EHTERAVB */
+	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
+	/* QSPI/RPC */
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, RPC_MSTP917);
+
+	freq = rcar_get_sdhi_config_clk();
+	writel(freq, SD0CKCR);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	/* Init PFC controller */
+	pinmux_init();
+#ifdef CONFIG_RAVB
+	/* GPSR1 */
+	gpio_request(GPIO_GFN_AVB0_AVTP_CAPTURE, NULL);
+	gpio_request(GPIO_FN_AVB0_AVTP_MATCH, NULL);
+	gpio_request(GPIO_FN_AVB0_LINK, NULL);
+	gpio_request(GPIO_FN_AVB0_PHY_INT, NULL);
+	/* gpio_request(GPIO_FN_AVB0_MAGIC, NULL); */
+	gpio_request(GPIO_FN_AVB0_MDC, NULL);
+	gpio_request(GPIO_FN_AVB0_MDIO, NULL);
+	gpio_request(GPIO_FN_AVB0_TXCREFCLK, NULL);
+	gpio_request(GPIO_FN_AVB0_TD3, NULL);
+	gpio_request(GPIO_FN_AVB0_TD2, NULL);
+	gpio_request(GPIO_FN_AVB0_TD1, NULL);
+	gpio_request(GPIO_FN_AVB0_TD0, NULL);
+	gpio_request(GPIO_FN_AVB0_TXC, NULL);
+	gpio_request(GPIO_FN_AVB0_TX_CTL, NULL);
+	gpio_request(GPIO_FN_AVB0_RD3, NULL);
+	gpio_request(GPIO_FN_AVB0_RD2, NULL);
+	gpio_request(GPIO_FN_AVB0_RD1, NULL);
+	gpio_request(GPIO_FN_AVB0_RD0, NULL);
+	gpio_request(GPIO_FN_AVB0_RXC, NULL);
+	gpio_request(GPIO_FN_AVB0_RX_CTL, NULL);
+	/* IPSR7 */
+	gpio_request(GPIO_IFN_AVB0_AVTP_CAPTURE, NULL);
+	/* IPSR3 */
+	gpio_request(GPIO_FN_AVB0_AVTP_PPS, NULL);
+#endif
+	/* QSPI/RPC */
+	gpio_request(GPIO_FN_QSPI0_SPCLK, NULL);
+	gpio_request(GPIO_FN_QSPI0_MOSI_IO0, NULL);
+	gpio_request(GPIO_FN_QSPI0_MISO_IO1, NULL);
+	gpio_request(GPIO_FN_QSPI0_IO2, NULL);
+	gpio_request(GPIO_FN_QSPI0_IO3, NULL);
+	gpio_request(GPIO_FN_QSPI0_SSL, NULL);
+	gpio_request(GPIO_FN_QSPI1_SPCLK, NULL);
+	gpio_request(GPIO_FN_QSPI1_MOSI_IO0, NULL);
+	gpio_request(GPIO_FN_QSPI1_MISO_IO1, NULL);
+	gpio_request(GPIO_FN_QSPI1_IO2, NULL);
+	gpio_request(GPIO_FN_QSPI1_IO3, NULL);
+	gpio_request(GPIO_FN_QSPI1_SSL, NULL);
+	gpio_request(GPIO_FN_RPC_RESET_N, NULL);
+	gpio_request(GPIO_FN_RPC_WP_N, NULL);
+	gpio_request(GPIO_FN_RPC_INT_N, NULL);
+
+	return 0;
+}
+
+#define MAHR 0xE68005C0
+#define MALR 0xE68005C8
+int board_eth_init(bd_t *bis)
+{
+	int ret = -ENODEV;
+	u32 val;
+	unsigned char enetaddr[6];
+
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		return ret;
+
+	/* Set Mac address */
+	val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+	    enetaddr[2] << 8 | enetaddr[3];
+	writel(val, MAHR);
+
+	val = enetaddr[4] << 8 | enetaddr[5];
+	writel(val, MALR);
+#ifdef CONFIG_RAVB
+	ret = ravb_initialize(bis);
+#endif
+	return ret;
+}
+
+/* V3MSK has KSZ9031RNX */
+int board_phy_config(struct phy_device *phydev)
+{
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret = -ENODEV;
+#ifdef CONFIG_SH_SDHI
+	/* SDHI2/eMMC */
+	gpio_request(GPIO_FN_MMC_D0, NULL);
+	gpio_request(GPIO_FN_MMC_D1, NULL);
+	gpio_request(GPIO_FN_MMC_D2, NULL);
+	gpio_request(GPIO_FN_MMC_D3, NULL);
+	gpio_request(GPIO_FN_MMC_D4, NULL);
+	gpio_request(GPIO_FN_MMC_D5, NULL);
+	gpio_request(GPIO_FN_MMC_D6, NULL);
+	gpio_request(GPIO_FN_MMC_D7, NULL);
+	gpio_request(GPIO_FN_MMC_CLK, NULL);
+	gpio_request(GPIO_FN_MMC_CMD, NULL);
+	gpio_request(GPIO_FN_MMC_CD, NULL);
+	gpio_request(GPIO_FN_MMC_WP, NULL);
+
+	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 0,
+			   SH_SDHI_QUIRK_64BIT_BUF);
+#endif
+	return ret;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+const struct rcar_sysinfo sysinfo = {
+	CONFIG_RCAR_BOARD_STRING
+};
+
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+int checkboard(void)
+{
+	printf("Board: %s\n", sysinfo.board_string);
+	return 0;
+}
+#endif
diff --git a/configs/v3msk_defconfig b/configs/v3msk_defconfig
new file mode 100644
index 0000000..d32840c
--- /dev/null
+++ b/configs/v3msk_defconfig
@@ -0,0 +1,9 @@
+CONFIG_ARM=y
+CONFIG_RCAR_GEN3=y
+CONFIG_DM_SERIAL=y
+CONFIG_TARGET_V3MSK=y
+CONFIG_R8A7797=y
+CONFIG_SPL=y
+CONFIG_SH_SDHI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
diff --git a/include/configs/v3msk.h b/include/configs/v3msk.h
new file mode 100644
index 0000000..225d462
--- /dev/null
+++ b/include/configs/v3msk.h
@@ -0,0 +1,133 @@
+/*
+ * include/configs/v3msk.h
+ *     This file is V3MSK board configuration.
+ *     CPU r8a7797.
+ *
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __V3MSK_H
+#define __V3MSK_H
+
+#undef DEBUG
+#define CONFIG_RCAR_BOARD_STRING "V3MSK"
+#define CONFIG_RCAR_TARGET_STRING "r8a7797"
+
+#include "rcar-gen3-common.h"
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF0
+#define CONFIG_SH_SCIF_CLK_FREQ	CONFIG_S3D4_CLK_FREQ
+
+/* [A] Hyper Flash */
+/* use to RPC(SPI Multi I/O Bus Controller) */
+
+	/* underconstruction */
+
+#define CONFIG_SYS_NO_FLASH
+#if defined(CONFIG_SYS_NO_FLASH)
+#define CONFIG_SPI
+#define CONFIG_RCAR_GEN3_QSPI
+#define CONFIG_SH_QSPI_BASE	0xEE200000
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#else
+#undef CONFIG_CMD_SF
+#undef CONFIG_CMD_SPI
+#undef CONFIG_SPI_FLASH
+#undef CONFIG_SPI_FLASH_SPANSION
+#endif
+
+/* Ethernet RAVB */
+#define CONFIG_RAVB
+#define CONFIG_RAVB_PHY_ADDR	0x0
+#define CONFIG_RAVB_PHY_MODE	PHY_INTERFACE_MODE_RGMII_ID
+#define CONFIG_NET_MULTI
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_BITBANG
+
+/* Board Clock */
+/* XTAL_CLK : 33.33MHz */
+#define RCAR_XTAL_CLK		33333333u
+#define CONFIG_SYS_CLK_FREQ	RCAR_XTAL_CLK
+/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
+/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz          */
+#define CONFIG_CP_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2)
+#define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 192 / 2)
+#define CONFIG_S3D2_CLK_FREQ	(266666666u/2)
+#define CONFIG_S3D4_CLK_FREQ	(266666666u/4)
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY	0xFE502A /* 16.66MHz from CPclk */
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE	(0xF1010000)
+#define GICC_BASE	(0xF1020000)
+#define CONFIG_GICV2
+
+/* USB */
+#undef CONFIG_CMD_USB
+
+/* SDHI */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SH_SDHI_FREQ	200000000
+#define CONFIG_SH_SDHI_MMC
+
+/* ENV setting */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+//#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_OFFSET	(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#define CONFIG_SYS_MMC_ENV_PART	2
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+/* Environment in QSPI */
+#define CONFIG_ENV_ADDR		0x700000
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+/* Module clock supply/stop status bits */
+/* MFIS */
+#define CONFIG_SMSTP2_ENA	0x00002000
+/* serial(SCIF0) */
+#define CONFIG_SMSTP3_ENA	0x00000400
+/* INTC-AP, INTC-EX */
+#define CONFIG_SMSTP4_ENA	0x00000180
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_high=0xffffffffffffffff\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"ethact=ravb\0" \
+	"ethaddr=2E:11:22:33:44:55\0"
+
+#define CONFIG_BOOTARGS \
+	"root=/dev/nfs rw ip=dhcp"
+
+#define CONFIG_BOOTCOMMAND \
+	"bootp 0x48080000 Image; tftp 0x48000000 r8a7797-v3msk.dtb; " \
+	"booti 0x48080000 - 0x48000000"
+
+#endif /* __V3MSK_H */
-- 
1.9.1