blob: ecbbfea6c1cb569434ec834f16b6fc355cff4686 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
|
From 4afdb59d00b3cf8c92006b929bd9e48f4f87d6ce Mon Sep 17 00:00:00 2001
From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Date: Thu, 19 May 2016 08:32:56 +0300
Subject: [PATCH] uboot: H3ULCB console on scif1
Set console on SCIF1 port for H3ULCB.
This is only for H3ULCB.HAD
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
include/configs/h3ulcb.h | 4 ++--
board/renesas/ulcb/ulcb.c | 3 +++
2 file changed, 4 insertions(+), 1 deletions(-)
diff --git a/include/configs/h3ulcb.h b/include/configs/h3ulcb.h
index b9be845..3da2e5a 100644
--- a/include/configs/h3ulcb.h
+++ b/include/configs/h3ulcb.h
@@ -23,6 +23,6 @@
/* SCIF */
#define CONFIG_SCIF_CONSOLE
-#define CONFIG_CONS_SCIF2
+#define CONFIG_CONS_SCIF1
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index 0d8752f..1be01cf 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -29,6 +29,7 @@
DECLARE_GLOBAL_DATA_PTR;
+#define SCIF1_MSTP206 (1 << 6)
#define SCIF2_MSTP310 (1 << 10)
#define ETHERAVB_MSTP812 (1 << 12)
#define DVFS_MSTP926 (1 << 26)
@@ -49,6 +50,8 @@ int board_early_init_f(void)
rcar_prr_init();
+ /* SCIF1 */
+ mstp_clrbits_le32(SMSTPCR2, SMSTPCR2, SCIF1_MSTP206);
/* SCIF2 */
mstp_clrbits_le32(SMSTPCR3, SMSTPCR3, SCIF2_MSTP310);
/* EHTERAVB */
--
1.9.1
|
