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blob: f8fb983b9635faf780767e0d101065ae33f171ec (plain)
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From 40240b74fe0b5c851127996328504e86a9fc4407 Mon Sep 17 00:00:00 2001
From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Date: Wed, 4 Jan 2017 10:41:48 +0300
Subject: [PATCH] arm64: dts: r8a7795-es1-h3ulcb-had: add ADAS board

H3ULCB.HAD board on R8A7795 ES1.x SoC

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
---
 arch/arm64/boot/dts/renesas/Makefile               |   1 +
 .../dts/renesas/r8a7795-es1-h3ulcb-had-alfa.dts    |  22 ++
 .../dts/renesas/r8a7795-es1-h3ulcb-had-beta.dts    |  23 +++
 .../boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi   | 224 +++++++++++++++++++++
 4 files changed, 270 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had-alfa.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had-beta.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 43aa35d..51a4ac9 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
 # ADAS boards
 dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x-view.dtb
 dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-view.dtb
+dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-had-alfa.dtb r8a7795-es1-h3ulcb-had-beta.dtb
 
 always		:= $(dtb-y)
 clean-files	:= *.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had-alfa.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had-alfa.dts
new file mode 100644
index 0000000..6b13f07
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had-alfa.dts
@@ -0,0 +1,22 @@
+/*
+ * Device Tree Source for the H3ULCB.HAD board Alfa side on r8a7795 ES1.x
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "r8a7795-es1-h3ulcb-had.dtsi"
+
+/ {
+	model = "Renesas H3ULCB.HAD board Alfa side based on r8a7795";
+};
+
+&pciec0 {
+	status = "okay";
+
+	/* Root complex */
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had-beta.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had-beta.dts
new file mode 100644
index 0000000..2f8b274
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had-beta.dts
@@ -0,0 +1,23 @@
+/*
+ * Device Tree Source for the H3ULCB.HAD board Beta side on r8a7795 ES1.x
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "r8a7795-es1-h3ulcb-had.dtsi"
+
+/ {
+	model = "Renesas H3ULCB.HAD board Beta side based on r8a7795";
+};
+
+&pciec0 {
+	status = "okay";
+
+	/* Endpoint */
+	endpoint;
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi
new file mode 100644
index 0000000..d18ff37
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-had.dtsi
@@ -0,0 +1,224 @@
+/*
+ * Device Tree Source for the H3ULCB.HAD board on r8a7795 ES1.x
+ *
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
+ * Copyright (C) 2016-2017 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/*
+ * MSIOF0 - /dev/spidev1.0 connected to FPGA ethernet switch (both sides)
+ * MSIOF1 - /dev/spidev2.0 connected to RH850 (sideA to CSIH1, sideB to CSIH0)
+ */
+
+#include "r8a7795-es1-h3ulcb-view.dts"
+
+/ {
+	model = "Renesas H3ULCB.HAD board based on r8a7795";
+
+	aliases {
+		spi1 = &spi0_gpio;
+		spi2 = &spi1_gpio;
+	};
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+
+	spi0_gpio: spi_gpio@0 {
+		compatible = "spi-gpio";
+		num-chipselects = <1>;
+		gpio-sck = <&gpio5 17 0>;
+		gpio-mosi = <&gpio5 20 0>;
+		gpio-miso = <&gpio5 22 0>;
+		cs-gpios = <&gpio5 19 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		spidev@0 {
+			compatible = "spi-gpio";
+			reg = <0>;
+			spi-max-frequency = <2000000>;
+			spi-cpha;
+			spi-cpol;
+		};
+	};
+
+	spi1_gpio: spi_gpio@1 {
+		compatible = "spi-gpio";
+		num-chipselects = <1>;
+		gpio-sck = <&gpio6 8 0>;
+		gpio-mosi = <&gpio6 7 0>;
+		gpio-miso = <&gpio6 10 0>;
+		cs-gpios = <&gpio6 5 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		spidev@0 {
+			compatible = "spi-gpio";
+			reg = <0>;
+			spi-max-frequency = <2000000>;
+			spi-cpha;
+			spi-cpol;
+		};
+	};
+
+	hdmi1-out {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi1_con: endpoint {
+				remote-endpoint = <&rcar_dw_hdmi1_out>;
+			};
+		};
+	};
+};
+
+&du {
+	ports {
+		port@1 {
+			endpoint {
+				remote-endpoint = <&rcar_dw_hdmi0_in>;
+			};
+		};
+		port@2 {
+			endpoint {
+				remote-endpoint = <&rcar_dw_hdmi1_in>;
+			};
+		};
+	};
+};
+
+&hdmi1 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+				rcar_dw_hdmi1_in: endpoint {
+				remote-endpoint = <&du_out_hdmi1>;
+			};
+		};
+		port@1 {
+			reg = <1>;
+				rcar_dw_hdmi1_out: endpoint {
+				remote-endpoint = <&hdmi1_con>;
+			};
+		};
+	};
+};
+
+&pfc {
+	scif1_pins: scif1 {
+		groups = "scif1_data_a";
+		function = "scif1";
+	};
+
+	msiof0_pins: spi1 {
+		groups = "msiof0_clk", "msiof0_rxd",  "msiof0_txd",
+			 "msiof0_ss1";
+		function = "msiof0";
+	};
+
+	msiof1_pins: spi2 {
+		groups = "msiof1_clk_a", "msiof1_rxd_a", "msiof1_txd_a",
+			 "msiof1_ss1_a";
+		function = "msiof1";
+	};
+
+	sound_clk_pins: sound-clk {
+		groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
+			 "audio_clkout_a" /*, "audio_clkout3_a"*/;
+		function = "audio_clk";
+	};
+
+	usb31_pins: usb31 {
+		groups = "usb31";
+		function = "usb31";
+	};
+
+	can0_pins: can0 {
+		groups = "can0_data_a";
+		function = "can0";
+	};
+
+	canfd0_pins: canfd0 {
+		groups = "canfd0_data_a";
+		function = "canfd0";
+	};
+};
+
+&scif1 {
+	pinctrl-0 = <&scif1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&avb {
+	/delete-property/phy-handle;
+	/delete-property/phy-gpios;
+	/delete-node/ethernet-phy@0;
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&msiof0 {
+	pinctrl-0 = <&msiof0_pins>;
+	pinctrl-names = "default";
+	status = "disabled";
+	cs-gpios = <&gpio5 19 0>;
+
+	spidev@0 {
+		compatible = "renesas,sh-msiof";
+		reg = <0>;
+		spi-max-frequency = <66666666>;
+		spi-cpha;
+		spi-cpol;
+	};
+};
+
+&msiof1 {
+	status = "disabled";
+	cs-gpios = <&gpio6 5 0>;
+};
+
+&can0 {
+	pinctrl-0 = <&can0_pins>;
+	pinctrl-names = "default";
+	status = "disabled";
+
+	renesas,can-clock-select = <0x0>;
+	gpios = <&gpio2 6 GPIO_ACTIVE_HIGH /* enable - shared with camera board */
+		 &gpio2 7 GPIO_ACTIVE_LOW /* standby */
+		>;
+};
+
+&canfd {
+	pinctrl-0 = <&canfd0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	renesas,can-clock-select = <0x0>;
+	gpios = <&gpio2 6 GPIO_ACTIVE_HIGH /* enable - shared with camera board */
+		 &gpio2 7 GPIO_ACTIVE_LOW /* standby */
+		>;
+
+	channel0 {
+		status = "okay";
+	};
+};
+
+&xhci1 {
+	status = "okay";
+	pinctrl-0 = <&usb31_pins>;
+	pinctrl-names = "default";
+};
-- 
1.9.1