aboutsummaryrefslogtreecommitdiffstats
path: root/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0064-ADV7511-limit-maximum-pixelclock.patch
blob: 3ca92845b214ab4f7ec486691d439a6db8048f69 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
From 1df040dabaec1697f81b71f15739b499f3e4266e Mon Sep 17 00:00:00 2001
From: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
Date: Fri, 9 Jun 2017 20:12:26 +0300
Subject: [PATCH] ADV7511: limit maximum pixelclock

DU0 (RGB) supports clock freq up to 100MHz only.
Add ability to set max clock via dts.

Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
---
 drivers/gpu/drm/bridge/adv7511/adv7511.h     | 3 +++
 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 6 +++++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h b/drivers/gpu/drm/bridge/adv7511/adv7511.h
index 161c923..12ee238 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511.h
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h
@@ -242,6 +242,7 @@ enum adv7511_sync_polarity {
  * @input_style:		The input component arrangement variant
  * @input_justification:	Video input format bit justification
  * @clock_delay:		Clock delay for the input clock (in ps)
+ * @clock_max_rate:		Clock maximum rate (in Hz)
  * @embedded_sync:		Video input uses BT.656-style embedded sync
  * @sync_pulse:			Select the sync pulse
  * @vsync_polarity:		vsync input signal configuration
@@ -255,6 +256,7 @@ struct adv7511_link_config {
 	enum adv7511_input_justification input_justification;
 
 	int clock_delay;
+	int clock_max_rate;
 
 	bool embedded_sync;
 	enum adv7511_input_sync_pulse sync_pulse;
@@ -307,6 +309,7 @@ struct adv7511 {
 	bool powered;
 
 	struct drm_display_mode curr_mode;
+	int clock_max_rate;
 
 	unsigned int f_tmds;
 
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index 41b45de..5dfa619 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
@@ -323,6 +323,7 @@ static void adv7511_set_link_config(struct adv7511 *adv7511,
 	adv7511->hsync_polarity = config->hsync_polarity;
 	adv7511->vsync_polarity = config->vsync_polarity;
 	adv7511->rgb = config->input_colorspace == HDMI_COLORSPACE_RGB;
+	adv7511->clock_max_rate = config->clock_max_rate;
 }
 
 static void adv7511_power_on(struct adv7511 *adv7511)
@@ -621,7 +622,7 @@ static int adv7511_get_modes(struct adv7511 *adv7511,
 static int adv7511_mode_valid(struct adv7511 *adv7511,
 			      struct drm_display_mode *mode)
 {
-	if (mode->clock > 165000)
+	if (mode->clock > adv7511->clock_max_rate)
 		return MODE_CLOCK_HIGH;
 
 	return MODE_OK;
@@ -917,6 +918,9 @@ static int adv7511_parse_dt(struct device_node *np,
 	if (config->clock_delay < -1200 || config->clock_delay > 1600)
 		return -EINVAL;
 
+	if (of_property_read_u32(np, "adi,clock-max-rate", &config->clock_max_rate))
+		config->clock_max_rate = 166000;
+
 	config->embedded_sync = of_property_read_bool(np, "adi,embedded-sync");
 
 	/* Hardcode the sync pulse configurations for now. */
-- 
1.9.1