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From 22f31ca58e24e9c8b92361e0d1f57a59d1fdbf64 Mon Sep 17 00:00:00 2001
From: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>
Date: Fri, 23 Mar 2018 16:32:07 +0300
Subject: [PATCH] r8a7797-v3msk,r8a7797-v3mzf: dts: Add spi flash s25fs512
Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts | 68 +++++++++++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a7797-v3mzf.dts | 68 +++++++++++++++++++++++++++
2 files changed, 136 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts
index 33c6c0d..604475d 100644
--- a/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7797-v3msk.dts
@@ -213,6 +213,74 @@
function = "mmc";
power-source = <3300>;
};
+
+ qspi0_pins: qspi0 {
+ groups = "qspi0_ctrl", "qspi0_data4";
+ function = "qspi0";
+ };
+
+ qspi1_pins: qspi1 {
+ groups = "qspi1_ctrl", "qspi1_data4";
+ function = "qspi1";
+ };
+};
+
+&qspi0 {
+ pinctrl-0 = <&qspi0_pins &qspi1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash@0 {
+ compatible = "spansion,s25fs512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootparam@0 {
+ reg = <0x00000000 0x040000>;
+ read-only;
+ };
+ cr7@00040000 {
+ reg = <0x00040000 0x080000>;
+ read-only;
+ };
+ cert_header_sa3@000C0000 {
+ reg = <0x000C0000 0x080000>;
+ read-only;
+ };
+ bl2@00140000 {
+ reg = <0x00140000 0x040000>;
+ read-only;
+ };
+ cert_header_sa6@00180000 {
+ reg = <0x00180000 0x040000>;
+ read-only;
+ };
+ bl31@001C0000 {
+ reg = <0x001C0000 0x460000>;
+ read-only;
+ };
+ uboot@00640000 {
+ reg = <0x00640000 0x100000>;
+ read-only;
+ };
+ dtb@00740000 {
+ reg = <0x00740000 0x080000>;
+ };
+ kernel@007C0000 {
+ reg = <0x007C0000 0x1400000>;
+ };
+ user@01BC0000 {
+ reg = <0x01BC0000 0x2440000>;
+ };
+ };
+ };
};
&scif0 {
diff --git a/arch/arm64/boot/dts/renesas/r8a7797-v3mzf.dts b/arch/arm64/boot/dts/renesas/r8a7797-v3mzf.dts
index 71d7bad..4a64881 100644
--- a/arch/arm64/boot/dts/renesas/r8a7797-v3mzf.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7797-v3mzf.dts
@@ -401,6 +401,74 @@
function = "mmc";
power-source = <3300>;
};
+
+ qspi0_pins: qspi0 {
+ groups = "qspi0_ctrl", "qspi0_data4";
+ function = "qspi0";
+ };
+
+ qspi1_pins: qspi1 {
+ groups = "qspi1_ctrl", "qspi1_data4";
+ function = "qspi1";
+ };
+};
+
+&qspi0 {
+ pinctrl-0 = <&qspi0_pins &qspi1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash@0 {
+ compatible = "spansion,s25fs512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootparam@0 {
+ reg = <0x00000000 0x040000>;
+ read-only;
+ };
+ cr7@00040000 {
+ reg = <0x00040000 0x080000>;
+ read-only;
+ };
+ cert_header_sa3@000C0000 {
+ reg = <0x000C0000 0x080000>;
+ read-only;
+ };
+ bl2@00140000 {
+ reg = <0x00140000 0x040000>;
+ read-only;
+ };
+ cert_header_sa6@00180000 {
+ reg = <0x00180000 0x040000>;
+ read-only;
+ };
+ bl31@001C0000 {
+ reg = <0x001C0000 0x460000>;
+ read-only;
+ };
+ uboot@00640000 {
+ reg = <0x00640000 0x100000>;
+ read-only;
+ };
+ dtb@00740000 {
+ reg = <0x00740000 0x080000>;
+ };
+ kernel@007C0000 {
+ reg = <0x007C0000 0x1400000>;
+ };
+ user@01BC0000 {
+ reg = <0x01BC0000 0x2440000>;
+ };
+ };
+ };
};
&scif0 {
--
2.7.4
|
