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From 102c206ea8ee28cf677061aa5e4ce509f776a924 Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm+renesas@opensource.se>
Date: Thu, 19 Mar 2015 10:49:43 +0900
Subject: [PATCH 14/18] serial: sh-sci: Break out default CTS/RTS pin setup
Break out CTS/RTS pin setup for the default case. We only
care about those pins in case SCIx_HAVE_RTSCTS is set.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
---
drivers/tty/serial/sh-sci.c | 45 +++++++++++++++++++++++++++++--------------
1 file changed, 31 insertions(+), 14 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 526409d..8465cfd 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -522,10 +522,29 @@ static void sci_poll_put_char(struct uart_port *port, unsigned char c)
}
#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
-static void sci_init_pins(struct uart_port *port, unsigned int cflag)
+static void sci_init_ctsrts_default(struct uart_port *port, bool hwflow_enabled)
{
struct sci_port *s = to_sci_port(port);
struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
+ unsigned short status;
+
+ /* If no SCSPTR register exists then skip. Same if hardware flow
+ * control has been enabled, in such case SCFCR.MCE will be set
+ * and the SCSPTR configuration is assumed to be overridden.
+ */
+ if (!reg->size || hwflow_enabled)
+ return;
+
+ status = serial_port_in(port, SCSPTR);
+ status &= ~SCSPTR_CTSIO;
+ status |= SCSPTR_RTSIO;
+ serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
+}
+
+static void sci_init_pins(struct uart_port *port, unsigned int cflag)
+{
+ struct sci_port *s = to_sci_port(port);
+ bool hwflow_enabled = cflag & CRTSCTS;
/*
* Use port-specific handler if provided.
@@ -535,22 +554,20 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag)
return;
}
- /*
- * For the generic path SCSPTR is necessary. Bail out if that's
- * unavailable, too.
+ /* SCIF hardware with RTS/CTS support needs special setup below.
+ *
+ * Please note that if RTS/CTS is available for the hardware
+ * platform depends on the particular SCIF channel on a certain
+ * SoC, and how this channel has been hooked up on the actual board.
+ *
+ * If the RTS/CTS signals will be used or not depends on what user
+ * space requests. In case RTS/CTS is available but not requested
+ * by user space we still need to configure the pins somehow.
*/
- if (!reg->size)
+ if (!(s->cfg->capabilities & SCIx_HAVE_RTSCTS))
return;
- if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
- ((!(cflag & CRTSCTS)))) {
- unsigned short status;
-
- status = serial_port_in(port, SCSPTR);
- status &= ~SCSPTR_CTSIO;
- status |= SCSPTR_RTSIO;
- serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
- }
+ sci_init_ctsrts_default(port, hwflow_enabled);
}
static int sci_txfill(struct uart_port *port)
--
1.7.10.4
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