diff options
Diffstat (limited to 'capstone/arch/RISCV/RISCVGenAsmWriter.inc')
| -rw-r--r-- | capstone/arch/RISCV/RISCVGenAsmWriter.inc | 2651 |
1 files changed, 2651 insertions, 0 deletions
diff --git a/capstone/arch/RISCV/RISCVGenAsmWriter.inc b/capstone/arch/RISCV/RISCVGenAsmWriter.inc new file mode 100644 index 000000000..220dd8ee9 --- /dev/null +++ b/capstone/arch/RISCV/RISCVGenAsmWriter.inc @@ -0,0 +1,2651 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Assembly Writer Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ + +#include <stdio.h> // debug +#include <capstone/platform.h> +#include <assert.h> + + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) +{ +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 'l', 'l', 'a', 9, 0, + /* 5 */ 's', 'f', 'e', 'n', 'c', 'e', '.', 'v', 'm', 'a', 9, 0, + /* 17 */ 's', 'r', 'a', 9, 0, + /* 22 */ 'l', 'b', 9, 0, + /* 26 */ 's', 'b', 9, 0, + /* 30 */ 'c', '.', 's', 'u', 'b', 9, 0, + /* 37 */ 'a', 'u', 'i', 'p', 'c', 9, 0, + /* 44 */ 'c', 's', 'r', 'r', 'c', 9, 0, + /* 51 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0, + /* 59 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0, + /* 68 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0, + /* 78 */ 's', 'c', '.', 'd', 9, 0, + /* 84 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0, + /* 92 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, + /* 101 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, + /* 111 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', 9, 0, + /* 121 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', 9, 0, + /* 131 */ 'f', 'l', 'e', '.', 'd', 9, 0, + /* 138 */ 'f', 's', 'g', 'n', 'j', '.', 'd', 9, 0, + /* 147 */ 'f', 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0, + /* 157 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0, + /* 165 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0, + /* 173 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', 9, 0, + /* 183 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 'd', 9, 0, + /* 193 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', 9, 0, + /* 204 */ 'f', 'e', 'q', '.', 'd', 9, 0, + /* 211 */ 'l', 'r', '.', 'd', 9, 0, + /* 217 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', 9, 0, + /* 226 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', 9, 0, + /* 236 */ 'f', 'c', 'v', 't', '.', 's', '.', 'd', 9, 0, + /* 246 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'd', 9, 0, + /* 256 */ 'f', 'l', 't', '.', 'd', 9, 0, + /* 263 */ 'f', 's', 'q', 'r', 't', '.', 'd', 9, 0, + /* 272 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 'd', 9, 0, + /* 283 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', 9, 0, + /* 294 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 'd', 9, 0, + /* 305 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', 9, 0, + /* 316 */ 'f', 'd', 'i', 'v', '.', 'd', 9, 0, + /* 324 */ 'f', 'c', 'v', 't', '.', 'w', '.', 'd', 9, 0, + /* 334 */ 'f', 'm', 'v', '.', 'x', '.', 'd', 9, 0, + /* 343 */ 'f', 'm', 'a', 'x', '.', 'd', 9, 0, + /* 351 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', 9, 0, + /* 361 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 'd', 9, 0, + /* 371 */ 'c', '.', 'a', 'd', 'd', 9, 0, + /* 378 */ 'c', '.', 'l', 'd', 9, 0, + /* 384 */ 'c', '.', 'f', 'l', 'd', 9, 0, + /* 391 */ 'c', '.', 'a', 'n', 'd', 9, 0, + /* 398 */ 'c', '.', 's', 'd', 9, 0, + /* 404 */ 'c', '.', 'f', 's', 'd', 9, 0, + /* 411 */ 'f', 'e', 'n', 'c', 'e', 9, 0, + /* 418 */ 'b', 'g', 'e', 9, 0, + /* 423 */ 'b', 'n', 'e', 9, 0, + /* 428 */ 'm', 'u', 'l', 'h', 9, 0, + /* 434 */ 's', 'h', 9, 0, + /* 438 */ 'f', 'e', 'n', 'c', 'e', '.', 'i', 9, 0, + /* 447 */ 'c', '.', 's', 'r', 'a', 'i', 9, 0, + /* 455 */ 'c', 's', 'r', 'r', 'c', 'i', 9, 0, + /* 463 */ 'c', '.', 'a', 'd', 'd', 'i', 9, 0, + /* 471 */ 'c', '.', 'a', 'n', 'd', 'i', 9, 0, + /* 479 */ 'w', 'f', 'i', 9, 0, + /* 484 */ 'c', '.', 'l', 'i', 9, 0, + /* 490 */ 'c', '.', 's', 'l', 'l', 'i', 9, 0, + /* 498 */ 'c', '.', 's', 'r', 'l', 'i', 9, 0, + /* 506 */ 'x', 'o', 'r', 'i', 9, 0, + /* 512 */ 'c', 's', 'r', 'r', 's', 'i', 9, 0, + /* 520 */ 's', 'l', 't', 'i', 9, 0, + /* 526 */ 'c', '.', 'l', 'u', 'i', 9, 0, + /* 533 */ 'c', 's', 'r', 'r', 'w', 'i', 9, 0, + /* 541 */ 'c', '.', 'j', 9, 0, + /* 546 */ 'c', '.', 'e', 'b', 'r', 'e', 'a', 'k', 9, 0, + /* 556 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 9, 0, + /* 566 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 9, 0, + /* 576 */ 'c', '.', 'j', 'a', 'l', 9, 0, + /* 583 */ 't', 'a', 'i', 'l', 9, 0, + /* 589 */ 'e', 'c', 'a', 'l', 'l', 9, 0, + /* 596 */ 's', 'l', 'l', 9, 0, + /* 601 */ 's', 'c', '.', 'd', '.', 'r', 'l', 9, 0, + /* 610 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'r', 'l', 9, 0, + /* 623 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'r', 'l', 9, 0, + /* 636 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'r', 'l', 9, 0, + /* 649 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'r', 'l', 9, 0, + /* 663 */ 'l', 'r', '.', 'd', '.', 'r', 'l', 9, 0, + /* 672 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0, + /* 684 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0, + /* 697 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'r', 'l', 9, 0, + /* 711 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'r', 'l', 9, 0, + /* 725 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'r', 'l', 9, 0, + /* 738 */ 's', 'c', '.', 'w', '.', 'r', 'l', 9, 0, + /* 747 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'r', 'l', 9, 0, + /* 760 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'r', 'l', 9, 0, + /* 773 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'r', 'l', 9, 0, + /* 786 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'r', 'l', 9, 0, + /* 800 */ 'l', 'r', '.', 'w', '.', 'r', 'l', 9, 0, + /* 809 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0, + /* 821 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0, + /* 834 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'r', 'l', 9, 0, + /* 848 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'r', 'l', 9, 0, + /* 862 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'r', 'l', 9, 0, + /* 875 */ 's', 'c', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 886 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 901 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 916 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 931 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 947 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 958 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 972 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 987 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 1003 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 1019 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 1034 */ 's', 'c', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 1045 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 1060 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 1075 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 1090 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 1106 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 1117 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 1131 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 1146 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 1162 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 1178 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, + /* 1193 */ 's', 'r', 'l', 9, 0, + /* 1198 */ 'm', 'u', 'l', 9, 0, + /* 1203 */ 'r', 'e', 'm', 9, 0, + /* 1208 */ 'c', '.', 'a', 'd', 'd', 'i', '4', 's', 'p', 'n', 9, 0, + /* 1220 */ 'f', 'e', 'n', 'c', 'e', '.', 't', 's', 'o', 9, 0, + /* 1231 */ 'c', '.', 'u', 'n', 'i', 'm', 'p', 9, 0, + /* 1240 */ 'c', '.', 'n', 'o', 'p', 9, 0, + /* 1247 */ 'c', '.', 'a', 'd', 'd', 'i', '1', '6', 's', 'p', 9, 0, + /* 1259 */ 'c', '.', 'l', 'd', 's', 'p', 9, 0, + /* 1267 */ 'c', '.', 'f', 'l', 'd', 's', 'p', 9, 0, + /* 1276 */ 'c', '.', 's', 'd', 's', 'p', 9, 0, + /* 1284 */ 'c', '.', 'f', 's', 'd', 's', 'p', 9, 0, + /* 1293 */ 'c', '.', 'l', 'w', 's', 'p', 9, 0, + /* 1301 */ 'c', '.', 'f', 'l', 'w', 's', 'p', 9, 0, + /* 1310 */ 'c', '.', 's', 'w', 's', 'p', 9, 0, + /* 1318 */ 'c', '.', 'f', 's', 'w', 's', 'p', 9, 0, + /* 1327 */ 's', 'c', '.', 'd', '.', 'a', 'q', 9, 0, + /* 1336 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 9, 0, + /* 1349 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 9, 0, + /* 1362 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 9, 0, + /* 1375 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 9, 0, + /* 1389 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 9, 0, + /* 1398 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0, + /* 1410 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0, + /* 1423 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 9, 0, + /* 1437 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 9, 0, + /* 1451 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 9, 0, + /* 1464 */ 's', 'c', '.', 'w', '.', 'a', 'q', 9, 0, + /* 1473 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 9, 0, + /* 1486 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 9, 0, + /* 1499 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 9, 0, + /* 1512 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 9, 0, + /* 1526 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 9, 0, + /* 1535 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0, + /* 1547 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0, + /* 1560 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 9, 0, + /* 1574 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 9, 0, + /* 1588 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 9, 0, + /* 1601 */ 'b', 'e', 'q', 9, 0, + /* 1606 */ 'c', '.', 'j', 'r', 9, 0, + /* 1612 */ 'c', '.', 'j', 'a', 'l', 'r', 9, 0, + /* 1620 */ 'c', '.', 'o', 'r', 9, 0, + /* 1626 */ 'c', '.', 'x', 'o', 'r', 9, 0, + /* 1633 */ 'f', 's', 'u', 'b', '.', 's', 9, 0, + /* 1641 */ 'f', 'm', 's', 'u', 'b', '.', 's', 9, 0, + /* 1650 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 's', 9, 0, + /* 1660 */ 'f', 'c', 'v', 't', '.', 'd', '.', 's', 9, 0, + /* 1670 */ 'f', 'a', 'd', 'd', '.', 's', 9, 0, + /* 1678 */ 'f', 'm', 'a', 'd', 'd', '.', 's', 9, 0, + /* 1687 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 's', 9, 0, + /* 1697 */ 'f', 'l', 'e', '.', 's', 9, 0, + /* 1704 */ 'f', 's', 'g', 'n', 'j', '.', 's', 9, 0, + /* 1713 */ 'f', 'c', 'v', 't', '.', 'l', '.', 's', 9, 0, + /* 1723 */ 'f', 'm', 'u', 'l', '.', 's', 9, 0, + /* 1731 */ 'f', 'm', 'i', 'n', '.', 's', 9, 0, + /* 1739 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 's', 9, 0, + /* 1749 */ 'f', 'e', 'q', '.', 's', 9, 0, + /* 1756 */ 'f', 'c', 'l', 'a', 's', 's', '.', 's', 9, 0, + /* 1766 */ 'f', 'l', 't', '.', 's', 9, 0, + /* 1773 */ 'f', 's', 'q', 'r', 't', '.', 's', 9, 0, + /* 1782 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 's', 9, 0, + /* 1793 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 's', 9, 0, + /* 1804 */ 'f', 'd', 'i', 'v', '.', 's', 9, 0, + /* 1812 */ 'f', 'c', 'v', 't', '.', 'w', '.', 's', 9, 0, + /* 1822 */ 'f', 'm', 'a', 'x', '.', 's', 9, 0, + /* 1830 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 's', 9, 0, + /* 1840 */ 'c', 's', 'r', 'r', 's', 9, 0, + /* 1847 */ 'm', 'r', 'e', 't', 9, 0, + /* 1853 */ 's', 'r', 'e', 't', 9, 0, + /* 1859 */ 'u', 'r', 'e', 't', 9, 0, + /* 1865 */ 'b', 'l', 't', 9, 0, + /* 1870 */ 's', 'l', 't', 9, 0, + /* 1875 */ 'l', 'b', 'u', 9, 0, + /* 1880 */ 'b', 'g', 'e', 'u', 9, 0, + /* 1886 */ 'm', 'u', 'l', 'h', 'u', 9, 0, + /* 1893 */ 's', 'l', 't', 'i', 'u', 9, 0, + /* 1900 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 'u', 9, 0, + /* 1911 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 'u', 9, 0, + /* 1922 */ 'r', 'e', 'm', 'u', 9, 0, + /* 1928 */ 'm', 'u', 'l', 'h', 's', 'u', 9, 0, + /* 1936 */ 'b', 'l', 't', 'u', 9, 0, + /* 1942 */ 's', 'l', 't', 'u', 9, 0, + /* 1948 */ 'd', 'i', 'v', 'u', 9, 0, + /* 1954 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 'u', 9, 0, + /* 1965 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 'u', 9, 0, + /* 1976 */ 'l', 'w', 'u', 9, 0, + /* 1981 */ 'd', 'i', 'v', 9, 0, + /* 1986 */ 'c', '.', 'm', 'v', 9, 0, + /* 1992 */ 's', 'c', '.', 'w', 9, 0, + /* 1998 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0, + /* 2008 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', 9, 0, + /* 2018 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', 9, 0, + /* 2028 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', 9, 0, + /* 2038 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', 9, 0, + /* 2049 */ 'l', 'r', '.', 'w', 9, 0, + /* 2055 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', 9, 0, + /* 2064 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', 9, 0, + /* 2074 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 9, 0, + /* 2084 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', 9, 0, + /* 2095 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', 9, 0, + /* 2106 */ 'f', 'm', 'v', '.', 'x', '.', 'w', 9, 0, + /* 2115 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', 9, 0, + /* 2125 */ 's', 'r', 'a', 'w', 9, 0, + /* 2131 */ 'c', '.', 's', 'u', 'b', 'w', 9, 0, + /* 2139 */ 'c', '.', 'a', 'd', 'd', 'w', 9, 0, + /* 2147 */ 's', 'r', 'a', 'i', 'w', 9, 0, + /* 2154 */ 'c', '.', 'a', 'd', 'd', 'i', 'w', 9, 0, + /* 2163 */ 's', 'l', 'l', 'i', 'w', 9, 0, + /* 2170 */ 's', 'r', 'l', 'i', 'w', 9, 0, + /* 2177 */ 'c', '.', 'l', 'w', 9, 0, + /* 2183 */ 'c', '.', 'f', 'l', 'w', 9, 0, + /* 2190 */ 's', 'l', 'l', 'w', 9, 0, + /* 2196 */ 's', 'r', 'l', 'w', 9, 0, + /* 2202 */ 'm', 'u', 'l', 'w', 9, 0, + /* 2208 */ 'r', 'e', 'm', 'w', 9, 0, + /* 2214 */ 'c', 's', 'r', 'r', 'w', 9, 0, + /* 2221 */ 'c', '.', 's', 'w', 9, 0, + /* 2227 */ 'c', '.', 'f', 's', 'w', 9, 0, + /* 2234 */ 'r', 'e', 'm', 'u', 'w', 9, 0, + /* 2241 */ 'd', 'i', 'v', 'u', 'w', 9, 0, + /* 2248 */ 'd', 'i', 'v', 'w', 9, 0, + /* 2254 */ 'f', 'm', 'v', '.', 'd', '.', 'x', 9, 0, + /* 2263 */ 'f', 'm', 'v', '.', 'w', '.', 'x', 9, 0, + /* 2272 */ 'c', '.', 'b', 'n', 'e', 'z', 9, 0, + /* 2280 */ 'c', '.', 'b', 'e', 'q', 'z', 9, 0, + /* 2288 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, + /* 2319 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, + /* 2343 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, + /* 2368 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, + /* 2391 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, + /* 2414 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, + /* 2436 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, + /* 2449 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, + /* 2456 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, + /* 2466 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, + /* 2476 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, + /* 2491 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, + }; +#endif + + static const uint16_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 2457U, // DBG_VALUE + 2467U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 2450U, // BUNDLE + 2477U, // LIFETIME_START + 2437U, // LIFETIME_END + 0U, // STACKMAP + 2492U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 2369U, // PATCHABLE_FUNCTION_ENTER + 2289U, // PATCHABLE_RET + 2415U, // PATCHABLE_FUNCTION_EXIT + 2392U, // PATCHABLE_TAIL_CALL + 2344U, // PATCHABLE_EVENT_CALL + 2320U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCANONICALIZE + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 4U, // ADJCALLSTACKDOWN + 4U, // ADJCALLSTACKUP + 4U, // BuildPairF64Pseudo + 4U, // PseudoAtomicLoadNand32 + 4U, // PseudoAtomicLoadNand64 + 4U, // PseudoBR + 4U, // PseudoBRIND + 4687U, // PseudoCALL + 4U, // PseudoCALLIndirect + 4U, // PseudoCmpXchg32 + 4U, // PseudoCmpXchg64 + 20482U, // PseudoLA + 20967U, // PseudoLI + 20481U, // PseudoLLA + 4U, // PseudoMaskedAtomicLoadAdd32 + 4U, // PseudoMaskedAtomicLoadMax32 + 4U, // PseudoMaskedAtomicLoadMin32 + 4U, // PseudoMaskedAtomicLoadNand32 + 4U, // PseudoMaskedAtomicLoadSub32 + 4U, // PseudoMaskedAtomicLoadUMax32 + 4U, // PseudoMaskedAtomicLoadUMin32 + 4U, // PseudoMaskedAtomicSwap32 + 4U, // PseudoMaskedCmpXchg32 + 4U, // PseudoRET + 4680U, // PseudoTAIL + 4U, // PseudoTAILIndirect + 4U, // Select_FPR32_Using_CC_GPR + 4U, // Select_FPR64_Using_CC_GPR + 4U, // Select_GPR_Using_CC_GPR + 4U, // SplitF64Pseudo + 20854U, // ADD + 20946U, // ADDI + 22637U, // ADDIW + 22622U, // ADDW + 20592U, // AMOADD_D + 21817U, // AMOADD_D_AQ + 21367U, // AMOADD_D_AQ_RL + 21091U, // AMOADD_D_RL + 22489U, // AMOADD_W + 21954U, // AMOADD_W_AQ + 21526U, // AMOADD_W_AQ_RL + 21228U, // AMOADD_W_RL + 20602U, // AMOAND_D + 21830U, // AMOAND_D_AQ + 21382U, // AMOAND_D_AQ_RL + 21104U, // AMOAND_D_RL + 22499U, // AMOAND_W + 21967U, // AMOAND_W_AQ + 21541U, // AMOAND_W_AQ_RL + 21241U, // AMOAND_W_RL + 20786U, // AMOMAXU_D + 21918U, // AMOMAXU_D_AQ + 21484U, // AMOMAXU_D_AQ_RL + 21192U, // AMOMAXU_D_RL + 22576U, // AMOMAXU_W + 22055U, // AMOMAXU_W_AQ + 21643U, // AMOMAXU_W_AQ_RL + 21329U, // AMOMAXU_W_RL + 20832U, // AMOMAX_D + 21932U, // AMOMAX_D_AQ + 21500U, // AMOMAX_D_AQ_RL + 21206U, // AMOMAX_D_RL + 22596U, // AMOMAX_W + 22069U, // AMOMAX_W_AQ + 21659U, // AMOMAX_W_AQ_RL + 21343U, // AMOMAX_W_RL + 20764U, // AMOMINU_D + 21904U, // AMOMINU_D_AQ + 21468U, // AMOMINU_D_AQ_RL + 21178U, // AMOMINU_D_RL + 22565U, // AMOMINU_W + 22041U, // AMOMINU_W_AQ + 21627U, // AMOMINU_W_AQ_RL + 21315U, // AMOMINU_W_RL + 20654U, // AMOMIN_D + 21843U, // AMOMIN_D_AQ + 21397U, // AMOMIN_D_AQ_RL + 21117U, // AMOMIN_D_RL + 22509U, // AMOMIN_W + 21980U, // AMOMIN_W_AQ + 21556U, // AMOMIN_W_AQ_RL + 21254U, // AMOMIN_W_RL + 20698U, // AMOOR_D + 21879U, // AMOOR_D_AQ + 21439U, // AMOOR_D_AQ_RL + 21153U, // AMOOR_D_RL + 22536U, // AMOOR_W + 22016U, // AMOOR_W_AQ + 21598U, // AMOOR_W_AQ_RL + 21290U, // AMOOR_W_RL + 20674U, // AMOSWAP_D + 21856U, // AMOSWAP_D_AQ + 21412U, // AMOSWAP_D_AQ_RL + 21130U, // AMOSWAP_D_RL + 22519U, // AMOSWAP_W + 21993U, // AMOSWAP_W_AQ + 21571U, // AMOSWAP_W_AQ_RL + 21267U, // AMOSWAP_W_RL + 20707U, // AMOXOR_D + 21891U, // AMOXOR_D_AQ + 21453U, // AMOXOR_D_AQ_RL + 21165U, // AMOXOR_D_RL + 22545U, // AMOXOR_W + 22028U, // AMOXOR_W_AQ + 21612U, // AMOXOR_W_AQ_RL + 21302U, // AMOXOR_W_RL + 20874U, // AND + 20954U, // ANDI + 20518U, // AUIPC + 22082U, // BEQ + 20899U, // BGE + 22361U, // BGEU + 22346U, // BLT + 22417U, // BLTU + 20904U, // BNE + 20525U, // CSRRC + 20936U, // CSRRCI + 22321U, // CSRRS + 20993U, // CSRRSI + 22695U, // CSRRW + 21014U, // CSRRWI + 8564U, // C_ADD + 8656U, // C_ADDI + 9440U, // C_ADDI16SP + 21689U, // C_ADDI4SPN + 10347U, // C_ADDIW + 10332U, // C_ADDW + 8584U, // C_AND + 8664U, // C_ANDI + 22761U, // C_BEQZ + 22753U, // C_BNEZ + 547U, // C_EBREAK + 20865U, // C_FLD + 21748U, // C_FLDSP + 22664U, // C_FLW + 21782U, // C_FLWSP + 20885U, // C_FSD + 21765U, // C_FSDSP + 22708U, // C_FSW + 21799U, // C_FSWSP + 4638U, // C_J + 4673U, // C_JAL + 5709U, // C_JALR + 5703U, // C_JR + 20859U, // C_LD + 21740U, // C_LDSP + 20965U, // C_LI + 21007U, // C_LUI + 22658U, // C_LW + 21774U, // C_LWSP + 22467U, // C_MV + 1241U, // C_NOP + 9813U, // C_OR + 20879U, // C_SD + 21757U, // C_SDSP + 8683U, // C_SLLI + 8640U, // C_SRAI + 8691U, // C_SRLI + 8223U, // C_SUB + 10324U, // C_SUBW + 22702U, // C_SW + 21791U, // C_SWSP + 1232U, // C_UNIMP + 9819U, // C_XOR + 22462U, // DIV + 22429U, // DIVU + 22722U, // DIVUW + 22729U, // DIVW + 549U, // EBREAK + 590U, // ECALL + 20565U, // FADD_D + 22151U, // FADD_S + 20727U, // FCLASS_D + 22237U, // FCLASS_S + 21037U, // FCVT_D_L + 22381U, // FCVT_D_LU + 22141U, // FCVT_D_S + 22479U, // FCVT_D_W + 22435U, // FCVT_D_WU + 20753U, // FCVT_LU_D + 22263U, // FCVT_LU_S + 20628U, // FCVT_L_D + 22194U, // FCVT_L_S + 20717U, // FCVT_S_D + 21047U, // FCVT_S_L + 22392U, // FCVT_S_LU + 22555U, // FCVT_S_W + 22446U, // FCVT_S_WU + 20775U, // FCVT_WU_D + 22274U, // FCVT_WU_S + 20805U, // FCVT_W_D + 22293U, // FCVT_W_S + 20797U, // FDIV_D + 22285U, // FDIV_S + 12700U, // FENCE + 439U, // FENCE_I + 1221U, // FENCE_TSO + 20685U, // FEQ_D + 22230U, // FEQ_S + 20867U, // FLD + 20612U, // FLE_D + 22178U, // FLE_S + 20737U, // FLT_D + 22247U, // FLT_S + 22666U, // FLW + 20573U, // FMADD_D + 22159U, // FMADD_S + 20824U, // FMAX_D + 22303U, // FMAX_S + 20646U, // FMIN_D + 22212U, // FMIN_S + 20540U, // FMSUB_D + 22122U, // FMSUB_S + 20638U, // FMUL_D + 22204U, // FMUL_S + 22735U, // FMV_D_X + 22744U, // FMV_W_X + 20815U, // FMV_X_D + 22587U, // FMV_X_W + 20582U, // FNMADD_D + 22168U, // FNMADD_S + 20549U, // FNMSUB_D + 22131U, // FNMSUB_S + 20887U, // FSD + 20664U, // FSGNJN_D + 22220U, // FSGNJN_S + 20842U, // FSGNJX_D + 22311U, // FSGNJX_S + 20619U, // FSGNJ_D + 22185U, // FSGNJ_S + 20744U, // FSQRT_D + 22254U, // FSQRT_S + 20532U, // FSUB_D + 22114U, // FSUB_S + 22710U, // FSW + 21059U, // JAL + 22095U, // JALR + 20503U, // LB + 22356U, // LBU + 20861U, // LD + 20911U, // LH + 22369U, // LHU + 37076U, // LR_D + 38254U, // LR_D_AQ + 37812U, // LR_D_AQ_RL + 37528U, // LR_D_RL + 38914U, // LR_W + 38391U, // LR_W_AQ + 37971U, // LR_W_AQ_RL + 37665U, // LR_W_RL + 21009U, // LUI + 22660U, // LW + 22457U, // LWU + 1848U, // MRET + 21679U, // MUL + 20909U, // MULH + 22409U, // MULHSU + 22367U, // MULHU + 22683U, // MULW + 22103U, // OR + 20988U, // ORI + 21684U, // REM + 22403U, // REMU + 22715U, // REMUW + 22689U, // REMW + 20507U, // SB + 20559U, // SC_D + 21808U, // SC_D_AQ + 21356U, // SC_D_AQ_RL + 21082U, // SC_D_RL + 22473U, // SC_W + 21945U, // SC_W_AQ + 21515U, // SC_W_AQ_RL + 21219U, // SC_W_RL + 20881U, // SD + 20486U, // SFENCE_VMA + 20915U, // SH + 21077U, // SLL + 20973U, // SLLI + 22644U, // SLLIW + 22671U, // SLLW + 22351U, // SLT + 21001U, // SLTI + 22374U, // SLTIU + 22423U, // SLTU + 20498U, // SRA + 20930U, // SRAI + 22628U, // SRAIW + 22606U, // SRAW + 1854U, // SRET + 21674U, // SRL + 20981U, // SRLI + 22651U, // SRLIW + 22677U, // SRLW + 20513U, // SUB + 22614U, // SUBW + 22704U, // SW + 1234U, // UNIMP + 1860U, // URET + 480U, // WFI + 22109U, // XOR + 20987U, // XORI + }; + + static const uint8_t OpInfo1[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCANONICALIZE + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // BuildPairF64Pseudo + 0U, // PseudoAtomicLoadNand32 + 0U, // PseudoAtomicLoadNand64 + 0U, // PseudoBR + 0U, // PseudoBRIND + 0U, // PseudoCALL + 0U, // PseudoCALLIndirect + 0U, // PseudoCmpXchg32 + 0U, // PseudoCmpXchg64 + 0U, // PseudoLA + 0U, // PseudoLI + 0U, // PseudoLLA + 0U, // PseudoMaskedAtomicLoadAdd32 + 0U, // PseudoMaskedAtomicLoadMax32 + 0U, // PseudoMaskedAtomicLoadMin32 + 0U, // PseudoMaskedAtomicLoadNand32 + 0U, // PseudoMaskedAtomicLoadSub32 + 0U, // PseudoMaskedAtomicLoadUMax32 + 0U, // PseudoMaskedAtomicLoadUMin32 + 0U, // PseudoMaskedAtomicSwap32 + 0U, // PseudoMaskedCmpXchg32 + 0U, // PseudoRET + 0U, // PseudoTAIL + 0U, // PseudoTAILIndirect + 0U, // Select_FPR32_Using_CC_GPR + 0U, // Select_FPR64_Using_CC_GPR + 0U, // Select_GPR_Using_CC_GPR + 0U, // SplitF64Pseudo + 4U, // ADD + 4U, // ADDI + 4U, // ADDIW + 4U, // ADDW + 9U, // AMOADD_D + 9U, // AMOADD_D_AQ + 9U, // AMOADD_D_AQ_RL + 9U, // AMOADD_D_RL + 9U, // AMOADD_W + 9U, // AMOADD_W_AQ + 9U, // AMOADD_W_AQ_RL + 9U, // AMOADD_W_RL + 9U, // AMOAND_D + 9U, // AMOAND_D_AQ + 9U, // AMOAND_D_AQ_RL + 9U, // AMOAND_D_RL + 9U, // AMOAND_W + 9U, // AMOAND_W_AQ + 9U, // AMOAND_W_AQ_RL + 9U, // AMOAND_W_RL + 9U, // AMOMAXU_D + 9U, // AMOMAXU_D_AQ + 9U, // AMOMAXU_D_AQ_RL + 9U, // AMOMAXU_D_RL + 9U, // AMOMAXU_W + 9U, // AMOMAXU_W_AQ + 9U, // AMOMAXU_W_AQ_RL + 9U, // AMOMAXU_W_RL + 9U, // AMOMAX_D + 9U, // AMOMAX_D_AQ + 9U, // AMOMAX_D_AQ_RL + 9U, // AMOMAX_D_RL + 9U, // AMOMAX_W + 9U, // AMOMAX_W_AQ + 9U, // AMOMAX_W_AQ_RL + 9U, // AMOMAX_W_RL + 9U, // AMOMINU_D + 9U, // AMOMINU_D_AQ + 9U, // AMOMINU_D_AQ_RL + 9U, // AMOMINU_D_RL + 9U, // AMOMINU_W + 9U, // AMOMINU_W_AQ + 9U, // AMOMINU_W_AQ_RL + 9U, // AMOMINU_W_RL + 9U, // AMOMIN_D + 9U, // AMOMIN_D_AQ + 9U, // AMOMIN_D_AQ_RL + 9U, // AMOMIN_D_RL + 9U, // AMOMIN_W + 9U, // AMOMIN_W_AQ + 9U, // AMOMIN_W_AQ_RL + 9U, // AMOMIN_W_RL + 9U, // AMOOR_D + 9U, // AMOOR_D_AQ + 9U, // AMOOR_D_AQ_RL + 9U, // AMOOR_D_RL + 9U, // AMOOR_W + 9U, // AMOOR_W_AQ + 9U, // AMOOR_W_AQ_RL + 9U, // AMOOR_W_RL + 9U, // AMOSWAP_D + 9U, // AMOSWAP_D_AQ + 9U, // AMOSWAP_D_AQ_RL + 9U, // AMOSWAP_D_RL + 9U, // AMOSWAP_W + 9U, // AMOSWAP_W_AQ + 9U, // AMOSWAP_W_AQ_RL + 9U, // AMOSWAP_W_RL + 9U, // AMOXOR_D + 9U, // AMOXOR_D_AQ + 9U, // AMOXOR_D_AQ_RL + 9U, // AMOXOR_D_RL + 9U, // AMOXOR_W + 9U, // AMOXOR_W_AQ + 9U, // AMOXOR_W_AQ_RL + 9U, // AMOXOR_W_RL + 4U, // AND + 4U, // ANDI + 0U, // AUIPC + 4U, // BEQ + 4U, // BGE + 4U, // BGEU + 4U, // BLT + 4U, // BLTU + 4U, // BNE + 2U, // CSRRC + 2U, // CSRRCI + 2U, // CSRRS + 2U, // CSRRSI + 2U, // CSRRW + 2U, // CSRRWI + 0U, // C_ADD + 0U, // C_ADDI + 0U, // C_ADDI16SP + 4U, // C_ADDI4SPN + 0U, // C_ADDIW + 0U, // C_ADDW + 0U, // C_AND + 0U, // C_ANDI + 0U, // C_BEQZ + 0U, // C_BNEZ + 0U, // C_EBREAK + 13U, // C_FLD + 13U, // C_FLDSP + 13U, // C_FLW + 13U, // C_FLWSP + 13U, // C_FSD + 13U, // C_FSDSP + 13U, // C_FSW + 13U, // C_FSWSP + 0U, // C_J + 0U, // C_JAL + 0U, // C_JALR + 0U, // C_JR + 13U, // C_LD + 13U, // C_LDSP + 0U, // C_LI + 0U, // C_LUI + 13U, // C_LW + 13U, // C_LWSP + 0U, // C_MV + 0U, // C_NOP + 0U, // C_OR + 13U, // C_SD + 13U, // C_SDSP + 0U, // C_SLLI + 0U, // C_SRAI + 0U, // C_SRLI + 0U, // C_SUB + 0U, // C_SUBW + 13U, // C_SW + 13U, // C_SWSP + 0U, // C_UNIMP + 0U, // C_XOR + 4U, // DIV + 4U, // DIVU + 4U, // DIVUW + 4U, // DIVW + 0U, // EBREAK + 0U, // ECALL + 36U, // FADD_D + 36U, // FADD_S + 0U, // FCLASS_D + 0U, // FCLASS_S + 20U, // FCVT_D_L + 20U, // FCVT_D_LU + 0U, // FCVT_D_S + 0U, // FCVT_D_W + 0U, // FCVT_D_WU + 20U, // FCVT_LU_D + 20U, // FCVT_LU_S + 20U, // FCVT_L_D + 20U, // FCVT_L_S + 20U, // FCVT_S_D + 20U, // FCVT_S_L + 20U, // FCVT_S_LU + 20U, // FCVT_S_W + 20U, // FCVT_S_WU + 20U, // FCVT_WU_D + 20U, // FCVT_WU_S + 20U, // FCVT_W_D + 20U, // FCVT_W_S + 36U, // FDIV_D + 36U, // FDIV_S + 0U, // FENCE + 0U, // FENCE_I + 0U, // FENCE_TSO + 4U, // FEQ_D + 4U, // FEQ_S + 13U, // FLD + 4U, // FLE_D + 4U, // FLE_S + 4U, // FLT_D + 4U, // FLT_S + 13U, // FLW + 100U, // FMADD_D + 100U, // FMADD_S + 4U, // FMAX_D + 4U, // FMAX_S + 4U, // FMIN_D + 4U, // FMIN_S + 100U, // FMSUB_D + 100U, // FMSUB_S + 36U, // FMUL_D + 36U, // FMUL_S + 0U, // FMV_D_X + 0U, // FMV_W_X + 0U, // FMV_X_D + 0U, // FMV_X_W + 100U, // FNMADD_D + 100U, // FNMADD_S + 100U, // FNMSUB_D + 100U, // FNMSUB_S + 13U, // FSD + 4U, // FSGNJN_D + 4U, // FSGNJN_S + 4U, // FSGNJX_D + 4U, // FSGNJX_S + 4U, // FSGNJ_D + 4U, // FSGNJ_S + 20U, // FSQRT_D + 20U, // FSQRT_S + 36U, // FSUB_D + 36U, // FSUB_S + 13U, // FSW + 0U, // JAL + 4U, // JALR + 13U, // LB + 13U, // LBU + 13U, // LD + 13U, // LH + 13U, // LHU + 0U, // LR_D + 0U, // LR_D_AQ + 0U, // LR_D_AQ_RL + 0U, // LR_D_RL + 0U, // LR_W + 0U, // LR_W_AQ + 0U, // LR_W_AQ_RL + 0U, // LR_W_RL + 0U, // LUI + 13U, // LW + 13U, // LWU + 0U, // MRET + 4U, // MUL + 4U, // MULH + 4U, // MULHSU + 4U, // MULHU + 4U, // MULW + 4U, // OR + 4U, // ORI + 4U, // REM + 4U, // REMU + 4U, // REMUW + 4U, // REMW + 13U, // SB + 9U, // SC_D + 9U, // SC_D_AQ + 9U, // SC_D_AQ_RL + 9U, // SC_D_RL + 9U, // SC_W + 9U, // SC_W_AQ + 9U, // SC_W_AQ_RL + 9U, // SC_W_RL + 13U, // SD + 0U, // SFENCE_VMA + 13U, // SH + 4U, // SLL + 4U, // SLLI + 4U, // SLLIW + 4U, // SLLW + 4U, // SLT + 4U, // SLTI + 4U, // SLTIU + 4U, // SLTU + 4U, // SRA + 4U, // SRAI + 4U, // SRAIW + 4U, // SRAW + 0U, // SRET + 4U, // SRL + 4U, // SRLI + 4U, // SRLIW + 4U, // SRLW + 4U, // SUB + 4U, // SUBW + 13U, // SW + 0U, // UNIMP + 0U, // URET + 0U, // WFI + 4U, // XOR + 4U, // XORI + }; + + // Emit the opcode for the instruction. + uint32_t Bits = 0; + Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0; + Bits |= OpInfo1[MCInst_getOpcode(MI)] << 16; + CS_ASSERT(Bits != 0 && "Cannot print this instruction."); +#ifndef CAPSTONE_DIET + SStream_concat0(O, AsmStrs+(Bits & 4095)-1); +#endif + + + // Fragment 0 encoded into 2 bits for 4 unique commands. + switch ((Bits >> 12) & 3) { + default: CS_ASSERT(0 && "Invalid command number."); + case 0: + // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... + return; + break; + case 1: + // PseudoCALL, PseudoLA, PseudoLI, PseudoLLA, PseudoTAIL, ADD, ADDI, ADDI... + printOperand(MI, 0, O); + break; + case 2: + // C_ADD, C_ADDI, C_ADDI16SP, C_ADDIW, C_ADDW, C_AND, C_ANDI, C_OR, C_SLL... + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 3: + // FENCE + printFenceArg(MI, 0, O); + SStream_concat0(O, ", "); + printFenceArg(MI, 1, O); + return; + break; + } + + + // Fragment 1 encoded into 2 bits for 3 unique commands. + switch ((Bits >> 14) & 3) { + default: CS_ASSERT(0 && "Invalid command number."); + case 0: + // PseudoCALL, PseudoTAIL, C_J, C_JAL, C_JALR, C_JR + return; + break; + case 1: + // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AMOADD_D, AMOAD... + SStream_concat0(O, ", "); + break; + case 2: + // LR_D, LR_D_AQ, LR_D_AQ_RL, LR_D_RL, LR_W, LR_W_AQ, LR_W_AQ_RL, LR_W_RL + SStream_concat0(O, ", ("); + printOperand(MI, 1, O); + SStream_concat0(O, ")"); + return; + break; + } + + + // Fragment 2 encoded into 2 bits for 3 unique commands. + switch ((Bits >> 16) & 3) { + default: CS_ASSERT(0 && "Invalid command number."); + case 0: + // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AND, ANDI, AUIP... + printOperand(MI, 1, O); + break; + case 1: + // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W... + printOperand(MI, 2, O); + break; + case 2: + // CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI + printCSRSystemRegister(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + } + + + // Fragment 3 encoded into 2 bits for 4 unique commands. + switch ((Bits >> 18) & 3) { + default: CS_ASSERT(0 && "Invalid command number."); + case 0: + // PseudoLA, PseudoLI, PseudoLLA, AUIPC, C_BEQZ, C_BNEZ, C_LI, C_LUI, C_M... + return; + break; + case 1: + // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A... + SStream_concat0(O, ", "); + break; + case 2: + // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W... + SStream_concat0(O, ", ("); + printOperand(MI, 1, O); + SStream_concat0(O, ")"); + return; + break; + case 3: + // C_FLD, C_FLDSP, C_FLW, C_FLWSP, C_FSD, C_FSDSP, C_FSW, C_FSWSP, C_LD, ... + SStream_concat0(O, "("); + printOperand(MI, 1, O); + SStream_concat0(O, ")"); + return; + break; + } + + + // Fragment 4 encoded into 1 bits for 2 unique commands. + if ((Bits >> 20) & 1) { + // FCVT_D_L, FCVT_D_LU, FCVT_LU_D, FCVT_LU_S, FCVT_L_D, FCVT_L_S, FCVT_S_... + printFRMArg(MI, 2, O); + return; + } else { + // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A... + printOperand(MI, 2, O); + } + + + // Fragment 5 encoded into 1 bits for 2 unique commands. + if ((Bits >> 21) & 1) { + // FADD_D, FADD_S, FDIV_D, FDIV_S, FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FM... + SStream_concat0(O, ", "); + } else { + // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A... + return; + } + + + // Fragment 6 encoded into 1 bits for 2 unique commands. + if ((Bits >> 22) & 1) { + // FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FNMADD_D, FNMADD_S, FNMSUB_D, FNMS... + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printFRMArg(MI, 4, O); + return; + } else { + // FADD_D, FADD_S, FDIV_D, FDIV_S, FMUL_D, FMUL_S, FSUB_D, FSUB_S + printFRMArg(MI, 3, O); + return; + } + +} + + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +static const char * +getRegisterName(unsigned RegNo, unsigned AltIdx) +{ + CS_ASSERT(RegNo && RegNo < 97 && "Invalid register number!"); + +#ifndef CAPSTONE_DIET + static const char AsmStrsABIRegAltName[] = { + /* 0 */ 'f', 's', '1', '0', 0, + /* 5 */ 'f', 't', '1', '0', 0, + /* 10 */ 'f', 'a', '0', 0, + /* 14 */ 'f', 's', '0', 0, + /* 18 */ 'f', 't', '0', 0, + /* 22 */ 'f', 's', '1', '1', 0, + /* 27 */ 'f', 't', '1', '1', 0, + /* 32 */ 'f', 'a', '1', 0, + /* 36 */ 'f', 's', '1', 0, + /* 40 */ 'f', 't', '1', 0, + /* 44 */ 'f', 'a', '2', 0, + /* 48 */ 'f', 's', '2', 0, + /* 52 */ 'f', 't', '2', 0, + /* 56 */ 'f', 'a', '3', 0, + /* 60 */ 'f', 's', '3', 0, + /* 64 */ 'f', 't', '3', 0, + /* 68 */ 'f', 'a', '4', 0, + /* 72 */ 'f', 's', '4', 0, + /* 76 */ 'f', 't', '4', 0, + /* 80 */ 'f', 'a', '5', 0, + /* 84 */ 'f', 's', '5', 0, + /* 88 */ 'f', 't', '5', 0, + /* 92 */ 'f', 'a', '6', 0, + /* 96 */ 'f', 's', '6', 0, + /* 100 */ 'f', 't', '6', 0, + /* 104 */ 'f', 'a', '7', 0, + /* 108 */ 'f', 's', '7', 0, + /* 112 */ 'f', 't', '7', 0, + /* 116 */ 'f', 's', '8', 0, + /* 120 */ 'f', 't', '8', 0, + /* 124 */ 'f', 's', '9', 0, + /* 128 */ 'f', 't', '9', 0, + /* 132 */ 'r', 'a', 0, + /* 135 */ 'z', 'e', 'r', 'o', 0, + /* 140 */ 'g', 'p', 0, + /* 143 */ 's', 'p', 0, + /* 146 */ 't', 'p', 0, + }; + + static const uint8_t RegAsmOffsetABIRegAltName[] = { + 135, 132, 143, 140, 146, 19, 41, 53, 15, 37, 11, 33, 45, 57, + 69, 81, 93, 105, 49, 61, 73, 85, 97, 109, 117, 125, 1, 23, + 65, 77, 89, 101, 18, 18, 40, 40, 52, 52, 64, 64, 76, 76, + 88, 88, 100, 100, 112, 112, 14, 14, 36, 36, 10, 10, 32, 32, + 44, 44, 56, 56, 68, 68, 80, 80, 92, 92, 104, 104, 48, 48, + 60, 60, 72, 72, 84, 84, 96, 96, 108, 108, 116, 116, 124, 124, + 0, 0, 22, 22, 120, 120, 128, 128, 5, 5, 27, 27, + }; + + static const char AsmStrsNoRegAltName[] = { + /* 0 */ 'f', '1', '0', 0, + /* 4 */ 'x', '1', '0', 0, + /* 8 */ 'f', '2', '0', 0, + /* 12 */ 'x', '2', '0', 0, + /* 16 */ 'f', '3', '0', 0, + /* 20 */ 'x', '3', '0', 0, + /* 24 */ 'f', '0', 0, + /* 27 */ 'x', '0', 0, + /* 30 */ 'f', '1', '1', 0, + /* 34 */ 'x', '1', '1', 0, + /* 38 */ 'f', '2', '1', 0, + /* 42 */ 'x', '2', '1', 0, + /* 46 */ 'f', '3', '1', 0, + /* 50 */ 'x', '3', '1', 0, + /* 54 */ 'f', '1', 0, + /* 57 */ 'x', '1', 0, + /* 60 */ 'f', '1', '2', 0, + /* 64 */ 'x', '1', '2', 0, + /* 68 */ 'f', '2', '2', 0, + /* 72 */ 'x', '2', '2', 0, + /* 76 */ 'f', '2', 0, + /* 79 */ 'x', '2', 0, + /* 82 */ 'f', '1', '3', 0, + /* 86 */ 'x', '1', '3', 0, + /* 90 */ 'f', '2', '3', 0, + /* 94 */ 'x', '2', '3', 0, + /* 98 */ 'f', '3', 0, + /* 101 */ 'x', '3', 0, + /* 104 */ 'f', '1', '4', 0, + /* 108 */ 'x', '1', '4', 0, + /* 112 */ 'f', '2', '4', 0, + /* 116 */ 'x', '2', '4', 0, + /* 120 */ 'f', '4', 0, + /* 123 */ 'x', '4', 0, + /* 126 */ 'f', '1', '5', 0, + /* 130 */ 'x', '1', '5', 0, + /* 134 */ 'f', '2', '5', 0, + /* 138 */ 'x', '2', '5', 0, + /* 142 */ 'f', '5', 0, + /* 145 */ 'x', '5', 0, + /* 148 */ 'f', '1', '6', 0, + /* 152 */ 'x', '1', '6', 0, + /* 156 */ 'f', '2', '6', 0, + /* 160 */ 'x', '2', '6', 0, + /* 164 */ 'f', '6', 0, + /* 167 */ 'x', '6', 0, + /* 170 */ 'f', '1', '7', 0, + /* 174 */ 'x', '1', '7', 0, + /* 178 */ 'f', '2', '7', 0, + /* 182 */ 'x', '2', '7', 0, + /* 186 */ 'f', '7', 0, + /* 189 */ 'x', '7', 0, + /* 192 */ 'f', '1', '8', 0, + /* 196 */ 'x', '1', '8', 0, + /* 200 */ 'f', '2', '8', 0, + /* 204 */ 'x', '2', '8', 0, + /* 208 */ 'f', '8', 0, + /* 211 */ 'x', '8', 0, + /* 214 */ 'f', '1', '9', 0, + /* 218 */ 'x', '1', '9', 0, + /* 222 */ 'f', '2', '9', 0, + /* 226 */ 'x', '2', '9', 0, + /* 230 */ 'f', '9', 0, + /* 233 */ 'x', '9', 0, + }; + + static const uint8_t RegAsmOffsetNoRegAltName[] = { + 27, 57, 79, 101, 123, 145, 167, 189, 211, 233, 4, 34, 64, 86, + 108, 130, 152, 174, 196, 218, 12, 42, 72, 94, 116, 138, 160, 182, + 204, 226, 20, 50, 24, 24, 54, 54, 76, 76, 98, 98, 120, 120, + 142, 142, 164, 164, 186, 186, 208, 208, 230, 230, 0, 0, 30, 30, + 60, 60, 82, 82, 104, 104, 126, 126, 148, 148, 170, 170, 192, 192, + 214, 214, 8, 8, 38, 38, 68, 68, 90, 90, 112, 112, 134, 134, + 156, 156, 178, 178, 200, 200, 222, 222, 16, 16, 46, 46, + }; + + switch(AltIdx) { + default: CS_ASSERT(0 && "Invalid register alt name index!"); + case RISCV_ABIRegAltName: + CS_ASSERT(*(AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]) && + "Invalid alt name index for register!"); + return AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]; + case RISCV_NoRegAltName: + CS_ASSERT(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && + "Invalid alt name index for register!"); + return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; + } +#else + return NULL; +#endif +} + +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp, + unsigned PredicateIndex); + +static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) +{ + MCRegisterInfo *MRI = (MCRegisterInfo *) info; + const char *AsmString; + unsigned I = 0; +#define ASMSTRING_CONTAIN_SIZE 64 + unsigned AsmStringLen = 0; + char tmpString_[ASMSTRING_CONTAIN_SIZE]; + char *tmpString = tmpString_; + switch (MCInst_getOpcode(MI)) { + default: return false; + case RISCV_ADDI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (ADDI X0, X0, 0) + AsmString = "nop"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (ADDI GPR:$rd, GPR:$rs, 0) + AsmString = "mv $\x01, $\x02"; + break; + } + return false; + case RISCV_ADDIW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (ADDIW GPR:$rd, GPR:$rs, 0) + AsmString = "sext.w $\x01, $\x02"; + break; + } + return false; + case RISCV_BEQ: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && + RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { + // (BEQ GPR:$rs, X0, simm13_lsb0:$offset) + AsmString = "beqz $\x01, $\x03"; + break; + } + return false; + case RISCV_BGE: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { + // (BGE X0, GPR:$rs, simm13_lsb0:$offset) + AsmString = "blez $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && + RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { + // (BGE GPR:$rs, X0, simm13_lsb0:$offset) + AsmString = "bgez $\x01, $\x03"; + break; + } + return false; + case RISCV_BLT: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && + RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { + // (BLT GPR:$rs, X0, simm13_lsb0:$offset) + AsmString = "bltz $\x01, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { + // (BLT X0, GPR:$rs, simm13_lsb0:$offset) + AsmString = "bgtz $\x02, $\x03"; + break; + } + return false; + case RISCV_BNE: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && + RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { + // (BNE GPR:$rs, X0, simm13_lsb0:$offset) + AsmString = "bnez $\x01, $\x03"; + break; + } + return false; + case RISCV_CSRRC: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + // (CSRRC X0, csr_sysreg:$csr, GPR:$rs) + AsmString = "csrc $\xFF\x02\x01, $\x03"; + break; + } + return false; + case RISCV_CSRRCI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) { + // (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm) + AsmString = "csrci $\xFF\x02\x01, $\x03"; + break; + } + return false; + case RISCV_CSRRS: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { + // (CSRRS GPR:$rd, 3, X0) + AsmString = "frcsr $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { + // (CSRRS GPR:$rd, 2, X0) + AsmString = "frrm $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { + // (CSRRS GPR:$rd, 1, X0) + AsmString = "frflags $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3074 && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { + // (CSRRS GPR:$rd, 3074, X0) + AsmString = "rdinstret $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3072 && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { + // (CSRRS GPR:$rd, 3072, X0) + AsmString = "rdcycle $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3073 && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { + // (CSRRS GPR:$rd, 3073, X0) + AsmString = "rdtime $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3202 && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { + // (CSRRS GPR:$rd, 3202, X0) + AsmString = "rdinstreth $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3200 && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { + // (CSRRS GPR:$rd, 3200, X0) + AsmString = "rdcycleh $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3201 && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { + // (CSRRS GPR:$rd, 3201, X0) + AsmString = "rdtimeh $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { + // (CSRRS GPR:$rd, csr_sysreg:$csr, X0) + AsmString = "csrr $\x01, $\xFF\x02\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + // (CSRRS X0, csr_sysreg:$csr, GPR:$rs) + AsmString = "csrs $\xFF\x02\x01, $\x03"; + break; + } + return false; + case RISCV_CSRRSI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) { + // (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm) + AsmString = "csrsi $\xFF\x02\x01, $\x03"; + break; + } + return false; + case RISCV_CSRRW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + // (CSRRW X0, 3, GPR:$rs) + AsmString = "fscsr $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + // (CSRRW X0, 2, GPR:$rs) + AsmString = "fsrm $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + // (CSRRW X0, 1, GPR:$rs) + AsmString = "fsflags $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + // (CSRRW X0, csr_sysreg:$csr, GPR:$rs) + AsmString = "csrw $\xFF\x02\x01, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + // (CSRRW GPR:$rd, 3, GPR:$rs) + AsmString = "fscsr $\x01, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + // (CSRRW GPR:$rd, 2, GPR:$rs) + AsmString = "fsrm $\x01, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + // (CSRRW GPR:$rd, 1, GPR:$rs) + AsmString = "fsflags $\x01, $\x03"; + break; + } + return false; + case RISCV_CSRRWI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { + // (CSRRWI X0, 2, uimm5:$imm) + AsmString = "fsrmi $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { + // (CSRRWI X0, 1, uimm5:$imm) + AsmString = "fsflagsi $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) { + // (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm) + AsmString = "csrwi $\xFF\x02\x01, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { + // (CSRRWI GPR:$rd, 2, uimm5:$imm) + AsmString = "fsrmi $\x01, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { + // (CSRRWI GPR:$rd, 1, uimm5:$imm) + AsmString = "fsflagsi $\x01, $\x03"; + break; + } + return false; + case RISCV_FADD_D: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (FADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) + AsmString = "fadd.d $\x01, $\x02, $\x03"; + break; + } + return false; + case RISCV_FADD_S: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (FADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) + AsmString = "fadd.s $\x01, $\x02, $\x03"; + break; + } + return false; + case RISCV_FCVT_D_L: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FCVT_D_L FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) + AsmString = "fcvt.d.l $\x01, $\x02"; + break; + } + return false; + case RISCV_FCVT_D_LU: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FCVT_D_LU FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) + AsmString = "fcvt.d.lu $\x01, $\x02"; + break; + } + return false; + case RISCV_FCVT_LU_D: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FCVT_LU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) + AsmString = "fcvt.lu.d $\x01, $\x02"; + break; + } + return false; + case RISCV_FCVT_LU_S: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FCVT_LU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) + AsmString = "fcvt.lu.s $\x01, $\x02"; + break; + } + return false; + case RISCV_FCVT_L_D: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FCVT_L_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) + AsmString = "fcvt.l.d $\x01, $\x02"; + break; + } + return false; + case RISCV_FCVT_L_S: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FCVT_L_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) + AsmString = "fcvt.l.s $\x01, $\x02"; + break; + } + return false; + case RISCV_FCVT_S_D: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FCVT_S_D FPR32:$rd, FPR64:$rs1, { 1, 1, 1 }) + AsmString = "fcvt.s.d $\x01, $\x02"; + break; + } + return false; + case RISCV_FCVT_S_L: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FCVT_S_L FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) + AsmString = "fcvt.s.l $\x01, $\x02"; + break; + } + return false; + case RISCV_FCVT_S_LU: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FCVT_S_LU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) + AsmString = "fcvt.s.lu $\x01, $\x02"; + break; + } + return false; + case RISCV_FCVT_S_W: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FCVT_S_W FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) + AsmString = "fcvt.s.w $\x01, $\x02"; + break; + } + return false; + case RISCV_FCVT_S_WU: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FCVT_S_WU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) + AsmString = "fcvt.s.wu $\x01, $\x02"; + break; + } + return false; + case RISCV_FCVT_WU_D: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FCVT_WU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) + AsmString = "fcvt.wu.d $\x01, $\x02"; + break; + } + return false; + case RISCV_FCVT_WU_S: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FCVT_WU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) + AsmString = "fcvt.wu.s $\x01, $\x02"; + break; + } + return false; + case RISCV_FCVT_W_D: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FCVT_W_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) + AsmString = "fcvt.w.d $\x01, $\x02"; + break; + } + return false; + case RISCV_FCVT_W_S: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FCVT_W_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) + AsmString = "fcvt.w.s $\x01, $\x02"; + break; + } + return false; + case RISCV_FDIV_D: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (FDIV_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) + AsmString = "fdiv.d $\x01, $\x02, $\x03"; + break; + } + return false; + case RISCV_FDIV_S: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (FDIV_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) + AsmString = "fdiv.s $\x01, $\x02, $\x03"; + break; + } + return false; + case RISCV_FENCE: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { + // (FENCE 15, 15) + AsmString = "fence"; + break; + } + return false; + case RISCV_FMADD_D: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { + // (FMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) + AsmString = "fmadd.d $\x01, $\x02, $\x03, $\x04"; + break; + } + return false; + case RISCV_FMADD_S: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { + // (FMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) + AsmString = "fmadd.s $\x01, $\x02, $\x03, $\x04"; + break; + } + return false; + case RISCV_FMSUB_D: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { + // (FMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) + AsmString = "fmsub.d $\x01, $\x02, $\x03, $\x04"; + break; + } + return false; + case RISCV_FMSUB_S: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { + // (FMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) + AsmString = "fmsub.s $\x01, $\x02, $\x03, $\x04"; + break; + } + return false; + case RISCV_FMUL_D: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (FMUL_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) + AsmString = "fmul.d $\x01, $\x02, $\x03"; + break; + } + return false; + case RISCV_FMUL_S: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (FMUL_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) + AsmString = "fmul.s $\x01, $\x02, $\x03"; + break; + } + return false; + case RISCV_FNMADD_D: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { + // (FNMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) + AsmString = "fnmadd.d $\x01, $\x02, $\x03, $\x04"; + break; + } + return false; + case RISCV_FNMADD_S: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { + // (FNMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) + AsmString = "fnmadd.s $\x01, $\x02, $\x03, $\x04"; + break; + } + return false; + case RISCV_FNMSUB_D: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { + // (FNMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) + AsmString = "fnmsub.d $\x01, $\x02, $\x03, $\x04"; + break; + } + return false; + case RISCV_FNMSUB_S: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { + // (FNMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) + AsmString = "fnmsub.s $\x01, $\x02, $\x03, $\x04"; + break; + } + return false; + case RISCV_FSGNJN_D: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs) + AsmString = "fneg.d $\x01, $\x02"; + break; + } + return false; + case RISCV_FSGNJN_S: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs) + AsmString = "fneg.s $\x01, $\x02"; + break; + } + return false; + case RISCV_FSGNJX_D: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs) + AsmString = "fabs.d $\x01, $\x02"; + break; + } + return false; + case RISCV_FSGNJX_S: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs) + AsmString = "fabs.s $\x01, $\x02"; + break; + } + return false; + case RISCV_FSGNJ_D: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs) + AsmString = "fmv.d $\x01, $\x02"; + break; + } + return false; + case RISCV_FSGNJ_S: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs) + AsmString = "fmv.s $\x01, $\x02"; + break; + } + return false; + case RISCV_FSQRT_D: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FSQRT_D FPR64:$rd, FPR64:$rs1, { 1, 1, 1 }) + AsmString = "fsqrt.d $\x01, $\x02"; + break; + } + return false; + case RISCV_FSQRT_S: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FSQRT_S FPR32:$rd, FPR32:$rs1, { 1, 1, 1 }) + AsmString = "fsqrt.s $\x01, $\x02"; + break; + } + return false; + case RISCV_FSUB_D: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (FSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) + AsmString = "fsub.d $\x01, $\x02, $\x03"; + break; + } + return false; + case RISCV_FSUB_S: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (FSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) + AsmString = "fsub.s $\x01, $\x02, $\x03"; + break; + } + return false; + case RISCV_JAL: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && + RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 2)) { + // (JAL X0, simm21_lsb0_jal:$offset) + AsmString = "j $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1 && + RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 2)) { + // (JAL X1, simm21_lsb0_jal:$offset) + AsmString = "jal $\x02"; + break; + } + return false; + case RISCV_JALR: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X1 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (JALR X0, X1, 0) + AsmString = "ret"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (JALR X0, GPR:$rs, 0) + AsmString = "jr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (JALR X1, GPR:$rs, 0) + AsmString = "jalr $\x02"; + break; + } + return false; + case RISCV_SFENCE_VMA: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) { + // (SFENCE_VMA X0, X0) + AsmString = "sfence.vma"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) { + // (SFENCE_VMA GPR:$rs, X0) + AsmString = "sfence.vma $\x01"; + break; + } + return false; + case RISCV_SLT: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { + // (SLT GPR:$rd, GPR:$rs, X0) + AsmString = "sltz $\x01, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + // (SLT GPR:$rd, X0, GPR:$rs) + AsmString = "sgtz $\x01, $\x03"; + break; + } + return false; + case RISCV_SLTIU: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (SLTIU GPR:$rd, GPR:$rs, 1) + AsmString = "seqz $\x01, $\x02"; + break; + } + return false; + case RISCV_SLTU: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + // (SLTU GPR:$rd, X0, GPR:$rs) + AsmString = "snez $\x01, $\x03"; + break; + } + return false; + case RISCV_SUB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + // (SUB GPR:$rd, X0, GPR:$rs) + AsmString = "neg $\x01, $\x03"; + break; + } + return false; + case RISCV_SUBW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + // (SUBW GPR:$rd, X0, GPR:$rs) + AsmString = "negw $\x01, $\x03"; + break; + } + return false; + case RISCV_XORI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1) { + // (XORI GPR:$rd, GPR:$rs, -1) + AsmString = "not $\x01, $\x02"; + break; + } + return false; + } + + AsmStringLen = strlen(AsmString); + if (ASMSTRING_CONTAIN_SIZE - 1 < AsmStringLen) + tmpString = cs_strdup(AsmString); + else + tmpString = memcpy(tmpString, AsmString, 1 + AsmStringLen); + + while (AsmString[I] != ' ' && AsmString[I] != '\t' && + AsmString[I] != '$' && AsmString[I] != '\0') + ++I; + tmpString[I] = 0; + SStream_concat0(OS, tmpString); + if (ASMSTRING_CONTAIN_SIZE - 1 < AsmStringLen) + /* Free the possible cs_strdup() memory. PR#1424. */ + cs_mem_free(tmpString); +#undef ASMSTRING_CONTAIN_SIZE + + if (AsmString[I] != '\0') { + if (AsmString[I] == ' ' || AsmString[I] == '\t') { + SStream_concat0(OS, " "); + ++I; + } + do { + if (AsmString[I] == '$') { + ++I; + if (AsmString[I] == (char)0xff) { + ++I; + int OpIdx = AsmString[I++] - 1; + int PrintMethodIdx = AsmString[I++] - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); + } else { + SStream_concat0(OS, &AsmString[I++]); + } + } while (AsmString[I] != '\0'); + } + + return true; +} + +static void printCustomAliasOperand( + MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, + SStream *OS) { + switch (PrintMethodIdx) { + default: + CS_ASSERT(0 && "Unknown PrintMethod kind"); + break; + case 0: + printCSRSystemRegister(MI, OpIdx, OS); + break; + } +} + +static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp, + unsigned PredicateIndex) { + // TODO: need some constant untils operate the MCOperand, + // but current CAPSTONE does't have. + // So, We just return true + return true; + +#if 0 + switch (PredicateIndex) { + default: + llvm_unreachable("Unknown MCOperandPredicate kind"); + break; + case 1: { + + int64_t Imm; + if (MCOp.evaluateAsConstantImm(Imm)) + return isShiftedInt<12, 1>(Imm); + return MCOp.isBareSymbolRef(); + + } + case 2: { + + int64_t Imm; + if (MCOp.evaluateAsConstantImm(Imm)) + return isShiftedInt<20, 1>(Imm); + return MCOp.isBareSymbolRef(); + + } + } +#endif +} + +#endif // PRINT_ALIAS_INSTR |