diff options
Diffstat (limited to 'capstone/arch/RISCV/RISCVGenSubtargetInfo.inc')
| -rw-r--r-- | capstone/arch/RISCV/RISCVGenSubtargetInfo.inc | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/capstone/arch/RISCV/RISCVGenSubtargetInfo.inc b/capstone/arch/RISCV/RISCVGenSubtargetInfo.inc new file mode 100644 index 000000000..c857ce6c1 --- /dev/null +++ b/capstone/arch/RISCV/RISCVGenSubtargetInfo.inc @@ -0,0 +1,33 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Subtarget Enumeration Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ + + +#ifdef GET_SUBTARGETINFO_ENUM +#undef GET_SUBTARGETINFO_ENUM + +/* + Make sure: + CS_MODE_RISCV64 = 0b11111 + CS_MODE_RISCV32 = 0b11110 +*/ + +enum { + RISCV_Feature64Bit = 1ULL << 0, + RISCV_FeatureStdExtA = 1ULL << 1, + RISCV_FeatureStdExtC = 1ULL << 2, + RISCV_FeatureStdExtD = 1ULL << 3, + RISCV_FeatureStdExtF = 1ULL << 4, + RISCV_FeatureStdExtM = 1ULL << 5, + RISCV_FeatureRelax = 1ULL << 6, +}; + +#endif // GET_SUBTARGETINFO_ENUM + |