diff options
Diffstat (limited to 'hw/cpu')
| -rw-r--r-- | hw/cpu/Kconfig | 8 | ||||
| -rw-r--r-- | hw/cpu/a15mpcore.c | 180 | ||||
| -rw-r--r-- | hw/cpu/a9mpcore.c | 194 | ||||
| -rw-r--r-- | hw/cpu/arm11mpcore.c | 169 | ||||
| -rw-r--r-- | hw/cpu/cluster.c | 100 | ||||
| -rw-r--r-- | hw/cpu/core.c | 106 | ||||
| -rw-r--r-- | hw/cpu/meson.build | 6 | ||||
| -rw-r--r-- | hw/cpu/realview_mpcore.c | 137 |
8 files changed, 900 insertions, 0 deletions
diff --git a/hw/cpu/Kconfig b/hw/cpu/Kconfig new file mode 100644 index 000000000..1767d028a --- /dev/null +++ b/hw/cpu/Kconfig @@ -0,0 +1,8 @@ +config ARM11MPCORE + bool + +config A9MPCORE + bool + +config A15MPCORE + bool diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c new file mode 100644 index 000000000..774ca9987 --- /dev/null +++ b/hw/cpu/a15mpcore.c @@ -0,0 +1,180 @@ +/* + * Cortex-A15MPCore internal peripheral emulation. + * + * Copyright (c) 2012 Linaro Limited. + * Written by Peter Maydell. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "hw/cpu/a15mpcore.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "sysemu/kvm.h" +#include "kvm_arm.h" + +static void a15mp_priv_set_irq(void *opaque, int irq, int level) +{ + A15MPPrivState *s = (A15MPPrivState *)opaque; + + qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); +} + +static void a15mp_priv_initfn(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + A15MPPrivState *s = A15MPCORE_PRIV(obj); + + memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000); + sysbus_init_mmio(sbd, &s->container); + + object_initialize_child(obj, "gic", &s->gic, gic_class_name()); + qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); +} + +static void a15mp_priv_realize(DeviceState *dev, Error **errp) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + A15MPPrivState *s = A15MPCORE_PRIV(dev); + DeviceState *gicdev; + SysBusDevice *busdev; + int i; + bool has_el3; + bool has_el2 = false; + Object *cpuobj; + + gicdev = DEVICE(&s->gic); + qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); + qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + + if (!kvm_irqchip_in_kernel()) { + /* Make the GIC's TZ support match the CPUs. We assume that + * either all the CPUs have TZ, or none do. + */ + cpuobj = OBJECT(qemu_get_cpu(0)); + has_el3 = object_property_find(cpuobj, "has_el3") && + object_property_get_bool(cpuobj, "has_el3", &error_abort); + qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); + /* Similarly for virtualization support */ + has_el2 = object_property_find(cpuobj, "has_el2") && + object_property_get_bool(cpuobj, "has_el2", &error_abort); + qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2); + } + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { + return; + } + busdev = SYS_BUS_DEVICE(&s->gic); + + /* Pass through outbound IRQ lines from the GIC */ + sysbus_pass_irq(sbd, busdev); + + /* Pass through inbound GPIO lines to the GIC */ + qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32); + + /* Wire the outputs from each CPU's generic timer to the + * appropriate GIC PPI inputs + */ + for (i = 0; i < s->num_cpu; i++) { + DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); + int ppibase = s->num_irq - 32 + i * 32; + int irq; + /* Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs used on the A15: + */ + const int timer_irq[] = { + [GTIMER_PHYS] = 30, + [GTIMER_VIRT] = 27, + [GTIMER_HYP] = 26, + [GTIMER_SEC] = 29, + }; + for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { + qdev_connect_gpio_out(cpudev, irq, + qdev_get_gpio_in(gicdev, + ppibase + timer_irq[irq])); + } + if (has_el2) { + /* Connect the GIC maintenance interrupt to PPI ID 25 */ + sysbus_connect_irq(SYS_BUS_DEVICE(gicdev), i + 4 * s->num_cpu, + qdev_get_gpio_in(gicdev, ppibase + 25)); + } + } + + /* Memory map (addresses are offsets from PERIPHBASE): + * 0x0000-0x0fff -- reserved + * 0x1000-0x1fff -- GIC Distributor + * 0x2000-0x3fff -- GIC CPU interface + * 0x4000-0x4fff -- GIC virtual interface control for this CPU + * 0x5000-0x51ff -- GIC virtual interface control for CPU 0 + * 0x5200-0x53ff -- GIC virtual interface control for CPU 1 + * 0x5400-0x55ff -- GIC virtual interface control for CPU 2 + * 0x5600-0x57ff -- GIC virtual interface control for CPU 3 + * 0x6000-0x7fff -- GIC virtual CPU interface + */ + memory_region_add_subregion(&s->container, 0x1000, + sysbus_mmio_get_region(busdev, 0)); + memory_region_add_subregion(&s->container, 0x2000, + sysbus_mmio_get_region(busdev, 1)); + if (has_el2) { + memory_region_add_subregion(&s->container, 0x4000, + sysbus_mmio_get_region(busdev, 2)); + memory_region_add_subregion(&s->container, 0x6000, + sysbus_mmio_get_region(busdev, 3)); + for (i = 0; i < s->num_cpu; i++) { + hwaddr base = 0x5000 + i * 0x200; + MemoryRegion *mr = sysbus_mmio_get_region(busdev, + 4 + s->num_cpu + i); + memory_region_add_subregion(&s->container, base, mr); + } + } +} + +static Property a15mp_priv_properties[] = { + DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), + /* The Cortex-A15MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 128+32, which + * is the number provided by the Cortex-A15MP test chip in the + * Versatile Express A15 development board. + * Other boards may differ and should set this property appropriately. + */ + DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160), + DEFINE_PROP_END_OF_LIST(), +}; + +static void a15mp_priv_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = a15mp_priv_realize; + device_class_set_props(dc, a15mp_priv_properties); + /* We currently have no savable state */ +} + +static const TypeInfo a15mp_priv_info = { + .name = TYPE_A15MPCORE_PRIV, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(A15MPPrivState), + .instance_init = a15mp_priv_initfn, + .class_init = a15mp_priv_class_init, +}; + +static void a15mp_register_types(void) +{ + type_register_static(&a15mp_priv_info); +} + +type_init(a15mp_register_types) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c new file mode 100644 index 000000000..d03f57e57 --- /dev/null +++ b/hw/cpu/a9mpcore.c @@ -0,0 +1,194 @@ +/* + * Cortex-A9MPCore internal peripheral emulation. + * + * Copyright (c) 2009 CodeSourcery. + * Copyright (c) 2011 Linaro Limited. + * Written by Paul Brook, Peter Maydell. + * + * This code is licensed under the GPL. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "hw/cpu/a9mpcore.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/core/cpu.h" +#include "cpu.h" + +#define A9_GIC_NUM_PRIORITY_BITS 5 + +static void a9mp_priv_set_irq(void *opaque, int irq, int level) +{ + A9MPPrivState *s = (A9MPPrivState *)opaque; + + qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); +} + +static void a9mp_priv_initfn(Object *obj) +{ + A9MPPrivState *s = A9MPCORE_PRIV(obj); + + memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); + + object_initialize_child(obj, "scu", &s->scu, TYPE_A9_SCU); + + object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); + + object_initialize_child(obj, "gtimer", &s->gtimer, TYPE_A9_GTIMER); + + object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER); + + object_initialize_child(obj, "wdt", &s->wdt, TYPE_ARM_MPTIMER); +} + +static void a9mp_priv_realize(DeviceState *dev, Error **errp) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + A9MPPrivState *s = A9MPCORE_PRIV(dev); + DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev; + SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev, + *wdtbusdev; + int i; + bool has_el3; + CPUState *cpu0; + Object *cpuobj; + + cpu0 = qemu_get_cpu(0); + cpuobj = OBJECT(cpu0); + if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9"))) { + /* We might allow Cortex-A5 once we model it */ + error_setg(errp, + "Cortex-A9MPCore peripheral can only use Cortex-A9 CPU"); + return; + } + + scudev = DEVICE(&s->scu); + qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { + return; + } + scubusdev = SYS_BUS_DEVICE(&s->scu); + + gicdev = DEVICE(&s->gic); + qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); + qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_prop_set_uint32(gicdev, "num-priority-bits", + A9_GIC_NUM_PRIORITY_BITS); + + /* Make the GIC's TZ support match the CPUs. We assume that + * either all the CPUs have TZ, or none do. + */ + has_el3 = object_property_find(cpuobj, "has_el3") && + object_property_get_bool(cpuobj, "has_el3", &error_abort); + qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { + return; + } + gicbusdev = SYS_BUS_DEVICE(&s->gic); + + /* Pass through outbound IRQ lines from the GIC */ + sysbus_pass_irq(sbd, gicbusdev); + + /* Pass through inbound GPIO lines to the GIC */ + qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32); + + gtimerdev = DEVICE(&s->gtimer); + qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gtimer), errp)) { + return; + } + gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer); + + mptimerdev = DEVICE(&s->mptimer); + qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), errp)) { + return; + } + mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer); + + wdtdev = DEVICE(&s->wdt); + qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt), errp)) { + return; + } + wdtbusdev = SYS_BUS_DEVICE(&s->wdt); + + /* Memory map (addresses are offsets from PERIPHBASE): + * 0x0000-0x00ff -- Snoop Control Unit + * 0x0100-0x01ff -- GIC CPU interface + * 0x0200-0x02ff -- Global Timer + * 0x0300-0x05ff -- nothing + * 0x0600-0x06ff -- private timers and watchdogs + * 0x0700-0x0fff -- nothing + * 0x1000-0x1fff -- GIC Distributor + */ + memory_region_add_subregion(&s->container, 0, + sysbus_mmio_get_region(scubusdev, 0)); + /* GIC CPU interface */ + memory_region_add_subregion(&s->container, 0x100, + sysbus_mmio_get_region(gicbusdev, 1)); + memory_region_add_subregion(&s->container, 0x200, + sysbus_mmio_get_region(gtimerbusdev, 0)); + /* Note that the A9 exposes only the "timer/watchdog for this core" + * memory region, not the "timer/watchdog for core X" ones 11MPcore has. + */ + memory_region_add_subregion(&s->container, 0x600, + sysbus_mmio_get_region(mptimerbusdev, 0)); + memory_region_add_subregion(&s->container, 0x620, + sysbus_mmio_get_region(wdtbusdev, 0)); + memory_region_add_subregion(&s->container, 0x1000, + sysbus_mmio_get_region(gicbusdev, 0)); + + /* Wire up the interrupt from each watchdog and timer. + * For each core the global timer is PPI 27, the private + * timer is PPI 29 and the watchdog PPI 30. + */ + for (i = 0; i < s->num_cpu; i++) { + int ppibase = (s->num_irq - 32) + i * 32; + sysbus_connect_irq(gtimerbusdev, i, + qdev_get_gpio_in(gicdev, ppibase + 27)); + sysbus_connect_irq(mptimerbusdev, i, + qdev_get_gpio_in(gicdev, ppibase + 29)); + sysbus_connect_irq(wdtbusdev, i, + qdev_get_gpio_in(gicdev, ppibase + 30)); + } +} + +static Property a9mp_priv_properties[] = { + DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), + /* The Cortex-A9MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 64+32, which + * is the number provided by the Cortex-A9MP test chip in the + * Realview PBX-A9 and Versatile Express A9 development boards. + * Other boards may differ and should set this property appropriately. + */ + DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), + DEFINE_PROP_END_OF_LIST(), +}; + +static void a9mp_priv_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = a9mp_priv_realize; + device_class_set_props(dc, a9mp_priv_properties); +} + +static const TypeInfo a9mp_priv_info = { + .name = TYPE_A9MPCORE_PRIV, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(A9MPPrivState), + .instance_init = a9mp_priv_initfn, + .class_init = a9mp_priv_class_init, +}; + +static void a9mp_register_types(void) +{ + type_register_static(&a9mp_priv_info); +} + +type_init(a9mp_register_types) diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c new file mode 100644 index 000000000..89c4e3514 --- /dev/null +++ b/hw/cpu/arm11mpcore.c @@ -0,0 +1,169 @@ +/* + * ARM11MPCore internal peripheral emulation. + * + * Copyright (c) 2006-2007 CodeSourcery. + * Written by Paul Brook + * + * This code is licensed under the GPL. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "hw/cpu/arm11mpcore.h" +#include "hw/intc/realview_gic.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" + +#define ARM11MPCORE_NUM_GIC_PRIORITY_BITS 4 + +static void mpcore_priv_set_irq(void *opaque, int irq, int level) +{ + ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; + + qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); +} + +static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) +{ + int i; + SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu); + DeviceState *gicdev = DEVICE(&s->gic); + SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic); + SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer); + SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer); + + memory_region_add_subregion(&s->container, 0, + sysbus_mmio_get_region(scubusdev, 0)); + /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs + * at 0x200, 0x300... + */ + for (i = 0; i < (s->num_cpu + 1); i++) { + hwaddr offset = 0x100 + (i * 0x100); + memory_region_add_subregion(&s->container, offset, + sysbus_mmio_get_region(gicbusdev, i + 1)); + } + /* Add the regions for timer and watchdog for "current CPU" and + * for each specific CPU. + */ + for (i = 0; i < (s->num_cpu + 1); i++) { + /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ + hwaddr offset = 0x600 + i * 0x100; + memory_region_add_subregion(&s->container, offset, + sysbus_mmio_get_region(timerbusdev, i)); + memory_region_add_subregion(&s->container, offset + 0x20, + sysbus_mmio_get_region(wdtbusdev, i)); + } + memory_region_add_subregion(&s->container, 0x1000, + sysbus_mmio_get_region(gicbusdev, 0)); + /* Wire up the interrupt from each watchdog and timer. + * For each core the timer is PPI 29 and the watchdog PPI 30. + */ + for (i = 0; i < s->num_cpu; i++) { + int ppibase = (s->num_irq - 32) + i * 32; + sysbus_connect_irq(timerbusdev, i, + qdev_get_gpio_in(gicdev, ppibase + 29)); + sysbus_connect_irq(wdtbusdev, i, + qdev_get_gpio_in(gicdev, ppibase + 30)); + } +} + +static void mpcore_priv_realize(DeviceState *dev, Error **errp) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev); + DeviceState *scudev = DEVICE(&s->scu); + DeviceState *gicdev = DEVICE(&s->gic); + DeviceState *mptimerdev = DEVICE(&s->mptimer); + DeviceState *wdtimerdev = DEVICE(&s->wdtimer); + + qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { + return; + } + + qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); + qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_prop_set_uint32(gicdev, "num-priority-bits", + ARM11MPCORE_NUM_GIC_PRIORITY_BITS); + + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { + return; + } + + /* Pass through outbound IRQ lines from the GIC */ + sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic)); + + /* Pass through inbound GPIO lines to the GIC */ + qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32); + + qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), errp)) { + return; + } + + qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdtimer), errp)) { + return; + } + + mpcore_priv_map_setup(s); +} + +static void mpcore_priv_initfn(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj); + + memory_region_init(&s->container, OBJECT(s), + "mpcore-priv-container", 0x2000); + sysbus_init_mmio(sbd, &s->container); + + object_initialize_child(obj, "scu", &s->scu, TYPE_ARM11_SCU); + + object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); + /* Request the legacy 11MPCore GIC behaviour: */ + qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0); + + object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER); + + object_initialize_child(obj, "wdtimer", &s->wdtimer, TYPE_ARM_MPTIMER); +} + +static Property mpcore_priv_properties[] = { + DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), + /* The ARM11 MPCORE TRM says the on-chip controller may have + * anything from 0 to 224 external interrupt IRQ lines (with another + * 32 internal). We default to 32+32, which is the number provided by + * the ARM11 MPCore test chip in the Realview Versatile Express + * coretile. Other boards may differ and should set this property + * appropriately. Some Linux kernels may not boot if the hardware + * has more IRQ lines than the kernel expects. + */ + DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mpcore_priv_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = mpcore_priv_realize; + device_class_set_props(dc, mpcore_priv_properties); +} + +static const TypeInfo mpcore_priv_info = { + .name = TYPE_ARM11MPCORE_PRIV, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(ARM11MPCorePriveState), + .instance_init = mpcore_priv_initfn, + .class_init = mpcore_priv_class_init, +}; + +static void arm11mpcore_register_types(void) +{ + type_register_static(&mpcore_priv_info); +} + +type_init(arm11mpcore_register_types) diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c new file mode 100644 index 000000000..e444b7c29 --- /dev/null +++ b/hw/cpu/cluster.c @@ -0,0 +1,100 @@ +/* + * QEMU CPU cluster + * + * Copyright (c) 2018 GreenSocs SAS + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * <http://www.gnu.org/licenses/gpl-2.0.html> + */ + +#include "qemu/osdep.h" +#include "hw/cpu/cluster.h" +#include "hw/qdev-properties.h" +#include "hw/core/cpu.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "qemu/cutils.h" + +static Property cpu_cluster_properties[] = { + DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0), + DEFINE_PROP_END_OF_LIST() +}; + +typedef struct CallbackData { + CPUClusterState *cluster; + int cpu_count; +} CallbackData; + +static int add_cpu_to_cluster(Object *obj, void *opaque) +{ + CallbackData *cbdata = opaque; + CPUState *cpu = (CPUState *)object_dynamic_cast(obj, TYPE_CPU); + + if (cpu) { + cpu->cluster_index = cbdata->cluster->cluster_id; + cbdata->cpu_count++; + } + return 0; +} + +static void cpu_cluster_realize(DeviceState *dev, Error **errp) +{ + /* Iterate through all our CPU children and set their cluster_index */ + CPUClusterState *cluster = CPU_CLUSTER(dev); + Object *cluster_obj = OBJECT(dev); + CallbackData cbdata = { + .cluster = cluster, + .cpu_count = 0, + }; + + if (cluster->cluster_id >= MAX_CLUSTERS) { + error_setg(errp, "cluster-id must be less than %d", MAX_CLUSTERS); + return; + } + + object_child_foreach_recursive(cluster_obj, add_cpu_to_cluster, &cbdata); + + /* + * A cluster with no CPUs is a bug in the board/SoC code that created it; + * if you hit this during development of new code, check that you have + * created the CPUs and parented them into the cluster object before + * realizing the cluster object. + */ + assert(cbdata.cpu_count > 0); +} + +static void cpu_cluster_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + device_class_set_props(dc, cpu_cluster_properties); + dc->realize = cpu_cluster_realize; + + /* This is not directly for users, CPU children must be attached by code */ + dc->user_creatable = false; +} + +static const TypeInfo cpu_cluster_type_info = { + .name = TYPE_CPU_CLUSTER, + .parent = TYPE_DEVICE, + .instance_size = sizeof(CPUClusterState), + .class_init = cpu_cluster_class_init, +}; + +static void cpu_cluster_register_types(void) +{ + type_register_static(&cpu_cluster_type_info); +} + +type_init(cpu_cluster_register_types) diff --git a/hw/cpu/core.c b/hw/cpu/core.c new file mode 100644 index 000000000..987607515 --- /dev/null +++ b/hw/cpu/core.c @@ -0,0 +1,106 @@ +/* + * CPU core abstract device + * + * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/cpu/core.h" +#include "qapi/visitor.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "sysemu/cpus.h" +#include "hw/boards.h" + +static void core_prop_get_core_id(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + CPUCore *core = CPU_CORE(obj); + int64_t value = core->core_id; + + visit_type_int(v, name, &value, errp); +} + +static void core_prop_set_core_id(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + CPUCore *core = CPU_CORE(obj); + int64_t value; + + if (!visit_type_int(v, name, &value, errp)) { + return; + } + + if (value < 0) { + error_setg(errp, "Invalid core id %"PRId64, value); + return; + } + + core->core_id = value; +} + +static void core_prop_get_nr_threads(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + CPUCore *core = CPU_CORE(obj); + int64_t value = core->nr_threads; + + visit_type_int(v, name, &value, errp); +} + +static void core_prop_set_nr_threads(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + CPUCore *core = CPU_CORE(obj); + int64_t value; + + if (!visit_type_int(v, name, &value, errp)) { + return; + } + + core->nr_threads = value; +} + +static void cpu_core_instance_init(Object *obj) +{ + CPUCore *core = CPU_CORE(obj); + + /* + * Only '-device something-cpu-core,help' can get us there before + * the machine has been created. We don't care to set nr_threads + * in this case since it isn't used afterwards. + */ + if (current_machine) { + core->nr_threads = current_machine->smp.threads; + } +} + +static void cpu_core_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + set_bit(DEVICE_CATEGORY_CPU, dc->categories); + object_class_property_add(oc, "core-id", "int", core_prop_get_core_id, + core_prop_set_core_id, NULL, NULL); + object_class_property_add(oc, "nr-threads", "int", core_prop_get_nr_threads, + core_prop_set_nr_threads, NULL, NULL); +} + +static const TypeInfo cpu_core_type_info = { + .name = TYPE_CPU_CORE, + .parent = TYPE_DEVICE, + .abstract = true, + .class_init = cpu_core_class_init, + .instance_size = sizeof(CPUCore), + .instance_init = cpu_core_instance_init, +}; + +static void cpu_core_register_types(void) +{ + type_register_static(&cpu_core_type_info); +} + +type_init(cpu_core_register_types) diff --git a/hw/cpu/meson.build b/hw/cpu/meson.build new file mode 100644 index 000000000..9e52fee9e --- /dev/null +++ b/hw/cpu/meson.build @@ -0,0 +1,6 @@ +softmmu_ss.add(files('core.c', 'cluster.c')) + +specific_ss.add(when: 'CONFIG_ARM11MPCORE', if_true: files('arm11mpcore.c')) +specific_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview_mpcore.c')) +specific_ss.add(when: 'CONFIG_A9MPCORE', if_true: files('a9mpcore.c')) +specific_ss.add(when: 'CONFIG_A15MPCORE', if_true: files('a15mpcore.c')) diff --git a/hw/cpu/realview_mpcore.c b/hw/cpu/realview_mpcore.c new file mode 100644 index 000000000..72c792eef --- /dev/null +++ b/hw/cpu/realview_mpcore.c @@ -0,0 +1,137 @@ +/* + * RealView ARM11MPCore internal peripheral emulation + * + * Copyright (c) 2006-2007 CodeSourcery. + * Copyright (c) 2013 SUSE LINUX Products GmbH + * Written by Paul Brook and Andreas Färber + * + * This code is licensed under the GPL. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "hw/cpu/arm11mpcore.h" +#include "hw/intc/realview_gic.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "qom/object.h" + +#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore" +OBJECT_DECLARE_SIMPLE_TYPE(mpcore_rirq_state, REALVIEW_MPCORE_RIRQ) + +/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ + controllers. The output of these, plus some of the raw input lines + are fed into a single SMP-aware interrupt controller on the CPU. */ +struct mpcore_rirq_state { + SysBusDevice parent_obj; + + qemu_irq cpuic[32]; + qemu_irq rvic[4][64]; + uint32_t num_cpu; + + ARM11MPCorePriveState priv; + RealViewGICState gic[4]; +}; + +/* Map baseboard IRQs onto CPU IRQ lines. */ +static const int mpcore_irq_map[32] = { + -1, -1, -1, -1, 1, 2, -1, -1, + -1, -1, 6, -1, 4, 5, -1, -1, + -1, 14, 15, 0, 7, 8, -1, -1, + -1, -1, -1, -1, 9, 3, -1, -1, +}; + +static void mpcore_rirq_set_irq(void *opaque, int irq, int level) +{ + mpcore_rirq_state *s = (mpcore_rirq_state *)opaque; + int i; + + for (i = 0; i < 4; i++) { + qemu_set_irq(s->rvic[i][irq], level); + } + if (irq < 32) { + irq = mpcore_irq_map[irq]; + if (irq >= 0) { + qemu_set_irq(s->cpuic[irq], level); + } + } +} + +static void realview_mpcore_realize(DeviceState *dev, Error **errp) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev); + DeviceState *priv = DEVICE(&s->priv); + DeviceState *gic; + SysBusDevice *gicbusdev; + int n; + int i; + + qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->priv), errp)) { + return; + } + sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->priv)); + for (i = 0; i < 32; i++) { + s->cpuic[i] = qdev_get_gpio_in(priv, i); + } + /* ??? IRQ routing is hardcoded to "normal" mode. */ + for (n = 0; n < 4; n++) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic[n]), errp)) { + return; + } + gic = DEVICE(&s->gic[n]); + gicbusdev = SYS_BUS_DEVICE(&s->gic[n]); + sysbus_mmio_map(gicbusdev, 0, 0x10040000 + n * 0x10000); + sysbus_connect_irq(gicbusdev, 0, s->cpuic[10 + n]); + for (i = 0; i < 64; i++) { + s->rvic[n][i] = qdev_get_gpio_in(gic, i); + } + } + qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64); +} + +static void mpcore_rirq_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(obj); + SysBusDevice *privbusdev; + int i; + + object_initialize_child(obj, "a11priv", &s->priv, TYPE_ARM11MPCORE_PRIV); + privbusdev = SYS_BUS_DEVICE(&s->priv); + sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0)); + + for (i = 0; i < 4; i++) { + object_initialize_child(obj, "gic[*]", &s->gic[i], TYPE_REALVIEW_GIC); + } +} + +static Property mpcore_rirq_properties[] = { + DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mpcore_rirq_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = realview_mpcore_realize; + device_class_set_props(dc, mpcore_rirq_properties); +} + +static const TypeInfo mpcore_rirq_info = { + .name = TYPE_REALVIEW_MPCORE_RIRQ, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(mpcore_rirq_state), + .instance_init = mpcore_rirq_init, + .class_init = mpcore_rirq_class_init, +}; + +static void realview_mpcore_register_types(void) +{ + type_register_static(&mpcore_rirq_info); +} + +type_init(realview_mpcore_register_types) |