diff options
Diffstat (limited to 'roms/edk2/MdePkg/Library/BaseLib')
394 files changed, 33074 insertions, 0 deletions
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.S b/roms/edk2/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.S new file mode 100644 index 000000000..7524fb188 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.S @@ -0,0 +1,31 @@ +#------------------------------------------------------------------------------
+#
+# CpuBreakpoint() for AArch64
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(CpuBreakpoint)
+
+#/**
+# Generates a breakpoint on the CPU.
+#
+# Generates a breakpoint on the CPU. The breakpoint must be implemented such
+# that code can resume normal execution after the breakpoint.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuBreakpoint (
+# VOID
+# );
+#
+ASM_PFX(CpuBreakpoint):
+ svc 0xdbdb // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here.
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm b/roms/edk2/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm new file mode 100644 index 000000000..4a5e05def --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; CpuBreakpoint() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+
+ EXPORT CpuBreakpoint
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+; Generates a breakpoint on the CPU.
+;
+; Generates a breakpoint on the CPU. The breakpoint must be implemented such
+; that code can resume normal execution after the breakpoint.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuBreakpoint (
+; VOID
+; );
+;
+CpuBreakpoint
+ svc 0xdbdb // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here.
+ ret
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.S b/roms/edk2/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.S new file mode 100644 index 000000000..f0faf16b0 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.S @@ -0,0 +1,30 @@ +#------------------------------------------------------------------------------
+#
+# DisableInterrupts() for AArch64
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(DisableInterrupts)
+
+.set DAIF_WR_IRQ_BIT, (1 << 1)
+
+#/**
+# Disables CPU interrupts.
+#
+#**/
+#VOID
+#EFIAPI
+#DisableInterrupts (
+# VOID
+# );
+#
+ASM_PFX(DisableInterrupts):
+ msr daifset, #DAIF_WR_IRQ_BIT
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm b/roms/edk2/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm new file mode 100644 index 000000000..f7be1ea27 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; DisableInterrupts() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT DisableInterrupts
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+DAIF_WR_IRQ_BIT EQU (1 << 1)
+
+;/**
+; Disables CPU interrupts.
+;
+;**/
+;VOID
+;EFIAPI
+;DisableInterrupts (
+; VOID
+; );
+;
+DisableInterrupts
+ msr daifset, #DAIF_WR_IRQ_BIT
+ ret
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.S b/roms/edk2/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.S new file mode 100644 index 000000000..97eeb13fb --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.S @@ -0,0 +1,30 @@ +#------------------------------------------------------------------------------
+#
+# EnableInterrupts() for AArch64
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(EnableInterrupts)
+
+.set DAIF_WR_IRQ_BIT, (1 << 1)
+
+#/**
+# Enables CPU interrupts.
+#
+#**/
+#VOID
+#EFIAPI
+#EnableInterrupts (
+# VOID
+# );
+#
+ASM_PFX(EnableInterrupts):
+ msr daifclr, #DAIF_WR_IRQ_BIT
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm b/roms/edk2/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm new file mode 100644 index 000000000..0c3a3103e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; EnableInterrupts() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT EnableInterrupts
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+DAIF_WR_IRQ_BIT EQU (1 << 1)
+
+;/**
+; Enables CPU interrupts.
+;
+;**/
+;VOID
+;EFIAPI
+;EnableInterrupts (
+; VOID
+; );
+;
+EnableInterrupts
+ msr daifclr, #DAIF_WR_IRQ_BIT
+ ret
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.S b/roms/edk2/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.S new file mode 100644 index 000000000..bf8b829bb --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.S @@ -0,0 +1,39 @@ +#------------------------------------------------------------------------------
+#
+# GetInterruptState() function for AArch64
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(GetInterruptState)
+
+.set DAIF_RD_IRQ_BIT, (1 << 7)
+
+#/**
+# Retrieves the current CPU interrupt state.
+#
+# Returns TRUE is interrupts are currently enabled. Otherwise
+# returns FALSE.
+#
+# @retval TRUE CPU interrupts are enabled.
+# @retval FALSE CPU interrupts are disabled.
+#
+#**/
+#
+#BOOLEAN
+#EFIAPI
+#GetInterruptState (
+# VOID
+# );
+#
+ASM_PFX(GetInterruptState):
+ mrs x0, daif
+ tst x0, #DAIF_RD_IRQ_BIT // Check IRQ mask; set Z=1 if clear/unmasked
+ cset w0, eq // if Z=1 (eq) return 1, else 0
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm b/roms/edk2/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm new file mode 100644 index 000000000..b169db45d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm @@ -0,0 +1,43 @@ +;------------------------------------------------------------------------------
+;
+; GetInterruptState() function for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT GetInterruptState
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+DAIF_RD_IRQ_BIT EQU (1 << 7)
+
+;/**
+; Retrieves the current CPU interrupt state.
+;
+; Returns TRUE is interrupts are currently enabled. Otherwise
+; returns FALSE.
+;
+; @retval TRUE CPU interrupts are enabled.
+; @retval FALSE CPU interrupts are disabled.
+;
+;**/
+;
+;BOOLEAN
+;EFIAPI
+;GetInterruptState (
+; VOID
+; );
+;
+GetInterruptState
+ mrs x0, daif
+ mov w0, wzr
+ tst x0, #DAIF_RD_IRQ_BIT // Check IRQ mask; set Z=1 if clear/unmasked
+ bne exit // if Z=1 (eq) return 1, else 0
+ mov w0, #1
+exit
+ ret
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/MemoryFence.S b/roms/edk2/MdePkg/Library/BaseLib/AArch64/MemoryFence.S new file mode 100644 index 000000000..e553bd2dc --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/MemoryFence.S @@ -0,0 +1,33 @@ +##------------------------------------------------------------------------------
+#
+# MemoryFence() for AArch64
+#
+# Copyright (c) 2013, ARM Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##------------------------------------------------------------------------------
+
+.text
+.p2align 2
+
+GCC_ASM_EXPORT(MemoryFence)
+
+
+#/**
+# Used to serialize load and store operations.
+#
+# All loads and stores that proceed calls to this function are guaranteed to be
+# globally visible when this function returns.
+#
+#**/
+#VOID
+#EFIAPI
+#MemoryFence (
+# VOID
+# );
+#
+ASM_PFX(MemoryFence):
+ // System wide Data Memory Barrier.
+ dmb sy
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm b/roms/edk2/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm new file mode 100644 index 000000000..85bc6c0f9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; MemoryFence() for AArch64
+;
+; Copyright (c) 2013, ARM Ltd. All rights reserved.
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT MemoryFence
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+; Used to serialize load and store operations.
+;
+; All loads and stores that proceed calls to this function are guaranteed to be
+; globally visible when this function returns.
+;
+;**/
+;VOID
+;EFIAPI
+;MemoryFence (
+; VOID
+; );
+;
+MemoryFence
+ // System wide Data Memory Barrier.
+ dmb sy
+ ret
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.S b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.S new file mode 100644 index 000000000..72cea259e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.S @@ -0,0 +1,91 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2009-2013, ARM Ltd. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+.text
+.p2align 3
+
+GCC_ASM_EXPORT(SetJump)
+GCC_ASM_EXPORT(InternalLongJump)
+
+#define GPR_LAYOUT \
+ REG_PAIR (x19, x20, 0); \
+ REG_PAIR (x21, x22, 16); \
+ REG_PAIR (x23, x24, 32); \
+ REG_PAIR (x25, x26, 48); \
+ REG_PAIR (x27, x28, 64); \
+ REG_PAIR (x29, x30, 80);/*FP, LR*/ \
+ REG_ONE (x16, 96) /*IP0*/
+
+#define FPR_LAYOUT \
+ REG_PAIR ( d8, d9, 112); \
+ REG_PAIR (d10, d11, 128); \
+ REG_PAIR (d12, d13, 144); \
+ REG_PAIR (d14, d15, 160);
+
+#/**
+# Saves the current CPU context that can be restored with a call to LongJump() and returns 0.#
+#
+# Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
+# call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
+# value to be returned by SetJump().
+#
+# If JumpBuffer is NULL, then ASSERT().
+# For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
+#
+# @param JumpBuffer A pointer to CPU context buffer.
+#
+#**/
+#
+#UINTN
+#EFIAPI
+#SetJump (
+# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // X0
+# );
+#
+ASM_PFX(SetJump):
+ mov x16, sp // use IP0 so save SP
+#define REG_PAIR(REG1, REG2, OFFS) stp REG1, REG2, [x0, OFFS]
+#define REG_ONE(REG1, OFFS) str REG1, [x0, OFFS]
+ GPR_LAYOUT
+ FPR_LAYOUT
+#undef REG_PAIR
+#undef REG_ONE
+ mov w0, #0
+ ret
+
+#/**
+# Restores the CPU context that was saved with SetJump().#
+#
+# Restores the CPU context from the buffer specified by JumpBuffer.
+# This function never returns to the caller.
+# Instead is resumes execution based on the state of JumpBuffer.
+#
+# @param JumpBuffer A pointer to CPU context buffer.
+# @param Value The value to return when the SetJump() context is restored.
+#
+#**/
+#VOID
+#EFIAPI
+#InternalLongJump (
+# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // X0
+# IN UINTN Value // X1
+# );
+#
+ASM_PFX(InternalLongJump):
+#define REG_PAIR(REG1, REG2, OFFS) ldp REG1, REG2, [x0, OFFS]
+#define REG_ONE(REG1, OFFS) ldr REG1, [x0, OFFS]
+ GPR_LAYOUT
+ FPR_LAYOUT
+#undef REG_PAIR
+#undef REG_ONE
+ mov sp, x16
+ cmp w1, #0
+ mov w0, #1
+ csel w0, w1, w0, ne
+ // use br not ret, as ret is guaranteed to mispredict
+ br x30
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm new file mode 100644 index 000000000..20dd0f1b8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm @@ -0,0 +1,95 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2009-2013, ARM Ltd. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT SetJump
+ EXPORT InternalLongJump
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+#define GPR_LAYOUT \
+ REG_PAIR (x19, x20, #0); \
+ REG_PAIR (x21, x22, #16); \
+ REG_PAIR (x23, x24, #32); \
+ REG_PAIR (x25, x26, #48); \
+ REG_PAIR (x27, x28, #64); \
+ REG_PAIR (x29, x30, #80);/*FP, LR*/ \
+ REG_ONE (x16, #96) /*IP0*/
+
+#define FPR_LAYOUT \
+ REG_PAIR ( d8, d9, #112); \
+ REG_PAIR (d10, d11, #128); \
+ REG_PAIR (d12, d13, #144); \
+ REG_PAIR (d14, d15, #160);
+
+;/**
+; Saves the current CPU context that can be restored with a call to LongJump() and returns 0.#
+;
+; Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
+; call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
+; value to be returned by SetJump().
+;
+; If JumpBuffer is NULL, then ASSERT().
+; For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
+;
+; @param JumpBuffer A pointer to CPU context buffer.
+;
+;**/
+;
+;UINTN
+;EFIAPI
+;SetJump (
+; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // X0
+; );
+;
+SetJump
+ mov x16, sp // use IP0 so save SP
+#define REG_PAIR(REG1, REG2, OFFS) stp REG1, REG2, [x0, OFFS]
+#define REG_ONE(REG1, OFFS) str REG1, [x0, OFFS]
+ GPR_LAYOUT
+ FPR_LAYOUT
+#undef REG_PAIR
+#undef REG_ONE
+ mov w0, #0
+ ret
+
+;/**
+; Restores the CPU context that was saved with SetJump().#
+;
+; Restores the CPU context from the buffer specified by JumpBuffer.
+; This function never returns to the caller.
+; Instead is resumes execution based on the state of JumpBuffer.
+;
+; @param JumpBuffer A pointer to CPU context buffer.
+; @param Value The value to return when the SetJump() context is restored.
+;
+;**/
+;VOID
+;EFIAPI
+;InternalLongJump (
+; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // X0
+; IN UINTN Value // X1
+; );
+;
+InternalLongJump
+#define REG_PAIR(REG1, REG2, OFFS) ldp REG1, REG2, [x0, OFFS]
+#define REG_ONE(REG1, OFFS) ldr REG1, [x0, OFFS]
+ GPR_LAYOUT
+ FPR_LAYOUT
+#undef REG_PAIR
+#undef REG_ONE
+ mov sp, x16
+ cmp w1, #0
+ mov w0, #1
+ beq exit
+ mov w0, w1
+exit
+ // use br not ret, as ret is guaranteed to mispredict
+ br x30
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
+
+ END
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.S b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.S new file mode 100644 index 000000000..a20d6aed0 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.S @@ -0,0 +1,33 @@ +##------------------------------------------------------------------------------
+#
+# SpeculationBarrier() for AArch64
+#
+# Copyright (c) 2019, Linaro Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##------------------------------------------------------------------------------
+
+.text
+.p2align 2
+
+GCC_ASM_EXPORT(SpeculationBarrier)
+
+
+#/**
+# Uses as a barrier to stop speculative execution.
+#
+# Ensures that no later instruction will execute speculatively, until all prior
+# instructions have completed.
+#
+#**/
+#VOID
+#EFIAPI
+#SpeculationBarrier (
+# VOID
+# );
+#
+ASM_PFX(SpeculationBarrier):
+ dsb sy
+ isb
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.asm b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.asm new file mode 100644 index 000000000..cafbe2bf2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.asm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; SpeculationBarrier() for AArch64
+;
+; Copyright (c) 2019, Linaro Ltd. All rights reserved.
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT SpeculationBarrier
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+; Uses as a barrier to stop speculative execution.
+;
+; Ensures that no later instruction will execute speculatively, until all prior
+; instructions have completed.
+;
+;**/
+;VOID
+;EFIAPI
+;SpeculationBarrier (
+; VOID
+; );
+;
+SpeculationBarrier
+ dsb sy
+ isb
+ ret
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/SwitchStack.S b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SwitchStack.S new file mode 100644 index 000000000..f3bce6a09 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SwitchStack.S @@ -0,0 +1,65 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Limited. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 5
+
+GCC_ASM_EXPORT(InternalSwitchStackAsm)
+GCC_ASM_EXPORT(CpuPause)
+
+#/**
+#
+# This allows the caller to switch the stack and goes to the new entry point
+#
+# @param EntryPoint The pointer to the location to enter
+# @param Context Parameter to pass in
+# @param Context2 Parameter2 to pass in
+# @param NewStack New Location of the stack
+#
+# @return Nothing. Goes to the Entry Point passing in the new parameters
+#
+#**/
+#VOID
+#EFIAPI
+#InternalSwitchStackAsm (
+# SWITCH_STACK_ENTRY_POINT EntryPoint,
+# VOID *Context,
+# VOID *Context2,
+# VOID *NewStack
+# );
+#
+ASM_PFX(InternalSwitchStackAsm):
+ mov x29, #0
+ mov x30, x0
+ mov sp, x3
+ mov x0, x1
+ mov x1, x2
+ ret
+
+#/**
+#
+# Requests CPU to pause for a short period of time.
+#
+# Requests CPU to pause for a short period of time. Typically used in MP
+# systems to prevent memory starvation while waiting for a spin lock.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuPause (
+# VOID
+# )
+#
+ASM_PFX(CpuPause):
+ nop
+ nop
+ nop
+ nop
+ nop
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm new file mode 100644 index 000000000..56dce5cbe --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm @@ -0,0 +1,65 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Limited. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT InternalSwitchStackAsm
+ EXPORT CpuPause
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+;
+; This allows the caller to switch the stack and goes to the new entry point
+;
+; @param EntryPoint The pointer to the location to enter
+; @param Context Parameter to pass in
+; @param Context2 Parameter2 to pass in
+; @param NewStack New Location of the stack
+;
+; @return Nothing. Goes to the Entry Point passing in the new parameters
+;
+;**/
+;VOID
+;EFIAPI
+;InternalSwitchStackAsm (
+; SWITCH_STACK_ENTRY_POINT EntryPoint,
+; VOID *Context,
+; VOID *Context2,
+; VOID *NewStack
+; );
+;
+InternalSwitchStackAsm
+ mov x29, #0
+ mov x30, x0
+ mov sp, x3
+ mov x0, x1
+ mov x1, x2
+ ret
+
+;/**
+;
+; Requests CPU to pause for a short period of time.
+;
+; Requests CPU to pause for a short period of time. Typically used in MP
+; systems to prevent memory starvation while waiting for a spin lock.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuPause (
+; VOID
+; )
+;
+CpuPause
+ nop
+ nop
+ nop
+ nop
+ nop
+ ret
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/ARShiftU64.c b/roms/edk2/MdePkg/Library/BaseLib/ARShiftU64.c new file mode 100644 index 000000000..9928854dd --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/ARShiftU64.c @@ -0,0 +1,35 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Shifts a 64-bit integer right between 0 and 63 bits. The high bits are filled
+ with the original integer's bit 63. The shifted value is returned.
+
+ This function shifts the 64-bit value Operand to the right by Count bits. The
+ high Count bits are set to bit 63 of Operand. The shifted value is returned.
+
+ If Count is greater than 63, then ASSERT().
+
+ @param Operand The 64-bit operand to shift right.
+ @param Count The number of bits to shift right.
+
+ @return Operand >> Count
+
+**/
+UINT64
+EFIAPI
+ARShiftU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ )
+{
+ ASSERT (Count < 64);
+ return InternalMathARShiftU64 (Operand, Count);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.S b/roms/edk2/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.S new file mode 100644 index 000000000..3bc2246a8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.S @@ -0,0 +1,30 @@ +#------------------------------------------------------------------------------
+#
+# CpuBreakpoint() for ARM
+#
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(CpuBreakpoint)
+
+#/**
+# Generates a breakpoint on the CPU.
+#
+# Generates a breakpoint on the CPU. The breakpoint must be implemented such
+# that code can resume normal execution after the breakpoint.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuBreakpoint (
+# VOID
+# );
+#
+ASM_PFX(CpuBreakpoint):
+ swi 0xdbdbdb
+ bx lr
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm b/roms/edk2/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm new file mode 100644 index 000000000..baf6d2783 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; CpuBreakpoint() for ARM
+;
+; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT CpuBreakpoint
+
+; Force ARM mode for this section, as MSFT assembler defaults to THUMB
+ AREA Cpu_Breakpoint, CODE, READONLY, ARM
+
+ ARM
+
+;/**
+; Generates a breakpoint on the CPU.
+;
+; Generates a breakpoint on the CPU. The breakpoint must be implemented such
+; that code can resume normal execution after the breakpoint.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuBreakpoint (
+; VOID
+; );
+;
+CpuBreakpoint
+ swi 0xdbdbdb
+ bx lr
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/CpuPause.asm b/roms/edk2/MdePkg/Library/BaseLib/Arm/CpuPause.asm new file mode 100644 index 000000000..a16223c7f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/CpuPause.asm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; CpuPause() for ARM
+;
+; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT CpuPause
+ AREA cpu_pause, CODE, READONLY
+
+;/**
+; Requests CPU to pause for a short period of time.
+;
+; Requests CPU to pause for a short period of time. Typically used in MP
+; systems to prevent memory starvation while waiting for a spin lock.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuPause (
+; VOID
+; );
+;
+CpuPause
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ BX LR
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/DisableInterrupts.S b/roms/edk2/MdePkg/Library/BaseLib/Arm/DisableInterrupts.S new file mode 100644 index 000000000..1f3fe7cc9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/DisableInterrupts.S @@ -0,0 +1,29 @@ +#------------------------------------------------------------------------------
+#
+# DisableInterrupts() for ARM
+#
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(DisableInterrupts)
+
+#/**
+# Disables CPU interrupts.
+#
+#**/
+#VOID
+#EFIAPI
+#DisableInterrupts (
+# VOID
+# );
+#
+ASM_PFX(DisableInterrupts):
+ mrs R0,CPSR
+ orr R0,R0,#0x80 @Disable IRQ interrupts
+ msr CPSR_c,R0
+ bx LR
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/DisableInterrupts.asm b/roms/edk2/MdePkg/Library/BaseLib/Arm/DisableInterrupts.asm new file mode 100644 index 000000000..e4e90b5f7 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/DisableInterrupts.asm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; DisableInterrupts() for ARM
+;
+; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT DisableInterrupts
+
+ AREA Interrupt_disable, CODE, READONLY
+
+;/**
+; Disables CPU interrupts.
+;
+;**/
+;VOID
+;EFIAPI
+;DisableInterrupts (
+; VOID
+; );
+;
+DisableInterrupts
+ MRS R0,CPSR
+ ORR R0,R0,#0x80 ;Disable IRQ interrupts
+ MSR CPSR_c,R0
+ BX LR
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/EnableInterrupts.S b/roms/edk2/MdePkg/Library/BaseLib/Arm/EnableInterrupts.S new file mode 100644 index 000000000..5de3b0945 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/EnableInterrupts.S @@ -0,0 +1,30 @@ +#------------------------------------------------------------------------------
+#
+# EnableInterrupts() for ARM
+#
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(EnableInterrupts)
+
+
+#/**
+# Enables CPU interrupts.
+#
+#**/
+#VOID
+#EFIAPI
+#EnableInterrupts (
+# VOID
+# );
+#
+ASM_PFX(EnableInterrupts):
+ mrs R0,CPSR
+ bic R0,R0,#0x80 @Enable IRQ interrupts
+ msr CPSR_c,R0
+ bx LR
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/EnableInterrupts.asm b/roms/edk2/MdePkg/Library/BaseLib/Arm/EnableInterrupts.asm new file mode 100644 index 000000000..0fcf66f7d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/EnableInterrupts.asm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; EnableInterrupts() for ARM
+;
+; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT EnableInterrupts
+
+ AREA Interrupt_enable, CODE, READONLY
+
+;/**
+; Enables CPU interrupts.
+;
+;**/
+;VOID
+;EFIAPI
+;EnableInterrupts (
+; VOID
+; );
+;
+EnableInterrupts
+ MRS R0,CPSR
+ BIC R0,R0,#0x80 ;Enable IRQ interrupts
+ MSR CPSR_c,R0
+ BX LR
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/GetInterruptsState.S b/roms/edk2/MdePkg/Library/BaseLib/Arm/GetInterruptsState.S new file mode 100644 index 000000000..d5ee7d0e2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/GetInterruptsState.S @@ -0,0 +1,37 @@ +#------------------------------------------------------------------------------
+#
+# GetInterruptState() function for ARM
+#
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT (GetInterruptState)
+
+#/**
+# Retrieves the current CPU interrupt state.
+#
+# Returns TRUE is interrupts are currently enabled. Otherwise
+# returns FALSE.
+#
+# @retval TRUE CPU interrupts are enabled.
+# @retval FALSE CPU interrupts are disabled.
+#
+#**/
+#
+#BOOLEAN
+#EFIAPI
+#GetInterruptState (
+# VOID
+# );
+#
+ASM_PFX(GetInterruptState):
+ mrs R0, CPSR
+ tst R0, #0x80 @Check if IRQ is enabled.
+ moveq R0, #1
+ movne R0, #0
+ bx LR
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/GetInterruptsState.asm b/roms/edk2/MdePkg/Library/BaseLib/Arm/GetInterruptsState.asm new file mode 100644 index 000000000..af7b9d6c6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/GetInterruptsState.asm @@ -0,0 +1,39 @@ +;------------------------------------------------------------------------------
+;
+; GetInterruptState() function for ARM
+;
+; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT GetInterruptState
+
+ AREA Interrupt_enable, CODE, READONLY
+
+;/**
+; Retrieves the current CPU interrupt state.
+;
+; Returns TRUE is interrupts are currently enabled. Otherwise
+; returns FALSE.
+;
+; @retval TRUE CPU interrupts are enabled.
+; @retval FALSE CPU interrupts are disabled.
+;
+;**/
+;
+;BOOLEAN
+;EFIAPI
+;GetInterruptState (
+; VOID
+; );
+;
+GetInterruptState
+ MRS R0, CPSR
+ TST R0, #0x80 ;Check if IRQ is enabled.
+ MOVEQ R0, #1
+ MOVNE R0, #0
+ BX LR
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/InternalSwitchStack.c b/roms/edk2/MdePkg/Library/BaseLib/Arm/InternalSwitchStack.c new file mode 100644 index 000000000..3fe1125b6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/InternalSwitchStack.c @@ -0,0 +1,73 @@ +/** @file
+ SwitchStack() function for ARM.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Transfers control to a function starting with a new stack.
+
+ This internal worker function transfers control to the function
+ specified by EntryPoint using the new stack specified by NewStack,
+ and passes in the parameters specified by Context1 and Context2.
+ Context1 and Context2 are optional and may be NULL.
+ The function EntryPoint must never return.
+
+ @param EntryPoint The pointer to the function to enter.
+ @param Context1 The first parameter to pass in.
+ @param Context2 The second Parameter to pass in
+ @param NewStack The new Location of the stack
+
+**/
+VOID
+EFIAPI
+InternalSwitchStackAsm (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack
+ );
+
+
+/**
+ Transfers control to a function starting with a new stack.
+
+ Transfers control to the function specified by EntryPoint using the
+ new stack specified by NewStack, and passes in the parameters specified
+ by Context1 and Context2. Context1 and Context2 are optional and may
+ be NULL. The function EntryPoint must never return.
+ Marker will be ignored on IA-32, x64, and EBC.
+ IPF CPUs expect one additional parameter of type VOID * that specifies
+ the new backing store pointer.
+
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ @param EntryPoint A pointer to function to call with the new stack.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function.
+ @param Marker A VA_LIST marker for the variable argument list.
+
+**/
+VOID
+EFIAPI
+InternalSwitchStack (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack,
+ IN VA_LIST Marker
+ )
+
+{
+ InternalSwitchStackAsm (EntryPoint, Context1, Context2, NewStack);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/Math64.S b/roms/edk2/MdePkg/Library/BaseLib/Arm/Math64.S new file mode 100755 index 000000000..ec12b1015 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/Math64.S @@ -0,0 +1,263 @@ +#------------------------------------------------------------------------------
+#
+# Replacement for Math64.c that is coded to use older GCC intrinsics.
+# Doing this reduces the number of intrinsics that are required when
+# you port to a new version of gcc.
+#
+# Need to split this into multple files to size optimize the image.
+#
+# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+ .text
+ .align 2
+ GCC_ASM_EXPORT(InternalMathLShiftU64)
+
+ASM_PFX(InternalMathLShiftU64):
+ stmfd sp!, {r4, r5, r6}
+ mov r6, r1
+ rsb ip, r2, #32
+ mov r4, r6, asl r2
+ subs r1, r2, #32
+ orr r4, r4, r0, lsr ip
+ mov r3, r0, asl r2
+ movpl r4, r0, asl r1
+ mov r5, r0
+ mov r0, r3
+ mov r1, r4
+ ldmfd sp!, {r4, r5, r6}
+ bx lr
+
+ .align 2
+ GCC_ASM_EXPORT(InternalMathRShiftU64)
+
+ASM_PFX(InternalMathRShiftU64):
+ stmfd sp!, {r4, r5, r6}
+ mov r5, r0
+ rsb ip, r2, #32
+ mov r3, r5, lsr r2
+ subs r0, r2, #32
+ orr r3, r3, r1, asl ip
+ mov r4, r1, lsr r2
+ movpl r3, r1, lsr r0
+ mov r6, r1
+ mov r0, r3
+ mov r1, r4
+ ldmfd sp!, {r4, r5, r6}
+ bx lr
+
+ .align 2
+ GCC_ASM_EXPORT(InternalMathARShiftU64)
+
+ASM_PFX(InternalMathARShiftU64):
+ stmfd sp!, {r4, r5, r6}
+ mov r5, r0
+ rsb ip, r2, #32
+ mov r3, r5, lsr r2
+ subs r0, r2, #32
+ orr r3, r3, r1, asl ip
+ mov r4, r1, asr r2
+ movpl r3, r1, asr r0
+ mov r6, r1
+ mov r0, r3
+ mov r1, r4
+ ldmfd sp!, {r4, r5, r6}
+ bx lr
+
+ .align 2
+ GCC_ASM_EXPORT(InternalMathLRotU64)
+
+ASM_PFX(InternalMathLRotU64):
+ stmfd sp!, {r4, r5, r6, r7, lr}
+ add r7, sp, #12
+ mov r6, r1
+ rsb ip, r2, #32
+ mov r4, r6, asl r2
+ rsb lr, r2, #64
+ subs r1, r2, #32
+ orr r4, r4, r0, lsr ip
+ mov r3, r0, asl r2
+ movpl r4, r0, asl r1
+ sub ip, r2, #32
+ mov r5, r0
+ mov r0, r0, lsr lr
+ rsbs r2, r2, #32
+ orr r0, r0, r6, asl ip
+ mov r1, r6, lsr lr
+ movpl r0, r6, lsr r2
+ orr r1, r1, r4
+ orr r0, r0, r3
+ ldmfd sp!, {r4, r5, r6, r7, pc}
+
+
+ .align 2
+ GCC_ASM_EXPORT(InternalMathRRotU64)
+
+ASM_PFX(InternalMathRRotU64):
+ stmfd sp!, {r4, r5, r6, r7, lr}
+ add r7, sp, #12
+ mov r5, r0
+ rsb ip, r2, #32
+ mov r3, r5, lsr r2
+ rsb lr, r2, #64
+ subs r0, r2, #32
+ orr r3, r3, r1, asl ip
+ mov r4, r1, lsr r2
+ movpl r3, r1, lsr r0
+ sub ip, r2, #32
+ mov r6, r1
+ mov r1, r1, asl lr
+ rsbs r2, r2, #32
+ orr r1, r1, r5, lsr ip
+ mov r0, r5, asl lr
+ movpl r1, r5, asl r2
+ orr r0, r0, r3
+ orr r1, r1, r4
+ ldmfd sp!, {r4, r5, r6, r7, pc}
+
+ .align 2
+ GCC_ASM_EXPORT(InternalMathMultU64x32)
+
+ASM_PFX(InternalMathMultU64x32):
+ stmfd sp!, {r7, lr}
+ add r7, sp, #0
+ mov r3, #0
+ mov ip, r0
+ mov lr, r1
+ umull r0, r1, ip, r2
+ mla r1, lr, r2, r1
+ mla r1, ip, r3, r1
+ ldmfd sp!, {r7, pc}
+
+ .align 2
+ GCC_ASM_EXPORT(InternalMathMultU64x64)
+
+ASM_PFX(InternalMathMultU64x64):
+ stmfd sp!, {r7, lr}
+ add r7, sp, #0
+ mov ip, r0
+ mov lr, r1
+ umull r0, r1, ip, r2
+ mla r1, lr, r2, r1
+ mla r1, ip, r3, r1
+ ldmfd sp!, {r7, pc}
+
+ .align 2
+ GCC_ASM_EXPORT(InternalMathDivU64x32)
+
+ASM_PFX(InternalMathDivU64x32):
+ stmfd sp!, {r7, lr}
+ add r7, sp, #0
+ mov r3, #0
+ bl ASM_PFX(__udivdi3)
+ ldmfd sp!, {r7, pc}
+
+
+ .align 2
+ GCC_ASM_EXPORT(InternalMathModU64x32)
+
+ASM_PFX(InternalMathModU64x32):
+ stmfd sp!, {r7, lr}
+ add r7, sp, #0
+ mov r3, #0
+ bl ASM_PFX(__umoddi3)
+ ldmfd sp!, {r7, pc}
+
+
+ .align 2
+ GCC_ASM_EXPORT(InternalMathDivRemU64x32)
+
+ASM_PFX(InternalMathDivRemU64x32):
+ stmfd sp!, {r4, r5, r6, r7, lr}
+ add r7, sp, #12
+ stmfd sp!, {r10, r11}
+ subs r6, r3, #0
+ mov r10, r0
+ mov r11, r1
+ moveq r4, r2
+ moveq r5, #0
+ beq L22
+ mov r4, r2
+ mov r5, #0
+ mov r3, #0
+ bl ASM_PFX(__umoddi3)
+ str r0, [r6, #0]
+L22:
+ mov r0, r10
+ mov r1, r11
+ mov r2, r4
+ mov r3, r5
+ bl ASM_PFX(__udivdi3)
+ ldmfd sp!, {r10, r11}
+ ldmfd sp!, {r4, r5, r6, r7, pc}
+
+
+ .align 2
+ GCC_ASM_EXPORT(InternalMathDivRemU64x64)
+
+ASM_PFX(InternalMathDivRemU64x64):
+ stmfd sp!, {r4, r5, r6, r7, lr}
+ add r7, sp, #12
+ stmfd sp!, {r10, r11}
+ ldr r6, [sp, #28]
+ mov r4, r0
+ cmp r6, #0
+ mov r5, r1
+ mov r10, r2
+ mov r11, r3
+ beq L26
+ bl ASM_PFX(__umoddi3)
+ stmia r6, {r0-r1}
+L26:
+ mov r0, r4
+ mov r1, r5
+ mov r2, r10
+ mov r3, r11
+ bl ASM_PFX(__udivdi3)
+ ldmfd sp!, {r10, r11}
+ ldmfd sp!, {r4, r5, r6, r7, pc}
+
+
+ .align 2
+ GCC_ASM_EXPORT(InternalMathDivRemS64x64)
+
+ASM_PFX(InternalMathDivRemS64x64):
+ stmfd sp!, {r4, r5, r6, r7, lr}
+ add r7, sp, #12
+ stmfd sp!, {r10, r11}
+ ldr r6, [sp, #28]
+ mov r4, r0
+ cmp r6, #0
+ mov r5, r1
+ mov r10, r2
+ mov r11, r3
+ beq L30
+ bl ASM_PFX(__moddi3)
+ stmia r6, {r0-r1}
+L30:
+ mov r0, r4
+ mov r1, r5
+ mov r2, r10
+ mov r3, r11
+ bl ASM_PFX(__divdi3)
+ ldmfd sp!, {r10, r11}
+ ldmfd sp!, {r4, r5, r6, r7, pc}
+
+
+ .align 2
+ GCC_ASM_EXPORT(InternalMathSwapBytes64)
+
+ASM_PFX(InternalMathSwapBytes64):
+ stmfd sp!, {r4, r5, r7, lr}
+ mov r5, r1
+ bl ASM_PFX(SwapBytes32)
+ mov r4, r0
+ mov r0, r5
+ bl ASM_PFX(SwapBytes32)
+ mov r1, r4
+ ldmfd sp!, {r4, r5, r7, pc}
+
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/MemoryFence.S b/roms/edk2/MdePkg/Library/BaseLib/Arm/MemoryFence.S new file mode 100644 index 000000000..8bf1a7505 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/MemoryFence.S @@ -0,0 +1,33 @@ +##------------------------------------------------------------------------------
+#
+# MemoryFence() for AArch64
+#
+# Copyright (c) 2013, ARM Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##------------------------------------------------------------------------------
+
+.text
+.p2align 2
+
+GCC_ASM_EXPORT(MemoryFence)
+
+
+#/**
+# Used to serialize load and store operations.
+#
+# All loads and stores that proceed calls to this function are guaranteed to be
+# globally visible when this function returns.
+#
+#**/
+#VOID
+#EFIAPI
+#MemoryFence (
+# VOID
+# );
+#
+ASM_PFX(MemoryFence):
+ // System wide Data Memory Barrier.
+ dmb
+ bx lr
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/MemoryFence.asm b/roms/edk2/MdePkg/Library/BaseLib/Arm/MemoryFence.asm new file mode 100644 index 000000000..e751584aa --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/MemoryFence.asm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; MemoryFence() for AArch64
+;
+; Copyright (c) 2013, ARM Ltd. All rights reserved.
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT MemoryFence
+
+ AREA MemoryBarriers, CODE, READONLY
+
+;/**
+; Used to serialize load and store operations.
+;
+; All loads and stores that proceed calls to this function are guaranteed to be
+; globally visible when this function returns.
+;
+;**/
+;VOID
+;EFIAPI
+;MemoryFence (
+; VOID
+; );
+;
+MemoryFence FUNCTION
+ dmb
+ bx lr
+ ENDFUNC
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/SetJumpLongJump.S b/roms/edk2/MdePkg/Library/BaseLib/Arm/SetJumpLongJump.S new file mode 100644 index 000000000..82d94faf6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/SetJumpLongJump.S @@ -0,0 +1,64 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+.text
+.p2align 2
+
+GCC_ASM_EXPORT(SetJump)
+GCC_ASM_EXPORT(InternalLongJump)
+
+#/**
+# Saves the current CPU context that can be restored with a call to LongJump() and returns 0.#
+#
+# Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
+# call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
+# value to be returned by SetJump().
+#
+# If JumpBuffer is NULL, then ASSERT().
+# For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
+#
+# @param JumpBuffer A pointer to CPU context buffer.
+#
+#**/
+#
+#UINTN
+#EFIAPI
+#SetJump (
+# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // R0
+# );
+#
+ASM_PFX(SetJump):
+ mov r3, r13
+ stmia r0, {r3-r12,r14}
+ eor r0, r0, r0
+ bx lr
+
+#/**
+# Restores the CPU context that was saved with SetJump().#
+#
+# Restores the CPU context from the buffer specified by JumpBuffer.
+# This function never returns to the caller.
+# Instead is resumes execution based on the state of JumpBuffer.
+#
+# @param JumpBuffer A pointer to CPU context buffer.
+# @param Value The value to return when the SetJump() context is restored.
+#
+#**/
+#VOID
+#EFIAPI
+#InternalLongJump (
+# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // R0
+# IN UINTN Value // R1
+# );
+#
+ASM_PFX(InternalLongJump):
+ ldmia r0, {r3-r12,r14}
+ mov r13, r3
+ mov r0, r1
+ bx lr
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/SetJumpLongJump.asm b/roms/edk2/MdePkg/Library/BaseLib/Arm/SetJumpLongJump.asm new file mode 100644 index 000000000..936f722be --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/SetJumpLongJump.asm @@ -0,0 +1,64 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT SetJump
+ EXPORT InternalLongJump
+
+ AREA BaseLib, CODE, READONLY
+
+;/**
+; Saves the current CPU context that can be restored with a call to LongJump() and returns 0.;
+;
+; Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
+; call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
+; value to be returned by SetJump().
+;
+; If JumpBuffer is NULL, then ASSERT().
+; For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
+;
+; @param JumpBuffer A pointer to CPU context buffer.
+;
+;**/
+;
+;UINTN
+;EFIAPI
+;SetJump (
+; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // R0
+; )
+;
+SetJump
+ MOV R3, R13
+ STM R0, {R3-R12,R14}
+ EOR R0, R0
+ BX LR
+
+;/**
+; Restores the CPU context that was saved with SetJump().;
+;
+; Restores the CPU context from the buffer specified by JumpBuffer.
+; This function never returns to the caller.
+; Instead is resumes execution based on the state of JumpBuffer.
+;
+; @param JumpBuffer A pointer to CPU context buffer.
+; @param Value The value to return when the SetJump() context is restored.
+;
+;**/
+;VOID
+;EFIAPI
+;InternalLongJump (
+; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // R0
+; IN UINTN Value // R1
+; );
+;
+InternalLongJump
+ LDM R0, {R3-R12,R14}
+ MOV R13, R3
+ MOV R0, R1
+ BX LR
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/SpeculationBarrier.S b/roms/edk2/MdePkg/Library/BaseLib/Arm/SpeculationBarrier.S new file mode 100644 index 000000000..73f8105e3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/SpeculationBarrier.S @@ -0,0 +1,33 @@ +##------------------------------------------------------------------------------
+#
+# SpeculationBarrier() for AArch64
+#
+# Copyright (c) 2019, Linaro Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##------------------------------------------------------------------------------
+
+.text
+.p2align 2
+
+GCC_ASM_EXPORT(SpeculationBarrier)
+
+
+#/**
+# Uses as a barrier to stop speculative execution.
+#
+# Ensures that no later instruction will execute speculatively, until all prior
+# instructions have completed.
+#
+#**/
+#VOID
+#EFIAPI
+#SpeculationBarrier (
+# VOID
+# );
+#
+ASM_PFX(SpeculationBarrier):
+ dsb
+ isb
+ bx lr
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/SpeculationBarrier.asm b/roms/edk2/MdePkg/Library/BaseLib/Arm/SpeculationBarrier.asm new file mode 100644 index 000000000..01a64346f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/SpeculationBarrier.asm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; SpeculationBarrier() for AArch64
+;
+; Copyright (c) 2019, Linaro Ltd. All rights reserved.
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT SpeculationBarrier
+
+ AREA MemoryBarriers, CODE, READONLY
+
+;/**
+; Uses as a barrier to stop speculative execution.
+;
+; Ensures that no later instruction will execute speculatively, until all prior
+; instructions have completed.
+;
+;**/
+;VOID
+;EFIAPI
+;SpeculationBarrier (
+; VOID
+; );
+;
+SpeculationBarrier
+ dsb
+ isb
+ bx lr
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/SwitchStack.S b/roms/edk2/MdePkg/Library/BaseLib/Arm/SwitchStack.S new file mode 100644 index 000000000..844c9a27f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/SwitchStack.S @@ -0,0 +1,62 @@ +//------------------------------------------------------------------------------
+//
+// Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+// Portions copyright (c) 2011, ARM Limited. All rights reserved.<BR>
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+.text
+.align 5
+
+GCC_ASM_EXPORT(InternalSwitchStackAsm)
+GCC_ASM_EXPORT(CpuPause)
+
+/**
+//
+// This allows the caller to switch the stack and goes to the new entry point
+//
+// @param EntryPoint The pointer to the location to enter
+// @param Context Parameter to pass in
+// @param Context2 Parameter2 to pass in
+// @param NewStack New Location of the stack
+//
+// @return Nothing. Goes to the Entry Point passing in the new parameters
+//
+VOID
+EFIAPI
+InternalSwitchStackAsm (
+ SWITCH_STACK_ENTRY_POINT EntryPoint,
+ VOID *Context,
+ VOID *Context2,
+ VOID *NewStack
+ );
+**/
+ASM_PFX(InternalSwitchStackAsm):
+ MOV LR, R0
+ MOV SP, R3
+ MOV R0, R1
+ MOV R1, R2
+ BX LR
+
+/**
+//
+// Requests CPU to pause for a short period of time.
+//
+// Requests CPU to pause for a short period of time. Typically used in MP
+// systems to prevent memory starvation while waiting for a spin lock.
+//
+VOID
+EFIAPI
+CpuPause (
+ VOID
+ )
+**/
+ASM_PFX(CpuPause):
+ nop
+ nop
+ nop
+ nop
+ nop
+ BX LR
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/SwitchStack.asm b/roms/edk2/MdePkg/Library/BaseLib/Arm/SwitchStack.asm new file mode 100644 index 000000000..690f632e6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/SwitchStack.asm @@ -0,0 +1,39 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT InternalSwitchStackAsm
+
+ AREA Switch_Stack, CODE, READONLY
+
+;/**
+; This allows the caller to switch the stack and goes to the new entry point
+;
+; @param EntryPoint The pointer to the location to enter
+; @param Context Parameter to pass in
+; @param Context2 Parameter2 to pass in
+; @param NewStack New Location of the stack
+;
+; @return Nothing. Goes to the Entry Point passing in the new parameters
+;
+;**/
+;VOID
+;EFIAPI
+;InternalSwitchStackAsm (
+; SWITCH_STACK_ENTRY_POINT EntryPoint,
+; VOID *Context,
+; VOID *Context2,
+; VOID *NewStack
+; );
+;
+InternalSwitchStackAsm
+ MOV LR, R0
+ MOV SP, R3
+ MOV R0, R1
+ MOV R1, R2
+ BX LR
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Arm/Unaligned.c b/roms/edk2/MdePkg/Library/BaseLib/Arm/Unaligned.c new file mode 100644 index 000000000..e9934e700 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Arm/Unaligned.c @@ -0,0 +1,246 @@ +/** @file
+ Unaligned access functions of BaseLib for ARM.
+
+ volatile was added to work around optimization issues.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Reads a 16-bit value from memory that may be unaligned.
+
+ This function returns the 16-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer The pointer to a 16-bit value that may be unaligned.
+
+ @return The 16-bit value read from Buffer.
+
+**/
+UINT16
+EFIAPI
+ReadUnaligned16 (
+ IN CONST UINT16 *Buffer
+ )
+{
+ volatile UINT8 LowerByte;
+ volatile UINT8 HigherByte;
+
+ ASSERT (Buffer != NULL);
+
+ LowerByte = ((UINT8*)Buffer)[0];
+ HigherByte = ((UINT8*)Buffer)[1];
+
+ return (UINT16)(LowerByte | (HigherByte << 8));
+}
+
+/**
+ Writes a 16-bit value to memory that may be unaligned.
+
+ This function writes the 16-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer The pointer to a 16-bit value that may be unaligned.
+ @param Value 16-bit value to write to Buffer.
+
+ @return The 16-bit value to write to Buffer.
+
+**/
+UINT16
+EFIAPI
+WriteUnaligned16 (
+ OUT UINT16 *Buffer,
+ IN UINT16 Value
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ ((volatile UINT8*)Buffer)[0] = (UINT8)Value;
+ ((volatile UINT8*)Buffer)[1] = (UINT8)(Value >> 8);
+
+ return Value;
+}
+
+/**
+ Reads a 24-bit value from memory that may be unaligned.
+
+ This function returns the 24-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer The pointer to a 24-bit value that may be unaligned.
+
+ @return The 24-bit value read from Buffer.
+
+**/
+UINT32
+EFIAPI
+ReadUnaligned24 (
+ IN CONST UINT32 *Buffer
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ return (UINT32)(
+ ReadUnaligned16 ((UINT16*)Buffer) |
+ (((UINT8*)Buffer)[2] << 16)
+ );
+}
+
+/**
+ Writes a 24-bit value to memory that may be unaligned.
+
+ This function writes the 24-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer The pointer to a 24-bit value that may be unaligned.
+ @param Value 24-bit value to write to Buffer.
+
+ @return The 24-bit value to write to Buffer.
+
+**/
+UINT32
+EFIAPI
+WriteUnaligned24 (
+ OUT UINT32 *Buffer,
+ IN UINT32 Value
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
+ *(UINT8*)((UINT16*)Buffer + 1) = (UINT8)(Value >> 16);
+ return Value;
+}
+
+/**
+ Reads a 32-bit value from memory that may be unaligned.
+
+ This function returns the 32-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer The pointer to a 32-bit value that may be unaligned.
+
+ @return The 32-bit value read from Buffer.
+
+**/
+UINT32
+EFIAPI
+ReadUnaligned32 (
+ IN CONST UINT32 *Buffer
+ )
+{
+ UINT16 LowerBytes;
+ UINT16 HigherBytes;
+
+ ASSERT (Buffer != NULL);
+
+ LowerBytes = ReadUnaligned16 ((UINT16*) Buffer);
+ HigherBytes = ReadUnaligned16 ((UINT16*) Buffer + 1);
+
+ return (UINT32) (LowerBytes | (HigherBytes << 16));
+}
+
+/**
+ Writes a 32-bit value to memory that may be unaligned.
+
+ This function writes the 32-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer The pointer to a 32-bit value that may be unaligned.
+ @param Value 32-bit value to write to Buffer.
+
+ @return The 32-bit value to write to Buffer.
+
+**/
+UINT32
+EFIAPI
+WriteUnaligned32 (
+ OUT UINT32 *Buffer,
+ IN UINT32 Value
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
+ WriteUnaligned16 ((UINT16*)Buffer + 1, (UINT16)(Value >> 16));
+ return Value;
+}
+
+/**
+ Reads a 64-bit value from memory that may be unaligned.
+
+ This function returns the 64-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer The pointer to a 64-bit value that may be unaligned.
+
+ @return The 64-bit value read from Buffer.
+
+**/
+UINT64
+EFIAPI
+ReadUnaligned64 (
+ IN CONST UINT64 *Buffer
+ )
+{
+ UINT32 LowerBytes;
+ UINT32 HigherBytes;
+
+ ASSERT (Buffer != NULL);
+
+ LowerBytes = ReadUnaligned32 ((UINT32*) Buffer);
+ HigherBytes = ReadUnaligned32 ((UINT32*) Buffer + 1);
+
+ return (UINT64) (LowerBytes | LShiftU64 (HigherBytes, 32));
+}
+
+/**
+ Writes a 64-bit value to memory that may be unaligned.
+
+ This function writes the 64-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer The pointer to a 64-bit value that may be unaligned.
+ @param Value 64-bit value to write to Buffer.
+
+ @return The 64-bit value to write to Buffer.
+
+**/
+UINT64
+EFIAPI
+WriteUnaligned64 (
+ OUT UINT64 *Buffer,
+ IN UINT64 Value
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ WriteUnaligned32 ((UINT32*)Buffer, (UINT32)Value);
+ WriteUnaligned32 ((UINT32*)Buffer + 1, (UINT32)RShiftU64 (Value, 32));
+ return Value;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/BaseLib.inf b/roms/edk2/MdePkg/Library/BaseLib/BaseLib.inf new file mode 100644 index 000000000..3b85c56c3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/BaseLib.inf @@ -0,0 +1,422 @@ +## @file
+# Base Library implementation.
+#
+# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseLib
+ MODULE_UNI_FILE = BaseLib.uni
+ FILE_GUID = 27d67720-ea68-48ae-93da-a3a074c90e30
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.1
+ LIBRARY_CLASS = BaseLib
+
+#
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
+#
+
+[Sources]
+ CheckSum.c
+ SwitchStack.c
+ SwapBytes64.c
+ SwapBytes32.c
+ SwapBytes16.c
+ LongJump.c
+ SetJump.c
+ RShiftU64.c
+ RRotU64.c
+ RRotU32.c
+ MultU64x64.c
+ MultU64x32.c
+ MultS64x64.c
+ ModU64x32.c
+ LShiftU64.c
+ LRotU64.c
+ LRotU32.c
+ LowBitSet64.c
+ LowBitSet32.c
+ HighBitSet64.c
+ HighBitSet32.c
+ GetPowerOfTwo64.c
+ GetPowerOfTwo32.c
+ DivU64x64Remainder.c
+ DivU64x32Remainder.c
+ DivU64x32.c
+ DivS64x64Remainder.c
+ ARShiftU64.c
+ BitField.c
+ CpuDeadLoop.c
+ Cpu.c
+ LinkedList.c
+ SafeString.c
+ String.c
+ FilePaths.c
+ BaseLibInternals.h
+
+[Sources.Ia32]
+ Ia32/WriteTr.nasm
+ Ia32/Lfence.nasm
+
+ Ia32/Wbinvd.c | MSFT
+ Ia32/WriteMm7.c | MSFT
+ Ia32/WriteMm6.c | MSFT
+ Ia32/WriteMm5.c | MSFT
+ Ia32/WriteMm4.c | MSFT
+ Ia32/WriteMm3.c | MSFT
+ Ia32/WriteMm2.c | MSFT
+ Ia32/WriteMm1.c | MSFT
+ Ia32/WriteMm0.c | MSFT
+ Ia32/WriteLdtr.c | MSFT
+ Ia32/WriteIdtr.c | MSFT
+ Ia32/WriteGdtr.c | MSFT
+ Ia32/WriteDr7.c | MSFT
+ Ia32/WriteDr6.c | MSFT
+ Ia32/WriteDr5.c | MSFT
+ Ia32/WriteDr4.c | MSFT
+ Ia32/WriteDr3.c | MSFT
+ Ia32/WriteDr2.c | MSFT
+ Ia32/WriteDr1.c | MSFT
+ Ia32/WriteDr0.c | MSFT
+ Ia32/WriteCr4.c | MSFT
+ Ia32/WriteCr3.c | MSFT
+ Ia32/WriteCr2.c | MSFT
+ Ia32/WriteCr0.c | MSFT
+ Ia32/WriteMsr64.c | MSFT
+ Ia32/SwapBytes64.c | MSFT
+ Ia32/RRotU64.c | MSFT
+ Ia32/RShiftU64.c | MSFT
+ Ia32/ReadPmc.c | MSFT
+ Ia32/ReadTsc.c | MSFT
+ Ia32/ReadLdtr.c | MSFT
+ Ia32/ReadIdtr.c | MSFT
+ Ia32/ReadGdtr.c | MSFT
+ Ia32/ReadTr.c | MSFT
+ Ia32/ReadSs.c | MSFT
+ Ia32/ReadGs.c | MSFT
+ Ia32/ReadFs.c | MSFT
+ Ia32/ReadEs.c | MSFT
+ Ia32/ReadDs.c | MSFT
+ Ia32/ReadCs.c | MSFT
+ Ia32/ReadMsr64.c | MSFT
+ Ia32/ReadMm7.c | MSFT
+ Ia32/ReadMm6.c | MSFT
+ Ia32/ReadMm5.c | MSFT
+ Ia32/ReadMm4.c | MSFT
+ Ia32/ReadMm3.c | MSFT
+ Ia32/ReadMm2.c | MSFT
+ Ia32/ReadMm1.c | MSFT
+ Ia32/ReadMm0.c | MSFT
+ Ia32/ReadEflags.c | MSFT
+ Ia32/ReadDr7.c | MSFT
+ Ia32/ReadDr6.c | MSFT
+ Ia32/ReadDr5.c | MSFT
+ Ia32/ReadDr4.c | MSFT
+ Ia32/ReadDr3.c | MSFT
+ Ia32/ReadDr2.c | MSFT
+ Ia32/ReadDr1.c | MSFT
+ Ia32/ReadDr0.c | MSFT
+ Ia32/ReadCr4.c | MSFT
+ Ia32/ReadCr3.c | MSFT
+ Ia32/ReadCr2.c | MSFT
+ Ia32/ReadCr0.c | MSFT
+ Ia32/Mwait.c | MSFT
+ Ia32/Monitor.c | MSFT
+ Ia32/ModU64x32.c | MSFT
+ Ia32/MultU64x64.c | MSFT
+ Ia32/MultU64x32.c | MSFT
+ Ia32/LShiftU64.c | MSFT
+ Ia32/LRotU64.c | MSFT
+ Ia32/Invd.c | MSFT
+ Ia32/FxRestore.c | MSFT
+ Ia32/FxSave.c | MSFT
+ Ia32/FlushCacheLine.c | MSFT
+ Ia32/EnablePaging32.c | MSFT
+ Ia32/EnableInterrupts.c | MSFT
+ Ia32/EnableDisableInterrupts.c | MSFT
+ Ia32/DivU64x32Remainder.c | MSFT
+ Ia32/DivU64x32.c | MSFT
+ Ia32/DisablePaging32.c | MSFT
+ Ia32/DisableInterrupts.c | MSFT
+ Ia32/CpuPause.c | MSFT
+ Ia32/CpuIdEx.c | MSFT
+ Ia32/CpuId.c | MSFT
+ Ia32/CpuBreakpoint.c | MSFT
+ Ia32/ARShiftU64.c | MSFT
+ Ia32/EnableCache.c | MSFT
+ Ia32/DisableCache.c | MSFT
+
+
+ Ia32/GccInline.c | GCC
+ Ia32/GccInlinePriv.c | GCC
+ Ia32/Thunk16.nasm
+ Ia32/EnableDisableInterrupts.nasm| GCC
+ Ia32/EnablePaging64.nasm
+ Ia32/DisablePaging32.nasm| GCC
+ Ia32/EnablePaging32.nasm| GCC
+ Ia32/Mwait.nasm| GCC
+ Ia32/Monitor.nasm| GCC
+ Ia32/CpuIdEx.nasm| GCC
+ Ia32/CpuId.nasm| GCC
+ Ia32/LongJump.nasm
+ Ia32/SetJump.nasm
+ Ia32/SwapBytes64.nasm| GCC
+ Ia32/DivU64x64Remainder.nasm
+ Ia32/DivU64x32Remainder.nasm| GCC
+ Ia32/ModU64x32.nasm| GCC
+ Ia32/DivU64x32.nasm| GCC
+ Ia32/MultU64x64.nasm| GCC
+ Ia32/MultU64x32.nasm| GCC
+ Ia32/RRotU64.nasm| GCC
+ Ia32/LRotU64.nasm| GCC
+ Ia32/ARShiftU64.nasm| GCC
+ Ia32/RShiftU64.nasm| GCC
+ Ia32/LShiftU64.nasm| GCC
+ Ia32/EnableCache.nasm| GCC
+ Ia32/DisableCache.nasm| GCC
+ Ia32/RdRand.nasm
+ Ia32/XGetBv.nasm
+ Ia32/VmgExit.nasm
+
+ Ia32/DivS64x64Remainder.c
+ Ia32/InternalSwitchStack.c | MSFT
+ Ia32/InternalSwitchStack.nasm | GCC
+ Ia32/Non-existing.c
+ Unaligned.c
+ X86WriteIdtr.c
+ X86WriteGdtr.c
+ X86Thunk.c
+ X86ReadIdtr.c
+ X86ReadGdtr.c
+ X86Msr.c
+ X86MemoryFence.c | MSFT
+ X86GetInterruptState.c
+ X86FxSave.c
+ X86FxRestore.c
+ X86EnablePaging64.c
+ X86EnablePaging32.c
+ X86DisablePaging64.c
+ X86DisablePaging32.c
+ X86RdRand.c
+ X86PatchInstruction.c
+ X86SpeculationBarrier.c
+
+[Sources.X64]
+ X64/Thunk16.nasm
+ X64/CpuIdEx.nasm
+ X64/CpuId.nasm
+ X64/LongJump.nasm
+ X64/SetJump.nasm
+ X64/SwitchStack.nasm
+ X64/EnableCache.nasm
+ X64/DisableCache.nasm
+ X64/WriteTr.nasm
+ X64/Lfence.nasm
+
+ X64/CpuBreakpoint.c | MSFT
+ X64/WriteMsr64.c | MSFT
+ X64/ReadMsr64.c | MSFT
+ X64/CpuPause.nasm| MSFT
+ X64/DisableInterrupts.nasm| MSFT
+ X64/EnableInterrupts.nasm| MSFT
+ X64/FlushCacheLine.nasm| MSFT
+ X64/Invd.nasm| MSFT
+ X64/Wbinvd.nasm| MSFT
+ X64/Mwait.nasm| MSFT
+ X64/Monitor.nasm| MSFT
+ X64/ReadPmc.nasm| MSFT
+ X64/ReadTsc.nasm| MSFT
+ X64/WriteMm7.nasm| MSFT
+ X64/WriteMm6.nasm| MSFT
+ X64/WriteMm5.nasm| MSFT
+ X64/WriteMm4.nasm| MSFT
+ X64/WriteMm3.nasm| MSFT
+ X64/WriteMm2.nasm| MSFT
+ X64/WriteMm1.nasm| MSFT
+ X64/WriteMm0.nasm| MSFT
+ X64/ReadMm7.nasm| MSFT
+ X64/ReadMm6.nasm| MSFT
+ X64/ReadMm5.nasm| MSFT
+ X64/ReadMm4.nasm| MSFT
+ X64/ReadMm3.nasm| MSFT
+ X64/ReadMm2.nasm| MSFT
+ X64/ReadMm1.nasm| MSFT
+ X64/ReadMm0.nasm| MSFT
+ X64/FxRestore.nasm| MSFT
+ X64/FxSave.nasm| MSFT
+ X64/WriteLdtr.nasm| MSFT
+ X64/ReadLdtr.nasm| MSFT
+ X64/WriteIdtr.nasm| MSFT
+ X64/ReadIdtr.nasm| MSFT
+ X64/WriteGdtr.nasm| MSFT
+ X64/ReadGdtr.nasm| MSFT
+ X64/ReadTr.nasm| MSFT
+ X64/ReadSs.nasm| MSFT
+ X64/ReadGs.nasm| MSFT
+ X64/ReadFs.nasm| MSFT
+ X64/ReadEs.nasm| MSFT
+ X64/ReadDs.nasm| MSFT
+ X64/ReadCs.nasm| MSFT
+ X64/WriteDr7.nasm| MSFT
+ X64/WriteDr6.nasm| MSFT
+ X64/WriteDr5.nasm| MSFT
+ X64/WriteDr4.nasm| MSFT
+ X64/WriteDr3.nasm| MSFT
+ X64/WriteDr2.nasm| MSFT
+ X64/WriteDr1.nasm| MSFT
+ X64/WriteDr0.nasm| MSFT
+ X64/ReadDr7.nasm| MSFT
+ X64/ReadDr6.nasm| MSFT
+ X64/ReadDr5.nasm| MSFT
+ X64/ReadDr4.nasm| MSFT
+ X64/ReadDr3.nasm| MSFT
+ X64/ReadDr2.nasm| MSFT
+ X64/ReadDr1.nasm| MSFT
+ X64/ReadDr0.nasm| MSFT
+ X64/WriteCr4.nasm| MSFT
+ X64/WriteCr3.nasm| MSFT
+ X64/WriteCr2.nasm| MSFT
+ X64/WriteCr0.nasm| MSFT
+ X64/ReadCr4.nasm| MSFT
+ X64/ReadCr3.nasm| MSFT
+ X64/ReadCr2.nasm| MSFT
+ X64/ReadCr0.nasm| MSFT
+ X64/ReadEflags.nasm| MSFT
+
+
+ X64/Non-existing.c
+ Math64.c
+ Unaligned.c
+ X86WriteIdtr.c
+ X86WriteGdtr.c
+ X86Thunk.c
+ X86ReadIdtr.c
+ X86ReadGdtr.c
+ X86Msr.c
+ X86MemoryFence.c | MSFT
+ X86GetInterruptState.c
+ X86FxSave.c
+ X86FxRestore.c
+ X86EnablePaging64.c
+ X86EnablePaging32.c
+ X86DisablePaging64.c
+ X86DisablePaging32.c
+ X86RdRand.c
+ X86PatchInstruction.c
+ X86SpeculationBarrier.c
+ X64/GccInline.c | GCC
+ X64/GccInlinePriv.c | GCC
+ X64/EnableDisableInterrupts.nasm
+ X64/DisablePaging64.nasm
+ X64/RdRand.nasm
+ X64/XGetBv.nasm
+ X64/VmgExit.nasm
+ ChkStkGcc.c | GCC
+
+[Sources.EBC]
+ Ebc/CpuBreakpoint.c
+ Ebc/SetJumpLongJump.c
+ Ebc/SwitchStack.c
+ Ebc/SpeculationBarrier.c
+ Unaligned.c
+ Math64.c
+
+[Sources.ARM]
+ Arm/InternalSwitchStack.c
+ Arm/Unaligned.c
+ Math64.c | RVCT
+ Math64.c | MSFT
+
+ Arm/SwitchStack.asm | RVCT
+ Arm/SetJumpLongJump.asm | RVCT
+ Arm/DisableInterrupts.asm | RVCT
+ Arm/EnableInterrupts.asm | RVCT
+ Arm/GetInterruptsState.asm | RVCT
+ Arm/CpuPause.asm | RVCT
+ Arm/CpuBreakpoint.asm | RVCT
+ Arm/MemoryFence.asm | RVCT
+ Arm/SpeculationBarrier.S | RVCT
+
+ Arm/SwitchStack.asm | MSFT
+ Arm/SetJumpLongJump.asm | MSFT
+ Arm/DisableInterrupts.asm | MSFT
+ Arm/EnableInterrupts.asm | MSFT
+ Arm/GetInterruptsState.asm | MSFT
+ Arm/CpuPause.asm | MSFT
+ Arm/CpuBreakpoint.asm | MSFT
+ Arm/MemoryFence.asm | MSFT
+ Arm/SpeculationBarrier.asm | MSFT
+
+ Arm/Math64.S | GCC
+ Arm/SwitchStack.S | GCC
+ Arm/EnableInterrupts.S | GCC
+ Arm/DisableInterrupts.S | GCC
+ Arm/GetInterruptsState.S | GCC
+ Arm/SetJumpLongJump.S | GCC
+ Arm/CpuBreakpoint.S | GCC
+ Arm/MemoryFence.S | GCC
+ Arm/SpeculationBarrier.S | GCC
+
+[Sources.AARCH64]
+ Arm/InternalSwitchStack.c
+ Arm/Unaligned.c
+ Math64.c
+
+ AArch64/MemoryFence.S | GCC
+ AArch64/SwitchStack.S | GCC
+ AArch64/EnableInterrupts.S | GCC
+ AArch64/DisableInterrupts.S | GCC
+ AArch64/GetInterruptsState.S | GCC
+ AArch64/SetJumpLongJump.S | GCC
+ AArch64/CpuBreakpoint.S | GCC
+ AArch64/SpeculationBarrier.S | GCC
+
+ AArch64/MemoryFence.asm | MSFT
+ AArch64/SwitchStack.asm | MSFT
+ AArch64/EnableInterrupts.asm | MSFT
+ AArch64/DisableInterrupts.asm | MSFT
+ AArch64/GetInterruptsState.asm | MSFT
+ AArch64/SetJumpLongJump.asm | MSFT
+ AArch64/CpuBreakpoint.asm | MSFT
+ AArch64/SpeculationBarrier.asm | MSFT
+
+[Sources.RISCV64]
+ Math64.c
+ Unaligned.c
+ RiscV64/InternalSwitchStack.c
+ RiscV64/CpuBreakpoint.c
+ RiscV64/GetInterruptState.c
+ RiscV64/DisableInterrupts.c
+ RiscV64/EnableInterrupts.c
+ RiscV64/CpuPause.c
+ RiscV64/RiscVSetJumpLongJump.S | GCC
+ RiscV64/RiscVCpuBreakpoint.S | GCC
+ RiscV64/RiscVCpuPause.S | GCC
+ RiscV64/RiscVInterrupt.S | GCC
+ RiscV64/FlushCache.S | GCC
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ PcdLib
+ DebugLib
+ BaseMemoryLib
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength ## SOMETIMES_CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength ## SOMETIMES_CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength ## SOMETIMES_CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask ## SOMETIMES_CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType ## SOMETIMES_CONSUMES
+
+[FeaturePcd]
+ gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList ## CONSUMES
diff --git a/roms/edk2/MdePkg/Library/BaseLib/BaseLib.uni b/roms/edk2/MdePkg/Library/BaseLib/BaseLib.uni new file mode 100644 index 000000000..3a1b2e744 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/BaseLib.uni @@ -0,0 +1,18 @@ +// /** @file
+// Base Library implementation.
+//
+// Base Library implementation.
+//
+// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+// Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Base Library implementation"
+
+#string STR_MODULE_DESCRIPTION #language en-US "Base Library implementation."
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/BaseLibInternals.h b/roms/edk2/MdePkg/Library/BaseLib/BaseLibInternals.h new file mode 100644 index 000000000..6837d67d9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/BaseLibInternals.h @@ -0,0 +1,869 @@ +/** @file
+ Declaration of internal functions in BaseLib.
+
+ Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __BASE_LIB_INTERNALS__
+#define __BASE_LIB_INTERNALS__
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+//
+// Math functions
+//
+
+/**
+ Shifts a 64-bit integer left between 0 and 63 bits. The low bits
+ are filled with zeros. The shifted value is returned.
+
+ This function shifts the 64-bit value Operand to the left by Count bits. The
+ low Count bits are set to zero. The shifted value is returned.
+
+ @param Operand The 64-bit operand to shift left.
+ @param Count The number of bits to shift left.
+
+ @return Operand << Count
+
+**/
+UINT64
+EFIAPI
+InternalMathLShiftU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ );
+
+/**
+ Shifts a 64-bit integer right between 0 and 63 bits. The high bits
+ are filled with zeros. The shifted value is returned.
+
+ This function shifts the 64-bit value Operand to the right by Count bits. The
+ high Count bits are set to zero. The shifted value is returned.
+
+ @param Operand The 64-bit operand to shift right.
+ @param Count The number of bits to shift right.
+
+ @return Operand >> Count
+
+**/
+UINT64
+EFIAPI
+InternalMathRShiftU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ );
+
+/**
+ Shifts a 64-bit integer right between 0 and 63 bits. The high bits
+ are filled with original integer's bit 63. The shifted value is returned.
+
+ This function shifts the 64-bit value Operand to the right by Count bits. The
+ high Count bits are set to bit 63 of Operand. The shifted value is returned.
+
+ @param Operand The 64-bit operand to shift right.
+ @param Count The number of bits to shift right.
+
+ @return Operand arithmetically shifted right by Count
+
+**/
+UINT64
+EFIAPI
+InternalMathARShiftU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ );
+
+/**
+ Rotates a 64-bit integer left between 0 and 63 bits, filling
+ the low bits with the high bits that were rotated.
+
+ This function rotates the 64-bit value Operand to the left by Count bits. The
+ low Count bits are filled with the high Count bits of Operand. The rotated
+ value is returned.
+
+ @param Operand The 64-bit operand to rotate left.
+ @param Count The number of bits to rotate left.
+
+ @return Operand <<< Count
+
+**/
+UINT64
+EFIAPI
+InternalMathLRotU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ );
+
+/**
+ Rotates a 64-bit integer right between 0 and 63 bits, filling
+ the high bits with the high low bits that were rotated.
+
+ This function rotates the 64-bit value Operand to the right by Count bits.
+ The high Count bits are filled with the low Count bits of Operand. The rotated
+ value is returned.
+
+ @param Operand The 64-bit operand to rotate right.
+ @param Count The number of bits to rotate right.
+
+ @return Operand >>> Count
+
+**/
+UINT64
+EFIAPI
+InternalMathRRotU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ );
+
+/**
+ Switches the endianess of a 64-bit integer.
+
+ This function swaps the bytes in a 64-bit unsigned value to switch the value
+ from little endian to big endian or vice versa. The byte swapped value is
+ returned.
+
+ @param Operand A 64-bit unsigned value.
+
+ @return The byte swapped Operand.
+
+**/
+UINT64
+EFIAPI
+InternalMathSwapBytes64 (
+ IN UINT64 Operand
+ );
+
+/**
+ Multiplies a 64-bit unsigned integer by a 32-bit unsigned integer
+ and generates a 64-bit unsigned result.
+
+ This function multiplies the 64-bit unsigned value Multiplicand by the 32-bit
+ unsigned value Multiplier and generates a 64-bit unsigned result. This 64-
+ bit unsigned result is returned.
+
+ @param Multiplicand A 64-bit unsigned value.
+ @param Multiplier A 32-bit unsigned value.
+
+ @return Multiplicand * Multiplier
+
+**/
+UINT64
+EFIAPI
+InternalMathMultU64x32 (
+ IN UINT64 Multiplicand,
+ IN UINT32 Multiplier
+ );
+
+/**
+ Multiplies a 64-bit unsigned integer by a 64-bit unsigned integer
+ and generates a 64-bit unsigned result.
+
+ This function multiples the 64-bit unsigned value Multiplicand by the 64-bit
+ unsigned value Multiplier and generates a 64-bit unsigned result. This 64-
+ bit unsigned result is returned.
+
+ @param Multiplicand A 64-bit unsigned value.
+ @param Multiplier A 64-bit unsigned value.
+
+ @return Multiplicand * Multiplier
+
+**/
+UINT64
+EFIAPI
+InternalMathMultU64x64 (
+ IN UINT64 Multiplicand,
+ IN UINT64 Multiplier
+ );
+
+/**
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and
+ generates a 64-bit unsigned result.
+
+ This function divides the 64-bit unsigned value Dividend by the 32-bit
+ unsigned value Divisor and generates a 64-bit unsigned quotient. This
+ function returns the 64-bit unsigned quotient.
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 32-bit unsigned value.
+
+ @return Dividend / Divisor
+
+**/
+UINT64
+EFIAPI
+InternalMathDivU64x32 (
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
+ );
+
+/**
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and
+ generates a 32-bit unsigned remainder.
+
+ This function divides the 64-bit unsigned value Dividend by the 32-bit
+ unsigned value Divisor and generates a 32-bit remainder. This function
+ returns the 32-bit unsigned remainder.
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 32-bit unsigned value.
+
+ @return Dividend % Divisor
+
+**/
+UINT32
+EFIAPI
+InternalMathModU64x32 (
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
+ );
+
+/**
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and
+ generates a 64-bit unsigned result and an optional 32-bit unsigned remainder.
+
+ This function divides the 64-bit unsigned value Dividend by the 32-bit
+ unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder
+ is not NULL, then the 32-bit unsigned remainder is returned in Remainder.
+ This function returns the 64-bit unsigned quotient.
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 32-bit unsigned value.
+ @param Remainder A pointer to a 32-bit unsigned value. This parameter is
+ optional and may be NULL.
+
+ @return Dividend / Divisor
+
+**/
+UINT64
+EFIAPI
+InternalMathDivRemU64x32 (
+ IN UINT64 Dividend,
+ IN UINT32 Divisor,
+ OUT UINT32 *Remainder OPTIONAL
+ );
+
+/**
+ Divides a 64-bit unsigned integer by a 64-bit unsigned integer and
+ generates a 64-bit unsigned result and an optional 64-bit unsigned remainder.
+
+ This function divides the 64-bit unsigned value Dividend by the 64-bit
+ unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder
+ is not NULL, then the 64-bit unsigned remainder is returned in Remainder.
+ This function returns the 64-bit unsigned quotient.
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 64-bit unsigned value.
+ @param Remainder A pointer to a 64-bit unsigned value. This parameter is
+ optional and may be NULL.
+
+ @return Dividend / Divisor
+
+**/
+UINT64
+EFIAPI
+InternalMathDivRemU64x64 (
+ IN UINT64 Dividend,
+ IN UINT64 Divisor,
+ OUT UINT64 *Remainder OPTIONAL
+ );
+
+/**
+ Divides a 64-bit signed integer by a 64-bit signed integer and
+ generates a 64-bit signed result and an optional 64-bit signed remainder.
+
+ This function divides the 64-bit signed value Dividend by the 64-bit
+ signed value Divisor and generates a 64-bit signed quotient. If Remainder
+ is not NULL, then the 64-bit signed remainder is returned in Remainder.
+ This function returns the 64-bit signed quotient.
+
+ @param Dividend A 64-bit signed value.
+ @param Divisor A 64-bit signed value.
+ @param Remainder A pointer to a 64-bit signed value. This parameter is
+ optional and may be NULL.
+
+ @return Dividend / Divisor
+
+**/
+INT64
+EFIAPI
+InternalMathDivRemS64x64 (
+ IN INT64 Dividend,
+ IN INT64 Divisor,
+ OUT INT64 *Remainder OPTIONAL
+ );
+
+/**
+ Transfers control to a function starting with a new stack.
+
+ Transfers control to the function specified by EntryPoint using the
+ new stack specified by NewStack and passing in the parameters specified
+ by Context1 and Context2. Context1 and Context2 are optional and may
+ be NULL. The function EntryPoint must never return.
+ Marker will be ignored on IA-32, x64, and EBC.
+ IPF CPUs expect one additional parameter of type VOID * that specifies
+ the new backing store pointer.
+
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ @param EntryPoint A pointer to function to call with the new stack.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function.
+ @param Marker VA_LIST marker for the variable argument list.
+
+**/
+VOID
+EFIAPI
+InternalSwitchStack (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack,
+ IN VA_LIST Marker
+ );
+
+
+/**
+ Worker function that returns a bit field from Operand.
+
+ Returns the bitfield specified by the StartBit and the EndBit from Operand.
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+
+ @return The bit field read.
+
+**/
+UINTN
+EFIAPI
+BitFieldReadUint (
+ IN UINTN Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+
+/**
+ Worker function that reads a bit field from Operand, performs a bitwise OR,
+ and returns the result.
+
+ Performs a bitwise OR between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData. All other bits in Operand are
+ preserved. The new value is returned.
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ @param OrData The value to OR with the read value from the value
+
+ @return The new value.
+
+**/
+UINTN
+EFIAPI
+BitFieldOrUint (
+ IN UINTN Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINTN OrData
+ );
+
+
+/**
+ Worker function that reads a bit field from Operand, performs a bitwise AND,
+ and returns the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData. All other bits in Operand are
+ preserved. The new value is returned.
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ @param AndData The value to And with the read value from the value
+
+ @return The new value.
+
+**/
+UINTN
+EFIAPI
+BitFieldAndUint (
+ IN UINTN Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINTN AndData
+ );
+
+
+/**
+ Worker function that checks ASSERT condition for JumpBuffer
+
+ Checks ASSERT condition for JumpBuffer.
+
+ If JumpBuffer is NULL, then ASSERT().
+ For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
+
+ @param JumpBuffer A pointer to CPU context buffer.
+
+**/
+VOID
+EFIAPI
+InternalAssertJumpBuffer (
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer
+ );
+
+
+/**
+ Restores the CPU context that was saved with SetJump().
+
+ Restores the CPU context from the buffer specified by JumpBuffer.
+ This function never returns to the caller.
+ Instead is resumes execution based on the state of JumpBuffer.
+
+ @param JumpBuffer A pointer to CPU context buffer.
+ @param Value The value to return when the SetJump() context is restored.
+
+**/
+VOID
+EFIAPI
+InternalLongJump (
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,
+ IN UINTN Value
+ );
+
+
+/**
+ Check if a Unicode character is a decimal character.
+
+ This internal function checks if a Unicode character is a
+ decimal character. The valid decimal character is from
+ L'0' to L'9'.
+
+ @param Char The character to check against.
+
+ @retval TRUE If the Char is a decmial character.
+ @retval FALSE If the Char is not a decmial character.
+
+**/
+BOOLEAN
+EFIAPI
+InternalIsDecimalDigitCharacter (
+ IN CHAR16 Char
+ );
+
+
+/**
+ Convert a Unicode character to numerical value.
+
+ This internal function only deal with Unicode character
+ which maps to a valid hexadecimal ASII character, i.e.
+ L'0' to L'9', L'a' to L'f' or L'A' to L'F'. For other
+ Unicode character, the value returned does not make sense.
+
+ @param Char The character to convert.
+
+ @return The numerical value converted.
+
+**/
+UINTN
+EFIAPI
+InternalHexCharToUintn (
+ IN CHAR16 Char
+ );
+
+
+/**
+ Check if a Unicode character is a hexadecimal character.
+
+ This internal function checks if a Unicode character is a
+ decimal character. The valid hexadecimal character is
+ L'0' to L'9', L'a' to L'f', or L'A' to L'F'.
+
+
+ @param Char The character to check against.
+
+ @retval TRUE If the Char is a hexadecmial character.
+ @retval FALSE If the Char is not a hexadecmial character.
+
+**/
+BOOLEAN
+EFIAPI
+InternalIsHexaDecimalDigitCharacter (
+ IN CHAR16 Char
+ );
+
+
+/**
+ Check if a ASCII character is a decimal character.
+
+ This internal function checks if a Unicode character is a
+ decimal character. The valid decimal character is from
+ '0' to '9'.
+
+ @param Char The character to check against.
+
+ @retval TRUE If the Char is a decmial character.
+ @retval FALSE If the Char is not a decmial character.
+
+**/
+BOOLEAN
+EFIAPI
+InternalAsciiIsDecimalDigitCharacter (
+ IN CHAR8 Char
+ );
+
+
+/**
+ Check if a ASCII character is a hexadecimal character.
+
+ This internal function checks if a ASCII character is a
+ decimal character. The valid hexadecimal character is
+ L'0' to L'9', L'a' to L'f', or L'A' to L'F'.
+
+
+ @param Char The character to check against.
+
+ @retval TRUE If the Char is a hexadecmial character.
+ @retval FALSE If the Char is not a hexadecmial character.
+
+**/
+BOOLEAN
+EFIAPI
+InternalAsciiIsHexaDecimalDigitCharacter (
+ IN CHAR8 Char
+ );
+
+
+/**
+ Convert a ASCII character to numerical value.
+
+ This internal function only deal with Unicode character
+ which maps to a valid hexadecimal ASII character, i.e.
+ '0' to '9', 'a' to 'f' or 'A' to 'F'. For other
+ ASCII character, the value returned does not make sense.
+
+ @param Char The character to convert.
+
+ @return The numerical value converted.
+
+**/
+UINTN
+EFIAPI
+InternalAsciiHexCharToUintn (
+ IN CHAR8 Char
+ );
+
+
+//
+// Ia32 and x64 specific functions
+//
+#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
+
+/**
+ Reads the current Global Descriptor Table Register(GDTR) descriptor.
+
+ Reads and returns the current GDTR descriptor and returns it in Gdtr. This
+ function is only available on IA-32 and x64.
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86ReadGdtr (
+ OUT IA32_DESCRIPTOR *Gdtr
+ );
+
+/**
+ Writes the current Global Descriptor Table Register (GDTR) descriptor.
+
+ Writes and the current GDTR descriptor specified by Gdtr. This function is
+ only available on IA-32 and x64.
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86WriteGdtr (
+ IN CONST IA32_DESCRIPTOR *Gdtr
+ );
+
+/**
+ Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.
+
+ Reads and returns the current IDTR descriptor and returns it in Idtr. This
+ function is only available on IA-32 and x64.
+
+ @param Idtr The pointer to an IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86ReadIdtr (
+ OUT IA32_DESCRIPTOR *Idtr
+ );
+
+/**
+ Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.
+
+ Writes the current IDTR descriptor and returns it in Idtr. This function is
+ only available on IA-32 and x64.
+
+ @param Idtr The pointer to an IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86WriteIdtr (
+ IN CONST IA32_DESCRIPTOR *Idtr
+ );
+
+/**
+ Save the current floating point/SSE/SSE2 context to a buffer.
+
+ Saves the current floating point/SSE/SSE2 state to the buffer specified by
+ Buffer. Buffer must be aligned on a 16-byte boundary. This function is only
+ available on IA-32 and x64.
+
+ @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context.
+
+**/
+VOID
+EFIAPI
+InternalX86FxSave (
+ OUT IA32_FX_BUFFER *Buffer
+ );
+
+/**
+ Restores the current floating point/SSE/SSE2 context from a buffer.
+
+ Restores the current floating point/SSE/SSE2 state from the buffer specified
+ by Buffer. Buffer must be aligned on a 16-byte boundary. This function is
+ only available on IA-32 and x64.
+
+ @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context.
+
+**/
+VOID
+EFIAPI
+InternalX86FxRestore (
+ IN CONST IA32_FX_BUFFER *Buffer
+ );
+
+/**
+ Enables the 32-bit paging mode on the CPU.
+
+ Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode. This function is
+ only available on IA-32. After the 32-bit paging mode is enabled, control is
+ transferred to the function specified by EntryPoint using the new stack
+ specified by NewStack and passing in the parameters specified by Context1 and
+ Context2. Context1 and Context2 are optional and may be NULL. The function
+ EntryPoint must never return.
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit protected mode with flat descriptors. This
+ means all descriptors must have a base of 0 and a limit of 4GB.
+ 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat
+ descriptors.
+ 4) CR3 must point to valid page tables that will be used once the transition
+ is complete, and those page tables must guarantee that the pages for this
+ function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is enabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is enabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is enabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+InternalX86EnablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack
+ );
+
+/**
+ Disables the 32-bit paging mode on the CPU.
+
+ Disables the 32-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 32-paged protected
+ mode. This function is only available on IA-32. After the 32-bit paging mode
+ is disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be NULL. The function EntryPoint must never return.
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit paged mode.
+ 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.
+ 4) CR3 must point to valid page tables that guarantee that the pages for
+ this function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is disabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is disabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is
+ disabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+InternalX86DisablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack
+ );
+
+/**
+ Enables the 64-bit paging mode on the CPU.
+
+ Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode with flat
+ descriptors. This function is only available on IA-32. After the 64-bit
+ paging mode is enabled, control is transferred to the function specified by
+ EntryPoint using the new stack specified by NewStack and passing in the
+ parameters specified by Context1 and Context2. Context1 and Context2 are
+ optional and may be 0. The function EntryPoint must never return.
+
+ @param Cs The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for long mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is enabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is enabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is enabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+InternalX86EnablePaging64 (
+ IN UINT16 Cs,
+ IN UINT64 EntryPoint,
+ IN UINT64 Context1, OPTIONAL
+ IN UINT64 Context2, OPTIONAL
+ IN UINT64 NewStack
+ );
+
+/**
+ Disables the 64-bit paging mode on the CPU.
+
+ Disables the 64-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 64-paging mode.
+ This function is only available on x64. After the 64-bit paging mode is
+ disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be 0. The function EntryPoint must never return.
+
+ @param Cs The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for 32-bit protected mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is disabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is disabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is disabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+InternalX86DisablePaging64 (
+ IN UINT16 Cs,
+ IN UINT32 EntryPoint,
+ IN UINT32 Context1, OPTIONAL
+ IN UINT32 Context2, OPTIONAL
+ IN UINT32 NewStack
+ );
+
+/**
+ Generates a 16-bit random number through RDRAND instruction.
+
+ @param[out] Rand Buffer pointer to store the random result.
+
+ @retval TRUE RDRAND call was successful.
+ @retval FALSE Failed attempts to call RDRAND.
+
+ **/
+BOOLEAN
+EFIAPI
+InternalX86RdRand16 (
+ OUT UINT16 *Rand
+ );
+
+/**
+ Generates a 32-bit random number through RDRAND instruction.
+
+ @param[out] Rand Buffer pointer to store the random result.
+
+ @retval TRUE RDRAND call was successful.
+ @retval FALSE Failed attempts to call RDRAND.
+
+**/
+BOOLEAN
+EFIAPI
+InternalX86RdRand32 (
+ OUT UINT32 *Rand
+ );
+
+/**
+ Generates a 64-bit random number through RDRAND instruction.
+
+
+ @param[out] Rand Buffer pointer to store the random result.
+
+ @retval TRUE RDRAND call was successful.
+ @retval FALSE Failed attempts to call RDRAND.
+
+**/
+BOOLEAN
+EFIAPI
+InternalX86RdRand64 (
+ OUT UINT64 *Rand
+ );
+
+#else
+
+#endif
+
+#endif
diff --git a/roms/edk2/MdePkg/Library/BaseLib/BitField.c b/roms/edk2/MdePkg/Library/BaseLib/BitField.c new file mode 100644 index 000000000..0f48a036b --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/BitField.c @@ -0,0 +1,1002 @@ +/** @file
+ Bit field functions of BaseLib.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Worker function that returns a bit field from Operand.
+
+ Returns the bitfield specified by the StartBit and the EndBit from Operand.
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+
+ @return The bit field read.
+
+**/
+UINTN
+EFIAPI
+InternalBaseLibBitFieldReadUint (
+ IN UINTN Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ //
+ // ~((UINTN)-2 << EndBit) is a mask in which bit[0] thru bit[EndBit]
+ // are 1's while bit[EndBit + 1] thru the most significant bit are 0's.
+ //
+ return (Operand & ~((UINTN)-2 << EndBit)) >> StartBit;
+}
+
+/**
+ Worker function that reads a bit field from Operand, performs a bitwise OR,
+ and returns the result.
+
+ Performs a bitwise OR between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData. All other bits in Operand are
+ preserved. The new value is returned.
+
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ @param OrData The value to OR with the read value from the value.
+
+ @return The new value.
+
+**/
+UINTN
+EFIAPI
+InternalBaseLibBitFieldOrUint (
+ IN UINTN Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINTN OrData
+ )
+{
+ //
+ // Higher bits in OrData those are not used must be zero.
+ //
+ // EndBit - StartBit + 1 might be 32 while the result right shifting 32 on a 32bit integer is undefined,
+ // So the logic is updated to right shift (EndBit - StartBit) bits and compare the last bit directly.
+ //
+ ASSERT ((OrData >> (EndBit - StartBit)) == ((OrData >> (EndBit - StartBit)) & 1));
+
+ //
+ // ~((UINTN)-2 << EndBit) is a mask in which bit[0] thru bit[EndBit]
+ // are 1's while bit[EndBit + 1] thru the most significant bit are 0's.
+ //
+ return Operand | ((OrData << StartBit) & ~((UINTN) -2 << EndBit));
+}
+
+/**
+ Worker function that reads a bit field from Operand, performs a bitwise AND,
+ and returns the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData. All other bits in Operand are
+ preserved. The new value is returned.
+
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ @param AndData The value to And with the read value from the value.
+
+ @return The new value.
+
+**/
+UINTN
+EFIAPI
+InternalBaseLibBitFieldAndUint (
+ IN UINTN Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINTN AndData
+ )
+{
+ //
+ // Higher bits in AndData those are not used must be zero.
+ //
+ // EndBit - StartBit + 1 might be 32 while the result right shifting 32 on a 32bit integer is undefined,
+ // So the logic is updated to right shift (EndBit - StartBit) bits and compare the last bit directly.
+ //
+ ASSERT ((AndData >> (EndBit - StartBit)) == ((AndData >> (EndBit - StartBit)) & 1));
+
+ //
+ // ~((UINTN)-2 << EndBit) is a mask in which bit[0] thru bit[EndBit]
+ // are 1's while bit[EndBit + 1] thru the most significant bit are 0's.
+ //
+ return Operand & ~((~AndData << StartBit) & ~((UINTN)-2 << EndBit));
+}
+
+/**
+ Returns a bit field from an 8-bit value.
+
+ Returns the bitfield specified by the StartBit and the EndBit from Operand.
+
+ If 8-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The bit field read.
+
+**/
+UINT8
+EFIAPI
+BitFieldRead8 (
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ ASSERT (EndBit < 8);
+ ASSERT (StartBit <= EndBit);
+ return (UINT8)InternalBaseLibBitFieldReadUint (Operand, StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to an 8-bit value, and returns the result.
+
+ Writes Value to the bit field specified by the StartBit and the EndBit in
+ Operand. All other bits in Operand are preserved. The new 8-bit value is
+ returned.
+
+ If 8-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value The new value of the bit field.
+
+ @return The new 8-bit value.
+
+**/
+UINT8
+EFIAPI
+BitFieldWrite8 (
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ ASSERT (EndBit < 8);
+ ASSERT (StartBit <= EndBit);
+ return BitFieldAndThenOr8 (Operand, StartBit, EndBit, 0, Value);
+}
+
+/**
+ Reads a bit field from an 8-bit value, performs a bitwise OR, and returns the
+ result.
+
+ Performs a bitwise OR between the bit field specified by StartBit
+ and EndBit in Operand and the value specified by OrData. All other bits in
+ Operand are preserved. The new 8-bit value is returned.
+
+ If 8-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the read value from the value.
+
+ @return The new 8-bit value.
+
+**/
+UINT8
+EFIAPI
+BitFieldOr8 (
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ ASSERT (EndBit < 8);
+ ASSERT (StartBit <= EndBit);
+ return (UINT8)InternalBaseLibBitFieldOrUint (Operand, StartBit, EndBit, OrData);
+}
+
+/**
+ Reads a bit field from an 8-bit value, performs a bitwise AND, and returns
+ the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData. All other bits in Operand are
+ preserved. The new 8-bit value is returned.
+
+ If 8-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the read value from the value.
+
+ @return The new 8-bit value.
+
+**/
+UINT8
+EFIAPI
+BitFieldAnd8 (
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ )
+{
+ ASSERT (EndBit < 8);
+ ASSERT (StartBit <= EndBit);
+ return (UINT8)InternalBaseLibBitFieldAndUint (Operand, StartBit, EndBit, AndData);
+}
+
+/**
+ Reads a bit field from an 8-bit value, performs a bitwise AND followed by a
+ bitwise OR, and returns the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData, followed by a bitwise
+ OR with value specified by OrData. All other bits in Operand are
+ preserved. The new 8-bit value is returned.
+
+ If 8-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the read value from the value.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The new 8-bit value.
+
+**/
+UINT8
+EFIAPI
+BitFieldAndThenOr8 (
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ ASSERT (EndBit < 8);
+ ASSERT (StartBit <= EndBit);
+ return BitFieldOr8 (
+ BitFieldAnd8 (Operand, StartBit, EndBit, AndData),
+ StartBit,
+ EndBit,
+ OrData
+ );
+}
+
+/**
+ Returns a bit field from a 16-bit value.
+
+ Returns the bitfield specified by the StartBit and the EndBit from Operand.
+
+ If 16-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The bit field read.
+
+**/
+UINT16
+EFIAPI
+BitFieldRead16 (
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ ASSERT (EndBit < 16);
+ ASSERT (StartBit <= EndBit);
+ return (UINT16)InternalBaseLibBitFieldReadUint (Operand, StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a 16-bit value, and returns the result.
+
+ Writes Value to the bit field specified by the StartBit and the EndBit in
+ Operand. All other bits in Operand are preserved. The new 16-bit value is
+ returned.
+
+ If 16-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value The new value of the bit field.
+
+ @return The new 16-bit value.
+
+**/
+UINT16
+EFIAPI
+BitFieldWrite16 (
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ )
+{
+ ASSERT (EndBit < 16);
+ ASSERT (StartBit <= EndBit);
+ return BitFieldAndThenOr16 (Operand, StartBit, EndBit, 0, Value);
+}
+
+/**
+ Reads a bit field from a 16-bit value, performs a bitwise OR, and returns the
+ result.
+
+ Performs a bitwise OR between the bit field specified by StartBit
+ and EndBit in Operand and the value specified by OrData. All other bits in
+ Operand are preserved. The new 16-bit value is returned.
+
+ If 16-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the read value from the value.
+
+ @return The new 16-bit value.
+
+**/
+UINT16
+EFIAPI
+BitFieldOr16 (
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ )
+{
+ ASSERT (EndBit < 16);
+ ASSERT (StartBit <= EndBit);
+ return (UINT16)InternalBaseLibBitFieldOrUint (Operand, StartBit, EndBit, OrData);
+}
+
+/**
+ Reads a bit field from a 16-bit value, performs a bitwise AND, and returns
+ the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData. All other bits in Operand are
+ preserved. The new 16-bit value is returned.
+
+ If 16-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the read value from the value.
+
+ @return The new 16-bit value.
+
+**/
+UINT16
+EFIAPI
+BitFieldAnd16 (
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ )
+{
+ ASSERT (EndBit < 16);
+ ASSERT (StartBit <= EndBit);
+ return (UINT16)InternalBaseLibBitFieldAndUint (Operand, StartBit, EndBit, AndData);
+}
+
+/**
+ Reads a bit field from a 16-bit value, performs a bitwise AND followed by a
+ bitwise OR, and returns the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData, followed by a bitwise
+ OR with value specified by OrData. All other bits in Operand are
+ preserved. The new 16-bit value is returned.
+
+ If 16-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the read value from the value.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The new 16-bit value.
+
+**/
+UINT16
+EFIAPI
+BitFieldAndThenOr16 (
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ ASSERT (EndBit < 16);
+ ASSERT (StartBit <= EndBit);
+ return BitFieldOr16 (
+ BitFieldAnd16 (Operand, StartBit, EndBit, AndData),
+ StartBit,
+ EndBit,
+ OrData
+ );
+}
+
+/**
+ Returns a bit field from a 32-bit value.
+
+ Returns the bitfield specified by the StartBit and the EndBit from Operand.
+
+ If 32-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The bit field read.
+
+**/
+UINT32
+EFIAPI
+BitFieldRead32 (
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ ASSERT (EndBit < 32);
+ ASSERT (StartBit <= EndBit);
+ return (UINT32)InternalBaseLibBitFieldReadUint (Operand, StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a 32-bit value, and returns the result.
+
+ Writes Value to the bit field specified by the StartBit and the EndBit in
+ Operand. All other bits in Operand are preserved. The new 32-bit value is
+ returned.
+
+ If 32-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value The new value of the bit field.
+
+ @return The new 32-bit value.
+
+**/
+UINT32
+EFIAPI
+BitFieldWrite32 (
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ ASSERT (EndBit < 32);
+ ASSERT (StartBit <= EndBit);
+ return BitFieldAndThenOr32 (Operand, StartBit, EndBit, 0, Value);
+}
+
+/**
+ Reads a bit field from a 32-bit value, performs a bitwise OR, and returns the
+ result.
+
+ Performs a bitwise OR between the bit field specified by StartBit
+ and EndBit in Operand and the value specified by OrData. All other bits in
+ Operand are preserved. The new 32-bit value is returned.
+
+ If 32-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the read value from the value.
+
+ @return The new 32-bit value.
+
+**/
+UINT32
+EFIAPI
+BitFieldOr32 (
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ ASSERT (EndBit < 32);
+ ASSERT (StartBit <= EndBit);
+ return (UINT32)InternalBaseLibBitFieldOrUint (Operand, StartBit, EndBit, OrData);
+}
+
+/**
+ Reads a bit field from a 32-bit value, performs a bitwise AND, and returns
+ the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData. All other bits in Operand are
+ preserved. The new 32-bit value is returned.
+
+ If 32-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the read value from the value.
+
+ @return The new 32-bit value.
+
+**/
+UINT32
+EFIAPI
+BitFieldAnd32 (
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ ASSERT (EndBit < 32);
+ ASSERT (StartBit <= EndBit);
+ return (UINT32)InternalBaseLibBitFieldAndUint (Operand, StartBit, EndBit, AndData);
+}
+
+/**
+ Reads a bit field from a 32-bit value, performs a bitwise AND followed by a
+ bitwise OR, and returns the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData, followed by a bitwise
+ OR with value specified by OrData. All other bits in Operand are
+ preserved. The new 32-bit value is returned.
+
+ If 32-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the read value from the value.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The new 32-bit value.
+
+**/
+UINT32
+EFIAPI
+BitFieldAndThenOr32 (
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ ASSERT (EndBit < 32);
+ ASSERT (StartBit <= EndBit);
+ return BitFieldOr32 (
+ BitFieldAnd32 (Operand, StartBit, EndBit, AndData),
+ StartBit,
+ EndBit,
+ OrData
+ );
+}
+
+/**
+ Returns a bit field from a 64-bit value.
+
+ Returns the bitfield specified by the StartBit and the EndBit from Operand.
+
+ If 64-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+
+ @return The bit field read.
+
+**/
+UINT64
+EFIAPI
+BitFieldRead64 (
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ ASSERT (EndBit < 64);
+ ASSERT (StartBit <= EndBit);
+ return RShiftU64 (Operand & ~LShiftU64 ((UINT64)-2, EndBit), StartBit);
+}
+
+/**
+ Writes a bit field to a 64-bit value, and returns the result.
+
+ Writes Value to the bit field specified by the StartBit and the EndBit in
+ Operand. All other bits in Operand are preserved. The new 64-bit value is
+ returned.
+
+ If 64-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param Value The new value of the bit field.
+
+ @return The new 64-bit value.
+
+**/
+UINT64
+EFIAPI
+BitFieldWrite64 (
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
+ )
+{
+ ASSERT (EndBit < 64);
+ ASSERT (StartBit <= EndBit);
+ return BitFieldAndThenOr64 (Operand, StartBit, EndBit, 0, Value);
+}
+
+/**
+ Reads a bit field from a 64-bit value, performs a bitwise OR, and returns the
+ result.
+
+ Performs a bitwise OR between the bit field specified by StartBit
+ and EndBit in Operand and the value specified by OrData. All other bits in
+ Operand are preserved. The new 64-bit value is returned.
+
+ If 64-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param OrData The value to OR with the read value from the value
+
+ @return The new 64-bit value.
+
+**/
+UINT64
+EFIAPI
+BitFieldOr64 (
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
+ )
+{
+ UINT64 Value1;
+ UINT64 Value2;
+
+ ASSERT (EndBit < 64);
+ ASSERT (StartBit <= EndBit);
+ //
+ // Higher bits in OrData those are not used must be zero.
+ //
+ // EndBit - StartBit + 1 might be 64 while the result right shifting 64 on RShiftU64() API is invalid,
+ // So the logic is updated to right shift (EndBit - StartBit) bits and compare the last bit directly.
+ //
+ ASSERT (RShiftU64 (OrData, EndBit - StartBit) == (RShiftU64 (OrData, EndBit - StartBit) & 1));
+
+ Value1 = LShiftU64 (OrData, StartBit);
+ Value2 = LShiftU64 ((UINT64) - 2, EndBit);
+
+ return Operand | (Value1 & ~Value2);
+}
+
+/**
+ Reads a bit field from a 64-bit value, performs a bitwise AND, and returns
+ the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData. All other bits in Operand are
+ preserved. The new 64-bit value is returned.
+
+ If 64-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with the read value from the value.
+
+ @return The new 64-bit value.
+
+**/
+UINT64
+EFIAPI
+BitFieldAnd64 (
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
+ )
+{
+ UINT64 Value1;
+ UINT64 Value2;
+
+ ASSERT (EndBit < 64);
+ ASSERT (StartBit <= EndBit);
+ //
+ // Higher bits in AndData those are not used must be zero.
+ //
+ // EndBit - StartBit + 1 might be 64 while the right shifting 64 on RShiftU64() API is invalid,
+ // So the logic is updated to right shift (EndBit - StartBit) bits and compare the last bit directly.
+ //
+ ASSERT (RShiftU64 (AndData, EndBit - StartBit) == (RShiftU64 (AndData, EndBit - StartBit) & 1));
+
+ Value1 = LShiftU64 (~AndData, StartBit);
+ Value2 = LShiftU64 ((UINT64)-2, EndBit);
+
+ return Operand & ~(Value1 & ~Value2);
+}
+
+/**
+ Reads a bit field from a 64-bit value, performs a bitwise AND followed by a
+ bitwise OR, and returns the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData, followed by a bitwise
+ OR with value specified by OrData. All other bits in Operand are
+ preserved. The new 64-bit value is returned.
+
+ If 64-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with the read value from the value.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The new 64-bit value.
+
+**/
+UINT64
+EFIAPI
+BitFieldAndThenOr64 (
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ )
+{
+ ASSERT (EndBit < 64);
+ ASSERT (StartBit <= EndBit);
+ return BitFieldOr64 (
+ BitFieldAnd64 (Operand, StartBit, EndBit, AndData),
+ StartBit,
+ EndBit,
+ OrData
+ );
+}
+
+/**
+ Reads a bit field from a 32-bit value, counts and returns
+ the number of set bits.
+
+ Counts the number of set bits in the bit field specified by
+ StartBit and EndBit in Operand. The count is returned.
+
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The number of bits set between StartBit and EndBit.
+
+**/
+UINT8
+EFIAPI
+BitFieldCountOnes32 (
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ UINT32 Count;
+
+ ASSERT (EndBit < 32);
+ ASSERT (StartBit <= EndBit);
+
+ Count = BitFieldRead32 (Operand, StartBit, EndBit);
+ Count -= ((Count >> 1) & 0x55555555);
+ Count = (Count & 0x33333333) + ((Count >> 2) & 0x33333333);
+ Count += Count >> 4;
+ Count &= 0x0F0F0F0F;
+ Count += Count >> 8;
+ Count += Count >> 16;
+
+ return (UINT8) Count & 0x3F;
+}
+
+/**
+ Reads a bit field from a 64-bit value, counts and returns
+ the number of set bits.
+
+ Counts the number of set bits in the bit field specified by
+ StartBit and EndBit in Operand. The count is returned.
+
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+
+ @return The number of bits set between StartBit and EndBit.
+
+**/
+UINT8
+EFIAPI
+BitFieldCountOnes64 (
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ UINT64 BitField;
+ UINT8 Count;
+
+ ASSERT (EndBit < 64);
+ ASSERT (StartBit <= EndBit);
+
+ BitField = BitFieldRead64 (Operand, StartBit, EndBit);
+ Count = BitFieldCountOnes32 ((UINT32) BitField, 0, 31);
+ Count += BitFieldCountOnes32 ((UINT32) RShiftU64(BitField, 32), 0, 31);
+
+ return Count;
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/CheckSum.c b/roms/edk2/MdePkg/Library/BaseLib/CheckSum.c new file mode 100644 index 000000000..d91a7a07c --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/CheckSum.c @@ -0,0 +1,626 @@ +/** @file
+ Utility functions to generate checksum based on 2's complement
+ algorithm.
+
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Returns the sum of all elements in a buffer in unit of UINT8.
+ During calculation, the carry bits are dropped.
+
+ This function calculates the sum of all elements in a buffer
+ in unit of UINT8. The carry bits in result of addition are dropped.
+ The result is returned as UINT8. If Length is Zero, then Zero is
+ returned.
+
+ If Buffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to carry out the sum operation.
+ @param Length The size, in bytes, of Buffer.
+
+ @return Sum The sum of Buffer with carry bits dropped during additions.
+
+**/
+UINT8
+EFIAPI
+CalculateSum8 (
+ IN CONST UINT8 *Buffer,
+ IN UINTN Length
+ )
+{
+ UINT8 Sum;
+ UINTN Count;
+
+ ASSERT (Buffer != NULL);
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
+
+ for (Sum = 0, Count = 0; Count < Length; Count++) {
+ Sum = (UINT8) (Sum + *(Buffer + Count));
+ }
+
+ return Sum;
+}
+
+
+/**
+ Returns the two's complement checksum of all elements in a buffer
+ of 8-bit values.
+
+ This function first calculates the sum of the 8-bit values in the
+ buffer specified by Buffer and Length. The carry bits in the result
+ of addition are dropped. Then, the two's complement of the sum is
+ returned. If Length is 0, then 0 is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to carry out the checksum operation.
+ @param Length The size, in bytes, of Buffer.
+
+ @return Checksum The 2's complement checksum of Buffer.
+
+**/
+UINT8
+EFIAPI
+CalculateCheckSum8 (
+ IN CONST UINT8 *Buffer,
+ IN UINTN Length
+ )
+{
+ UINT8 CheckSum;
+
+ CheckSum = CalculateSum8 (Buffer, Length);
+
+ //
+ // Return the checksum based on 2's complement.
+ //
+ return (UINT8) (0x100 - CheckSum);
+}
+
+/**
+ Returns the sum of all elements in a buffer of 16-bit values. During
+ calculation, the carry bits are dropped.
+
+ This function calculates the sum of the 16-bit values in the buffer
+ specified by Buffer and Length. The carry bits in result of addition are dropped.
+ The 16-bit result is returned. If Length is 0, then 0 is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().
+ If Length is not aligned on a 16-bit boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to carry out the sum operation.
+ @param Length The size, in bytes, of Buffer.
+
+ @return Sum The sum of Buffer with carry bits dropped during additions.
+
+**/
+UINT16
+EFIAPI
+CalculateSum16 (
+ IN CONST UINT16 *Buffer,
+ IN UINTN Length
+ )
+{
+ UINT16 Sum;
+ UINTN Count;
+ UINTN Total;
+
+ ASSERT (Buffer != NULL);
+ ASSERT (((UINTN) Buffer & 0x1) == 0);
+ ASSERT ((Length & 0x1) == 0);
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
+
+ Total = Length / sizeof (*Buffer);
+ for (Sum = 0, Count = 0; Count < Total; Count++) {
+ Sum = (UINT16) (Sum + *(Buffer + Count));
+ }
+
+ return Sum;
+}
+
+
+/**
+ Returns the two's complement checksum of all elements in a buffer of
+ 16-bit values.
+
+ This function first calculates the sum of the 16-bit values in the buffer
+ specified by Buffer and Length. The carry bits in the result of addition
+ are dropped. Then, the two's complement of the sum is returned. If Length
+ is 0, then 0 is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().
+ If Length is not aligned on a 16-bit boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to carry out the checksum operation.
+ @param Length The size, in bytes, of Buffer.
+
+ @return Checksum The 2's complement checksum of Buffer.
+
+**/
+UINT16
+EFIAPI
+CalculateCheckSum16 (
+ IN CONST UINT16 *Buffer,
+ IN UINTN Length
+ )
+{
+ UINT16 CheckSum;
+
+ CheckSum = CalculateSum16 (Buffer, Length);
+
+ //
+ // Return the checksum based on 2's complement.
+ //
+ return (UINT16) (0x10000 - CheckSum);
+}
+
+
+/**
+ Returns the sum of all elements in a buffer of 32-bit values. During
+ calculation, the carry bits are dropped.
+
+ This function calculates the sum of the 32-bit values in the buffer
+ specified by Buffer and Length. The carry bits in result of addition are dropped.
+ The 32-bit result is returned. If Length is 0, then 0 is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().
+ If Length is not aligned on a 32-bit boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to carry out the sum operation.
+ @param Length The size, in bytes, of Buffer.
+
+ @return Sum The sum of Buffer with carry bits dropped during additions.
+
+**/
+UINT32
+EFIAPI
+CalculateSum32 (
+ IN CONST UINT32 *Buffer,
+ IN UINTN Length
+ )
+{
+ UINT32 Sum;
+ UINTN Count;
+ UINTN Total;
+
+ ASSERT (Buffer != NULL);
+ ASSERT (((UINTN) Buffer & 0x3) == 0);
+ ASSERT ((Length & 0x3) == 0);
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
+
+ Total = Length / sizeof (*Buffer);
+ for (Sum = 0, Count = 0; Count < Total; Count++) {
+ Sum = Sum + *(Buffer + Count);
+ }
+
+ return Sum;
+}
+
+
+/**
+ Returns the two's complement checksum of all elements in a buffer of
+ 32-bit values.
+
+ This function first calculates the sum of the 32-bit values in the buffer
+ specified by Buffer and Length. The carry bits in the result of addition
+ are dropped. Then, the two's complement of the sum is returned. If Length
+ is 0, then 0 is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().
+ If Length is not aligned on a 32-bit boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to carry out the checksum operation.
+ @param Length The size, in bytes, of Buffer.
+
+ @return Checksum The 2's complement checksum of Buffer.
+
+**/
+UINT32
+EFIAPI
+CalculateCheckSum32 (
+ IN CONST UINT32 *Buffer,
+ IN UINTN Length
+ )
+{
+ UINT32 CheckSum;
+
+ CheckSum = CalculateSum32 (Buffer, Length);
+
+ //
+ // Return the checksum based on 2's complement.
+ //
+ return (UINT32) ((UINT32)(-1) - CheckSum + 1);
+}
+
+
+/**
+ Returns the sum of all elements in a buffer of 64-bit values. During
+ calculation, the carry bits are dropped.
+
+ This function calculates the sum of the 64-bit values in the buffer
+ specified by Buffer and Length. The carry bits in result of addition are dropped.
+ The 64-bit result is returned. If Length is 0, then 0 is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().
+ If Length is not aligned on a 64-bit boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to carry out the sum operation.
+ @param Length The size, in bytes, of Buffer.
+
+ @return Sum The sum of Buffer with carry bits dropped during additions.
+
+**/
+UINT64
+EFIAPI
+CalculateSum64 (
+ IN CONST UINT64 *Buffer,
+ IN UINTN Length
+ )
+{
+ UINT64 Sum;
+ UINTN Count;
+ UINTN Total;
+
+ ASSERT (Buffer != NULL);
+ ASSERT (((UINTN) Buffer & 0x7) == 0);
+ ASSERT ((Length & 0x7) == 0);
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
+
+ Total = Length / sizeof (*Buffer);
+ for (Sum = 0, Count = 0; Count < Total; Count++) {
+ Sum = Sum + *(Buffer + Count);
+ }
+
+ return Sum;
+}
+
+
+/**
+ Returns the two's complement checksum of all elements in a buffer of
+ 64-bit values.
+
+ This function first calculates the sum of the 64-bit values in the buffer
+ specified by Buffer and Length. The carry bits in the result of addition
+ are dropped. Then, the two's complement of the sum is returned. If Length
+ is 0, then 0 is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().
+ If Length is not aligned on a 64-bit boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to carry out the checksum operation.
+ @param Length The size, in bytes, of Buffer.
+
+ @return Checksum The 2's complement checksum of Buffer.
+
+**/
+UINT64
+EFIAPI
+CalculateCheckSum64 (
+ IN CONST UINT64 *Buffer,
+ IN UINTN Length
+ )
+{
+ UINT64 CheckSum;
+
+ CheckSum = CalculateSum64 (Buffer, Length);
+
+ //
+ // Return the checksum based on 2's complement.
+ //
+ return (UINT64) ((UINT64)(-1) - CheckSum + 1);
+}
+
+GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 mCrcTable[256] = {
+ 0x00000000,
+ 0x77073096,
+ 0xEE0E612C,
+ 0x990951BA,
+ 0x076DC419,
+ 0x706AF48F,
+ 0xE963A535,
+ 0x9E6495A3,
+ 0x0EDB8832,
+ 0x79DCB8A4,
+ 0xE0D5E91E,
+ 0x97D2D988,
+ 0x09B64C2B,
+ 0x7EB17CBD,
+ 0xE7B82D07,
+ 0x90BF1D91,
+ 0x1DB71064,
+ 0x6AB020F2,
+ 0xF3B97148,
+ 0x84BE41DE,
+ 0x1ADAD47D,
+ 0x6DDDE4EB,
+ 0xF4D4B551,
+ 0x83D385C7,
+ 0x136C9856,
+ 0x646BA8C0,
+ 0xFD62F97A,
+ 0x8A65C9EC,
+ 0x14015C4F,
+ 0x63066CD9,
+ 0xFA0F3D63,
+ 0x8D080DF5,
+ 0x3B6E20C8,
+ 0x4C69105E,
+ 0xD56041E4,
+ 0xA2677172,
+ 0x3C03E4D1,
+ 0x4B04D447,
+ 0xD20D85FD,
+ 0xA50AB56B,
+ 0x35B5A8FA,
+ 0x42B2986C,
+ 0xDBBBC9D6,
+ 0xACBCF940,
+ 0x32D86CE3,
+ 0x45DF5C75,
+ 0xDCD60DCF,
+ 0xABD13D59,
+ 0x26D930AC,
+ 0x51DE003A,
+ 0xC8D75180,
+ 0xBFD06116,
+ 0x21B4F4B5,
+ 0x56B3C423,
+ 0xCFBA9599,
+ 0xB8BDA50F,
+ 0x2802B89E,
+ 0x5F058808,
+ 0xC60CD9B2,
+ 0xB10BE924,
+ 0x2F6F7C87,
+ 0x58684C11,
+ 0xC1611DAB,
+ 0xB6662D3D,
+ 0x76DC4190,
+ 0x01DB7106,
+ 0x98D220BC,
+ 0xEFD5102A,
+ 0x71B18589,
+ 0x06B6B51F,
+ 0x9FBFE4A5,
+ 0xE8B8D433,
+ 0x7807C9A2,
+ 0x0F00F934,
+ 0x9609A88E,
+ 0xE10E9818,
+ 0x7F6A0DBB,
+ 0x086D3D2D,
+ 0x91646C97,
+ 0xE6635C01,
+ 0x6B6B51F4,
+ 0x1C6C6162,
+ 0x856530D8,
+ 0xF262004E,
+ 0x6C0695ED,
+ 0x1B01A57B,
+ 0x8208F4C1,
+ 0xF50FC457,
+ 0x65B0D9C6,
+ 0x12B7E950,
+ 0x8BBEB8EA,
+ 0xFCB9887C,
+ 0x62DD1DDF,
+ 0x15DA2D49,
+ 0x8CD37CF3,
+ 0xFBD44C65,
+ 0x4DB26158,
+ 0x3AB551CE,
+ 0xA3BC0074,
+ 0xD4BB30E2,
+ 0x4ADFA541,
+ 0x3DD895D7,
+ 0xA4D1C46D,
+ 0xD3D6F4FB,
+ 0x4369E96A,
+ 0x346ED9FC,
+ 0xAD678846,
+ 0xDA60B8D0,
+ 0x44042D73,
+ 0x33031DE5,
+ 0xAA0A4C5F,
+ 0xDD0D7CC9,
+ 0x5005713C,
+ 0x270241AA,
+ 0xBE0B1010,
+ 0xC90C2086,
+ 0x5768B525,
+ 0x206F85B3,
+ 0xB966D409,
+ 0xCE61E49F,
+ 0x5EDEF90E,
+ 0x29D9C998,
+ 0xB0D09822,
+ 0xC7D7A8B4,
+ 0x59B33D17,
+ 0x2EB40D81,
+ 0xB7BD5C3B,
+ 0xC0BA6CAD,
+ 0xEDB88320,
+ 0x9ABFB3B6,
+ 0x03B6E20C,
+ 0x74B1D29A,
+ 0xEAD54739,
+ 0x9DD277AF,
+ 0x04DB2615,
+ 0x73DC1683,
+ 0xE3630B12,
+ 0x94643B84,
+ 0x0D6D6A3E,
+ 0x7A6A5AA8,
+ 0xE40ECF0B,
+ 0x9309FF9D,
+ 0x0A00AE27,
+ 0x7D079EB1,
+ 0xF00F9344,
+ 0x8708A3D2,
+ 0x1E01F268,
+ 0x6906C2FE,
+ 0xF762575D,
+ 0x806567CB,
+ 0x196C3671,
+ 0x6E6B06E7,
+ 0xFED41B76,
+ 0x89D32BE0,
+ 0x10DA7A5A,
+ 0x67DD4ACC,
+ 0xF9B9DF6F,
+ 0x8EBEEFF9,
+ 0x17B7BE43,
+ 0x60B08ED5,
+ 0xD6D6A3E8,
+ 0xA1D1937E,
+ 0x38D8C2C4,
+ 0x4FDFF252,
+ 0xD1BB67F1,
+ 0xA6BC5767,
+ 0x3FB506DD,
+ 0x48B2364B,
+ 0xD80D2BDA,
+ 0xAF0A1B4C,
+ 0x36034AF6,
+ 0x41047A60,
+ 0xDF60EFC3,
+ 0xA867DF55,
+ 0x316E8EEF,
+ 0x4669BE79,
+ 0xCB61B38C,
+ 0xBC66831A,
+ 0x256FD2A0,
+ 0x5268E236,
+ 0xCC0C7795,
+ 0xBB0B4703,
+ 0x220216B9,
+ 0x5505262F,
+ 0xC5BA3BBE,
+ 0xB2BD0B28,
+ 0x2BB45A92,
+ 0x5CB36A04,
+ 0xC2D7FFA7,
+ 0xB5D0CF31,
+ 0x2CD99E8B,
+ 0x5BDEAE1D,
+ 0x9B64C2B0,
+ 0xEC63F226,
+ 0x756AA39C,
+ 0x026D930A,
+ 0x9C0906A9,
+ 0xEB0E363F,
+ 0x72076785,
+ 0x05005713,
+ 0x95BF4A82,
+ 0xE2B87A14,
+ 0x7BB12BAE,
+ 0x0CB61B38,
+ 0x92D28E9B,
+ 0xE5D5BE0D,
+ 0x7CDCEFB7,
+ 0x0BDBDF21,
+ 0x86D3D2D4,
+ 0xF1D4E242,
+ 0x68DDB3F8,
+ 0x1FDA836E,
+ 0x81BE16CD,
+ 0xF6B9265B,
+ 0x6FB077E1,
+ 0x18B74777,
+ 0x88085AE6,
+ 0xFF0F6A70,
+ 0x66063BCA,
+ 0x11010B5C,
+ 0x8F659EFF,
+ 0xF862AE69,
+ 0x616BFFD3,
+ 0x166CCF45,
+ 0xA00AE278,
+ 0xD70DD2EE,
+ 0x4E048354,
+ 0x3903B3C2,
+ 0xA7672661,
+ 0xD06016F7,
+ 0x4969474D,
+ 0x3E6E77DB,
+ 0xAED16A4A,
+ 0xD9D65ADC,
+ 0x40DF0B66,
+ 0x37D83BF0,
+ 0xA9BCAE53,
+ 0xDEBB9EC5,
+ 0x47B2CF7F,
+ 0x30B5FFE9,
+ 0xBDBDF21C,
+ 0xCABAC28A,
+ 0x53B39330,
+ 0x24B4A3A6,
+ 0xBAD03605,
+ 0xCDD70693,
+ 0x54DE5729,
+ 0x23D967BF,
+ 0xB3667A2E,
+ 0xC4614AB8,
+ 0x5D681B02,
+ 0x2A6F2B94,
+ 0xB40BBE37,
+ 0xC30C8EA1,
+ 0x5A05DF1B,
+ 0x2D02EF8D
+};
+
+/**
+ Computes and returns a 32-bit CRC for a data buffer.
+ CRC32 value bases on ITU-T V.42.
+
+ If Buffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param[in] Buffer A pointer to the buffer on which the 32-bit CRC is to be computed.
+ @param[in] Length The number of bytes in the buffer Data.
+
+ @retval Crc32 The 32-bit CRC was computed for the data buffer.
+
+**/
+UINT32
+EFIAPI
+CalculateCrc32(
+ IN VOID *Buffer,
+ IN UINTN Length
+ )
+{
+ UINTN Index;
+ UINT32 Crc;
+ UINT8 *Ptr;
+
+ ASSERT (Buffer != NULL);
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
+
+ //
+ // Compute CRC
+ //
+ Crc = 0xffffffff;
+ for (Index = 0, Ptr = Buffer; Index < Length; Index++, Ptr++) {
+ Crc = (Crc >> 8) ^ mCrcTable[(UINT8) Crc ^ *Ptr];
+ }
+
+ return Crc ^ 0xffffffff;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/ChkStkGcc.c b/roms/edk2/MdePkg/Library/BaseLib/ChkStkGcc.c new file mode 100644 index 000000000..7f07ba2d6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/ChkStkGcc.c @@ -0,0 +1,18 @@ +/** @file
+ Provides hack function for passng GCC build.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Hack function for passing GCC build.
+**/
+VOID
+__chkstk()
+{
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Cpu.c b/roms/edk2/MdePkg/Library/BaseLib/Cpu.c new file mode 100644 index 000000000..689246f16 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Cpu.c @@ -0,0 +1,59 @@ +/** @file
+ Base Library CPU Functions for all architectures.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+
+/**
+ Disables CPU interrupts and returns the interrupt state prior to the disable
+ operation.
+
+ @retval TRUE CPU interrupts were enabled on entry to this call.
+ @retval FALSE CPU interrupts were disabled on entry to this call.
+
+**/
+BOOLEAN
+EFIAPI
+SaveAndDisableInterrupts (
+ VOID
+ )
+{
+ BOOLEAN InterruptState;
+
+ InterruptState = GetInterruptState ();
+ DisableInterrupts ();
+ return InterruptState;
+}
+
+/**
+ Set the current CPU interrupt state.
+
+ Sets the current CPU interrupt state to the state specified by
+ InterruptState. If InterruptState is TRUE, then interrupts are enabled. If
+ InterruptState is FALSE, then interrupts are disabled. InterruptState is
+ returned.
+
+ @param InterruptState TRUE if interrupts should be enabled. FALSE if
+ interrupts should be disabled.
+
+ @return InterruptState
+
+**/
+BOOLEAN
+EFIAPI
+SetInterruptState (
+ IN BOOLEAN InterruptState
+ )
+{
+ if (InterruptState) {
+ EnableInterrupts ();
+ } else {
+ DisableInterrupts ();
+ }
+ return InterruptState;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/CpuDeadLoop.c b/roms/edk2/MdePkg/Library/BaseLib/CpuDeadLoop.c new file mode 100644 index 000000000..9e110cacb --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/CpuDeadLoop.c @@ -0,0 +1,32 @@ +/** @file
+ Base Library CPU Functions for all architectures.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+
+/**
+ Executes an infinite loop.
+
+ Forces the CPU to execute an infinite loop. A debugger may be used to skip
+ past the loop and the code that follows the loop must execute properly. This
+ implies that the infinite loop must not cause the code that follow it to be
+ optimized away.
+
+**/
+VOID
+EFIAPI
+CpuDeadLoop (
+ VOID
+ )
+{
+ volatile UINTN Index;
+
+ for (Index = 0; Index == 0;);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/DivS64x64Remainder.c b/roms/edk2/MdePkg/Library/BaseLib/DivS64x64Remainder.c new file mode 100644 index 000000000..bdf25b836 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/DivS64x64Remainder.c @@ -0,0 +1,47 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Divides a 64-bit signed integer by a 64-bit signed integer and generates a
+ 64-bit signed result and a optional 64-bit signed remainder.
+
+ This function divides the 64-bit signed value Dividend by the 64-bit signed
+ value Divisor and generates a 64-bit signed quotient. If Remainder is not
+ NULL, then the 64-bit signed remainder is returned in Remainder. This
+ function returns the 64-bit signed quotient.
+
+ It is the caller's responsibility to not call this function with a Divisor of 0.
+ If Divisor is 0, then the quotient and remainder should be assumed to be
+ the largest negative integer.
+
+ If Divisor is 0, then ASSERT().
+
+ @param Dividend A 64-bit signed value.
+ @param Divisor A 64-bit signed value.
+ @param Remainder A pointer to a 64-bit signed value. This parameter is
+ optional and may be NULL.
+
+ @return Dividend / Divisor
+
+**/
+INT64
+EFIAPI
+DivS64x64Remainder (
+ IN INT64 Dividend,
+ IN INT64 Divisor,
+ OUT INT64 *Remainder OPTIONAL
+ )
+{
+ ASSERT (Divisor != 0);
+ return InternalMathDivRemS64x64 (Dividend, Divisor, Remainder);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/DivU64x32.c b/roms/edk2/MdePkg/Library/BaseLib/DivU64x32.c new file mode 100644 index 000000000..fa377ec55 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/DivU64x32.c @@ -0,0 +1,39 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates
+ a 64-bit unsigned result.
+
+ This function divides the 64-bit unsigned value Dividend by the 32-bit
+ unsigned value Divisor and generates a 64-bit unsigned quotient. This
+ function returns the 64-bit unsigned quotient.
+
+ If Divisor is 0, then ASSERT().
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 32-bit unsigned value.
+
+ @return Dividend / Divisor
+
+**/
+UINT64
+EFIAPI
+DivU64x32 (
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
+ )
+{
+ ASSERT (Divisor != 0);
+ return InternalMathDivU64x32 (Dividend, Divisor);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/DivU64x32Remainder.c b/roms/edk2/MdePkg/Library/BaseLib/DivU64x32Remainder.c new file mode 100644 index 000000000..df9d3310e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/DivU64x32Remainder.c @@ -0,0 +1,43 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates
+ a 64-bit unsigned result and an optional 32-bit unsigned remainder.
+
+ This function divides the 64-bit unsigned value Dividend by the 32-bit
+ unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder
+ is not NULL, then the 32-bit unsigned remainder is returned in Remainder.
+ This function returns the 64-bit unsigned quotient.
+
+ If Divisor is 0, then ASSERT().
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 32-bit unsigned value.
+ @param Remainder A pointer to a 32-bit unsigned value. This parameter is
+ optional and may be NULL.
+
+ @return Dividend / Divisor
+
+**/
+UINT64
+EFIAPI
+DivU64x32Remainder (
+ IN UINT64 Dividend,
+ IN UINT32 Divisor,
+ OUT UINT32 *Remainder OPTIONAL
+ )
+{
+ ASSERT (Divisor != 0);
+ return InternalMathDivRemU64x32 (Dividend, Divisor, Remainder);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/DivU64x64Remainder.c b/roms/edk2/MdePkg/Library/BaseLib/DivU64x64Remainder.c new file mode 100644 index 000000000..94dc2b1a6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/DivU64x64Remainder.c @@ -0,0 +1,43 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Divides a 64-bit unsigned integer by a 64-bit unsigned integer and generates
+ a 64-bit unsigned result and an optional 64-bit unsigned remainder.
+
+ This function divides the 64-bit unsigned value Dividend by the 64-bit
+ unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder
+ is not NULL, then the 64-bit unsigned remainder is returned in Remainder.
+ This function returns the 64-bit unsigned quotient.
+
+ If Divisor is 0, then ASSERT().
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 64-bit unsigned value.
+ @param Remainder A pointer to a 64-bit unsigned value. This parameter is
+ optional and may be NULL.
+
+ @return Dividend / Divisor
+
+**/
+UINT64
+EFIAPI
+DivU64x64Remainder (
+ IN UINT64 Dividend,
+ IN UINT64 Divisor,
+ OUT UINT64 *Remainder OPTIONAL
+ )
+{
+ ASSERT (Divisor != 0);
+ return InternalMathDivRemU64x64 (Dividend, Divisor, Remainder);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c b/roms/edk2/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c new file mode 100644 index 000000000..d0debec30 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c @@ -0,0 +1,123 @@ +/** @file
+ Base Library CPU Functions for EBC
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+extern
+UINT64
+_break (
+ CHAR8 BreakCode
+ );
+
+/**
+ Generates a breakpoint on the CPU.
+
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such
+ that code can resume normal execution after the breakpoint.
+
+**/
+VOID
+EFIAPI
+CpuBreakpoint (
+ VOID
+ )
+{
+ _break (3);
+}
+
+/**
+ Used to serialize load and store operations.
+
+ All loads and stores that proceed calls to this function are guaranteed to be
+ globally visible when this function returns.
+
+**/
+VOID
+EFIAPI
+MemoryFence (
+ VOID
+ )
+{
+}
+
+/**
+ Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+DisableInterrupts (
+ VOID
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+EnableInterrupts (
+ VOID
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Retrieves the current CPU interrupt state.
+
+ Returns TRUE means interrupts are currently enabled. Otherwise,
+ returns FALSE.
+
+ @retval TRUE CPU interrupts are enabled.
+ @retval FALSE CPU interrupts are disabled.
+
+**/
+BOOLEAN
+EFIAPI
+GetInterruptState (
+ VOID
+ )
+{
+ ASSERT (FALSE);
+ return FALSE;
+}
+
+/**
+ Enables CPU interrupts for the smallest window required to capture any
+ pending interrupts.
+
+**/
+VOID
+EFIAPI
+EnableDisableInterrupts (
+ VOID
+ )
+{
+ EnableInterrupts ();
+ DisableInterrupts ();
+}
+
+/**
+ Requests CPU to pause for a short period of time.
+
+ Requests CPU to pause for a short period of time. Typically used in MP
+ systems to prevent memory starvation while waiting for a spin lock.
+
+**/
+VOID
+EFIAPI
+CpuPause (
+ VOID
+ )
+{
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ebc/SetJumpLongJump.c b/roms/edk2/MdePkg/Library/BaseLib/Ebc/SetJumpLongJump.c new file mode 100644 index 000000000..631853cd0 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ebc/SetJumpLongJump.c @@ -0,0 +1,62 @@ +/** @file
+ Implementation of SetJump() and LongJump() on EBC.
+
+ SetJump() and LongJump() are not currently supported for the EBC processor type.
+ Implementation for EBC just returns 0 for SetJump(), and ASSERT() for LongJump().
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Saves the current CPU context that can be restored with a call to LongJump() and returns 0.
+
+ Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
+ call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
+ value to be returned by SetJump().
+
+ If JumpBuffer is NULL, then ASSERT().
+ For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
+
+ @param JumpBuffer A pointer to CPU context buffer.
+
+ @retval 0 Indicates a return from SetJump().
+
+**/
+RETURNS_TWICE
+UINTN
+EFIAPI
+SetJump (
+ OUT BASE_LIBRARY_JUMP_BUFFER *JumpBuffer
+ )
+{
+ InternalAssertJumpBuffer (JumpBuffer);
+ return 0;
+}
+
+/**
+ Restores the CPU context that was saved with SetJump().
+
+ Restores the CPU context from the buffer specified by JumpBuffer.
+ This function never returns to the caller.
+ Instead it resumes execution based on the state of JumpBuffer.
+
+ @param JumpBuffer A pointer to CPU context buffer.
+ @param Value The value to return when the SetJump() context is restored.
+
+**/
+VOID
+EFIAPI
+InternalLongJump (
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,
+ IN UINTN Value
+ )
+{
+ //
+ // This function cannot work on EBC
+ //
+ ASSERT (FALSE);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ebc/SpeculationBarrier.c b/roms/edk2/MdePkg/Library/BaseLib/Ebc/SpeculationBarrier.c new file mode 100644 index 000000000..d4067a4a0 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ebc/SpeculationBarrier.c @@ -0,0 +1,24 @@ +/** @file
+ SpeculationBarrier() function for EBC.
+
+ Copyright (C) 2018, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+/**
+ Uses as a barrier to stop speculative execution.
+
+ Ensures that no later instruction will execute speculatively, until all prior
+ instructions have completed.
+
+**/
+VOID
+EFIAPI
+SpeculationBarrier (
+ VOID
+ )
+{
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ebc/SwitchStack.c b/roms/edk2/MdePkg/Library/BaseLib/Ebc/SwitchStack.c new file mode 100644 index 000000000..92cbef8d2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ebc/SwitchStack.c @@ -0,0 +1,52 @@ +/** @file
+ Switch Stack functions.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Transfers control to a function starting with a new stack.
+
+ Transfers control to the function specified by EntryPoint using the
+ new stack specified by NewStack and passing in the parameters specified
+ by Context1 and Context2. Context1 and Context2 are optional and may
+ be NULL. The function EntryPoint must never return.
+ Marker will be ignored on IA-32, x64, and EBC.
+ IPF CPUs expect one additional parameter of type VOID * that specifies
+ the new backing store pointer.
+
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ @param EntryPoint A pointer to function to call with the new stack.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function.
+ @param Marker A VA_LIST marker for the variable argument list.
+
+**/
+VOID
+EFIAPI
+InternalSwitchStack (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack,
+ IN VA_LIST Marker
+ )
+
+{
+ //
+ // This version of this function does not actually change the stack pointer
+ // This is to support compilation of CPU types that do not support assemblers
+ // such as EBC
+ //
+ EntryPoint (Context1, Context2);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/FilePaths.c b/roms/edk2/MdePkg/Library/BaseLib/FilePaths.c new file mode 100644 index 000000000..c2c561ac6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/FilePaths.c @@ -0,0 +1,115 @@ +/** @file
+ Defines file-path manipulation functions.
+
+ Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2018, Dell Technologies. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Library/BaseMemoryLib.h>
+#include <Library/BaseLib.h>
+
+/**
+ Removes the last directory or file entry in a path. For a path which is
+ like L"fs0:startup.nsh", it's converted to L"fs0:".
+
+ @param[in,out] Path A pointer to the path to modify.
+
+ @retval FALSE Nothing was found to remove.
+ @retval TRUE A directory or file was removed.
+**/
+BOOLEAN
+EFIAPI
+PathRemoveLastItem(
+ IN OUT CHAR16 *Path
+ )
+{
+ CHAR16 *Walker;
+ CHAR16 *LastSlash;
+ //
+ // get directory name from path... ('chop' off extra)
+ //
+ for ( Walker = Path, LastSlash = NULL
+ ; Walker != NULL && *Walker != CHAR_NULL
+ ; Walker++
+ ){
+ if (*Walker == L'\\' && *(Walker + 1) != CHAR_NULL) {
+ LastSlash = Walker+1;
+ } else if (*Walker == L':' && *(Walker + 1) != L'\\' && *(Walker + 1) != CHAR_NULL) {
+ LastSlash = Walker+1;
+ }
+ }
+ if (LastSlash != NULL) {
+ *LastSlash = CHAR_NULL;
+ return (TRUE);
+ }
+ return (FALSE);
+}
+
+/**
+ Function to clean up paths.
+
+ - Single periods in the path are removed.
+ - Double periods in the path are removed along with a single parent directory.
+ - Forward slashes L'/' are converted to backward slashes L'\'.
+
+ This will be done inline and the existing buffer may be larger than required
+ upon completion.
+
+ @param[in] Path The pointer to the string containing the path.
+
+ @return Returns Path, otherwise returns NULL to indicate that an error has occurred.
+**/
+CHAR16*
+EFIAPI
+PathCleanUpDirectories(
+ IN CHAR16 *Path
+)
+{
+ CHAR16 *TempString;
+
+ if (Path == NULL) {
+ return NULL;
+ }
+
+ //
+ // Replace the '/' with '\'
+ //
+ for (TempString = Path; *TempString != CHAR_NULL; TempString++) {
+ if (*TempString == L'/') {
+ *TempString = L'\\';
+ }
+ }
+
+ //
+ // Replace the "\\" with "\"
+ //
+ while ((TempString = StrStr (Path, L"\\\\")) != NULL) {
+ CopyMem (TempString, TempString + 1, StrSize (TempString + 1));
+ }
+
+ //
+ // Remove all the "\.". E.g.: fs0:\abc\.\def\.
+ //
+ while ((TempString = StrStr (Path, L"\\.\\")) != NULL) {
+ CopyMem (TempString, TempString + 2, StrSize (TempString + 2));
+ }
+ if ((StrLen (Path) >= 2) && (StrCmp (Path + StrLen (Path) - 2, L"\\.") == 0)) {
+ Path[StrLen (Path) - 1] = CHAR_NULL;
+ }
+
+ //
+ // Remove all the "\..". E.g.: fs0:\abc\..\def\..
+ //
+ while (((TempString = StrStr(Path, L"\\..")) != NULL) &&
+ ((*(TempString + 3) == L'\\') || (*(TempString + 3) == CHAR_NULL))
+ ) {
+ *(TempString + 1) = CHAR_NULL;
+ PathRemoveLastItem(Path);
+ if (*(TempString + 3) != CHAR_NULL) {
+ CopyMem (Path + StrLen (Path), TempString + 4, StrSize (TempString + 4));
+ }
+ }
+
+ return Path;
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/GetPowerOfTwo32.c b/roms/edk2/MdePkg/Library/BaseLib/GetPowerOfTwo32.c new file mode 100644 index 000000000..76f5e3cfb --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/GetPowerOfTwo32.c @@ -0,0 +1,38 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Returns the value of the highest bit set in a 32-bit value. Equivalent to
+ 1 << log2(x).
+
+ This function computes the value of the highest bit set in the 32-bit value
+ specified by Operand. If Operand is zero, then zero is returned.
+
+ @param Operand The 32-bit operand to evaluate.
+
+ @return 1 << HighBitSet32(Operand)
+ @retval 0 Operand is zero.
+
+**/
+UINT32
+EFIAPI
+GetPowerOfTwo32 (
+ IN UINT32 Operand
+ )
+{
+ if (0 == Operand) {
+ return 0;
+ }
+
+ return 1ul << HighBitSet32 (Operand);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/GetPowerOfTwo64.c b/roms/edk2/MdePkg/Library/BaseLib/GetPowerOfTwo64.c new file mode 100644 index 000000000..5033076f8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/GetPowerOfTwo64.c @@ -0,0 +1,38 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Returns the value of the highest bit set in a 64-bit value. Equivalent to
+ 1 << log2(x).
+
+ This function computes the value of the highest bit set in the 64-bit value
+ specified by Operand. If Operand is zero, then zero is returned.
+
+ @param Operand The 64-bit operand to evaluate.
+
+ @return 1 << HighBitSet64(Operand)
+ @retval 0 Operand is zero.
+
+**/
+UINT64
+EFIAPI
+GetPowerOfTwo64 (
+ IN UINT64 Operand
+ )
+{
+ if (Operand == 0) {
+ return 0;
+ }
+
+ return LShiftU64 (1, (UINTN) HighBitSet64 (Operand));
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/HighBitSet32.c b/roms/edk2/MdePkg/Library/BaseLib/HighBitSet32.c new file mode 100644 index 000000000..b3c9ed158 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/HighBitSet32.c @@ -0,0 +1,41 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Returns the bit position of the highest bit set in a 32-bit value. Equivalent
+ to log2(x).
+
+ This function computes the bit position of the highest bit set in the 32-bit
+ value specified by Operand. If Operand is zero, then -1 is returned.
+ Otherwise, a value between 0 and 31 is returned.
+
+ @param Operand The 32-bit operand to evaluate.
+
+ @retval 0..31 Position of the highest bit set in Operand if found.
+ @retval -1 Operand is zero.
+
+**/
+INTN
+EFIAPI
+HighBitSet32 (
+ IN UINT32 Operand
+ )
+{
+ INTN BitIndex;
+
+ if (Operand == 0) {
+ return - 1;
+ }
+ for (BitIndex = 31; (INT32)Operand > 0; BitIndex--, Operand <<= 1);
+ return BitIndex;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/HighBitSet64.c b/roms/edk2/MdePkg/Library/BaseLib/HighBitSet64.c new file mode 100644 index 000000000..4f06dfc88 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/HighBitSet64.c @@ -0,0 +1,49 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Returns the bit position of the highest bit set in a 64-bit value. Equivalent
+ to log2(x).
+
+ This function computes the bit position of the highest bit set in the 64-bit
+ value specified by Operand. If Operand is zero, then -1 is returned.
+ Otherwise, a value between 0 and 63 is returned.
+
+ @param Operand The 64-bit operand to evaluate.
+
+ @retval 0..63 Position of the highest bit set in Operand if found.
+ @retval -1 Operand is zero.
+
+**/
+INTN
+EFIAPI
+HighBitSet64 (
+ IN UINT64 Operand
+ )
+{
+ if (Operand == (UINT32)Operand) {
+ //
+ // Operand is just a 32-bit integer
+ //
+ return HighBitSet32 ((UINT32)Operand);
+ }
+
+ //
+ // Operand is really a 64-bit integer
+ //
+ if (sizeof (UINTN) == sizeof (UINT32)) {
+ return HighBitSet32 (((UINT32*)&Operand)[1]) + 32;
+ } else {
+ return HighBitSet32 ((UINT32)RShiftU64 (Operand, 32)) + 32;
+ }
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ARShiftU64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ARShiftU64.c new file mode 100644 index 000000000..836108364 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ARShiftU64.c @@ -0,0 +1,45 @@ +/** @file
+ 64-bit arithmetic right shift function for IA-32.
+
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Shifts a 64-bit integer right between 0 and 63 bits. The high bits
+ are filled with original integer's bit 63. The shifted value is returned.
+
+ This function shifts the 64-bit value Operand to the right by Count bits. The
+ high Count bits are set to bit 63 of Operand. The shifted value is returned.
+
+ @param Operand The 64-bit operand to shift right.
+ @param Count The number of bits to shift right.
+
+ @return Operand arithmetically shifted right by Count.
+
+**/
+UINT64
+EFIAPI
+InternalMathARShiftU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ )
+{
+ _asm {
+ mov cl, byte ptr [Count]
+ mov eax, dword ptr [Operand + 4]
+ cdq
+ test cl, 32
+ jnz L0
+ mov edx, eax
+ mov eax, dword ptr [Operand + 0]
+L0:
+ shrd eax, edx, cl
+ sar edx, cl
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ARShiftU64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ARShiftU64.nasm new file mode 100644 index 000000000..94aa88229 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ARShiftU64.nasm @@ -0,0 +1,39 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ARShiftU64.nasm
+;
+; Abstract:
+;
+; 64-bit arithmetic right shift function for IA-32
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; InternalMathARShiftU64 (
+; IN UINT64 Operand,
+; IN UINTN Count
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalMathARShiftU64)
+ASM_PFX(InternalMathARShiftU64):
+ mov cl, [esp + 12]
+ mov eax, [esp + 8]
+ cdq
+ test cl, 32
+ jnz .0
+ mov edx, eax
+ mov eax, [esp + 4]
+.0:
+ shrd eax, edx, cl
+ sar edx, cl
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.c new file mode 100644 index 000000000..a59da0cee --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.c @@ -0,0 +1,35 @@ +/** @file
+ CpuBreakpoint function.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
+**/
+
+void __debugbreak (VOID);
+
+#pragma intrinsic(__debugbreak)
+
+/**
+ Generates a breakpoint on the CPU.
+
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such
+ that code can resume normal execution after the breakpoint.
+
+**/
+VOID
+EFIAPI
+CpuBreakpoint (
+ VOID
+ )
+{
+ __debugbreak ();
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.nasm new file mode 100644 index 000000000..a62e4f5c3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.nasm @@ -0,0 +1,30 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuBreakpoint.Asm
+;
+; Abstract:
+;
+; CpuBreakpoint function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuBreakpoint (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(CpuBreakpoint)
+ASM_PFX(CpuBreakpoint):
+ int 3
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuId.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuId.c new file mode 100644 index 000000000..bcb0fa78f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuId.c @@ -0,0 +1,68 @@ +/** @file
+ AsmCpuid function.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Retrieves CPUID information.
+
+ Executes the CPUID instruction with EAX set to the value specified by Index.
+ This function always returns Index.
+ If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
+ If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
+ If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
+ If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
+ This function is only available on IA-32 and x64.
+
+ @param Index The 32-bit value to load into EAX prior to invoking the CPUID
+ instruction.
+ @param RegisterEax A pointer to the 32-bit EAX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param RegisterEbx A pointer to the 32-bit EBX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param RegisterEcx A pointer to the 32-bit ECX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param RegisterEdx A pointer to the 32-bit EDX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+
+ @return Index.
+
+**/
+UINT32
+EFIAPI
+AsmCpuid (
+ IN UINT32 Index,
+ OUT UINT32 *RegisterEax, OPTIONAL
+ OUT UINT32 *RegisterEbx, OPTIONAL
+ OUT UINT32 *RegisterEcx, OPTIONAL
+ OUT UINT32 *RegisterEdx OPTIONAL
+ )
+{
+ _asm {
+ mov eax, Index
+ cpuid
+ push ecx
+ mov ecx, RegisterEax
+ jecxz SkipEax
+ mov [ecx], eax
+SkipEax:
+ mov ecx, RegisterEbx
+ jecxz SkipEbx
+ mov [ecx], ebx
+SkipEbx:
+ pop eax
+ mov ecx, RegisterEcx
+ jecxz SkipEcx
+ mov [ecx], eax
+SkipEcx:
+ mov ecx, RegisterEdx
+ jecxz SkipEdx
+ mov [ecx], edx
+SkipEdx:
+ mov eax, Index
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuId.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuId.nasm new file mode 100644 index 000000000..d38135fcd --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuId.nasm @@ -0,0 +1,59 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuId.Asm
+;
+; Abstract:
+;
+; AsmCpuid function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmCpuid (
+; IN UINT32 RegisterInEax,
+; OUT UINT32 *RegisterOutEax OPTIONAL,
+; OUT UINT32 *RegisterOutEbx OPTIONAL,
+; OUT UINT32 *RegisterOutEcx OPTIONAL,
+; OUT UINT32 *RegisterOutEdx OPTIONAL
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmCpuid)
+ASM_PFX(AsmCpuid):
+ push ebx
+ push ebp
+ mov ebp, esp
+ mov eax, [ebp + 12]
+ cpuid
+ push ecx
+ mov ecx, [ebp + 16]
+ jecxz .0
+ mov [ecx], eax
+.0:
+ mov ecx, [ebp + 20]
+ jecxz .1
+ mov [ecx], ebx
+.1:
+ mov ecx, [ebp + 24]
+ jecxz .2
+ pop DWORD [ecx]
+.2:
+ mov ecx, [ebp + 28]
+ jecxz .3
+ mov [ecx], edx
+.3:
+ mov eax, [ebp + 12]
+ leave
+ pop ebx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuIdEx.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuIdEx.c new file mode 100644 index 000000000..b537182a6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuIdEx.c @@ -0,0 +1,76 @@ +/** @file
+ AsmCpuidEx function.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Retrieves CPUID information using an extended leaf identifier.
+
+ Executes the CPUID instruction with EAX set to the value specified by Index
+ and ECX set to the value specified by SubIndex. This function always returns
+ Index. This function is only available on IA-32 and x64.
+
+ If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
+ If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
+ If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
+ If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
+
+ @param Index The 32-bit value to load into EAX prior to invoking the
+ CPUID instruction.
+ @param SubIndex The 32-bit value to load into ECX prior to invoking the
+ CPUID instruction.
+ @param RegisterEax A pointer to the 32-bit EAX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param RegisterEbx A pointer to the 32-bit EBX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param RegisterEcx A pointer to the 32-bit ECX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param RegisterEdx A pointer to the 32-bit EDX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+
+ @return Index.
+
+**/
+UINT32
+EFIAPI
+AsmCpuidEx (
+ IN UINT32 Index,
+ IN UINT32 SubIndex,
+ OUT UINT32 *RegisterEax, OPTIONAL
+ OUT UINT32 *RegisterEbx, OPTIONAL
+ OUT UINT32 *RegisterEcx, OPTIONAL
+ OUT UINT32 *RegisterEdx OPTIONAL
+ )
+{
+ _asm {
+ mov eax, Index
+ mov ecx, SubIndex
+ cpuid
+ push ecx
+ mov ecx, RegisterEax
+ jecxz SkipEax
+ mov [ecx], eax
+SkipEax:
+ mov ecx, RegisterEbx
+ jecxz SkipEbx
+ mov [ecx], ebx
+SkipEbx:
+ pop eax
+ mov ecx, RegisterEcx
+ jecxz SkipEcx
+ mov [ecx], eax
+SkipEcx:
+ mov ecx, RegisterEdx
+ jecxz SkipEdx
+ mov [ecx], edx
+SkipEdx:
+ mov eax, Index
+ }
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuIdEx.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuIdEx.nasm new file mode 100644 index 000000000..f381069c6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuIdEx.nasm @@ -0,0 +1,61 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuIdEx.Asm
+;
+; Abstract:
+;
+; AsmCpuidEx function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT32
+; EFIAPI
+; AsmCpuidEx (
+; IN UINT32 RegisterInEax,
+; IN UINT32 RegisterInEcx,
+; OUT UINT32 *RegisterOutEax OPTIONAL,
+; OUT UINT32 *RegisterOutEbx OPTIONAL,
+; OUT UINT32 *RegisterOutEcx OPTIONAL,
+; OUT UINT32 *RegisterOutEdx OPTIONAL
+; )
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmCpuidEx)
+ASM_PFX(AsmCpuidEx):
+ push ebx
+ push ebp
+ mov ebp, esp
+ mov eax, [ebp + 12]
+ mov ecx, [ebp + 16]
+ cpuid
+ push ecx
+ mov ecx, [ebp + 20]
+ jecxz .0
+ mov [ecx], eax
+.0:
+ mov ecx, [ebp + 24]
+ jecxz .1
+ mov [ecx], ebx
+.1:
+ mov ecx, [ebp + 32]
+ jecxz .2
+ mov [ecx], edx
+.2:
+ mov ecx, [ebp + 28]
+ jecxz .3
+ pop DWORD [ecx]
+.3:
+ mov eax, [ebp + 12]
+ leave
+ pop ebx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuPause.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuPause.c new file mode 100644 index 000000000..12dc896fe --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuPause.c @@ -0,0 +1,29 @@ +/** @file
+ CpuPause function.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Requests CPU to pause for a short period of time.
+
+ Requests CPU to pause for a short period of time. Typically used in MP
+ systems to prevent memory starvation while waiting for a spin lock.
+
+**/
+VOID
+EFIAPI
+CpuPause (
+ VOID
+ )
+{
+ _asm {
+ pause
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuPause.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuPause.nasm new file mode 100644 index 000000000..8fac8c518 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/CpuPause.nasm @@ -0,0 +1,30 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuPause.Asm
+;
+; Abstract:
+;
+; CpuPause function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuPause (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(CpuPause)
+ASM_PFX(CpuPause):
+ pause
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableCache.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableCache.c new file mode 100644 index 000000000..6a8be4ef2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableCache.c @@ -0,0 +1,30 @@ +/** @file
+ AsmDisableCache function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Set CD bit and clear NW bit of CR0 followed by a WBINVD.
+
+ Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,
+ and executing a WBINVD instruction. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+AsmDisableCache (
+ VOID
+ )
+{
+ _asm {
+ mov eax, cr0
+ bts eax, 30
+ btr eax, 29
+ mov cr0, eax
+ wbinvd
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableCache.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableCache.nasm new file mode 100644 index 000000000..c379e4a6b --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableCache.nasm @@ -0,0 +1,36 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; DisableCache.Asm
+;
+; Abstract:
+;
+; Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a
+; WBINVD instruction.
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmDisableCache (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmDisableCache)
+ASM_PFX(AsmDisableCache):
+ mov eax, cr0
+ bts eax, 30
+ btr eax, 29
+ mov cr0, eax
+ wbinvd
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.c new file mode 100644 index 000000000..4141ef751 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.c @@ -0,0 +1,26 @@ +/** @file
+ DisableInterrupts function.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+DisableInterrupts (
+ VOID
+ )
+{
+ _asm {
+ cli
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.nasm new file mode 100644 index 000000000..ed73f66be --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; DisableInterrupts.Asm
+;
+; Abstract:
+;
+; DisableInterrupts function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; DisableInterrupts (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(DisableInterrupts)
+ASM_PFX(DisableInterrupts):
+ cli
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisablePaging32.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisablePaging32.c new file mode 100644 index 000000000..12ee87413 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisablePaging32.c @@ -0,0 +1,71 @@ +/** @file
+ AsmDisablePaging32 function.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Disables the 32-bit paging mode on the CPU.
+
+ Disables the 32-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 32-paged protected
+ mode. This function is only available on IA-32. After the 32-bit paging mode
+ is disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be NULL. The function EntryPoint must never return.
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit paged mode.
+ 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.
+ 4) CR3 must point to valid page tables that guarantee that the pages for
+ this function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is disabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is disabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is
+ disabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is disabled.
+
+**/
+__declspec (naked)
+VOID
+EFIAPI
+InternalX86DisablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack
+ )
+{
+ _asm {
+ push ebp
+ mov ebp, esp
+ mov ebx, EntryPoint
+ mov ecx, Context1
+ mov edx, Context2
+ pushfd
+ pop edi // save EFLAGS to edi
+ cli
+ mov eax, cr0
+ btr eax, 31
+ mov esp, NewStack
+ mov cr0, eax
+ push edi
+ popfd // restore EFLAGS from edi
+ push edx
+ push ecx
+ call ebx
+ jmp $ // EntryPoint() should not return
+ }
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisablePaging32.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisablePaging32.nasm new file mode 100644 index 000000000..0cab3304a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DisablePaging32.nasm @@ -0,0 +1,48 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; DisablePaging32.Asm
+;
+; Abstract:
+;
+; AsmDisablePaging32 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86DisablePaging32 (
+; IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+; IN VOID *Context1, OPTIONAL
+; IN VOID *Context2, OPTIONAL
+; IN VOID *NewStack
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86DisablePaging32)
+ASM_PFX(InternalX86DisablePaging32):
+ mov ebx, [esp + 4]
+ mov ecx, [esp + 8]
+ mov edx, [esp + 12]
+ pushfd
+ pop edi ; save EFLAGS to edi
+ cli
+ mov eax, cr0
+ btr eax, 31
+ mov esp, [esp + 16]
+ mov cr0, eax
+ push edi
+ popfd ; restore EFLAGS from edi
+ push edx
+ push ecx
+ call ebx
+ jmp $ ; EntryPoint() should not return
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivS64x64Remainder.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivS64x64Remainder.c new file mode 100644 index 000000000..4e6496404 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivS64x64Remainder.c @@ -0,0 +1,47 @@ +/** @file
+ Integer division worker functions for Ia32.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Worker function that Divides a 64-bit signed integer by a 64-bit signed integer and
+ generates a 64-bit signed result and a optional 64-bit signed remainder.
+
+ This function divides the 64-bit signed value Dividend by the 64-bit
+ signed value Divisor and generates a 64-bit signed quotient. If Remainder
+ is not NULL, then the 64-bit signed remainder is returned in Remainder.
+ This function returns the 64-bit signed quotient.
+
+ @param Dividend A 64-bit signed value.
+ @param Divisor A 64-bit signed value.
+ @param Remainder A pointer to a 64-bit signed value. This parameter is
+ optional and may be NULL.
+
+ @return Dividend / Divisor
+
+**/
+INT64
+EFIAPI
+InternalMathDivRemS64x64 (
+ IN INT64 Dividend,
+ IN INT64 Divisor,
+ OUT INT64 *Remainder OPTIONAL
+ )
+{
+ INT64 Quot;
+
+ Quot = InternalMathDivRemU64x64 (
+ (UINT64) (Dividend >= 0 ? Dividend : -Dividend),
+ (UINT64) (Divisor >= 0 ? Divisor : -Divisor),
+ (UINT64 *) Remainder
+ );
+ if (Remainder != NULL && Dividend < 0) {
+ *Remainder = -*Remainder;
+ }
+ return (Dividend ^ Divisor) >= 0 ? Quot : -Quot;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32.c new file mode 100644 index 000000000..538f77a83 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32.c @@ -0,0 +1,44 @@ +/** @file
+ Calculate the quotient of a 64-bit integer by a 32-bit integer
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and
+ generates a 64-bit unsigned result.
+
+ This function divides the 64-bit unsigned value Dividend by the 32-bit
+ unsigned value Divisor and generates a 64-bit unsigned quotient. This
+ function returns the 64-bit unsigned quotient.
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 32-bit unsigned value.
+
+ @return Dividend / Divisor
+
+**/
+UINT64
+EFIAPI
+InternalMathDivU64x32 (
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
+ )
+{
+ _asm {
+ mov eax, dword ptr [Dividend + 4]
+ mov ecx, Divisor
+ xor edx, edx
+ div ecx
+ push eax ; save quotient on stack
+ mov eax, dword ptr [Dividend]
+ div ecx
+ pop edx ; restore high-order dword of the quotient
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32.nasm new file mode 100644 index 000000000..d462119d4 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32.nasm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; DivU64x32.nasm
+;
+; Abstract:
+;
+; Calculate the quotient of a 64-bit integer by a 32-bit integer
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; InternalMathDivU64x32 (
+; IN UINT64 Dividend,
+; IN UINT32 Divisor
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalMathDivU64x32)
+ASM_PFX(InternalMathDivU64x32):
+ mov eax, [esp + 8]
+ mov ecx, [esp + 12]
+ xor edx, edx
+ div ecx
+ push eax ; save quotient on stack
+ mov eax, [esp + 8]
+ div ecx
+ pop edx ; restore high-order dword of the quotient
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.c new file mode 100644 index 000000000..035d4340d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.c @@ -0,0 +1,49 @@ +/** @file
+ Set error flag for all division functions
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and
+ generates a 64-bit unsigned result and an optional 32-bit unsigned remainder.
+
+ This function divides the 64-bit unsigned value Dividend by the 32-bit
+ unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder
+ is not NULL, then the 32-bit unsigned remainder is returned in Remainder.
+ This function returns the 64-bit unsigned quotient.
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 32-bit unsigned value.
+ @param Remainder A pointer to a 32-bit unsigned value. This parameter is
+ optional and may be NULL.
+
+ @return Dividend / Divisor
+
+**/
+UINT64
+EFIAPI
+InternalMathDivRemU64x32 (
+ IN UINT64 Dividend,
+ IN UINT32 Divisor,
+ OUT UINT32 *Remainder
+ )
+{
+ _asm {
+ mov ecx, Divisor
+ mov eax, dword ptr [Dividend + 4]
+ xor edx, edx
+ div ecx
+ push eax
+ mov eax, dword ptr [Dividend + 0]
+ div ecx
+ mov ecx, Remainder
+ jecxz RemainderNull // abandon remainder if Remainder == NULL
+ mov [ecx], edx
+RemainderNull:
+ pop edx
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.nasm new file mode 100644 index 000000000..944ba73f1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.nasm @@ -0,0 +1,42 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; DivError.asm
+;
+; Abstract:
+;
+; Set error flag for all division functions
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; InternalMathDivRemU64x32 (
+; IN UINT64 Dividend,
+; IN UINT32 Divisor,
+; OUT UINT32 *Remainder
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalMathDivRemU64x32)
+ASM_PFX(InternalMathDivRemU64x32):
+ mov ecx, [esp + 12] ; ecx <- divisor
+ mov eax, [esp + 8] ; eax <- dividend[32..63]
+ xor edx, edx
+ div ecx ; eax <- quotient[32..63], edx <- remainder
+ push eax
+ mov eax, [esp + 8] ; eax <- dividend[0..31]
+ div ecx ; eax <- quotient[0..31]
+ mov ecx, [esp + 20] ; ecx <- Remainder
+ jecxz .0 ; abandon remainder if Remainder == NULL
+ mov [ecx], edx
+.0:
+ pop edx ; edx <- quotient[32..63]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.nasm new file mode 100644 index 000000000..0adb07f73 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.nasm @@ -0,0 +1,88 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; DivU64x64Remainder.nasm
+;
+; Abstract:
+;
+; Calculate the quotient of a 64-bit integer by a 64-bit integer and returns
+; both the quotient and the remainder
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+extern ASM_PFX(InternalMathDivRemU64x32)
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; InternalMathDivRemU64x64 (
+; IN UINT64 Dividend,
+; IN UINT64 Divisor,
+; OUT UINT64 *Remainder OPTIONAL
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalMathDivRemU64x64)
+ASM_PFX(InternalMathDivRemU64x64):
+ mov ecx, [esp + 16] ; ecx <- divisor[32..63]
+ test ecx, ecx
+ jnz _@DivRemU64x64 ; call _@DivRemU64x64 if Divisor > 2^32
+ mov ecx, [esp + 20]
+ jecxz .0
+ and dword [ecx + 4], 0 ; zero high dword of remainder
+ mov [esp + 16], ecx ; set up stack frame to match DivRemU64x32
+.0:
+ jmp ASM_PFX(InternalMathDivRemU64x32)
+
+_@DivRemU64x64:
+ push ebx
+ push esi
+ push edi
+ mov edx, dword [esp + 20]
+ mov eax, dword [esp + 16] ; edx:eax <- dividend
+ mov edi, edx
+ mov esi, eax ; edi:esi <- dividend
+ mov ebx, dword [esp + 24] ; ecx:ebx <- divisor
+.1:
+ shr edx, 1
+ rcr eax, 1
+ shrd ebx, ecx, 1
+ shr ecx, 1
+ jnz .1
+ div ebx
+ mov ebx, eax ; ebx <- quotient
+ mov ecx, [esp + 28] ; ecx <- high dword of divisor
+ mul dword [esp + 24] ; edx:eax <- quotient * divisor[0..31]
+ imul ecx, ebx ; ecx <- quotient * divisor[32..63]
+ add edx, ecx ; edx <- (quotient * divisor)[32..63]
+ mov ecx, dword [esp + 32] ; ecx <- addr for Remainder
+ jc @TooLarge ; product > 2^64
+ cmp edi, edx ; compare high 32 bits
+ ja @Correct
+ jb @TooLarge ; product > dividend
+ cmp esi, eax
+ jae @Correct ; product <= dividend
+@TooLarge:
+ dec ebx ; adjust quotient by -1
+ jecxz @Return ; return if Remainder == NULL
+ sub eax, dword [esp + 24]
+ sbb edx, dword [esp + 28] ; edx:eax <- (quotient - 1) * divisor
+@Correct:
+ jecxz @Return
+ sub esi, eax
+ sbb edi, edx ; edi:esi <- remainder
+ mov [ecx], esi
+ mov [ecx + 4], edi
+@Return:
+ mov eax, ebx ; eax <- quotient
+ xor edx, edx ; quotient is 32 bits long
+ pop edi
+ pop esi
+ pop ebx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.c new file mode 100644 index 000000000..4f5c6e9ab --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.c @@ -0,0 +1,30 @@ +/** @file
+ AsmEnableCache function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Perform a WBINVD and clear both the CD and NW bits of CR0.
+
+ Enables the caches by executing a WBINVD instruction and then clear both the CD and NW
+ bits of CR0 to 0. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+AsmEnableCache (
+ VOID
+ )
+{
+ _asm {
+ wbinvd
+ mov eax, cr0
+ btr eax, 30
+ btr eax, 29
+ mov cr0, eax
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm new file mode 100644 index 000000000..02ed72921 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableCache.nasm @@ -0,0 +1,36 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; EnableCache.Asm
+;
+; Abstract:
+;
+; Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear
+; the NW bit of CR0 to 0
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmEnableCache (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmEnableCache)
+ASM_PFX(AsmEnableCache):
+ wbinvd
+ mov eax, cr0
+ btr eax, 29
+ btr eax, 30
+ mov cr0, eax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.c new file mode 100644 index 000000000..7ec62147f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.c @@ -0,0 +1,30 @@ +/** @file
+ EnableDisableInterrupts function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Enables CPU interrupts for the smallest window required to capture any
+ pending interrupts.
+
+**/
+VOID
+EFIAPI
+EnableDisableInterrupts (
+ VOID
+ )
+{
+ _asm {
+ sti
+ nop
+ nop
+ cli
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.nasm new file mode 100644 index 000000000..2da094f0d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; EnableDisableInterrupts.Asm
+;
+; Abstract:
+;
+; EnableDisableInterrupts function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; EnableDisableInterrupts (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(EnableDisableInterrupts)
+ASM_PFX(EnableDisableInterrupts):
+ sti
+ cli
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.c new file mode 100644 index 000000000..bc03144c4 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.c @@ -0,0 +1,26 @@ +/** @file
+ EnableInterrupts function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+EnableInterrupts (
+ VOID
+ )
+{
+ _asm {
+ sti
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.nasm new file mode 100644 index 000000000..979e70820 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; EnableInterrupts.Asm
+;
+; Abstract:
+;
+; EnableInterrupts function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; EnableInterrupts (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(EnableInterrupts)
+ASM_PFX(EnableInterrupts):
+ sti
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging32.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging32.c new file mode 100644 index 000000000..ce0c71067 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging32.c @@ -0,0 +1,75 @@ +/** @file
+ AsmEnablePaging32 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Enables the 32-bit paging mode on the CPU.
+
+ Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode. This function is
+ only available on IA-32. After the 32-bit paging mode is enabled, control is
+ transferred to the function specified by EntryPoint using the new stack
+ specified by NewStack and passing in the parameters specified by Context1 and
+ Context2. Context1 and Context2 are optional and may be NULL. The function
+ EntryPoint must never return.
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit protected mode with flat descriptors. This
+ means all descriptors must have a base of 0 and a limit of 4GB.
+ 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat
+ descriptors.
+ 4) CR3 must point to valid page tables that will be used once the transition
+ is complete, and those page tables must guarantee that the pages for this
+ function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is enabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is enabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is enabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is enabled.
+
+**/
+__declspec (naked)
+VOID
+EFIAPI
+InternalX86EnablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack
+ )
+{
+ _asm {
+ push ebp
+ mov ebp, esp
+ mov ebx, EntryPoint
+ mov ecx, Context1
+ mov edx, Context2
+ pushfd
+ pop edi
+ cli
+ mov eax, cr0
+ bts eax, 31
+ mov esp, NewStack
+ mov cr0, eax
+ push edi
+ popfd
+ push edx
+ push ecx
+ call ebx
+ jmp $
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging32.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging32.nasm new file mode 100644 index 000000000..3f00167b3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging32.nasm @@ -0,0 +1,48 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; EnablePaging32.Asm
+;
+; Abstract:
+;
+; AsmEnablePaging32 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86EnablePaging32 (
+; IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+; IN VOID *Context1, OPTIONAL
+; IN VOID *Context2, OPTIONAL
+; IN VOID *NewStack
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86EnablePaging32)
+ASM_PFX(InternalX86EnablePaging32):
+ mov ebx, [esp + 4]
+ mov ecx, [esp + 8]
+ mov edx, [esp + 12]
+ pushfd
+ pop edi ; save flags in edi
+ cli
+ mov eax, cr0
+ bts eax, 31
+ mov esp, [esp + 16]
+ mov cr0, eax
+ push edi
+ popfd ; restore flags
+ push edx
+ push ecx
+ call ebx
+ jmp $
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm new file mode 100644 index 000000000..544e3c389 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm @@ -0,0 +1,59 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; EnablePaging64.Asm
+;
+; Abstract:
+;
+; AsmEnablePaging64 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86EnablePaging64 (
+; IN UINT16 Cs,
+; IN UINT64 EntryPoint,
+; IN UINT64 Context1, OPTIONAL
+; IN UINT64 Context2, OPTIONAL
+; IN UINT64 NewStack
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86EnablePaging64)
+ASM_PFX(InternalX86EnablePaging64):
+ cli
+ mov DWORD [esp], .0 ; offset for far retf, seg is the 1st arg
+ mov eax, cr4
+ or al, (1 << 5)
+ mov cr4, eax ; enable PAE
+ mov ecx, 0xc0000080
+ rdmsr
+ or ah, 1 ; set LME
+ wrmsr
+ mov eax, cr0
+ bts eax, 31 ; set PG
+ mov cr0, eax ; enable paging
+ retf ; topmost 2 dwords hold the address
+.0:
+ DB 0x67, 0x48 ; 32-bit address size, 64-bit operand size
+ mov ebx, [esp] ; mov rbx, [esp]
+ DB 0x67, 0x48
+ mov ecx, [esp + 8] ; mov rcx, [esp + 8]
+ DB 0x67, 0x48
+ mov edx, [esp + 0x10] ; mov rdx, [esp + 10h]
+ DB 0x67, 0x48
+ mov esp, [esp + 0x18] ; mov rsp, [esp + 18h]
+ DB 0x48
+ add esp, -0x20 ; add rsp, -20h
+ call ebx ; call rbx
+ hlt ; no one should get here
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c new file mode 100644 index 000000000..8fbda0670 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c @@ -0,0 +1,52 @@ +/** @file
+ AsmFlushCacheLine function
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Flushes a cache line from all the instruction and data caches within the
+ coherency domain of the CPU.
+
+ Flushed the cache line specified by LinearAddress, and returns LinearAddress.
+ This function is only available on IA-32 and x64.
+
+ @param LinearAddress The address of the cache line to flush. If the CPU is
+ in a physical addressing mode, then LinearAddress is a
+ physical address. If the CPU is in a virtual
+ addressing mode, then LinearAddress is a virtual
+ address.
+
+ @return LinearAddress
+**/
+VOID *
+EFIAPI
+AsmFlushCacheLine (
+ IN VOID *LinearAddress
+ )
+{
+ //
+ // If the CPU does not support CLFLUSH instruction,
+ // then promote flush range to flush entire cache.
+ //
+ _asm {
+ mov eax, 1
+ cpuid
+ test edx, BIT19
+ jz NoClflush
+ mov eax, dword ptr [LinearAddress]
+ clflush [eax]
+ jmp Done
+NoClflush:
+ wbinvd
+Done:
+ }
+
+ return LinearAddress;
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.nasm new file mode 100644 index 000000000..8afd4cbdc --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.nasm @@ -0,0 +1,45 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; FlushCacheLine.Asm
+;
+; Abstract:
+;
+; AsmFlushCacheLine function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID *
+; EFIAPI
+; AsmFlushCacheLine (
+; IN VOID *LinearAddress
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmFlushCacheLine)
+ASM_PFX(AsmFlushCacheLine):
+ ;
+ ; If the CPU does not support CLFLUSH instruction,
+ ; then promote flush range to flush entire cache.
+ ;
+ mov eax, 1
+ push ebx
+ cpuid
+ pop ebx
+ mov eax, [esp + 4]
+ test edx, BIT19
+ jz .0
+ clflush [eax]
+ ret
+.0:
+ wbinvd
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxRestore.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxRestore.c new file mode 100644 index 000000000..ddd1e4903 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxRestore.c @@ -0,0 +1,34 @@ +/** @file
+ AsmFxRestore function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+
+/**
+ Restores the current floating point/SSE/SSE2 context from a buffer.
+
+ Restores the current floating point/SSE/SSE2 state from the buffer specified
+ by Buffer. Buffer must be aligned on a 16-byte boundary. This function is
+ only available on IA-32 and x64.
+
+ @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context.
+
+**/
+VOID
+EFIAPI
+InternalX86FxRestore (
+ IN CONST IA32_FX_BUFFER *Buffer
+ )
+{
+ _asm {
+ mov eax, Buffer
+ fxrstor [eax]
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxRestore.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxRestore.nasm new file mode 100644 index 000000000..c48746890 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxRestore.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; FxRestore.Asm
+;
+; Abstract:
+;
+; AsmFxRestore function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86FxRestore (
+; IN CONST IA32_FX_BUFFER *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86FxRestore)
+ASM_PFX(InternalX86FxRestore):
+ mov eax, [esp + 4] ; Buffer must be 16-byte aligned
+ fxrstor [eax]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxSave.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxSave.c new file mode 100644 index 000000000..a8c888217 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxSave.c @@ -0,0 +1,34 @@ +/** @file
+ AsmFxSave function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+
+/**
+ Save the current floating point/SSE/SSE2 context to a buffer.
+
+ Saves the current floating point/SSE/SSE2 state to the buffer specified by
+ Buffer. Buffer must be aligned on a 16-byte boundary. This function is only
+ available on IA-32 and x64.
+
+ @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context.
+
+**/
+VOID
+EFIAPI
+InternalX86FxSave (
+ OUT IA32_FX_BUFFER *Buffer
+ )
+{
+ _asm {
+ mov eax, Buffer
+ fxsave [eax]
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxSave.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxSave.nasm new file mode 100644 index 000000000..c1982c064 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/FxSave.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; FxSave.Asm
+;
+; Abstract:
+;
+; AsmFxSave function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86FxSave (
+; OUT IA32_FX_BUFFER *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86FxSave)
+ASM_PFX(InternalX86FxSave):
+ mov eax, [esp + 4] ; Buffer must be 16-byte aligned
+ fxsave [eax]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/GccInline.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/GccInline.c new file mode 100644 index 000000000..6ed938187 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/GccInline.c @@ -0,0 +1,586 @@ +/** @file
+ GCC inline implementation of BaseLib processor specific functions.
+
+ Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Used to serialize load and store operations.
+
+ All loads and stores that proceed calls to this function are guaranteed to be
+ globally visible when this function returns.
+
+**/
+VOID
+EFIAPI
+MemoryFence (
+ VOID
+ )
+{
+ // This is a little bit of overkill and it is more about the compiler that it is
+ // actually processor synchronization. This is like the _ReadWriteBarrier
+ // Microsoft specific intrinsic
+ __asm__ __volatile__ ("":::"memory");
+}
+
+/**
+ Requests CPU to pause for a short period of time.
+
+ Requests CPU to pause for a short period of time. Typically used in MP
+ systems to prevent memory starvation while waiting for a spin lock.
+
+**/
+VOID
+EFIAPI
+CpuPause (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("pause");
+}
+
+/**
+ Generates a breakpoint on the CPU.
+
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such
+ that code can resume normal execution after the breakpoint.
+
+**/
+VOID
+EFIAPI
+CpuBreakpoint (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("int $3");
+}
+
+/**
+ Reads the current value of the EFLAGS register.
+
+ Reads and returns the current value of the EFLAGS register. This function is
+ only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a
+ 64-bit value on X64.
+
+ @return EFLAGS on IA-32 or RFLAGS on X64.
+
+**/
+UINTN
+EFIAPI
+AsmReadEflags (
+ VOID
+ )
+{
+ UINTN Eflags;
+
+ __asm__ __volatile__ (
+ "pushfl \n\t"
+ "popl %0 "
+ : "=r" (Eflags)
+ );
+
+ return Eflags;
+}
+
+/**
+ Save the current floating point/SSE/SSE2 context to a buffer.
+
+ Saves the current floating point/SSE/SSE2 state to the buffer specified by
+ Buffer. Buffer must be aligned on a 16-byte boundary. This function is only
+ available on IA-32 and X64.
+
+ @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context.
+
+**/
+VOID
+EFIAPI
+InternalX86FxSave (
+ OUT IA32_FX_BUFFER *Buffer
+ )
+{
+ __asm__ __volatile__ (
+ "fxsave %0"
+ :
+ : "m" (*Buffer) // %0
+ );
+}
+
+
+/**
+ Restores the current floating point/SSE/SSE2 context from a buffer.
+
+ Restores the current floating point/SSE/SSE2 state from the buffer specified
+ by Buffer. Buffer must be aligned on a 16-byte boundary. This function is
+ only available on IA-32 and X64.
+
+ @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context.
+
+**/
+VOID
+EFIAPI
+InternalX86FxRestore (
+ IN CONST IA32_FX_BUFFER *Buffer
+ )
+{
+ __asm__ __volatile__ (
+ "fxrstor %0"
+ :
+ : "m" (*Buffer) // %0
+ );
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #0 (MM0).
+
+ Reads and returns the current value of MM0. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM0.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm0 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "push %%eax \n\t"
+ "push %%eax \n\t"
+ "movq %%mm0, (%%esp)\n\t"
+ "pop %%eax \n\t"
+ "pop %%edx \n\t"
+ : "=A" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #1 (MM1).
+
+ Reads and returns the current value of MM1. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM1.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm1 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "push %%eax \n\t"
+ "push %%eax \n\t"
+ "movq %%mm1, (%%esp)\n\t"
+ "pop %%eax \n\t"
+ "pop %%edx \n\t"
+ : "=A" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #2 (MM2).
+
+ Reads and returns the current value of MM2. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM2.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm2 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "push %%eax \n\t"
+ "push %%eax \n\t"
+ "movq %%mm2, (%%esp)\n\t"
+ "pop %%eax \n\t"
+ "pop %%edx \n\t"
+ : "=A" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #3 (MM3).
+
+ Reads and returns the current value of MM3. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM3.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm3 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "push %%eax \n\t"
+ "push %%eax \n\t"
+ "movq %%mm3, (%%esp)\n\t"
+ "pop %%eax \n\t"
+ "pop %%edx \n\t"
+ : "=A" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #4 (MM4).
+
+ Reads and returns the current value of MM4. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM4.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm4 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "push %%eax \n\t"
+ "push %%eax \n\t"
+ "movq %%mm4, (%%esp)\n\t"
+ "pop %%eax \n\t"
+ "pop %%edx \n\t"
+ : "=A" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #5 (MM5).
+
+ Reads and returns the current value of MM5. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM5.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm5 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "push %%eax \n\t"
+ "push %%eax \n\t"
+ "movq %%mm5, (%%esp)\n\t"
+ "pop %%eax \n\t"
+ "pop %%edx \n\t"
+ : "=A" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #6 (MM6).
+
+ Reads and returns the current value of MM6. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM6.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm6 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "push %%eax \n\t"
+ "push %%eax \n\t"
+ "movq %%mm6, (%%esp)\n\t"
+ "pop %%eax \n\t"
+ "pop %%edx \n\t"
+ : "=A" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #7 (MM7).
+
+ Reads and returns the current value of MM7. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM7.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm7 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "push %%eax \n\t"
+ "push %%eax \n\t"
+ "movq %%mm7, (%%esp)\n\t"
+ "pop %%eax \n\t"
+ "pop %%edx \n\t"
+ : "=A" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #0 (MM0).
+
+ Writes the current value of MM0. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM0.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm0 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movq %0, %%mm0" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #1 (MM1).
+
+ Writes the current value of MM1. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM1.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm1 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movq %0, %%mm1" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #2 (MM2).
+
+ Writes the current value of MM2. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM2.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm2 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movq %0, %%mm2" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #3 (MM3).
+
+ Writes the current value of MM3. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM3.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm3 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movq %0, %%mm3" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #4 (MM4).
+
+ Writes the current value of MM4. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM4.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm4 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movq %0, %%mm4" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #5 (MM5).
+
+ Writes the current value of MM5. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM5.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm5 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movq %0, %%mm5" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #6 (MM6).
+
+ Writes the current value of MM6. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM6.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm6 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movq %0, %%mm6" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #7 (MM7).
+
+ Writes the current value of MM7. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM7.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm7 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movq %0, %%mm7" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Reads the current value of Time Stamp Counter (TSC).
+
+ Reads and returns the current value of TSC. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of TSC
+
+**/
+UINT64
+EFIAPI
+AsmReadTsc (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "rdtsc"
+ : "=A" (Data)
+ );
+
+ return Data;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c new file mode 100644 index 000000000..30aa63243 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c @@ -0,0 +1,1170 @@ +/** @file
+ GCC inline implementation of BaseLib processor specific functions that use
+ privlidged instructions.
+
+ Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Enables CPU interrupts.
+
+ Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+EnableInterrupts (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("sti"::: "memory");
+}
+
+
+/**
+ Disables CPU interrupts.
+
+ Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+DisableInterrupts (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("cli"::: "memory");
+}
+
+/**
+ Returns a 64-bit Machine Specific Register(MSR).
+
+ Reads and returns the 64-bit MSR specified by Index. No parameter checking is
+ performed on Index, and some Index values may cause CPU exceptions. The
+ caller must either guarantee that Index is valid, or the caller must set up
+ exception handlers to catch the exceptions. This function is only available
+ on IA-32 and X64.
+
+ @param Index The 32-bit MSR index to read.
+
+ @return The value of the MSR identified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadMsr64 (
+ IN UINT32 Index
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "rdmsr"
+ : "=A" (Data) // %0
+ : "c" (Index) // %1
+ );
+
+ return Data;
+}
+
+/**
+ Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
+ value.
+
+ Writes the 64-bit value specified by Value to the MSR specified by Index. The
+ 64-bit value written to the MSR is returned. No parameter checking is
+ performed on Index or Value, and some of these may cause CPU exceptions. The
+ caller must either guarantee that Index and Value are valid, or the caller
+ must establish proper exception handlers. This function is only available on
+ IA-32 and X64.
+
+ @param Index The 32-bit MSR index to write.
+ @param Value The 64-bit value to write to the MSR.
+
+ @return Value
+
+**/
+UINT64
+EFIAPI
+AsmWriteMsr64 (
+ IN UINT32 Index,
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "wrmsr"
+ :
+ : "c" (Index),
+ "A" (Value)
+ );
+
+ return Value;
+}
+
+/**
+ Reads the current value of the Control Register 0 (CR0).
+
+ Reads and returns the current value of CR0. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of the Control Register 0 (CR0).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr0 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "movl %%cr0,%0"
+ : "=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of the Control Register 2 (CR2).
+
+ Reads and returns the current value of CR2. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of the Control Register 2 (CR2).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr2 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "movl %%cr2, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+/**
+ Reads the current value of the Control Register 3 (CR3).
+
+ Reads and returns the current value of CR3. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of the Control Register 3 (CR3).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr3 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "movl %%cr3, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of the Control Register 4 (CR4).
+
+ Reads and returns the current value of CR4. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of the Control Register 4 (CR4).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr4 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "movl %%cr4, %0"
+ : "=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Writes a value to Control Register 0 (CR0).
+
+ Writes and returns a new value to CR0. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Cr0 The value to write to CR0.
+
+ @return The value written to CR0.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr0 (
+ UINTN Cr0
+ )
+{
+ __asm__ __volatile__ (
+ "movl %0, %%cr0"
+ :
+ : "r" (Cr0)
+ );
+ return Cr0;
+}
+
+
+/**
+ Writes a value to Control Register 2 (CR2).
+
+ Writes and returns a new value to CR2. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Cr2 The value to write to CR2.
+
+ @return The value written to CR2.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr2 (
+ UINTN Cr2
+ )
+{
+ __asm__ __volatile__ (
+ "movl %0, %%cr2"
+ :
+ : "r" (Cr2)
+ );
+ return Cr2;
+}
+
+
+/**
+ Writes a value to Control Register 3 (CR3).
+
+ Writes and returns a new value to CR3. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Cr3 The value to write to CR3.
+
+ @return The value written to CR3.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr3 (
+ UINTN Cr3
+ )
+{
+ __asm__ __volatile__ (
+ "movl %0, %%cr3"
+ :
+ : "r" (Cr3)
+ );
+ return Cr3;
+}
+
+
+/**
+ Writes a value to Control Register 4 (CR4).
+
+ Writes and returns a new value to CR4. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Cr4 The value to write to CR4.
+
+ @return The value written to CR4.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr4 (
+ UINTN Cr4
+ )
+{
+ __asm__ __volatile__ (
+ "movl %0, %%cr4"
+ :
+ : "r" (Cr4)
+ );
+ return Cr4;
+}
+
+
+/**
+ Reads the current value of Debug Register 0 (DR0).
+
+ Reads and returns the current value of DR0. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr0 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "movl %%dr0, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 1 (DR1).
+
+ Reads and returns the current value of DR1. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr1 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "movl %%dr1, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 2 (DR2).
+
+ Reads and returns the current value of DR2. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr2 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "movl %%dr2, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 3 (DR3).
+
+ Reads and returns the current value of DR3. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr3 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "movl %%dr3, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 4 (DR4).
+
+ Reads and returns the current value of DR4. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr4 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "movl %%dr4, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 5 (DR5).
+
+ Reads and returns the current value of DR5. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr5 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "movl %%dr5, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 6 (DR6).
+
+ Reads and returns the current value of DR6. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr6 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "movl %%dr6, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 7 (DR7).
+
+ Reads and returns the current value of DR7. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr7 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "movl %%dr7, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Writes a value to Debug Register 0 (DR0).
+
+ Writes and returns a new value to DR0. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr0 The value to write to Dr0.
+
+ @return The value written to Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr0 (
+ UINTN Dr0
+ )
+{
+ __asm__ __volatile__ (
+ "movl %0, %%dr0"
+ :
+ : "r" (Dr0)
+ );
+ return Dr0;
+}
+
+
+/**
+ Writes a value to Debug Register 1 (DR1).
+
+ Writes and returns a new value to DR1. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr1 The value to write to Dr1.
+
+ @return The value written to Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr1 (
+ UINTN Dr1
+ )
+{
+ __asm__ __volatile__ (
+ "movl %0, %%dr1"
+ :
+ : "r" (Dr1)
+ );
+ return Dr1;
+}
+
+
+/**
+ Writes a value to Debug Register 2 (DR2).
+
+ Writes and returns a new value to DR2. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr2 The value to write to Dr2.
+
+ @return The value written to Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr2 (
+ UINTN Dr2
+ )
+{
+ __asm__ __volatile__ (
+ "movl %0, %%dr2"
+ :
+ : "r" (Dr2)
+ );
+ return Dr2;
+}
+
+
+/**
+ Writes a value to Debug Register 3 (DR3).
+
+ Writes and returns a new value to DR3. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr3 The value to write to Dr3.
+
+ @return The value written to Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr3 (
+ UINTN Dr3
+ )
+{
+ __asm__ __volatile__ (
+ "movl %0, %%dr3"
+ :
+ : "r" (Dr3)
+ );
+ return Dr3;
+}
+
+
+/**
+ Writes a value to Debug Register 4 (DR4).
+
+ Writes and returns a new value to DR4. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr4 The value to write to Dr4.
+
+ @return The value written to Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr4 (
+ UINTN Dr4
+ )
+{
+ __asm__ __volatile__ (
+ "movl %0, %%dr4"
+ :
+ : "r" (Dr4)
+ );
+ return Dr4;
+}
+
+
+/**
+ Writes a value to Debug Register 5 (DR5).
+
+ Writes and returns a new value to DR5. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr5 The value to write to Dr5.
+
+ @return The value written to Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr5 (
+ UINTN Dr5
+ )
+{
+ __asm__ __volatile__ (
+ "movl %0, %%dr5"
+ :
+ : "r" (Dr5)
+ );
+ return Dr5;
+}
+
+
+/**
+ Writes a value to Debug Register 6 (DR6).
+
+ Writes and returns a new value to DR6. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr6 The value to write to Dr6.
+
+ @return The value written to Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr6 (
+ UINTN Dr6
+ )
+{
+ __asm__ __volatile__ (
+ "movl %0, %%dr6"
+ :
+ : "r" (Dr6)
+ );
+ return Dr6;
+}
+
+
+/**
+ Writes a value to Debug Register 7 (DR7).
+
+ Writes and returns a new value to DR7. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr7 The value to write to Dr7.
+
+ @return The value written to Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr7 (
+ UINTN Dr7
+ )
+{
+ __asm__ __volatile__ (
+ "movl %0, %%dr7"
+ :
+ : "r" (Dr7)
+ );
+ return Dr7;
+}
+
+
+/**
+ Reads the current value of Code Segment Register (CS).
+
+ Reads and returns the current value of CS. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of CS.
+
+**/
+UINT16
+EFIAPI
+AsmReadCs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%cs, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Data Segment Register (DS).
+
+ Reads and returns the current value of DS. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of DS.
+
+**/
+UINT16
+EFIAPI
+AsmReadDs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%ds, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Extra Segment Register (ES).
+
+ Reads and returns the current value of ES. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of ES.
+
+**/
+UINT16
+EFIAPI
+AsmReadEs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%es, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of FS Data Segment Register (FS).
+
+ Reads and returns the current value of FS. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of FS.
+
+**/
+UINT16
+EFIAPI
+AsmReadFs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%fs, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of GS Data Segment Register (GS).
+
+ Reads and returns the current value of GS. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of GS.
+
+**/
+UINT16
+EFIAPI
+AsmReadGs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%gs, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Stack Segment Register (SS).
+
+ Reads and returns the current value of SS. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of SS.
+
+**/
+UINT16
+EFIAPI
+AsmReadSs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%ds, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Task Register (TR).
+
+ Reads and returns the current value of TR. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of TR.
+
+**/
+UINT16
+EFIAPI
+AsmReadTr (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "str %0"
+ : "=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current Global Descriptor Table Register(GDTR) descriptor.
+
+ Reads and returns the current GDTR descriptor and returns it in Gdtr. This
+ function is only available on IA-32 and X64.
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86ReadGdtr (
+ OUT IA32_DESCRIPTOR *Gdtr
+ )
+{
+ __asm__ __volatile__ (
+ "sgdt %0"
+ : "=m" (*Gdtr)
+ );
+}
+
+
+/**
+ Writes the current Global Descriptor Table Register (GDTR) descriptor.
+
+ Writes and the current GDTR descriptor specified by Gdtr. This function is
+ only available on IA-32 and X64.
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86WriteGdtr (
+ IN CONST IA32_DESCRIPTOR *Gdtr
+ )
+{
+ __asm__ __volatile__ (
+ "lgdt %0"
+ :
+ : "m" (*Gdtr)
+ );
+
+}
+
+
+/**
+ Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.
+
+ Reads and returns the current IDTR descriptor and returns it in Idtr. This
+ function is only available on IA-32 and X64.
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86ReadIdtr (
+ OUT IA32_DESCRIPTOR *Idtr
+ )
+{
+ __asm__ __volatile__ (
+ "sidt %0"
+ : "=m" (*Idtr)
+ );
+}
+
+
+/**
+ Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.
+
+ Writes the current IDTR descriptor and returns it in Idtr. This function is
+ only available on IA-32 and X64.
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86WriteIdtr (
+ IN CONST IA32_DESCRIPTOR *Idtr
+ )
+{
+ __asm__ __volatile__ (
+ "lidt %0"
+ :
+ : "m" (*Idtr)
+ );
+}
+
+
+/**
+ Reads the current Local Descriptor Table Register(LDTR) selector.
+
+ Reads and returns the current 16-bit LDTR descriptor value. This function is
+ only available on IA-32 and X64.
+
+ @return The current selector of LDT.
+
+**/
+UINT16
+EFIAPI
+AsmReadLdtr (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "sldt %0"
+ : "=g" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Writes the current Local Descriptor Table Register (GDTR) selector.
+
+ Writes and the current LDTR descriptor specified by Ldtr. This function is
+ only available on IA-32 and X64.
+
+ @param Ldtr 16-bit LDTR selector value.
+
+**/
+VOID
+EFIAPI
+AsmWriteLdtr (
+ IN UINT16 Ldtr
+ )
+{
+ __asm__ __volatile__ (
+ "lldtw %0"
+ :
+ : "g" (Ldtr) // %0
+ );
+}
+
+/**
+ Reads the current value of a Performance Counter (PMC).
+
+ Reads and returns the current value of performance counter specified by
+ Index. This function is only available on IA-32 and X64.
+
+ @param Index The 32-bit Performance Counter index to read.
+
+ @return The value of the PMC specified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadPmc (
+ IN UINT32 Index
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "rdpmc"
+ : "=A" (Data)
+ : "c" (Index)
+ );
+
+ return Data;
+}
+
+/**
+ Executes a WBINVD instruction.
+
+ Executes a WBINVD instruction. This function is only available on IA-32 and
+ X64.
+
+**/
+VOID
+EFIAPI
+AsmWbinvd (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("wbinvd":::"memory");
+}
+
+/**
+ Executes a INVD instruction.
+
+ Executes a INVD instruction. This function is only available on IA-32 and
+ X64.
+
+**/
+VOID
+EFIAPI
+AsmInvd (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("invd":::"memory");
+
+}
+
+
+/**
+ Flushes a cache line from all the instruction and data caches within the
+ coherency domain of the CPU.
+
+ Flushed the cache line specified by LinearAddress, and returns LinearAddress.
+ This function is only available on IA-32 and X64.
+
+ @param LinearAddress The address of the cache line to flush. If the CPU is
+ in a physical addressing mode, then LinearAddress is a
+ physical address. If the CPU is in a virtual
+ addressing mode, then LinearAddress is a virtual
+ address.
+
+ @return LinearAddress
+**/
+VOID *
+EFIAPI
+AsmFlushCacheLine (
+ IN VOID *LinearAddress
+ )
+{
+ UINT32 RegEdx;
+
+ //
+ // If the CPU does not support CLFLUSH instruction,
+ // then promote flush range to flush entire cache.
+ //
+ AsmCpuid (0x01, NULL, NULL, NULL, &RegEdx);
+ if ((RegEdx & BIT19) == 0) {
+ __asm__ __volatile__ ("wbinvd":::"memory");
+ return LinearAddress;
+ }
+
+
+ __asm__ __volatile__ (
+ "clflush (%0)"
+ : "+a" (LinearAddress)
+ :
+ : "memory"
+ );
+
+ return LinearAddress;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.c new file mode 100644 index 000000000..6f4cf79e6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.c @@ -0,0 +1,54 @@ +/** @file
+ SwitchStack() function for IA-32.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Transfers control to a function starting with a new stack.
+
+ Transfers control to the function specified by EntryPoint using the
+ new stack specified by NewStack and passing in the parameters specified
+ by Context1 and Context2. Context1 and Context2 are optional and may
+ be NULL. The function EntryPoint must never return.
+ Marker will be ignored on IA-32, x64, and EBC.
+ IPF CPUs expect one additional parameter of type VOID * that specifies
+ the new backing store pointer.
+
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ @param EntryPoint A pointer to function to call with the new stack.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function.
+ @param Marker VA_LIST marker for the variable argument list.
+
+**/
+VOID
+EFIAPI
+InternalSwitchStack (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack,
+ IN VA_LIST Marker
+ )
+{
+ BASE_LIBRARY_JUMP_BUFFER JumpBuffer;
+
+ JumpBuffer.Eip = (UINTN)EntryPoint;
+ JumpBuffer.Esp = (UINTN)NewStack - sizeof (VOID*);
+ JumpBuffer.Esp -= sizeof (Context1) + sizeof (Context2);
+ ((VOID**)JumpBuffer.Esp)[1] = Context1;
+ ((VOID**)JumpBuffer.Esp)[2] = Context2;
+
+ LongJump (&JumpBuffer, (UINTN)-1);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.nasm new file mode 100644 index 000000000..adfcdf779 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.nasm @@ -0,0 +1,41 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2011, Apple Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; InternalSwitchStack.nasm
+;
+; Abstract:
+;
+; Implementation of a stack switch on IA-32.
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalSwitchStack (
+; IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+; IN VOID *Context1, OPTIONAL
+; IN VOID *Context2, OPTIONAL
+; IN VOID *NewStack
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalSwitchStack)
+ASM_PFX(InternalSwitchStack):
+ push ebp
+ mov ebp, esp
+
+ mov esp, [ebp + 20] ; switch stack
+ sub esp, 8
+ mov eax, [ebp + 16]
+ mov [esp + 4], eax
+ mov eax, [ebp + 12]
+ mov [esp], eax
+ push 0 ; keeps gdb from unwinding stack
+ jmp dword [ebp + 8] ; call and never return
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Invd.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Invd.c new file mode 100644 index 000000000..9870cf9c6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Invd.c @@ -0,0 +1,29 @@ +/** @file
+ AsmInvd function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Executes a INVD instruction.
+
+ Executes a INVD instruction. This function is only available on IA-32 and
+ x64.
+
+**/
+VOID
+EFIAPI
+AsmInvd (
+ VOID
+ )
+{
+ _asm {
+ invd
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Invd.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Invd.nasm new file mode 100644 index 000000000..f6d1beb1b --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Invd.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Invd.Asm
+;
+; Abstract:
+;
+; AsmInvd function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmInvd (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmInvd)
+ASM_PFX(AsmInvd):
+ invd
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/LRotU64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LRotU64.c new file mode 100644 index 000000000..87d370c6f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LRotU64.c @@ -0,0 +1,49 @@ +/** @file
+ 64-bit left rotation for Ia32
+
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Rotates a 64-bit integer left between 0 and 63 bits, filling
+ the low bits with the high bits that were rotated.
+
+ This function rotates the 64-bit value Operand to the left by Count bits. The
+ low Count bits are fill with the high Count bits of Operand. The rotated
+ value is returned.
+
+ @param Operand The 64-bit operand to rotate left.
+ @param Count The number of bits to rotate left.
+
+ @return Operand <<< Count
+
+**/
+UINT64
+EFIAPI
+InternalMathLRotU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ )
+{
+ _asm {
+ mov cl, byte ptr [Count]
+ mov edx, dword ptr [Operand + 4]
+ mov eax, dword ptr [Operand + 0]
+ shld ebx, edx, cl
+ shld edx, eax, cl
+ ror ebx, cl
+ shld eax, ebx, cl
+ test cl, 32 ; Count >= 32?
+ jz L0
+ mov ecx, eax
+ mov eax, edx
+ mov edx, ecx
+L0:
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/LRotU64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LRotU64.nasm new file mode 100644 index 000000000..3922ae229 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LRotU64.nasm @@ -0,0 +1,44 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; LRotU64.nasm
+;
+; Abstract:
+;
+; 64-bit left rotation for Ia32
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; InternalMathLRotU64 (
+; IN UINT64 Operand,
+; IN UINTN Count
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalMathLRotU64)
+ASM_PFX(InternalMathLRotU64):
+ push ebx
+ mov cl, [esp + 16]
+ mov edx, [esp + 12]
+ mov eax, [esp + 8]
+ shld ebx, edx, cl
+ shld edx, eax, cl
+ ror ebx, cl
+ shld eax, ebx, cl
+ test cl, 32 ; Count >= 32?
+ jz .0
+ mov ecx, eax
+ mov eax, edx
+ mov edx, ecx
+.0:
+ pop ebx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/LShiftU64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LShiftU64.c new file mode 100644 index 000000000..1604e7e2f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LShiftU64.c @@ -0,0 +1,45 @@ +/** @file
+ 64-bit left shift function for IA-32.
+
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Shifts a 64-bit integer left between 0 and 63 bits. The low bits
+ are filled with zeros. The shifted value is returned.
+
+ This function shifts the 64-bit value Operand to the left by Count bits. The
+ low Count bits are set to zero. The shifted value is returned.
+
+ @param Operand The 64-bit operand to shift left.
+ @param Count The number of bits to shift left.
+
+ @return Operand << Count
+
+**/
+UINT64
+EFIAPI
+InternalMathLShiftU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ )
+{
+ _asm {
+ mov cl, byte ptr [Count]
+ xor eax, eax
+ mov edx, dword ptr [Operand + 0]
+ test cl, 32 // Count >= 32?
+ jnz L0
+ mov eax, edx
+ mov edx, dword ptr [Operand + 4]
+L0:
+ shld edx, eax, cl
+ shl eax, cl
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/LShiftU64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LShiftU64.nasm new file mode 100644 index 000000000..26c38a122 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LShiftU64.nasm @@ -0,0 +1,39 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; LShiftU64.nasm
+;
+; Abstract:
+;
+; 64-bit left shift function for IA-32
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; InternalMathLShiftU64 (
+; IN UINT64 Operand,
+; IN UINTN Count
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalMathLShiftU64)
+ASM_PFX(InternalMathLShiftU64):
+ mov cl, [esp + 12]
+ xor eax, eax
+ mov edx, [esp + 4]
+ test cl, 32 ; Count >= 32?
+ jnz .0
+ mov eax, edx
+ mov edx, [esp + 8]
+.0:
+ shld edx, eax, cl
+ shl eax, cl
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Lfence.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Lfence.nasm new file mode 100644 index 000000000..44478be35 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Lfence.nasm @@ -0,0 +1,30 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Lfence.nasm
+;
+; Abstract:
+;
+; Performs a serializing operation on all load-from-memory instructions that
+; were issued prior to the call of this function.
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmLfence (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmLfence)
+ASM_PFX(AsmLfence):
+ lfence
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/LongJump.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LongJump.nasm new file mode 100644 index 000000000..f94d10f80 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/LongJump.nasm @@ -0,0 +1,60 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; LongJump.Asm
+;
+; Abstract:
+;
+; Implementation of _LongJump() on IA-32.
+;
+;------------------------------------------------------------------------------
+
+%include "Nasm.inc"
+
+ SECTION .text
+
+extern ASM_PFX(PcdGet32 (PcdControlFlowEnforcementPropertyMask))
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalLongJump (
+; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalLongJump)
+ASM_PFX(InternalLongJump):
+
+ mov eax, [ASM_PFX(PcdGet32 (PcdControlFlowEnforcementPropertyMask))]
+ test eax, eax
+ jz CetDone
+ mov eax, cr4
+ bt eax, 23 ; check if CET is enabled
+ jnc CetDone
+
+ mov edx, [esp + 4] ; edx = JumpBuffer
+ mov edx, [edx + 24] ; edx = target SSP
+ READSSP_EAX
+ sub edx, eax ; edx = delta
+ mov eax, edx ; eax = delta
+
+ shr eax, 2 ; eax = delta/sizeof(UINT32)
+ INCSSP_EAX
+
+CetDone:
+
+ pop eax ; skip return address
+ pop edx ; edx <- JumpBuffer
+ pop eax ; eax <- Value
+ mov ebx, [edx]
+ mov esi, [edx + 4]
+ mov edi, [edx + 8]
+ mov ebp, [edx + 12]
+ mov esp, [edx + 16]
+ jmp dword [edx + 20] ; restore "eip"
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ModU64x32.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ModU64x32.c new file mode 100644 index 000000000..26a19cbd9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ModU64x32.c @@ -0,0 +1,42 @@ +/** @file
+ Calculate the remainder of a 64-bit integer by a 32-bit integer
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and
+ generates a 32-bit unsigned remainder.
+
+ This function divides the 64-bit unsigned value Dividend by the 32-bit
+ unsigned value Divisor and generates a 32-bit remainder. This function
+ returns the 32-bit unsigned remainder.
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 32-bit unsigned value.
+
+ @return Dividend % Divisor
+
+**/
+UINT32
+EFIAPI
+InternalMathModU64x32 (
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
+ )
+{
+ _asm {
+ mov eax, dword ptr [Dividend + 4]
+ mov ecx, Divisor
+ xor edx, edx
+ div ecx
+ mov eax, dword ptr [Dividend + 0]
+ div ecx
+ mov eax, edx
+ }
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ModU64x32.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ModU64x32.nasm new file mode 100644 index 000000000..9f05fded3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ModU64x32.nasm @@ -0,0 +1,36 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; DivU64x32.asm
+;
+; Abstract:
+;
+; Calculate the remainder of a 64-bit integer by a 32-bit integer
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT32
+; EFIAPI
+; InternalMathModU64x32 (
+; IN UINT64 Dividend,
+; IN UINT32 Divisor
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalMathModU64x32)
+ASM_PFX(InternalMathModU64x32):
+ mov eax, [esp + 8]
+ mov ecx, [esp + 12]
+ xor edx, edx
+ div ecx
+ mov eax, [esp + 4]
+ div ecx
+ mov eax, edx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Monitor.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Monitor.c new file mode 100644 index 000000000..966b128a3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Monitor.c @@ -0,0 +1,42 @@ +/** @file
+ AsmMonitor function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Sets up a monitor buffer that is used by AsmMwait().
+
+ Executes a MONITOR instruction with the register state specified by Eax, Ecx
+ and Edx. Returns Eax. This function is only available on IA-32 and x64.
+
+ @param RegisterEax The value to load into EAX or RAX before executing the MONITOR
+ instruction.
+ @param RegisterEcx The value to load into ECX or RCX before executing the MONITOR
+ instruction.
+ @param RegisterEdx The value to load into EDX or RDX before executing the MONITOR
+ instruction.
+
+ @return RegisterEax
+
+**/
+UINTN
+EFIAPI
+AsmMonitor (
+ IN UINTN RegisterEax,
+ IN UINTN RegisterEcx,
+ IN UINTN RegisterEdx
+ )
+{
+ _asm {
+ mov eax, RegisterEax
+ mov ecx, RegisterEcx
+ mov edx, RegisterEdx
+ _emit 0x0f // monitor
+ _emit 0x01
+ _emit 0xc8
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Monitor.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Monitor.nasm new file mode 100644 index 000000000..28dc0ba70 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Monitor.nasm @@ -0,0 +1,36 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Monitor.Asm
+;
+; Abstract:
+;
+; AsmMonitor function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmMonitor (
+; IN UINTN Eax,
+; IN UINTN Ecx,
+; IN UINTN Edx
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmMonitor)
+ASM_PFX(AsmMonitor):
+ mov eax, [esp + 4]
+ mov ecx, [esp + 8]
+ mov edx, [esp + 12]
+ DB 0xf, 1, 0xc8 ; monitor
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x32.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x32.c new file mode 100644 index 000000000..a72868464 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x32.c @@ -0,0 +1,41 @@ +/** @file
+ Calculate the product of a 64-bit integer and a 32-bit integer
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Multiples a 64-bit unsigned integer by a 32-bit unsigned integer
+ and generates a 64-bit unsigned result.
+
+ This function multiples the 64-bit unsigned value Multiplicand by the 32-bit
+ unsigned value Multiplier and generates a 64-bit unsigned result. This 64-
+ bit unsigned result is returned.
+
+ @param Multiplicand A 64-bit unsigned value.
+ @param Multiplier A 32-bit unsigned value.
+
+ @return Multiplicand * Multiplier
+
+**/
+UINT64
+EFIAPI
+InternalMathMultU64x32 (
+ IN UINT64 Multiplicand,
+ IN UINT32 Multiplier
+ )
+{
+ _asm {
+ mov ecx, Multiplier
+ mov eax, ecx
+ imul ecx, dword ptr [Multiplicand + 4] // overflow not detectable
+ mul dword ptr [Multiplicand + 0]
+ add edx, ecx
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x32.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x32.nasm new file mode 100644 index 000000000..f7591b120 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x32.nasm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; MultU64x32.nasm
+;
+; Abstract:
+;
+; Calculate the product of a 64-bit integer and a 32-bit integer
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; InternalMathMultU64x32 (
+; IN UINT64 Multiplicand,
+; IN UINT32 Multiplier
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalMathMultU64x32)
+ASM_PFX(InternalMathMultU64x32):
+ mov ecx, [esp + 12]
+ mov eax, ecx
+ imul ecx, [esp + 8] ; overflow not detectable
+ mul dword [esp + 4]
+ add edx, ecx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x64.c new file mode 100644 index 000000000..806cbd565 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x64.c @@ -0,0 +1,45 @@ +/** @file
+ Calculate the product of a 64-bit integer and another 64-bit integer
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Multiplies a 64-bit unsigned integer by a 64-bit unsigned integer
+ and generates a 64-bit unsigned result.
+
+ This function multiplies the 64-bit unsigned value Multiplicand by the 64-bit
+ unsigned value Multiplier and generates a 64-bit unsigned result. This 64-
+ bit unsigned result is returned.
+
+ @param Multiplicand A 64-bit unsigned value.
+ @param Multiplier A 64-bit unsigned value.
+
+ @return Multiplicand * Multiplier
+
+**/
+UINT64
+EFIAPI
+InternalMathMultU64x64 (
+ IN UINT64 Multiplicand,
+ IN UINT64 Multiplier
+ )
+{
+ _asm {
+ mov ebx, dword ptr [Multiplicand + 0]
+ mov edx, dword ptr [Multiplier + 0]
+ mov ecx, ebx
+ mov eax, edx
+ imul ebx, dword ptr [Multiplier + 4]
+ imul edx, dword ptr [Multiplicand + 4]
+ add ebx, edx
+ mul ecx
+ add edx, ebx
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x64.nasm new file mode 100644 index 000000000..c128022f9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/MultU64x64.nasm @@ -0,0 +1,40 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; MultU64x64.nasm
+;
+; Abstract:
+;
+; Calculate the product of a 64-bit integer and another 64-bit integer
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; InternalMathMultU64x64 (
+; IN UINT64 Multiplicand,
+; IN UINT64 Multiplier
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalMathMultU64x64)
+ASM_PFX(InternalMathMultU64x64):
+ push ebx
+ mov ebx, [esp + 8] ; ebx <- M1[0..31]
+ mov edx, [esp + 16] ; edx <- M2[0..31]
+ mov ecx, ebx
+ mov eax, edx
+ imul ebx, [esp + 20] ; ebx <- M1[0..31] * M2[32..63]
+ imul edx, [esp + 12] ; edx <- M1[32..63] * M2[0..31]
+ add ebx, edx ; carries are abandoned
+ mul ecx ; edx:eax <- M1[0..31] * M2[0..31]
+ add edx, ebx ; carries are abandoned
+ pop ebx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Mwait.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Mwait.c new file mode 100644 index 000000000..08c666f79 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Mwait.c @@ -0,0 +1,38 @@ +/** @file
+ AsmMwait function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Executes an MWAIT instruction.
+
+ Executes an MWAIT instruction with the register state specified by Eax and
+ Ecx. Returns Eax. This function is only available on IA-32 and x64.
+
+ @param RegisterEax The value to load into EAX or RAX before executing the MONITOR
+ instruction.
+ @param RegisterEcx The value to load into ECX or RCX before executing the MONITOR
+ instruction.
+
+ @return RegisterEax
+
+**/
+UINTN
+EFIAPI
+AsmMwait (
+ IN UINTN RegisterEax,
+ IN UINTN RegisterEcx
+ )
+{
+ _asm {
+ mov eax, RegisterEax
+ mov ecx, RegisterEcx
+ _emit 0x0f // mwait
+ _emit 0x01
+ _emit 0xC9
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Mwait.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Mwait.nasm new file mode 100644 index 000000000..3956940ca --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Mwait.nasm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Mwait.Asm
+;
+; Abstract:
+;
+; AsmMwait function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmMwait (
+; IN UINTN Eax,
+; IN UINTN Ecx
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmMwait)
+ASM_PFX(AsmMwait):
+ mov eax, [esp + 4]
+ mov ecx, [esp + 8]
+ DB 0xf, 1, 0xc9 ; mwait
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Non-existing.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Non-existing.c new file mode 100644 index 000000000..889ece463 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Non-existing.c @@ -0,0 +1,51 @@ +/** @file
+ Non-existing BaseLib functions on Ia32
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/DebugLib.h>
+
+/**
+ Disables the 64-bit paging mode on the CPU.
+
+ Disables the 64-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 64-paging mode.
+ This function is only available on x64. After the 64-bit paging mode is
+ disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be 0. The function EntryPoint must never return.
+
+ @param CodeSelector The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for 32-bit protected mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is disabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is disabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is disabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+InternalX86DisablePaging64 (
+ IN UINT16 CodeSelector,
+ IN UINT32 EntryPoint,
+ IN UINT32 Context1, OPTIONAL
+ IN UINT32 Context2, OPTIONAL
+ IN UINT32 NewStack
+ )
+{
+ //
+ // This function cannot work on IA32 platform
+ //
+ ASSERT (FALSE);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/RRotU64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RRotU64.c new file mode 100644 index 000000000..82711a5f8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RRotU64.c @@ -0,0 +1,49 @@ +/** @file
+ 64-bit right rotation for Ia32
+
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Rotates a 64-bit integer right between 0 and 63 bits, filling
+ the high bits with the high low bits that were rotated.
+
+ This function rotates the 64-bit value Operand to the right by Count bits.
+ The high Count bits are fill with the low Count bits of Operand. The rotated
+ value is returned.
+
+ @param Operand The 64-bit operand to rotate right.
+ @param Count The number of bits to rotate right.
+
+ @return Operand >>> Count
+
+**/
+UINT64
+EFIAPI
+InternalMathRRotU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ )
+{
+ _asm {
+ mov cl, byte ptr [Count]
+ mov eax, dword ptr [Operand + 0]
+ mov edx, dword ptr [Operand + 4]
+ shrd ebx, eax, cl
+ shrd eax, edx, cl
+ rol ebx, cl
+ shrd edx, ebx, cl
+ test cl, 32 // Count >= 32?
+ jz L0
+ mov ecx, eax
+ mov eax, edx
+ mov edx, ecx
+L0:
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/RRotU64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RRotU64.nasm new file mode 100644 index 000000000..7e4646e1e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RRotU64.nasm @@ -0,0 +1,44 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; RRotU64.nasm
+;
+; Abstract:
+;
+; 64-bit right rotation for Ia32
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; InternalMathRRotU64 (
+; IN UINT64 Operand,
+; IN UINTN Count
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalMathRRotU64)
+ASM_PFX(InternalMathRRotU64):
+ push ebx
+ mov cl, [esp + 16]
+ mov eax, [esp + 8]
+ mov edx, [esp + 12]
+ shrd ebx, eax, cl
+ shrd eax, edx, cl
+ rol ebx, cl
+ shrd edx, ebx, cl
+ test cl, 32 ; Count >= 32?
+ jz .0
+ mov ecx, eax ; switch eax & edx if Count >= 32
+ mov eax, edx
+ mov edx, ecx
+.0:
+ pop ebx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/RShiftU64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RShiftU64.c new file mode 100644 index 000000000..35d843705 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RShiftU64.c @@ -0,0 +1,45 @@ +/** @file
+ 64-bit logical right shift function for IA-32
+
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Shifts a 64-bit integer right between 0 and 63 bits. This high bits
+ are filled with zeros. The shifted value is returned.
+
+ This function shifts the 64-bit value Operand to the right by Count bits. The
+ high Count bits are set to zero. The shifted value is returned.
+
+ @param Operand The 64-bit operand to shift right.
+ @param Count The number of bits to shift right.
+
+ @return Operand >> Count
+
+**/
+UINT64
+EFIAPI
+InternalMathRShiftU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ )
+{
+ _asm {
+ mov cl, byte ptr [Count]
+ xor edx, edx
+ mov eax, dword ptr [Operand + 4]
+ test cl, 32
+ jnz L0
+ mov edx, eax
+ mov eax, dword ptr [Operand + 0]
+L0:
+ shrd eax, edx, cl
+ shr edx, cl
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/RShiftU64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RShiftU64.nasm new file mode 100644 index 000000000..ef30e7f33 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RShiftU64.nasm @@ -0,0 +1,39 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; RShiftU64.nasm
+;
+; Abstract:
+;
+; 64-bit logical right shift function for IA-32
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; InternalMathRShiftU64 (
+; IN UINT64 Operand,
+; IN UINTN Count
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalMathRShiftU64)
+ASM_PFX(InternalMathRShiftU64):
+ mov cl, [esp + 12] ; cl <- Count
+ xor edx, edx
+ mov eax, [esp + 8]
+ test cl, 32 ; Count >= 32?
+ jnz .0
+ mov edx, eax
+ mov eax, [esp + 4]
+.0:
+ shrd eax, edx, cl
+ shr edx, cl
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/RdRand.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RdRand.nasm new file mode 100644 index 000000000..e12b8e961 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/RdRand.nasm @@ -0,0 +1,84 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; RdRand.nasm
+;
+; Abstract:
+;
+; Generates random number through CPU RdRand instruction under 32-bit platform.
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+SECTION .text
+
+;------------------------------------------------------------------------------
+; Generates a 16 bit random number through RDRAND instruction.
+; Return TRUE if Rand generated successfully, or FALSE if not.
+;
+; BOOLEAN EFIAPI InternalX86RdRand16 (UINT16 *Rand);
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86RdRand16)
+ASM_PFX(InternalX86RdRand16):
+ ; rdrand ax ; generate a 16 bit RN into ax
+ ; CF=1 if RN generated ok, otherwise CF=0
+ db 0xf, 0xc7, 0xf0 ; rdrand r16: "0f c7 /6 ModRM:r/m(w)"
+ jc rn16_ok ; jmp if CF=1
+ xor eax, eax ; reg=0 if CF=0
+ ret ; return with failure status
+rn16_ok:
+ mov edx, dword [esp + 4]
+ mov [edx], ax
+ mov eax, 1
+ ret
+
+;------------------------------------------------------------------------------
+; Generates a 32 bit random number through RDRAND instruction.
+; Return TRUE if Rand generated successfully, or FALSE if not.
+;
+; BOOLEAN EFIAPI InternalX86RdRand32 (UINT32 *Rand);
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86RdRand32)
+ASM_PFX(InternalX86RdRand32):
+ ; rdrand eax ; generate a 32 bit RN into eax
+ ; CF=1 if RN generated ok, otherwise CF=0
+ db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)"
+ jc rn32_ok ; jmp if CF=1
+ xor eax, eax ; reg=0 if CF=0
+ ret ; return with failure status
+rn32_ok:
+ mov edx, dword [esp + 4]
+ mov [edx], eax
+ mov eax, 1
+ ret
+
+;------------------------------------------------------------------------------
+; Generates a 64 bit random number through RDRAND instruction.
+; Return TRUE if Rand generated successfully, or FALSE if not.
+;
+; BOOLEAN EFIAPI InternalX86RdRand64 (UINT64 *Rand);
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86RdRand64)
+ASM_PFX(InternalX86RdRand64):
+ ; rdrand eax ; generate a 32 bit RN into eax
+ ; CF=1 if RN generated ok, otherwise CF=0
+ db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)"
+ jnc rn64_ret ; jmp if CF=0
+ mov edx, dword [esp + 4]
+ mov [edx], eax
+
+ db 0xf, 0xc7, 0xf0 ; generate another 32 bit RN
+ jnc rn64_ret ; jmp if CF=0
+ mov [edx + 4], eax
+
+ mov eax, 1
+ ret
+rn64_ret:
+ xor eax, eax
+ ret ; return with failure status
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr0.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr0.c new file mode 100644 index 000000000..4a37c7b02 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr0.c @@ -0,0 +1,31 @@ +/** @file
+ AsmReadCr0 function
+
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of the Control Register 0 (CR0).
+
+ Reads and returns the current value of CR0. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 0 (CR0).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr0 (
+ VOID
+ )
+{
+ __asm {
+ mov eax, cr0
+ }
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr0.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr0.nasm new file mode 100644 index 000000000..8303313f2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr0.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadCr0.Asm
+;
+; Abstract:
+;
+; AsmReadCr0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadCr0 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadCr0)
+ASM_PFX(AsmReadCr0):
+ mov eax, cr0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr2.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr2.c new file mode 100644 index 000000000..feab38055 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr2.c @@ -0,0 +1,32 @@ +/** @file
+ AsmReadCr2 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of the Control Register 2 (CR2).
+
+ Reads and returns the current value of CR2. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 2 (CR2).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr2 (
+ VOID
+ )
+{
+ __asm {
+ mov eax, cr2
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr2.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr2.nasm new file mode 100644 index 000000000..202fb53ee --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr2.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadCr2.Asm
+;
+; Abstract:
+;
+; AsmReadCr2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadCr2 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadCr2)
+ASM_PFX(AsmReadCr2):
+ mov eax, cr2
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr3.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr3.c new file mode 100644 index 000000000..b00e32491 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr3.c @@ -0,0 +1,32 @@ +/** @file
+ AsmReadCr3 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of the Control Register 3 (CR3).
+
+ Reads and returns the current value of CR3. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 3 (CR3).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr3 (
+ VOID
+ )
+{
+ __asm {
+ mov eax, cr3
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr3.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr3.nasm new file mode 100644 index 000000000..67b80ea9a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr3.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadCr3.Asm
+;
+; Abstract:
+;
+; AsmReadCr3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadCr3 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadCr3)
+ASM_PFX(AsmReadCr3):
+ mov eax, cr3
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr4.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr4.c new file mode 100644 index 000000000..f948f82b7 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr4.c @@ -0,0 +1,34 @@ +/** @file
+ AsmReadCr4 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of the Control Register 4 (CR4).
+
+ Reads and returns the current value of CR4. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 4 (CR4).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr4 (
+ VOID
+ )
+{
+ __asm {
+ _emit 0x0f // mov eax, cr4
+ _emit 0x20
+ _emit 0xE0
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr4.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr4.nasm new file mode 100644 index 000000000..8202da7c6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCr4.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadCr4.Asm
+;
+; Abstract:
+;
+; AsmReadCr4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadCr4 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadCr4)
+ASM_PFX(AsmReadCr4):
+ mov eax, cr4
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCs.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCs.c new file mode 100644 index 000000000..02f23f5f1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCs.c @@ -0,0 +1,32 @@ +/** @file
+ AsmReadCs function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of Code Segment Register (CS).
+
+ Reads and returns the current value of CS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of CS.
+
+**/
+UINT16
+EFIAPI
+AsmReadCs (
+ VOID
+ )
+{
+ __asm {
+ xor eax, eax
+ mov ax, cs
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCs.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCs.nasm new file mode 100644 index 000000000..8c2a3f08b --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadCs.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadCs.Asm
+;
+; Abstract:
+;
+; AsmReadCs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadCs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadCs)
+ASM_PFX(AsmReadCs):
+ mov eax, cs
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr0.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr0.c new file mode 100644 index 000000000..5418f92a3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr0.c @@ -0,0 +1,32 @@ +/** @file
+ AsmReadDr0 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of Debug Register 0 (DR0).
+
+ Reads and returns the current value of DR0. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr0 (
+ VOID
+ )
+{
+ __asm {
+ mov eax, dr0
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr0.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr0.nasm new file mode 100644 index 000000000..ab700fc41 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr0.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr0.Asm
+;
+; Abstract:
+;
+; AsmReadDr0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr0 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr0)
+ASM_PFX(AsmReadDr0):
+ mov eax, dr0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr1.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr1.c new file mode 100644 index 000000000..d72adaadb --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr1.c @@ -0,0 +1,32 @@ +/** @file
+ AsmReadDr1 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of Debug Register 1 (DR1).
+
+ Reads and returns the current value of DR1. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr1 (
+ VOID
+ )
+{
+ __asm {
+ mov eax, dr1
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr1.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr1.nasm new file mode 100644 index 000000000..594aa73a2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr1.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr1.Asm
+;
+; Abstract:
+;
+; AsmReadDr1 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr1 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr1)
+ASM_PFX(AsmReadDr1):
+ mov eax, dr1
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr2.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr2.c new file mode 100644 index 000000000..fde799728 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr2.c @@ -0,0 +1,32 @@ +/** @file
+ AsmReadDr2 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of Debug Register 2 (DR2).
+
+ Reads and returns the current value of DR2. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr2 (
+ VOID
+ )
+{
+ __asm {
+ mov eax, dr2
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr2.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr2.nasm new file mode 100644 index 000000000..ec7eb5d47 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr2.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr2.Asm
+;
+; Abstract:
+;
+; AsmReadDr2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr2 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr2)
+ASM_PFX(AsmReadDr2):
+ mov eax, dr2
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr3.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr3.c new file mode 100644 index 000000000..9b899e79c --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr3.c @@ -0,0 +1,32 @@ +/** @file
+ AsmReadDr3 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of Debug Register 3 (DR3).
+
+ Reads and returns the current value of DR3. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr3 (
+ VOID
+ )
+{
+ __asm {
+ mov eax, dr3
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr3.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr3.nasm new file mode 100644 index 000000000..9e79ef6e1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr3.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr3.Asm
+;
+; Abstract:
+;
+; AsmReadDr3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr3 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr3)
+ASM_PFX(AsmReadDr3):
+ mov eax, dr3
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr4.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr4.c new file mode 100644 index 000000000..52293d335 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr4.c @@ -0,0 +1,34 @@ +/** @file
+ AsmReadDr4 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of Debug Register 4 (DR4).
+
+ Reads and returns the current value of DR4. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr4 (
+ VOID
+ )
+{
+ __asm {
+ _emit 0x0f
+ _emit 0x21
+ _emit 0xe0
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm new file mode 100644 index 000000000..81c681de3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm @@ -0,0 +1,38 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr4.Asm
+;
+; Abstract:
+;
+; AsmReadDr4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr4 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr4)
+ASM_PFX(AsmReadDr4):
+ ;
+ ; DR4 is alias to DR6 only if DE (in CR4) is cleared. Otherwise, reading
+ ; this register will cause a #UD exception.
+ ;
+ ; MS assembler doesn't support this instruction since no one would use it
+ ; under normal circustances. Here opcode is used.
+ ;
+ DB 0xf, 0x21, 0xe0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr5.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr5.c new file mode 100644 index 000000000..ecf6dc2d2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr5.c @@ -0,0 +1,34 @@ +/** @file
+ AsmReadDr5 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of Debug Register 5 (DR5).
+
+ Reads and returns the current value of DR5. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr5 (
+ VOID
+ )
+{
+ __asm {
+ _emit 0x0f
+ _emit 0x21
+ _emit 0xe8
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm new file mode 100644 index 000000000..e2deacb83 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm @@ -0,0 +1,38 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr5.Asm
+;
+; Abstract:
+;
+; AsmReadDr5 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr5 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr5)
+ASM_PFX(AsmReadDr5):
+ ;
+ ; DR5 is alias to DR7 only if DE (in CR4) is cleared. Otherwise, reading
+ ; this register will cause a #UD exception.
+ ;
+ ; MS assembler doesn't support this instruction since no one would use it
+ ; under normal circustances. Here opcode is used.
+ ;
+ DB 0xf, 0x21, 0xe8
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr6.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr6.c new file mode 100644 index 000000000..2b082970f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr6.c @@ -0,0 +1,32 @@ +/** @file
+ AsmReadDr6 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of Debug Register 6 (DR6).
+
+ Reads and returns the current value of DR6. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr6 (
+ VOID
+ )
+{
+ __asm {
+ mov eax, dr6
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr6.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr6.nasm new file mode 100644 index 000000000..a3e38aa11 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr6.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr6.Asm
+;
+; Abstract:
+;
+; AsmReadDr6 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr6 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr6)
+ASM_PFX(AsmReadDr6):
+ mov eax, dr6
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr7.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr7.c new file mode 100644 index 000000000..8be80482f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr7.c @@ -0,0 +1,32 @@ +/** @file
+ AsmReadDr7 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of Debug Register 7 (DR7).
+
+ Reads and returns the current value of DR7. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr7 (
+ VOID
+ )
+{
+ __asm {
+ mov eax, dr7
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr7.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr7.nasm new file mode 100644 index 000000000..6cbbb484e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDr7.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr7.Asm
+;
+; Abstract:
+;
+; AsmReadDr7 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr7 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr7)
+ASM_PFX(AsmReadDr7):
+ mov eax, dr7
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDs.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDs.c new file mode 100644 index 000000000..3cdada3ac --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDs.c @@ -0,0 +1,32 @@ +/** @file
+ AsmReadDs function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of Data Segment Register (DS).
+
+ Reads and returns the current value of DS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of DS.
+
+**/
+UINT16
+EFIAPI
+AsmReadDs (
+ VOID
+ )
+{
+ __asm {
+ xor eax, eax
+ mov ax, ds
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDs.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDs.nasm new file mode 100644 index 000000000..e2d3a05ec --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadDs.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDs.Asm
+;
+; Abstract:
+;
+; AsmReadDs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadDs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDs)
+ASM_PFX(AsmReadDs):
+ mov eax, ds
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEflags.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEflags.c new file mode 100644 index 000000000..1cea323c5 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEflags.c @@ -0,0 +1,33 @@ +/** @file
+ AsmReadEflags function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of the EFLAGS register.
+
+ Reads and returns the current value of the EFLAGS register. This function is
+ only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a
+ 64-bit value on x64.
+
+ @return EFLAGS on IA-32 or RFLAGS on x64.
+
+**/
+UINTN
+EFIAPI
+AsmReadEflags (
+ VOID
+ )
+{
+ __asm {
+ pushfd
+ pop eax
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEflags.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEflags.nasm new file mode 100644 index 000000000..05dca3fa6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEflags.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadEflags.Asm
+;
+; Abstract:
+;
+; AsmReadEflags function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadEflags (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadEflags)
+ASM_PFX(AsmReadEflags):
+ pushfd
+ pop eax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEs.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEs.c new file mode 100644 index 000000000..30953fdf3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEs.c @@ -0,0 +1,32 @@ +/** @file
+ AsmReadEs function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of ES Data Segment Register (ES).
+
+ Reads and returns the current value of ES. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of ES.
+
+**/
+UINT16
+EFIAPI
+AsmReadEs (
+ VOID
+ )
+{
+ __asm {
+ xor eax, eax
+ mov ax, es
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEs.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEs.nasm new file mode 100644 index 000000000..5228298cf --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadEs.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadEs.Asm
+;
+; Abstract:
+;
+; AsmReadEs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadEs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadEs)
+ASM_PFX(AsmReadEs):
+ mov eax, es
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadFs.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadFs.c new file mode 100644 index 000000000..51fb020b1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadFs.c @@ -0,0 +1,32 @@ +/** @file
+ AsmReadFs function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of FS Data Segment Register (FS).
+
+ Reads and returns the current value of FS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of FS.
+
+**/
+UINT16
+EFIAPI
+AsmReadFs (
+ VOID
+ )
+{
+ __asm {
+ xor eax, eax
+ mov ax, fs
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadFs.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadFs.nasm new file mode 100644 index 000000000..fa7fbc351 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadFs.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadFs.Asm
+;
+; Abstract:
+;
+; AsmReadFs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadFs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadFs)
+ASM_PFX(AsmReadFs):
+ mov eax, fs
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGdtr.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGdtr.c new file mode 100644 index 000000000..5b01300b4 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGdtr.c @@ -0,0 +1,33 @@ +/** @file
+ AsmReadGdtr function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+
+/**
+ Reads the current Global Descriptor Table Register(GDTR) descriptor.
+
+ Reads and returns the current GDTR descriptor and returns it in Gdtr. This
+ function is only available on IA-32 and x64.
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86ReadGdtr (
+ OUT IA32_DESCRIPTOR *Gdtr
+ )
+{
+ _asm {
+ mov eax, Gdtr
+ sgdt fword ptr [eax]
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGdtr.nasm new file mode 100644 index 000000000..03b03a89b --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadGdtr.Asm
+;
+; Abstract:
+;
+; AsmReadGdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86ReadGdtr (
+; OUT IA32_DESCRIPTOR *Gdtr
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86ReadGdtr)
+ASM_PFX(InternalX86ReadGdtr):
+ mov eax, [esp + 4]
+ sgdt [eax]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGs.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGs.c new file mode 100644 index 000000000..6209a31ae --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGs.c @@ -0,0 +1,32 @@ +/** @file
+ AsmReadGs function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of GS Data Segment Register (GS).
+
+ Reads and returns the current value of GS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of GS.
+
+**/
+UINT16
+EFIAPI
+AsmReadGs (
+ VOID
+ )
+{
+ __asm {
+ xor eax, eax
+ mov ax, gs
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGs.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGs.nasm new file mode 100644 index 000000000..b1e46deef --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadGs.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadGs.Asm
+;
+; Abstract:
+;
+; AsmReadGs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadGs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadGs)
+ASM_PFX(AsmReadGs):
+ mov eax, gs
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadIdtr.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadIdtr.c new file mode 100644 index 000000000..93f44535d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadIdtr.c @@ -0,0 +1,32 @@ +/** @file
+ AsmReadIdtr function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+
+/**
+ Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.
+
+ Reads and returns the current IDTR descriptor and returns it in Idtr. This
+ function is only available on IA-32 and x64.
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86ReadIdtr (
+ OUT IA32_DESCRIPTOR *Idtr
+ )
+{
+ _asm {
+ mov eax, Idtr
+ sidt fword ptr [eax]
+ }
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadIdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadIdtr.nasm new file mode 100644 index 000000000..9fa1c62e3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadIdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadIdtr.Asm
+;
+; Abstract:
+;
+; AsmReadIdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86ReadIdtr (
+; OUT IA32_DESCRIPTOR *Idtr
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86ReadIdtr)
+ASM_PFX(InternalX86ReadIdtr):
+ mov eax, [esp + 4]
+ sidt [eax]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadLdtr.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadLdtr.c new file mode 100644 index 000000000..407676a46 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadLdtr.c @@ -0,0 +1,31 @@ +/** @file
+ AsmReadLdtr function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current Local Descriptor Table Register(LDTR) selector.
+
+ Reads and returns the current 16-bit LDTR descriptor value. This function is
+ only available on IA-32 and x64.
+
+ @return The current selector of LDT.
+
+**/
+UINT16
+EFIAPI
+AsmReadLdtr (
+ VOID
+ )
+{
+ _asm {
+ sldt ax
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadLdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadLdtr.nasm new file mode 100644 index 000000000..c1e169b65 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadLdtr.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadLdtr.Asm
+;
+; Abstract:
+;
+; AsmReadLdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadLdtr (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadLdtr)
+ASM_PFX(AsmReadLdtr):
+ sldt ax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm0.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm0.c new file mode 100644 index 000000000..00dfe0589 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm0.c @@ -0,0 +1,36 @@ +/** @file
+ AsmReadMm0 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of 64-bit MMX Register #0 (MM0).
+
+ Reads and returns the current value of MM0. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of MM0.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm0 (
+ VOID
+ )
+{
+ _asm {
+ push eax
+ push eax
+ movq [esp], mm0
+ pop eax
+ pop edx
+ emms
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm0.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm0.nasm new file mode 100644 index 000000000..36da46f43 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm0.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm0.Asm
+;
+; Abstract:
+;
+; AsmReadMm0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm0 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm0)
+ASM_PFX(AsmReadMm0):
+ push eax
+ push eax
+ movq [esp], mm0
+ pop eax
+ pop edx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm1.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm1.c new file mode 100644 index 000000000..0ed311e41 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm1.c @@ -0,0 +1,36 @@ +/** @file
+ AsmReadMm1 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of 64-bit MMX Register #1 (MM1).
+
+ Reads and returns the current value of MM1. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of MM1.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm1 (
+ VOID
+ )
+{
+ _asm {
+ push eax
+ push eax
+ movq [esp], mm1
+ pop eax
+ pop edx
+ emms
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm1.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm1.nasm new file mode 100644 index 000000000..49ae74264 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm1.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm1.Asm
+;
+; Abstract:
+;
+; AsmReadMm1 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm1 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm1)
+ASM_PFX(AsmReadMm1):
+ push eax
+ push eax
+ movq [esp], mm1
+ pop eax
+ pop edx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm2.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm2.c new file mode 100644 index 000000000..bd830c557 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm2.c @@ -0,0 +1,36 @@ +/** @file
+ AsmReadMm2 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of 64-bit MMX Register #2 (MM2).
+
+ Reads and returns the current value of MM2. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of MM2.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm2 (
+ VOID
+ )
+{
+ _asm {
+ push eax
+ push eax
+ movq [esp], mm2
+ pop eax
+ pop edx
+ emms
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm2.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm2.nasm new file mode 100644 index 000000000..3023592a6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm2.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm2.Asm
+;
+; Abstract:
+;
+; AsmReadMm2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm2 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm2)
+ASM_PFX(AsmReadMm2):
+ push eax
+ push eax
+ movq [esp], mm2
+ pop eax
+ pop edx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm3.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm3.c new file mode 100644 index 000000000..c8967083b --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm3.c @@ -0,0 +1,36 @@ +/** @file
+ AsmReadMm3 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of 64-bit MMX Register #3 (MM3).
+
+ Reads and returns the current value of MM3. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of MM3.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm3 (
+ VOID
+ )
+{
+ _asm {
+ push eax
+ push eax
+ movq [esp], mm3
+ pop eax
+ pop edx
+ emms
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm3.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm3.nasm new file mode 100644 index 000000000..339468cc0 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm3.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm3.Asm
+;
+; Abstract:
+;
+; AsmReadMm3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm3 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm3)
+ASM_PFX(AsmReadMm3):
+ push eax
+ push eax
+ movq [esp], mm3
+ pop eax
+ pop edx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm4.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm4.c new file mode 100644 index 000000000..9e2794cd4 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm4.c @@ -0,0 +1,36 @@ +/** @file
+ AsmReadMm4 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of 64-bit MMX Register #4 (MM4).
+
+ Reads and returns the current value of MM4. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of MM4.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm4 (
+ VOID
+ )
+{
+ _asm {
+ push eax
+ push eax
+ movq [esp], mm4
+ pop eax
+ pop edx
+ emms
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm4.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm4.nasm new file mode 100644 index 000000000..53da33a3f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm4.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm4.Asm
+;
+; Abstract:
+;
+; AsmReadMm4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm4 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm4)
+ASM_PFX(AsmReadMm4):
+ push eax
+ push eax
+ movq [esp], mm4
+ pop eax
+ pop edx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm5.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm5.c new file mode 100644 index 000000000..93cad05a4 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm5.c @@ -0,0 +1,36 @@ +/** @file
+ AsmReadMm5 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of 64-bit MMX Register #5 (MM5).
+
+ Reads and returns the current value of MM5. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of MM5.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm5 (
+ VOID
+ )
+{
+ _asm {
+ push eax
+ push eax
+ movq [esp], mm5
+ pop eax
+ pop edx
+ emms
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm5.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm5.nasm new file mode 100644 index 000000000..dd1e87cf8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm5.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm5.Asm
+;
+; Abstract:
+;
+; AsmReadMm5 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm5 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm5)
+ASM_PFX(AsmReadMm5):
+ push eax
+ push eax
+ movq [esp], mm5
+ pop eax
+ pop edx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm6.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm6.c new file mode 100644 index 000000000..d2c559163 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm6.c @@ -0,0 +1,36 @@ +/** @file
+ AsmReadMm6 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of 64-bit MMX Register #6 (MM6).
+
+ Reads and returns the current value of MM6. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of MM6.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm6 (
+ VOID
+ )
+{
+ _asm {
+ push eax
+ push eax
+ movq [esp], mm6
+ pop eax
+ pop edx
+ emms
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm6.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm6.nasm new file mode 100644 index 000000000..1b43d056e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm6.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm6.Asm
+;
+; Abstract:
+;
+; AsmReadMm6 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm6 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm6)
+ASM_PFX(AsmReadMm6):
+ push eax
+ push eax
+ movq [esp], mm6
+ pop eax
+ pop edx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm7.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm7.c new file mode 100644 index 000000000..68cf03928 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm7.c @@ -0,0 +1,36 @@ +/** @file
+ AsmReadMm7 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of 64-bit MMX Register #7 (MM7).
+
+ Reads and returns the current value of MM7. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of MM7.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm7 (
+ VOID
+ )
+{
+ _asm {
+ push eax
+ push eax
+ movq [esp], mm7
+ pop eax
+ pop edx
+ emms
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm7.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm7.nasm new file mode 100644 index 000000000..3df4c9fc8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMm7.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm7.Asm
+;
+; Abstract:
+;
+; AsmReadMm7 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm7 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm7)
+ASM_PFX(AsmReadMm7):
+ push eax
+ push eax
+ movq [esp], mm7
+ pop eax
+ pop edx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c new file mode 100644 index 000000000..6d2394b1a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c @@ -0,0 +1,37 @@ +/** @file
+ AsmReadMsr64 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Returns a 64-bit Machine Specific Register(MSR).
+
+ Reads and returns the 64-bit MSR specified by Index. No parameter checking is
+ performed on Index, and some Index values may cause CPU exceptions. The
+ caller must either guarantee that Index is valid, or the caller must set up
+ exception handlers to catch the exceptions. This function is only available
+ on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to read.
+
+ @return The value of the MSR identified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadMsr64 (
+ IN UINT32 Index
+ )
+{
+ _asm {
+ mov ecx, Index
+ rdmsr
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMsr64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMsr64.nasm new file mode 100644 index 000000000..97b853a3a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadMsr64.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMsr64.Asm
+;
+; Abstract:
+;
+; AsmReadMsr64 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMsr64 (
+; IN UINT64 Index
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMsr64)
+ASM_PFX(AsmReadMsr64):
+ mov ecx, [esp + 4]
+ rdmsr
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadPmc.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadPmc.c new file mode 100644 index 000000000..cc09ed700 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadPmc.c @@ -0,0 +1,31 @@ +/** @file
+ AsmReadPmc function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Reads the current value of a Performance Counter (PMC).
+
+ Reads and returns the current value of performance counter specified by
+ Index. This function is only available on IA-32 and x64.
+
+ @param Index The 32-bit Performance Counter index to read.
+
+ @return The value of the PMC specified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadPmc (
+ IN UINT32 Index
+ )
+{
+ _asm {
+ mov ecx, Index
+ rdpmc
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadPmc.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadPmc.nasm new file mode 100644 index 000000000..53142e33f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadPmc.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadPmc.Asm
+;
+; Abstract:
+;
+; AsmReadPmc function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadPmc (
+; IN UINT32 PmcIndex
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadPmc)
+ASM_PFX(AsmReadPmc):
+ mov ecx, [esp + 4]
+ rdpmc
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadSs.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadSs.c new file mode 100644 index 000000000..9d7a6411a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadSs.c @@ -0,0 +1,32 @@ +/** @file
+ AsmReadSs function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of Stack Segment Register (SS).
+
+ Reads and returns the current value of SS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of SS.
+
+**/
+UINT16
+EFIAPI
+AsmReadSs (
+ VOID
+ )
+{
+ __asm {
+ xor eax, eax
+ mov ax, ss
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadSs.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadSs.nasm new file mode 100644 index 000000000..61628dec3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadSs.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadSs.Asm
+;
+; Abstract:
+;
+; AsmReadSs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadSs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadSs)
+ASM_PFX(AsmReadSs):
+ mov eax, ss
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTr.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTr.c new file mode 100644 index 000000000..b52f8f31d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTr.c @@ -0,0 +1,31 @@ +/** @file
+ AsmReadTr function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of Task Register (TR).
+
+ Reads and returns the current value of TR. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of TR.
+
+**/
+UINT16
+EFIAPI
+AsmReadTr (
+ VOID
+ )
+{
+ _asm {
+ str ax
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTr.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTr.nasm new file mode 100644 index 000000000..9f238e2ae --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTr.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadTr.Asm
+;
+; Abstract:
+;
+; AsmReadTr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadTr (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadTr)
+ASM_PFX(AsmReadTr):
+ str ax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTsc.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTsc.c new file mode 100644 index 000000000..a67b57a77 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTsc.c @@ -0,0 +1,31 @@ +/** @file
+ AsmReadTsc function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Reads the current value of Time Stamp Counter (TSC).
+
+ Reads and returns the current value of TSC. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of TSC
+
+**/
+UINT64
+EFIAPI
+AsmReadTsc (
+ VOID
+ )
+{
+ _asm {
+ rdtsc
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTsc.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTsc.nasm new file mode 100644 index 000000000..1bc875bd3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/ReadTsc.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadTsc.Asm
+;
+; Abstract:
+;
+; AsmReadTsc function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadTsc (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadTsc)
+ASM_PFX(AsmReadTsc):
+ rdtsc
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/SetJump.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/SetJump.nasm new file mode 100644 index 000000000..364613b5f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/SetJump.nasm @@ -0,0 +1,63 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; SetJump.Asm
+;
+; Abstract:
+;
+; Implementation of SetJump() on IA-32.
+;
+;------------------------------------------------------------------------------
+
+%include "Nasm.inc"
+
+ SECTION .text
+
+extern ASM_PFX(InternalAssertJumpBuffer)
+extern ASM_PFX(PcdGet32 (PcdControlFlowEnforcementPropertyMask))
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; SetJump (
+; OUT BASE_LIBRARY_JUMP_BUFFER *JumpBuffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(SetJump)
+ASM_PFX(SetJump):
+ push DWORD [esp + 4]
+ call ASM_PFX(InternalAssertJumpBuffer) ; To validate JumpBuffer
+ pop ecx
+ pop ecx ; ecx <- return address
+ mov edx, [esp]
+
+ xor eax, eax
+ mov [edx + 24], eax ; save 0 to SSP
+
+ mov eax, [ASM_PFX(PcdGet32 (PcdControlFlowEnforcementPropertyMask))]
+ test eax, eax
+ jz CetDone
+ mov eax, cr4
+ bt eax, 23 ; check if CET is enabled
+ jnc CetDone
+
+ mov eax, 1
+ INCSSP_EAX ; to read original SSP
+ READSSP_EAX
+ mov [edx + 0x24], eax ; save SSP
+
+CetDone:
+
+ mov [edx], ebx
+ mov [edx + 4], esi
+ mov [edx + 8], edi
+ mov [edx + 12], ebp
+ mov [edx + 16], esp
+ mov [edx + 20], ecx ; eip value to restore in LongJump
+ xor eax, eax
+ jmp ecx
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/SwapBytes64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/SwapBytes64.c new file mode 100644 index 000000000..67587f1d2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/SwapBytes64.c @@ -0,0 +1,37 @@ +/** @file
+ Implementation of 64-bit swap bytes
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Switches the endianess of a 64-bit integer.
+
+ This function swaps the bytes in a 64-bit unsigned value to switch the value
+ from little endian to big endian or vice versa. The byte swapped value is
+ returned.
+
+ @param Operand A 64-bit unsigned value.
+
+ @return The byte swaped Operand.
+
+**/
+UINT64
+EFIAPI
+InternalMathSwapBytes64 (
+ IN UINT64 Operand
+ )
+{
+ _asm {
+ mov eax, dword ptr [Operand + 4]
+ mov edx, dword ptr [Operand + 0]
+ bswap eax
+ bswap edx
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/SwapBytes64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/SwapBytes64.nasm new file mode 100644 index 000000000..73a109415 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/SwapBytes64.nasm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuId.Asm
+;
+; Abstract:
+;
+; AsmCpuid function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; InternalMathSwapBytes64 (
+; IN UINT64 Operand
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalMathSwapBytes64)
+ASM_PFX(InternalMathSwapBytes64):
+ mov eax, [esp + 8] ; eax <- upper 32 bits
+ mov edx, [esp + 4] ; edx <- lower 32 bits
+ bswap eax
+ bswap edx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Thunk16.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Thunk16.nasm new file mode 100644 index 000000000..03a300dc6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Thunk16.nasm @@ -0,0 +1,257 @@ +
+#include "BaseLibInternals.h"
+
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Thunk.asm
+;
+; Abstract:
+;
+; Real mode thunk
+;
+;------------------------------------------------------------------------------
+
+global ASM_PFX(m16Size)
+global ASM_PFX(mThunk16Attr)
+global ASM_PFX(m16Gdt)
+global ASM_PFX(m16GdtrBase)
+global ASM_PFX(mTransition)
+global ASM_PFX(m16Start)
+
+struc IA32_REGS
+
+ ._EDI: resd 1
+ ._ESI: resd 1
+ ._EBP: resd 1
+ ._ESP: resd 1
+ ._EBX: resd 1
+ ._EDX: resd 1
+ ._ECX: resd 1
+ ._EAX: resd 1
+ ._DS: resw 1
+ ._ES: resw 1
+ ._FS: resw 1
+ ._GS: resw 1
+ ._EFLAGS: resd 1
+ ._EIP: resd 1
+ ._CS: resw 1
+ ._SS: resw 1
+ .size:
+
+endstruc
+
+;; .const
+
+SECTION .data
+
+;
+; These are global constant to convey information to C code.
+;
+ASM_PFX(m16Size) DW ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)
+ASM_PFX(mThunk16Attr) DW _BackFromUserCode.ThunkAttrEnd - 4 - ASM_PFX(m16Start)
+ASM_PFX(m16Gdt) DW _NullSegDesc - ASM_PFX(m16Start)
+ASM_PFX(m16GdtrBase) DW _16GdtrBase - ASM_PFX(m16Start)
+ASM_PFX(mTransition) DW _EntryPoint - ASM_PFX(m16Start)
+
+SECTION .text
+
+ASM_PFX(m16Start):
+
+SavedGdt:
+ dw 0
+ dd 0
+
+;------------------------------------------------------------------------------
+; _BackFromUserCode() takes control in real mode after 'retf' has been executed
+; by user code. It will be shadowed to somewhere in memory below 1MB.
+;------------------------------------------------------------------------------
+_BackFromUserCode:
+ ;
+ ; The order of saved registers on the stack matches the order they appears
+ ; in IA32_REGS structure. This facilitates wrapper function to extract them
+ ; into that structure.
+ ;
+BITS 16
+ push ss
+ push cs
+ ;
+ ; Note: We can't use o32 on the next instruction because of a bug
+ ; in NASM 2.09.04 through 2.10rc1.
+ ;
+ call dword .Base ; push eip
+.Base:
+ pushfd
+ cli ; disable interrupts
+ push gs
+ push fs
+ push es
+ push ds
+ pushad
+ mov edx, strict dword 0
+.ThunkAttrEnd:
+ test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15
+ jz .1
+ mov ax, 2401h
+ int 15h
+ cli ; disable interrupts
+ jnc .2
+.1:
+ test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL
+ jz .2
+ in al, 92h
+ or al, 2
+ out 92h, al ; deactivate A20M#
+.2:
+ xor eax, eax
+ mov ax, ss
+ lea ebp, [esp + IA32_REGS.size]
+ mov [bp - IA32_REGS.size + IA32_REGS._ESP], ebp
+ mov bx, [bp - IA32_REGS.size + IA32_REGS._EIP]
+ shl eax, 4 ; shl eax, 4
+ add ebp, eax ; add ebp, eax
+ mov eax, strict dword 0
+.SavedCr4End:
+ mov cr4, eax
+o32 lgdt [cs:bx + (SavedGdt - .Base)]
+ mov eax, strict dword 0
+.SavedCr0End:
+ mov cr0, eax
+ mov ax, strict word 0
+.SavedSsEnd:
+ mov ss, eax
+ mov esp, strict dword 0
+.SavedEspEnd:
+o32 retf ; return to protected mode
+
+_EntryPoint:
+ DD _ToUserCode - ASM_PFX(m16Start)
+ DW 8h
+_16Idtr:
+ DW (1 << 10) - 1
+ DD 0
+_16Gdtr:
+ DW GdtEnd - _NullSegDesc - 1
+_16GdtrBase:
+ DD 0
+
+;------------------------------------------------------------------------------
+; _ToUserCode() takes control in real mode before passing control to user code.
+; It will be shadowed to somewhere in memory below 1MB.
+;------------------------------------------------------------------------------
+_ToUserCode:
+BITS 16
+ mov dx, ss
+ mov ss, cx ; set new segment selectors
+ mov ds, cx
+ mov es, cx
+ mov fs, cx
+ mov gs, cx
+ mov cr0, eax ; real mode starts at next instruction
+ ; which (per SDM) *must* be a far JMP.
+ jmp 0:strict word 0
+.RealAddrEnd:
+ mov cr4, ebp
+ mov ss, si ; set up 16-bit stack segment
+ xchg esp, ebx ; set up 16-bit stack pointer
+ mov bp, [esp + IA32_REGS.size]
+ mov [cs:bp + (_BackFromUserCode.SavedSsEnd - 2 - _BackFromUserCode)], dx
+ mov [cs:bp + (_BackFromUserCode.SavedEspEnd - 4 - _BackFromUserCode)], ebx
+ lidt [cs:bp + (_16Idtr - _BackFromUserCode)]
+
+ popad
+ pop ds
+ pop es
+ pop fs
+ pop gs
+ popfd
+
+o32 retf ; transfer control to user code
+
+ALIGN 16
+_NullSegDesc DQ 0
+_16CsDesc:
+ DW -1
+ DW 0
+ DB 0
+ DB 9bh
+ DB 8fh ; 16-bit segment, 4GB limit
+ DB 0
+_16DsDesc:
+ DW -1
+ DW 0
+ DB 0
+ DB 93h
+ DB 8fh ; 16-bit segment, 4GB limit
+ DB 0
+GdtEnd:
+
+;------------------------------------------------------------------------------
+; IA32_REGISTER_SET *
+; EFIAPI
+; InternalAsmThunk16 (
+; IN IA32_REGISTER_SET *RegisterSet,
+; IN OUT VOID *Transition
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalAsmThunk16)
+ASM_PFX(InternalAsmThunk16):
+BITS 32
+ push ebp
+ push ebx
+ push esi
+ push edi
+ push ds
+ push es
+ push fs
+ push gs
+ mov esi, [esp + 36] ; esi <- RegSet, the 1st parameter
+ movzx edx, word [esi + IA32_REGS._SS]
+ mov edi, [esi + IA32_REGS._ESP]
+ add edi, - (IA32_REGS.size + 4) ; reserve stack space
+ mov ebx, edi ; ebx <- stack offset
+ imul eax, edx, 16 ; eax <- edx * 16
+ push IA32_REGS.size / 4
+ add edi, eax ; edi <- linear address of 16-bit stack
+ pop ecx
+ rep movsd ; copy RegSet
+ mov eax, [esp + 40] ; eax <- address of transition code
+ mov esi, edx ; esi <- 16-bit stack segment
+ lea edx, [eax + (_BackFromUserCode.SavedCr0End - ASM_PFX(m16Start))]
+ mov ecx, eax
+ and ecx, 0fh
+ shl eax, 12
+ lea ecx, [ecx + (_BackFromUserCode - ASM_PFX(m16Start))]
+ mov ax, cx
+ stosd ; [edi] <- return address of user code
+ add eax, _ToUserCode.RealAddrEnd - _BackFromUserCode
+ mov [edx + (_ToUserCode.RealAddrEnd - 4 - _BackFromUserCode.SavedCr0End)], eax
+ sgdt [edx + (SavedGdt - _BackFromUserCode.SavedCr0End)]
+ sidt [esp + 36] ; save IDT stack in argument space
+ mov eax, cr0
+ mov [edx - 4], eax ; save CR0 in _BackFromUserCode.SavedCr0End - 4
+ and eax, 7ffffffeh ; clear PE, PG bits
+ mov ebp, cr4
+ mov [edx + (_BackFromUserCode.SavedCr4End - 4 - _BackFromUserCode.SavedCr0End)], ebp
+ and ebp, ~30h ; clear PAE, PSE bits
+ push 10h
+ pop ecx ; ecx <- selector for data segments
+ lgdt [edx + (_16Gdtr - _BackFromUserCode.SavedCr0End)]
+ pushfd ; Save df/if indeed
+ call dword far [edx + (_EntryPoint - _BackFromUserCode.SavedCr0End)]
+ popfd
+ lidt [esp + 36] ; restore protected mode IDTR
+ lea eax, [ebp - IA32_REGS.size] ; eax <- the address of IA32_REGS
+ pop gs
+ pop fs
+ pop es
+ pop ds
+ pop edi
+ pop esi
+ pop ebx
+ pop ebp
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/VmgExit.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/VmgExit.nasm new file mode 100644 index 000000000..69f7fbf35 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/VmgExit.nasm @@ -0,0 +1,38 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; VmgExit.Asm
+;
+; Abstract:
+;
+; AsmVmgExit function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmVmgExit (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmVmgExit)
+ASM_PFX(AsmVmgExit):
+;
+; NASM doesn't support the vmmcall instruction in 32-bit mode and NASM versions
+; before 2.12 cannot translate the 64-bit "rep vmmcall" instruction into elf32
+; format. Given that VMGEXIT does not make sense on IA32, provide a stub
+; implementation that is identical to CpuBreakpoint(). In practice, AsmVmgExit()
+; should never be called on IA32.
+;
+ int 3
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Wbinvd.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Wbinvd.c new file mode 100644 index 000000000..87bd71f05 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Wbinvd.c @@ -0,0 +1,29 @@ +/** @file
+ AsmWbinvd function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Executes a WBINVD instruction.
+
+ Executes a WBINVD instruction. This function is only available on IA-32 and
+ x64.
+
+**/
+VOID
+EFIAPI
+AsmWbinvd (
+ VOID
+ )
+{
+ _asm {
+ wbinvd
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/Wbinvd.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Wbinvd.nasm new file mode 100644 index 000000000..714e42789 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/Wbinvd.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Wbinvd.Asm
+;
+; Abstract:
+;
+; AsmWbinvd function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWbinvd (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWbinvd)
+ASM_PFX(AsmWbinvd):
+ wbinvd
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr0.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr0.c new file mode 100644 index 000000000..46e49a678 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr0.c @@ -0,0 +1,31 @@ +/** @file
+ AsmWriteCr0 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Writes a value to Control Register 0 (CR0).
+
+ Writes and returns a new value to CR0. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Value The value to write to CR0.
+
+ @return The value written to CR0.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr0 (
+ UINTN Value
+ )
+{
+ _asm {
+ mov eax, Value
+ mov cr0, eax
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr0.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr0.nasm new file mode 100644 index 000000000..6730fbe37 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr0.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteCr0.Asm
+;
+; Abstract:
+;
+; AsmWriteCr0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteCr0 (
+; UINTN Cr0
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteCr0)
+ASM_PFX(AsmWriteCr0):
+ mov eax, [esp + 4]
+ mov cr0, eax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr2.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr2.c new file mode 100644 index 000000000..f437bfc8c --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr2.c @@ -0,0 +1,31 @@ +/** @file
+ AsmWriteCr2 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Writes a value to Control Register 2 (CR2).
+
+ Writes and returns a new value to CR2. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Value The value to write to CR2.
+
+ @return The value written to CR2.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr2 (
+ UINTN Value
+ )
+{
+ _asm {
+ mov eax, Value
+ mov cr2, eax
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr2.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr2.nasm new file mode 100644 index 000000000..989639066 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr2.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteCr2.Asm
+;
+; Abstract:
+;
+; AsmWriteCr2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteCr2 (
+; UINTN Cr2
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteCr2)
+ASM_PFX(AsmWriteCr2):
+ mov eax, [esp + 4]
+ mov cr2, eax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr3.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr3.c new file mode 100644 index 000000000..48cb8ad16 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr3.c @@ -0,0 +1,31 @@ +/** @file
+ AsmWriteCr3 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Writes a value to Control Register 3 (CR3).
+
+ Writes and returns a new value to CR3. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Value The value to write to CR3.
+
+ @return The value written to CR3.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr3 (
+ UINTN Value
+ )
+{
+ _asm {
+ mov eax, Value
+ mov cr3, eax
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr3.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr3.nasm new file mode 100644 index 000000000..21114f35c --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr3.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteCr3.Asm
+;
+; Abstract:
+;
+; AsmWriteCr3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteCr3 (
+; UINTN Cr3
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteCr3)
+ASM_PFX(AsmWriteCr3):
+ mov eax, [esp + 4]
+ mov cr3, eax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr4.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr4.c new file mode 100644 index 000000000..01f059ffa --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr4.c @@ -0,0 +1,33 @@ +/** @file
+ AsmWriteCr4 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Writes a value to Control Register 4 (CR4).
+
+ Writes and returns a new value to CR4. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Value The value to write to CR4.
+
+ @return The value written to CR4.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr4 (
+ UINTN Value
+ )
+{
+ _asm {
+ mov eax, Value
+ _emit 0x0f // mov cr4, eax
+ _emit 0x22
+ _emit 0xE0
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr4.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr4.nasm new file mode 100644 index 000000000..b090606b1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteCr4.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteCr4.Asm
+;
+; Abstract:
+;
+; AsmWriteCr4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteCr4 (
+; UINTN Cr4
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteCr4)
+ASM_PFX(AsmWriteCr4):
+ mov eax, [esp + 4]
+ mov cr4, eax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr0.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr0.c new file mode 100644 index 000000000..80bb23818 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr0.c @@ -0,0 +1,31 @@ +/** @file
+ AsmWriteDr0 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Writes a value to Debug Register 0 (DR0).
+
+ Writes and returns a new value to DR0. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Value The value to write to Dr0.
+
+ @return The value written to Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr0 (
+ IN UINTN Value
+ )
+{
+ _asm {
+ mov eax, Value
+ mov dr0, eax
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr0.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr0.nasm new file mode 100644 index 000000000..24cd2c2e8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr0.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr0.Asm
+;
+; Abstract:
+;
+; AsmWriteDr0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr0 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr0)
+ASM_PFX(AsmWriteDr0):
+ mov eax, [esp + 4]
+ mov dr0, eax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr1.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr1.c new file mode 100644 index 000000000..f1c8f325e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr1.c @@ -0,0 +1,31 @@ +/** @file
+ AsmWriteDr1 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Writes a value to Debug Register 1 (DR1).
+
+ Writes and returns a new value to DR1. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Value The value to write to Dr1.
+
+ @return The value written to Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr1 (
+ IN UINTN Value
+ )
+{
+ _asm {
+ mov eax, Value
+ mov dr1, eax
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr1.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr1.nasm new file mode 100644 index 000000000..57afac4f1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr1.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr1.Asm
+;
+; Abstract:
+;
+; AsmWriteDr1 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr1 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr1)
+ASM_PFX(AsmWriteDr1):
+ mov eax, [esp + 4]
+ mov dr1, eax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr2.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr2.c new file mode 100644 index 000000000..6e1e7f240 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr2.c @@ -0,0 +1,31 @@ +/** @file
+ AsmWriteDr2 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Writes a value to Debug Register 2 (DR2).
+
+ Writes and returns a new value to DR2. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Value The value to write to Dr2.
+
+ @return The value written to Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr2 (
+ IN UINTN Value
+ )
+{
+ _asm {
+ mov eax, Value
+ mov dr2, eax
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr2.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr2.nasm new file mode 100644 index 000000000..3fd32a772 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr2.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr2.Asm
+;
+; Abstract:
+;
+; AsmWriteDr2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr2 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr2)
+ASM_PFX(AsmWriteDr2):
+ mov eax, [esp + 4]
+ mov dr2, eax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr3.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr3.c new file mode 100644 index 000000000..7cb1d3724 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr3.c @@ -0,0 +1,31 @@ +/** @file
+ AsmWriteDr3 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Writes a value to Debug Register 3 (DR3).
+
+ Writes and returns a new value to DR3. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Value The value to write to Dr3.
+
+ @return The value written to Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr3 (
+ IN UINTN Value
+ )
+{
+ _asm {
+ mov eax, Value
+ mov dr3, eax
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr3.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr3.nasm new file mode 100644 index 000000000..73ad24a8c --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr3.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr3.Asm
+;
+; Abstract:
+;
+; AsmWriteDr3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr3 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr3)
+ASM_PFX(AsmWriteDr3):
+ mov eax, [esp + 4]
+ mov dr3, eax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr4.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr4.c new file mode 100644 index 000000000..778017f33 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr4.c @@ -0,0 +1,33 @@ +/** @file
+ AsmWriteDr4 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Writes a value to Debug Register 4 (DR4).
+
+ Writes and returns a new value to DR4. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Value The value to write to Dr4.
+
+ @return The value written to Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr4 (
+ IN UINTN Value
+ )
+{
+ _asm {
+ mov eax, Value
+ _emit 0x0f // mov dr4, eax
+ _emit 0x23
+ _emit 0xe0
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm new file mode 100644 index 000000000..0d23fca11 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm @@ -0,0 +1,39 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr4.Asm
+;
+; Abstract:
+;
+; AsmWriteDr4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr4 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr4)
+ASM_PFX(AsmWriteDr4):
+ mov eax, [esp + 4]
+ ;
+ ; DR4 is alias to DR6 only if DE (in CR4) is cleared. Otherwise, writing to
+ ; this register will cause a #UD exception.
+ ;
+ ; MS assembler doesn't support this instruction since no one would use it
+ ; under normal circustances. Here opcode is used.
+ ;
+ DB 0xf, 0x23, 0xe0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr5.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr5.c new file mode 100644 index 000000000..2159813a3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr5.c @@ -0,0 +1,33 @@ +/** @file
+ AsmWriteDr5 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Writes a value to Debug Register 5 (DR5).
+
+ Writes and returns a new value to DR5. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Value The value to write to Dr5.
+
+ @return The value written to Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr5 (
+ IN UINTN Value
+ )
+{
+ _asm {
+ mov eax, Value
+ _emit 0x0f // mov dr5, eax
+ _emit 0x23
+ _emit 0xe8
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm new file mode 100644 index 000000000..bc5f424b8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm @@ -0,0 +1,39 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr5.Asm
+;
+; Abstract:
+;
+; AsmWriteDr5 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr5 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr5)
+ASM_PFX(AsmWriteDr5):
+ mov eax, [esp + 4]
+ ;
+ ; DR5 is alias to DR7 only if DE (in CR4) is cleared. Otherwise, writing to
+ ; this register will cause a #UD exception.
+ ;
+ ; MS assembler doesn't support this instruction since no one would use it
+ ; under normal circustances. Here opcode is used.
+ ;
+ DB 0xf, 0x23, 0xe8
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr6.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr6.c new file mode 100644 index 000000000..c03d71643 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr6.c @@ -0,0 +1,31 @@ +/** @file
+ AsmWriteDr6 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Writes a value to Debug Register 6 (DR6).
+
+ Writes and returns a new value to DR6. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Value The value to write to Dr6.
+
+ @return The value written to Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr6 (
+ IN UINTN Value
+ )
+{
+ _asm {
+ mov eax, Value
+ mov dr6, eax
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr6.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr6.nasm new file mode 100644 index 000000000..9089c52c9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr6.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr6.Asm
+;
+; Abstract:
+;
+; AsmWriteDr6 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr6 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr6)
+ASM_PFX(AsmWriteDr6):
+ mov eax, [esp + 4]
+ mov dr6, eax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr7.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr7.c new file mode 100644 index 000000000..c4821e4cd --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr7.c @@ -0,0 +1,31 @@ +/** @file
+ AsmWriteDr7 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Writes a value to Debug Register 7 (DR7).
+
+ Writes and returns a new value to DR7. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Value The value to write to Dr7.
+
+ @return The value written to Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr7 (
+ IN UINTN Value
+ )
+{
+ _asm {
+ mov eax, Value
+ mov dr7, eax
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr7.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr7.nasm new file mode 100644 index 000000000..5dc22b695 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteDr7.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr7.Asm
+;
+; Abstract:
+;
+; AsmWriteDr7 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr7 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr7)
+ASM_PFX(AsmWriteDr7):
+ mov eax, [esp + 4]
+ mov dr7, eax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteGdtr.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteGdtr.c new file mode 100644 index 000000000..37ceae73f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteGdtr.c @@ -0,0 +1,33 @@ +/** @file
+ AsmWriteGdtr function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+
+/**
+ Writes the current Global Descriptor Table Register (GDTR) descriptor.
+
+ Writes and the current GDTR descriptor specified by Gdtr. This function is
+ only available on IA-32 and x64.
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86WriteGdtr (
+ IN CONST IA32_DESCRIPTOR *Gdtr
+ )
+{
+ _asm {
+ mov eax, Gdtr
+ lgdt fword ptr [eax]
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteGdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteGdtr.nasm new file mode 100644 index 000000000..cc1a08a53 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteGdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteGdtr.Asm
+;
+; Abstract:
+;
+; AsmWriteGdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86WriteGdtr (
+; IN CONST IA32_DESCRIPTOR *Idtr
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86WriteGdtr)
+ASM_PFX(InternalX86WriteGdtr):
+ mov eax, [esp + 4]
+ lgdt [eax]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteIdtr.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteIdtr.c new file mode 100644 index 000000000..49ef22b99 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteIdtr.c @@ -0,0 +1,35 @@ +/** @file
+ AsmWriteIdtr function
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.
+
+ Writes the current IDTR descriptor and returns it in Idtr. This function is
+ only available on IA-32 and x64.
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86WriteIdtr (
+ IN CONST IA32_DESCRIPTOR *Idtr
+ )
+{
+ _asm {
+ mov eax, Idtr
+ pushfd
+ cli
+ lidt fword ptr [eax]
+ popfd
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteIdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteIdtr.nasm new file mode 100644 index 000000000..074dc1846 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteIdtr.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteIdtr.Asm
+;
+; Abstract:
+;
+; AsmWriteIdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86WriteIdtr (
+; IN CONST IA32_DESCRIPTOR *Idtr
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86WriteIdtr)
+ASM_PFX(InternalX86WriteIdtr):
+ mov eax, [esp + 4]
+ pushfd
+ cli
+ lidt [eax]
+ popfd
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteLdtr.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteLdtr.c new file mode 100644 index 000000000..8e12f7840 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteLdtr.c @@ -0,0 +1,33 @@ +/** @file
+ AsmWriteLdtr function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Writes the current Local Descriptor Table Register (GDTR) selector.
+
+ Writes and the current LDTR descriptor specified by Ldtr. This function is
+ only available on IA-32 and x64.
+
+ @param Ldtr 16-bit LDTR selector value.
+
+**/
+VOID
+EFIAPI
+AsmWriteLdtr (
+ IN UINT16 Ldtr
+ )
+{
+ _asm {
+ xor eax, eax
+ mov ax, Ldtr
+ lldt ax
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteLdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteLdtr.nasm new file mode 100644 index 000000000..870ea18d7 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteLdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteLdtr.Asm
+;
+; Abstract:
+;
+; AsmWriteLdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteLdtr (
+; IN UINT16 Ldtr
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteLdtr)
+ASM_PFX(AsmWriteLdtr):
+ mov eax, [esp + 4]
+ lldt ax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm0.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm0.c new file mode 100644 index 000000000..ea26009a6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm0.c @@ -0,0 +1,32 @@ +/** @file
+ AsmWriteMm0 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Writes the current value of 64-bit MMX Register #0 (MM0).
+
+ Writes the current value of MM0. This function is only available on IA32 and
+ x64.
+
+ @param Value The 64-bit value to write to MM0.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm0 (
+ IN UINT64 Value
+ )
+{
+ _asm {
+ movq mm0, qword ptr [Value]
+ emms
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm0.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm0.nasm new file mode 100644 index 000000000..4fcf9da85 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm0.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm0.Asm
+;
+; Abstract:
+;
+; AsmWriteMm0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm0 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm0)
+ASM_PFX(AsmWriteMm0):
+ movq mm0, [esp + 4]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm1.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm1.c new file mode 100644 index 000000000..b8da47329 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm1.c @@ -0,0 +1,32 @@ +/** @file
+ AsmWriteMm1 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Writes the current value of 64-bit MMX Register #1 (MM1).
+
+ Writes the current value of MM1. This function is only available on IA32 and
+ x64.
+
+ @param Value The 64-bit value to write to MM1.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm1 (
+ IN UINT64 Value
+ )
+{
+ _asm {
+ movq mm1, qword ptr [Value]
+ emms
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm1.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm1.nasm new file mode 100644 index 000000000..00e2d10b9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm1.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm1.Asm
+;
+; Abstract:
+;
+; AsmWriteMm1 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm1 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm1)
+ASM_PFX(AsmWriteMm1):
+ movq mm1, [esp + 4]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm2.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm2.c new file mode 100644 index 000000000..6b77aed7a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm2.c @@ -0,0 +1,32 @@ +/** @file
+ AsmWriteMm2 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Writes the current value of 64-bit MMX Register #2 (MM2).
+
+ Writes the current value of MM2. This function is only available on IA32 and
+ x64.
+
+ @param Value The 64-bit value to write to MM2.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm2 (
+ IN UINT64 Value
+ )
+{
+ _asm {
+ movq mm2, qword ptr [Value]
+ emms
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm2.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm2.nasm new file mode 100644 index 000000000..ec9d2b299 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm2.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm2.Asm
+;
+; Abstract:
+;
+; AsmWriteMm2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm2 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm2)
+ASM_PFX(AsmWriteMm2):
+ movq mm2, [esp + 4]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm3.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm3.c new file mode 100644 index 000000000..4fc7d7042 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm3.c @@ -0,0 +1,32 @@ +/** @file
+ AsmWriteMm3 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Writes the current value of 64-bit MMX Register #3 (MM3).
+
+ Writes the current value of MM3. This function is only available on IA32 and
+ x64.
+
+ @param Value The 64-bit value to write to MM3.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm3 (
+ IN UINT64 Value
+ )
+{
+ _asm {
+ movq mm3, qword ptr [Value]
+ emms
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm3.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm3.nasm new file mode 100644 index 000000000..01d29c49a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm3.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm3.Asm
+;
+; Abstract:
+;
+; AsmWriteMm3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm3 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm3)
+ASM_PFX(AsmWriteMm3):
+ movq mm3, [esp + 4]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm4.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm4.c new file mode 100644 index 000000000..2fce55497 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm4.c @@ -0,0 +1,31 @@ +/** @file
+ AsmWriteMm4 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Writes the current value of 64-bit MMX Register #4 (MM4).
+
+ Writes the current value of MM4. This function is only available on IA32 and
+ x64.
+
+ @param Value The 64-bit value to write to MM4.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm4 (
+ IN UINT64 Value
+ )
+{
+ _asm {
+ movq mm4, qword ptr [Value]
+ emms
+ }
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm4.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm4.nasm new file mode 100644 index 000000000..0b2255655 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm4.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm4.Asm
+;
+; Abstract:
+;
+; AsmWriteMm4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm4 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm4)
+ASM_PFX(AsmWriteMm4):
+ movq mm4, [esp + 4]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm5.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm5.c new file mode 100644 index 000000000..a0ec714e3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm5.c @@ -0,0 +1,31 @@ +/** @file
+ AsmWriteMm5 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Writes the current value of 64-bit MMX Register #5 (MM5).
+
+ Writes the current value of MM5. This function is only available on IA32 and
+ x64.
+
+ @param Value The 64-bit value to write to MM5.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm5 (
+ IN UINT64 Value
+ )
+{
+ _asm {
+ movq mm5, qword ptr [Value]
+ emms
+ }
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm5.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm5.nasm new file mode 100644 index 000000000..4a3c0df48 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm5.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm5.Asm
+;
+; Abstract:
+;
+; AsmWriteMm5 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm5 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm5)
+ASM_PFX(AsmWriteMm5):
+ movq mm5, [esp + 4]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm6.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm6.c new file mode 100644 index 000000000..c3b57b4b5 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm6.c @@ -0,0 +1,32 @@ +/** @file
+ AsmWriteMm6 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Writes the current value of 64-bit MMX Register #6 (MM6).
+
+ Writes the current value of MM6. This function is only available on IA32 and
+ x64.
+
+ @param Value The 64-bit value to write to MM6.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm6 (
+ IN UINT64 Value
+ )
+{
+ _asm {
+ movq mm6, qword ptr [Value]
+ emms
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm6.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm6.nasm new file mode 100644 index 000000000..397ccfbc2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm6.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm6.Asm
+;
+; Abstract:
+;
+; AsmWriteMm6 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm6 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm6)
+ASM_PFX(AsmWriteMm6):
+ movq mm6, [esp + 4]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm7.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm7.c new file mode 100644 index 000000000..e1e893245 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm7.c @@ -0,0 +1,32 @@ +/** @file
+ AsmWriteMm7 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Writes the current value of 64-bit MMX Register #7 (MM7).
+
+ Writes the current value of MM7. This function is only available on IA32 and
+ x64.
+
+ @param Value The 64-bit value to write to MM7.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm7 (
+ IN UINT64 Value
+ )
+{
+ _asm {
+ movq mm7, qword ptr [Value]
+ emms
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm7.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm7.nasm new file mode 100644 index 000000000..ee3c7f1d1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMm7.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm7.Asm
+;
+; Abstract:
+;
+; AsmWriteMm7 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm7 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm7)
+ASM_PFX(AsmWriteMm7):
+ movq mm7, [esp + 4]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c new file mode 100644 index 000000000..badf1d8e5 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c @@ -0,0 +1,43 @@ +/** @file
+ AsmWriteMsr64 function
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
+ value.
+
+ Writes the 64-bit value specified by Value to the MSR specified by Index. The
+ 64-bit value written to the MSR is returned. No parameter checking is
+ performed on Index or Value, and some of these may cause CPU exceptions. The
+ caller must either guarantee that Index and Value are valid, or the caller
+ must establish proper exception handlers. This function is only available on
+ IA-32 and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param Value The 64-bit value to write to the MSR.
+
+ @return Value
+
+**/
+UINT64
+EFIAPI
+AsmWriteMsr64 (
+ IN UINT32 Index,
+ IN UINT64 Value
+ )
+{
+ _asm {
+ mov edx, dword ptr [Value + 4]
+ mov eax, dword ptr [Value + 0]
+ mov ecx, Index
+ wrmsr
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMsr64.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMsr64.nasm new file mode 100644 index 000000000..f9e3b0561 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteMsr64.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMsr64.Asm
+;
+; Abstract:
+;
+; AsmWriteMsr64 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmWriteMsr64 (
+; IN UINT32 Index,
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMsr64)
+ASM_PFX(AsmWriteMsr64):
+ mov edx, [esp + 12]
+ mov eax, [esp + 8]
+ mov ecx, [esp + 4]
+ wrmsr
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm new file mode 100644 index 000000000..e36c63863 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm @@ -0,0 +1,30 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteTr.nasm
+;
+; Abstract:
+;
+; Write TR register
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; AsmWriteTr (
+; UINT16 Selector
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteTr)
+ASM_PFX(AsmWriteTr):
+ mov eax, [esp+4]
+ ltr ax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm b/roms/edk2/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm new file mode 100644 index 000000000..9f7b03bbf --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; XGetBv.Asm
+;
+; Abstract:
+;
+; AsmXgetBv function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmXGetBv (
+; IN UINT32 Index
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmXGetBv)
+ASM_PFX(AsmXGetBv):
+ mov ecx, [esp + 4]
+ xgetbv
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/LRotU32.c b/roms/edk2/MdePkg/Library/BaseLib/LRotU32.c new file mode 100644 index 000000000..4e671a320 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/LRotU32.c @@ -0,0 +1,36 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Rotates a 32-bit integer left between 0 and 31 bits, filling the low bits
+ with the high bits that were rotated.
+
+ This function rotates the 32-bit value Operand to the left by Count bits. The
+ low Count bits are fill with the high Count bits of Operand. The rotated
+ value is returned.
+
+ If Count is greater than 31, then ASSERT().
+
+ @param Operand The 32-bit operand to rotate left.
+ @param Count The number of bits to rotate left.
+
+ @return Operand << Count
+
+**/
+UINT32
+EFIAPI
+LRotU32 (
+ IN UINT32 Operand,
+ IN UINTN Count
+ )
+{
+ ASSERT (Count < 32);
+ return (Operand << Count) | (Operand >> (32 - Count));
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/LRotU64.c b/roms/edk2/MdePkg/Library/BaseLib/LRotU64.c new file mode 100644 index 000000000..48f35dc63 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/LRotU64.c @@ -0,0 +1,36 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Rotates a 64-bit integer left between 0 and 63 bits, filling the low bits
+ with the high bits that were rotated.
+
+ This function rotates the 64-bit value Operand to the left by Count bits. The
+ low Count bits are fill with the high Count bits of Operand. The rotated
+ value is returned.
+
+ If Count is greater than 63, then ASSERT().
+
+ @param Operand The 64-bit operand to rotate left.
+ @param Count The number of bits to rotate left.
+
+ @return Operand << Count
+
+**/
+UINT64
+EFIAPI
+LRotU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ )
+{
+ ASSERT (Count < 64);
+ return InternalMathLRotU64 (Operand, Count);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/LShiftU64.c b/roms/edk2/MdePkg/Library/BaseLib/LShiftU64.c new file mode 100644 index 000000000..7b41a3efb --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/LShiftU64.c @@ -0,0 +1,35 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Shifts a 64-bit integer left between 0 and 63 bits. The low bits are filled
+ with zeros. The shifted value is returned.
+
+ This function shifts the 64-bit value Operand to the left by Count bits. The
+ low Count bits are set to zero. The shifted value is returned.
+
+ If Count is greater than 63, then ASSERT().
+
+ @param Operand The 64-bit operand to shift left.
+ @param Count The number of bits to shift left.
+
+ @return Operand << Count.
+
+**/
+UINT64
+EFIAPI
+LShiftU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ )
+{
+ ASSERT (Count < 64);
+ return InternalMathLShiftU64 (Operand, Count);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/LinkedList.c b/roms/edk2/MdePkg/Library/BaseLib/LinkedList.c new file mode 100644 index 000000000..5648c1877 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/LinkedList.c @@ -0,0 +1,599 @@ +/** @file
+ Linked List Library Functions.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ If PcdVerifyNodeInList is TRUE, ASSERTs when SecondEntry is or is not part of
+ the same doubly-linked list as FirstEntry depending on the value of InList.
+ Independent of PcdVerifyNodeInList, ASSERTs when FirstEntry is not part of a
+ valid list.
+
+ If FirstEntry is NULL, then ASSERT().
+ If FirstEntry->ForwardLink is NULL, then ASSERT().
+ If FirstEntry->BackLink is NULL, then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and List contains more than
+ PcdMaximumLinkedListLength nodes, then ASSERT().
+ If PcdVerifyNodeInList is TRUE and SecondEntry is NULL, then ASSERT().
+
+ @param FirstEntry A pointer to a node in a linked list.
+ @param SecondEntry A pointer to the node to locate.
+ @param InList Defines whether to check if SecondEntry is or is not part
+ of the same doubly-linked list as FirstEntry.
+
+**/
+#if !defined (MDEPKG_NDEBUG)
+ #define ASSERT_VERIFY_NODE_IN_VALID_LIST(FirstEntry, SecondEntry, InList) \
+ do { \
+ if (FeaturePcdGet (PcdVerifyNodeInList)) { \
+ ASSERT (InList == IsNodeInList ((FirstEntry), (SecondEntry))); \
+ } else { \
+ ASSERT (InternalBaseLibIsListValid (FirstEntry)); \
+ } \
+ } while (FALSE)
+#else
+ #define ASSERT_VERIFY_NODE_IN_VALID_LIST(FirstEntry, SecondEntry, InList)
+#endif
+
+/**
+ Worker function that verifies the validity of this list.
+
+ If List is NULL, then ASSERT().
+ If List->ForwardLink is NULL, then ASSERT().
+ If List->BackLink is NULL, then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and List contains more than
+ PcdMaximumLinkedListLength nodes, then ASSERT().
+
+ @param List A pointer to a node in a linked list.
+
+ @retval TRUE if PcdVerifyNodeInList is FALSE
+ @retval TRUE if DoMembershipCheck is FALSE
+ @retval TRUE if PcdVerifyNodeInList is TRUE and DoMembershipCheck is TRUE
+ and Node is a member of List.
+ @retval FALSE if PcdVerifyNodeInList is TRUE and DoMembershipCheck is TRUE
+ and Node is in not a member of List.
+
+**/
+BOOLEAN
+EFIAPI
+InternalBaseLibIsListValid (
+ IN CONST LIST_ENTRY *List
+ )
+{
+ UINTN Count;
+ CONST LIST_ENTRY *Ptr;
+
+ //
+ // Test the validity of List and Node
+ //
+ ASSERT (List != NULL);
+ ASSERT (List->ForwardLink != NULL);
+ ASSERT (List->BackLink != NULL);
+
+ if (PcdGet32 (PcdMaximumLinkedListLength) > 0) {
+ Count = 0;
+ Ptr = List;
+
+ //
+ // Count the total number of nodes in List.
+ // Exit early if the number of nodes in List >= PcdMaximumLinkedListLength
+ //
+ do {
+ Ptr = Ptr->ForwardLink;
+ Count++;
+ } while ((Ptr != List) && (Count < PcdGet32 (PcdMaximumLinkedListLength)));
+
+ //
+ // return whether linked list is too long
+ //
+ return (BOOLEAN)(Count < PcdGet32 (PcdMaximumLinkedListLength));
+ }
+
+ return TRUE;
+}
+
+/**
+ Checks whether FirstEntry and SecondEntry are part of the same doubly-linked
+ list.
+
+ If FirstEntry is NULL, then ASSERT().
+ If FirstEntry->ForwardLink is NULL, then ASSERT().
+ If FirstEntry->BackLink is NULL, then ASSERT().
+ If SecondEntry is NULL, then ASSERT();
+ If PcdMaximumLinkedListLength is not zero, and List contains more than
+ PcdMaximumLinkedListLength nodes, then ASSERT().
+
+ @param FirstEntry A pointer to a node in a linked list.
+ @param SecondEntry A pointer to the node to locate.
+
+ @retval TRUE SecondEntry is in the same doubly-linked list as FirstEntry.
+ @retval FALSE SecondEntry isn't in the same doubly-linked list as FirstEntry,
+ or FirstEntry is invalid.
+
+**/
+BOOLEAN
+EFIAPI
+IsNodeInList (
+ IN CONST LIST_ENTRY *FirstEntry,
+ IN CONST LIST_ENTRY *SecondEntry
+ )
+{
+ UINTN Count;
+ CONST LIST_ENTRY *Ptr;
+
+ //
+ // ASSERT List not too long
+ //
+ ASSERT (InternalBaseLibIsListValid (FirstEntry));
+
+ ASSERT (SecondEntry != NULL);
+
+ Count = 0;
+ Ptr = FirstEntry;
+
+ //
+ // Check to see if SecondEntry is a member of FirstEntry.
+ // Exit early if the number of nodes in List >= PcdMaximumLinkedListLength
+ //
+ do {
+ Ptr = Ptr->ForwardLink;
+ if (PcdGet32 (PcdMaximumLinkedListLength) > 0) {
+ Count++;
+
+ //
+ // Return if the linked list is too long
+ //
+ if (Count == PcdGet32 (PcdMaximumLinkedListLength)) {
+ return (BOOLEAN)(Ptr == SecondEntry);
+ }
+ }
+
+ if (Ptr == SecondEntry) {
+ return TRUE;
+ }
+ } while (Ptr != FirstEntry);
+
+ return FALSE;
+}
+
+/**
+ Initializes the head node of a doubly-linked list, and returns the pointer to
+ the head node of the doubly-linked list.
+
+ Initializes the forward and backward links of a new linked list. After
+ initializing a linked list with this function, the other linked list
+ functions may be used to add and remove nodes from the linked list. It is up
+ to the caller of this function to allocate the memory for ListHead.
+
+ If ListHead is NULL, then ASSERT().
+
+ @param ListHead A pointer to the head node of a new doubly-linked list.
+
+ @return ListHead
+
+**/
+LIST_ENTRY *
+EFIAPI
+InitializeListHead (
+ IN OUT LIST_ENTRY *ListHead
+ )
+
+{
+ ASSERT (ListHead != NULL);
+
+ ListHead->ForwardLink = ListHead;
+ ListHead->BackLink = ListHead;
+ return ListHead;
+}
+
+/**
+ Adds a node to the beginning of a doubly-linked list, and returns the pointer
+ to the head node of the doubly-linked list.
+
+ Adds the node Entry at the beginning of the doubly-linked list denoted by
+ ListHead, and returns ListHead.
+
+ If ListHead is NULL, then ASSERT().
+ If Entry is NULL, then ASSERT().
+ If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
+ InitializeListHead(), then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and prior to insertion the number
+ of nodes in ListHead, including the ListHead node, is greater than or
+ equal to PcdMaximumLinkedListLength, then ASSERT().
+
+ @param ListHead A pointer to the head node of a doubly-linked list.
+ @param Entry A pointer to a node that is to be inserted at the beginning
+ of a doubly-linked list.
+
+ @return ListHead
+
+**/
+LIST_ENTRY *
+EFIAPI
+InsertHeadList (
+ IN OUT LIST_ENTRY *ListHead,
+ IN OUT LIST_ENTRY *Entry
+ )
+{
+ //
+ // ASSERT List not too long and Entry is not one of the nodes of List
+ //
+ ASSERT_VERIFY_NODE_IN_VALID_LIST (ListHead, Entry, FALSE);
+
+ Entry->ForwardLink = ListHead->ForwardLink;
+ Entry->BackLink = ListHead;
+ Entry->ForwardLink->BackLink = Entry;
+ ListHead->ForwardLink = Entry;
+ return ListHead;
+}
+
+/**
+ Adds a node to the end of a doubly-linked list, and returns the pointer to
+ the head node of the doubly-linked list.
+
+ Adds the node Entry to the end of the doubly-linked list denoted by ListHead,
+ and returns ListHead.
+
+ If ListHead is NULL, then ASSERT().
+ If Entry is NULL, then ASSERT().
+ If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
+ InitializeListHead(), then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and prior to insertion the number
+ of nodes in ListHead, including the ListHead node, is greater than or
+ equal to PcdMaximumLinkedListLength, then ASSERT().
+
+ @param ListHead A pointer to the head node of a doubly-linked list.
+ @param Entry A pointer to a node that is to be added at the end of the
+ doubly-linked list.
+
+ @return ListHead
+
+**/
+LIST_ENTRY *
+EFIAPI
+InsertTailList (
+ IN OUT LIST_ENTRY *ListHead,
+ IN OUT LIST_ENTRY *Entry
+ )
+{
+ //
+ // ASSERT List not too long and Entry is not one of the nodes of List
+ //
+ ASSERT_VERIFY_NODE_IN_VALID_LIST (ListHead, Entry, FALSE);
+
+ Entry->ForwardLink = ListHead;
+ Entry->BackLink = ListHead->BackLink;
+ Entry->BackLink->ForwardLink = Entry;
+ ListHead->BackLink = Entry;
+ return ListHead;
+}
+
+/**
+ Retrieves the first node of a doubly-linked list.
+
+ Returns the first node of a doubly-linked list. List must have been
+ initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead().
+ If List is empty, then List is returned.
+
+ If List is NULL, then ASSERT().
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
+ InitializeListHead(), then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and the number of nodes
+ in List, including the List node, is greater than or equal to
+ PcdMaximumLinkedListLength, then ASSERT().
+
+ @param List A pointer to the head node of a doubly-linked list.
+
+ @return The first node of a doubly-linked list.
+ @retval List The list is empty.
+
+**/
+LIST_ENTRY *
+EFIAPI
+GetFirstNode (
+ IN CONST LIST_ENTRY *List
+ )
+{
+ //
+ // ASSERT List not too long
+ //
+ ASSERT (InternalBaseLibIsListValid (List));
+
+ return List->ForwardLink;
+}
+
+/**
+ Retrieves the next node of a doubly-linked list.
+
+ Returns the node of a doubly-linked list that follows Node.
+ List must have been initialized with INTIALIZE_LIST_HEAD_VARIABLE()
+ or InitializeListHead(). If List is empty, then List is returned.
+
+ If List is NULL, then ASSERT().
+ If Node is NULL, then ASSERT().
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
+ InitializeListHead(), then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and List contains more than
+ PcdMaximumLinkedListLength nodes, then ASSERT().
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT().
+
+ @param List A pointer to the head node of a doubly-linked list.
+ @param Node A pointer to a node in the doubly-linked list.
+
+ @return A pointer to the next node if one exists. Otherwise List is returned.
+
+**/
+LIST_ENTRY *
+EFIAPI
+GetNextNode (
+ IN CONST LIST_ENTRY *List,
+ IN CONST LIST_ENTRY *Node
+ )
+{
+ //
+ // ASSERT List not too long and Node is one of the nodes of List
+ //
+ ASSERT_VERIFY_NODE_IN_VALID_LIST (List, Node, TRUE);
+
+ return Node->ForwardLink;
+}
+
+/**
+ Retrieves the previous node of a doubly-linked list.
+
+ Returns the node of a doubly-linked list that precedes Node.
+ List must have been initialized with INTIALIZE_LIST_HEAD_VARIABLE()
+ or InitializeListHead(). If List is empty, then List is returned.
+
+ If List is NULL, then ASSERT().
+ If Node is NULL, then ASSERT().
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
+ InitializeListHead(), then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and List contains more than
+ PcdMaximumLinkedListLength nodes, then ASSERT().
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT().
+
+ @param List A pointer to the head node of a doubly-linked list.
+ @param Node A pointer to a node in the doubly-linked list.
+
+ @return A pointer to the previous node if one exists. Otherwise List is returned.
+
+**/
+LIST_ENTRY *
+EFIAPI
+GetPreviousNode (
+ IN CONST LIST_ENTRY *List,
+ IN CONST LIST_ENTRY *Node
+ )
+{
+ //
+ // ASSERT List not too long and Node is one of the nodes of List
+ //
+ ASSERT_VERIFY_NODE_IN_VALID_LIST (List, Node, TRUE);
+
+ return Node->BackLink;
+}
+
+/**
+ Checks to see if a doubly-linked list is empty or not.
+
+ Checks to see if the doubly-linked list is empty. If the linked list contains
+ zero nodes, this function returns TRUE. Otherwise, it returns FALSE.
+
+ If ListHead is NULL, then ASSERT().
+ If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
+ InitializeListHead(), then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and the number of nodes
+ in List, including the List node, is greater than or equal to
+ PcdMaximumLinkedListLength, then ASSERT().
+
+ @param ListHead A pointer to the head node of a doubly-linked list.
+
+ @retval TRUE The linked list is empty.
+ @retval FALSE The linked list is not empty.
+
+**/
+BOOLEAN
+EFIAPI
+IsListEmpty (
+ IN CONST LIST_ENTRY *ListHead
+ )
+{
+ //
+ // ASSERT List not too long
+ //
+ ASSERT (InternalBaseLibIsListValid (ListHead));
+
+ return (BOOLEAN)(ListHead->ForwardLink == ListHead);
+}
+
+/**
+ Determines if a node in a doubly-linked list is the head node of a the same
+ doubly-linked list. This function is typically used to terminate a loop that
+ traverses all the nodes in a doubly-linked list starting with the head node.
+
+ Returns TRUE if Node is equal to List. Returns FALSE if Node is one of the
+ nodes in the doubly-linked list specified by List. List must have been
+ initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead().
+
+ If List is NULL, then ASSERT().
+ If Node is NULL, then ASSERT().
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead(),
+ then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and the number of nodes
+ in List, including the List node, is greater than or equal to
+ PcdMaximumLinkedListLength, then ASSERT().
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List and Node is not
+ equal to List, then ASSERT().
+
+ @param List A pointer to the head node of a doubly-linked list.
+ @param Node A pointer to a node in the doubly-linked list.
+
+ @retval TRUE Node is the head of the doubly-linked list pointed by List.
+ @retval FALSE Node is not the head of the doubly-linked list pointed by List.
+
+**/
+BOOLEAN
+EFIAPI
+IsNull (
+ IN CONST LIST_ENTRY *List,
+ IN CONST LIST_ENTRY *Node
+ )
+{
+ //
+ // ASSERT List not too long and Node is one of the nodes of List
+ //
+ ASSERT_VERIFY_NODE_IN_VALID_LIST (List, Node, TRUE);
+
+ return (BOOLEAN)(Node == List);
+}
+
+/**
+ Determines if a node the last node in a doubly-linked list.
+
+ Returns TRUE if Node is the last node in the doubly-linked list specified by
+ List. Otherwise, FALSE is returned. List must have been initialized with
+ INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead().
+
+ If List is NULL, then ASSERT().
+ If Node is NULL, then ASSERT().
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
+ InitializeListHead(), then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and the number of nodes
+ in List, including the List node, is greater than or equal to
+ PcdMaximumLinkedListLength, then ASSERT().
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT().
+
+ @param List A pointer to the head node of a doubly-linked list.
+ @param Node A pointer to a node in the doubly-linked list.
+
+ @retval TRUE Node is the last node in the linked list.
+ @retval FALSE Node is not the last node in the linked list.
+
+**/
+BOOLEAN
+EFIAPI
+IsNodeAtEnd (
+ IN CONST LIST_ENTRY *List,
+ IN CONST LIST_ENTRY *Node
+ )
+{
+ //
+ // ASSERT List not too long and Node is one of the nodes of List
+ //
+ ASSERT_VERIFY_NODE_IN_VALID_LIST (List, Node, TRUE);
+
+ return (BOOLEAN)(!IsNull (List, Node) && List->BackLink == Node);
+}
+
+/**
+ Swaps the location of two nodes in a doubly-linked list, and returns the
+ first node after the swap.
+
+ If FirstEntry is identical to SecondEntry, then SecondEntry is returned.
+ Otherwise, the location of the FirstEntry node is swapped with the location
+ of the SecondEntry node in a doubly-linked list. SecondEntry must be in the
+ same double linked list as FirstEntry and that double linked list must have
+ been initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead().
+ SecondEntry is returned after the nodes are swapped.
+
+ If FirstEntry is NULL, then ASSERT().
+ If SecondEntry is NULL, then ASSERT().
+ If PcdVerifyNodeInList is TRUE and SecondEntry and FirstEntry are not in the
+ same linked list, then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and the number of nodes in the
+ linked list containing the FirstEntry and SecondEntry nodes, including
+ the FirstEntry and SecondEntry nodes, is greater than or equal to
+ PcdMaximumLinkedListLength, then ASSERT().
+
+ @param FirstEntry A pointer to a node in a linked list.
+ @param SecondEntry A pointer to another node in the same linked list.
+
+ @return SecondEntry.
+
+**/
+LIST_ENTRY *
+EFIAPI
+SwapListEntries (
+ IN OUT LIST_ENTRY *FirstEntry,
+ IN OUT LIST_ENTRY *SecondEntry
+ )
+{
+ LIST_ENTRY *Ptr;
+
+ if (FirstEntry == SecondEntry) {
+ return SecondEntry;
+ }
+
+ //
+ // ASSERT Entry1 and Entry2 are in the same linked list
+ //
+ ASSERT_VERIFY_NODE_IN_VALID_LIST (FirstEntry, SecondEntry, TRUE);
+
+ //
+ // Ptr is the node pointed to by FirstEntry->ForwardLink
+ //
+ Ptr = RemoveEntryList (FirstEntry);
+
+ //
+ // If FirstEntry immediately follows SecondEntry, FirstEntry will be placed
+ // immediately in front of SecondEntry
+ //
+ if (Ptr->BackLink == SecondEntry) {
+ return InsertTailList (SecondEntry, FirstEntry);
+ }
+
+ //
+ // Ptr == SecondEntry means SecondEntry immediately follows FirstEntry,
+ // then there are no further steps necessary
+ //
+ if (Ptr == InsertHeadList (SecondEntry, FirstEntry)) {
+ return Ptr;
+ }
+
+ //
+ // Move SecondEntry to the front of Ptr
+ //
+ RemoveEntryList (SecondEntry);
+ InsertTailList (Ptr, SecondEntry);
+ return SecondEntry;
+}
+
+/**
+ Removes a node from a doubly-linked list, and returns the node that follows
+ the removed node.
+
+ Removes the node Entry from a doubly-linked list. It is up to the caller of
+ this function to release the memory used by this node if that is required. On
+ exit, the node following Entry in the doubly-linked list is returned. If
+ Entry is the only node in the linked list, then the head node of the linked
+ list is returned.
+
+ If Entry is NULL, then ASSERT().
+ If Entry is the head node of an empty list, then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and the number of nodes in the
+ linked list containing Entry, including the Entry node, is greater than
+ or equal to PcdMaximumLinkedListLength, then ASSERT().
+
+ @param Entry A pointer to a node in a linked list.
+
+ @return Entry.
+
+**/
+LIST_ENTRY *
+EFIAPI
+RemoveEntryList (
+ IN CONST LIST_ENTRY *Entry
+ )
+{
+ ASSERT (!IsListEmpty (Entry));
+
+ Entry->ForwardLink->BackLink = Entry->BackLink;
+ Entry->BackLink->ForwardLink = Entry->ForwardLink;
+ return Entry->ForwardLink;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/LongJump.c b/roms/edk2/MdePkg/Library/BaseLib/LongJump.c new file mode 100644 index 000000000..1d88e4121 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/LongJump.c @@ -0,0 +1,41 @@ +/** @file
+ Long Jump functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Restores the CPU context that was saved with SetJump().
+
+ Restores the CPU context from the buffer specified by JumpBuffer. This
+ function never returns to the caller. Instead is resumes execution based on
+ the state of JumpBuffer.
+
+ If JumpBuffer is NULL, then ASSERT().
+ For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
+ If Value is 0, then ASSERT().
+
+ @param JumpBuffer A pointer to CPU context buffer.
+ @param Value The value to return when the SetJump() context is
+ restored and must be non-zero.
+
+**/
+VOID
+EFIAPI
+LongJump (
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,
+ IN UINTN Value
+ )
+{
+ InternalAssertJumpBuffer (JumpBuffer);
+ ASSERT (Value != 0);
+
+ InternalLongJump (JumpBuffer, Value);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/LowBitSet32.c b/roms/edk2/MdePkg/Library/BaseLib/LowBitSet32.c new file mode 100644 index 000000000..8383c7954 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/LowBitSet32.c @@ -0,0 +1,41 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Returns the bit position of the lowest bit set in a 32-bit value.
+
+ This function computes the bit position of the lowest bit set in the 32-bit
+ value specified by Operand. If Operand is zero, then -1 is returned.
+ Otherwise, a value between 0 and 31 is returned.
+
+ @param Operand The 32-bit operand to evaluate.
+
+ @retval 0..31 The lowest bit set in Operand was found.
+ @retval -1 Operand is zero.
+
+**/
+INTN
+EFIAPI
+LowBitSet32 (
+ IN UINT32 Operand
+ )
+{
+ INTN BitIndex;
+
+ if (Operand == 0) {
+ return -1;
+ }
+
+ for (BitIndex = 0; 0 == (Operand & 1); BitIndex++, Operand >>= 1);
+ return BitIndex;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/LowBitSet64.c b/roms/edk2/MdePkg/Library/BaseLib/LowBitSet64.c new file mode 100644 index 000000000..349ed526b --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/LowBitSet64.c @@ -0,0 +1,44 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Returns the bit position of the lowest bit set in a 64-bit value.
+
+ This function computes the bit position of the lowest bit set in the 64-bit
+ value specified by Operand. If Operand is zero, then -1 is returned.
+ Otherwise, a value between 0 and 63 is returned.
+
+ @param Operand The 64-bit operand to evaluate.
+
+ @retval 0..63 The lowest bit set in Operand was found.
+ @retval -1 Operand is zero.
+
+
+**/
+INTN
+EFIAPI
+LowBitSet64 (
+ IN UINT64 Operand
+ )
+{
+ INTN BitIndex;
+
+ if (Operand == 0) {
+ return -1;
+ }
+
+ for (BitIndex = 0;
+ (Operand & 1) == 0;
+ BitIndex++, Operand = RShiftU64 (Operand, 1));
+ return BitIndex;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Math64.c b/roms/edk2/MdePkg/Library/BaseLib/Math64.c new file mode 100644 index 000000000..154b97ae7 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Math64.c @@ -0,0 +1,362 @@ +/** @file
+ Leaf math worker functions that require 64-bit arithmetic support from the
+ compiler.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Shifts a 64-bit integer left between 0 and 63 bits. The low bits
+ are filled with zeros. The shifted value is returned.
+
+ This function shifts the 64-bit value Operand to the left by Count bits. The
+ low Count bits are set to zero. The shifted value is returned.
+
+ @param Operand The 64-bit operand to shift left.
+ @param Count The number of bits to shift left.
+
+ @return Operand << Count.
+
+**/
+UINT64
+EFIAPI
+InternalMathLShiftU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ )
+{
+ return Operand << Count;
+}
+
+/**
+ Shifts a 64-bit integer right between 0 and 63 bits. This high bits
+ are filled with zeros. The shifted value is returned.
+
+ This function shifts the 64-bit value Operand to the right by Count bits. The
+ high Count bits are set to zero. The shifted value is returned.
+
+ @param Operand The 64-bit operand to shift right.
+ @param Count The number of bits to shift right.
+
+ @return Operand >> Count.
+
+**/
+UINT64
+EFIAPI
+InternalMathRShiftU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ )
+{
+ return Operand >> Count;
+}
+
+/**
+ Shifts a 64-bit integer right between 0 and 63 bits. The high bits
+ are filled with original integer's bit 63. The shifted value is returned.
+
+ This function shifts the 64-bit value Operand to the right by Count bits. The
+ high Count bits are set to bit 63 of Operand. The shifted value is returned.
+
+ @param Operand The 64-bit operand to shift right.
+ @param Count The number of bits to shift right.
+
+ @return Operand arithmetically shifted right by Count.
+
+**/
+UINT64
+EFIAPI
+InternalMathARShiftU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ )
+{
+ INTN TestValue;
+
+ //
+ // Test if this compiler supports arithmetic shift
+ //
+ TestValue = (INTN)((INT64)(1ULL << 63) >> 63);
+ if (TestValue == -1) {
+ //
+ // Arithmetic shift is supported
+ //
+ return (UINT64)((INT64)Operand >> Count);
+ }
+
+ //
+ // Arithmetic is not supported
+ //
+ return (Operand >> Count) |
+ ((INTN)Operand < 0 ? ~((UINTN)-1 >> Count) : 0);
+}
+
+
+/**
+ Rotates a 64-bit integer left between 0 and 63 bits, filling
+ the low bits with the high bits that were rotated.
+
+ This function rotates the 64-bit value Operand to the left by Count bits. The
+ low Count bits are fill with the high Count bits of Operand. The rotated
+ value is returned.
+
+ @param Operand The 64-bit operand to rotate left.
+ @param Count The number of bits to rotate left.
+
+ @return Operand <<< Count.
+
+**/
+UINT64
+EFIAPI
+InternalMathLRotU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ )
+{
+ return (Operand << Count) | (Operand >> (64 - Count));
+}
+
+/**
+ Rotates a 64-bit integer right between 0 and 63 bits, filling
+ the high bits with the high low bits that were rotated.
+
+ This function rotates the 64-bit value Operand to the right by Count bits.
+ The high Count bits are fill with the low Count bits of Operand. The rotated
+ value is returned.
+
+ @param Operand The 64-bit operand to rotate right.
+ @param Count The number of bits to rotate right.
+
+ @return Operand >>> Count.
+
+**/
+UINT64
+EFIAPI
+InternalMathRRotU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ )
+{
+ return (Operand >> Count) | (Operand << (64 - Count));
+}
+
+/**
+ Switches the endianess of a 64-bit integer.
+
+ This function swaps the bytes in a 64-bit unsigned value to switch the value
+ from little endian to big endian or vice versa. The byte swapped value is
+ returned.
+
+ @param Operand A 64-bit unsigned value.
+
+ @return The byte swapped Operand.
+
+**/
+UINT64
+EFIAPI
+InternalMathSwapBytes64 (
+ IN UINT64 Operand
+ )
+{
+ UINT64 LowerBytes;
+ UINT64 HigherBytes;
+
+ LowerBytes = (UINT64) SwapBytes32 ((UINT32) Operand);
+ HigherBytes = (UINT64) SwapBytes32 ((UINT32) (Operand >> 32));
+
+ return (LowerBytes << 32 | HigherBytes);
+}
+
+/**
+ Multiplies a 64-bit unsigned integer by a 32-bit unsigned integer
+ and generates a 64-bit unsigned result.
+
+ This function multiplies the 64-bit unsigned value Multiplicand by the 32-bit
+ unsigned value Multiplier and generates a 64-bit unsigned result. This 64-
+ bit unsigned result is returned.
+
+ @param Multiplicand A 64-bit unsigned value.
+ @param Multiplier A 32-bit unsigned value.
+
+ @return Multiplicand * Multiplier
+
+**/
+UINT64
+EFIAPI
+InternalMathMultU64x32 (
+ IN UINT64 Multiplicand,
+ IN UINT32 Multiplier
+ )
+{
+ return Multiplicand * Multiplier;
+}
+
+
+/**
+ Multiplies a 64-bit unsigned integer by a 64-bit unsigned integer
+ and generates a 64-bit unsigned result.
+
+ This function multiplies the 64-bit unsigned value Multiplicand by the 64-bit
+ unsigned value Multiplier and generates a 64-bit unsigned result. This 64-
+ bit unsigned result is returned.
+
+ @param Multiplicand A 64-bit unsigned value.
+ @param Multiplier A 64-bit unsigned value.
+
+ @return Multiplicand * Multiplier.
+
+**/
+UINT64
+EFIAPI
+InternalMathMultU64x64 (
+ IN UINT64 Multiplicand,
+ IN UINT64 Multiplier
+ )
+{
+ return Multiplicand * Multiplier;
+}
+
+/**
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and
+ generates a 64-bit unsigned result.
+
+ This function divides the 64-bit unsigned value Dividend by the 32-bit
+ unsigned value Divisor and generates a 64-bit unsigned quotient. This
+ function returns the 64-bit unsigned quotient.
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 32-bit unsigned value.
+
+ @return Dividend / Divisor.
+
+**/
+UINT64
+EFIAPI
+InternalMathDivU64x32 (
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
+ )
+{
+ return Dividend / Divisor;
+}
+
+/**
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and
+ generates a 32-bit unsigned remainder.
+
+ This function divides the 64-bit unsigned value Dividend by the 32-bit
+ unsigned value Divisor and generates a 32-bit remainder. This function
+ returns the 32-bit unsigned remainder.
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 32-bit unsigned value.
+
+ @return Dividend % Divisor.
+
+**/
+UINT32
+EFIAPI
+InternalMathModU64x32 (
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
+ )
+{
+ return (UINT32)(Dividend % Divisor);
+}
+
+/**
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and
+ generates a 64-bit unsigned result and an optional 32-bit unsigned remainder.
+
+ This function divides the 64-bit unsigned value Dividend by the 32-bit
+ unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder
+ is not NULL, then the 32-bit unsigned remainder is returned in Remainder.
+ This function returns the 64-bit unsigned quotient.
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 32-bit unsigned value.
+ @param Remainder A pointer to a 32-bit unsigned value. This parameter is
+ optional and may be NULL.
+
+ @return Dividend / Divisor.
+
+**/
+UINT64
+EFIAPI
+InternalMathDivRemU64x32 (
+ IN UINT64 Dividend,
+ IN UINT32 Divisor,
+ OUT UINT32 *Remainder OPTIONAL
+ )
+{
+ if (Remainder != NULL) {
+ *Remainder = (UINT32)(Dividend % Divisor);
+ }
+ return Dividend / Divisor;
+}
+
+/**
+ Divides a 64-bit unsigned integer by a 64-bit unsigned integer and
+ generates a 64-bit unsigned result and an optional 64-bit unsigned remainder.
+
+ This function divides the 64-bit unsigned value Dividend by the 64-bit
+ unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder
+ is not NULL, then the 64-bit unsigned remainder is returned in Remainder.
+ This function returns the 64-bit unsigned quotient.
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 64-bit unsigned value.
+ @param Remainder A pointer to a 64-bit unsigned value. This parameter is
+ optional and may be NULL.
+
+ @return Dividend / Divisor
+
+**/
+UINT64
+EFIAPI
+InternalMathDivRemU64x64 (
+ IN UINT64 Dividend,
+ IN UINT64 Divisor,
+ OUT UINT64 *Remainder OPTIONAL
+ )
+{
+ if (Remainder != NULL) {
+ *Remainder = Dividend % Divisor;
+ }
+ return Dividend / Divisor;
+}
+
+/**
+ Divides a 64-bit signed integer by a 64-bit signed integer and
+ generates a 64-bit signed result and an optional 64-bit signed remainder.
+
+ This function divides the 64-bit signed value Dividend by the 64-bit
+ signed value Divisor and generates a 64-bit signed quotient. If Remainder
+ is not NULL, then the 64-bit signed remainder is returned in Remainder.
+ This function returns the 64-bit signed quotient.
+
+ @param Dividend A 64-bit signed value.
+ @param Divisor A 64-bit signed value.
+ @param Remainder A pointer to a 64-bit signed value. This parameter is
+ optional and may be NULL.
+
+ @return Dividend / Divisor.
+
+**/
+INT64
+EFIAPI
+InternalMathDivRemS64x64 (
+ IN INT64 Dividend,
+ IN INT64 Divisor,
+ OUT INT64 *Remainder OPTIONAL
+ )
+{
+ if (Remainder != NULL) {
+ *Remainder = Dividend % Divisor;
+ }
+ return Dividend / Divisor;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/ModU64x32.c b/roms/edk2/MdePkg/Library/BaseLib/ModU64x32.c new file mode 100644 index 000000000..ee99ab322 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/ModU64x32.c @@ -0,0 +1,39 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates
+ a 32-bit unsigned remainder.
+
+ This function divides the 64-bit unsigned value Dividend by the 32-bit
+ unsigned value Divisor and generates a 32-bit remainder. This function
+ returns the 32-bit unsigned remainder.
+
+ If Divisor is 0, then ASSERT().
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 32-bit unsigned value.
+
+ @return Dividend % Divisor.
+
+**/
+UINT32
+EFIAPI
+ModU64x32 (
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
+ )
+{
+ ASSERT (Divisor != 0);
+ return InternalMathModU64x32 (Dividend, Divisor);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/MultS64x64.c b/roms/edk2/MdePkg/Library/BaseLib/MultS64x64.c new file mode 100644 index 000000000..b5c745f7c --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/MultS64x64.c @@ -0,0 +1,36 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Multiplies a 64-bit signed integer by a 64-bit signed integer and generates a
+ 64-bit signed result.
+
+ This function multiplies the 64-bit signed value Multiplicand by the 64-bit
+ signed value Multiplier and generates a 64-bit signed result. This 64-bit
+ signed result is returned.
+
+ @param Multiplicand A 64-bit signed value.
+ @param Multiplier A 64-bit signed value.
+
+ @return Multiplicand * Multiplier.
+
+**/
+INT64
+EFIAPI
+MultS64x64 (
+ IN INT64 Multiplicand,
+ IN INT64 Multiplier
+ )
+{
+ return (INT64)MultU64x64 ((UINT64) Multiplicand, (UINT64) Multiplier);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/MultU64x32.c b/roms/edk2/MdePkg/Library/BaseLib/MultU64x32.c new file mode 100644 index 000000000..2bbff51c8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/MultU64x32.c @@ -0,0 +1,40 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Multiplies a 64-bit unsigned integer by a 32-bit unsigned integer and
+ generates a 64-bit unsigned result.
+
+ This function multiplies the 64-bit unsigned value Multiplicand by the 32-bit
+ unsigned value Multiplier and generates a 64-bit unsigned result. This 64-
+ bit unsigned result is returned.
+
+ @param Multiplicand A 64-bit unsigned value.
+ @param Multiplier A 32-bit unsigned value.
+
+ @return Multiplicand * Multiplier.
+
+**/
+UINT64
+EFIAPI
+MultU64x32 (
+ IN UINT64 Multiplicand,
+ IN UINT32 Multiplier
+ )
+{
+ UINT64 Result;
+
+ Result = InternalMathMultU64x32 (Multiplicand, Multiplier);
+
+ return Result;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/MultU64x64.c b/roms/edk2/MdePkg/Library/BaseLib/MultU64x64.c new file mode 100644 index 000000000..e1ee9f1c9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/MultU64x64.c @@ -0,0 +1,40 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Multiplies a 64-bit unsigned integer by a 64-bit unsigned integer and
+ generates a 64-bit unsigned result.
+
+ This function multiplies the 64-bit unsigned value Multiplicand by the 64-bit
+ unsigned value Multiplier and generates a 64-bit unsigned result. This 64-
+ bit unsigned result is returned.
+
+ @param Multiplicand A 64-bit unsigned value.
+ @param Multiplier A 64-bit unsigned value.
+
+ @return Multiplicand * Multiplier.
+
+**/
+UINT64
+EFIAPI
+MultU64x64 (
+ IN UINT64 Multiplicand,
+ IN UINT64 Multiplier
+ )
+{
+ UINT64 Result;
+
+ Result = InternalMathMultU64x64 (Multiplicand, Multiplier);
+
+ return Result;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/RRotU32.c b/roms/edk2/MdePkg/Library/BaseLib/RRotU32.c new file mode 100644 index 000000000..3956faddd --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/RRotU32.c @@ -0,0 +1,36 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Rotates a 32-bit integer right between 0 and 31 bits, filling the high bits
+ with the low bits that were rotated.
+
+ This function rotates the 32-bit value Operand to the right by Count bits.
+ The high Count bits are fill with the low Count bits of Operand. The rotated
+ value is returned.
+
+ If Count is greater than 31, then ASSERT().
+
+ @param Operand The 32-bit operand to rotate right.
+ @param Count The number of bits to rotate right.
+
+ @return Operand >> Count.
+
+**/
+UINT32
+EFIAPI
+RRotU32 (
+ IN UINT32 Operand,
+ IN UINTN Count
+ )
+{
+ ASSERT (Count < 32);
+ return (Operand >> Count) | (Operand << (32 - Count));
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/RRotU64.c b/roms/edk2/MdePkg/Library/BaseLib/RRotU64.c new file mode 100644 index 000000000..e07ffd656 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/RRotU64.c @@ -0,0 +1,36 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Rotates a 64-bit integer right between 0 and 63 bits, filling the high bits
+ with the high low bits that were rotated.
+
+ This function rotates the 64-bit value Operand to the right by Count bits.
+ The high Count bits are fill with the low Count bits of Operand. The rotated
+ value is returned.
+
+ If Count is greater than 63, then ASSERT().
+
+ @param Operand The 64-bit operand to rotate right.
+ @param Count The number of bits to rotate right.
+
+ @return Operand >> Count.
+
+**/
+UINT64
+EFIAPI
+RRotU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ )
+{
+ ASSERT (Count < 64);
+ return InternalMathRRotU64 (Operand, Count);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/RShiftU64.c b/roms/edk2/MdePkg/Library/BaseLib/RShiftU64.c new file mode 100644 index 000000000..20f94f774 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/RShiftU64.c @@ -0,0 +1,35 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Shifts a 64-bit integer right between 0 and 63 bits. This high bits are
+ filled with zeros. The shifted value is returned.
+
+ This function shifts the 64-bit value Operand to the right by Count bits. The
+ high Count bits are set to zero. The shifted value is returned.
+
+ If Count is greater than 63, then ASSERT().
+
+ @param Operand The 64-bit operand to shift right.
+ @param Count The number of bits to shift right.
+
+ @return Operand >> Count.
+
+**/
+UINT64
+EFIAPI
+RShiftU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ )
+{
+ ASSERT (Count < 64);
+ return InternalMathRShiftU64 (Operand, Count);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c new file mode 100644 index 000000000..88d0877a2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c @@ -0,0 +1,27 @@ +/** @file
+ CPU breakpoint for RISC-V
+
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+extern VOID RiscVCpuBreakpoint (VOID);
+
+/**
+ Generates a breakpoint on the CPU.
+
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such
+ that code can resume normal execution after the breakpoint.
+
+**/
+VOID
+EFIAPI
+CpuBreakpoint (
+ VOID
+ )
+{
+ RiscVCpuBreakpoint ();
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/RiscV64/CpuPause.c b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/CpuPause.c new file mode 100644 index 000000000..9931bad29 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/CpuPause.c @@ -0,0 +1,29 @@ +/** @file
+ CPU pause for RISC-V
+
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+extern VOID RiscVCpuPause (VOID);
+
+
+/**
+ Requests CPU to pause for a short period of time.
+
+ Requests CPU to pause for a short period of time. Typically used in MP
+ systems to prevent memory starvation while waiting for a spin lock.
+
+**/
+VOID
+EFIAPI
+CpuPause (
+ VOID
+ )
+{
+ RiscVCpuPause ();
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c new file mode 100644 index 000000000..867086c09 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c @@ -0,0 +1,24 @@ +/** @file
+ CPU disable interrupt function for RISC-V
+
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "BaseLibInternals.h"
+
+extern VOID RiscVDisableSupervisorModeInterrupts (VOID);
+
+/**
+ Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+DisableInterrupts (
+ VOID
+ )
+{
+ RiscVDisableSupervisorModeInterrupts ();
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c new file mode 100644 index 000000000..22ef73067 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c @@ -0,0 +1,25 @@ +/** @file
+ CPU enable interrupt function for RISC-V
+
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+extern VOID RiscVEnableSupervisorModeInterrupt (VOID);
+
+/**
+ Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+EnableInterrupts (
+ VOID
+ )
+{
+ RiscVEnableSupervisorModeInterrupt ();
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/FlushCache.S new file mode 100644 index 000000000..7c10fdd26 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/FlushCache.S @@ -0,0 +1,21 @@ +//------------------------------------------------------------------------------
+//
+// RISC-V cache operation.
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+.align 3
+ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
+
+ASM_PFX(RiscVInvalidateInstCacheAsm):
+ fence.i
+ ret
+
+ASM_PFX(RiscVInvalidateDataCacheAsm):
+ fence
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c new file mode 100644 index 000000000..292f1ec44 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c @@ -0,0 +1,35 @@ +/** @file
+ CPU get interrupt state function for RISC-V
+
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+extern UINT32 RiscVGetSupervisorModeInterrupts (VOID);
+
+/**
+ Retrieves the current CPU interrupt state.
+
+ Returns TRUE is interrupts are currently enabled. Otherwise
+ returns FALSE.
+
+ @retval TRUE CPU interrupts are enabled.
+ @retval FALSE CPU interrupts are disabled.
+
+**/
+BOOLEAN
+EFIAPI
+GetInterruptState (
+ VOID
+ )
+{
+ unsigned long RetValue;
+
+ RetValue = RiscVGetSupervisorModeInterrupts ();
+ return RetValue? TRUE: FALSE;
+}
+
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c new file mode 100644 index 000000000..0bb292141 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c @@ -0,0 +1,55 @@ +/** @file
+ Switch stack function for RISC-V
+
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Transfers control to a function starting with a new stack.
+
+ Transfers control to the function specified by EntryPoint using the
+ new stack specified by NewStack and passing in the parameters specified
+ by Context1 and Context2. Context1 and Context2 are optional and may
+ be NULL. The function EntryPoint must never return.
+ Marker will be ignored on IA-32, x64, and EBC.
+ IPF CPUs expect one additional parameter of type VOID * that specifies
+ the new backing store pointer.
+
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ @param EntryPoint A pointer to function to call with the new stack.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function.
+ @param Marker VA_LIST marker for the variable argument list.
+
+**/
+VOID
+EFIAPI
+InternalSwitchStack (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack,
+ IN VA_LIST Marker
+ )
+{
+ BASE_LIBRARY_JUMP_BUFFER JumpBuffer;
+
+ DEBUG ((DEBUG_INFO, "RISC-V InternalSwitchStack Entry:%x Context1:%x Context2:%x NewStack%x\n", \
+ EntryPoint, Context1, Context2, NewStack));
+ JumpBuffer.RA = (UINTN)EntryPoint;
+ JumpBuffer.SP = (UINTN)NewStack - sizeof (VOID *);
+ JumpBuffer.S0 = (UINT64)(UINTN)Context1;
+ JumpBuffer.S1 = (UINT64)(UINTN)Context2;
+ LongJump (&JumpBuffer, (UINTN)-1);
+ ASSERT(FALSE);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S new file mode 100644 index 000000000..ccf91df81 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S @@ -0,0 +1,14 @@ +//------------------------------------------------------------------------------
+//
+// CpuBreakpoint for RISC-V
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(RiscVCpuBreakpoint)
+ASM_PFX(RiscVCpuBreakpoint):
+ ebreak
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S new file mode 100644 index 000000000..6660c2fcb --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S @@ -0,0 +1,14 @@ +//------------------------------------------------------------------------------
+//
+// CpuPause for RISC-V
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(RiscVCpuPause)
+ASM_PFX(RiscVCpuPause):
+ nop
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S new file mode 100644 index 000000000..87b3468fc --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S @@ -0,0 +1,63 @@ +//------------------------------------------------------------------------------
+//
+// RISC-V Supervisor Mode interrupt enable/disable
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts)
+ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt)
+ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts)
+
+#define SSTATUS_SIE 0x00000002
+#define CSR_SSTATUS 0x100
+ #define SSTATUS_SPP_BIT_POSITION 8
+
+//
+// This routine disables supervisor mode interrupt
+//
+ASM_PFX(RiscVDisableSupervisorModeInterrupts):
+ add sp, sp, -(__SIZEOF_POINTER__)
+ sd a1, (sp)
+ li a1, SSTATUS_SIE
+ csrc CSR_SSTATUS, a1
+ ld a1, (sp)
+ add sp, sp, (__SIZEOF_POINTER__)
+ ret
+
+//
+// This routine enables supervisor mode interrupt
+//
+ASM_PFX(RiscVEnableSupervisorModeInterrupt):
+ add sp, sp, -2*(__SIZEOF_POINTER__)
+ sd a0, (0*__SIZEOF_POINTER__)(sp)
+ sd a1, (1*__SIZEOF_POINTER__)(sp)
+
+ csrr a0, CSR_SSTATUS
+ and a0, a0, (1 << SSTATUS_SPP_BIT_POSITION)
+ bnez a0, InTrap // We are in supervisor mode (SMode)
+ // trap handler.
+ // Skip enabling SIE becasue SIE
+ // is set to disabled by RISC-V hart
+ // when the trap takes hart to SMode.
+
+ li a1, SSTATUS_SIE
+ csrs CSR_SSTATUS, a1
+InTrap:
+ ld a0, (0*__SIZEOF_POINTER__)(sp)
+ ld a1, (1*__SIZEOF_POINTER__)(sp)
+ add sp, sp, 2*(__SIZEOF_POINTER__)
+ ret
+
+//
+// This routine returns supervisor mode interrupt
+// status.
+//
+ASM_PFX(RiscVGetSupervisorModeInterrupts):
+ csrr a0, CSR_SSTATUS
+ andi a0, a0, SSTATUS_SIE
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S new file mode 100644 index 000000000..34486eabb --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S @@ -0,0 +1,55 @@ +//------------------------------------------------------------------------------
+//
+// Set/Long jump for RISC-V
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+# define REG_S sd
+# define REG_L ld
+# define SZREG 8
+.align 3
+ .globl SetJump
+
+SetJump:
+ REG_S ra, 0*SZREG(a0)
+ REG_S s0, 1*SZREG(a0)
+ REG_S s1, 2*SZREG(a0)
+ REG_S s2, 3*SZREG(a0)
+ REG_S s3, 4*SZREG(a0)
+ REG_S s4, 5*SZREG(a0)
+ REG_S s5, 6*SZREG(a0)
+ REG_S s6, 7*SZREG(a0)
+ REG_S s7, 8*SZREG(a0)
+ REG_S s8, 9*SZREG(a0)
+ REG_S s9, 10*SZREG(a0)
+ REG_S s10, 11*SZREG(a0)
+ REG_S s11, 12*SZREG(a0)
+ REG_S sp, 13*SZREG(a0)
+ li a0, 0
+ ret
+
+ .globl InternalLongJump
+InternalLongJump:
+ REG_L ra, 0*SZREG(a0)
+ REG_L s0, 1*SZREG(a0)
+ REG_L s1, 2*SZREG(a0)
+ REG_L s2, 3*SZREG(a0)
+ REG_L s3, 4*SZREG(a0)
+ REG_L s4, 5*SZREG(a0)
+ REG_L s5, 6*SZREG(a0)
+ REG_L s6, 7*SZREG(a0)
+ REG_L s7, 8*SZREG(a0)
+ REG_L s8, 9*SZREG(a0)
+ REG_L s9, 10*SZREG(a0)
+ REG_L s10, 11*SZREG(a0)
+ REG_L s11, 12*SZREG(a0)
+ REG_L sp, 13*SZREG(a0)
+
+ add a0, s0, 0
+ add a1, s1, 0
+ add a2, s2, 0
+ add a3, s3, 0
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/SafeString.c b/roms/edk2/MdePkg/Library/BaseLib/SafeString.c new file mode 100644 index 000000000..3bb23ca1a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/SafeString.c @@ -0,0 +1,3535 @@ +/** @file
+ Safe String functions.
+
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+#define RSIZE_MAX (PcdGet32 (PcdMaximumUnicodeStringLength))
+
+#define ASCII_RSIZE_MAX (PcdGet32 (PcdMaximumAsciiStringLength))
+
+#define SAFE_STRING_CONSTRAINT_CHECK(Expression, Status) \
+ do { \
+ if (!(Expression)) { \
+ DEBUG ((DEBUG_VERBOSE, \
+ "%a(%d) %a: SAFE_STRING_CONSTRAINT_CHECK(%a) failed. Return %r\n", \
+ __FILE__, __LINE__, __FUNCTION__, #Expression, Status)); \
+ return Status; \
+ } \
+ } while (FALSE)
+
+/**
+ Returns if 2 memory blocks are overlapped.
+
+ @param Base1 Base address of 1st memory block.
+ @param Size1 Size of 1st memory block.
+ @param Base2 Base address of 2nd memory block.
+ @param Size2 Size of 2nd memory block.
+
+ @retval TRUE 2 memory blocks are overlapped.
+ @retval FALSE 2 memory blocks are not overlapped.
+**/
+BOOLEAN
+InternalSafeStringIsOverlap (
+ IN VOID *Base1,
+ IN UINTN Size1,
+ IN VOID *Base2,
+ IN UINTN Size2
+ )
+{
+ if ((((UINTN)Base1 >= (UINTN)Base2) && ((UINTN)Base1 < (UINTN)Base2 + Size2)) ||
+ (((UINTN)Base2 >= (UINTN)Base1) && ((UINTN)Base2 < (UINTN)Base1 + Size1))) {
+ return TRUE;
+ }
+ return FALSE;
+}
+
+/**
+ Returns if 2 Unicode strings are not overlapped.
+
+ @param Str1 Start address of 1st Unicode string.
+ @param Size1 The number of char in 1st Unicode string,
+ including terminating null char.
+ @param Str2 Start address of 2nd Unicode string.
+ @param Size2 The number of char in 2nd Unicode string,
+ including terminating null char.
+
+ @retval TRUE 2 Unicode strings are NOT overlapped.
+ @retval FALSE 2 Unicode strings are overlapped.
+**/
+BOOLEAN
+InternalSafeStringNoStrOverlap (
+ IN CHAR16 *Str1,
+ IN UINTN Size1,
+ IN CHAR16 *Str2,
+ IN UINTN Size2
+ )
+{
+ return !InternalSafeStringIsOverlap (Str1, Size1 * sizeof(CHAR16), Str2, Size2 * sizeof(CHAR16));
+}
+
+/**
+ Returns if 2 Ascii strings are not overlapped.
+
+ @param Str1 Start address of 1st Ascii string.
+ @param Size1 The number of char in 1st Ascii string,
+ including terminating null char.
+ @param Str2 Start address of 2nd Ascii string.
+ @param Size2 The number of char in 2nd Ascii string,
+ including terminating null char.
+
+ @retval TRUE 2 Ascii strings are NOT overlapped.
+ @retval FALSE 2 Ascii strings are overlapped.
+**/
+BOOLEAN
+InternalSafeStringNoAsciiStrOverlap (
+ IN CHAR8 *Str1,
+ IN UINTN Size1,
+ IN CHAR8 *Str2,
+ IN UINTN Size2
+ )
+{
+ return !InternalSafeStringIsOverlap (Str1, Size1, Str2, Size2);
+}
+
+/**
+ Returns the length of a Null-terminated Unicode string.
+
+ This function is similar as strlen_s defined in C11.
+
+ If String is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param String A pointer to a Null-terminated Unicode string.
+ @param MaxSize The maximum number of Destination Unicode
+ char, including terminating null char.
+
+ @retval 0 If String is NULL.
+ @retval MaxSize If there is no null character in the first MaxSize characters of String.
+ @return The number of characters that percede the terminating null character.
+
+**/
+UINTN
+EFIAPI
+StrnLenS (
+ IN CONST CHAR16 *String,
+ IN UINTN MaxSize
+ )
+{
+ UINTN Length;
+
+ ASSERT (((UINTN) String & BIT0) == 0);
+
+ //
+ // If String is a null pointer or MaxSize is 0, then the StrnLenS function returns zero.
+ //
+ if ((String == NULL) || (MaxSize == 0)) {
+ return 0;
+ }
+
+ //
+ // Otherwise, the StrnLenS function returns the number of characters that precede the
+ // terminating null character. If there is no null character in the first MaxSize characters of
+ // String then StrnLenS returns MaxSize. At most the first MaxSize characters of String shall
+ // be accessed by StrnLenS.
+ //
+ Length = 0;
+ while (String[Length] != 0) {
+ if (Length >= MaxSize - 1) {
+ return MaxSize;
+ }
+ Length++;
+ }
+ return Length;
+}
+
+/**
+ Returns the size of a Null-terminated Unicode string in bytes, including the
+ Null terminator.
+
+ This function returns the size of the Null-terminated Unicode string
+ specified by String in bytes, including the Null terminator.
+
+ If String is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param String A pointer to a Null-terminated Unicode string.
+ @param MaxSize The maximum number of Destination Unicode
+ char, including the Null terminator.
+
+ @retval 0 If String is NULL.
+ @retval (sizeof (CHAR16) * (MaxSize + 1))
+ If there is no Null terminator in the first MaxSize characters of
+ String.
+ @return The size of the Null-terminated Unicode string in bytes, including
+ the Null terminator.
+
+**/
+UINTN
+EFIAPI
+StrnSizeS (
+ IN CONST CHAR16 *String,
+ IN UINTN MaxSize
+ )
+{
+ //
+ // If String is a null pointer, then the StrnSizeS function returns zero.
+ //
+ if (String == NULL) {
+ return 0;
+ }
+
+ //
+ // Otherwise, the StrnSizeS function returns the size of the Null-terminated
+ // Unicode string in bytes, including the Null terminator. If there is no
+ // Null terminator in the first MaxSize characters of String, then StrnSizeS
+ // returns (sizeof (CHAR16) * (MaxSize + 1)) to keep a consistent map with
+ // the StrnLenS function.
+ //
+ return (StrnLenS (String, MaxSize) + 1) * sizeof (*String);
+}
+
+/**
+ Copies the string pointed to by Source (including the terminating null char)
+ to the array pointed to by Destination.
+
+ This function is similar as strcpy_s defined in C11.
+
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().
+ If Source is not aligned on a 16-bit boundary, then ASSERT().
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Destination A pointer to a Null-terminated Unicode string.
+ @param DestMax The maximum number of Destination Unicode
+ char, including terminating null char.
+ @param Source A pointer to a Null-terminated Unicode string.
+
+ @retval RETURN_SUCCESS String is copied.
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than StrLen(Source).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumUnicodeStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumUnicodeStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+**/
+RETURN_STATUS
+EFIAPI
+StrCpyS (
+ OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR16 *Source
+ )
+{
+ UINTN SourceLen;
+
+ ASSERT (((UINTN) Destination & BIT0) == 0);
+ ASSERT (((UINTN) Source & BIT0) == 0);
+
+ //
+ // 1. Neither Destination nor Source shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((Destination != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Source != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. DestMax shall not be greater than RSIZE_MAX.
+ //
+ if (RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ //
+ // 3. DestMax shall not equal zero.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax != 0), RETURN_INVALID_PARAMETER);
+
+ //
+ // 4. DestMax shall be greater than StrnLenS(Source, DestMax).
+ //
+ SourceLen = StrnLenS (Source, DestMax);
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax > SourceLen), RETURN_BUFFER_TOO_SMALL);
+
+ //
+ // 5. Copying shall not take place between objects that overlap.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK (InternalSafeStringNoStrOverlap (Destination, DestMax, (CHAR16 *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
+
+ //
+ // The StrCpyS function copies the string pointed to by Source (including the terminating
+ // null character) into the array pointed to by Destination.
+ //
+ while (*Source != 0) {
+ *(Destination++) = *(Source++);
+ }
+ *Destination = 0;
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Copies not more than Length successive char from the string pointed to by
+ Source to the array pointed to by Destination. If no null char is copied from
+ Source, then Destination[Length] is always set to null.
+
+ This function is similar as strncpy_s defined in C11.
+
+ If Length > 0 and Destination is not aligned on a 16-bit boundary, then ASSERT().
+ If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT().
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Destination A pointer to a Null-terminated Unicode string.
+ @param DestMax The maximum number of Destination Unicode
+ char, including terminating null char.
+ @param Source A pointer to a Null-terminated Unicode string.
+ @param Length The maximum number of Unicode characters to copy.
+
+ @retval RETURN_SUCCESS String is copied.
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than
+ MIN(StrLen(Source), Length).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumUnicodeStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumUnicodeStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+**/
+RETURN_STATUS
+EFIAPI
+StrnCpyS (
+ OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR16 *Source,
+ IN UINTN Length
+ )
+{
+ UINTN SourceLen;
+
+ ASSERT (((UINTN) Destination & BIT0) == 0);
+ ASSERT (((UINTN) Source & BIT0) == 0);
+
+ //
+ // 1. Neither Destination nor Source shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((Destination != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Source != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. Neither DestMax nor Length shall be greater than RSIZE_MAX
+ //
+ if (RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Length <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ //
+ // 3. DestMax shall not equal zero.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax != 0), RETURN_INVALID_PARAMETER);
+
+ //
+ // 4. If Length is not less than DestMax, then DestMax shall be greater than StrnLenS(Source, DestMax).
+ //
+ SourceLen = StrnLenS (Source, MIN (DestMax, Length));
+ if (Length >= DestMax) {
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax > SourceLen), RETURN_BUFFER_TOO_SMALL);
+ }
+
+ //
+ // 5. Copying shall not take place between objects that overlap.
+ //
+ if (SourceLen > Length) {
+ SourceLen = Length;
+ }
+ SAFE_STRING_CONSTRAINT_CHECK (InternalSafeStringNoStrOverlap (Destination, DestMax, (CHAR16 *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
+
+ //
+ // The StrnCpyS function copies not more than Length successive characters (characters that
+ // follow a null character are not copied) from the array pointed to by Source to the array
+ // pointed to by Destination. If no null character was copied from Source, then Destination[Length] is set to a null
+ // character.
+ //
+ while ((SourceLen > 0) && (*Source != 0)) {
+ *(Destination++) = *(Source++);
+ SourceLen--;
+ }
+ *Destination = 0;
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Appends a copy of the string pointed to by Source (including the terminating
+ null char) to the end of the string pointed to by Destination.
+
+ This function is similar as strcat_s defined in C11.
+
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().
+ If Source is not aligned on a 16-bit boundary, then ASSERT().
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Destination A pointer to a Null-terminated Unicode string.
+ @param DestMax The maximum number of Destination Unicode
+ char, including terminating null char.
+ @param Source A pointer to a Null-terminated Unicode string.
+
+ @retval RETURN_SUCCESS String is appended.
+ @retval RETURN_BAD_BUFFER_SIZE If DestMax is NOT greater than
+ StrLen(Destination).
+ @retval RETURN_BUFFER_TOO_SMALL If (DestMax - StrLen(Destination)) is NOT
+ greater than StrLen(Source).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumUnicodeStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumUnicodeStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+**/
+RETURN_STATUS
+EFIAPI
+StrCatS (
+ IN OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR16 *Source
+ )
+{
+ UINTN DestLen;
+ UINTN CopyLen;
+ UINTN SourceLen;
+
+ ASSERT (((UINTN) Destination & BIT0) == 0);
+ ASSERT (((UINTN) Source & BIT0) == 0);
+
+ //
+ // Let CopyLen denote the value DestMax - StrnLenS(Destination, DestMax) upon entry to StrCatS.
+ //
+ DestLen = StrnLenS (Destination, DestMax);
+ CopyLen = DestMax - DestLen;
+
+ //
+ // 1. Neither Destination nor Source shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((Destination != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Source != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. DestMax shall not be greater than RSIZE_MAX.
+ //
+ if (RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ //
+ // 3. DestMax shall not equal zero.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax != 0), RETURN_INVALID_PARAMETER);
+
+ //
+ // 4. CopyLen shall not equal zero.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((CopyLen != 0), RETURN_BAD_BUFFER_SIZE);
+
+ //
+ // 5. CopyLen shall be greater than StrnLenS(Source, CopyLen).
+ //
+ SourceLen = StrnLenS (Source, CopyLen);
+ SAFE_STRING_CONSTRAINT_CHECK ((CopyLen > SourceLen), RETURN_BUFFER_TOO_SMALL);
+
+ //
+ // 6. Copying shall not take place between objects that overlap.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK (InternalSafeStringNoStrOverlap (Destination, DestMax, (CHAR16 *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
+
+ //
+ // The StrCatS function appends a copy of the string pointed to by Source (including the
+ // terminating null character) to the end of the string pointed to by Destination. The initial character
+ // from Source overwrites the null character at the end of Destination.
+ //
+ Destination = Destination + DestLen;
+ while (*Source != 0) {
+ *(Destination++) = *(Source++);
+ }
+ *Destination = 0;
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Appends not more than Length successive char from the string pointed to by
+ Source to the end of the string pointed to by Destination. If no null char is
+ copied from Source, then Destination[StrLen(Destination) + Length] is always
+ set to null.
+
+ This function is similar as strncat_s defined in C11.
+
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().
+ If Source is not aligned on a 16-bit boundary, then ASSERT().
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Destination A pointer to a Null-terminated Unicode string.
+ @param DestMax The maximum number of Destination Unicode
+ char, including terminating null char.
+ @param Source A pointer to a Null-terminated Unicode string.
+ @param Length The maximum number of Unicode characters to copy.
+
+ @retval RETURN_SUCCESS String is appended.
+ @retval RETURN_BAD_BUFFER_SIZE If DestMax is NOT greater than
+ StrLen(Destination).
+ @retval RETURN_BUFFER_TOO_SMALL If (DestMax - StrLen(Destination)) is NOT
+ greater than MIN(StrLen(Source), Length).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumUnicodeStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumUnicodeStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+**/
+RETURN_STATUS
+EFIAPI
+StrnCatS (
+ IN OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR16 *Source,
+ IN UINTN Length
+ )
+{
+ UINTN DestLen;
+ UINTN CopyLen;
+ UINTN SourceLen;
+
+ ASSERT (((UINTN) Destination & BIT0) == 0);
+ ASSERT (((UINTN) Source & BIT0) == 0);
+
+ //
+ // Let CopyLen denote the value DestMax - StrnLenS(Destination, DestMax) upon entry to StrnCatS.
+ //
+ DestLen = StrnLenS (Destination, DestMax);
+ CopyLen = DestMax - DestLen;
+
+ //
+ // 1. Neither Destination nor Source shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((Destination != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Source != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. Neither DestMax nor Length shall be greater than RSIZE_MAX.
+ //
+ if (RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Length <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ //
+ // 3. DestMax shall not equal zero.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax != 0), RETURN_INVALID_PARAMETER);
+
+ //
+ // 4. CopyLen shall not equal zero.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((CopyLen != 0), RETURN_BAD_BUFFER_SIZE);
+
+ //
+ // 5. If Length is not less than CopyLen, then CopyLen shall be greater than StrnLenS(Source, CopyLen).
+ //
+ SourceLen = StrnLenS (Source, MIN (CopyLen, Length));
+ if (Length >= CopyLen) {
+ SAFE_STRING_CONSTRAINT_CHECK ((CopyLen > SourceLen), RETURN_BUFFER_TOO_SMALL);
+ }
+
+ //
+ // 6. Copying shall not take place between objects that overlap.
+ //
+ if (SourceLen > Length) {
+ SourceLen = Length;
+ }
+ SAFE_STRING_CONSTRAINT_CHECK (InternalSafeStringNoStrOverlap (Destination, DestMax, (CHAR16 *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
+
+ //
+ // The StrnCatS function appends not more than Length successive characters (characters
+ // that follow a null character are not copied) from the array pointed to by Source to the end of
+ // the string pointed to by Destination. The initial character from Source overwrites the null character at
+ // the end of Destination. If no null character was copied from Source, then Destination[DestMax-CopyLen+Length] is set to
+ // a null character.
+ //
+ Destination = Destination + DestLen;
+ while ((SourceLen > 0) && (*Source != 0)) {
+ *(Destination++) = *(Source++);
+ SourceLen--;
+ }
+ *Destination = 0;
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated Unicode decimal string to a value of type UINTN.
+
+ This function outputs a value of type UINTN by interpreting the contents of
+ the Unicode string specified by String as a decimal number. The format of the
+ input Unicode string String is:
+
+ [spaces] [decimal digits].
+
+ The valid decimal digit character is in the range [0-9]. The function will
+ ignore the pad space, which includes spaces or tab characters, before
+ [decimal digits]. The running zero in the beginning of [decimal digits] will
+ be ignored. Then, the function stops at the first character that is a not a
+ valid decimal character or a Null-terminator, whichever one comes first.
+
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+
+ If String has no valid decimal digits in the above format, then 0 is stored
+ at the location pointed to by Data.
+ If the number represented by String exceeds the range defined by UINTN, then
+ MAX_UINTN is stored at the location pointed to by Data.
+
+ If EndPointer is not NULL, a pointer to the character that stopped the scan
+ is stored at the location pointed to by EndPointer. If String has no valid
+ decimal digits right after the optional pad spaces, the value of String is
+ stored at the location pointed to by EndPointer.
+
+ @param String Pointer to a Null-terminated Unicode string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Data Pointer to the converted value.
+
+ @retval RETURN_SUCCESS Value is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If PcdMaximumUnicodeStringLength is not
+ zero, and String contains more than
+ PcdMaximumUnicodeStringLength Unicode
+ characters, not including the
+ Null-terminator.
+ @retval RETURN_UNSUPPORTED If the number represented by String exceeds
+ the range defined by UINTN.
+
+**/
+RETURN_STATUS
+EFIAPI
+StrDecimalToUintnS (
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer, OPTIONAL
+ OUT UINTN *Data
+ )
+{
+ ASSERT (((UINTN) String & BIT0) == 0);
+
+ //
+ // 1. Neither String nor Data shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Data != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. The length of String shall not be greater than RSIZE_MAX.
+ //
+ if (RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((StrnLenS (String, RSIZE_MAX + 1) <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR16 *) String;
+ }
+
+ //
+ // Ignore the pad spaces (space or tab)
+ //
+ while ((*String == L' ') || (*String == L'\t')) {
+ String++;
+ }
+
+ //
+ // Ignore leading Zeros after the spaces
+ //
+ while (*String == L'0') {
+ String++;
+ }
+
+ *Data = 0;
+
+ while (InternalIsDecimalDigitCharacter (*String)) {
+ //
+ // If the number represented by String overflows according to the range
+ // defined by UINTN, then MAX_UINTN is stored in *Data and
+ // RETURN_UNSUPPORTED is returned.
+ //
+ if (*Data > ((MAX_UINTN - (*String - L'0')) / 10)) {
+ *Data = MAX_UINTN;
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR16 *) String;
+ }
+ return RETURN_UNSUPPORTED;
+ }
+
+ *Data = *Data * 10 + (*String - L'0');
+ String++;
+ }
+
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR16 *) String;
+ }
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated Unicode decimal string to a value of type UINT64.
+
+ This function outputs a value of type UINT64 by interpreting the contents of
+ the Unicode string specified by String as a decimal number. The format of the
+ input Unicode string String is:
+
+ [spaces] [decimal digits].
+
+ The valid decimal digit character is in the range [0-9]. The function will
+ ignore the pad space, which includes spaces or tab characters, before
+ [decimal digits]. The running zero in the beginning of [decimal digits] will
+ be ignored. Then, the function stops at the first character that is a not a
+ valid decimal character or a Null-terminator, whichever one comes first.
+
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+
+ If String has no valid decimal digits in the above format, then 0 is stored
+ at the location pointed to by Data.
+ If the number represented by String exceeds the range defined by UINT64, then
+ MAX_UINT64 is stored at the location pointed to by Data.
+
+ If EndPointer is not NULL, a pointer to the character that stopped the scan
+ is stored at the location pointed to by EndPointer. If String has no valid
+ decimal digits right after the optional pad spaces, the value of String is
+ stored at the location pointed to by EndPointer.
+
+ @param String Pointer to a Null-terminated Unicode string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Data Pointer to the converted value.
+
+ @retval RETURN_SUCCESS Value is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If PcdMaximumUnicodeStringLength is not
+ zero, and String contains more than
+ PcdMaximumUnicodeStringLength Unicode
+ characters, not including the
+ Null-terminator.
+ @retval RETURN_UNSUPPORTED If the number represented by String exceeds
+ the range defined by UINT64.
+
+**/
+RETURN_STATUS
+EFIAPI
+StrDecimalToUint64S (
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer, OPTIONAL
+ OUT UINT64 *Data
+ )
+{
+ ASSERT (((UINTN) String & BIT0) == 0);
+
+ //
+ // 1. Neither String nor Data shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Data != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. The length of String shall not be greater than RSIZE_MAX.
+ //
+ if (RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((StrnLenS (String, RSIZE_MAX + 1) <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR16 *) String;
+ }
+
+ //
+ // Ignore the pad spaces (space or tab)
+ //
+ while ((*String == L' ') || (*String == L'\t')) {
+ String++;
+ }
+
+ //
+ // Ignore leading Zeros after the spaces
+ //
+ while (*String == L'0') {
+ String++;
+ }
+
+ *Data = 0;
+
+ while (InternalIsDecimalDigitCharacter (*String)) {
+ //
+ // If the number represented by String overflows according to the range
+ // defined by UINT64, then MAX_UINT64 is stored in *Data and
+ // RETURN_UNSUPPORTED is returned.
+ //
+ if (*Data > DivU64x32 (MAX_UINT64 - (*String - L'0'), 10)) {
+ *Data = MAX_UINT64;
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR16 *) String;
+ }
+ return RETURN_UNSUPPORTED;
+ }
+
+ *Data = MultU64x32 (*Data, 10) + (*String - L'0');
+ String++;
+ }
+
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR16 *) String;
+ }
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated Unicode hexadecimal string to a value of type
+ UINTN.
+
+ This function outputs a value of type UINTN by interpreting the contents of
+ the Unicode string specified by String as a hexadecimal number. The format of
+ the input Unicode string String is:
+
+ [spaces][zeros][x][hexadecimal digits].
+
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix.
+ If "x" appears in the input string, it must be prefixed with at least one 0.
+ The function will ignore the pad space, which includes spaces or tab
+ characters, before [zeros], [x] or [hexadecimal digit]. The running zero
+ before [x] or [hexadecimal digit] will be ignored. Then, the decoding starts
+ after [x] or the first valid hexadecimal digit. Then, the function stops at
+ the first character that is a not a valid hexadecimal character or NULL,
+ whichever one comes first.
+
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+
+ If String has no valid hexadecimal digits in the above format, then 0 is
+ stored at the location pointed to by Data.
+ If the number represented by String exceeds the range defined by UINTN, then
+ MAX_UINTN is stored at the location pointed to by Data.
+
+ If EndPointer is not NULL, a pointer to the character that stopped the scan
+ is stored at the location pointed to by EndPointer. If String has no valid
+ hexadecimal digits right after the optional pad spaces, the value of String
+ is stored at the location pointed to by EndPointer.
+
+ @param String Pointer to a Null-terminated Unicode string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Data Pointer to the converted value.
+
+ @retval RETURN_SUCCESS Value is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If PcdMaximumUnicodeStringLength is not
+ zero, and String contains more than
+ PcdMaximumUnicodeStringLength Unicode
+ characters, not including the
+ Null-terminator.
+ @retval RETURN_UNSUPPORTED If the number represented by String exceeds
+ the range defined by UINTN.
+
+**/
+RETURN_STATUS
+EFIAPI
+StrHexToUintnS (
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer, OPTIONAL
+ OUT UINTN *Data
+ )
+{
+ ASSERT (((UINTN) String & BIT0) == 0);
+
+ //
+ // 1. Neither String nor Data shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Data != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. The length of String shall not be greater than RSIZE_MAX.
+ //
+ if (RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((StrnLenS (String, RSIZE_MAX + 1) <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR16 *) String;
+ }
+
+ //
+ // Ignore the pad spaces (space or tab)
+ //
+ while ((*String == L' ') || (*String == L'\t')) {
+ String++;
+ }
+
+ //
+ // Ignore leading Zeros after the spaces
+ //
+ while (*String == L'0') {
+ String++;
+ }
+
+ if (CharToUpper (*String) == L'X') {
+ if (*(String - 1) != L'0') {
+ *Data = 0;
+ return RETURN_SUCCESS;
+ }
+ //
+ // Skip the 'X'
+ //
+ String++;
+ }
+
+ *Data = 0;
+
+ while (InternalIsHexaDecimalDigitCharacter (*String)) {
+ //
+ // If the number represented by String overflows according to the range
+ // defined by UINTN, then MAX_UINTN is stored in *Data and
+ // RETURN_UNSUPPORTED is returned.
+ //
+ if (*Data > ((MAX_UINTN - InternalHexCharToUintn (*String)) >> 4)) {
+ *Data = MAX_UINTN;
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR16 *) String;
+ }
+ return RETURN_UNSUPPORTED;
+ }
+
+ *Data = (*Data << 4) + InternalHexCharToUintn (*String);
+ String++;
+ }
+
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR16 *) String;
+ }
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated Unicode hexadecimal string to a value of type
+ UINT64.
+
+ This function outputs a value of type UINT64 by interpreting the contents of
+ the Unicode string specified by String as a hexadecimal number. The format of
+ the input Unicode string String is:
+
+ [spaces][zeros][x][hexadecimal digits].
+
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix.
+ If "x" appears in the input string, it must be prefixed with at least one 0.
+ The function will ignore the pad space, which includes spaces or tab
+ characters, before [zeros], [x] or [hexadecimal digit]. The running zero
+ before [x] or [hexadecimal digit] will be ignored. Then, the decoding starts
+ after [x] or the first valid hexadecimal digit. Then, the function stops at
+ the first character that is a not a valid hexadecimal character or NULL,
+ whichever one comes first.
+
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+
+ If String has no valid hexadecimal digits in the above format, then 0 is
+ stored at the location pointed to by Data.
+ If the number represented by String exceeds the range defined by UINT64, then
+ MAX_UINT64 is stored at the location pointed to by Data.
+
+ If EndPointer is not NULL, a pointer to the character that stopped the scan
+ is stored at the location pointed to by EndPointer. If String has no valid
+ hexadecimal digits right after the optional pad spaces, the value of String
+ is stored at the location pointed to by EndPointer.
+
+ @param String Pointer to a Null-terminated Unicode string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Data Pointer to the converted value.
+
+ @retval RETURN_SUCCESS Value is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If PcdMaximumUnicodeStringLength is not
+ zero, and String contains more than
+ PcdMaximumUnicodeStringLength Unicode
+ characters, not including the
+ Null-terminator.
+ @retval RETURN_UNSUPPORTED If the number represented by String exceeds
+ the range defined by UINT64.
+
+**/
+RETURN_STATUS
+EFIAPI
+StrHexToUint64S (
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer, OPTIONAL
+ OUT UINT64 *Data
+ )
+{
+ ASSERT (((UINTN) String & BIT0) == 0);
+
+ //
+ // 1. Neither String nor Data shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Data != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. The length of String shall not be greater than RSIZE_MAX.
+ //
+ if (RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((StrnLenS (String, RSIZE_MAX + 1) <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR16 *) String;
+ }
+
+ //
+ // Ignore the pad spaces (space or tab)
+ //
+ while ((*String == L' ') || (*String == L'\t')) {
+ String++;
+ }
+
+ //
+ // Ignore leading Zeros after the spaces
+ //
+ while (*String == L'0') {
+ String++;
+ }
+
+ if (CharToUpper (*String) == L'X') {
+ if (*(String - 1) != L'0') {
+ *Data = 0;
+ return RETURN_SUCCESS;
+ }
+ //
+ // Skip the 'X'
+ //
+ String++;
+ }
+
+ *Data = 0;
+
+ while (InternalIsHexaDecimalDigitCharacter (*String)) {
+ //
+ // If the number represented by String overflows according to the range
+ // defined by UINT64, then MAX_UINT64 is stored in *Data and
+ // RETURN_UNSUPPORTED is returned.
+ //
+ if (*Data > RShiftU64 (MAX_UINT64 - InternalHexCharToUintn (*String), 4)) {
+ *Data = MAX_UINT64;
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR16 *) String;
+ }
+ return RETURN_UNSUPPORTED;
+ }
+
+ *Data = LShiftU64 (*Data, 4) + InternalHexCharToUintn (*String);
+ String++;
+ }
+
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR16 *) String;
+ }
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated Unicode string to IPv6 address and prefix length.
+
+ This function outputs a value of type IPv6_ADDRESS and may output a value
+ of type UINT8 by interpreting the contents of the Unicode string specified
+ by String. The format of the input Unicode string String is as follows:
+
+ X:X:X:X:X:X:X:X[/P]
+
+ X contains one to four hexadecimal digit characters in the range [0-9], [a-f] and
+ [A-F]. X is converted to a value of type UINT16, whose low byte is stored in low
+ memory address and high byte is stored in high memory address. P contains decimal
+ digit characters in the range [0-9]. The running zero in the beginning of P will
+ be ignored. /P is optional.
+
+ When /P is not in the String, the function stops at the first character that is
+ not a valid hexadecimal digit character after eight X's are converted.
+
+ When /P is in the String, the function stops at the first character that is not
+ a valid decimal digit character after P is converted.
+
+ "::" can be used to compress one or more groups of X when X contains only 0.
+ The "::" can only appear once in the String.
+
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+
+ If EndPointer is not NULL and Address is translated from String, a pointer
+ to the character that stopped the scan is stored at the location pointed to
+ by EndPointer.
+
+ @param String Pointer to a Null-terminated Unicode string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Address Pointer to the converted IPv6 address.
+ @param PrefixLength Pointer to the converted IPv6 address prefix
+ length. MAX_UINT8 is returned when /P is
+ not in the String.
+
+ @retval RETURN_SUCCESS Address is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ @retval RETURN_UNSUPPORTED If X contains more than four hexadecimal
+ digit characters.
+ If String contains "::" and number of X
+ is not less than 8.
+ If P starts with character that is not a
+ valid decimal digit character.
+ If the decimal number converted from P
+ exceeds 128.
+
+**/
+RETURN_STATUS
+EFIAPI
+StrToIpv6Address (
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer, OPTIONAL
+ OUT IPv6_ADDRESS *Address,
+ OUT UINT8 *PrefixLength OPTIONAL
+ )
+{
+ RETURN_STATUS Status;
+ UINTN AddressIndex;
+ UINTN Uintn;
+ IPv6_ADDRESS LocalAddress;
+ UINT8 LocalPrefixLength;
+ CONST CHAR16 *Pointer;
+ CHAR16 *End;
+ UINTN CompressStart;
+ BOOLEAN ExpectPrefix;
+
+ LocalPrefixLength = MAX_UINT8;
+ CompressStart = ARRAY_SIZE (Address->Addr);
+ ExpectPrefix = FALSE;
+
+ ASSERT (((UINTN) String & BIT0) == 0);
+
+ //
+ // 1. None of String or Guid shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Address != NULL), RETURN_INVALID_PARAMETER);
+
+ for (Pointer = String, AddressIndex = 0; AddressIndex < ARRAY_SIZE (Address->Addr) + 1;) {
+ if (!InternalIsHexaDecimalDigitCharacter (*Pointer)) {
+ if (*Pointer != L':') {
+ //
+ // ":" or "/" should be followed by digit characters.
+ //
+ return RETURN_UNSUPPORTED;
+ }
+
+ //
+ // Meet second ":" after previous ":" or "/"
+ // or meet first ":" in the beginning of String.
+ //
+ if (ExpectPrefix) {
+ //
+ // ":" shall not be after "/"
+ //
+ return RETURN_UNSUPPORTED;
+ }
+
+ if (CompressStart != ARRAY_SIZE (Address->Addr) || AddressIndex == ARRAY_SIZE (Address->Addr)) {
+ //
+ // "::" can only appear once.
+ // "::" can only appear when address is not full length.
+ //
+ return RETURN_UNSUPPORTED;
+ } else {
+ //
+ // Remember the start of zero compressing.
+ //
+ CompressStart = AddressIndex;
+ Pointer++;
+
+ if (CompressStart == 0) {
+ if (*Pointer != L':') {
+ //
+ // Single ":" shall not be in the beginning of String.
+ //
+ return RETURN_UNSUPPORTED;
+ }
+ Pointer++;
+ }
+ }
+ }
+
+ if (!InternalIsHexaDecimalDigitCharacter (*Pointer)) {
+ if (*Pointer == L'/') {
+ //
+ // Might be optional "/P" after "::".
+ //
+ if (CompressStart != AddressIndex) {
+ return RETURN_UNSUPPORTED;
+ }
+ } else {
+ break;
+ }
+ } else {
+ if (!ExpectPrefix) {
+ //
+ // Get X.
+ //
+ Status = StrHexToUintnS (Pointer, &End, &Uintn);
+ if (RETURN_ERROR (Status) || End - Pointer > 4) {
+ //
+ // Number of hexadecimal digit characters is no more than 4.
+ //
+ return RETURN_UNSUPPORTED;
+ }
+ Pointer = End;
+ //
+ // Uintn won't exceed MAX_UINT16 if number of hexadecimal digit characters is no more than 4.
+ //
+ ASSERT (AddressIndex + 1 < ARRAY_SIZE (Address->Addr));
+ LocalAddress.Addr[AddressIndex] = (UINT8) ((UINT16) Uintn >> 8);
+ LocalAddress.Addr[AddressIndex + 1] = (UINT8) Uintn;
+ AddressIndex += 2;
+ } else {
+ //
+ // Get P, then exit the loop.
+ //
+ Status = StrDecimalToUintnS (Pointer, &End, &Uintn);
+ if (RETURN_ERROR (Status) || End == Pointer || Uintn > 128) {
+ //
+ // Prefix length should not exceed 128.
+ //
+ return RETURN_UNSUPPORTED;
+ }
+ LocalPrefixLength = (UINT8) Uintn;
+ Pointer = End;
+ break;
+ }
+ }
+
+ //
+ // Skip ':' or "/"
+ //
+ if (*Pointer == L'/') {
+ ExpectPrefix = TRUE;
+ } else if (*Pointer == L':') {
+ if (AddressIndex == ARRAY_SIZE (Address->Addr)) {
+ //
+ // Meet additional ":" after all 8 16-bit address
+ //
+ break;
+ }
+ } else {
+ //
+ // Meet other character that is not "/" or ":" after all 8 16-bit address
+ //
+ break;
+ }
+ Pointer++;
+ }
+
+ if ((AddressIndex == ARRAY_SIZE (Address->Addr) && CompressStart != ARRAY_SIZE (Address->Addr)) ||
+ (AddressIndex != ARRAY_SIZE (Address->Addr) && CompressStart == ARRAY_SIZE (Address->Addr))
+ ) {
+ //
+ // Full length of address shall not have compressing zeros.
+ // Non-full length of address shall have compressing zeros.
+ //
+ return RETURN_UNSUPPORTED;
+ }
+ CopyMem (&Address->Addr[0], &LocalAddress.Addr[0], CompressStart);
+ ZeroMem (&Address->Addr[CompressStart], ARRAY_SIZE (Address->Addr) - AddressIndex);
+ if (AddressIndex > CompressStart) {
+ CopyMem (
+ &Address->Addr[CompressStart + ARRAY_SIZE (Address->Addr) - AddressIndex],
+ &LocalAddress.Addr[CompressStart],
+ AddressIndex - CompressStart
+ );
+ }
+
+ if (PrefixLength != NULL) {
+ *PrefixLength = LocalPrefixLength;
+ }
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR16 *) Pointer;
+ }
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated Unicode string to IPv4 address and prefix length.
+
+ This function outputs a value of type IPv4_ADDRESS and may output a value
+ of type UINT8 by interpreting the contents of the Unicode string specified
+ by String. The format of the input Unicode string String is as follows:
+
+ D.D.D.D[/P]
+
+ D and P are decimal digit characters in the range [0-9]. The running zero in
+ the beginning of D and P will be ignored. /P is optional.
+
+ When /P is not in the String, the function stops at the first character that is
+ not a valid decimal digit character after four D's are converted.
+
+ When /P is in the String, the function stops at the first character that is not
+ a valid decimal digit character after P is converted.
+
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+
+ If EndPointer is not NULL and Address is translated from String, a pointer
+ to the character that stopped the scan is stored at the location pointed to
+ by EndPointer.
+
+ @param String Pointer to a Null-terminated Unicode string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Address Pointer to the converted IPv4 address.
+ @param PrefixLength Pointer to the converted IPv4 address prefix
+ length. MAX_UINT8 is returned when /P is
+ not in the String.
+
+ @retval RETURN_SUCCESS Address is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ @retval RETURN_UNSUPPORTED If String is not in the correct format.
+ If any decimal number converted from D
+ exceeds 255.
+ If the decimal number converted from P
+ exceeds 32.
+
+**/
+RETURN_STATUS
+EFIAPI
+StrToIpv4Address (
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer, OPTIONAL
+ OUT IPv4_ADDRESS *Address,
+ OUT UINT8 *PrefixLength OPTIONAL
+ )
+{
+ RETURN_STATUS Status;
+ UINTN AddressIndex;
+ UINTN Uintn;
+ IPv4_ADDRESS LocalAddress;
+ UINT8 LocalPrefixLength;
+ CHAR16 *Pointer;
+
+ LocalPrefixLength = MAX_UINT8;
+
+ ASSERT (((UINTN) String & BIT0) == 0);
+
+ //
+ // 1. None of String or Guid shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Address != NULL), RETURN_INVALID_PARAMETER);
+
+ for (Pointer = (CHAR16 *) String, AddressIndex = 0; AddressIndex < ARRAY_SIZE (Address->Addr) + 1;) {
+ if (!InternalIsDecimalDigitCharacter (*Pointer)) {
+ //
+ // D or P contains invalid characters.
+ //
+ break;
+ }
+
+ //
+ // Get D or P.
+ //
+ Status = StrDecimalToUintnS ((CONST CHAR16 *) Pointer, &Pointer, &Uintn);
+ if (RETURN_ERROR (Status)) {
+ return RETURN_UNSUPPORTED;
+ }
+ if (AddressIndex == ARRAY_SIZE (Address->Addr)) {
+ //
+ // It's P.
+ //
+ if (Uintn > 32) {
+ return RETURN_UNSUPPORTED;
+ }
+ LocalPrefixLength = (UINT8) Uintn;
+ } else {
+ //
+ // It's D.
+ //
+ if (Uintn > MAX_UINT8) {
+ return RETURN_UNSUPPORTED;
+ }
+ LocalAddress.Addr[AddressIndex] = (UINT8) Uintn;
+ AddressIndex++;
+ }
+
+ //
+ // Check the '.' or '/', depending on the AddressIndex.
+ //
+ if (AddressIndex == ARRAY_SIZE (Address->Addr)) {
+ if (*Pointer == L'/') {
+ //
+ // '/P' is in the String.
+ // Skip "/" and get P in next loop.
+ //
+ Pointer++;
+ } else {
+ //
+ // '/P' is not in the String.
+ //
+ break;
+ }
+ } else if (AddressIndex < ARRAY_SIZE (Address->Addr)) {
+ if (*Pointer == L'.') {
+ //
+ // D should be followed by '.'
+ //
+ Pointer++;
+ } else {
+ return RETURN_UNSUPPORTED;
+ }
+ }
+ }
+
+ if (AddressIndex < ARRAY_SIZE (Address->Addr)) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ CopyMem (Address, &LocalAddress, sizeof (*Address));
+ if (PrefixLength != NULL) {
+ *PrefixLength = LocalPrefixLength;
+ }
+ if (EndPointer != NULL) {
+ *EndPointer = Pointer;
+ }
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated Unicode GUID string to a value of type
+ EFI_GUID.
+
+ This function outputs a GUID value by interpreting the contents of
+ the Unicode string specified by String. The format of the input
+ Unicode string String consists of 36 characters, as follows:
+
+ aabbccdd-eeff-gghh-iijj-kkllmmnnoopp
+
+ The pairs aa - pp are two characters in the range [0-9], [a-f] and
+ [A-F], with each pair representing a single byte hexadecimal value.
+
+ The mapping between String and the EFI_GUID structure is as follows:
+ aa Data1[24:31]
+ bb Data1[16:23]
+ cc Data1[8:15]
+ dd Data1[0:7]
+ ee Data2[8:15]
+ ff Data2[0:7]
+ gg Data3[8:15]
+ hh Data3[0:7]
+ ii Data4[0:7]
+ jj Data4[8:15]
+ kk Data4[16:23]
+ ll Data4[24:31]
+ mm Data4[32:39]
+ nn Data4[40:47]
+ oo Data4[48:55]
+ pp Data4[56:63]
+
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+
+ @param String Pointer to a Null-terminated Unicode string.
+ @param Guid Pointer to the converted GUID.
+
+ @retval RETURN_SUCCESS Guid is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ @retval RETURN_UNSUPPORTED If String is not as the above format.
+
+**/
+RETURN_STATUS
+EFIAPI
+StrToGuid (
+ IN CONST CHAR16 *String,
+ OUT GUID *Guid
+ )
+{
+ RETURN_STATUS Status;
+ GUID LocalGuid;
+
+ ASSERT (((UINTN) String & BIT0) == 0);
+
+ //
+ // 1. None of String or Guid shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Guid != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // Get aabbccdd in big-endian.
+ //
+ Status = StrHexToBytes (String, 2 * sizeof (LocalGuid.Data1), (UINT8 *) &LocalGuid.Data1, sizeof (LocalGuid.Data1));
+ if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data1)] != L'-') {
+ return RETURN_UNSUPPORTED;
+ }
+ //
+ // Convert big-endian to little-endian.
+ //
+ LocalGuid.Data1 = SwapBytes32 (LocalGuid.Data1);
+ String += 2 * sizeof (LocalGuid.Data1) + 1;
+
+ //
+ // Get eeff in big-endian.
+ //
+ Status = StrHexToBytes (String, 2 * sizeof (LocalGuid.Data2), (UINT8 *) &LocalGuid.Data2, sizeof (LocalGuid.Data2));
+ if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data2)] != L'-') {
+ return RETURN_UNSUPPORTED;
+ }
+ //
+ // Convert big-endian to little-endian.
+ //
+ LocalGuid.Data2 = SwapBytes16 (LocalGuid.Data2);
+ String += 2 * sizeof (LocalGuid.Data2) + 1;
+
+ //
+ // Get gghh in big-endian.
+ //
+ Status = StrHexToBytes (String, 2 * sizeof (LocalGuid.Data3), (UINT8 *) &LocalGuid.Data3, sizeof (LocalGuid.Data3));
+ if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data3)] != L'-') {
+ return RETURN_UNSUPPORTED;
+ }
+ //
+ // Convert big-endian to little-endian.
+ //
+ LocalGuid.Data3 = SwapBytes16 (LocalGuid.Data3);
+ String += 2 * sizeof (LocalGuid.Data3) + 1;
+
+ //
+ // Get iijj.
+ //
+ Status = StrHexToBytes (String, 2 * 2, &LocalGuid.Data4[0], 2);
+ if (RETURN_ERROR (Status) || String[2 * 2] != L'-') {
+ return RETURN_UNSUPPORTED;
+ }
+ String += 2 * 2 + 1;
+
+ //
+ // Get kkllmmnnoopp.
+ //
+ Status = StrHexToBytes (String, 2 * 6, &LocalGuid.Data4[2], 6);
+ if (RETURN_ERROR (Status)) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ CopyGuid (Guid, &LocalGuid);
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated Unicode hexadecimal string to a byte array.
+
+ This function outputs a byte array by interpreting the contents of
+ the Unicode string specified by String in hexadecimal format. The format of
+ the input Unicode string String is:
+
+ [XX]*
+
+ X is a hexadecimal digit character in the range [0-9], [a-f] and [A-F].
+ The function decodes every two hexadecimal digit characters as one byte. The
+ decoding stops after Length of characters and outputs Buffer containing
+ (Length / 2) bytes.
+
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+
+ @param String Pointer to a Null-terminated Unicode string.
+ @param Length The number of Unicode characters to decode.
+ @param Buffer Pointer to the converted bytes array.
+ @param MaxBufferSize The maximum size of Buffer.
+
+ @retval RETURN_SUCCESS Buffer is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If Length is not multiple of 2.
+ If PcdMaximumUnicodeStringLength is not zero,
+ and Length is greater than
+ PcdMaximumUnicodeStringLength.
+ @retval RETURN_UNSUPPORTED If Length of characters from String contain
+ a character that is not valid hexadecimal
+ digit characters, or a Null-terminator.
+ @retval RETURN_BUFFER_TOO_SMALL If MaxBufferSize is less than (Length / 2).
+**/
+RETURN_STATUS
+EFIAPI
+StrHexToBytes (
+ IN CONST CHAR16 *String,
+ IN UINTN Length,
+ OUT UINT8 *Buffer,
+ IN UINTN MaxBufferSize
+ )
+{
+ UINTN Index;
+
+ ASSERT (((UINTN) String & BIT0) == 0);
+
+ //
+ // 1. None of String or Buffer shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Buffer != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. Length shall not be greater than RSIZE_MAX.
+ //
+ if (RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((Length <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ //
+ // 3. Length shall not be odd.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK (((Length & BIT0) == 0), RETURN_INVALID_PARAMETER);
+
+ //
+ // 4. MaxBufferSize shall equal to or greater than Length / 2.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((MaxBufferSize >= Length / 2), RETURN_BUFFER_TOO_SMALL);
+
+ //
+ // 5. String shall not contains invalid hexadecimal digits.
+ //
+ for (Index = 0; Index < Length; Index++) {
+ if (!InternalIsHexaDecimalDigitCharacter (String[Index])) {
+ break;
+ }
+ }
+ if (Index != Length) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ //
+ // Convert the hex string to bytes.
+ //
+ for(Index = 0; Index < Length; Index++) {
+
+ //
+ // For even characters, write the upper nibble for each buffer byte,
+ // and for even characters, the lower nibble.
+ //
+ if ((Index & BIT0) == 0) {
+ Buffer[Index / 2] = (UINT8) InternalHexCharToUintn (String[Index]) << 4;
+ } else {
+ Buffer[Index / 2] |= (UINT8) InternalHexCharToUintn (String[Index]);
+ }
+ }
+ return RETURN_SUCCESS;
+}
+
+/**
+ Returns the length of a Null-terminated Ascii string.
+
+ This function is similar as strlen_s defined in C11.
+
+ @param String A pointer to a Null-terminated Ascii string.
+ @param MaxSize The maximum number of Destination Ascii
+ char, including terminating null char.
+
+ @retval 0 If String is NULL.
+ @retval MaxSize If there is no null character in the first MaxSize characters of String.
+ @return The number of characters that percede the terminating null character.
+
+**/
+UINTN
+EFIAPI
+AsciiStrnLenS (
+ IN CONST CHAR8 *String,
+ IN UINTN MaxSize
+ )
+{
+ UINTN Length;
+
+ //
+ // If String is a null pointer or MaxSize is 0, then the AsciiStrnLenS function returns zero.
+ //
+ if ((String == NULL) || (MaxSize == 0)) {
+ return 0;
+ }
+
+ //
+ // Otherwise, the AsciiStrnLenS function returns the number of characters that precede the
+ // terminating null character. If there is no null character in the first MaxSize characters of
+ // String then AsciiStrnLenS returns MaxSize. At most the first MaxSize characters of String shall
+ // be accessed by AsciiStrnLenS.
+ //
+ Length = 0;
+ while (String[Length] != 0) {
+ if (Length >= MaxSize - 1) {
+ return MaxSize;
+ }
+ Length++;
+ }
+ return Length;
+}
+
+/**
+ Returns the size of a Null-terminated Ascii string in bytes, including the
+ Null terminator.
+
+ This function returns the size of the Null-terminated Ascii string specified
+ by String in bytes, including the Null terminator.
+
+ @param String A pointer to a Null-terminated Ascii string.
+ @param MaxSize The maximum number of Destination Ascii
+ char, including the Null terminator.
+
+ @retval 0 If String is NULL.
+ @retval (sizeof (CHAR8) * (MaxSize + 1))
+ If there is no Null terminator in the first MaxSize characters of
+ String.
+ @return The size of the Null-terminated Ascii string in bytes, including the
+ Null terminator.
+
+**/
+UINTN
+EFIAPI
+AsciiStrnSizeS (
+ IN CONST CHAR8 *String,
+ IN UINTN MaxSize
+ )
+{
+ //
+ // If String is a null pointer, then the AsciiStrnSizeS function returns
+ // zero.
+ //
+ if (String == NULL) {
+ return 0;
+ }
+
+ //
+ // Otherwise, the AsciiStrnSizeS function returns the size of the
+ // Null-terminated Ascii string in bytes, including the Null terminator. If
+ // there is no Null terminator in the first MaxSize characters of String,
+ // then AsciiStrnSizeS returns (sizeof (CHAR8) * (MaxSize + 1)) to keep a
+ // consistent map with the AsciiStrnLenS function.
+ //
+ return (AsciiStrnLenS (String, MaxSize) + 1) * sizeof (*String);
+}
+
+/**
+ Copies the string pointed to by Source (including the terminating null char)
+ to the array pointed to by Destination.
+
+ This function is similar as strcpy_s defined in C11.
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Destination A pointer to a Null-terminated Ascii string.
+ @param DestMax The maximum number of Destination Ascii
+ char, including terminating null char.
+ @param Source A pointer to a Null-terminated Ascii string.
+
+ @retval RETURN_SUCCESS String is copied.
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than StrLen(Source).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumAsciiStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrCpyS (
+ OUT CHAR8 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR8 *Source
+ )
+{
+ UINTN SourceLen;
+
+ //
+ // 1. Neither Destination nor Source shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((Destination != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Source != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. DestMax shall not be greater than ASCII_RSIZE_MAX.
+ //
+ if (ASCII_RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ //
+ // 3. DestMax shall not equal zero.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax != 0), RETURN_INVALID_PARAMETER);
+
+ //
+ // 4. DestMax shall be greater than AsciiStrnLenS(Source, DestMax).
+ //
+ SourceLen = AsciiStrnLenS (Source, DestMax);
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax > SourceLen), RETURN_BUFFER_TOO_SMALL);
+
+ //
+ // 5. Copying shall not take place between objects that overlap.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK (InternalSafeStringNoAsciiStrOverlap (Destination, DestMax, (CHAR8 *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
+
+ //
+ // The AsciiStrCpyS function copies the string pointed to by Source (including the terminating
+ // null character) into the array pointed to by Destination.
+ //
+ while (*Source != 0) {
+ *(Destination++) = *(Source++);
+ }
+ *Destination = 0;
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Copies not more than Length successive char from the string pointed to by
+ Source to the array pointed to by Destination. If no null char is copied from
+ Source, then Destination[Length] is always set to null.
+
+ This function is similar as strncpy_s defined in C11.
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Destination A pointer to a Null-terminated Ascii string.
+ @param DestMax The maximum number of Destination Ascii
+ char, including terminating null char.
+ @param Source A pointer to a Null-terminated Ascii string.
+ @param Length The maximum number of Ascii characters to copy.
+
+ @retval RETURN_SUCCESS String is copied.
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than
+ MIN(StrLen(Source), Length).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumAsciiStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrnCpyS (
+ OUT CHAR8 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR8 *Source,
+ IN UINTN Length
+ )
+{
+ UINTN SourceLen;
+
+ //
+ // 1. Neither Destination nor Source shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((Destination != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Source != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. Neither DestMax nor Length shall be greater than ASCII_RSIZE_MAX
+ //
+ if (ASCII_RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Length <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ //
+ // 3. DestMax shall not equal zero.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax != 0), RETURN_INVALID_PARAMETER);
+
+ //
+ // 4. If Length is not less than DestMax, then DestMax shall be greater than AsciiStrnLenS(Source, DestMax).
+ //
+ SourceLen = AsciiStrnLenS (Source, MIN (DestMax, Length));
+ if (Length >= DestMax) {
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax > SourceLen), RETURN_BUFFER_TOO_SMALL);
+ }
+
+ //
+ // 5. Copying shall not take place between objects that overlap.
+ //
+ if (SourceLen > Length) {
+ SourceLen = Length;
+ }
+ SAFE_STRING_CONSTRAINT_CHECK (InternalSafeStringNoAsciiStrOverlap (Destination, DestMax, (CHAR8 *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
+
+ //
+ // The AsciiStrnCpyS function copies not more than Length successive characters (characters that
+ // follow a null character are not copied) from the array pointed to by Source to the array
+ // pointed to by Destination. If no null character was copied from Source, then Destination[Length] is set to a null
+ // character.
+ //
+ while ((SourceLen > 0) && (*Source != 0)) {
+ *(Destination++) = *(Source++);
+ SourceLen--;
+ }
+ *Destination = 0;
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Appends a copy of the string pointed to by Source (including the terminating
+ null char) to the end of the string pointed to by Destination.
+
+ This function is similar as strcat_s defined in C11.
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Destination A pointer to a Null-terminated Ascii string.
+ @param DestMax The maximum number of Destination Ascii
+ char, including terminating null char.
+ @param Source A pointer to a Null-terminated Ascii string.
+
+ @retval RETURN_SUCCESS String is appended.
+ @retval RETURN_BAD_BUFFER_SIZE If DestMax is NOT greater than
+ StrLen(Destination).
+ @retval RETURN_BUFFER_TOO_SMALL If (DestMax - StrLen(Destination)) is NOT
+ greater than StrLen(Source).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumAsciiStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrCatS (
+ IN OUT CHAR8 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR8 *Source
+ )
+{
+ UINTN DestLen;
+ UINTN CopyLen;
+ UINTN SourceLen;
+
+ //
+ // Let CopyLen denote the value DestMax - AsciiStrnLenS(Destination, DestMax) upon entry to AsciiStrCatS.
+ //
+ DestLen = AsciiStrnLenS (Destination, DestMax);
+ CopyLen = DestMax - DestLen;
+
+ //
+ // 1. Neither Destination nor Source shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((Destination != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Source != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. DestMax shall not be greater than ASCII_RSIZE_MAX.
+ //
+ if (ASCII_RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ //
+ // 3. DestMax shall not equal zero.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax != 0), RETURN_INVALID_PARAMETER);
+
+ //
+ // 4. CopyLen shall not equal zero.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((CopyLen != 0), RETURN_BAD_BUFFER_SIZE);
+
+ //
+ // 5. CopyLen shall be greater than AsciiStrnLenS(Source, CopyLen).
+ //
+ SourceLen = AsciiStrnLenS (Source, CopyLen);
+ SAFE_STRING_CONSTRAINT_CHECK ((CopyLen > SourceLen), RETURN_BUFFER_TOO_SMALL);
+
+ //
+ // 6. Copying shall not take place between objects that overlap.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK (InternalSafeStringNoAsciiStrOverlap (Destination, DestMax, (CHAR8 *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
+
+ //
+ // The AsciiStrCatS function appends a copy of the string pointed to by Source (including the
+ // terminating null character) to the end of the string pointed to by Destination. The initial character
+ // from Source overwrites the null character at the end of Destination.
+ //
+ Destination = Destination + DestLen;
+ while (*Source != 0) {
+ *(Destination++) = *(Source++);
+ }
+ *Destination = 0;
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Appends not more than Length successive char from the string pointed to by
+ Source to the end of the string pointed to by Destination. If no null char is
+ copied from Source, then Destination[StrLen(Destination) + Length] is always
+ set to null.
+
+ This function is similar as strncat_s defined in C11.
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Destination A pointer to a Null-terminated Ascii string.
+ @param DestMax The maximum number of Destination Ascii
+ char, including terminating null char.
+ @param Source A pointer to a Null-terminated Ascii string.
+ @param Length The maximum number of Ascii characters to copy.
+
+ @retval RETURN_SUCCESS String is appended.
+ @retval RETURN_BAD_BUFFER_SIZE If DestMax is NOT greater than
+ StrLen(Destination).
+ @retval RETURN_BUFFER_TOO_SMALL If (DestMax - StrLen(Destination)) is NOT
+ greater than MIN(StrLen(Source), Length).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumAsciiStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrnCatS (
+ IN OUT CHAR8 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR8 *Source,
+ IN UINTN Length
+ )
+{
+ UINTN DestLen;
+ UINTN CopyLen;
+ UINTN SourceLen;
+
+ //
+ // Let CopyLen denote the value DestMax - AsciiStrnLenS(Destination, DestMax) upon entry to AsciiStrnCatS.
+ //
+ DestLen = AsciiStrnLenS (Destination, DestMax);
+ CopyLen = DestMax - DestLen;
+
+ //
+ // 1. Neither Destination nor Source shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((Destination != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Source != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. Neither DestMax nor Length shall be greater than ASCII_RSIZE_MAX.
+ //
+ if (ASCII_RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Length <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ //
+ // 3. DestMax shall not equal zero.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax != 0), RETURN_INVALID_PARAMETER);
+
+ //
+ // 4. CopyLen shall not equal zero.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((CopyLen != 0), RETURN_BAD_BUFFER_SIZE);
+
+ //
+ // 5. If Length is not less than CopyLen, then CopyLen shall be greater than AsciiStrnLenS(Source, CopyLen).
+ //
+ SourceLen = AsciiStrnLenS (Source, MIN (CopyLen, Length));
+ if (Length >= CopyLen) {
+ SAFE_STRING_CONSTRAINT_CHECK ((CopyLen > SourceLen), RETURN_BUFFER_TOO_SMALL);
+ }
+
+ //
+ // 6. Copying shall not take place between objects that overlap.
+ //
+ if (SourceLen > Length) {
+ SourceLen = Length;
+ }
+ SAFE_STRING_CONSTRAINT_CHECK (InternalSafeStringNoAsciiStrOverlap (Destination, DestMax, (CHAR8 *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
+
+ //
+ // The AsciiStrnCatS function appends not more than Length successive characters (characters
+ // that follow a null character are not copied) from the array pointed to by Source to the end of
+ // the string pointed to by Destination. The initial character from Source overwrites the null character at
+ // the end of Destination. If no null character was copied from Source, then Destination[DestMax-CopyLen+Length] is set to
+ // a null character.
+ //
+ Destination = Destination + DestLen;
+ while ((SourceLen > 0) && (*Source != 0)) {
+ *(Destination++) = *(Source++);
+ SourceLen--;
+ }
+ *Destination = 0;
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated Ascii decimal string to a value of type UINTN.
+
+ This function outputs a value of type UINTN by interpreting the contents of
+ the Ascii string specified by String as a decimal number. The format of the
+ input Ascii string String is:
+
+ [spaces] [decimal digits].
+
+ The valid decimal digit character is in the range [0-9]. The function will
+ ignore the pad space, which includes spaces or tab characters, before
+ [decimal digits]. The running zero in the beginning of [decimal digits] will
+ be ignored. Then, the function stops at the first character that is a not a
+ valid decimal character or a Null-terminator, whichever one comes first.
+
+ If String has no valid decimal digits in the above format, then 0 is stored
+ at the location pointed to by Data.
+ If the number represented by String exceeds the range defined by UINTN, then
+ MAX_UINTN is stored at the location pointed to by Data.
+
+ If EndPointer is not NULL, a pointer to the character that stopped the scan
+ is stored at the location pointed to by EndPointer. If String has no valid
+ decimal digits right after the optional pad spaces, the value of String is
+ stored at the location pointed to by EndPointer.
+
+ @param String Pointer to a Null-terminated Ascii string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Data Pointer to the converted value.
+
+ @retval RETURN_SUCCESS Value is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and String contains more than
+ PcdMaximumAsciiStringLength Ascii
+ characters, not including the
+ Null-terminator.
+ @retval RETURN_UNSUPPORTED If the number represented by String exceeds
+ the range defined by UINTN.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrDecimalToUintnS (
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer, OPTIONAL
+ OUT UINTN *Data
+ )
+{
+ //
+ // 1. Neither String nor Data shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Data != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. The length of String shall not be greater than ASCII_RSIZE_MAX.
+ //
+ if (ASCII_RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((AsciiStrnLenS (String, ASCII_RSIZE_MAX + 1) <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR8 *) String;
+ }
+
+ //
+ // Ignore the pad spaces (space or tab)
+ //
+ while ((*String == ' ') || (*String == '\t')) {
+ String++;
+ }
+
+ //
+ // Ignore leading Zeros after the spaces
+ //
+ while (*String == '0') {
+ String++;
+ }
+
+ *Data = 0;
+
+ while (InternalAsciiIsDecimalDigitCharacter (*String)) {
+ //
+ // If the number represented by String overflows according to the range
+ // defined by UINTN, then MAX_UINTN is stored in *Data and
+ // RETURN_UNSUPPORTED is returned.
+ //
+ if (*Data > ((MAX_UINTN - (*String - '0')) / 10)) {
+ *Data = MAX_UINTN;
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR8 *) String;
+ }
+ return RETURN_UNSUPPORTED;
+ }
+
+ *Data = *Data * 10 + (*String - '0');
+ String++;
+ }
+
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR8 *) String;
+ }
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated Ascii decimal string to a value of type UINT64.
+
+ This function outputs a value of type UINT64 by interpreting the contents of
+ the Ascii string specified by String as a decimal number. The format of the
+ input Ascii string String is:
+
+ [spaces] [decimal digits].
+
+ The valid decimal digit character is in the range [0-9]. The function will
+ ignore the pad space, which includes spaces or tab characters, before
+ [decimal digits]. The running zero in the beginning of [decimal digits] will
+ be ignored. Then, the function stops at the first character that is a not a
+ valid decimal character or a Null-terminator, whichever one comes first.
+
+ If String has no valid decimal digits in the above format, then 0 is stored
+ at the location pointed to by Data.
+ If the number represented by String exceeds the range defined by UINT64, then
+ MAX_UINT64 is stored at the location pointed to by Data.
+
+ If EndPointer is not NULL, a pointer to the character that stopped the scan
+ is stored at the location pointed to by EndPointer. If String has no valid
+ decimal digits right after the optional pad spaces, the value of String is
+ stored at the location pointed to by EndPointer.
+
+ @param String Pointer to a Null-terminated Ascii string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Data Pointer to the converted value.
+
+ @retval RETURN_SUCCESS Value is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and String contains more than
+ PcdMaximumAsciiStringLength Ascii
+ characters, not including the
+ Null-terminator.
+ @retval RETURN_UNSUPPORTED If the number represented by String exceeds
+ the range defined by UINT64.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrDecimalToUint64S (
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer, OPTIONAL
+ OUT UINT64 *Data
+ )
+{
+ //
+ // 1. Neither String nor Data shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Data != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. The length of String shall not be greater than ASCII_RSIZE_MAX.
+ //
+ if (ASCII_RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((AsciiStrnLenS (String, ASCII_RSIZE_MAX + 1) <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR8 *) String;
+ }
+
+ //
+ // Ignore the pad spaces (space or tab)
+ //
+ while ((*String == ' ') || (*String == '\t')) {
+ String++;
+ }
+
+ //
+ // Ignore leading Zeros after the spaces
+ //
+ while (*String == '0') {
+ String++;
+ }
+
+ *Data = 0;
+
+ while (InternalAsciiIsDecimalDigitCharacter (*String)) {
+ //
+ // If the number represented by String overflows according to the range
+ // defined by UINT64, then MAX_UINT64 is stored in *Data and
+ // RETURN_UNSUPPORTED is returned.
+ //
+ if (*Data > DivU64x32 (MAX_UINT64 - (*String - '0'), 10)) {
+ *Data = MAX_UINT64;
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR8 *) String;
+ }
+ return RETURN_UNSUPPORTED;
+ }
+
+ *Data = MultU64x32 (*Data, 10) + (*String - '0');
+ String++;
+ }
+
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR8 *) String;
+ }
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated Ascii hexadecimal string to a value of type UINTN.
+
+ This function outputs a value of type UINTN by interpreting the contents of
+ the Ascii string specified by String as a hexadecimal number. The format of
+ the input Ascii string String is:
+
+ [spaces][zeros][x][hexadecimal digits].
+
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. If
+ "x" appears in the input string, it must be prefixed with at least one 0. The
+ function will ignore the pad space, which includes spaces or tab characters,
+ before [zeros], [x] or [hexadecimal digits]. The running zero before [x] or
+ [hexadecimal digits] will be ignored. Then, the decoding starts after [x] or
+ the first valid hexadecimal digit. Then, the function stops at the first
+ character that is a not a valid hexadecimal character or Null-terminator,
+ whichever on comes first.
+
+ If String has no valid hexadecimal digits in the above format, then 0 is
+ stored at the location pointed to by Data.
+ If the number represented by String exceeds the range defined by UINTN, then
+ MAX_UINTN is stored at the location pointed to by Data.
+
+ If EndPointer is not NULL, a pointer to the character that stopped the scan
+ is stored at the location pointed to by EndPointer. If String has no valid
+ hexadecimal digits right after the optional pad spaces, the value of String
+ is stored at the location pointed to by EndPointer.
+
+ @param String Pointer to a Null-terminated Ascii string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Data Pointer to the converted value.
+
+ @retval RETURN_SUCCESS Value is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and String contains more than
+ PcdMaximumAsciiStringLength Ascii
+ characters, not including the
+ Null-terminator.
+ @retval RETURN_UNSUPPORTED If the number represented by String exceeds
+ the range defined by UINTN.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrHexToUintnS (
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer, OPTIONAL
+ OUT UINTN *Data
+ )
+{
+ //
+ // 1. Neither String nor Data shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Data != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. The length of String shall not be greater than ASCII_RSIZE_MAX.
+ //
+ if (ASCII_RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((AsciiStrnLenS (String, ASCII_RSIZE_MAX + 1) <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR8 *) String;
+ }
+
+ //
+ // Ignore the pad spaces (space or tab)
+ //
+ while ((*String == ' ') || (*String == '\t')) {
+ String++;
+ }
+
+ //
+ // Ignore leading Zeros after the spaces
+ //
+ while (*String == '0') {
+ String++;
+ }
+
+ if (AsciiCharToUpper (*String) == 'X') {
+ if (*(String - 1) != '0') {
+ *Data = 0;
+ return RETURN_SUCCESS;
+ }
+ //
+ // Skip the 'X'
+ //
+ String++;
+ }
+
+ *Data = 0;
+
+ while (InternalAsciiIsHexaDecimalDigitCharacter (*String)) {
+ //
+ // If the number represented by String overflows according to the range
+ // defined by UINTN, then MAX_UINTN is stored in *Data and
+ // RETURN_UNSUPPORTED is returned.
+ //
+ if (*Data > ((MAX_UINTN - InternalAsciiHexCharToUintn (*String)) >> 4)) {
+ *Data = MAX_UINTN;
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR8 *) String;
+ }
+ return RETURN_UNSUPPORTED;
+ }
+
+ *Data = (*Data << 4) + InternalAsciiHexCharToUintn (*String);
+ String++;
+ }
+
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR8 *) String;
+ }
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated Ascii hexadecimal string to a value of type UINT64.
+
+ This function outputs a value of type UINT64 by interpreting the contents of
+ the Ascii string specified by String as a hexadecimal number. The format of
+ the input Ascii string String is:
+
+ [spaces][zeros][x][hexadecimal digits].
+
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. If
+ "x" appears in the input string, it must be prefixed with at least one 0. The
+ function will ignore the pad space, which includes spaces or tab characters,
+ before [zeros], [x] or [hexadecimal digits]. The running zero before [x] or
+ [hexadecimal digits] will be ignored. Then, the decoding starts after [x] or
+ the first valid hexadecimal digit. Then, the function stops at the first
+ character that is a not a valid hexadecimal character or Null-terminator,
+ whichever on comes first.
+
+ If String has no valid hexadecimal digits in the above format, then 0 is
+ stored at the location pointed to by Data.
+ If the number represented by String exceeds the range defined by UINT64, then
+ MAX_UINT64 is stored at the location pointed to by Data.
+
+ If EndPointer is not NULL, a pointer to the character that stopped the scan
+ is stored at the location pointed to by EndPointer. If String has no valid
+ hexadecimal digits right after the optional pad spaces, the value of String
+ is stored at the location pointed to by EndPointer.
+
+ @param String Pointer to a Null-terminated Ascii string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Data Pointer to the converted value.
+
+ @retval RETURN_SUCCESS Value is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and String contains more than
+ PcdMaximumAsciiStringLength Ascii
+ characters, not including the
+ Null-terminator.
+ @retval RETURN_UNSUPPORTED If the number represented by String exceeds
+ the range defined by UINT64.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrHexToUint64S (
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer, OPTIONAL
+ OUT UINT64 *Data
+ )
+{
+ //
+ // 1. Neither String nor Data shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Data != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. The length of String shall not be greater than ASCII_RSIZE_MAX.
+ //
+ if (ASCII_RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((AsciiStrnLenS (String, ASCII_RSIZE_MAX + 1) <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR8 *) String;
+ }
+
+ //
+ // Ignore the pad spaces (space or tab)
+ //
+ while ((*String == ' ') || (*String == '\t')) {
+ String++;
+ }
+
+ //
+ // Ignore leading Zeros after the spaces
+ //
+ while (*String == '0') {
+ String++;
+ }
+
+ if (AsciiCharToUpper (*String) == 'X') {
+ if (*(String - 1) != '0') {
+ *Data = 0;
+ return RETURN_SUCCESS;
+ }
+ //
+ // Skip the 'X'
+ //
+ String++;
+ }
+
+ *Data = 0;
+
+ while (InternalAsciiIsHexaDecimalDigitCharacter (*String)) {
+ //
+ // If the number represented by String overflows according to the range
+ // defined by UINT64, then MAX_UINT64 is stored in *Data and
+ // RETURN_UNSUPPORTED is returned.
+ //
+ if (*Data > RShiftU64 (MAX_UINT64 - InternalAsciiHexCharToUintn (*String), 4)) {
+ *Data = MAX_UINT64;
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR8 *) String;
+ }
+ return RETURN_UNSUPPORTED;
+ }
+
+ *Data = LShiftU64 (*Data, 4) + InternalAsciiHexCharToUintn (*String);
+ String++;
+ }
+
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR8 *) String;
+ }
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated Unicode string to a Null-terminated
+ ASCII string.
+
+ This function is similar to AsciiStrCpyS.
+
+ This function converts the content of the Unicode string Source
+ to the ASCII string Destination by copying the lower 8 bits of
+ each Unicode character. The function terminates the ASCII string
+ Destination by appending a Null-terminator character at the end.
+
+ The caller is responsible to make sure Destination points to a buffer with size
+ equal or greater than ((StrLen (Source) + 1) * sizeof (CHAR8)) in bytes.
+
+ If any Unicode characters in Source contain non-zero value in
+ the upper 8 bits, then ASSERT().
+
+ If Source is not aligned on a 16-bit boundary, then ASSERT().
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Source The pointer to a Null-terminated Unicode string.
+ @param Destination The pointer to a Null-terminated ASCII string.
+ @param DestMax The maximum number of Destination Ascii
+ char, including terminating null char.
+
+ @retval RETURN_SUCCESS String is converted.
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than StrLen(Source).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumAsciiStringLength.
+ If PcdMaximumUnicodeStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumUnicodeStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+
+**/
+RETURN_STATUS
+EFIAPI
+UnicodeStrToAsciiStrS (
+ IN CONST CHAR16 *Source,
+ OUT CHAR8 *Destination,
+ IN UINTN DestMax
+ )
+{
+ UINTN SourceLen;
+
+ ASSERT (((UINTN) Source & BIT0) == 0);
+
+ //
+ // 1. Neither Destination nor Source shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((Destination != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Source != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. DestMax shall not be greater than ASCII_RSIZE_MAX or RSIZE_MAX.
+ //
+ if (ASCII_RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+ if (RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ //
+ // 3. DestMax shall not equal zero.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax != 0), RETURN_INVALID_PARAMETER);
+
+ //
+ // 4. DestMax shall be greater than StrnLenS (Source, DestMax).
+ //
+ SourceLen = StrnLenS (Source, DestMax);
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax > SourceLen), RETURN_BUFFER_TOO_SMALL);
+
+ //
+ // 5. Copying shall not take place between objects that overlap.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax, (VOID *)Source, (SourceLen + 1) * sizeof(CHAR16)), RETURN_ACCESS_DENIED);
+
+ //
+ // convert string
+ //
+ while (*Source != '\0') {
+ //
+ // If any Unicode characters in Source contain
+ // non-zero value in the upper 8 bits, then ASSERT().
+ //
+ ASSERT (*Source < 0x100);
+ *(Destination++) = (CHAR8) *(Source++);
+ }
+ *Destination = '\0';
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert not more than Length successive characters from a Null-terminated
+ Unicode string to a Null-terminated Ascii string. If no null char is copied
+ from Source, then Destination[Length] is always set to null.
+
+ This function converts not more than Length successive characters from the
+ Unicode string Source to the Ascii string Destination by copying the lower 8
+ bits of each Unicode character. The function terminates the Ascii string
+ Destination by appending a Null-terminator character at the end.
+
+ The caller is responsible to make sure Destination points to a buffer with
+ size not smaller than ((MIN(StrLen(Source), Length) + 1) * sizeof (CHAR8))
+ in bytes.
+
+ If any Unicode characters in Source contain non-zero value in the upper 8
+ bits, then ASSERT().
+ If Source is not aligned on a 16-bit boundary, then ASSERT().
+
+ If an error is returned, then Destination and DestinationLength are
+ unmodified.
+
+ @param Source The pointer to a Null-terminated Unicode string.
+ @param Length The maximum number of Unicode characters to
+ convert.
+ @param Destination The pointer to a Null-terminated Ascii string.
+ @param DestMax The maximum number of Destination Ascii char,
+ including terminating null char.
+ @param DestinationLength The number of Unicode characters converted.
+
+ @retval RETURN_SUCCESS String is converted.
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If DestinationLength is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and Length or DestMax is greater than
+ PcdMaximumAsciiStringLength.
+ If PcdMaximumUnicodeStringLength is not
+ zero, and Length or DestMax is greater than
+ PcdMaximumUnicodeStringLength.
+ If DestMax is 0.
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than
+ MIN(StrLen(Source), Length).
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+
+**/
+RETURN_STATUS
+EFIAPI
+UnicodeStrnToAsciiStrS (
+ IN CONST CHAR16 *Source,
+ IN UINTN Length,
+ OUT CHAR8 *Destination,
+ IN UINTN DestMax,
+ OUT UINTN *DestinationLength
+ )
+{
+ UINTN SourceLen;
+
+ ASSERT (((UINTN) Source & BIT0) == 0);
+
+ //
+ // 1. None of Destination, Source or DestinationLength shall be a null
+ // pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((Destination != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Source != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((DestinationLength != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. Neither Length nor DestMax shall be greater than ASCII_RSIZE_MAX or
+ // RSIZE_MAX.
+ //
+ if (ASCII_RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((Length <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+ if (RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((Length <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ //
+ // 3. DestMax shall not equal zero.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax != 0), RETURN_INVALID_PARAMETER);
+
+ //
+ // 4. If Length is not less than DestMax, then DestMax shall be greater than
+ // StrnLenS(Source, DestMax).
+ //
+ SourceLen = StrnLenS (Source, DestMax);
+ if (Length >= DestMax) {
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax > SourceLen), RETURN_BUFFER_TOO_SMALL);
+ }
+
+ //
+ // 5. Copying shall not take place between objects that overlap.
+ //
+ if (SourceLen > Length) {
+ SourceLen = Length;
+ }
+ SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax, (VOID *)Source, (SourceLen + 1) * sizeof(CHAR16)), RETURN_ACCESS_DENIED);
+
+ *DestinationLength = 0;
+
+ //
+ // Convert string
+ //
+ while ((*Source != 0) && (SourceLen > 0)) {
+ //
+ // If any Unicode characters in Source contain non-zero value in the upper
+ // 8 bits, then ASSERT().
+ //
+ ASSERT (*Source < 0x100);
+ *(Destination++) = (CHAR8) *(Source++);
+ SourceLen--;
+ (*DestinationLength)++;
+ }
+ *Destination = 0;
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert one Null-terminated ASCII string to a Null-terminated
+ Unicode string.
+
+ This function is similar to StrCpyS.
+
+ This function converts the contents of the ASCII string Source to the Unicode
+ string Destination. The function terminates the Unicode string Destination by
+ appending a Null-terminator character at the end.
+
+ The caller is responsible to make sure Destination points to a buffer with size
+ equal or greater than ((AsciiStrLen (Source) + 1) * sizeof (CHAR16)) in bytes.
+
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Source The pointer to a Null-terminated ASCII string.
+ @param Destination The pointer to a Null-terminated Unicode string.
+ @param DestMax The maximum number of Destination Unicode
+ char, including terminating null char.
+
+ @retval RETURN_SUCCESS String is converted.
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than StrLen(Source).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumUnicodeStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumUnicodeStringLength.
+ If PcdMaximumAsciiStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumAsciiStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrToUnicodeStrS (
+ IN CONST CHAR8 *Source,
+ OUT CHAR16 *Destination,
+ IN UINTN DestMax
+ )
+{
+ UINTN SourceLen;
+
+ ASSERT (((UINTN) Destination & BIT0) == 0);
+
+ //
+ // 1. Neither Destination nor Source shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((Destination != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Source != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. DestMax shall not be greater than RSIZE_MAX or ASCII_RSIZE_MAX.
+ //
+ if (RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+ if (ASCII_RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ //
+ // 3. DestMax shall not equal zero.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax != 0), RETURN_INVALID_PARAMETER);
+
+ //
+ // 4. DestMax shall be greater than AsciiStrnLenS(Source, DestMax).
+ //
+ SourceLen = AsciiStrnLenS (Source, DestMax);
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax > SourceLen), RETURN_BUFFER_TOO_SMALL);
+
+ //
+ // 5. Copying shall not take place between objects that overlap.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax * sizeof(CHAR16), (VOID *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
+
+ //
+ // Convert string
+ //
+ while (*Source != '\0') {
+ *(Destination++) = (CHAR16)(UINT8)*(Source++);
+ }
+ *Destination = '\0';
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert not more than Length successive characters from a Null-terminated
+ Ascii string to a Null-terminated Unicode string. If no null char is copied
+ from Source, then Destination[Length] is always set to null.
+
+ This function converts not more than Length successive characters from the
+ Ascii string Source to the Unicode string Destination. The function
+ terminates the Unicode string Destination by appending a Null-terminator
+ character at the end.
+
+ The caller is responsible to make sure Destination points to a buffer with
+ size not smaller than
+ ((MIN(AsciiStrLen(Source), Length) + 1) * sizeof (CHAR8)) in bytes.
+
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().
+
+ If an error is returned, then Destination and DestinationLength are
+ unmodified.
+
+ @param Source The pointer to a Null-terminated Ascii string.
+ @param Length The maximum number of Ascii characters to convert.
+ @param Destination The pointer to a Null-terminated Unicode string.
+ @param DestMax The maximum number of Destination Unicode char,
+ including terminating null char.
+ @param DestinationLength The number of Ascii characters converted.
+
+ @retval RETURN_SUCCESS String is converted.
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If DestinationLength is NULL.
+ If PcdMaximumUnicodeStringLength is not
+ zero, and Length or DestMax is greater than
+ PcdMaximumUnicodeStringLength.
+ If PcdMaximumAsciiStringLength is not zero,
+ and Length or DestMax is greater than
+ PcdMaximumAsciiStringLength.
+ If DestMax is 0.
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than
+ MIN(AsciiStrLen(Source), Length).
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrnToUnicodeStrS (
+ IN CONST CHAR8 *Source,
+ IN UINTN Length,
+ OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ OUT UINTN *DestinationLength
+ )
+{
+ UINTN SourceLen;
+
+ ASSERT (((UINTN) Destination & BIT0) == 0);
+
+ //
+ // 1. None of Destination, Source or DestinationLength shall be a null
+ // pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((Destination != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Source != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((DestinationLength != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. Neither Length nor DestMax shall be greater than ASCII_RSIZE_MAX or
+ // RSIZE_MAX.
+ //
+ if (RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((Length <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+ if (ASCII_RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((Length <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ //
+ // 3. DestMax shall not equal zero.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax != 0), RETURN_INVALID_PARAMETER);
+
+ //
+ // 4. If Length is not less than DestMax, then DestMax shall be greater than
+ // AsciiStrnLenS(Source, DestMax).
+ //
+ SourceLen = AsciiStrnLenS (Source, DestMax);
+ if (Length >= DestMax) {
+ SAFE_STRING_CONSTRAINT_CHECK ((DestMax > SourceLen), RETURN_BUFFER_TOO_SMALL);
+ }
+
+ //
+ // 5. Copying shall not take place between objects that overlap.
+ //
+ if (SourceLen > Length) {
+ SourceLen = Length;
+ }
+ SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax * sizeof(CHAR16), (VOID *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
+
+ *DestinationLength = 0;
+
+ //
+ // Convert string
+ //
+ while ((*Source != 0) && (SourceLen > 0)) {
+ *(Destination++) = (CHAR16)(UINT8)*(Source++);
+ SourceLen--;
+ (*DestinationLength)++;
+ }
+ *Destination = 0;
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated ASCII string to IPv6 address and prefix length.
+
+ This function outputs a value of type IPv6_ADDRESS and may output a value
+ of type UINT8 by interpreting the contents of the ASCII string specified
+ by String. The format of the input ASCII string String is as follows:
+
+ X:X:X:X:X:X:X:X[/P]
+
+ X contains one to four hexadecimal digit characters in the range [0-9], [a-f] and
+ [A-F]. X is converted to a value of type UINT16, whose low byte is stored in low
+ memory address and high byte is stored in high memory address. P contains decimal
+ digit characters in the range [0-9]. The running zero in the beginning of P will
+ be ignored. /P is optional.
+
+ When /P is not in the String, the function stops at the first character that is
+ not a valid hexadecimal digit character after eight X's are converted.
+
+ When /P is in the String, the function stops at the first character that is not
+ a valid decimal digit character after P is converted.
+
+ "::" can be used to compress one or more groups of X when X contains only 0.
+ The "::" can only appear once in the String.
+
+ If EndPointer is not NULL and Address is translated from String, a pointer
+ to the character that stopped the scan is stored at the location pointed to
+ by EndPointer.
+
+ @param String Pointer to a Null-terminated ASCII string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Address Pointer to the converted IPv6 address.
+ @param PrefixLength Pointer to the converted IPv6 address prefix
+ length. MAX_UINT8 is returned when /P is
+ not in the String.
+
+ @retval RETURN_SUCCESS Address is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ @retval RETURN_UNSUPPORTED If X contains more than four hexadecimal
+ digit characters.
+ If String contains "::" and number of X
+ is not less than 8.
+ If P starts with character that is not a
+ valid decimal digit character.
+ If the decimal number converted from P
+ exceeds 128.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrToIpv6Address (
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer, OPTIONAL
+ OUT IPv6_ADDRESS *Address,
+ OUT UINT8 *PrefixLength OPTIONAL
+ )
+{
+ RETURN_STATUS Status;
+ UINTN AddressIndex;
+ UINTN Uintn;
+ IPv6_ADDRESS LocalAddress;
+ UINT8 LocalPrefixLength;
+ CONST CHAR8 *Pointer;
+ CHAR8 *End;
+ UINTN CompressStart;
+ BOOLEAN ExpectPrefix;
+
+ LocalPrefixLength = MAX_UINT8;
+ CompressStart = ARRAY_SIZE (Address->Addr);
+ ExpectPrefix = FALSE;
+
+ //
+ // None of String or Address shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Address != NULL), RETURN_INVALID_PARAMETER);
+
+ for (Pointer = String, AddressIndex = 0; AddressIndex < ARRAY_SIZE (Address->Addr) + 1;) {
+ if (!InternalAsciiIsHexaDecimalDigitCharacter (*Pointer)) {
+ if (*Pointer != ':') {
+ //
+ // ":" or "/" should be followed by digit characters.
+ //
+ return RETURN_UNSUPPORTED;
+ }
+
+ //
+ // Meet second ":" after previous ":" or "/"
+ // or meet first ":" in the beginning of String.
+ //
+ if (ExpectPrefix) {
+ //
+ // ":" shall not be after "/"
+ //
+ return RETURN_UNSUPPORTED;
+ }
+
+ if (CompressStart != ARRAY_SIZE (Address->Addr) || AddressIndex == ARRAY_SIZE (Address->Addr)) {
+ //
+ // "::" can only appear once.
+ // "::" can only appear when address is not full length.
+ //
+ return RETURN_UNSUPPORTED;
+ } else {
+ //
+ // Remember the start of zero compressing.
+ //
+ CompressStart = AddressIndex;
+ Pointer++;
+
+ if (CompressStart == 0) {
+ if (*Pointer != ':') {
+ //
+ // Single ":" shall not be in the beginning of String.
+ //
+ return RETURN_UNSUPPORTED;
+ }
+ Pointer++;
+ }
+ }
+ }
+
+ if (!InternalAsciiIsHexaDecimalDigitCharacter (*Pointer)) {
+ if (*Pointer == '/') {
+ //
+ // Might be optional "/P" after "::".
+ //
+ if (CompressStart != AddressIndex) {
+ return RETURN_UNSUPPORTED;
+ }
+ } else {
+ break;
+ }
+ } else {
+ if (!ExpectPrefix) {
+ //
+ // Get X.
+ //
+ Status = AsciiStrHexToUintnS (Pointer, &End, &Uintn);
+ if (RETURN_ERROR (Status) || End - Pointer > 4) {
+ //
+ // Number of hexadecimal digit characters is no more than 4.
+ //
+ return RETURN_UNSUPPORTED;
+ }
+ Pointer = End;
+ //
+ // Uintn won't exceed MAX_UINT16 if number of hexadecimal digit characters is no more than 4.
+ //
+ ASSERT (AddressIndex + 1 < ARRAY_SIZE (Address->Addr));
+ LocalAddress.Addr[AddressIndex] = (UINT8) ((UINT16) Uintn >> 8);
+ LocalAddress.Addr[AddressIndex + 1] = (UINT8) Uintn;
+ AddressIndex += 2;
+ } else {
+ //
+ // Get P, then exit the loop.
+ //
+ Status = AsciiStrDecimalToUintnS (Pointer, &End, &Uintn);
+ if (RETURN_ERROR (Status) || End == Pointer || Uintn > 128) {
+ //
+ // Prefix length should not exceed 128.
+ //
+ return RETURN_UNSUPPORTED;
+ }
+ LocalPrefixLength = (UINT8) Uintn;
+ Pointer = End;
+ break;
+ }
+ }
+
+ //
+ // Skip ':' or "/"
+ //
+ if (*Pointer == '/') {
+ ExpectPrefix = TRUE;
+ } else if (*Pointer == ':') {
+ if (AddressIndex == ARRAY_SIZE (Address->Addr)) {
+ //
+ // Meet additional ":" after all 8 16-bit address
+ //
+ break;
+ }
+ } else {
+ //
+ // Meet other character that is not "/" or ":" after all 8 16-bit address
+ //
+ break;
+ }
+ Pointer++;
+ }
+
+ if ((AddressIndex == ARRAY_SIZE (Address->Addr) && CompressStart != ARRAY_SIZE (Address->Addr)) ||
+ (AddressIndex != ARRAY_SIZE (Address->Addr) && CompressStart == ARRAY_SIZE (Address->Addr))
+ ) {
+ //
+ // Full length of address shall not have compressing zeros.
+ // Non-full length of address shall have compressing zeros.
+ //
+ return RETURN_UNSUPPORTED;
+ }
+ CopyMem (&Address->Addr[0], &LocalAddress.Addr[0], CompressStart);
+ ZeroMem (&Address->Addr[CompressStart], ARRAY_SIZE (Address->Addr) - AddressIndex);
+ if (AddressIndex > CompressStart) {
+ CopyMem (
+ &Address->Addr[CompressStart + ARRAY_SIZE (Address->Addr) - AddressIndex],
+ &LocalAddress.Addr[CompressStart],
+ AddressIndex - CompressStart
+ );
+
+ }
+
+ if (PrefixLength != NULL) {
+ *PrefixLength = LocalPrefixLength;
+ }
+ if (EndPointer != NULL) {
+ *EndPointer = (CHAR8 *) Pointer;
+ }
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated ASCII string to IPv4 address and prefix length.
+
+ This function outputs a value of type IPv4_ADDRESS and may output a value
+ of type UINT8 by interpreting the contents of the ASCII string specified
+ by String. The format of the input ASCII string String is as follows:
+
+ D.D.D.D[/P]
+
+ D and P are decimal digit characters in the range [0-9]. The running zero in
+ the beginning of D and P will be ignored. /P is optional.
+
+ When /P is not in the String, the function stops at the first character that is
+ not a valid decimal digit character after four D's are converted.
+
+ When /P is in the String, the function stops at the first character that is not
+ a valid decimal digit character after P is converted.
+
+ If EndPointer is not NULL and Address is translated from String, a pointer
+ to the character that stopped the scan is stored at the location pointed to
+ by EndPointer.
+
+ @param String Pointer to a Null-terminated ASCII string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Address Pointer to the converted IPv4 address.
+ @param PrefixLength Pointer to the converted IPv4 address prefix
+ length. MAX_UINT8 is returned when /P is
+ not in the String.
+
+ @retval RETURN_SUCCESS Address is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ @retval RETURN_UNSUPPORTED If String is not in the correct format.
+ If any decimal number converted from D
+ exceeds 255.
+ If the decimal number converted from P
+ exceeds 32.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrToIpv4Address (
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer, OPTIONAL
+ OUT IPv4_ADDRESS *Address,
+ OUT UINT8 *PrefixLength OPTIONAL
+ )
+{
+ RETURN_STATUS Status;
+ UINTN AddressIndex;
+ UINTN Uintn;
+ IPv4_ADDRESS LocalAddress;
+ UINT8 LocalPrefixLength;
+ CHAR8 *Pointer;
+
+ LocalPrefixLength = MAX_UINT8;
+
+ //
+ // None of String or Address shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Address != NULL), RETURN_INVALID_PARAMETER);
+
+ for (Pointer = (CHAR8 *) String, AddressIndex = 0; AddressIndex < ARRAY_SIZE (Address->Addr) + 1;) {
+ if (!InternalAsciiIsDecimalDigitCharacter (*Pointer)) {
+ //
+ // D or P contains invalid characters.
+ //
+ break;
+ }
+
+ //
+ // Get D or P.
+ //
+ Status = AsciiStrDecimalToUintnS ((CONST CHAR8 *) Pointer, &Pointer, &Uintn);
+ if (RETURN_ERROR (Status)) {
+ return RETURN_UNSUPPORTED;
+ }
+ if (AddressIndex == ARRAY_SIZE (Address->Addr)) {
+ //
+ // It's P.
+ //
+ if (Uintn > 32) {
+ return RETURN_UNSUPPORTED;
+ }
+ LocalPrefixLength = (UINT8) Uintn;
+ } else {
+ //
+ // It's D.
+ //
+ if (Uintn > MAX_UINT8) {
+ return RETURN_UNSUPPORTED;
+ }
+ LocalAddress.Addr[AddressIndex] = (UINT8) Uintn;
+ AddressIndex++;
+ }
+
+ //
+ // Check the '.' or '/', depending on the AddressIndex.
+ //
+ if (AddressIndex == ARRAY_SIZE (Address->Addr)) {
+ if (*Pointer == '/') {
+ //
+ // '/P' is in the String.
+ // Skip "/" and get P in next loop.
+ //
+ Pointer++;
+ } else {
+ //
+ // '/P' is not in the String.
+ //
+ break;
+ }
+ } else if (AddressIndex < ARRAY_SIZE (Address->Addr)) {
+ if (*Pointer == '.') {
+ //
+ // D should be followed by '.'
+ //
+ Pointer++;
+ } else {
+ return RETURN_UNSUPPORTED;
+ }
+ }
+ }
+
+ if (AddressIndex < ARRAY_SIZE (Address->Addr)) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ CopyMem (Address, &LocalAddress, sizeof (*Address));
+ if (PrefixLength != NULL) {
+ *PrefixLength = LocalPrefixLength;
+ }
+ if (EndPointer != NULL) {
+ *EndPointer = Pointer;
+ }
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated ASCII GUID string to a value of type
+ EFI_GUID.
+
+ This function outputs a GUID value by interpreting the contents of
+ the ASCII string specified by String. The format of the input
+ ASCII string String consists of 36 characters, as follows:
+
+ aabbccdd-eeff-gghh-iijj-kkllmmnnoopp
+
+ The pairs aa - pp are two characters in the range [0-9], [a-f] and
+ [A-F], with each pair representing a single byte hexadecimal value.
+
+ The mapping between String and the EFI_GUID structure is as follows:
+ aa Data1[24:31]
+ bb Data1[16:23]
+ cc Data1[8:15]
+ dd Data1[0:7]
+ ee Data2[8:15]
+ ff Data2[0:7]
+ gg Data3[8:15]
+ hh Data3[0:7]
+ ii Data4[0:7]
+ jj Data4[8:15]
+ kk Data4[16:23]
+ ll Data4[24:31]
+ mm Data4[32:39]
+ nn Data4[40:47]
+ oo Data4[48:55]
+ pp Data4[56:63]
+
+ @param String Pointer to a Null-terminated ASCII string.
+ @param Guid Pointer to the converted GUID.
+
+ @retval RETURN_SUCCESS Guid is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ @retval RETURN_UNSUPPORTED If String is not as the above format.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrToGuid (
+ IN CONST CHAR8 *String,
+ OUT GUID *Guid
+ )
+{
+ RETURN_STATUS Status;
+ GUID LocalGuid;
+
+ //
+ // None of String or Guid shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Guid != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // Get aabbccdd in big-endian.
+ //
+ Status = AsciiStrHexToBytes (String, 2 * sizeof (LocalGuid.Data1), (UINT8 *) &LocalGuid.Data1, sizeof (LocalGuid.Data1));
+ if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data1)] != '-') {
+ return RETURN_UNSUPPORTED;
+ }
+ //
+ // Convert big-endian to little-endian.
+ //
+ LocalGuid.Data1 = SwapBytes32 (LocalGuid.Data1);
+ String += 2 * sizeof (LocalGuid.Data1) + 1;
+
+ //
+ // Get eeff in big-endian.
+ //
+ Status = AsciiStrHexToBytes (String, 2 * sizeof (LocalGuid.Data2), (UINT8 *) &LocalGuid.Data2, sizeof (LocalGuid.Data2));
+ if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data2)] != '-') {
+ return RETURN_UNSUPPORTED;
+ }
+ //
+ // Convert big-endian to little-endian.
+ //
+ LocalGuid.Data2 = SwapBytes16 (LocalGuid.Data2);
+ String += 2 * sizeof (LocalGuid.Data2) + 1;
+
+ //
+ // Get gghh in big-endian.
+ //
+ Status = AsciiStrHexToBytes (String, 2 * sizeof (LocalGuid.Data3), (UINT8 *) &LocalGuid.Data3, sizeof (LocalGuid.Data3));
+ if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data3)] != '-') {
+ return RETURN_UNSUPPORTED;
+ }
+ //
+ // Convert big-endian to little-endian.
+ //
+ LocalGuid.Data3 = SwapBytes16 (LocalGuid.Data3);
+ String += 2 * sizeof (LocalGuid.Data3) + 1;
+
+ //
+ // Get iijj.
+ //
+ Status = AsciiStrHexToBytes (String, 2 * 2, &LocalGuid.Data4[0], 2);
+ if (RETURN_ERROR (Status) || String[2 * 2] != '-') {
+ return RETURN_UNSUPPORTED;
+ }
+ String += 2 * 2 + 1;
+
+ //
+ // Get kkllmmnnoopp.
+ //
+ Status = AsciiStrHexToBytes (String, 2 * 6, &LocalGuid.Data4[2], 6);
+ if (RETURN_ERROR (Status)) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ CopyGuid (Guid, &LocalGuid);
+ return RETURN_SUCCESS;
+}
+
+/**
+ Convert a Null-terminated ASCII hexadecimal string to a byte array.
+
+ This function outputs a byte array by interpreting the contents of
+ the ASCII string specified by String in hexadecimal format. The format of
+ the input ASCII string String is:
+
+ [XX]*
+
+ X is a hexadecimal digit character in the range [0-9], [a-f] and [A-F].
+ The function decodes every two hexadecimal digit characters as one byte. The
+ decoding stops after Length of characters and outputs Buffer containing
+ (Length / 2) bytes.
+
+ @param String Pointer to a Null-terminated ASCII string.
+ @param Length The number of ASCII characters to decode.
+ @param Buffer Pointer to the converted bytes array.
+ @param MaxBufferSize The maximum size of Buffer.
+
+ @retval RETURN_SUCCESS Buffer is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If Length is not multiple of 2.
+ If PcdMaximumAsciiStringLength is not zero,
+ and Length is greater than
+ PcdMaximumAsciiStringLength.
+ @retval RETURN_UNSUPPORTED If Length of characters from String contain
+ a character that is not valid hexadecimal
+ digit characters, or a Null-terminator.
+ @retval RETURN_BUFFER_TOO_SMALL If MaxBufferSize is less than (Length / 2).
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrHexToBytes (
+ IN CONST CHAR8 *String,
+ IN UINTN Length,
+ OUT UINT8 *Buffer,
+ IN UINTN MaxBufferSize
+ )
+{
+ UINTN Index;
+
+ //
+ // 1. None of String or Buffer shall be a null pointer.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
+ SAFE_STRING_CONSTRAINT_CHECK ((Buffer != NULL), RETURN_INVALID_PARAMETER);
+
+ //
+ // 2. Length shall not be greater than ASCII_RSIZE_MAX.
+ //
+ if (ASCII_RSIZE_MAX != 0) {
+ SAFE_STRING_CONSTRAINT_CHECK ((Length <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
+ }
+
+ //
+ // 3. Length shall not be odd.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK (((Length & BIT0) == 0), RETURN_INVALID_PARAMETER);
+
+ //
+ // 4. MaxBufferSize shall equal to or greater than Length / 2.
+ //
+ SAFE_STRING_CONSTRAINT_CHECK ((MaxBufferSize >= Length / 2), RETURN_BUFFER_TOO_SMALL);
+
+ //
+ // 5. String shall not contains invalid hexadecimal digits.
+ //
+ for (Index = 0; Index < Length; Index++) {
+ if (!InternalAsciiIsHexaDecimalDigitCharacter (String[Index])) {
+ break;
+ }
+ }
+ if (Index != Length) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ //
+ // Convert the hex string to bytes.
+ //
+ for(Index = 0; Index < Length; Index++) {
+
+ //
+ // For even characters, write the upper nibble for each buffer byte,
+ // and for even characters, the lower nibble.
+ //
+ if ((Index & BIT0) == 0) {
+ Buffer[Index / 2] = (UINT8) InternalAsciiHexCharToUintn (String[Index]) << 4;
+ } else {
+ Buffer[Index / 2] |= (UINT8) InternalAsciiHexCharToUintn (String[Index]);
+ }
+ }
+ return RETURN_SUCCESS;
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/SetJump.c b/roms/edk2/MdePkg/Library/BaseLib/SetJump.c new file mode 100644 index 000000000..516f92f28 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/SetJump.c @@ -0,0 +1,34 @@ +/** @file
+ Internal ASSERT () functions for SetJump.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Worker function that checks ASSERT condition for JumpBuffer
+
+ Checks ASSERT condition for JumpBuffer.
+
+ If JumpBuffer is NULL, then ASSERT().
+ For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
+
+ @param JumpBuffer A pointer to CPU context buffer.
+
+**/
+VOID
+EFIAPI
+InternalAssertJumpBuffer (
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer
+ )
+{
+ ASSERT (JumpBuffer != NULL);
+
+ ASSERT (((UINTN)JumpBuffer & (BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT - 1)) == 0);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/String.c b/roms/edk2/MdePkg/Library/BaseLib/String.c new file mode 100644 index 000000000..45198373f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/String.c @@ -0,0 +1,2270 @@ +/** @file
+ Unicode and ASCII string primitives.
+
+ Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+#ifndef DISABLE_NEW_DEPRECATED_INTERFACES
+
+/**
+ [ATTENTION] This function will be deprecated for security reason.
+
+ Copies one Null-terminated Unicode string to another Null-terminated Unicode
+ string and returns the new Unicode string.
+
+ This function copies the contents of the Unicode string Source to the Unicode
+ string Destination, and returns Destination. If Source and Destination
+ overlap, then the results are undefined.
+
+ If Destination is NULL, then ASSERT().
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().
+ If Source is NULL, then ASSERT().
+ If Source is not aligned on a 16-bit boundary, then ASSERT().
+ If Source and Destination overlap, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and Source contains more than
+ PcdMaximumUnicodeStringLength Unicode characters, not including the
+ Null-terminator, then ASSERT().
+
+ @param Destination A pointer to a Null-terminated Unicode string.
+ @param Source A pointer to a Null-terminated Unicode string.
+
+ @return Destination.
+
+**/
+CHAR16 *
+EFIAPI
+StrCpy (
+ OUT CHAR16 *Destination,
+ IN CONST CHAR16 *Source
+ )
+{
+ CHAR16 *ReturnValue;
+
+ //
+ // Destination cannot be NULL
+ //
+ ASSERT (Destination != NULL);
+ ASSERT (((UINTN) Destination & BIT0) == 0);
+
+ //
+ // Destination and source cannot overlap
+ //
+ ASSERT ((UINTN)(Destination - Source) > StrLen (Source));
+ ASSERT ((UINTN)(Source - Destination) > StrLen (Source));
+
+ ReturnValue = Destination;
+ while (*Source != 0) {
+ *(Destination++) = *(Source++);
+ }
+ *Destination = 0;
+ return ReturnValue;
+}
+
+/**
+ [ATTENTION] This function will be deprecated for security reason.
+
+ Copies up to a specified length from one Null-terminated Unicode string to
+ another Null-terminated Unicode string and returns the new Unicode string.
+
+ This function copies the contents of the Unicode string Source to the Unicode
+ string Destination, and returns Destination. At most, Length Unicode
+ characters are copied from Source to Destination. If Length is 0, then
+ Destination is returned unmodified. If Length is greater that the number of
+ Unicode characters in Source, then Destination is padded with Null Unicode
+ characters. If Source and Destination overlap, then the results are
+ undefined.
+
+ If Length > 0 and Destination is NULL, then ASSERT().
+ If Length > 0 and Destination is not aligned on a 16-bit boundary, then ASSERT().
+ If Length > 0 and Source is NULL, then ASSERT().
+ If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT().
+ If Source and Destination overlap, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and Length is greater than
+ PcdMaximumUnicodeStringLength, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and Source contains more than
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,
+ then ASSERT().
+
+ @param Destination A pointer to a Null-terminated Unicode string.
+ @param Source A pointer to a Null-terminated Unicode string.
+ @param Length The maximum number of Unicode characters to copy.
+
+ @return Destination.
+
+**/
+CHAR16 *
+EFIAPI
+StrnCpy (
+ OUT CHAR16 *Destination,
+ IN CONST CHAR16 *Source,
+ IN UINTN Length
+ )
+{
+ CHAR16 *ReturnValue;
+
+ if (Length == 0) {
+ return Destination;
+ }
+
+ //
+ // Destination cannot be NULL if Length is not zero
+ //
+ ASSERT (Destination != NULL);
+ ASSERT (((UINTN) Destination & BIT0) == 0);
+
+ //
+ // Destination and source cannot overlap
+ //
+ ASSERT ((UINTN)(Destination - Source) > StrLen (Source));
+ ASSERT ((UINTN)(Source - Destination) >= Length);
+
+ if (PcdGet32 (PcdMaximumUnicodeStringLength) != 0) {
+ ASSERT (Length <= PcdGet32 (PcdMaximumUnicodeStringLength));
+ }
+
+ ReturnValue = Destination;
+
+ while ((*Source != L'\0') && (Length > 0)) {
+ *(Destination++) = *(Source++);
+ Length--;
+ }
+
+ ZeroMem (Destination, Length * sizeof (*Destination));
+ return ReturnValue;
+}
+#endif
+
+/**
+ Returns the length of a Null-terminated Unicode string.
+
+ This function returns the number of Unicode characters in the Null-terminated
+ Unicode string specified by String.
+
+ If String is NULL, then ASSERT().
+ If String is not aligned on a 16-bit boundary, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and String contains more than
+ PcdMaximumUnicodeStringLength Unicode characters, not including the
+ Null-terminator, then ASSERT().
+
+ @param String A pointer to a Null-terminated Unicode string.
+
+ @return The length of String.
+
+**/
+UINTN
+EFIAPI
+StrLen (
+ IN CONST CHAR16 *String
+ )
+{
+ UINTN Length;
+
+ ASSERT (String != NULL);
+ ASSERT (((UINTN) String & BIT0) == 0);
+
+ for (Length = 0; *String != L'\0'; String++, Length++) {
+ //
+ // If PcdMaximumUnicodeStringLength is not zero,
+ // length should not more than PcdMaximumUnicodeStringLength
+ //
+ if (PcdGet32 (PcdMaximumUnicodeStringLength) != 0) {
+ ASSERT (Length < PcdGet32 (PcdMaximumUnicodeStringLength));
+ }
+ }
+ return Length;
+}
+
+/**
+ Returns the size of a Null-terminated Unicode string in bytes, including the
+ Null terminator.
+
+ This function returns the size, in bytes, of the Null-terminated Unicode string
+ specified by String.
+
+ If String is NULL, then ASSERT().
+ If String is not aligned on a 16-bit boundary, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and String contains more than
+ PcdMaximumUnicodeStringLength Unicode characters, not including the
+ Null-terminator, then ASSERT().
+
+ @param String A pointer to a Null-terminated Unicode string.
+
+ @return The size of String.
+
+**/
+UINTN
+EFIAPI
+StrSize (
+ IN CONST CHAR16 *String
+ )
+{
+ return (StrLen (String) + 1) * sizeof (*String);
+}
+
+/**
+ Compares two Null-terminated Unicode strings, and returns the difference
+ between the first mismatched Unicode characters.
+
+ This function compares the Null-terminated Unicode string FirstString to the
+ Null-terminated Unicode string SecondString. If FirstString is identical to
+ SecondString, then 0 is returned. Otherwise, the value returned is the first
+ mismatched Unicode character in SecondString subtracted from the first
+ mismatched Unicode character in FirstString.
+
+ If FirstString is NULL, then ASSERT().
+ If FirstString is not aligned on a 16-bit boundary, then ASSERT().
+ If SecondString is NULL, then ASSERT().
+ If SecondString is not aligned on a 16-bit boundary, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and FirstString contains more
+ than PcdMaximumUnicodeStringLength Unicode characters, not including the
+ Null-terminator, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and SecondString contains more
+ than PcdMaximumUnicodeStringLength Unicode characters, not including the
+ Null-terminator, then ASSERT().
+
+ @param FirstString A pointer to a Null-terminated Unicode string.
+ @param SecondString A pointer to a Null-terminated Unicode string.
+
+ @retval 0 FirstString is identical to SecondString.
+ @return others FirstString is not identical to SecondString.
+
+**/
+INTN
+EFIAPI
+StrCmp (
+ IN CONST CHAR16 *FirstString,
+ IN CONST CHAR16 *SecondString
+ )
+{
+ //
+ // ASSERT both strings are less long than PcdMaximumUnicodeStringLength
+ //
+ ASSERT (StrSize (FirstString) != 0);
+ ASSERT (StrSize (SecondString) != 0);
+
+ while ((*FirstString != L'\0') && (*FirstString == *SecondString)) {
+ FirstString++;
+ SecondString++;
+ }
+ return *FirstString - *SecondString;
+}
+
+/**
+ Compares up to a specified length the contents of two Null-terminated Unicode strings,
+ and returns the difference between the first mismatched Unicode characters.
+
+ This function compares the Null-terminated Unicode string FirstString to the
+ Null-terminated Unicode string SecondString. At most, Length Unicode
+ characters will be compared. If Length is 0, then 0 is returned. If
+ FirstString is identical to SecondString, then 0 is returned. Otherwise, the
+ value returned is the first mismatched Unicode character in SecondString
+ subtracted from the first mismatched Unicode character in FirstString.
+
+ If Length > 0 and FirstString is NULL, then ASSERT().
+ If Length > 0 and FirstString is not aligned on a 16-bit boundary, then ASSERT().
+ If Length > 0 and SecondString is NULL, then ASSERT().
+ If Length > 0 and SecondString is not aligned on a 16-bit boundary, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and Length is greater than
+ PcdMaximumUnicodeStringLength, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and FirstString contains more than
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,
+ then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and SecondString contains more than
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,
+ then ASSERT().
+
+ @param FirstString A pointer to a Null-terminated Unicode string.
+ @param SecondString A pointer to a Null-terminated Unicode string.
+ @param Length The maximum number of Unicode characters to compare.
+
+ @retval 0 FirstString is identical to SecondString.
+ @return others FirstString is not identical to SecondString.
+
+**/
+INTN
+EFIAPI
+StrnCmp (
+ IN CONST CHAR16 *FirstString,
+ IN CONST CHAR16 *SecondString,
+ IN UINTN Length
+ )
+{
+ if (Length == 0) {
+ return 0;
+ }
+
+ //
+ // ASSERT both strings are less long than PcdMaximumUnicodeStringLength.
+ // Length tests are performed inside StrLen().
+ //
+ ASSERT (StrSize (FirstString) != 0);
+ ASSERT (StrSize (SecondString) != 0);
+
+ if (PcdGet32 (PcdMaximumUnicodeStringLength) != 0) {
+ ASSERT (Length <= PcdGet32 (PcdMaximumUnicodeStringLength));
+ }
+
+ while ((*FirstString != L'\0') &&
+ (*SecondString != L'\0') &&
+ (*FirstString == *SecondString) &&
+ (Length > 1)) {
+ FirstString++;
+ SecondString++;
+ Length--;
+ }
+
+ return *FirstString - *SecondString;
+}
+
+#ifndef DISABLE_NEW_DEPRECATED_INTERFACES
+
+/**
+ [ATTENTION] This function will be deprecated for security reason.
+
+ Concatenates one Null-terminated Unicode string to another Null-terminated
+ Unicode string, and returns the concatenated Unicode string.
+
+ This function concatenates two Null-terminated Unicode strings. The contents
+ of Null-terminated Unicode string Source are concatenated to the end of
+ Null-terminated Unicode string Destination. The Null-terminated concatenated
+ Unicode String is returned. If Source and Destination overlap, then the
+ results are undefined.
+
+ If Destination is NULL, then ASSERT().
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().
+ If Source is NULL, then ASSERT().
+ If Source is not aligned on a 16-bit boundary, then ASSERT().
+ If Source and Destination overlap, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and Destination contains more
+ than PcdMaximumUnicodeStringLength Unicode characters, not including the
+ Null-terminator, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and Source contains more than
+ PcdMaximumUnicodeStringLength Unicode characters, not including the
+ Null-terminator, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and concatenating Destination
+ and Source results in a Unicode string with more than
+ PcdMaximumUnicodeStringLength Unicode characters, not including the
+ Null-terminator, then ASSERT().
+
+ @param Destination A pointer to a Null-terminated Unicode string.
+ @param Source A pointer to a Null-terminated Unicode string.
+
+ @return Destination.
+
+**/
+CHAR16 *
+EFIAPI
+StrCat (
+ IN OUT CHAR16 *Destination,
+ IN CONST CHAR16 *Source
+ )
+{
+ StrCpy (Destination + StrLen (Destination), Source);
+
+ //
+ // Size of the resulting string should never be zero.
+ // PcdMaximumUnicodeStringLength is tested inside StrLen().
+ //
+ ASSERT (StrSize (Destination) != 0);
+ return Destination;
+}
+
+/**
+ [ATTENTION] This function will be deprecated for security reason.
+
+ Concatenates up to a specified length one Null-terminated Unicode to the end
+ of another Null-terminated Unicode string, and returns the concatenated
+ Unicode string.
+
+ This function concatenates two Null-terminated Unicode strings. The contents
+ of Null-terminated Unicode string Source are concatenated to the end of
+ Null-terminated Unicode string Destination, and Destination is returned. At
+ most, Length Unicode characters are concatenated from Source to the end of
+ Destination, and Destination is always Null-terminated. If Length is 0, then
+ Destination is returned unmodified. If Source and Destination overlap, then
+ the results are undefined.
+
+ If Destination is NULL, then ASSERT().
+ If Length > 0 and Destination is not aligned on a 16-bit boundary, then ASSERT().
+ If Length > 0 and Source is NULL, then ASSERT().
+ If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT().
+ If Source and Destination overlap, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and Length is greater than
+ PcdMaximumUnicodeStringLength, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and Destination contains more
+ than PcdMaximumUnicodeStringLength Unicode characters, not including the
+ Null-terminator, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and Source contains more than
+ PcdMaximumUnicodeStringLength Unicode characters, not including the
+ Null-terminator, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and concatenating Destination
+ and Source results in a Unicode string with more than PcdMaximumUnicodeStringLength
+ Unicode characters, not including the Null-terminator, then ASSERT().
+
+ @param Destination A pointer to a Null-terminated Unicode string.
+ @param Source A pointer to a Null-terminated Unicode string.
+ @param Length The maximum number of Unicode characters to concatenate from
+ Source.
+
+ @return Destination.
+
+**/
+CHAR16 *
+EFIAPI
+StrnCat (
+ IN OUT CHAR16 *Destination,
+ IN CONST CHAR16 *Source,
+ IN UINTN Length
+ )
+{
+ UINTN DestinationLen;
+
+ DestinationLen = StrLen (Destination);
+ StrnCpy (Destination + DestinationLen, Source, Length);
+ Destination[DestinationLen + Length] = L'\0';
+
+ //
+ // Size of the resulting string should never be zero.
+ // PcdMaximumUnicodeStringLength is tested inside StrLen().
+ //
+ ASSERT (StrSize (Destination) != 0);
+ return Destination;
+}
+#endif
+
+/**
+ Returns the first occurrence of a Null-terminated Unicode sub-string
+ in a Null-terminated Unicode string.
+
+ This function scans the contents of the Null-terminated Unicode string
+ specified by String and returns the first occurrence of SearchString.
+ If SearchString is not found in String, then NULL is returned. If
+ the length of SearchString is zero, then String is
+ returned.
+
+ If String is NULL, then ASSERT().
+ If String is not aligned on a 16-bit boundary, then ASSERT().
+ If SearchString is NULL, then ASSERT().
+ If SearchString is not aligned on a 16-bit boundary, then ASSERT().
+
+ If PcdMaximumUnicodeStringLength is not zero, and SearchString
+ or String contains more than PcdMaximumUnicodeStringLength Unicode
+ characters, not including the Null-terminator, then ASSERT().
+
+ @param String A pointer to a Null-terminated Unicode string.
+ @param SearchString A pointer to a Null-terminated Unicode string to search for.
+
+ @retval NULL If the SearchString does not appear in String.
+ @return others If there is a match.
+
+**/
+CHAR16 *
+EFIAPI
+StrStr (
+ IN CONST CHAR16 *String,
+ IN CONST CHAR16 *SearchString
+ )
+{
+ CONST CHAR16 *FirstMatch;
+ CONST CHAR16 *SearchStringTmp;
+
+ //
+ // ASSERT both strings are less long than PcdMaximumUnicodeStringLength.
+ // Length tests are performed inside StrLen().
+ //
+ ASSERT (StrSize (String) != 0);
+ ASSERT (StrSize (SearchString) != 0);
+
+ if (*SearchString == L'\0') {
+ return (CHAR16 *) String;
+ }
+
+ while (*String != L'\0') {
+ SearchStringTmp = SearchString;
+ FirstMatch = String;
+
+ while ((*String == *SearchStringTmp)
+ && (*String != L'\0')) {
+ String++;
+ SearchStringTmp++;
+ }
+
+ if (*SearchStringTmp == L'\0') {
+ return (CHAR16 *) FirstMatch;
+ }
+
+ if (*String == L'\0') {
+ return NULL;
+ }
+
+ String = FirstMatch + 1;
+ }
+
+ return NULL;
+}
+
+/**
+ Check if a Unicode character is a decimal character.
+
+ This internal function checks if a Unicode character is a
+ decimal character. The valid decimal character is from
+ L'0' to L'9'.
+
+ @param Char The character to check against.
+
+ @retval TRUE If the Char is a decmial character.
+ @retval FALSE If the Char is not a decmial character.
+
+**/
+BOOLEAN
+EFIAPI
+InternalIsDecimalDigitCharacter (
+ IN CHAR16 Char
+ )
+{
+ return (BOOLEAN) (Char >= L'0' && Char <= L'9');
+}
+
+/**
+ Convert a Unicode character to upper case only if
+ it maps to a valid small-case ASCII character.
+
+ This internal function only deal with Unicode character
+ which maps to a valid small-case ASCII character, i.e.
+ L'a' to L'z'. For other Unicode character, the input character
+ is returned directly.
+
+ @param Char The character to convert.
+
+ @retval LowerCharacter If the Char is with range L'a' to L'z'.
+ @retval Unchanged Otherwise.
+
+**/
+CHAR16
+EFIAPI
+CharToUpper (
+ IN CHAR16 Char
+ )
+{
+ if (Char >= L'a' && Char <= L'z') {
+ return (CHAR16) (Char - (L'a' - L'A'));
+ }
+
+ return Char;
+}
+
+/**
+ Convert a Unicode character to numerical value.
+
+ This internal function only deal with Unicode character
+ which maps to a valid hexadecimal ASII character, i.e.
+ L'0' to L'9', L'a' to L'f' or L'A' to L'F'. For other
+ Unicode character, the value returned does not make sense.
+
+ @param Char The character to convert.
+
+ @return The numerical value converted.
+
+**/
+UINTN
+EFIAPI
+InternalHexCharToUintn (
+ IN CHAR16 Char
+ )
+{
+ if (InternalIsDecimalDigitCharacter (Char)) {
+ return Char - L'0';
+ }
+
+ return (10 + CharToUpper (Char) - L'A');
+}
+
+/**
+ Check if a Unicode character is a hexadecimal character.
+
+ This internal function checks if a Unicode character is a
+ decimal character. The valid hexadecimal character is
+ L'0' to L'9', L'a' to L'f', or L'A' to L'F'.
+
+
+ @param Char The character to check against.
+
+ @retval TRUE If the Char is a hexadecmial character.
+ @retval FALSE If the Char is not a hexadecmial character.
+
+**/
+BOOLEAN
+EFIAPI
+InternalIsHexaDecimalDigitCharacter (
+ IN CHAR16 Char
+ )
+{
+
+ return (BOOLEAN) (InternalIsDecimalDigitCharacter (Char) ||
+ (Char >= L'A' && Char <= L'F') ||
+ (Char >= L'a' && Char <= L'f'));
+}
+
+/**
+ Convert a Null-terminated Unicode decimal string to a value of
+ type UINTN.
+
+ This function returns a value of type UINTN by interpreting the contents
+ of the Unicode string specified by String as a decimal number. The format
+ of the input Unicode string String is:
+
+ [spaces] [decimal digits].
+
+ The valid decimal digit character is in the range [0-9]. The
+ function will ignore the pad space, which includes spaces or
+ tab characters, before [decimal digits]. The running zero in the
+ beginning of [decimal digits] will be ignored. Then, the function
+ stops at the first character that is a not a valid decimal character
+ or a Null-terminator, whichever one comes first.
+
+ If String is NULL, then ASSERT().
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+ If String has only pad spaces, then 0 is returned.
+ If String has no pad spaces or valid decimal digits,
+ then 0 is returned.
+ If the number represented by String overflows according
+ to the range defined by UINTN, then MAX_UINTN is returned.
+
+ If PcdMaximumUnicodeStringLength is not zero, and String contains
+ more than PcdMaximumUnicodeStringLength Unicode characters, not including
+ the Null-terminator, then ASSERT().
+
+ @param String A pointer to a Null-terminated Unicode string.
+
+ @retval Value translated from String.
+
+**/
+UINTN
+EFIAPI
+StrDecimalToUintn (
+ IN CONST CHAR16 *String
+ )
+{
+ UINTN Result;
+
+ StrDecimalToUintnS (String, (CHAR16 **) NULL, &Result);
+ return Result;
+}
+
+
+/**
+ Convert a Null-terminated Unicode decimal string to a value of
+ type UINT64.
+
+ This function returns a value of type UINT64 by interpreting the contents
+ of the Unicode string specified by String as a decimal number. The format
+ of the input Unicode string String is:
+
+ [spaces] [decimal digits].
+
+ The valid decimal digit character is in the range [0-9]. The
+ function will ignore the pad space, which includes spaces or
+ tab characters, before [decimal digits]. The running zero in the
+ beginning of [decimal digits] will be ignored. Then, the function
+ stops at the first character that is a not a valid decimal character
+ or a Null-terminator, whichever one comes first.
+
+ If String is NULL, then ASSERT().
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+ If String has only pad spaces, then 0 is returned.
+ If String has no pad spaces or valid decimal digits,
+ then 0 is returned.
+ If the number represented by String overflows according
+ to the range defined by UINT64, then MAX_UINT64 is returned.
+
+ If PcdMaximumUnicodeStringLength is not zero, and String contains
+ more than PcdMaximumUnicodeStringLength Unicode characters, not including
+ the Null-terminator, then ASSERT().
+
+ @param String A pointer to a Null-terminated Unicode string.
+
+ @retval Value translated from String.
+
+**/
+UINT64
+EFIAPI
+StrDecimalToUint64 (
+ IN CONST CHAR16 *String
+ )
+{
+ UINT64 Result;
+
+ StrDecimalToUint64S (String, (CHAR16 **) NULL, &Result);
+ return Result;
+}
+
+/**
+ Convert a Null-terminated Unicode hexadecimal string to a value of type UINTN.
+
+ This function returns a value of type UINTN by interpreting the contents
+ of the Unicode string specified by String as a hexadecimal number.
+ The format of the input Unicode string String is:
+
+ [spaces][zeros][x][hexadecimal digits].
+
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix.
+ If "x" appears in the input string, it must be prefixed with at least one 0.
+ The function will ignore the pad space, which includes spaces or tab characters,
+ before [zeros], [x] or [hexadecimal digit]. The running zero before [x] or
+ [hexadecimal digit] will be ignored. Then, the decoding starts after [x] or the
+ first valid hexadecimal digit. Then, the function stops at the first character that is
+ a not a valid hexadecimal character or NULL, whichever one comes first.
+
+ If String is NULL, then ASSERT().
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+ If String has only pad spaces, then zero is returned.
+ If String has no leading pad spaces, leading zeros or valid hexadecimal digits,
+ then zero is returned.
+ If the number represented by String overflows according to the range defined by
+ UINTN, then MAX_UINTN is returned.
+
+ If PcdMaximumUnicodeStringLength is not zero, and String contains more than
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,
+ then ASSERT().
+
+ @param String A pointer to a Null-terminated Unicode string.
+
+ @retval Value translated from String.
+
+**/
+UINTN
+EFIAPI
+StrHexToUintn (
+ IN CONST CHAR16 *String
+ )
+{
+ UINTN Result;
+
+ StrHexToUintnS (String, (CHAR16 **) NULL, &Result);
+ return Result;
+}
+
+
+/**
+ Convert a Null-terminated Unicode hexadecimal string to a value of type UINT64.
+
+ This function returns a value of type UINT64 by interpreting the contents
+ of the Unicode string specified by String as a hexadecimal number.
+ The format of the input Unicode string String is
+
+ [spaces][zeros][x][hexadecimal digits].
+
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix.
+ If "x" appears in the input string, it must be prefixed with at least one 0.
+ The function will ignore the pad space, which includes spaces or tab characters,
+ before [zeros], [x] or [hexadecimal digit]. The running zero before [x] or
+ [hexadecimal digit] will be ignored. Then, the decoding starts after [x] or the
+ first valid hexadecimal digit. Then, the function stops at the first character that is
+ a not a valid hexadecimal character or NULL, whichever one comes first.
+
+ If String is NULL, then ASSERT().
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+ If String has only pad spaces, then zero is returned.
+ If String has no leading pad spaces, leading zeros or valid hexadecimal digits,
+ then zero is returned.
+ If the number represented by String overflows according to the range defined by
+ UINT64, then MAX_UINT64 is returned.
+
+ If PcdMaximumUnicodeStringLength is not zero, and String contains more than
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,
+ then ASSERT().
+
+ @param String A pointer to a Null-terminated Unicode string.
+
+ @retval Value translated from String.
+
+**/
+UINT64
+EFIAPI
+StrHexToUint64 (
+ IN CONST CHAR16 *String
+ )
+{
+ UINT64 Result;
+
+ StrHexToUint64S (String, (CHAR16 **) NULL, &Result);
+ return Result;
+}
+
+/**
+ Check if a ASCII character is a decimal character.
+
+ This internal function checks if a Unicode character is a
+ decimal character. The valid decimal character is from
+ '0' to '9'.
+
+ @param Char The character to check against.
+
+ @retval TRUE If the Char is a decmial character.
+ @retval FALSE If the Char is not a decmial character.
+
+**/
+BOOLEAN
+EFIAPI
+InternalAsciiIsDecimalDigitCharacter (
+ IN CHAR8 Char
+ )
+{
+ return (BOOLEAN) (Char >= '0' && Char <= '9');
+}
+
+/**
+ Check if a ASCII character is a hexadecimal character.
+
+ This internal function checks if a ASCII character is a
+ decimal character. The valid hexadecimal character is
+ L'0' to L'9', L'a' to L'f', or L'A' to L'F'.
+
+
+ @param Char The character to check against.
+
+ @retval TRUE If the Char is a hexadecmial character.
+ @retval FALSE If the Char is not a hexadecmial character.
+
+**/
+BOOLEAN
+EFIAPI
+InternalAsciiIsHexaDecimalDigitCharacter (
+ IN CHAR8 Char
+ )
+{
+
+ return (BOOLEAN) (InternalAsciiIsDecimalDigitCharacter (Char) ||
+ (Char >= 'A' && Char <= 'F') ||
+ (Char >= 'a' && Char <= 'f'));
+}
+
+#ifndef DISABLE_NEW_DEPRECATED_INTERFACES
+
+/**
+ [ATTENTION] This function is deprecated for security reason.
+
+ Convert a Null-terminated Unicode string to a Null-terminated
+ ASCII string and returns the ASCII string.
+
+ This function converts the content of the Unicode string Source
+ to the ASCII string Destination by copying the lower 8 bits of
+ each Unicode character. It returns Destination.
+
+ The caller is responsible to make sure Destination points to a buffer with size
+ equal or greater than ((StrLen (Source) + 1) * sizeof (CHAR8)) in bytes.
+
+ If any Unicode characters in Source contain non-zero value in
+ the upper 8 bits, then ASSERT().
+
+ If Destination is NULL, then ASSERT().
+ If Source is NULL, then ASSERT().
+ If Source is not aligned on a 16-bit boundary, then ASSERT().
+ If Source and Destination overlap, then ASSERT().
+
+ If PcdMaximumUnicodeStringLength is not zero, and Source contains
+ more than PcdMaximumUnicodeStringLength Unicode characters, not including
+ the Null-terminator, then ASSERT().
+
+ If PcdMaximumAsciiStringLength is not zero, and Source contains more
+ than PcdMaximumAsciiStringLength Unicode characters, not including the
+ Null-terminator, then ASSERT().
+
+ @param Source A pointer to a Null-terminated Unicode string.
+ @param Destination A pointer to a Null-terminated ASCII string.
+
+ @return Destination.
+
+**/
+CHAR8 *
+EFIAPI
+UnicodeStrToAsciiStr (
+ IN CONST CHAR16 *Source,
+ OUT CHAR8 *Destination
+ )
+{
+ CHAR8 *ReturnValue;
+
+ ASSERT (Destination != NULL);
+
+ //
+ // ASSERT if Source is long than PcdMaximumUnicodeStringLength.
+ // Length tests are performed inside StrLen().
+ //
+ ASSERT (StrSize (Source) != 0);
+
+ //
+ // Source and Destination should not overlap
+ //
+ ASSERT ((UINTN) (Destination - (CHAR8 *) Source) >= StrSize (Source));
+ ASSERT ((UINTN) ((CHAR8 *) Source - Destination) > StrLen (Source));
+
+
+ ReturnValue = Destination;
+ while (*Source != '\0') {
+ //
+ // If any Unicode characters in Source contain
+ // non-zero value in the upper 8 bits, then ASSERT().
+ //
+ ASSERT (*Source < 0x100);
+ *(Destination++) = (CHAR8) *(Source++);
+ }
+
+ *Destination = '\0';
+
+ //
+ // ASSERT Original Destination is less long than PcdMaximumAsciiStringLength.
+ // Length tests are performed inside AsciiStrLen().
+ //
+ ASSERT (AsciiStrSize (ReturnValue) != 0);
+
+ return ReturnValue;
+}
+
+/**
+ [ATTENTION] This function will be deprecated for security reason.
+
+ Copies one Null-terminated ASCII string to another Null-terminated ASCII
+ string and returns the new ASCII string.
+
+ This function copies the contents of the ASCII string Source to the ASCII
+ string Destination, and returns Destination. If Source and Destination
+ overlap, then the results are undefined.
+
+ If Destination is NULL, then ASSERT().
+ If Source is NULL, then ASSERT().
+ If Source and Destination overlap, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero and Source contains more than
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,
+ then ASSERT().
+
+ @param Destination A pointer to a Null-terminated ASCII string.
+ @param Source A pointer to a Null-terminated ASCII string.
+
+ @return Destination
+
+**/
+CHAR8 *
+EFIAPI
+AsciiStrCpy (
+ OUT CHAR8 *Destination,
+ IN CONST CHAR8 *Source
+ )
+{
+ CHAR8 *ReturnValue;
+
+ //
+ // Destination cannot be NULL
+ //
+ ASSERT (Destination != NULL);
+
+ //
+ // Destination and source cannot overlap
+ //
+ ASSERT ((UINTN)(Destination - Source) > AsciiStrLen (Source));
+ ASSERT ((UINTN)(Source - Destination) > AsciiStrLen (Source));
+
+ ReturnValue = Destination;
+ while (*Source != 0) {
+ *(Destination++) = *(Source++);
+ }
+ *Destination = 0;
+ return ReturnValue;
+}
+
+/**
+ [ATTENTION] This function will be deprecated for security reason.
+
+ Copies up to a specified length one Null-terminated ASCII string to another
+ Null-terminated ASCII string and returns the new ASCII string.
+
+ This function copies the contents of the ASCII string Source to the ASCII
+ string Destination, and returns Destination. At most, Length ASCII characters
+ are copied from Source to Destination. If Length is 0, then Destination is
+ returned unmodified. If Length is greater that the number of ASCII characters
+ in Source, then Destination is padded with Null ASCII characters. If Source
+ and Destination overlap, then the results are undefined.
+
+ If Destination is NULL, then ASSERT().
+ If Source is NULL, then ASSERT().
+ If Source and Destination overlap, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and Length is greater than
+ PcdMaximumAsciiStringLength, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and Source contains more than
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,
+ then ASSERT().
+
+ @param Destination A pointer to a Null-terminated ASCII string.
+ @param Source A pointer to a Null-terminated ASCII string.
+ @param Length The maximum number of ASCII characters to copy.
+
+ @return Destination
+
+**/
+CHAR8 *
+EFIAPI
+AsciiStrnCpy (
+ OUT CHAR8 *Destination,
+ IN CONST CHAR8 *Source,
+ IN UINTN Length
+ )
+{
+ CHAR8 *ReturnValue;
+
+ if (Length == 0) {
+ return Destination;
+ }
+
+ //
+ // Destination cannot be NULL
+ //
+ ASSERT (Destination != NULL);
+
+ //
+ // Destination and source cannot overlap
+ //
+ ASSERT ((UINTN)(Destination - Source) > AsciiStrLen (Source));
+ ASSERT ((UINTN)(Source - Destination) >= Length);
+
+ if (PcdGet32 (PcdMaximumAsciiStringLength) != 0) {
+ ASSERT (Length <= PcdGet32 (PcdMaximumAsciiStringLength));
+ }
+
+ ReturnValue = Destination;
+
+ while (*Source != 0 && Length > 0) {
+ *(Destination++) = *(Source++);
+ Length--;
+ }
+
+ ZeroMem (Destination, Length * sizeof (*Destination));
+ return ReturnValue;
+}
+#endif
+
+/**
+ Returns the length of a Null-terminated ASCII string.
+
+ This function returns the number of ASCII characters in the Null-terminated
+ ASCII string specified by String.
+
+ If Length > 0 and Destination is NULL, then ASSERT().
+ If Length > 0 and Source is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero and String contains more than
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,
+ then ASSERT().
+
+ @param String A pointer to a Null-terminated ASCII string.
+
+ @return The length of String.
+
+**/
+UINTN
+EFIAPI
+AsciiStrLen (
+ IN CONST CHAR8 *String
+ )
+{
+ UINTN Length;
+
+ ASSERT (String != NULL);
+
+ for (Length = 0; *String != '\0'; String++, Length++) {
+ //
+ // If PcdMaximumUnicodeStringLength is not zero,
+ // length should not more than PcdMaximumUnicodeStringLength
+ //
+ if (PcdGet32 (PcdMaximumAsciiStringLength) != 0) {
+ ASSERT (Length < PcdGet32 (PcdMaximumAsciiStringLength));
+ }
+ }
+ return Length;
+}
+
+/**
+ Returns the size of a Null-terminated ASCII string in bytes, including the
+ Null terminator.
+
+ This function returns the size, in bytes, of the Null-terminated ASCII string
+ specified by String.
+
+ If String is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero and String contains more than
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,
+ then ASSERT().
+
+ @param String A pointer to a Null-terminated ASCII string.
+
+ @return The size of String.
+
+**/
+UINTN
+EFIAPI
+AsciiStrSize (
+ IN CONST CHAR8 *String
+ )
+{
+ return (AsciiStrLen (String) + 1) * sizeof (*String);
+}
+
+/**
+ Compares two Null-terminated ASCII strings, and returns the difference
+ between the first mismatched ASCII characters.
+
+ This function compares the Null-terminated ASCII string FirstString to the
+ Null-terminated ASCII string SecondString. If FirstString is identical to
+ SecondString, then 0 is returned. Otherwise, the value returned is the first
+ mismatched ASCII character in SecondString subtracted from the first
+ mismatched ASCII character in FirstString.
+
+ If FirstString is NULL, then ASSERT().
+ If SecondString is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero and FirstString contains more than
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,
+ then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero and SecondString contains more
+ than PcdMaximumAsciiStringLength ASCII characters, not including the
+ Null-terminator, then ASSERT().
+
+ @param FirstString A pointer to a Null-terminated ASCII string.
+ @param SecondString A pointer to a Null-terminated ASCII string.
+
+ @retval ==0 FirstString is identical to SecondString.
+ @retval !=0 FirstString is not identical to SecondString.
+
+**/
+INTN
+EFIAPI
+AsciiStrCmp (
+ IN CONST CHAR8 *FirstString,
+ IN CONST CHAR8 *SecondString
+ )
+{
+ //
+ // ASSERT both strings are less long than PcdMaximumAsciiStringLength
+ //
+ ASSERT (AsciiStrSize (FirstString));
+ ASSERT (AsciiStrSize (SecondString));
+
+ while ((*FirstString != '\0') && (*FirstString == *SecondString)) {
+ FirstString++;
+ SecondString++;
+ }
+
+ return *FirstString - *SecondString;
+}
+
+/**
+ Converts a lowercase Ascii character to upper one.
+
+ If Chr is lowercase Ascii character, then converts it to upper one.
+
+ If Value >= 0xA0, then ASSERT().
+ If (Value & 0x0F) >= 0x0A, then ASSERT().
+
+ @param Chr one Ascii character
+
+ @return The uppercase value of Ascii character
+
+**/
+CHAR8
+EFIAPI
+AsciiCharToUpper (
+ IN CHAR8 Chr
+ )
+{
+ return (UINT8) ((Chr >= 'a' && Chr <= 'z') ? Chr - ('a' - 'A') : Chr);
+}
+
+/**
+ Convert a ASCII character to numerical value.
+
+ This internal function only deal with Unicode character
+ which maps to a valid hexadecimal ASII character, i.e.
+ '0' to '9', 'a' to 'f' or 'A' to 'F'. For other
+ ASCII character, the value returned does not make sense.
+
+ @param Char The character to convert.
+
+ @return The numerical value converted.
+
+**/
+UINTN
+EFIAPI
+InternalAsciiHexCharToUintn (
+ IN CHAR8 Char
+ )
+{
+ if (InternalIsDecimalDigitCharacter (Char)) {
+ return Char - '0';
+ }
+
+ return (10 + AsciiCharToUpper (Char) - 'A');
+}
+
+
+/**
+ Performs a case insensitive comparison of two Null-terminated ASCII strings,
+ and returns the difference between the first mismatched ASCII characters.
+
+ This function performs a case insensitive comparison of the Null-terminated
+ ASCII string FirstString to the Null-terminated ASCII string SecondString. If
+ FirstString is identical to SecondString, then 0 is returned. Otherwise, the
+ value returned is the first mismatched lower case ASCII character in
+ SecondString subtracted from the first mismatched lower case ASCII character
+ in FirstString.
+
+ If FirstString is NULL, then ASSERT().
+ If SecondString is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero and FirstString contains more than
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,
+ then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero and SecondString contains more
+ than PcdMaximumAsciiStringLength ASCII characters, not including the
+ Null-terminator, then ASSERT().
+
+ @param FirstString A pointer to a Null-terminated ASCII string.
+ @param SecondString A pointer to a Null-terminated ASCII string.
+
+ @retval ==0 FirstString is identical to SecondString using case insensitive
+ comparisons.
+ @retval !=0 FirstString is not identical to SecondString using case
+ insensitive comparisons.
+
+**/
+INTN
+EFIAPI
+AsciiStriCmp (
+ IN CONST CHAR8 *FirstString,
+ IN CONST CHAR8 *SecondString
+ )
+{
+ CHAR8 UpperFirstString;
+ CHAR8 UpperSecondString;
+
+ //
+ // ASSERT both strings are less long than PcdMaximumAsciiStringLength
+ //
+ ASSERT (AsciiStrSize (FirstString));
+ ASSERT (AsciiStrSize (SecondString));
+
+ UpperFirstString = AsciiCharToUpper (*FirstString);
+ UpperSecondString = AsciiCharToUpper (*SecondString);
+ while ((*FirstString != '\0') && (*SecondString != '\0') && (UpperFirstString == UpperSecondString)) {
+ FirstString++;
+ SecondString++;
+ UpperFirstString = AsciiCharToUpper (*FirstString);
+ UpperSecondString = AsciiCharToUpper (*SecondString);
+ }
+
+ return UpperFirstString - UpperSecondString;
+}
+
+/**
+ Compares two Null-terminated ASCII strings with maximum lengths, and returns
+ the difference between the first mismatched ASCII characters.
+
+ This function compares the Null-terminated ASCII string FirstString to the
+ Null-terminated ASCII string SecondString. At most, Length ASCII characters
+ will be compared. If Length is 0, then 0 is returned. If FirstString is
+ identical to SecondString, then 0 is returned. Otherwise, the value returned
+ is the first mismatched ASCII character in SecondString subtracted from the
+ first mismatched ASCII character in FirstString.
+
+ If Length > 0 and FirstString is NULL, then ASSERT().
+ If Length > 0 and SecondString is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and Length is greater than
+ PcdMaximumAsciiStringLength, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and FirstString contains more than
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,
+ then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and SecondString contains more than
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,
+ then ASSERT().
+
+ @param FirstString A pointer to a Null-terminated ASCII string.
+ @param SecondString A pointer to a Null-terminated ASCII string.
+ @param Length The maximum number of ASCII characters for compare.
+
+ @retval ==0 FirstString is identical to SecondString.
+ @retval !=0 FirstString is not identical to SecondString.
+
+**/
+INTN
+EFIAPI
+AsciiStrnCmp (
+ IN CONST CHAR8 *FirstString,
+ IN CONST CHAR8 *SecondString,
+ IN UINTN Length
+ )
+{
+ if (Length == 0) {
+ return 0;
+ }
+
+ //
+ // ASSERT both strings are less long than PcdMaximumAsciiStringLength
+ //
+ ASSERT (AsciiStrSize (FirstString));
+ ASSERT (AsciiStrSize (SecondString));
+
+ if (PcdGet32 (PcdMaximumAsciiStringLength) != 0) {
+ ASSERT (Length <= PcdGet32 (PcdMaximumAsciiStringLength));
+ }
+
+ while ((*FirstString != '\0') &&
+ (*SecondString != '\0') &&
+ (*FirstString == *SecondString) &&
+ (Length > 1)) {
+ FirstString++;
+ SecondString++;
+ Length--;
+ }
+ return *FirstString - *SecondString;
+}
+
+#ifndef DISABLE_NEW_DEPRECATED_INTERFACES
+
+/**
+ [ATTENTION] This function will be deprecated for security reason.
+
+ Concatenates one Null-terminated ASCII string to another Null-terminated
+ ASCII string, and returns the concatenated ASCII string.
+
+ This function concatenates two Null-terminated ASCII strings. The contents of
+ Null-terminated ASCII string Source are concatenated to the end of Null-
+ terminated ASCII string Destination. The Null-terminated concatenated ASCII
+ String is returned.
+
+ If Destination is NULL, then ASSERT().
+ If Source is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero and Destination contains more than
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,
+ then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero and Source contains more than
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,
+ then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero and concatenating Destination and
+ Source results in a ASCII string with more than PcdMaximumAsciiStringLength
+ ASCII characters, then ASSERT().
+
+ @param Destination A pointer to a Null-terminated ASCII string.
+ @param Source A pointer to a Null-terminated ASCII string.
+
+ @return Destination
+
+**/
+CHAR8 *
+EFIAPI
+AsciiStrCat (
+ IN OUT CHAR8 *Destination,
+ IN CONST CHAR8 *Source
+ )
+{
+ AsciiStrCpy (Destination + AsciiStrLen (Destination), Source);
+
+ //
+ // Size of the resulting string should never be zero.
+ // PcdMaximumUnicodeStringLength is tested inside StrLen().
+ //
+ ASSERT (AsciiStrSize (Destination) != 0);
+ return Destination;
+}
+
+/**
+ [ATTENTION] This function will be deprecated for security reason.
+
+ Concatenates up to a specified length one Null-terminated ASCII string to
+ the end of another Null-terminated ASCII string, and returns the
+ concatenated ASCII string.
+
+ This function concatenates two Null-terminated ASCII strings. The contents
+ of Null-terminated ASCII string Source are concatenated to the end of Null-
+ terminated ASCII string Destination, and Destination is returned. At most,
+ Length ASCII characters are concatenated from Source to the end of
+ Destination, and Destination is always Null-terminated. If Length is 0, then
+ Destination is returned unmodified. If Source and Destination overlap, then
+ the results are undefined.
+
+ If Length > 0 and Destination is NULL, then ASSERT().
+ If Length > 0 and Source is NULL, then ASSERT().
+ If Source and Destination overlap, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and Length is greater than
+ PcdMaximumAsciiStringLength, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and Destination contains more than
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,
+ then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and Source contains more than
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,
+ then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and concatenating Destination and
+ Source results in a ASCII string with more than PcdMaximumAsciiStringLength
+ ASCII characters, not including the Null-terminator, then ASSERT().
+
+ @param Destination A pointer to a Null-terminated ASCII string.
+ @param Source A pointer to a Null-terminated ASCII string.
+ @param Length The maximum number of ASCII characters to concatenate from
+ Source.
+
+ @return Destination
+
+**/
+CHAR8 *
+EFIAPI
+AsciiStrnCat (
+ IN OUT CHAR8 *Destination,
+ IN CONST CHAR8 *Source,
+ IN UINTN Length
+ )
+{
+ UINTN DestinationLen;
+
+ DestinationLen = AsciiStrLen (Destination);
+ AsciiStrnCpy (Destination + DestinationLen, Source, Length);
+ Destination[DestinationLen + Length] = '\0';
+
+ //
+ // Size of the resulting string should never be zero.
+ // PcdMaximumUnicodeStringLength is tested inside StrLen().
+ //
+ ASSERT (AsciiStrSize (Destination) != 0);
+ return Destination;
+}
+#endif
+
+/**
+ Returns the first occurrence of a Null-terminated ASCII sub-string
+ in a Null-terminated ASCII string.
+
+ This function scans the contents of the ASCII string specified by String
+ and returns the first occurrence of SearchString. If SearchString is not
+ found in String, then NULL is returned. If the length of SearchString is zero,
+ then String is returned.
+
+ If String is NULL, then ASSERT().
+ If SearchString is NULL, then ASSERT().
+
+ If PcdMaximumAsciiStringLength is not zero, and SearchString or
+ String contains more than PcdMaximumAsciiStringLength Unicode characters
+ not including the Null-terminator, then ASSERT().
+
+ @param String A pointer to a Null-terminated ASCII string.
+ @param SearchString A pointer to a Null-terminated ASCII string to search for.
+
+ @retval NULL If the SearchString does not appear in String.
+ @retval others If there is a match return the first occurrence of SearchingString.
+ If the length of SearchString is zero,return String.
+
+**/
+CHAR8 *
+EFIAPI
+AsciiStrStr (
+ IN CONST CHAR8 *String,
+ IN CONST CHAR8 *SearchString
+ )
+{
+ CONST CHAR8 *FirstMatch;
+ CONST CHAR8 *SearchStringTmp;
+
+ //
+ // ASSERT both strings are less long than PcdMaximumAsciiStringLength
+ //
+ ASSERT (AsciiStrSize (String) != 0);
+ ASSERT (AsciiStrSize (SearchString) != 0);
+
+ if (*SearchString == '\0') {
+ return (CHAR8 *) String;
+ }
+
+ while (*String != '\0') {
+ SearchStringTmp = SearchString;
+ FirstMatch = String;
+
+ while ((*String == *SearchStringTmp)
+ && (*String != '\0')) {
+ String++;
+ SearchStringTmp++;
+ }
+
+ if (*SearchStringTmp == '\0') {
+ return (CHAR8 *) FirstMatch;
+ }
+
+ if (*String == '\0') {
+ return NULL;
+ }
+
+ String = FirstMatch + 1;
+ }
+
+ return NULL;
+}
+
+/**
+ Convert a Null-terminated ASCII decimal string to a value of type
+ UINTN.
+
+ This function returns a value of type UINTN by interpreting the contents
+ of the ASCII string String as a decimal number. The format of the input
+ ASCII string String is:
+
+ [spaces] [decimal digits].
+
+ The valid decimal digit character is in the range [0-9]. The function will
+ ignore the pad space, which includes spaces or tab characters, before the digits.
+ The running zero in the beginning of [decimal digits] will be ignored. Then, the
+ function stops at the first character that is a not a valid decimal character or
+ Null-terminator, whichever on comes first.
+
+ If String has only pad spaces, then 0 is returned.
+ If String has no pad spaces or valid decimal digits, then 0 is returned.
+ If the number represented by String overflows according to the range defined by
+ UINTN, then MAX_UINTN is returned.
+ If String is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and String contains more than
+ PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,
+ then ASSERT().
+
+ @param String A pointer to a Null-terminated ASCII string.
+
+ @retval Value translated from String.
+
+**/
+UINTN
+EFIAPI
+AsciiStrDecimalToUintn (
+ IN CONST CHAR8 *String
+ )
+{
+ UINTN Result;
+
+ AsciiStrDecimalToUintnS (String, (CHAR8 **) NULL, &Result);
+ return Result;
+}
+
+
+/**
+ Convert a Null-terminated ASCII decimal string to a value of type
+ UINT64.
+
+ This function returns a value of type UINT64 by interpreting the contents
+ of the ASCII string String as a decimal number. The format of the input
+ ASCII string String is:
+
+ [spaces] [decimal digits].
+
+ The valid decimal digit character is in the range [0-9]. The function will
+ ignore the pad space, which includes spaces or tab characters, before the digits.
+ The running zero in the beginning of [decimal digits] will be ignored. Then, the
+ function stops at the first character that is a not a valid decimal character or
+ Null-terminator, whichever on comes first.
+
+ If String has only pad spaces, then 0 is returned.
+ If String has no pad spaces or valid decimal digits, then 0 is returned.
+ If the number represented by String overflows according to the range defined by
+ UINT64, then MAX_UINT64 is returned.
+ If String is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and String contains more than
+ PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,
+ then ASSERT().
+
+ @param String A pointer to a Null-terminated ASCII string.
+
+ @retval Value translated from String.
+
+**/
+UINT64
+EFIAPI
+AsciiStrDecimalToUint64 (
+ IN CONST CHAR8 *String
+ )
+{
+ UINT64 Result;
+
+ AsciiStrDecimalToUint64S (String, (CHAR8 **) NULL, &Result);
+ return Result;
+}
+
+/**
+ Convert a Null-terminated ASCII hexadecimal string to a value of type UINTN.
+
+ This function returns a value of type UINTN by interpreting the contents of
+ the ASCII string String as a hexadecimal number. The format of the input ASCII
+ string String is:
+
+ [spaces][zeros][x][hexadecimal digits].
+
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. If "x"
+ appears in the input string, it must be prefixed with at least one 0. The function
+ will ignore the pad space, which includes spaces or tab characters, before [zeros],
+ [x] or [hexadecimal digits]. The running zero before [x] or [hexadecimal digits]
+ will be ignored. Then, the decoding starts after [x] or the first valid hexadecimal
+ digit. Then, the function stops at the first character that is a not a valid
+ hexadecimal character or Null-terminator, whichever on comes first.
+
+ If String has only pad spaces, then 0 is returned.
+ If String has no leading pad spaces, leading zeros or valid hexadecimal digits, then
+ 0 is returned.
+
+ If the number represented by String overflows according to the range defined by UINTN,
+ then MAX_UINTN is returned.
+ If String is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero,
+ and String contains more than PcdMaximumAsciiStringLength ASCII characters not including
+ the Null-terminator, then ASSERT().
+
+ @param String A pointer to a Null-terminated ASCII string.
+
+ @retval Value translated from String.
+
+**/
+UINTN
+EFIAPI
+AsciiStrHexToUintn (
+ IN CONST CHAR8 *String
+ )
+{
+ UINTN Result;
+
+ AsciiStrHexToUintnS (String, (CHAR8 **) NULL, &Result);
+ return Result;
+}
+
+
+/**
+ Convert a Null-terminated ASCII hexadecimal string to a value of type UINT64.
+
+ This function returns a value of type UINT64 by interpreting the contents of
+ the ASCII string String as a hexadecimal number. The format of the input ASCII
+ string String is:
+
+ [spaces][zeros][x][hexadecimal digits].
+
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. If "x"
+ appears in the input string, it must be prefixed with at least one 0. The function
+ will ignore the pad space, which includes spaces or tab characters, before [zeros],
+ [x] or [hexadecimal digits]. The running zero before [x] or [hexadecimal digits]
+ will be ignored. Then, the decoding starts after [x] or the first valid hexadecimal
+ digit. Then, the function stops at the first character that is a not a valid
+ hexadecimal character or Null-terminator, whichever on comes first.
+
+ If String has only pad spaces, then 0 is returned.
+ If String has no leading pad spaces, leading zeros or valid hexadecimal digits, then
+ 0 is returned.
+
+ If the number represented by String overflows according to the range defined by UINT64,
+ then MAX_UINT64 is returned.
+ If String is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero,
+ and String contains more than PcdMaximumAsciiStringLength ASCII characters not including
+ the Null-terminator, then ASSERT().
+
+ @param String A pointer to a Null-terminated ASCII string.
+
+ @retval Value translated from String.
+
+**/
+UINT64
+EFIAPI
+AsciiStrHexToUint64 (
+ IN CONST CHAR8 *String
+ )
+{
+ UINT64 Result;
+
+ AsciiStrHexToUint64S (String, (CHAR8 **) NULL, &Result);
+ return Result;
+}
+
+#ifndef DISABLE_NEW_DEPRECATED_INTERFACES
+
+/**
+ [ATTENTION] This function is deprecated for security reason.
+
+ Convert one Null-terminated ASCII string to a Null-terminated
+ Unicode string and returns the Unicode string.
+
+ This function converts the contents of the ASCII string Source to the Unicode
+ string Destination, and returns Destination. The function terminates the
+ Unicode string Destination by appending a Null-terminator character at the end.
+ The caller is responsible to make sure Destination points to a buffer with size
+ equal or greater than ((AsciiStrLen (Source) + 1) * sizeof (CHAR16)) in bytes.
+
+ If Destination is NULL, then ASSERT().
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().
+ If Source is NULL, then ASSERT().
+ If Source and Destination overlap, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and Source contains more than
+ PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,
+ then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and Source contains more than
+ PcdMaximumUnicodeStringLength ASCII characters not including the
+ Null-terminator, then ASSERT().
+
+ @param Source A pointer to a Null-terminated ASCII string.
+ @param Destination A pointer to a Null-terminated Unicode string.
+
+ @return Destination.
+
+**/
+CHAR16 *
+EFIAPI
+AsciiStrToUnicodeStr (
+ IN CONST CHAR8 *Source,
+ OUT CHAR16 *Destination
+ )
+{
+ CHAR16 *ReturnValue;
+
+ ASSERT (Destination != NULL);
+
+ //
+ // ASSERT Source is less long than PcdMaximumAsciiStringLength
+ //
+ ASSERT (AsciiStrSize (Source) != 0);
+
+ //
+ // Source and Destination should not overlap
+ //
+ ASSERT ((UINTN) ((CHAR8 *) Destination - Source) > AsciiStrLen (Source));
+ ASSERT ((UINTN) (Source - (CHAR8 *) Destination) >= (AsciiStrSize (Source) * sizeof (CHAR16)));
+
+
+ ReturnValue = Destination;
+ while (*Source != '\0') {
+ *(Destination++) = (CHAR16)(UINT8) *(Source++);
+ }
+ //
+ // End the Destination with a NULL.
+ //
+ *Destination = '\0';
+
+ //
+ // ASSERT Original Destination is less long than PcdMaximumUnicodeStringLength
+ //
+ ASSERT (StrSize (ReturnValue) != 0);
+
+ return ReturnValue;
+}
+
+#endif
+
+STATIC CHAR8 EncodingTable[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
+ "abcdefghijklmnopqrstuvwxyz"
+ "0123456789+/";
+
+/**
+ Convert binary data to a Base64 encoded ascii string based on RFC4648.
+
+ Produce a Null-terminated Ascii string in the output buffer specified by Destination and DestinationSize.
+ The Ascii string is produced by converting the data string specified by Source and SourceLength.
+
+ @param Source Input UINT8 data
+ @param SourceLength Number of UINT8 bytes of data
+ @param Destination Pointer to output string buffer
+ @param DestinationSize Size of ascii buffer. Set to 0 to get the size needed.
+ Caller is responsible for passing in buffer of DestinationSize
+
+ @retval RETURN_SUCCESS When ascii buffer is filled in.
+ @retval RETURN_INVALID_PARAMETER If Source is NULL or DestinationSize is NULL.
+ @retval RETURN_INVALID_PARAMETER If SourceLength or DestinationSize is bigger than (MAX_ADDRESS - (UINTN)Destination).
+ @retval RETURN_BUFFER_TOO_SMALL If SourceLength is 0 and DestinationSize is <1.
+ @retval RETURN_BUFFER_TOO_SMALL If Destination is NULL or DestinationSize is smaller than required buffersize.
+
+**/
+RETURN_STATUS
+EFIAPI
+Base64Encode (
+ IN CONST UINT8 *Source,
+ IN UINTN SourceLength,
+ OUT CHAR8 *Destination OPTIONAL,
+ IN OUT UINTN *DestinationSize
+ )
+{
+
+ UINTN RequiredSize;
+ UINTN Left;
+
+ //
+ // Check pointers, and SourceLength is valid
+ //
+ if ((Source == NULL) || (DestinationSize == NULL)) {
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ //
+ // Allow for RFC 4648 test vector 1
+ //
+ if (SourceLength == 0) {
+ if (*DestinationSize < 1) {
+ *DestinationSize = 1;
+ return RETURN_BUFFER_TOO_SMALL;
+ }
+ *DestinationSize = 1;
+ *Destination = '\0';
+ return RETURN_SUCCESS;
+ }
+
+ //
+ // Check if SourceLength or DestinationSize is valid
+ //
+ if ((SourceLength >= (MAX_ADDRESS - (UINTN)Source)) || (*DestinationSize >= (MAX_ADDRESS - (UINTN)Destination))){
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ //
+ // 4 ascii per 3 bytes + NULL
+ //
+ RequiredSize = ((SourceLength + 2) / 3) * 4 + 1;
+ if ((Destination == NULL) || *DestinationSize < RequiredSize) {
+ *DestinationSize = RequiredSize;
+ return RETURN_BUFFER_TOO_SMALL;
+ }
+
+ Left = SourceLength;
+
+ //
+ // Encode 24 bits (three bytes) into 4 ascii characters
+ //
+ while (Left >= 3) {
+
+ *Destination++ = EncodingTable[( Source[0] & 0xfc) >> 2 ];
+ *Destination++ = EncodingTable[((Source[0] & 0x03) << 4) + ((Source[1] & 0xf0) >> 4)];
+ *Destination++ = EncodingTable[((Source[1] & 0x0f) << 2) + ((Source[2] & 0xc0) >> 6)];
+ *Destination++ = EncodingTable[( Source[2] & 0x3f)];
+ Left -= 3;
+ Source += 3;
+ }
+
+ //
+ // Handle the remainder, and add padding '=' characters as necessary.
+ //
+ switch (Left) {
+ case 0:
+
+ //
+ // No bytes Left, done.
+ //
+ break;
+ case 1:
+
+ //
+ // One more data byte, two pad characters
+ //
+ *Destination++ = EncodingTable[( Source[0] & 0xfc) >> 2];
+ *Destination++ = EncodingTable[((Source[0] & 0x03) << 4)];
+ *Destination++ = '=';
+ *Destination++ = '=';
+ break;
+ case 2:
+
+ //
+ // Two more data bytes, and one pad character
+ //
+ *Destination++ = EncodingTable[( Source[0] & 0xfc) >> 2];
+ *Destination++ = EncodingTable[((Source[0] & 0x03) << 4) + ((Source[1] & 0xf0) >> 4)];
+ *Destination++ = EncodingTable[((Source[1] & 0x0f) << 2)];
+ *Destination++ = '=';
+ break;
+ }
+ //
+ // Add terminating NULL
+ //
+ *Destination = '\0';
+ return RETURN_SUCCESS;
+}
+
+/**
+ Decode Base64 ASCII encoded data to 8-bit binary representation, based on
+ RFC4648.
+
+ Decoding occurs according to "Table 1: The Base 64 Alphabet" in RFC4648.
+
+ Whitespace is ignored at all positions:
+ - 0x09 ('\t') horizontal tab
+ - 0x0A ('\n') new line
+ - 0x0B ('\v') vertical tab
+ - 0x0C ('\f') form feed
+ - 0x0D ('\r') carriage return
+ - 0x20 (' ') space
+
+ The minimum amount of required padding (with ASCII 0x3D, '=') is tolerated
+ and enforced at the end of the Base64 ASCII encoded data, and only there.
+
+ Other characters outside of the encoding alphabet cause the function to
+ reject the Base64 ASCII encoded data.
+
+ @param[in] Source Array of CHAR8 elements containing the Base64
+ ASCII encoding. May be NULL if SourceSize is
+ zero.
+
+ @param[in] SourceSize Number of CHAR8 elements in Source.
+
+ @param[out] Destination Array of UINT8 elements receiving the decoded
+ 8-bit binary representation. Allocated by the
+ caller. May be NULL if DestinationSize is
+ zero on input. If NULL, decoding is
+ performed, but the 8-bit binary
+ representation is not stored. If non-NULL and
+ the function returns an error, the contents
+ of Destination are indeterminate.
+
+ @param[in,out] DestinationSize On input, the number of UINT8 elements that
+ the caller allocated for Destination. On
+ output, if the function returns
+ RETURN_SUCCESS or RETURN_BUFFER_TOO_SMALL,
+ the number of UINT8 elements that are
+ required for decoding the Base64 ASCII
+ representation. If the function returns a
+ value different from both RETURN_SUCCESS and
+ RETURN_BUFFER_TOO_SMALL, then DestinationSize
+ is indeterminate on output.
+
+ @retval RETURN_SUCCESS SourceSize CHAR8 elements at Source have
+ been decoded to on-output DestinationSize
+ UINT8 elements at Destination. Note that
+ RETURN_SUCCESS covers the case when
+ DestinationSize is zero on input, and
+ Source decodes to zero bytes (due to
+ containing at most ignored whitespace).
+
+ @retval RETURN_BUFFER_TOO_SMALL The input value of DestinationSize is not
+ large enough for decoding SourceSize CHAR8
+ elements at Source. The required number of
+ UINT8 elements has been stored to
+ DestinationSize.
+
+ @retval RETURN_INVALID_PARAMETER DestinationSize is NULL.
+
+ @retval RETURN_INVALID_PARAMETER Source is NULL, but SourceSize is not zero.
+
+ @retval RETURN_INVALID_PARAMETER Destination is NULL, but DestinationSize is
+ not zero on input.
+
+ @retval RETURN_INVALID_PARAMETER Source is non-NULL, and (Source +
+ SourceSize) would wrap around MAX_ADDRESS.
+
+ @retval RETURN_INVALID_PARAMETER Destination is non-NULL, and (Destination +
+ DestinationSize) would wrap around
+ MAX_ADDRESS, as specified on input.
+
+ @retval RETURN_INVALID_PARAMETER None of Source and Destination are NULL,
+ and CHAR8[SourceSize] at Source overlaps
+ UINT8[DestinationSize] at Destination, as
+ specified on input.
+
+ @retval RETURN_INVALID_PARAMETER Invalid CHAR8 element encountered in
+ Source.
+**/
+RETURN_STATUS
+EFIAPI
+Base64Decode (
+ IN CONST CHAR8 *Source OPTIONAL,
+ IN UINTN SourceSize,
+ OUT UINT8 *Destination OPTIONAL,
+ IN OUT UINTN *DestinationSize
+ )
+{
+ BOOLEAN PaddingMode;
+ UINTN SixBitGroupsConsumed;
+ UINT32 Accumulator;
+ UINTN OriginalDestinationSize;
+ UINTN SourceIndex;
+ CHAR8 SourceChar;
+ UINT32 Base64Value;
+ UINT8 DestinationOctet;
+
+ if (DestinationSize == NULL) {
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ //
+ // Check Source array validity.
+ //
+ if (Source == NULL) {
+ if (SourceSize > 0) {
+ //
+ // At least one CHAR8 element at NULL Source.
+ //
+ return RETURN_INVALID_PARAMETER;
+ }
+ } else if (SourceSize > MAX_ADDRESS - (UINTN)Source) {
+ //
+ // Non-NULL Source, but it wraps around.
+ //
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ //
+ // Check Destination array validity.
+ //
+ if (Destination == NULL) {
+ if (*DestinationSize > 0) {
+ //
+ // At least one UINT8 element at NULL Destination.
+ //
+ return RETURN_INVALID_PARAMETER;
+ }
+ } else if (*DestinationSize > MAX_ADDRESS - (UINTN)Destination) {
+ //
+ // Non-NULL Destination, but it wraps around.
+ //
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ //
+ // Check for overlap.
+ //
+ if (Source != NULL && Destination != NULL) {
+ //
+ // Both arrays have been provided, and we know from earlier that each array
+ // is valid in itself.
+ //
+ if ((UINTN)Source + SourceSize <= (UINTN)Destination) {
+ //
+ // Source array precedes Destination array, OK.
+ //
+ } else if ((UINTN)Destination + *DestinationSize <= (UINTN)Source) {
+ //
+ // Destination array precedes Source array, OK.
+ //
+ } else {
+ //
+ // Overlap.
+ //
+ return RETURN_INVALID_PARAMETER;
+ }
+ }
+
+ //
+ // Decoding loop setup.
+ //
+ PaddingMode = FALSE;
+ SixBitGroupsConsumed = 0;
+ Accumulator = 0;
+ OriginalDestinationSize = *DestinationSize;
+ *DestinationSize = 0;
+
+ //
+ // Decoding loop.
+ //
+ for (SourceIndex = 0; SourceIndex < SourceSize; SourceIndex++) {
+ SourceChar = Source[SourceIndex];
+
+ //
+ // Whitespace is ignored at all positions (regardless of padding mode).
+ //
+ if (SourceChar == '\t' || SourceChar == '\n' || SourceChar == '\v' ||
+ SourceChar == '\f' || SourceChar == '\r' || SourceChar == ' ') {
+ continue;
+ }
+
+ //
+ // If we're in padding mode, accept another padding character, as long as
+ // that padding character completes the quantum. This completes case (2)
+ // from RFC4648, Chapter 4. "Base 64 Encoding":
+ //
+ // (2) The final quantum of encoding input is exactly 8 bits; here, the
+ // final unit of encoded output will be two characters followed by two
+ // "=" padding characters.
+ //
+ if (PaddingMode) {
+ if (SourceChar == '=' && SixBitGroupsConsumed == 3) {
+ SixBitGroupsConsumed = 0;
+ continue;
+ }
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ //
+ // When not in padding mode, decode Base64Value based on RFC4648, "Table 1:
+ // The Base 64 Alphabet".
+ //
+ if ('A' <= SourceChar && SourceChar <= 'Z') {
+ Base64Value = SourceChar - 'A';
+ } else if ('a' <= SourceChar && SourceChar <= 'z') {
+ Base64Value = 26 + (SourceChar - 'a');
+ } else if ('0' <= SourceChar && SourceChar <= '9') {
+ Base64Value = 52 + (SourceChar - '0');
+ } else if (SourceChar == '+') {
+ Base64Value = 62;
+ } else if (SourceChar == '/') {
+ Base64Value = 63;
+ } else if (SourceChar == '=') {
+ //
+ // Enter padding mode.
+ //
+ PaddingMode = TRUE;
+
+ if (SixBitGroupsConsumed == 2) {
+ //
+ // If we have consumed two 6-bit groups from the current quantum before
+ // encountering the first padding character, then this is case (2) from
+ // RFC4648, Chapter 4. "Base 64 Encoding". Bump SixBitGroupsConsumed,
+ // and we'll enforce another padding character.
+ //
+ SixBitGroupsConsumed = 3;
+ } else if (SixBitGroupsConsumed == 3) {
+ //
+ // If we have consumed three 6-bit groups from the current quantum
+ // before encountering the first padding character, then this is case
+ // (3) from RFC4648, Chapter 4. "Base 64 Encoding". The quantum is now
+ // complete.
+ //
+ SixBitGroupsConsumed = 0;
+ } else {
+ //
+ // Padding characters are not allowed at the first two positions of a
+ // quantum.
+ //
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ //
+ // Wherever in a quantum we enter padding mode, we enforce the padding
+ // bits pending in the accumulator -- from the last 6-bit group just
+ // preceding the padding character -- to be zero. Refer to RFC4648,
+ // Chapter 3.5. "Canonical Encoding".
+ //
+ if (Accumulator != 0) {
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ //
+ // Advance to the next source character.
+ //
+ continue;
+ } else {
+ //
+ // Other characters outside of the encoding alphabet are rejected.
+ //
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ //
+ // Feed the bits of the current 6-bit group of the quantum to the
+ // accumulator.
+ //
+ Accumulator = (Accumulator << 6) | Base64Value;
+ SixBitGroupsConsumed++;
+ switch (SixBitGroupsConsumed) {
+ case 1:
+ //
+ // No octet to spill after consuming the first 6-bit group of the
+ // quantum; advance to the next source character.
+ //
+ continue;
+ case 2:
+ //
+ // 12 bits accumulated (6 pending + 6 new); prepare for spilling an
+ // octet. 4 bits remain pending.
+ //
+ DestinationOctet = (UINT8)(Accumulator >> 4);
+ Accumulator &= 0xF;
+ break;
+ case 3:
+ //
+ // 10 bits accumulated (4 pending + 6 new); prepare for spilling an
+ // octet. 2 bits remain pending.
+ //
+ DestinationOctet = (UINT8)(Accumulator >> 2);
+ Accumulator &= 0x3;
+ break;
+ default:
+ ASSERT (SixBitGroupsConsumed == 4);
+ //
+ // 8 bits accumulated (2 pending + 6 new); prepare for spilling an octet.
+ // The quantum is complete, 0 bits remain pending.
+ //
+ DestinationOctet = (UINT8)Accumulator;
+ Accumulator = 0;
+ SixBitGroupsConsumed = 0;
+ break;
+ }
+
+ //
+ // Store the decoded octet if there's room left. Increment
+ // (*DestinationSize) unconditionally.
+ //
+ if (*DestinationSize < OriginalDestinationSize) {
+ ASSERT (Destination != NULL);
+ Destination[*DestinationSize] = DestinationOctet;
+ }
+ (*DestinationSize)++;
+
+ //
+ // Advance to the next source character.
+ //
+ }
+
+ //
+ // If Source terminates mid-quantum, then Source is invalid.
+ //
+ if (SixBitGroupsConsumed != 0) {
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ //
+ // Done.
+ //
+ if (*DestinationSize <= OriginalDestinationSize) {
+ return RETURN_SUCCESS;
+ }
+ return RETURN_BUFFER_TOO_SMALL;
+}
+
+/**
+ Converts an 8-bit value to an 8-bit BCD value.
+
+ Converts the 8-bit value specified by Value to BCD. The BCD value is
+ returned.
+
+ If Value >= 100, then ASSERT().
+
+ @param Value The 8-bit value to convert to BCD. Range 0..99.
+
+ @return The BCD value.
+
+**/
+UINT8
+EFIAPI
+DecimalToBcd8 (
+ IN UINT8 Value
+ )
+{
+ ASSERT (Value < 100);
+ return (UINT8) (((Value / 10) << 4) | (Value % 10));
+}
+
+/**
+ Converts an 8-bit BCD value to an 8-bit value.
+
+ Converts the 8-bit BCD value specified by Value to an 8-bit value. The 8-bit
+ value is returned.
+
+ If Value >= 0xA0, then ASSERT().
+ If (Value & 0x0F) >= 0x0A, then ASSERT().
+
+ @param Value The 8-bit BCD value to convert to an 8-bit value.
+
+ @return The 8-bit value is returned.
+
+**/
+UINT8
+EFIAPI
+BcdToDecimal8 (
+ IN UINT8 Value
+ )
+{
+ ASSERT (Value < 0xa0);
+ ASSERT ((Value & 0xf) < 0xa);
+ return (UINT8) ((Value >> 4) * 10 + (Value & 0xf));
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/SwapBytes16.c b/roms/edk2/MdePkg/Library/BaseLib/SwapBytes16.c new file mode 100644 index 000000000..52e7f71d2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/SwapBytes16.c @@ -0,0 +1,33 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Switches the endianess of a 16-bit integer.
+
+ This function swaps the bytes in a 16-bit unsigned value to switch the value
+ from little endian to big endian or vice versa. The byte swapped value is
+ returned.
+
+ @param Value A 16-bit unsigned value.
+
+ @return The byte swapped Value.
+
+**/
+UINT16
+EFIAPI
+SwapBytes16 (
+ IN UINT16 Value
+ )
+{
+ return (UINT16) ((Value<< 8) | (Value>> 8));
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/SwapBytes32.c b/roms/edk2/MdePkg/Library/BaseLib/SwapBytes32.c new file mode 100644 index 000000000..5109ad512 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/SwapBytes32.c @@ -0,0 +1,39 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Switches the endianess of a 32-bit integer.
+
+ This function swaps the bytes in a 32-bit unsigned value to switch the value
+ from little endian to big endian or vice versa. The byte swapped value is
+ returned.
+
+ @param Value A 32-bit unsigned value.
+
+ @return The byte swapped Value.
+
+**/
+UINT32
+EFIAPI
+SwapBytes32 (
+ IN UINT32 Value
+ )
+{
+ UINT32 LowerBytes;
+ UINT32 HigherBytes;
+
+ LowerBytes = (UINT32) SwapBytes16 ((UINT16) Value);
+ HigherBytes = (UINT32) SwapBytes16 ((UINT16) (Value >> 16));
+
+ return (LowerBytes << 16 | HigherBytes);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/SwapBytes64.c b/roms/edk2/MdePkg/Library/BaseLib/SwapBytes64.c new file mode 100644 index 000000000..500f76d48 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/SwapBytes64.c @@ -0,0 +1,33 @@ +/** @file
+ Math worker functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Switches the endianess of a 64-bit integer.
+
+ This function swaps the bytes in a 64-bit unsigned value to switch the value
+ from little endian to big endian or vice versa. The byte swapped value is
+ returned.
+
+ @param Value A 64-bit unsigned value.
+
+ @return The byte swapped Value.
+
+**/
+UINT64
+EFIAPI
+SwapBytes64 (
+ IN UINT64 Value
+ )
+{
+ return InternalMathSwapBytes64 (Value);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/SwitchStack.c b/roms/edk2/MdePkg/Library/BaseLib/SwitchStack.c new file mode 100644 index 000000000..cb9f69f1e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/SwitchStack.c @@ -0,0 +1,70 @@ +/** @file
+ Switch Stack functions.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Transfers control to a function starting with a new stack.
+
+ Transfers control to the function specified by EntryPoint using the
+ new stack specified by NewStack and passing in the parameters specified
+ by Context1 and Context2. Context1 and Context2 are optional and may
+ be NULL. The function EntryPoint must never return. This function
+ supports a variable number of arguments following the NewStack parameter.
+ These additional arguments are ignored on IA-32, x64, and EBC.
+ IPF CPUs expect one additional parameter of type VOID * that specifies
+ the new backing store pointer.
+
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ @param EntryPoint A pointer to function to call with the new stack.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function.
+ @param ... This variable argument list is ignored for IA32, x64, and EBC.
+ For IPF, this variable argument list is expected to contain
+ a single parameter of type VOID * that specifies the new backing
+ store pointer.
+
+
+**/
+VOID
+EFIAPI
+SwitchStack (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack,
+ ...
+ )
+{
+ VA_LIST Marker;
+
+ ASSERT (EntryPoint != NULL);
+ ASSERT (NewStack != NULL);
+
+ //
+ // New stack must be aligned with CPU_STACK_ALIGNMENT
+ //
+ ASSERT (((UINTN)NewStack & (CPU_STACK_ALIGNMENT - 1)) == 0);
+
+ VA_START (Marker, NewStack);
+
+ InternalSwitchStack (EntryPoint, Context1, Context2, NewStack, Marker);
+
+ VA_END (Marker);
+
+ //
+ // InternalSwitchStack () will never return
+ //
+ ASSERT (FALSE);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/Unaligned.c b/roms/edk2/MdePkg/Library/BaseLib/Unaligned.c new file mode 100644 index 000000000..a419cb85e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/Unaligned.c @@ -0,0 +1,216 @@ +/** @file
+ Unaligned access functions of BaseLib.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+
+/**
+ Reads a 16-bit value from memory that may be unaligned.
+
+ This function returns the 16-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer A pointer to a 16-bit value that may be unaligned.
+
+ @return The 16-bit value read from Buffer.
+
+**/
+UINT16
+EFIAPI
+ReadUnaligned16 (
+ IN CONST UINT16 *Buffer
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ return *Buffer;
+}
+
+/**
+ Writes a 16-bit value to memory that may be unaligned.
+
+ This function writes the 16-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer A pointer to a 16-bit value that may be unaligned.
+ @param Value 16-bit value to write to Buffer.
+
+ @return The 16-bit value to write to Buffer.
+
+**/
+UINT16
+EFIAPI
+WriteUnaligned16 (
+ OUT UINT16 *Buffer,
+ IN UINT16 Value
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ return *Buffer = Value;
+}
+
+/**
+ Reads a 24-bit value from memory that may be unaligned.
+
+ This function returns the 24-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer A pointer to a 24-bit value that may be unaligned.
+
+ @return The 24-bit value read from Buffer.
+
+**/
+UINT32
+EFIAPI
+ReadUnaligned24 (
+ IN CONST UINT32 *Buffer
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ return *Buffer & 0xffffff;
+}
+
+/**
+ Writes a 24-bit value to memory that may be unaligned.
+
+ This function writes the 24-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer A pointer to a 24-bit value that may be unaligned.
+ @param Value 24-bit value to write to Buffer.
+
+ @return The 24-bit value to write to Buffer.
+
+**/
+UINT32
+EFIAPI
+WriteUnaligned24 (
+ OUT UINT32 *Buffer,
+ IN UINT32 Value
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ *Buffer = BitFieldWrite32 (*Buffer, 0, 23, Value);
+ return Value;
+}
+
+/**
+ Reads a 32-bit value from memory that may be unaligned.
+
+ This function returns the 32-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer A pointer to a 32-bit value that may be unaligned.
+
+ @return The 32-bit value read from Buffer.
+
+**/
+UINT32
+EFIAPI
+ReadUnaligned32 (
+ IN CONST UINT32 *Buffer
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ return *Buffer;
+}
+
+/**
+ Writes a 32-bit value to memory that may be unaligned.
+
+ This function writes the 32-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer A pointer to a 32-bit value that may be unaligned.
+ @param Value The 32-bit value to write to Buffer.
+
+ @return The 32-bit value to write to Buffer.
+
+**/
+UINT32
+EFIAPI
+WriteUnaligned32 (
+ OUT UINT32 *Buffer,
+ IN UINT32 Value
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ return *Buffer = Value;
+}
+
+/**
+ Reads a 64-bit value from memory that may be unaligned.
+
+ This function returns the 64-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer A pointer to a 64-bit value that may be unaligned.
+
+ @return The 64-bit value read from Buffer.
+
+**/
+UINT64
+EFIAPI
+ReadUnaligned64 (
+ IN CONST UINT64 *Buffer
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ return *Buffer;
+}
+
+/**
+ Writes a 64-bit value to memory that may be unaligned.
+
+ This function writes the 64-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer A pointer to a 64-bit value that may be unaligned.
+ @param Value The 64-bit value to write to Buffer.
+
+ @return The 64-bit value to write to Buffer.
+
+**/
+UINT64
+EFIAPI
+WriteUnaligned64 (
+ OUT UINT64 *Buffer,
+ IN UINT64 Value
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ return *Buffer = Value;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/UnitTestHost.c b/roms/edk2/MdePkg/Library/BaseLib/UnitTestHost.c new file mode 100644 index 000000000..79eec7cac --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/UnitTestHost.c @@ -0,0 +1,140 @@ +/** @file
+ Common Unit Test Host functions.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "UnitTestHost.h"
+
+///
+/// Module global variable for simple system emulation of interrupt state
+///
+STATIC BOOLEAN mUnitTestHostBaseLibInterruptState;
+
+/**
+ Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibEnableInterrupts (
+ VOID
+ )
+{
+ mUnitTestHostBaseLibInterruptState = TRUE;
+}
+
+/**
+ Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibDisableInterrupts (
+ VOID
+ )
+{
+ mUnitTestHostBaseLibInterruptState = FALSE;
+}
+
+/**
+ Enables CPU interrupts for the smallest window required to capture any
+ pending interrupts.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibEnableDisableInterrupts (
+ VOID
+ )
+{
+ mUnitTestHostBaseLibInterruptState = FALSE;
+}
+
+/**
+ Set the current CPU interrupt state.
+
+ Sets the current CPU interrupt state to the state specified by
+ InterruptState. If InterruptState is TRUE, then interrupts are enabled. If
+ InterruptState is FALSE, then interrupts are disabled. InterruptState is
+ returned.
+
+ @param InterruptState TRUE if interrupts should enabled. FALSE if
+ interrupts should be disabled.
+
+ @return InterruptState
+
+**/
+BOOLEAN
+EFIAPI
+UnitTestHostBaseLibGetInterruptState (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibInterruptState;
+}
+
+/**
+ Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+EnableInterrupts (
+ VOID
+ )
+{
+ gUnitTestHostBaseLib.Common->EnableInterrupts ();
+}
+
+/**
+ Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+DisableInterrupts (
+ VOID
+ )
+{
+ gUnitTestHostBaseLib.Common->DisableInterrupts ();
+}
+
+/**
+ Enables CPU interrupts for the smallest window required to capture any
+ pending interrupts.
+
+**/
+VOID
+EFIAPI
+EnableDisableInterrupts (
+ VOID
+ )
+{
+ gUnitTestHostBaseLib.Common->EnableDisableInterrupts ();
+}
+
+/**
+ Set the current CPU interrupt state.
+
+ Sets the current CPU interrupt state to the state specified by
+ InterruptState. If InterruptState is TRUE, then interrupts are enabled. If
+ InterruptState is FALSE, then interrupts are disabled. InterruptState is
+ returned.
+
+ @param InterruptState TRUE if interrupts should enabled. FALSE if
+ interrupts should be disabled.
+
+ @return InterruptState
+
+**/
+BOOLEAN
+EFIAPI
+GetInterruptState (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.Common->GetInterruptState ();
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/UnitTestHost.h b/roms/edk2/MdePkg/Library/BaseLib/UnitTestHost.h new file mode 100644 index 000000000..42bc6b777 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/UnitTestHost.h @@ -0,0 +1,66 @@ +/** @file
+ Unit Test Host functions.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __UNIT_TEST_HOST_H__
+#define __UNIT_TEST_HOST_H__
+
+#include "BaseLibInternals.h"
+#include <Library/UnitTestHostBaseLib.h>
+
+/**
+ Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibEnableInterrupts (
+ VOID
+ );
+
+/**
+ Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibDisableInterrupts (
+ VOID
+ );
+
+/**
+ Enables CPU interrupts for the smallest window required to capture any
+ pending interrupts.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibEnableDisableInterrupts (
+ VOID
+ );
+
+/**
+ Set the current CPU interrupt state.
+
+ Sets the current CPU interrupt state to the state specified by
+ InterruptState. If InterruptState is TRUE, then interrupts are enabled. If
+ InterruptState is FALSE, then interrupts are disabled. InterruptState is
+ returned.
+
+ @param InterruptState TRUE if interrupts should enabled. FALSE if
+ interrupts should be disabled.
+
+ @return InterruptState
+
+**/
+BOOLEAN
+EFIAPI
+UnitTestHostBaseLibGetInterruptState (
+ VOID
+ );
+
+#endif
diff --git a/roms/edk2/MdePkg/Library/BaseLib/UnitTestHostBaseLib.inf b/roms/edk2/MdePkg/Library/BaseLib/UnitTestHostBaseLib.inf new file mode 100644 index 000000000..eae1a7158 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/UnitTestHostBaseLib.inf @@ -0,0 +1,251 @@ +## @file
+# Base Library implementation for use with host based unit tests.
+#
+# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = UnitTestHostBaseLib
+ MODULE_UNI_FILE = UnitTestHostBaseLib.uni
+ FILE_GUID = 9555A0D3-09BA-46C4-A51A-45198E3C765E
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.1
+ LIBRARY_CLASS = BaseLib|HOST_APPLICATION
+ LIBRARY_CLASS = UnitTestHostBaseLib|HOST_APPLICATION
+
+#
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
+#
+
+[Sources]
+ CheckSum.c
+ SwitchStack.c
+ SwapBytes64.c
+ SwapBytes32.c
+ SwapBytes16.c
+ LongJump.c
+ SetJump.c
+ RShiftU64.c
+ RRotU64.c
+ RRotU32.c
+ MultU64x64.c
+ MultU64x32.c
+ MultS64x64.c
+ ModU64x32.c
+ LShiftU64.c
+ LRotU64.c
+ LRotU32.c
+ LowBitSet64.c
+ LowBitSet32.c
+ HighBitSet64.c
+ HighBitSet32.c
+ GetPowerOfTwo64.c
+ GetPowerOfTwo32.c
+ DivU64x64Remainder.c
+ DivU64x32Remainder.c
+ DivU64x32.c
+ DivS64x64Remainder.c
+ ARShiftU64.c
+ BitField.c
+ CpuDeadLoop.c
+ Cpu.c
+ LinkedList.c
+ SafeString.c
+ String.c
+ FilePaths.c
+ BaseLibInternals.h
+ UnitTestHost.c
+ UnitTestHost.h
+
+[Sources.Ia32]
+ Ia32/WriteMm7.c | MSFT
+ Ia32/WriteMm6.c | MSFT
+ Ia32/WriteMm5.c | MSFT
+ Ia32/WriteMm4.c | MSFT
+ Ia32/WriteMm3.c | MSFT
+ Ia32/WriteMm2.c | MSFT
+ Ia32/WriteMm1.c | MSFT
+ Ia32/WriteMm0.c | MSFT
+ Ia32/ReadMm7.c | MSFT
+ Ia32/ReadMm6.c | MSFT
+ Ia32/ReadMm5.c | MSFT
+ Ia32/ReadMm4.c | MSFT
+ Ia32/ReadMm3.c | MSFT
+ Ia32/ReadMm2.c | MSFT
+ Ia32/ReadMm1.c | MSFT
+ Ia32/ReadMm0.c | MSFT
+ Ia32/SwapBytes64.c | MSFT
+ Ia32/RRotU64.c | MSFT
+ Ia32/RShiftU64.c | MSFT
+ Ia32/ReadTsc.c | MSFT
+ Ia32/ReadEflags.c | MSFT
+ Ia32/ModU64x32.c | MSFT
+ Ia32/MultU64x64.c | MSFT
+ Ia32/MultU64x32.c | MSFT
+ Ia32/LShiftU64.c | MSFT
+ Ia32/LRotU64.c | MSFT
+ Ia32/FxRestore.c | MSFT
+ Ia32/FxSave.c | MSFT
+ Ia32/DivU64x32Remainder.c | MSFT
+ Ia32/DivU64x32.c | MSFT
+ Ia32/CpuPause.c | MSFT
+ Ia32/CpuBreakpoint.c | MSFT
+ Ia32/ARShiftU64.c | MSFT
+ Ia32/GccInline.c | GCC
+ Ia32/LongJump.nasm
+ Ia32/SetJump.nasm
+ Ia32/SwapBytes64.nasm| GCC
+ Ia32/DivU64x64Remainder.nasm
+ Ia32/DivU64x32Remainder.nasm| GCC
+ Ia32/ModU64x32.nasm| GCC
+ Ia32/DivU64x32.nasm| GCC
+ Ia32/MultU64x64.nasm| GCC
+ Ia32/MultU64x32.nasm| GCC
+ Ia32/RRotU64.nasm| GCC
+ Ia32/LRotU64.nasm| GCC
+ Ia32/ARShiftU64.nasm| GCC
+ Ia32/RShiftU64.nasm| GCC
+ Ia32/LShiftU64.nasm| GCC
+ Ia32/RdRand.nasm
+ Ia32/DivS64x64Remainder.c
+ Ia32/InternalSwitchStack.c | MSFT
+ Ia32/InternalSwitchStack.nasm | GCC
+ Ia32/Non-existing.c
+ Unaligned.c
+ X86MemoryFence.c | MSFT
+ X86FxSave.c
+ X86FxRestore.c
+ X86Msr.c
+ X86RdRand.c
+ X86SpeculationBarrier.c
+ X86UnitTestHost.c
+
+[Sources.X64]
+ X64/LongJump.nasm
+ X64/SetJump.nasm
+ X64/SwitchStack.nasm
+ X64/CpuBreakpoint.c | MSFT
+ X64/CpuPause.nasm| MSFT
+ X64/ReadTsc.nasm| MSFT
+ X64/WriteMm7.nasm| MSFT
+ X64/WriteMm6.nasm| MSFT
+ X64/WriteMm5.nasm| MSFT
+ X64/WriteMm4.nasm| MSFT
+ X64/WriteMm3.nasm| MSFT
+ X64/WriteMm2.nasm| MSFT
+ X64/WriteMm1.nasm| MSFT
+ X64/WriteMm0.nasm| MSFT
+ X64/ReadMm7.nasm| MSFT
+ X64/ReadMm6.nasm| MSFT
+ X64/ReadMm5.nasm| MSFT
+ X64/ReadMm4.nasm| MSFT
+ X64/ReadMm3.nasm| MSFT
+ X64/ReadMm2.nasm| MSFT
+ X64/ReadMm1.nasm| MSFT
+ X64/ReadMm0.nasm| MSFT
+ X64/FxRestore.nasm| MSFT
+ X64/FxSave.nasm| MSFT
+ X64/ReadEflags.nasm| MSFT
+ X64/Non-existing.c
+ Math64.c
+ Unaligned.c
+ X86MemoryFence.c | MSFT
+ X86FxSave.c
+ X86FxRestore.c
+ X86Msr.c
+ X86RdRand.c
+ X86SpeculationBarrier.c
+ X64/GccInline.c | GCC
+ X64/RdRand.nasm
+ ChkStkGcc.c | GCC
+ X86UnitTestHost.c
+
+[Sources.EBC]
+ Ebc/CpuBreakpoint.c
+ Ebc/SetJumpLongJump.c
+ Ebc/SwitchStack.c
+ Ebc/SpeculationBarrier.c
+ Unaligned.c
+ Math64.c
+
+[Sources.ARM]
+ Arm/InternalSwitchStack.c
+ Arm/Unaligned.c
+ Math64.c | RVCT
+ Math64.c | MSFT
+
+ Arm/SwitchStack.asm | RVCT
+ Arm/SetJumpLongJump.asm | RVCT
+ Arm/CpuPause.asm | RVCT
+ Arm/CpuBreakpoint.asm | RVCT
+ Arm/MemoryFence.asm | RVCT
+ Arm/SpeculationBarrier.S | RVCT
+
+ Arm/SwitchStack.asm | MSFT
+ Arm/SetJumpLongJump.asm | MSFT
+ Arm/CpuPause.asm | MSFT
+ Arm/CpuBreakpoint.asm | MSFT
+ Arm/MemoryFence.asm | MSFT
+ Arm/SpeculationBarrier.asm | MSFT
+
+ Arm/Math64.S | GCC
+ Arm/SwitchStack.S | GCC
+ Arm/SetJumpLongJump.S | GCC
+ Arm/CpuBreakpoint.S | GCC
+ Arm/MemoryFence.S | GCC
+ Arm/SpeculationBarrier.S | GCC
+
+[Sources.AARCH64]
+ Arm/InternalSwitchStack.c
+ Arm/Unaligned.c
+ Math64.c
+
+ AArch64/MemoryFence.S | GCC
+ AArch64/SwitchStack.S | GCC
+ AArch64/SetJumpLongJump.S | GCC
+ AArch64/CpuBreakpoint.S | GCC
+ AArch64/SpeculationBarrier.S | GCC
+
+ AArch64/MemoryFence.asm | MSFT
+ AArch64/SwitchStack.asm | MSFT
+ AArch64/SetJumpLongJump.asm | MSFT
+ AArch64/CpuBreakpoint.asm | MSFT
+ AArch64/SpeculationBarrier.asm | MSFT
+
+[Sources.RISCV64]
+ Math64.c
+ Unaligned.c
+ RiscV64/InternalSwitchStack.c
+ RiscV64/CpuBreakpoint.c
+ RiscV64/CpuPause.c
+ RiscV64/RiscVSetJumpLongJump.S | GCC
+ RiscV64/RiscVCpuBreakpoint.S | GCC
+ RiscV64/RiscVCpuPause.S | GCC
+ RiscV64/RiscVInterrupt.S | GCC
+ RiscV64/FlushCache.S | GCC
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ PcdLib
+ DebugLib
+ BaseMemoryLib
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength ## SOMETIMES_CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength ## SOMETIMES_CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength ## SOMETIMES_CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask ## SOMETIMES_CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType ## SOMETIMES_CONSUMES
+
+[FeaturePcd]
+ gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList ## CONSUMES
diff --git a/roms/edk2/MdePkg/Library/BaseLib/UnitTestHostBaseLib.uni b/roms/edk2/MdePkg/Library/BaseLib/UnitTestHostBaseLib.uni new file mode 100644 index 000000000..e63ecef82 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/UnitTestHostBaseLib.uni @@ -0,0 +1,11 @@ +// /** @file
+// Base Library implementation for use with host based unit tests.
+//
+// Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_MODULE_ABSTRACT #language en-US "Base Library implementation for use with host based unit tests."
+
+#string STR_MODULE_DESCRIPTION #language en-US "Base Library implementation for use with host based unit tests."
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/CpuBreakpoint.c b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuBreakpoint.c new file mode 100644 index 000000000..c626ef8ec --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuBreakpoint.c @@ -0,0 +1,33 @@ +/** @file
+ CpuBreakpoint function.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+/**
+ Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
+**/
+
+void __debugbreak (VOID);
+
+#pragma intrinsic(__debugbreak)
+
+/**
+ Generates a breakpoint on the CPU.
+
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such
+ that code can resume normal execution after the breakpoint.
+
+**/
+VOID
+EFIAPI
+CpuBreakpoint (
+ VOID
+ )
+{
+ __debugbreak ();
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/CpuBreakpoint.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuBreakpoint.nasm new file mode 100644 index 000000000..5bdbe3290 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuBreakpoint.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuBreakpoint.Asm
+;
+; Abstract:
+;
+; CpuBreakpoint function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuBreakpoint (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(CpuBreakpoint)
+ASM_PFX(CpuBreakpoint):
+ int 3
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/CpuId.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuId.nasm new file mode 100644 index 000000000..bb83017c8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuId.nasm @@ -0,0 +1,58 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuId.Asm
+;
+; Abstract:
+;
+; AsmCpuid function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmCpuid (
+; IN UINT32 RegisterInEax,
+; OUT UINT32 *RegisterOutEax OPTIONAL,
+; OUT UINT32 *RegisterOutEbx OPTIONAL,
+; OUT UINT32 *RegisterOutEcx OPTIONAL,
+; OUT UINT32 *RegisterOutEdx OPTIONAL
+; )
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmCpuid)
+ASM_PFX(AsmCpuid):
+ push rbx
+ mov eax, ecx
+ push rax ; save Index on stack
+ push rdx
+ cpuid
+ test r9, r9
+ jz .0
+ mov [r9], ecx
+.0:
+ pop rcx
+ jrcxz .1
+ mov [rcx], eax
+.1:
+ mov rcx, r8
+ jrcxz .2
+ mov [rcx], ebx
+.2:
+ mov rcx, [rsp + 0x38]
+ jrcxz .3
+ mov [rcx], edx
+.3:
+ pop rax ; restore Index to rax as return value
+ pop rbx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/CpuIdEx.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuIdEx.nasm new file mode 100644 index 000000000..fd5caa328 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuIdEx.nasm @@ -0,0 +1,60 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuIdEx.Asm
+;
+; Abstract:
+;
+; AsmCpuidEx function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT32
+; EFIAPI
+; AsmCpuidEx (
+; IN UINT32 RegisterInEax,
+; IN UINT32 RegisterInEcx,
+; OUT UINT32 *RegisterOutEax OPTIONAL,
+; OUT UINT32 *RegisterOutEbx OPTIONAL,
+; OUT UINT32 *RegisterOutEcx OPTIONAL,
+; OUT UINT32 *RegisterOutEdx OPTIONAL
+; )
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmCpuidEx)
+ASM_PFX(AsmCpuidEx):
+ push rbx
+ mov eax, ecx
+ mov ecx, edx
+ push rax ; save Index on stack
+ cpuid
+ mov r10, [rsp + 0x38]
+ test r10, r10
+ jz .0
+ mov [r10], ecx
+.0:
+ mov rcx, r8
+ jrcxz .1
+ mov [rcx], eax
+.1:
+ mov rcx, r9
+ jrcxz .2
+ mov [rcx], ebx
+.2:
+ mov rcx, [rsp + 0x40]
+ jrcxz .3
+ mov [rcx], edx
+.3:
+ pop rax ; restore Index to rax as return value
+ pop rbx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/CpuPause.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuPause.nasm new file mode 100644 index 000000000..ca3519741 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuPause.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuPause.Asm
+;
+; Abstract:
+;
+; CpuPause function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuPause (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(CpuPause)
+ASM_PFX(CpuPause):
+ pause
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/DisableCache.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/DisableCache.nasm new file mode 100644 index 000000000..93f5f7539 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/DisableCache.nasm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; DisableCache.Asm
+;
+; Abstract:
+;
+; Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a
+; WBINVD instruction.
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmDisableCache (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmDisableCache)
+ASM_PFX(AsmDisableCache):
+ mov rax, cr0
+ bts rax, 30
+ btr rax, 29
+ mov cr0, rax
+ wbinvd
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/DisableInterrupts.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/DisableInterrupts.nasm new file mode 100644 index 000000000..43c7e5d02 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/DisableInterrupts.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; DisableInterrupts.Asm
+;
+; Abstract:
+;
+; DisableInterrupts function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; DisableInterrupts (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(DisableInterrupts)
+ASM_PFX(DisableInterrupts):
+ cli
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm new file mode 100644 index 000000000..c76ed1a76 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm @@ -0,0 +1,78 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; DisablePaging64.Asm
+;
+; Abstract:
+;
+; AsmDisablePaging64 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86DisablePaging64 (
+; IN UINT16 Cs,
+; IN UINT32 EntryPoint,
+; IN UINT32 Context1, OPTIONAL
+; IN UINT32 Context2, OPTIONAL
+; IN UINT32 NewStack
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86DisablePaging64)
+ASM_PFX(InternalX86DisablePaging64):
+ cli
+ lea rsi, [.0] ; rsi <- The start address of transition code
+ mov edi, [rsp + 0x28] ; rdi <- New stack
+ lea rax, [mTransitionEnd] ; rax <- end of transition code
+ sub rax, rsi ; rax <- The size of transition piece code
+ add rax, 4 ; Round RAX up to the next 4 byte boundary
+ and al, 0xfc
+ sub rdi, rax ; rdi <- Use stack to hold transition code
+ mov r10d, edi ; r10 <- The start address of transicition code below 4G
+ push rcx ; save rcx to stack
+ mov rcx, rax ; rcx <- The size of transition piece code
+ rep movsb ; copy transition code to top of new stack which must be below 4GB
+ pop rcx ; restore rcx
+
+ mov esi, r8d
+ mov edi, r9d
+ mov eax, r10d ; eax <- start of the transition code on the stack
+ sub eax, 4 ; eax <- One slot below transition code on the stack
+ push rcx ; push Cs to stack
+ push r10 ; push address of tansition code on stack
+ DB 0x48 ; prefix to composite "retq" with next "retf"
+ retf ; Use far return to load CS register from stack
+
+; Start of transition code
+.0:
+ mov esp, eax ; set up new stack
+ mov rax, cr0
+ btr eax, 31 ; Clear CR0.PG
+ mov cr0, rax ; disable paging and caches
+
+ mov ebx, edx ; save EntryPoint to rbx, for rdmsr will overwrite rdx
+ mov ecx, 0xc0000080
+ rdmsr
+ and ah, ~ 1 ; clear LME
+ wrmsr
+ mov rax, cr4
+ and al, ~ (1 << 5) ; clear PAE
+ mov cr4, rax
+ push rdi ; push Context2
+ push rsi ; push Context1
+ call rbx ; transfer control to EntryPoint
+ hlt ; no one should get here
+
+mTransitionEnd:
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/EnableCache.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/EnableCache.nasm new file mode 100644 index 000000000..b6fae3cbf --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/EnableCache.nasm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; EnableCache.Asm
+;
+; Abstract:
+;
+; Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear
+; the NW bit of CR0 to 0
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmEnableCache (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmEnableCache)
+ASM_PFX(AsmEnableCache):
+ wbinvd
+ mov rax, cr0
+ btr rax, 29
+ btr rax, 30
+ mov cr0, rax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/EnableDisableInterrupts.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/EnableDisableInterrupts.nasm new file mode 100644 index 000000000..3c7e9e78d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/EnableDisableInterrupts.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; EnableDisableInterrupts.Asm
+;
+; Abstract:
+;
+; EnableDisableInterrupts function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; EnableDisableInterrupts (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(EnableDisableInterrupts)
+ASM_PFX(EnableDisableInterrupts):
+ sti
+ cli
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/EnableInterrupts.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/EnableInterrupts.nasm new file mode 100644 index 000000000..6057afd62 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/EnableInterrupts.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; EnableInterrupts.Asm
+;
+; Abstract:
+;
+; EnableInterrupts function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; EnableInterrupts (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(EnableInterrupts)
+ASM_PFX(EnableInterrupts):
+ sti
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/FlushCacheLine.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/FlushCacheLine.nasm new file mode 100644 index 000000000..1effabe0d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/FlushCacheLine.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; FlushCacheLine.Asm
+;
+; Abstract:
+;
+; AsmFlushCacheLine function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID *
+; EFIAPI
+; AsmFlushCacheLine (
+; IN VOID *LinearAddress
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmFlushCacheLine)
+ASM_PFX(AsmFlushCacheLine):
+ clflush [rcx]
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/FxRestore.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/FxRestore.nasm new file mode 100644 index 000000000..261981edf --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/FxRestore.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; FxRestore.Asm
+;
+; Abstract:
+;
+; AsmFxRestore function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86FxRestore (
+; IN CONST IA32_FX_BUFFER *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86FxRestore)
+ASM_PFX(InternalX86FxRestore):
+ fxrstor [rcx]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/FxSave.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/FxSave.nasm new file mode 100644 index 000000000..fafe24d62 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/FxSave.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; FxSave.Asm
+;
+; Abstract:
+;
+; AsmFxSave function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86FxSave (
+; OUT IA32_FX_BUFFER *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86FxSave)
+ASM_PFX(InternalX86FxSave):
+ fxsave [rcx]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/GccInline.c b/roms/edk2/MdePkg/Library/BaseLib/X64/GccInline.c new file mode 100644 index 000000000..40a208f19 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/GccInline.c @@ -0,0 +1,562 @@ +/** @file
+ GCC inline implementation of BaseLib processor specific functions.
+
+ Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+
+
+
+/**
+ Used to serialize load and store operations.
+
+ All loads and stores that proceed calls to this function are guaranteed to be
+ globally visible when this function returns.
+
+**/
+VOID
+EFIAPI
+MemoryFence (
+ VOID
+ )
+{
+ // This is a little bit of overkill and it is more about the compiler that it is
+ // actually processor synchronization. This is like the _ReadWriteBarrier
+ // Microsoft specific intrinsic
+ __asm__ __volatile__ ("":::"memory");
+}
+
+
+/**
+ Requests CPU to pause for a short period of time.
+
+ Requests CPU to pause for a short period of time. Typically used in MP
+ systems to prevent memory starvation while waiting for a spin lock.
+
+**/
+VOID
+EFIAPI
+CpuPause (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("pause");
+}
+
+
+/**
+ Generates a breakpoint on the CPU.
+
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such
+ that code can resume normal execution after the breakpoint.
+
+**/
+VOID
+EFIAPI
+CpuBreakpoint (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("int $3");
+}
+
+
+/**
+ Reads the current value of the EFLAGS register.
+
+ Reads and returns the current value of the EFLAGS register. This function is
+ only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a
+ 64-bit value on X64.
+
+ @return EFLAGS on IA-32 or RFLAGS on X64.
+
+**/
+UINTN
+EFIAPI
+AsmReadEflags (
+ VOID
+ )
+{
+ UINTN Eflags;
+
+ __asm__ __volatile__ (
+ "pushfq \n\t"
+ "pop %0 "
+ : "=r" (Eflags) // %0
+ );
+
+ return Eflags;
+}
+
+/**
+ Save the current floating point/SSE/SSE2 context to a buffer.
+
+ Saves the current floating point/SSE/SSE2 state to the buffer specified by
+ Buffer. Buffer must be aligned on a 16-byte boundary. This function is only
+ available on IA-32 and X64.
+
+ @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context.
+
+**/
+VOID
+EFIAPI
+InternalX86FxSave (
+ OUT IA32_FX_BUFFER *Buffer
+ )
+{
+ __asm__ __volatile__ (
+ "fxsave %0"
+ :
+ : "m" (*Buffer) // %0
+ );
+}
+
+
+/**
+ Restores the current floating point/SSE/SSE2 context from a buffer.
+
+ Restores the current floating point/SSE/SSE2 state from the buffer specified
+ by Buffer. Buffer must be aligned on a 16-byte boundary. This function is
+ only available on IA-32 and X64.
+
+ @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context.
+
+**/
+VOID
+EFIAPI
+InternalX86FxRestore (
+ IN CONST IA32_FX_BUFFER *Buffer
+ )
+{
+ __asm__ __volatile__ (
+ "fxrstor %0"
+ :
+ : "m" (*Buffer) // %0
+ );
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #0 (MM0).
+
+ Reads and returns the current value of MM0. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM0.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm0 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "movd %%mm0, %0 \n\t"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #1 (MM1).
+
+ Reads and returns the current value of MM1. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM1.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm1 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "movd %%mm1, %0 \n\t"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #2 (MM2).
+
+ Reads and returns the current value of MM2. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM2.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm2 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "movd %%mm2, %0 \n\t"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #3 (MM3).
+
+ Reads and returns the current value of MM3. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM3.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm3 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "movd %%mm3, %0 \n\t"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #4 (MM4).
+
+ Reads and returns the current value of MM4. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM4.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm4 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "movd %%mm4, %0 \n\t"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #5 (MM5).
+
+ Reads and returns the current value of MM5. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM5.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm5 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "movd %%mm5, %0 \n\t"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #6 (MM6).
+
+ Reads and returns the current value of MM6. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM6.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm6 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "movd %%mm6, %0 \n\t"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #7 (MM7).
+
+ Reads and returns the current value of MM7. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM7.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm7 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "movd %%mm7, %0 \n\t"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #0 (MM0).
+
+ Writes the current value of MM0. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM0.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm0 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movd %0, %%mm0" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #1 (MM1).
+
+ Writes the current value of MM1. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM1.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm1 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movd %0, %%mm1" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #2 (MM2).
+
+ Writes the current value of MM2. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM2.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm2 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movd %0, %%mm2" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #3 (MM3).
+
+ Writes the current value of MM3. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM3.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm3 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movd %0, %%mm3" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #4 (MM4).
+
+ Writes the current value of MM4. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM4.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm4 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movd %0, %%mm4" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #5 (MM5).
+
+ Writes the current value of MM5. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM5.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm5 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movd %0, %%mm5" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #6 (MM6).
+
+ Writes the current value of MM6. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM6.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm6 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movd %0, %%mm6" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #7 (MM7).
+
+ Writes the current value of MM7. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM7.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm7 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movd %0, %%mm7" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Reads the current value of Time Stamp Counter (TSC).
+
+ Reads and returns the current value of TSC. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of TSC
+
+**/
+UINT64
+EFIAPI
+AsmReadTsc (
+ VOID
+ )
+{
+ UINT32 LowData;
+ UINT32 HiData;
+
+ __asm__ __volatile__ (
+ "rdtsc"
+ : "=a" (LowData),
+ "=d" (HiData)
+ );
+
+ return (((UINT64)HiData) << 32) | LowData;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/GccInlinePriv.c b/roms/edk2/MdePkg/Library/BaseLib/X64/GccInlinePriv.c new file mode 100644 index 000000000..98be19b3c --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/GccInlinePriv.c @@ -0,0 +1,1234 @@ +/** @file
+ GCC inline implementation of BaseLib processor specific functions that use
+ privlidged instructions.
+
+ Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Enables CPU interrupts.
+
+ Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+EnableInterrupts (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("sti"::: "memory");
+}
+
+
+/**
+ Disables CPU interrupts.
+
+ Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+DisableInterrupts (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("cli"::: "memory");
+}
+
+/**
+ Returns a 64-bit Machine Specific Register(MSR).
+
+ Reads and returns the 64-bit MSR specified by Index. No parameter checking is
+ performed on Index, and some Index values may cause CPU exceptions. The
+ caller must either guarantee that Index is valid, or the caller must set up
+ exception handlers to catch the exceptions. This function is only available
+ on IA-32 and X64.
+
+ @param Index The 32-bit MSR index to read.
+
+ @return The value of the MSR identified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadMsr64 (
+ IN UINT32 Index
+ )
+{
+ UINT32 LowData;
+ UINT32 HighData;
+
+ __asm__ __volatile__ (
+ "rdmsr"
+ : "=a" (LowData), // %0
+ "=d" (HighData) // %1
+ : "c" (Index) // %2
+ );
+
+ return (((UINT64)HighData) << 32) | LowData;
+}
+
+/**
+ Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
+ value.
+
+ Writes the 64-bit value specified by Value to the MSR specified by Index. The
+ 64-bit value written to the MSR is returned. No parameter checking is
+ performed on Index or Value, and some of these may cause CPU exceptions. The
+ caller must either guarantee that Index and Value are valid, or the caller
+ must establish proper exception handlers. This function is only available on
+ IA-32 and X64.
+
+ @param Index The 32-bit MSR index to write.
+ @param Value The 64-bit value to write to the MSR.
+
+ @return Value
+
+**/
+UINT64
+EFIAPI
+AsmWriteMsr64 (
+ IN UINT32 Index,
+ IN UINT64 Value
+ )
+{
+ UINT32 LowData;
+ UINT32 HighData;
+
+ LowData = (UINT32)(Value);
+ HighData = (UINT32)(Value >> 32);
+
+ __asm__ __volatile__ (
+ "wrmsr"
+ :
+ : "c" (Index),
+ "a" (LowData),
+ "d" (HighData)
+ );
+
+ return Value;
+}
+
+/**
+ Reads the current value of the Control Register 0 (CR0).
+
+ Reads and returns the current value of CR0. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of the Control Register 0 (CR0).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr0 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%cr0,%0"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of the Control Register 2 (CR2).
+
+ Reads and returns the current value of CR2. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of the Control Register 2 (CR2).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr2 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%cr2, %0"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+/**
+ Reads the current value of the Control Register 3 (CR3).
+
+ Reads and returns the current value of CR3. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of the Control Register 3 (CR3).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr3 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%cr3, %0"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of the Control Register 4 (CR4).
+
+ Reads and returns the current value of CR4. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of the Control Register 4 (CR4).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr4 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%cr4, %0"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Writes a value to Control Register 0 (CR0).
+
+ Writes and returns a new value to CR0. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Cr0 The value to write to CR0.
+
+ @return The value written to CR0.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr0 (
+ UINTN Cr0
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr0"
+ :
+ : "r" (Cr0)
+ );
+ return Cr0;
+}
+
+
+/**
+ Writes a value to Control Register 2 (CR2).
+
+ Writes and returns a new value to CR2. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Cr2 The value to write to CR2.
+
+ @return The value written to CR2.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr2 (
+ UINTN Cr2
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr2"
+ :
+ : "r" (Cr2)
+ );
+ return Cr2;
+}
+
+
+/**
+ Writes a value to Control Register 3 (CR3).
+
+ Writes and returns a new value to CR3. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Cr3 The value to write to CR3.
+
+ @return The value written to CR3.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr3 (
+ UINTN Cr3
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr3"
+ :
+ : "r" (Cr3)
+ );
+ return Cr3;
+}
+
+
+/**
+ Writes a value to Control Register 4 (CR4).
+
+ Writes and returns a new value to CR4. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Cr4 The value to write to CR4.
+
+ @return The value written to CR4.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr4 (
+ UINTN Cr4
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr4"
+ :
+ : "r" (Cr4)
+ );
+ return Cr4;
+}
+
+
+/**
+ Reads the current value of Debug Register 0 (DR0).
+
+ Reads and returns the current value of DR0. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr0 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%dr0, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 1 (DR1).
+
+ Reads and returns the current value of DR1. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr1 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%dr1, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 2 (DR2).
+
+ Reads and returns the current value of DR2. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr2 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%dr2, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 3 (DR3).
+
+ Reads and returns the current value of DR3. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr3 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%dr3, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 4 (DR4).
+
+ Reads and returns the current value of DR4. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr4 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%dr4, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 5 (DR5).
+
+ Reads and returns the current value of DR5. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr5 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%dr5, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 6 (DR6).
+
+ Reads and returns the current value of DR6. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr6 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%dr6, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 7 (DR7).
+
+ Reads and returns the current value of DR7. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr7 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%dr7, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Writes a value to Debug Register 0 (DR0).
+
+ Writes and returns a new value to DR0. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr0 The value to write to Dr0.
+
+ @return The value written to Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr0 (
+ UINTN Dr0
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr0"
+ :
+ : "r" (Dr0)
+ );
+ return Dr0;
+}
+
+
+/**
+ Writes a value to Debug Register 1 (DR1).
+
+ Writes and returns a new value to DR1. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr1 The value to write to Dr1.
+
+ @return The value written to Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr1 (
+ UINTN Dr1
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr1"
+ :
+ : "r" (Dr1)
+ );
+ return Dr1;
+}
+
+
+/**
+ Writes a value to Debug Register 2 (DR2).
+
+ Writes and returns a new value to DR2. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr2 The value to write to Dr2.
+
+ @return The value written to Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr2 (
+ UINTN Dr2
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr2"
+ :
+ : "r" (Dr2)
+ );
+ return Dr2;
+}
+
+
+/**
+ Writes a value to Debug Register 3 (DR3).
+
+ Writes and returns a new value to DR3. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr3 The value to write to Dr3.
+
+ @return The value written to Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr3 (
+ UINTN Dr3
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr3"
+ :
+ : "r" (Dr3)
+ );
+ return Dr3;
+}
+
+
+/**
+ Writes a value to Debug Register 4 (DR4).
+
+ Writes and returns a new value to DR4. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr4 The value to write to Dr4.
+
+ @return The value written to Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr4 (
+ UINTN Dr4
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr4"
+ :
+ : "r" (Dr4)
+ );
+ return Dr4;
+}
+
+
+/**
+ Writes a value to Debug Register 5 (DR5).
+
+ Writes and returns a new value to DR5. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr5 The value to write to Dr5.
+
+ @return The value written to Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr5 (
+ UINTN Dr5
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr5"
+ :
+ : "r" (Dr5)
+ );
+ return Dr5;
+}
+
+
+/**
+ Writes a value to Debug Register 6 (DR6).
+
+ Writes and returns a new value to DR6. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr6 The value to write to Dr6.
+
+ @return The value written to Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr6 (
+ UINTN Dr6
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr6"
+ :
+ : "r" (Dr6)
+ );
+ return Dr6;
+}
+
+
+/**
+ Writes a value to Debug Register 7 (DR7).
+
+ Writes and returns a new value to DR7. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr7 The value to write to Dr7.
+
+ @return The value written to Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr7 (
+ UINTN Dr7
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr7"
+ :
+ : "r" (Dr7)
+ );
+ return Dr7;
+}
+
+
+/**
+ Reads the current value of Code Segment Register (CS).
+
+ Reads and returns the current value of CS. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of CS.
+
+**/
+UINT16
+EFIAPI
+AsmReadCs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%cs, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Data Segment Register (DS).
+
+ Reads and returns the current value of DS. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of DS.
+
+**/
+UINT16
+EFIAPI
+AsmReadDs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%ds, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Extra Segment Register (ES).
+
+ Reads and returns the current value of ES. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of ES.
+
+**/
+UINT16
+EFIAPI
+AsmReadEs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%es, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of FS Data Segment Register (FS).
+
+ Reads and returns the current value of FS. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of FS.
+
+**/
+UINT16
+EFIAPI
+AsmReadFs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%fs, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of GS Data Segment Register (GS).
+
+ Reads and returns the current value of GS. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of GS.
+
+**/
+UINT16
+EFIAPI
+AsmReadGs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%gs, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Stack Segment Register (SS).
+
+ Reads and returns the current value of SS. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of SS.
+
+**/
+UINT16
+EFIAPI
+AsmReadSs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%ds, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Task Register (TR).
+
+ Reads and returns the current value of TR. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of TR.
+
+**/
+UINT16
+EFIAPI
+AsmReadTr (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "str %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current Global Descriptor Table Register(GDTR) descriptor.
+
+ Reads and returns the current GDTR descriptor and returns it in Gdtr. This
+ function is only available on IA-32 and X64.
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86ReadGdtr (
+ OUT IA32_DESCRIPTOR *Gdtr
+ )
+{
+ __asm__ __volatile__ (
+ "sgdt %0"
+ : "=m" (*Gdtr)
+ );
+}
+
+
+/**
+ Writes the current Global Descriptor Table Register (GDTR) descriptor.
+
+ Writes and the current GDTR descriptor specified by Gdtr. This function is
+ only available on IA-32 and X64.
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86WriteGdtr (
+ IN CONST IA32_DESCRIPTOR *Gdtr
+ )
+{
+ __asm__ __volatile__ (
+ "lgdt %0"
+ :
+ : "m" (*Gdtr)
+ );
+
+}
+
+
+/**
+ Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.
+
+ Reads and returns the current IDTR descriptor and returns it in Idtr. This
+ function is only available on IA-32 and X64.
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86ReadIdtr (
+ OUT IA32_DESCRIPTOR *Idtr
+ )
+{
+ __asm__ __volatile__ (
+ "sidt %0"
+ : "=m" (*Idtr)
+ );
+}
+
+
+/**
+ Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.
+
+ Writes the current IDTR descriptor and returns it in Idtr. This function is
+ only available on IA-32 and X64.
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86WriteIdtr (
+ IN CONST IA32_DESCRIPTOR *Idtr
+ )
+{
+ __asm__ __volatile__ (
+ "lidt %0"
+ :
+ : "m" (*Idtr)
+ );
+}
+
+
+/**
+ Reads the current Local Descriptor Table Register(LDTR) selector.
+
+ Reads and returns the current 16-bit LDTR descriptor value. This function is
+ only available on IA-32 and X64.
+
+ @return The current selector of LDT.
+
+**/
+UINT16
+EFIAPI
+AsmReadLdtr (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "sldt %0"
+ : "=g" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Writes the current Local Descriptor Table Register (GDTR) selector.
+
+ Writes and the current LDTR descriptor specified by Ldtr. This function is
+ only available on IA-32 and X64.
+
+ @param Ldtr 16-bit LDTR selector value.
+
+**/
+VOID
+EFIAPI
+AsmWriteLdtr (
+ IN UINT16 Ldtr
+ )
+{
+ __asm__ __volatile__ (
+ "lldtw %0"
+ :
+ : "g" (Ldtr) // %0
+ );
+}
+
+/**
+ Reads the current value of a Performance Counter (PMC).
+
+ Reads and returns the current value of performance counter specified by
+ Index. This function is only available on IA-32 and X64.
+
+ @param Index The 32-bit Performance Counter index to read.
+
+ @return The value of the PMC specified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadPmc (
+ IN UINT32 Index
+ )
+{
+ UINT32 LowData;
+ UINT32 HiData;
+
+ __asm__ __volatile__ (
+ "rdpmc"
+ : "=a" (LowData),
+ "=d" (HiData)
+ : "c" (Index)
+ );
+
+ return (((UINT64)HiData) << 32) | LowData;
+}
+
+/**
+ Sets up a monitor buffer that is used by AsmMwait().
+
+ Executes a MONITOR instruction with the register state specified by Eax, Ecx
+ and Edx. Returns Eax. This function is only available on IA-32 and X64.
+
+ @param Eax The value to load into EAX or RAX before executing the MONITOR
+ instruction.
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR
+ instruction.
+ @param Edx The value to load into EDX or RDX before executing the MONITOR
+ instruction.
+
+ @return Eax
+
+**/
+UINTN
+EFIAPI
+AsmMonitor (
+ IN UINTN Eax,
+ IN UINTN Ecx,
+ IN UINTN Edx
+ )
+{
+ __asm__ __volatile__ (
+ "monitor"
+ :
+ : "a" (Eax),
+ "c" (Ecx),
+ "d" (Edx)
+ );
+
+ return Eax;
+}
+
+/**
+ Executes an MWAIT instruction.
+
+ Executes an MWAIT instruction with the register state specified by Eax and
+ Ecx. Returns Eax. This function is only available on IA-32 and X64.
+
+ @param Eax The value to load into EAX or RAX before executing the MONITOR
+ instruction.
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR
+ instruction.
+
+ @return Eax
+
+**/
+UINTN
+EFIAPI
+AsmMwait (
+ IN UINTN Eax,
+ IN UINTN Ecx
+ )
+{
+ __asm__ __volatile__ (
+ "mwait"
+ :
+ : "a" (Eax),
+ "c" (Ecx)
+ );
+
+ return Eax;
+}
+
+/**
+ Executes a WBINVD instruction.
+
+ Executes a WBINVD instruction. This function is only available on IA-32 and
+ X64.
+
+**/
+VOID
+EFIAPI
+AsmWbinvd (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("wbinvd":::"memory");
+}
+
+/**
+ Executes a INVD instruction.
+
+ Executes a INVD instruction. This function is only available on IA-32 and
+ X64.
+
+**/
+VOID
+EFIAPI
+AsmInvd (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("invd":::"memory");
+
+}
+
+
+/**
+ Flushes a cache line from all the instruction and data caches within the
+ coherency domain of the CPU.
+
+ Flushed the cache line specified by LinearAddress, and returns LinearAddress.
+ This function is only available on IA-32 and X64.
+
+ @param LinearAddress The address of the cache line to flush. If the CPU is
+ in a physical addressing mode, then LinearAddress is a
+ physical address. If the CPU is in a virtual
+ addressing mode, then LinearAddress is a virtual
+ address.
+
+ @return LinearAddress
+**/
+VOID *
+EFIAPI
+AsmFlushCacheLine (
+ IN VOID *LinearAddress
+ )
+{
+ __asm__ __volatile__ (
+ "clflush (%0)"
+ :
+ : "r" (LinearAddress)
+ : "memory"
+ );
+
+ return LinearAddress;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/Invd.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/Invd.nasm new file mode 100644 index 000000000..5580f64c5 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/Invd.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Invd.Asm
+;
+; Abstract:
+;
+; AsmInvd function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmInvd (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmInvd)
+ASM_PFX(AsmInvd):
+ invd
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/Lfence.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/Lfence.nasm new file mode 100644 index 000000000..25fd0746a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/Lfence.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Lfence.nasm
+;
+; Abstract:
+;
+; Performs a serializing operation on all load-from-memory instructions that
+; were issued prior to the call of this function.
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmLfence (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmLfence)
+ASM_PFX(AsmLfence):
+ lfence
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/LongJump.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/LongJump.nasm new file mode 100644 index 000000000..59f709216 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/LongJump.nasm @@ -0,0 +1,77 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; LongJump.Asm
+;
+; Abstract:
+;
+; Implementation of _LongJump() on x64.
+;
+;------------------------------------------------------------------------------
+
+%include "Nasm.inc"
+
+ DEFAULT REL
+ SECTION .text
+
+extern ASM_PFX(PcdGet32 (PcdControlFlowEnforcementPropertyMask))
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalLongJump (
+; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalLongJump)
+ASM_PFX(InternalLongJump):
+
+ mov eax, [ASM_PFX(PcdGet32 (PcdControlFlowEnforcementPropertyMask))]
+ test eax, eax
+ jz CetDone
+ mov rax, cr4
+ bt eax, 23 ; check if CET is enabled
+ jnc CetDone
+
+ push rdx ; save rdx
+
+ mov rdx, [rcx + 0xF8] ; rdx = target SSP
+ READSSP_RAX
+ sub rdx, rax ; rdx = delta
+ mov rax, rdx ; rax = delta
+
+ shr rax, 3 ; rax = delta/sizeof(UINT64)
+ INCSSP_RAX
+
+ pop rdx ; restore rdx
+CetDone:
+
+ mov rbx, [rcx]
+ mov rsp, [rcx + 8]
+ mov rbp, [rcx + 0x10]
+ mov rdi, [rcx + 0x18]
+ mov rsi, [rcx + 0x20]
+ mov r12, [rcx + 0x28]
+ mov r13, [rcx + 0x30]
+ mov r14, [rcx + 0x38]
+ mov r15, [rcx + 0x40]
+ ; load non-volatile fp registers
+ ldmxcsr [rcx + 0x50]
+ movdqu xmm6, [rcx + 0x58]
+ movdqu xmm7, [rcx + 0x68]
+ movdqu xmm8, [rcx + 0x78]
+ movdqu xmm9, [rcx + 0x88]
+ movdqu xmm10, [rcx + 0x98]
+ movdqu xmm11, [rcx + 0xA8]
+ movdqu xmm12, [rcx + 0xB8]
+ movdqu xmm13, [rcx + 0xC8]
+ movdqu xmm14, [rcx + 0xD8]
+ movdqu xmm15, [rcx + 0xE8]
+ mov rax, rdx ; set return value
+ jmp qword [rcx + 0x48]
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/Monitor.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/Monitor.nasm new file mode 100644 index 000000000..e1ccb83a8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/Monitor.nasm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Monitor.Asm
+;
+; Abstract:
+;
+; AsmMonitor function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmMonitor (
+; IN UINTN Eax,
+; IN UINTN Ecx,
+; IN UINTN Edx
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmMonitor)
+ASM_PFX(AsmMonitor):
+ mov eax, ecx
+ mov ecx, edx
+ mov edx, r8d
+ DB 0xf, 1, 0xc8 ; monitor
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/Mwait.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/Mwait.nasm new file mode 100644 index 000000000..83fc89549 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/Mwait.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Mwait.Asm
+;
+; Abstract:
+;
+; AsmMwait function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmMwait (
+; IN UINTN Eax,
+; IN UINTN Ecx
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmMwait)
+ASM_PFX(AsmMwait):
+ mov eax, ecx
+ mov ecx, edx
+ DB 0xf, 1, 0xc9 ; mwait
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/Non-existing.c b/roms/edk2/MdePkg/Library/BaseLib/X64/Non-existing.c new file mode 100644 index 000000000..e00cb7eb5 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/Non-existing.c @@ -0,0 +1,147 @@ +/** @file
+ Non-existing BaseLib functions on x64
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ Enables the 32-bit paging mode on the CPU.
+
+ Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode. This function is
+ only available on IA-32. After the 32-bit paging mode is enabled, control is
+ transferred to the function specified by EntryPoint using the new stack
+ specified by NewStack and passing in the parameters specified by Context1 and
+ Context2. Context1 and Context2 are optional and may be NULL. The function
+ EntryPoint must never return.
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit protected mode with flat descriptors. This
+ means all descriptors must have a base of 0 and a limit of 4GB.
+ 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat
+ descriptors.
+ 4) CR3 must point to valid page tables that will be used once the transition
+ is complete, and those page tables must guarantee that the pages for this
+ function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is enabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is enabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is enabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+InternalX86EnablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack
+ )
+{
+ //
+ // This function cannot work on x64 platform
+ //
+ ASSERT (FALSE);
+}
+
+/**
+ Disables the 32-bit paging mode on the CPU.
+
+ Disables the 32-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 32-paged protected
+ mode. This function is only available on IA-32. After the 32-bit paging mode
+ is disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be NULL. The function EntryPoint must never return.
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit paged mode.
+ 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.
+ 4) CR3 must point to valid page tables that guarantee that the pages for
+ this function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is disabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is disabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is
+ disabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+InternalX86DisablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack
+ )
+{
+ //
+ // This function cannot work on x64 platform
+ //
+ ASSERT (FALSE);
+}
+
+
+/**
+ Enables the 64-bit paging mode on the CPU.
+
+ Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode with flat
+ descriptors. This function is only available on IA-32. After the 64-bit
+ paging mode is enabled, control is transferred to the function specified by
+ EntryPoint using the new stack specified by NewStack and passing in the
+ parameters specified by Context1 and Context2. Context1 and Context2 are
+ optional and may be 0. The function EntryPoint must never return.
+
+ @param Cs The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for long mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is enabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is enabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is enabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+InternalX86EnablePaging64 (
+ IN UINT16 Cs,
+ IN UINT64 EntryPoint,
+ IN UINT64 Context1, OPTIONAL
+ IN UINT64 Context2, OPTIONAL
+ IN UINT64 NewStack
+ )
+{
+ //
+ // This function cannot work on x64 platform.
+ //
+ ASSERT (FALSE);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/RdRand.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/RdRand.nasm new file mode 100644 index 000000000..7e7fe9967 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/RdRand.nasm @@ -0,0 +1,77 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; RdRand.nasm
+;
+; Abstract:
+;
+; Generates random number through CPU RdRand instruction under 64-bit platform.
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; Generates a 16 bit random number through RDRAND instruction.
+; Return TRUE if Rand generated successfully, or FALSE if not.
+;
+; BOOLEAN EFIAPI InternalX86RdRand16 (UINT16 *Rand);
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86RdRand16)
+ASM_PFX(InternalX86RdRand16):
+ ; rdrand ax ; generate a 16 bit RN into eax,
+ ; CF=1 if RN generated ok, otherwise CF=0
+ db 0xf, 0xc7, 0xf0 ; rdrand r16: "0f c7 /6 ModRM:r/m(w)"
+ jc rn16_ok ; jmp if CF=1
+ xor rax, rax ; reg=0 if CF=0
+ ret ; return with failure status
+rn16_ok:
+ mov [rcx], ax
+ mov rax, 1
+ ret
+
+;------------------------------------------------------------------------------
+; Generates a 32 bit random number through RDRAND instruction.
+; Return TRUE if Rand generated successfully, or FALSE if not.
+;
+; BOOLEAN EFIAPI InternalX86RdRand32 (UINT32 *Rand);
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86RdRand32)
+ASM_PFX(InternalX86RdRand32):
+ ; rdrand eax ; generate a 32 bit RN into eax,
+ ; CF=1 if RN generated ok, otherwise CF=0
+ db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)"
+ jc rn32_ok ; jmp if CF=1
+ xor rax, rax ; reg=0 if CF=0
+ ret ; return with failure status
+rn32_ok:
+ mov [rcx], eax
+ mov rax, 1
+ ret
+
+;------------------------------------------------------------------------------
+; Generates a 64 bit random number through one RDRAND instruction.
+; Return TRUE if Rand generated successfully, or FALSE if not.
+;
+; BOOLEAN EFIAPI InternalX86RdRand64 (UINT64 *Random);
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86RdRand64)
+ASM_PFX(InternalX86RdRand64):
+ ; rdrand rax ; generate a 64 bit RN into rax,
+ ; CF=1 if RN generated ok, otherwise CF=0
+ db 0x48, 0xf, 0xc7, 0xf0 ; rdrand r64: "REX.W + 0f c7 /6 ModRM:r/m(w)"
+ jc rn64_ok ; jmp if CF=1
+ xor rax, rax ; reg=0 if CF=0
+ ret ; return with failure status
+rn64_ok:
+ mov [rcx], rax
+ mov rax, 1
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr0.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr0.nasm new file mode 100644 index 000000000..aaa6f81a7 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr0.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadCr0.Asm
+;
+; Abstract:
+;
+; AsmReadCr0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadCr0 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadCr0)
+ASM_PFX(AsmReadCr0):
+ mov rax, cr0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr2.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr2.nasm new file mode 100644 index 000000000..74c4778e1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr2.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadCr2.Asm
+;
+; Abstract:
+;
+; AsmReadCr2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadCr2 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadCr2)
+ASM_PFX(AsmReadCr2):
+ mov rax, cr2
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr3.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr3.nasm new file mode 100644 index 000000000..ea8173f64 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr3.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadCr3.Asm
+;
+; Abstract:
+;
+; AsmReadCr3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadCr3 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadCr3)
+ASM_PFX(AsmReadCr3):
+ mov rax, cr3
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr4.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr4.nasm new file mode 100644 index 000000000..70c2650ee --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr4.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadCr4.Asm
+;
+; Abstract:
+;
+; AsmReadCr4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadCr4 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadCr4)
+ASM_PFX(AsmReadCr4):
+ mov rax, cr4
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCs.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCs.nasm new file mode 100644 index 000000000..ec069b8f5 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCs.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadCs.Asm
+;
+; Abstract:
+;
+; AsmReadCs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadCs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadCs)
+ASM_PFX(AsmReadCs):
+ mov eax, cs
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr0.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr0.nasm new file mode 100644 index 000000000..7973e52b6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr0.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr0.Asm
+;
+; Abstract:
+;
+; AsmReadDr0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr0 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr0)
+ASM_PFX(AsmReadDr0):
+ mov rax, dr0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr1.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr1.nasm new file mode 100644 index 000000000..1a4b15917 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr1.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr1.Asm
+;
+; Abstract:
+;
+; AsmReadDr1 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr1 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr1)
+ASM_PFX(AsmReadDr1):
+ mov rax, dr1
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr2.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr2.nasm new file mode 100644 index 000000000..d1e403d6a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr2.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr2.Asm
+;
+; Abstract:
+;
+; AsmReadDr2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr2 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr2)
+ASM_PFX(AsmReadDr2):
+ mov rax, dr2
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr3.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr3.nasm new file mode 100644 index 000000000..96a9c5b0c --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr3.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr3.Asm
+;
+; Abstract:
+;
+; AsmReadDr3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr3 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr3)
+ASM_PFX(AsmReadDr3):
+ mov rax, dr3
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr4.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr4.nasm new file mode 100644 index 000000000..82c0a9a58 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr4.nasm @@ -0,0 +1,36 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr4.Asm
+;
+; Abstract:
+;
+; AsmReadDr4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr4 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr4)
+ASM_PFX(AsmReadDr4):
+ ;
+ ; There's no obvious reason to access this register, since it's aliased to
+ ; DR7 when DE=0 or an exception generated when DE=1
+ ;
+ DB 0xf, 0x21, 0xe0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr5.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr5.nasm new file mode 100644 index 000000000..c309c66df --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr5.nasm @@ -0,0 +1,36 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr5.Asm
+;
+; Abstract:
+;
+; AsmReadDr5 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr5 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr5)
+ASM_PFX(AsmReadDr5):
+ ;
+ ; There's no obvious reason to access this register, since it's aliased to
+ ; DR7 when DE=0 or an exception generated when DE=1
+ ;
+ DB 0xf, 0x21, 0xe8
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr6.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr6.nasm new file mode 100644 index 000000000..7bdc10313 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr6.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr6.Asm
+;
+; Abstract:
+;
+; AsmReadDr6 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr6 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr6)
+ASM_PFX(AsmReadDr6):
+ mov rax, dr6
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr7.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr7.nasm new file mode 100644 index 000000000..219d2e459 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr7.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr7.Asm
+;
+; Abstract:
+;
+; AsmReadDr7 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr7 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr7)
+ASM_PFX(AsmReadDr7):
+ mov rax, dr7
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDs.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDs.nasm new file mode 100644 index 000000000..597450d53 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDs.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDs.Asm
+;
+; Abstract:
+;
+; AsmReadDs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadDs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDs)
+ASM_PFX(AsmReadDs):
+ mov eax, ds
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadEflags.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadEflags.nasm new file mode 100644 index 000000000..e0a5ea065 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadEflags.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadEflags.Asm
+;
+; Abstract:
+;
+; AsmReadEflags function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadEflags (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadEflags)
+ASM_PFX(AsmReadEflags):
+ pushfq
+ pop rax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadEs.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadEs.nasm new file mode 100644 index 000000000..963394572 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadEs.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadEs.Asm
+;
+; Abstract:
+;
+; AsmReadEs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadEs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadEs)
+ASM_PFX(AsmReadEs):
+ mov eax, es
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadFs.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadFs.nasm new file mode 100644 index 000000000..9d032ff48 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadFs.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadFs.Asm
+;
+; Abstract:
+;
+; AsmReadFs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadFs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadFs)
+ASM_PFX(AsmReadFs):
+ mov eax, fs
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadGdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadGdtr.nasm new file mode 100644 index 000000000..1712c11eb --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadGdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadGdtr.Asm
+;
+; Abstract:
+;
+; AsmReadGdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86ReadGdtr (
+; OUT IA32_DESCRIPTOR *Gdtr
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86ReadGdtr)
+ASM_PFX(InternalX86ReadGdtr):
+ sgdt [rcx]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadGs.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadGs.nasm new file mode 100644 index 000000000..953fe9c0c --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadGs.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadGs.Asm
+;
+; Abstract:
+;
+; AsmReadGs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadGs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadGs)
+ASM_PFX(AsmReadGs):
+ mov eax, gs
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadIdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadIdtr.nasm new file mode 100644 index 000000000..086ab7087 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadIdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadIdtr.Asm
+;
+; Abstract:
+;
+; AsmReadIdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86ReadIdtr (
+; OUT IA32_DESCRIPTOR *Idtr
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86ReadIdtr)
+ASM_PFX(InternalX86ReadIdtr):
+ sidt [rcx]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadLdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadLdtr.nasm new file mode 100644 index 000000000..9339161a3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadLdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadLdtr.Asm
+;
+; Abstract:
+;
+; AsmReadLdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadLdtr (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadLdtr)
+ASM_PFX(AsmReadLdtr):
+ sldt eax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm0.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm0.nasm new file mode 100644 index 000000000..615721b6a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm0.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm0.Asm
+;
+; Abstract:
+;
+; AsmReadMm0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm0 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm0)
+ASM_PFX(AsmReadMm0):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x7e, 0xc0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm1.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm1.nasm new file mode 100644 index 000000000..7b2739349 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm1.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm1.Asm
+;
+; Abstract:
+;
+; AsmReadMm1 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm1 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm1)
+ASM_PFX(AsmReadMm1):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x7e, 0xc8
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm2.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm2.nasm new file mode 100644 index 000000000..c654b91a7 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm2.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm2.Asm
+;
+; Abstract:
+;
+; AsmReadMm2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm2 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm2)
+ASM_PFX(AsmReadMm2):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x7e, 0xd0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm3.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm3.nasm new file mode 100644 index 000000000..88d51c078 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm3.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm3.Asm
+;
+; Abstract:
+;
+; AsmReadMm3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm3 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm3)
+ASM_PFX(AsmReadMm3):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x7e, 0xd8
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm4.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm4.nasm new file mode 100644 index 000000000..4252d20bb --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm4.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm4.Asm
+;
+; Abstract:
+;
+; AsmReadMm4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm4 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm4)
+ASM_PFX(AsmReadMm4):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x7e, 0xe0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm5.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm5.nasm new file mode 100644 index 000000000..d8f530dec --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm5.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm5.Asm
+;
+; Abstract:
+;
+; AsmReadMm5 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm5 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm5)
+ASM_PFX(AsmReadMm5):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x7e, 0xe8
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm6.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm6.nasm new file mode 100644 index 000000000..6f6883c2b --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm6.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm6.Asm
+;
+; Abstract:
+;
+; AsmReadMm6 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm6 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm6)
+ASM_PFX(AsmReadMm6):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x7e, 0xf0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm7.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm7.nasm new file mode 100644 index 000000000..573f15dfc --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm7.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm7.Asm
+;
+; Abstract:
+;
+; AsmReadMm7 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm7 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm7)
+ASM_PFX(AsmReadMm7):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x7e, 0xf8
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMsr64.c b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMsr64.c new file mode 100644 index 000000000..5ee7ca53f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMsr64.c @@ -0,0 +1,33 @@ +/** @file
+ CpuBreakpoint function.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
+**/
+
+unsigned __int64 __readmsr (int register);
+
+#pragma intrinsic(__readmsr)
+
+/**
+ Read data to MSR.
+
+ @param Index Register index of MSR.
+
+ @return Value read from MSR.
+
+**/
+UINT64
+EFIAPI
+AsmReadMsr64 (
+ IN UINT32 Index
+ )
+{
+ return __readmsr (Index);
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMsr64.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMsr64.nasm new file mode 100644 index 000000000..df6925529 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMsr64.nasm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMsr64.Asm
+;
+; Abstract:
+;
+; AsmReadMsr64 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMsr64 (
+; IN UINT32 Index
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMsr64)
+ASM_PFX(AsmReadMsr64):
+ rdmsr ; edx & eax are zero extended
+ shl rdx, 0x20
+ or rax, rdx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadPmc.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadPmc.nasm new file mode 100644 index 000000000..1785a09de --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadPmc.nasm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadPmc.Asm
+;
+; Abstract:
+;
+; AsmReadPmc function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadPmc (
+; IN UINT32 PmcIndex
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadPmc)
+ASM_PFX(AsmReadPmc):
+ rdpmc
+ shl rdx, 0x20
+ or rax, rdx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadSs.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadSs.nasm new file mode 100644 index 000000000..5fbe6985a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadSs.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadSs.Asm
+;
+; Abstract:
+;
+; AsmReadSs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadSs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadSs)
+ASM_PFX(AsmReadSs):
+ mov eax, ss
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadTr.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadTr.nasm new file mode 100644 index 000000000..492ef6cd1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadTr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadTr.Asm
+;
+; Abstract:
+;
+; AsmReadTr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadTr (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadTr)
+ASM_PFX(AsmReadTr):
+ str eax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadTsc.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadTsc.nasm new file mode 100644 index 000000000..45672d680 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadTsc.nasm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadTsc.Asm
+;
+; Abstract:
+;
+; AsmReadTsc function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadTsc (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadTsc)
+ASM_PFX(AsmReadTsc):
+ rdtsc
+ shl rdx, 0x20
+ or rax, rdx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/SetJump.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/SetJump.nasm new file mode 100644 index 000000000..5a68396ee --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/SetJump.nasm @@ -0,0 +1,81 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; SetJump.Asm
+;
+; Abstract:
+;
+; Implementation of SetJump() on x64.
+;
+;------------------------------------------------------------------------------
+
+%include "Nasm.inc"
+
+ DEFAULT REL
+ SECTION .text
+
+extern ASM_PFX(InternalAssertJumpBuffer)
+extern ASM_PFX(PcdGet32 (PcdControlFlowEnforcementPropertyMask))
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; SetJump (
+; OUT BASE_LIBRARY_JUMP_BUFFER *JumpBuffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(SetJump)
+ASM_PFX(SetJump):
+ push rcx
+ add rsp, -0x20
+ call ASM_PFX(InternalAssertJumpBuffer)
+ add rsp, 0x20
+ pop rcx
+ pop rdx
+
+ xor rax, rax
+ mov [rcx + 0xF8], rax ; save 0 to SSP
+
+ mov eax, [ASM_PFX(PcdGet32 (PcdControlFlowEnforcementPropertyMask))]
+ test eax, eax
+ jz CetDone
+ mov rax, cr4
+ bt eax, 23 ; check if CET is enabled
+ jnc CetDone
+
+ mov rax, 1
+ INCSSP_RAX ; to read original SSP
+ READSSP_RAX
+ mov [rcx + 0xF8], rax ; save SSP
+
+CetDone:
+
+ mov [rcx], rbx
+ mov [rcx + 8], rsp
+ mov [rcx + 0x10], rbp
+ mov [rcx + 0x18], rdi
+ mov [rcx + 0x20], rsi
+ mov [rcx + 0x28], r12
+ mov [rcx + 0x30], r13
+ mov [rcx + 0x38], r14
+ mov [rcx + 0x40], r15
+ mov [rcx + 0x48], rdx
+ ; save non-volatile fp registers
+ stmxcsr [rcx + 0x50]
+ movdqu [rcx + 0x58], xmm6
+ movdqu [rcx + 0x68], xmm7
+ movdqu [rcx + 0x78], xmm8
+ movdqu [rcx + 0x88], xmm9
+ movdqu [rcx + 0x98], xmm10
+ movdqu [rcx + 0xA8], xmm11
+ movdqu [rcx + 0xB8], xmm12
+ movdqu [rcx + 0xC8], xmm13
+ movdqu [rcx + 0xD8], xmm14
+ movdqu [rcx + 0xE8], xmm15
+ xor rax, rax
+ jmp rdx
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/SwitchStack.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/SwitchStack.nasm new file mode 100644 index 000000000..7be666dbd --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/SwitchStack.nasm @@ -0,0 +1,45 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; SwitchStack.Asm
+;
+; Abstract:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; Routine Description:
+;
+; Routine for switching stacks with 2 parameters
+;
+; Arguments:
+;
+; (rcx) EntryPoint - Entry point with new stack.
+; (rdx) Context1 - Parameter1 for entry point.
+; (r8) Context2 - Parameter2 for entry point.
+; (r9) NewStack - The pointer to new stack.
+;
+; Returns:
+;
+; None
+;
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalSwitchStack)
+ASM_PFX(InternalSwitchStack):
+ mov rax, rcx
+ mov rcx, rdx
+ mov rdx, r8
+ ;
+ ; Reserve space for register parameters (rcx, rdx, r8 & r9) on the stack,
+ ; in case the callee wishes to spill them.
+ ;
+ lea rsp, [r9 - 0x20]
+ call rax
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/Thunk16.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/Thunk16.nasm new file mode 100644 index 000000000..e83b31c59 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/Thunk16.nasm @@ -0,0 +1,319 @@ +
+#include "BaseLibInternals.h"
+
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Thunk.asm
+;
+; Abstract:
+;
+; Real mode thunk
+;
+;------------------------------------------------------------------------------
+
+global ASM_PFX(m16Size)
+global ASM_PFX(mThunk16Attr)
+global ASM_PFX(m16Gdt)
+global ASM_PFX(m16GdtrBase)
+global ASM_PFX(mTransition)
+global ASM_PFX(m16Start)
+
+struc IA32_REGS
+
+ ._EDI: resd 1
+ ._ESI: resd 1
+ ._EBP: resd 1
+ ._ESP: resd 1
+ ._EBX: resd 1
+ ._EDX: resd 1
+ ._ECX: resd 1
+ ._EAX: resd 1
+ ._DS: resw 1
+ ._ES: resw 1
+ ._FS: resw 1
+ ._GS: resw 1
+ ._EFLAGS: resq 1
+ ._EIP: resd 1
+ ._CS: resw 1
+ ._SS: resw 1
+ .size:
+
+endstruc
+
+SECTION .data
+
+;
+; These are global constant to convey information to C code.
+;
+ASM_PFX(m16Size) DW ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)
+ASM_PFX(mThunk16Attr) DW _BackFromUserCode.ThunkAttrEnd - 4 - ASM_PFX(m16Start)
+ASM_PFX(m16Gdt) DW _NullSeg - ASM_PFX(m16Start)
+ASM_PFX(m16GdtrBase) DW _16GdtrBase - ASM_PFX(m16Start)
+ASM_PFX(mTransition) DW _EntryPoint - ASM_PFX(m16Start)
+
+SECTION .text
+
+ASM_PFX(m16Start):
+
+SavedGdt:
+ dw 0
+ dq 0
+
+;------------------------------------------------------------------------------
+; _BackFromUserCode() takes control in real mode after 'retf' has been executed
+; by user code. It will be shadowed to somewhere in memory below 1MB.
+;------------------------------------------------------------------------------
+_BackFromUserCode:
+ ;
+ ; The order of saved registers on the stack matches the order they appears
+ ; in IA32_REGS structure. This facilitates wrapper function to extract them
+ ; into that structure.
+ ;
+BITS 16
+ push ss
+ push cs
+ ;
+ ; Note: We can't use o32 on the next instruction because of a bug
+ ; in NASM 2.09.04 through 2.10rc1.
+ ;
+ call dword .Base ; push eip
+.Base:
+ push dword 0 ; reserved high order 32 bits of EFlags
+ pushfd
+ cli ; disable interrupts
+ push gs
+ push fs
+ push es
+ push ds
+ pushad
+ mov edx, strict dword 0
+.ThunkAttrEnd:
+ test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15
+ jz .1
+ mov ax, 2401h
+ int 15h
+ cli ; disable interrupts
+ jnc .2
+.1:
+ test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL
+ jz .2
+ in al, 92h
+ or al, 2
+ out 92h, al ; deactivate A20M#
+.2:
+ xor eax, eax
+ mov ax, ss
+ lea ebp, [esp + IA32_REGS.size]
+ mov [bp - IA32_REGS.size + IA32_REGS._ESP], ebp
+ mov ebx, [bp - IA32_REGS.size + IA32_REGS._EIP]
+ shl eax, 4 ; shl eax, 4
+ add ebp, eax ; add ebp, eax
+ mov eax, cs
+ shl eax, 4
+ lea eax, [eax + ebx + (.X64JmpEnd - .Base)]
+ mov [cs:bx + (.X64JmpEnd - 6 - .Base)], eax
+ mov eax, strict dword 0
+.SavedCr4End:
+ mov cr4, eax
+o32 lgdt [cs:bx + (SavedGdt - .Base)]
+ mov ecx, 0c0000080h
+ rdmsr
+ or ah, 1
+ wrmsr
+ mov eax, strict dword 0
+.SavedCr0End:
+ mov cr0, eax
+ jmp 0:strict dword 0
+.X64JmpEnd:
+BITS 64
+ nop
+ mov rsp, strict qword 0
+.SavedSpEnd:
+ nop
+ ret
+
+_EntryPoint:
+ DD _ToUserCode - ASM_PFX(m16Start)
+ DW CODE16
+_16Gdtr:
+ DW GDT_SIZE - 1
+_16GdtrBase:
+ DQ 0
+_16Idtr:
+ DW (1 << 10) - 1
+ DD 0
+
+;------------------------------------------------------------------------------
+; _ToUserCode() takes control in real mode before passing control to user code.
+; It will be shadowed to somewhere in memory below 1MB.
+;------------------------------------------------------------------------------
+_ToUserCode:
+BITS 16
+ mov ss, dx ; set new segment selectors
+ mov ds, dx
+ mov es, dx
+ mov fs, dx
+ mov gs, dx
+ mov ecx, 0c0000080h
+ mov cr0, eax ; real mode starts at next instruction
+ rdmsr
+ and ah, ~1
+ wrmsr
+ mov cr4, ebp
+ mov ss, si ; set up 16-bit stack segment
+ mov esp, ebx ; set up 16-bit stack pointer
+ call dword .Base ; push eip
+.Base:
+ pop ebp ; ebp <- address of .Base
+ push word [dword esp + IA32_REGS.size + 2]
+ lea ax, [bp + (.RealMode - .Base)]
+ push ax
+ retf ; execution begins at next instruction
+.RealMode:
+
+o32 lidt [cs:bp + (_16Idtr - .Base)]
+
+ popad
+ pop ds
+ pop es
+ pop fs
+ pop gs
+ popfd
+ lea esp, [esp + 4] ; skip high order 32 bits of EFlags
+
+o32 retf ; transfer control to user code
+
+ALIGN 8
+
+CODE16 equ _16Code - $
+DATA16 equ _16Data - $
+DATA32 equ _32Data - $
+
+_NullSeg DQ 0
+_16Code:
+ DW -1
+ DW 0
+ DB 0
+ DB 9bh
+ DB 8fh ; 16-bit segment, 4GB limit
+ DB 0
+_16Data:
+ DW -1
+ DW 0
+ DB 0
+ DB 93h
+ DB 8fh ; 16-bit segment, 4GB limit
+ DB 0
+_32Data:
+ DW -1
+ DW 0
+ DB 0
+ DB 93h
+ DB 0cfh ; 16-bit segment, 4GB limit
+ DB 0
+
+GDT_SIZE equ $ - _NullSeg
+
+;------------------------------------------------------------------------------
+; IA32_REGISTER_SET *
+; EFIAPI
+; InternalAsmThunk16 (
+; IN IA32_REGISTER_SET *RegisterSet,
+; IN OUT VOID *Transition
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalAsmThunk16)
+ASM_PFX(InternalAsmThunk16):
+BITS 64
+ push rbp
+ push rbx
+ push rsi
+ push rdi
+
+ mov ebx, ds
+ push rbx ; Save ds segment register on the stack
+ mov ebx, es
+ push rbx ; Save es segment register on the stack
+ mov ebx, ss
+ push rbx ; Save ss segment register on the stack
+
+ push fs
+ push gs
+ mov rsi, rcx
+ movzx r8d, word [rsi + IA32_REGS._SS]
+ mov edi, [rsi + IA32_REGS._ESP]
+ lea rdi, [edi - (IA32_REGS.size + 4)]
+ imul eax, r8d, 16 ; eax <- r8d(stack segment) * 16
+ mov ebx, edi ; ebx <- stack for 16-bit code
+ push IA32_REGS.size / 4
+ add edi, eax ; edi <- linear address of 16-bit stack
+ pop rcx
+ rep movsd ; copy RegSet
+ lea ecx, [rdx + (_BackFromUserCode.SavedCr4End - ASM_PFX(m16Start))]
+ mov eax, edx ; eax <- transition code address
+ and edx, 0fh
+ shl eax, 12 ; segment address in high order 16 bits
+ lea ax, [rdx + (_BackFromUserCode - ASM_PFX(m16Start))] ; offset address
+ stosd ; [edi] <- return address of user code
+
+ sgdt [rsp + 60h] ; save GDT stack in argument space
+ movzx r10, word [rsp + 60h] ; r10 <- GDT limit
+ lea r11, [rcx + (ASM_PFX(InternalAsmThunk16) - _BackFromUserCode.SavedCr4End) + 0xf]
+ and r11, ~0xf ; r11 <- 16-byte aligned shadowed GDT table in real mode buffer
+
+ mov [rcx + (SavedGdt - _BackFromUserCode.SavedCr4End)], r10w ; save the limit of shadowed GDT table
+ mov [rcx + (SavedGdt - _BackFromUserCode.SavedCr4End) + 2], r11 ; save the base address of shadowed GDT table
+
+ mov rsi, [rsp + 62h] ; rsi <- the original GDT base address
+ xchg rcx, r10 ; save rcx to r10 and initialize rcx to be the limit of GDT table
+ inc rcx ; rcx <- the size of memory to copy
+ xchg rdi, r11 ; save rdi to r11 and initialize rdi to the base address of shadowed GDT table
+ rep movsb ; perform memory copy to shadow GDT table
+ mov rcx, r10 ; restore the orignal rcx before memory copy
+ mov rdi, r11 ; restore the original rdi before memory copy
+
+ sidt [rsp + 50h] ; save IDT stack in argument space
+ mov rax, cr0
+ mov [rcx + (_BackFromUserCode.SavedCr0End - 4 - _BackFromUserCode.SavedCr4End)], eax
+ and eax, 7ffffffeh ; clear PE, PG bits
+ mov rbp, cr4
+ mov [rcx - 4], ebp ; save CR4 in _BackFromUserCode.SavedCr4End - 4
+ and ebp, ~30h ; clear PAE, PSE bits
+ mov esi, r8d ; esi <- 16-bit stack segment
+ push DATA32
+ pop rdx ; rdx <- 32-bit data segment selector
+ lgdt [rcx + (_16Gdtr - _BackFromUserCode.SavedCr4End)]
+ mov ss, edx
+ pushfq
+ lea edx, [rdx + DATA16 - DATA32]
+ lea r8, [REL .RetFromRealMode]
+ push r8
+ mov r8d, cs
+ mov [rcx + (_BackFromUserCode.X64JmpEnd - 2 - _BackFromUserCode.SavedCr4End)], r8w
+ mov [rcx + (_BackFromUserCode.SavedSpEnd - 8 - _BackFromUserCode.SavedCr4End)], rsp
+ jmp dword far [rcx + (_EntryPoint - _BackFromUserCode.SavedCr4End)]
+.RetFromRealMode:
+ popfq
+ lgdt [rsp + 60h] ; restore protected mode GDTR
+ lidt [rsp + 50h] ; restore protected mode IDTR
+ lea eax, [rbp - IA32_REGS.size]
+ pop gs
+ pop fs
+ pop rbx
+ mov ss, ebx
+ pop rbx
+ mov es, ebx
+ pop rbx
+ mov ds, ebx
+
+ pop rdi
+ pop rsi
+ pop rbx
+ pop rbp
+
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/VmgExit.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/VmgExit.nasm new file mode 100644 index 000000000..26f034593 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/VmgExit.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; VmgExit.Asm
+;
+; Abstract:
+;
+; AsmVmgExit function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmVmgExit (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmVmgExit)
+ASM_PFX(AsmVmgExit):
+ rep vmmcall
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/Wbinvd.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/Wbinvd.nasm new file mode 100644 index 000000000..90427fe20 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/Wbinvd.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Wbinvd.Asm
+;
+; Abstract:
+;
+; AsmWbinvd function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWbinvd (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWbinvd)
+ASM_PFX(AsmWbinvd):
+ wbinvd
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr0.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr0.nasm new file mode 100644 index 000000000..d351396ff --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr0.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteCr0.Asm
+;
+; Abstract:
+;
+; AsmWriteCr0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteCr0 (
+; UINTN Cr0
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteCr0)
+ASM_PFX(AsmWriteCr0):
+ mov cr0, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr2.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr2.nasm new file mode 100644 index 000000000..2b6bce03f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr2.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteCr2.Asm
+;
+; Abstract:
+;
+; AsmWriteCr2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteCr2 (
+; UINTN Cr2
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteCr2)
+ASM_PFX(AsmWriteCr2):
+ mov cr2, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr3.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr3.nasm new file mode 100644 index 000000000..fb0b5bad2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr3.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteCr3.Asm
+;
+; Abstract:
+;
+; AsmWriteCr3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteCr3 (
+; UINTN Cr3
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteCr3)
+ASM_PFX(AsmWriteCr3):
+ mov cr3, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr4.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr4.nasm new file mode 100644 index 000000000..483a996d8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr4.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteCr4.Asm
+;
+; Abstract:
+;
+; AsmWriteCr4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteCr4 (
+; UINTN Cr4
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteCr4)
+ASM_PFX(AsmWriteCr4):
+ mov cr4, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr0.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr0.nasm new file mode 100644 index 000000000..3c8815468 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr0.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr0.Asm
+;
+; Abstract:
+;
+; AsmWriteDr0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr0 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr0)
+ASM_PFX(AsmWriteDr0):
+ mov dr0, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr1.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr1.nasm new file mode 100644 index 000000000..6fcbbfc9e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr1.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr1.Asm
+;
+; Abstract:
+;
+; AsmWriteDr1 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr1 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr1)
+ASM_PFX(AsmWriteDr1):
+ mov dr1, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr2.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr2.nasm new file mode 100644 index 000000000..a8e0bfc05 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr2.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr2.Asm
+;
+; Abstract:
+;
+; AsmWriteDr2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr2 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr2)
+ASM_PFX(AsmWriteDr2):
+ mov dr2, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr3.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr3.nasm new file mode 100644 index 000000000..ac46ab8b7 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr3.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr3.Asm
+;
+; Abstract:
+;
+; AsmWriteDr3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr3 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr3)
+ASM_PFX(AsmWriteDr3):
+ mov dr3, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr4.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr4.nasm new file mode 100644 index 000000000..c4b12c9e9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr4.nasm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr4.Asm
+;
+; Abstract:
+;
+; AsmWriteDr4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr4 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr4)
+ASM_PFX(AsmWriteDr4):
+ ;
+ ; There's no obvious reason to access this register, since it's aliased to
+ ; DR6 when DE=0 or an exception generated when DE=1
+ ;
+ DB 0xf, 0x23, 0xe1
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr5.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr5.nasm new file mode 100644 index 000000000..986a4a95d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr5.nasm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr5.Asm
+;
+; Abstract:
+;
+; AsmWriteDr5 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr5 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr5)
+ASM_PFX(AsmWriteDr5):
+ ;
+ ; There's no obvious reason to access this register, since it's aliased to
+ ; DR7 when DE=0 or an exception generated when DE=1
+ ;
+ DB 0xf, 0x23, 0xe9
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr6.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr6.nasm new file mode 100644 index 000000000..196993df2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr6.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr6.Asm
+;
+; Abstract:
+;
+; AsmWriteDr6 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr6 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr6)
+ASM_PFX(AsmWriteDr6):
+ mov dr6, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr7.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr7.nasm new file mode 100644 index 000000000..1b3c18114 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr7.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr7.Asm
+;
+; Abstract:
+;
+; AsmWriteDr7 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr7 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr7)
+ASM_PFX(AsmWriteDr7):
+ mov dr7, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteGdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteGdtr.nasm new file mode 100644 index 000000000..0a26ba099 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteGdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteGdtr.Asm
+;
+; Abstract:
+;
+; AsmWriteGdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86WriteGdtr (
+; IN CONST IA32_DESCRIPTOR *Idtr
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86WriteGdtr)
+ASM_PFX(InternalX86WriteGdtr):
+ lgdt [rcx]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteIdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteIdtr.nasm new file mode 100644 index 000000000..c6155c018 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteIdtr.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteIdtr.Asm
+;
+; Abstract:
+;
+; AsmWriteIdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86WriteIdtr (
+; IN CONST IA32_DESCRIPTOR *Idtr
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86WriteIdtr)
+ASM_PFX(InternalX86WriteIdtr):
+ pushfq
+ cli
+ lidt [rcx]
+ popfq
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteLdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteLdtr.nasm new file mode 100644 index 000000000..55881db16 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteLdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteLdtr.Asm
+;
+; Abstract:
+;
+; AsmWriteLdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteLdtr (
+; IN UINT16 Ldtr
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteLdtr)
+ASM_PFX(AsmWriteLdtr):
+ lldt cx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm0.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm0.nasm new file mode 100644 index 000000000..3f03529ed --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm0.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm0.Asm
+;
+; Abstract:
+;
+; AsmWriteMm0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm0 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm0)
+ASM_PFX(AsmWriteMm0):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x6e, 0xc1
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm1.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm1.nasm new file mode 100644 index 000000000..f552d4071 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm1.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm1.Asm
+;
+; Abstract:
+;
+; AsmWriteMm1 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm1 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm1)
+ASM_PFX(AsmWriteMm1):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x6e, 0xc9
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm2.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm2.nasm new file mode 100644 index 000000000..1bd176ced --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm2.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm2.Asm
+;
+; Abstract:
+;
+; AsmWriteMm2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm2 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm2)
+ASM_PFX(AsmWriteMm2):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x6e, 0xd1
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm3.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm3.nasm new file mode 100644 index 000000000..403f14073 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm3.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm3.Asm
+;
+; Abstract:
+;
+; AsmWriteMm3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm3 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm3)
+ASM_PFX(AsmWriteMm3):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x6e, 0xd9
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm4.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm4.nasm new file mode 100644 index 000000000..d99709d49 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm4.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm4.Asm
+;
+; Abstract:
+;
+; AsmWriteMm4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm4 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm4)
+ASM_PFX(AsmWriteMm4):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x6e, 0xe1
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm5.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm5.nasm new file mode 100644 index 000000000..0467ac422 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm5.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm5.Asm
+;
+; Abstract:
+;
+; AsmWriteMm5 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm5 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm5)
+ASM_PFX(AsmWriteMm5):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x6e, 0xe9
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm6.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm6.nasm new file mode 100644 index 000000000..6d2e5eb8f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm6.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm6.Asm
+;
+; Abstract:
+;
+; AsmWriteMm6 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm6 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm6)
+ASM_PFX(AsmWriteMm6):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x6e, 0xf1
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm7.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm7.nasm new file mode 100644 index 000000000..de72adf68 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm7.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm7.Asm
+;
+; Abstract:
+;
+; AsmWriteMm7 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm7 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm7)
+ASM_PFX(AsmWriteMm7):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x6e, 0xf9
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMsr64.c b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMsr64.c new file mode 100644 index 000000000..98c5458d8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMsr64.c @@ -0,0 +1,36 @@ +/** @file
+ CpuBreakpoint function.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
+**/
+
+void __writemsr (unsigned long Register, unsigned __int64 Value);
+
+#pragma intrinsic(__writemsr)
+
+/**
+ Write data to MSR.
+
+ @param Index The register index of MSR.
+ @param Value Data wants to be written.
+
+ @return Value written to MSR.
+
+**/
+UINT64
+EFIAPI
+AsmWriteMsr64 (
+ IN UINT32 Index,
+ IN UINT64 Value
+ )
+{
+ __writemsr (Index, Value);
+ return Value;
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMsr64.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMsr64.nasm new file mode 100644 index 000000000..11224d304 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMsr64.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMsr64.Asm
+;
+; Abstract:
+;
+; AsmWriteMsr64 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmWriteMsr64 (
+; IN UINT32 Index,
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMsr64)
+ASM_PFX(AsmWriteMsr64):
+ mov rax, rdx ; meanwhile, rax <- return value
+ shr rdx, 0x20 ; edx:eax contains the value to write
+ wrmsr
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteTr.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteTr.nasm new file mode 100644 index 000000000..4e364bc8e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteTr.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteTr.nasm
+;
+; Abstract:
+;
+; Write TR register
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; AsmWriteTr (
+; UINT16 Selector
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteTr)
+ASM_PFX(AsmWriteTr):
+ mov eax, ecx
+ ltr ax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/XGetBv.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/XGetBv.nasm new file mode 100644 index 000000000..09f3be8ae --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/XGetBv.nasm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; XGetBv.Asm
+;
+; Abstract:
+;
+; AsmXgetBv function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmXGetBv (
+; IN UINT32 Index
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmXGetBv)
+ASM_PFX(AsmXGetBv):
+ xgetbv
+ shl rdx, 32
+ or rax, rdx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86DisablePaging32.c b/roms/edk2/MdePkg/Library/BaseLib/X86DisablePaging32.c new file mode 100644 index 000000000..b7378c028 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86DisablePaging32.c @@ -0,0 +1,60 @@ +/** @file
+ IA-32/x64 AsmDisablePaging32()
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Disables the 32-bit paging mode on the CPU.
+
+ Disables the 32-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 32-paged protected
+ mode. This function is only available on IA-32. After the 32-bit paging mode
+ is disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be NULL. The function EntryPoint must never return.
+
+ If the current execution mode is not 32-bit paged mode, then ASSERT().
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit paged mode.
+ 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.
+ 4) CR3 must point to valid page tables that guarantee that the pages for
+ this function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is disabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is disabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is
+ disabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+AsmDisablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack
+ )
+{
+ ASSERT (EntryPoint != NULL);
+ ASSERT (NewStack != NULL);
+ InternalX86DisablePaging32 (EntryPoint, Context1, Context2, NewStack);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86DisablePaging64.c b/roms/edk2/MdePkg/Library/BaseLib/X86DisablePaging64.c new file mode 100644 index 000000000..867a8eba9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86DisablePaging64.c @@ -0,0 +1,57 @@ +/** @file
+ IA-32/x64 AsmDisablePaging64()
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Disables the 64-bit paging mode on the CPU.
+
+ Disables the 64-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 64-paging mode.
+ This function is only available on x64. After the 64-bit paging mode is
+ disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be 0. The function EntryPoint must never return.
+
+ If the current execution mode is not 64-bit paged mode, then ASSERT().
+ If EntryPoint is 0, then ASSERT().
+ If NewStack is 0, then ASSERT().
+
+ @param Cs The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for 32-bit protected mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is disabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is disabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is disabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+AsmDisablePaging64 (
+ IN UINT16 Cs,
+ IN UINT32 EntryPoint,
+ IN UINT32 Context1, OPTIONAL
+ IN UINT32 Context2, OPTIONAL
+ IN UINT32 NewStack
+ )
+{
+ ASSERT (EntryPoint != 0);
+ ASSERT (NewStack != 0);
+ InternalX86DisablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86EnablePaging32.c b/roms/edk2/MdePkg/Library/BaseLib/X86EnablePaging32.c new file mode 100644 index 000000000..32a0054d2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86EnablePaging32.c @@ -0,0 +1,63 @@ +/** @file
+ IA-32/x64 AsmEnablePaging32()
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Enables the 32-bit paging mode on the CPU.
+
+ Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode. This function is
+ only available on IA-32. After the 32-bit paging mode is enabled, control is
+ transferred to the function specified by EntryPoint using the new stack
+ specified by NewStack and passing in the parameters specified by Context1 and
+ Context2. Context1 and Context2 are optional and may be NULL. The function
+ EntryPoint must never return.
+
+ If the current execution mode is not 32-bit protected mode, then ASSERT().
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit protected mode with flat descriptors. This
+ means all descriptors must have a base of 0 and a limit of 4GB.
+ 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat
+ descriptors.
+ 4) CR3 must point to valid page tables that will be used once the transition
+ is complete, and those page tables must guarantee that the pages for this
+ function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is enabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is enabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is enabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+AsmEnablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack
+ )
+{
+ ASSERT (EntryPoint != NULL);
+ ASSERT (NewStack != NULL);
+ InternalX86EnablePaging32 (EntryPoint, Context1, Context2, NewStack);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86EnablePaging64.c b/roms/edk2/MdePkg/Library/BaseLib/X86EnablePaging64.c new file mode 100644 index 000000000..1323e68de --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86EnablePaging64.c @@ -0,0 +1,59 @@ +/** @file
+ IA-32/x64 AsmEnablePaging64()
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Enables the 64-bit paging mode on the CPU.
+
+ Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode with flat
+ descriptors. This function is only available on IA-32. After the 64-bit
+ paging mode is enabled, control is transferred to the function specified by
+ EntryPoint using the new stack specified by NewStack and passing in the
+ parameters specified by Context1 and Context2. Context1 and Context2 are
+ optional and may be 0. The function EntryPoint must never return.
+
+ If the current execution mode is not 32-bit protected mode with flat
+ descriptors, then ASSERT().
+ If EntryPoint is 0, then ASSERT().
+ If NewStack is 0, then ASSERT().
+
+ @param Cs The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for long mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is enabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is enabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is enabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+AsmEnablePaging64 (
+ IN UINT16 Cs,
+ IN UINT64 EntryPoint,
+ IN UINT64 Context1, OPTIONAL
+ IN UINT64 Context2, OPTIONAL
+ IN UINT64 NewStack
+ )
+{
+ ASSERT (EntryPoint != 0);
+ ASSERT (NewStack != 0);
+ InternalX86EnablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86FxRestore.c b/roms/edk2/MdePkg/Library/BaseLib/X86FxRestore.c new file mode 100644 index 000000000..c4fa66856 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86FxRestore.c @@ -0,0 +1,43 @@ +/** @file
+ IA-32/x64 AsmFxRestore()
+
+ Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Restores the current floating point/SSE/SSE2 context from a buffer.
+
+ Restores the current floating point/SSE/SSE2 state from the buffer specified
+ by Buffer. Buffer must be aligned on a 16-byte boundary. This function is
+ only available on IA-32 and x64.
+
+ If Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 16-byte boundary, then ASSERT().
+ If Buffer was not saved with AsmFxSave(), then ASSERT().
+
+ @param Buffer A pointer to a buffer to save the floating point/SSE/SSE2 context.
+
+**/
+VOID
+EFIAPI
+AsmFxRestore (
+ IN CONST IA32_FX_BUFFER *Buffer
+ )
+{
+ ASSERT (Buffer != NULL);
+ ASSERT (0 == ((UINTN)Buffer & 0xf));
+
+ //
+ // Check the flag recorded by AsmFxSave()
+ //
+ ASSERT (0xAA5555AA == *(UINT32 *) (&Buffer->Buffer[sizeof (Buffer->Buffer) - 4]));
+
+ InternalX86FxRestore (Buffer);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86FxSave.c b/roms/edk2/MdePkg/Library/BaseLib/X86FxSave.c new file mode 100644 index 000000000..2621a08a3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86FxSave.c @@ -0,0 +1,42 @@ +/** @file
+ IA-32/x64 AsmFxSave()
+
+ Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Save the current floating point/SSE/SSE2 context to a buffer.
+
+ Saves the current floating point/SSE/SSE2 state to the buffer specified by
+ Buffer. Buffer must be aligned on a 16-byte boundary. This function is only
+ available on IA-32 and x64.
+
+ If Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 16-byte boundary, then ASSERT().
+
+ @param Buffer A pointer to a buffer to save the floating point/SSE/SSE2 context.
+
+**/
+VOID
+EFIAPI
+AsmFxSave (
+ OUT IA32_FX_BUFFER *Buffer
+ )
+{
+ ASSERT (Buffer != NULL);
+ ASSERT (0 == ((UINTN)Buffer & 0xf));
+
+ InternalX86FxSave (Buffer);
+
+ //
+ // Mark one flag at end of Buffer, it will be check by AsmFxRestor()
+ //
+ *(UINT32 *) (&Buffer->Buffer[sizeof (Buffer->Buffer) - 4]) = 0xAA5555AA;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86GetInterruptState.c b/roms/edk2/MdePkg/Library/BaseLib/X86GetInterruptState.c new file mode 100644 index 000000000..4363a7fda --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86GetInterruptState.c @@ -0,0 +1,35 @@ +/** @file
+ IA-32/x64 GetInterruptState()
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+
+/**
+ Retrieves the current CPU interrupt state.
+
+ Returns TRUE is interrupts are currently enabled. Otherwise
+ returns FALSE.
+
+ @retval TRUE CPU interrupts are enabled.
+ @retval FALSE CPU interrupts are disabled.
+
+**/
+BOOLEAN
+EFIAPI
+GetInterruptState (
+ VOID
+ )
+{
+ IA32_EFLAGS32 EFlags;
+
+ EFlags.UintN = AsmReadEflags ();
+ return (BOOLEAN)(1 == EFlags.Bits.IF);
+}
+
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86MemoryFence.c b/roms/edk2/MdePkg/Library/BaseLib/X86MemoryFence.c new file mode 100644 index 000000000..399b36b56 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86MemoryFence.c @@ -0,0 +1,26 @@ +/** @file
+ IA-32/x64 MemoryFence().
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+ Used to serialize load and store operations.
+
+ All loads and stores that proceed calls to this function are guaranteed to be
+ globally visible when this function returns.
+
+**/
+VOID
+EFIAPI
+MemoryFence (
+ VOID
+ )
+{
+ return;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86Msr.c b/roms/edk2/MdePkg/Library/BaseLib/X86Msr.c new file mode 100644 index 000000000..ea51ca9ad --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86Msr.c @@ -0,0 +1,654 @@ +/** @file
+ IA-32/x64 MSR functions.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+
+/**
+ Returns the lower 32-bits of a Machine Specific Register(MSR).
+
+ Reads and returns the lower 32-bits of the MSR specified by Index.
+ No parameter checking is performed on Index, and some Index values may cause
+ CPU exceptions. The caller must either guarantee that Index is valid, or the
+ caller must set up exception handlers to catch the exceptions. This function
+ is only available on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to read.
+
+ @return The lower 32 bits of the MSR identified by Index.
+
+**/
+UINT32
+EFIAPI
+AsmReadMsr32 (
+ IN UINT32 Index
+ )
+{
+ return (UINT32)AsmReadMsr64 (Index);
+}
+
+/**
+ Writes a 32-bit value to a Machine Specific Register(MSR), and returns the value.
+ The upper 32-bits of the MSR are set to zero.
+
+ Writes the 32-bit value specified by Value to the MSR specified by Index. The
+ upper 32-bits of the MSR write are set to zero. The 32-bit value written to
+ the MSR is returned. No parameter checking is performed on Index or Value,
+ and some of these may cause CPU exceptions. The caller must either guarantee
+ that Index and Value are valid, or the caller must establish proper exception
+ handlers. This function is only available on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param Value The 32-bit value to write to the MSR.
+
+ @return Value
+
+**/
+UINT32
+EFIAPI
+AsmWriteMsr32 (
+ IN UINT32 Index,
+ IN UINT32 Value
+ )
+{
+ return (UINT32)AsmWriteMsr64 (Index, Value);
+}
+
+/**
+ Reads a 64-bit MSR, performs a bitwise OR on the lower 32-bits, and
+ writes the result back to the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR
+ between the lower 32-bits of the read result and the value specified by
+ OrData, and writes the result to the 64-bit MSR specified by Index. The lower
+ 32-bits of the value written to the MSR is returned. No parameter checking is
+ performed on Index or OrData, and some of these may cause CPU exceptions. The
+ caller must either guarantee that Index and OrData are valid, or the caller
+ must establish proper exception handlers. This function is only available on
+ IA-32 and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param OrData The value to OR with the read value from the MSR.
+
+ @return The lower 32-bit value written to the MSR.
+
+**/
+UINT32
+EFIAPI
+AsmMsrOr32 (
+ IN UINT32 Index,
+ IN UINT32 OrData
+ )
+{
+ return (UINT32)AsmMsrOr64 (Index, OrData);
+}
+
+/**
+ Reads a 64-bit MSR, performs a bitwise AND on the lower 32-bits, and writes
+ the result back to the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between the
+ lower 32-bits of the read result and the value specified by AndData, and
+ writes the result to the 64-bit MSR specified by Index. The lower 32-bits of
+ the value written to the MSR is returned. No parameter checking is performed
+ on Index or AndData, and some of these may cause CPU exceptions. The caller
+ must either guarantee that Index and AndData are valid, or the caller must
+ establish proper exception handlers. This function is only available on IA-32
+ and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param AndData The value to AND with the read value from the MSR.
+
+ @return The lower 32-bit value written to the MSR.
+
+**/
+UINT32
+EFIAPI
+AsmMsrAnd32 (
+ IN UINT32 Index,
+ IN UINT32 AndData
+ )
+{
+ return (UINT32)AsmMsrAnd64 (Index, AndData);
+}
+
+/**
+ Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise OR
+ on the lower 32-bits, and writes the result back to the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between the
+ lower 32-bits of the read result and the value specified by AndData
+ preserving the upper 32-bits, performs a bitwise OR between the
+ result of the AND operation and the value specified by OrData, and writes the
+ result to the 64-bit MSR specified by Address. The lower 32-bits of the value
+ written to the MSR is returned. No parameter checking is performed on Index,
+ AndData, or OrData, and some of these may cause CPU exceptions. The caller
+ must either guarantee that Index, AndData, and OrData are valid, or the
+ caller must establish proper exception handlers. This function is only
+ available on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param AndData The value to AND with the read value from the MSR.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The lower 32-bit value written to the MSR.
+
+**/
+UINT32
+EFIAPI
+AsmMsrAndThenOr32 (
+ IN UINT32 Index,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return (UINT32)AsmMsrAndThenOr64 (Index, AndData, OrData);
+}
+
+/**
+ Reads a bit field of an MSR.
+
+ Reads the bit field in the lower 32-bits of a 64-bit MSR. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned. The caller must either guarantee that Index is valid, or the caller
+ must set up exception handlers to catch the exceptions. This function is only
+ available on IA-32 and x64.
+
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The bit field read from the MSR.
+
+**/
+UINT32
+EFIAPI
+AsmMsrBitFieldRead32 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead32 (AsmReadMsr32 (Index), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to an MSR.
+
+ Writes Value to a bit field in the lower 32-bits of a 64-bit MSR. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination MSR are preserved. The lower 32-bits of the MSR written is
+ returned. The caller must either guarantee that Index and the data written
+ is valid, or the caller must set up exception handlers to catch the exceptions.
+ This function is only available on IA-32 and x64.
+
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value The new value of the bit field.
+
+ @return The lower 32-bit of the value written to the MSR.
+
+**/
+UINT32
+EFIAPI
+AsmMsrBitFieldWrite32 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ ASSERT (EndBit < sizeof (Value) * 8);
+ ASSERT (StartBit <= EndBit);
+ return (UINT32)AsmMsrBitFieldWrite64 (Index, StartBit, EndBit, Value);
+}
+
+/**
+ Reads a bit field in a 64-bit MSR, performs a bitwise OR, and writes the
+ result back to the bit field in the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 64-bit MSR specified by Index. The lower 32-bits of the value
+ written to the MSR are returned. Extra left bits in OrData are stripped. The
+ caller must either guarantee that Index and the data written is valid, or
+ the caller must set up exception handlers to catch the exceptions. This
+ function is only available on IA-32 and x64.
+
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the read value from the MSR.
+
+ @return The lower 32-bit of the value written to the MSR.
+
+**/
+UINT32
+EFIAPI
+AsmMsrBitFieldOr32 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ ASSERT (EndBit < sizeof (OrData) * 8);
+ ASSERT (StartBit <= EndBit);
+ return (UINT32)AsmMsrBitFieldOr64 (Index, StartBit, EndBit, OrData);
+}
+
+/**
+ Reads a bit field in a 64-bit MSR, performs a bitwise AND, and writes the
+ result back to the bit field in the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between the
+ read result and the value specified by AndData, and writes the result to the
+ 64-bit MSR specified by Index. The lower 32-bits of the value written to the
+ MSR are returned. Extra left bits in AndData are stripped. The caller must
+ either guarantee that Index and the data written is valid, or the caller must
+ set up exception handlers to catch the exceptions. This function is only
+ available on IA-32 and x64.
+
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the read value from the MSR.
+
+ @return The lower 32-bit of the value written to the MSR.
+
+**/
+UINT32
+EFIAPI
+AsmMsrBitFieldAnd32 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ ASSERT (EndBit < sizeof (AndData) * 8);
+ ASSERT (StartBit <= EndBit);
+ return (UINT32)AsmMsrBitFieldAnd64 (Index, StartBit, EndBit, AndData);
+}
+
+/**
+ Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND followed by a
+ bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 64-bit MSR specified by Index. The
+ lower 32-bits of the value written to the MSR are returned. Extra left bits
+ in both AndData and OrData are stripped. The caller must either guarantee
+ that Index and the data written is valid, or the caller must set up exception
+ handlers to catch the exceptions. This function is only available on IA-32
+ and x64.
+
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the read value from the MSR.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The lower 32-bit of the value written to the MSR.
+
+**/
+UINT32
+EFIAPI
+AsmMsrBitFieldAndThenOr32 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ ASSERT (EndBit < sizeof (AndData) * 8);
+ ASSERT (StartBit <= EndBit);
+ return (UINT32)AsmMsrBitFieldAndThenOr64 (
+ Index,
+ StartBit,
+ EndBit,
+ AndData,
+ OrData
+ );
+}
+
+/**
+ Reads a 64-bit MSR, performs a bitwise OR, and writes the result
+ back to the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 64-bit MSR specified by Index. The value written to the MSR is
+ returned. No parameter checking is performed on Index or OrData, and some of
+ these may cause CPU exceptions. The caller must either guarantee that Index
+ and OrData are valid, or the caller must establish proper exception handlers.
+ This function is only available on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param OrData The value to OR with the read value from the MSR.
+
+ @return The value written back to the MSR.
+
+**/
+UINT64
+EFIAPI
+AsmMsrOr64 (
+ IN UINT32 Index,
+ IN UINT64 OrData
+ )
+{
+ return AsmWriteMsr64 (Index, AsmReadMsr64 (Index) | OrData);
+}
+
+/**
+ Reads a 64-bit MSR, performs a bitwise AND, and writes the result back to the
+ 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between the
+ read result and the value specified by OrData, and writes the result to the
+ 64-bit MSR specified by Index. The value written to the MSR is returned. No
+ parameter checking is performed on Index or OrData, and some of these may
+ cause CPU exceptions. The caller must either guarantee that Index and OrData
+ are valid, or the caller must establish proper exception handlers. This
+ function is only available on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param AndData The value to AND with the read value from the MSR.
+
+ @return The value written back to the MSR.
+
+**/
+UINT64
+EFIAPI
+AsmMsrAnd64 (
+ IN UINT32 Index,
+ IN UINT64 AndData
+ )
+{
+ return AsmWriteMsr64 (Index, AsmReadMsr64 (Index) & AndData);
+}
+
+/**
+ Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise
+ OR, and writes the result back to the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between read
+ result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 64-bit MSR specified by Index. The value written
+ to the MSR is returned. No parameter checking is performed on Index, AndData,
+ or OrData, and some of these may cause CPU exceptions. The caller must either
+ guarantee that Index, AndData, and OrData are valid, or the caller must
+ establish proper exception handlers. This function is only available on IA-32
+ and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param AndData The value to AND with the read value from the MSR.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MSR.
+
+**/
+UINT64
+EFIAPI
+AsmMsrAndThenOr64 (
+ IN UINT32 Index,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ )
+{
+ return AsmWriteMsr64 (Index, (AsmReadMsr64 (Index) & AndData) | OrData);
+}
+
+/**
+ Reads a bit field of an MSR.
+
+ Reads the bit field in the 64-bit MSR. The bit field is specified by the
+ StartBit and the EndBit. The value of the bit field is returned. The caller
+ must either guarantee that Index is valid, or the caller must set up
+ exception handlers to catch the exceptions. This function is only available
+ on IA-32 and x64.
+
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+
+ @return The value read from the MSR.
+
+**/
+UINT64
+EFIAPI
+AsmMsrBitFieldRead64 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead64 (AsmReadMsr64 (Index), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to an MSR.
+
+ Writes Value to a bit field in a 64-bit MSR. The bit field is specified by
+ the StartBit and the EndBit. All other bits in the destination MSR are
+ preserved. The MSR written is returned. The caller must either guarantee
+ that Index and the data written is valid, or the caller must set up exception
+ handlers to catch the exceptions. This function is only available on IA-32 and x64.
+
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param Value The new value of the bit field.
+
+ @return The value written back to the MSR.
+
+**/
+UINT64
+EFIAPI
+AsmMsrBitFieldWrite64 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
+ )
+{
+ return AsmWriteMsr64 (
+ Index,
+ BitFieldWrite64 (AsmReadMsr64 (Index), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 64-bit MSR, performs a bitwise OR, and
+ writes the result back to the bit field in the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 64-bit MSR specified by Index. The value written to the MSR is
+ returned. Extra left bits in OrData are stripped. The caller must either
+ guarantee that Index and the data written is valid, or the caller must set up
+ exception handlers to catch the exceptions. This function is only available
+ on IA-32 and x64.
+
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param OrData The value to OR with the read value from the bit field.
+
+ @return The value written back to the MSR.
+
+**/
+UINT64
+EFIAPI
+AsmMsrBitFieldOr64 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
+ )
+{
+ return AsmWriteMsr64 (
+ Index,
+ BitFieldOr64 (AsmReadMsr64 (Index), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 64-bit MSR, performs a bitwise AND, and writes the
+ result back to the bit field in the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between the
+ read result and the value specified by AndData, and writes the result to the
+ 64-bit MSR specified by Index. The value written to the MSR is returned.
+ Extra left bits in AndData are stripped. The caller must either guarantee
+ that Index and the data written is valid, or the caller must set up exception
+ handlers to catch the exceptions. This function is only available on IA-32
+ and x64.
+
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with the read value from the bit field.
+
+ @return The value written back to the MSR.
+
+**/
+UINT64
+EFIAPI
+AsmMsrBitFieldAnd64 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
+ )
+{
+ return AsmWriteMsr64 (
+ Index,
+ BitFieldAnd64 (AsmReadMsr64 (Index), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND followed by
+ a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 64-bit MSR specified by Index. The
+ value written to the MSR is returned. Extra left bits in both AndData and
+ OrData are stripped. The caller must either guarantee that Index and the data
+ written is valid, or the caller must set up exception handlers to catch the
+ exceptions. This function is only available on IA-32 and x64.
+
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with the read value from the bit field.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MSR.
+
+**/
+UINT64
+EFIAPI
+AsmMsrBitFieldAndThenOr64 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ )
+{
+ return AsmWriteMsr64 (
+ Index,
+ BitFieldAndThenOr64 (
+ AsmReadMsr64 (Index),
+ StartBit,
+ EndBit,
+ AndData,
+ OrData
+ )
+ );
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86PatchInstruction.c b/roms/edk2/MdePkg/Library/BaseLib/X86PatchInstruction.c new file mode 100644 index 000000000..fc70a352d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86PatchInstruction.c @@ -0,0 +1,83 @@ +/** @file
+ IA-32/x64 PatchInstructionX86()
+
+ Copyright (C) 2018, Intel Corporation. All rights reserved.<BR>
+ Copyright (C) 2018, Red Hat, Inc.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Patch the immediate operand of an IA32 or X64 instruction such that the byte,
+ word, dword or qword operand is encoded at the end of the instruction's
+ binary representation.
+
+ This function should be used to update object code that was compiled with
+ NASM from assembly source code. Example:
+
+ NASM source code:
+
+ mov eax, strict dword 0 ; the imm32 zero operand will be patched
+ ASM_PFX(gPatchCr3):
+ mov cr3, eax
+
+ C source code:
+
+ X86_ASSEMBLY_PATCH_LABEL gPatchCr3;
+ PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);
+
+ @param[out] InstructionEnd Pointer right past the instruction to patch. The
+ immediate operand to patch is expected to
+ comprise the trailing bytes of the instruction.
+ If InstructionEnd is closer to address 0 than
+ ValueSize permits, then ASSERT().
+
+ @param[in] PatchValue The constant to write to the immediate operand.
+ The caller is responsible for ensuring that
+ PatchValue can be represented in the byte, word,
+ dword or qword operand (as indicated through
+ ValueSize); otherwise ASSERT().
+
+ @param[in] ValueSize The size of the operand in bytes; must be 1, 2,
+ 4, or 8. ASSERT() otherwise.
+**/
+VOID
+EFIAPI
+PatchInstructionX86 (
+ OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
+ IN UINT64 PatchValue,
+ IN UINTN ValueSize
+ )
+{
+ //
+ // The equality ((UINTN)InstructionEnd == ValueSize) would assume a zero-size
+ // instruction at address 0; forbid it.
+ //
+ ASSERT ((UINTN)InstructionEnd > ValueSize);
+
+ switch (ValueSize) {
+ case 1:
+ ASSERT (PatchValue <= MAX_UINT8);
+ *((UINT8 *)(UINTN)InstructionEnd - 1) = (UINT8)PatchValue;
+ break;
+
+ case 2:
+ ASSERT (PatchValue <= MAX_UINT16);
+ WriteUnaligned16 ((UINT16 *)(UINTN)InstructionEnd - 1, (UINT16)PatchValue);
+ break;
+
+ case 4:
+ ASSERT (PatchValue <= MAX_UINT32);
+ WriteUnaligned32 ((UINT32 *)(UINTN)InstructionEnd - 1, (UINT32)PatchValue);
+ break;
+
+ case 8:
+ WriteUnaligned64 ((UINT64 *)(UINTN)InstructionEnd - 1, PatchValue);
+ break;
+
+ default:
+ ASSERT (FALSE);
+ }
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86RdRand.c b/roms/edk2/MdePkg/Library/BaseLib/X86RdRand.c new file mode 100644 index 000000000..dcbd96957 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86RdRand.c @@ -0,0 +1,73 @@ +/** @file
+ IA-32/x64 AsmRdRandxx()
+ Generates random number through CPU RdRand instruction.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Generates a 16-bit random number through RDRAND instruction.
+
+ if Rand is NULL, then ASSERT().
+
+ @param[out] Rand Buffer pointer to store the random result.
+
+ @retval TRUE RDRAND call was successful.
+ @retval FALSE Failed attempts to call RDRAND.
+
+ **/
+BOOLEAN
+EFIAPI
+AsmRdRand16 (
+ OUT UINT16 *Rand
+ )
+{
+ ASSERT (Rand != NULL);
+ return InternalX86RdRand16 (Rand);
+}
+
+/**
+ Generates a 32-bit random number through RDRAND instruction.
+
+ if Rand is NULL, then ASSERT().
+
+ @param[out] Rand Buffer pointer to store the random result.
+
+ @retval TRUE RDRAND call was successful.
+ @retval FALSE Failed attempts to call RDRAND.
+
+**/
+BOOLEAN
+EFIAPI
+AsmRdRand32 (
+ OUT UINT32 *Rand
+ )
+{
+ ASSERT (Rand != NULL);
+ return InternalX86RdRand32 (Rand);
+}
+
+/**
+ Generates a 64-bit random number through RDRAND instruction.
+
+ if Rand is NULL, then ASSERT().
+
+ @param[out] Rand Buffer pointer to store the random result.
+
+ @retval TRUE RDRAND call was successful.
+ @retval FALSE Failed attempts to call RDRAND.
+
+**/
+BOOLEAN
+EFIAPI
+AsmRdRand64 (
+ OUT UINT64 *Rand
+ )
+{
+ ASSERT (Rand != NULL);
+ return InternalX86RdRand64 (Rand);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86ReadGdtr.c b/roms/edk2/MdePkg/Library/BaseLib/X86ReadGdtr.c new file mode 100644 index 000000000..ca7c5de6a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86ReadGdtr.c @@ -0,0 +1,33 @@ +/** @file
+ IA-32/x64 AsmReadGdtr()
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Reads the current Global Descriptor Table Register(GDTR) descriptor.
+
+ Reads and returns the current GDTR descriptor and returns it in Gdtr. This
+ function is only available on IA-32 and x64.
+
+ If Gdtr is NULL, then ASSERT().
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+AsmReadGdtr (
+ OUT IA32_DESCRIPTOR *Gdtr
+ )
+{
+ ASSERT (Gdtr != NULL);
+ InternalX86ReadGdtr (Gdtr);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86ReadIdtr.c b/roms/edk2/MdePkg/Library/BaseLib/X86ReadIdtr.c new file mode 100644 index 000000000..f9133f9aa --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86ReadIdtr.c @@ -0,0 +1,33 @@ +/** @file
+ IA-32/x64 AsmReadIdtr()
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.
+
+ Reads and returns the current IDTR descriptor and returns it in Idtr. This
+ function is only available on IA-32 and x64.
+
+ If Idtr is NULL, then ASSERT().
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+AsmReadIdtr (
+ OUT IA32_DESCRIPTOR *Idtr
+ )
+{
+ ASSERT (Idtr != NULL);
+ InternalX86ReadIdtr (Idtr);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86SpeculationBarrier.c b/roms/edk2/MdePkg/Library/BaseLib/X86SpeculationBarrier.c new file mode 100644 index 000000000..b28fd8de9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86SpeculationBarrier.c @@ -0,0 +1,30 @@ +/** @file
+ SpeculationBarrier() function for IA32 and x64.
+
+ Copyright (C) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseLib.h>
+
+/**
+ Uses as a barrier to stop speculative execution.
+
+ Ensures that no later instruction will execute speculatively, until all prior
+ instructions have completed.
+
+**/
+VOID
+EFIAPI
+SpeculationBarrier (
+ VOID
+ )
+{
+ if (PcdGet8 (PcdSpeculationBarrierType) == 0x01) {
+ AsmLfence ();
+ } else if (PcdGet8 (PcdSpeculationBarrierType) == 0x02) {
+ AsmCpuid (0x01, NULL, NULL, NULL, NULL);
+ }
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86Thunk.c b/roms/edk2/MdePkg/Library/BaseLib/X86Thunk.c new file mode 100644 index 000000000..5c8a03989 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86Thunk.c @@ -0,0 +1,262 @@ +/** @file
+ Real Mode Thunk Functions for IA32 and x64.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+extern CONST UINT8 m16Start;
+extern CONST UINT16 m16Size;
+extern CONST UINT16 mThunk16Attr;
+extern CONST UINT16 m16Gdt;
+extern CONST UINT16 m16GdtrBase;
+extern CONST UINT16 mTransition;
+
+/**
+ Invokes 16-bit code in big real mode and returns the updated register set.
+
+ This function transfers control to the 16-bit code specified by CS:EIP using
+ the stack specified by SS:ESP in RegisterSet. The updated registers are saved
+ on the real mode stack and the starting address of the save area is returned.
+
+ @param RegisterSet Values of registers before invocation of 16-bit code.
+ @param Transition The pointer to the transition code under 1MB.
+
+ @return The pointer to a IA32_REGISTER_SET structure containing the updated
+ register values.
+
+**/
+IA32_REGISTER_SET *
+EFIAPI
+InternalAsmThunk16 (
+ IN IA32_REGISTER_SET *RegisterSet,
+ IN OUT VOID *Transition
+ );
+
+/**
+ Retrieves the properties for 16-bit thunk functions.
+
+ Computes the size of the buffer and stack below 1MB required to use the
+ AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This
+ buffer size is returned in RealModeBufferSize, and the stack size is returned
+ in ExtraStackSize. If parameters are passed to the 16-bit real mode code,
+ then the actual minimum stack size is ExtraStackSize plus the maximum number
+ of bytes that need to be passed to the 16-bit real mode code.
+
+ If RealModeBufferSize is NULL, then ASSERT().
+ If ExtraStackSize is NULL, then ASSERT().
+
+ @param RealModeBufferSize A pointer to the size of the buffer below 1MB
+ required to use the 16-bit thunk functions.
+ @param ExtraStackSize A pointer to the extra size of stack below 1MB
+ that the 16-bit thunk functions require for
+ temporary storage in the transition to and from
+ 16-bit real mode.
+
+**/
+VOID
+EFIAPI
+AsmGetThunk16Properties (
+ OUT UINT32 *RealModeBufferSize,
+ OUT UINT32 *ExtraStackSize
+ )
+{
+ ASSERT (RealModeBufferSize != NULL);
+ ASSERT (ExtraStackSize != NULL);
+
+ *RealModeBufferSize = m16Size;
+
+ //
+ // Extra 4 bytes for return address, and another 4 bytes for mode transition
+ //
+ *ExtraStackSize = sizeof (IA32_DWORD_REGS) + 8;
+}
+
+/**
+ Prepares all structures a code required to use AsmThunk16().
+
+ Prepares all structures and code required to use AsmThunk16().
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
+
+ If ThunkContext is NULL, then ASSERT().
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+AsmPrepareThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ )
+{
+ IA32_SEGMENT_DESCRIPTOR *RealModeGdt;
+
+ ASSERT (ThunkContext != NULL);
+ ASSERT ((UINTN)ThunkContext->RealModeBuffer < 0x100000);
+ ASSERT (ThunkContext->RealModeBufferSize >= m16Size);
+ ASSERT ((UINTN)ThunkContext->RealModeBuffer + m16Size <= 0x100000);
+
+ CopyMem (ThunkContext->RealModeBuffer, &m16Start, m16Size);
+
+ //
+ // Point RealModeGdt to the GDT to be used in transition
+ //
+ // RealModeGdt[0]: Reserved as NULL descriptor
+ // RealModeGdt[1]: Code Segment
+ // RealModeGdt[2]: Data Segment
+ // RealModeGdt[3]: Call Gate
+ //
+ RealModeGdt = (IA32_SEGMENT_DESCRIPTOR*)(
+ (UINTN)ThunkContext->RealModeBuffer + m16Gdt);
+
+ //
+ // Update Code & Data Segment Descriptor
+ //
+ RealModeGdt[1].Bits.BaseLow =
+ (UINT32)(UINTN)ThunkContext->RealModeBuffer & ~0xf;
+ RealModeGdt[1].Bits.BaseMid =
+ (UINT32)(UINTN)ThunkContext->RealModeBuffer >> 16;
+
+ //
+ // Update transition code entry point offset
+ //
+ *(UINT32*)((UINTN)ThunkContext->RealModeBuffer + mTransition) +=
+ (UINT32)(UINTN)ThunkContext->RealModeBuffer & 0xf;
+
+ //
+ // Update Segment Limits for both Code and Data Segment Descriptors
+ //
+ if ((ThunkContext->ThunkAttributes & THUNK_ATTRIBUTE_BIG_REAL_MODE) == 0) {
+ //
+ // Set segment limits to 64KB
+ //
+ RealModeGdt[1].Bits.LimitHigh = 0;
+ RealModeGdt[1].Bits.G = 0;
+ RealModeGdt[2].Bits.LimitHigh = 0;
+ RealModeGdt[2].Bits.G = 0;
+ }
+
+ //
+ // Update GDTBASE for this thunk context
+ //
+ *(VOID**)((UINTN)ThunkContext->RealModeBuffer + m16GdtrBase) = RealModeGdt;
+
+ //
+ // Update Thunk Attributes
+ //
+ *(UINT32*)((UINTN)ThunkContext->RealModeBuffer + mThunk16Attr) =
+ ThunkContext->ThunkAttributes;
+}
+
+/**
+ Transfers control to a 16-bit real mode entry point and returns the results.
+
+ Transfers control to a 16-bit real mode entry point and returns the results.
+ AsmPrepareThunk16() must be called with ThunkContext before this function is used.
+ This function must be called with interrupts disabled.
+
+ The register state from the RealModeState field of ThunkContext is restored just prior
+ to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState,
+ which is used to set the interrupt state when a 16-bit real mode entry point is called.
+ Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.
+ The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to
+ the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.
+ The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,
+ so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment
+ and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry
+ point must exit with a RETF instruction. The register state is captured into RealModeState immediately
+ after the RETF instruction is executed.
+
+ If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
+ or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure
+ the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.
+
+ If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
+ then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.
+ This includes the base vectors, the interrupt masks, and the edge/level trigger mode.
+
+ If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code
+ is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.
+
+ If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
+ ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to
+ disable the A20 mask.
+
+ If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in
+ ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails,
+ then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
+
+ If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in
+ ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
+
+ If ThunkContext is NULL, then ASSERT().
+ If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().
+ If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
+ ThunkAttributes, then ASSERT().
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+AsmThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ )
+{
+ IA32_REGISTER_SET *UpdatedRegs;
+
+ ASSERT (ThunkContext != NULL);
+ ASSERT ((UINTN)ThunkContext->RealModeBuffer < 0x100000);
+ ASSERT (ThunkContext->RealModeBufferSize >= m16Size);
+ ASSERT ((UINTN)ThunkContext->RealModeBuffer + m16Size <= 0x100000);
+ ASSERT (((ThunkContext->ThunkAttributes & (THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 | THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL)) != \
+ (THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 | THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL)));
+
+ UpdatedRegs = InternalAsmThunk16 (
+ ThunkContext->RealModeState,
+ ThunkContext->RealModeBuffer
+ );
+
+ CopyMem (ThunkContext->RealModeState, UpdatedRegs, sizeof (*UpdatedRegs));
+}
+
+/**
+ Prepares all structures and code for a 16-bit real mode thunk, transfers
+ control to a 16-bit real mode entry point, and returns the results.
+
+ Prepares all structures and code for a 16-bit real mode thunk, transfers
+ control to a 16-bit real mode entry point, and returns the results. If the
+ caller only need to perform a single 16-bit real mode thunk, then this
+ service should be used. If the caller intends to make more than one 16-bit
+ real mode thunk, then it is more efficient if AsmPrepareThunk16() is called
+ once and AsmThunk16() can be called for each 16-bit real mode thunk.
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
+
+ See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+AsmPrepareAndThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ )
+{
+ AsmPrepareThunk16 (ThunkContext);
+ AsmThunk16 (ThunkContext);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86UnitTestHost.c b/roms/edk2/MdePkg/Library/BaseLib/X86UnitTestHost.c new file mode 100644 index 000000000..d0e428457 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86UnitTestHost.c @@ -0,0 +1,2977 @@ +/** @file
+ IA32/X64 specific Unit Test Host functions.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "UnitTestHost.h"
+
+///
+/// Defines for mUnitTestHostBaseLibSegment indexes
+///
+#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS 0
+#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS 1
+#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES 2
+#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS 3
+#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS 4
+#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS 5
+#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR 6
+#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR 7
+
+///
+/// Module global variables for simple system emulation of MSRs, CRx, DRx,
+/// GDTR, IDTR, and Segment Selectors.
+///
+STATIC UINT64 mUnitTestHostBaseLibMsr[2][0x1000];
+STATIC UINTN mUnitTestHostBaseLibCr[5];
+STATIC UINTN mUnitTestHostBaseLibDr[8];
+STATIC UINT16 mUnitTestHostBaseLibSegment[8];
+STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibGdtr;
+STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibIdtr;
+
+/**
+ Retrieves CPUID information.
+
+ Executes the CPUID instruction with EAX set to the value specified by Index.
+ This function always returns Index.
+ If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
+ If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
+ If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
+ If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
+ This function is only available on IA-32 and x64.
+
+ @param Index The 32-bit value to load into EAX prior to invoking the CPUID
+ instruction.
+ @param Eax The pointer to the 32-bit EAX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param Edx The pointer to the 32-bit EDX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+
+ @return Index.
+
+**/
+UINT32
+EFIAPI
+UnitTestHostBaseLibAsmCpuid (
+ IN UINT32 Index,
+ OUT UINT32 *Eax, OPTIONAL
+ OUT UINT32 *Ebx, OPTIONAL
+ OUT UINT32 *Ecx, OPTIONAL
+ OUT UINT32 *Edx OPTIONAL
+ )
+{
+ if (Eax != NULL) {
+ *Eax = 0;
+ }
+ if (Ebx != NULL) {
+ *Ebx = 0;
+ }
+ if (Ecx != NULL) {
+ *Ecx = 0;
+ }
+ if (Edx != NULL) {
+ *Edx = 0;
+ }
+ return Index;
+}
+
+/**
+ Retrieves CPUID information using an extended leaf identifier.
+
+ Executes the CPUID instruction with EAX set to the value specified by Index
+ and ECX set to the value specified by SubIndex. This function always returns
+ Index. This function is only available on IA-32 and x64.
+
+ If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
+ If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
+ If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
+ If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
+
+ @param Index The 32-bit value to load into EAX prior to invoking the
+ CPUID instruction.
+ @param SubIndex The 32-bit value to load into ECX prior to invoking the
+ CPUID instruction.
+ @param Eax The pointer to the 32-bit EAX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param Edx The pointer to the 32-bit EDX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+
+ @return Index.
+
+**/
+UINT32
+EFIAPI
+UnitTestHostBaseLibAsmCpuidEx (
+ IN UINT32 Index,
+ IN UINT32 SubIndex,
+ OUT UINT32 *Eax, OPTIONAL
+ OUT UINT32 *Ebx, OPTIONAL
+ OUT UINT32 *Ecx, OPTIONAL
+ OUT UINT32 *Edx OPTIONAL
+ )
+{
+ if (Eax != NULL) {
+ *Eax = 0;
+ }
+ if (Ebx != NULL) {
+ *Ebx = 0;
+ }
+ if (Ecx != NULL) {
+ *Ecx = 0;
+ }
+ if (Edx != NULL) {
+ *Edx = 0;
+ }
+ return Index;
+}
+
+/**
+ Set CD bit and clear NW bit of CR0 followed by a WBINVD.
+
+ Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,
+ and executing a WBINVD instruction. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmDisableCache (
+ VOID
+ )
+{
+}
+
+/**
+ Perform a WBINVD and clear both the CD and NW bits of CR0.
+
+ Enables the caches by executing a WBINVD instruction and then clear both the CD and NW
+ bits of CR0 to 0. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmEnableCache (
+ VOID
+ )
+{
+}
+
+/**
+ Returns a 64-bit Machine Specific Register(MSR).
+
+ Reads and returns the 64-bit MSR specified by Index. No parameter checking is
+ performed on Index, and some Index values may cause CPU exceptions. The
+ caller must either guarantee that Index is valid, or the caller must set up
+ exception handlers to catch the exceptions. This function is only available
+ on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to read.
+
+ @return The value of the MSR identified by Index.
+
+**/
+UINT64
+EFIAPI
+UnitTestHostBaseLibAsmReadMsr64 (
+ IN UINT32 Index
+ )
+{
+ if (Index < 0x1000) {
+ return mUnitTestHostBaseLibMsr[0][Index];
+ }
+ if (Index >= 0xC0000000 && Index < 0xC0001000) {
+ return mUnitTestHostBaseLibMsr[1][Index];
+ }
+ return 0;
+}
+
+/**
+ Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
+ value.
+
+ Writes the 64-bit value specified by Value to the MSR specified by Index. The
+ 64-bit value written to the MSR is returned. No parameter checking is
+ performed on Index or Value, and some of these may cause CPU exceptions. The
+ caller must either guarantee that Index and Value are valid, or the caller
+ must establish proper exception handlers. This function is only available on
+ IA-32 and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param Value The 64-bit value to write to the MSR.
+
+ @return Value
+
+**/
+UINT64
+EFIAPI
+UnitTestHostBaseLibAsmWriteMsr64 (
+ IN UINT32 Index,
+ IN UINT64 Value
+ )
+{
+ if (Index < 0x1000) {
+ mUnitTestHostBaseLibMsr[0][Index] = Value;
+ }
+ if (Index >= 0xC0000000 && Index < 0xC0001000) {
+ mUnitTestHostBaseLibMsr[1][Index - 0xC00000000] = Value;
+ }
+ return Value;
+}
+
+/**
+ Reads the current value of the Control Register 0 (CR0).
+
+ Reads and returns the current value of CR0. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 0 (CR0).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadCr0 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibCr[0];
+}
+
+/**
+ Reads the current value of the Control Register 2 (CR2).
+
+ Reads and returns the current value of CR2. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 2 (CR2).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadCr2 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibCr[2];
+}
+
+/**
+ Reads the current value of the Control Register 3 (CR3).
+
+ Reads and returns the current value of CR3. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 3 (CR3).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadCr3 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibCr[3];
+}
+
+/**
+ Reads the current value of the Control Register 4 (CR4).
+
+ Reads and returns the current value of CR4. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 4 (CR4).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadCr4 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibCr[4];
+}
+
+/**
+ Writes a value to Control Register 0 (CR0).
+
+ Writes and returns a new value to CR0. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr0 The value to write to CR0.
+
+ @return The value written to CR0.
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteCr0 (
+ UINTN Cr0
+ )
+{
+ mUnitTestHostBaseLibCr[0] = Cr0;
+ return Cr0;
+}
+
+/**
+ Writes a value to Control Register 2 (CR2).
+
+ Writes and returns a new value to CR2. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr2 The value to write to CR2.
+
+ @return The value written to CR2.
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteCr2 (
+ UINTN Cr2
+ )
+{
+ mUnitTestHostBaseLibCr[2] = Cr2;
+ return Cr2;
+}
+
+/**
+ Writes a value to Control Register 3 (CR3).
+
+ Writes and returns a new value to CR3. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr3 The value to write to CR3.
+
+ @return The value written to CR3.
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteCr3 (
+ UINTN Cr3
+ )
+{
+ mUnitTestHostBaseLibCr[3] = Cr3;
+ return Cr3;
+}
+
+/**
+ Writes a value to Control Register 4 (CR4).
+
+ Writes and returns a new value to CR4. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr4 The value to write to CR4.
+
+ @return The value written to CR4.
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteCr4 (
+ UINTN Cr4
+ )
+{
+ mUnitTestHostBaseLibCr[4] = Cr4;
+ return Cr4;
+}
+
+/**
+ Reads the current value of Debug Register 0 (DR0).
+
+ Reads and returns the current value of DR0. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadDr0 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibDr[0];
+}
+
+/**
+ Reads the current value of Debug Register 1 (DR1).
+
+ Reads and returns the current value of DR1. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadDr1 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibDr[1];
+}
+
+/**
+ Reads the current value of Debug Register 2 (DR2).
+
+ Reads and returns the current value of DR2. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadDr2 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibDr[2];
+}
+
+/**
+ Reads the current value of Debug Register 3 (DR3).
+
+ Reads and returns the current value of DR3. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadDr3 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibDr[3];
+}
+
+/**
+ Reads the current value of Debug Register 4 (DR4).
+
+ Reads and returns the current value of DR4. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadDr4 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibDr[4];
+}
+
+/**
+ Reads the current value of Debug Register 5 (DR5).
+
+ Reads and returns the current value of DR5. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadDr5 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibDr[5];
+}
+
+/**
+ Reads the current value of Debug Register 6 (DR6).
+
+ Reads and returns the current value of DR6. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadDr6 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibDr[6];
+}
+
+/**
+ Reads the current value of Debug Register 7 (DR7).
+
+ Reads and returns the current value of DR7. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadDr7 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibDr[7];
+}
+
+/**
+ Writes a value to Debug Register 0 (DR0).
+
+ Writes and returns a new value to DR0. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr0 The value to write to Dr0.
+
+ @return The value written to Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteDr0 (
+ UINTN Dr0
+ )
+{
+ mUnitTestHostBaseLibDr[0] = Dr0;
+ return Dr0;
+}
+
+/**
+ Writes a value to Debug Register 1 (DR1).
+
+ Writes and returns a new value to DR1. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr1 The value to write to Dr1.
+
+ @return The value written to Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteDr1 (
+ UINTN Dr1
+ )
+{
+ mUnitTestHostBaseLibDr[1] = Dr1;
+ return Dr1;
+}
+
+/**
+ Writes a value to Debug Register 2 (DR2).
+
+ Writes and returns a new value to DR2. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr2 The value to write to Dr2.
+
+ @return The value written to Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteDr2 (
+ UINTN Dr2
+ )
+{
+ mUnitTestHostBaseLibDr[2] = Dr2;
+ return Dr2;
+}
+
+/**
+ Writes a value to Debug Register 3 (DR3).
+
+ Writes and returns a new value to DR3. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr3 The value to write to Dr3.
+
+ @return The value written to Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteDr3 (
+ UINTN Dr3
+ )
+{
+ mUnitTestHostBaseLibDr[3] = Dr3;
+ return Dr3;
+}
+
+/**
+ Writes a value to Debug Register 4 (DR4).
+
+ Writes and returns a new value to DR4. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr4 The value to write to Dr4.
+
+ @return The value written to Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteDr4 (
+ UINTN Dr4
+ )
+{
+ mUnitTestHostBaseLibDr[4] = Dr4;
+ return Dr4;
+}
+
+/**
+ Writes a value to Debug Register 5 (DR5).
+
+ Writes and returns a new value to DR5. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr5 The value to write to Dr5.
+
+ @return The value written to Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteDr5 (
+ UINTN Dr5
+ )
+{
+ mUnitTestHostBaseLibDr[5] = Dr5;
+ return Dr5;
+}
+
+/**
+ Writes a value to Debug Register 6 (DR6).
+
+ Writes and returns a new value to DR6. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr6 The value to write to Dr6.
+
+ @return The value written to Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteDr6 (
+ UINTN Dr6
+ )
+{
+ mUnitTestHostBaseLibDr[6] = Dr6;
+ return Dr6;
+}
+
+/**
+ Writes a value to Debug Register 7 (DR7).
+
+ Writes and returns a new value to DR7. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr7 The value to write to Dr7.
+
+ @return The value written to Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteDr7 (
+ UINTN Dr7
+ )
+{
+ mUnitTestHostBaseLibDr[7] = Dr7;
+ return Dr7;
+}
+
+/**
+ Reads the current value of Code Segment Register (CS).
+
+ Reads and returns the current value of CS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of CS.
+
+**/
+UINT16
+EFIAPI
+UnitTestHostBaseLibAsmReadCs (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS];
+}
+
+/**
+ Reads the current value of Data Segment Register (DS).
+
+ Reads and returns the current value of DS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of DS.
+
+**/
+UINT16
+EFIAPI
+UnitTestHostBaseLibAsmReadDs (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS];
+}
+
+/**
+ Reads the current value of Extra Segment Register (ES).
+
+ Reads and returns the current value of ES. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of ES.
+
+**/
+UINT16
+EFIAPI
+UnitTestHostBaseLibAsmReadEs (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES];
+}
+
+/**
+ Reads the current value of FS Data Segment Register (FS).
+
+ Reads and returns the current value of FS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of FS.
+
+**/
+UINT16
+EFIAPI
+UnitTestHostBaseLibAsmReadFs (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS];
+}
+
+/**
+ Reads the current value of GS Data Segment Register (GS).
+
+ Reads and returns the current value of GS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of GS.
+
+**/
+UINT16
+EFIAPI
+UnitTestHostBaseLibAsmReadGs (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS];
+}
+
+/**
+ Reads the current value of Stack Segment Register (SS).
+
+ Reads and returns the current value of SS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of SS.
+
+**/
+UINT16
+EFIAPI
+UnitTestHostBaseLibAsmReadSs (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS];
+}
+
+/**
+ Reads the current value of Task Register (TR).
+
+ Reads and returns the current value of TR. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of TR.
+
+**/
+UINT16
+EFIAPI
+UnitTestHostBaseLibAsmReadTr (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR];
+}
+
+/**
+ Reads the current Global Descriptor Table Register(GDTR) descriptor.
+
+ Reads and returns the current GDTR descriptor and returns it in Gdtr. This
+ function is only available on IA-32 and x64.
+
+ If Gdtr is NULL, then ASSERT().
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmReadGdtr (
+ OUT IA32_DESCRIPTOR *Gdtr
+ )
+{
+ Gdtr = &mUnitTestHostBaseLibGdtr;
+}
+
+/**
+ Writes the current Global Descriptor Table Register (GDTR) descriptor.
+
+ Writes and the current GDTR descriptor specified by Gdtr. This function is
+ only available on IA-32 and x64.
+
+ If Gdtr is NULL, then ASSERT().
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmWriteGdtr (
+ IN CONST IA32_DESCRIPTOR *Gdtr
+ )
+{
+ CopyMem (&mUnitTestHostBaseLibGdtr, Gdtr, sizeof (IA32_DESCRIPTOR));
+}
+
+/**
+ Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.
+
+ Reads and returns the current IDTR descriptor and returns it in Idtr. This
+ function is only available on IA-32 and x64.
+
+ If Idtr is NULL, then ASSERT().
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmReadIdtr (
+ OUT IA32_DESCRIPTOR *Idtr
+ )
+{
+ Idtr = &mUnitTestHostBaseLibIdtr;
+}
+
+/**
+ Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.
+
+ Writes the current IDTR descriptor and returns it in Idtr. This function is
+ only available on IA-32 and x64.
+
+ If Idtr is NULL, then ASSERT().
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmWriteIdtr (
+ IN CONST IA32_DESCRIPTOR *Idtr
+ )
+{
+ CopyMem (&mUnitTestHostBaseLibIdtr, Idtr, sizeof (IA32_DESCRIPTOR));
+}
+
+/**
+ Reads the current Local Descriptor Table Register(LDTR) selector.
+
+ Reads and returns the current 16-bit LDTR descriptor value. This function is
+ only available on IA-32 and x64.
+
+ @return The current selector of LDT.
+
+**/
+UINT16
+EFIAPI
+UnitTestHostBaseLibAsmReadLdtr (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR];
+}
+
+/**
+ Writes the current Local Descriptor Table Register (LDTR) selector.
+
+ Writes and the current LDTR descriptor specified by Ldtr. This function is
+ only available on IA-32 and x64.
+
+ @param Ldtr 16-bit LDTR selector value.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmWriteLdtr (
+ IN UINT16 Ldtr
+ )
+{
+ mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR] = Ldtr;
+}
+
+/**
+ Reads the current value of a Performance Counter (PMC).
+
+ Reads and returns the current value of performance counter specified by
+ Index. This function is only available on IA-32 and x64.
+
+ @param Index The 32-bit Performance Counter index to read.
+
+ @return The value of the PMC specified by Index.
+
+**/
+UINT64
+EFIAPI
+UnitTestHostBaseLibAsmReadPmc (
+ IN UINT32 Index
+ )
+{
+ return 0;
+}
+
+/**
+ Sets up a monitor buffer that is used by AsmMwait().
+
+ Executes a MONITOR instruction with the register state specified by Eax, Ecx
+ and Edx. Returns Eax. This function is only available on IA-32 and x64.
+
+ @param Eax The value to load into EAX or RAX before executing the MONITOR
+ instruction.
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR
+ instruction.
+ @param Edx The value to load into EDX or RDX before executing the MONITOR
+ instruction.
+
+ @return Eax
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmMonitor (
+ IN UINTN Eax,
+ IN UINTN Ecx,
+ IN UINTN Edx
+ )
+{
+ return Eax;
+}
+
+/**
+ Executes an MWAIT instruction.
+
+ Executes an MWAIT instruction with the register state specified by Eax and
+ Ecx. Returns Eax. This function is only available on IA-32 and x64.
+
+ @param Eax The value to load into EAX or RAX before executing the MONITOR
+ instruction.
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR
+ instruction.
+
+ @return Eax
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmMwait (
+ IN UINTN Eax,
+ IN UINTN Ecx
+ )
+{
+ return Eax;
+}
+
+/**
+ Executes a WBINVD instruction.
+
+ Executes a WBINVD instruction. This function is only available on IA-32 and
+ x64.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmWbinvd (
+ VOID
+ )
+{
+}
+
+/**
+ Executes a INVD instruction.
+
+ Executes a INVD instruction. This function is only available on IA-32 and
+ x64.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmInvd (
+ VOID
+ )
+{
+}
+
+/**
+ Flushes a cache line from all the instruction and data caches within the
+ coherency domain of the CPU.
+
+ Flushed the cache line specified by LinearAddress, and returns LinearAddress.
+ This function is only available on IA-32 and x64.
+
+ @param LinearAddress The address of the cache line to flush. If the CPU is
+ in a physical addressing mode, then LinearAddress is a
+ physical address. If the CPU is in a virtual
+ addressing mode, then LinearAddress is a virtual
+ address.
+
+ @return LinearAddress.
+**/
+VOID *
+EFIAPI
+UnitTestHostBaseLibAsmFlushCacheLine (
+ IN VOID *LinearAddress
+ )
+{
+ return LinearAddress;
+}
+
+/**
+ Enables the 32-bit paging mode on the CPU.
+
+ Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode. This function is
+ only available on IA-32. After the 32-bit paging mode is enabled, control is
+ transferred to the function specified by EntryPoint using the new stack
+ specified by NewStack and passing in the parameters specified by Context1 and
+ Context2. Context1 and Context2 are optional and may be NULL. The function
+ EntryPoint must never return.
+
+ If the current execution mode is not 32-bit protected mode, then ASSERT().
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit protected mode with flat descriptors. This
+ means all descriptors must have a base of 0 and a limit of 4GB.
+ 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat
+ descriptors.
+ 4) CR3 must point to valid page tables that will be used once the transition
+ is complete, and those page tables must guarantee that the pages for this
+ function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is enabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is enabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is enabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmEnablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack
+ )
+{
+ EntryPoint (Context1, Context2);
+}
+
+/**
+ Disables the 32-bit paging mode on the CPU.
+
+ Disables the 32-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 32-paged protected
+ mode. This function is only available on IA-32. After the 32-bit paging mode
+ is disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be NULL. The function EntryPoint must never return.
+
+ If the current execution mode is not 32-bit paged mode, then ASSERT().
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit paged mode.
+ 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.
+ 4) CR3 must point to valid page tables that guarantee that the pages for
+ this function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is disabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is disabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is
+ disabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmDisablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack
+ )
+{
+ EntryPoint (Context1, Context2);
+}
+
+/**
+ Enables the 64-bit paging mode on the CPU.
+
+ Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode with flat
+ descriptors. This function is only available on IA-32. After the 64-bit
+ paging mode is enabled, control is transferred to the function specified by
+ EntryPoint using the new stack specified by NewStack and passing in the
+ parameters specified by Context1 and Context2. Context1 and Context2 are
+ optional and may be 0. The function EntryPoint must never return.
+
+ If the current execution mode is not 32-bit protected mode with flat
+ descriptors, then ASSERT().
+ If EntryPoint is 0, then ASSERT().
+ If NewStack is 0, then ASSERT().
+
+ @param Cs The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for long mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is enabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is enabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is enabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmEnablePaging64 (
+ IN UINT16 Cs,
+ IN UINT64 EntryPoint,
+ IN UINT64 Context1, OPTIONAL
+ IN UINT64 Context2, OPTIONAL
+ IN UINT64 NewStack
+ )
+{
+ SWITCH_STACK_ENTRY_POINT NewEntryPoint;
+
+ NewEntryPoint = (SWITCH_STACK_ENTRY_POINT)(UINTN)(EntryPoint);
+ NewEntryPoint ((VOID *)(UINTN)Context1, (VOID *)(UINTN)Context2);
+}
+
+/**
+ Disables the 64-bit paging mode on the CPU.
+
+ Disables the 64-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 64-paging mode.
+ This function is only available on x64. After the 64-bit paging mode is
+ disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be 0. The function EntryPoint must never return.
+
+ If the current execution mode is not 64-bit paged mode, then ASSERT().
+ If EntryPoint is 0, then ASSERT().
+ If NewStack is 0, then ASSERT().
+
+ @param Cs The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for 32-bit protected mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is disabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is disabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is disabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmDisablePaging64 (
+ IN UINT16 Cs,
+ IN UINT32 EntryPoint,
+ IN UINT32 Context1, OPTIONAL
+ IN UINT32 Context2, OPTIONAL
+ IN UINT32 NewStack
+ )
+{
+ SWITCH_STACK_ENTRY_POINT NewEntryPoint;
+
+ NewEntryPoint = (SWITCH_STACK_ENTRY_POINT)(UINTN)(EntryPoint);
+ NewEntryPoint ((VOID *)(UINTN)Context1, (VOID *)(UINTN)Context2);
+}
+
+/**
+ Retrieves the properties for 16-bit thunk functions.
+
+ Computes the size of the buffer and stack below 1MB required to use the
+ AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This
+ buffer size is returned in RealModeBufferSize, and the stack size is returned
+ in ExtraStackSize. If parameters are passed to the 16-bit real mode code,
+ then the actual minimum stack size is ExtraStackSize plus the maximum number
+ of bytes that need to be passed to the 16-bit real mode code.
+
+ If RealModeBufferSize is NULL, then ASSERT().
+ If ExtraStackSize is NULL, then ASSERT().
+
+ @param RealModeBufferSize A pointer to the size of the buffer below 1MB
+ required to use the 16-bit thunk functions.
+ @param ExtraStackSize A pointer to the extra size of stack below 1MB
+ that the 16-bit thunk functions require for
+ temporary storage in the transition to and from
+ 16-bit real mode.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmGetThunk16Properties (
+ OUT UINT32 *RealModeBufferSize,
+ OUT UINT32 *ExtraStackSize
+ )
+{
+ *RealModeBufferSize = 0;
+ *ExtraStackSize = 0;
+}
+
+/**
+ Prepares all structures a code required to use AsmThunk16().
+
+ Prepares all structures and code required to use AsmThunk16().
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
+
+ If ThunkContext is NULL, then ASSERT().
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmPrepareThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ )
+{
+}
+
+/**
+ Transfers control to a 16-bit real mode entry point and returns the results.
+
+ Transfers control to a 16-bit real mode entry point and returns the results.
+ AsmPrepareThunk16() must be called with ThunkContext before this function is used.
+ This function must be called with interrupts disabled.
+
+ The register state from the RealModeState field of ThunkContext is restored just prior
+ to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState,
+ which is used to set the interrupt state when a 16-bit real mode entry point is called.
+ Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.
+ The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to
+ the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.
+ The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,
+ so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment
+ and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry
+ point must exit with a RETF instruction. The register state is captured into RealModeState immediately
+ after the RETF instruction is executed.
+
+ If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
+ or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure
+ the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.
+
+ If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
+ then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.
+ This includes the base vectors, the interrupt masks, and the edge/level trigger mode.
+
+ If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code
+ is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.
+
+ If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
+ ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to
+ disable the A20 mask.
+
+ If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in
+ ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails,
+ then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
+
+ If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in
+ ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
+
+ If ThunkContext is NULL, then ASSERT().
+ If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().
+ If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
+ ThunkAttributes, then ASSERT().
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer are mapped 1:1.
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ )
+{
+}
+
+/**
+ Prepares all structures and code for a 16-bit real mode thunk, transfers
+ control to a 16-bit real mode entry point, and returns the results.
+
+ Prepares all structures and code for a 16-bit real mode thunk, transfers
+ control to a 16-bit real mode entry point, and returns the results. If the
+ caller only need to perform a single 16-bit real mode thunk, then this
+ service should be used. If the caller intends to make more than one 16-bit
+ real mode thunk, then it is more efficient if AsmPrepareThunk16() is called
+ once and AsmThunk16() can be called for each 16-bit real mode thunk.
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
+
+ See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmPrepareAndThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ )
+{
+}
+
+/**
+ Load given selector into TR register.
+
+ @param[in] Selector Task segment selector
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmWriteTr (
+ IN UINT16 Selector
+ )
+{
+ mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR] = Selector;
+}
+
+/**
+ Performs a serializing operation on all load-from-memory instructions that
+ were issued prior the AsmLfence function.
+
+ Executes a LFENCE instruction. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmLfence (
+ VOID
+ )
+{
+}
+
+/**
+ Patch the immediate operand of an IA32 or X64 instruction such that the byte,
+ word, dword or qword operand is encoded at the end of the instruction's
+ binary representation.
+
+ This function should be used to update object code that was compiled with
+ NASM from assembly source code. Example:
+
+ NASM source code:
+
+ mov eax, strict dword 0 ; the imm32 zero operand will be patched
+ ASM_PFX(gPatchCr3):
+ mov cr3, eax
+
+ C source code:
+
+ X86_ASSEMBLY_PATCH_LABEL gPatchCr3;
+ PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);
+
+ @param[out] InstructionEnd Pointer right past the instruction to patch. The
+ immediate operand to patch is expected to
+ comprise the trailing bytes of the instruction.
+ If InstructionEnd is closer to address 0 than
+ ValueSize permits, then ASSERT().
+
+ @param[in] PatchValue The constant to write to the immediate operand.
+ The caller is responsible for ensuring that
+ PatchValue can be represented in the byte, word,
+ dword or qword operand (as indicated through
+ ValueSize); otherwise ASSERT().
+
+ @param[in] ValueSize The size of the operand in bytes; must be 1, 2,
+ 4, or 8. ASSERT() otherwise.
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibPatchInstructionX86 (
+ OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
+ IN UINT64 PatchValue,
+ IN UINTN ValueSize
+ )
+{
+}
+
+/**
+ Retrieves CPUID information.
+
+ Executes the CPUID instruction with EAX set to the value specified by Index.
+ This function always returns Index.
+ If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
+ If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
+ If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
+ If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
+ This function is only available on IA-32 and x64.
+
+ @param Index The 32-bit value to load into EAX prior to invoking the CPUID
+ instruction.
+ @param Eax The pointer to the 32-bit EAX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param Edx The pointer to the 32-bit EDX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+
+ @return Index.
+
+**/
+UINT32
+EFIAPI
+AsmCpuid (
+ IN UINT32 Index,
+ OUT UINT32 *Eax, OPTIONAL
+ OUT UINT32 *Ebx, OPTIONAL
+ OUT UINT32 *Ecx, OPTIONAL
+ OUT UINT32 *Edx OPTIONAL
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmCpuid (Index, Eax, Ebx, Ecx, Edx);
+}
+
+/**
+ Retrieves CPUID information using an extended leaf identifier.
+
+ Executes the CPUID instruction with EAX set to the value specified by Index
+ and ECX set to the value specified by SubIndex. This function always returns
+ Index. This function is only available on IA-32 and x64.
+
+ If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
+ If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
+ If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
+ If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
+
+ @param Index The 32-bit value to load into EAX prior to invoking the
+ CPUID instruction.
+ @param SubIndex The 32-bit value to load into ECX prior to invoking the
+ CPUID instruction.
+ @param Eax The pointer to the 32-bit EAX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param Edx The pointer to the 32-bit EDX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+
+ @return Index.
+
+**/
+UINT32
+EFIAPI
+AsmCpuidEx (
+ IN UINT32 Index,
+ IN UINT32 SubIndex,
+ OUT UINT32 *Eax, OPTIONAL
+ OUT UINT32 *Ebx, OPTIONAL
+ OUT UINT32 *Ecx, OPTIONAL
+ OUT UINT32 *Edx OPTIONAL
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmCpuidEx (Index, SubIndex, Eax, Ebx, Ecx, Edx);
+}
+
+/**
+ Set CD bit and clear NW bit of CR0 followed by a WBINVD.
+
+ Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,
+ and executing a WBINVD instruction. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+AsmDisableCache (
+ VOID
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmDisableCache ();
+}
+
+/**
+ Perform a WBINVD and clear both the CD and NW bits of CR0.
+
+ Enables the caches by executing a WBINVD instruction and then clear both the CD and NW
+ bits of CR0 to 0. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+AsmEnableCache (
+ VOID
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmEnableCache ();
+}
+
+/**
+ Returns a 64-bit Machine Specific Register(MSR).
+
+ Reads and returns the 64-bit MSR specified by Index. No parameter checking is
+ performed on Index, and some Index values may cause CPU exceptions. The
+ caller must either guarantee that Index is valid, or the caller must set up
+ exception handlers to catch the exceptions. This function is only available
+ on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to read.
+
+ @return The value of the MSR identified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadMsr64 (
+ IN UINT32 Index
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadMsr64 (Index);
+}
+
+/**
+ Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
+ value.
+
+ Writes the 64-bit value specified by Value to the MSR specified by Index. The
+ 64-bit value written to the MSR is returned. No parameter checking is
+ performed on Index or Value, and some of these may cause CPU exceptions. The
+ caller must either guarantee that Index and Value are valid, or the caller
+ must establish proper exception handlers. This function is only available on
+ IA-32 and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param Value The 64-bit value to write to the MSR.
+
+ @return Value
+
+**/
+UINT64
+EFIAPI
+AsmWriteMsr64 (
+ IN UINT32 Index,
+ IN UINT64 Value
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteMsr64 (Index, Value);
+}
+
+/**
+ Reads the current value of the Control Register 0 (CR0).
+
+ Reads and returns the current value of CR0. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 0 (CR0).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr0 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadCr0 ();
+}
+
+/**
+ Reads the current value of the Control Register 2 (CR2).
+
+ Reads and returns the current value of CR2. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 2 (CR2).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr2 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadCr2 ();
+}
+
+/**
+ Reads the current value of the Control Register 3 (CR3).
+
+ Reads and returns the current value of CR3. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 3 (CR3).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr3 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadCr3 ();
+}
+
+/**
+ Reads the current value of the Control Register 4 (CR4).
+
+ Reads and returns the current value of CR4. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 4 (CR4).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr4 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadCr4 ();
+}
+
+/**
+ Writes a value to Control Register 0 (CR0).
+
+ Writes and returns a new value to CR0. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr0 The value to write to CR0.
+
+ @return The value written to CR0.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr0 (
+ UINTN Cr0
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteCr0 (Cr0);
+}
+
+/**
+ Writes a value to Control Register 2 (CR2).
+
+ Writes and returns a new value to CR2. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr2 The value to write to CR2.
+
+ @return The value written to CR2.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr2 (
+ UINTN Cr2
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteCr2 (Cr2);
+}
+
+/**
+ Writes a value to Control Register 3 (CR3).
+
+ Writes and returns a new value to CR3. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr3 The value to write to CR3.
+
+ @return The value written to CR3.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr3 (
+ UINTN Cr3
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteCr3 (Cr3);
+}
+
+/**
+ Writes a value to Control Register 4 (CR4).
+
+ Writes and returns a new value to CR4. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr4 The value to write to CR4.
+
+ @return The value written to CR4.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr4 (
+ UINTN Cr4
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteCr4 (Cr4);
+}
+
+/**
+ Reads the current value of Debug Register 0 (DR0).
+
+ Reads and returns the current value of DR0. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr0 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDr0 ();
+}
+
+/**
+ Reads the current value of Debug Register 1 (DR1).
+
+ Reads and returns the current value of DR1. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr1 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDr1 ();
+}
+
+/**
+ Reads the current value of Debug Register 2 (DR2).
+
+ Reads and returns the current value of DR2. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr2 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDr2 ();
+}
+
+/**
+ Reads the current value of Debug Register 3 (DR3).
+
+ Reads and returns the current value of DR3. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr3 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDr3 ();
+}
+
+/**
+ Reads the current value of Debug Register 4 (DR4).
+
+ Reads and returns the current value of DR4. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr4 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDr4 ();
+}
+
+/**
+ Reads the current value of Debug Register 5 (DR5).
+
+ Reads and returns the current value of DR5. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr5 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDr5 ();
+}
+
+/**
+ Reads the current value of Debug Register 6 (DR6).
+
+ Reads and returns the current value of DR6. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr6 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDr6 ();
+}
+
+/**
+ Reads the current value of Debug Register 7 (DR7).
+
+ Reads and returns the current value of DR7. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr7 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDr7 ();
+}
+
+/**
+ Writes a value to Debug Register 0 (DR0).
+
+ Writes and returns a new value to DR0. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr0 The value to write to Dr0.
+
+ @return The value written to Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr0 (
+ UINTN Dr0
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteDr0 (Dr0);
+}
+
+/**
+ Writes a value to Debug Register 1 (DR1).
+
+ Writes and returns a new value to DR1. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr1 The value to write to Dr1.
+
+ @return The value written to Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr1 (
+ UINTN Dr1
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteDr1 (Dr1);
+}
+
+/**
+ Writes a value to Debug Register 2 (DR2).
+
+ Writes and returns a new value to DR2. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr2 The value to write to Dr2.
+
+ @return The value written to Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr2 (
+ UINTN Dr2
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteDr2 (Dr2);
+}
+
+/**
+ Writes a value to Debug Register 3 (DR3).
+
+ Writes and returns a new value to DR3. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr3 The value to write to Dr3.
+
+ @return The value written to Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr3 (
+ UINTN Dr3
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteDr3 (Dr3);
+}
+
+/**
+ Writes a value to Debug Register 4 (DR4).
+
+ Writes and returns a new value to DR4. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr4 The value to write to Dr4.
+
+ @return The value written to Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr4 (
+ UINTN Dr4
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteDr4 (Dr4);
+}
+
+/**
+ Writes a value to Debug Register 5 (DR5).
+
+ Writes and returns a new value to DR5. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr5 The value to write to Dr5.
+
+ @return The value written to Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr5 (
+ UINTN Dr5
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteDr5 (Dr5);
+}
+
+/**
+ Writes a value to Debug Register 6 (DR6).
+
+ Writes and returns a new value to DR6. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr6 The value to write to Dr6.
+
+ @return The value written to Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr6 (
+ UINTN Dr6
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteDr6 (Dr6);
+}
+
+/**
+ Writes a value to Debug Register 7 (DR7).
+
+ Writes and returns a new value to DR7. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr7 The value to write to Dr7.
+
+ @return The value written to Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr7 (
+ UINTN Dr7
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteDr7 (Dr7);
+}
+
+/**
+ Reads the current value of Code Segment Register (CS).
+
+ Reads and returns the current value of CS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of CS.
+
+**/
+UINT16
+EFIAPI
+AsmReadCs (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadCs ();
+}
+
+/**
+ Reads the current value of Data Segment Register (DS).
+
+ Reads and returns the current value of DS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of DS.
+
+**/
+UINT16
+EFIAPI
+AsmReadDs (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDs ();
+}
+
+/**
+ Reads the current value of Extra Segment Register (ES).
+
+ Reads and returns the current value of ES. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of ES.
+
+**/
+UINT16
+EFIAPI
+AsmReadEs (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadEs ();
+}
+
+/**
+ Reads the current value of FS Data Segment Register (FS).
+
+ Reads and returns the current value of FS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of FS.
+
+**/
+UINT16
+EFIAPI
+AsmReadFs (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadFs ();
+}
+
+/**
+ Reads the current value of GS Data Segment Register (GS).
+
+ Reads and returns the current value of GS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of GS.
+
+**/
+UINT16
+EFIAPI
+AsmReadGs (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadGs ();
+}
+
+/**
+ Reads the current value of Stack Segment Register (SS).
+
+ Reads and returns the current value of SS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of SS.
+
+**/
+UINT16
+EFIAPI
+AsmReadSs (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadSs ();
+}
+
+/**
+ Reads the current value of Task Register (TR).
+
+ Reads and returns the current value of TR. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of TR.
+
+**/
+UINT16
+EFIAPI
+AsmReadTr (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadTr ();
+}
+
+/**
+ Reads the current Global Descriptor Table Register(GDTR) descriptor.
+
+ Reads and returns the current GDTR descriptor and returns it in Gdtr. This
+ function is only available on IA-32 and x64.
+
+ If Gdtr is NULL, then ASSERT().
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+AsmReadGdtr (
+ OUT IA32_DESCRIPTOR *Gdtr
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmReadGdtr (Gdtr);
+}
+
+/**
+ Writes the current Global Descriptor Table Register (GDTR) descriptor.
+
+ Writes and the current GDTR descriptor specified by Gdtr. This function is
+ only available on IA-32 and x64.
+
+ If Gdtr is NULL, then ASSERT().
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+AsmWriteGdtr (
+ IN CONST IA32_DESCRIPTOR *Gdtr
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmWriteGdtr (Gdtr);
+}
+
+/**
+ Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.
+
+ Reads and returns the current IDTR descriptor and returns it in Idtr. This
+ function is only available on IA-32 and x64.
+
+ If Idtr is NULL, then ASSERT().
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+AsmReadIdtr (
+ OUT IA32_DESCRIPTOR *Idtr
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmReadIdtr (Idtr);
+}
+
+/**
+ Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.
+
+ Writes the current IDTR descriptor and returns it in Idtr. This function is
+ only available on IA-32 and x64.
+
+ If Idtr is NULL, then ASSERT().
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+AsmWriteIdtr (
+ IN CONST IA32_DESCRIPTOR *Idtr
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmWriteIdtr (Idtr);
+}
+
+/**
+ Reads the current Local Descriptor Table Register(LDTR) selector.
+
+ Reads and returns the current 16-bit LDTR descriptor value. This function is
+ only available on IA-32 and x64.
+
+ @return The current selector of LDT.
+
+**/
+UINT16
+EFIAPI
+AsmReadLdtr (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadLdtr ();
+}
+
+/**
+ Writes the current Local Descriptor Table Register (LDTR) selector.
+
+ Writes and the current LDTR descriptor specified by Ldtr. This function is
+ only available on IA-32 and x64.
+
+ @param Ldtr 16-bit LDTR selector value.
+
+**/
+VOID
+EFIAPI
+AsmWriteLdtr (
+ IN UINT16 Ldtr
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmWriteLdtr (Ldtr);
+}
+
+/**
+ Reads the current value of a Performance Counter (PMC).
+
+ Reads and returns the current value of performance counter specified by
+ Index. This function is only available on IA-32 and x64.
+
+ @param Index The 32-bit Performance Counter index to read.
+
+ @return The value of the PMC specified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadPmc (
+ IN UINT32 Index
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadPmc (Index);
+}
+
+/**
+ Sets up a monitor buffer that is used by AsmMwait().
+
+ Executes a MONITOR instruction with the register state specified by Eax, Ecx
+ and Edx. Returns Eax. This function is only available on IA-32 and x64.
+
+ @param Eax The value to load into EAX or RAX before executing the MONITOR
+ instruction.
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR
+ instruction.
+ @param Edx The value to load into EDX or RDX before executing the MONITOR
+ instruction.
+
+ @return Eax
+
+**/
+UINTN
+EFIAPI
+AsmMonitor (
+ IN UINTN Eax,
+ IN UINTN Ecx,
+ IN UINTN Edx
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmMonitor (Eax, Ecx, Edx);
+}
+
+/**
+ Executes an MWAIT instruction.
+
+ Executes an MWAIT instruction with the register state specified by Eax and
+ Ecx. Returns Eax. This function is only available on IA-32 and x64.
+
+ @param Eax The value to load into EAX or RAX before executing the MONITOR
+ instruction.
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR
+ instruction.
+
+ @return Eax
+
+**/
+UINTN
+EFIAPI
+AsmMwait (
+ IN UINTN Eax,
+ IN UINTN Ecx
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmMwait (Eax, Ecx);
+}
+
+/**
+ Executes a WBINVD instruction.
+
+ Executes a WBINVD instruction. This function is only available on IA-32 and
+ x64.
+
+**/
+VOID
+EFIAPI
+AsmWbinvd (
+ VOID
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmWbinvd ();
+}
+
+/**
+ Executes a INVD instruction.
+
+ Executes a INVD instruction. This function is only available on IA-32 and
+ x64.
+
+**/
+VOID
+EFIAPI
+AsmInvd (
+ VOID
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmInvd ();
+}
+
+/**
+ Flushes a cache line from all the instruction and data caches within the
+ coherency domain of the CPU.
+
+ Flushed the cache line specified by LinearAddress, and returns LinearAddress.
+ This function is only available on IA-32 and x64.
+
+ @param LinearAddress The address of the cache line to flush. If the CPU is
+ in a physical addressing mode, then LinearAddress is a
+ physical address. If the CPU is in a virtual
+ addressing mode, then LinearAddress is a virtual
+ address.
+
+ @return LinearAddress.
+**/
+VOID *
+EFIAPI
+AsmFlushCacheLine (
+ IN VOID *LinearAddress
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmFlushCacheLine (LinearAddress);
+}
+
+/**
+ Enables the 32-bit paging mode on the CPU.
+
+ Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode. This function is
+ only available on IA-32. After the 32-bit paging mode is enabled, control is
+ transferred to the function specified by EntryPoint using the new stack
+ specified by NewStack and passing in the parameters specified by Context1 and
+ Context2. Context1 and Context2 are optional and may be NULL. The function
+ EntryPoint must never return.
+
+ If the current execution mode is not 32-bit protected mode, then ASSERT().
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit protected mode with flat descriptors. This
+ means all descriptors must have a base of 0 and a limit of 4GB.
+ 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat
+ descriptors.
+ 4) CR3 must point to valid page tables that will be used once the transition
+ is complete, and those page tables must guarantee that the pages for this
+ function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is enabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is enabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is enabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+AsmEnablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmEnablePaging32 (EntryPoint, Context1, Context2, NewStack);
+}
+
+/**
+ Disables the 32-bit paging mode on the CPU.
+
+ Disables the 32-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 32-paged protected
+ mode. This function is only available on IA-32. After the 32-bit paging mode
+ is disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be NULL. The function EntryPoint must never return.
+
+ If the current execution mode is not 32-bit paged mode, then ASSERT().
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit paged mode.
+ 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.
+ 4) CR3 must point to valid page tables that guarantee that the pages for
+ this function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is disabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is disabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is
+ disabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+AsmDisablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmDisablePaging32 (EntryPoint, Context1, Context2, NewStack);
+}
+
+/**
+ Enables the 64-bit paging mode on the CPU.
+
+ Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode with flat
+ descriptors. This function is only available on IA-32. After the 64-bit
+ paging mode is enabled, control is transferred to the function specified by
+ EntryPoint using the new stack specified by NewStack and passing in the
+ parameters specified by Context1 and Context2. Context1 and Context2 are
+ optional and may be 0. The function EntryPoint must never return.
+
+ If the current execution mode is not 32-bit protected mode with flat
+ descriptors, then ASSERT().
+ If EntryPoint is 0, then ASSERT().
+ If NewStack is 0, then ASSERT().
+
+ @param Cs The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for long mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is enabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is enabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is enabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+AsmEnablePaging64 (
+ IN UINT16 Cs,
+ IN UINT64 EntryPoint,
+ IN UINT64 Context1, OPTIONAL
+ IN UINT64 Context2, OPTIONAL
+ IN UINT64 NewStack
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmEnablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);
+}
+
+/**
+ Disables the 64-bit paging mode on the CPU.
+
+ Disables the 64-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 64-paging mode.
+ This function is only available on x64. After the 64-bit paging mode is
+ disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be 0. The function EntryPoint must never return.
+
+ If the current execution mode is not 64-bit paged mode, then ASSERT().
+ If EntryPoint is 0, then ASSERT().
+ If NewStack is 0, then ASSERT().
+
+ @param Cs The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for 32-bit protected mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is disabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is disabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is disabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+AsmDisablePaging64 (
+ IN UINT16 Cs,
+ IN UINT32 EntryPoint,
+ IN UINT32 Context1, OPTIONAL
+ IN UINT32 Context2, OPTIONAL
+ IN UINT32 NewStack
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmDisablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);
+}
+
+/**
+ Retrieves the properties for 16-bit thunk functions.
+
+ Computes the size of the buffer and stack below 1MB required to use the
+ AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This
+ buffer size is returned in RealModeBufferSize, and the stack size is returned
+ in ExtraStackSize. If parameters are passed to the 16-bit real mode code,
+ then the actual minimum stack size is ExtraStackSize plus the maximum number
+ of bytes that need to be passed to the 16-bit real mode code.
+
+ If RealModeBufferSize is NULL, then ASSERT().
+ If ExtraStackSize is NULL, then ASSERT().
+
+ @param RealModeBufferSize A pointer to the size of the buffer below 1MB
+ required to use the 16-bit thunk functions.
+ @param ExtraStackSize A pointer to the extra size of stack below 1MB
+ that the 16-bit thunk functions require for
+ temporary storage in the transition to and from
+ 16-bit real mode.
+
+**/
+VOID
+EFIAPI
+AsmGetThunk16Properties (
+ OUT UINT32 *RealModeBufferSize,
+ OUT UINT32 *ExtraStackSize
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmGetThunk16Properties (RealModeBufferSize, ExtraStackSize);
+}
+
+/**
+ Prepares all structures a code required to use AsmThunk16().
+
+ Prepares all structures and code required to use AsmThunk16().
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
+
+ If ThunkContext is NULL, then ASSERT().
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+AsmPrepareThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmPrepareThunk16 (ThunkContext);
+}
+
+/**
+ Transfers control to a 16-bit real mode entry point and returns the results.
+
+ Transfers control to a 16-bit real mode entry point and returns the results.
+ AsmPrepareThunk16() must be called with ThunkContext before this function is used.
+ This function must be called with interrupts disabled.
+
+ The register state from the RealModeState field of ThunkContext is restored just prior
+ to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState,
+ which is used to set the interrupt state when a 16-bit real mode entry point is called.
+ Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.
+ The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to
+ the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.
+ The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,
+ so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment
+ and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry
+ point must exit with a RETF instruction. The register state is captured into RealModeState immediately
+ after the RETF instruction is executed.
+
+ If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
+ or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure
+ the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.
+
+ If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
+ then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.
+ This includes the base vectors, the interrupt masks, and the edge/level trigger mode.
+
+ If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code
+ is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.
+
+ If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
+ ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to
+ disable the A20 mask.
+
+ If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in
+ ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails,
+ then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
+
+ If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in
+ ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
+
+ If ThunkContext is NULL, then ASSERT().
+ If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().
+ If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
+ ThunkAttributes, then ASSERT().
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer are mapped 1:1.
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+AsmThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmThunk16 (ThunkContext);
+}
+
+/**
+ Prepares all structures and code for a 16-bit real mode thunk, transfers
+ control to a 16-bit real mode entry point, and returns the results.
+
+ Prepares all structures and code for a 16-bit real mode thunk, transfers
+ control to a 16-bit real mode entry point, and returns the results. If the
+ caller only need to perform a single 16-bit real mode thunk, then this
+ service should be used. If the caller intends to make more than one 16-bit
+ real mode thunk, then it is more efficient if AsmPrepareThunk16() is called
+ once and AsmThunk16() can be called for each 16-bit real mode thunk.
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
+
+ See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+AsmPrepareAndThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmPrepareAndThunk16 (ThunkContext);
+}
+
+/**
+ Load given selector into TR register.
+
+ @param[in] Selector Task segment selector
+**/
+VOID
+EFIAPI
+AsmWriteTr (
+ IN UINT16 Selector
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmWriteTr (Selector);
+}
+
+/**
+ Performs a serializing operation on all load-from-memory instructions that
+ were issued prior the AsmLfence function.
+
+ Executes a LFENCE instruction. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+AsmLfence (
+ VOID
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmLfence ();
+}
+
+/**
+ Patch the immediate operand of an IA32 or X64 instruction such that the byte,
+ word, dword or qword operand is encoded at the end of the instruction's
+ binary representation.
+
+ This function should be used to update object code that was compiled with
+ NASM from assembly source code. Example:
+
+ NASM source code:
+
+ mov eax, strict dword 0 ; the imm32 zero operand will be patched
+ ASM_PFX(gPatchCr3):
+ mov cr3, eax
+
+ C source code:
+
+ X86_ASSEMBLY_PATCH_LABEL gPatchCr3;
+ PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);
+
+ @param[out] InstructionEnd Pointer right past the instruction to patch. The
+ immediate operand to patch is expected to
+ comprise the trailing bytes of the instruction.
+ If InstructionEnd is closer to address 0 than
+ ValueSize permits, then ASSERT().
+
+ @param[in] PatchValue The constant to write to the immediate operand.
+ The caller is responsible for ensuring that
+ PatchValue can be represented in the byte, word,
+ dword or qword operand (as indicated through
+ ValueSize); otherwise ASSERT().
+
+ @param[in] ValueSize The size of the operand in bytes; must be 1, 2,
+ 4, or 8. ASSERT() otherwise.
+**/
+VOID
+EFIAPI
+PatchInstructionX86 (
+ OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
+ IN UINT64 PatchValue,
+ IN UINTN ValueSize
+ )
+{
+ gUnitTestHostBaseLib.X86->PatchInstructionX86 (InstructionEnd, PatchValue, ValueSize);
+}
+
+///
+/// Common services
+///
+STATIC UNIT_TEST_HOST_BASE_LIB_COMMON mUnitTestHostBaseLibCommon = {
+ UnitTestHostBaseLibEnableInterrupts,
+ UnitTestHostBaseLibDisableInterrupts,
+ UnitTestHostBaseLibEnableDisableInterrupts,
+ UnitTestHostBaseLibGetInterruptState,
+};
+
+///
+/// IA32/X64 services
+///
+STATIC UNIT_TEST_HOST_BASE_LIB_X86 mUnitTestHostBaseLibX86 = {
+ UnitTestHostBaseLibAsmCpuid,
+ UnitTestHostBaseLibAsmCpuidEx,
+ UnitTestHostBaseLibAsmDisableCache,
+ UnitTestHostBaseLibAsmEnableCache,
+ UnitTestHostBaseLibAsmReadMsr64,
+ UnitTestHostBaseLibAsmWriteMsr64,
+ UnitTestHostBaseLibAsmReadCr0,
+ UnitTestHostBaseLibAsmReadCr2,
+ UnitTestHostBaseLibAsmReadCr3,
+ UnitTestHostBaseLibAsmReadCr4,
+ UnitTestHostBaseLibAsmWriteCr0,
+ UnitTestHostBaseLibAsmWriteCr2,
+ UnitTestHostBaseLibAsmWriteCr3,
+ UnitTestHostBaseLibAsmWriteCr4,
+ UnitTestHostBaseLibAsmReadDr0,
+ UnitTestHostBaseLibAsmReadDr1,
+ UnitTestHostBaseLibAsmReadDr2,
+ UnitTestHostBaseLibAsmReadDr3,
+ UnitTestHostBaseLibAsmReadDr4,
+ UnitTestHostBaseLibAsmReadDr5,
+ UnitTestHostBaseLibAsmReadDr6,
+ UnitTestHostBaseLibAsmReadDr7,
+ UnitTestHostBaseLibAsmWriteDr0,
+ UnitTestHostBaseLibAsmWriteDr1,
+ UnitTestHostBaseLibAsmWriteDr2,
+ UnitTestHostBaseLibAsmWriteDr3,
+ UnitTestHostBaseLibAsmWriteDr4,
+ UnitTestHostBaseLibAsmWriteDr5,
+ UnitTestHostBaseLibAsmWriteDr6,
+ UnitTestHostBaseLibAsmWriteDr7,
+ UnitTestHostBaseLibAsmReadCs,
+ UnitTestHostBaseLibAsmReadDs,
+ UnitTestHostBaseLibAsmReadEs,
+ UnitTestHostBaseLibAsmReadFs,
+ UnitTestHostBaseLibAsmReadGs,
+ UnitTestHostBaseLibAsmReadSs,
+ UnitTestHostBaseLibAsmReadTr,
+ UnitTestHostBaseLibAsmReadGdtr,
+ UnitTestHostBaseLibAsmWriteGdtr,
+ UnitTestHostBaseLibAsmReadIdtr,
+ UnitTestHostBaseLibAsmWriteIdtr,
+ UnitTestHostBaseLibAsmReadLdtr,
+ UnitTestHostBaseLibAsmWriteLdtr,
+ UnitTestHostBaseLibAsmReadPmc,
+ UnitTestHostBaseLibAsmMonitor,
+ UnitTestHostBaseLibAsmMwait,
+ UnitTestHostBaseLibAsmWbinvd,
+ UnitTestHostBaseLibAsmInvd,
+ UnitTestHostBaseLibAsmFlushCacheLine,
+ UnitTestHostBaseLibAsmEnablePaging32,
+ UnitTestHostBaseLibAsmDisablePaging32,
+ UnitTestHostBaseLibAsmEnablePaging64,
+ UnitTestHostBaseLibAsmDisablePaging64,
+ UnitTestHostBaseLibAsmGetThunk16Properties,
+ UnitTestHostBaseLibAsmPrepareThunk16,
+ UnitTestHostBaseLibAsmThunk16,
+ UnitTestHostBaseLibAsmPrepareAndThunk16,
+ UnitTestHostBaseLibAsmWriteTr,
+ UnitTestHostBaseLibAsmLfence,
+ UnitTestHostBaseLibPatchInstructionX86
+};
+
+///
+/// Structure of hook functions for BaseLib functions that can not be used from
+/// a host application. A simple emulation of these function is provided by
+/// default. A specific unit test can provide its own implementation for any
+/// of these functions.
+///
+UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib = {
+ &mUnitTestHostBaseLibCommon,
+ &mUnitTestHostBaseLibX86
+};
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86WriteGdtr.c b/roms/edk2/MdePkg/Library/BaseLib/X86WriteGdtr.c new file mode 100644 index 000000000..1a570e3d9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86WriteGdtr.c @@ -0,0 +1,33 @@ +/** @file
+ IA-32/x64 AsmWriteGdtr()
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Writes the current Global Descriptor Table Register (GDTR) descriptor.
+
+ Writes and the current GDTR descriptor specified by Gdtr. This function is
+ only available on IA-32 and x64.
+
+ If Gdtr is NULL, then ASSERT().
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+AsmWriteGdtr (
+ IN CONST IA32_DESCRIPTOR *Gdtr
+ )
+{
+ ASSERT (Gdtr != NULL);
+ InternalX86WriteGdtr (Gdtr);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X86WriteIdtr.c b/roms/edk2/MdePkg/Library/BaseLib/X86WriteIdtr.c new file mode 100644 index 000000000..9ea979b76 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X86WriteIdtr.c @@ -0,0 +1,33 @@ +/** @file
+ IA-32/x64 AsmWriteIdtr()
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.
+
+ Writes the current IDTR descriptor and returns it in Idtr. This function is
+ only available on IA-32 and x64.
+
+ If Idtr is NULL, then ASSERT().
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+AsmWriteIdtr (
+ IN CONST IA32_DESCRIPTOR *Idtr
+ )
+{
+ ASSERT (Idtr != NULL);
+ InternalX86WriteIdtr (Idtr);
+}
|