diff options
Diffstat (limited to 'roms/u-boot/doc/device-tree-bindings/pci')
3 files changed, 218 insertions, 0 deletions
diff --git a/roms/u-boot/doc/device-tree-bindings/pci/armada8k-pcie.txt b/roms/u-boot/doc/device-tree-bindings/pci/armada8k-pcie.txt new file mode 100644 index 000000000..7230f1044 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/pci/armada8k-pcie.txt @@ -0,0 +1,49 @@ +Armada-8K PCIe DT details: +========================== + +Armada-8k uses synopsis designware PCIe controller. + +Required properties: +- compatible : should be "marvell,armada8k-pcie", "snps,dw-pcie". +- reg: base addresses and lengths of the pcie control and global control registers. + "ctrl" registers points to the global control registers, while the "config" space + points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below. +- interrupt-map-mask and interrupt-map, standard PCI properties to + define the mapping of the PCIe interface to interrupt numbers. +- All other definitions as per generic PCI bindings +See Linux kernel documentation: +"Documentation/devicetree/bindings/pci/designware-pcie.txt" + +Optional properties: +PHY support is still not supported for armada-8k, once it will, the following parameters can be used: +- phys : phandle to phy node associated with pcie controller. +- phy-names : must be "pcie-phy" +- marvell,reset-gpio : specifies a gpio that needs to be activated for plug-in + card reset signal release. +Example: + +cpm_pcie0: pcie@f2600000 { + compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; + reg = <0 0xf2600000 0 0x10000>, + <0 0xf6f00000 0 0x80000>; + reg-names = "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + + bus-range = <0 0xff>; + ranges = + /* downstream I/O */ + <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + num-lanes = <1>; + clocks = <&cpm_syscon0 1 13>; + marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/pci/mediatek-pcie.txt b/roms/u-boot/doc/device-tree-bindings/pci/mediatek-pcie.txt new file mode 100644 index 000000000..2f9f549b7 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/pci/mediatek-pcie.txt @@ -0,0 +1,122 @@ +MediaTek Gen2 PCIe controller + +Required properties: +- compatible: Should contain one of the following strings: + "mediatek,mt7623-pcie" +- device_type: Must be "pci" +- reg: Base addresses and lengths of the PCIe subsys and root ports. +- reg-names: Names of the above areas to use during resource lookup. +- #address-cells: Address representation for root ports (must be 3) +- #size-cells: Size representation for root ports (must be 2) +- clocks: Must contain an entry for each entry in clock-names. +- clock-names: + Mandatory entries: + - sys_ckN :transaction layer and data link layer clock + Required entries for MT7623: + - free_ck :for reference clock of PCIe subsys + where N starting from 0 to one less than the number of root ports. +- phys: List of PHY specifiers (used by generic PHY framework). +- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the + number of PHYs as specified in *phys* property. +- power-domains: A phandle and power domain specifier pair to the power domain + which is responsible for collapsing and restoring power to the peripheral. +- bus-range: Range of bus numbers associated with this controller. +- ranges: Ranges for the PCI memory and I/O regions. + +Required properties for MT7623: +- #interrupt-cells: Size representation for interrupts (must be 1) +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties + Please refer to the standard PCI bus binding document for a more detailed + explanation. +- resets: Must contain an entry for each entry in reset-names. +- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the + number of root ports. + +In addition, the device tree node must have sub-nodes describing each +PCIe port interface, having the following mandatory properties: + +Required properties: +- device_type: Must be "pci" +- reg: Only the first four bytes are used to refer to the correct bus number + and device number. +- #address-cells: Must be 3 +- #size-cells: Must be 2 +- #interrupt-cells: Must be 1 +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties + Please refer to the standard PCI bus binding document for a more detailed + explanation. +- ranges: Sub-ranges distributed from the PCIe controller node. An empty + property is sufficient. + +Examples for MT7623: + + hifsys: syscon@1a000000 { + compatible = "mediatek,mt7623-hifsys", + "syscon"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pcie: pcie@1a140000 { + compatible = "mediatek,mt7623-pcie"; + device_type = "pci"; + reg = <0x1a140000 0x1000>, /* PCIe shared registers */ + <0x1a142000 0x1000>, /* Port0 registers */ + <0x1a143000 0x1000>, /* Port1 registers */ + <0x1a144000 0x1000>; /* Port2 registers */ + reg-names = "subsys", "port0", "port1", "port2"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + resets = <&hifsys HIFSYS_PCIE0_RST>, + <&hifsys HIFSYS_PCIE1_RST>, + <&hifsys HIFSYS_PCIE2_RST>; + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, + <&pcie2_phy PHY_TYPE_PCIE>; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000 /* I/O space */ + 0x83000000 0 0x60000000 0x60000000 0 0x10000000>; /* memory space */ + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + + pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + + pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + }; diff --git a/roms/u-boot/doc/device-tree-bindings/pci/x86-pci.txt b/roms/u-boot/doc/device-tree-bindings/pci/x86-pci.txt new file mode 100644 index 000000000..95e370b3e --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/pci/x86-pci.txt @@ -0,0 +1,47 @@ +x86 PCI DT details: +=================== + +Some options are available to affect how PCI operates on x86. + +Optional properties: +- u-boot,skip-auto-config-until-reloc : Don't set up PCI configuration until + after U-Boot has relocated. Normally if PCI is used before relocation, + this happens before relocation also. Some platforms set up static + configuration in TPL/SPL to reduce code size and boot time, since these + phases only know about a small subset of PCI devices. + +For PCI devices the following optional property is available: + +- pci,no-autoconfig : Don't automatically configure this PCI device at all. + This is used when the device is statically configured and must maintain + this same config throughout the boot process. An example is a serial + UART being used to debug PCI configuration, since reconfiguring it stops + the UART from working until the driver is re-probed, and this can cause + output to be lost. This should not generally be used in production code, + although it is often harmless. + + +Example: + +pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 + 0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000 + 0x01000000 0x0 0x1000 0x1000 0 0xefff>; + u-boot,skip-auto-config-until-reloc; + + + serial: serial@18,2 { + reg = <0x0200c210 0 0 0 0>; + u-boot,dm-pre-reloc; + compatible = "intel,apl-ns16550"; + early-regs = <0xde000000 0x20>; + reg-shift = <2>; + clock-frequency = <1843200>; + current-speed = <115200>; + pci,no-autoconfig; + }; +}; |