diff options
Diffstat (limited to 'roms/u-boot/doc/device-tree-bindings/remoteproc')
5 files changed, 356 insertions, 0 deletions
diff --git a/roms/u-boot/doc/device-tree-bindings/remoteproc/k3-rproc.txt b/roms/u-boot/doc/device-tree-bindings/remoteproc/k3-rproc.txt new file mode 100644 index 000000000..0a1e85822 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/remoteproc/k3-rproc.txt @@ -0,0 +1,50 @@ +Texas Instruments' K3 Remote processor driver +============================================= + +In K3 generation Socs, loading an image on any processing entity +cannot be done directly from U-Boot. In order to load an image, +remoteproc driver should communicate to SYSFW with a specific sequence. +Also enable the timer required for this remotecore. + +Required properties: +-------------------- +- compatible: Shall be: "ti,am654-rproc" +- reg: base address of the remoteproc timer. +- power-domains: Should contain two sets of entries: + First set corresponds to pm domain of the + remotecore timer. Seconf entry corresponds to the + remoteproc to start. + This property is as per the binding, + doc/device-tree-bindings/power/ti,sci-pm-domain.txt +- resets: Should contain a phandle to a reset controller node + and an args specifier containing the remote code + device id and reset mask value. This is as per the + doc/device-tree-bindings/reset/ti,sci-reset.txt +- ti,sci: Phandle to TI-SCI compatible System controller node. +- ti,sci-proc-id: Processor id as identified by TISCI + +Optional properties: +-------------------- +- assigned-clocks: Should contain a phandle to clock node and an args + specifier containing the remote core device id and + the clock id within the remote core. This is as per + doc/device-tree-bindings/clock/ti,sci-clk.txt +- assigned-clock-rates: One entry for each entry of assigned-clocks. This is + the frequency at which the corresponding clock needs + to be assigned. +- ti,sci-host-id: Host ID to which the processor control is transferred to + +Example: +--------- + +a53_0: a53@0 { + compatible = "ti,am654-rproc"; + power-domains = <&k3_pds 61>, + <&k3_pds 202>; + resets = <&k3_reset 202 0>; + assigned-clocks = <&k3_clks 202 0>; + assigned-clock-rates = <800000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/remoteproc/k3-system-controller.txt b/roms/u-boot/doc/device-tree-bindings/remoteproc/k3-system-controller.txt new file mode 100644 index 000000000..32f4720b0 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/remoteproc/k3-system-controller.txt @@ -0,0 +1,24 @@ +Texas Instruments' K3 System Controller +========================================= + +K3 specific SoCs have a dedicated microcontroller for doing +resource management. Any HLOS/firmware on compute clusters should +load a firmware to this microcontroller before accessing any resource. +This driver communicates with ROM for loading this firmware. + +Required properties: +-------------------- +- compatible: Shall be: "ti,am654-system-controller" +- mbox-names: "tx" for Transfer channel + "rx" for Receive channel +- mboxes: Corresponding phandles to mailbox channels. + + +Example: +-------- + +system-controller: system-controller { + compatible = "ti,am654-system-controller"; + mboxes= <&secproxy 4>, <&secproxy 5>; + mbox-names = "tx", "rx"; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/remoteproc/remoteproc.txt b/roms/u-boot/doc/device-tree-bindings/remoteproc/remoteproc.txt new file mode 100644 index 000000000..031764f51 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/remoteproc/remoteproc.txt @@ -0,0 +1,14 @@ +Remote Processor uclass + +Binding: + +Remoteproc devices shall have compatible corresponding to thier +drivers. However the following generic properties will be supported + +Optional Properties: +- remoteproc-name: a string, used if provided to describe the processor. + This must be unique in an operational system. +- remoteproc-internal-memory-mapped: a bool, indicates that the remote + processor has internal memory that it uses to execute code and store + data. Such a device is not expected to have a MMU. If no type property + is provided, the device is assumed to map to such a model. diff --git a/roms/u-boot/doc/device-tree-bindings/remoteproc/ti,k3-dsp-rproc.txt b/roms/u-boot/doc/device-tree-bindings/remoteproc/ti,k3-dsp-rproc.txt new file mode 100644 index 000000000..80ab7a409 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/remoteproc/ti,k3-dsp-rproc.txt @@ -0,0 +1,101 @@ +TI K3 DSP devices +================= + +The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems that +are used to offload some of the processor-intensive tasks or algorithms, for +achieving various system level goals. + +These processor sub-systems usually contain additional sub-modules like L1 +and/or L2 caches/SRAMs, an Interrupt Controller, an external memory controller, +a dedicated local power/sleep controller etc. The DSP processor cores in the +K3 SoCs is usually either a TMS320C66x CorePac processor or a TMS320C71x CorePac +processor. + +DSP Device Node: +================ +Each DSP Core sub-system is represented as a single DT node. Each node has a +number of required or optional properties that enable the OS running on the +host processor (Arm CorePac) to perform the device management of the remote +processor and to communicate with the remote processor. + +Required properties: +-------------------- +The following are the mandatory properties: + +- compatible: Should be one of the following, + "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs + "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs + +- reg: Should contain an entry for each value in 'reg-names'. + Each entry should have the memory region's start address + and the size of the region, the representation matching + the parent node's '#address-cells' and '#size-cells' values. + +- reg-names: Should contain strings with the following names, each + representing a specific internal memory region (if + present), and should be defined in this order, + "l2sram", "l1pram", "l1dram" + NOTE: C71x DSPs do not have a "l1pram" memory. + +- ti,sci: Should be a phandle to the TI-SCI System Controller node + +- ti,sci-dev-id: Should contain the TI-SCI device id corresponding to the + DSP Core. Please refer to the corresponding System + Controller documentation for valid values for the DSP + cores. + +- ti,sci-proc-ids: Should contain 2 integer values. The first cell should + contain the TI-SCI processor id for the DSP core device + and the second cell should contain the TI-SCI host id to + which the processor control ownership should be + transferred to. + +- resets: Should contain the phandle to the reset controller node + managing the resets for this device, and a reset + specifier. Please refer to the following reset bindings + for the reset argument specifier, + Documentation/devicetree/bindings/reset/ti,sci-reset.txt + +Example: +--------- + +1. J721E SoC + /* J721E remoteproc alias */ + aliases { + rproc6 = &c66_0; + rproc8 = &c71_0; + }; + + cbass_main: interconnect@100000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */ + <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ + <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */ + + /* J721E C66_0 DSP node */ + c66_0: dsp@4d80800000 { + compatible = "ti,j721e-c66-dsp"; + reg = <0x4d 0x80800000 0x00 0x00048000>, + <0x4d 0x80e00000 0x00 0x00008000>, + <0x4d 0x80f00000 0x00 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <142>; + ti,sci-proc-ids = <0x03 0xFF>; + resets = <&k3_reset 142 1>; + }; + + /* J721E C71_0 DSP node */ + c71_0: dsp@64800000 { + compatible = "ti,j721e-c71-dsp"; + reg = <0x00 0x64800000 0x00 0x00080000>, + <0x00 0x64e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <15>; + ti,sci-proc-ids = <0x30 0xFF>; + resets = <&k3_reset 15 1>; + }; + }; diff --git a/roms/u-boot/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt b/roms/u-boot/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt new file mode 100644 index 000000000..25ee495fe --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt @@ -0,0 +1,167 @@ +TI K3 R5F processor subsystems +============================== + +The TI K3 family of SoCs usually have one or more dual-core Arm Cortex +R5F processor subsystems/clusters (R5FSS). The dual core cluster can be +used either in a LockStep mode providing safety/fault tolerance features +or in a Split mode providing two individual compute cores for doubling +the compute capacity. These are used together with other processors +present on the SoC to achieve various system level goals. + +R5F Sub-System Device Node: +=========================== +Each Dual-Core R5F sub-system is represented as a single DTS node representing +the cluster, with a pair of child DT nodes representing the individual R5F +cores. Each node has a number of required or optional properties that enable +the OS running on the host processor to perform the device management of the +remote processor and to communicate with the remote processor. + +Required properties: +-------------------- +The following are the mandatory properties: + +- compatible: Should be one of the following, + "ti,am654-r5fss" for R5F clusters/subsystems on + K3 AM65x SoCs + "ti,j721e-r5fss" for R5F clusters/subsystems on + K3 J721E SoCs + "ti,j7200-r5fss" for R5F clusters/subsystems on + K3 J7200 SoCs +- power-domains: Should contain a phandle to a PM domain provider node + and an args specifier containing the R5FSS device id + value. This property is as per the binding, + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt +- #address-cells: Should be 1 +- #size-cells: Should be 1 +- ranges: Standard ranges definition providing translations for + R5F TCM address spaces + +Optional properties: +-------------------- +- ti,cluster-mode: Configuration Mode for the Dual R5F cores within the R5F + cluster. Should be either a value of 1 (LockStep mode) or + 0 (Split mode), default is LockStep mode if omitted. + + +R5F Processor Child Nodes: +========================== +The R5F Sub-System device node should define two R5F child nodes, each node +representing a TI instantiation of the Arm Cortex R5F core. There are some +specific integration differences for the IP like the usage of a Region Address +Translator (RAT) for translating the larger SoC bus addresses into a 32-bit +address space for the processor. + +Required properties: +-------------------- +The following are the mandatory properties: + +- compatible: Should be one of the following, + "ti,am654-r5f" for the R5F cores in K3 AM65x SoCs + "ti,j721e-r5f" for the R5F cores in K3 J721E SOCs + "ti,j7200-r5f" for the R5F cores in K3 J7200 SOCs +- reg: Should contain an entry for each value in 'reg-names'. + Each entry should have the memory region's start address + and the size of the region, the representation matching + the parent node's '#address-cells' and '#size-cells' values. +- reg-names: Should contain strings with the following names, each + representing a specific internal memory region, and + should be defined in this order, + "atcm", "btcm" +- ti,sci: Should be a phandle to the TI-SCI System Controller node +- ti,sci-dev-id: Should contain the TI-SCI device id corresponding to the + R5F Core. Please refer to the corresponding System + Controller documentation for valid values for the R5F + cores. +- ti,sci-proc-ids: Should contain 2 integer values. The first cell should + contain the TI-SCI processor id for the R5F core device + and the second cell should contain the TI-SCI host id to + which the processor control ownership should be + transferred to. +- resets: Should contain the phandle to the reset controller node + managing the resets for this device, and a reset + specifier. Please refer to the following reset bindings + for the reset argument specifier, + Documentation/devicetree/bindings/reset/ti,sci-reset.txt + for AM65x, J721E and J7200 SoCs + +Optional properties: +-------------------- +The following properties are optional properties for each of the R5F cores: + +- ti,atcm-enable: R5F core configuration mode dictating if ATCM should be + enabled. Should be either a value of 1 (enabled) or + 0 (disabled), default is disabled if omitted. R5F view + of ATCM dictated by ti,loczrama property. +- ti,btcm-enable: R5F core configuration mode dictating if BTCM should be + enabled. Should be either a value of 1 (enabled) or + 0 (disabled), default is enabled if omitted. R5F view + of BTCM dictated by ti,loczrama property. +- ti,loczrama: R5F core configuration mode dictating which TCM should + appear at address 0 (from core's view). Should be either + a value of 1 (ATCM at 0x0) or 0 (BTCM at 0x0), default + value is 1 if omitted. + +Example: +-------- +1. AM654 SoC + /* AM65x remoteproc alias */ + aliases { + remoteproc0 = &mcu_r5fss0_core0; + }; + + cbass_main: interconnect@100000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; + + cbass_mcu: interconnect@28380000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */ + + /* AM65x MCU R5FSS node */ + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,am654-r5fss"; + power-domains = <&k3_pds 129>; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + + mcu_r5f0: r5f@41000000 { + compatible = "ti,am654-r5f"; + reg = <0x41000000 0x00008000>, + <0x41010000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <159>; + ti,sci-proc-ids = <0x01 0xFF>; + resets = <&k3_reset 159 1>; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + mcu_r5f1: r5f@41400000 { + compatible = "ti,am654-r5f"; + reg = <0x41400000 0x00008000>, + <0x41410000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <245>; + ti,sci-proc-ids = <0x02 0xFF>; + resets = <&k3_reset 245 1>; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + }; + }; |