diff options
Diffstat (limited to 'roms/u-boot/drivers/pinctrl/mediatek')
| -rw-r--r-- | roms/u-boot/drivers/pinctrl/mediatek/Kconfig | 31 | ||||
| -rw-r--r-- | roms/u-boot/drivers/pinctrl/mediatek/Makefile | 11 | ||||
| -rw-r--r-- | roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt7622.c | 754 | ||||
| -rw-r--r-- | roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt7623.c | 1415 | ||||
| -rw-r--r-- | roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt7629.c | 418 | ||||
| -rw-r--r-- | roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt8512.c | 387 | ||||
| -rw-r--r-- | roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt8516.c | 393 | ||||
| -rw-r--r-- | roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt8518.c | 413 | ||||
| -rw-r--r-- | roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 672 | ||||
| -rw-r--r-- | roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 195 |
10 files changed, 4689 insertions, 0 deletions
diff --git a/roms/u-boot/drivers/pinctrl/mediatek/Kconfig b/roms/u-boot/drivers/pinctrl/mediatek/Kconfig new file mode 100644 index 000000000..58df508d7 --- /dev/null +++ b/roms/u-boot/drivers/pinctrl/mediatek/Kconfig @@ -0,0 +1,31 @@ +if ARCH_MEDIATEK + +config PINCTRL_MTK + depends on PINCTRL_GENERIC + bool + +config PINCTRL_MT7622 + bool "MT7622 SoC pinctrl driver" + select PINCTRL_MTK + +config PINCTRL_MT7623 + bool "MT7623 SoC pinctrl driver" + select PINCTRL_MTK + +config PINCTRL_MT7629 + bool "MT7629 SoC pinctrl driver" + select PINCTRL_MTK + +config PINCTRL_MT8512 + bool "MT8512 SoC pinctrl driver" + select PINCTRL_MTK + +config PINCTRL_MT8516 + bool "MT8516 SoC pinctrl driver" + select PINCTRL_MTK + +config PINCTRL_MT8518 + bool "MT8518 SoC pinctrl driver" + select PINCTRL_MTK + +endif diff --git a/roms/u-boot/drivers/pinctrl/mediatek/Makefile b/roms/u-boot/drivers/pinctrl/mediatek/Makefile new file mode 100644 index 000000000..d7e8cf172 --- /dev/null +++ b/roms/u-boot/drivers/pinctrl/mediatek/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 +# Core +obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o + +# SoC Drivers +obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o +obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o +obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o +obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o +obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o +obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o diff --git a/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt7622.c new file mode 100644 index 000000000..b413a4c7e --- /dev/null +++ b/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt7622.c @@ -0,0 +1,754 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <dm.h> + +#include "pinctrl-mtk-common.h" + +#define MT7622_PIN(_number, _name) MTK_PIN(_number, _name, DRV_GRP1) + +#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 0) + +#define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 1) + +static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = { + PIN_FIELD(0, 0, 0x320, 0x10, 16, 4), + PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4), + PIN_FIELD(5, 5, 0x320, 0x10, 0, 4), + PINS_FIELD(6, 7, 0x300, 0x10, 4, 4), + PIN_FIELD(8, 9, 0x350, 0x10, 20, 4), + PINS_FIELD(10, 13, 0x300, 0x10, 8, 4), + PIN_FIELD(14, 15, 0x320, 0x10, 4, 4), + PIN_FIELD(16, 17, 0x320, 0x10, 20, 4), + PIN_FIELD(18, 21, 0x310, 0x10, 16, 4), + PIN_FIELD(22, 22, 0x380, 0x10, 16, 4), + PINS_FIELD(23, 24, 0x300, 0x10, 24, 4), + PINS_FIELD(25, 36, 0x300, 0x10, 12, 4), + PINS_FIELD(37, 50, 0x300, 0x10, 20, 4), + PIN_FIELD(51, 70, 0x330, 0x10, 4, 4), + PINS_FIELD(71, 72, 0x300, 0x10, 16, 4), + PIN_FIELD(73, 76, 0x310, 0x10, 0, 4), + PIN_FIELD(77, 77, 0x320, 0x10, 28, 4), + PIN_FIELD(78, 78, 0x320, 0x10, 12, 4), + PIN_FIELD(79, 82, 0x3a0, 0x10, 0, 4), + PIN_FIELD(83, 83, 0x350, 0x10, 28, 4), + PIN_FIELD(84, 84, 0x330, 0x10, 0, 4), + PIN_FIELD(85, 90, 0x360, 0x10, 4, 4), + PIN_FIELD(91, 94, 0x390, 0x10, 16, 4), + PIN_FIELD(95, 97, 0x380, 0x10, 20, 4), + PIN_FIELD(98, 101, 0x390, 0x10, 0, 4), + PIN_FIELD(102, 102, 0x360, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = { + PIN_FIELD(0, 102, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_di_range[] = { + PIN_FIELD(0, 102, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_do_range[] = { + PIN_FIELD(0, 102, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = { + PIN_FIELD(0, 31, 0x920, 0x10, 0, 1), + PIN_FIELD(32, 50, 0xa20, 0x10, 0, 1), + PIN_FIELD(51, 70, 0x820, 0x10, 0, 1), + PIN_FIELD(71, 72, 0xb20, 0x10, 0, 1), + PIN_FIELD(73, 86, 0xb20, 0x10, 4, 1), + PIN_FIELD(87, 90, 0xc20, 0x10, 0, 1), + PIN_FIELD(91, 102, 0xb20, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = { + PIN_FIELD(0, 31, 0x930, 0x10, 0, 1), + PIN_FIELD(32, 50, 0xa30, 0x10, 0, 1), + PIN_FIELD(51, 70, 0x830, 0x10, 0, 1), + PIN_FIELD(71, 72, 0xb30, 0x10, 0, 1), + PIN_FIELD(73, 86, 0xb30, 0x10, 4, 1), + PIN_FIELD(87, 90, 0xc30, 0x10, 0, 1), + PIN_FIELD(91, 102, 0xb30, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = { + PIN_FIELD(0, 31, 0x940, 0x10, 0, 1), + PIN_FIELD(32, 50, 0xa40, 0x10, 0, 1), + PIN_FIELD(51, 70, 0x840, 0x10, 0, 1), + PIN_FIELD(71, 72, 0xb40, 0x10, 0, 1), + PIN_FIELD(73, 86, 0xb40, 0x10, 4, 1), + PIN_FIELD(87, 90, 0xc40, 0x10, 0, 1), + PIN_FIELD(91, 102, 0xb40, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = { + PIN_FIELD(0, 31, 0x960, 0x10, 0, 1), + PIN_FIELD(32, 50, 0xa60, 0x10, 0, 1), + PIN_FIELD(51, 70, 0x860, 0x10, 0, 1), + PIN_FIELD(71, 72, 0xb60, 0x10, 0, 1), + PIN_FIELD(73, 86, 0xb60, 0x10, 4, 1), + PIN_FIELD(87, 90, 0xc60, 0x10, 0, 1), + PIN_FIELD(91, 102, 0xb60, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = { + PIN_FIELD(0, 31, 0x970, 0x10, 0, 1), + PIN_FIELD(32, 50, 0xa70, 0x10, 0, 1), + PIN_FIELD(51, 70, 0x870, 0x10, 0, 1), + PIN_FIELD(71, 72, 0xb70, 0x10, 0, 1), + PIN_FIELD(73, 86, 0xb70, 0x10, 4, 1), + PIN_FIELD(87, 90, 0xc70, 0x10, 0, 1), + PIN_FIELD(91, 102, 0xb70, 0x10, 18, 1), +}; + +static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range), + [PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range), + [PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range), +}; + +static const struct mtk_pin_desc mt7622_pins[] = { + MT7622_PIN(0, "GPIO_A"), + MT7622_PIN(1, "I2S1_IN"), + MT7622_PIN(2, "I2S1_OUT"), + MT7622_PIN(3, "I2S_BCLK"), + MT7622_PIN(4, "I2S_WS"), + MT7622_PIN(5, "I2S_MCLK"), + MT7622_PIN(6, "TXD0"), + MT7622_PIN(7, "RXD0"), + MT7622_PIN(8, "SPI_WP"), + MT7622_PIN(9, "SPI_HOLD"), + MT7622_PIN(10, "SPI_CLK"), + MT7622_PIN(11, "SPI_MOSI"), + MT7622_PIN(12, "SPI_MISO"), + MT7622_PIN(13, "SPI_CS"), + MT7622_PIN(14, "I2C_SDA"), + MT7622_PIN(15, "I2C_SCL"), + MT7622_PIN(16, "I2S2_IN"), + MT7622_PIN(17, "I2S3_IN"), + MT7622_PIN(18, "I2S4_IN"), + MT7622_PIN(19, "I2S2_OUT"), + MT7622_PIN(20, "I2S3_OUT"), + MT7622_PIN(21, "I2S4_OUT"), + MT7622_PIN(22, "GPIO_B"), + MT7622_PIN(23, "MDC"), + MT7622_PIN(24, "MDIO"), + MT7622_PIN(25, "G2_TXD0"), + MT7622_PIN(26, "G2_TXD1"), + MT7622_PIN(27, "G2_TXD2"), + MT7622_PIN(28, "G2_TXD3"), + MT7622_PIN(29, "G2_TXEN"), + MT7622_PIN(30, "G2_TXC"), + MT7622_PIN(31, "G2_RXD0"), + MT7622_PIN(32, "G2_RXD1"), + MT7622_PIN(33, "G2_RXD2"), + MT7622_PIN(34, "G2_RXD3"), + MT7622_PIN(35, "G2_RXDV"), + MT7622_PIN(36, "G2_RXC"), + MT7622_PIN(37, "NCEB"), + MT7622_PIN(38, "NWEB"), + MT7622_PIN(39, "NREB"), + MT7622_PIN(40, "NDL4"), + MT7622_PIN(41, "NDL5"), + MT7622_PIN(42, "NDL6"), + MT7622_PIN(43, "NDL7"), + MT7622_PIN(44, "NRB"), + MT7622_PIN(45, "NCLE"), + MT7622_PIN(46, "NALE"), + MT7622_PIN(47, "NDL0"), + MT7622_PIN(48, "NDL1"), + MT7622_PIN(49, "NDL2"), + MT7622_PIN(50, "NDL3"), + MT7622_PIN(51, "MDI_TP_P0"), + MT7622_PIN(52, "MDI_TN_P0"), + MT7622_PIN(53, "MDI_RP_P0"), + MT7622_PIN(54, "MDI_RN_P0"), + MT7622_PIN(55, "MDI_TP_P1"), + MT7622_PIN(56, "MDI_TN_P1"), + MT7622_PIN(57, "MDI_RP_P1"), + MT7622_PIN(58, "MDI_RN_P1"), + MT7622_PIN(59, "MDI_RP_P2"), + MT7622_PIN(60, "MDI_RN_P2"), + MT7622_PIN(61, "MDI_TP_P2"), + MT7622_PIN(62, "MDI_TN_P2"), + MT7622_PIN(63, "MDI_TP_P3"), + MT7622_PIN(64, "MDI_TN_P3"), + MT7622_PIN(65, "MDI_RP_P3"), + MT7622_PIN(66, "MDI_RN_P3"), + MT7622_PIN(67, "MDI_RP_P4"), + MT7622_PIN(68, "MDI_RN_P4"), + MT7622_PIN(69, "MDI_TP_P4"), + MT7622_PIN(70, "MDI_TN_P4"), + MT7622_PIN(71, "PMIC_SCL"), + MT7622_PIN(72, "PMIC_SDA"), + MT7622_PIN(73, "SPIC1_CLK"), + MT7622_PIN(74, "SPIC1_MOSI"), + MT7622_PIN(75, "SPIC1_MISO"), + MT7622_PIN(76, "SPIC1_CS"), + MT7622_PIN(77, "GPIO_D"), + MT7622_PIN(78, "WATCHDOG"), + MT7622_PIN(79, "RTS3_N"), + MT7622_PIN(80, "CTS3_N"), + MT7622_PIN(81, "TXD3"), + MT7622_PIN(82, "RXD3"), + MT7622_PIN(83, "PERST0_N"), + MT7622_PIN(84, "PERST1_N"), + MT7622_PIN(85, "WLED_N"), + MT7622_PIN(86, "EPHY_LED0_N"), + MT7622_PIN(87, "AUXIN0"), + MT7622_PIN(88, "AUXIN1"), + MT7622_PIN(89, "AUXIN2"), + MT7622_PIN(90, "AUXIN3"), + MT7622_PIN(91, "TXD4"), + MT7622_PIN(92, "RXD4"), + MT7622_PIN(93, "RTS4_N"), + MT7622_PIN(94, "CTS4_N"), + MT7622_PIN(95, "PWM1"), + MT7622_PIN(96, "PWM2"), + MT7622_PIN(97, "PWM3"), + MT7622_PIN(98, "PWM4"), + MT7622_PIN(99, "PWM5"), + MT7622_PIN(100, "PWM6"), + MT7622_PIN(101, "PWM7"), + MT7622_PIN(102, "GPIO_E"), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. The + * hardware probably has multiple combinations of these pinouts. + */ + +/* EMMC */ +static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, }; +static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + +static int mt7622_emmc_rst_pins[] = { 37, }; +static int mt7622_emmc_rst_funcs[] = { 1, }; + +/* LED for EPHY */ +static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, }; +static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, }; +static int mt7622_ephy0_led_pins[] = { 86, }; +static int mt7622_ephy0_led_funcs[] = { 0, }; +static int mt7622_ephy1_led_pins[] = { 91, }; +static int mt7622_ephy1_led_funcs[] = { 2, }; +static int mt7622_ephy2_led_pins[] = { 92, }; +static int mt7622_ephy2_led_funcs[] = { 2, }; +static int mt7622_ephy3_led_pins[] = { 93, }; +static int mt7622_ephy3_led_funcs[] = { 2, }; +static int mt7622_ephy4_led_pins[] = { 94, }; +static int mt7622_ephy4_led_funcs[] = { 2, }; + +/* Embedded Switch */ +static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, + 62, 63, 64, 65, 66, 67, 68, 69, 70, }; +static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, }; +static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, }; +static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67, + 68, 69, 70, }; +static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, }; +/* RGMII via ESW */ +static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, + 67, 68, 69, 70, }; +static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, }; + +/* RGMII via GMAC1 */ +static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, + 67, 68, 69, 70, }; +static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, }; + +/* RGMII via GMAC2 */ +static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32, + 33, 34, 35, 36, }; +static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, }; + +/* I2C */ +static int mt7622_i2c0_pins[] = { 14, 15, }; +static int mt7622_i2c0_funcs[] = { 0, 0, }; +static int mt7622_i2c1_0_pins[] = { 55, 56, }; +static int mt7622_i2c1_0_funcs[] = { 0, 0, }; +static int mt7622_i2c1_1_pins[] = { 73, 74, }; +static int mt7622_i2c1_1_funcs[] = { 3, 3, }; +static int mt7622_i2c1_2_pins[] = { 87, 88, }; +static int mt7622_i2c1_2_funcs[] = { 0, 0, }; +static int mt7622_i2c2_0_pins[] = { 57, 58, }; +static int mt7622_i2c2_0_funcs[] = { 0, 0, }; +static int mt7622_i2c2_1_pins[] = { 75, 76, }; +static int mt7622_i2c2_1_funcs[] = { 3, 3, }; +static int mt7622_i2c2_2_pins[] = { 89, 90, }; +static int mt7622_i2c2_2_funcs[] = { 0, 0, }; + +/* I2S */ +static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, }; +static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, }; +static int mt7622_i2s1_in_data_pins[] = { 1, }; +static int mt7622_i2s1_in_data_funcs[] = { 0, }; +static int mt7622_i2s2_in_data_pins[] = { 16, }; +static int mt7622_i2s2_in_data_funcs[] = { 0, }; +static int mt7622_i2s3_in_data_pins[] = { 17, }; +static int mt7622_i2s3_in_data_funcs[] = { 0, }; +static int mt7622_i2s4_in_data_pins[] = { 18, }; +static int mt7622_i2s4_in_data_funcs[] = { 0, }; +static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, }; +static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, }; +static int mt7622_i2s1_out_data_pins[] = { 2, }; +static int mt7622_i2s1_out_data_funcs[] = { 0, }; +static int mt7622_i2s2_out_data_pins[] = { 19, }; +static int mt7622_i2s2_out_data_funcs[] = { 0, }; +static int mt7622_i2s3_out_data_pins[] = { 20, }; +static int mt7622_i2s3_out_data_funcs[] = { 0, }; +static int mt7622_i2s4_out_data_pins[] = { 21, }; +static int mt7622_i2s4_out_data_funcs[] = { 0, }; + +/* IR */ +static int mt7622_ir_0_tx_pins[] = { 16, }; +static int mt7622_ir_0_tx_funcs[] = { 4, }; +static int mt7622_ir_1_tx_pins[] = { 59, }; +static int mt7622_ir_1_tx_funcs[] = { 5, }; +static int mt7622_ir_2_tx_pins[] = { 99, }; +static int mt7622_ir_2_tx_funcs[] = { 3, }; +static int mt7622_ir_0_rx_pins[] = { 17, }; +static int mt7622_ir_0_rx_funcs[] = { 4, }; +static int mt7622_ir_1_rx_pins[] = { 60, }; +static int mt7622_ir_1_rx_funcs[] = { 5, }; +static int mt7622_ir_2_rx_pins[] = { 100, }; +static int mt7622_ir_2_rx_funcs[] = { 3, }; + +/* MDIO */ +static int mt7622_mdc_mdio_pins[] = { 23, 24, }; +static int mt7622_mdc_mdio_funcs[] = { 0, 0, }; + +/* PCIE */ +static int mt7622_pcie0_0_waken_pins[] = { 14, }; +static int mt7622_pcie0_0_waken_funcs[] = { 2, }; +static int mt7622_pcie0_0_clkreq_pins[] = { 15, }; +static int mt7622_pcie0_0_clkreq_funcs[] = { 2, }; +static int mt7622_pcie0_1_waken_pins[] = { 79, }; +static int mt7622_pcie0_1_waken_funcs[] = { 4, }; +static int mt7622_pcie0_1_clkreq_pins[] = { 80, }; +static int mt7622_pcie0_1_clkreq_funcs[] = { 4, }; +static int mt7622_pcie1_0_waken_pins[] = { 14, }; +static int mt7622_pcie1_0_waken_funcs[] = { 3, }; +static int mt7622_pcie1_0_clkreq_pins[] = { 15, }; +static int mt7622_pcie1_0_clkreq_funcs[] = { 3, }; + +static int mt7622_pcie0_pad_perst_pins[] = { 83, }; +static int mt7622_pcie0_pad_perst_funcs[] = { 0, }; +static int mt7622_pcie1_pad_perst_pins[] = { 84, }; +static int mt7622_pcie1_pad_perst_funcs[] = { 0, }; + +/* PMIC bus */ +static int mt7622_pmic_bus_pins[] = { 71, 72, }; +static int mt7622_pmic_bus_funcs[] = { 0, 0, }; + +/* Parallel NAND */ +static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, }; +static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, }; + +/* PWM */ +static int mt7622_pwm_ch1_0_pins[] = { 51, }; +static int mt7622_pwm_ch1_0_funcs[] = { 3, }; +static int mt7622_pwm_ch1_1_pins[] = { 73, }; +static int mt7622_pwm_ch1_1_funcs[] = { 4, }; +static int mt7622_pwm_ch1_2_pins[] = { 95, }; +static int mt7622_pwm_ch1_2_funcs[] = { 0, }; +static int mt7622_pwm_ch2_0_pins[] = { 52, }; +static int mt7622_pwm_ch2_0_funcs[] = { 3, }; +static int mt7622_pwm_ch2_1_pins[] = { 74, }; +static int mt7622_pwm_ch2_1_funcs[] = { 4, }; +static int mt7622_pwm_ch2_2_pins[] = { 96, }; +static int mt7622_pwm_ch2_2_funcs[] = { 0, }; +static int mt7622_pwm_ch3_0_pins[] = { 53, }; +static int mt7622_pwm_ch3_0_funcs[] = { 3, }; +static int mt7622_pwm_ch3_1_pins[] = { 75, }; +static int mt7622_pwm_ch3_1_funcs[] = { 4, }; +static int mt7622_pwm_ch3_2_pins[] = { 97, }; +static int mt7622_pwm_ch3_2_funcs[] = { 0, }; +static int mt7622_pwm_ch4_0_pins[] = { 54, }; +static int mt7622_pwm_ch4_0_funcs[] = { 3, }; +static int mt7622_pwm_ch4_1_pins[] = { 67, }; +static int mt7622_pwm_ch4_1_funcs[] = { 3, }; +static int mt7622_pwm_ch4_2_pins[] = { 76, }; +static int mt7622_pwm_ch4_2_funcs[] = { 4, }; +static int mt7622_pwm_ch4_3_pins[] = { 98, }; +static int mt7622_pwm_ch4_3_funcs[] = { 0, }; +static int mt7622_pwm_ch5_0_pins[] = { 68, }; +static int mt7622_pwm_ch5_0_funcs[] = { 3, }; +static int mt7622_pwm_ch5_1_pins[] = { 77, }; +static int mt7622_pwm_ch5_1_funcs[] = { 4, }; +static int mt7622_pwm_ch5_2_pins[] = { 99, }; +static int mt7622_pwm_ch5_2_funcs[] = { 0, }; +static int mt7622_pwm_ch6_0_pins[] = { 69, }; +static int mt7622_pwm_ch6_0_funcs[] = { 3, }; +static int mt7622_pwm_ch6_1_pins[] = { 78, }; +static int mt7622_pwm_ch6_1_funcs[] = { 4, }; +static int mt7622_pwm_ch6_2_pins[] = { 81, }; +static int mt7622_pwm_ch6_2_funcs[] = { 4, }; +static int mt7622_pwm_ch6_3_pins[] = { 100, }; +static int mt7622_pwm_ch6_3_funcs[] = { 0, }; +static int mt7622_pwm_ch7_0_pins[] = { 70, }; +static int mt7622_pwm_ch7_0_funcs[] = { 3, }; +static int mt7622_pwm_ch7_1_pins[] = { 82, }; +static int mt7622_pwm_ch7_1_funcs[] = { 4, }; +static int mt7622_pwm_ch7_2_pins[] = { 101, }; +static int mt7622_pwm_ch7_2_funcs[] = { 0, }; + +/* SD */ +static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, }; +static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, }; +static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, }; +static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, }; + +/* Serial NAND */ +static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, }; +static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, }; + +/* SPI NOR */ +static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 }; +static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, }; + +/* SPIC */ +static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, }; +static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, }; +static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, }; +static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, }; +static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, }; +static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, }; +static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, }; +static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, }; +static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, }; +static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, }; +static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, }; +static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, }; + +/* TDM */ +static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, }; +static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, }; +static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +static int mt7622_tdm_0_out_data_pins[] = { 20, }; +static int mt7622_tdm_0_out_data_funcs[] = { 3, }; +static int mt7622_tdm_0_in_data_pins[] = { 21, }; +static int mt7622_tdm_0_in_data_funcs[] = { 3, }; +static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, }; +static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, }; +static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +static int mt7622_tdm_1_out_data_pins[] = { 55, }; +static int mt7622_tdm_1_out_data_funcs[] = { 3, }; +static int mt7622_tdm_1_in_data_pins[] = { 56, }; +static int mt7622_tdm_1_in_data_funcs[] = { 3, }; + +/* UART */ +static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, }; +static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, }; +static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, }; +static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, }; +static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, }; +static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, }; +static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, }; +static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, }; +static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, }; +static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, }; +static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, }; +static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, }; +static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, }; +static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, }; +static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, }; +static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, }; +static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, }; +static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, }; +static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, }; +static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, }; +static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, }; +static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, }; +static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, }; +static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, }; +static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, }; +static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, }; +static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, }; +static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, }; +static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, }; +static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, }; +static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, }; +static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, }; +static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, }; +static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, }; +static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 }; +static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, }; +static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, }; +static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, }; +static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 }; +static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, }; + +/* Watchdog */ +static int mt7622_watchdog_pins[] = { 78, }; +static int mt7622_watchdog_funcs[] = { 0, }; + +/* WLAN LED */ +static int mt7622_wled_pins[] = { 85, }; +static int mt7622_wled_funcs[] = { 0, }; + +static const struct mtk_group_desc mt7622_groups[] = { + PINCTRL_PIN_GROUP("emmc", mt7622_emmc), + PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst), + PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds), + PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led), + PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led), + PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led), + PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led), + PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led), + PINCTRL_PIN_GROUP("esw", mt7622_esw), + PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1), + PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4), + PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw), + PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1), + PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2), + PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0), + PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0), + PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1), + PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2), + PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0), + PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1), + PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2), + PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws), + PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws), + PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data), + PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data), + PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data), + PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data), + PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data), + PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data), + PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data), + PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data), + PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx), + PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx), + PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx), + PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx), + PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx), + PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx), + PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio), + PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken), + PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq), + PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken), + PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq), + PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken), + PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq), + PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst), + PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst), + PINCTRL_PIN_GROUP("par_nand", mt7622_pnand), + PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus), + PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0), + PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1), + PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2), + PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0), + PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1), + PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2), + PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0), + PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1), + PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2), + PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0), + PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1), + PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2), + PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3), + PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0), + PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1), + PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2), + PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0), + PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1), + PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2), + PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3), + PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0), + PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1), + PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2), + PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0), + PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1), + PINCTRL_PIN_GROUP("snfi", mt7622_snfi), + PINCTRL_PIN_GROUP("spi_nor", mt7622_spi), + PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0), + PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1), + PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0), + PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1), + PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0), + PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold), + PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws", + mt7622_tdm_0_out_mclk_bclk_ws), + PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws", + mt7622_tdm_0_in_mclk_bclk_ws), + PINCTRL_PIN_GROUP("tdm_0_out_data", mt7622_tdm_0_out_data), + PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data), + PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws", + mt7622_tdm_1_out_mclk_bclk_ws), + PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws", + mt7622_tdm_1_in_mclk_bclk_ws), + PINCTRL_PIN_GROUP("tdm_1_out_data", mt7622_tdm_1_out_data), + PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data), + PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx), + PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx), + PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts), + PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx), + PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts), + PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx), + PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts), + PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx), + PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts), + PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx), + PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts), + PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx), + PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx), + PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx), + PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts), + PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx), + PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx), + PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts), + PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx), + PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts), + PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog), + PINCTRL_PIN_GROUP("wled", mt7622_wled), +}; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ +static const char *const mt7622_emmc_groups[] = { "emmc", "emmc_rst", }; +static const char *const mt7622_ethernet_groups[] = { "esw", "esw_p0_p1", + "esw_p2_p3_p4", "mdc_mdio", + "rgmii_via_gmac1", + "rgmii_via_gmac2", + "rgmii_via_esw", }; +static const char *const mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1", + "i2c1_2", "i2c2_0", "i2c2_1", + "i2c2_2", }; +static const char *const mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws", + "i2s_in_mclk_bclk_ws", + "i2s1_in_data", "i2s2_in_data", + "i2s3_in_data", "i2s4_in_data", + "i2s1_out_data", "i2s2_out_data", + "i2s3_out_data", "i2s4_out_data", }; +static const char *const mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx", + "ir_0_rx", "ir_1_rx", "ir_2_rx"}; +static const char *const mt7622_led_groups[] = { "ephy_leds", "ephy0_led", + "ephy1_led", "ephy2_led", + "ephy3_led", "ephy4_led", + "wled", }; +static const char *const mt7622_flash_groups[] = { "par_nand", "snfi", + "spi_nor"}; +static const char *const mt7622_pcie_groups[] = { "pcie0_0_waken", + "pcie0_0_clkreq", "pcie0_1_waken", + "pcie0_1_clkreq", "pcie1_0_waken", + "pcie1_0_clkreq", "pcie0_pad_perst", + "pcie1_pad_perst", }; +static const char *const mt7622_pmic_bus_groups[] = { "pmic_bus", }; +static const char *const mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1", + "pwm_ch1_2", "pwm_ch2_0", + "pwm_ch2_1", "pwm_ch2_2", + "pwm_ch3_0", "pwm_ch3_1", + "pwm_ch3_2", "pwm_ch4_0", + "pwm_ch4_1", "pwm_ch4_2", + "pwm_ch4_3", "pwm_ch5_0", + "pwm_ch5_1", "pwm_ch5_2", + "pwm_ch6_0", "pwm_ch6_1", + "pwm_ch6_2", "pwm_ch6_3", + "pwm_ch7_0", "pwm_ch7_1", + "pwm_ch7_2", }; +static const char *const mt7622_sd_groups[] = { "sd_0", "sd_1", }; +static const char *const mt7622_spic_groups[] = { "spic0_0", "spic0_1", + "spic1_0", "spic1_1", "spic2_0", + "spic2_0_wp_hold", }; +static const char *const mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws", + "tdm_0_in_mclk_bclk_ws", + "tdm_0_out_data", + "tdm_0_in_data", + "tdm_1_out_mclk_bclk_ws", + "tdm_1_in_mclk_bclk_ws", + "tdm_1_out_data", + "tdm_1_in_data", }; + +static const char *const mt7622_uart_groups[] = { "uart0_0_tx_rx", + "uart1_0_tx_rx", "uart1_0_rts_cts", + "uart1_1_tx_rx", "uart1_1_rts_cts", + "uart2_0_tx_rx", "uart2_0_rts_cts", + "uart2_1_tx_rx", "uart2_1_rts_cts", + "uart2_2_tx_rx", "uart2_2_rts_cts", + "uart2_3_tx_rx", + "uart3_0_tx_rx", + "uart3_1_tx_rx", "uart3_1_rts_cts", + "uart4_0_tx_rx", + "uart4_1_tx_rx", "uart4_1_rts_cts", + "uart4_2_tx_rx", + "uart4_2_rts_cts",}; +static const char *const mt7622_wdt_groups[] = { "watchdog", }; + +static const struct mtk_function_desc mt7622_functions[] = { + {"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)}, + {"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)}, + {"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)}, + {"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)}, + {"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)}, + {"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)}, + {"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)}, + {"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)}, + {"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)}, + {"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)}, + {"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)}, + {"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)}, + {"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)}, + {"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)}, + {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)}, +}; + +static struct mtk_pinctrl_soc mt7622_data = { + .name = "mt7622_pinctrl", + .reg_cal = mt7622_reg_cals, + .pins = mt7622_pins, + .npins = ARRAY_SIZE(mt7622_pins), + .grps = mt7622_groups, + .ngrps = ARRAY_SIZE(mt7622_groups), + .funcs = mt7622_functions, + .nfuncs = ARRAY_SIZE(mt7622_functions), + .gpio_mode = 1, + .rev = MTK_PINCTRL_V0, +}; + +static int mtk_pinctrl_mt7622_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt7622_data); +} + +static const struct udevice_id mt7622_pctrl_match[] = { + { .compatible = "mediatek,mt7622-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt7622_pinctrl) = { + .name = "mt7622_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt7622_pctrl_match, + .ops = &mtk_pinctrl_ops, + .probe = mtk_pinctrl_mt7622_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; + + diff --git a/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt7623.c new file mode 100644 index 000000000..2e3ae34b8 --- /dev/null +++ b/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt7623.c @@ -0,0 +1,1415 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + */ + +#include <dm.h> + +#include "pinctrl-mtk-common.h" + +#define PIN_BOND_REG0 0xb10 +#define PIN_BOND_REG1 0xf20 +#define PIN_BOND_REG2 0xef0 +#define BOND_PCIE_CLR (0x77 << 3) +#define BOND_I2S_CLR 0x3 +#define BOND_MSDC0E_CLR 0x1 + +#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 15, false) + +#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 16, false) + +#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)\ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 16, true) + +static const struct mtk_pin_field_calc mt7623_pin_mode_range[] = { + PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3), +}; + +static const struct mtk_pin_field_calc mt7623_pin_dir_range[] = { + PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1), + PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7623_pin_di_range[] = { + PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7623_pin_do_range[] = { + PIN_FIELD16(0, 278, 0x500, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7623_pin_ies_range[] = { + PINS_FIELD16(0, 6, 0xb20, 0x10, 0, 1), + PINS_FIELD16(7, 9, 0xb20, 0x10, 1, 1), + PINS_FIELD16(10, 13, 0xb30, 0x10, 3, 1), + PINS_FIELD16(14, 15, 0xb30, 0x10, 13, 1), + PINS_FIELD16(16, 17, 0xb40, 0x10, 7, 1), + PINS_FIELD16(18, 29, 0xb40, 0x10, 13, 1), + PINS_FIELD16(30, 32, 0xb40, 0x10, 7, 1), + PINS_FIELD16(33, 37, 0xb40, 0x10, 13, 1), + PIN_FIELD16(38, 38, 0xb20, 0x10, 13, 1), + PINS_FIELD16(39, 42, 0xb40, 0x10, 13, 1), + PINS_FIELD16(43, 45, 0xb20, 0x10, 10, 1), + PINS_FIELD16(47, 48, 0xb20, 0x10, 11, 1), + PIN_FIELD16(49, 49, 0xb20, 0x10, 12, 1), + PINS_FIELD16(50, 52, 0xb20, 0x10, 13, 1), + PINS_FIELD16(53, 56, 0xb20, 0x10, 14, 1), + PINS_FIELD16(57, 58, 0xb20, 0x10, 15, 1), + PIN_FIELD16(59, 59, 0xb30, 0x10, 10, 1), + PINS_FIELD16(60, 62, 0xb30, 0x10, 0, 1), + PINS_FIELD16(63, 65, 0xb30, 0x10, 1, 1), + PINS_FIELD16(66, 71, 0xb30, 0x10, 2, 1), + PINS_FIELD16(72, 74, 0xb20, 0x10, 12, 1), + PINS_FIELD16(75, 76, 0xb30, 0x10, 3, 1), + PINS_FIELD16(77, 78, 0xb30, 0x10, 4, 1), + PINS_FIELD16(79, 82, 0xb30, 0x10, 5, 1), + PINS_FIELD16(83, 84, 0xb30, 0x10, 2, 1), + PIN_FIELD16(85, 85, 0xda0, 0x10, 4, 1), + PIN_FIELD16(86, 86, 0xd90, 0x10, 4, 1), + PINS_FIELD16(87, 90, 0xdb0, 0x10, 4, 1), + PINS_FIELD16(101, 104, 0xb30, 0x10, 6, 1), + PIN_FIELD16(105, 105, 0xd40, 0x10, 4, 1), + PIN_FIELD16(106, 106, 0xd30, 0x10, 4, 1), + PINS_FIELD16(107, 110, 0xd50, 0x10, 4, 1), + PINS_FIELD16(111, 115, 0xce0, 0x10, 4, 1), + PIN_FIELD16(116, 116, 0xcd0, 0x10, 4, 1), + PIN_FIELD16(117, 117, 0xcc0, 0x10, 4, 1), + PINS_FIELD16(118, 121, 0xce0, 0x10, 4, 1), + PINS_FIELD16(122, 125, 0xb30, 0x10, 7, 1), + PIN_FIELD16(126, 126, 0xb20, 0x10, 12, 1), + PINS_FIELD16(127, 142, 0xb30, 0x10, 9, 1), + PINS_FIELD16(143, 160, 0xb30, 0x10, 10, 1), + PINS_FIELD16(161, 168, 0xb30, 0x10, 12, 1), + PINS_FIELD16(169, 183, 0xb30, 0x10, 10, 1), + PINS_FIELD16(184, 186, 0xb30, 0x10, 9, 1), + PIN_FIELD16(187, 187, 0xb30, 0x10, 14, 1), + PIN_FIELD16(188, 188, 0xb20, 0x10, 13, 1), + PINS_FIELD16(189, 193, 0xb30, 0x10, 15, 1), + PINS_FIELD16(194, 198, 0xb40, 0x10, 0, 1), + PIN_FIELD16(199, 199, 0xb20, 0x10, 1, 1), + PINS_FIELD16(200, 202, 0xb40, 0x10, 1, 1), + PINS_FIELD16(203, 207, 0xb40, 0x10, 2, 1), + PINS_FIELD16(208, 209, 0xb40, 0x10, 3, 1), + PIN_FIELD16(210, 210, 0xb40, 0x10, 4, 1), + PINS_FIELD16(211, 235, 0xb40, 0x10, 5, 1), + PINS_FIELD16(236, 241, 0xb40, 0x10, 6, 1), + PINS_FIELD16(242, 243, 0xb40, 0x10, 7, 1), + PINS_FIELD16(244, 247, 0xb40, 0x10, 8, 1), + PIN_FIELD16(248, 248, 0xb40, 0x10, 9, 1), + PINS_FIELD16(249, 257, 0xfc0, 0x10, 4, 1), + PIN_FIELD16(258, 258, 0xcb0, 0x10, 4, 1), + PIN_FIELD16(259, 259, 0xc90, 0x10, 4, 1), + PIN_FIELD16(260, 260, 0x3a0, 0x10, 4, 1), + PIN_FIELD16(261, 261, 0xd50, 0x10, 4, 1), + PINS_FIELD16(262, 277, 0xb40, 0x10, 12, 1), + PIN_FIELD16(278, 278, 0xb40, 0x10, 13, 1), +}; + +static const struct mtk_pin_field_calc mt7623_pin_smt_range[] = { + PINS_FIELD16(0, 6, 0xb50, 0x10, 0, 1), + PINS_FIELD16(7, 9, 0xb50, 0x10, 1, 1), + PINS_FIELD16(10, 13, 0xb60, 0x10, 3, 1), + PINS_FIELD16(14, 15, 0xb60, 0x10, 13, 1), + PINS_FIELD16(16, 17, 0xb70, 0x10, 7, 1), + PINS_FIELD16(18, 29, 0xb70, 0x10, 13, 1), + PINS_FIELD16(30, 32, 0xb70, 0x10, 7, 1), + PINS_FIELD16(33, 37, 0xb70, 0x10, 13, 1), + PIN_FIELD16(38, 38, 0xb50, 0x10, 13, 1), + PINS_FIELD16(39, 42, 0xb70, 0x10, 13, 1), + PINS_FIELD16(43, 45, 0xb50, 0x10, 10, 1), + PINS_FIELD16(47, 48, 0xb50, 0x10, 11, 1), + PIN_FIELD16(49, 49, 0xb50, 0x10, 12, 1), + PINS_FIELD16(50, 52, 0xb50, 0x10, 13, 1), + PINS_FIELD16(53, 56, 0xb50, 0x10, 14, 1), + PINS_FIELD16(57, 58, 0xb50, 0x10, 15, 1), + PIN_FIELD16(59, 59, 0xb60, 0x10, 10, 1), + PINS_FIELD16(60, 62, 0xb60, 0x10, 0, 1), + PINS_FIELD16(63, 65, 0xb60, 0x10, 1, 1), + PINS_FIELD16(66, 71, 0xb60, 0x10, 2, 1), + PINS_FIELD16(72, 74, 0xb50, 0x10, 12, 1), + PINS_FIELD16(75, 76, 0xb60, 0x10, 3, 1), + PINS_FIELD16(77, 78, 0xb60, 0x10, 4, 1), + PINS_FIELD16(79, 82, 0xb60, 0x10, 5, 1), + PINS_FIELD16(83, 84, 0xb60, 0x10, 2, 1), + PIN_FIELD16(85, 85, 0xda0, 0x10, 11, 1), + PIN_FIELD16(86, 86, 0xd90, 0x10, 11, 1), + PIN_FIELD16(87, 87, 0xdc0, 0x10, 3, 1), + PIN_FIELD16(88, 88, 0xdc0, 0x10, 7, 1), + PIN_FIELD16(89, 89, 0xdc0, 0x10, 11, 1), + PIN_FIELD16(90, 90, 0xdc0, 0x10, 15, 1), + PINS_FIELD16(101, 104, 0xb60, 0x10, 6, 1), + PIN_FIELD16(105, 105, 0xd40, 0x10, 11, 1), + PIN_FIELD16(106, 106, 0xd30, 0x10, 11, 1), + PIN_FIELD16(107, 107, 0xd60, 0x10, 3, 1), + PIN_FIELD16(108, 108, 0xd60, 0x10, 7, 1), + PIN_FIELD16(109, 109, 0xd60, 0x10, 11, 1), + PIN_FIELD16(110, 110, 0xd60, 0x10, 15, 1), + PIN_FIELD16(111, 111, 0xd00, 0x10, 15, 1), + PIN_FIELD16(112, 112, 0xd00, 0x10, 11, 1), + PIN_FIELD16(113, 113, 0xd00, 0x10, 7, 1), + PIN_FIELD16(114, 114, 0xd00, 0x10, 3, 1), + PIN_FIELD16(115, 115, 0xd10, 0x10, 3, 1), + PIN_FIELD16(116, 116, 0xcd0, 0x10, 11, 1), + PIN_FIELD16(117, 117, 0xcc0, 0x10, 11, 1), + PIN_FIELD16(118, 118, 0xcf0, 0x10, 15, 1), + PIN_FIELD16(119, 119, 0xcf0, 0x10, 7, 1), + PIN_FIELD16(120, 120, 0xcf0, 0x10, 3, 1), + PIN_FIELD16(121, 121, 0xcf0, 0x10, 7, 1), + PINS_FIELD16(122, 125, 0xb60, 0x10, 7, 1), + PIN_FIELD16(126, 126, 0xb50, 0x10, 12, 1), + PINS_FIELD16(127, 142, 0xb60, 0x10, 9, 1), + PINS_FIELD16(143, 160, 0xb60, 0x10, 10, 1), + PINS_FIELD16(161, 168, 0xb60, 0x10, 12, 1), + PINS_FIELD16(169, 183, 0xb60, 0x10, 10, 1), + PINS_FIELD16(184, 186, 0xb60, 0x10, 9, 1), + PIN_FIELD16(187, 187, 0xb60, 0x10, 14, 1), + PIN_FIELD16(188, 188, 0xb50, 0x10, 13, 1), + PINS_FIELD16(189, 193, 0xb60, 0x10, 15, 1), + PINS_FIELD16(194, 198, 0xb70, 0x10, 0, 1), + PIN_FIELD16(199, 199, 0xb50, 0x10, 1, 1), + PINS_FIELD16(200, 202, 0xb70, 0x10, 1, 1), + PINS_FIELD16(203, 207, 0xb70, 0x10, 2, 1), + PINS_FIELD16(208, 209, 0xb70, 0x10, 3, 1), + PIN_FIELD16(210, 210, 0xb70, 0x10, 4, 1), + PINS_FIELD16(211, 235, 0xb70, 0x10, 5, 1), + PINS_FIELD16(236, 241, 0xb70, 0x10, 6, 1), + PINS_FIELD16(242, 243, 0xb70, 0x10, 7, 1), + PINS_FIELD16(244, 247, 0xb70, 0x10, 8, 1), + PIN_FIELD16(248, 248, 0xb70, 0x10, 9, 10), + PIN_FIELD16(249, 249, 0x140, 0x10, 3, 1), + PIN_FIELD16(250, 250, 0x130, 0x10, 15, 1), + PIN_FIELD16(251, 251, 0x130, 0x10, 11, 1), + PIN_FIELD16(252, 252, 0x130, 0x10, 7, 1), + PIN_FIELD16(253, 253, 0x130, 0x10, 3, 1), + PIN_FIELD16(254, 254, 0xf40, 0x10, 15, 1), + PIN_FIELD16(255, 255, 0xf40, 0x10, 11, 1), + PIN_FIELD16(256, 256, 0xf40, 0x10, 7, 1), + PIN_FIELD16(257, 257, 0xf40, 0x10, 3, 1), + PIN_FIELD16(258, 258, 0xcb0, 0x10, 11, 1), + PIN_FIELD16(259, 259, 0xc90, 0x10, 11, 1), + PIN_FIELD16(260, 260, 0x3a0, 0x10, 11, 1), + PIN_FIELD16(261, 261, 0x0b0, 0x10, 3, 1), + PINS_FIELD16(262, 277, 0xb70, 0x10, 12, 1), + PIN_FIELD16(278, 278, 0xb70, 0x10, 13, 1), +}; + +static const struct mtk_pin_field_calc mt7623_pin_pullen_range[] = { + PIN_FIELD16(0, 278, 0x150, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7623_pin_pullsel_range[] = { + PIN_FIELD16(0, 278, 0x280, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7623_pin_drv_range[] = { + PINS_FIELD16(0, 6, 0xf50, 0x10, 0, 4), + PINS_FIELD16(7, 9, 0xf50, 0x10, 4, 4), + PINS_FIELD16(10, 13, 0xf50, 0x10, 4, 4), + PINS_FIELD16(14, 15, 0xf50, 0x10, 12, 4), + PINS_FIELD16(16, 17, 0xf60, 0x10, 0, 4), + PINS_FIELD16(18, 21, 0xf60, 0x10, 0, 4), + PINS_FIELD16(22, 26, 0xf60, 0x10, 8, 4), + PINS_FIELD16(27, 29, 0xf60, 0x10, 12, 4), + PINS_FIELD16(30, 32, 0xf60, 0x10, 0, 4), + PINS_FIELD16(33, 37, 0xf70, 0x10, 0, 4), + PIN_FIELD16(38, 38, 0xf70, 0x10, 4, 4), + PINS_FIELD16(39, 42, 0xf70, 0x10, 8, 4), + PINS_FIELD16(43, 45, 0xf70, 0x10, 12, 4), + PINS_FIELD16(47, 48, 0xf80, 0x10, 0, 4), + PIN_FIELD16(49, 49, 0xf80, 0x10, 4, 4), + PINS_FIELD16(50, 52, 0xf70, 0x10, 4, 4), + PINS_FIELD16(53, 56, 0xf80, 0x10, 12, 4), + PINS_FIELD16(60, 62, 0xf90, 0x10, 8, 4), + PINS_FIELD16(63, 65, 0xf90, 0x10, 12, 4), + PINS_FIELD16(66, 71, 0xfa0, 0x10, 0, 4), + PINS_FIELD16(72, 74, 0xf80, 0x10, 4, 4), + PIN_FIELD16(85, 85, 0xda0, 0x10, 0, 4), + PIN_FIELD16(86, 86, 0xd90, 0x10, 0, 4), + PINS_FIELD16(87, 90, 0xdb0, 0x10, 0, 4), + PIN_FIELD16(105, 105, 0xd40, 0x10, 0, 4), + PIN_FIELD16(106, 106, 0xd30, 0x10, 0, 4), + PINS_FIELD16(107, 110, 0xd50, 0x10, 0, 4), + PINS_FIELD16(111, 115, 0xce0, 0x10, 0, 4), + PIN_FIELD16(116, 116, 0xcd0, 0x10, 0, 4), + PIN_FIELD16(117, 117, 0xcc0, 0x10, 0, 4), + PINS_FIELD16(118, 121, 0xce0, 0x10, 0, 4), + PIN_FIELD16(126, 126, 0xf80, 0x10, 4, 4), + PIN_FIELD16(188, 188, 0xf70, 0x10, 4, 4), + PINS_FIELD16(189, 193, 0xfe0, 0x10, 8, 4), + PINS_FIELD16(194, 198, 0xfe0, 0x10, 12, 4), + PIN_FIELD16(199, 199, 0xf50, 0x10, 4, 4), + PINS_FIELD16(200, 202, 0xfd0, 0x10, 0, 4), + PINS_FIELD16(203, 207, 0xfd0, 0x10, 4, 4), + PINS_FIELD16(208, 209, 0xfd0, 0x10, 8, 4), + PIN_FIELD16(210, 210, 0xfd0, 0x10, 12, 4), + PINS_FIELD16(211, 235, 0xff0, 0x10, 0, 4), + PINS_FIELD16(236, 241, 0xff0, 0x10, 4, 4), + PINS_FIELD16(242, 243, 0xff0, 0x10, 8, 4), + PIN_FIELD16(248, 248, 0xf00, 0x10, 0, 4), + PINS_FIELD16(249, 256, 0xfc0, 0x10, 0, 4), + PIN_FIELD16(257, 257, 0xce0, 0x10, 0, 4), + PIN_FIELD16(258, 258, 0xcb0, 0x10, 0, 4), + PIN_FIELD16(259, 259, 0xc90, 0x10, 0, 4), + PIN_FIELD16(260, 260, 0x3a0, 0x10, 0, 4), + PIN_FIELD16(261, 261, 0xd50, 0x10, 0, 4), + PINS_FIELD16(262, 277, 0xf00, 0x10, 8, 4), + PIN_FIELD16(278, 278, 0xf70, 0x10, 8, 4), +}; + +static const struct mtk_pin_field_calc mt7623_pin_pupd_range[] = { + /* MSDC0 */ + PIN_FIELD16(111, 111, 0xd00, 0x10, 12, 1), + PIN_FIELD16(112, 112, 0xd00, 0x10, 8, 1), + PIN_FIELD16(113, 113, 0xd00, 0x10, 4, 1), + PIN_FIELD16(114, 114, 0xd00, 0x10, 0, 1), + PIN_FIELD16(115, 115, 0xd10, 0x10, 0, 1), + PIN_FIELD16(116, 116, 0xcd0, 0x10, 8, 1), + PIN_FIELD16(117, 117, 0xcc0, 0x10, 8, 1), + PIN_FIELD16(118, 118, 0xcf0, 0x10, 12, 1), + PIN_FIELD16(119, 119, 0xcf0, 0x10, 8, 1), + PIN_FIELD16(120, 120, 0xcf0, 0x10, 4, 1), + PIN_FIELD16(121, 121, 0xcf0, 0x10, 0, 1), + /* MSDC1 */ + PIN_FIELD16(105, 105, 0xd40, 0x10, 8, 1), + PIN_FIELD16(106, 106, 0xd30, 0x10, 8, 1), + PIN_FIELD16(107, 107, 0xd60, 0x10, 0, 1), + PIN_FIELD16(108, 108, 0xd60, 0x10, 10, 1), + PIN_FIELD16(109, 109, 0xd60, 0x10, 4, 1), + PIN_FIELD16(110, 110, 0xc60, 0x10, 12, 1), + /* MSDC1 */ + PIN_FIELD16(85, 85, 0xda0, 0x10, 8, 1), + PIN_FIELD16(86, 86, 0xd90, 0x10, 8, 1), + PIN_FIELD16(87, 87, 0xdc0, 0x10, 0, 1), + PIN_FIELD16(88, 88, 0xdc0, 0x10, 10, 1), + PIN_FIELD16(89, 89, 0xdc0, 0x10, 4, 1), + PIN_FIELD16(90, 90, 0xdc0, 0x10, 12, 1), + /* MSDC0E */ + PIN_FIELD16(249, 249, 0x140, 0x10, 0, 1), + PIN_FIELD16(250, 250, 0x130, 0x10, 12, 1), + PIN_FIELD16(251, 251, 0x130, 0x10, 8, 1), + PIN_FIELD16(252, 252, 0x130, 0x10, 4, 1), + PIN_FIELD16(253, 253, 0x130, 0x10, 0, 1), + PIN_FIELD16(254, 254, 0xf40, 0x10, 12, 1), + PIN_FIELD16(255, 255, 0xf40, 0x10, 8, 1), + PIN_FIELD16(256, 256, 0xf40, 0x10, 4, 1), + PIN_FIELD16(257, 257, 0xf40, 0x10, 0, 1), + PIN_FIELD16(258, 258, 0xcb0, 0x10, 8, 1), + PIN_FIELD16(259, 259, 0xc90, 0x10, 8, 1), + PIN_FIELD16(261, 261, 0x140, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7623_pin_r1_range[] = { + /* MSDC0 */ + PIN_FIELD16(111, 111, 0xd00, 0x10, 13, 1), + PIN_FIELD16(112, 112, 0xd00, 0x10, 9, 1), + PIN_FIELD16(113, 113, 0xd00, 0x10, 5, 1), + PIN_FIELD16(114, 114, 0xd00, 0x10, 1, 1), + PIN_FIELD16(115, 115, 0xd10, 0x10, 1, 1), + PIN_FIELD16(116, 116, 0xcd0, 0x10, 9, 1), + PIN_FIELD16(117, 117, 0xcc0, 0x10, 9, 1), + PIN_FIELD16(118, 118, 0xcf0, 0x10, 13, 1), + PIN_FIELD16(119, 119, 0xcf0, 0x10, 9, 1), + PIN_FIELD16(120, 120, 0xcf0, 0x10, 5, 1), + PIN_FIELD16(121, 121, 0xcf0, 0x10, 1, 1), + /* MSDC1 */ + PIN_FIELD16(105, 105, 0xd40, 0x10, 9, 1), + PIN_FIELD16(106, 106, 0xd30, 0x10, 9, 1), + PIN_FIELD16(107, 107, 0xd60, 0x10, 1, 1), + PIN_FIELD16(108, 108, 0xd60, 0x10, 9, 1), + PIN_FIELD16(109, 109, 0xd60, 0x10, 5, 1), + PIN_FIELD16(110, 110, 0xc60, 0x10, 13, 1), + /* MSDC2 */ + PIN_FIELD16(85, 85, 0xda0, 0x10, 9, 1), + PIN_FIELD16(86, 86, 0xd90, 0x10, 9, 1), + PIN_FIELD16(87, 87, 0xdc0, 0x10, 1, 1), + PIN_FIELD16(88, 88, 0xdc0, 0x10, 9, 1), + PIN_FIELD16(89, 89, 0xdc0, 0x10, 5, 1), + PIN_FIELD16(90, 90, 0xdc0, 0x10, 13, 1), + /* MSDC0E */ + PIN_FIELD16(249, 249, 0x140, 0x10, 1, 1), + PIN_FIELD16(250, 250, 0x130, 0x10, 13, 1), + PIN_FIELD16(251, 251, 0x130, 0x10, 9, 1), + PIN_FIELD16(252, 252, 0x130, 0x10, 5, 1), + PIN_FIELD16(253, 253, 0x130, 0x10, 1, 1), + PIN_FIELD16(254, 254, 0xf40, 0x10, 13, 1), + PIN_FIELD16(255, 255, 0xf40, 0x10, 9, 1), + PIN_FIELD16(256, 256, 0xf40, 0x10, 5, 1), + PIN_FIELD16(257, 257, 0xf40, 0x10, 1, 1), + PIN_FIELD16(258, 258, 0xcb0, 0x10, 9, 1), + PIN_FIELD16(259, 259, 0xc90, 0x10, 9, 1), + PIN_FIELD16(261, 261, 0x140, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt7623_pin_r0_range[] = { + /* MSDC0 */ + PIN_FIELD16(111, 111, 0xd00, 0x10, 14, 1), + PIN_FIELD16(112, 112, 0xd00, 0x10, 10, 1), + PIN_FIELD16(113, 113, 0xd00, 0x10, 6, 1), + PIN_FIELD16(114, 114, 0xd00, 0x10, 2, 1), + PIN_FIELD16(115, 115, 0xd10, 0x10, 2, 1), + PIN_FIELD16(116, 116, 0xcd0, 0x10, 10, 1), + PIN_FIELD16(117, 117, 0xcc0, 0x10, 10, 1), + PIN_FIELD16(118, 118, 0xcf0, 0x10, 14, 1), + PIN_FIELD16(119, 119, 0xcf0, 0x10, 10, 1), + PIN_FIELD16(120, 120, 0xcf0, 0x10, 6, 1), + PIN_FIELD16(121, 121, 0xcf0, 0x10, 2, 1), + /* MSDC1 */ + PIN_FIELD16(105, 105, 0xd40, 0x10, 10, 1), + PIN_FIELD16(106, 106, 0xd30, 0x10, 10, 1), + PIN_FIELD16(107, 107, 0xd60, 0x10, 2, 1), + PIN_FIELD16(108, 108, 0xd60, 0x10, 8, 1), + PIN_FIELD16(109, 109, 0xd60, 0x10, 6, 1), + PIN_FIELD16(110, 110, 0xc60, 0x10, 14, 1), + /* MSDC2 */ + PIN_FIELD16(85, 85, 0xda0, 0x10, 10, 1), + PIN_FIELD16(86, 86, 0xd90, 0x10, 10, 1), + PIN_FIELD16(87, 87, 0xdc0, 0x10, 2, 1), + PIN_FIELD16(88, 88, 0xdc0, 0x10, 8, 1), + PIN_FIELD16(89, 89, 0xdc0, 0x10, 6, 1), + PIN_FIELD16(90, 90, 0xdc0, 0x10, 14, 1), + /* MSDC0E */ + PIN_FIELD16(249, 249, 0x140, 0x10, 2, 1), + PIN_FIELD16(250, 250, 0x130, 0x10, 14, 1), + PIN_FIELD16(251, 251, 0x130, 0x10, 10, 1), + PIN_FIELD16(252, 252, 0x130, 0x10, 6, 1), + PIN_FIELD16(253, 253, 0x130, 0x10, 2, 1), + PIN_FIELD16(254, 254, 0xf40, 0x10, 14, 1), + PIN_FIELD16(255, 255, 0xf40, 0x10, 10, 1), + PIN_FIELD16(256, 256, 0xf40, 0x10, 6, 1), + PIN_FIELD16(257, 257, 0xf40, 0x10, 5, 1), + PIN_FIELD16(258, 258, 0xcb0, 0x10, 10, 1), + PIN_FIELD16(259, 259, 0xc90, 0x10, 10, 1), + PIN_FIELD16(261, 261, 0x140, 0x10, 10, 1), +}; + +static const struct mtk_pin_reg_calc mt7623_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7623_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7623_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7623_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7623_pin_do_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7623_pin_ies_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7623_pin_smt_range), + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7623_pin_pullsel_range), + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7623_pin_pullen_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7623_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7623_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7623_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7623_pin_r1_range), +}; + +static const struct mtk_pin_desc mt7623_pins[] = { + MTK_PIN(0, "PWRAP_SPI0_MI", DRV_GRP3), + MTK_PIN(1, "PWRAP_SPI0_MO", DRV_GRP3), + MTK_PIN(2, "PWRAP_INT", DRV_GRP3), + MTK_PIN(3, "PWRAP_SPI0_CK", DRV_GRP3), + MTK_PIN(4, "PWRAP_SPI0_CSN", DRV_GRP3), + MTK_PIN(5, "PWRAP_SPI0_CK2", DRV_GRP3), + MTK_PIN(6, "PWRAP_SPI0_CSN2", DRV_GRP3), + MTK_PIN(7, "SPI1_CSN", DRV_GRP3), + MTK_PIN(8, "SPI1_MI", DRV_GRP3), + MTK_PIN(9, "SPI1_MO", DRV_GRP3), + MTK_PIN(10, "RTC32K_CK", DRV_GRP3), + MTK_PIN(11, "WATCHDOG", DRV_GRP3), + MTK_PIN(12, "SRCLKENA", DRV_GRP3), + MTK_PIN(13, "SRCLKENAI", DRV_GRP3), + MTK_PIN(14, "URXD2", DRV_GRP1), + MTK_PIN(15, "UTXD2", DRV_GRP1), + MTK_PIN(16, "I2S5_DATA_IN", DRV_GRP1), + MTK_PIN(17, "I2S5_BCK", DRV_GRP1), + MTK_PIN(18, "PCM_CLK", DRV_GRP1), + MTK_PIN(19, "PCM_SYNC", DRV_GRP1), + MTK_PIN(20, "PCM_RX", DRV_GRP1), + MTK_PIN(21, "PCM_TX", DRV_GRP1), + MTK_PIN(22, "EINT0", DRV_GRP1), + MTK_PIN(23, "EINT1", DRV_GRP1), + MTK_PIN(24, "EINT2", DRV_GRP1), + MTK_PIN(25, "EINT3", DRV_GRP1), + MTK_PIN(26, "EINT4", DRV_GRP1), + MTK_PIN(27, "EINT5", DRV_GRP1), + MTK_PIN(28, "EINT6", DRV_GRP1), + MTK_PIN(29, "EINT7", DRV_GRP1), + MTK_PIN(30, "I2S5_LRCK", DRV_GRP1), + MTK_PIN(31, "I2S5_MCLK", DRV_GRP1), + MTK_PIN(32, "I2S5_DATA", DRV_GRP1), + MTK_PIN(33, "I2S1_DATA", DRV_GRP1), + MTK_PIN(34, "I2S1_DATA_IN", DRV_GRP1), + MTK_PIN(35, "I2S1_BCK", DRV_GRP1), + MTK_PIN(36, "I2S1_LRCK", DRV_GRP1), + MTK_PIN(37, "I2S1_MCLK", DRV_GRP1), + MTK_PIN(38, "I2S2_DATA", DRV_GRP1), + MTK_PIN(39, "JTMS", DRV_GRP3), + MTK_PIN(40, "JTCK", DRV_GRP3), + MTK_PIN(41, "JTDI", DRV_GRP3), + MTK_PIN(42, "JTDO", DRV_GRP3), + MTK_PIN(43, "NCLE", DRV_GRP1), + MTK_PIN(44, "NCEB1", DRV_GRP1), + MTK_PIN(45, "NCEB0", DRV_GRP1), + MTK_PIN(46, "IR", DRV_FIXED), + MTK_PIN(47, "NREB", DRV_GRP1), + MTK_PIN(48, "NRNB", DRV_GRP1), + MTK_PIN(49, "I2S0_DATA", DRV_GRP1), + MTK_PIN(50, "I2S2_BCK", DRV_GRP1), + MTK_PIN(51, "I2S2_DATA_IN", DRV_GRP1), + MTK_PIN(52, "I2S2_LRCK", DRV_GRP1), + MTK_PIN(53, "SPI0_CSN", DRV_GRP1), + MTK_PIN(54, "SPI0_CK", DRV_GRP1), + MTK_PIN(55, "SPI0_MI", DRV_GRP1), + MTK_PIN(56, "SPI0_MO", DRV_GRP1), + MTK_PIN(57, "SDA1", DRV_FIXED), + MTK_PIN(58, "SCL1", DRV_FIXED), + MTK_PIN(59, "RAMBUF_I_CLK", DRV_FIXED), + MTK_PIN(60, "WB_RSTB", DRV_GRP3), + MTK_PIN(61, "F2W_DATA", DRV_GRP3), + MTK_PIN(62, "F2W_CLK", DRV_GRP3), + MTK_PIN(63, "WB_SCLK", DRV_GRP3), + MTK_PIN(64, "WB_SDATA", DRV_GRP3), + MTK_PIN(65, "WB_SEN", DRV_GRP3), + MTK_PIN(66, "WB_CRTL0", DRV_GRP3), + MTK_PIN(67, "WB_CRTL1", DRV_GRP3), + MTK_PIN(68, "WB_CRTL2", DRV_GRP3), + MTK_PIN(69, "WB_CRTL3", DRV_GRP3), + MTK_PIN(70, "WB_CRTL4", DRV_GRP3), + MTK_PIN(71, "WB_CRTL5", DRV_GRP3), + MTK_PIN(72, "I2S0_DATA_IN", DRV_GRP1), + MTK_PIN(73, "I2S0_LRCK", DRV_GRP1), + MTK_PIN(74, "I2S0_BCK", DRV_GRP1), + MTK_PIN(75, "SDA0", DRV_FIXED), + MTK_PIN(76, "SCL0", DRV_FIXED), + MTK_PIN(77, "SDA2", DRV_FIXED), + MTK_PIN(78, "SCL2", DRV_FIXED), + MTK_PIN(79, "URXD0", DRV_FIXED), + MTK_PIN(80, "UTXD0", DRV_FIXED), + MTK_PIN(81, "URXD1", DRV_FIXED), + MTK_PIN(82, "UTXD1", DRV_FIXED), + MTK_PIN(83, "LCM_RST", DRV_FIXED), + MTK_PIN(84, "DSI_TE", DRV_FIXED), + MTK_PIN(85, "MSDC2_CMD", DRV_GRP4), + MTK_PIN(86, "MSDC2_CLK", DRV_GRP4), + MTK_PIN(87, "MSDC2_DAT0", DRV_GRP4), + MTK_PIN(88, "MSDC2_DAT1", DRV_GRP4), + MTK_PIN(89, "MSDC2_DAT2", DRV_GRP4), + MTK_PIN(90, "MSDC2_DAT3", DRV_GRP4), + MTK_PIN(91, "TDN3", DRV_FIXED), + MTK_PIN(92, "TDP3", DRV_FIXED), + MTK_PIN(93, "TDN2", DRV_FIXED), + MTK_PIN(94, "TDP2", DRV_FIXED), + MTK_PIN(95, "TCN", DRV_FIXED), + MTK_PIN(96, "TCP", DRV_FIXED), + MTK_PIN(97, "TDN1", DRV_FIXED), + MTK_PIN(98, "TDP1", DRV_FIXED), + MTK_PIN(99, "TDN0", DRV_FIXED), + MTK_PIN(100, "TDP0", DRV_FIXED), + MTK_PIN(101, "SPI2_CSN", DRV_FIXED), + MTK_PIN(102, "SPI2_MI", DRV_FIXED), + MTK_PIN(103, "SPI2_MO", DRV_FIXED), + MTK_PIN(104, "SPI2_CLK", DRV_FIXED), + MTK_PIN(105, "MSDC1_CMD", DRV_GRP4), + MTK_PIN(106, "MSDC1_CLK", DRV_GRP4), + MTK_PIN(107, "MSDC1_DAT0", DRV_GRP4), + MTK_PIN(108, "MSDC1_DAT1", DRV_GRP4), + MTK_PIN(109, "MSDC1_DAT2", DRV_GRP4), + MTK_PIN(110, "MSDC1_DAT3", DRV_GRP4), + MTK_PIN(111, "MSDC0_DAT7", DRV_GRP4), + MTK_PIN(112, "MSDC0_DAT6", DRV_GRP4), + MTK_PIN(113, "MSDC0_DAT5", DRV_GRP4), + MTK_PIN(114, "MSDC0_DAT4", DRV_GRP4), + MTK_PIN(115, "MSDC0_RSTB", DRV_GRP4), + MTK_PIN(116, "MSDC0_CMD", DRV_GRP4), + MTK_PIN(117, "MSDC0_CLK", DRV_GRP4), + MTK_PIN(118, "MSDC0_DAT3", DRV_GRP4), + MTK_PIN(119, "MSDC0_DAT2", DRV_GRP4), + MTK_PIN(120, "MSDC0_DAT1", DRV_GRP4), + MTK_PIN(121, "MSDC0_DAT0", DRV_GRP4), + MTK_PIN(122, "CEC", DRV_FIXED), + MTK_PIN(123, "HTPLG", DRV_FIXED), + MTK_PIN(124, "HDMISCK", DRV_FIXED), + MTK_PIN(125, "HDMISD", DRV_FIXED), + MTK_PIN(126, "I2S0_MCLK", DRV_GRP1), + MTK_PIN(127, "RAMBUF_IDATA0", DRV_FIXED), + MTK_PIN(128, "RAMBUF_IDATA1", DRV_FIXED), + MTK_PIN(129, "RAMBUF_IDATA2", DRV_FIXED), + MTK_PIN(130, "RAMBUF_IDATA3", DRV_FIXED), + MTK_PIN(131, "RAMBUF_IDATA4", DRV_FIXED), + MTK_PIN(132, "RAMBUF_IDATA5", DRV_FIXED), + MTK_PIN(133, "RAMBUF_IDATA6", DRV_FIXED), + MTK_PIN(134, "RAMBUF_IDATA7", DRV_FIXED), + MTK_PIN(135, "RAMBUF_IDATA8", DRV_FIXED), + MTK_PIN(136, "RAMBUF_IDATA9", DRV_FIXED), + MTK_PIN(137, "RAMBUF_IDATA10", DRV_FIXED), + MTK_PIN(138, "RAMBUF_IDATA11", DRV_FIXED), + MTK_PIN(139, "RAMBUF_IDATA12", DRV_FIXED), + MTK_PIN(140, "RAMBUF_IDATA13", DRV_FIXED), + MTK_PIN(141, "RAMBUF_IDATA14", DRV_FIXED), + MTK_PIN(142, "RAMBUF_IDATA15", DRV_FIXED), + MTK_PIN(143, "RAMBUF_ODATA0", DRV_FIXED), + MTK_PIN(144, "RAMBUF_ODATA1", DRV_FIXED), + MTK_PIN(145, "RAMBUF_ODATA2", DRV_FIXED), + MTK_PIN(146, "RAMBUF_ODATA3", DRV_FIXED), + MTK_PIN(147, "RAMBUF_ODATA4", DRV_FIXED), + MTK_PIN(148, "RAMBUF_ODATA5", DRV_FIXED), + MTK_PIN(149, "RAMBUF_ODATA6", DRV_FIXED), + MTK_PIN(150, "RAMBUF_ODATA7", DRV_FIXED), + MTK_PIN(151, "RAMBUF_ODATA8", DRV_FIXED), + MTK_PIN(152, "RAMBUF_ODATA9", DRV_FIXED), + MTK_PIN(153, "RAMBUF_ODATA10", DRV_FIXED), + MTK_PIN(154, "RAMBUF_ODATA11", DRV_FIXED), + MTK_PIN(155, "RAMBUF_ODATA12", DRV_FIXED), + MTK_PIN(156, "RAMBUF_ODATA13", DRV_FIXED), + MTK_PIN(157, "RAMBUF_ODATA14", DRV_FIXED), + MTK_PIN(158, "RAMBUF_ODATA15", DRV_FIXED), + MTK_PIN(159, "RAMBUF_BE0", DRV_FIXED), + MTK_PIN(160, "RAMBUF_BE1", DRV_FIXED), + MTK_PIN(161, "AP2PT_INT", DRV_FIXED), + MTK_PIN(162, "AP2PT_INT_CLR", DRV_FIXED), + MTK_PIN(163, "PT2AP_INT", DRV_FIXED), + MTK_PIN(164, "PT2AP_INT_CLR", DRV_FIXED), + MTK_PIN(165, "AP2UP_INT", DRV_FIXED), + MTK_PIN(166, "AP2UP_INT_CLR", DRV_FIXED), + MTK_PIN(167, "UP2AP_INT", DRV_FIXED), + MTK_PIN(168, "UP2AP_INT_CLR", DRV_FIXED), + MTK_PIN(169, "RAMBUF_ADDR0", DRV_FIXED), + MTK_PIN(170, "RAMBUF_ADDR1", DRV_FIXED), + MTK_PIN(171, "RAMBUF_ADDR2", DRV_FIXED), + MTK_PIN(172, "RAMBUF_ADDR3", DRV_FIXED), + MTK_PIN(173, "RAMBUF_ADDR4", DRV_FIXED), + MTK_PIN(174, "RAMBUF_ADDR5", DRV_FIXED), + MTK_PIN(175, "RAMBUF_ADDR6", DRV_FIXED), + MTK_PIN(176, "RAMBUF_ADDR7", DRV_FIXED), + MTK_PIN(177, "RAMBUF_ADDR8", DRV_FIXED), + MTK_PIN(178, "RAMBUF_ADDR9", DRV_FIXED), + MTK_PIN(179, "RAMBUF_ADDR10", DRV_FIXED), + MTK_PIN(180, "RAMBUF_RW", DRV_FIXED), + MTK_PIN(181, "RAMBUF_LAST", DRV_FIXED), + MTK_PIN(182, "RAMBUF_HP", DRV_FIXED), + MTK_PIN(183, "RAMBUF_REQ", DRV_FIXED), + MTK_PIN(184, "RAMBUF_ALE", DRV_FIXED), + MTK_PIN(185, "RAMBUF_DLE", DRV_FIXED), + MTK_PIN(186, "RAMBUF_WDLE", DRV_FIXED), + MTK_PIN(187, "RAMBUF_O_CLK", DRV_FIXED), + MTK_PIN(188, "I2S2_MCLK", DRV_GRP1), + MTK_PIN(189, "I2S3_DATA", DRV_GRP1), + MTK_PIN(190, "I2S3_DATA_IN", DRV_GRP1), + MTK_PIN(191, "I2S3_BCK", DRV_GRP1), + MTK_PIN(192, "I2S3_LRCK", DRV_GRP1), + MTK_PIN(193, "I2S3_MCLK", DRV_GRP1), + MTK_PIN(194, "I2S4_DATA", DRV_GRP1), + MTK_PIN(195, "I2S4_DATA_IN", DRV_GRP1), + MTK_PIN(196, "I2S4_BCK", DRV_GRP1), + MTK_PIN(197, "I2S4_LRCK", DRV_GRP1), + MTK_PIN(198, "I2S4_MCLK", DRV_GRP1), + MTK_PIN(199, "SPI1_CLK", DRV_GRP3), + MTK_PIN(200, "SPDIF_OUT", DRV_GRP1), + MTK_PIN(201, "SPDIF_IN0", DRV_GRP1), + MTK_PIN(202, "SPDIF_IN1", DRV_GRP1), + MTK_PIN(203, "PWM0", DRV_GRP1), + MTK_PIN(204, "PWM1", DRV_GRP1), + MTK_PIN(205, "PWM2", DRV_GRP1), + MTK_PIN(206, "PWM3", DRV_GRP1), + MTK_PIN(207, "PWM4", DRV_GRP1), + MTK_PIN(208, "AUD_EXT_CK1", DRV_GRP1), + MTK_PIN(209, "AUD_EXT_CK2", DRV_GRP1), + MTK_PIN(210, "AUD_CLOCK", DRV_GRP3), + MTK_PIN(211, "DVP_RESET", DRV_GRP3), + MTK_PIN(212, "DVP_CLOCK", DRV_GRP3), + MTK_PIN(213, "DVP_CS", DRV_GRP3), + MTK_PIN(214, "DVP_CK", DRV_GRP3), + MTK_PIN(215, "DVP_DI", DRV_GRP3), + MTK_PIN(216, "DVP_DO", DRV_GRP3), + MTK_PIN(217, "AP_CS", DRV_GRP3), + MTK_PIN(218, "AP_CK", DRV_GRP3), + MTK_PIN(219, "AP_DI", DRV_GRP3), + MTK_PIN(220, "AP_DO", DRV_GRP3), + MTK_PIN(221, "DVD_BCLK", DRV_GRP3), + MTK_PIN(222, "T8032_CLK", DRV_GRP3), + MTK_PIN(223, "AP_BCLK", DRV_GRP3), + MTK_PIN(224, "HOST_CS", DRV_GRP3), + MTK_PIN(225, "HOST_CK", DRV_GRP3), + MTK_PIN(226, "HOST_DO0", DRV_GRP3), + MTK_PIN(227, "HOST_DO1", DRV_GRP3), + MTK_PIN(228, "SLV_CS", DRV_GRP3), + MTK_PIN(229, "SLV_CK", DRV_GRP3), + MTK_PIN(230, "SLV_DI0", DRV_GRP3), + MTK_PIN(231, "SLV_DI1", DRV_GRP3), + MTK_PIN(232, "AP2DSP_INT", DRV_GRP3), + MTK_PIN(233, "AP2DSP_INT_CLR", DRV_GRP3), + MTK_PIN(234, "DSP2AP_INT", DRV_GRP3), + MTK_PIN(235, "DSP2AP_INT_CLR", DRV_GRP3), + MTK_PIN(236, "EXT_SDIO3", DRV_GRP1), + MTK_PIN(237, "EXT_SDIO2", DRV_GRP1), + MTK_PIN(238, "EXT_SDIO1", DRV_GRP1), + MTK_PIN(239, "EXT_SDIO0", DRV_GRP1), + MTK_PIN(240, "EXT_XCS", DRV_GRP1), + MTK_PIN(241, "EXT_SCK", DRV_GRP1), + MTK_PIN(242, "URTS2", DRV_GRP1), + MTK_PIN(243, "UCTS2", DRV_GRP1), + MTK_PIN(244, "HDMI_SDA_RX", DRV_FIXED), + MTK_PIN(245, "HDMI_SCL_RX", DRV_FIXED), + MTK_PIN(246, "MHL_SENCE", DRV_FIXED), + MTK_PIN(247, "HDMI_HPD_CBUS_RX", DRV_FIXED), + MTK_PIN(248, "HDMI_TESTOUTP_RX", DRV_GRP1), + MTK_PIN(249, "MSDC0E_RSTB", DRV_GRP4), + MTK_PIN(250, "MSDC0E_DAT7", DRV_GRP4), + MTK_PIN(251, "MSDC0E_DAT6", DRV_GRP4), + MTK_PIN(252, "MSDC0E_DAT5", DRV_GRP4), + MTK_PIN(253, "MSDC0E_DAT4", DRV_GRP4), + MTK_PIN(254, "MSDC0E_DAT3", DRV_GRP4), + MTK_PIN(255, "MSDC0E_DAT2", DRV_GRP4), + MTK_PIN(256, "MSDC0E_DAT1", DRV_GRP4), + MTK_PIN(257, "MSDC0E_DAT0", DRV_GRP4), + MTK_PIN(258, "MSDC0E_CMD", DRV_GRP4), + MTK_PIN(259, "MSDC0E_CLK", DRV_GRP4), + MTK_PIN(260, "MSDC0E_DSL", DRV_GRP4), + MTK_PIN(261, "MSDC1_INS", DRV_GRP4), + MTK_PIN(262, "G2_TXEN", DRV_GRP1), + MTK_PIN(263, "G2_TXD3", DRV_GRP1), + MTK_PIN(264, "G2_TXD2", DRV_GRP1), + MTK_PIN(265, "G2_TXD1", DRV_GRP1), + MTK_PIN(266, "G2_TXD0", DRV_GRP1), + MTK_PIN(267, "G2_TXC", DRV_GRP1), + MTK_PIN(268, "G2_RXC", DRV_GRP1), + MTK_PIN(269, "G2_RXD0", DRV_GRP1), + MTK_PIN(270, "G2_RXD1", DRV_GRP1), + MTK_PIN(271, "G2_RXD2", DRV_GRP1), + MTK_PIN(272, "G2_RXD3", DRV_GRP1), + MTK_PIN(273, "ESW_INT", DRV_GRP1), + MTK_PIN(274, "G2_RXDV", DRV_GRP1), + MTK_PIN(275, "MDC", DRV_GRP1), + MTK_PIN(276, "MDIO", DRV_GRP1), + MTK_PIN(277, "ESW_RST", DRV_GRP1), + MTK_PIN(278, "JTAG_RESET", DRV_GRP3), + MTK_PIN(279, "USB3_RES_BOND", DRV_GRP1), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +/* AUDIO EXT CLK */ +static int mt7623_aud_ext_clk0_pins[] = { 208, }; +static int mt7623_aud_ext_clk0_funcs[] = { 1, }; +static int mt7623_aud_ext_clk1_pins[] = { 209, }; +static int mt7623_aud_ext_clk1_funcs[] = { 1, }; + +/* DISP PWM */ +static int mt7623_disp_pwm_0_pins[] = { 72, }; +static int mt7623_disp_pwm_0_funcs[] = { 5, }; +static int mt7623_disp_pwm_1_pins[] = { 203, }; +static int mt7623_disp_pwm_1_funcs[] = { 2, }; +static int mt7623_disp_pwm_2_pins[] = { 208, }; +static int mt7623_disp_pwm_2_funcs[] = { 5, }; + +/* ESW */ +static int mt7623_esw_int_pins[] = { 273, }; +static int mt7623_esw_int_funcs[] = { 1, }; +static int mt7623_esw_rst_pins[] = { 277, }; +static int mt7623_esw_rst_funcs[] = { 1, }; + +/* EPHY */ +static int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268, + 269, 270, 271, 272, 274, }; +static int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +/* EXT_SDIO */ +static int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, }; +static int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, }; + +/* HDMI RX */ +static int mt7623_hdmi_rx_pins[] = { 247, 248, }; +static int mt7623_hdmi_rx_funcs[] = { 1, 1 }; +static int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, }; +static int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 }; + +/* HDMI TX */ +static int mt7623_hdmi_cec_pins[] = { 122, }; +static int mt7623_hdmi_cec_funcs[] = { 1, }; +static int mt7623_hdmi_htplg_pins[] = { 123, }; +static int mt7623_hdmi_htplg_funcs[] = { 1, }; +static int mt7623_hdmi_i2c_pins[] = { 124, 125, }; +static int mt7623_hdmi_i2c_funcs[] = { 1, 1 }; + +/* I2C */ +static int mt7623_i2c0_pins[] = { 75, 76, }; +static int mt7623_i2c0_funcs[] = { 1, 1, }; +static int mt7623_i2c1_0_pins[] = { 57, 58, }; +static int mt7623_i2c1_0_funcs[] = { 1, 1, }; +static int mt7623_i2c1_1_pins[] = { 242, 243, }; +static int mt7623_i2c1_1_funcs[] = { 4, 4, }; +static int mt7623_i2c1_2_pins[] = { 85, 86, }; +static int mt7623_i2c1_2_funcs[] = { 3, 3, }; +static int mt7623_i2c1_3_pins[] = { 105, 106, }; +static int mt7623_i2c1_3_funcs[] = { 3, 3, }; +static int mt7623_i2c1_4_pins[] = { 124, 125, }; +static int mt7623_i2c1_4_funcs[] = { 4, 4, }; +static int mt7623_i2c2_0_pins[] = { 77, 78, }; +static int mt7623_i2c2_0_funcs[] = { 1, 1, }; +static int mt7623_i2c2_1_pins[] = { 89, 90, }; +static int mt7623_i2c2_1_funcs[] = { 3, 3, }; +static int mt7623_i2c2_2_pins[] = { 109, 110, }; +static int mt7623_i2c2_2_funcs[] = { 3, 3, }; +static int mt7623_i2c2_3_pins[] = { 122, 123, }; +static int mt7623_i2c2_3_funcs[] = { 4, 4, }; + +/* I2S */ +static int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, }; +static int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, }; +static int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, }; +static int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, }; +static int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, }; +static int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; +static int mt7623_i2s2_data_in_pins[] = { 51, }; +static int mt7623_i2s2_data_in_funcs[] = { 1, }; +static int mt7623_i2s2_data_0_pins[] = { 203, }; +static int mt7623_i2s2_data_0_funcs[] = { 9, }; +static int mt7623_i2s2_data_1_pins[] = { 38, }; +static int mt7623_i2s2_data_1_funcs[] = { 4, }; +static int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, }; +static int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; +static int mt7623_i2s3_data_in_pins[] = { 190, }; +static int mt7623_i2s3_data_in_funcs[] = { 1, }; +static int mt7623_i2s3_data_0_pins[] = { 204, }; +static int mt7623_i2s3_data_0_funcs[] = { 9, }; +static int mt7623_i2s3_data_1_pins[] = { 2, }; +static int mt7623_i2s3_data_1_funcs[] = { 0, }; +static int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, }; +static int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, }; +static int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, }; +static int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, }; + +/* IR */ +static int mt7623_ir_pins[] = { 46, }; +static int mt7623_ir_funcs[] = { 1, }; + +/* LCD */ +static int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98, + 99, 100, }; +static int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +static int mt7623_dsi_te_pins[] = { 84, }; +static int mt7623_dsi_te_funcs[] = { 1, }; +static int mt7623_lcm_rst_pins[] = { 83, }; +static int mt7623_lcm_rst_funcs[] = { 1, }; + +/* MDC/MDIO */ +static int mt7623_mdc_mdio_pins[] = { 275, 276, }; +static int mt7623_mdc_mdio_funcs[] = { 1, 1, }; + +/* MSDC */ +static int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118, + 119, 120, 121, }; +static int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +static int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, }; +static int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, }; +static int mt7623_msdc1_ins_pins[] = { 261, }; +static int mt7623_msdc1_ins_funcs[] = { 1, }; +static int mt7623_msdc1_wp_0_pins[] = { 29, }; +static int mt7623_msdc1_wp_0_funcs[] = { 1, }; +static int mt7623_msdc1_wp_1_pins[] = { 55, }; +static int mt7623_msdc1_wp_1_funcs[] = { 3, }; +static int mt7623_msdc1_wp_2_pins[] = { 209, }; +static int mt7623_msdc1_wp_2_funcs[] = { 2, }; +static int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, }; +static int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, }; +static int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256, + 257, 258, 259, 260, }; +static int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +/* NAND */ +static int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115, + 116, 117, 118, 119, 120, 121, }; +static int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4, + 4, 4, }; +static int mt7623_nandc_ceb0_pins[] = { 45, }; +static int mt7623_nandc_ceb0_funcs[] = { 1, }; +static int mt7623_nandc_ceb1_pins[] = { 44, }; +static int mt7623_nandc_ceb1_funcs[] = { 1, }; + +/* RTC */ +static int mt7623_rtc_pins[] = { 10, }; +static int mt7623_rtc_funcs[] = { 1, }; + +/* OTG */ +static int mt7623_otg_iddig0_0_pins[] = { 29, }; +static int mt7623_otg_iddig0_0_funcs[] = { 1, }; +static int mt7623_otg_iddig0_1_pins[] = { 44, }; +static int mt7623_otg_iddig0_1_funcs[] = { 2, }; +static int mt7623_otg_iddig0_2_pins[] = { 236, }; +static int mt7623_otg_iddig0_2_funcs[] = { 2, }; +static int mt7623_otg_iddig1_0_pins[] = { 27, }; +static int mt7623_otg_iddig1_0_funcs[] = { 2, }; +static int mt7623_otg_iddig1_1_pins[] = { 47, }; +static int mt7623_otg_iddig1_1_funcs[] = { 2, }; +static int mt7623_otg_iddig1_2_pins[] = { 238, }; +static int mt7623_otg_iddig1_2_funcs[] = { 2, }; +static int mt7623_otg_drv_vbus0_0_pins[] = { 28, }; +static int mt7623_otg_drv_vbus0_0_funcs[] = { 1, }; +static int mt7623_otg_drv_vbus0_1_pins[] = { 45, }; +static int mt7623_otg_drv_vbus0_1_funcs[] = { 2, }; +static int mt7623_otg_drv_vbus0_2_pins[] = { 237, }; +static int mt7623_otg_drv_vbus0_2_funcs[] = { 2, }; +static int mt7623_otg_drv_vbus1_0_pins[] = { 26, }; +static int mt7623_otg_drv_vbus1_0_funcs[] = { 2, }; +static int mt7623_otg_drv_vbus1_1_pins[] = { 48, }; +static int mt7623_otg_drv_vbus1_1_funcs[] = { 2, }; +static int mt7623_otg_drv_vbus1_2_pins[] = { 239, }; +static int mt7623_otg_drv_vbus1_2_funcs[] = { 2, }; + +/* PCIE */ +static int mt7623_pcie0_0_perst_pins[] = { 208, }; +static int mt7623_pcie0_0_perst_funcs[] = { 3, }; +static int mt7623_pcie0_1_perst_pins[] = { 22, }; +static int mt7623_pcie0_1_perst_funcs[] = { 2, }; +static int mt7623_pcie1_0_perst_pins[] = { 209, }; +static int mt7623_pcie1_0_perst_funcs[] = { 3, }; +static int mt7623_pcie1_1_perst_pins[] = { 23, }; +static int mt7623_pcie1_1_perst_funcs[] = { 2, }; +static int mt7623_pcie2_0_perst_pins[] = { 24, }; +static int mt7623_pcie2_0_perst_funcs[] = { 2, }; +static int mt7623_pcie2_1_perst_pins[] = { 29, }; +static int mt7623_pcie2_1_perst_funcs[] = { 6, }; +static int mt7623_pcie0_0_wake_pins[] = { 28, }; +static int mt7623_pcie0_0_wake_funcs[] = { 6, }; +static int mt7623_pcie0_1_wake_pins[] = { 251, }; +static int mt7623_pcie0_1_wake_funcs[] = { 6, }; +static int mt7623_pcie1_0_wake_pins[] = { 27, }; +static int mt7623_pcie1_0_wake_funcs[] = { 6, }; +static int mt7623_pcie1_1_wake_pins[] = { 253, }; +static int mt7623_pcie1_1_wake_funcs[] = { 6, }; +static int mt7623_pcie2_0_wake_pins[] = { 26, }; +static int mt7623_pcie2_0_wake_funcs[] = { 6, }; +static int mt7623_pcie2_1_wake_pins[] = { 255, }; +static int mt7623_pcie2_1_wake_funcs[] = { 6, }; +static int mt7623_pcie0_clkreq_pins[] = { 250, }; +static int mt7623_pcie0_clkreq_funcs[] = { 6, }; +static int mt7623_pcie1_clkreq_pins[] = { 252, }; +static int mt7623_pcie1_clkreq_funcs[] = { 6, }; +static int mt7623_pcie2_clkreq_pins[] = { 254, }; +static int mt7623_pcie2_clkreq_funcs[] = { 6, }; +/* the pcie_*_rev are only used for MT7623 */ +static int mt7623_pcie0_0_rev_perst_pins[] = { 208, }; +static int mt7623_pcie0_0_rev_perst_funcs[] = { 11, }; +static int mt7623_pcie0_1_rev_perst_pins[] = { 22, }; +static int mt7623_pcie0_1_rev_perst_funcs[] = { 10, }; +static int mt7623_pcie1_0_rev_perst_pins[] = { 209, }; +static int mt7623_pcie1_0_rev_perst_funcs[] = { 11, }; +static int mt7623_pcie1_1_rev_perst_pins[] = { 23, }; +static int mt7623_pcie1_1_rev_perst_funcs[] = { 10, }; +static int mt7623_pcie2_0_rev_perst_pins[] = { 24, }; +static int mt7623_pcie2_0_rev_perst_funcs[] = { 11, }; +static int mt7623_pcie2_1_rev_perst_pins[] = { 29, }; +static int mt7623_pcie2_1_rev_perst_funcs[] = { 14, }; + +/* PCM */ +static int mt7623_pcm_clk_0_pins[] = { 18, }; +static int mt7623_pcm_clk_0_funcs[] = { 1, }; +static int mt7623_pcm_clk_1_pins[] = { 17, }; +static int mt7623_pcm_clk_1_funcs[] = { 3, }; +static int mt7623_pcm_clk_2_pins[] = { 35, }; +static int mt7623_pcm_clk_2_funcs[] = { 3, }; +static int mt7623_pcm_clk_3_pins[] = { 50, }; +static int mt7623_pcm_clk_3_funcs[] = { 3, }; +static int mt7623_pcm_clk_4_pins[] = { 74, }; +static int mt7623_pcm_clk_4_funcs[] = { 3, }; +static int mt7623_pcm_clk_5_pins[] = { 191, }; +static int mt7623_pcm_clk_5_funcs[] = { 3, }; +static int mt7623_pcm_clk_6_pins[] = { 196, }; +static int mt7623_pcm_clk_6_funcs[] = { 3, }; +static int mt7623_pcm_sync_0_pins[] = { 19, }; +static int mt7623_pcm_sync_0_funcs[] = { 1, }; +static int mt7623_pcm_sync_1_pins[] = { 30, }; +static int mt7623_pcm_sync_1_funcs[] = { 3, }; +static int mt7623_pcm_sync_2_pins[] = { 36, }; +static int mt7623_pcm_sync_2_funcs[] = { 3, }; +static int mt7623_pcm_sync_3_pins[] = { 52, }; +static int mt7623_pcm_sync_3_funcs[] = { 31, }; +static int mt7623_pcm_sync_4_pins[] = { 73, }; +static int mt7623_pcm_sync_4_funcs[] = { 3, }; +static int mt7623_pcm_sync_5_pins[] = { 192, }; +static int mt7623_pcm_sync_5_funcs[] = { 3, }; +static int mt7623_pcm_sync_6_pins[] = { 197, }; +static int mt7623_pcm_sync_6_funcs[] = { 3, }; +static int mt7623_pcm_rx_0_pins[] = { 20, }; +static int mt7623_pcm_rx_0_funcs[] = { 1, }; +static int mt7623_pcm_rx_1_pins[] = { 16, }; +static int mt7623_pcm_rx_1_funcs[] = { 3, }; +static int mt7623_pcm_rx_2_pins[] = { 34, }; +static int mt7623_pcm_rx_2_funcs[] = { 3, }; +static int mt7623_pcm_rx_3_pins[] = { 51, }; +static int mt7623_pcm_rx_3_funcs[] = { 3, }; +static int mt7623_pcm_rx_4_pins[] = { 72, }; +static int mt7623_pcm_rx_4_funcs[] = { 3, }; +static int mt7623_pcm_rx_5_pins[] = { 190, }; +static int mt7623_pcm_rx_5_funcs[] = { 3, }; +static int mt7623_pcm_rx_6_pins[] = { 195, }; +static int mt7623_pcm_rx_6_funcs[] = { 3, }; +static int mt7623_pcm_tx_0_pins[] = { 21, }; +static int mt7623_pcm_tx_0_funcs[] = { 1, }; +static int mt7623_pcm_tx_1_pins[] = { 32, }; +static int mt7623_pcm_tx_1_funcs[] = { 3, }; +static int mt7623_pcm_tx_2_pins[] = { 33, }; +static int mt7623_pcm_tx_2_funcs[] = { 3, }; +static int mt7623_pcm_tx_3_pins[] = { 38, }; +static int mt7623_pcm_tx_3_funcs[] = { 3, }; +static int mt7623_pcm_tx_4_pins[] = { 49, }; +static int mt7623_pcm_tx_4_funcs[] = { 3, }; +static int mt7623_pcm_tx_5_pins[] = { 189, }; +static int mt7623_pcm_tx_5_funcs[] = { 3, }; +static int mt7623_pcm_tx_6_pins[] = { 194, }; +static int mt7623_pcm_tx_6_funcs[] = { 3, }; + +/* PWM */ +static int mt7623_pwm_ch1_0_pins[] = { 203, }; +static int mt7623_pwm_ch1_0_funcs[] = { 1, }; +static int mt7623_pwm_ch1_1_pins[] = { 208, }; +static int mt7623_pwm_ch1_1_funcs[] = { 2, }; +static int mt7623_pwm_ch1_2_pins[] = { 72, }; +static int mt7623_pwm_ch1_2_funcs[] = { 4, }; +static int mt7623_pwm_ch1_3_pins[] = { 88, }; +static int mt7623_pwm_ch1_3_funcs[] = { 3, }; +static int mt7623_pwm_ch1_4_pins[] = { 108, }; +static int mt7623_pwm_ch1_4_funcs[] = { 3, }; +static int mt7623_pwm_ch2_0_pins[] = { 204, }; +static int mt7623_pwm_ch2_0_funcs[] = { 1, }; +static int mt7623_pwm_ch2_1_pins[] = { 53, }; +static int mt7623_pwm_ch2_1_funcs[] = { 5, }; +static int mt7623_pwm_ch2_2_pins[] = { 88, }; +static int mt7623_pwm_ch2_2_funcs[] = { 6, }; +static int mt7623_pwm_ch2_3_pins[] = { 108, }; +static int mt7623_pwm_ch2_3_funcs[] = { 6, }; +static int mt7623_pwm_ch2_4_pins[] = { 209, }; +static int mt7623_pwm_ch2_4_funcs[] = { 5, }; +static int mt7623_pwm_ch3_0_pins[] = { 205, }; +static int mt7623_pwm_ch3_0_funcs[] = { 1, }; +static int mt7623_pwm_ch3_1_pins[] = { 55, }; +static int mt7623_pwm_ch3_1_funcs[] = { 5, }; +static int mt7623_pwm_ch3_2_pins[] = { 89, }; +static int mt7623_pwm_ch3_2_funcs[] = { 6, }; +static int mt7623_pwm_ch3_3_pins[] = { 109, }; +static int mt7623_pwm_ch3_3_funcs[] = { 6, }; +static int mt7623_pwm_ch4_0_pins[] = { 206, }; +static int mt7623_pwm_ch4_0_funcs[] = { 1, }; +static int mt7623_pwm_ch4_1_pins[] = { 90, }; +static int mt7623_pwm_ch4_1_funcs[] = { 6, }; +static int mt7623_pwm_ch4_2_pins[] = { 110, }; +static int mt7623_pwm_ch4_2_funcs[] = { 6, }; +static int mt7623_pwm_ch4_3_pins[] = { 124, }; +static int mt7623_pwm_ch4_3_funcs[] = { 5, }; +static int mt7623_pwm_ch5_0_pins[] = { 207, }; +static int mt7623_pwm_ch5_0_funcs[] = { 1, }; +static int mt7623_pwm_ch5_1_pins[] = { 125, }; +static int mt7623_pwm_ch5_1_funcs[] = { 5, }; + +/* PWRAP */ +static int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, }; +static int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; + +/* SPDIF */ +static int mt7623_spdif_in0_0_pins[] = { 56, }; +static int mt7623_spdif_in0_0_funcs[] = { 3, }; +static int mt7623_spdif_in0_1_pins[] = { 201, }; +static int mt7623_spdif_in0_1_funcs[] = { 1, }; +static int mt7623_spdif_in1_0_pins[] = { 54, }; +static int mt7623_spdif_in1_0_funcs[] = { 3, }; +static int mt7623_spdif_in1_1_pins[] = { 202, }; +static int mt7623_spdif_in1_1_funcs[] = { 1, }; +static int mt7623_spdif_out_pins[] = { 202, }; +static int mt7623_spdif_out_funcs[] = { 1, }; + +/* SPI */ +static int mt7623_spi0_pins[] = { 53, 54, 55, 56, }; +static int mt7623_spi0_funcs[] = { 1, 1, 1, 1, }; +static int mt7623_spi1_pins[] = { 7, 199, 8, 9, }; +static int mt7623_spi1_funcs[] = { 1, 1, 1, 1, }; +static int mt7623_spi2_pins[] = { 101, 104, 102, 103, }; +static int mt7623_spi2_funcs[] = { 1, 1, 1, 1, }; + +/* UART */ +static int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, }; +static int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, }; +static int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, }; +static int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, }; +static int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, }; +static int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, }; +static int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, }; +static int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, }; +static int mt7623_uart0_rts_cts_pins[] = { 22, 23, }; +static int mt7623_uart0_rts_cts_funcs[] = { 1, 1, }; +static int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, }; +static int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, }; +static int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, }; +static int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, }; +static int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, }; +static int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, }; +static int mt7623_uart1_rts_cts_pins[] = { 24, 25, }; +static int mt7623_uart1_rts_cts_funcs[] = { 1, 1, }; +static int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, }; +static int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, }; +static int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, }; +static int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, }; +static int mt7623_uart2_rts_cts_pins[] = { 242, 243, }; +static int mt7623_uart2_rts_cts_funcs[] = { 1, 1, }; +static int mt7623_uart3_txd_rxd_pins[] = { 242, 243, }; +static int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, }; +static int mt7623_uart3_rts_cts_pins[] = { 26, 27, }; +static int mt7623_uart3_rts_cts_funcs[] = { 1, 1, }; + +/* Watchdog */ +static int mt7623_watchdog_0_pins[] = { 11, }; +static int mt7623_watchdog_0_funcs[] = { 1, }; +static int mt7623_watchdog_1_pins[] = { 121, }; +static int mt7623_watchdog_1_funcs[] = { 5, }; + +static const struct mtk_group_desc mt7623_groups[] = { + PINCTRL_PIN_GROUP("aud_ext_clk0", mt7623_aud_ext_clk0), + PINCTRL_PIN_GROUP("aud_ext_clk1", mt7623_aud_ext_clk1), + PINCTRL_PIN_GROUP("dsi_te", mt7623_dsi_te), + PINCTRL_PIN_GROUP("disp_pwm_0", mt7623_disp_pwm_0), + PINCTRL_PIN_GROUP("disp_pwm_1", mt7623_disp_pwm_1), + PINCTRL_PIN_GROUP("disp_pwm_2", mt7623_disp_pwm_2), + PINCTRL_PIN_GROUP("ephy", mt7623_ephy), + PINCTRL_PIN_GROUP("esw_int", mt7623_esw_int), + PINCTRL_PIN_GROUP("esw_rst", mt7623_esw_rst), + PINCTRL_PIN_GROUP("ext_sdio", mt7623_ext_sdio), + PINCTRL_PIN_GROUP("hdmi_cec", mt7623_hdmi_cec), + PINCTRL_PIN_GROUP("hdmi_htplg", mt7623_hdmi_htplg), + PINCTRL_PIN_GROUP("hdmi_i2c", mt7623_hdmi_i2c), + PINCTRL_PIN_GROUP("hdmi_rx", mt7623_hdmi_rx), + PINCTRL_PIN_GROUP("hdmi_rx_i2c", mt7623_hdmi_rx_i2c), + PINCTRL_PIN_GROUP("i2c0", mt7623_i2c0), + PINCTRL_PIN_GROUP("i2c1_0", mt7623_i2c1_0), + PINCTRL_PIN_GROUP("i2c1_1", mt7623_i2c1_1), + PINCTRL_PIN_GROUP("i2c1_2", mt7623_i2c1_2), + PINCTRL_PIN_GROUP("i2c1_3", mt7623_i2c1_3), + PINCTRL_PIN_GROUP("i2c1_4", mt7623_i2c1_4), + PINCTRL_PIN_GROUP("i2c2_0", mt7623_i2c2_0), + PINCTRL_PIN_GROUP("i2c2_1", mt7623_i2c2_1), + PINCTRL_PIN_GROUP("i2c2_2", mt7623_i2c2_2), + PINCTRL_PIN_GROUP("i2c2_3", mt7623_i2c2_3), + PINCTRL_PIN_GROUP("i2s0", mt7623_i2s0), + PINCTRL_PIN_GROUP("i2s1", mt7623_i2s1), + PINCTRL_PIN_GROUP("i2s4", mt7623_i2s4), + PINCTRL_PIN_GROUP("i2s5", mt7623_i2s5), + PINCTRL_PIN_GROUP("i2s2_bclk_lrclk_mclk", mt7623_i2s2_bclk_lrclk_mclk), + PINCTRL_PIN_GROUP("i2s3_bclk_lrclk_mclk", mt7623_i2s3_bclk_lrclk_mclk), + PINCTRL_PIN_GROUP("i2s2_data_in", mt7623_i2s2_data_in), + PINCTRL_PIN_GROUP("i2s3_data_in", mt7623_i2s3_data_in), + PINCTRL_PIN_GROUP("i2s2_data_0", mt7623_i2s2_data_0), + PINCTRL_PIN_GROUP("i2s2_data_1", mt7623_i2s2_data_1), + PINCTRL_PIN_GROUP("i2s3_data_0", mt7623_i2s3_data_0), + PINCTRL_PIN_GROUP("i2s3_data_1", mt7623_i2s3_data_1), + PINCTRL_PIN_GROUP("ir", mt7623_ir), + PINCTRL_PIN_GROUP("lcm_rst", mt7623_lcm_rst), + PINCTRL_PIN_GROUP("mdc_mdio", mt7623_mdc_mdio), + PINCTRL_PIN_GROUP("mipi_tx", mt7623_mipi_tx), + PINCTRL_PIN_GROUP("msdc0", mt7623_msdc0), + PINCTRL_PIN_GROUP("msdc1", mt7623_msdc1), + PINCTRL_PIN_GROUP("msdc1_ins", mt7623_msdc1_ins), + PINCTRL_PIN_GROUP("msdc1_wp_0", mt7623_msdc1_wp_0), + PINCTRL_PIN_GROUP("msdc1_wp_1", mt7623_msdc1_wp_1), + PINCTRL_PIN_GROUP("msdc1_wp_2", mt7623_msdc1_wp_2), + PINCTRL_PIN_GROUP("msdc2", mt7623_msdc2), + PINCTRL_PIN_GROUP("msdc3", mt7623_msdc3), + PINCTRL_PIN_GROUP("nandc", mt7623_nandc), + PINCTRL_PIN_GROUP("nandc_ceb0", mt7623_nandc_ceb0), + PINCTRL_PIN_GROUP("nandc_ceb1", mt7623_nandc_ceb1), + PINCTRL_PIN_GROUP("otg_iddig0_0", mt7623_otg_iddig0_0), + PINCTRL_PIN_GROUP("otg_iddig0_1", mt7623_otg_iddig0_1), + PINCTRL_PIN_GROUP("otg_iddig0_2", mt7623_otg_iddig0_2), + PINCTRL_PIN_GROUP("otg_iddig1_0", mt7623_otg_iddig1_0), + PINCTRL_PIN_GROUP("otg_iddig1_1", mt7623_otg_iddig1_1), + PINCTRL_PIN_GROUP("otg_iddig1_2", mt7623_otg_iddig1_2), + PINCTRL_PIN_GROUP("otg_drv_vbus0_0", mt7623_otg_drv_vbus0_0), + PINCTRL_PIN_GROUP("otg_drv_vbus0_1", mt7623_otg_drv_vbus0_1), + PINCTRL_PIN_GROUP("otg_drv_vbus0_2", mt7623_otg_drv_vbus0_2), + PINCTRL_PIN_GROUP("otg_drv_vbus1_0", mt7623_otg_drv_vbus1_0), + PINCTRL_PIN_GROUP("otg_drv_vbus1_1", mt7623_otg_drv_vbus1_1), + PINCTRL_PIN_GROUP("otg_drv_vbus1_2", mt7623_otg_drv_vbus1_2), + PINCTRL_PIN_GROUP("pcie0_0_perst", mt7623_pcie0_0_perst), + PINCTRL_PIN_GROUP("pcie0_1_perst", mt7623_pcie0_1_perst), + PINCTRL_PIN_GROUP("pcie1_0_perst", mt7623_pcie1_0_perst), + PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst), + PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst), + PINCTRL_PIN_GROUP("pcie0_0_rev_perst", mt7623_pcie0_0_rev_perst), + PINCTRL_PIN_GROUP("pcie0_1_rev_perst", mt7623_pcie0_1_rev_perst), + PINCTRL_PIN_GROUP("pcie1_0_rev_perst", mt7623_pcie1_0_rev_perst), + PINCTRL_PIN_GROUP("pcie1_1_rev_perst", mt7623_pcie1_1_rev_perst), + PINCTRL_PIN_GROUP("pcie2_0_rev_perst", mt7623_pcie2_0_rev_perst), + PINCTRL_PIN_GROUP("pcie2_1_rev_perst", mt7623_pcie2_1_rev_perst), + PINCTRL_PIN_GROUP("pcie2_0_perst", mt7623_pcie2_0_perst), + PINCTRL_PIN_GROUP("pcie2_1_perst", mt7623_pcie2_1_perst), + PINCTRL_PIN_GROUP("pcie0_0_wake", mt7623_pcie0_0_wake), + PINCTRL_PIN_GROUP("pcie0_1_wake", mt7623_pcie0_1_wake), + PINCTRL_PIN_GROUP("pcie1_0_wake", mt7623_pcie1_0_wake), + PINCTRL_PIN_GROUP("pcie1_1_wake", mt7623_pcie1_1_wake), + PINCTRL_PIN_GROUP("pcie2_0_wake", mt7623_pcie2_0_wake), + PINCTRL_PIN_GROUP("pcie2_1_wake", mt7623_pcie2_1_wake), + PINCTRL_PIN_GROUP("pcie0_clkreq", mt7623_pcie0_clkreq), + PINCTRL_PIN_GROUP("pcie1_clkreq", mt7623_pcie1_clkreq), + PINCTRL_PIN_GROUP("pcie2_clkreq", mt7623_pcie2_clkreq), + PINCTRL_PIN_GROUP("pcm_clk_0", mt7623_pcm_clk_0), + PINCTRL_PIN_GROUP("pcm_clk_1", mt7623_pcm_clk_1), + PINCTRL_PIN_GROUP("pcm_clk_2", mt7623_pcm_clk_2), + PINCTRL_PIN_GROUP("pcm_clk_3", mt7623_pcm_clk_3), + PINCTRL_PIN_GROUP("pcm_clk_4", mt7623_pcm_clk_4), + PINCTRL_PIN_GROUP("pcm_clk_5", mt7623_pcm_clk_5), + PINCTRL_PIN_GROUP("pcm_clk_6", mt7623_pcm_clk_6), + PINCTRL_PIN_GROUP("pcm_sync_0", mt7623_pcm_sync_0), + PINCTRL_PIN_GROUP("pcm_sync_1", mt7623_pcm_sync_1), + PINCTRL_PIN_GROUP("pcm_sync_2", mt7623_pcm_sync_2), + PINCTRL_PIN_GROUP("pcm_sync_3", mt7623_pcm_sync_3), + PINCTRL_PIN_GROUP("pcm_sync_4", mt7623_pcm_sync_4), + PINCTRL_PIN_GROUP("pcm_sync_5", mt7623_pcm_sync_5), + PINCTRL_PIN_GROUP("pcm_sync_6", mt7623_pcm_sync_6), + PINCTRL_PIN_GROUP("pcm_rx_0", mt7623_pcm_rx_0), + PINCTRL_PIN_GROUP("pcm_rx_1", mt7623_pcm_rx_1), + PINCTRL_PIN_GROUP("pcm_rx_2", mt7623_pcm_rx_2), + PINCTRL_PIN_GROUP("pcm_rx_3", mt7623_pcm_rx_3), + PINCTRL_PIN_GROUP("pcm_rx_4", mt7623_pcm_rx_4), + PINCTRL_PIN_GROUP("pcm_rx_5", mt7623_pcm_rx_5), + PINCTRL_PIN_GROUP("pcm_rx_6", mt7623_pcm_rx_6), + PINCTRL_PIN_GROUP("pcm_tx_0", mt7623_pcm_tx_0), + PINCTRL_PIN_GROUP("pcm_tx_1", mt7623_pcm_tx_1), + PINCTRL_PIN_GROUP("pcm_tx_2", mt7623_pcm_tx_2), + PINCTRL_PIN_GROUP("pcm_tx_3", mt7623_pcm_tx_3), + PINCTRL_PIN_GROUP("pcm_tx_4", mt7623_pcm_tx_4), + PINCTRL_PIN_GROUP("pcm_tx_5", mt7623_pcm_tx_5), + PINCTRL_PIN_GROUP("pcm_tx_6", mt7623_pcm_tx_6), + PINCTRL_PIN_GROUP("pwm_ch1_0", mt7623_pwm_ch1_0), + PINCTRL_PIN_GROUP("pwm_ch1_1", mt7623_pwm_ch1_1), + PINCTRL_PIN_GROUP("pwm_ch1_2", mt7623_pwm_ch1_2), + PINCTRL_PIN_GROUP("pwm_ch1_3", mt7623_pwm_ch1_3), + PINCTRL_PIN_GROUP("pwm_ch1_4", mt7623_pwm_ch1_4), + PINCTRL_PIN_GROUP("pwm_ch2_0", mt7623_pwm_ch2_0), + PINCTRL_PIN_GROUP("pwm_ch2_1", mt7623_pwm_ch2_1), + PINCTRL_PIN_GROUP("pwm_ch2_2", mt7623_pwm_ch2_2), + PINCTRL_PIN_GROUP("pwm_ch2_3", mt7623_pwm_ch2_3), + PINCTRL_PIN_GROUP("pwm_ch2_4", mt7623_pwm_ch2_4), + PINCTRL_PIN_GROUP("pwm_ch3_0", mt7623_pwm_ch3_0), + PINCTRL_PIN_GROUP("pwm_ch3_1", mt7623_pwm_ch3_1), + PINCTRL_PIN_GROUP("pwm_ch3_2", mt7623_pwm_ch3_2), + PINCTRL_PIN_GROUP("pwm_ch3_3", mt7623_pwm_ch3_3), + PINCTRL_PIN_GROUP("pwm_ch4_0", mt7623_pwm_ch4_0), + PINCTRL_PIN_GROUP("pwm_ch4_1", mt7623_pwm_ch4_1), + PINCTRL_PIN_GROUP("pwm_ch4_2", mt7623_pwm_ch4_2), + PINCTRL_PIN_GROUP("pwm_ch4_3", mt7623_pwm_ch4_3), + PINCTRL_PIN_GROUP("pwm_ch5_0", mt7623_pwm_ch5_0), + PINCTRL_PIN_GROUP("pwm_ch5_1", mt7623_pwm_ch5_1), + PINCTRL_PIN_GROUP("pwrap", mt7623_pwrap), + PINCTRL_PIN_GROUP("rtc", mt7623_rtc), + PINCTRL_PIN_GROUP("spdif_in0_0", mt7623_spdif_in0_0), + PINCTRL_PIN_GROUP("spdif_in0_1", mt7623_spdif_in0_1), + PINCTRL_PIN_GROUP("spdif_in1_0", mt7623_spdif_in1_0), + PINCTRL_PIN_GROUP("spdif_in1_1", mt7623_spdif_in1_1), + PINCTRL_PIN_GROUP("spdif_out", mt7623_spdif_out), + PINCTRL_PIN_GROUP("spi0", mt7623_spi0), + PINCTRL_PIN_GROUP("spi1", mt7623_spi1), + PINCTRL_PIN_GROUP("spi2", mt7623_spi2), + PINCTRL_PIN_GROUP("uart0_0_txd_rxd", mt7623_uart0_0_txd_rxd), + PINCTRL_PIN_GROUP("uart0_1_txd_rxd", mt7623_uart0_1_txd_rxd), + PINCTRL_PIN_GROUP("uart0_2_txd_rxd", mt7623_uart0_2_txd_rxd), + PINCTRL_PIN_GROUP("uart0_3_txd_rxd", mt7623_uart0_3_txd_rxd), + PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7623_uart1_0_txd_rxd), + PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7623_uart1_1_txd_rxd), + PINCTRL_PIN_GROUP("uart1_2_txd_rxd", mt7623_uart1_2_txd_rxd), + PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7623_uart2_0_txd_rxd), + PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7623_uart2_1_txd_rxd), + PINCTRL_PIN_GROUP("uart3_txd_rxd", mt7623_uart3_txd_rxd), + PINCTRL_PIN_GROUP("uart0_rts_cts", mt7623_uart0_rts_cts), + PINCTRL_PIN_GROUP("uart1_rts_cts", mt7623_uart1_rts_cts), + PINCTRL_PIN_GROUP("uart2_rts_cts", mt7623_uart2_rts_cts), + PINCTRL_PIN_GROUP("uart3_rts_cts", mt7623_uart3_rts_cts), + PINCTRL_PIN_GROUP("watchdog_0", mt7623_watchdog_0), + PINCTRL_PIN_GROUP("watchdog_1", mt7623_watchdog_1), +}; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ + +static const char *const mt7623_aud_clk_groups[] = { "aud_ext_clk0", + "aud_ext_clk1", }; +static const char *const mt7623_disp_pwm_groups[] = { "disp_pwm_0", + "disp_pwm_1", + "disp_pwm_2", }; +static const char *const mt7623_ethernet_groups[] = { "esw_int", "esw_rst", + "ephy", "mdc_mdio", }; +static const char *const mt7623_ext_sdio_groups[] = { "ext_sdio", }; +static const char *const mt7623_hdmi_groups[] = { "hdmi_cec", "hdmi_htplg", + "hdmi_i2c", "hdmi_rx", + "hdmi_rx_i2c", }; +static const char *const mt7623_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1", + "i2c1_2", "i2c1_3", "i2c1_4", + "i2c2_0", "i2c2_1", "i2c2_2", + "i2c2_3", }; +static const char *const mt7623_i2s_groups[] = { "i2s0", "i2s1", + "i2s2_bclk_lrclk_mclk", + "i2s3_bclk_lrclk_mclk", + "i2s4", "i2s5", + "i2s2_data_in", "i2s3_data_in", + "i2s2_data_0", "i2s2_data_1", + "i2s3_data_0", "i2s3_data_1",}; +static const char *const mt7623_ir_groups[] = { "ir", }; +static const char *const mt7623_lcd_groups[] = { "dsi_te", "lcm_rst", + "mipi_tx", }; +static const char *const mt7623_msdc_groups[] = { "msdc0", "msdc1", + "msdc1_ins", "msdc1_wp_0", + "msdc1_wp_1", "msdc1_wp_2", + "msdc2", "msdc3", }; +static const char *const mt7623_nandc_groups[] = { "nandc", "nandc_ceb0", + "nandc_ceb1", }; +static const char *const mt7623_otg_groups[] = { "otg_iddig0_0", + "otg_iddig0_1", + "otg_iddig0_2", + "otg_iddig1_0", + "otg_iddig1_1", + "otg_iddig1_2", + "otg_drv_vbus0_0", + "otg_drv_vbus0_1", + "otg_drv_vbus0_2", + "otg_drv_vbus1_0", + "otg_drv_vbus1_1", + "otg_drv_vbus1_2", }; +static const char *const mt7623_pcie_groups[] = { "pcie0_0_perst", + "pcie0_1_perst", + "pcie1_0_perst", + "pcie1_1_perst", + "pcie2_0_perst", + "pcie2_1_perst", + "pcie0_0_rev_perst", + "pcie0_1_rev_perst", + "pcie1_0_rev_perst", + "pcie1_1_rev_perst", + "pcie2_0_rev_perst", + "pcie2_1_rev_perst", + "pcie0_0_wake", "pcie0_1_wake", + "pcie2_0_wake", "pcie2_1_wake", + "pcie0_clkreq", "pcie1_clkreq", + "pcie2_clkreq", }; +static const char *const mt7623_pcm_groups[] = { "pcm_clk_0", "pcm_clk_1", + "pcm_clk_2", "pcm_clk_3", + "pcm_clk_4", "pcm_clk_5", + "pcm_clk_6", "pcm_sync_0", + "pcm_sync_1", "pcm_sync_2", + "pcm_sync_3", "pcm_sync_4", + "pcm_sync_5", "pcm_sync_6", + "pcm_rx_0", "pcm_rx_1", + "pcm_rx_2", "pcm_rx_3", + "pcm_rx_4", "pcm_rx_5", + "pcm_rx_6", "pcm_tx_0", + "pcm_tx_1", "pcm_tx_2", + "pcm_tx_3", "pcm_tx_4", + "pcm_tx_5", "pcm_tx_6", }; +static const char *const mt7623_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1", + "pwm_ch1_2", "pwm_ch2_0", + "pwm_ch2_1", "pwm_ch2_2", + "pwm_ch3_0", "pwm_ch3_1", + "pwm_ch3_2", "pwm_ch4_0", + "pwm_ch4_1", "pwm_ch4_2", + "pwm_ch4_3", "pwm_ch5_0", + "pwm_ch5_1", "pwm_ch5_2", + "pwm_ch6_0", "pwm_ch6_1", + "pwm_ch6_2", "pwm_ch6_3", + "pwm_ch7_0", "pwm_ch7_1", + "pwm_ch7_2", }; +static const char *const mt7623_pwrap_groups[] = { "pwrap", }; +static const char *const mt7623_rtc_groups[] = { "rtc", }; +static const char *const mt7623_spi_groups[] = { "spi0", "spi2", "spi2", }; +static const char *const mt7623_spdif_groups[] = { "spdif_in0_0", + "spdif_in0_1", "spdif_in1_0", + "spdif_in1_1", "spdif_out", }; +static const char *const mt7623_uart_groups[] = { "uart0_0_txd_rxd", + "uart0_1_txd_rxd", + "uart0_2_txd_rxd", + "uart0_3_txd_rxd", + "uart1_0_txd_rxd", + "uart1_1_txd_rxd", + "uart1_2_txd_rxd", + "uart2_0_txd_rxd", + "uart2_1_txd_rxd", + "uart3_txd_rxd", + "uart0_rts_cts", + "uart1_rts_cts", + "uart2_rts_cts", + "uart3_rts_cts", }; +static const char *const mt7623_wdt_groups[] = { "watchdog_0", "watchdog_1", }; + +static const struct mtk_function_desc mt7623_functions[] = { + {"audck", mt7623_aud_clk_groups, ARRAY_SIZE(mt7623_aud_clk_groups)}, + {"disp", mt7623_disp_pwm_groups, ARRAY_SIZE(mt7623_disp_pwm_groups)}, + {"eth", mt7623_ethernet_groups, ARRAY_SIZE(mt7623_ethernet_groups)}, + {"sdio", mt7623_ext_sdio_groups, ARRAY_SIZE(mt7623_ext_sdio_groups)}, + {"hdmi", mt7623_hdmi_groups, ARRAY_SIZE(mt7623_hdmi_groups)}, + {"i2c", mt7623_i2c_groups, ARRAY_SIZE(mt7623_i2c_groups)}, + {"i2s", mt7623_i2s_groups, ARRAY_SIZE(mt7623_i2s_groups)}, + {"ir", mt7623_ir_groups, ARRAY_SIZE(mt7623_ir_groups)}, + {"lcd", mt7623_lcd_groups, ARRAY_SIZE(mt7623_lcd_groups)}, + {"msdc", mt7623_msdc_groups, ARRAY_SIZE(mt7623_msdc_groups)}, + {"nand", mt7623_nandc_groups, ARRAY_SIZE(mt7623_nandc_groups)}, + {"otg", mt7623_otg_groups, ARRAY_SIZE(mt7623_otg_groups)}, + {"pcie", mt7623_pcie_groups, ARRAY_SIZE(mt7623_pcie_groups)}, + {"pcm", mt7623_pcm_groups, ARRAY_SIZE(mt7623_pcm_groups)}, + {"pwm", mt7623_pwm_groups, ARRAY_SIZE(mt7623_pwm_groups)}, + {"pwrap", mt7623_pwrap_groups, ARRAY_SIZE(mt7623_pwrap_groups)}, + {"rtc", mt7623_rtc_groups, ARRAY_SIZE(mt7623_rtc_groups)}, + {"spi", mt7623_spi_groups, ARRAY_SIZE(mt7623_spi_groups)}, + {"spdif", mt7623_spdif_groups, ARRAY_SIZE(mt7623_spdif_groups)}, + {"uart", mt7623_uart_groups, ARRAY_SIZE(mt7623_uart_groups)}, + {"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)}, +}; + +static struct mtk_pinctrl_soc mt7623_data = { + .name = "mt7623_pinctrl", + .reg_cal = mt7623_reg_cals, + .pins = mt7623_pins, + .npins = ARRAY_SIZE(mt7623_pins), + .grps = mt7623_groups, + .ngrps = ARRAY_SIZE(mt7623_groups), + .funcs = mt7623_functions, + .nfuncs = ARRAY_SIZE(mt7623_functions), + .gpio_mode = 0, + .rev = MTK_PINCTRL_V1, +}; + +/* + * There are some specific pins have mux functions greater than 8, + * and if we want to switch thees high modes we need to disable + * bonding constraints firstly. + */ +static void mt7623_bonding_disable(struct udevice *dev) +{ + mtk_rmw(dev, PIN_BOND_REG0, BOND_PCIE_CLR, BOND_PCIE_CLR); + mtk_rmw(dev, PIN_BOND_REG1, BOND_I2S_CLR, BOND_I2S_CLR); + mtk_rmw(dev, PIN_BOND_REG2, BOND_MSDC0E_CLR, BOND_MSDC0E_CLR); +} + +static int mtk_pinctrl_mt7623_probe(struct udevice *dev) +{ + int err; + + err = mtk_pinctrl_common_probe(dev, &mt7623_data); + if (err) + return err; + + mt7623_bonding_disable(dev); + + return 0; +} + +static const struct udevice_id mt7623_pctrl_match[] = { + { .compatible = "mediatek,mt7623-pinctrl", }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt7623_pinctrl) = { + .name = "mt7623_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt7623_pctrl_match, + .ops = &mtk_pinctrl_ops, + .probe = mtk_pinctrl_mt7623_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt7629.c b/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt7629.c new file mode 100644 index 000000000..5d4bec223 --- /dev/null +++ b/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt7629.c @@ -0,0 +1,418 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + */ + +#include <dm.h> + +#include "pinctrl-mtk-common.h" + +#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, false) + +#define MT7629_PIN(_number, _name) MTK_PIN(_number, _name, DRV_GRP1) + +static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = { + PIN_FIELD(0, 78, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = { + PIN_FIELD(0, 78, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_di_range[] = { + PIN_FIELD(0, 78, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_do_range[] = { + PIN_FIELD(0, 78, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = { + PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1), + PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1), + PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1), + PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1), + PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1), + PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1), + PIN_FIELD(70, 78, 0x7000, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_smt_range[] = { + PIN_FIELD(0, 10, 0x1100, 0x10, 0, 1), + PIN_FIELD(11, 18, 0x2100, 0x10, 0, 1), + PIN_FIELD(19, 32, 0x3100, 0x10, 0, 1), + PIN_FIELD(33, 48, 0x4100, 0x10, 0, 1), + PIN_FIELD(49, 50, 0x5100, 0x10, 0, 1), + PIN_FIELD(51, 69, 0x6100, 0x10, 0, 1), + PIN_FIELD(70, 78, 0x7100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_pullen_range[] = { + PIN_FIELD(0, 10, 0x1400, 0x10, 0, 1), + PIN_FIELD(11, 18, 0x2400, 0x10, 0, 1), + PIN_FIELD(19, 32, 0x3400, 0x10, 0, 1), + PIN_FIELD(33, 48, 0x4400, 0x10, 0, 1), + PIN_FIELD(49, 50, 0x5400, 0x10, 0, 1), + PIN_FIELD(51, 69, 0x6400, 0x10, 0, 1), + PIN_FIELD(70, 78, 0x7400, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_pullsel_range[] = { + PIN_FIELD(0, 10, 0x1500, 0x10, 0, 1), + PIN_FIELD(11, 18, 0x2500, 0x10, 0, 1), + PIN_FIELD(19, 32, 0x3500, 0x10, 0, 1), + PIN_FIELD(33, 48, 0x4500, 0x10, 0, 1), + PIN_FIELD(49, 50, 0x5500, 0x10, 0, 1), + PIN_FIELD(51, 69, 0x6500, 0x10, 0, 1), + PIN_FIELD(70, 78, 0x7500, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_drv_range[] = { + PIN_FIELD(0, 10, 0x1600, 0x10, 0, 4), + PIN_FIELD(11, 18, 0x2600, 0x10, 0, 4), + PIN_FIELD(19, 32, 0x3600, 0x10, 0, 4), + PIN_FIELD(33, 48, 0x4600, 0x10, 0, 4), + PIN_FIELD(49, 50, 0x5600, 0x10, 0, 4), + PIN_FIELD(51, 69, 0x6600, 0x10, 0, 4), + PIN_FIELD(70, 78, 0x7600, 0x10, 0, 4), +}; + +static const struct mtk_pin_reg_calc mt7629_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7629_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7629_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7629_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7629_pin_do_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7629_pin_ies_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7629_pin_smt_range), + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7629_pin_pullsel_range), + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7629_pin_pullen_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7629_pin_drv_range), +}; + +static const struct mtk_pin_desc mt7629_pins[] = { + MT7629_PIN(0, "TOP_5G_CLK"), + MT7629_PIN(1, "TOP_5G_DATA"), + MT7629_PIN(2, "WF0_5G_HB0"), + MT7629_PIN(3, "WF0_5G_HB1"), + MT7629_PIN(4, "WF0_5G_HB2"), + MT7629_PIN(5, "WF0_5G_HB3"), + MT7629_PIN(6, "WF0_5G_HB4"), + MT7629_PIN(7, "WF0_5G_HB5"), + MT7629_PIN(8, "WF0_5G_HB6"), + MT7629_PIN(9, "XO_REQ"), + MT7629_PIN(10, "TOP_RST_N"), + MT7629_PIN(11, "SYS_WATCHDOG"), + MT7629_PIN(12, "EPHY_LED0_N_JTDO"), + MT7629_PIN(13, "EPHY_LED1_N_JTDI"), + MT7629_PIN(14, "EPHY_LED2_N_JTMS"), + MT7629_PIN(15, "EPHY_LED3_N_JTCLK"), + MT7629_PIN(16, "EPHY_LED4_N_JTRST_N"), + MT7629_PIN(17, "WF2G_LED_N"), + MT7629_PIN(18, "WF5G_LED_N"), + MT7629_PIN(19, "I2C_SDA"), + MT7629_PIN(20, "I2C_SCL"), + MT7629_PIN(21, "GPIO_9"), + MT7629_PIN(22, "GPIO_10"), + MT7629_PIN(23, "GPIO_11"), + MT7629_PIN(24, "GPIO_12"), + MT7629_PIN(25, "UART1_TXD"), + MT7629_PIN(26, "UART1_RXD"), + MT7629_PIN(27, "UART1_CTS"), + MT7629_PIN(28, "UART1_RTS"), + MT7629_PIN(29, "UART2_TXD"), + MT7629_PIN(30, "UART2_RXD"), + MT7629_PIN(31, "UART2_CTS"), + MT7629_PIN(32, "UART2_RTS"), + MT7629_PIN(33, "MDI_TP_P1"), + MT7629_PIN(34, "MDI_TN_P1"), + MT7629_PIN(35, "MDI_RP_P1"), + MT7629_PIN(36, "MDI_RN_P1"), + MT7629_PIN(37, "MDI_RP_P2"), + MT7629_PIN(38, "MDI_RN_P2"), + MT7629_PIN(39, "MDI_TP_P2"), + MT7629_PIN(40, "MDI_TN_P2"), + MT7629_PIN(41, "MDI_TP_P3"), + MT7629_PIN(42, "MDI_TN_P3"), + MT7629_PIN(43, "MDI_RP_P3"), + MT7629_PIN(44, "MDI_RN_P3"), + MT7629_PIN(45, "MDI_RP_P4"), + MT7629_PIN(46, "MDI_RN_P4"), + MT7629_PIN(47, "MDI_TP_P4"), + MT7629_PIN(48, "MDI_TN_P4"), + MT7629_PIN(49, "SMI_MDC"), + MT7629_PIN(50, "SMI_MDIO"), + MT7629_PIN(51, "PCIE_PERESET_N"), + MT7629_PIN(52, "PWM_0"), + MT7629_PIN(53, "GPIO_0"), + MT7629_PIN(54, "GPIO_1"), + MT7629_PIN(55, "GPIO_2"), + MT7629_PIN(56, "GPIO_3"), + MT7629_PIN(57, "GPIO_4"), + MT7629_PIN(58, "GPIO_5"), + MT7629_PIN(59, "GPIO_6"), + MT7629_PIN(60, "GPIO_7"), + MT7629_PIN(61, "GPIO_8"), + MT7629_PIN(62, "SPI_CLK"), + MT7629_PIN(63, "SPI_CS"), + MT7629_PIN(64, "SPI_MOSI"), + MT7629_PIN(65, "SPI_MISO"), + MT7629_PIN(66, "SPI_WP"), + MT7629_PIN(67, "SPI_HOLD"), + MT7629_PIN(68, "UART0_TXD"), + MT7629_PIN(69, "UART0_RXD"), + MT7629_PIN(70, "TOP_2G_CLK"), + MT7629_PIN(71, "TOP_2G_DATA"), + MT7629_PIN(72, "WF0_2G_HB0"), + MT7629_PIN(73, "WF0_2G_HB1"), + MT7629_PIN(74, "WF0_2G_HB2"), + MT7629_PIN(75, "WF0_2G_HB3"), + MT7629_PIN(76, "WF0_2G_HB4"), + MT7629_PIN(77, "WF0_2G_HB5"), + MT7629_PIN(78, "WF0_2G_HB6"), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +/* WF 5G */ +static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, }; +static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +/* LED for EPHY */ +static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, }; +static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; +static int mt7629_ephy_led0_pins[] = { 12, }; +static int mt7629_ephy_led0_funcs[] = { 1, }; +static int mt7629_ephy_led1_pins[] = { 13, }; +static int mt7629_ephy_led1_funcs[] = { 1, }; +static int mt7629_ephy_led2_pins[] = { 14, }; +static int mt7629_ephy_led2_funcs[] = { 1, }; +static int mt7629_ephy_led3_pins[] = { 15, }; +static int mt7629_ephy_led3_funcs[] = { 1, }; +static int mt7629_ephy_led4_pins[] = { 16, }; +static int mt7629_ephy_led4_funcs[] = { 1, }; +static int mt7629_wf2g_led_pins[] = { 17, }; +static int mt7629_wf2g_led_funcs[] = { 1, }; +static int mt7629_wf5g_led_pins[] = { 18, }; +static int mt7629_wf5g_led_funcs[] = { 1, }; + +/* LED for EPHY used as JTAG */ +static int mt7629_ephy_leds_jtag_pins[] = { 12, 13, 14, 15, 16, }; +static int mt7629_ephy_leds_jtag_funcs[] = { 7, 7, 7, 7, 7, }; + +/* Watchdog */ +static int mt7629_watchdog_pins[] = { 11, }; +static int mt7629_watchdog_funcs[] = { 1, }; + +/* LED for GPHY */ +static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, }; +static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, }; +static int mt7629_gphy_led1_0_pins[] = { 21, }; +static int mt7629_gphy_led1_0_funcs[] = { 2, }; +static int mt7629_gphy_led2_0_pins[] = { 22, }; +static int mt7629_gphy_led2_0_funcs[] = { 2, }; +static int mt7629_gphy_led3_0_pins[] = { 23, }; +static int mt7629_gphy_led3_0_funcs[] = { 2, }; +static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, }; +static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, }; +static int mt7629_gphy_led1_1_pins[] = { 57, }; +static int mt7629_gphy_led1_1_funcs[] = { 1, }; +static int mt7629_gphy_led2_1_pins[] = { 58, }; +static int mt7629_gphy_led2_1_funcs[] = { 1, }; +static int mt7629_gphy_led3_1_pins[] = { 59, }; +static int mt7629_gphy_led3_1_funcs[] = { 1, }; + +/* I2C */ +static int mt7629_i2c_0_pins[] = { 19, 20, }; +static int mt7629_i2c_0_funcs[] = { 1, 1, }; +static int mt7629_i2c_1_pins[] = { 53, 54, }; +static int mt7629_i2c_1_funcs[] = { 1, 1, }; + +/* SPI */ +static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, }; +static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, }; +static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, }; +static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, }; +static int mt7629_spi_wp_pins[] = { 66, }; +static int mt7629_spi_wp_funcs[] = { 1, }; +static int mt7629_spi_hold_pins[] = { 67, }; +static int mt7629_spi_hold_funcs[] = { 1, }; + +/* UART */ +static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, }; +static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, }; +static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, }; +static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, }; +static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, }; +static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, }; +static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, }; +static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, }; +static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, }; +static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, }; +static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, }; +static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, }; +static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, }; +static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, }; +static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, }; +static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, }; +static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, }; +static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, }; + +/* MDC/MDIO */ +static int mt7629_mdc_mdio_pins[] = { 49, 50, }; +static int mt7629_mdc_mdio_funcs[] = { 1, 1, }; + +/* PCIE */ +static int mt7629_pcie_pereset_pins[] = { 51, }; +static int mt7629_pcie_pereset_funcs[] = { 1, }; +static int mt7629_pcie_wake_pins[] = { 55, }; +static int mt7629_pcie_wake_funcs[] = { 1, }; +static int mt7629_pcie_clkreq_pins[] = { 56, }; +static int mt7629_pcie_clkreq_funcs[] = { 1, }; + +/* PWM */ +static int mt7629_pwm_0_pins[] = { 52, }; +static int mt7629_pwm_0_funcs[] = { 1, }; +static int mt7629_pwm_1_pins[] = { 61, }; +static int mt7629_pwm_1_funcs[] = { 2, }; + +/* WF 2G */ +static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, }; +static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; + +/* SNFI */ +static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 }; +static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; + +/* SPI NOR */ +static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 }; +static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 }; + +static const struct mtk_group_desc mt7629_groups[] = { + PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g), + PINCTRL_PIN_GROUP("ephy_leds", mt7629_ephy_leds), + PINCTRL_PIN_GROUP("ephy_led0", mt7629_ephy_led0), + PINCTRL_PIN_GROUP("ephy_led1", mt7629_ephy_led1), + PINCTRL_PIN_GROUP("ephy_led2", mt7629_ephy_led2), + PINCTRL_PIN_GROUP("ephy_led3", mt7629_ephy_led3), + PINCTRL_PIN_GROUP("ephy_led4", mt7629_ephy_led4), + PINCTRL_PIN_GROUP("ephy_leds_jtag", mt7629_ephy_leds_jtag), + PINCTRL_PIN_GROUP("wf2g_led", mt7629_wf2g_led), + PINCTRL_PIN_GROUP("wf5g_led", mt7629_wf5g_led), + PINCTRL_PIN_GROUP("watchdog", mt7629_watchdog), + PINCTRL_PIN_GROUP("gphy_leds_0", mt7629_gphy_leds_0), + PINCTRL_PIN_GROUP("gphy_led1_0", mt7629_gphy_led1_0), + PINCTRL_PIN_GROUP("gphy_led2_0", mt7629_gphy_led2_0), + PINCTRL_PIN_GROUP("gphy_led3_0", mt7629_gphy_led3_0), + PINCTRL_PIN_GROUP("gphy_leds_1", mt7629_gphy_leds_1), + PINCTRL_PIN_GROUP("gphy_led1_1", mt7629_gphy_led1_1), + PINCTRL_PIN_GROUP("gphy_led2_1", mt7629_gphy_led2_1), + PINCTRL_PIN_GROUP("gphy_led3_1", mt7629_gphy_led3_1), + PINCTRL_PIN_GROUP("i2c_0", mt7629_i2c_0), + PINCTRL_PIN_GROUP("i2c_1", mt7629_i2c_1), + PINCTRL_PIN_GROUP("spi_0", mt7629_spi_0), + PINCTRL_PIN_GROUP("spi_1", mt7629_spi_1), + PINCTRL_PIN_GROUP("spi_wp", mt7629_spi_wp), + PINCTRL_PIN_GROUP("spi_hold", mt7629_spi_hold), + PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7629_uart1_0_txd_rxd), + PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7629_uart1_1_txd_rxd), + PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7629_uart2_0_txd_rxd), + PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7629_uart2_1_txd_rxd), + PINCTRL_PIN_GROUP("uart1_0_cts_rts", mt7629_uart1_0_cts_rts), + PINCTRL_PIN_GROUP("uart1_1_cts_rts", mt7629_uart1_1_cts_rts), + PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7629_uart2_0_cts_rts), + PINCTRL_PIN_GROUP("uart2_1_cts_rts", mt7629_uart2_1_cts_rts), + PINCTRL_PIN_GROUP("uart0_txd_rxd", mt7629_uart0_txd_rxd), + PINCTRL_PIN_GROUP("mdc_mdio", mt7629_mdc_mdio), + PINCTRL_PIN_GROUP("pcie_pereset", mt7629_pcie_pereset), + PINCTRL_PIN_GROUP("pcie_wake", mt7629_pcie_wake), + PINCTRL_PIN_GROUP("pcie_clkreq", mt7629_pcie_clkreq), + PINCTRL_PIN_GROUP("pwm_0", mt7629_pwm_0), + PINCTRL_PIN_GROUP("pwm_1", mt7629_pwm_1), + PINCTRL_PIN_GROUP("wf0_2g", mt7629_wf0_2g), + PINCTRL_PIN_GROUP("snfi", mt7629_snfi), + PINCTRL_PIN_GROUP("spi_nor", mt7629_snor), +}; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ +static const char *const mt7629_ethernet_groups[] = { "mdc_mdio", }; +static const char *const mt7629_i2c_groups[] = { "i2c_0", "i2c_1", }; +static const char *const mt7629_led_groups[] = { "ephy_leds", "ephy_led0", + "ephy_led1", "ephy_led2", + "ephy_led3", "ephy_led4", + "wf2g_led", "wf5g_led", + "gphy_leds_0", "gphy_led1_0", + "gphy_led2_0", "gphy_led3_0", + "gphy_leds_1", "gphy_led1_1", + "gphy_led2_1", "gphy_led3_1",}; +static const char *const mt7629_pcie_groups[] = { "pcie_pereset", "pcie_wake", + "pcie_clkreq", }; +static const char *const mt7629_pwm_groups[] = { "pwm_0", "pwm_1", }; +static const char *const mt7629_spi_groups[] = { "spi_0", "spi_1", "spi_wp", + "spi_hold", }; +static const char *const mt7629_uart_groups[] = { "uart1_0_txd_rxd", + "uart1_1_txd_rxd", + "uart2_0_txd_rxd", + "uart2_1_txd_rxd", + "uart1_0_cts_rts", + "uart1_1_cts_rts", + "uart2_0_cts_rts", + "uart2_1_cts_rts", + "uart0_txd_rxd", }; +static const char *const mt7629_wdt_groups[] = { "watchdog", }; +static const char *const mt7629_wifi_groups[] = { "wf0_5g", "wf0_2g", }; +static const char *const mt7629_flash_groups[] = { "snfi", "spi_nor" }; +static const char *const mt7629_jtag_groups[] = { "ephy_leds_jtag" }; + +static const struct mtk_function_desc mt7629_functions[] = { + {"eth", mt7629_ethernet_groups, ARRAY_SIZE(mt7629_ethernet_groups)}, + {"i2c", mt7629_i2c_groups, ARRAY_SIZE(mt7629_i2c_groups)}, + {"led", mt7629_led_groups, ARRAY_SIZE(mt7629_led_groups)}, + {"pcie", mt7629_pcie_groups, ARRAY_SIZE(mt7629_pcie_groups)}, + {"pwm", mt7629_pwm_groups, ARRAY_SIZE(mt7629_pwm_groups)}, + {"spi", mt7629_spi_groups, ARRAY_SIZE(mt7629_spi_groups)}, + {"uart", mt7629_uart_groups, ARRAY_SIZE(mt7629_uart_groups)}, + {"watchdog", mt7629_wdt_groups, ARRAY_SIZE(mt7629_wdt_groups)}, + {"wifi", mt7629_wifi_groups, ARRAY_SIZE(mt7629_wifi_groups)}, + {"flash", mt7629_flash_groups, ARRAY_SIZE(mt7629_flash_groups)}, + {"jtag", mt7629_jtag_groups, ARRAY_SIZE(mt7629_jtag_groups)}, +}; + +static struct mtk_pinctrl_soc mt7629_data = { + .name = "mt7629_pinctrl", + .reg_cal = mt7629_reg_cals, + .pins = mt7629_pins, + .npins = ARRAY_SIZE(mt7629_pins), + .grps = mt7629_groups, + .ngrps = ARRAY_SIZE(mt7629_groups), + .funcs = mt7629_functions, + .nfuncs = ARRAY_SIZE(mt7629_functions), + .gpio_mode = 0, + .rev = MTK_PINCTRL_V1, +}; + +static int mtk_pinctrl_mt7629_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt7629_data); +} + +static const struct udevice_id mt7629_pctrl_match[] = { + { .compatible = "mediatek,mt7629-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt7629_pinctrl) = { + .name = "mt7629_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt7629_pctrl_match, + .ops = &mtk_pinctrl_ops, + .probe = mtk_pinctrl_mt7629_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt8512.c b/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt8512.c new file mode 100644 index 000000000..3d9c0abe3 --- /dev/null +++ b/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt8512.c @@ -0,0 +1,387 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + */ + +#include <dm.h> + +#include "pinctrl-mtk-common.h" + +#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, false) +#define PIN_FIELDS(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, true) +#define PIN_FIELD30(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 30, false) + +static const struct mtk_pin_field_calc mt8512_pin_mode_range[] = { + PIN_FIELD30(0, 115, 0x1E0, 0x10, 0, 3), +}; + +static const struct mtk_pin_field_calc mt8512_pin_dir_range[] = { + PIN_FIELD(0, 115, 0x140, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_di_range[] = { + PIN_FIELD(0, 115, 0x000, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_do_range[] = { + PIN_FIELD(0, 115, 0x0A0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_pullen_range[] = { + PIN_FIELD(0, 115, 0x860, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_pullsel_range[] = { + PIN_FIELD(0, 115, 0x900, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_ies_range[] = { + PIN_FIELDS(0, 2, 0x410, 0x10, 0, 1), + PIN_FIELDS(3, 5, 0x410, 0x10, 1, 1), + PIN_FIELDS(6, 7, 0x410, 0x10, 2, 1), + PIN_FIELDS(8, 11, 0x410, 0x10, 3, 1), + PIN_FIELDS(12, 15, 0x410, 0x10, 4, 1), + PIN_FIELDS(16, 19, 0x410, 0x10, 5, 1), + PIN_FIELD(20, 20, 0x410, 0x10, 6, 1), + PIN_FIELDS(21, 25, 0x410, 0x10, 7, 1), + PIN_FIELDS(26, 27, 0x410, 0x10, 8, 1), + PIN_FIELDS(28, 31, 0x410, 0x10, 9, 1), + PIN_FIELD(32, 32, 0x410, 0x10, 10, 1), + PIN_FIELDS(33, 39, 0x410, 0x10, 11, 1), + PIN_FIELD(40, 40, 0x410, 0x10, 12, 1), + PIN_FIELDS(41, 43, 0x410, 0x10, 13, 1), + PIN_FIELDS(44, 47, 0x410, 0x10, 14, 1), + PIN_FIELDS(48, 51, 0x410, 0x10, 15, 1), + PIN_FIELDS(52, 53, 0x410, 0x10, 16, 1), + PIN_FIELDS(54, 57, 0x410, 0x10, 17, 1), + PIN_FIELDS(58, 63, 0x410, 0x10, 18, 1), + PIN_FIELDS(64, 65, 0x410, 0x10, 19, 1), + PIN_FIELDS(66, 67, 0x410, 0x10, 20, 1), + PIN_FIELDS(68, 69, 0x410, 0x10, 21, 1), + PIN_FIELD(70, 70, 0x410, 0x10, 22, 1), + PIN_FIELD(71, 71, 0x410, 0x10, 23, 1), + PIN_FIELD(72, 72, 0x410, 0x10, 24, 1), + PIN_FIELD(73, 73, 0x410, 0x10, 25, 1), + PIN_FIELD(74, 74, 0x410, 0x10, 26, 1), + PIN_FIELD(75, 75, 0x410, 0x10, 27, 1), + PIN_FIELD(76, 76, 0x410, 0x10, 28, 1), + PIN_FIELD(77, 77, 0x410, 0x10, 29, 1), + PIN_FIELD(78, 78, 0x410, 0x10, 30, 1), + PIN_FIELD(79, 79, 0x410, 0x10, 31, 1), + PIN_FIELD(80, 80, 0x420, 0x10, 0, 1), + PIN_FIELD(81, 81, 0x420, 0x10, 1, 1), + PIN_FIELD(82, 82, 0x420, 0x10, 2, 1), + PIN_FIELD(83, 83, 0x420, 0x10, 3, 1), + PIN_FIELD(84, 84, 0x420, 0x10, 4, 1), + PIN_FIELDS(85, 86, 0x420, 0x10, 5, 1), + PIN_FIELD(87, 87, 0x420, 0x10, 6, 1), + PIN_FIELDS(88, 91, 0x420, 0x10, 7, 1), + PIN_FIELDS(92, 98, 0x420, 0x10, 8, 1), + PIN_FIELDS(99, 101, 0x420, 0x10, 9, 1), + PIN_FIELDS(102, 104, 0x420, 0x10, 10, 1), + PIN_FIELDS(105, 111, 0x420, 0x10, 11, 1), + PIN_FIELDS(112, 115, 0x420, 0x10, 12, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_smt_range[] = { + PIN_FIELDS(0, 2, 0x470, 0x10, 0, 1), + PIN_FIELDS(3, 5, 0x470, 0x10, 1, 1), + PIN_FIELDS(6, 7, 0x470, 0x10, 2, 1), + PIN_FIELDS(8, 11, 0x470, 0x10, 3, 1), + PIN_FIELDS(12, 15, 0x470, 0x10, 4, 1), + PIN_FIELDS(16, 19, 0x470, 0x10, 5, 1), + PIN_FIELD(20, 20, 0x470, 0x10, 6, 1), + PIN_FIELDS(21, 25, 0x470, 0x10, 7, 1), + PIN_FIELDS(26, 27, 0x470, 0x10, 8, 1), + PIN_FIELDS(28, 31, 0x470, 0x10, 9, 1), + PIN_FIELD(32, 32, 0x470, 0x10, 10, 1), + PIN_FIELDS(33, 39, 0x470, 0x10, 11, 1), + PIN_FIELD(40, 40, 0x470, 0x10, 12, 1), + PIN_FIELDS(41, 43, 0x470, 0x10, 13, 1), + PIN_FIELDS(44, 47, 0x470, 0x10, 14, 1), + PIN_FIELDS(48, 51, 0x470, 0x10, 15, 1), + PIN_FIELDS(52, 53, 0x470, 0x10, 16, 1), + PIN_FIELDS(54, 57, 0x470, 0x10, 17, 1), + PIN_FIELDS(58, 63, 0x470, 0x10, 18, 1), + PIN_FIELDS(64, 65, 0x470, 0x10, 19, 1), + PIN_FIELDS(66, 67, 0x470, 0x10, 20, 1), + PIN_FIELDS(68, 69, 0x470, 0x10, 21, 1), + PIN_FIELD(70, 70, 0x470, 0x10, 22, 1), + PIN_FIELD(71, 71, 0x470, 0x10, 23, 1), + PIN_FIELD(72, 72, 0x470, 0x10, 24, 1), + PIN_FIELD(73, 73, 0x470, 0x10, 25, 1), + PIN_FIELD(74, 74, 0x470, 0x10, 26, 1), + PIN_FIELD(75, 75, 0x470, 0x10, 27, 1), + PIN_FIELD(76, 76, 0x470, 0x10, 28, 1), + PIN_FIELD(77, 77, 0x470, 0x10, 29, 1), + PIN_FIELD(78, 78, 0x470, 0x10, 30, 1), + PIN_FIELD(79, 79, 0x470, 0x10, 31, 1), + PIN_FIELD(80, 80, 0x480, 0x10, 0, 1), + PIN_FIELD(81, 81, 0x480, 0x10, 1, 1), + PIN_FIELD(82, 82, 0x480, 0x10, 2, 1), + PIN_FIELD(83, 83, 0x480, 0x10, 3, 1), + PIN_FIELD(84, 84, 0x480, 0x10, 4, 1), + PIN_FIELDS(85, 86, 0x480, 0x10, 5, 1), + PIN_FIELD(87, 87, 0x480, 0x10, 6, 1), + PIN_FIELDS(88, 91, 0x480, 0x10, 7, 1), + PIN_FIELDS(92, 98, 0x480, 0x10, 8, 1), + PIN_FIELDS(99, 101, 0x480, 0x10, 9, 1), + PIN_FIELDS(102, 104, 0x480, 0x10, 10, 1), + PIN_FIELDS(105, 111, 0x480, 0x10, 11, 1), + PIN_FIELDS(112, 115, 0x480, 0x10, 12, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_drv_range[] = { + PIN_FIELDS(0, 2, 0x710, 0x10, 0, 4), + PIN_FIELDS(3, 5, 0x710, 0x10, 4, 4), + PIN_FIELDS(6, 7, 0x710, 0x10, 8, 4), + PIN_FIELDS(8, 11, 0x710, 0x10, 12, 4), + PIN_FIELDS(12, 15, 0x710, 0x10, 16, 4), + PIN_FIELDS(16, 19, 0x710, 0x10, 20, 4), + PIN_FIELD(20, 20, 0x710, 0x10, 24, 4), + PIN_FIELDS(21, 25, 0x710, 0x10, 28, 4), + PIN_FIELDS(26, 27, 0x720, 0x10, 0, 4), + PIN_FIELDS(28, 31, 0x720, 0x10, 4, 4), + PIN_FIELD(32, 32, 0x720, 0x10, 8, 4), + PIN_FIELDS(33, 39, 0x720, 0x10, 12, 4), + PIN_FIELD(40, 40, 0x720, 0x10, 16, 4), + PIN_FIELDS(41, 43, 0x720, 0x10, 20, 4), + PIN_FIELDS(44, 47, 0x720, 0x10, 24, 4), + PIN_FIELDS(48, 51, 0x720, 0x10, 28, 4), + PIN_FIELDS(52, 53, 0x730, 0x10, 0, 4), + PIN_FIELDS(54, 57, 0x730, 0x10, 4, 4), + PIN_FIELDS(58, 63, 0x730, 0x10, 8, 4), + PIN_FIELDS(64, 65, 0x730, 0x10, 12, 4), + PIN_FIELDS(66, 67, 0x730, 0x10, 16, 4), + PIN_FIELDS(68, 69, 0x730, 0x10, 20, 4), + PIN_FIELD(70, 70, 0x730, 0x10, 24, 4), + PIN_FIELD(71, 71, 0x730, 0x10, 28, 4), + PIN_FIELDS(72, 75, 0x740, 0x10, 0, 4), + PIN_FIELDS(76, 79, 0x740, 0x10, 16, 4), + PIN_FIELD(80, 80, 0x750, 0x10, 0, 4), + PIN_FIELD(81, 81, 0x750, 0x10, 4, 4), + PIN_FIELD(82, 82, 0x750, 0x10, 8, 4), + PIN_FIELDS(83, 86, 0x740, 0x10, 16, 4), + PIN_FIELD(87, 87, 0x750, 0x10, 24, 4), + PIN_FIELDS(88, 91, 0x750, 0x10, 28, 4), + PIN_FIELDS(92, 98, 0x760, 0x10, 0, 4), + PIN_FIELDS(99, 101, 0x760, 0x10, 4, 4), + PIN_FIELDS(102, 104, 0x760, 0x10, 8, 4), + PIN_FIELDS(105, 111, 0x760, 0x10, 12, 4), + PIN_FIELDS(112, 115, 0x760, 0x10, 16, 4), +}; + +static const struct mtk_pin_reg_calc mt8512_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8512_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8512_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8512_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8512_pin_do_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8512_pin_ies_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8512_pin_smt_range), + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8512_pin_pullsel_range), + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8512_pin_pullen_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8512_pin_drv_range), +}; + +static const struct mtk_pin_desc mt8512_pins[] = { + MTK_PIN(0, "GPIO0", DRV_GRP4), + MTK_PIN(1, "GPIO1", DRV_GRP4), + MTK_PIN(2, "GPIO2", DRV_GRP4), + MTK_PIN(3, "GPIO3", DRV_GRP4), + MTK_PIN(4, "GPIO4", DRV_GRP4), + MTK_PIN(5, "GPIO5", DRV_GRP4), + MTK_PIN(6, "GPIO6", DRV_GRP4), + MTK_PIN(7, "GPIO7", DRV_GRP4), + MTK_PIN(8, "GPIO8", DRV_GRP4), + MTK_PIN(9, "GPIO9", DRV_GRP4), + MTK_PIN(10, "GPIO10", DRV_GRP4), + MTK_PIN(11, "GPIO11", DRV_GRP4), + MTK_PIN(12, "GPIO12", DRV_GRP4), + MTK_PIN(13, "GPIO13", DRV_GRP4), + MTK_PIN(14, "GPIO14", DRV_GRP4), + MTK_PIN(15, "GPIO15", DRV_GRP4), + MTK_PIN(16, "GPIO16", DRV_GRP4), + MTK_PIN(17, "GPIO17", DRV_GRP4), + MTK_PIN(18, "GPIO18", DRV_GRP4), + MTK_PIN(19, "GPIO19", DRV_GRP4), + MTK_PIN(20, "GPIO20", DRV_GRP4), + MTK_PIN(21, "AUDIO_SYNC", DRV_GRP4), + MTK_PIN(22, "WIFI_INTB", DRV_GRP4), + MTK_PIN(23, "BT_INTB", DRV_GRP4), + MTK_PIN(24, "BT_STEREO", DRV_GRP4), + MTK_PIN(25, "RSTNB", DRV_GRP4), + MTK_PIN(26, "USB_ID", DRV_GRP4), + MTK_PIN(27, "USB_DRV", DRV_GRP4), + MTK_PIN(28, "EINT_GAUGEING", DRV_GRP4), + MTK_PIN(29, "CHG_IRQ", DRV_GRP4), + MTK_PIN(30, "CHG_OTG", DRV_GRP4), + MTK_PIN(31, "CHG_CEB", DRV_GRP4), + MTK_PIN(32, "FL_EN", DRV_GRP4), + MTK_PIN(33, "WAN_SMS_RDY", DRV_GRP4), + MTK_PIN(34, "SOC2WAN_RESET", DRV_GRP4), + MTK_PIN(35, "WAN_FM_RDY", DRV_GRP4), + MTK_PIN(36, "WAN_DIS", DRV_GRP4), + MTK_PIN(37, "WAN_VBUS_EN", DRV_GRP4), + MTK_PIN(38, "WAN_VBAT_EN", DRV_GRP4), + MTK_PIN(39, "WAN_PWR_EN", DRV_GRP4), + MTK_PIN(40, "KPROW0", DRV_GRP4), + MTK_PIN(41, "KPROW1", DRV_GRP4), + MTK_PIN(42, "KPCOL0", DRV_GRP4), + MTK_PIN(43, "KPCOL1", DRV_GRP4), + MTK_PIN(44, "PWM0", DRV_GRP4), + MTK_PIN(45, "PWM1", DRV_GRP4), + MTK_PIN(46, "PWM2", DRV_GRP4), + MTK_PIN(47, "PWM3", DRV_GRP4), + MTK_PIN(48, "JTMS", DRV_GRP4), + MTK_PIN(49, "JTCK", DRV_GRP4), + MTK_PIN(50, "JTDI", DRV_GRP4), + MTK_PIN(51, "JTDO", DRV_GRP4), + MTK_PIN(52, "URXD0", DRV_GRP4), + MTK_PIN(53, "UTXD0", DRV_GRP4), + MTK_PIN(54, "URXD1", DRV_GRP4), + MTK_PIN(55, "UTXD1", DRV_GRP4), + MTK_PIN(56, "URTS1", DRV_GRP4), + MTK_PIN(57, "UCTS1", DRV_GRP4), + MTK_PIN(58, "RTC32K_CK", DRV_GRP4), + MTK_PIN(59, "PMIC_DVS_REQ0", DRV_GRP4), + MTK_PIN(60, "PMIC_DVS_REQ1", DRV_GRP4), + MTK_PIN(61, "WATCHDOG", DRV_GRP4), + MTK_PIN(62, "PMIC_INT", DRV_GRP4), + MTK_PIN(63, "SUSPEND", DRV_GRP4), + MTK_PIN(64, "SDA0", DRV_GRP4), + MTK_PIN(65, "SCL0", DRV_GRP4), + MTK_PIN(66, "SDA1", DRV_GRP4), + MTK_PIN(67, "SCL1", DRV_GRP4), + MTK_PIN(68, "SDA2", DRV_GRP4), + MTK_PIN(69, "SCL2", DRV_GRP4), + MTK_PIN(70, "MSDC1_CMD", DRV_GRP4), + MTK_PIN(71, "MSDC1_CLK", DRV_GRP4), + MTK_PIN(72, "MSDC1_DAT0", DRV_GRP4), + MTK_PIN(73, "MSDC1_DAT1", DRV_GRP4), + MTK_PIN(74, "MSDC1_DAT2", DRV_GRP4), + MTK_PIN(75, "MSDC1_DAT3", DRV_GRP4), + MTK_PIN(76, "MSDC0_DAT7", DRV_GRP4), + MTK_PIN(77, "MSDC0_DAT6", DRV_GRP4), + MTK_PIN(78, "MSDC0_DAT5", DRV_GRP4), + MTK_PIN(79, "MSDC0_DAT4", DRV_GRP4), + MTK_PIN(80, "MSDC0_RSTB", DRV_GRP4), + MTK_PIN(81, "MSDC0_CMD", DRV_GRP4), + MTK_PIN(82, "MSDC0_CLK", DRV_GRP4), + MTK_PIN(83, "MSDC0_DAT3", DRV_GRP4), + MTK_PIN(84, "MSDC0_DAT2", DRV_GRP4), + MTK_PIN(85, "MSDC0_DAT1", DRV_GRP4), + MTK_PIN(86, "MSDC0_DAT0", DRV_GRP4), + MTK_PIN(87, "SPDIF", DRV_GRP4), + MTK_PIN(88, "PCM_CLK", DRV_GRP4), + MTK_PIN(89, "PCM_SYNC", DRV_GRP4), + MTK_PIN(90, "PCM_RX", DRV_GRP4), + MTK_PIN(91, "PCM_TX", DRV_GRP4), + MTK_PIN(92, "I2SIN_MCLK", DRV_GRP4), + MTK_PIN(93, "I2SIN_LRCK", DRV_GRP4), + MTK_PIN(94, "I2SIN_BCK", DRV_GRP4), + MTK_PIN(95, "I2SIN_DAT0", DRV_GRP4), + MTK_PIN(96, "I2SIN_DAT1", DRV_GRP4), + MTK_PIN(97, "I2SIN_DAT2", DRV_GRP4), + MTK_PIN(98, "I2SIN_DAT3", DRV_GRP4), + MTK_PIN(99, "DMIC0_CLK", DRV_GRP4), + MTK_PIN(100, "DMIC0_DAT0", DRV_GRP4), + MTK_PIN(101, "DMIC0_DAT1", DRV_GRP4), + MTK_PIN(102, "DMIC1_CLK", DRV_GRP4), + MTK_PIN(103, "DMIC1_DAT0", DRV_GRP4), + MTK_PIN(104, "DMIC1_DAT1", DRV_GRP4), + MTK_PIN(105, "I2SO_BCK", DRV_GRP4), + MTK_PIN(106, "I2SO_LRCK", DRV_GRP4), + MTK_PIN(107, "I2SO_MCLK", DRV_GRP4), + MTK_PIN(108, "I2SO_DAT0", DRV_GRP4), + MTK_PIN(109, "I2SO_DAT1", DRV_GRP4), + MTK_PIN(110, "I2SO_DAT2", DRV_GRP4), + MTK_PIN(111, "I2SO_DAT3", DRV_GRP4), + MTK_PIN(112, "SPI_CSB", DRV_GRP4), + MTK_PIN(113, "SPI_CLK", DRV_GRP4), + MTK_PIN(114, "SPI_MISO", DRV_GRP4), + MTK_PIN(115, "SPI_MOSI", DRV_GRP4), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +/* UART */ +static int mt8512_uart0_0_rxd_txd_pins[] = { 52, 53, }; +static int mt8512_uart0_0_rxd_txd_funcs[] = { 1, 1, }; +static int mt8512_uart1_0_rxd_txd_pins[] = { 54, 55, }; +static int mt8512_uart1_0_rxd_txd_funcs[] = { 1, 1, }; +static int mt8512_uart2_0_rxd_txd_pins[] = { 28, 29, }; +static int mt8512_uart2_0_rxd_txd_funcs[] = { 1, 1, }; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ +static const char *const mt8512_uart_groups[] = { "uart0_0_rxd_txd", + "uart1_0_rxd_txd", + "uart2_0_rxd_txd", }; + +/* SNAND */ +static int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, }; +static int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; + +/* MMC0 */ +static int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84, + 85, 86, }; +static int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +static const struct mtk_group_desc mt8512_groups[] = { + PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8512_uart0_0_rxd_txd), + PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8512_uart1_0_rxd_txd), + PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8512_uart2_0_rxd_txd), + + PINCTRL_PIN_GROUP("msdc0", mt8512_msdc0), + + PINCTRL_PIN_GROUP("snfi", mt8512_snfi), +}; + +static const char *const mt8512_msdc_groups[] = { "msdc0" }; + +static const struct mtk_function_desc mt8512_functions[] = { + {"uart", mt8512_uart_groups, ARRAY_SIZE(mt8512_uart_groups)}, + {"msdc", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)}, + {"snand", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)}, +}; + +static struct mtk_pinctrl_soc mt8512_data = { + .name = "mt8512_pinctrl", + .reg_cal = mt8512_reg_cals, + .pins = mt8512_pins, + .npins = ARRAY_SIZE(mt8512_pins), + .grps = mt8512_groups, + .ngrps = ARRAY_SIZE(mt8512_groups), + .funcs = mt8512_functions, + .nfuncs = ARRAY_SIZE(mt8512_functions), +}; + +static int mtk_pinctrl_mt8512_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt8512_data); +} + +static const struct udevice_id mt8512_pctrl_match[] = { + { .compatible = "mediatek,mt8512-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt8512_pinctrl) = { + .name = "mt8512_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt8512_pctrl_match, + .ops = &mtk_pinctrl_ops, + .probe = mtk_pinctrl_mt8512_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt8516.c new file mode 100644 index 000000000..6f94f762d --- /dev/null +++ b/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt8516.c @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 BayLibre, SAS + * Author: Fabien Parent <fparent@baylibre.com> + */ + +#include <dm.h> + +#include "pinctrl-mtk-common.h" + +#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 16, false) + +static const struct mtk_pin_field_calc mt8516_pin_mode_range[] = { + PIN_FIELD_CALC(0, 124, 0x300, 0x10, 0, 3, 15, false), +}; + +static const struct mtk_pin_field_calc mt8516_pin_dir_range[] = { + PIN_FIELD(0, 124, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8516_pin_di_range[] = { + PIN_FIELD(0, 124, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8516_pin_do_range[] = { + PIN_FIELD(0, 124, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8516_pin_ies_range[] = { + PIN_FIELD(0, 6, 0x900, 0x10, 2, 1), + PIN_FIELD(7, 10, 0x900, 0x10, 3, 1), + PIN_FIELD(11, 13, 0x900, 0x10, 12, 1), + PIN_FIELD(14, 17, 0x900, 0x10, 13, 1), + PIN_FIELD(18, 20, 0x910, 0x10, 10, 1), + PIN_FIELD(21, 23, 0x900, 0x10, 13, 1), + PIN_FIELD(24, 25, 0x900, 0x10, 12, 1), + PIN_FIELD(26, 30, 0x900, 0x10, 0, 1), + PIN_FIELD(31, 33, 0x900, 0x10, 1, 1), + PIN_FIELD(34, 39, 0x900, 0x10, 2, 1), + PIN_FIELD(40, 40, 0x910, 0x10, 11, 1), + PIN_FIELD(41, 43, 0x900, 0x10, 10, 1), + PIN_FIELD(44, 47, 0x900, 0x10, 11, 1), + PIN_FIELD(48, 51, 0x900, 0x10, 14, 1), + PIN_FIELD(52, 53, 0x910, 0x10, 0, 1), + PIN_FIELD(54, 54, 0x910, 0x10, 2, 1), + PIN_FIELD(55, 57, 0x910, 0x10, 4, 1), + PIN_FIELD(58, 59, 0x900, 0x10, 15, 1), + PIN_FIELD(60, 61, 0x910, 0x10, 1, 1), + PIN_FIELD(62, 65, 0x910, 0x10, 5, 1), + PIN_FIELD(66, 67, 0x910, 0x10, 6, 1), + PIN_FIELD(68, 68, 0x930, 0x10, 2, 1), + PIN_FIELD(69, 69, 0x930, 0x10, 1, 1), + PIN_FIELD(70, 70, 0x930, 0x10, 6, 1), + PIN_FIELD(71, 71, 0x930, 0x10, 5, 1), + PIN_FIELD(72, 72, 0x930, 0x10, 4, 1), + PIN_FIELD(73, 73, 0x930, 0x10, 3, 1), + + PIN_FIELD(100, 103, 0x910, 0x10, 7, 1), + PIN_FIELD(104, 104, 0x920, 0x10, 12, 1), + PIN_FIELD(105, 105, 0x920, 0x10, 11, 1), + PIN_FIELD(106, 106, 0x930, 0x10, 0, 1), + PIN_FIELD(107, 107, 0x920, 0x10, 15, 1), + PIN_FIELD(108, 108, 0x920, 0x10, 14, 1), + PIN_FIELD(109, 109, 0x920, 0x10, 13, 1), + PIN_FIELD(110, 110, 0x920, 0x10, 9, 1), + PIN_FIELD(111, 111, 0x920, 0x10, 8, 1), + PIN_FIELD(112, 112, 0x920, 0x10, 7, 1), + PIN_FIELD(113, 113, 0x920, 0x10, 6, 1), + PIN_FIELD(114, 114, 0x920, 0x10, 10, 1), + PIN_FIELD(115, 115, 0x920, 0x10, 1, 1), + PIN_FIELD(116, 116, 0x920, 0x10, 0, 1), + PIN_FIELD(117, 117, 0x920, 0x10, 5, 1), + PIN_FIELD(118, 118, 0x920, 0x10, 4, 1), + PIN_FIELD(119, 119, 0x920, 0x10, 3, 1), + PIN_FIELD(120, 120, 0x920, 0x10, 2, 1), + PIN_FIELD(121, 124, 0x910, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt8516_pin_smt_range[] = { + PIN_FIELD(0, 6, 0xA00, 0x10, 2, 1), + PIN_FIELD(7, 10, 0xA00, 0x10, 3, 1), + PIN_FIELD(11, 13, 0xA00, 0x10, 12, 1), + PIN_FIELD(14, 17, 0xA00, 0x10, 13, 1), + PIN_FIELD(18, 20, 0xA10, 0x10, 10, 1), + PIN_FIELD(21, 23, 0xA00, 0x10, 13, 1), + PIN_FIELD(24, 25, 0xA00, 0x10, 12, 1), + PIN_FIELD(26, 30, 0xA00, 0x10, 0, 1), + PIN_FIELD(31, 33, 0xA00, 0x10, 1, 1), + PIN_FIELD(40, 40, 0xA10, 0x10, 11, 1), + PIN_FIELD(41, 43, 0xA00, 0x10, 10, 1), + PIN_FIELD(44, 47, 0xA00, 0x10, 11, 1), + PIN_FIELD(48, 51, 0xA00, 0x10, 14, 1), + PIN_FIELD(52, 53, 0xA10, 0x10, 0, 1), + PIN_FIELD(54, 54, 0xA10, 0x10, 2, 1), + PIN_FIELD(55, 57, 0xA10, 0x10, 4, 1), + PIN_FIELD(58, 59, 0xA00, 0x10, 15, 1), + PIN_FIELD(60, 61, 0xA10, 0x10, 1, 1), + PIN_FIELD(62, 65, 0xA10, 0x10, 5, 1), + PIN_FIELD(66, 67, 0xA10, 0x10, 6, 1), + PIN_FIELD(68, 68, 0xA30, 0x10, 2, 1), + PIN_FIELD(69, 69, 0xA30, 0x10, 1, 1), + PIN_FIELD(70, 70, 0xA30, 0x10, 3, 1), + PIN_FIELD(71, 71, 0xA30, 0x10, 4, 1), + PIN_FIELD(72, 72, 0xA30, 0x10, 5, 1), + PIN_FIELD(73, 73, 0xA30, 0x10, 6, 1), + + PIN_FIELD(100, 103, 0xA10, 0x10, 7, 1), + PIN_FIELD(104, 104, 0xA20, 0x10, 12, 1), + PIN_FIELD(105, 105, 0xA20, 0x10, 11, 1), + PIN_FIELD(106, 106, 0xA30, 0x10, 13, 1), + PIN_FIELD(107, 107, 0xA20, 0x10, 14, 1), + PIN_FIELD(108, 108, 0xA20, 0x10, 15, 1), + PIN_FIELD(109, 109, 0xA30, 0x10, 0, 1), + PIN_FIELD(110, 110, 0xA20, 0x10, 9, 1), + PIN_FIELD(111, 111, 0xA20, 0x10, 8, 1), + PIN_FIELD(112, 112, 0xA20, 0x10, 7, 1), + PIN_FIELD(113, 113, 0xA20, 0x10, 6, 1), + PIN_FIELD(114, 114, 0xA20, 0x10, 10, 1), + PIN_FIELD(115, 115, 0xA20, 0x10, 1, 1), + PIN_FIELD(116, 116, 0xA20, 0x10, 0, 1), + PIN_FIELD(117, 117, 0xA20, 0x10, 5, 1), + PIN_FIELD(118, 118, 0xA20, 0x10, 4, 1), + PIN_FIELD(119, 119, 0xA20, 0x10, 3, 1), + PIN_FIELD(120, 120, 0xA20, 0x10, 2, 1), + PIN_FIELD(121, 124, 0xA10, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt8516_pin_pullen_range[] = { + PIN_FIELD(0, 13, 0x500, 0x10, 0, 1), + PIN_FIELD(18, 20, 0x510, 0x10, 2, 1), + PIN_FIELD(24, 31, 0x510, 0x10, 8, 1), + PIN_FIELD(32, 39, 0x520, 0x10, 0, 1), + PIN_FIELD(44, 47, 0x520, 0x10, 12, 1), + PIN_FIELD(48, 63, 0x530, 0x10, 0, 1), + PIN_FIELD(64, 67, 0x540, 0x10, 0, 1), + PIN_FIELD(100, 103, 0x560, 0x10, 4, 1), + PIN_FIELD(121, 124, 0x570, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt8516_pin_pullsel_range[] = { + PIN_FIELD(0, 13, 0x600, 0x10, 0, 1), + PIN_FIELD(18, 20, 0x610, 0x10, 2, 1), + PIN_FIELD(24, 31, 0x610, 0x10, 8, 1), + PIN_FIELD(32, 39, 0x620, 0x10, 0, 1), + PIN_FIELD(44, 47, 0x620, 0x10, 12, 1), + PIN_FIELD(48, 63, 0x630, 0x10, 0, 1), + PIN_FIELD(64, 67, 0x640, 0x10, 0, 1), + PIN_FIELD(100, 103, 0x660, 0x10, 4, 1), + PIN_FIELD(121, 124, 0x670, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt8516_pin_drv_range[] = { + PIN_FIELD(0, 4, 0xd00, 0x10, 0, 4), + PIN_FIELD(5, 10, 0xd00, 0x10, 4, 4), + PIN_FIELD(11, 13, 0xd00, 0x10, 8, 4), + PIN_FIELD(14, 17, 0xd00, 0x10, 12, 4), + PIN_FIELD(18, 20, 0xd10, 0x10, 0, 4), + PIN_FIELD(21, 23, 0xd00, 0x10, 12, 4), + PIN_FIELD(24, 25, 0xd00, 0x10, 8, 4), + PIN_FIELD(26, 30, 0xd10, 0x10, 4, 4), + PIN_FIELD(31, 33, 0xd10, 0x10, 8, 4), + PIN_FIELD(34, 35, 0xd10, 0x10, 12, 4), + PIN_FIELD(36, 39, 0xd20, 0x10, 0, 4), + PIN_FIELD(40, 40, 0xd20, 0x10, 4, 4), + PIN_FIELD(41, 43, 0xd20, 0x10, 8, 4), + PIN_FIELD(44, 47, 0xd20, 0x10, 12, 4), + PIN_FIELD(48, 51, 0xd30, 0x10, 0, 4), + PIN_FIELD(54, 54, 0xd30, 0x10, 8, 4), + PIN_FIELD(55, 57, 0xd30, 0x10, 12, 4), + PIN_FIELD(62, 67, 0xd40, 0x10, 8, 4), + PIN_FIELD(68, 68, 0xd40, 0x10, 12, 4), + PIN_FIELD(69, 69, 0xd50, 0x10, 0, 4), + PIN_FIELD(70, 73, 0xd50, 0x10, 4, 4), + PIN_FIELD(100, 103, 0xd50, 0x10, 8, 4), + PIN_FIELD(104, 104, 0xd50, 0x10, 12, 4), + PIN_FIELD(105, 105, 0xd60, 0x10, 0, 4), + PIN_FIELD(106, 109, 0xd60, 0x10, 4, 4), + PIN_FIELD(110, 113, 0xd70, 0x10, 0, 4), + PIN_FIELD(114, 114, 0xd70, 0x10, 4, 4), + PIN_FIELD(115, 115, 0xd60, 0x10, 12, 4), + PIN_FIELD(116, 116, 0xd60, 0x10, 8, 4), + PIN_FIELD(117, 120, 0xd70, 0x10, 0, 4), +}; + +static const struct mtk_pin_reg_calc mt8516_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8516_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8516_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8516_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8516_pin_do_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8516_pin_ies_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8516_pin_smt_range), + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8516_pin_pullsel_range), + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8516_pin_pullen_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8516_pin_drv_range), +}; + +static const struct mtk_pin_desc mt8516_pins[] = { + MTK_PIN(0, "EINT0", DRV_GRP0), + MTK_PIN(1, "EINT1", DRV_GRP0), + MTK_PIN(2, "EINT2", DRV_GRP0), + MTK_PIN(3, "EINT3", DRV_GRP0), + MTK_PIN(4, "EINT4", DRV_GRP0), + MTK_PIN(5, "EINT5", DRV_GRP0), + MTK_PIN(6, "EINT6", DRV_GRP0), + MTK_PIN(7, "EINT7", DRV_GRP0), + MTK_PIN(8, "EINT8", DRV_GRP0), + MTK_PIN(9, "EINT9", DRV_GRP0), + MTK_PIN(10, "EINT10", DRV_GRP0), + MTK_PIN(11, "EINT11", DRV_GRP0), + MTK_PIN(12, "EINT12", DRV_GRP0), + MTK_PIN(13, "EINT13", DRV_GRP0), + MTK_PIN(14, "EINT14", DRV_GRP2), + MTK_PIN(15, "EINT15", DRV_GRP2), + MTK_PIN(16, "EINT16", DRV_GRP2), + MTK_PIN(17, "EINT17", DRV_GRP2), + MTK_PIN(18, "EINT18", DRV_GRP0), + MTK_PIN(19, "EINT19", DRV_GRP0), + MTK_PIN(20, "EINT20", DRV_GRP0), + MTK_PIN(21, "EINT21", DRV_GRP2), + MTK_PIN(22, "EINT22", DRV_GRP2), + MTK_PIN(23, "EINT23", DRV_GRP2), + MTK_PIN(24, "EINT24", DRV_GRP0), + MTK_PIN(25, "EINT25", DRV_GRP0), + MTK_PIN(26, "PWRAP_SPI0_MI", DRV_GRP4), + MTK_PIN(27, "PWRAP_SPI0_MO", DRV_GRP4), + MTK_PIN(28, "PWRAP_INT", DRV_GRP4), + MTK_PIN(29, "PWRAP_SPIO0_CK", DRV_GRP4), + MTK_PIN(30, "PWARP_SPI0_CSN", DRV_GRP4), + MTK_PIN(31, "RTC32K_CK", DRV_GRP4), + MTK_PIN(32, "WATCHDOG", DRV_GRP4), + MTK_PIN(33, "SRCLKENA0", DRV_GRP4), + MTK_PIN(34, "URXD2", DRV_GRP0), + MTK_PIN(35, "UTXD2", DRV_GRP0), + MTK_PIN(36, "MRG_CLK", DRV_GRP0), + MTK_PIN(37, "MRG_SYNC", DRV_GRP0), + MTK_PIN(38, "MRG_DI", DRV_GRP0), + MTK_PIN(39, "MRG_DO", DRV_GRP0), + MTK_PIN(40, "KPROW0", DRV_GRP2), + MTK_PIN(41, "KPROW1", DRV_GRP2), + MTK_PIN(42, "KPCOL0", DRV_GRP2), + MTK_PIN(43, "KPCOL1", DRV_GRP2), + MTK_PIN(44, "JMTS", DRV_GRP2), + MTK_PIN(45, "JTCK", DRV_GRP2), + MTK_PIN(46, "JTDI", DRV_GRP2), + MTK_PIN(47, "JTDO", DRV_GRP2), + MTK_PIN(48, "SPI_CS", DRV_GRP2), + MTK_PIN(49, "SPI_CK", DRV_GRP2), + MTK_PIN(50, "SPI_MI", DRV_GRP2), + MTK_PIN(51, "SPI_MO", DRV_GRP2), + MTK_PIN(52, "SDA1", DRV_GRP2), + MTK_PIN(53, "SCL1", DRV_GRP2), + MTK_PIN(54, "DISP_PWM", DRV_GRP2), + MTK_PIN(55, "I2S_DATA_IN", DRV_GRP2), + MTK_PIN(56, "I2S_LRCK", DRV_GRP2), + MTK_PIN(57, "I2S_BCK", DRV_GRP2), + MTK_PIN(58, "SDA0", DRV_GRP2), + MTK_PIN(59, "SCL0", DRV_GRP2), + MTK_PIN(60, "SDA2", DRV_GRP2), + MTK_PIN(61, "SCL2", DRV_GRP2), + MTK_PIN(62, "URXD0", DRV_GRP2), + MTK_PIN(63, "UTXD0", DRV_GRP2), + MTK_PIN(64, "URXD1", DRV_GRP2), + MTK_PIN(65, "UTXD1", DRV_GRP2), + MTK_PIN(66, "LCM_RST", DRV_GRP2), + MTK_PIN(67, "DSI_TE", DRV_GRP2), + MTK_PIN(68, "MSDC2_CMD", DRV_GRP4), + MTK_PIN(69, "MSDC2_CLK", DRV_GRP4), + MTK_PIN(70, "MSDC2_DAT0", DRV_GRP4), + MTK_PIN(71, "MSDC2_DAT1", DRV_GRP4), + MTK_PIN(72, "MSDC2_DAT2", DRV_GRP4), + MTK_PIN(73, "MSDC2_DAT3", DRV_GRP4), + MTK_PIN(74, "TDN3", DRV_GRP0), + MTK_PIN(75, "TDP3", DRV_GRP0), + MTK_PIN(76, "TDN2", DRV_GRP0), + MTK_PIN(77, "TDP2", DRV_GRP0), + MTK_PIN(78, "TCN", DRV_GRP0), + MTK_PIN(79, "TCP", DRV_GRP0), + MTK_PIN(80, "TDN1", DRV_GRP0), + MTK_PIN(81, "TDP1", DRV_GRP0), + MTK_PIN(82, "TDN0", DRV_GRP0), + MTK_PIN(83, "TDP0", DRV_GRP0), + MTK_PIN(84, "RDN0", DRV_GRP0), + MTK_PIN(85, "RDP0", DRV_GRP0), + MTK_PIN(86, "RDN1", DRV_GRP0), + MTK_PIN(87, "RDP1", DRV_GRP0), + MTK_PIN(88, "RCN", DRV_GRP0), + MTK_PIN(89, "RCP", DRV_GRP0), + MTK_PIN(90, "RDN2", DRV_GRP0), + MTK_PIN(91, "RDP2", DRV_GRP0), + MTK_PIN(92, "RDN3", DRV_GRP0), + MTK_PIN(93, "RDP3", DRV_GRP0), + MTK_PIN(94, "RCN_A", DRV_GRP0), + MTK_PIN(95, "RCP_A", DRV_GRP0), + MTK_PIN(96, "RDN1_A", DRV_GRP0), + MTK_PIN(97, "RDP1_A", DRV_GRP0), + MTK_PIN(98, "RDN0_A", DRV_GRP0), + MTK_PIN(99, "RDP0_A", DRV_GRP0), + MTK_PIN(100, "CMDDAT0", DRV_GRP2), + MTK_PIN(101, "CMDDAT1", DRV_GRP2), + MTK_PIN(102, "CMMCLK", DRV_GRP2), + MTK_PIN(103, "CMPCLK", DRV_GRP2), + MTK_PIN(104, "MSDC1_CMD", DRV_GRP4), + MTK_PIN(105, "MSDC1_CLK", DRV_GRP4), + MTK_PIN(106, "MSDC1_DAT0", DRV_GRP4), + MTK_PIN(107, "MSDC1_DAT1", DRV_GRP4), + MTK_PIN(108, "MSDC1_DAT2", DRV_GRP4), + MTK_PIN(109, "MSDC1_DAT3", DRV_GRP4), + MTK_PIN(110, "MSDC0_DAT7", DRV_GRP4), + MTK_PIN(111, "MSDC0_DAT6", DRV_GRP4), + MTK_PIN(112, "MSDC0_DAT5", DRV_GRP4), + MTK_PIN(113, "MSDC0_DAT4", DRV_GRP4), + MTK_PIN(114, "MSDC0_RSTB", DRV_GRP4), + MTK_PIN(115, "MSDC0_CMD", DRV_GRP4), + MTK_PIN(116, "MSDC0_CLK", DRV_GRP4), + MTK_PIN(117, "MSDC0_DAT3", DRV_GRP4), + MTK_PIN(118, "MSDC0_DAT2", DRV_GRP4), + MTK_PIN(119, "MSDC0_DAT1", DRV_GRP4), + MTK_PIN(120, "MSDC0_DAT0", DRV_GRP4), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +/* UART */ +static int mt8516_uart0_0_rxd_txd_pins[] = { 62, 63, }; +static int mt8516_uart0_0_rxd_txd_funcs[] = { 1, 1, }; +static int mt8516_uart1_0_rxd_txd_pins[] = { 64, 65, }; +static int mt8516_uart1_0_rxd_txd_funcs[] = { 1, 1, }; +static int mt8516_uart2_0_rxd_txd_pins[] = { 34, 35, }; +static int mt8516_uart2_0_rxd_txd_funcs[] = { 1, 1, }; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ +static const char *const mt8516_uart_groups[] = { "uart0_0_rxd_txd", + "uart1_0_rxd_txd", + "uart2_0_rxd_txd", }; + +/* MMC0 */ +static int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117, 118, + 119, 120, }; +static int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +static const struct mtk_group_desc mt8516_groups[] = { + PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8516_uart0_0_rxd_txd), + PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8516_uart1_0_rxd_txd), + PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8516_uart2_0_rxd_txd), + + PINCTRL_PIN_GROUP("msdc0", mt8516_msdc0), +}; + +static const char *const mt8516_msdc_groups[] = { "msdc0" }; + +static const struct mtk_function_desc mt8516_functions[] = { + {"uart", mt8516_uart_groups, ARRAY_SIZE(mt8516_uart_groups)}, + {"msdc", mt8516_msdc_groups, ARRAY_SIZE(mt8516_msdc_groups)}, +}; + +static struct mtk_pinctrl_soc mt8516_data = { + .name = "mt8516_pinctrl", + .reg_cal = mt8516_reg_cals, + .pins = mt8516_pins, + .npins = ARRAY_SIZE(mt8516_pins), + .grps = mt8516_groups, + .ngrps = ARRAY_SIZE(mt8516_groups), + .funcs = mt8516_functions, + .nfuncs = ARRAY_SIZE(mt8516_functions), + .gpio_mode = 0, + .rev = MTK_PINCTRL_V1, +}; + +static int mtk_pinctrl_mt8516_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt8516_data); +} + +static const struct udevice_id mt8516_pctrl_match[] = { + { .compatible = "mediatek,mt8516-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt8516_pinctrl) = { + .name = "mt8516_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt8516_pctrl_match, + .ops = &mtk_pinctrl_ops, + .probe = mtk_pinctrl_mt8516_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt8518.c b/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt8518.c new file mode 100644 index 000000000..ed51bd3bb --- /dev/null +++ b/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mt8518.c @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + */ + +#include <dm.h> + +#include "pinctrl-mtk-common.h" + +#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 16, false) + +static const struct mtk_pin_field_calc mt8518_pin_mode_range[] = { + PIN_FIELD_CALC(0, 119, 0x300, 0x10, 0, 3, 15, false), +}; + +static const struct mtk_pin_field_calc mt8518_pin_dir_range[] = { + PIN_FIELD(0, 119, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8518_pin_di_range[] = { + PIN_FIELD(0, 119, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8518_pin_do_range[] = { + PIN_FIELD(0, 119, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8518_pin_ies_range[] = { + PIN_FIELD(0, 2, 0x900, 0x10, 0, 1), + PIN_FIELD(3, 3, 0x920, 0x10, 9, 1), + PIN_FIELD(4, 4, 0x920, 0x10, 8, 1), + PIN_FIELD(5, 5, 0x920, 0x10, 7, 1), + PIN_FIELD(6, 6, 0x920, 0x10, 6, 1), + PIN_FIELD(7, 7, 0x920, 0x10, 10, 1), + PIN_FIELD(8, 8, 0x920, 0x10, 1, 1), + PIN_FIELD(9, 9, 0x920, 0x10, 0, 1), + PIN_FIELD(10, 10, 0x920, 0x10, 5, 1), + PIN_FIELD(11, 11, 0x920, 0x10, 4, 1), + PIN_FIELD(12, 12, 0x920, 0x10, 3, 1), + PIN_FIELD(13, 13, 0x920, 0x10, 2, 1), + PIN_FIELD(14, 14, 0x900, 0x10, 1, 1), + PIN_FIELD(15, 15, 0x900, 0x10, 2, 1), + PIN_FIELD(16, 16, 0x900, 0x10, 3, 1), + PIN_FIELD(17, 20, 0x900, 0x10, 4, 1), + PIN_FIELD(21, 22, 0x900, 0x10, 5, 1), + PIN_FIELD(23, 27, 0x910, 0x10, 15, 1), + PIN_FIELD(28, 28, 0x900, 0x10, 6, 1), + PIN_FIELD(29, 29, 0x930, 0x10, 2, 1), + PIN_FIELD(30, 30, 0x930, 0x10, 1, 1), + PIN_FIELD(31, 31, 0x930, 0x10, 6, 1), + PIN_FIELD(32, 32, 0x930, 0x10, 5, 1), + PIN_FIELD(33, 33, 0x930, 0x10, 4, 1), + PIN_FIELD(34, 35, 0x930, 0x10, 3, 1), + PIN_FIELD(36, 39, 0x900, 0x10, 7, 1), + PIN_FIELD(40, 41, 0x900, 0x10, 8, 1), + PIN_FIELD(42, 44, 0x900, 0x10, 9, 1), + PIN_FIELD(45, 47, 0x900, 0x10, 10, 1), + PIN_FIELD(48, 51, 0x900, 0x10, 11, 1), + PIN_FIELD(52, 55, 0x900, 0x10, 12, 1), + PIN_FIELD(56, 56, 0x900, 0x10, 13, 1), + PIN_FIELD(57, 57, 0x900, 0x10, 14, 1), + PIN_FIELD(58, 58, 0x900, 0x10, 15, 1), + PIN_FIELD(59, 60, 0x910, 0x10, 0, 1), + + PIN_FIELD(61, 61, 0x910, 0x10, 1, 1), + PIN_FIELD(62, 62, 0x910, 0x10, 2, 1), + PIN_FIELD(63, 69, 0x910, 0x10, 3, 1), + PIN_FIELD(70, 70, 0x910, 0x10, 4, 1), + PIN_FIELD(71, 76, 0x910, 0x10, 5, 1), + PIN_FIELD(77, 80, 0x910, 0x10, 6, 1), + PIN_FIELD(81, 87, 0x910, 0x10, 7, 1), + PIN_FIELD(88, 97, 0x910, 0x10, 8, 1), + PIN_FIELD(98, 103, 0x910, 0x10, 9, 1), + PIN_FIELD(104, 107, 0x910, 0x10, 10, 1), + PIN_FIELD(108, 109, 0x910, 0x10, 11, 1), + PIN_FIELD(110, 111, 0x910, 0x10, 12, 1), + PIN_FIELD(112, 113, 0x910, 0x10, 13, 1), + PIN_FIELD(114, 114, 0x920, 0x10, 12, 1), + PIN_FIELD(115, 115, 0x920, 0x10, 11, 1), + PIN_FIELD(116, 116, 0x930, 0x10, 0, 1), + PIN_FIELD(117, 117, 0x920, 0x10, 15, 1), + PIN_FIELD(118, 118, 0x920, 0x10, 14, 1), + PIN_FIELD(119, 119, 0x920, 0x10, 13, 1), +}; + +static const struct mtk_pin_field_calc mt8518_pin_smt_range[] = { + PIN_FIELD(0, 2, 0xA00, 0x10, 0, 1), + PIN_FIELD(3, 3, 0xA20, 0x10, 9, 1), + PIN_FIELD(4, 4, 0xA20, 0x10, 8, 1), + PIN_FIELD(5, 5, 0xA20, 0x10, 7, 1), + PIN_FIELD(6, 6, 0xA20, 0x10, 6, 1), + PIN_FIELD(7, 7, 0xA20, 0x10, 10, 1), + PIN_FIELD(8, 8, 0xA20, 0x10, 1, 1), + PIN_FIELD(9, 9, 0xA20, 0x10, 0, 1), + PIN_FIELD(10, 10, 0xA20, 0x10, 5, 1), + PIN_FIELD(11, 11, 0xA20, 0x10, 4, 1), + PIN_FIELD(12, 12, 0xA20, 0x10, 3, 1), + PIN_FIELD(13, 13, 0xA20, 0x10, 2, 1), + PIN_FIELD(14, 14, 0xA00, 0x10, 1, 1), + PIN_FIELD(15, 15, 0xA00, 0x10, 2, 1), + PIN_FIELD(16, 16, 0xA00, 0x10, 3, 1), + PIN_FIELD(17, 20, 0xA00, 0x10, 4, 1), + PIN_FIELD(21, 22, 0xA00, 0x10, 5, 1), + PIN_FIELD(23, 27, 0xA10, 0x10, 15, 1), + PIN_FIELD(28, 28, 0xA00, 0x10, 6, 1), + PIN_FIELD(29, 29, 0xA30, 0x10, 2, 1), + PIN_FIELD(30, 30, 0xA30, 0x10, 1, 1), + PIN_FIELD(31, 31, 0xA30, 0x10, 6, 1), + PIN_FIELD(32, 32, 0xA30, 0x10, 5, 1), + PIN_FIELD(33, 33, 0xA30, 0x10, 4, 1), + PIN_FIELD(34, 35, 0xA30, 0x10, 3, 1), + PIN_FIELD(36, 39, 0xA00, 0x10, 7, 1), + PIN_FIELD(40, 41, 0xA00, 0x10, 8, 1), + PIN_FIELD(42, 44, 0xA00, 0x10, 9, 1), + PIN_FIELD(45, 47, 0xA00, 0x10, 10, 1), + PIN_FIELD(48, 51, 0xA00, 0x10, 11, 1), + PIN_FIELD(52, 55, 0xA00, 0x10, 12, 1), + PIN_FIELD(56, 56, 0xA00, 0x10, 13, 1), + PIN_FIELD(57, 57, 0xA00, 0x10, 14, 1), + PIN_FIELD(58, 58, 0xA00, 0x10, 15, 1), + PIN_FIELD(59, 60, 0xA10, 0x10, 0, 1), + + PIN_FIELD(61, 61, 0xA10, 0x10, 1, 1), + PIN_FIELD(62, 62, 0xA10, 0x10, 2, 1), + PIN_FIELD(63, 69, 0xA10, 0x10, 3, 1), + PIN_FIELD(70, 70, 0xA10, 0x10, 4, 1), + PIN_FIELD(71, 76, 0xA10, 0x10, 5, 1), + PIN_FIELD(77, 80, 0xA10, 0x10, 6, 1), + PIN_FIELD(81, 87, 0xA10, 0x10, 7, 1), + PIN_FIELD(88, 97, 0xA10, 0x10, 8, 1), + PIN_FIELD(98, 103, 0xA10, 0x10, 9, 1), + PIN_FIELD(104, 107, 0xA10, 0x10, 10, 1), + PIN_FIELD(108, 109, 0xA10, 0x10, 11, 1), + PIN_FIELD(110, 111, 0xA10, 0x10, 12, 1), + PIN_FIELD(112, 113, 0xA10, 0x10, 13, 1), + PIN_FIELD(114, 114, 0xA20, 0x10, 12, 1), + PIN_FIELD(115, 115, 0xA20, 0x10, 11, 1), + PIN_FIELD(116, 116, 0xA30, 0x10, 0, 1), + PIN_FIELD(117, 117, 0xA20, 0x10, 15, 1), + PIN_FIELD(118, 118, 0xA20, 0x10, 14, 1), + PIN_FIELD(119, 119, 0xA20, 0x10, 13, 1), +}; + +static const struct mtk_pin_field_calc mt8518_pin_pullen_range[] = { + PIN_FIELD(14, 15, 0x500, 0x10, 14, 1), + PIN_FIELD(16, 28, 0x510, 0x10, 0, 1), + PIN_FIELD(36, 47, 0x520, 0x10, 4, 1), + PIN_FIELD(48, 63, 0x530, 0x10, 0, 1), + PIN_FIELD(64, 79, 0x540, 0x10, 0, 1), + PIN_FIELD(80, 95, 0x550, 0x10, 0, 1), + PIN_FIELD(96, 111, 0x560, 0x10, 0, 1), + PIN_FIELD(112, 113, 0x570, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8518_pin_pullsel_range[] = { + PIN_FIELD(14, 15, 0x600, 0x10, 14, 1), + PIN_FIELD(16, 28, 0x610, 0x10, 0, 1), + PIN_FIELD(36, 47, 0x620, 0x10, 4, 1), + PIN_FIELD(48, 63, 0x630, 0x10, 0, 1), + PIN_FIELD(64, 79, 0x640, 0x10, 0, 1), + PIN_FIELD(80, 95, 0x650, 0x10, 0, 1), + PIN_FIELD(96, 111, 0x660, 0x10, 0, 1), + PIN_FIELD(112, 113, 0x670, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8518_pin_drv_range[] = { + PIN_FIELD(0, 2, 0xd70, 0x10, 8, 4), + PIN_FIELD(3, 6, 0xd70, 0x10, 0, 4), + PIN_FIELD(7, 7, 0xd70, 0x10, 4, 4), + PIN_FIELD(8, 8, 0xd60, 0x10, 8, 4), + PIN_FIELD(9, 9, 0xd60, 0x10, 12, 4), + PIN_FIELD(10, 13, 0xd70, 0x10, 0, 4), + PIN_FIELD(14, 14, 0xd50, 0x10, 8, 4), + PIN_FIELD(15, 15, 0xd20, 0x10, 4, 4), + PIN_FIELD(16, 16, 0xd50, 0x10, 8, 4), + PIN_FIELD(17, 20, 0xd20, 0x10, 12, 4), + PIN_FIELD(23, 27, 0xd30, 0x10, 8, 4), + PIN_FIELD(28, 28, 0xd10, 0x10, 0, 4), + PIN_FIELD(29, 29, 0xd40, 0x10, 12, 4), + PIN_FIELD(30, 30, 0xd50, 0x10, 0, 4), + PIN_FIELD(31, 35, 0xd50, 0x10, 4, 4), + PIN_FIELD(36, 41, 0xd00, 0x10, 0, 4), + PIN_FIELD(42, 47, 0xd00, 0x10, 4, 4), + PIN_FIELD(48, 51, 0xd00, 0x10, 8, 4), + PIN_FIELD(52, 55, 0xd10, 0x10, 12, 4), + PIN_FIELD(56, 56, 0xdb0, 0x10, 4, 4), + PIN_FIELD(57, 58, 0xd00, 0x10, 8, 4), + PIN_FIELD(59, 62, 0xd00, 0x10, 12, 4), + PIN_FIELD(63, 68, 0xd90, 0x10, 12, 4), + PIN_FIELD(69, 69, 0xda0, 0x10, 0, 4), + PIN_FIELD(70, 70, 0xda0, 0x10, 12, 4), + PIN_FIELD(71, 73, 0xd80, 0x10, 12, 4), + PIN_FIELD(74, 76, 0xd90, 0x10, 0, 4), + PIN_FIELD(77, 80, 0xd20, 0x10, 0, 4), + PIN_FIELD(81, 87, 0xd80, 0x10, 8, 4), + PIN_FIELD(88, 97, 0xd30, 0x10, 0, 4), + PIN_FIELD(98, 103, 0xd10, 0x10, 4, 4), + PIN_FIELD(104, 105, 0xd40, 0x10, 8, 4), + PIN_FIELD(106, 107, 0xd10, 0x10, 8, 4), + PIN_FIELD(114, 114, 0xd50, 0x10, 12, 4), + PIN_FIELD(115, 115, 0xd60, 0x10, 0, 4), + PIN_FIELD(116, 119, 0xd60, 0x10, 4, 4), +}; + +static const struct mtk_pin_reg_calc mt8518_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8518_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8518_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8518_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8518_pin_do_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8518_pin_ies_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8518_pin_smt_range), + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8518_pin_pullsel_range), + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8518_pin_pullen_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8518_pin_drv_range), +}; + +static const struct mtk_pin_desc mt8518_pins[] = { + MTK_PIN(0, "NFI_NCEB0", DRV_GRP4), + MTK_PIN(1, "NFI_NREB", DRV_GRP4), + MTK_PIN(2, "NFI_NRNB", DRV_GRP4), + MTK_PIN(3, "MSDC0_DAT7", DRV_GRP4), + MTK_PIN(4, "MSDC0_DAT6", DRV_GRP4), + MTK_PIN(5, "MSDC0_DAT5", DRV_GRP4), + MTK_PIN(6, "MSDC0_DAT4", DRV_GRP4), + MTK_PIN(7, "MSDC0_RSTB", DRV_GRP4), + MTK_PIN(8, "MSDC0_CMD", DRV_GRP4), + MTK_PIN(9, "MSDC0_CLK", DRV_GRP4), + MTK_PIN(10, "MSDC0_DAT3", DRV_GRP4), + MTK_PIN(11, "MSDC0_DAT2", DRV_GRP4), + MTK_PIN(12, "MSDC0_DAT1", DRV_GRP4), + MTK_PIN(13, "MSDC0_DAT0", DRV_GRP4), + MTK_PIN(14, "RTC32K_CK", DRV_GRP2), + MTK_PIN(15, "WATCHDOG", DRV_GRP2), + MTK_PIN(16, "SUSPEND", DRV_GRP2), + MTK_PIN(17, "JTMS", DRV_GRP2), + MTK_PIN(18, "JTCK", DRV_GRP2), + MTK_PIN(19, "JTDI", DRV_GRP2), + MTK_PIN(20, "JTDO", DRV_GRP2), + MTK_PIN(21, "SDA3", DRV_GRP2), + MTK_PIN(22, "SCL3", DRV_GRP2), + MTK_PIN(23, "PWRAP_SPI_CLK", DRV_GRP2), + MTK_PIN(24, "PWRAP_SPI_CSN", DRV_GRP2), + MTK_PIN(25, "PWRAP_SPI_MOSI", DRV_GRP2), + MTK_PIN(26, "PWRAP_SPI_MISO", DRV_GRP2), + MTK_PIN(27, "PWRAP_INT", DRV_GRP2), + MTK_PIN(28, "EINT22", DRV_GRP2), + MTK_PIN(29, "MSDC2_CMD", DRV_GRP4), + MTK_PIN(30, "MSDC2_CLK", DRV_GRP4), + MTK_PIN(31, "MSDC2_DAT0", DRV_GRP4), + MTK_PIN(32, "MSDC2_DAT1", DRV_GRP4), + MTK_PIN(33, "MSDC2_DAT2", DRV_GRP4), + MTK_PIN(34, "MSDC2_DAT3", DRV_GRP4), + MTK_PIN(35, "MSDC2_DS", DRV_GRP4), + MTK_PIN(36, "EINT0", DRV_GRP0), + MTK_PIN(37, "EINT1", DRV_GRP0), + MTK_PIN(38, "EINT2", DRV_GRP0), + MTK_PIN(39, "EINT3", DRV_GRP0), + MTK_PIN(40, "EINT4", DRV_GRP0), + MTK_PIN(41, "EINT5", DRV_GRP0), + MTK_PIN(42, "EINT6", DRV_GRP0), + MTK_PIN(43, "EINT7", DRV_GRP0), + MTK_PIN(44, "EINT8", DRV_GRP0), + MTK_PIN(45, "EINT9", DRV_GRP0), + MTK_PIN(46, "EINT10", DRV_GRP0), + MTK_PIN(47, "EINT11", DRV_GRP0), + MTK_PIN(48, "EINT12", DRV_GRP0), + MTK_PIN(49, "EINT13", DRV_GRP0), + MTK_PIN(50, "EINT14", DRV_GRP0), + MTK_PIN(51, "EINT15", DRV_GRP0), + MTK_PIN(52, "URXD1", DRV_GRP0), + MTK_PIN(53, "UTXD1", DRV_GRP0), + MTK_PIN(54, "URTS1", DRV_GRP0), + MTK_PIN(55, "UCTS1", DRV_GRP0), + MTK_PIN(56, "IR", DRV_GRP0), + MTK_PIN(57, "EINT16", DRV_GRP0), + MTK_PIN(58, "EINT17", DRV_GRP0), + MTK_PIN(59, "EINT18", DRV_GRP0), + MTK_PIN(60, "EINT19", DRV_GRP0), + MTK_PIN(61, "EINT20", DRV_GRP0), + MTK_PIN(62, "EINT21", DRV_GRP0), + MTK_PIN(63, "I2SO_MCLK", DRV_GRP0), + MTK_PIN(64, "I2SO_BCK", DRV_GRP0), + MTK_PIN(65, "I2SO_LRCK", DRV_GRP0), + MTK_PIN(66, "I2SO_D0", DRV_GRP0), + MTK_PIN(67, "I2SO_D1", DRV_GRP0), + MTK_PIN(68, "I2SO_D2", DRV_GRP0), + MTK_PIN(69, "I2SO_D3", DRV_GRP0), + MTK_PIN(70, "SPDIF_IN0", DRV_GRP0), + MTK_PIN(71, "DMIC_CLK0", DRV_GRP0), + MTK_PIN(72, "DMIC_CLK1", DRV_GRP0), + MTK_PIN(73, "DMIC_DAT0", DRV_GRP0), + MTK_PIN(74, "DMIC_DAT1", DRV_GRP0), + MTK_PIN(75, "DMIC_DAT2", DRV_GRP0), + MTK_PIN(76, "DMIC_DAT3", DRV_GRP0), + MTK_PIN(77, "TDM_MCLK", DRV_GRP0), + MTK_PIN(78, "TDM_BCK", DRV_GRP0), + MTK_PIN(79, "TDM_LRCK", DRV_GRP0), + MTK_PIN(80, "TDM_DI", DRV_GRP0), + MTK_PIN(81, "I2SIN_D0", DRV_GRP0), + MTK_PIN(82, "I2SIN_D1", DRV_GRP0), + MTK_PIN(83, "I2SIN_D2", DRV_GRP0), + MTK_PIN(84, "I2SIN_D3", DRV_GRP0), + MTK_PIN(85, "I2SIN_MCLK", DRV_GRP0), + MTK_PIN(86, "I2SIN_BCK", DRV_GRP0), + MTK_PIN(87, "I2SIN_LRCK", DRV_GRP0), + MTK_PIN(88, "SPI1_CS", DRV_GRP0), + MTK_PIN(89, "SPI1_CK", DRV_GRP0), + MTK_PIN(90, "SPI1_MI", DRV_GRP0), + MTK_PIN(91, "SPI1_MO", DRV_GRP0), + MTK_PIN(92, "SPI2_CS", DRV_GRP0), + MTK_PIN(93, "SPI2_CK", DRV_GRP0), + MTK_PIN(94, "SPI2_MI0", DRV_GRP0), + MTK_PIN(95, "SPI2_MI1", DRV_GRP0), + MTK_PIN(96, "SPI2_MI2", DRV_GRP0), + MTK_PIN(97, "SPI2_MI3", DRV_GRP0), + MTK_PIN(98, "SW_RESET_DSP", DRV_GRP0), + MTK_PIN(99, "GPIO1", DRV_GRP0), + MTK_PIN(100, "GPIO2", DRV_GRP0), + MTK_PIN(101, "GPIO3", DRV_GRP0), + MTK_PIN(102, "GPIO4", DRV_GRP0), + MTK_PIN(103, "RTC32K_DSP", DRV_GRP0), + MTK_PIN(104, "URXD0", DRV_GRP2), + MTK_PIN(105, "UTXD0", DRV_GRP2), + MTK_PIN(106, "URXD2", DRV_GRP2), + MTK_PIN(107, "UTXD2", DRV_GRP2), + MTK_PIN(108, "SDA1", DRV_GRP4), + MTK_PIN(109, "SCL1", DRV_GRP4), + MTK_PIN(110, "SDA0", DRV_GRP4), + MTK_PIN(111, "SCL0", DRV_GRP4), + MTK_PIN(112, "SDA2", DRV_GRP4), + MTK_PIN(113, "SCL2", DRV_GRP4), + MTK_PIN(114, "MSDC1_CMD", DRV_GRP4), + MTK_PIN(115, "MSDC1_CLK", DRV_GRP4), + MTK_PIN(116, "MSDC1_DAT0", DRV_GRP4), + MTK_PIN(117, "MSDC1_DAT1", DRV_GRP4), + MTK_PIN(118, "MSDC1_DAT2", DRV_GRP4), + MTK_PIN(119, "MSDC1_DAT3", DRV_GRP4), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +/* UART */ +static int mt8518_uart0_0_rxd_txd_pins[] = { 104, 105, }; +static int mt8518_uart0_0_rxd_txd_funcs[] = { 1, 1, }; +static int mt8518_uart1_0_rxd_txd_pins[] = { 52, 53, }; +static int mt8518_uart1_0_rxd_txd_funcs[] = { 1, 1, }; +static int mt8518_uart2_0_rxd_txd_pins[] = { 106, 107, }; +static int mt8518_uart2_0_rxd_txd_funcs[] = { 1, 1, }; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ +static const char *const mt8518_uart_groups[] = { "uart0_0_rxd_txd", + "uart1_0_rxd_txd", + "uart2_0_rxd_txd", }; + +/* MMC0 */ +static int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, }; +static int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +static const struct mtk_group_desc mt8518_groups[] = { + PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8518_uart0_0_rxd_txd), + PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8518_uart1_0_rxd_txd), + PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8518_uart2_0_rxd_txd), + + PINCTRL_PIN_GROUP("msdc0", mt8518_msdc0), +}; + +static const char *const mt8518_msdc_groups[] = { "msdc0" }; + +static const struct mtk_function_desc mt8518_functions[] = { + {"uart", mt8518_uart_groups, ARRAY_SIZE(mt8518_uart_groups)}, + {"msdc", mt8518_msdc_groups, ARRAY_SIZE(mt8518_msdc_groups)}, +}; + +static struct mtk_pinctrl_soc mt8518_data = { + .name = "mt8518_pinctrl", + .reg_cal = mt8518_reg_cals, + .pins = mt8518_pins, + .npins = ARRAY_SIZE(mt8518_pins), + .grps = mt8518_groups, + .ngrps = ARRAY_SIZE(mt8518_groups), + .funcs = mt8518_functions, + .nfuncs = ARRAY_SIZE(mt8518_functions), + .gpio_mode = 0, + .rev = MTK_PINCTRL_V1, +}; + +static int mtk_pinctrl_mt8518_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt8518_data); +} + +static const struct udevice_id mt8518_pctrl_match[] = { + { .compatible = "mediatek,mt8518-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt8518_pinctrl) = { + .name = "mt8518_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt8518_pctrl_match, + .ops = &mtk_pinctrl_ops, + .probe = mtk_pinctrl_mt8518_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mtk-common.c new file mode 100644 index 000000000..3bd23befd --- /dev/null +++ b/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -0,0 +1,672 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + */ + +#include <common.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dm/pinctrl.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <linux/bitops.h> + +#include "pinctrl-mtk-common.h" + +#if CONFIG_IS_ENABLED(PINCONF) +/** + * struct mtk_drive_desc - the structure that holds the information + * of the driving current + * @min: the minimum current of this group + * @max: the maximum current of this group + * @step: the step current of this group + * @scal: the weight factor + * + * formula: output = ((input) / step - 1) * scal + */ +struct mtk_drive_desc { + u8 min; + u8 max; + u8 step; + u8 scal; +}; + +/* The groups of drive strength */ +static const struct mtk_drive_desc mtk_drive[] = { + [DRV_GRP0] = { 4, 16, 4, 1 }, + [DRV_GRP1] = { 4, 16, 4, 2 }, + [DRV_GRP2] = { 2, 8, 2, 1 }, + [DRV_GRP3] = { 2, 8, 2, 2 }, + [DRV_GRP4] = { 2, 16, 2, 1 }, +}; +#endif + +static const char *mtk_pinctrl_dummy_name = "_dummy"; + +static void mtk_w32(struct udevice *dev, u32 reg, u32 val) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + + __raw_writel(val, priv->base + reg); +} + +static u32 mtk_r32(struct udevice *dev, u32 reg) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + + return __raw_readl(priv->base + reg); +} + +static inline int get_count_order(unsigned int count) +{ + int order; + + order = fls(count) - 1; + if (count & (count - 1)) + order++; + return order; +} + +void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set) +{ + u32 val; + + val = mtk_r32(dev, reg); + val &= ~mask; + val |= set; + mtk_w32(dev, reg, val); +} + +static int mtk_hw_pin_field_lookup(struct udevice *dev, int pin, + const struct mtk_pin_reg_calc *rc, + struct mtk_pin_field *pfd) +{ + const struct mtk_pin_field_calc *c, *e; + u32 bits; + + c = rc->range; + e = c + rc->nranges; + + while (c < e) { + if (pin >= c->s_pin && pin <= c->e_pin) + break; + c++; + } + + if (c >= e) + return -EINVAL; + + /* Calculated bits as the overall offset the pin is located at, + * if c->fixed is held, that determines the all the pins in the + * range use the same field with the s_pin. + */ + bits = c->fixed ? c->s_bit : c->s_bit + (pin - c->s_pin) * (c->x_bits); + + /* Fill pfd from bits. For example 32-bit register applied is assumed + * when c->sz_reg is equal to 32. + */ + pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg); + pfd->bitpos = bits % c->sz_reg; + pfd->mask = (1 << c->x_bits) - 1; + + /* pfd->next is used for indicating that bit wrapping-around happens + * which requires the manipulation for bit 0 starting in the next + * register to form the complete field read/write. + */ + pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0; + + return 0; +} + +static int mtk_hw_pin_field_get(struct udevice *dev, int pin, + int field, struct mtk_pin_field *pfd) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + const struct mtk_pin_reg_calc *rc; + + if (field < 0 || field >= PINCTRL_PIN_REG_MAX) + return -EINVAL; + + if (priv->soc->reg_cal && priv->soc->reg_cal[field].range) + rc = &priv->soc->reg_cal[field]; + else + return -EINVAL; + + return mtk_hw_pin_field_lookup(dev, pin, rc, pfd); +} + +static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l) +{ + *l = 32 - pf->bitpos; + *h = get_count_order(pf->mask) - *l; +} + +static void mtk_hw_write_cross_field(struct udevice *dev, + struct mtk_pin_field *pf, int value) +{ + int nbits_l, nbits_h; + + mtk_hw_bits_part(pf, &nbits_h, &nbits_l); + + mtk_rmw(dev, pf->offset, pf->mask << pf->bitpos, + (value & pf->mask) << pf->bitpos); + + mtk_rmw(dev, pf->offset + pf->next, BIT(nbits_h) - 1, + (value & pf->mask) >> nbits_l); +} + +static void mtk_hw_read_cross_field(struct udevice *dev, + struct mtk_pin_field *pf, int *value) +{ + int nbits_l, nbits_h, h, l; + + mtk_hw_bits_part(pf, &nbits_h, &nbits_l); + + l = (mtk_r32(dev, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1); + h = (mtk_r32(dev, pf->offset + pf->next)) & (BIT(nbits_h) - 1); + + *value = (h << nbits_l) | l; +} + +static int mtk_hw_set_value(struct udevice *dev, int pin, int field, + int value) +{ + struct mtk_pin_field pf; + int err; + + err = mtk_hw_pin_field_get(dev, pin, field, &pf); + if (err) + return err; + + if (!pf.next) + mtk_rmw(dev, pf.offset, pf.mask << pf.bitpos, + (value & pf.mask) << pf.bitpos); + else + mtk_hw_write_cross_field(dev, &pf, value); + + return 0; +} + +static int mtk_hw_get_value(struct udevice *dev, int pin, int field, + int *value) +{ + struct mtk_pin_field pf; + int err; + + err = mtk_hw_pin_field_get(dev, pin, field, &pf); + if (err) + return err; + + if (!pf.next) + *value = (mtk_r32(dev, pf.offset) >> pf.bitpos) & pf.mask; + else + mtk_hw_read_cross_field(dev, &pf, value); + + return 0; +} + +static int mtk_get_groups_count(struct udevice *dev) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->soc->ngrps; +} + +static const char *mtk_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + + if (!priv->soc->pins[selector].name) + return mtk_pinctrl_dummy_name; + + return priv->soc->pins[selector].name; +} + +static int mtk_get_pins_count(struct udevice *dev) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->soc->npins; +} + +static int mtk_get_pin_muxing(struct udevice *dev, unsigned int selector, + char *buf, int size) +{ + int val, err; + + err = mtk_hw_get_value(dev, selector, PINCTRL_PIN_REG_MODE, &val); + if (err) + return err; + + snprintf(buf, size, "Aux Func.%d", val); + return 0; +} + +static const char *mtk_get_group_name(struct udevice *dev, + unsigned int selector) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + + if (!priv->soc->grps[selector].name) + return mtk_pinctrl_dummy_name; + + return priv->soc->grps[selector].name; +} + +static int mtk_get_functions_count(struct udevice *dev) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->soc->nfuncs; +} + +static const char *mtk_get_function_name(struct udevice *dev, + unsigned int selector) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + + if (!priv->soc->funcs[selector].name) + return mtk_pinctrl_dummy_name; + + return priv->soc->funcs[selector].name; +} + +static int mtk_pinmux_group_set(struct udevice *dev, + unsigned int group_selector, + unsigned int func_selector) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + const struct mtk_group_desc *grp = + &priv->soc->grps[group_selector]; + int i; + + for (i = 0; i < grp->num_pins; i++) { + int *pin_modes = grp->data; + + mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE, + pin_modes[i]); + } + + return 0; +} + +#if CONFIG_IS_ENABLED(PINCONF) +static const struct pinconf_param mtk_conf_params[] = { + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, + { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, + { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 }, + { "output-high", PIN_CONFIG_OUTPUT, 1, }, + { "output-low", PIN_CONFIG_OUTPUT, 0, }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, +}; + + +int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg, u32 val) +{ + int err, disable, pullup; + + disable = (arg == PIN_CONFIG_BIAS_DISABLE); + pullup = (arg == PIN_CONFIG_BIAS_PULL_UP); + + if (disable) { + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, 0); + if (err) + return err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, 0); + if (err) + return err; + + } else { + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, pullup); + if (err) + return err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, !pullup); + if (err) + return err; + } + + return 0; +} + +int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, u32 arg, u32 val) +{ + int err, disable, pullup, r0, r1; + + disable = (arg == PIN_CONFIG_BIAS_DISABLE); + pullup = (arg == PIN_CONFIG_BIAS_PULL_UP); + r0 = !!(val & 1); + r1 = !!(val & 2); + + if (disable) { + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 0); + if (err) + return err; + } else { + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 1); + if (err) + return err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLSEL, + pullup); + if (err) + return err; + } + + /* Also set PUPD/R0/R1 if the pin has them */ + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup); + if (err != -EINVAL) { + mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0); + mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1); + } + + return 0; +} + +int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg) +{ + int err; + + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_IES, 1); + if (err) + return err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0); + if (err) + return err; + return 0; +} + +int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + const struct mtk_pin_desc *desc = &priv->soc->pins[pin]; + const struct mtk_drive_desc *tb; + int err = -ENOTSUPP; + + tb = &mtk_drive[desc->drv_n]; + /* 4mA when (e8, e4) = (0, 0) + * 8mA when (e8, e4) = (0, 1) + * 12mA when (e8, e4) = (1, 0) + * 16mA when (e8, e4) = (1, 1) + */ + if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { + arg = (arg / tb->step - 1) * tb->scal; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_E4, + arg & 0x1); + if (err) + return err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_E8, + (arg & 0x2) >> 1); + if (err) + return err; + } + + return 0; +} + + +int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + const struct mtk_pin_desc *desc = &priv->soc->pins[pin]; + const struct mtk_drive_desc *tb; + int err = -ENOTSUPP; + + tb = &mtk_drive[desc->drv_n]; + if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { + arg = (arg / tb->step - 1) * tb->scal; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DRV, arg); + if (err) + return err; + } + + return 0; +} + +static int mtk_pinconf_set(struct udevice *dev, unsigned int pin, + unsigned int param, unsigned int arg) +{ + int err = 0; + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + int rev = priv->soc->rev; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + if (rev == MTK_PINCTRL_V0) + err = mtk_pinconf_bias_set_v0(dev, pin, param, arg); + else + err = mtk_pinconf_bias_set_v1(dev, pin, param, arg); + if (err) + goto err; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_SMT, 0); + if (err) + goto err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 1); + if (err) + goto err; + break; + case PIN_CONFIG_INPUT_ENABLE: + if (rev == MTK_PINCTRL_V1) + err = mtk_pinconf_input_enable_v1(dev, pin, param); + if (err) + goto err; + break; + case PIN_CONFIG_OUTPUT: + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 1); + if (err) + goto err; + + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DO, arg); + if (err) + goto err; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + /* arg = 1: Input mode & SMT enable ; + * arg = 0: Output mode & SMT disable + */ + arg = arg ? 2 : 1; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, + arg & 1); + if (err) + goto err; + + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_SMT, + !!(arg & 2)); + if (err) + goto err; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + if (rev == MTK_PINCTRL_V0) + err = mtk_pinconf_drive_set_v0(dev, pin, arg); + else + err = mtk_pinconf_drive_set_v1(dev, pin, arg); + if (err) + goto err; + break; + + default: + err = -ENOTSUPP; + } + +err: + + return err; +} + +static int mtk_pinconf_group_set(struct udevice *dev, + unsigned int group_selector, + unsigned int param, unsigned int arg) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + const struct mtk_group_desc *grp = + &priv->soc->grps[group_selector]; + int i, ret; + + for (i = 0; i < grp->num_pins; i++) { + ret = mtk_pinconf_set(dev, grp->pins[i], param, arg); + if (ret) + return ret; + } + + return 0; +} +#endif + +const struct pinctrl_ops mtk_pinctrl_ops = { + .get_pins_count = mtk_get_pins_count, + .get_pin_name = mtk_get_pin_name, + .get_pin_muxing = mtk_get_pin_muxing, + .get_groups_count = mtk_get_groups_count, + .get_group_name = mtk_get_group_name, + .get_functions_count = mtk_get_functions_count, + .get_function_name = mtk_get_function_name, + .pinmux_group_set = mtk_pinmux_group_set, +#if CONFIG_IS_ENABLED(PINCONF) + .pinconf_num_params = ARRAY_SIZE(mtk_conf_params), + .pinconf_params = mtk_conf_params, + .pinconf_set = mtk_pinconf_set, + .pinconf_group_set = mtk_pinconf_group_set, +#endif + .set_state = pinctrl_generic_set_state, +}; + +#if CONFIG_IS_ENABLED(DM_GPIO) || \ + (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) +static int mtk_gpio_get(struct udevice *dev, unsigned int off) +{ + int val, err; + + err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DI, &val); + if (err) + return err; + + return !!val; +} + +static int mtk_gpio_set(struct udevice *dev, unsigned int off, int val) +{ + return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DO, !!val); +} + +static int mtk_gpio_get_direction(struct udevice *dev, unsigned int off) +{ + int val, err; + + err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DIR, &val); + if (err) + return err; + + return val ? GPIOF_OUTPUT : GPIOF_INPUT; +} + +static int mtk_gpio_direction_input(struct udevice *dev, unsigned int off) +{ + return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 0); +} + +static int mtk_gpio_direction_output(struct udevice *dev, + unsigned int off, int val) +{ + mtk_gpio_set(dev, off, val); + + /* And set the requested value */ + return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 1); +} + +static int mtk_gpio_request(struct udevice *dev, unsigned int off, + const char *label) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent); + + return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE, + priv->soc->gpio_mode); +} + +static int mtk_gpio_probe(struct udevice *dev) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent); + struct gpio_dev_priv *uc_priv; + + uc_priv = dev_get_uclass_priv(dev); + uc_priv->bank_name = priv->soc->name; + uc_priv->gpio_count = priv->soc->npins; + + return 0; +} + +static const struct dm_gpio_ops mtk_gpio_ops = { + .request = mtk_gpio_request, + .set_value = mtk_gpio_set, + .get_value = mtk_gpio_get, + .get_function = mtk_gpio_get_direction, + .direction_input = mtk_gpio_direction_input, + .direction_output = mtk_gpio_direction_output, +}; + +static struct driver mtk_gpio_driver = { + .name = "mediatek_gpio", + .id = UCLASS_GPIO, + .probe = mtk_gpio_probe, + .ops = &mtk_gpio_ops, +}; + +static int mtk_gpiochip_register(struct udevice *parent) +{ + struct uclass_driver *drv; + struct udevice *dev; + int ret; + ofnode node; + + drv = lists_uclass_lookup(UCLASS_GPIO); + if (!drv) + return -ENOENT; + + ret = -ENOENT; + dev_for_each_subnode(node, parent) + if (ofnode_read_bool(node, "gpio-controller")) { + ret = 0; + break; + } + + if (ret) + return ret; + + ret = device_bind_with_driver_data(parent, &mtk_gpio_driver, + "mediatek_gpio", 0, node, + &dev); + if (ret) + return ret; + + return 0; +} +#endif + +int mtk_pinctrl_common_probe(struct udevice *dev, + struct mtk_pinctrl_soc *soc) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + int ret = 0; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + priv->soc = soc; + +#if CONFIG_IS_ENABLED(DM_GPIO) || \ + (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) + ret = mtk_gpiochip_register(dev); +#endif + + return ret; +} diff --git a/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mtk-common.h new file mode 100644 index 000000000..5e51a9a90 --- /dev/null +++ b/roms/u-boot/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + */ +#ifndef __PINCTRL_MEDIATEK_H__ +#define __PINCTRL_MEDIATEK_H__ + +#define MTK_PINCTRL_V0 0x0 +#define MTK_PINCTRL_V1 0x1 + +#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), } +#define MTK_PIN(_number, _name, _drv_n) { \ + .number = _number, \ + .name = _name, \ + .drv_n = _drv_n, \ + } + +#define PINCTRL_PIN_GROUP(name, id) \ + { \ + name, \ + id##_pins, \ + ARRAY_SIZE(id##_pins), \ + id##_funcs, \ + } + +#define PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, _sz_reg, _fixed) { \ + .s_pin = _s_pin, \ + .e_pin = _e_pin, \ + .s_addr = _s_addr, \ + .x_addrs = _x_addrs, \ + .s_bit = _s_bit, \ + .x_bits = _x_bits, \ + .sz_reg = _sz_reg, \ + .fixed = _fixed, \ + } + +/* List these attributes which could be modified for the pin */ +enum { + PINCTRL_PIN_REG_MODE, + PINCTRL_PIN_REG_DIR, + PINCTRL_PIN_REG_DI, + PINCTRL_PIN_REG_DO, + PINCTRL_PIN_REG_SMT, + PINCTRL_PIN_REG_PD, + PINCTRL_PIN_REG_PU, + PINCTRL_PIN_REG_E4, + PINCTRL_PIN_REG_E8, + PINCTRL_PIN_REG_IES, + PINCTRL_PIN_REG_PULLEN, + PINCTRL_PIN_REG_PULLSEL, + PINCTRL_PIN_REG_DRV, + PINCTRL_PIN_REG_PUPD, + PINCTRL_PIN_REG_R0, + PINCTRL_PIN_REG_R1, + PINCTRL_PIN_REG_MAX, +}; + +/* Group the pins by the driving current */ +enum { + DRV_FIXED, + DRV_GRP0, + DRV_GRP1, + DRV_GRP2, + DRV_GRP3, + DRV_GRP4, +}; + +/** + * struct mtk_pin_field - the structure that holds the information of the field + * used to describe the attribute for the pin + * @offset: the register offset relative to the base address + * @mask: the mask used to filter out the field from the register + * @bitpos: the start bit relative to the register + * @next: the indication that the field would be extended to the + next register + */ +struct mtk_pin_field { + u32 offset; + u32 mask; + u8 bitpos; + u8 next; +}; + +/** + * struct mtk_pin_field_calc - the structure that holds the range providing + * the guide used to look up the relevant field + * @s_pin: the start pin within the range + * @e_pin: the end pin within the range + * @s_addr: the start address for the range + * @x_addrs: the address distance between two consecutive registers + * within the range + * @s_bit: the start bit for the first register within the range + * @x_bits: the bit distance between two consecutive pins within + * the range + * @sz_reg: the size of bits in a register + * @fixed: the consecutive pins share the same bits with the 1st + * pin + */ +struct mtk_pin_field_calc { + u16 s_pin; + u16 e_pin; + u32 s_addr; + u8 x_addrs; + u8 s_bit; + u8 x_bits; + u8 sz_reg; + u8 fixed; +}; + +/** + * struct mtk_pin_reg_calc - the structure that holds all ranges used to + * determine which register the pin would make use of + * for certain pin attribute. + * @range: the start address for the range + * @nranges: the number of items in the range + */ +struct mtk_pin_reg_calc { + const struct mtk_pin_field_calc *range; + unsigned int nranges; +}; + +/** + * struct mtk_pin_desc - the structure that providing information + * for each pin of chips + * @number: unique pin number from the global pin number space + * @name: name for this pin + * @drv_n: the index with the driving group + */ +struct mtk_pin_desc { + unsigned int number; + const char *name; + u8 drv_n; +}; + +/** + * struct mtk_group_desc - generic pin group descriptor + * @name: name of the pin group + * @pins: array of pins that belong to the group + * @num_pins: number of pins in the group + * @data: pin controller driver specific data + */ +struct mtk_group_desc { + const char *name; + int *pins; + int num_pins; + void *data; +}; + +/** + * struct mtk_function_desc - generic function descriptor + * @name: name of the function + * @group_names: array of pin group names + * @num_group_names: number of pin group names + */ +struct mtk_function_desc { + const char *name; + const char * const *group_names; + int num_group_names; +}; + +/* struct mtk_pin_soc - the structure that holds SoC-specific data */ +struct mtk_pinctrl_soc { + const char *name; + const struct mtk_pin_reg_calc *reg_cal; + const struct mtk_pin_desc *pins; + int npins; + const struct mtk_group_desc *grps; + int ngrps; + const struct mtk_function_desc *funcs; + int nfuncs; + int gpio_mode; + int rev; +}; + +/** + * struct mtk_pinctrl_priv - private data for MTK pinctrl driver + * + * @base: base address of the pinctrl device + * @soc: SoC specific data + */ +struct mtk_pinctrl_priv { + void __iomem *base; + struct mtk_pinctrl_soc *soc; +}; + +extern const struct pinctrl_ops mtk_pinctrl_ops; + +/* A common read-modify-write helper for MediaTek chips */ +void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set); +int mtk_pinctrl_common_probe(struct udevice *dev, + struct mtk_pinctrl_soc *soc); + +#endif /* __PINCTRL_MEDIATEK_H__ */ |