diff options
| author |   ToshikazuOhiwa <toshikazu_ohiwa@mail.toyota.co.jp> | 2020-03-30 09:24:26 +0900 |
|---|---|---|
| committer | ToshikazuOhiwa <toshikazu_ohiwa@mail.toyota.co.jp> | 2020-03-30 09:24:26 +0900 |
| commit | 5b80bfd7bffd4c20d80b7c70a7130529e9a755dd (patch) | |
| tree | b4bb18dcd1487dbf1ea8127e5671b7bb2eded033 /bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch | |
| parent | 706ad73eb02caf8532deaf5d38995bd258725cb8 (diff) | |
agl-basesystem
Diffstat (limited to 'bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch')
| -rw-r--r-- | bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch new file mode 100644 index 00000000..91505b7c --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch @@ -0,0 +1,41 @@ +From da0bd33c8c8f6a1b77ecaa4c676f8ee14997b9e9 Mon Sep 17 00:00:00 2001 +From: "Ang, Chee Hong" <chee.hong.ang@intel.com> +Date: Wed, 30 Jan 2019 21:29:09 -0800 +Subject: [PATCH 08/12] ARM: socfpga: stratix10: Enable DMA330 DMA controller + +Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> +--- + arch/arm/mach-socfpga/include/mach/reset_manager_s10.h | 1 + + arch/arm/mach-socfpga/spl_s10.c | 4 ++++ + 2 files changed, 5 insertions(+) + +diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h +index 1939ffa149..85424c28a6 100644 +--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h ++++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h +@@ -97,6 +97,7 @@ struct socfpga_reset_manager { + #define RSTMGR_DMA RSTMGR_DEFINE(1, 16) + #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17) + #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18) ++#define RSTMGR_DMA_OCP RSTMGR_DEFINE(1, 21) + #define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) + #define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1) + #define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2) +diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c +index ec65e1ce64..04fa1a5696 100644 +--- a/arch/arm/mach-socfpga/spl_s10.c ++++ b/arch/arm/mach-socfpga/spl_s10.c +@@ -158,6 +158,10 @@ void board_init_f(ulong dummy) + writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma); + writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph); + ++ /* enable DMA330 DMA */ ++ socfpga_per_reset(SOCFPGA_RESET(DMA), 0); ++ socfpga_per_reset(SOCFPGA_RESET(DMA_OCP), 0); ++ + spl_disable_firewall_l4_per(); + + spl_disable_firewall_l4_sys(); +-- +2.21.0 + |