diff options
| author |   ToshikazuOhiwa <toshikazu_ohiwa@mail.toyota.co.jp> | 2020-03-30 09:24:26 +0900 |
|---|---|---|
| committer | ToshikazuOhiwa <toshikazu_ohiwa@mail.toyota.co.jp> | 2020-03-30 09:24:26 +0900 |
| commit | 5b80bfd7bffd4c20d80b7c70a7130529e9a755dd (patch) | |
| tree | b4bb18dcd1487dbf1ea8127e5671b7bb2eded033 /bsp/meta-altera/recipes-bsp | |
| parent | 706ad73eb02caf8532deaf5d38995bd258725cb8 (diff) | |
agl-basesystem
Diffstat (limited to 'bsp/meta-altera/recipes-bsp')
32 files changed, 2008 insertions, 0 deletions
diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/0001-Fix-native-build-by-using-env-variables.patch b/bsp/meta-altera/recipes-bsp/u-boot/files/0001-Fix-native-build-by-using-env-variables.patch new file mode 100644 index 00000000..5443bce4 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/0001-Fix-native-build-by-using-env-variables.patch @@ -0,0 +1,31 @@ +From 5aa1e2d99a26f1cab1774fa1e94b53de42897d1c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jan-Simon=20M=C3=B6ller?= <jsmoeller@linuxfoundation.org> +Date: Thu, 10 Aug 2017 19:36:21 +0200 +Subject: [PATCH] Fix native build by using env variables +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Jan-Simon Möller <jsmoeller@linuxfoundation.org> +--- + Makefile | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/Makefile b/Makefile +index 8ca1db5..fef1059 100644 +--- a/Makefile ++++ b/Makefile +@@ -254,8 +254,8 @@ CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ + else if [ -x /bin/bash ]; then echo /bin/bash; \ + else echo sh; fi ; fi) + +-HOSTCC = cc +-HOSTCXX = c++ ++HOSTCC = $(CC) ++HOSTCXX = $(CXX) + HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer \ + $(if $(CONFIG_TOOLS_DEBUG),-g) + HOSTCXXFLAGS = -O2 +-- +2.1.4 + diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/fix-build-error-under-gcc6.patch b/bsp/meta-altera/recipes-bsp/u-boot/files/fix-build-error-under-gcc6.patch new file mode 100644 index 00000000..18c5e748 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/fix-build-error-under-gcc6.patch @@ -0,0 +1,91 @@ +From 07373b2e477ae61f9f6a0e2eff41be3276d92923 Mon Sep 17 00:00:00 2001 +From: yocto <yocto@yocto.org> +Date: Thu, 2 Jun 2016 03:21:51 -0500 +Subject: [PATCH] fix build error under gcc6 + +Fix the following error: +| ../include/linux/compiler-gcc.h:114:30: fatal error: linux/compiler-gcc6.h: No such file or directory +| #include gcc_header(__GNUC__) + +Signed-off-by: Zhenhua Luo <zhenhua.luo@nxp.com> + +Upstream-Status: Pending +--- + include/linux/compiler-gcc6.h | 65 +++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 65 insertions(+) + create mode 100644 include/linux/compiler-gcc6.h + +diff --git a/include/linux/compiler-gcc6.h b/include/linux/compiler-gcc6.h +new file mode 100644 +index 0000000..c8c5659 +--- /dev/null ++++ b/include/linux/compiler-gcc6.h +@@ -0,0 +1,65 @@ ++#ifndef __LINUX_COMPILER_H ++#error "Please don't include <linux/compiler-gcc5.h> directly, include <linux/compiler.h> instead." ++#endif ++ ++#define __used __attribute__((__used__)) ++#define __must_check __attribute__((warn_unused_result)) ++#define __compiler_offsetof(a, b) __builtin_offsetof(a, b) ++ ++/* Mark functions as cold. gcc will assume any path leading to a call ++ to them will be unlikely. This means a lot of manual unlikely()s ++ are unnecessary now for any paths leading to the usual suspects ++ like BUG(), printk(), panic() etc. [but let's keep them for now for ++ older compilers] ++ ++ Early snapshots of gcc 4.3 don't support this and we can't detect this ++ in the preprocessor, but we can live with this because they're unreleased. ++ Maketime probing would be overkill here. ++ ++ gcc also has a __attribute__((__hot__)) to move hot functions into ++ a special section, but I don't see any sense in this right now in ++ the kernel context */ ++#define __cold __attribute__((__cold__)) ++ ++#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) ++ ++#ifndef __CHECKER__ ++# define __compiletime_warning(message) __attribute__((warning(message))) ++# define __compiletime_error(message) __attribute__((error(message))) ++#endif /* __CHECKER__ */ ++ ++/* ++ * Mark a position in code as unreachable. This can be used to ++ * suppress control flow warnings after asm blocks that transfer ++ * control elsewhere. ++ * ++ * Early snapshots of gcc 4.5 don't support this and we can't detect ++ * this in the preprocessor, but we can live with this because they're ++ * unreleased. Really, we need to have autoconf for the kernel. ++ */ ++#define unreachable() __builtin_unreachable() ++ ++/* Mark a function definition as prohibited from being cloned. */ ++#define __noclone __attribute__((__noclone__)) ++ ++/* ++ * Tell the optimizer that something else uses this function or variable. ++ */ ++#define __visible __attribute__((externally_visible)) ++ ++/* ++ * GCC 'asm goto' miscompiles certain code sequences: ++ * ++ * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670 ++ * ++ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek. ++ * ++ * (asm goto is automatically volatile - the naming reflects this.) ++ */ ++#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0) ++ ++#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP ++#define __HAVE_BUILTIN_BSWAP32__ ++#define __HAVE_BUILTIN_BSWAP64__ ++#define __HAVE_BUILTIN_BSWAP16__ ++#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */ +-- +2.5.0 + diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2016.11/cyclone5-socdk.env b/bsp/meta-altera/recipes-bsp/u-boot/files/v2016.11/cyclone5-socdk.env new file mode 100644 index 00000000..15c329fe --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2016.11/cyclone5-socdk.env @@ -0,0 +1,11 @@ +baudrate=115200 +bootargs=console=ttyS0,115200 +bootcmd=run mmcload; run mmcboot +fdtimage=socfpga_cyclone5_socdk.dtb +bootimage=zImage +fdt_addr=100 +loadaddr=0x01000000 +mmcboot=setenv bootargs console=ttyS0,115200 root=${mmcroot} rw rootwait;bootz ${loadaddr} - ${fdt_addr} +mmcload=mmc rescan;load mmc 0:1 ${loadaddr} ${bootimage};load mmc 0:1 ${fdt_addr} ${fdtimage} +mmcroot=/dev/mmcblk0p3 +ramboot=setenv bootargs console=ttyS0,115200;bootm ${loadaddr} - ${fdt_addr} diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2016.11/de0-nano-soc.env b/bsp/meta-altera/recipes-bsp/u-boot/files/v2016.11/de0-nano-soc.env new file mode 100644 index 00000000..b7d69cbe --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2016.11/de0-nano-soc.env @@ -0,0 +1,11 @@ +baudrate=115200 +bootargs=console=ttyS0,115200 +bootcmd=run mmcload; run mmcboot +fdtimage=socfpga_cyclone5_de0_sockit.dtb +bootimage=zImage +fdt_addr=100 +loadaddr=0x01000000 +mmcboot=setenv bootargs console=ttyS0,115200 root=${mmcroot} rw rootwait;bootz ${loadaddr} - ${fdt_addr} +mmcload=mmc rescan;load mmc 0:1 ${loadaddr} ${bootimage};load mmc 0:1 ${fdt_addr} ${fdtimage} +mmcroot=/dev/mmcblk0p3 +ramboot=setenv bootargs console=ttyS0,115200;bootm ${loadaddr} - ${fdt_addr} diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2017.07/cyclone5-socdk.env b/bsp/meta-altera/recipes-bsp/u-boot/files/v2017.07/cyclone5-socdk.env new file mode 100644 index 00000000..15c329fe --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2017.07/cyclone5-socdk.env @@ -0,0 +1,11 @@ +baudrate=115200 +bootargs=console=ttyS0,115200 +bootcmd=run mmcload; run mmcboot +fdtimage=socfpga_cyclone5_socdk.dtb +bootimage=zImage +fdt_addr=100 +loadaddr=0x01000000 +mmcboot=setenv bootargs console=ttyS0,115200 root=${mmcroot} rw rootwait;bootz ${loadaddr} - ${fdt_addr} +mmcload=mmc rescan;load mmc 0:1 ${loadaddr} ${bootimage};load mmc 0:1 ${fdt_addr} ${fdtimage} +mmcroot=/dev/mmcblk0p3 +ramboot=setenv bootargs console=ttyS0,115200;bootm ${loadaddr} - ${fdt_addr} diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2017.07/de0-nano-soc.env b/bsp/meta-altera/recipes-bsp/u-boot/files/v2017.07/de0-nano-soc.env new file mode 100644 index 00000000..b7d69cbe --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2017.07/de0-nano-soc.env @@ -0,0 +1,11 @@ +baudrate=115200 +bootargs=console=ttyS0,115200 +bootcmd=run mmcload; run mmcboot +fdtimage=socfpga_cyclone5_de0_sockit.dtb +bootimage=zImage +fdt_addr=100 +loadaddr=0x01000000 +mmcboot=setenv bootargs console=ttyS0,115200 root=${mmcroot} rw rootwait;bootz ${loadaddr} - ${fdt_addr} +mmcload=mmc rescan;load mmc 0:1 ${loadaddr} ${bootimage};load mmc 0:1 ${fdt_addr} ${fdtimage} +mmcroot=/dev/mmcblk0p3 +ramboot=setenv bootargs console=ttyS0,115200;bootm ${loadaddr} - ${fdt_addr} diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch new file mode 100644 index 00000000..e954ac07 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch @@ -0,0 +1,30 @@ +From 45dd1ac82881153c73bd4243cd20f3b13955ad21 Mon Sep 17 00:00:00 2001 +From: Chee Hong Ang <chee.hong.ang@intel.com> +Date: Sat, 11 May 2019 00:09:46 +0800 +Subject: [PATCH] ARM: socfpga: Stratix10: Disable CONFIG_PSCI_RESET + +Avoid invoking 'SYSTEM_RESET' PSCI function because PSCI +function calls are not supported in u-boot running in EL3. + +Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> +--- + arch/arm/cpu/armv8/Kconfig | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig +index 7405c3a4a1..409ee7ada0 100644 +--- a/arch/arm/cpu/armv8/Kconfig ++++ b/arch/arm/cpu/armv8/Kconfig +@@ -108,7 +108,8 @@ config PSCI_RESET + !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ + !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ + !TARGET_LX2160AQDS && \ +- !ARCH_UNIPHIER && !TARGET_S32V234EVB ++ !ARCH_UNIPHIER && !TARGET_S32V234EVB && \ ++ !TARGET_SOCFPGA_STRATIX10 + help + Most armv8 systems have PSCI support enabled in EL3, either through + ARM Trusted Firmware or other firmware. +-- +2.13.0 + diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-stratix10-Enable-PSCI-system-reset.patch b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-stratix10-Enable-PSCI-system-reset.patch new file mode 100644 index 00000000..a4b78573 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-stratix10-Enable-PSCI-system-reset.patch @@ -0,0 +1,59 @@ +From 97f599b2a7b34d17067b4ccf6c468cdcc6805349 Mon Sep 17 00:00:00 2001 +From: "Ang, Chee Hong" <chee.hong.ang@intel.com> +Date: Mon, 29 Apr 2019 23:35:30 -0700 +Subject: [PATCH 01/12] ARM: socfpga: stratix10: Enable PSCI system reset + +Enable psci_system_reset support for Stratix10. This PSCI function +will eventually trigger the mailbox HPS_REBOOT to SDM. + +Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> +--- + arch/arm/mach-socfpga/Makefile | 3 +++ + arch/arm/mach-socfpga/psci.c | 21 +++++++++++++++++++++ + 2 files changed, 24 insertions(+) + create mode 100644 arch/arm/mach-socfpga/psci.c + +diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile +index e66720447f..f77b229a38 100644 +--- a/arch/arm/mach-socfpga/Makefile ++++ b/arch/arm/mach-socfpga/Makefile +@@ -38,6 +38,9 @@ obj-y += system_manager_s10.o + obj-y += timer_s10.o + obj-y += wrap_pinmux_config_s10.o + obj-y += wrap_pll_config_s10.o ++ifndef CONFIG_SPL_BUILD ++obj-$(CONFIG_ARMV8_PSCI) += psci.o ++endif + endif + + ifdef CONFIG_SPL_BUILD +diff --git a/arch/arm/mach-socfpga/psci.c b/arch/arm/mach-socfpga/psci.c +new file mode 100644 +index 0000000000..9ef393110d +--- /dev/null ++++ b/arch/arm/mach-socfpga/psci.c +@@ -0,0 +1,21 @@ ++/* ++ * Copyright (C) 2017 Intel Corporation <www.intel.com> ++ * ++ * SPDX-License-Identifier: GPL-2.0 ++ */ ++ ++#include <common.h> ++#include <asm/io.h> ++#include <asm/psci.h> ++#include <errno.h> ++#include <asm/arch/mailbox_s10.h> ++#include <asm/secure.h> ++ ++void __noreturn __secure psci_system_reset(void) ++{ ++ mbox_send_cmd_psci(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, ++ MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL); ++ ++ while (1) ++ ; ++} +-- +2.21.0 + diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0002-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0002-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch new file mode 100644 index 00000000..ebf6fe7e --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0002-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch @@ -0,0 +1,67 @@ +From 257cff780ec1a50600a77cf361df27746801d684 Mon Sep 17 00:00:00 2001 +From: "Ang, Chee Hong" <chee.hong.ang@intel.com> +Date: Mon, 14 Jan 2019 01:07:50 -0800 +Subject: [PATCH 02/12] ARM: socfpga: stratix10: Enable PSCI CPU_ON + +Enable psci_cpu_on support for Stratix10. This PSCI function +will pass the cpu release address for CPU1-CPU3. Then send event +signal shall be triggered to get these CPUs running Linux code. + +Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> +--- + arch/arm/mach-socfpga/psci.c | 35 +++++++++++++++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + +diff --git a/arch/arm/mach-socfpga/psci.c b/arch/arm/mach-socfpga/psci.c +index 9ef393110d..0af3eb195c 100644 +--- a/arch/arm/mach-socfpga/psci.c ++++ b/arch/arm/mach-socfpga/psci.c +@@ -11,6 +11,9 @@ + #include <asm/arch/mailbox_s10.h> + #include <asm/secure.h> + ++static u64 psci_cpu_on_64_cpuid __secure_data; ++static u64 psci_cpu_on_64_entry_point __secure_data; ++ + void __noreturn __secure psci_system_reset(void) + { + mbox_send_cmd_psci(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, +@@ -19,3 +22,35 @@ void __noreturn __secure psci_system_reset(void) + while (1) + ; + } ++ ++/* This function will handle multiple core release based PSCI */ ++void __secure psci_cpu_on_64_mpidr(void) ++{ ++ asm volatile( ++ ".align 5 \n" ++ "1: wfe \n" ++ " ldr x0, [%0] \n" ++ " ldr x1, [%1] \n" ++ " mrs x2, mpidr_el1 \n" ++ " and x2, x2, #0xff \n" ++ " cmp x0, x2 \n" ++ " b.ne 1b \n" ++ " br x1 \n" ++ : : "r"(&psci_cpu_on_64_cpuid), "r"(&psci_cpu_on_64_entry_point) ++ : "x0", "x1", "x2", "memory", "cc"); ++} ++ ++int __secure psci_cpu_on_64(u32 function_id, u64 cpuid, u64 entry_point) ++{ ++ /* Releases all secondary CPUs to jump into psci_cpu_on_64_mpidr */ ++ writeq(0, &psci_cpu_on_64_cpuid); ++ writeq(0, &psci_cpu_on_64_entry_point); ++ writeq((u64)&psci_cpu_on_64_mpidr, CPU_RELEASE_ADDR); ++ ++ /* to store in global so psci_cpu_on_64_mpidr function can refer */ ++ writeq(entry_point, &psci_cpu_on_64_entry_point); ++ writeq(cpuid, &psci_cpu_on_64_cpuid); ++ asm volatile("sev"); ++ ++ return ARM_PSCI_RET_SUCCESS; ++} +-- +2.21.0 + diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0003-ARM-socfpga-stratix10-Enable-PSCI-support-for-Strati.patch b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0003-ARM-socfpga-stratix10-Enable-PSCI-support-for-Strati.patch new file mode 100644 index 00000000..ed60cc0f --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0003-ARM-socfpga-stratix10-Enable-PSCI-support-for-Strati.patch @@ -0,0 +1,45 @@ +From 504f8bd14f703bfb2ffd5dccac7126d5fd22e0d1 Mon Sep 17 00:00:00 2001 +From: "Ang, Chee Hong" <chee.hong.ang@intel.com> +Date: Mon, 29 Apr 2019 23:18:38 -0700 +Subject: [PATCH 03/12] ARM: socfpga: stratix10: Enable PSCI support for + Stratix 10 + +The address of PSCI text, data and stack sections start at +0x00001000 (SDRAM). + +Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> +--- + arch/arm/mach-socfpga/Kconfig | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig +index 48f02f08d4..755bab5dd2 100644 +--- a/arch/arm/mach-socfpga/Kconfig ++++ b/arch/arm/mach-socfpga/Kconfig +@@ -12,6 +12,12 @@ config SPL_SYS_MALLOC_F_LEN + config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE + default 0xa2 + ++config ARMV8_SECURE_BASE ++ default 0x00001000 if TARGET_SOCFPGA_STRATIX10 ++ ++config SYS_HAS_ARMV8_SECURE_BASE ++ default y if TARGET_SOCFPGA_STRATIX10 ++ + config SYS_MALLOC_F_LEN + default 0x2000 if TARGET_SOCFPGA_ARRIA10 + default 0x2000 if TARGET_SOCFPGA_GEN5 +@@ -56,8 +62,9 @@ config TARGET_SOCFPGA_GEN5 + config TARGET_SOCFPGA_STRATIX10 + bool + select ARMV8_MULTIENTRY ++ select ARMV8_PSCI ++ select ARMV8_SEC_FIRMWARE_SUPPORT + select ARMV8_SET_SMPEN +- select ARMV8_SPIN_TABLE + select FPGA_STRATIX10 + + choice +-- +2.21.0 + diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch new file mode 100644 index 00000000..7d307066 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch @@ -0,0 +1,153 @@ +From a859bc214aa913be022a7aa8f03723079a325b07 Mon Sep 17 00:00:00 2001 +From: Chee Hong Ang <chee.hong.ang@intel.com> +Date: Fri, 20 Apr 2018 18:28:07 +0800 +Subject: [PATCH 04/12] ARM: socfpga: stratix10: Enable SMC/PSCI calls from + slave CPUs + +Before this patch, only master CPU (CPU0) is able to +make SMC/PSCI calls to EL3 exception handler. This patch +allow SMC/PSCI calls from slave CPUs (CPU1/2/3) as well. + +Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> +--- + arch/arm/mach-socfpga/Makefile | 1 + + arch/arm/mach-socfpga/lowlevel_init.S | 97 +++++++++++++++++++++++ + include/configs/socfpga_stratix10_socdk.h | 6 ++ + 3 files changed, 104 insertions(+) + create mode 100644 arch/arm/mach-socfpga/lowlevel_init.S + +diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile +index f77b229a38..d34198d159 100644 +--- a/arch/arm/mach-socfpga/Makefile ++++ b/arch/arm/mach-socfpga/Makefile +@@ -29,6 +29,7 @@ obj-y += reset_manager_arria10.o + endif + + ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 ++obj-y += lowlevel_init.o + obj-y += clock_manager_s10.o + obj-y += mailbox_s10.o + obj-y += misc_s10.o +diff --git a/arch/arm/mach-socfpga/lowlevel_init.S b/arch/arm/mach-socfpga/lowlevel_init.S +new file mode 100644 +index 0000000000..832785a682 +--- /dev/null ++++ b/arch/arm/mach-socfpga/lowlevel_init.S +@@ -0,0 +1,97 @@ ++/* ++ * Copyright (C) 2018 Intel Corporation. All rights reserved ++ * ++ * SPDX-License-Identifier: GPL-2.0 ++ */ ++ ++#include <asm-offsets.h> ++#include <config.h> ++#include <linux/linkage.h> ++#include <asm/macro.h> ++ ++#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMV8_PSCI) ++.align 3 ++_el3_exception_vectors: ++ .word el3_exception_vectors; ++ .word 0 ++#endif ++ ++ENTRY(lowlevel_init) ++ mov x29, lr /* Save LR */ ++ ++#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) ++ branch_if_slave x0, 1f ++ ldr x0, =GICD_BASE ++ bl gic_init_secure ++1: ++#if defined(CONFIG_GICV3) ++ ldr x0, =GICR_BASE ++ bl gic_init_secure_percpu ++#elif defined(CONFIG_GICV2) ++ ldr x0, =GICD_BASE ++ ldr x1, =GICC_BASE ++ bl gic_init_secure_percpu ++#endif ++#endif ++ ++#ifdef CONFIG_ARMV8_MULTIENTRY ++ branch_if_master x0, x1, 2f ++ ++ /* ++ * Slave should wait for master clearing spin table. ++ * This sync prevent slaves observing incorrect ++ * value of spin table and jumping to wrong place. ++ */ ++#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) ++#ifdef CONFIG_GICV2 ++ ldr x0, =GICC_BASE ++#endif ++ bl gic_wait_for_interrupt ++#endif ++ ++#ifdef CONFIG_SPL_BUILD ++ /* ++ * Read the u-boot's PSCI exception handler's vector base ++ * address from the sysmgr.boot_scratch_cold6 & 7 and update ++ * their VBAR_EL3 respectively. ++ */ ++wait_vbar_el3: ++ ldr x4, =VBAR_EL3_BASE_ADDR ++ ldr x5, [x4] ++ cbz x5, wait_vbar_el3 ++ msr vbar_el3, x5 ++#endif ++ /* ++ * All slaves will enter EL2 and optionally EL1. ++ */ ++ adr x4, lowlevel_in_el2 ++ ldr x5, =ES_TO_AARCH64 ++ bl armv8_switch_to_el2 ++ ++lowlevel_in_el2: ++#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 ++ adr x4, lowlevel_in_el1 ++ ldr x5, =ES_TO_AARCH64 ++ bl armv8_switch_to_el1 ++ ++lowlevel_in_el1: ++#endif ++ ++#endif /* CONFIG_ARMV8_MULTIENTRY */ ++ ++2: ++#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMV8_PSCI) ++ /* ++ * Write the u-boot PSCI exception handler's vector base address ++ * into a sysmgr.boot_scratch_cold6 & 7 so that other slave cpus ++ * are able to get the vector base address and update their VBAR_EL3 ++ * respectively. ++ */ ++ adr x0, _el3_exception_vectors ++ ldr x5, [x0] ++ ldr x4, =VBAR_EL3_BASE_ADDR ++ str x5, [x4] ++#endif ++ mov lr, x29 /* Restore LR */ ++ ret ++ENDPROC(lowlevel_init) +diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h +index 8d2971c6e2..39d757d737 100644 +--- a/include/configs/socfpga_stratix10_socdk.h ++++ b/include/configs/socfpga_stratix10_socdk.h +@@ -19,6 +19,12 @@ + #define CONFIG_REMAKE_ELF + /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ + #define CPU_RELEASE_ADDR 0xFFD12210 ++/* ++ * sysmgr.boot_scratch_cold6 & 7 (64bit) will be used by master CPU to ++ * store its VBAR_EL3 value. Other slave CPUs will read from this ++ * location and update their VBAR_EL3 respectively ++ */ ++#define VBAR_EL3_BASE_ADDR 0xFFD12218 + #define CONFIG_SYS_CACHELINE_SIZE 64 + #define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */ + +-- +2.21.0 + diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0005-ARM-socfpga-stratix10-Add-SOCFPGA-bridges-reset-supp.patch b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0005-ARM-socfpga-stratix10-Add-SOCFPGA-bridges-reset-supp.patch new file mode 100644 index 00000000..fd43dd24 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0005-ARM-socfpga-stratix10-Add-SOCFPGA-bridges-reset-supp.patch @@ -0,0 +1,102 @@ +From 16460c05fe576050cf485282151fd5623d6e862a Mon Sep 17 00:00:00 2001 +From: Dalon Westergreen <dalon.westergreen@intel.com> +Date: Wed, 22 May 2019 17:05:12 -0700 +Subject: [PATCH 05/12] ARM: socfpga: stratix10: Add SOCFPGA bridges reset + support for PSCI call + +Add SOCFPGA bridges reset support for FPGA configuration SMC services +to disable/enable the bridges before and after the FPGA configuration +process. + +Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> +Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> +--- + .../include/mach/reset_manager_s10.h | 1 + + arch/arm/mach-socfpga/reset_manager_s10.c | 25 ++++++++++++++++++- + 2 files changed, 25 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h +index 452147b017..1939ffa149 100644 +--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h ++++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h +@@ -11,6 +11,7 @@ void reset_cpu(ulong addr); + int cpu_has_been_warmreset(void); + + void socfpga_bridges_reset(int enable); ++void socfpga_bridges_reset_psci(int enable); + + void socfpga_per_reset(u32 reset, int set); + void socfpga_per_reset_all(void); +diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c +index 499a84aff5..4494f6666f 100644 +--- a/arch/arm/mach-socfpga/reset_manager_s10.c ++++ b/arch/arm/mach-socfpga/reset_manager_s10.c +@@ -9,6 +9,7 @@ + #include <asm/arch/reset_manager.h> + #include <asm/arch/system_manager.h> + #include <dt-bindings/reset/altr,rst-mgr-s10.h> ++#include <asm/secure.h> + + DECLARE_GLOBAL_DATA_PTR; + +@@ -20,6 +21,8 @@ static const struct socfpga_system_manager *system_manager_base = + /* Assert or de-assert SoCFPGA reset manager reset. */ + void socfpga_per_reset(u32 reset, int set) + { ++ static const struct socfpga_reset_manager *reset_manager_base = ++ (void *)SOCFPGA_RSTMGR_ADDRESS; + const void *reg; + + if (RSTMGR_BANK(reset) == 0) +@@ -46,6 +49,8 @@ void socfpga_per_reset(u32 reset, int set) + */ + void socfpga_per_reset_all(void) + { ++ static const struct socfpga_reset_manager *reset_manager_base = ++ (void *)SOCFPGA_RSTMGR_ADDRESS; + const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); + + /* disable all except OCP and l4wd0. OCP disable later */ +@@ -55,8 +60,13 @@ void socfpga_per_reset_all(void) + writel(0xffffffff, &reset_manager_base->per1modrst); + } + +-void socfpga_bridges_reset(int enable) ++static __always_inline void __socfpga_bridges_reset(int enable) + { ++ static const struct socfpga_reset_manager *reset_manager_base = ++ (void *)SOCFPGA_RSTMGR_ADDRESS; ++ static const struct socfpga_system_manager *system_manager_base = ++ (void *)SOCFPGA_SYSMGR_ADDRESS; ++ + if (enable) { + /* clear idle request to all bridges */ + setbits_le32(&system_manager_base->noc_idlereq_clr, ~0); +@@ -94,11 +104,24 @@ void socfpga_bridges_reset(int enable) + } + } + ++void socfpga_bridges_reset(int enable) ++{ ++ __socfpga_bridges_reset(enable); ++} ++ ++void __secure socfpga_bridges_reset_psci(int enable) ++{ ++ __socfpga_bridges_reset(enable); ++} ++ + /* + * Return non-zero if the CPU has been warm reset + */ + int cpu_has_been_warmreset(void) + { ++ static const struct socfpga_reset_manager *reset_manager_base = ++ (void *)SOCFPGA_RSTMGR_ADDRESS; ++ + return readl(&reset_manager_base->status) & + RSTMGR_L4WD_MPU_WARMRESET_MASK; + } +-- +2.21.0 + diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0006-ARM-socfpga-stratix10-Add-Stratix10-FPGA-configurati.patch b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0006-ARM-socfpga-stratix10-Add-Stratix10-FPGA-configurati.patch new file mode 100644 index 00000000..cc0be27b --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0006-ARM-socfpga-stratix10-Add-Stratix10-FPGA-configurati.patch @@ -0,0 +1,833 @@ +From 04187fba93e6d359ebb4dd8e397dff282f53ec5a Mon Sep 17 00:00:00 2001 +From: "Ang, Chee Hong" <chee.hong.ang@intel.com> +Date: Mon, 29 Apr 2019 23:42:39 -0700 +Subject: [PATCH 06/12] ARM: socfpga: stratix10: Add Stratix10 FPGA + configuration PSCI services + +Allow PSCI layer to handle the S10 FPGA configuration (SiP) service +calls. All these services are also known as FPGA configuration service +layer for S10. This service layer support FPGA configuration service +requests from OS (EL1). It acts as the middle layer between SDM +(Secure Device Manager) and the OS. It enables OS (EL1) to invoke SMC +call to this service layer (EL3) and pass the FPGA bit stream to SDM +for FPGA configuration. + +Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> +--- + arch/arm/mach-socfpga/Makefile | 1 + + arch/arm/mach-socfpga/include/mach/smc_s10.h | 42 ++ + arch/arm/mach-socfpga/smc_fpga_reconfig_s10.c | 422 ++++++++++++++++++ + include/linux/intel-smc.h | 311 +++++++++++++ + 4 files changed, 776 insertions(+) + create mode 100644 arch/arm/mach-socfpga/include/mach/smc_s10.h + create mode 100644 arch/arm/mach-socfpga/smc_fpga_reconfig_s10.c + create mode 100644 include/linux/intel-smc.h + +diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile +index d34198d159..88970e7555 100644 +--- a/arch/arm/mach-socfpga/Makefile ++++ b/arch/arm/mach-socfpga/Makefile +@@ -41,6 +41,7 @@ obj-y += wrap_pinmux_config_s10.o + obj-y += wrap_pll_config_s10.o + ifndef CONFIG_SPL_BUILD + obj-$(CONFIG_ARMV8_PSCI) += psci.o ++obj-$(CONFIG_FPGA_STRATIX10) += smc_fpga_reconfig_s10.o + endif + endif + +diff --git a/arch/arm/mach-socfpga/include/mach/smc_s10.h b/arch/arm/mach-socfpga/include/mach/smc_s10.h +new file mode 100644 +index 0000000000..9c82d863e5 +--- /dev/null ++++ b/arch/arm/mach-socfpga/include/mach/smc_s10.h +@@ -0,0 +1,42 @@ ++/* ++ * Copyright (C) 2018 Intel Corporation. All rights reserved ++ * ++ * SPDX-License-Identifier: GPL-2.0 ++ */ ++ ++#include <common.h> ++ ++#define SMC_ARG0 0 ++#define SMC_ARG1 (SMC_ARG0 + 1) ++#define SMC_ARG2 (SMC_ARG1 + 1) ++#define SMC_ARG3 (SMC_ARG2 + 1) ++#define SMC_RETURN_ARGS_MAX (SMC_ARG3 + 1) ++ ++/* Macro functions for allocation and read/write of ++ variables to be assigned to registers */ ++/* Allocate memory for variable */ ++#define SMC_ALLOC_REG_MEM(var) unsigned long var[SMC_RETURN_ARGS_MAX] ++/* Clear variable */ ++#define SMC_INIT_REG_MEM(var) \ ++ do { \ ++ int i; \ ++ for (i = 0; i < SMC_RETURN_ARGS_MAX; i++) \ ++ var[i] = 0; \ ++ } while (0) ++/* Read variable */ ++#define SMC_GET_REG_MEM(var, i) var[i] ++/* Write Variable */ ++#define SMC_ASSIGN_REG_MEM(var, i, val) \ ++ do { \ ++ var[i] = (val); \ ++ } while (0) ++/* Assign variables back to registers */ ++#define SMC_RET_REG_MEM(var) \ ++ do { \ ++ asm volatile("ldr x0, %0\n" \ ++ "ldr x1, %1\n" \ ++ "ldr x2, %2\n" \ ++ "ldr x3, %3\n" \ ++ : : "m" (var[0]), "m" (var[1]), \ ++ "m" (var[2]), "m" (var[3]) : ); \ ++ } while (0) +diff --git a/arch/arm/mach-socfpga/smc_fpga_reconfig_s10.c b/arch/arm/mach-socfpga/smc_fpga_reconfig_s10.c +new file mode 100644 +index 0000000000..0ed12e16b4 +--- /dev/null ++++ b/arch/arm/mach-socfpga/smc_fpga_reconfig_s10.c +@@ -0,0 +1,422 @@ ++/* ++ * Copyright (C) 2018 Intel Corporation. All rights reserved ++ * ++ * SPDX-License-Identifier: GPL-2.0 ++ */ ++ ++#include <common.h> ++#include <errno.h> ++#include <asm/io.h> ++#include <asm/psci.h> ++#include <asm/secure.h> ++#include <asm/arch/mailbox_s10.h> ++#include <asm/arch/smc_s10.h> ++#include <linux/intel-smc.h> ++#include <asm/arch/reset_manager.h> ++ ++/* Start of reserved memory */ ++#define FPGA_CONFIG_RESEVED_MEM_START (CONFIG_SYS_SDRAM_BASE + \ ++ 0x400000) ++/* End of reserved memory */ ++#define FPGA_CONFIG_RESERVED_MEM_END (CONFIG_SYS_SDRAM_BASE + \ ++ 0xFFFFFF) ++ ++#define FPGA_CONFIG_BUF_MAX 16 ++ ++#define FPGA_BUF_STAT_IDLE 0 ++#define FPGA_BUF_STAT_PENDING 1 ++#define FPGA_BUF_STAT_COMPLETED 2 ++#define FPGA_BUF_STAT_SUCCESS 3 ++#define FPGA_BUF_STAT_ERROR 4 ++ ++#define IS_BUF_FREE(x) (x.state == FPGA_BUF_STAT_IDLE) ++#define IS_BUF_PENDING(x) (x.state == FPGA_BUF_STAT_PENDING) ++#define IS_BUF_SUBMITTED(x) (x.state >= FPGA_BUF_STAT_PENDING && \ ++ x.submit_count > 0) ++#define IS_BUF_COMPLETED(x) (x.state == FPGA_BUF_STAT_COMPLETED && \ ++ x.submit_count > 0) ++#define IS_BUF_FULLY_COMPLETED(x) (x.state == FPGA_BUF_STAT_COMPLETED && \ ++ x.submit_count == 0) ++#define IS_BUF_SUCCESS(x) (x.state == FPGA_BUF_STAT_SUCCESS) ++#define IS_BUF_ERROR(x) (x.state == FPGA_BUF_STAT_ERROR) ++ ++static __secure_data struct fpga_buf_list { ++ u32 state; ++ u32 buf_id; ++ u64 buf_addr; ++ u64 buf_size; ++ u32 buf_off; ++ u32 submit_count; ++} fpga_buf_list[FPGA_CONFIG_BUF_MAX]; ++ ++static u8 __secure_data fpga_error = 1; ++static u8 __secure_data is_partial_reconfig; ++static u8 __secure_data fpga_buf_id = 1; ++static u32 __secure_data fpga_xfer_max = 4; ++static u32 __secure_data fpga_buf_read_index; ++static u32 __secure_data fpga_buf_write_index; ++static u32 __secure_data fpga_buf_count; ++/* 20bits DMA size with 8 bytes alignment */ ++static u32 __secure_data fpga_buf_size_max = 0xFFFF8; ++/* Number of data blocks received from OS(EL1) */ ++static u32 __secure_data fpga_buf_rcv_count; ++/* Number of data blocks submitted to SDM */ ++static u32 __secure_data fpga_xfer_submitted_count; ++ ++/* Check for any responses from SDM and update the status in buffer list */ ++static void __secure reclaim_completed_buf(void) ++{ ++ u32 i, j; ++ u32 resp_len; ++ u32 buf[MBOX_RESP_BUFFER_SIZE]; ++ ++ /* If no buffer has been submitted to SDM */ ++ if (!fpga_xfer_submitted_count) ++ return; ++ ++ /* Read the SDM responses asynchronously */ ++ resp_len = mbox_rcv_resp_psci(buf, MBOX_RESP_BUFFER_SIZE); ++ ++ for (i = 0; i < resp_len; i++) { ++ /* Skip mailbox response headers which are not belong to us */ ++ if (MBOX_RESP_LEN_GET(buf[i]) || ++ MBOX_RESP_CLIENT_GET(buf[i]) != MBOX_CLIENT_ID_UBOOT) ++ continue; ++ ++ for (j = 0; j < FPGA_CONFIG_BUF_MAX; j++) { ++ /* Check buffer id */ ++ if (fpga_buf_list[j].buf_id != ++ MBOX_RESP_ID_GET(buf[i])) ++ continue; ++ ++ if (IS_BUF_SUBMITTED(fpga_buf_list[j])) { ++ if (fpga_buf_list[j].submit_count) ++ fpga_buf_list[j].submit_count--; ++ fpga_xfer_submitted_count--; ++ /* Error occur in transaction */ ++ if (MBOX_RESP_ERR_GET(buf[i])) { ++ fpga_error = 1; ++ fpga_buf_list[j].state = ++ FPGA_BUF_STAT_ERROR; ++ fpga_buf_list[j].submit_count = 0; ++ } else if (IS_BUF_FULLY_COMPLETED( ++ fpga_buf_list[j])) { ++ /* Last chunk in buffer and no error */ ++ fpga_buf_list[j].state = ++ FPGA_BUF_STAT_SUCCESS; ++ } ++ break; ++ } else if (IS_BUF_ERROR(fpga_buf_list[j])) { ++ fpga_xfer_submitted_count--; ++ break; ++ } ++ } ++ } ++} ++ ++static void __secure do_xfer_buf(void) ++{ ++ u32 i = fpga_buf_read_index; ++ u32 args[3]; ++ int ret; ++ ++ /* No buffer found in buffer list or SDM can't handle xfer anymore */ ++ if (!fpga_buf_rcv_count || ++ fpga_xfer_submitted_count == fpga_xfer_max) ++ return; ++ ++ while (fpga_xfer_submitted_count < fpga_xfer_max) { ++ if (IS_BUF_FREE(fpga_buf_list[i]) || ++ IS_BUF_ERROR(fpga_buf_list[i])) ++ break; ++ if (IS_BUF_PENDING(fpga_buf_list[i])) { ++ /* ++ * Argument descriptor for RECONFIG_DATA ++ * must always be 1. ++ */ ++ args[0] = MBOX_ARG_DESC_COUNT(1); ++ args[1] = (u32)(fpga_buf_list[i].buf_addr + ++ fpga_buf_list[i].buf_off); ++ if ((fpga_buf_list[i].buf_size - ++ fpga_buf_list[i].buf_off) > fpga_buf_size_max) { ++ args[2] = fpga_buf_size_max; ++ fpga_buf_list[i].buf_off += fpga_buf_size_max; ++ } else { ++ args[2] = (u32)(fpga_buf_list[i].buf_size - ++ fpga_buf_list[i].buf_off); ++ fpga_buf_list[i].state = ++ FPGA_BUF_STAT_COMPLETED; ++ } ++ ++ ret = mbox_send_cmd_only_psci(fpga_buf_list[i].buf_id, ++ MBOX_RECONFIG_DATA, MBOX_CMD_INDIRECT, 3, ++ args); ++ if (ret) { ++ fpga_error = 1; ++ fpga_buf_list[i].state = ++ FPGA_BUF_STAT_ERROR; ++ fpga_buf_list[i].submit_count = 0; ++ break; ++ } else { ++ fpga_buf_list[i].submit_count++; ++ fpga_xfer_submitted_count++; ++ } ++ ++ if (fpga_xfer_submitted_count >= fpga_xfer_max) ++ break; ++ } ++ ++ if (IS_BUF_COMPLETED(fpga_buf_list[i]) || ++ IS_BUF_SUCCESS(fpga_buf_list[i])) { ++ i++; ++ i %= FPGA_CONFIG_BUF_MAX; ++ if (i == fpga_buf_write_index) ++ break; ++ } ++ } ++} ++ ++static void __secure smc_config_get_mem(unsigned long function_id) ++{ ++ SMC_ALLOC_REG_MEM(r); ++ ++ SMC_INIT_REG_MEM(r); ++ ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG0, INTEL_SIP_SMC_STATUS_OK); ++ /* Start physical address of reserved memory */ ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG1, FPGA_CONFIG_RESEVED_MEM_START); ++ /* Size of reserved memory */ ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG2, FPGA_CONFIG_RESERVED_MEM_END - ++ FPGA_CONFIG_RESEVED_MEM_START + 1); ++ ++ SMC_RET_REG_MEM(r); ++} ++ ++static void __secure smc_config_start(unsigned long function_id, ++ unsigned long config_type) ++{ ++ SMC_ALLOC_REG_MEM(r); ++ int ret, i; ++ u32 resp_len = 2; ++ u32 resp_buf[2]; ++ ++ /* Clear any previous pending SDM reponses */ ++ mbox_rcv_resp_psci(NULL, MBOX_RESP_BUFFER_SIZE); ++ ++ SMC_INIT_REG_MEM(r); ++ ++ fpga_error = 0; ++ ++ ret = mbox_send_cmd_psci(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, ++ 0, NULL, 0, &resp_len, resp_buf); ++ if (ret) { ++ fpga_error = 1; ++ goto ret; ++ } ++ ++ /* Initialize the state of the buffer list */ ++ for (i = 0; i < FPGA_CONFIG_BUF_MAX; i++) { ++ fpga_buf_list[i].state = FPGA_BUF_STAT_IDLE; ++ fpga_buf_list[i].buf_id = 0; ++ } ++ ++ /* Read maximum transaction allowed by SDM */ ++ fpga_xfer_max = resp_buf[0]; ++ /* Read maximum buffer size allowed by SDM */ ++ fpga_buf_size_max = resp_buf[1]; ++ fpga_buf_count = 0; ++ fpga_buf_rcv_count = 0; ++ fpga_xfer_submitted_count = 0; ++ fpga_buf_read_index = 0; ++ fpga_buf_write_index = 0; ++ fpga_buf_id = 1; ++ ++ is_partial_reconfig = (u8)config_type; ++ ++ /* Check whether config type is full reconfiguration */ ++ if (!is_partial_reconfig) { ++ /* Disable bridge */ ++ socfpga_bridges_reset_psci(0); ++ } ++ ++ret: ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG0, INTEL_SIP_SMC_STATUS_OK); ++ ++ SMC_RET_REG_MEM(r); ++} ++ ++static void __secure smc_config_write(unsigned long function_id, ++ unsigned long phys_addr, ++ unsigned long phys_size) ++{ ++ SMC_ALLOC_REG_MEM(r); ++ ++ SMC_INIT_REG_MEM(r); ++ ++ reclaim_completed_buf(); ++ ++ if (fpga_error) { ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG0, ++ INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR); ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG1, ++ fpga_buf_list[fpga_buf_read_index]. ++ buf_addr); ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG2, ++ fpga_buf_list[fpga_buf_read_index]. ++ buf_size); ++ goto ret; ++ } ++ ++ do_xfer_buf(); ++ ++ if (fpga_buf_rcv_count == fpga_xfer_max || ++ (fpga_buf_count == FPGA_CONFIG_BUF_MAX && ++ fpga_buf_write_index == fpga_buf_read_index)) { ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG0, ++ INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED); ++ goto ret; ++ } ++ ++ if (!phys_addr || !phys_size) { ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG0, ++ INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR); ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG1, phys_addr); ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG2, phys_size); ++ goto ret; ++ } ++ ++ /* Look for free buffer in buffer list */ ++ if (IS_BUF_FREE(fpga_buf_list[fpga_buf_write_index])) { ++ fpga_buf_list[fpga_buf_write_index].state = ++ FPGA_BUF_STAT_PENDING; ++ fpga_buf_list[fpga_buf_write_index].buf_addr = phys_addr; ++ fpga_buf_list[fpga_buf_write_index].buf_size = phys_size; ++ fpga_buf_list[fpga_buf_write_index].buf_off = 0; ++ fpga_buf_list[fpga_buf_write_index].buf_id = fpga_buf_id++; ++ /* Rollover buffer id */ ++ if (fpga_buf_id > 15) ++ fpga_buf_id = 1; ++ fpga_buf_count++; ++ fpga_buf_write_index++; ++ fpga_buf_write_index %= FPGA_CONFIG_BUF_MAX; ++ fpga_buf_rcv_count++; ++ if (fpga_buf_rcv_count == fpga_xfer_max) ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG0, ++ INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY); ++ else ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG0, ++ INTEL_SIP_SMC_STATUS_OK); ++ /* Attempt to submit new buffer to SDM */ ++ do_xfer_buf(); ++ } else { ++ /* No free buffer available in buffer list */ ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG0, ++ INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED); ++ } ++ ++ret: ++ SMC_RET_REG_MEM(r); ++} ++ ++static void __secure smc_config_completed_write(unsigned long function_id) ++{ ++ SMC_ALLOC_REG_MEM(r); ++ int i; ++ int count = 3, r_index = 1; ++ ++ SMC_INIT_REG_MEM(r); ++ ++ reclaim_completed_buf(); ++ do_xfer_buf(); ++ ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG0, ++ INTEL_SIP_SMC_STATUS_OK); ++ ++ for (i = 0; i < FPGA_CONFIG_BUF_MAX; i++) { ++ if (IS_BUF_SUCCESS(fpga_buf_list[fpga_buf_read_index])) { ++ SMC_ASSIGN_REG_MEM(r, r_index++, ++ fpga_buf_list[fpga_buf_read_index].buf_addr); ++ fpga_buf_list[fpga_buf_read_index].state = ++ FPGA_BUF_STAT_IDLE; ++ fpga_buf_list[fpga_buf_read_index].buf_id = 0; ++ fpga_buf_count--; ++ fpga_buf_read_index++; ++ fpga_buf_read_index %= FPGA_CONFIG_BUF_MAX; ++ fpga_buf_rcv_count--; ++ count--; ++ if (!count) ++ break; ++ } else if (IS_BUF_ERROR(fpga_buf_list[fpga_buf_read_index]) && ++ !fpga_buf_list[fpga_buf_read_index].submit_count) { ++ SMC_INIT_REG_MEM(r); ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG0, ++ INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR); ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG1, ++ fpga_buf_list[fpga_buf_read_index].buf_addr); ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG2, ++ fpga_buf_list[fpga_buf_read_index].buf_size); ++ goto ret; ++ } ++ } ++ ++ /* No completed buffers found */ ++ if (r_index == 1 && fpga_xfer_submitted_count) ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG0, ++ INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY); ++ ++ret: ++ SMC_RET_REG_MEM(r); ++} ++ ++static void __secure smc_config_isdone(unsigned long function_id) ++{ ++ SMC_ALLOC_REG_MEM(r); ++ int ret; ++ ++ SMC_INIT_REG_MEM(r); ++ ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG0, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY); ++ ++ reclaim_completed_buf(); ++ do_xfer_buf(); ++ ++ if (fpga_error) { ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG0, ++ INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR); ++ goto ret; ++ } ++ ++ if (fpga_xfer_submitted_count) ++ goto ret; ++ ++ ret = mbox_get_fpga_config_status_psci(MBOX_RECONFIG_STATUS); ++ if (ret) { ++ if (ret != MBOX_CFGSTAT_STATE_CONFIG) { ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG0, ++ INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR); ++ fpga_error = 1; ++ } ++ goto ret; ++ } ++ ++ /* FPGA configuration completed successfully */ ++ SMC_ASSIGN_REG_MEM(r, SMC_ARG0, INTEL_SIP_SMC_STATUS_OK); ++ ++ /* Check whether config type is full reconfiguration */ ++ if (!is_partial_reconfig) ++ socfpga_bridges_reset_psci(1); /* Enable bridge */ ++ret: ++ SMC_RET_REG_MEM(r); ++} ++ ++DECLARE_SECURE_SVC(config_get_mem, INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM, ++ smc_config_get_mem); ++DECLARE_SECURE_SVC(config_start, INTEL_SIP_SMC_FPGA_CONFIG_START, ++ smc_config_start); ++DECLARE_SECURE_SVC(config_write, INTEL_SIP_SMC_FPGA_CONFIG_WRITE, ++ smc_config_write); ++DECLARE_SECURE_SVC(config_completed_write, ++ INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE, ++ smc_config_completed_write); ++DECLARE_SECURE_SVC(config_isdone, INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, ++ smc_config_isdone); +diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h +new file mode 100644 +index 0000000000..5e4c156e42 +--- /dev/null ++++ b/include/linux/intel-smc.h +@@ -0,0 +1,311 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2017-2018, Intel Corporation ++ */ ++ ++#ifndef __INTEL_SMC_H ++#define __INTEL_SMC_H ++ ++#include <linux/arm-smccc.h> ++#include <linux/bitops.h> ++ ++/* ++ * This file defines the Secure Monitor Call (SMC) message protocol used for ++ * service layer driver in normal world (EL1) to communicate with secure ++ * monitor software in Secure Monitor Exception Level 3 (EL3). ++ * ++ * This file is shared with secure firmware (FW) which is out of kernel tree. ++ * ++ * An ARM SMC instruction takes a function identifier and up to 6 64-bit ++ * register values as arguments, and can return up to 4 64-bit register ++ * value. The operation of the secure monitor is determined by the parameter ++ * values passed in through registers. ++ ++ * EL1 and EL3 communicates pointer as physical address rather than the ++ * virtual address. ++ */ ++ ++/* ++ * Functions specified by ARM SMC Calling convention: ++ * ++ * FAST call executes atomic operations, returns when the requested operation ++ * has completed. ++ * STD call starts a operation which can be preempted by a non-secure ++ * interrupt. The call can return before the requested operation has ++ * completed. ++ * ++ * a0..a7 is used as register names in the descriptions below, on arm32 ++ * that translates to r0..r7 and on arm64 to w0..w7. ++ */ ++ ++#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \ ++ ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ ++ ARM_SMCCC_OWNER_SIP, (func_num)) ++ ++#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \ ++ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ ++ ARM_SMCCC_OWNER_SIP, (func_num)) ++ ++/* ++ * Return values in INTEL_SIP_SMC_* call ++ * ++ * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION: ++ * Secure monitor software doesn't recognize the request. ++ * ++ * INTEL_SIP_SMC_STATUS_OK: ++ * FPGA configuration completed successfully, ++ * In case of FPGA configuration write operation, it means secure monitor ++ * software can accept the next chunk of FPGA configuration data. ++ * ++ * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY: ++ * In case of FPGA configuration write operation, it means secure monitor ++ * software is still processing previous data & can't accept the next chunk ++ * of data. Service driver needs to issue ++ * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the ++ * completed block(s). ++ * ++ * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR: ++ * There is error during the FPGA configuration process. ++ * ++ * INTEL_SIP_SMC_REG_ERROR: ++ * There is error during a read or write operation of the protected ++ * registers. ++ */ ++#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF ++#define INTEL_SIP_SMC_STATUS_OK 0x0 ++#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY 0x1 ++#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED 0x2 ++#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR 0x4 ++#define INTEL_SIP_SMC_REG_ERROR 0x5 ++#define INTEL_SIP_SMC_RSU_ERROR 0x7 ++ ++/* ++ * Request INTEL_SIP_SMC_FPGA_CONFIG_START ++ * ++ * Sync call used by service driver at EL1 to request the FPGA in EL3 to ++ * be prepare to receive a new configuration. ++ * ++ * Call register usage: ++ * a0: INTEL_SIP_SMC_FPGA_CONFIG_START. ++ * a1: flag for full or partial configuration ++ * 0 full reconfiguration. ++ * 1 partial reconfiguration. ++ * a2-7: not used. ++ * ++ * Return status: ++ * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. ++ * a1-3: not used. ++ */ ++#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 ++#define INTEL_SIP_SMC_FPGA_CONFIG_START \ ++ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START) ++ ++/* ++ * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE ++ * ++ * Async call used by service driver at EL1 to provide FPGA configuration data ++ * to secure world. ++ * ++ * Call register usage: ++ * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE. ++ * a1: 64bit physical address of the configuration data memory block ++ * a2: Size of configuration data block. ++ * a3-7: not used. ++ * ++ * Return status: ++ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or ++ * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. ++ * a1: 64bit physical address of 1st completed memory block if any completed ++ * block, otherwise zero value. ++ * a2: 64bit physical address of 2nd completed memory block if any completed ++ * block, otherwise zero value. ++ * a3: 64bit physical address of 3rd completed memory block if any completed ++ * block, otherwise zero value. ++ */ ++#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE 2 ++#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE \ ++ INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE) ++ ++/* ++ * Request INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE ++ * ++ * Sync call used by service driver at EL1 to track the completed write ++ * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE ++ * call returns INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY. ++ * ++ * Call register usage: ++ * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE. ++ * a1-7: not used. ++ * ++ * Return status: ++ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or ++ * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. ++ * a1: 64bit physical address of 1st completed memory block. ++ * a2: 64bit physical address of 2nd completed memory block if ++ * any completed block, otherwise zero value. ++ * a3: 64bit physical address of 3rd completed memory block if ++ * any completed block, otherwise zero value. ++ */ ++#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE 3 ++#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE \ ++INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) ++ ++/* ++ * Request INTEL_SIP_SMC_FPGA_CONFIG_ISDONE ++ * ++ * Sync call used by service driver at EL1 to inform secure world that all ++ * data are sent, to check whether or not the secure world had completed ++ * the FPGA configuration process. ++ * ++ * Call register usage: ++ * a0: INTEL_SIP_SMC_FPGA_CONFIG_ISDONE. ++ * a1-7: not used. ++ * ++ * Return status: ++ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or ++ * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. ++ * a1-3: not used. ++ */ ++#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4 ++#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE \ ++ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE) ++ ++/* ++ * Request INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM ++ * ++ * Sync call used by service driver at EL1 to query the physical address of ++ * memory block reserved by secure monitor software. ++ * ++ * Call register usage: ++ * a0:INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM. ++ * a1-7: not used. ++ * ++ * Return status: ++ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. ++ * a1: start of physical address of reserved memory block. ++ * a2: size of reserved memory block. ++ * a3: not used. ++ */ ++#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM 5 ++#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM \ ++ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM) ++ ++/* ++ * Request INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK ++ * ++ * For SMC loop-back mode only, used for internal integration, debugging ++ * or troubleshooting. ++ * ++ * Call register usage: ++ * a0: INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK. ++ * a1-7: not used. ++ * ++ * Return status: ++ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. ++ * a1-3: not used. ++ */ ++#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6 ++#define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \ ++ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK) ++ ++/* ++ * Request INTEL_SIP_SMC_REG_READ ++ * ++ * Read a protected register using SMCCC ++ * ++ * Call register usage: ++ * a0: INTEL_SIP_SMC_REG_READ. ++ * a1: register address. ++ * a2-7: not used. ++ * ++ * Return status: ++ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. ++ * a1: Value in the register ++ * a2-3: not used. ++ */ ++#define INTEL_SIP_SMC_FUNCID_REG_READ 7 ++#define INTEL_SIP_SMC_REG_READ \ ++ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ) ++ ++/* ++ * Request INTEL_SIP_SMC_REG_WRITE ++ * ++ * Write a protected register using SMCCC ++ * ++ * Call register usage: ++ * a0: INTEL_SIP_SMC_REG_WRITE. ++ * a1: register address ++ * a2: value to program into register. ++ * a3-7: not used. ++ * ++ * Return status: ++ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. ++ * a1-3: not used. ++ */ ++#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8 ++#define INTEL_SIP_SMC_REG_WRITE \ ++ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE) ++ ++/* ++ * Request INTEL_SIP_SMC_FUNCID_REG_UPDATE ++ * ++ * Update one or more bits in a protected register using a ++ * read-modify-write operation. ++ * ++ * Call register usage: ++ * a0: INTEL_SIP_SMC_REG_UPDATE. ++ * a1: register address ++ * a2: Write Mask. ++ * a3: Value to write. ++ * a4-7: not used. ++ * ++ * Return status: ++ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. ++ * a1-3: Not used. ++ */ ++#define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9 ++#define INTEL_SIP_SMC_REG_UPDATE \ ++ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_UPDATE) ++ ++/* ++ * Request INTEL_SIP_SMC_RSU_STATUS ++ * ++ * Sync call used by service driver at EL1 to query the RSU status ++ * ++ * Call register usage: ++ * a0 INTEL_SIP_SMC_RSU_STATUS ++ * a1-7 not used ++ * ++ * Return status ++ * a0: Current Image ++ * a1: Last Failing Image ++ * a2: Version [width 32 bit] | State [width 32 bit] ++ * a3: Error details [width 32 bit] | Error location [width 32 bit] ++ * ++ * Or ++ * ++ * a0: INTEL_SIP_SMC_RSU_ERROR ++ */ ++#define INTEL_SIP_SMC_FUNCID_RSU_STATUS 11 ++#define INTEL_SIP_SMC_RSU_STATUS \ ++ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_STATUS) ++ ++/* ++ * Request INTEL_SIP_SMC_RSU_UPDATE ++ * ++ * Sync call used by service driver at EL1 to tell you next reboot is RSU_UPDATE ++ * ++ * Call register usage: ++ * a0 INTEL_SIP_SMC_RSU_UPDATE ++ * a1 64bit physical address of the configuration data memory in flash ++ * a2-7 not used ++ * ++ * Return status ++ * a0 INTEL_SIP_SMC_STATUS_OK ++ */ ++#define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12 ++#define INTEL_SIP_SMC_RSU_UPDATE \ ++ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE) ++ ++ ++#endif +-- +2.21.0 + diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch new file mode 100644 index 00000000..8da5892c --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch @@ -0,0 +1,60 @@ +From 17366d3b46cf70a8fa4d807519790ef4b1b03772 Mon Sep 17 00:00:00 2001 +From: "Ang, Chee Hong" <chee.hong.ang@intel.com> +Date: Wed, 30 Jan 2019 21:47:36 -0800 +Subject: [PATCH 07/12] mmc: dwmmc: Enable small delay before returning error + +'SET_BLOCKLEN' may occasionally fail on first attempt. +This patch enable a small delay in dwmci_send_cmd() on +busy, I/O or CRC error to allow the MMC controller recovers +from the failure/error on subsequent retries. + +Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> +--- + drivers/mmc/dw_mmc.c | 14 ++++++++++---- + 1 file changed, 10 insertions(+), 4 deletions(-) + +diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c +index 1992d61182..8b9c6a8e60 100644 +--- a/drivers/mmc/dw_mmc.c ++++ b/drivers/mmc/dw_mmc.c +@@ -294,8 +294,11 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + if (data) + flags = dwmci_set_transfer_mode(host, data); + +- if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) +- return -1; ++ if ((cmd->resp_type & MMC_RSP_136) && ++ (cmd->resp_type & MMC_RSP_BUSY)) { ++ ret = -1; ++ goto delay_ret; ++ } + + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) + flags |= DWMCI_CMD_ABORT_STOP; +@@ -344,11 +347,13 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + return -ETIMEDOUT; + } else if (mask & DWMCI_INTMSK_RE) { + debug("%s: Response Error.\n", __func__); +- return -EIO; ++ ret = -EIO; ++ goto delay_ret; + } else if ((cmd->resp_type & MMC_RSP_CRC) && + (mask & DWMCI_INTMSK_RCRC)) { + debug("%s: Response CRC Error.\n", __func__); +- return -EIO; ++ ret = -EIO; ++ goto delay_ret; + } + + +@@ -387,6 +392,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + } + } + ++delay_ret: + udelay(100); + + return ret; +-- +2.21.0 + diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch new file mode 100644 index 00000000..91505b7c --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch @@ -0,0 +1,41 @@ +From da0bd33c8c8f6a1b77ecaa4c676f8ee14997b9e9 Mon Sep 17 00:00:00 2001 +From: "Ang, Chee Hong" <chee.hong.ang@intel.com> +Date: Wed, 30 Jan 2019 21:29:09 -0800 +Subject: [PATCH 08/12] ARM: socfpga: stratix10: Enable DMA330 DMA controller + +Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> +--- + arch/arm/mach-socfpga/include/mach/reset_manager_s10.h | 1 + + arch/arm/mach-socfpga/spl_s10.c | 4 ++++ + 2 files changed, 5 insertions(+) + +diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h +index 1939ffa149..85424c28a6 100644 +--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h ++++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h +@@ -97,6 +97,7 @@ struct socfpga_reset_manager { + #define RSTMGR_DMA RSTMGR_DEFINE(1, 16) + #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17) + #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18) ++#define RSTMGR_DMA_OCP RSTMGR_DEFINE(1, 21) + #define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) + #define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1) + #define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2) +diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c +index ec65e1ce64..04fa1a5696 100644 +--- a/arch/arm/mach-socfpga/spl_s10.c ++++ b/arch/arm/mach-socfpga/spl_s10.c +@@ -158,6 +158,10 @@ void board_init_f(ulong dummy) + writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma); + writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph); + ++ /* enable DMA330 DMA */ ++ socfpga_per_reset(SOCFPGA_RESET(DMA), 0); ++ socfpga_per_reset(SOCFPGA_RESET(DMA_OCP), 0); ++ + spl_disable_firewall_l4_per(); + + spl_disable_firewall_l4_sys(); +-- +2.21.0 + diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch new file mode 100644 index 00000000..54fa812e --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch @@ -0,0 +1,32 @@ +From 8569e08a1a4b3bd810f60083058053a39b27534e Mon Sep 17 00:00:00 2001 +From: Chee Hong Ang <chee.hong.ang@intel.com> +Date: Sat, 18 May 2019 16:42:10 +0800 +Subject: [PATCH 09/12] ARM: socfpga: Stratix10: Fix el3_exception_vectors + relocation issue + +New toolchain has issue relocating the 32-bit pointer to address of +el3_exception_vectors in secure section. This patch make sure the +address pointer to the secure section is 64-bit. + +Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> +--- + arch/arm/mach-socfpga/lowlevel_init.S | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/mach-socfpga/lowlevel_init.S b/arch/arm/mach-socfpga/lowlevel_init.S +index 832785a682..342d5190b5 100644 +--- a/arch/arm/mach-socfpga/lowlevel_init.S ++++ b/arch/arm/mach-socfpga/lowlevel_init.S +@@ -12,8 +12,7 @@ + #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMV8_PSCI) + .align 3 + _el3_exception_vectors: +- .word el3_exception_vectors; +- .word 0 ++ .quad el3_exception_vectors; + #endif + + ENTRY(lowlevel_init) +-- +2.21.0 + diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch new file mode 100644 index 00000000..113d7672 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch @@ -0,0 +1,79 @@ +From 939875d39e56d6d2c965c2b63d5d2f20dff532e0 Mon Sep 17 00:00:00 2001 +From: Dalon Westergreen <dalon.westergreen@intel.com> +Date: Wed, 20 Mar 2019 11:21:20 -0700 +Subject: [PATCH 10/12] Makefile: Add target to generate hex output for + combined spl and dtb + +Some architectures, Stratix10, require a hex formatted spl that combines +the spl image and dtb. This adds a target to create said hex file with +and offset of SPL_TEXT_BASE. + +Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> +--- + Makefile | 12 +++++++----- + scripts/Makefile.spl | 8 ++++++++ + 2 files changed, 15 insertions(+), 5 deletions(-) + +diff --git a/Makefile b/Makefile +index 059978bfe6..62d85ff279 100644 +--- a/Makefile ++++ b/Makefile +@@ -1121,11 +1121,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ + $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \ + $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec) + +-OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex) +- +-spl/u-boot-spl.hex: spl/u-boot-spl FORCE +- $(call if_changed,objcopy) +- + binary_size_check: u-boot-nodtb.bin FORCE + @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \ + map_size=$(shell cat u-boot.map | \ +@@ -1704,6 +1699,13 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE + + spl/u-boot-spl.bin: spl/u-boot-spl + @: ++ ++spl/u-boot-spl-dtb.bin: spl/u-boot-spl ++ @: ++ ++spl/u-boot-spl-dtb.hex: spl/u-boot-spl ++ @: ++ + spl/u-boot-spl: tools prepare \ + $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \ + $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb) +diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl +index 7af6b120b6..3c90e2cd72 100644 +--- a/scripts/Makefile.spl ++++ b/scripts/Makefile.spl +@@ -216,6 +216,8 @@ ifneq ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),) + ALL-y += $(obj)/$(SPL_BIN).sfp + endif + ++ALL-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/u-boot-spl-dtb.hex ++ + ifdef CONFIG_ARCH_SUNXI + ALL-y += $(obj)/sunxi-spl.bin + +@@ -363,6 +365,11 @@ endif + $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE + $(call if_changed,mkimage) + ++OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex --change-address=$(CONFIG_SPL_TEXT_BASE) ++ ++$(obj)/u-boot-spl-dtb.hex: $(obj)/u-boot-spl-dtb.bin FORCE ++ $(call if_changed,objcopy) ++ + quiet_cmd_mksunxiboot = MKSUNXI $@ + cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \ + --default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@ +@@ -463,3 +470,4 @@ ifdef CONFIG_ARCH_K3 + tispl.bin: $(obj)/u-boot-spl-nodtb.bin $(SHRUNK_ARCH_DTB) $(SPL_ITS) FORCE + $(call if_changed,mkfitimage) + endif ++ +-- +2.21.0 + diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch new file mode 100644 index 00000000..21794d20 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch @@ -0,0 +1,52 @@ +From 37814e55403a9ec5f852b58576618ba9a1936a20 Mon Sep 17 00:00:00 2001 +From: Dalon Westergreen <dalon.westergreen@intel.com> +Date: Fri, 10 May 2019 10:30:44 -0700 +Subject: [PATCH 11/12] ARM: socfpga: stratix10: Remove CONFIG_OF_EMBED + +CONFIG_OF_EMBED was primarily enabled to support the stratix10 +spl hex file requirements. Since this option now produces a +warning during build, and the spl hex can be created using +alternate methods, CONFIG_OF_EMBED is no longer needed. + +Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> +--- + configs/socfpga_stratix10_defconfig | 1 - + include/configs/socfpga_stratix10_socdk.h | 4 ++-- + 2 files changed, 2 insertions(+), 3 deletions(-) + +diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig +index fbab388b43..f27180385d 100644 +--- a/configs/socfpga_stratix10_defconfig ++++ b/configs/socfpga_stratix10_defconfig +@@ -26,7 +26,6 @@ CONFIG_CMD_CACHE=y + CONFIG_CMD_EXT4=y + CONFIG_CMD_FAT=y + CONFIG_CMD_FS_GENERIC=y +-CONFIG_OF_EMBED=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" + CONFIG_ENV_IS_IN_MMC=y + CONFIG_NET_RANDOM_ETHADDR=y +diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h +index 39d757d737..e93c598be9 100644 +--- a/include/configs/socfpga_stratix10_socdk.h ++++ b/include/configs/socfpga_stratix10_socdk.h +@@ -197,7 +197,7 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); + * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) + * + */ +-#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex" ++#define CONFIG_SPL_TARGET "spl/u-boot-spl-dtb.hex" + #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE + #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +@@ -210,6 +210,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); + + /* SPL SDMMC boot support */ + #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" ++#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" + + #endif /* __CONFIG_H */ +-- +2.21.0 + diff --git a/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch new file mode 100644 index 00000000..c7f73bab --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch @@ -0,0 +1,31 @@ +From 97d491bda1dea7d2afe74a7c3fb4ea43a83a79ff Mon Sep 17 00:00:00 2001 +From: Dalon Westergreen <dalon.westergreen@intel.com> +Date: Fri, 10 May 2019 10:31:15 -0700 +Subject: [PATCH 12/12] ARM: socfpga: stratix10: Temporarily revert to 2GB DRAM + +The current shipping GHRD still has the DDR configured as a +2GB DDR. This reverts the devicetree to use 2GB instead of +4GB. + +Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> +--- + arch/arm/dts/socfpga_stratix10_socdk.dts | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts +index 2745050810..1caae0ab6f 100755 +--- a/arch/arm/dts/socfpga_stratix10_socdk.dts ++++ b/arch/arm/dts/socfpga_stratix10_socdk.dts +@@ -37,8 +37,7 @@ + memory { + device_type = "memory"; + /* 4GB */ +- reg = <0 0x00000000 0 0x80000000>, +- <1 0x80000000 0 0x80000000>; ++ reg = <0 0x00000000 0 0x80000000>; + u-boot,dm-pre-reloc; + }; + }; +-- +2.21.0 + diff --git a/bsp/meta-altera/recipes-bsp/u-boot/u-boot-mkenvimage_v2016.11.bb b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-mkenvimage_v2016.11.bb new file mode 100644 index 00000000..19ea6c60 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-mkenvimage_v2016.11.bb @@ -0,0 +1,34 @@ +SUMMARY = "U-Boot bootloader environment image creation tool" + +HOMEPAGE = "http://www.denx.de/wiki/U-Boot/WebHome" +SECTION = "bootloaders" + +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://Licenses/README;md5=a2c678cfd4a4d97135585cad908541c6" + +PV_append = "+git${SRCPV}" + +SRC_URI = "git://git.denx.de/u-boot.git;branch=master" +SRC_URI += "file://0001-Fix-native-build-by-using-env-variables.patch" + +S = "${WORKDIR}/git" + +# This revision corresponds to the tag "v2016.11" +# We use the revision in order to avoid having to fetch it from the +# repo during parse +SRCREV = "29e0cfb4f77f7aa369136302cee14a91e22dca71" + +EXTRA_OEMAKE = 'CROSS_COMPILE="${TARGET_PREFIX}" CC="${CC} ${CFLAGS} ${LDFLAGS}" STRIP=true V=1' + +do_compile () { + oe_runmake sandbox_defconfig + oe_runmake cross_tools NO_SDL=1 +} + +do_install () { + install -d ${D}${bindir} + install -m 0755 tools/mkenvimage ${D}${bindir}/uboot-mkenvimage + ln -sf uboot-mkenvimage ${D}${bindir}/mkenvimage +} + +BBCLASSEXTEND = "native nativesdk" diff --git a/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga-common.inc b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga-common.inc new file mode 100644 index 00000000..06f09922 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga-common.inc @@ -0,0 +1,10 @@ +HOMEPAGE = "http://www.denx.de/wiki/U-Boot/WebHome" +SECTION = "bootloaders" + +PV_append = "+git${SRCPV}" + +SRC_URI = "git://git.denx.de/u-boot.git;branch=master" + +S = "${WORKDIR}/git" + +RPROVIDES_${PN} += "u-boot" diff --git a/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga-env.inc b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga-env.inc new file mode 100644 index 00000000..1798d277 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga-env.inc @@ -0,0 +1,26 @@ +DEPENDS += "u-boot-mkenvimage-native" + +#Env binary size +ENV_SIZE = "4096" + +#Env base Name +ENV_BASE_NAME ??= "${UBOOT_CONFIG}" + +# Env base file correspond to common part of all environment +ENV_BASE_FILE = "${WORKDIR}/${ENV_BASE_NAME}.env" + +do_environment_mkimage() { + if [ -e "${WORKDIR}/${ENV_BASE_NAME}.env" ]; then + mkenvimage -s ${ENV_SIZE} -o ${WORKDIR}/${ENV_BASE_NAME}.bin ${WORKDIR}/${ENV_BASE_NAME}.env + fi +} + +do_deploy_append() { + + if [ -e "${WORKDIR}/${ENV_BASE_NAME}.bin" ]; then + install -d ${DEPLOYDIR} + install -m 644 ${WORKDIR}/${ENV_BASE_NAME}.bin ${DEPLOYDIR}/u-boot-env-${ENV_BASE_NAME}.bin + fi +} + +addtask environment_mkimage after do_compile before do_deploy diff --git a/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2013.01.01.bb b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2013.01.01.bb new file mode 100644 index 00000000..449f6c33 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2013.01.01.bb @@ -0,0 +1,23 @@ +require ${COREBASE}/meta/recipes-bsp/u-boot/u-boot.inc +PR="r1" + +SRCREV = "95ab599e1ad7840e08be0aa567eea3fca357572f" + +UBOOT_BRANCH ?= "socfpga_${PV}" +UBOOT_REPO ?= "git://github.com/altera-opensource/u-boot-socfpga.git" +UBOOT_PROT ?= "https" + +SRC_URI = "\ + ${UBOOT_REPO};protocol=${UBOOT_PROT};branch=${UBOOT_BRANCH} \ + file://fix-build-error-under-gcc6.patch \ + " + +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://README;md5=176c127db28f1a9e8d88f682a2a34963" + +DEPENDS += "dtc-native" + +UBOOT_CONFIG[cyclone5-socdk] = "socfpga_cyclone5_config" + +SPL_BINARY_cyclone5 = "spl/u-boot-spl.bin" +SPL_BINARY_arria5 = "spl/u-boot-spl.bin" diff --git a/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2014.10.bb b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2014.10.bb new file mode 100644 index 00000000..3b9b8852 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2014.10.bb @@ -0,0 +1,21 @@ +require ${COREBASE}/meta/recipes-bsp/u-boot/u-boot.inc +PR="r1" +# This revision corresponds to the SoCEDS 16.1 release +SRCREV = "ab2181dd766157a74b309d12e0b61c4f3cdc8564" + +UBOOT_BRANCH ?= "socfpga_${PV}_arria10_bringup" +UBOOT_REPO ?= "git://github.com/altera-opensource/u-boot-socfpga.git" +UBOOT_PROT ?= "https" + +SRC_URI = "\ + ${UBOOT_REPO};protocol=${UBOOT_PROT};branch=${UBOOT_BRANCH} \ + file://fix-build-error-under-gcc6.patch \ + " + +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://Licenses/README;md5=c7383a594871c03da76b3707929d2919" + +DEPENDS += "dtc-native" + +UBOOT_BINARY = "u-boot-dtb.bin" + diff --git a/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2016.05.bb b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2016.05.bb new file mode 100644 index 00000000..68a529db --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2016.05.bb @@ -0,0 +1,12 @@ +require u-boot-socfpga-common.inc +require ${COREBASE}/meta/recipes-bsp/u-boot/u-boot.inc + +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://Licenses/README;md5=a2c678cfd4a4d97135585cad908541c6" + +# This revision corresponds to the tag "v2016.05" +# We use the revision in order to avoid having to fetch it from the +# repo during parse +SRCREV = "aeaec0e682f45b9e0c62c522fafea353931f73ed" +PR = "r1" +DEPENDS += "dtc-native" diff --git a/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2016.11.bb b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2016.11.bb new file mode 100644 index 00000000..1337c8a8 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2016.11.bb @@ -0,0 +1,23 @@ +require u-boot-socfpga-common.inc +require u-boot-socfpga-env.inc +require ${COREBASE}/meta/recipes-bsp/u-boot/u-boot.inc + +FILESEXTRAPATHS =. "${THISDIR}/files/v2016.11:" + +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://Licenses/README;md5=a2c678cfd4a4d97135585cad908541c6" + +# This revision corresponds to the tag "v2016.11" +# We use the revision in order to avoid having to fetch it from the +# repo during parse +SRCREV = "29e0cfb4f77f7aa369136302cee14a91e22dca71" + +PR = "r1" + +SRC_URI_append = "\ + file://de0-nano-soc.env \ + file://cyclone5-socdk.env \ + " + +DEPENDS += "dtc-native bc-native" +DEPENDS += "u-boot-mkimage-native" diff --git a/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2017.07.bb b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2017.07.bb new file mode 100644 index 00000000..c41b4689 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2017.07.bb @@ -0,0 +1,20 @@ +require u-boot-socfpga-common.inc +require u-boot-socfpga-env.inc +require ${COREBASE}/meta/recipes-bsp/u-boot/u-boot.inc + +FILESEXTRAPATHS =. "${THISDIR}/files/v2017.07:" + +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://Licenses/README;md5=a2c678cfd4a4d97135585cad908541c6" + +# This revision corresponds to the tag "v2017.07" +# We use the revision in order to avoid having to fetch it from the +# repo during parse +SRCREV = "d85ca029f257b53a96da6c2fb421e78a003a9943" + +SRC_URI_append = "\ + file://de0-nano-soc.env \ + file://cyclone5-socdk.env \ + " + +DEPENDS += "dtc-native bc-native u-boot-mkimage-native" diff --git a/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2017.09.bb b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2017.09.bb new file mode 100644 index 00000000..389020a1 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2017.09.bb @@ -0,0 +1,18 @@ +require u-boot-socfpga-common.inc +require ${COREBASE}/meta/recipes-bsp/u-boot/u-boot.inc + +FILESEXTRAPATHS =. "${THISDIR}/files/v2017.09:" + +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://Licenses/README;md5=a2c678cfd4a4d97135585cad908541c6" + +SRCREV = "c98ac3487e413c71e5d36322ef3324b21c6f60f9" + +# Stratix10 is not mainlined yet +SRCREV_stratix10 = "53ce6e587a478bf613b1af42b49b5beba2dd2f3a" +SRC_URI_stratix10 = "git://github.com/altera-opensource/u-boot-socfpga.git;branch=socfpga_v2017.09;prot=https" + +SRC_URI_append = "\ + " + +DEPENDS += "dtc-native bc-native u-boot-mkimage-native" diff --git a/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2018.03.bb b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2018.03.bb new file mode 100644 index 00000000..9e0d937f --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2018.03.bb @@ -0,0 +1,14 @@ +require u-boot-socfpga-common.inc +require ${COREBASE}/meta/recipes-bsp/u-boot/u-boot.inc + +FILESEXTRAPATHS =. "${THISDIR}/files/v2018.03:" + +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://Licenses/README;md5=a2c678cfd4a4d97135585cad908541c6" + +SRCREV = "f95ab1fb6e37f0601f397091bb011edf7a98b890" + +SRC_URI_append = "\ + " + +DEPENDS += "dtc-native bc-native u-boot-mkimage-native" diff --git a/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2018.05.bb b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2018.05.bb new file mode 100644 index 00000000..b0358f1c --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2018.05.bb @@ -0,0 +1,14 @@ +require u-boot-socfpga-common.inc +require ${COREBASE}/meta/recipes-bsp/u-boot/u-boot.inc + +FILESEXTRAPATHS =. "${THISDIR}/files/v2018.05:" + +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://Licenses/README;md5=a2c678cfd4a4d97135585cad908541c6" + +SRCREV = "890e79f2b1c26c5ba1a86d179706348aec7feef7" + +SRC_URI_append = "\ + " + +DEPENDS += "dtc-native bc-native u-boot-mkimage-native" diff --git a/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2019.01.bb b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2019.01.bb new file mode 100644 index 00000000..d3c80e78 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2019.01.bb @@ -0,0 +1,14 @@ +require u-boot-socfpga-common.inc +require ${COREBASE}/meta/recipes-bsp/u-boot/u-boot.inc + +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://Licenses/README;md5=30503fd321432fc713238f582193b78e" + +FILESEXTRAPATHS =. "${THISDIR}/files/v2019.01:" + +SRCREV = "d3689267f92c5956e09cc7d1baa4700141662bff" + +SRC_URI_append = "\ + " + +DEPENDS += "dtc-native bc-native bison-native u-boot-mkimage-native" diff --git a/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2019.07.bb b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2019.07.bb new file mode 100644 index 00000000..48a517d0 --- /dev/null +++ b/bsp/meta-altera/recipes-bsp/u-boot/u-boot-socfpga_v2019.07.bb @@ -0,0 +1,29 @@ +require u-boot-socfpga-common.inc +require ${COREBASE}/meta/recipes-bsp/u-boot/u-boot.inc + +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://Licenses/README;md5=30503fd321432fc713238f582193b78e" + +PR = "2" + +FILESEXTRAPATHS =. "${THISDIR}/files/v2019.07:" + +SRCREV = "7e090b466c5ba874d31c1bf22c3a130d516cdc32" + +SRC_URI_append = "\ + file://0001-ARM-socfpga-stratix10-Enable-PSCI-system-reset.patch \ + file://0002-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch \ + file://0003-ARM-socfpga-stratix10-Enable-PSCI-support-for-Strati.patch \ + file://0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch \ + file://0005-ARM-socfpga-stratix10-Add-SOCFPGA-bridges-reset-supp.patch \ + file://0006-ARM-socfpga-stratix10-Add-Stratix10-FPGA-configurati.patch \ + file://0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch \ + file://0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch \ + file://0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch \ + file://0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch \ + file://0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch \ + file://0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch \ + file://0001-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch \ + " + +DEPENDS += "dtc-native bc-native bison-native u-boot-mkimage-native" |