agl-basesystem

1 files changed, 399 insertions, 0 deletions

diff --git a/bsp/meta-freescale-3rdparty/recipes-kernel/linux/linux-compulab-3.14.28/0001-ARM-i.MX6-dts-Add-initial-support-for-cm-fx6.patch b/bsp/meta-freescale-3rdparty/recipes-kernel/linux/linux-compulab-3.14.28/0001-ARM-i.MX6-dts-Add-initial-support-for-cm-fx6.patch
new file mode 100644
index 00000000..1156b835
--- /dev/null
+++ b/bsp/meta-freescale-3rdparty/recipes-kernel/linux/linux-compulab-3.14.28/0001-ARM-i.MX6-dts-Add-initial-support-for-cm-fx6.patch
@@ -0,0 +1,399 @@
+From af4b4f2854d6223ba2f1235400f8e8dac660a6a2 Mon Sep 17 00:00:00 2001
+From: Valentin Raevsky <valentin@compulab.co.il>
+Date: Thu, 15 May 2014 17:18:11 +0300
+Subject: [PATCH 01/59] ARM: i.MX6: dts: Add initial support for cm-fx6
+
+Add initial support for cm-fx6 module.
+
+This patch configures:
+1) serial console
+2) hearbeat led
+3) FreeScale NIC
+4) pcie
+5) Intel I210 NIC
+6) wif/bt
+7) sata
+
+Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
+---
+ arch/arm/boot/dts/imx6q-cm-fx6.dts |  368 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 368 insertions(+)
+ create mode 100644 arch/arm/boot/dts/imx6q-cm-fx6.dts
+
+diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
+new file mode 100644
+index 0000000..1f06d95
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
+@@ -0,0 +1,368 @@
++/*
++* Copyright 2013 CompuLab Ltd.
++*
++* Author: Valentin Raevsky <valentin@compulab.co.il>
++*
++* The code contained herein is licensed under the GNU General Public
++* License. You may obtain a copy of the GNU General Public License
++* Version 2 or later at the following locations:
++*
++* http://www.opensource.org/licenses/gpl-license.html
++* http://www.gnu.org/copyleft/gpl.html
++*/
++
++/dts-v1/;
++#include "imx6q.dtsi"
++
++/ {
++   model = "CompuLab CM-FX6";
++   compatible = "compulab,cm-fx6", "fsl,imx6q";
++
++   memory {
++      reg = <0x10000000 0x80000000>;
++   };
++
++   leds {
++      compatible = "gpio-leds";
++
++      heartbeat-led {
++         label = "Heartbeat";
++         gpios = <&gpio2 31 0>;
++         linux,default-trigger = "heartbeat";
++      };
++   };
++
++   regulators {
++      compatible = "simple-bus";
++      #address-cells = <1>;
++      #size-cells = <0>;
++
++      /* regulator for mmc */
++      reg_3p3v: 3p3v {
++         compatible = "regulator-fixed";
++         regulator-name = "3P3V";
++         regulator-min-microvolt = <3300000>;
++         regulator-max-microvolt = <3300000>;
++         regulator-always-on;
++      };
++
++      /* regulator for usb otg */
++      reg_usb_otg_vbus: usb_otg_vbus {
++         compatible = "regulator-fixed";
++         regulator-name = "usb_otg_vbus";
++         regulator-min-microvolt = <5000000>;
++         regulator-max-microvolt = <5000000>;
++         gpio = <&gpio3 22 0>;
++         enable-active-high;
++      };
++
++      /* regulator for usb hub1 */
++      reg_usb_h1_vbus: usb_h1_vbus {
++         compatible = "regulator-fixed";
++         regulator-name = "usb_h1_vbus";
++         regulator-min-microvolt = <5000000>;
++         regulator-max-microvolt = <5000000>;
++         gpio = <&gpio7 8 0>;
++         enable-active-high;
++      };
++
++      /* regulator1 for wifi/bt */
++      awnh387_npoweron: regulator-awnh387-npoweron {
++         compatible = "regulator-fixed";
++         regulator-name = "regulator-awnh387-npoweron";
++         regulator-min-microvolt = <3300000>;
++         regulator-max-microvolt = <3300000>;
++         gpio = <&gpio7 12 0>;
++         enable-active-high;
++      };
++      
++      /* regulator2 for wifi/bt */
++      awnh387_wifi_nreset: regulator-awnh387-wifi-nreset {
++         compatible = "regulator-fixed";
++         regulator-name = "regulator-awnh387-wifi-nreset";
++         regulator-min-microvolt = <3300000>;
++         regulator-max-microvolt = <3300000>;
++         gpio = <&gpio6 16 0>;
++         startup-delay-us = <10000>;
++      };
++   };
++};
++
++&iomuxc {
++   imx6q-cm-fx6 {
++       /* pins for eth0 */
++      pinctrl_enet: enetgrp {
++         fsl,pins = <
++            MX6QDL_PAD_RGMII_RXC__RGMII_RXC      0x1b0b0
++            MX6QDL_PAD_RGMII_RD0__RGMII_RD0      0x1b0b0
++            MX6QDL_PAD_RGMII_RD1__RGMII_RD1      0x1b0b0
++            MX6QDL_PAD_RGMII_RD2__RGMII_RD2      0x1b0b0
++            MX6QDL_PAD_RGMII_RD3__RGMII_RD3      0x1b0b0
++            MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
++            MX6QDL_PAD_RGMII_TXC__RGMII_TXC      0x1b0b0
++            MX6QDL_PAD_RGMII_TD0__RGMII_TD0      0x1b0b0
++            MX6QDL_PAD_RGMII_TD1__RGMII_TD1      0x1b0b0
++            MX6QDL_PAD_RGMII_TD2__RGMII_TD2      0x1b0b0
++            MX6QDL_PAD_RGMII_TD3__RGMII_TD3      0x1b0b0
++            MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
++            MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK   0x1b0b0
++            MX6QDL_PAD_ENET_MDIO__ENET_MDIO      0x1b0b0
++            MX6QDL_PAD_ENET_MDC__ENET_MDC      0x1b0b0
++            MX6QDL_PAD_GPIO_16__ENET_REF_CLK   0x4001b0a8
++         >;
++      };
++      
++      /* pins for spi */
++      pinctrl_ecspi1: ecspi1grp {
++         fsl,pins = <
++            MX6QDL_PAD_EIM_D16__ECSPI1_SCLK      0x100b1
++            MX6QDL_PAD_EIM_D17__ECSPI1_MISO      0x100b1
++            MX6QDL_PAD_EIM_D18__ECSPI1_MOSI      0x100b1
++            MX6QDL_PAD_EIM_EB2__GPIO2_IO30      0x100b1
++            MX6QDL_PAD_EIM_D19__GPIO3_IO19      0x100b1
++         >;
++      };
++
++      /* pins for nand */
++      pinctrl_gpmi_nand: gpminandgrp {
++         fsl,pins = <
++            MX6QDL_PAD_NANDF_CLE__NAND_CLE      0xb0b1
++            MX6QDL_PAD_NANDF_ALE__NAND_ALE      0xb0b1
++            MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
++            MX6QDL_PAD_NANDF_RB0__NAND_READY_B   0xb000
++            MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
++            MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
++            MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
++            MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
++            MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
++            MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
++            MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
++            MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
++            MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
++            MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
++            MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
++            MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
++            MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
++         >;
++      };
++
++      /* pins for i2c1 */
++      pinctrl_i2c1: i2c1grp {
++         fsl,pins = <
++            MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
++            MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
++         >;
++      };
++      
++      /* pins for i2c2 */
++      pinctrl_i2c2: i2c2grp {
++         fsl,pins = <
++            MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++            MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++         >;
++      };
++      
++      /* pins for i2c3 */
++      pinctrl_i2c3: i2c3grp {
++         fsl,pins = <
++            MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
++            MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
++         >;
++      };
++
++      /* pins for console */
++      pinctrl_uart4: uart4grp {
++         fsl,pins = <
++            MX6QDL_PAD_KEY_COL0__UART4_TX_DATA   0x1b0b1
++            MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA   0x1b0b1
++         >;
++      };
++      
++      /* pins for usb hub1 */
++      pinctrl_usbh1: usbh1grp {
++         fsl,pins = <
++            MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
++         >;
++      };
++      
++      /* pins for usb otg */
++      pinctrl_usbotg: usbotggrp {
++         fsl,pins = <
++            MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
++         >;
++      };
++
++      /* pins for wifi/bt */
++      pinctrl_usdhc1: usdhc1grp {
++         fsl,pins = <
++            MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
++            MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
++            MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
++            MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
++            MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
++            MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
++         >;
++      };
++
++      /* pins for mmc */
++      pinctrl_usdhc3: usdhc3grp {
++         fsl,pins = <
++            MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
++            MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
++            MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++            MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++            MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++            MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++         >;
++      };
++   };
++};
++
++/* spi */
++&ecspi1 {
++   fsl,spi-num-chipselects = <2>;
++   cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
++   pinctrl-names = "default";
++   pinctrl-0 = <&pinctrl_ecspi1>;
++   status = "okay";
++
++   flash: m25p80@0 {
++      #address-cells = <1>;
++      #size-cells = <1>;
++      compatible = "st,m25px16", "st,m25p";
++      spi-max-frequency = <20000000>;
++      reg = <0>;
++
++      partition@0 {
++         label = "uboot";
++         reg = <0x0 0xc0000>;
++      };
++
++      partition@c0000 {
++         label = "uboot environment";
++         reg = <0xc0000 0x40000>;
++      };
++
++      partition@100000 {
++         label = "reserved";
++         reg = <0x100000 0x100000>;
++      };
++   };
++};
++
++/* eth0 */
++&fec {
++   pinctrl-names = "default";
++   pinctrl-0 = <&pinctrl_enet>;
++   phy-mode = "rgmii";
++   status = "okay";
++};
++
++/* nand */
++&gpmi {
++   pinctrl-names = "default";
++   pinctrl-0 = <&pinctrl_gpmi_nand>;
++   status = "okay";
++};
++
++/* i2c1 */
++&i2c1 {
++   pinctrl-names = "default";
++   pinctrl-0 = <&pinctrl_i2c1>;
++   status = "okay";
++
++   eeprom@50 {
++      compatible = "at24,24c02";
++      reg = <0x50>;
++      pagesize = <16>;
++   };
++
++   rtc@56 {
++      compatible = "emmicro,em3027";
++      reg = <0x56>;
++   };
++};
++
++/* i2c2 */
++&i2c2 {
++   pinctrl-names = "default";
++   pinctrl-0 = <&pinctrl_i2c2>;
++   status = "okay";
++};
++
++/* i2c3 */
++&i2c3 {
++   pinctrl-names = "default";
++   pinctrl-0 = <&pinctrl_i2c3>;
++   status = "okay";
++
++   eeprom@50 {
++      compatible = "at24,24c02";
++      reg = <0x50>;
++      pagesize = <16>;
++   };
++};
++
++/* eth1 */ 
++&pcie {
++   reset-gpio = <&gpio1 26 0>;
++   status = "okay";
++};
++
++/* sata */
++&sata {
++   status = "okay";
++};
++
++/* rear serial console */
++&uart2 {
++   pinctrl-names = "default";
++   pinctrl-0 = <&pinctrl_uart2_2>;
++   fsl,dte-mode;
++   fsl,uart-has-rtscts;
++   dma-names = "rx", "tx";
++   dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
++   status = "okay";
++};
++
++/* console */
++&uart4 {
++   pinctrl-names = "default";
++   pinctrl-0 = <&pinctrl_uart4>;
++   status = "okay";
++};
++
++/* usb otg */
++&usbotg {
++   vbus-supply = <&reg_usb_otg_vbus>;
++   pinctrl-names = "default";
++   pinctrl-0 = <&pinctrl_usbotg>;
++   dr_mode = "otg";
++   status = "okay";
++};
++
++/* usb hub1 */
++&usbh1 {
++   vbus-supply = <&reg_usb_h1_vbus>;
++   pinctrl-names = "default";
++   pinctrl-0 = <&pinctrl_usbh1>;
++   status = "okay";
++};
++
++/* wifi/bt */
++&usdhc1 {
++   pinctrl-names = "default";
++   pinctrl-0 = <&pinctrl_usdhc1>;
++   non-removable;
++   vmmc-supply = <&awnh387_npoweron>;
++   vmmc_aux-supply = <&awnh387_wifi_nreset>;
++   status = "okay";
++};
++
++/* mmc */
++&usdhc3 {
++   pinctrl-names = "default";
++   pinctrl-0 = <&pinctrl_usdhc3>;
++   vmmc-supply = <&reg_3p3v>;
++   status = "okay";
++};
+-- 
+1.7.9.5
+